Texas Instruments | TPS65917-Q1 to Power DRA7xx and TDA2x/TDA2Ex (Rev. F) | User Guides | Texas Instruments TPS65917-Q1 to Power DRA7xx and TDA2x/TDA2Ex (Rev. F) User guides

Texas Instruments TPS65917-Q1 to Power DRA7xx and TDA2x/TDA2Ex (Rev. F) User guides
User's Guide
SLVUAJ1F – November 2015 – Revised May 2018
TPS65917-Q1 User’s Guide to Power DRA7xx and
TDA2x/TDA2Ex
This User’s Guide can be used as a guide for integrating the TPS65917-Q1 power-management
integrated circuit (PMIC) into a system powering the DRA72x, DRA74x, DRA75x, TDA2x, or TDA2Ex
device.
1
2
3
4
5
6
Contents
Introduction ................................................................................................................... 2
Device Versions .............................................................................................................. 2
Platform Connection ......................................................................................................... 2
BOOT OTP Configuration .................................................................................................. 6
Static Platform Settings ..................................................................................................... 6
5.1
System Voltage Monitoring ........................................................................................ 6
5.2
SMPS ................................................................................................................. 8
5.3
LDO ................................................................................................................... 8
5.4
Interrupts ............................................................................................................. 8
5.5
GPIO.................................................................................................................. 9
5.6
MISC ................................................................................................................ 11
5.7
SWOFF_HWRST .................................................................................................. 12
5.8
Shutdown_ColdReset ............................................................................................. 13
Sequence Platform Settings .............................................................................................. 14
6.1
OFF2ACT Sequences ............................................................................................ 14
6.2
ACT2OFF Sequences ............................................................................................ 16
6.3
ACT2SLP and SLP2ACT Sequences .......................................................................... 18
6.4
Warm Reset Sequences ......................................................................................... 21
List of Figures
1
Processor Connection With O917A130TRGZRQ1 or O917A131TRGZRQ1 ........................................ 3
2
Processor Connection With O917A132TRGZRQ1 or O917A133TRGZRQ1 ........................................ 4
3
Reset Connections With POWERHOLD Configuration ................................................................. 5
4
Reset Connections With PWRON Configuration ........................................................................ 5
5
PMIC Comparators .......................................................................................................... 7
6
State Transitions ............................................................................................................. 7
7
Reset Levels versus Registers ........................................................................................... 12
8
OFF2ACT Sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1 ......................................... 14
9
OFF2ACT Sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1 ......................................... 15
10
Power Down Sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1 ...................................... 16
11
Power Down Sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1 ...................................... 17
12
ACT2SLP and SLP2ACT Sequences of O917A131TRGZRQ1 ...................................................... 19
13
ACT2SLP and SLP2ACT Sequences of O917A133TRGZRQ1 ...................................................... 20
14
Warm Reset Sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1 ...................................... 21
15
Warm Reset Sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1 ...................................... 22
Trademarks
All trademarks are the property of their respective owners.
SLVUAJ1F – November 2015 – Revised May 2018
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1
Introduction
1
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Introduction
This user’s guide can be used as a guide for connectivity between the TPS65917-Q1 PMIC and a
processor. This guide describes the platform connections as well as the power-up, power-down, and sleep
entry and exit sequences along with the OTP configurations. In addition, this user’s guide describes the
initialization software and advises how to get started with the TPS65917-Q1 PMIC. This document does
not provide details about the power resources, external components, or the functionality of the device. For
such information, see the TPS65917-Q1 data sheet, TPS65917-Q1 Power Management Unit (PMU) for
Processor. The TPS65917-Q1 is optimized to power DRA72x and TDA2Ex. When using TPS65917-Q1 to
power the other processors, the user should make sure that the power requirements of the processor do
not exceed the current capabilities of the TPS65917-Q1 device.
In the event of any inconsistency between the official specification and any user's guide, application
report, or other referenced material, the data sheet specification will be the definitive source.
2
Device Versions
Four different versions of the TPS65917-Q1 device are available and the OTP settings for each version
are described in this document. The three different versions of the device can be used to power the
DRA7xx and TDA2x/TDA2Ex processor devices. The OTP version can be read from the SW_REVISION
register. In this guide, each device version is distinguished either by the part number or the
SW_REVISION value which are both listed in Table 1.
Texas Instruments recommends having 15% margin in the load current. Therefore the current
requirements listed in Table 1 are 15% lower than the maximum capability of the regulator.
Table 1. TPS65917-Q1 OTP Settings Differentiation
LOAD CURRENT REQUIREMENT (1)
GPIO_6 FUNCTION
ORDERABLE PART NUMBER
CONTENT OF
SW_REVISION
REGISTER
DSPEVE + GPU + IVA < 2.55 A
POWERGOOD
O917A130TRGZRQ1
0x30
DSPEVE + GPU + IVA < 2.55 A
NSLEEP
O917A131TRGZRQ1
0x31
DSPEVE + GPU + IVA < 3 A
POWERGOOD
O917A132TRGZRQ1
0x32
DSPEVE + GPU + IVA < 3 A
NSLEEP
O917A133TRGZRQ1
0x33
(1)
The load current must only be considered when powering Jacinto 6. All four OTP options can power the maximum performance
of the Jacinto 6 Eco (DRA72x and TDA2Ex) devices.
All four OTP configurations are capable of powering the DRA72x and TDA2Ex devices, or powering the
DRA74x, DRA75x, and TDA2x devices with DSPEVE + GPU + IVA < 2.55 A. In this case, select the 0x30
or 0x31 configurations because they have the same power mapping as the DRA72x EVM.
3
Platform Connection
Figure 1 shows the detailed connections between a processor and the O917A130TRGZRQ1 or
O917A131TRGZRQ1. Both devices use the same power configuration, and it is the same configuration
used on the DRA72x and TDA2Ex EVM. If VIO_IN of the PMIC should be 1.8 V, it could be supplied by
SMPS4. If VIO_IN of the PMIC should be 3.3 V, it could be supplied by the switched 3.3-V output of the
TPS22965-Q1 device. When using DDR self-refresh mode, VIO_IN must be supplied before GPIO_4 is
enabled in the power sequence but must ramp after VCC is stable. In this case, VIO_IN should be an
external supply, either enabled externally or by an early signal such as SMPS4. When DDR self-refresh
mode is not used, the load switch enabled by GPIO_4 is not required.
2
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Platform Connection
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1.15V
12-V
Power
Source
VDD_MPU
VBUCKB
AVS
SMPS2
(3.5 A max)
AVS
VDD_GPU
1.06 V
VDD_IVAHD
1.15V
VDD_CORE
1.15V
SMPS4
(1.5 A max)
VDD_RTC
5V
1.8 V
1.8 V
LDO5(LN)
(100 mA max)
LDO3
(200 mA max)
LDO2
(300 mA max)
1.8 V
1.8 V
1.8 V
VDD_1V8
VDDA_1V8 (PLLs)
VDDA_1V8 (PHYs)
VDDA_1V8 (PHYs)
Processor
VBUCKA
3.3 V
SMPS3
(3 A max)
VDD_DSPEVE
1.8-V Supplies
TPS43351-Q1
SMPS1
(3.5 A max)
AVS
Core Supplies
TPS65917-Q1
VDDA_RTC
LDOVRTC
(25 mA max)
VDDSHV8 (SDIO)
3.3 V
LDO4 (USB)
(100 mA max)
SMPS5
(2 A max)
1.35 V or 1.5 V
TPS22965-Q1
(load switch)
3.3 V
0.675 V or 0.75 V
VDDA_USB3V3
VDD_DDR
Dual-Voltage Rails
(set to 3.3 V)
Other Supplies
3.3 V (bypass)
LDO1 (bypass)
(300 mA max)
DDR_VREF
GPIO4
1.35 V or 1.5 V
TPS22965-Q1
1V8
VDD, VDDQ
(load switch)
0.675 V or 0.75 V
TPS51200-Q1
VREF
0.675 V or 0.75 V
VTT
3.3 V
System
1.8 V
GPIO0
DDR
ADC (8 ch)
3V3
5V
5V0
Figure 1. Processor Connection With O917A130TRGZRQ1 or O917A131TRGZRQ1
Figure 2 shows the detailed connections between the processor and the O917A132TRGZRQ1 or
O917A133TRGZRQ1. Compared to the previous configuration, this configuration swaps SMPS2 and
SMPS3 which provides a higher current capacity for the DSPEVE/GPU/IVA domains. When using
DRA74x/75x or TDA2x, this configuration is recommended because of the higher current capacity on
those domains. If VIO_IN of the PMIC should be 1.8 V, it could be supplied by SMPS4. If VIO_IN of the
PMIC should be 3.3 V, it could be supplied by the switched 3.3-V output of the TPS22965-Q1 device.
When using DDR self-refresh mode, VIO_IN must be supplied before GPIO_4 is enabled in the power
sequence but must ramp after VCC is stable. In this case, VIO_IN should be an external supply, either
enabled externally or by an early signal such as SMPS4. When DDR self-refresh mode is not used, the
load switch enabled by GPIO_4 is not required.
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Platform Connection
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1.15V
12-V
Power
Source
VDD_MPU
TPS43351-Q1
SMPS2
(3.5 A max)
AVS
SMPS3
(3 A max)
AVS
VDD_GPU
1.06 V
VDD_IVAHD
1.15V
VDD_CORE
1.15V
SMPS4
(1.5 A max)
VDD_RTC
5V
VDD_1V8
1.8 V
1.8 V
VDDA_1V8 (PHYs)
1.8 V
VDDA_RTC
3.3 V (bypass)
VDDSHV8 (SDIO)
3.3 V
LDO4 (USB)
(100 mA max)
1.35 V or 1.5 V
TPS22965-Q1
(load switch)
3.3 V
0.675 V or 0.75 V
ADC (8 ch)
1.8 V
GPIO4
1.35 V or 1.5 V
TPS22965-Q1
VDDA_USB3V3
VDD_DDR
Dual-Voltage Rails
(set to 3.3 V)
DDR_VREF
1V8
VDD, VDDQ
0.675 V or 0.75 V
TPS51200-Q1
DDR
(load switch)
VREF
0.675 V or 0.75 V
VTT
3.3 V
System
LDO1 (bypass)
(300 mA max)
GPIO0
VDDA_1V8 (PHYs)
1.8 V
LDOVRTC
(25 mA max)
SMPS5
(2 A max)
VDDA_1V8 (PLLs)
Processor
1.8 V
LDO5(LN)
(100 mA max)
LDO3
(200 mA max)
LDO2
(300 mA max)
1.8-V Supplies
VBUCKB
AVS
Other Supplies
VBUCKA
3.3 V
SMPS1
(3.5 A max)
VDD_DSPEVE
Core Supplies
TPS65917-Q1
3V3
5V
5V0
Figure 2. Processor Connection With O917A132TRGZRQ1 or O917A133TRGZRQ1
In both configurations, LDO2 and LDO3 are used to supply the PHY domains. Table 2 describes how the
PHY domains should be split between the two LDOs.
Table 2. LDO2 and LDO3 Mapping to PHY Domains
TPS65917-Q1 LDO
LDO3 (200 mA)
LDO2 (300 mA)
4
PROCESSOR BALL
VOLTAGE RAIL
(DRA74x/DRA75x/TDA2x)
VOLTAGE RAIL
(DRA72x/TDA2Ex)
AA13
VDDA_USB1
VDDA_USB1
AB12
VDDA_USB2
VDDA_USB2
W12
VDDA_USB3
VDDA_CSI2
V13
VDDA_SATA
VDDA_SATA
Y17
VDDA_HDMI
VDDA_HDMI
W14
VDDA_PCIE
VDDA_USB3
AA17
VDDA_PCIE0
VDDA_PCIE
AA16
VDDA_PCIE1
VDDA_PCIE0
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Platform Connection
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PMIC
TPS65917-Q1
VSYS
Reset to Board
VIO
Reset Input
Board
Figure 3 and Figure 4 show the reset connections required between the TPS65917-Q1 and the processor.
All of the OTP configurations have the same reset connections to the processor, along with one of the two
options for enabling the power supply; either POWERHOLD or PWRON. Enabling either of these signals
turns on the TPS65917-Q1 device and starts the startup sequence for the processor. Figure 3 shows the
POWERHOLD configuration for the TPS65917-Q1 and the processor. GPIO_5 is configured as
POWERHOLD in the OTP memory. To turn on the TPS65917-Q1, GPIO_5 must be set to a high logic
level. When using POWERHOLD, the PWRON signal can be left floating.
VRTC
RESETn
GPIO_1
RSTOUTn
(nRESWARM)
PORz
RESET_OUT
RTC_PORz
RTC_ISO
GPIO_5
EN
Processor
PWRON
(POWERHOLD)
INT
GPIO
Figure 3. Reset Connections With POWERHOLD Configuration
Figure 4 shows the PWRON configuration for the TPS65917-Q1 and the processor. This configuration is
used when a push button enables the system. As shown, PWRON is connected to a switch that pulls
PWRON to a low logic level when the switch is pressed on.
In some applications, a warm reset is required. This allows for the TPS65917-Q1 to reset to its default
settings without turning off first. To complete a warm reset correctly, POWERHOLD must be kept at a high
logic level so the TPS65917-Q1 does not turn off. One solution for this scenario is that GPIO_5 is tied to
GPIO_2 and pulled up to VIO. Pulling GPIO_5 to VIO ensures that POWERHOLD is kept high during a
warm reset. Tying GPIO_2 to POWERHOLD provides a method to set POWERHOLD low, which is
necessary to turn off the device.
For this solution to work, a few software writes must occur:
1. First, enable the TPS65917-Q1 by the push button.
2. Second, set GPIO_2 to a high logic level.
3. Third, set GPIO_2 as an output.
PMIC
TPS65917-Q1
VSYS
Reset to Board
VIO
Reset Input
Board
When ready to disable the TPS65917-Q1, set GPIO_2 to a low logic level.
VRTC
RESETn
GPIO_1
(nRESWARM)
VIO
PORz
RESET_OUT
10 k
RTC_PORz
RTC_ISO
GPIO_5
GND
RSTOUTn
Processor
PWRON
(POWERHOLD)
GPIO_2
INT
GPIO
Figure 4. Reset Connections With PWRON Configuration
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5
BOOT OTP Configuration
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BOOT OTP Configuration
All TPS65917-Q1 resource settings are stored in the form of registers. Therefore, all platform-related
settings are linked to an action altering these registers. This action can be a static update (register
initialization value) or a dynamic update of the register (either from the user or from a power sequence).
Resources and platform settings are stored in nonvolatile memory (OTP). These settings are defined as
follows:
Static platform settings — These settings define, for example, SMPS or LDO default voltages, and
GPIO functionality. Most static platform settings can be overwritten by a power sequence or by the
user.
Sequence platform settings — These settings define the TPS65917-Q1 power sequences between
state transitions, such as the OFF2ACT sequence when transitioning from OFF mode to ACTIVE
mode. The power sequence is composed of several register accesses that define which resources
(and the corresponding registers) must be updated during the respective state transition. The state
of these resources can be overwritten by the user after the power sequence completes execution.
5
Static Platform Settings
Each device has predefined values stored in OTP which control the default configuration of the device.
The tables in this section list the OTP-programmed values for each device, distinguished by the
SW_REVISION.
5.1
System Voltage Monitoring
Table 3. System Voltage Monitoring OTP Settings
REGISTER
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
UNIT
VSYS_MON
VSYS_HI
System voltage rising-edge
threshold
3.1
V
VSYS_LO
VSYS_LO
System voltage falling-edge
threshold
2.75
V
Comparators that monitor the voltage on the VCC_SENSE, and VCCA pins control the power state
machine of the TPS65917-Q1 device. For electrical parameters, refer to the data sheet.
POR— When the supply at the VCCA pin is below the POR threshold, the TPS65917-Q1 device is in the
NO SUPPLY state. All functionality is off. The device moves from the NO SUPPLY state to the
BACKUP state when the voltage in VCCA rises above the POR threshold.
VSYS_LO— When the voltage on the VCCA pin rises above VSYS_LO, the device enters from the
BACKUP state to the OFF state. When the device is in an ACTIVE, SLEEP, or OFF state and the
voltage on VCCA decreases below the VSYS_LO level, the device enters backup mode. The level
of VSYS_LO is OTP programmable.
VSYS_MON— During power up, the value of VSYS_HI OTP is used as a threshold for the VSYS_MON
comparator which is gating PMIC start-up (that is, as a threshold for transition from the OFF state to
the ACTIVE state). The VSYS_MON comparator monitors the VCC_SENSE pin. After power up,
software can configure the comparator threshold in the VSYS_MON register.
VBUS_DET— The VBUS_DET comparator is monitoring the VBUS_SENSE (secondary function of
GPIO1) pin. This comparator is active when VCCA is greater than the POR threshold. Triggering
the threshold level generates an interrupt. It can wake up the device from the SLEEP state, but can
also switch on the device from the OFF state.
6
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OTP bits
Register bits
VCCA
POR
Power-On Reset Threshold
VCCA
VSYS_LO
VSYS_LO
VCC_SENSE
VSYS_MON
VSYS_MON
Default VSYS_HI
VBUS_SENSE
VBUS_DET
VBUS_WKUP_UP
Figure 5. PMIC Comparators
VSYS_HI
VSYS_MON
VSYS_LO
Start-Up Event
POR
INT
STATE
NO SUPPLY
BACKUP
OFF
ACTIVE / SLEEP
BACKUP
NO SUPPLY
Figure 6. State Transitions
NOTE: The maximum input voltage of the VCC_SENSE pin depend on the OTP setting of
PMU_CONFIG [HIGH_VCC_SENSE] as listed in the Recommended Operating Conditions
table of the TPS65917-Q1 data sheet. This configuration is set as HIGH_VCC_SENSE = 0
with the VCC_SENSE and pins are connected to VCCA.
For the recommended operating conditions of the electrical parameters, see the TPS65917-Q1 data
sheet, TPS65917-Q1 Power Management Unit (PMU) for Processor.
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Static Platform Settings
5.2
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SMPS
This section describes the default voltage for each SMPS. Both options have two default voltages for
SMPS5 based on the connection of the BOOT pin. If the BOOT pin is connected to 0 V, then SMPS5
defaults to 1.35 V. If the BOOT0 pin is connected to 1.8 V, then SMPS5 outputs 1.5 V.
Table 4. SMPS OTP Settings
BIT
DESCRIPTION
0x30, 0x31 VALUE
(1)
BOOT = 1
BOOT = 0
BOOT = 1
SMPS1_VOLTAGE
Default output voltage for the regulator
SMPS2_VOLTAGE
Default output voltage for the regulator
1.15
1.06
V
SMPS3_VOLTAGE
Default output voltage for the regulator
1.06
1.15
V
SMPS4_VOLTAGE
Default output voltage for the regulator
SMPS5_VOLTAGE
Default output voltage for the regulator
SMPS1_SMPS12_EN
SMPS12 single-phase or dual-phase
configuration.
0: SMPS1 and SMPS2 single-phase
1: SMPS12 dual-phase
(1)
5.3
0x32, 0x33 VALUE
UNIT
BOOT = 0
1.15
V
1.80
1.35
1.50
V
1.35
1.50
0
V
NA
The regulator output voltage cannot be modified while active from one (0.7 to 1.65 V) voltage range to the other (1 to 3.3 V)
voltage range or the other way around. The regulator must be turned off to do so.
LDO
This section describes the default output voltage for each LDO. Note that by default LDO1 is in bypass
mode, which means its output is equal to its input. Typically, LDO1 would be supplied by a 3.3V supply
from a pre-regulator or from the switched 3.3V output of the load switch enabled by GPIO_0.
Table 5. LDO OTP Settings
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
UNIT
LDO1_VOLTAGE
Default output voltage for the regulator
BYPASS
V
LDO2_VOLTAGE
Default output voltage for the regulator
1.8
V
LDO3_VOLTAGE
Default output voltage for the regulator
1.8
V
LDO4_VOLTAGE
Default output voltage for the regulator
3.3
V
LDO5_VOLTAGE
Default output voltage for the regulator
1.8
V
NOTE: LDO1 and LDO2 share a single input LDO12_IN and must by supplied by the same voltage.
Refer to the input voltage parameter in the data sheet.
5.4
Interrupts
The interrupts are split into four register groups (INT1, INT2, INT3, and INT4). All interrupts are logically
combined on a single output line, INT (default active-low). This line is used as an external interrupt line to
warn the host processor of any interrupt event that has occurred within the device. The OTP settings in
this section show whether each interrupt is enabled or disabled by default.
Table 6. INT1 OTP Settings
REGISTER
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
VSYS_MON
Enable and disable interrupt from the VSYS_MON comparator
1: Interrupt generation disabled
PWRDOWN
Enable and disable interrupt from the PWRDOWN pin
PWRON
Enable and disable interrupt from PWRON pin. A PWRON event
is always an ON request.
1: Interrupt generation disabled
LONG_PRESS_KEY
Enable and disable interrupt from long key press on the
PWRON pin
1: Interrupt generation disabled
HOTDIE
Enable and disable interrupt from device hot-die detection. The
interrupt can be used as a pre-warning for processor to limit the
PMIC load, before increasing die temperature forces shutdown.
INT1_MASK
8
TPS65917-Q1 User’s Guide to Power DRA7xx and TDA2x/TDA2Ex
0: Interrupt generated
0: Interrupt generated
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Table 7. INT2 OTP Settings
REGISTER
INT2_MASK
BIT
DESCRIPTION
SHORT
Triggered from internal event of SMPS or LDO outputs failing. If
an interrupt is enabled, it is an ON request.
0x30, 0x31, 0x32, 0x33 VALUE
WDT
Enable and disable interrupt from watchdog expiration
FSD
Enable and disable First Supply Detection (FSD) interrupt
1: Interrupt generation disabled
RESET_IN
Enable and disable interrupt from the RESET_IN pin
1: Interrupt generated disabled
0: Interrupt generated
0: Interrupt generated
Table 8. INT3 OTP Settings
REGISTER
INT3_MASK
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
VBUS
Interrupt to detect rising or falling VBUS line
1: Interrupt generation disabled
GPADC_EOC_SW
GPADC result ready from software-initiated conversion
1: Interrupt generation disabled
GPADC_AUTO_1
GPADC automatic conversion result 1 above or below the
reference threshold
0: Interrupt generated
GPADC_AUTO_0
GPADC automatic conversion result 0 above or below the
reference threshold
0: Interrupt generated
Table 9. INT4 OTP Settings
REGISTER
INT4_MASK
5.5
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
GPIO_6
Enable and disable interrupt from the GPIO6 pin rising or falling
edge
1: Interrupt generation disabled
GPIO_5
Enable and disable interrupt from the GPIO5 pin rising or falling
edge
1: Interrupt generation disabled
GPIO_4
Enable and disable interrupt from the GPIO4 pin rising or falling
edge
1: Interrupt generation disabled
GPIO_3
Enable and disable interrupt from the GPIO3 pin rising or falling
edge
1: Interrupt generation disabled
GPIO_2
Enable and disable interrupt from the GPIO2 pin rising or falling
edge
1: Interrupt generation disabled
GPIO_1
Enable and disable interrupt from the GPIO1 pin rising or falling
edge
1: Interrupt generation disabled
GPIO_0
Enable and disable interrupt from the GPIO0 pin rising or falling
edge
1: Interrupt generation disabled
GPIO
TPS65917-Q1 integrates eight configurable general-purpose I/Os (GPIOs) that are multiplexed with
alternative features. This section describes the default configuration of each GPIO, as well as the
configuration of internal pullup or pulldown resistors on the GPIOs.
Table 10. GPIO Function OTP Settings
REGISTER
PRIMARY_SECONDARY_PAD2
BIT
DESCRIPTION
GPIO_6
Select pin function
0x30, 0x32 VALUE
0x31, 0x33 VALUE
GPIO_5
Select pin function
GPIO_4
Select pin function
REGEN2
GPIO_3
Select pin function
SYNCDCDC
GPIO_2
Select pin function
GPIO_2
GPIO_1
Select pin function
NRESWARM
GPIO_0
Select pin function
REGEN1
POWERGOOD
NSLEEP
POWERHOLD
PRIMARY_SECONDARY_PAD1
NOTE: The GPIO_0 pin is an open drain pin and therefore must be pulled up externally. TI does not
recommend pulling the GPIO_0 pin up to any always-on signal such as VCCA or
LDOVRTC_OUT. The GPIO_0 pin is configured as an input before the OTP memory is
loaded at power up, and pulling the pin up to an always-on rail can cause a glitch on the
GPIO_0 pin. Therefore, TI recommends pulling this signal up to a sequenced output, such as
SMPS3 (1.8 V) or LDO4 (3.3 V).
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Table 11 describes the pullup, pulldown, and open-drain settings for the corresponding GPIOs. These
settings only apply in GPIO mode (eg. GPIO_0), and do not apply to any of the secondary functions (eg.
REGEN1).
Table 11. GPIO Pullup, Pulldown, and Open Drain Settings
REGISTER
PU_PD_GPIO_CTRL2
PU_PD_GPIO_CTRL1
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
GPIO_6_PD
Configure pulldown for GPIO_6
0: Pulldown disabled
GPIO_5_PD
Configure pulldown for GPIO_5
0: Pulldown disabled
GPIO_4_PU
Configure pullup for GPIO_4
0: Pullup disabled
GPIO_4_PD
Configure pulldown for GPIO_4
0: Pulldown disabled
GPIO_3_PD
Configure pulldown for GPIO_3
1: Pulldown enabled
GPIO_2_PU
Configure pullup for GPIO_2
1: Pullup enabled
GPIO_2_PD
Configure pulldown for GPIO_2
0: Pulldown disabled
GPIO_1_PD
Configure pulldown for GPIO_1
0: Pulldown disabled
GPIO_0_PD
Configure pulldown for GPIO_0
0: Pulldown disabled
GPIO_4_OD
Configure GPIO_4 to be opendrain or push-pull
0: Push-pull
GPIO_2_OD
Configure GPIO_2 to be opendrain or push-pull
0: Push-pull
OD_OUTPUT_GPIO
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Table 12 describes the polarity settings for each GPIO. These settings apply to both GPIO mode and
secondary functions.
Table 12. GPIO Polarity Settings
REGISTER
POLARITY_CTRL
5.6
BIT
DESCRIPTION
0x30, 0x31, 0x32, 0x33 VALUE
GPIO_6_POLARITY
Enable or disable polarity
inversion for GPIO_6
0: Inversion disabled
GPIO_5_POLARITY
Enable or disable polarity
inversion for GPIO_5
0: Inversion disabled
GPIO_4_POLARITY
Enable or disable polarity
inversion for GPIO_4
0: Inversion disabled
GPIO_3_POLARITY
Enable or disable polarity
inversion for GPIO_3
0: Inversion disabled
GPIO_2_POLARITY
Enable or disable polarity
inversion for GPIO_2
0: Inversion disabled
GPIO_1_POLARITY
Enable or disable polarity
inversion for GPIO_1
0: Inversion disabled
GPIO_0_POLARITY
Enable or disable polarity
inversion for GPIO_0
0: Inversion disabled
MISC
This section describes miscellaneous device configuration settings including pulldowns, polarity of signals,
communication settings, and other functionality.
Table 13. MISC1 OTP Settings
REGISTER
BIT
DESCRIPTION
RESET_IN_PD
Enable and disable internal pulldown for the
RESET_IN pin
0x30, 0x31, 0x32, 0x33 VALUE
1: Pulldown enabled
PWRDOWN_PD
Enable and disable internal pulldown for the
PWRDOWN pin
1: Pulldown enabled
PU_PD_INPUT_CTRL1
Table 14. MISC2 OTP Settings
REGISTER
BIT
DESCRIPTION
I2C_SPI
Selection of control interface, I2C, or SPI
0x30, 0x31, 0x32, 0x33 VALUE
ID_I2C2
I2C_2 address for page access versus initial address (0H12)
0: Address is 0x12
ID_I2C1
I2C_1 address for I2C register access
I2C_1[0] = 1: 0x58
I2C_1[1] = 1: 0x59
I2C_1[2] = 1: 0x5A
I2C_1[3] = 1: 0x5B
HIGH_VCC_SENSE
Enable internal buffers on VCC_SENSE to allow voltage
sensing above 5.25 V
AUTODEVON
Automatically set DEV_ON bit after startup sequence
completes
SWOFF_DLY
Delay before switch-off to allow host processor to save
context. Device is maintained as ACTIVE until delay
expiration then switches off.
INT_LINE_DIS
Configure INT output to be standard buffer or highimpedance buffer with pullup to VIO
WDT_HOLD_IN_SLEEP
Configure watchdog timer operation during device sleep
state
PWRDOWN_FASTOFF
Configure shut-down sequence from PWRDOWN pin event
TSHUT_FASTOFF
Configure shut-down sequence from thermal shutdown event
RESET_OUT_OD
Configure RESET_OUT to be push-pull or open-drain
REGEN2_OD
Configure REGEN2 to be push-pull or open-drain
PMU_SECONDARY_INT
FSD_MASK
Secondary level of mask for FSD interrupt line
POLARITY_CTRL
INT_POLARITY
Configure polarity of INT line
SYNCCLKOUT
Configure SYNCCLKOUT to output SYNCDCDCCLK or
CLK32KGO
I2C_SPI
PMU_CONFIG
PMU_CTRL2
0: I2C
0: High VCC sense not enabled
0: AUTODEVON
disabled
00: No delay
0: Standard buffer: open-drain or push-pull
0: Watchdog timer continues to run in sleep state
0: PWRDOWN pin event triggers sequenced shut down
0: Thermal shutdown triggers sequenced shut down
0: RESET_OUT is push-pull
OD_OUTPUT_CTRL2
PRIMARY_SECONDARY
_PAD2
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1: FSD_INT_SRC is masked
0: INT line is low when interrupt is pending
0: SYNCDCDCCLK
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Static Platform Settings
5.7
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SWOFF_HWRST
This section describes whether each reset type is configured to generate a HWRST or SWORST.
Hardware reset (HWRST) — A hardware reset occurs when any OFF request is configured to generate a
hardware reset. This reset triggers a transition to the OFF state from either the ACTIVE or SLEEP
state (execute either the ACT2OFF or SLP2OFF sequence).
Switch-off reset (SWORST) — A switch-off reset occurs when any OFF request is configured to not
generate a hardware reset. This reset acts as the HWRST, except only the SWO registers are
reset. The device enters the OFF state, from either ACTIVE or SLEEP, and therefore executes the
ACT2OFF or SLP2OFF sequence.
The power resource control registers for SMPS and LDO voltage levels and operating mode control
are in SWORST domain. Additionally some registers control the 32-kHz, REGENx and SYSENx,
watchdog, and VSYS_MON comparator. This list is indicative only.
POR reset
HWRST reset
SWORST reset
POR Registers
v
SWO Registers
HW Registers
Figure 7. Reset Levels versus Registers
Table 15. SWOFF_HWRST OTP Settings
REGISTER
SWOFF_HWRST
12
BIT
DESCRIPTION
PWRON_LPK
Define if PWRON long key press is causing HWRST or
SWORST
PWRDOWN
Define if PWRDOWN pin is causing HWRST or
SWORST
WTD
Define if watchdog expiration is causing HWRST or
SWORST
1: HWRST
TSHUT
Define if thermal shutdown is causing HWRST or
SWORST
1: HWRST
RESET_IN
Define if RESET_IN pin is causing HWRST or
SWORST
1: HWRST
SW_RST
Define if register bit is causing HWRST or SWORST
1: HWRST
VSYS_LO
Define if VSYS_LO is causing HWRST or SWORST
GPADC_SHUTDOWN
Define if GPADC event is causing HWRST or SWORST
TPS65917-Q1 User’s Guide to Power DRA7xx and TDA2x/TDA2Ex
0x30, 0x31, 0x32, 0x33 VALUE
1: HWRST
0: SWORST
1: HWRST
0: SWORST
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5.8
Shutdown_ColdReset
These OTP settings show whether each OFF request is configured to generate a shutdown request (SD)
or cold reset request (CR).
• When configured to generate an SD, the embedded power controller (EPC) executes a transition to the
OFF state (SLP2OFF or ACT2OFF power sequence) and remains in the OFF state.
• When configured to generate a CR, the EPC executes a transition to the OFF state (SLP2OFF or
ACT2OFF power sequence) and restarts, transitioning to the ACTIVE state (OFF2ACT power
sequence) if none of the ON request gating conditions are present.
Table 16. Shutdown_ColdReset OTP Settings
REGISTER
BIT
DESCRIPTION
PWRON_LPK
Define if PWRON long key press causes shutdown or
cold reset
0: Shutdown
PWRDOWN
Define if PWRDOWN pin causes shutdown or cold
reset
0: Shutdown
WTD
Define if watchdog timer expiration causes shutdown
or cold reset
1: Cold reset
TSHUT
Define if thermal shutdown causes shutdown or cold
reset
0: Shutdown
RESET_IN
Define if RESET_IN pin causes shutdown or cold
reset
0: Shutdown
SW_RST
Define if SW_RST register bit causes shutdown or
cold reset
1: Cold reset
VSYS_LO
Define if VSYS_LO causes shutdown or cold reset
0: Shutdown
GPADC_SHUTDOWN
Define if GPADC shutdown causes shutdown or cold
reset
0: Shutdown
SWOFF_COLDRST
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0x30, 0x31, 0x32, 0x33 VALUE
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Sequence Platform Settings
6
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Sequence Platform Settings
A power sequence is an automatic preprogrammed sequence handled by the TPS65917-Q1 device to
configure the device resources: SMPSs, LDOs, part of GPIOs, and REGEN signals into ON, OFF, or
SLEEP state.
6.1
OFF2ACT Sequences
When an ON request occurs in the OFF state, the device is switched on and each resource is enabled
based on the programmed OFF2ACT sequence.
Figure 8 shows the OFF2ACT sequence of the O917A130TRGZRQ1 and O917A131TRGZRQ1 devices.
On Request
SMPS4
1.8 V
LDO5
1.8 V
SMPS5
1.35 V if BOOT = 0
1.5 V if BOOT = 1
GPIO_4
VIO
SMPS2
1.15 V
SMPS1
1.15 V
SMPS3
1.06 V
LDO3
1.8 V
LDO2
1.8 V
GPIO_0
1.8 V
LDO4
3.3 V
LDO1
Bypass
RESET_OUT
VIO
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
2.5 ms
550 µs
550 µs
Figure 8. OFF2ACT Sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1
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Figure 9 shows the OFF2ACT sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1 devices.
On Request
SMPS4
1.8 V
LDO5
1.8 V
SMPS5
1.35 V if BOOT = 0
1.5 V if BOOT = 1
GPIO_4
VIO
SMPS3
1.15 V
SMPS1
1.15 V
SMPS2
1.06 V
LDO3
1.8 V
LDO2
1.8 V
GPIO_0
1.8 V
LDO4
3.3 V
LDO1
Bypass
RESET_OUT
VIO
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
2.5 ms
550 µs
550 µs
Figure 9. OFF2ACT Sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1
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6.2
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ACT2OFF Sequences
When an OFF request occurs during active mode, each resource is disabled based on the programmed
ACT2OFF sequence.
Figure 10 shows the ACT2OFF sequences of O917A130TRGZRQ1 and O917A131TRGZRQ1 devices.
Off Request
RESET_OUT
LDO1
LDO4
GPIO_0
LDO2
550 µs
550 µs
550 µs
2.5 ms
LDO3
550 µs
SMPS3
550 µs
SMPS1
550 µs
SMPS2
GPIO_4
550 µs
SMPS5
550 µs
LDO5
550 µs
550 µs
SMPS4
Figure 10. Power Down Sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1
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Figure 11 shows the ACT2OFF sequences of O917A132TRGZRQ1 and O917A133TRGZRQ1 devices.
Off Request
RESET_OUT
LDO1
550 µs
550 µs
LDO4
550 µs
GPIO_0
2.5 ms
LDO2
LDO3
550 µs
SMPS2
550 µs
SMPS1
550 µs
SMPS3
GPIO_4
550 µs
SMPS5
550 µs
LDO5
550 µs
550 µs
SMPS4
Figure 11. Power Down Sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1
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Sequence Platform Settings
6.3
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ACT2SLP and SLP2ACT Sequences
When a SLEEP request occurs during active mode, each resource transitions to the sleep operating mode
(MODE_SLEEP bits of the corresponding CTRL register) based on the programmed ACT2SLP sequence.
When a WAKE request occurs during sleep mode, each resource transitions to the active operating mode
(MODE_ACTIVE bits of the corresponding CTRL register) based on the programmed SLP2ACT
sequence. Since OTP versions 0x30 and 0x32 do not have the NSLEEP function selected on GPIO_6,
they do not support a sleep sequence.
The sleep sequences of 0x31 and 0x33 are intended to support a DDR self-refresh mode. In this sleep
mode, all resources will remain off except for SMPS5 which powers the DDR supply. When using this
mode, GPIO_4 should enable a switch between SMPS5 and the processor's DDR domain, so that the
processor can be unpowered in DDR self refresh mode by disabling the switch while SMPS5 remains on.
The following five steps must occur before a resource shuts off in sleep mode.
Step 1. Each resource must be set to be OFF in sleep mode by clearing the MODE_SLEEP bits of
the appropriate xxxx_CTRL register, for example SMPS1_CTRL register.
Step 2. Each resource must be assigned to NSLEEP through the appropriate
NSLEEP_xxxx_ASSIGN registers. For example, the NSLEEP_SMPS_ASSIGN register.
Step 3. The NSLEEP pin must be unmasked through the POWER_CTRL.NSLEEP_MASK register bit
Step 4. All interrupts must be cleared, because any pending interrupt prevents the PMIC from going
to sleep mode.
Step 5. A SLEEP request is generated through the NSLEEP pin.
For the OTP versions 0x31 and 0x33 which support a sleep sequence, step 1 is completed in OTP. The
control register of each resource in the sleep sequences will have the MODE_SLEEP bits set to "0" after
power-up.
Note that RESET_OUT and GPIO_4 are in the VIO domain, and therefore output the same voltage as
VIO_IN. When VIO_IN is connected to SMPS4 or a switched 3.3V rail, then RESET_OUT will be shut off
during sleep mode at the same time as VIO_IN of the PMIC. If VIO_IN remains supplied during sleep
mode, then RESET_OUT will remain high. To keep the processor sequence requirements when using
DDR self-refresh mode, VIO_IN should not be disabled until GPIO_4 is turned off in the ACT2SLP
sequence, and VIO_IN should be enabled before GPIO_4 is turned on in the SLP2ACT sequence.
Figure 12 shows the ACT2SLP and SLP2ACT sequences of O917A131TRGZRQ1. Figure 13 shows the
ACT2SLP and SLP2ACT sequences of O917A133TRGZRQ1.
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NSLEEP
RESET_OUT
SLEEP Request
WAKE Request
Remains High
550 µs
LDO1
LDO4
GPIO_0
LDO2
2.5 ms
550 µs
550 µs
550 µs
2.5 ms
550 µs
LDO3
550 µs
550 µs
SMPS3
550 µs
550 µs
SMPS1
550 µs
550 µs
SMPS2
550 µs
550 µs
GPIO_4
SMPS5
Remains On
550 µs
550 µs
LDO5
550 µs
SMPS4
Figure 12. ACT2SLP and SLP2ACT Sequences of O917A131TRGZRQ1
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Sequence Platform Settings
NSLEEP
RESET_OUT
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SLEEP Request
WAKE Request
Remains High
550 µs
LDO1
LDO4
GPIO_0
LDO2
2.5 ms
550 µs
550 µs
550 µs
2.5 ms
550 µs
LDO3
SMPS2
SMPS1
SMPS3
GPIO_4
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
550 µs
SMPS5
Remains On
550 µs
550 µs
LDO5
550 µs
SMPS4
Figure 13. ACT2SLP and SLP2ACT Sequences of O917A133TRGZRQ1
20
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6.4
Warm Reset Sequences
A warm reset is triggered by the NRESWARM pin. During a warm reset, the OFF2ACT sequence is
executed regardless of the actual state (ACTIVE, SLEEP) and the device returns to or remains in the
ACTIVE state. Resources that are part of power-up sequence go to ACTIVE mode and the output voltage
level is reloaded from OTP or kept in the previous value depending on the WR_S bit in the SMPSx_CTRL
register or the LDOx_CTRL register. Resources that are not part of the OFF2ACT sequence are not
impacted by a warm reset and maintain the previous state.
Additionally, RESET_OUT is asserted low during the warm reset sequence. Therefore the PMIC must be
enabled by the POWERHOLD (GPIO_5) pin or by AUTODEVON. If POWERHOLD is set to GND and
AUTODEVON is disabled, the PMIC will shut off during the warm reset sequence.
Figure 14 shows the warm reset sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1. If any
resource is on when NRESWARM is asserted, the resource remains on as shown by the solid black lines.
The dashed red lines show the timing in case any resource is off before the warm reset. If VIO_IN is
switched off before the warm reset sequence, then RESET_OUT and GPIO_4 will be off because they are
in the VIO domain. In this example, VIO_IN is supplied by SMPS4, so RESET_OUT follows the SMPS4
timing.
NRESWARM
SMPS4
1.8 V
LDO5
1.8 V
SMPS5
1.35 V if BOOT = 0
1.5 V if BOOT =1
GPIO_4
VIO
SMPS2
AVS
SMPS1
AVS
1.15V
SMPS3
AVS
1.06V
LDO3
1.8 V
LDO2
1.8 V
GPIO_0
1.8 V
LDO4
3.3 V
LDO1
Bypass
RESET_OUT
VIO
550 µs
550 µs
1.15V
550 µs
550 µs
550 µs
550 µs
550 µs
2.5ms
550 µs
550 µs
Figure 14. Warm Reset Sequence of O917A130TRGZRQ1 and O917A131TRGZRQ1
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Figure 15 shows the warm reset sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1. If any
resource is on when NRESWARM is asserted, the resource remains on as shown by the solid black lines.
The dashed red lines show the timing in case any resource is off before the warm reset. If VIO_IN is
switched off before the warm reset sequence, then RESET_OUT and GPIO_4 will be off because they are
in the VIO domain. In this example, VIO_IN is supplied by SMPS4, so RESET_OUT follows the SMPS4
timing.
NRESWARM
SMPS4
1.8 V
LDO5
1.8 V
SMPS5
1.35 V if BOOT = 0
1.5 V if BOOT =1
GPIO_4
VIO
SMPS3
AVS
SMPS1
AVS
1.15V
SMPS2
AVS
1.06V
LDO3
1.8 V
LDO2
1.8 V
GPIO_0
1.8 V
LDO4
3.3 V
LDO1
Bypass
RESET_OUT
VIO
550 µs
550 µs
1.15V
550 µs
550 µs
550 µs
550 µs
550 µs
2.5ms
550 µs
550 µs
Figure 15. Warm Reset Sequence of O917A132TRGZRQ1 and O917A133TRGZRQ1
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from E Revision (October 2017) to F Revision ............................................................................................... Page
•
•
Added GPIO_6 function and load current requirements for Jacinto 6 processors in the OTP summary table ............... 2
Added information and diagrams on the two power up options for the TPS65917-Q1. ......................................... 5
Changes from E Revision (October 2017) to F Revision ............................................................................................... Page
•
•
Added GPIO_6 function and load current requirements for Jacinto 6 processors in the OTP summary table ............... 2
Added information and diagrams on the two power up options for the TPS65917-Q1. ......................................... 5
Changes from D Revision (July 2017) to E Revision ...................................................................................................... Page
•
Added GPIO_0 pull-up note
.............................................................................................................
9
Changes from C Revision (March 2017) to D Revision .................................................................................................. Page
•
Changed GPIO_3 to be in PRIMARY_SECONDARY_PAD1 register
.............................................................
9
Changes from B Revision (February 2016) to C Revision ............................................................................................. Page
•
First public release of document ........................................................................................................ 2
Changes from A Revision (December 2015) to B Revision ........................................................................................... Page
•
•
Updated System Voltage Monitoring ................................................................................................... 6
Removed reference to VCC_SENSE2 ................................................................................................. 7
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