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Texas Instruments Powering the AM335x With the TPS650250 (Rev. B) User guides
User's Guide
SLVU731B – May 2012 – Revised March 2018
Powering the AM335x With the TPS650250
This document details a power solution for the AM335x application processor with a TPS650250 power
management unit (PMU) or power management IC (PMIC).
Portable application solution size demands a high level of integration and the AM335x requires at least
three different voltage rails with specific power-on and power-off sequencing requirements. The
TPS650250 is a highly integrated power solution that provides the 1.8-, 3.3-, and 1.1-V rail signals
required by the AM335x. The TPS650250 has three step-down converters, three low-dropout (LDO)
regulators, and a voltage supervisor.
This document can be used as a reference for connectivity between the TPS650250 and the AM335x.
1
2
3
4
5
6
7
8
Contents
Power Requirements ........................................................................................................ 2
1.1
Power-On Sequence ............................................................................................... 3
1.2
Power-Off Sequence ............................................................................................... 3
Schematic ..................................................................................................................... 4
Waveforms .................................................................................................................... 5
Bill of Materials ............................................................................................................... 9
Use of a Clamping Circuit for Simultaneous Ramp Down ............................................................ 10
Using the TPS650250 to Support DDR3 or DDR3L ................................................................... 11
6.1
Adjusting DCDC2 Output Voltage to 1.5 V or 1.35 V ......................................................... 12
Conclusion .................................................................................................................. 13
References .................................................................................................................. 13
List of Figures
1
TPS650250 With Sequencing Circuit and AM335x Functional Block Diagram...................................... 2
2
TPS650250 Powering and Sequencing Circuit for the AM335x Powering Requirements ......................... 4
3
Power-On Sequence With PWRONRSTn
4
Power-On Sequence for the TPS650250 Converter Rails ............................................................. 6
5
Power-Off Sequence With PWRONRSTn ................................................................................ 7
6
Power-Off Sequence for the TPS650250 Converter Rails ............................................................. 8
7
Clamping Circuit ............................................................................................................ 10
8
TPS650250 Shutdown without Clamping Circuit ....................................................................... 11
9
TPS650250 Shutdown with Clamping Circuit
10
...............................................................................
..........................................................................
DCDC2 Resistor Change (R14) to Achieve 1.5 V .....................................................................
5
11
12
List of Tables
1
AM335x Power Requirements ............................................................................................. 2
2
Bill of Materials ............................................................................................................... 9
3
Clamp Circuit Testing ...................................................................................................... 10
4
AM335x Power Requirements for Supporting DDR3 or DDR3L ..................................................... 11
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Powering the AM335x With the TPS650250
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1
Power Requirements
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Trademarks
Sitara is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1
Power Requirements
Figure 1 shows a block diagram of the TPS650250-AM335x interface. Figure 2 shows a detailed circuit
schematic of the power solution (TPS650250 and sequencing circuit).
AM335x
Processor
VO_1.1
VIN = 6 V max
DCDC1
VCC,
VINDCDC1-3,
VIN_LDO
VDD_CORE, VDD_MPU, VDD_RTC
VO_1.8
DCDC2
SYS_EN
1.1 V
1.6 A
1.8 V
0.8 A
VDDS_DDR, VDDS, VDDS_RTC
VO_3.3
EN_DCDC2
EN_LDO
DCDC3
3.3 V
0.8 A
VDDA3P3V_USB0/1
VDDSHVx [1-6]
TPS650250
PMIC
VO_1.8
1.8 V
EN_DCDC3
LDO1
200 mA
VDDS_SRAM_CORE_BG,
VDDS_SRAM_MPU_BB, VDDA_ADC
VO_3.3
LDO2
EN_DCDC1
Vdd_alive
1.8 V
200 mA
VDDS_PLL_DDR, VDDS_PLL_CORE_LCD,
VDDS_PLL_MPU, VDDS_OSC,
VDDA1P8V_USB0/1
1.0 V
30 mA
VO_1.1
PWRFAIL
PWRONRSTn
PWRFAIL_SNS
DDR Memory
VDD, VDDQ, VDDCA,
VDD1, VDD2
RREF
VREF
Sequencing circuit
RREF
Copyright © 2018, Texas Instruments Incorporated
Figure 1. TPS650250 With Sequencing Circuit and AM335x Functional Block Diagram
Table 1 lists the AM335x power requirements.
Table 1. AM335x Power Requirements
TPS650250
Power-Up
Sequence
Power-Down
Sequence
Power
Supply
VOUT
[V]
IOUT
[mA]
3
1
DCDC1
2.8, 3.3,
Adjustable
1600
1.1
1
3
DCDC2
1.8, 2.5,
Adjustable
800
2
2
DCDC3
Adjustable
1
3
VLDO1
1-3.3
1
2
AM335x
Output
Voltage
[V]
3
Nominal
Rating
Grouping
Max
Current
[mA]
VDD_CORE, VDD_MPU, VDD_RTC
1.1 V ±4%
1.1-V Core
902
1.8
VDDS_DDR, VDDS, VDDS_RTC, VDDSHVx
1.8 V ±5%
1.8-V IO
605
800
3.3
VDDA3P3V_USB0, VDDA3P3V_USB1,
VDDSHVx
3.3 V ±5%
3.3-V Analog
and IO
370
200
1.8
VDDS_SRAM_MPU_BB,
VDDS_SRAM_CORE_BG, VDDA_ADC
1.8 V ±5%
1.8-V Analog
30
1.8 V ±5%
1.8-V Analog
125
n/a
n/a
n/a
Power Supply
VLDO2
1-3.3
200
1.8
VDDS_PLL_DDR, VDDS_PLL_MPU,
VDDS_PLL_CORE_LCD, VDDS_OSC,
VDDA1P8V_USB0, VDDA1P8V_USB1
VLDO3
1.0
30
1.0
n/a
Powering the AM335x With the TPS650250
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Power Requirements
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The TPS650250 meets these power requirements with its three step-down converters and three LDO
regulators. A simple sequencing circuit is required to meet power-sequence requirements. This document
details a power-sequencing solution for the RTC feature disable as described in the AM335x Sitara™
Processors data sheet and timing diagram, Power Supply Sequencing with RTC Feature Disabled.
1.1
Power-On Sequence
According to the excerpt from the AM335x datasheet, the device must be powered on in the following
order:
1. 1.8-V Analog and I/O
2. 3.3-V Analog and I/O
3. 1.1-V Core
An external system enable signal, SYS_EN, is enabled HIGH for power up. Diodes D2, D3, and D4 are
reversed biased. Diode D1 is forward biased and EN1.8 is HIGH. This turns ON the 1.8-V rails DCDC2,
LDO1, and LDO2. The output voltage of the DCDC2 converter, VO_1.8, is filtered into the enable of the
DCDC3 converter EN3.3 and creates an RC (R7 and C12) delay before turning ON the 3.3-V rail. When
EN3.3 reaches the turn-on threshold of the converter, VO_3.3 ramps up to nominal voltage. The output
voltage of the DCDC3 converter, VO_3.3, is filtered into the enable of the DCDC1 converter EN1.1 and
creates an RC (R16 and C15) delay before turning ON the 1.1 V rail. When EN1.1 reaches the turn-on
threshold of the converter, VO_1.1 ramps up to nominal voltage. Lastly, the output voltage of the DCDC1
converter VO_1.1 is filtered into the power sense fail pin of the TPS650250 PWRRAIL_SNS and creates
an RC (R17 and C16) delay between the last rail turning on and the Power On Reset signal,
PWRONRSTn, pulling HIGH. The PWRFAIL_SNS signal is sensed through an internal comparator in the
TPS650250 and triggers the PWRONRSTn signal HIGH when PWRRAIL_SNS reaches 1 V.
Power-on sequence is complete.
Figure 2 shows the correct connections for this power-on sequencing.
1.2
Power-Off Sequence
As shown in the excerpt from the AM335x data sheet, the device must be powered off in reverse order as
power-on.
1. 1.1-V Core
2. 3.3-V Analog and I/O
3. 1.8-V Analog and I/O
SYS_EN is LOW for power down. D2, D3, and D4 are forward biased. PWRFAIL_SNS becomes LOW to
pull PWRONRSTn LOW. EN1.1 becomes LOW and VO_1.1 ramps down. EN3.3 signal is filtered to create
an RC (R3 and C12) delay between VO_1.1 ramping down and VO_3.3 ramping down. Lastly, D1 is
reversed biased and capacitor C11 discharges through resistor R2 with a delay longer than the ramping
down of VO1.1 and VO3.3. After VO1.1 and VO3.3 are off, the 1.8-V rail ramps down.
Power-off sequence is complete.
Figure 2 shows the correct connections for this power-off sequencing.
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Schematic
2
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Schematic
Figure 2 shows the circuit schematic detailing the external components required by the TPS650250 to
achieve the 1.8-, 3.3-, and 1.1-V power rails required by the AM335x. In addition, Figure 2 shows the
sequencing circuit that achieves the proper power-on, power-off, and PWRONRSTn sequencing required
by the AM335x.
VIN
R1
10
C5
1µF
U1
29
5
L1
VCC
VINDCDC1
L1
VO_1.1
1600 mA max output current
SW1
6
VDD_CORE
VDD_MPU
VDD_RTC
2.2uH
C2
10uF
20
EN_1.1
VDCDC1
EN_DCDC1
8
PGND1
C6
10uF
DEFDCDC1
9
DEFDCDC1
7
L2
28
VINDCDC2
L2
C7
10uF
VO_1.8
800 mA max output current
SW2
27
VDDS_DDR
VDDS
VDDS_RTC
2.2uH
C3
10uF
19
EN1.8
VDCDC2
EN_DCDC2
25
DEFDCDC2
22
DEFDCDC2
PGND2
C8
10uF
26
L3
4
VINDCDC3
L3
C10
10uF
VO_3.3
800 mA max output current
SW3
3
VDDA3P3V_USB0
VDDA3P3V_USB1
2.2uH
C4
10uF
18
EN3.3
VDCDC3
EN_DCDC3
DEFDCDC3
PGND3
VIN
23
1
C9
10uF
DEFDCDC3
32
C1
10uF
2
VO2_1.8
MODE
VLDO1
200 mA max output current
16
VDDS_SRAM_MPU_BB
VDDS_SRAM_CORE_BG
VDDA_ADC
C13
2.2 µF
15
17
VINLDO
FB_LDO1
EN_LDO
VLDO2
FBLDO1
11
VO3_1.8
200 mA max output current
14
C14
2.2 µF
24
FB_LDO2
EN_VDD_ALIVE
VDD_ALIVE
30
PWRFAIL_SNS
PWRFAIL
PWRFAIL_SNS
AGND1
AGND2
PAD
VDDS_PLL_DDR
VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
VDDS_OSC
VDDA1P8V_USB0
VDDA1P8V_USB1
VO_3.3
FBLDO2
10
R1
100k
12
21
PWRONRSTn
31
13
33
TPS650250RHBR
On-Off Sequence Circuit
D1
SYS_EN
EN1.8
External resistors for setting DCDCx and LDOx Voltages
MBR0540T1G
C11
1µF
R2
5.1k
VO_1.8
Voltage Divider for DEFDCDC1
Voltage Divider for DEFDCDC2
VO_1.1
Voltage Divider for DEFDCDC3
VO_1.8
VO_3.3
R7
2.0k
D2
EN3.3
R3
R12
165k
R14
402k
DEFDCDC1
1.0k
R11
432k
DEFDCDC2
DEFDCDC3
MBR0540T1G
VO_3.3
R13
200k
C12
1µF
R15
200k
R10
95.3k
R16
2.0k
D3
EN_1.1
Voltage Divider for FBLDO1
MBR0540T1G
C15
1µF
VO2_1.8
Voltage Divider for FBLDO2
VO3_1.8
VO_1.1
R6
162k
R17
1.0k
D4
R8
162k
FBLDO1
PWRFAIL_SNS
R5
200k
MBR0540T1G
C16
1µF
FBLDO2
R9
200k
Copyright © 2018, Texas Instruments Incorporated
Figure 2. TPS650250 Powering and Sequencing Circuit for the AM335x Powering Requirements
4
Powering the AM335x With the TPS650250
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Waveforms
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3
Waveforms
The following waveforms demonstrate the power-on and power-off sequence of the TPS650250 as
required by the AM335x.
Figure 3 shows the power-on sequence for each of the output voltage rails and the PWRONRSTn signal.
The 1.8-, 3.3-, and 1.1-V rails turn on sequentially and the PWRONRSTn signal goes HIGH after all rails
are ON.
PWRONRSTn 5V/div
DCDC2 1 V/div
DCDC3 1 V/div
DCDC1 1 V/div
Time scale = 1 ms/div
1.8-V (DCDC2), 3.3-V (DCDC3), and 1.1-V (DCDC1) Rails
Figure 3. Power-On Sequence With PWRONRSTn
Figure 4 shows the power-on sequence for each of the output voltages of the TPS650250. DCDC2 (1.8 V)
and the LDOs (1.8 V) of the TPS650250 turn on before DCDC3 (3.3 V) and DCDC1 (1.1 V).
Figure 5 shows the power-off sequence for each of the output voltage rails and the PWRONRSTn signal.
The 1.8-, 3.3-, and 1.1-V rails turn off sequentially and the PWRONRSTn signal goes LOW when the 1.1V rail begins to ramp down.
Figure 6 shows the power-off sequence for each of the output voltages of the TPS650250. DCDC2 (1.8 V)
and the LDOs (1.8 V) of the TPS650250 turn off after DCDC1 (1.1 V) and DCDC3 (3.3 V) have ramped
down.
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Waveforms
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LDO1/2 1 V/div
DCDC2 1 V/div
DCDC3 1 V/div
DCDC1 1 V/div
Time scale = 1 ms/div
1.8-V (DCDC2,LDO1/2), 3.3-V (DCDC3), and 1.1-V (DCDC1) Rails
Figure 4. Power-On Sequence for the TPS650250 Converter Rails
6
Powering the AM335x With the TPS650250
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Waveforms
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PWRONRSTn 5V/div
DCDC2 1 V/div
DCDC3 1 V/div
DCDC1 1 V/div
Time scale = 1 ms/div
1.8-V (DCDC2), 3.3-V (DCDC3), and 1.1-V (DCDC1) Rails
Figure 5. Power-Off Sequence With PWRONRSTn
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Waveforms
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LDO1/2 1 V/div
DCDC2 1 V/div
DCDC3 1 V/div
DCDC1 1 V/div
Time
scale= =1 ms/div
1 ms/div
Time scale
1.8-V (DCDC2,LDO1/2), 3.3-V (DCDC3), and 1.1-V (DCDC1) Rails
Figure 6. Power-Off Sequence for the TPS650250 Converter Rails
8
Powering the AM335x With the TPS650250
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Bill of Materials
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4
Bill of Materials
Table 2 lists the bill of materials (BOM).
Table 2. Bill of Materials
Count
RefDes
Value
Description
Size
Part Number
MFR
1
C1
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C2
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C3
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C4
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C5
1.0 µF
Capacitor, ceramic, 6.3 V, X5R,10%
0603
Std
Std
1
C6
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C7
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C8
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C9
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C10
10 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C11
1 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C12
1 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C13
2.2 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0603
Std
Std
1
C14
2.2 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0603
Std
Std
1
C15
1 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
C16
1 µF
Capacitor, ceramic, 6.3 V, X5R, 10%
0805
Std
Std
1
D1
MBR054O
Diode, Schottky, 0.5 A, x0V
SOD-123
MBR054O
MCC Semi
1
D2
MBR054O
Diode, Schottky, 0.5 A, x0V
SOD-123
MBR054O
MCC Semi
1
D3
MBR054O
Diode, Schottky, 0.5 A, x0V
SOD-123
MBR054O
MCC Semi
1
D4
MBR054O
Diode, Schottky, 0.5 A, x0V
SOD-123
MBR054O
MCC Semi
1
L1
2.2 µH
Inductor, SMT, 1.72 A, 59 mΩ
0.157 × 0.157 inch
VLCF4020T-2R2N1R7
TDK
1
L2
3.3 µH
Inductor, SMT, 1.52 A, 78 mΩ
0.157 × 0.157 inch
VLCF4020T-3R3N1R5
TDK
1
L3
2.2 µH
Inductor, SMT, 1.72 A, 59 mΩ
0.157 × 0.157 inch
VLCF4020T-2R2N1R7
TDK
1
R1
100 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R2
5 kΩ
Resistor, chip, 1/16W, 5%
0603
Std
Std
1
R3
1 kΩ
Resistor, chip, 1/16W, 5%
0603
Std
Std
1
R4
1Ω
Resistor, chip, 1/16W, 5%
0603
Std
Std
1
R5
200 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R6
162 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R7
2 kΩ
Resistor, chip, 1/16W, 5%
0603
Std
Std
1
R8
162 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R9
200 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R10
95.3 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R11
432 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R12
165 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R13
200 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R14
402 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R15
200 kΩ
Resistor, chip, 1/16W, 1%
0603
Std
Std
1
R16
2 kΩ
Resistor, chip, 1/16W, 5%
0603
Std
Std
1
R17
1 kΩ
Resistor, chip, 1/16W, 5%
0603
Std
Std
1
U1
TPS650250
IC, Power Management ICs for Li-Ion Powered
Systems
QFN-32
TI
Notes: 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG components.
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Use of a Clamping Circuit for Simultaneous Ramp Down
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Use of a Clamping Circuit for Simultaneous Ramp Down
Ramping down the VDDS and VDDSHVx [1–6] power rails for the AM335x processor at the same time
presents a challenge that is made clear in the AM335x Sitara™ Processors data sheet. For this power
design, the following statement only refers to the DCDC2 rail named VO_1.8 (1.8-V for VDDS of the
processor) and the DCDC3 rail named VO_3.3 (3.3-V for VDDSHVx of the processor):
If it is desired to ramp down VDDS and VDDSHVx [1–6] simultaneously, it should always be ensured
that the difference between VDDS and VDDSHVx [1–6] during the entire power-down sequence is
< 2 V. If this is violated it can result in reliability risks for the device.
The worst-case scenario of this issue is the 3.3-V rail remains high possibly because of large output
capacitance or no load being present on the output while, the 1.8-V rail ramps down quickly such as if it
were fully loaded.
A solution to this issue is the use of a clamping circuit between the 1.8-V VDDS and 3.3-V VDDSHVx
rails, ensuring proper shutdown when VIN is removed. As illustrated in Figure 7, the clamping circuit
suggested is only five additional components, 3 of which are resistors. The 3.3-V VDDSHVx rail powered
by DCDC3 is shown using the net name VO_3.3 as defined by the schematic in Figure 2. The 1.8-V
VDDS rail powered by DCDC2 is shown using the net name VO_1.8 as defined by the schematic. The
TLVH431 is regulated at 1.5 V through resistor divider R1 and R2. Before the rails ramp down, Q1 is off.
When the 1.8-V rail drops, Vbase drops and Q1 turns ON. The 3.3-V rail discharges through Q1 and the
1.8-V rail. This technique ensures that the difference between the 3.3-V VDDSHVx rails and the 1.8-V
VDDS rail never exceeds 2 V.
VO_3.3
R3
500 Ω
2N2907A
Q1
R1
10 kΩ
U1
TLVH431
R2
40 kΩ
VO_1.8
Figure 7. Clamping Circuit
Figure 8 shows the power-down sequence for the DCDCs, LDOs and PWRONRSTn outputs and signals
of the TPS650250 without the clamping circuit. This is the worst-case scenario since the VDDSHVx 3.3-V
rail is not loaded at all while the VDDS 1.8-V rail is fully loaded. Notice that the difference between
DCDC3 and DCDC2 (VDDSHVx and VDDS) exceeds 2 V. Table 3 lists details of the testing performed to
identify this violation of the AM335x data sheet.
Figure 9 shows the power-down sequence for the DCDCs, LDOs and PWRONRSTn output voltages of
the TPS650250 with the clamping circuit. With the same load conditions, the clamp circuit test results
show the difference between DCDC3 and DCDC2 is kept below 2 V. Notice how the 3.3-V rail tracks the
1.8-V rail. Refer to Table 3 for more testing details.
Table 3. Clamp Circuit Testing
10
Rail
Steady-State VOUT [V]
Net Name
Load Current [mA]
DCDC2
1.8
VO_1.8
600
DCDC3
3.3
VO_3.3
0.01
DCDC3 – DCDC2
(3.3 – 1.8) = 1.5
(VO_3.3 – VO_1.8)
n/a
Powering the AM335x With the TPS650250
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Using the TPS650250 to Support DDR3 or DDR3L
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Figure 8. TPS650250 Shutdown without Clamping Circuit
Figure 9. TPS650250 Shutdown with Clamping Circuit
6
Using the TPS650250 to Support DDR3 or DDR3L
The TPS650250 provides the power required by the AM335x and is capable of supporting external DDR3
or DDR3L memory applications. However, the 1.8-V I/O output current capabilities are reduced from what
was presented in Section 1. Table 4 shows the power requirements for powering the AM335x with DDR3
or DDR3L support.
Table 4. AM335x Power Requirements for Supporting DDR3 or DDR3L
TPS650250
AM335x
Power-Up
Sequence
Power-Down
Sequence
Power
Supply
VOUT
[V]
IOUT
[mA]
Output
Voltage
[V]
4
1
DCDC1
2.8, 3.3,
Adjustable
1600
1.1
2
3
DCDC2
1.8, 2.5,
Adjustable
3
2
DCDC3
Adjustable
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Nominal
Rating
Grouping
Max
Current
[mA]
VDD_CORE, VDD_MPU,
VDD_RTC
1.1 V ± 4%
1.1-V
Core
902
800
1.5,
1.35
VDDS_DDR
1.5 V ± 5%,
1.35 ± 5%
1.5-V (DDR3),
1.35-V (DDR3L)
300
800
3.3
VDDA3P3V_USB0,
VDDA3P3V_USB1, VDDSHVx
3.3 V ±5%
3.3-V
Analog and IO
370
Power Supply
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11
Using the TPS650250 to Support DDR3 or DDR3L
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Table 4. AM335x Power Requirements for Supporting DDR3 or DDR3L (continued)
TPS650250
Power-Up
Sequence
Power-Down
Sequence
Power
Supply
AM335x
VOUT
[V]
IOUT
[mA]
Output
Voltage
[V]
Power Supply
1
4
VLDO1
1–3.3
200
1.8
VDDS_SRAM_MPU_BB,
VDDS_SRAM_CORE_BG,
VDDA_ADC,
VDDSHVx,VDDS_PLL_DDR,
VDDS_PLL_MPU,
VDDS_PLL_CORE_LCD,
VDDS_OSC, VDDA1P8V_USB0,
VDDA1P8V_USB1
1
4
VLDO2
1–3.3
200
1.8
VDDS, VDDS_RTC, VDDSHVx
VLDO3
1.0
30
1.0
n/a
Nominal
Rating
Grouping
Max
Current
[mA]
1.8 V ± 5%
1.8-V
Analog
155
1.8 V ± 5%
1.8-V
IO
55
n/a
n/a
n/a
On the TPS650250, DCDC2 is dedicated to 1.5 V to support external DDR3 applications. The AM335x
DDR3 I/O domain (VDDS_DDR) must be 1.5 V, leaving 500 mA of available current for external DDR3
memory. The output voltage of DCDC2 is set to 1.35 V to support DDR3L with lower supply voltage.
The 1.8-V I/O domains (VDDSHVx) are now powered through the 1.8-V rails, VLDO1 and VLDO2, of the
TPS650250. The added loads cause current constraints on LDO1 and LDO2 so as not to go over the
rated current of 200 mA. Therefore, the AM335x must be operated such that VDDSHVx does not cause
each LDO current to exceed 200 mA on VLDO1 or VLDO2.
6.1
Adjusting DCDC2 Output Voltage to 1.5 V or 1.35 V
A 1.5-V rail is required to power DDR3. If R15 is 200 kΩ, change R14 to 301 kΩ to adjust the output
voltage of DCDC2 to 1.5 V. Figure 10 shows this change of the resistor divider for DCDC2.
DCDC2
1.35 V
DCDC2 Block
(TPS650250)
L2
R14
301 k
DEFDCDC2
R15
200 k
Figure 10. DCDC2 Resistor Change (R14) to Achieve 1.5 V
A 1.35-V rail is required to power DDR3L. If R15 is kept as 200 kΩ, change R14 to 255 kΩ to adjust the
output voltage to 1.35 V.
12
Powering the AM335x With the TPS650250
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Conclusion
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7
Conclusion
The TPS650250 provides a low-cost, comprehensive power solution for the AM335x. This reference
design demonstrates the external components of the TPS650250 to provide the required voltage rails and
a simple sequencing circuit that meets power-on and power-off sequencing required by the AM335x. For
external DDR3 applications, the output voltage of DCDC2 for the TPS650250 can be easily adjusted to
accommodate a 1.5-V rail. However, this limits the output-current capabilities of the 1.8-V I/O Domains
(VDDSHVx) in the AM335x. If simultaneous ramp down of the VDDSHVx and VDDS rail is desired a
clamping circuit may be required.
8
References
1. Texas Instruments, TPS650250 Power Management IC for Li-Ion Powered Systems data sheet
2. Texas Instruments, AM335x, AM335x ARM® Cortex™-A8 Microprocessors (MPUs) data sheet
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Powering the AM335x With the TPS650250
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13
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (December 2012) to B Revision ........................................................................................... Page
•
•
•
•
14
Updated resolution and clarity of all figures ........................................................................................... 2
Clarified terminology and test data in the Use of a Clamping Circuit for Simultaneous Ramp Down section ............... 10
Moved the Use of a Clamping Circuit for Simultaneous Ramp Down section to before the Using the TPS650250 to
Support DDR3 section .................................................................................................................. 10
Added support for DDR3L (1.35 V) in the Using the TPS650250 to Support DDR3 section .................................. 12
Revision History
SLVU731B – May 2012 – Revised March 2018
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