Texas Instruments | DM50x SoC for Vision Analytics (Rev. B) | User Guides | Texas Instruments DM50x SoC for Vision Analytics (Rev. B) User guides

Texas Instruments DM50x SoC for Vision Analytics (Rev. B) User guides
DM50x
SoC for Vision Analytics
Silicon Revision 2.0
Texas Instruments Family of Products
Technical Reference Manual
Literature Number: SPRUIC6B
January 2017 – Revised October 2017
Contents
Revision History ........................................................................................................................ 307
Preface ..................................................................................................................................... 308
1
Introduction ..................................................................................................................... 315
1.1
1.2
1.3
1.4
1.5
1.6
2
2.3
2.4
2.5
2.6
2.7
Introduction ................................................................................................................
L3_MAIN Memory Map ..................................................................................................
2.2.1 L3_INSTR Memory Map ........................................................................................
L4 Memory Map ...........................................................................................................
2.3.1 L4_CFG Memory Map ..........................................................................................
2.3.2 L4_WKUP Memory Map ........................................................................................
L4_PER Memory Map ....................................................................................................
2.4.1 L4_PER1 Memory Space Mapping............................................................................
2.4.2 L4_PER2 Memory Map .........................................................................................
2.4.3 L4_PER3 Memory Map .........................................................................................
IPU Memory Map .........................................................................................................
DSP Memory Map ........................................................................................................
EVE Memory Map ........................................................................................................
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Memory Mapping .............................................................................................................. 329
2.1
2.2
3
DM50x Overview ..........................................................................................................
DM50x Environment ......................................................................................................
DM50x Description .......................................................................................................
1.3.1 Block Diagram ....................................................................................................
1.3.2 MCU Subsystem .................................................................................................
1.3.3 DSP Subsystem..................................................................................................
1.3.4 EVE Subsystem ..................................................................................................
1.3.5 Imaging Subsystem..............................................................................................
1.3.6 Video Input Capture .............................................................................................
1.3.7 Display Subsystem ..............................................................................................
1.3.8 On-Chip Debug Support ........................................................................................
1.3.9 On-Chip Memory .................................................................................................
1.3.10 Memory Management ..........................................................................................
1.3.11 External Memory Interfaces ...................................................................................
1.3.12 Power, Reset, and Clock Management ......................................................................
1.3.13 System and Connectivity Peripherals ........................................................................
1.3.13.1 System Peripherals........................................................................................
1.3.13.2 Connectivity Peripherals ..................................................................................
1.3.13.3 Serial Control Peripherals ................................................................................
DM50x Family .............................................................................................................
DM50x Device Identification .............................................................................................
DM50x Package Characteristics Overview ............................................................................
Device Power Management Introduction ..............................................................................
3.1.1 Device Power-Management Architecture Building Blocks..................................................
3.1.1.1
Clock Management ........................................................................................
3.1.1.1.1 Module Interface and Functional Clocks ...........................................................
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3.2
3.3
3.4
3.5
3.1.1.1.2 Module-Level Clock Management ..................................................................
3.1.1.1.3 Clock Domain ..........................................................................................
3.1.1.1.4 Clock Domain-Level Clock Management ..........................................................
3.1.1.1.5 Clock Domain HW_AUTO Mode Sequences .....................................................
3.1.1.1.6 Clock Domain Sleep/Wake-up ......................................................................
3.1.1.1.7 Clock Domain Dependency ..........................................................................
3.1.1.2
Power Management .......................................................................................
3.1.1.2.1 Power Domain .........................................................................................
3.1.1.2.2 Module Logic and Memory Context ................................................................
3.1.1.2.3 Power Domain Management ........................................................................
3.1.1.3
Voltage Management .....................................................................................
3.1.1.3.1 Voltage Domain .......................................................................................
3.1.1.3.2 Voltage Domain Management .......................................................................
3.1.1.3.3 AVS Overview .........................................................................................
3.1.2 Power-Management Techniques ..............................................................................
3.1.2.1
Standby Leakage Management .........................................................................
3.1.2.2
Dynamic Voltage and Frequency Scaling ..............................................................
3.1.2.3
Dynamic Power Switching ................................................................................
3.1.2.4
Adaptive Voltage Scaling .................................................................................
3.1.2.5
Combining Power-Management Techniques ..........................................................
3.1.2.5.1 DPS Versus SLM .....................................................................................
PRCM Subsystem Overview ............................................................................................
3.2.1 Introduction .......................................................................................................
3.2.2 Power-Management Framework Features ...................................................................
PRCM Subsystem Environment ........................................................................................
3.3.1 External Clock Signals ..........................................................................................
3.3.2 External Boot Signals ...........................................................................................
3.3.3 External Reset Signals ..........................................................................................
3.3.4 External Voltage Inputs .........................................................................................
PRCM Subsystem Integration ...........................................................................................
3.4.1 Device Power-Management Layout ...........................................................................
3.4.2 Power-Management Scheme, Reset, and Interrupt Requests.............................................
3.4.2.1
Power Domain .............................................................................................
3.4.2.2
Resets.......................................................................................................
3.4.2.3
PRCM Interrupt Requests ................................................................................
Reset Management Functional Description ...........................................................................
3.5.1 Overview ..........................................................................................................
3.5.1.1
Reset Management Functional Description ............................................................
3.5.1.1.1 Power-On Reset ......................................................................................
3.5.1.1.2 Warm Reset ...........................................................................................
3.5.1.2
PRM Reset Management Functional Description .....................................................
3.5.2 General Characteristics of Reset Signals ....................................................................
3.5.2.1
Scope .......................................................................................................
3.5.2.2
Occurrence .................................................................................................
3.5.2.3
Source Type ................................................................................................
3.5.2.4
Retention Type .............................................................................................
3.5.3 Reset Sources....................................................................................................
3.5.3.1
Global Reset Sources .....................................................................................
3.5.3.2
Local Reset Sources ......................................................................................
3.5.4 Reset Logging ....................................................................................................
3.5.5 Reset Domains ...................................................................................................
3.5.6 Reset Sequences ................................................................................................
3.5.6.1
IPU1 Subsystem Power-On Reset Sequence .........................................................
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3.6
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3.5.6.2
DSP1 Subsystem Power-On Reset Sequence ........................................................
3.5.6.3
DSP1 Subsystem Software Warm Reset Sequence..................................................
3.5.6.4
DSP2 Subsystem Power-On Reset Sequence ........................................................
3.5.6.5
DSP2 Subsystem Software Warm Reset Sequence..................................................
3.5.6.6
EVE Subsystem Power-On Reset Sequence ..........................................................
3.5.6.7
EVE Subsystem Software Warm Reset Sequence ...................................................
3.5.6.8
Global Warm Reset Sequence ..........................................................................
Clock Management Functional Description ...........................................................................
3.6.1 Overview ..........................................................................................................
3.6.2 External Clock Inputs ............................................................................................
3.6.2.1
High-Frequency System Clock Input ....................................................................
3.6.2.2
External Reference Clock Input .........................................................................
3.6.3 Internal Clock Sources/Generators ............................................................................
3.6.3.1
PRM Clock Source ........................................................................................
3.6.3.2
CM Clock Source ..........................................................................................
3.6.3.2.1 CM_CORE_AON Clock Generator .................................................................
3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview .......................................................
3.6.3.2.3 CM_CORE_AON_TIMER Overview ...............................................................
3.6.3.2.4 CM_CORE_AON_MCASP1 Overview ............................................................
3.6.3.3
Clock Control in Control Module .........................................................................
3.6.3.3.1 Programming Guide For Control Module ..........................................................
3.6.3.4
Generic DPLL Overview ..................................................................................
3.6.3.4.1 DPLLs Output Clocks Parameters ..................................................................
3.6.3.4.2 Enable Control, Status, and Low-Power Operation Mode .......................................
3.6.3.4.3 DPLL Power Modes ..................................................................................
3.6.3.4.4 DPLL Recalibration ...................................................................................
3.6.3.4.5 DPLL Output Power Down ...........................................................................
3.6.3.5
DPLL_PER Description ...................................................................................
3.6.3.5.1 DPLL_PER Overview .................................................................................
3.6.3.5.2 DPLL_PER Synthesized Clock Parameters .......................................................
3.6.3.5.3 DPLL_PER Power Modes ...........................................................................
3.6.3.5.4 DPLL_PER Recalibration ............................................................................
3.6.3.6
DPLL_CORE Description .................................................................................
3.6.3.6.1 DPLL_CORE Overview ..............................................................................
3.6.3.6.2 DPLL_CORE Synthesized Clock Parameters .....................................................
3.6.3.6.3 DPLL_CORE Power Modes .........................................................................
3.6.3.6.4 DPLL_CORE Recalibration ..........................................................................
3.6.3.6.5 Fractional M-factor ...................................................................................
3.6.3.7
DPLL_EVE_VID_DSP Description ......................................................................
3.6.3.7.1 DPLL_EVE_VID_DSP Overview ....................................................................
3.6.3.7.2 DPLL_EVE_VID_DSP Synthesized Clock Parameters ..........................................
3.6.3.7.3 DPLL_EVE_VID_DSP Power Modes ..............................................................
3.6.3.7.4 DPLL_EVE_VID_DSP Recalibration ...............................................................
3.6.3.8
DPLL_GMAC_DSP Description .........................................................................
3.6.3.8.1 DPLL_GMAC_DSP Overview .......................................................................
3.6.3.8.2 DPLL_GMAC_DSP Synthesized Clock Parameters .............................................
3.6.3.8.3 DPLL_GMAC_DSP Power Modes ..................................................................
3.6.3.8.4 DPLL_GMAC_DSP Recalibration...................................................................
3.6.3.9
DPLL_DDR Description...................................................................................
3.6.3.9.1 DPLL_DDR Overview ................................................................................
3.6.3.9.2 DPLL_DDR Synthesized Clock Parameters.......................................................
3.6.3.9.3 DPLL_DDR Power Modes ...........................................................................
3.6.3.9.4 DPLL_DDR Recalibration ............................................................................
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3.6.4 Clock Domains ...................................................................................................
3.6.4.1
CD_WKUPAON Clock Domain ..........................................................................
3.6.4.1.1 Overview ...............................................................................................
3.6.4.1.2 Clock Domain Modes .................................................................................
3.6.4.1.3 Clock Domain Dependency ..........................................................................
3.6.4.1.4 Clock Domain Module Attributes ....................................................................
3.6.4.2
CD_DSP1 Clock Domain .................................................................................
3.6.4.2.1 Overview ...............................................................................................
3.6.4.2.2 Clock Domain Modes .................................................................................
3.6.4.2.3 Clock Domain Dependency ..........................................................................
3.6.4.2.4 Clock Domain Module Attributes ....................................................................
3.6.4.3
CD_DSP2 Clock Domain .................................................................................
3.6.4.3.1 Overview ...............................................................................................
3.6.4.3.2 Clock Domain Modes .................................................................................
3.6.4.3.3 Clock Domain Dependency ..........................................................................
3.6.4.3.4 Clock Domain Module Attributes ....................................................................
3.6.4.4
CD_CUSTEFUSE Clock Domain........................................................................
3.6.4.4.1 Overview ...............................................................................................
3.6.4.4.2 Clock Domain Modes .................................................................................
3.6.4.4.3 Clock Domain Dependency ..........................................................................
3.6.4.4.4 Clock Domain Module Attributes ....................................................................
3.6.4.5
CD_L4PER1 Clock Domain ..............................................................................
3.6.4.5.1 Overview ...............................................................................................
3.6.4.5.2 Clock Domain Modes .................................................................................
3.6.4.5.3 Clock Domain Dependency ..........................................................................
3.6.4.5.4 Clock Domain Module Attributes ....................................................................
3.6.4.6
CD_L4PER2 Clock Domain ..............................................................................
3.6.4.6.1 Overview ...............................................................................................
3.6.4.6.2 Clock Domain Modes .................................................................................
3.6.4.6.3 Clock Domain Dependency ..........................................................................
3.6.4.6.4 Clock Domain Module Attributes ....................................................................
3.6.4.7
CD_L4PER3 Clock Domain ..............................................................................
3.6.4.7.1 Overview ...............................................................................................
3.6.4.7.2 Clock Domain Modes .................................................................................
3.6.4.7.3 Clock Domain Dependency ..........................................................................
3.6.4.7.4 Clock Domain Module Attributes ....................................................................
3.6.4.8
CD_L3INIT Clock Domain ................................................................................
3.6.4.8.1 Overview ...............................................................................................
3.6.4.8.2 Clock Domain Modes .................................................................................
3.6.4.8.3 Clock Domain Dependency ..........................................................................
3.6.4.8.4 Clock Domain Module Attributes ....................................................................
3.6.4.9
CD_EMU Clock Domain ..................................................................................
3.6.4.9.1 Overview ...............................................................................................
3.6.4.9.2 Clock Domain Modes .................................................................................
3.6.4.9.3 Clock Domain Dependency ..........................................................................
3.6.4.9.4 Clock Domain Module Attributes ....................................................................
3.6.4.10 CD_DSS Clock Domain ..................................................................................
3.6.4.10.1 Overview ...............................................................................................
3.6.4.10.2 Clock Domain Modes.................................................................................
3.6.4.10.3 Clock Domain Dependency .........................................................................
3.6.4.10.4 Clock Domain Module Attributes....................................................................
3.6.4.11 CD_L4_CFG Clock Domain ..............................................................................
3.6.4.11.1 Overview ...............................................................................................
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3.6.4.11.2 Clock Domain Modes.................................................................................
3.6.4.11.3 Clock Domain Dependency .........................................................................
3.6.4.11.4 Clock Domain Module Attributes....................................................................
3.6.4.12 CD_L3_INSTR Clock Domain ...........................................................................
3.6.4.12.1 Overview ...............................................................................................
3.6.4.12.2 Clock Domain Modes.................................................................................
3.6.4.12.3 Clock Domain Dependency .........................................................................
3.6.4.12.4 Clock Domain Module Attributes....................................................................
3.6.4.13 CD_L3_MAIN1 Clock Domain ...........................................................................
3.6.4.13.1 Overview ...............................................................................................
3.6.4.13.2 Clock Domain Modes.................................................................................
3.6.4.13.3 Clock Domain Dependency .........................................................................
3.6.4.13.4 Clock Domain Module Attributes....................................................................
3.6.4.14 CD_EMIF Clock Domain .................................................................................
3.6.4.14.1 Overview ...............................................................................................
3.6.4.14.2 Clock Domain Modes.................................................................................
3.6.4.14.3 Clock Domain Dependency .........................................................................
3.6.4.14.4 Clock Domain Module Attributes....................................................................
3.6.4.15 CD_IPU Clock Domain ...................................................................................
3.6.4.15.1 Overview ...............................................................................................
3.6.4.15.2 Clock Domain Modes.................................................................................
3.6.4.15.3 Clock Domain Dependency .........................................................................
3.6.4.15.4 Clock Domain Module Attributes....................................................................
3.6.4.16 CD_IPU1 Clock Domain ..................................................................................
3.6.4.16.1 Overview ...............................................................................................
3.6.4.16.2 Clock Domain Modes.................................................................................
3.6.4.16.3 Clock Domain Dependency .........................................................................
3.6.4.16.4 Clock Domain Module Attributes....................................................................
3.6.4.17 CD_CRC Clock Domain ..................................................................................
3.6.4.17.1 Overview ...............................................................................................
3.6.4.17.2 Clock Domain Modes.................................................................................
3.6.4.17.3 Clock Domain Module Attributes....................................................................
3.6.4.18 CD_CAM Clock Domain ..................................................................................
3.6.4.18.1 Overview ...............................................................................................
3.6.4.18.2 Clock Domain Modes.................................................................................
3.6.4.18.3 Clock Domain Dependency .........................................................................
3.6.4.18.4 Clock Domain Module Attributes....................................................................
3.6.4.19 CD_COREAON_L4 Clock Domain ......................................................................
3.6.4.19.1 CD_COREAON_L4 Overview .......................................................................
3.6.4.19.2 Clock Domain Modes.................................................................................
3.6.4.19.3 Clock Domain Dependency .........................................................................
3.6.4.20 CD_GMAC Clock Domain ................................................................................
3.6.4.20.1 Overview ...............................................................................................
3.6.4.20.2 Clock Domain Modes.................................................................................
3.6.4.20.3 Clock Domain Dependency .........................................................................
3.6.4.20.4 Clock Domain Module Attributes....................................................................
3.6.4.21 CD_ISS Clock Domain....................................................................................
3.6.4.21.1 CD_ISS Overview.....................................................................................
3.6.4.21.2 Clock Domain Modes.................................................................................
3.6.4.21.3 Clock Domain Dependency .........................................................................
3.6.4.21.4 Clock Domain Module Attributes....................................................................
3.6.4.22 CD_EVE1 Clock Domain .................................................................................
3.6.4.22.1 CD_EVE1 Overview ..................................................................................
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3.7
3.8
3.6.4.22.2 Clock Domain Modes.................................................................................
3.6.4.22.3 Clock Domain Dependency .........................................................................
3.6.4.22.4 Clock Domain Module Attributes....................................................................
Power Management Functional Description...........................................................................
3.7.1 PD_WKUPAON Description ....................................................................................
3.7.1.1
Power Domain Modes ....................................................................................
3.7.1.1.1 Logic and Memory Area Power Modes ............................................................
3.7.2 PD_DSP1 Description ...........................................................................................
3.7.2.1
Power Domain Modes ....................................................................................
3.7.2.1.1 Logic and Memory Area Power Modes ............................................................
3.7.2.1.2 Logic and Memory Area Power Modes Control and Status .....................................
3.7.3 PD_DSP2 Description ...........................................................................................
3.7.3.1
Power Domain Modes ....................................................................................
3.7.3.1.1 Logic and Memory Area Power Modes ............................................................
3.7.3.1.2 Logic and Memory Area Power Modes Control and Status .....................................
3.7.4 PD_CUSTEFUSE Description .................................................................................
3.7.4.1
Power Domain Modes ....................................................................................
3.7.4.1.1 Logic and Memory Area Power Modes ............................................................
3.7.4.1.2 Logic and Memory Area Power Modes Control and Status .....................................
3.7.5 PD_IPU Description .............................................................................................
3.7.5.1
Power Domain Modes ....................................................................................
3.7.5.1.1 Logic and Memory Area Power Modes ............................................................
3.7.5.1.2 Logic and Memory Area Power Modes Control and Status .....................................
3.7.6 PD_DSS Description ............................................................................................
3.7.6.1
Power Domain Modes ....................................................................................
3.7.6.1.1 Logic and Memory Area Power Modes ............................................................
3.7.6.1.2 Logic and Memory Area Power Mode Control and Status ......................................
3.7.7 PD_CAM Description ............................................................................................
3.7.7.1
Power Domain Modes ....................................................................................
3.7.7.1.1 Logic and Memory Area Power Modes ............................................................
3.7.7.1.2 Logic and Memory Area Power Mode Control and Status ......................................
3.7.8 PD_MMAON Description .......................................................................................
3.7.8.1
Power Domain Modes ....................................................................................
3.7.9 PD_COREAON Description ....................................................................................
3.7.9.1
Power Domain Modes ....................................................................................
3.7.10 PD_ISS Description ............................................................................................
3.7.10.1 Power Domain Modes ....................................................................................
3.7.10.1.1 Logic and Memory Area Power Modes ............................................................
3.7.10.1.2 Logic and Memory Area Power Modes Control and Status .....................................
3.7.11 PD_EVE1 Description ..........................................................................................
3.7.11.1 Power Domain Modes ....................................................................................
3.7.11.1.1 Logic and Memory Area Power Modes ............................................................
3.7.11.1.2 Logic and Memory Area Power Modes Control and Status .....................................
Voltage-Management Functional Description .........................................................................
3.8.1 Overview ..........................................................................................................
3.8.2 Voltage-Control Architecture ...................................................................................
3.8.3 Internal LDOs Control ...........................................................................................
3.8.3.1
VDD_CORE_L and VDD_DSPEVE_L Control ........................................................
3.8.3.1.1 Adaptive Voltage Scaling ............................................................................
3.8.3.2
Memory LDOs..............................................................................................
3.8.3.3
BANDGAP Control ........................................................................................
3.8.3.4
Memory LDO Transitions .................................................................................
3.8.3.5
VDD_WKUP_L Transitions ...............................................................................
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3.9
3.10
3.11
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Device Low-Power States ...............................................................................................
3.9.1 Device Wake-Up Source Summary ...........................................................................
3.9.2 Wakeup Upon Global Warm Reset ............................................................................
3.9.3 Global Warm Reset During a Device Wake-Up Sequence ................................................
3.9.4 I/O Management .................................................................................................
3.9.4.1
Isolation / Wakeup Sequence ............................................................................
3.9.4.1.1 Software-Controlled I/O Isolation ...................................................................
PRCM Module Programming Guide ....................................................................................
3.10.1 DPLLs Low-Level Programming Models ....................................................................
3.10.1.1 Global Initialization ........................................................................................
3.10.1.1.1 Surrounding Module Global Initialization ..........................................................
3.10.1.1.2 DPLL Global Initialization ............................................................................
3.10.1.2 DPLL Output Frequency Change........................................................................
3.10.2 Clock Management Low-Level Programming Models .....................................................
3.10.2.1 Global Initialization ........................................................................................
3.10.2.1.1 Surrounding Module Global Initialization ..........................................................
3.10.2.1.2 Clock Management Global Initialization ...........................................................
3.10.2.2 Clock Domain Sleep Transition and Troubleshooting ................................................
3.10.2.3 Enable/Disable Software-Programmable Static Dependency .......................................
3.10.3 Power Management Low-Level Programming Models ....................................................
3.10.3.1 Global Initialization ........................................................................................
3.10.3.1.1 Surrounding Module Global Initialization ..........................................................
3.10.3.1.2 Power Management Global Initialization...........................................................
3.10.3.2 Forced Memory Area State Change With Power Domain ON.......................................
3.10.3.3 Forced Power Domain Low-Power State Transition ..................................................
PRCM Register Manual ..................................................................................................
3.11.1 Not Supported Functionality (Registers and Bitfields) .....................................................
3.11.2 PRCM Instance Summary .....................................................................................
3.11.3 CKGEN_CM_CORE_AON registers .........................................................................
3.11.3.1 CKGEN_CM_CORE_AON Register Summary .......................................................
3.11.3.2 CKGEN_CM_CORE_AON Register Description .....................................................
3.11.4 DSP1_CM_CORE_AON registers ............................................................................
3.11.4.1 DSP1_CM_CORE_AON Register Summary ..........................................................
3.11.4.2 DSP1_CM_CORE_AON Register Description ........................................................
3.11.5 DSP2_CM_CORE_AON registers ............................................................................
3.11.5.1 DSP2_CM_CORE_AON Register Summary ..........................................................
3.11.5.2 DSP2_CM_CORE_AON Register Description ........................................................
3.11.6 EVE1_CM_CORE_AON registers ............................................................................
3.11.6.1 EVE1_CM_CORE_AON Register Summary ..........................................................
3.11.6.2 EVE1_CM_CORE_AON Register Description ........................................................
3.11.7 EVE2_CM_CORE_AON registers ............................................................................
3.11.7.1 EVE2_CM_CORE_AON Register Summary ..........................................................
3.11.7.2 EVE2_CM_CORE_AON Register Description ........................................................
3.11.8 EVE3_CM_CORE_AON registers ............................................................................
3.11.8.1 EVE3_CM_CORE_AON Register Summary ..........................................................
3.11.8.2 EVE3_CM_CORE_AON Register Description ........................................................
3.11.9 EVE4_CM_CORE_AON registers ............................................................................
3.11.9.1 EVE4_CM_CORE_AON Register Summary ..........................................................
3.11.9.2 EVE4_CM_CORE_AON Register Description ........................................................
3.11.10 INSTR_CM_CORE_AON registers .........................................................................
3.11.10.1 INSTR_CM_CORE_AON Register Summary ......................................................
3.11.10.2 INSTR_CM_CORE_AON Register Description .....................................................
3.11.11 IPU_CM_CORE_AON registers .............................................................................
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3.11.11.1 IPU_CM_CORE_AON Register Summary ..........................................................
3.11.11.2 IPU_CM_CORE_AON Register Description ........................................................
3.11.12 MPU_CM_CORE_AON registers ...........................................................................
3.11.12.1 MPU_CM_CORE_AON Register Summary .........................................................
3.11.12.2 MPU_CM_CORE_AON Register Description .......................................................
3.11.13 OCP_SOCKET_CM_CORE_AON registers ...............................................................
3.11.13.1 OCP_SOCKET_CM_CORE_AON Register Summary ............................................
3.11.13.2 OCP_SOCKET_CM_CORE_AON Register Description ..........................................
3.11.14 RESTORE_CM_CORE_AON registers ....................................................................
3.11.14.1 RESTORE_CM_CORE_AON Register Summary ..................................................
3.11.14.2 RESTORE_CM_CORE_AON Register Description ................................................
3.11.15 RTC_CM_CORE_AON registers ............................................................................
3.11.15.1 RTC_CM_CORE_AON Register Summary .........................................................
3.11.15.2 RTC_CM_CORE_AON Register Description .......................................................
3.11.16 ISS_CM_CORE_AON registers .............................................................................
3.11.16.1 ISS_CM_CORE_AON Register Summary ..........................................................
3.11.16.2 ISS_CM_CORE_AON Register Description ........................................................
3.11.17 CAM_CM_CORE registers...................................................................................
3.11.17.1 CAM_CM_CORE Register Summary ................................................................
3.11.17.2 CAM_CM_CORE Register Description ..............................................................
3.11.18 CKGEN_CM_CORE registers ...............................................................................
3.11.18.1 CKGEN_CM_CORE Register Summary ............................................................
3.11.18.2 CKGEN_CM_CORE Register Description ..........................................................
3.11.19 COREAON_CM_CORE registers ...........................................................................
3.11.19.1 COREAON_CM_CORE Register Summary ........................................................
3.11.19.2 COREAON_CM_CORE Register Description ......................................................
3.11.20 CORE_CM_CORE registers .................................................................................
3.11.20.1 CORE_CM_CORE Register Summary ..............................................................
3.11.20.2 CORE_CM_CORE Register Description ............................................................
3.11.21 CUSTEFUSE_CM_CORE registers ........................................................................
3.11.21.1 CUSTEFUSE_CM_CORE Register Summary ......................................................
3.11.21.2 CUSTEFUSE_CM_CORE Register Description ....................................................
3.11.22 DSS_CM_CORE registers ...................................................................................
3.11.22.1 DSS_CM_CORE Register Summary ................................................................
3.11.22.2 DSS_CM_CORE Register Description ..............................................................
3.11.23 GPU_CM_CORE registers ...................................................................................
3.11.23.1 GPU_CM_CORE Register Summary ................................................................
3.11.23.2 GPU_CM_CORE Register Description ..............................................................
3.11.24 IVA_CM_CORE registers ....................................................................................
3.11.24.1 IVA_CM_CORE Register Summary ..................................................................
3.11.24.2 IVA_CM_CORE Register Description ................................................................
3.11.25 L3INIT_CM_CORE registers ................................................................................
3.11.25.1 L3INIT_CM_CORE Register Summary ..............................................................
3.11.25.2 L3INIT_CM_CORE Register Description ............................................................
3.11.26 L4PER_CM_CORE registers ................................................................................
3.11.26.1 L4PER_CM_CORE Register Summary .............................................................
3.11.26.2 L4PER_CM_CORE Register Description ...........................................................
3.11.27 OCP_SOCKET_CM_CORE registers ......................................................................
3.11.27.1 OCP_SOCKET_CM_CORE Register Summary ...................................................
3.11.27.2 OCP_SOCKET_CM_CORE Register Description ..................................................
3.11.28 RESTORE_CM_CORE registers............................................................................
3.11.28.1 RESTORE_CM_CORE Register Summary .........................................................
3.11.28.2 RESTORE_CM_CORE Register Description .......................................................
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Contents
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722
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724
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795
819
819
820
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896
896
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3.11.29 SMARTREFLEX_CORE registers .......................................................................... 901
3.11.29.1 SMARTREFLEX_CORE Register Summary ........................................................ 901
3.11.29.2 SMARTREFLEX_CORE Register Description ...................................................... 902
3.11.30 CAM_PRM registers .......................................................................................... 909
3.11.30.1 CAM_PRM Register Summary ....................................................................... 909
3.11.30.2 CAM_PRM Register Description ..................................................................... 909
3.11.31 CKGEN_PRM registers ...................................................................................... 919
3.11.31.1 CKGEN_PRM Register Summary .................................................................... 919
3.11.31.2 CKGEN_PRM Register Description .................................................................. 920
3.11.32 COREAON_PRM registers .................................................................................. 955
3.11.32.1 COREAON_PRM Register Summary ................................................................ 955
3.11.32.2 COREAON_PRM Register Description .............................................................. 956
3.11.33 CORE_PRM registers ........................................................................................ 967
3.11.33.1 CORE_PRM Register Summary ...................................................................... 967
3.11.33.2 CORE_PRM Register Description .................................................................... 969
3.11.34 CUSTEFUSE_PRM registers .............................................................................. 1014
3.11.34.1 CUSTEFUSE_PRM Register Summary ............................................................ 1014
3.11.34.2 CUSTEFUSE_PRM Register Description .......................................................... 1014
3.11.35 DEVICE_PRM registers..................................................................................... 1017
3.11.35.1 DEVICE_PRM Register Summary .................................................................. 1017
3.11.35.2 DEVICE_PRM Register Description ................................................................ 1019
3.11.36 DSP1_PRM registers ....................................................................................... 1071
3.11.36.1 DSP1_PRM Register Summary ..................................................................... 1071
3.11.36.2 DSP1_PRM Register Description ................................................................... 1071
3.11.37 DSP2_PRM registers ....................................................................................... 1076
3.11.37.1 DSP2_PRM Register Summary ..................................................................... 1076
3.11.37.2 DSP2_PRM Register Description ................................................................... 1076
3.11.38 DSS_PRM registers ......................................................................................... 1081
3.11.38.1 DSS_PRM Register Summary ...................................................................... 1081
3.11.38.2 DSS_PRM Register Description .................................................................... 1081
3.11.39 EMU_CM registers .......................................................................................... 1091
3.11.39.1 EMU_CM Register Summary ........................................................................ 1091
3.11.39.2 EMU_CM Register Description ...................................................................... 1092
3.11.40 EMU_PRM Registers........................................................................................ 1095
3.11.40.1 EMU_PRM Register Summary ...................................................................... 1095
3.11.40.2 EMU_PRM Register Description .................................................................... 1095
3.11.41 EVE1_PRM registers ........................................................................................ 1097
3.11.41.1 EVE1_PRM Register Summary ..................................................................... 1097
3.11.41.2 EVE1_PRM Register Description ................................................................... 1098
3.11.42 EVE2_PRM registers ........................................................................................ 1104
3.11.42.1 EVE2_PRM Register Summary ..................................................................... 1104
3.11.42.2 EVE2_PRM Register Description ................................................................... 1104
3.11.43 EVE3_PRM registers ........................................................................................ 1109
3.11.43.1 EVE3_PRM Register Summary ..................................................................... 1109
3.11.43.2 EVE3_PRM Register Description ................................................................... 1109
3.11.44 EVE4_PRM registers ........................................................................................ 1114
3.11.44.1 EVE4_PRM Register Summary ..................................................................... 1114
3.11.44.2 EVE4_PRM Register Description ................................................................... 1114
3.11.45 GPU_PRM registers ......................................................................................... 1119
3.11.45.1 GPU_PRM Register Summary ...................................................................... 1119
3.11.45.2 GPU_PRM Register Description .................................................................... 1119
3.11.46 INSTR_PRM registers ...................................................................................... 1121
3.11.46.1 INSTR_PRM Register Summary .................................................................... 1121
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3.11.46.2 INSTR_PRM Register Description ..................................................................
3.11.47 IPU_PRM registers ..........................................................................................
3.11.47.1 IPU_PRM Register Summary .......................................................................
3.11.47.2 IPU_PRM Register Description .....................................................................
3.11.48 IVA_PRM registers ..........................................................................................
3.11.48.1 IVA_PRM Register Summary ........................................................................
3.11.48.2 IVA_PRM Register Description ......................................................................
3.11.49 L3INIT_PRM registers ......................................................................................
3.11.49.1 L3INIT_PRM Register Summary ....................................................................
3.11.49.2 L3INIT_PRM Register Description ..................................................................
3.11.50 L4PER_PRM registers ......................................................................................
3.11.50.1 L4PER_PRM Register Summary ...................................................................
3.11.50.2 L4PER_PRM Register Description .................................................................
3.11.51 MPU_PRM registers.........................................................................................
3.11.51.1 MPU_PRM Register Summary ......................................................................
3.11.51.2 MPU_PRM Register Description ....................................................................
3.11.52 OCP_SOCKET_PRM registers ............................................................................
3.11.52.1 OCP_SOCKET_PRM Register Summary .........................................................
3.11.52.2 OCP_SOCKET_PRM Register Description ........................................................
3.11.53 RTC_PRM registers .........................................................................................
3.11.53.1 RTC_PRM Register Summary ......................................................................
3.11.53.2 RTC_PRM Register Description ....................................................................
3.11.54 ISS_PRM registers ..........................................................................................
3.11.54.1 ISS_PRM Register Summary ........................................................................
3.11.54.2 ISS_PRM Register Description ......................................................................
3.11.55 WKUPAON_CM registers ..................................................................................
3.11.55.1 WKUPAON_CM Register Summary ................................................................
3.11.55.2 WKUPAON_CM Register Description ..............................................................
3.11.56 WKUPAON_PRM registers .................................................................................
3.11.56.1 WKUPAON_PRM Register Summary ..............................................................
3.11.56.2 WKUPAON_PRM Register Description ............................................................
4
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1125
1125
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DSP Subsystems ............................................................................................................ 1376
4.1
4.2
4.3
DSP Subsystems Overview ............................................................................................
4.1.1 DSP Subsystems Key Features ..............................................................................
DSP Subsystem Integration............................................................................................
DSP Subsystems Functional Description ............................................................................
4.3.1 DSP Subsystems Block Diagram ............................................................................
4.3.2 DSP Subsystem Components ................................................................................
4.3.2.1
C66x DSP Subsystem Introduction ....................................................................
4.3.2.2
DSP TMS320C66x CorePac ...........................................................................
4.3.2.2.1 DSP TMS320C66x CorePac CPU ................................................................
4.3.2.2.2 DSP TMS320C66x CorePac Internal Memory Controllers and Memories ..................
4.3.2.2.3 DSP C66x CorePac Internal Peripherals .........................................................
4.3.2.3
DSP Debug and Trace Support ........................................................................
4.3.2.3.1 DSP Advanced Event Triggering (AET) ..........................................................
4.3.2.3.2 DSP Trace Support .................................................................................
4.3.3 DSP System Control Logic ....................................................................................
4.3.3.1
DSP System Clocks .....................................................................................
4.3.3.2
DSP Hardware Resets ..................................................................................
4.3.3.3
DSP Software Resets ...................................................................................
4.3.3.4
DSP Power Management ...............................................................................
4.3.3.4.1 DSP System Powerdown Protocols ...............................................................
4.3.3.4.2 DSP Software and Hardware Power Down Sequence Overview .............................
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Contents
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Dual Cortex-M4 IPU Subsystem ........................................................................................ 1469
5.1
5.2
5.3
12
4.3.3.4.3 DSP IDLE Wakeup ..................................................................................
4.3.3.4.4 DSP SYSTEM IRQWAKEEN registers ...........................................................
4.3.3.4.5 DSP Automatic Power Transition..................................................................
4.3.4 DSP Interrupt Requests .......................................................................................
4.3.4.1
DSP Input Interrupts .....................................................................................
4.3.4.1.1 DSP Non-maskable Interrupt Input................................................................
4.3.4.2
DSP Event and Interrupt Generation Outputs ........................................................
4.3.4.2.1 DSP MDMA and DSP EDMA Mflag Event Outputs ............................................
4.3.4.2.2 DSP Aggregated Error Interrupt Output ..........................................................
4.3.4.2.3 Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs ...........................
4.3.5 DSP DMA Requests ...........................................................................................
4.3.5.1
DSP EDMA Wakeup Interrupt .........................................................................
4.3.6 DSP Intergated Memory Management Units ...............................................................
4.3.6.1
DSP MMUs Overview ...................................................................................
4.3.6.2
Routing MDMA Traffic through DSP MMU0 .........................................................
4.3.6.3
Routing EDMA Traffic thorugh DSP MMU1 .........................................................
4.3.7 DSP Integrated EDMA Subsystem ..........................................................................
4.3.7.1
DSP EDMA Overview ...................................................................................
4.3.7.2
DSP System and Device Level Settings of DSP EDMA ...........................................
4.3.8 DSP L2 interconnect Network ................................................................................
4.3.8.1
DSP Public Firewall Settings ...........................................................................
4.3.8.2
DSP NoC Flag Mux and Error Log Registers ........................................................
4.3.8.3
DSP NoC Arbitration .....................................................................................
4.3.9 DSP Boot Configuration .......................................................................................
4.3.10 DSP Internal and External Memory Views .................................................................
4.3.10.1 C66x CPU View of the Address Space ...............................................................
4.3.10.2 DSP_EDMA View of the Address Space .............................................................
4.3.10.3 L3_MAIN View of the DSP Address Space ..........................................................
DSP Subsystem Register Manual.....................................................................................
4.4.1 DSP Subsystem Instance Summary .........................................................................
4.4.2 DSP_ICFG Registers ..........................................................................................
4.4.2.1
DSP_ICFG Register Summary ........................................................................
4.4.2.2
DSP_ICFG Register Description ......................................................................
4.4.3 DSP_SYSTEM Registers .....................................................................................
4.4.3.1
DSP_SYSTEM Register Summary ...................................................................
4.4.3.2
DSP_SYSTEM Register Description .................................................................
4.4.4 DSP_FW_L2_NOC_CFG Registers .........................................................................
4.4.4.1
DSP_FW_L2_NOC_CFG Register Summary .......................................................
4.4.4.2
DSP_FW_L2_NOC_CFG Register Description .....................................................
Dual Cortex-M4 IPU Subsystem Overview ..........................................................................
5.1.1 Introduction ......................................................................................................
5.1.2 Key Features ....................................................................................................
Dual Cortex-M4 IPU Subsystem Integration .........................................................................
5.2.1 IPU Subsystem Clock Distribution ...........................................................................
5.2.2 IPU Subsystem Reset Distribution ...........................................................................
Dual Cortex-M4 IPU Subsystem Functional Description ...........................................................
5.3.1 IPU Block Diagram .............................................................................................
5.3.2 Cortex-M4 Core.................................................................................................
5.3.2.1
Cortex-M4 Microprocessor ..............................................................................
5.3.2.2
Nested Vectored Interrupt Controller (NVIC) .........................................................
5.3.2.3
Cortex-M4 Configuration in this Device ...............................................................
5.3.3 IPU Memory System ...........................................................................................
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5.4
6
5.3.3.1
Cache Interface ..........................................................................................
5.3.3.2
L1 Unified Cache (IPU_UNICACHE) ..................................................................
5.3.3.2.1 IPU_UNICACHE Configuration in the Device....................................................
5.3.3.2.2 IPU_UNICACHE Maintenance .....................................................................
5.3.3.3
L1 MMU (IPU_UNICACHE_MMU) .....................................................................
5.3.3.3.1 IPU_UNICACHE_MMU Configuration in the Device............................................
5.3.3.3.2 Page Attributes ......................................................................................
5.3.3.3.3 Policy Support........................................................................................
5.3.3.4
Subsystem Counter Timer Module (SCTM) ..........................................................
5.3.3.4.1 Counter Functions ...................................................................................
5.3.3.4.2 Timer Functions......................................................................................
5.3.3.5
L2 MMU (IPU_MMU) ....................................................................................
5.3.3.5.1 IPU_MMU Behavior on Page-Fault ...............................................................
5.3.3.6
L2 MPORT ................................................................................................
5.3.3.7
ECC Implementation.....................................................................................
5.3.4 IPU Power Management ......................................................................................
5.3.4.1
Wake-Up Generator (IPU_WUGEN) ..................................................................
5.3.4.2
Cortex-M4 Local Power Management .................................................................
5.3.4.3
STANDBY and IDLE Protocols.........................................................................
5.3.4.4
Power Domains ..........................................................................................
5.3.4.5
Voltage Domain ..........................................................................................
5.3.4.6
Power States and Modes ...............................................................................
5.3.5 IPU Interprocessor Communication (IPC)...................................................................
5.3.5.1
Use of WFE and SEV ...................................................................................
5.3.5.2
Use of Interrupt for IPC..................................................................................
5.3.5.3
Use of the Bit-Band Feature for Semaphore Operations ...........................................
5.3.5.4
Cortex-M4 Private Memory Space .....................................................................
5.3.6 IPU Memory Mapping..........................................................................................
5.3.7 IPU Boot Configuration ........................................................................................
5.3.8 IPU Debug and Emulation Features .........................................................................
Dual Cortex-M4 IPU Subsystem Register Manual ..................................................................
5.4.1 IPU Subsystem Instance Summary ..........................................................................
5.4.2 IPU_UNICACHE_CFG Registers ............................................................................
5.4.2.1
IPU_UNICACHE_CFG Register Summary ...........................................................
5.4.2.2
IPU_UNICACHE_CFG Register Description .........................................................
5.4.3 IPU_UNICACHE_SCTM Registers ..........................................................................
5.4.3.1
IPU_UNICACHE_SCTM Register Summary .........................................................
5.4.3.2
IPU_UNICACHE_SCTM Register Description .......................................................
5.4.4 IPU_UNICACHE_MMU (AMMU) Registers .................................................................
5.4.4.1
IPU_UNICACHE_MMU (AMMU) Register Summary ...............................................
5.4.4.2
IPU_UNICACHE_MMU (AMMU) Register Description .............................................
5.4.5 IPU_MMU Registers ...........................................................................................
5.4.6 IPU_Cx_INTC Registers ......................................................................................
5.4.7 IPU_WUGEN Registers .......................................................................................
5.4.7.1
IPU_WUGEN Register Summary ......................................................................
5.4.7.2
IPU_WUGEN Register Description ....................................................................
5.4.8 IPU_Cx_RW_TABLE Registers ..............................................................................
5.4.8.1
IPU_Cx_RW_TABLE Register Summary .............................................................
5.4.8.2
IPU_Cx_RW_TABLE Register Description ...........................................................
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1480
1480
1480
1481
1481
1481
1482
1482
1483
1484
1485
1485
1486
1486
1488
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1489
1489
1489
1489
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1512
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1523
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1527
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1527
Embedded Vision Engine ................................................................................................. 1529
6.1
6.2
Embedded Vision Engine (EVE) Subsystem ........................................................................ 1530
6.1.1 EVE Overview .................................................................................................. 1530
ARP32 CPU and Instruction Set ...................................................................................... 1532
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6.2.1 Overview.........................................................................................................
6.2.2 Features .........................................................................................................
6.2.3 Block Diagram ..................................................................................................
6.2.4 Architecture .....................................................................................................
6.2.4.1
Interface Description .....................................................................................
6.2.4.1.1 Data Memory Interface .............................................................................
6.2.4.1.2 Instruction Memory Interface .......................................................................
6.2.4.2
Pipeline ....................................................................................................
6.2.4.2.1 Overview ..............................................................................................
6.2.4.2.2 Pipeline Operation ...................................................................................
6.2.4.2.3 Pipeline Interlocks ...................................................................................
6.2.4.3
Data Format ..............................................................................................
6.2.4.4
Endian Support ...........................................................................................
6.2.4.5
Architectural Register File ..............................................................................
6.2.4.6
CPU Control Registers ..................................................................................
6.2.4.6.1 Control Status Register (CSR) .....................................................................
6.2.4.6.2 Interrupt Enable Register (IER) ....................................................................
6.2.4.6.3 Interrupt Flag Register (IFR) .......................................................................
6.2.4.6.4 Interrupt Set Register (ISR) ........................................................................
6.2.4.6.5 Interrupt Clear Register (ICR)......................................................................
6.2.4.6.6 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) .................................
6.2.4.6.7 Interrupt Return Pointer Register (IRP) ...........................................................
6.2.4.6.8 Stack Pointer Register (SP) ........................................................................
6.2.4.6.9 Global Data Pointer Register (GDP) ..............................................................
6.2.4.6.10 Link Register (LR) ...................................................................................
6.2.4.6.11 Loop 0 Start Address Register (LSA0) ...........................................................
6.2.4.6.12 Loop 0 End Address Register (LEA0) ............................................................
6.2.4.6.13 Loop 0 Iteration Count Register (LCNT0) ........................................................
6.2.4.6.14 Loop 1 Start Address Register (LSA1) ...........................................................
6.2.4.6.15 Loop 1 End Address Register (LEA1) ............................................................
6.2.4.6.16 Loop 1 Iteration Count Register (LCNT1) ........................................................
6.2.4.6.17 Loop 0 Iteration Count Reload Value Register (LCNT0RLD) .................................
6.2.4.6.18 Shadow Control Status Register (SCSR) ........................................................
6.2.4.6.19 NMI Shadow Control Status Register (NMISCSR) .............................................
6.2.4.6.20 CPU Identification Register (CPUID) .............................................................
6.2.4.6.21 Decode Program Counter Register (DPC) .......................................................
6.2.4.6.22 Time Stamp Counter Registers (TSCL and TSCH) .............................................
6.2.4.7
CPU Shadow Registers .................................................................................
6.2.4.8
Functional Units ..........................................................................................
6.2.4.9
Instruction Fetch .........................................................................................
6.2.4.10 Alignment of 32-bit Instructions ........................................................................
6.2.4.11 Instruction Execution in Branch Delay Slot ...........................................................
6.2.4.12 Address Space ..........................................................................................
6.2.4.13 Program Counter Convention ..........................................................................
6.2.4.14 Stack Pointer Convention ...............................................................................
6.2.4.15 Global Data Pointer Convention .......................................................................
6.2.4.16 Conditional Execution ...................................................................................
6.2.4.17 Hardware Loop Acceleration ...........................................................................
6.2.4.17.1 Overview..............................................................................................
6.2.4.17.2 Loop Registers .......................................................................................
6.2.4.17.3 Loop Setup Instructions ............................................................................
6.2.4.17.4 Loop Operation ......................................................................................
6.2.4.17.5 Call and Branch within Loop Context .............................................................
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6.3
6.2.4.17.6 Dynamic Changes to Loop Iteration Count ......................................................
6.2.4.17.7 Interrupt Processing During HLA ..................................................................
6.2.4.17.8 HLA Usage in Interrupt Context ...................................................................
6.2.4.17.9 HLA Usage Restrictions ............................................................................
6.2.4.17.10 HLA Mapping Examples ..........................................................................
6.2.4.18 Interrupts ..................................................................................................
6.2.4.18.1 Overview..............................................................................................
6.2.4.18.2 Interrupt Processing .................................................................................
6.2.4.18.3 Interrupt Acknowledgment .........................................................................
6.2.4.18.4 Interrupt Priorities ...................................................................................
6.2.4.18.5 Interrupt Service Table (IST).......................................................................
6.2.4.18.6 Interrupt Flags .......................................................................................
6.2.4.18.7 Interrupt Behavior ...................................................................................
6.2.4.18.8 Interrupt Context Save and Restore ..............................................................
6.2.4.18.9 Nested Interrupts ....................................................................................
6.2.4.18.10 Non-nested Interrupt Latency ....................................................................
6.2.5 Instruction Set ..................................................................................................
6.2.5.1
Instruction Operation and Execution Notations ......................................................
6.2.5.2
Instruction Syntax and Opcode Notations ............................................................
6.2.5.3
Instruction Scheduling Restrictions ....................................................................
6.2.5.3.1 Restrictions Applicable to a Branch Delay Slot ..................................................
6.2.5.3.2 Restrictions on Loops Using Hardware Loop Assist (HLA) ....................................
6.2.5.3.3 Restrictions on Other Types of Control Flow Instructions ......................................
6.2.5.3.4 Restrictions for Write Data Bypass to Control Register Reads ................................
6.2.5.3.5 Restrictions for Write Data Bypass to Shadow Register Reads ...............................
6.2.5.3.6 Restrictions for Link Register Update .............................................................
6.2.5.4
Instruction Set Encoding ................................................................................
6.2.5.5
Instruction Descriptions .................................................................................
6.2.6 Clock, Reset, and Dynamic Power Management ..........................................................
6.2.6.1
Introduction ...............................................................................................
6.2.6.2
CPU Reset Modes .......................................................................................
6.2.6.3
Dynamic Power Management ..........................................................................
6.2.7 Notes on Programming Model ................................................................................
6.2.7.1
Booting ....................................................................................................
6.2.7.2
Enabling and Disabling Interrupts......................................................................
6.2.7.2.1 Globally Enabling or Disabling Maskable Interrupts ............................................
6.2.7.2.2 Enabling or Disabling Individual Interrupts .......................................................
6.2.7.3
Stack Usage in Interrupt Service Routine ............................................................
6.2.7.4
General Restrictions .....................................................................................
VCOP CPU and Instruction Set .......................................................................................
6.3.1 Module Overview ...............................................................................................
6.3.2 Features .........................................................................................................
6.3.3 Block Diagram ..................................................................................................
6.3.4 System Interfaces ..............................................................................................
6.3.4.1
Interrupts .................................................................................................
6.3.4.2
Configuration Bus Slave Port ..........................................................................
6.3.4.3
Performance Counter Interface ........................................................................
6.3.4.4
Data Memory Map ......................................................................................
6.3.5 Functional Description .........................................................................................
6.3.5.1
Scalar-Vector Architecture ..............................................................................
6.3.5.1.1 Scalar Core ..........................................................................................
6.3.5.1.2 Scalar-Vector Interaction ...........................................................................
6.3.5.2
Vector Core Overview ..................................................................................
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6.3.5.2.1 Nested for Loop Model .............................................................................
6.3.5.2.2 Instruction Organization ............................................................................
6.3.5.3
Vector Control ............................................................................................
6.3.5.3.1 Repeat End Count ...................................................................................
6.3.5.3.2 Parameter Pointer ...................................................................................
6.3.5.3.3 Switch Buffers ........................................................................................
6.3.5.4
Vector-Scalar Synchronization .........................................................................
6.3.5.4.1 Wait for Vector Core Done .........................................................................
6.3.5.4.2 Wait for Vector Core Ready ........................................................................
6.3.5.5
Vector Computation .....................................................................................
6.3.5.5.1 Vector Loop ..........................................................................................
6.3.5.5.2 Vector Register Initialization .......................................................................
6.3.5.5.3 Address Generator (agen) .........................................................................
6.3.5.5.4 Vector Load ..........................................................................................
6.3.5.5.5 Vector Arithmetic/Logic Operations ..............................................................
6.3.5.5.6 Vector Store ..........................................................................................
6.3.5.5.7 Table Lookup Operation ...........................................................................
6.3.5.5.8 Histogram Operation ...............................................................................
6.3.5.5.9 Circular Buffer Addressing Support ...............................................................
6.3.5.5.10 Load/Store Address Alignment Constraints ......................................................
6.3.5.6
Load/Store Buffer and Scheduling .....................................................................
6.3.5.7
VCOP Per-Loop Overhead .............................................................................
6.3.5.8
VCOP Error Handling....................................................................................
6.3.5.9
Vector Operation Details ................................................................................
6.3.5.9.1 VABS ..................................................................................................
6.3.5.9.2 VABSDIF .............................................................................................
6.3.5.9.3 VADD .................................................................................................
6.3.5.9.4 VADDH................................................................................................
6.3.5.9.5 VADDSUB ............................................................................................
6.3.5.9.6 VADD3 ................................................................................................
6.3.5.9.7 VADIF3................................................................................................
6.3.5.9.8 VAND .................................................................................................
6.3.5.9.9 VANDN................................................................................................
6.3.5.9.10 VAND3 ...............................................................................................
6.3.5.9.11 VBINLOG ............................................................................................
6.3.5.9.12 VBITC .................................................................................................
6.3.5.9.13 VBITDI ...............................................................................................
6.3.5.9.14 VBITI .................................................................................................
6.3.5.9.15 VBITPK ..............................................................................................
6.3.5.9.16 VBITR .................................................................................................
6.3.5.9.17 VBITTR ...............................................................................................
6.3.5.9.18 VBITUNPK ..........................................................................................
6.3.5.9.19 VCMOV ..............................................................................................
6.3.5.9.20 VCMPEQ ............................................................................................
6.3.5.9.21 VCMPGE .............................................................................................
6.3.5.9.22 VCMPGT .............................................................................................
6.3.5.9.23 VDINTRLV ...........................................................................................
6.3.5.9.24 VDINTRLV2 ..........................................................................................
6.3.5.9.25 VEXITNZ .............................................................................................
6.3.5.9.26 VINTRLV .............................................................................................
6.3.5.9.27 VINTRLV2 ...........................................................................................
6.3.5.9.28 VINTRLV4 ............................................................................................
6.3.5.9.29 VLMBD ...............................................................................................
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6.3.5.9.30 VMADD ..............................................................................................
6.3.5.9.31 VMAX ................................................................................................
6.3.5.9.32 VMAXSETF .........................................................................................
6.3.5.9.33 VMIN .................................................................................................
6.3.5.9.34 VMINSETF ..........................................................................................
6.3.5.9.35 VMPY .................................................................................................
6.3.5.9.36 VMSUB ..............................................................................................
6.3.5.9.37 VNOP ................................................................................................
6.3.5.9.38 VNOT ................................................................................................
6.3.5.9.39 VOR ..................................................................................................
6.3.5.9.40 VOR3 .................................................................................................
6.3.5.9.41 VRND ................................................................................................
6.3.5.9.42 VSAD .................................................................................................
6.3.5.9.43 VSEL .................................................................................................
6.3.5.9.44 VSHF ..................................................................................................
6.3.5.9.45 VSHFOR .............................................................................................
6.3.5.9.46 VSHF16 ..............................................................................................
6.3.5.9.47 VSIGN ................................................................................................
6.3.5.9.48 VSORT2 ..............................................................................................
6.3.5.9.49 VSUB .................................................................................................
6.3.5.9.50 VSWAP ..............................................................................................
6.3.5.9.51 VXOR ................................................................................................
6.3.6 Debug Support..................................................................................................
6.3.7 VCOP Register Manual ........................................................................................
6.3.7.1
VCOP Instance Summary ..............................................................................
6.3.7.2
VCOP Registers ..........................................................................................
6.3.7.2.1 VCOP Registers Mapping Summary .............................................................
6.3.7.2.2 VCOP Register Description .......................................................................
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7.1
ISS Overview ............................................................................................................
7.1.1 ISS Integration ..................................................................................................
7.1.1.1
ISS PRCM Interface Integration........................................................................
7.1.1.1.1 ISS Clock Domains ..................................................................................
7.1.2 ISS Functional Description ....................................................................................
7.1.2.1
ISS Interrupts .............................................................................................
7.1.2.1.1 ISS Interrupt Merger ................................................................................
7.1.2.1.2 ISS Submodule Interrupts ..........................................................................
7.1.2.2
ISS Interconnect .........................................................................................
7.1.2.3
ISS Video Mux............................................................................................
7.1.2.4
ISS Clocks ................................................................................................
7.1.2.5
ISS Reset .................................................................................................
7.1.2.6
ISS Power Management ................................................................................
7.1.2.6.1 ISS Power-Management Infrastructure Overview ...............................................
7.1.2.6.2 ISS STANDBY Mechanism ........................................................................
7.1.2.6.3 ISS IDLE Mechanism ...............................................................................
7.1.2.6.4 ISS Debug Support ..................................................................................
7.1.3 ISS Register Manual ...........................................................................................
7.1.3.1
ISS Instance Summary ..................................................................................
7.1.3.2
ISS Registers .............................................................................................
7.1.3.2.1 ISS TOP Register Summary .......................................................................
7.1.3.2.2 ISS TOP Register Description ....................................................................
7.1.3.3
ISS CTSET registers ....................................................................................
7.1.3.3.1 ISS CTSET Register Summary ...................................................................
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7.2
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7.1.3.3.2 ISS CTSET Register Description .................................................................
ISS Interfaces ............................................................................................................
7.2.1 ISS Interfaces Overview .......................................................................................
7.2.1.1
ISS Interfaces Features .................................................................................
7.2.2 ISS Interfaces Environment ...................................................................................
7.2.2.1
ISS Interfaces Signal Descriptions.....................................................................
7.2.2.2
ISS Interfaces Modes....................................................................................
7.2.3 ISS Camera Parallel Interface ...............................................................................
7.2.3.1
CPI Generic Configuration Protocol and Data Format (8, 10, 12, 16 Bits) .......................
7.2.3.2
ISS Interfaces CPI ITU-R BT.656/1120 422 Protocol and Data Formats (8, 10 Bits) ..........
7.2.4 ISS CSI2 PHY ..................................................................................................
7.2.4.1
ISS CSI2 PHY Overview ................................................................................
7.2.4.2
ISS CSI2 PHY Functional Description ................................................................
7.2.4.2.1 ISS CSI2 PHY Configuration .......................................................................
7.2.4.2.2 ISS CSI2 PHY HiSPi Mode Configuration........................................................
7.2.4.2.3 ISS CSI2 PHY MIPI D-PHY Link Initialization Sequence ......................................
7.2.4.2.4 ISS CSI2 PHY HiSPi Link Initialization Sequence ..............................................
7.2.4.2.5 ISS CSI2 PHY Error Signals .......................................................................
7.2.4.3
ISS CSI2 PHY Register Manual .......................................................................
7.2.4.3.1 ISS CSI2 PHY Instance Summary ................................................................
7.2.4.3.2 ISS CSI2 PHY Registers ...........................................................................
7.2.5 ISS LVDS Receiver ............................................................................................
7.2.5.1
ISS LVDS-RX Environment .............................................................................
7.2.5.2
ISS LVDS-RX Integration ...............................................................................
7.2.5.2.1 LVDS-RX Main Integration Attributes .............................................................
7.2.5.2.2 LVDS-RX Integration - PPI Interface..............................................................
7.2.5.3
ISS LVDS-RX Functional Description .................................................................
7.2.5.3.1 LVDS-RX Word Conversion Module ..............................................................
7.2.5.3.2 LVDS-RX Sync Detect Module ....................................................................
7.2.5.3.3 LVDS-RX Data Parser Module ....................................................................
7.2.5.3.4 LVDS-RX Async FIFO Module.....................................................................
7.2.5.3.5 LVDS-RX Sync FIFO Module ......................................................................
7.2.5.3.6 LVDS-RX Parallel Output Interface Module ......................................................
7.2.5.3.7 LVDS-RX Wide dynamic range ....................................................................
7.2.5.3.8 LVDS-RX Test Features ............................................................................
7.2.5.4
ISS LVDS-RX Register Manual ........................................................................
7.2.5.4.1 ISS LVDS-RX Instance Summary .................................................................
7.2.5.4.2 ISS LVDS-RX Registers ............................................................................
7.2.6 ISS Camera Adapter Layer ...................................................................................
7.2.6.1
ISS CAL Environment ...................................................................................
7.2.6.1.1 CAL_A Interface Signal Descriptions .............................................................
7.2.6.2
ISS CAL Integration......................................................................................
7.2.6.2.1 CAL Main Integration Attributes ...................................................................
7.2.6.2.2 CAL Integration - Video Port .......................................................................
7.2.6.2.3 CAL Integration - PPI Interface ....................................................................
7.2.6.3
ISS CAL Functional Description........................................................................
7.2.6.3.1 CAL Block Diagram .................................................................................
7.2.6.3.2 CAL Hardware and Software Reset ...............................................................
7.2.6.3.3 CAL Clock Configuration ...........................................................................
7.2.6.3.4 CAL Power Management ...........................................................................
7.2.6.3.5 CAL Interrupt Events ................................................................................
7.2.6.3.6 CAL CSI2 Low Level Protocol .....................................................................
7.2.6.3.7 CAL Data Stream Merger ..........................................................................
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7.3
7.2.6.3.8 CAL Pixel Extraction ................................................................................
7.2.6.3.9 CAL DPCM Decoding and Encoding .............................................................
7.2.6.3.10 CAL Stream Interleaving ...........................................................................
7.2.6.3.11 CAL Pixel Packing ..................................................................................
7.2.6.3.12 CAL Write DMA ......................................................................................
7.2.6.3.13 CAL Read DMA .....................................................................................
7.2.6.3.14 CAL Video Port ......................................................................................
7.2.6.3.15 CAL Registers Shadowing .........................................................................
7.2.6.4
ISS CAL Register Manual...............................................................................
7.2.6.4.1 CAL Instance Summary ............................................................................
7.2.6.4.2 CAL Registers........................................................................................
7.2.7 ISS Timing Control Module ...................................................................................
7.2.7.1
ISS TCTRL Environment ................................................................................
7.2.7.2
ISS TCTRL Integration ..................................................................................
7.2.7.3
ISS TCTRL Functional Description ....................................................................
7.2.7.3.1 ISS TCTRL Features ................................................................................
7.2.7.3.2 ISS TCTRL Control-Signal Generator ............................................................
7.2.7.4
ISS TCTRL Programming Model ......................................................................
7.2.7.4.1 ISS TCTRL Camera-Control Signal Generator ..................................................
7.2.7.5
ISS TCTRL Register Manual ...........................................................................
7.2.7.5.1 ISS TCTRL Instance Summary ....................................................................
7.2.7.5.2 ISS TCTRL Registers ...............................................................................
ISS Image Signal Processor ...........................................................................................
7.3.1 ISS ISP Overview ..............................................................................................
7.3.1.1
ISS ISP Features.........................................................................................
7.3.1.2
ISS ISP Block Diagram..................................................................................
7.3.2 ISS ISP Integration .............................................................................................
7.3.2.1
ISS ISP PRCM Interface ................................................................................
7.3.2.1.1 ISS ISP Clocks.......................................................................................
7.3.2.1.2 ISS ISP Reset ........................................................................................
7.3.2.2
ISS ISP Interrupt Tree ...................................................................................
7.3.2.3
ISS ISP IPIPEIF Integration ............................................................................
7.3.2.3.1 ISS ISP IPIPEIF Interrupts .........................................................................
7.3.2.4
ISS ISP IPIPE Integration ...............................................................................
7.3.2.4.1 ISS ISP IPIPE Interrupts............................................................................
7.3.2.4.2 ISS ISP DMA Requests ............................................................................
7.3.2.5
ISS ISP RSZ Integration ................................................................................
7.3.2.5.1 ISS ISP RSZ PRCM Interface .....................................................................
7.3.2.5.2 ISS ISP RSZ Interrupts .............................................................................
7.3.2.6
ISS ISP H3A Integration ................................................................................
7.3.2.6.1 ISS ISP H3A Interrupts .............................................................................
7.3.2.7
ISS ISP ISIF Integration .................................................................................
7.3.2.7.1 ISS ISP ISIF Interrupts..............................................................................
7.3.2.8
ISS ISP BL Integration ..................................................................................
7.3.3 ISS ISP Functional Description ...............................................................................
7.3.3.1
ISS ISP VP Functional Description ....................................................................
7.3.3.1.1 ISS ISP VP Overview ...............................................................................
7.3.3.1.2 ISS ISP VP Data Formats ..........................................................................
7.3.3.1.3 ISS ISP VP Top-Level Communication With CAL_A/LVDS-RX/CPI .........................
7.3.3.1.4 ISS ISP VP Pixel Clock Inversion .................................................................
7.3.3.2
ISS ISP GLBCE Functional Description ..............................................................
7.3.3.2.1 ISS ISP GLBCE Overview .........................................................................
7.3.3.2.2 ISS ISP GLBCE Interface ..........................................................................
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7.3.3.2.3 ISS ISP GLBCE Core ...............................................................................
7.3.3.2.4 ISS ISP GLBCE Embedded Memory .............................................................
7.3.3.2.5 ISS ISP GLBCE Programming Model ............................................................
7.3.3.3
ISS ISP NSF3V Functional Description ...............................................................
7.3.3.3.1 ISS ISP NSF3V Overview ..........................................................................
7.3.3.3.2 ISS ISP NSF3V Register Shadlwing ..............................................................
7.3.3.3.3 ISS ISP NSF3V Programming Model ............................................................
7.3.3.4
ISS ISP IPIPEIF Functional Description ..............................................................
7.3.3.4.1 ISS ISP IPIPEIF Overview .........................................................................
7.3.3.4.2 ISS ISP IPIPEIF Top-Level Block Diagram ......................................................
7.3.3.4.3 ISS ISP IPIPEIF Input Interface ...................................................................
7.3.3.4.4 ISS ISP IPIPEIF Data Path Selection .............................................................
7.3.3.4.5 ISS ISP IPIPEIF Timing Generation ..............................................................
7.3.3.4.6 ISS ISP IPIPEIF Decompression (DPCM) Subblock: Unpack and Decompression
Function ...............................................................................................
7.3.3.4.7 ISS ISP IPIPEIF Dark-Frame Subtraction Functionality ........................................
7.3.3.4.8 ISS ISP IPIPEIF Wide Dynamic Range WDR Merging Functionality .........................
7.3.3.4.9 ISS ISP IPIPEIF (1, 2, 1) Averaging Filter for IPIPE Data Path ...............................
7.3.3.4.10 ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for IPIPE Data Path .............
7.3.3.4.11 ISS ISP IPIPEIF RAW Data Gain for IPIPE Data Path.........................................
7.3.3.4.12 ISS ISP IPIPEIF (1, 2 ,1) Averaging Filter for H3A Data Path ................................
7.3.3.4.13 ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for H3A Data Path ..............
7.3.3.4.14 ISS ISP IPIPEIF YUV4:2:2 8-bit Packed Data Input Coming From ISIF Module ...........
7.3.3.4.15 ISS ISP IPIPEIF YUV4:2:0 Data Input for Memory-to-Memory Resize Operations ........
7.3.3.4.16 ISS ISP IPIPEIF Module Events and Status Checking .........................................
7.3.3.5
ISS ISP IPIPE Functional Description .................................................................
7.3.3.5.1 ISS ISP IPIPE Overview ............................................................................
7.3.3.5.2 ISS ISP IPIPE Top-Level Block Diagram.........................................................
7.3.3.5.3 ISS ISP IPIPE Input Interface ......................................................................
7.3.3.5.4 ISS ISP IPIPE Defect Pixel Correction ...........................................................
7.3.3.5.5 ISS ISP IPIPE DPC Interface ......................................................................
7.3.3.5.6 ISS ISP IPIPE White Balance......................................................................
7.3.3.5.7 ISS ISP IPIPE YUV422to444 .....................................................................
7.3.3.5.8 ISS ISP IPIPE RGB2RGB Blending Module .....................................................
7.3.3.5.9 ISS ISP IPIPE Gamma Correction Module ......................................................
7.3.3.5.10 ISS ISP IPIPE Second RGB2RGB Conversion Matrix .........................................
7.3.3.5.11 ISS ISP IPIPE RGB2YCbCr Conversion Matrix .................................................
7.3.3.5.12 ISS ISP IPIPE 4:2:2 Conversion Module .........................................................
7.3.3.5.13 ISS ISP IPIPE 2D Edge-Enhancer ................................................................
7.3.3.5.14 ISS ISP IPIPE Histogram ..........................................................................
7.3.3.5.15 ISS ISP IPIPE Boxcar ..............................................................................
7.3.3.6
ISS ISP RSZ Functional Description ..................................................................
7.3.3.6.1 ISS ISP RSZ Overview .............................................................................
7.3.3.6.2 ISS ISP RSZ Top-Level Block Diagram ..........................................................
7.3.3.6.3 ISS ISP RSZ Interfaces .............................................................................
7.3.3.6.4 ISS ISP RSZ ICM Handshake Signals ...........................................................
7.3.3.6.5 ISS ISP RSZ Integration ............................................................................
7.3.3.6.6 ISS ISP RSZ Functional Description ..............................................................
7.3.3.7
ISS ISP CNF Functional Description ..................................................................
7.3.3.7.1 ISS ISP CNF Overview .............................................................................
7.3.3.7.2 ISS ISP CNF Top Level Block Diagram ..........................................................
7.3.3.7.3 ISS ISP CNF Noise Filter Algorithm ..............................................................
7.3.3.7.4 ISS ISP CNF Chroma Downsampling and Upsampling ........................................
7.3.3.7.5 ISS ISP CNF Vertical and Horizontal Blanking ..................................................
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2171
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SPRUIC6B – January 2017 – Revised October 2017
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7.3.3.7.6 ISS ISP CNF configuring ranges/restrictions ...................................................
7.3.3.8
ISS ISP H3A Functional Description ..................................................................
7.3.3.8.1 ISS ISP H3A Overview .............................................................................
7.3.3.8.2 ISS ISP H3A Top-Level Block Diagram ..........................................................
7.3.3.8.3 ISS ISP H3A Line Framing Logic..................................................................
7.3.3.8.4 ISS ISP H3A Optional Preprocessing.............................................................
7.3.3.8.5 ISS ISP H3A Autofocus Engine ...................................................................
7.3.3.8.6 ISS ISP H3A AE/AWB Engine .....................................................................
7.3.3.8.7 ISS ISP H3A DMA Interface .......................................................................
7.3.3.8.8 ISS ISP H3A Events and Status Checking.......................................................
7.3.3.9
ISS ISP ISIF Functional Description ...................................................................
7.3.3.9.1 ISS ISP ISIF Overview ..............................................................................
7.3.3.9.2 ISS ISP ISIF Top-Level Block Diagram...........................................................
7.3.3.9.3 ISS ISP ISIF Input Interface ........................................................................
7.3.3.9.4 ISS ISP ISIF Interface ..............................................................................
7.3.3.9.5 ISS ISP ISIF Sensor Linearization ................................................................
7.3.3.9.6 ISS ISP ISIF Input Data Formatter ................................................................
7.3.3.9.7 ISS ISP ISIF Color Space Converter .............................................................
7.3.3.9.8 ISS ISP ISIF Black Clamp ..........................................................................
7.3.3.9.9 ISS ISP ISIF Vertical Line Defect Correction (VDFC) ..........................................
7.3.3.9.10 ISS ISP ISIF Lens Shading Correction Module (2D-LSC) .....................................
7.3.3.9.11 ISS ISP ISIF White Balance .......................................................................
7.3.3.9.12 ISS ISP ISIF Low-Pass Filter ......................................................................
7.3.3.9.13 ISS ISP ISIF A-Law Compression ................................................................
7.3.3.9.14 ISS ISP ISIF Culling ................................................................................
7.3.3.9.15 ISS ISP ISIF 12-to-8-Bit DPCM Compression Block ...........................................
7.3.3.9.16 ISP ISIF Storage Formatter ........................................................................
7.3.3.9.17 ISS ISP ISIF Circular Buffer .......................................................................
7.3.3.9.18 ISS ISP ISIF YCbCr Signal Processing ..........................................................
7.3.3.9.19 ISS ISP ISIF Expected Bandwidth on BL Ports .................................................
7.3.3.9.20 ISS ISP ISIF Events and Status Checking .......................................................
7.3.3.10 ISS ISP BL Functional Description ....................................................................
7.3.3.10.1 ISS ISP BL Overview ...............................................................................
7.3.3.10.2 ISS ISP BL Functional Description ................................................................
7.3.3.10.3 ISS ISP BL Address Alignment ....................................................................
7.3.3.10.4 ISS ISP BL Out-of-Order Responses .............................................................
7.3.3.10.5 ISS ISP BL Stalling..................................................................................
7.3.3.10.6 ISS ISP BL Dynamic and Static MFlag Generation.............................................
7.3.3.10.7 ISS ISP BL VBUSM2OCP Last Beat Command Delay ........................................
7.3.3.10.8 ISS ISP BL Peak Memory Bandwidth Reduction ...............................................
7.3.3.11 ISS ISP Memory Mapping ..............................................................................
7.3.4 ISS ISP Register Manual ......................................................................................
7.3.4.1
ISS ISP Instance Summary .............................................................................
7.3.4.2
ISS ISP6P5_SYS1 registers ............................................................................
7.3.4.2.1 ISS ISP6P5_SYS1 Register Summary ..........................................................
7.3.4.2.2 ISS ISP6P5_SYS1 Register Description ........................................................
7.3.4.3
ISS ISP6P5_SYS2 Registers...........................................................................
7.3.4.3.1 ISS ISP6P5_SYS2 Register Summary ..........................................................
7.3.4.3.2 ISS ISP6P5_SYS2 Register Description ........................................................
7.3.4.4
ISS ISP6P5_RESIZER Registers ......................................................................
7.3.4.4.1 ISS ISP6P5_RESIZER Register Summary .....................................................
7.3.4.4.2 ISS ISP6P5_RESIZER Register Description ....................................................
7.3.4.5
ISS ISP6P5_IPIPE Registers...........................................................................
SPRUIC6B – January 2017 – Revised October 2017
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2253
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2272
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7.4
22
7.3.4.5.1 ISS ISP6P5_IPIPE Register Summary ..........................................................
7.3.4.5.2 ISS ISP6P5_IPIPE Register Description ........................................................
7.3.4.6
ISS ISP6P5_ISIF Registers.............................................................................
7.3.4.6.1 ISS ISP6P5_ISIF Register Summary ............................................................
7.3.4.6.2 ISS ISP6P5_ISIF Register Description ..........................................................
7.3.4.7
ISS ISP6P5_IPIPEIF Registers ........................................................................
7.3.4.7.1 ISS ISP6P5_IPIPEIF Register Summary ........................................................
7.3.4.7.2 ISS ISP6P5_IPIPEIF Register Description ......................................................
7.3.4.8
ISS ISP6P5_H3A Registers ............................................................................
7.3.4.8.1 ISS ISP6P5_H3A Register Summary ............................................................
7.3.4.8.2 ISS ISP6P5_H3A Register Description ..........................................................
7.3.4.9
ISS ISP6P5_SYS3 Registers...........................................................................
7.3.4.9.1 ISS ISP6P5_SYS3 Register Summary ..........................................................
7.3.4.9.2 ISS ISP6P5_SYS3 Register Description ........................................................
7.3.4.10 ISS ISP6P5 CNF1 and NSF3V Registers ............................................................
7.3.4.10.1 ISS ISP6P5 CNF1 and NSF3V Register Summary ............................................
7.3.4.10.2 ISS ISP6P5 CNF1 and NSF3V Register Description .........................................
7.3.4.11 ISS ISP6P5_GLBCE Registers ........................................................................
7.3.4.11.1 ISS ISP6P5_GLBCE Register Summary .......................................................
7.3.4.11.2 ISS ISP6P5_GLBCE Register Description .....................................................
ISS Still Image Coprocessor ...........................................................................................
7.4.1 ISS SIMCOP Overview ........................................................................................
7.4.1.1
ISS SIMCOP Integration ................................................................................
7.4.1.2
ISS SIMCOP Functional Description ..................................................................
7.4.1.2.1 ISS SIMCOP Local Power and Clock Management ............................................
7.4.1.2.2 ISS SIMCOP Reset .................................................................................
7.4.1.2.3 ISS SIMCOP Interrupt Merger .....................................................................
7.4.1.2.4 ISS SIMCOP Modules Description ................................................................
7.4.1.3
ISS SIMCOP Programming Models ...................................................................
7.4.1.3.1 Global Initialization ..................................................................................
7.4.1.3.2 ISS SIMCOP Operational Modes Configuration .................................................
7.4.1.4
ISS SIMCOP Registers Manual ........................................................................
7.4.1.4.1 SIMCOP Instance Summary .......................................................................
7.4.1.4.2 SIMCOP Registers ..................................................................................
7.4.2 ISS SIMCOP Hardware Sequencer and Buffers Module .................................................
7.4.2.1
ISS SIMCOP Hardware Sequencer and Buffers Overview .........................................
7.4.2.2
ISS SIMCOP Hardware Sequencer and Buffer Integration ........................................
7.4.2.3
ISS SIMCOP Hardware Sequencer and Buffers Functional Description .........................
7.4.2.3.1 ISS SIMCOP Hardware Sequencer and Buffers Software Reset .............................
7.4.2.3.2 ISS SIMCOP Hardware Sequencer and Buffers Power Management .......................
7.4.2.3.3 ISS SIMCOP Hardware Sequencer and Buffer Interrupt Requests ..........................
7.4.2.3.4 ISS SIMCOP Hardware Sequencer ...............................................................
7.4.2.4
ISS SIMCOP Hardware Sequencer and Buffers Basic Programming Model ....................
7.4.2.4.1 ISS SIMCOP Hardware Sequencer and Buffers Application Programming Principle ......
7.4.2.4.2 External CPU Use for Data Processing ..........................................................
7.4.2.5
ISS SIMCOP Hardware Sequencer and Buffer Registers Manual ................................
7.4.2.5.1 Hardware Sequencer Instance Summary ........................................................
7.4.2.5.2 Hardware Sequencer Registers ...................................................................
7.4.3 ISS SIMCOP DMA Module....................................................................................
7.4.3.1
ISS SIMCOP DMA Overview ...........................................................................
7.4.3.2
ISS SIMCOP DMA Integration .........................................................................
7.4.3.3
ISS SIMCOP DMA Functional Description ...........................................................
7.4.3.3.1 ISS SIMCOP DMA Block Diagram ................................................................
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SPRUIC6B – January 2017 – Revised October 2017
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7.4.3.3.2 ISS SIMCOP DMA Power Management .........................................................
7.4.3.3.3 ISS SIMCOP DMA Interrupt Requests ...........................................................
7.4.3.3.4 ISS SIMCOP DMA Logical Channels .............................................................
7.4.3.3.5 Transaction Generation .............................................................................
7.4.3.4
ISS SIMCOP DMA Basic Programming Model ......................................................
7.4.3.4.1 Initialization of Surrounding Modules .............................................................
7.4.3.4.2 ISS SIMCOP DMA Channel Configuration and Hardware Synchronization .................
7.4.3.4.3 Software Synchronization ..........................................................................
7.4.3.5
ISS SIMCOP DMA Register Manual ..................................................................
7.4.3.5.1 ISS SIMCOP DMA Instance Summary ...........................................................
7.4.3.5.2 ISS SIMCOP DMA Registers ......................................................................
7.4.4 ISS SIMCOP VTNF Module ..................................................................................
7.4.4.1
ISS SIMCOP VTNF Overview ..........................................................................
7.4.4.2
ISS SIMCOP VTNF Environment ......................................................................
7.4.4.2.1 ISS SIMCOP VTNF Protocols and Data Formats ...............................................
7.4.4.3
ISS SIMCOP VTNF Integration ........................................................................
7.4.4.4
ISS SIMCOP VTNF Functional Description ..........................................................
7.4.4.4.1 ISS SIMCOP VTNF Block Diagram ...............................................................
7.4.4.4.2 ISS SIMCOP VTNF Clocks Management ........................................................
7.4.4.4.3 ISS SIMCOP VTNF Interrupt Requests ..........................................................
7.4.4.4.4 ISS SIMCOP VTNF Configuration ................................................................
7.4.4.5
ISS SIMCOP VTNF Register Manual .................................................................
7.4.4.5.1 ISS SIMCOP VTNF Instance Summary ..........................................................
7.4.4.5.2 ISS SIMCOP VTNF registers ......................................................................
7.4.5 ISS SIMCOP LDC Module ....................................................................................
7.4.5.1
ISS SIMCOP LDC Overview ...........................................................................
7.4.5.2
ISS SIMCOP LDC Integration ..........................................................................
7.4.5.3
ISS SIMCOP LDC Functional Description ............................................................
7.4.5.3.1 ISS SIMCOP LDC Block Diagram.................................................................
7.4.5.3.2 ISS SIMCOP LDC Interrupt Requests ............................................................
7.4.5.3.3 ISS SIMCOP LDC Input/Output Format Data ...................................................
7.4.5.3.4 ISS SIMCOP Lens Distortion Back-Mapping ....................................................
7.4.5.3.5 ISS SIMCOP LCD Bayer Chromatic Aberration Correction Implementation ................
7.4.5.3.6 ISS SIMCOP LDC Affine Transform ..............................................................
7.4.5.3.7 ISS SIMCOP LDC Perspective Transformation .................................................
7.4.5.3.8 ISS SIMCOP LDC Pixel Interpolation .............................................................
7.4.5.3.9 ISS SIMCOP LDC Buffer Management ..........................................................
7.4.5.3.10 ISS SIMCOP LDC Input Circular Buffer ..........................................................
7.4.5.3.11 ISS SIMCOP LDC and Hardware Sequencer ...................................................
7.4.5.4
ISS SIMCOP LDC Basic Programming Model .......................................................
7.4.5.4.1 ISS SIMCOP LDC Initialization of Surrounding Modules.......................................
7.4.5.4.2 ISS SIMCOP LDC Geometric Distortion Mode ..................................................
7.4.5.4.3 ISS SIMCOP LDC Bayer Chromatic Aberration Mode .........................................
7.4.5.4.4 ISS SIMCOP LDC Programming Affine Transformation .......................................
7.4.5.4.5 ISS SIMCOP LDC Programming Perspective Transformation ................................
7.4.5.5
ISS SIMCOP LDC Register Manual ...................................................................
7.4.5.5.1 ISS SIMCOP LDC Instance Summary ............................................................
7.4.5.5.2 ISS SIMCOP LDC Registers .......................................................................
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3000
3000
3001
3001
3004
3004
3004
3016
3016
3017
3019
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Video Input Port .............................................................................................................. 3053
8.1
8.2
8.3
8.4
VIP Overview ............................................................................................................
VIP Environment ........................................................................................................
VIP Integration ...........................................................................................................
VIP Functional Description ............................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
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8.4.1 VIP Block Diagram .............................................................................................
8.4.2 VIP Software Reset ............................................................................................
8.4.3 VIP Power and Clocks Management .......................................................................
8.4.3.1
VIP Clocks ................................................................................................
8.4.3.2
VIP Idle Mode ............................................................................................
8.4.3.3
VIP StandBy Mode.......................................................................................
8.4.4 VIP Slice .........................................................................................................
8.4.4.1
VIP Slice Processing Path Overview ..................................................................
8.4.4.2
VIP Slice Processing Path Multiplexers ...............................................................
8.4.4.2.1 VIP_CSC Multiplexers .............................................................................
8.4.4.2.2 VIP_SC Multiplexer..................................................................................
8.4.4.2.3 Output to VPDMA Multiplexers ....................................................................
8.4.4.3
VIP Slice Processing Path Examples .................................................................
8.4.4.3.1 Input: B:YUV422; Output: B:RGB .................................................................
8.4.4.3.2 Input: A:YUV422 8/16, B:YUV422; Output: A:Scaled YUV420, B: RGB .....................
8.4.4.3.3 Input: B:YUV422; Output: B:Scaled YUV420 ....................................................
8.4.4.3.4 Input: A: YUV422 8/16; Output A:Scaled YUV420, B:Scaled YUV444 .......................
8.4.4.3.5 Input: A:YUV422 8/16, B:YUV422; Output: A: Scaled YUV420, B:YUV420 .................
8.4.4.3.6 Input : A: YUV422 8/16, B: YUV422; Output: A: YUV420, B: YUV420 .......................
8.4.5 VIP Parser .......................................................................................................
8.4.5.1
Features ...................................................................................................
8.4.5.2
Repacker ..................................................................................................
8.4.5.3
Analog Video .............................................................................................
8.4.5.4
Digitized Video ...........................................................................................
8.4.5.5
Frame Buffers ............................................................................................
8.4.5.6
Input Data Interface ......................................................................................
8.4.5.6.1 8b Interface Mode ...................................................................................
8.4.5.6.2 16b Interface Mode ..................................................................................
8.4.5.6.3 Signal Relationships ................................................................................
8.4.5.6.4 General 5 Pin Interfaces ............................................................................
8.4.5.6.5 Signal Subsets—4 Pin VSYNC, ACTVID, and FID .............................................
8.4.5.6.6 Signal Subsets—4 Pin VSYNC, HSYNC, and FID ..............................................
8.4.5.6.7 Vertical Sync .........................................................................................
8.4.5.6.8 Field ID Determination Using Dedicated Signal .................................................
8.4.5.6.9 Field ID Determination Using VSYNC Skew .....................................................
8.4.5.6.10 Rationale for FID Determination By VSYNC Skew .............................................
8.4.5.6.11 ACTVID Framing ....................................................................................
8.4.5.6.12 Ancillary Data Storage in Descrete Sync Mode .................................................
8.4.5.7
BT.656 Style Embedded Sync .........................................................................
8.4.5.7.1 Data Input ............................................................................................
8.4.5.7.2 Sync Words ..........................................................................................
8.4.5.7.3 Error Correction ......................................................................................
8.4.5.7.4 Embedded Sync Ancillary Data ....................................................................
8.4.5.8
Source Multiplexing ......................................................................................
8.4.5.8.1 Multiplexing Scenarios ..............................................................................
8.4.5.8.2 2-Way Multiplexing ..................................................................................
8.4.5.8.3 4-Way Multiplexing ..................................................................................
8.4.5.8.4 Line Multiplexing .....................................................................................
8.4.5.8.5 Super Frame Concept in Line Multiplexing ......................................................
8.4.5.8.6 8-bit Data Interface in Line Multiplexing ..........................................................
8.4.5.8.7 16-bit Data Interface in Line Multiplexing.........................................................
8.4.5.8.8 Split Lines in Line Multiplex Mode .................................................................
8.4.5.8.9 Meta Data ............................................................................................
24
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SPRUIC6B – January 2017 – Revised October 2017
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8.4.5.8.10 TI Line Mux Mode, Split Lines, and Channel ID Remapping ..................................
8.4.5.9
Channel ID Extraction for 2x/4x Multiplexed Source ................................................
8.4.5.9.1 Channel ID Extraction Overview...................................................................
8.4.5.9.2 Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing ....................
8.4.5.9.3 Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing .
8.4.5.10 Embedded Sync Mux Modes and Data Bus Widths ................................................
8.4.5.11 Ancillary and Active Video Cropping ..................................................................
8.4.5.12 Interrupts ..................................................................................................
8.4.5.13 VDET Interrupt ...........................................................................................
8.4.5.14 Source Video Size .......................................................................................
8.4.5.15 Clipping ....................................................................................................
8.4.5.16 Current and Last FID Value ............................................................................
8.4.5.17 Disable Handling .........................................................................................
8.4.5.18 Picture Size Interrupt ....................................................................................
8.4.5.19 Discrete Sync Signals ...................................................................................
8.4.5.19.1 VBLNK and HBLNK .................................................................................
8.4.5.19.2 BLNK and ACTVID (1) ..............................................................................
8.4.5.19.3 VBLNK and ACTVID(2) .............................................................................
8.4.5.19.4 VBLNK and HSYNC ................................................................................
8.4.5.19.5 VSYNC and HBLNK ................................................................................
8.4.5.19.6 VSYNC and ACTIVID(1) ...........................................................................
8.4.5.19.7 VSYNC and ACTIVID(2) ...........................................................................
8.4.5.19.8 VSYNC and HSYNC ................................................................................
8.4.5.19.9 Line and Pixel Capture Examples .................................................................
8.4.5.20 VIP Overflow Detection and Recovery ................................................................
8.4.6 VIP Color Space Converter (CSC) ...........................................................................
8.4.6.1
CSC Features ............................................................................................
8.4.6.2
CSC Functional Description ............................................................................
8.4.6.2.1 HDTV Application ....................................................................................
8.4.6.2.2 SDTV Application ....................................................................................
8.4.6.3
CSC Bypass Mode.......................................................................................
8.4.7 VIP Scaler (SC) .................................................................................................
8.4.7.1
SC Features ..............................................................................................
8.4.7.2
SC Functional Description ..............................................................................
8.4.7.2.1 Trimmer ...............................................................................................
8.4.7.2.2 Peaking ...............................................................................................
8.4.7.2.3 Vertical Scaler........................................................................................
8.4.7.2.4 Horizontal Scaler ....................................................................................
8.4.7.2.5 Basic Configurations ................................................................................
8.4.7.2.6 Coefficient Memory ..................................................................................
8.4.7.3
SC Code ..................................................................................................
8.4.7.3.1 Generate Coefficient Memory Image .............................................................
8.4.7.3.2 Scaler Configuration Calculation ..................................................................
8.4.7.3.3 Typical Configuration Values.......................................................................
8.4.7.4
SC Coefficient Data Files ...............................................................................
8.4.7.4.1 HS Polyphase Filter Coefficients ..................................................................
8.4.7.4.2 VS Polyphase Filter Coefficients ..................................................................
8.4.7.4.3 VS (Bilinear Filter Coefficients) ....................................................................
8.4.8 VIP Video Port Direct Memory Access (VPDMA) ..........................................................
8.4.8.1
VPDMA Introduction .....................................................................................
8.4.8.2
VPDMA Basic Definitions ...............................................................................
8.4.8.2.1 Client ..................................................................................................
8.4.8.2.2 Channel ...............................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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3200
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3292
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3297
Display Subsystem.......................................................................................................... 3466
9.1
9.2
26
8.4.8.2.3 List .....................................................................................................
8.4.8.2.4 Data Formats Supported ...........................................................................
8.4.8.3
VPDMA Client Buffering and Functionality ...........................................................
8.4.8.4
VPDMA Channels Assignment .........................................................................
8.4.8.5
VPDMA MFLAG Mechanism ...........................................................................
8.4.8.6
VPDMA Interrupts .......................................................................................
8.4.8.7
VPDMA Descriptors .....................................................................................
8.4.8.7.1 Data Transfer Descriptors ..........................................................................
8.4.8.7.2 Configuration Descriptor ............................................................................
8.4.8.7.3 Control Descriptor ...................................................................................
8.4.8.8
VPDMA Configuration ...................................................................................
8.4.8.8.1 Regular List...........................................................................................
8.4.8.8.2 Video Input Ports ....................................................................................
8.4.8.9
VPDMA Data Formats ...................................................................................
8.4.8.9.1 YUV Data Formats ..................................................................................
8.4.8.9.2 RGB Data Formats ..................................................................................
8.4.8.9.3 Miscellaneous Data Type...........................................................................
VIP Register Manual ....................................................................................................
8.5.1 VIP Instance Summary ........................................................................................
8.5.2 VIP Top Level Registers.......................................................................................
8.5.2.1
VIP Top Level Register Summary ....................................................................
8.5.2.2
VIP Top Level Register Description ..................................................................
8.5.3 VIP Parser Registers ..........................................................................................
8.5.3.1
VIP Parser Register Summary ........................................................................
8.5.3.2
VIP Parser Register Description .......................................................................
8.5.4 VIP CSC Registers .............................................................................................
8.5.4.1
VIP CSC Register Summary ...........................................................................
8.5.4.2
VIP CSC Register Description .........................................................................
8.5.5 VIP SC registers ................................................................................................
8.5.5.1
VIP SC Register Summary .............................................................................
8.5.5.2
VIP SC Register Description ...........................................................................
8.5.6 VIP VPDMA Registers .........................................................................................
8.5.6.1
VIP VPDMA Register Summary .......................................................................
8.5.6.2
VIP VPDMA Register Description .....................................................................
Display Subsystem Overview ..........................................................................................
9.1.1 Display Subsystem Environment .............................................................................
9.1.1.1
Display Subsystem Parallel Interface .................................................................
9.1.1.2
Display Subsystem TV Output .........................................................................
9.1.2 Display Subsystem Integration ...............................................................................
9.1.2.1
Display Subsystem Interrupt and DMA Requests ...................................................
9.1.2.2
Display Subsystem Clocks..............................................................................
9.1.2.3
Display Subsystem Reset ...............................................................................
9.1.2.4
Display Subsystem Power Management .............................................................
9.1.2.4.1 Display Subsystem Standby Mode ................................................................
9.1.2.4.2 Display Subsystem Wake-Up Mode ..............................................................
9.1.3 Display Subsystem Register Manual ........................................................................
9.1.3.1
Display Subsystem Instance Summary ...............................................................
9.1.3.2
Display Subsystem Registers ..........................................................................
9.1.3.2.1 Display Subsystem Registers Mapping Summary ..............................................
9.1.3.2.2 Display Subsystem Register Description .........................................................
Display Controller .......................................................................................................
9.2.1 DISPC Overview ...............................................................................................
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SPRUIC6B – January 2017 – Revised October 2017
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9.2.2 DISPC Environment............................................................................................
9.2.2.1
DISPC VP1 Output and Data Formats ...............................................................
9.2.2.2
DISPC VP1 Active Marix Display Timing Diagrams .................................................
9.2.3 DISPC Integration ..............................................................................................
9.2.4 DISPC Functional Description ................................................................................
9.2.4.1
DISPC Clock Configuration .............................................................................
9.2.4.2
DISPC Software Reset ..................................................................................
9.2.4.3
DISPC Power Management ............................................................................
9.2.4.3.1 DISPC Idle Mode ....................................................................................
9.2.4.3.2 DISPC StandBy Mode ..............................................................................
9.2.4.3.3 DISPC Wakeup ......................................................................................
9.2.4.4
DISPC Interrupt Requests ..............................................................................
9.2.4.5
DISPC DMA Requests ..................................................................................
9.2.4.6
DISPC DMA Engine .....................................................................................
9.2.4.6.1 DISPC DMA Addressing and Bursts ..............................................................
9.2.4.6.2 DISPC DMA Buffers.................................................................................
9.2.4.6.3 DISPC DMA MFLAG Mechanism and Arbitration ...............................................
9.2.4.6.4 DISPC DMA Predecimation ........................................................................
9.2.4.6.5 DISPC DMA Arbitration ............................................................................
9.2.4.6.6 DISPC DMA Power Modes.........................................................................
9.2.4.7
DISPC Memory Formats ................................................................................
9.2.4.8
DISPC Graphics Pipeline ...............................................................................
9.2.4.8.1 DISPC GFX Replication Logic .....................................................................
9.2.4.8.2 DISPC GFX Anti-Aliasing Filter ....................................................................
9.2.4.8.3 DISPC GFX Color Look-Up Table (CLUT) .......................................................
9.2.4.9
DISPC Video Pipelines ..................................................................................
9.2.4.9.1 DISPC VID Replication Logic ......................................................................
9.2.4.9.2 DISPC VID VC-1 Range Mapping Unit ...........................................................
9.2.4.9.3 DISPC VID Color Look-Up Table (CLUT) ........................................................
9.2.4.9.4 DISPC VID CSC Unit YUV to RGB ...............................................................
9.2.4.9.5 DISPC VID Scaler Unit .............................................................................
9.2.4.9.6 DISPC VID Progressive to Interlace conversion ................................................
9.2.4.10 DISPC Write-Back Pipeline .............................................................................
9.2.4.10.1 DISPC WB CSC Unit RGB to YUV ...............................................................
9.2.4.10.2 DISPC WB Scaler Unit .............................................................................
9.2.4.10.3 DISPC WB RGB Truncation Logic ................................................................
9.2.4.11 DISPC Region-Based Mechanism .....................................................................
9.2.4.11.1 Region-Based Mechanism Overview .............................................................
9.2.4.11.2 Region-Based Mechanism for a Single Region Write-Back ...................................
9.2.4.12 DISPC Overlay Managers ..............................................................................
9.2.4.12.1 DISPC Overlay Priority Rule .......................................................................
9.2.4.12.2 DISPC Overlay Alpha Blender .....................................................................
9.2.4.12.3 DISPC Overlay Transparency Color Keys .......................................................
9.2.4.13 DISPC Video Port Output ...............................................................................
9.2.4.13.1 DISPC VP1 Gamma Correction Unit .............................................................
9.2.4.13.2 DISPC VP1 Color Phase Rotation Unit ..........................................................
9.2.4.13.3 DISPC VP1 Color Space Conversion ............................................................
9.2.4.13.4 DISPC VP1 BT.656 and BT.1120 Modes .......................................................
9.2.4.13.5 DISPC VP1 Spatial/Temporal Dithering ..........................................................
9.2.4.13.6 DISPC VP1 Multiple Cycle Output Format (TDM) ..............................................
9.2.4.13.7 DISPC VP1 Timing Generator and Panel Settings .............................................
9.2.4.13.8 DISPC VP1 Configuration for TV Support .......................................................
9.2.4.14 DISPC Extended 3D Support ..........................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
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9.3
28
9.2.4.14.1 DISPC Extended 3D Support - Line Alternative Format .......................................
9.2.4.14.2 DISPC Extended 3D Support - Frame Packing Format ........................................
9.2.4.15 DISPC Shadow Registers ..............................................................................
9.2.5 DISPC Register Manual .......................................................................................
9.2.5.1
DISPC Instance Summary ..............................................................................
9.2.5.2
DISPC_COMMON Registers ...........................................................................
9.2.5.2.1 DISPC_COMMON Register Summary ...........................................................
9.2.5.2.2 DISPC_COMMON Register Description .........................................................
9.2.5.3
DISPC_GFX1 Registers ................................................................................
9.2.5.3.1 DISPC_GFX1 Register Summary ................................................................
9.2.5.3.2 DISPC_GFX1 Register Description ..............................................................
9.2.5.4
DISPC_WB Registers ...................................................................................
9.2.5.4.1 DISPC_WB Register Summary ...................................................................
9.2.5.4.2 DISPC_WB Register Description .................................................................
9.2.5.5
DISPC_VID Registers ...................................................................................
9.2.5.5.1 DISPC_VID Register Summary ...................................................................
9.2.5.5.2 DISPC_VID Register Description .................................................................
9.2.5.6
DISPC_OVR Registers ..................................................................................
9.2.5.6.1 DISPC_OVR Register Summary .................................................................
9.2.5.6.2 DISPC_OVR Register Description ...............................................................
9.2.5.7
DISPC_VP1 Registers ..................................................................................
9.2.5.7.1 DISPC_VP1 Register Summary ..................................................................
9.2.5.7.2 DISPC_VP1 Register Description ................................................................
Video Encoder ...........................................................................................................
9.3.1 Video Encoder Overview ......................................................................................
9.3.2 Video Encoder Environment ..................................................................................
9.3.3 Video Encoder Integration ....................................................................................
9.3.4 Video Encoder Functional Description ......................................................................
9.3.4.1
Video Encoder Data Manager ..........................................................................
9.3.4.1.1 Video Encoder Color Space Converter ...........................................................
9.3.4.1.2 Video Encoder Test Pattern Generation..........................................................
9.3.4.2
Video Encoder Luma Stage ............................................................................
9.3.4.3
Video Encoder Chroma Stage .........................................................................
9.3.4.4
Video Encoder Subcarrier and Burst Generation ....................................................
9.3.4.5
Video Encoder Vertical Blanking Interval .............................................................
9.3.4.5.1 Video Encoder Closed Caption Encoding ........................................................
9.3.4.5.2 Video Encoder Wide-Screen Signaling (WSS) Encoding ......................................
9.3.4.6
Video Encoder SD_DAC ................................................................................
9.3.4.6.1 Video SD_DAC DC/AC Coupled TV Load .......................................................
9.3.4.6.2 Video SD_DAC TV Detection/Disconnection Pulse Generation and Use....................
9.3.4.6.3 Video SD_DAC TV Short Detection ...............................................................
9.3.4.6.4 Video SD_DAC Normal Mode .....................................................................
9.3.4.6.5 Video SD_DAC Bypass Mode .....................................................................
9.3.4.6.6 Video SD_DAC Test Mode .........................................................................
9.3.4.6.7 Video SD_DAC Power Management .............................................................
9.3.5 Video Encoder Programming Guide .........................................................................
9.3.5.1
Video Encoder Low-level Programming Models .....................................................
9.3.5.1.1 Surrounding Modules Global Initialization ........................................................
9.3.5.1.2 Video Encoder Global Initialization ................................................................
9.3.6 Video Encoder Use Case and Tips ..........................................................................
9.3.6.1
Video Encoder Register Settings ......................................................................
9.3.7 Video Encoder Register Manual..............................................................................
9.3.7.1
Video Encoder Instance Summary ....................................................................
Contents
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SPRUIC6B – January 2017 – Revised October 2017
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9.3.7.2
Video Encoder Registers................................................................................ 3670
9.3.7.2.1 Video Encoder Register Summary ................................................................ 3670
9.3.7.2.2 Video Encoder Register Description .............................................................. 3671
10
Interconnect ................................................................................................................... 3698
10.1
10.2
10.3
Interconnect Overview ..................................................................................................
10.1.1 Terminology ....................................................................................................
10.1.2 Architecture Overview ........................................................................................
L3_MAIN Interconnect ..................................................................................................
10.2.1 L3_MAIN Interconnect Overview ............................................................................
10.2.2 L3_MAIN Interconnect Integration ..........................................................................
10.2.3 L3_MAIN Interconnect Functional Description ............................................................
10.2.3.1 Module Use in L3_MAIN Interconnect ................................................................
10.2.3.2 Module Distribution ......................................................................................
10.2.3.2.1 L3_MAIN Interconnect Agents .....................................................................
10.2.3.2.2 L3_MAIN Connectivity Matrix ......................................................................
10.2.3.2.3 Master NIU Identification ...........................................................................
10.2.3.3 Bandwidth Regulators ...................................................................................
10.2.3.4 Bandwidth Limiters .......................................................................................
10.2.3.5 Flag Muxing ...............................................................................................
10.2.3.5.1 Time-out Flag Muxing ...............................................................................
10.2.3.6 Statistic Collectors Group ...............................................................................
10.2.3.7 L3_MAIN Protection and Firewalls.....................................................................
10.2.3.7.1 L3_MAIN Firewall Reset ............................................................................
10.2.3.7.2 Power Management .................................................................................
10.2.3.7.3 L3_MAIN Firewall Functionality ...................................................................
10.2.3.8 L3_MAIN Interconnect Error Handling ................................................................
10.2.3.8.1 Global Error-Routing Scheme .....................................................................
10.2.3.8.2 Slave NIU Error Logging ...........................................................................
10.2.3.8.3 Severity Level of Standard and Custom Errors .................................................
10.2.3.8.4 Example for Decoding Standard/Custom Errors Logged in L3_MAIN .......................
10.2.4 L3_MAIN Interconnect Programming Guide ...............................................................
10.2.4.1 L3 _MAIN Interconnect Low-Level Programming Models ..........................................
10.2.4.1.1 Global Initialization ..................................................................................
10.2.4.2 Operational Modes Configuration ......................................................................
10.2.4.2.1 L3_MAIN Interconnect Error Analysis Mode .....................................................
10.2.5 L3_MAIN Interconnect Register Manual ...................................................................
10.2.5.1 L3_MAIN Register Group Summary ...................................................................
10.2.5.1.1 L3_MAIN Firewall Registers Summary and Description .......................................
10.2.5.1.2 L3_MAIN Host Register Summary and Description ............................................
10.2.5.1.3 L3_MAIN TARG Register Summary and Description ..........................................
10.2.5.1.4 L3_MAIN Flag Muxing Registers Summary and Description ..................................
10.2.5.1.5 L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description ..................
10.2.5.1.6 L3_MAIN Time-out Flag Muxing Registers Summary and Description ......................
10.2.5.1.7 L3_MAIN Bandwidth Regulator Register Summary and Description .........................
10.2.5.1.8 L3_MAIN Bandwidth Limiter Register Summary and Description ............................
10.2.5.1.9 L3_MAIN STATCOLL Register Summary and Description ....................................
L4 Interconnects .........................................................................................................
10.3.1 L4 Interconnect Overview ....................................................................................
10.3.2 L4 Interconnect Integration ..................................................................................
10.3.3 L4 Interconnect Functional Description ....................................................................
10.3.3.1 Module Distribution ......................................................................................
10.3.3.1.1 L4_PER1 Interconnect Agents ....................................................................
10.3.3.1.2 L4_PER2 Interconnect Agents ....................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
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10.3.3.1.3 L4_PER3 Interconnect Agents ....................................................................
10.3.3.1.4 L4_CFG Interconnect Agents ......................................................................
10.3.3.1.5 L4_WKUP Interconnect Agents ...................................................................
10.3.3.2 Power Management .....................................................................................
10.3.3.3 L4 Firewalls ...............................................................................................
10.3.3.3.1 Protection Group ....................................................................................
10.3.3.3.2 Segments and Regions .............................................................................
10.3.3.3.3 L4 Firewall Address and Protection Register Settings .........................................
10.3.3.4 L4 Error Detection and Reporting ......................................................................
10.3.3.4.1 IA and TA Error Detection and Logging ..........................................................
10.3.3.4.2 Time-Out..............................................................................................
10.3.3.4.3 Error Reporting ......................................................................................
10.3.3.4.4 Error Recovery .......................................................................................
10.3.3.4.5 Firewall Error Logging in the Control Module ....................................................
10.3.4 L4 Interconnect Programming Guide .......................................................................
10.3.4.1 L4 Interconnect Low-level Programming Models ....................................................
10.3.4.1.1 Global Initialization ..................................................................................
10.3.4.1.2 Operational Modes Configuration .................................................................
10.3.5 L4 Interconnects Register Manual ..........................................................................
10.3.5.1 L4 Interconnects Instance Summary ..................................................................
10.3.5.2 L4 Initiator Agent (L4 IA) ................................................................................
10.3.5.2.1 L4 Initiator Agent (L4 IA) Register Summary ....................................................
10.3.5.2.2 L4 Initiator Agent (L4 IA) Register Description ..................................................
10.3.5.3 L4 Target Agent (L4 TA) ................................................................................
10.3.5.3.1 L4 Target Agent (L4 TA) Register Summary ....................................................
10.3.5.3.2 L4 Target Agent (L4 TA) Register Description ..................................................
10.3.5.4 L4 Link Agent (L4 LA) ...................................................................................
10.3.5.4.1 L4 Link Agent (L4 LA) Register Summary .......................................................
10.3.5.4.2 L4 Link Agent (L4 LA) Register Description .....................................................
10.3.5.5 L4 Address Protection (L4 AP) .........................................................................
10.3.5.5.1 L4 Address Protection (L4 AP) Register Summary .............................................
10.3.5.5.2 L4 Address Protection (L4 AP) Register Description ...........................................
11
Memory Subsystem ......................................................................................................... 3913
11.1
11.2
30
3847
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3903
Memory Subsystem Overview .........................................................................................
11.1.1 EMIF Overview ................................................................................................
11.1.2 GPMC Overview...............................................................................................
11.1.3 ELM Overview .................................................................................................
11.1.4 OCM Overview ................................................................................................
EMIF Controller ..........................................................................................................
11.2.1 EMIF Controller Overview ....................................................................................
11.2.2 EMIF Module Environment ...................................................................................
11.2.3 EMIF Module Integration .....................................................................................
11.2.4 EMIF Functional Description .................................................................................
11.2.4.1 Block Diagram ............................................................................................
11.2.4.1.1 Local Interface .......................................................................................
11.2.4.1.2 FIFO Description ....................................................................................
11.2.4.1.3 Arbitration of Commands in the Command FIFO ..............................................
11.2.4.2 Clock Management ......................................................................................
11.2.4.3 Reset ......................................................................................................
11.2.4.4 System Power Management ...........................................................................
11.2.4.4.1 Power-Down Mode ..................................................................................
11.2.4.4.2 LPDDR2 Deep Power-Down Mode ...............................................................
11.2.4.4.3 Self-Refresh Mode ..................................................................................
Contents
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SPRUIC6B – January 2017 – Revised October 2017
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11.3
11.2.4.5 Interrupt Requests .......................................................................................
11.2.4.6 SDRAM Refresh Scheduling ...........................................................................
11.2.4.7 SDRAM Initialization .....................................................................................
11.2.4.7.1 DDR2 SDRAM Initialization ........................................................................
11.2.4.7.2 DDR3/DDR3L SDRAM Initialization ..............................................................
11.2.4.7.3 LPDDR2 SDRAM Initialization .....................................................................
11.2.4.8 DDR3/DDR3L Read-Write Leveling ...................................................................
11.2.4.8.1 Full Leveling ..........................................................................................
11.2.4.8.2 Software Leveling ...................................................................................
11.2.4.9 EMIF Access Cycles .....................................................................................
11.2.4.10 Turnaround Time .......................................................................................
11.2.4.11 PHY DLL Calibration ...................................................................................
11.2.4.12 SDRAM Address Mapping .............................................................................
11.2.4.12.1 Address Mapping for IBANK_POS = 0 and EBANK_POS = 0 ..............................
11.2.4.12.2 Address Mapping for IBANK_POS = 1 and EBANK_POS = 0 ..............................
11.2.4.12.3 Address Mapping for IBANK_POS = 2 and EBANK_POS = 0 ..............................
11.2.4.12.4 Address Mapping for IBANK_POS = 3 and EBANK_POS = 0 ..............................
11.2.4.12.5 Address Mapping for IBANK_POS = 0 and EBANK_POS = 1 ..............................
11.2.4.12.6 Address Mapping for IBANK_POS = 1 and EBANK_POS = 1 ..............................
11.2.4.12.7 Address Mapping for IBANK_POS = 2 and EBANK_POS = 1 ..............................
11.2.4.12.8 Address Mapping for IBANK_POS = 3 and EBANK_POS = 1 ..............................
11.2.4.13 Output Impedance Calibration ........................................................................
11.2.4.14 LPDDR2 Temperature Monitoring ....................................................................
11.2.4.15 Error Correction And Detection Feature .............................................................
11.2.4.16 Class of Service .........................................................................................
11.2.4.17 Performance Counters ................................................................................
11.2.4.17.1 Performance Counters General Examples .....................................................
11.2.4.18 Forcing CKE to tri-state ................................................................................
11.2.5 EMIF Programming Guide ...................................................................................
11.2.5.1 EMIF Low-Level Programming Models ...............................................................
11.2.5.1.1 Global Initialization ..................................................................................
11.2.5.1.2 Operational Modes Configuration .................................................................
11.2.6 EMIF Register Manual ........................................................................................
11.2.6.1 EMIF Instance Summary ................................................................................
11.2.6.2 EMIF Registers ...........................................................................................
11.2.6.2.1 EMIF Register Summary ...........................................................................
11.2.6.2.2 EMIF Register Description .........................................................................
General-Purpose Memory Controller .................................................................................
11.3.1 GPMC Overview...............................................................................................
11.3.2 GPMC Environment ...........................................................................................
11.3.2.1 GPMC Modes ............................................................................................
11.3.2.2 GPMC Signals ............................................................................................
11.3.3 GPMC Integration .............................................................................................
11.3.4 GPMC Functional Description ...............................................................................
11.3.4.1 GPMC Block Diagram ...................................................................................
11.3.4.2 GPMC Clock Configuration .............................................................................
11.3.4.3 GPMC Software Reset ..................................................................................
11.3.4.4 GPMC Power Management ............................................................................
11.3.4.5 GPMC Interrupt Requests ..............................................................................
11.3.4.6 L3 Interconnect Interface................................................................................
11.3.4.7 GPMC Address and Data Bus .........................................................................
11.3.4.7.1 GPMC I/O Configuration Setting ..................................................................
11.3.4.7.2 GPMC CS0 Default Configuration at Device Reset ............................................
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Contents
3933
3934
3935
3935
3936
3938
3938
3939
3939
3940
3941
3941
3942
3942
3943
3943
3944
3944
3944
3945
3945
3946
3946
3947
3948
3949
3949
3950
3952
3952
3952
3959
3962
3962
3962
3962
3966
4068
4068
4068
4068
4071
4072
4076
4076
4077
4078
4078
4079
4079
4079
4080
4080
31
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11.4
32
11.3.4.8 Address Decoder and Chip-Select Configuration .................................................... 4082
11.3.4.8.1 Chip-Select Base Address and Region Size .................................................... 4082
11.3.4.8.2 Access Protocol ..................................................................................... 4083
11.3.4.8.3 External Signals ..................................................................................... 4084
11.3.4.8.4 Error Handling ....................................................................................... 4093
11.3.4.9 Timing Setting ............................................................................................ 4093
11.3.4.9.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME) ............. 4094
11.3.4.9.2 nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME /
CSWROFFTIME / CSEXTRADELAY) ............................................................ 4094
11.3.4.9.3 nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME /
ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFF
TIME) .................................................................................................. 4094
11.3.4.9.4 nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME /
OEAADMUXOFFTIME) ............................................................................. 4095
11.3.4.9.5 nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY) .................................................................................. 4096
11.3.4.9.6 GPMC_CLK .......................................................................................... 4096
11.3.4.9.7 GPMC_CLK and Control Signals Setup and Hold .............................................. 4097
11.3.4.9.8 Access Time (RDACCESSTIME / WRACCESSTIME) ......................................... 4097
11.3.4.9.9 Page Burst Access Time (PAGEBURSTACCESSTIME) ...................................... 4098
11.3.4.9.10 Bus Keeping Support .............................................................................. 4098
11.3.4.10 NOR Access Description .............................................................................. 4098
11.3.4.10.1 Asynchronous Access Description .............................................................. 4099
11.3.4.10.2 Synchronous Access Description ................................................................ 4106
11.3.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode ...................... 4115
11.3.4.10.4 Page and Burst Support .......................................................................... 4119
11.3.4.10.5 System Burst vs External Device Burst Support............................................... 4119
11.3.4.11 pSRAM Access Specificities .......................................................................... 4120
11.3.4.12 NAND Access Description ............................................................................. 4120
11.3.4.12.1 NAND Memory Device in Byte or 16-bit Word Stream Mode ................................ 4120
11.3.4.12.2 NAND Device-Ready Pin ......................................................................... 4127
11.3.4.12.3 ECC Calculator ..................................................................................... 4128
11.3.4.12.4 Prefetch and Write-Posting Engine .............................................................. 4144
11.3.5 GPMC Basic Programming Model .......................................................................... 4152
11.3.5.1 GPMC High-Level Programming Model Overview .................................................. 4152
11.3.5.2 GPMC Initialization ...................................................................................... 4154
11.3.5.3 GPMC Configuration in NOR Mode ................................................................... 4154
11.3.5.4 GPMC Configuration in NAND Mode .................................................................. 4155
11.3.5.5 Set Memory Access ..................................................................................... 4157
11.3.5.6 GPMC Timing Parameters .............................................................................. 4158
11.3.5.6.1 GPMC Timing Parameters Formulas ............................................................. 4161
11.3.6 GPMC Use Cases and Tips ................................................................................. 4171
11.3.6.1 How to Set GPMC Timing Parameters for Typical Accesses ...................................... 4171
11.3.6.1.1 External Memory Attached to the GPMC Module ............................................... 4171
11.3.6.1.2 Typical GPMC Setup ............................................................................... 4171
11.3.6.2 How to Choose a Suitable Memory to Use With the GPMC ....................................... 4177
11.3.6.2.1 Supported Memories or Devices .................................................................. 4177
11.3.6.2.2 GPMC Features and Settings ..................................................................... 4180
11.3.7 GPMC Register Manual ...................................................................................... 4181
11.3.7.1 GPMC Register Summary .............................................................................. 4181
11.3.7.2 GPMC Register Descriptions ........................................................................... 4182
Error Location Module .................................................................................................. 4214
11.4.1 Error Location Module Overview ............................................................................ 4214
Contents
SPRUIC6B – January 2017 – Revised October 2017
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11.5
12
11.4.2 ELM Integration................................................................................................
11.4.3 ELM Functional Description ..................................................................................
11.4.3.1 ELM Software Reset .....................................................................................
11.4.3.2 ELM Power Management ...............................................................................
11.4.3.3 ELM Interrupt Requests .................................................................................
11.4.3.4 Processing Initialization .................................................................................
11.4.3.5 Processing Sequence ...................................................................................
11.4.3.6 Processing Completion ..................................................................................
11.4.4 ELM Basic Programming Model.............................................................................
11.4.4.1 ELM Low-Level Programming Model ..................................................................
11.4.4.1.1 Processing Initialization.............................................................................
11.4.4.1.2 Read Results.........................................................................................
11.4.4.2 Use Case: ELM Used in Continuous Mode ..........................................................
11.4.4.3 Use Case: ELM Used in Page Mode ..................................................................
11.4.5 ELM Register Manual .........................................................................................
11.4.5.1 ELM Instance Summary.................................................................................
11.4.5.2 ELM Registers ............................................................................................
11.4.5.2.1 ELM Register Summary ............................................................................
11.4.5.2.2 ELM Register Description ..........................................................................
On-Chip Memory (OCM) Subsystem .................................................................................
11.5.1 OCM Subsystem Overview ..................................................................................
11.5.2 OCM Subsystem Integration .................................................................................
11.5.3 OCM Subsystem Functional Desctiption ...................................................................
11.5.3.1 Block Diagram ............................................................................................
11.5.3.2 Resets .....................................................................................................
11.5.3.3 Clock Management ......................................................................................
11.5.3.4 Interrupt Requests .......................................................................................
11.5.3.5 OCM Subsystem Memory Regions ....................................................................
11.5.3.6 OCM Controller Modes Of Operation .................................................................
11.5.3.7 ECC Associated FIFOs .................................................................................
11.5.3.8 ECC Counters And Corrected Bit Distribution Register .............................................
11.5.3.9 ECC Support..............................................................................................
11.5.3.10 Circular Buffer (CBUF) Support .......................................................................
11.5.3.11 CBUF Mode Error Handling ..........................................................................
11.5.3.11.1 VBUF Address Not Mapped to a CBUF Memory Space .....................................
11.5.3.11.2 VBUF Access Not Starting At The Base Address .............................................
11.5.3.11.3 Illegal Address Change Between Two Same Type Accesses ...............................
11.5.3.11.4 Illegal Frame SIze (Short Frame Detection)....................................................
11.5.3.11.5 CBUF Overflow.....................................................................................
11.5.3.11.6 CBUF Underflow ...................................................................................
11.5.3.12 Status Reporting .......................................................................................
11.5.4 OCM Subsystem Register Manual ..........................................................................
11.5.4.1 OCM Subsystem Instance Summary ..................................................................
11.5.4.2 OCM Subsystem Registers .............................................................................
11.5.4.2.1 OCM Subsystem Register Summary .............................................................
11.5.4.2.2 OCM Subsystem Register Description ...........................................................
4215
4216
4216
4216
4217
4217
4218
4219
4219
4219
4219
4220
4221
4222
4225
4225
4225
4225
4226
4243
4243
4243
4245
4245
4246
4246
4246
4250
4250
4250
4251
4251
4253
4254
4254
4255
4255
4256
4257
4257
4258
4258
4258
4258
4258
4259
Enhanced DMA ............................................................................................................... 4293
12.1
12.2
12.3
EDMA Module Overview ...............................................................................................
12.1.1 EDMA Features ...............................................................................................
12.1.2 EDMA Controllers Configuration ............................................................................
EDMA Controller Environment.........................................................................................
EDMA Controller Integration ...........................................................................................
12.3.1 DMA Requests to the EDMA Controller ....................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
4294
4295
4297
4298
4299
4303
33
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12.4
34
12.3.2 Mapping of DMA Requests to DMA_CROSSBAR Inputs ................................................
EDMA Controller Functional Description .............................................................................
12.4.1 Block Diagram .................................................................................................
12.4.1.1 Third-Party Channel Controller .........................................................................
12.4.1.2 Third-Party Transfer Controller .........................................................................
12.4.2 Types of EDMA controller Transfers........................................................................
12.4.2.1 A-Synchronized Transfers ..............................................................................
12.4.2.2 AB-Synchronized Transfers ............................................................................
12.4.3 Parameter RAM (PaRAM) ...................................................................................
12.4.3.1 PaRAM ....................................................................................................
12.4.3.2 EDMA Channel PaRAM Set Entry Fields .............................................................
12.4.3.2.1 Channel Options Parameter (OPT) ..............................................................
12.4.3.2.2 Channel Source Address (SRC) ..................................................................
12.4.3.2.3 Channel Destination Address (DST) ..............................................................
12.4.3.2.4 Count for 1st Dimension (ACNT) ..................................................................
12.4.3.2.5 Count for 2nd Dimension (BCNT) .................................................................
12.4.3.2.6 Count for 3rd Dimension (CCNT) .................................................................
12.4.3.2.7 BCNT Reload (BCNTRLD) .........................................................................
12.4.3.2.8 Source B Index (SBIDX)............................................................................
12.4.3.2.9 Destination B Index (DBIDX) ......................................................................
12.4.3.2.10 Source C Index (SCIDX) ..........................................................................
12.4.3.2.11 Destination C Index (DCIDX) .....................................................................
12.4.3.2.12 Link Address (LINK) ...............................................................................
12.4.3.3 Null PaRAM Set ..........................................................................................
12.4.3.4 Dummy PaRAM Set .....................................................................................
12.4.3.5 Dummy Versus Null Transfer Comparison ...........................................................
12.4.3.6 Parameter Set Updates .................................................................................
12.4.3.7 Linking Transfers .........................................................................................
12.4.3.8 Constant Addressing Mode Transfers/Alignment Issues ...........................................
12.4.3.9 Element Size..............................................................................................
12.4.4 Initiating a DMA Transfer .....................................................................................
12.4.4.1 DMA Channels ...........................................................................................
12.4.4.1.1 Event-Triggered Transfer Request ................................................................
12.4.4.1.2 Manually-Triggered Transfer Request ............................................................
12.4.4.1.3 Chain-Triggered Transfer Request ................................................................
12.4.4.2 QDMA Channels .........................................................................................
12.4.4.2.1 Auto-triggered and Link-Triggered Transfer Request ..........................................
12.4.4.3 Comparison Between DMA and QDMA Channels ..................................................
12.4.5 Completion of a DMA Transfer ..............................................................................
12.4.5.1 Normal Completion ......................................................................................
12.4.5.2 Early Completion .........................................................................................
12.4.5.3 Dummy or Null Completion .............................................................................
12.4.6 Event, Channel, and PaRAM Mapping .....................................................................
12.4.6.1 DMA Channel to PaRAM Mapping ....................................................................
12.4.6.2 QDMA Channel to PaRAM Mapping ..................................................................
12.4.7 EDMA Channel Controller Regions .........................................................................
12.4.7.1 Region Overview .........................................................................................
12.4.7.2 Channel Controller Regions ............................................................................
12.4.7.3 Region Interrupts .........................................................................................
12.4.8 Chaining EDMA Channels ...................................................................................
12.4.9 EDMA Interrupts ...............................................................................................
12.4.9.1 Transfer Completion Interrupts .........................................................................
12.4.9.1.1 Enabling Transfer Completion Interrupts .........................................................
Contents
4306
4311
4311
4311
4313
4314
4315
4316
4316
4317
4320
4320
4320
4320
4320
4320
4320
4321
4321
4321
4321
4321
4322
4322
4322
4322
4323
4325
4328
4328
4328
4328
4328
4329
4329
4330
4330
4330
4331
4332
4332
4332
4332
4332
4333
4334
4334
4336
4336
4336
4338
4339
4340
SPRUIC6B – January 2017 – Revised October 2017
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12.5
12.6
12.7
12.4.9.1.2 Clearing Transfer Completion Interrupts .........................................................
12.4.9.2 EDMA Interrupt Servicing ...............................................................................
12.4.9.3 Interrupt Evaluation Operations ........................................................................
12.4.9.4 Error Interrupts ...........................................................................................
12.4.10 Memory Protection ..........................................................................................
12.4.10.1 Active Memory Protection .............................................................................
12.4.10.2 Proxy Memory Protection ..............................................................................
12.4.11 Event Queue(s) ..............................................................................................
12.4.11.1 DMA/QDMA Channel to Event Queue Mapping ....................................................
12.4.11.2 Queue RAM Debug Visibility ..........................................................................
12.4.11.3 Queue Resource Tracking .............................................................................
12.4.11.4 Performance Considerations ..........................................................................
12.4.12 EDMA Transfer Controller (EDMA_TPTC) ...............................................................
12.4.12.1 Architecture Details .....................................................................................
12.4.12.1.1 Command Fragmentation .........................................................................
12.4.12.1.2 TR Pipelining .......................................................................................
12.4.12.1.3 Performance Tuning ...............................................................................
12.4.12.2 Memory Protection......................................................................................
12.4.12.3 Error Generation ........................................................................................
12.4.12.4 Debug Features .........................................................................................
12.4.12.4.1 Destination FIFO Register Pointer ...............................................................
12.4.12.5 EDMA_TPTC Configuration ...........................................................................
12.4.13 Event Dataflow ...............................................................................................
12.4.14 EDMA controller Prioritization ..............................................................................
12.4.14.1 Channel Priority .........................................................................................
12.4.14.2 Trigger Source Priority .................................................................................
12.4.14.3 Dequeue Priority ........................................................................................
12.4.15 EDMA Power, Reset and Clock Management ...........................................................
12.4.15.1 Clock and Power Management .......................................................................
12.4.15.2 Reset Considerations ..................................................................................
12.4.16 Emulation Considerations ..................................................................................
EDMA Transfer Examples .............................................................................................
12.5.1 Block Move Example .........................................................................................
12.5.2 Subframe Extraction Example ...............................................................................
12.5.3 Data Sorting Example ........................................................................................
12.5.4 Peripheral Servicing Example ...............................................................................
12.5.4.1 Non-bursting Peripherals................................................................................
12.5.4.2 Bursting Peripherals .....................................................................................
12.5.4.3 Continuous Operation ...................................................................................
12.5.4.3.1 Receive Channel ....................................................................................
12.5.4.3.2 Transmit Channel ...................................................................................
12.5.4.4 Ping-Pong Buffering .....................................................................................
12.5.4.4.1 Synchronization with the CPU .....................................................................
12.5.4.5 Transfer Chaining Examples ...........................................................................
12.5.4.5.1 Servicing Input/Output FIFOs with a Single Event ..............................................
12.5.4.5.2 Breaking Up Large Transfers with Intermediate Chaining .....................................
12.5.5 Setting Up an EDMA Transfer ...............................................................................
EDMA Debug Checklist and Programming Tips ....................................................................
12.6.1 EDMA Debug Checklist ......................................................................................
12.6.2 EDMA Programming Tips ....................................................................................
EDMA Register Manual ................................................................................................
12.7.1 EDMA Instance Summary....................................................................................
12.7.2 EDMA Registers ...............................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
4342
4342
4343
4344
4346
4346
4349
4351
4351
4352
4352
4352
4353
4353
4353
4353
4354
4354
4354
4355
4355
4355
4356
4356
4357
4358
4358
4358
4358
4359
4359
4360
4360
4362
4363
4365
4365
4367
4369
4369
4369
4372
4372
4376
4376
4377
4379
4381
4381
4382
4383
4383
4383
35
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12.7.2.1 EDMA Register Summary ..............................................................................
12.7.2.2 EDMA Register Description.............................................................................
12.7.2.2.1 EDMA_TPCC Register Description .............................................................
12.7.2.2.2 EDMA_TPTC0 and EDMA_TPTC1 Register Description ....................................
13
Interrupt Controllers ........................................................................................................ 4552
13.1
13.2
13.3
13.4
14
Interrupt Controllers Overview .........................................................................................
Interrupt Controllers Environment .....................................................................................
Interrupt Controllers Integration .......................................................................................
13.3.1 Interrupt Requests to DSP1_INTC ..........................................................................
13.3.2 Interrupt Requests to DSP2_INTC ..........................................................................
13.3.3 Interrupt Requests to IPU_Cx_INTC .......................................................................
13.3.4 Interrupt Requests to EVE_INTC1 ..........................................................................
13.3.5 Mapping of Device Interrupts to IRQ_CROSSBAR Inputs...............................................
Interrupt Controllers Functional Description .........................................................................
4553
4555
4556
4556
4562
4567
4572
4573
4582
Control Module ............................................................................................................... 4583
14.1
14.2
14.3
14.4
14.5
36
4383
4401
4401
4522
Control Module Overview ..............................................................................................
Control Module Environment ..........................................................................................
Control Module Integration .............................................................................................
Control Module Functional Description ...............................................................................
14.4.1 Control Module Clock Configuration ........................................................................
14.4.2 Control Module Resets .......................................................................................
14.4.3 Control Module Power Management .......................................................................
14.4.3.1 Power Management Protocols .........................................................................
14.4.4 Hardware Requests ...........................................................................................
14.4.5 Control Module Initialization .................................................................................
14.4.6 Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule .
14.4.6.1 Pad Configuration Registers ............................................................................
14.4.6.2 Pull Selection .............................................................................................
14.4.6.3 Thermal Management Related Registers .............................................................
14.4.6.3.1 Temperature Sensor Control Registers ..........................................................
14.4.6.3.2 Registers For The Thermal Alert Comparator Block............................................
14.4.6.3.3 Thermal Shutdown Comparator Block ............................................................
14.4.6.3.4 Temperature Timestamp Registers ...............................................................
14.4.6.3.5 Other Thermal Management Related Registers ................................................
14.4.6.3.6 Summary Of The Thermal Management Related Registers...................................
14.4.6.3.7 ADC Values Versus Temperature.................................................................
14.4.6.4 IRQ_CROSSBAR Module Functional Description ...................................................
14.4.6.5 DMA_CROSSBAR Module Functional Description ..................................................
14.4.6.6 SDRAM Initiator Priority Registers .....................................................................
14.4.6.7 L3_MAIN Initiator Priority Registers ...................................................................
14.4.6.8 Memory Region Lock Registers ........................................................................
14.4.6.9 NMI Mapping To Respective Cores ...................................................................
14.4.6.10 Software Controls for the LPDDR2/DDR2/DDR3 I/O Cells .......................................
14.4.6.11 Reference Voltage for the Device LPDDR2/DDR2/DDR3 Receivers ............................
14.4.6.12 AVS Class 0 Associated Registers ...................................................................
14.4.6.13 Registers For Other Miscellaneous Functions ......................................................
14.4.6.13.1 System Boot Status Settings .....................................................................
14.4.6.13.2 Firewall Error Status Registers...................................................................
14.4.6.13.3 Settings Related To Different Peripheral Modules ............................................
14.4.6.14 Hardware Observability Related Registers ..........................................................
14.4.7 Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule ..
14.4.7.1 Registers For Basic EMIF configuration ..............................................................
Control Module Register Manual ......................................................................................
Contents
4584
4586
4587
4589
4589
4589
4589
4589
4589
4589
4590
4590
4591
4591
4593
4593
4595
4595
4596
4597
4597
4599
4603
4607
4607
4607
4608
4608
4611
4613
4614
4614
4615
4615
4615
4616
4617
4617
SPRUIC6B – January 2017 – Revised October 2017
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14.5.1 Control Module Instance Summary .........................................................................
14.5.2 CTRL_MODULE_CORE Registers .........................................................................
14.5.2.1 CTRL_MODULE_CORE Register Summary ........................................................
14.5.2.2 CTRL_MODULE_CORE Register Description ......................................................
14.5.3 CTRL_MODULE_WKUP Registers .........................................................................
14.5.3.1 CTRL_MODULE_WKUP Register Summary .........................................................
14.5.3.2 CTRL_MODULE_WKUP Register Description .......................................................
15
Mailbox .......................................................................................................................... 4996
15.1
15.2
15.3
15.4
15.5
16
4617
4617
4617
4629
4960
4960
4962
Mailbox Overview .......................................................................................................
Mailbox Integration ......................................................................................................
15.2.1 System MAILBOX Integration ...............................................................................
15.2.2 EVE Mailbox Integration ......................................................................................
Mailbox Functional Description ........................................................................................
15.3.1 Mailbox Block Diagram .......................................................................................
15.3.2 Mailbox Software Reset ......................................................................................
15.3.3 Mailbox Power Management ................................................................................
15.3.4 Mailbox Interrupt Requests ..................................................................................
15.3.5 Mailbox Assignment ..........................................................................................
15.3.5.1 Description ................................................................................................
15.3.6 Sending and Receiving Messages ..........................................................................
15.3.6.1 Description ................................................................................................
15.3.7 16-Bit Register Access .......................................................................................
15.3.7.1 Description ................................................................................................
15.3.8 Example of Communication ..................................................................................
Mailbox Programming Guide ..........................................................................................
15.4.1 Mailbox Low-level Programming Models ...................................................................
15.4.1.1 Global Initialization .......................................................................................
15.4.1.1.1 Surrounding Modules Global Initialization........................................................
15.4.1.1.2 Mailbox Global Initialization ........................................................................
15.4.1.2 Mailbox Operational Modes Configuration ............................................................
15.4.1.2.1 Mailbox Processing modes ........................................................................
15.4.1.3 Mailbox Events Servicing ...............................................................................
15.4.1.3.1 Events Servicing in Sending Mode ...............................................................
15.4.1.3.2 Events Servicing in Receiving Mode..............................................................
Mailbox Register Manual ...............................................................................................
15.5.1 Mailbox Instance Summary ..................................................................................
15.5.2 Mailbox Registers .............................................................................................
15.5.2.1 Mailbox Register Summary .............................................................................
15.5.2.2 Mailbox Register Description ...........................................................................
4997
4997
4997
4999
5001
5002
5002
5002
5003
5003
5003
5004
5004
5004
5004
5006
5007
5007
5007
5007
5007
5007
5007
5008
5008
5009
5010
5010
5010
5010
5011
Memory Management Units .............................................................................................. 5033
16.1
16.2
16.3
MMU Overview ..........................................................................................................
MMU Integration .........................................................................................................
MMU Functional Description ...........................................................................................
16.3.1 MMU Block Diagram ..........................................................................................
16.3.1.1 MMU Address Translation Process ....................................................................
16.3.1.2 Translation Tables .......................................................................................
16.3.1.2.1 Translation Table Hierarchy........................................................................
16.3.1.2.2 First-Level Translation Table ......................................................................
16.3.1.2.3 Two-Level Translation ..............................................................................
16.3.1.3 Translation Lookaside Buffer ...........................................................................
16.3.1.3.1 TLB Entry Format ...................................................................................
16.3.1.4 No Translation (Bypass) Regions ......................................................................
16.3.2 MMU Software Reset .........................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
Contents
5034
5036
5038
5038
5038
5039
5039
5040
5043
5046
5047
5048
5048
37
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16.4
16.5
17
17.4
17.5
Spinlock Overview.......................................................................................................
Spinlock Integration .....................................................................................................
Spinlock Functional Description .......................................................................................
17.3.1 Spinlock Software Reset .....................................................................................
17.3.2 Spinlock Power Management ...............................................................................
17.3.3 About Spinlocks ...............................................................................................
17.3.4 Spinlock Functional Operation...............................................................................
Spinlock Programming Guide..........................................................................................
17.4.1 Spinlock Low-level Programming Models ..................................................................
17.4.1.1 Surrounding Modules Global Initialization ............................................................
17.4.1.2 Basic Spinlock Operations ..............................................................................
17.4.1.2.1 Spinlocks Clearing After a System Bug Recovery ..............................................
17.4.1.2.2 Take and Release Spinlock ........................................................................
Spinlock Register Manual ..............................................................................................
17.5.1 Spinlock Instance Summary .................................................................................
17.5.2 Spinlock Registers ............................................................................................
17.5.2.1 Spinlock Register Summary ............................................................................
17.5.2.2 Spinlock Register Description ..........................................................................
5077
5078
5079
5079
5079
5079
5080
5081
5081
5081
5081
5081
5081
5084
5084
5084
5084
5084
Timers ........................................................................................................................... 5088
18.1
18.2
38
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5058
Spinlock ......................................................................................................................... 5076
17.1
17.2
17.3
18
16.3.3 MMU Power Management ...................................................................................
16.3.4 MMU Interrupt Requests .....................................................................................
16.3.5 MMU Error Handling ..........................................................................................
MMU Low-level Programming Models ................................................................................
16.4.1 Global Initialization ............................................................................................
16.4.1.1 Surrounding Modules Global Initialization ............................................................
16.4.1.2 MMU Global Initialization................................................................................
16.4.1.2.1 Main Sequence - MMU Global Initialization......................................................
16.4.1.2.2 Subsequence - Configure a TLB entry ...........................................................
16.4.1.3 Operational Modes Configuration ......................................................................
16.4.1.3.1 Main Sequence - Writing TLB Entries Statically.................................................
16.4.1.3.2 Main Sequence - Protecting TLB Entries ........................................................
16.4.1.3.3 Main Sequence - Deleting TLB Entries ...........................................................
16.4.1.3.4 Main Sequence - Read TLB Entries ..............................................................
MMU Register Manual ..................................................................................................
16.5.1 MMU Instance Summary .....................................................................................
16.5.2 MMU Registers ................................................................................................
16.5.2.1 MMU Register Summary ................................................................................
16.5.2.2 MMU Register Description ..............................................................................
Timers Overview ........................................................................................................
General-Purpose Timers ...............................................................................................
18.2.1 General-Purpose Timers Overview .........................................................................
18.2.1.1 GP Timer Features ......................................................................................
18.2.2 GP Timer Environment .......................................................................................
18.2.2.1 GP Timer External System Interface ..................................................................
18.2.3 GP Timer Integration..........................................................................................
18.2.4 GP Timer Functional Description............................................................................
18.2.4.1 GP Timer Block Diagram ...............................................................................
18.2.4.2 TIMER1 Power Management...........................................................................
18.2.4.2.1 Wake-Up Capability .................................................................................
18.2.4.3 Power Management of Other GP Timers .............................................................
18.2.4.3.1 Wake-Up Capability .................................................................................
18.2.4.4 Software Reset ...........................................................................................
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SPRUIC6B – January 2017 – Revised October 2017
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18.3
19
18.2.4.5 GP Timer Interrupts ......................................................................................
18.2.4.6 Timer Mode Functionality ...............................................................................
18.2.4.6.1 1-ms Tick Generation (Only TIMER1) ............................................................
18.2.4.7 Capture Mode Functionality ............................................................................
18.2.4.8 Compare Mode Functionality ...........................................................................
18.2.4.9 Prescaler Functionality ..................................................................................
18.2.4.10 Pulse-Width Modulation ................................................................................
18.2.4.11 Timer Counting Rate ...................................................................................
18.2.4.12 Timer Under Emulation ................................................................................
18.2.4.13 Accessing GP Timer Registers .......................................................................
18.2.4.13.1 Writing to Timer Registers ........................................................................
18.2.4.13.2 Reading From Timer Counter Registers ........................................................
18.2.4.14 Posted Mode Selection ................................................................................
18.2.5 GP Timer Low-Level Programming Models ...............................................................
18.2.5.1 Global Initialization .......................................................................................
18.2.5.1.1 Global Initialization of Surrounding Modules.....................................................
18.2.5.1.2 GP Timer Module Global Initialization ............................................................
18.2.5.2 Operational Mode Configuration .......................................................................
18.2.5.2.1 GP Timer Mode ......................................................................................
18.2.5.2.2 GP Timer Compare Mode ..........................................................................
18.2.5.2.3 GP Timer Capture Mode ...........................................................................
18.2.5.2.4 GP Timer PWM Mode ..............................................................................
18.2.6 GP Timer Register Manual...................................................................................
18.2.6.1 GP Timer Instance Summary...........................................................................
18.2.6.2 GP Timer Registers ......................................................................................
18.2.6.2.1 GP Timer Register Summary ......................................................................
18.2.6.2.2 GP Timer Register Description ....................................................................
18.2.6.2.3 TIMER1 Register Description ......................................................................
32-kHz Synchronized Timer (COUNTER_32K) .....................................................................
18.3.1 32-kHz Synchronized Timer Overview .....................................................................
18.3.1.1 32-kHz Synchronized Timer Features .................................................................
18.3.2 32-kHz Synchronized Timer Integration ....................................................................
18.3.3 32-kHz Synchronized Timer Functional Description ......................................................
18.3.3.1 Reading the 32-kHz Synchronized Timer .............................................................
18.3.4 COUNTER_32K Timer Register Manual ...................................................................
18.3.4.1 COUNTER_32K Timer Register Mapping Summary ................................................
18.3.4.2 COUNTER_32K Timer Register Description .........................................................
5102
5102
5103
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5112
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5136
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5136
5137
5138
5139
5139
5140
Serial Communication Interfaces ...................................................................................... 5142
19.1
Multimaster I2C Controller ..............................................................................................
19.1.1 I2C Overview ...................................................................................................
19.1.2 I2C Environment ...............................................................................................
19.1.2.1 I2C Typical Application...................................................................................
19.1.2.1.1 I2C Pins for Typical Connections in I2C Mode ..................................................
19.1.2.1.2 I2C Interface Typical Connections .................................................................
19.1.2.2 I2C Typical Connection Protocol and Data Format ..................................................
19.1.2.2.1 I2C Serial Data Format ..............................................................................
19.1.2.2.2 I2C Data Validity .....................................................................................
19.1.2.2.3 I2C Start and Stop Conditions......................................................................
19.1.2.2.4 I2C Addressing .......................................................................................
19.1.2.2.5 I2C Master Transmitter ..............................................................................
19.1.2.2.6 I2C Master Receiver .................................................................................
19.1.2.2.7 I2C Slave Transmitter ...............................................................................
19.1.2.2.8 I2C Slave Receiver ..................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
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19.1.2.2.9 I C Bus Arbitration ...................................................................................
19.1.2.2.10 I2C Clock Generation and Synchronization .....................................................
19.1.3 I2C Integration ..................................................................................................
19.1.4 2C Functional Description ....................................................................................
19.1.4.1 I2C Block Diagram........................................................................................
19.1.4.2 I2C Clocks .................................................................................................
19.1.4.2.1 I2C Clocking ..........................................................................................
19.1.4.2.2 I2C Automatic Blocking of the I2C Clock Feature ...............................................
19.1.4.3 I2C Software Reset .......................................................................................
19.1.4.4 I2C Power Management .................................................................................
19.1.4.5 I2C Interrupt Requests ...................................................................................
19.1.4.6 I2C DMA Requests .......................................................................................
19.1.4.7 I2C Programmable Multislave Channel Feature .....................................................
19.1.4.8 I2C FIFO Management ..................................................................................
19.1.4.8.1 I2C FIFO Interrupt Mode ............................................................................
19.1.4.8.2 I2C FIFO Polling Mode ..............................................................................
19.1.4.8.3 I2C FIFO DMA Mode ................................................................................
19.1.4.8.4 I2C Draining Feature ...............................................................................
19.1.4.9 I2C Noise Filter ...........................................................................................
19.1.4.10 I2C System Test Mode .................................................................................
19.1.5 I2C Programming Guide ......................................................................................
19.1.5.1 I2C Low-Level Programming Models ..................................................................
19.1.5.1.1 I2C Programming Model ...........................................................................
19.1.6 I2C Register Manual ...........................................................................................
19.1.6.1 I2C Instance Summary...................................................................................
19.1.6.2 I2C Registers ..............................................................................................
19.1.6.2.1 I2C Register Summary ..............................................................................
19.1.6.2.2 I2C Register Description ............................................................................
UART .....................................................................................................................
19.2.1 UART Overview ...............................................................................................
19.2.1.1 UART Features ...........................................................................................
19.2.2 UART Environment ...........................................................................................
19.2.2.1 UART Interface ...........................................................................................
19.2.2.1.1 System Using UART Communication With Hardware Handshake ...........................
19.2.2.1.2 UART Interface Description ........................................................................
19.2.2.1.3 UART Protocol and Data Format..................................................................
19.2.3 UART Integration ..............................................................................................
19.2.4 UART Functional Description ................................................................................
19.2.4.1 Block Diagram ............................................................................................
19.2.4.2 Clock Configuration ......................................................................................
19.2.4.3 Software Reset ...........................................................................................
19.2.4.4 Power Management .....................................................................................
19.2.4.4.1 UART Mode Power Management .................................................................
19.2.4.4.2 Local Power Management .........................................................................
19.2.4.5 Interrupt Requests .......................................................................................
19.2.4.5.1 UART Interrupt Management ......................................................................
19.2.4.6 FIFO Management .......................................................................................
19.2.4.6.1 FIFO Trigger .........................................................................................
19.2.4.6.2 FIFO Interrupt Mode ................................................................................
19.2.4.6.3 FIFO Polled Mode Operation ......................................................................
19.2.4.6.4 FIFO DMA Mode Operation ........................................................................
19.2.4.7 Mode Selection ...........................................................................................
19.2.4.7.1 Register Access Modes ............................................................................
2
19.2
40
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SPRUIC6B – January 2017 – Revised October 2017
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19.3
19.2.4.7.2 UART Mode Selection ..............................................................................
19.2.4.8 Protocol Formatting ......................................................................................
19.2.4.8.1 UART Mode ..........................................................................................
19.2.5 UART Basic Programming Model ...........................................................................
19.2.5.1 Global Initialization .......................................................................................
19.2.5.1.1 Surrounding Modules Global Initialization........................................................
19.2.5.1.2 UART Module Global Initialization ................................................................
19.2.5.2 Mode selection ..........................................................................................
19.2.5.3 Submode selection ......................................................................................
19.2.5.4 Load FIFO trigger and DMA mode settings ..........................................................
19.2.5.4.1 DMA mode Settings .................................................................................
19.2.5.4.2 FIFO Trigger Settings ...............................................................................
19.2.5.5 Protocol, Baud rate and interrupt settings ............................................................
19.2.5.5.1 Baud rate settings ...................................................................................
19.2.5.5.2 Interrupt settings .....................................................................................
19.2.5.5.3 Protocol settings .....................................................................................
19.2.5.5.4 UART Mode Selection ..............................................................................
19.2.5.6 Hardware and Software Flow Control Configuration ................................................
19.2.5.6.1 Hardware Flow Control Configuration ............................................................
19.2.5.6.2 Software Flow Control Configuration .............................................................
19.2.6 UART Register Manual .......................................................................................
19.2.6.1 UART Instance Summary ...............................................................................
19.2.6.2 UART Registers ..........................................................................................
19.2.6.2.1 UART Register Summary .........................................................................
19.2.6.2.2 UART Register Description ........................................................................
Multichannel Serial Peripheral Interface..............................................................................
19.3.1 McSPI Overview ...............................................................................................
19.3.2 McSPI Environment ...........................................................................................
19.3.2.1 Basic McSPI Pins for Master Mode....................................................................
19.3.2.2 Basic McSPI Pins for Slave Mode .....................................................................
19.3.2.3 Multichannel SPI Protocol and Data Format .........................................................
19.3.2.3.1 Transfer Format .....................................................................................
19.3.2.4 SPI in Master Mode ......................................................................................
19.3.2.5 SPI in Slave Mode .......................................................................................
19.3.3 McSPI Integration .............................................................................................
19.3.4 McSPI Functional Description ...............................................................................
19.3.4.1 McSPI Block Diagram ...................................................................................
19.3.4.2 Reset ......................................................................................................
19.3.4.3 Master Mode ..............................................................................................
19.3.4.3.1 Master Mode Features..............................................................................
19.3.4.3.2 Master Transmit-and-Receive Mode (Full Duplex) .............................................
19.3.4.3.3 Master Transmit-Only Mode (Half Duplex) .......................................................
19.3.4.3.4 Master Receive-Only Mode (Half Duplex) .......................................................
19.3.4.3.5 Single-Channel Master Mode ......................................................................
19.3.4.3.6 Start-Bit Mode .......................................................................................
19.3.4.3.7 Chip-Select Timing Control ........................................................................
19.3.4.3.8 Programmable SPI Clock ..........................................................................
19.3.4.4 Slave Mode ...............................................................................................
19.3.4.4.1 Dedicated Resources ...............................................................................
19.3.4.4.2 Slave Transmit-and-Receive Mode ...............................................................
19.3.4.4.3 Slave Transmit-Only Mode .........................................................................
19.3.4.4.4 Slave Receive-Only Mode .........................................................................
19.3.4.5 3-Pin or 4-Pin Mode .....................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
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19.4
19.5
42
19.3.4.6 FIFO Buffer Management ...............................................................................
19.3.4.6.1 Buffer Almost Full ...................................................................................
19.3.4.6.2 Buffer Almost Empty ................................................................................
19.3.4.6.3 End of Transfer Management......................................................................
19.3.4.7 Interrupts ..................................................................................................
19.3.4.7.1 Interrupt Events in Master Mode ..................................................................
19.3.4.7.2 Interrupt Events in Slave Mode ....................................................................
19.3.4.7.3 Interrupt-Driven Operation .........................................................................
19.3.4.7.4 Polling .................................................................................................
19.3.4.8 DMA Requests ...........................................................................................
19.3.4.9 Power Saving Management ............................................................................
19.3.4.9.1 Normal Mode.........................................................................................
19.3.4.9.2 Idle Mode .............................................................................................
19.3.5 McSPI Programming Guide ..................................................................................
19.3.5.1 McSPI Low-Level Programming Models ..............................................................
19.3.5.1.1 Global Initialization ..................................................................................
19.3.5.1.2 Operational Mode Configuration ..................................................................
19.3.5.1.3 Common Transfer Procedures Without FIFO – Polling Method ..............................
19.3.5.1.4 Common Transfer Procedures With FIFO – Polling Method ..................................
19.3.6 McSPI Register Manual ......................................................................................
19.3.6.1 McSPI Instance Summary ..............................................................................
19.3.6.2 McSPI Registers .........................................................................................
19.3.6.2.1 McSPI Register Summary ..........................................................................
19.3.6.2.2 McSPI Register Description ........................................................................
Quad Serial Peripheral Interface ......................................................................................
19.4.1 Quad Serial Peripheral Interface Overview ................................................................
19.4.2 QSPI Environment ............................................................................................
19.4.3 QSPI Integration ...............................................................................................
19.4.4 QSPI Functional Description .................................................................................
19.4.4.1 QSPI Block Diagram .....................................................................................
19.4.4.1.1 SFI Register Control ................................................................................
19.4.4.1.2 SFI Translator ........................................................................................
19.4.4.1.3 SPI Control Interface ................................................................................
19.4.4.1.4 SPI Clock Generator ...............................................................................
19.4.4.1.5 SPI Control State-Machine .........................................................................
19.4.4.1.6 SPI Data Shifter .....................................................................................
19.4.4.2 QSPI Clock Configuration ...............................................................................
19.4.4.3 QSPI Interrupt Requests ................................................................................
19.4.4.4 QSPI Memory Regions ..................................................................................
19.4.5 QSPI Register Manual ........................................................................................
19.4.5.1 QSPI Instance Summary ................................................................................
19.4.5.2 QSPI registers ............................................................................................
19.4.5.2.1 QSPI Register Summary ..........................................................................
19.4.5.2.2 QSPI Register Description ........................................................................
Multichannel Audio Serial Port ........................................................................................
19.5.1 McASP Overview ..............................................................................................
19.5.2 McASP Environment ..........................................................................................
19.5.2.1 McASP Signals ..........................................................................................
19.5.2.2 Protocols and Data Formats ............................................................................
19.5.2.2.1 Protocols Supported ................................................................................
19.5.2.2.2 Definition of Terms ..................................................................................
19.5.2.2.3 TDM Format ..........................................................................................
19.5.2.2.4 I2S Format ...........................................................................................
Contents
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SPRUIC6B – January 2017 – Revised October 2017
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19.5.2.2.5 S/PDIF Coding Format .............................................................................
19.5.3 McASP Integration ............................................................................................
19.5.4 McASP Functional Description ..............................................................................
19.5.4.1 McASP Block Diagram ..................................................................................
19.5.4.2 McASP Clock and Frame-Sync Configurations ......................................................
19.5.4.2.1 McASP Transmit Clock .............................................................................
19.5.4.2.2 McASP Receive Clock ..............................................................................
19.5.4.2.3 Frame-Sync Generator ............................................................................
19.5.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations .........................
19.5.4.3 Serializers .................................................................................................
19.5.4.4 Format Units ..............................................................................................
19.5.4.4.1 Transmit Format Unit ...............................................................................
19.5.4.4.2 Receive Format Unit ................................................................................
19.5.4.5 State-Machines ...........................................................................................
19.5.4.6 TDM Sequencers ........................................................................................
19.5.4.7 McASP Software Reset .................................................................................
19.5.4.8 McASP Power Management ...........................................................................
19.5.4.9 Transfer Modes...........................................................................................
19.5.4.9.1 Burst Transfer Mode ................................................................................
19.5.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode ...............................................
19.5.4.9.3 DIT Transfer Mode ..................................................................................
19.5.4.10 Data Transmission and Reception ...................................................................
19.5.4.10.1 Data Ready Status and Event/Interrupt Generation...........................................
19.5.4.11 McASP Audio FIFO (AFIFO) ..........................................................................
19.5.4.11.1 AFIFO Data Transmission ........................................................................
19.5.4.11.2 AFIFO Data Reception ............................................................................
19.5.4.11.3 Arbitration Between Transmit and Receive DMA Requests..................................
19.5.4.12 McASP Events and Interrupt Requests ..............................................................
19.5.4.12.1 Transmit Data Ready Event and Interrupt ......................................................
19.5.4.12.2 Receive Data Ready Event and Interrupt.......................................................
19.5.4.12.3 Error Interrupt ......................................................................................
19.5.4.12.4 Multiple Interrupts ..................................................................................
19.5.4.13 DMA Requests ..........................................................................................
19.5.4.14 Loopback Modes ........................................................................................
19.5.4.14.1 Loopback Mode Configurations ..................................................................
19.5.4.15 Error Reporting ..........................................................................................
19.5.4.15.1 Buffer Underrun Error -Transmitter ..............................................................
19.5.4.15.2 Buffer Overrun Error-Receiver ...................................................................
19.5.4.15.3 DATA Port Error - Transmitter ...................................................................
19.5.4.15.4 DATA Port Error - Receiver ......................................................................
19.5.4.15.5 Unexpected Frame Sync Error ...................................................................
19.5.4.15.6 Clock Failure Detection ...........................................................................
19.5.5 McASP Low-Level Programming Model ...................................................................
19.5.5.1 Global Initialization .......................................................................................
19.5.5.1.1 Surrounding Modules Global Initialization........................................................
19.5.5.1.2 McASP Global Initialization ........................................................................
19.5.5.2 Operational Modes Configuration ......................................................................
19.5.5.2.1 McASP Transmission Modes ......................................................................
19.5.5.2.2 McASP Reception Modes ..........................................................................
19.5.5.2.3 McASP Event Servicing ............................................................................
19.5.6 McASP Register Manual .....................................................................................
19.5.6.1 McASP Instance Summary .............................................................................
19.5.6.2 MCASP Registers ........................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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19.6
44
19.5.6.2.1 MCASP_CFG Register Summary .................................................................
19.5.6.2.2 MCASP_CFG Register Description ...............................................................
19.5.6.2.3 MCASP_AFIFO Register Summary...............................................................
19.5.6.2.4 MCASP_AFIFO Register Description .............................................................
19.5.6.2.5 MCASP_DAT Register Summary .................................................................
19.5.6.2.6 MCASP_DAT Register Description ...............................................................
DCAN .....................................................................................................................
19.6.1 DCAN Overview ...............................................................................................
19.6.1.1 Features ...................................................................................................
19.6.2 DCAN Environment ...........................................................................................
19.6.2.1 CAN Network Basics ....................................................................................
19.6.3 DCAN Integration .............................................................................................
19.6.4 DCAN Functional Description ...............................................................................
19.6.4.1 Module Clocking Requirements ........................................................................
19.6.4.2 Interrupt Functionality ...................................................................................
19.6.4.2.1 Message Object Interrupts .........................................................................
19.6.4.2.2 Status Change Interrupts ...........................................................................
19.6.4.2.3 Error Interrupts .......................................................................................
19.6.4.3 DMA Functionality........................................................................................
19.6.4.4 Local Power-Down Mode ...............................................................................
19.6.4.4.1 Entering Local Power-Down Mode ................................................................
19.6.4.4.2 Wakeup From Local Power Down ................................................................
19.6.4.5 SECDED Mechanism ....................................................................................
19.6.4.5.1 Behavior on Single Bit Error .......................................................................
19.6.4.5.2 Behavior on Double Bit Error ......................................................................
19.6.4.5.3 SECDED Testing ....................................................................................
19.6.4.6 Debug/Suspend Mode...................................................................................
19.6.4.7 Configuration of Message Objects Description ......................................................
19.6.4.7.1 Configuration of a Transmit Object for Data Frames ...........................................
19.6.4.7.2 Configuration of a Transmit Object for Remote Frames .......................................
19.6.4.7.3 Configuration of a Single Receive Object for Data Frames....................................
19.6.4.7.4 Configuration of a Single Receive Object for Remote Frames ................................
19.6.4.7.5 Configuration of a FIFO Buffer ....................................................................
19.6.4.8 Message Handling .......................................................................................
19.6.4.8.1 Message Handler Overview........................................................................
19.6.4.8.2 Receive/Transmit Priority ...........................................................................
19.6.4.8.3 Transmission of Messages in Event Driven CAN Communication ...........................
19.6.4.8.4 Updating a Transmit Object ........................................................................
19.6.4.8.5 Changing a Transmit Object .......................................................................
19.6.4.8.6 Acceptance Filtering of Received Messages ....................................................
19.6.4.8.7 Reception of Data Frames .........................................................................
19.6.4.8.8 Reception of Remote Frames .....................................................................
19.6.4.8.9 Reading Received Messages ......................................................................
19.6.4.8.10 Requesting New Data for a Receive Object....................................................
19.6.4.8.11 Storing Received Messages in FIFO Buffers ..................................................
19.6.4.8.12 Reading From a FIFO Buffer .....................................................................
19.6.4.9 CAN Bit Timing ...........................................................................................
19.6.4.9.1 Bit Time and Bit Rate ...............................................................................
19.6.4.9.2 DCAN Bit Timing Registers ........................................................................
19.6.4.10 Message Interface Register Sets .....................................................................
19.6.4.10.1 Message Interface Register Sets 1 and 2 ......................................................
19.6.4.10.2 IF3 Register Set ....................................................................................
19.6.4.11 Message RAM ..........................................................................................
Contents
5452
5455
5503
5504
5507
5508
5509
5509
5509
5511
5511
5513
5515
5516
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5517
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5538
SPRUIC6B – January 2017 – Revised October 2017
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19.7
19.6.4.11.1 Structure of Message Objects....................................................................
19.6.4.11.2 Addressing Message Objects in RAM ..........................................................
19.6.4.11.3 ECC RAM ...........................................................................................
19.6.4.11.4 Message RAM Representation in Debug/Suspend Mode ....................................
19.6.4.11.5 Message RAM Representation in Direct Access Mode .......................................
19.6.4.12 CAN Operation ..........................................................................................
19.6.4.12.1 CAN Module Initialization .........................................................................
19.6.4.12.2 CAN Message Transfer (Normal Operation) ...................................................
19.6.4.12.3 Test Modes .........................................................................................
19.6.4.13 GPIO Support ...........................................................................................
19.6.5 DCAN Register Manual.......................................................................................
19.6.5.1 DCAN Instance Summary ..............................................................................
19.6.5.2 DCAN Registers ..........................................................................................
19.6.5.2.1 DCAN Register Summary ..........................................................................
19.6.5.2.2 DCAN Register Description ........................................................................
MCAN .....................................................................................................................
19.7.1 MCAN Overview ...............................................................................................
19.7.1.1 Features ...................................................................................................
19.7.2 MCAN Environment ...........................................................................................
19.7.2.1 CAN Network Basics ....................................................................................
19.7.3 MCAN Integration .............................................................................................
19.7.4 MCAN Functional Description ...............................................................................
19.7.4.1 Module Clocking Requirements ........................................................................
19.7.4.2 Interrupt and DMA Requests ...........................................................................
19.7.4.2.1 Interrupt Requests...................................................................................
19.7.4.2.2 DMA Requests .......................................................................................
19.7.4.3 Fuseable CAN FD Operation Enable ..................................................................
19.7.4.4 Operating Modes .........................................................................................
19.7.4.4.1 Software Initialization ...............................................................................
19.7.4.4.2 Normal Operation ...................................................................................
19.7.4.4.3 CAN FD Operation ..................................................................................
19.7.4.4.4 Transmitter Delay Compensation .................................................................
19.7.4.4.5 Restricted Operation Mode ........................................................................
19.7.4.4.6 Bus Monitoring Mode ...............................................................................
19.7.4.4.7 Disabled Automatic Retransmission (DAR) Mode ..............................................
19.7.4.4.8 Power Down (Sleep Mode) ........................................................................
19.7.4.4.9 Test Modes ...........................................................................................
19.7.4.5 Timestamp Generation ..................................................................................
19.7.4.5.1 External Timestamp Counter ......................................................................
19.7.4.6 Timeout Counter .........................................................................................
19.7.4.7 Safety ......................................................................................................
19.7.4.7.1 ECC Wrapper ........................................................................................
19.7.4.7.2 ECC Aggregator .....................................................................................
19.7.4.8 Rx Handling ...............................................................................................
19.7.4.8.1 Acceptance Filtering ................................................................................
19.7.4.8.2 Rx FIFOs .............................................................................................
19.7.4.8.3 Dedicated Rx Buffers ...............................................................................
19.7.4.9 Tx Handling ...............................................................................................
19.7.4.9.1 Transmit Pause ......................................................................................
19.7.4.9.2 Dedicated Tx Buffers ...............................................................................
19.7.4.9.3 Tx FIFO ...............................................................................................
19.7.4.9.4 Tx Queue .............................................................................................
19.7.4.9.5 Mixed Dedicated Tx Buffers/Tx FIFO .............................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
5538
5540
5541
5542
5543
5544
5544
5547
5548
5551
5552
5552
5552
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5553
5608
5608
5608
5610
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5612
5613
5614
5614
5614
5615
5615
5615
5615
5616
5616
5618
5619
5619
5620
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5622
5623
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5630
5632
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19.8
46
19.7.4.9.6 Mixed Dedicated Tx Buffers/Tx Queue ...........................................................
19.7.4.9.7 Transmit Cancellation ...............................................................................
19.7.4.9.8 Tx Event Handling ...................................................................................
19.7.4.10 FIFO Acknowledge Handling ..........................................................................
19.7.4.11 Message RAM ..........................................................................................
19.7.4.11.1 Message RAM Configuration .....................................................................
19.7.4.11.2 Rx Buffer and FIFO Element .....................................................................
19.7.4.11.3 Tx Buffer Element..................................................................................
19.7.4.11.4 Tx Event FIFO Element ...........................................................................
19.7.4.11.5 Standard Message ID Filter Element............................................................
19.7.4.11.6 Extended Message ID Filter Element ...........................................................
19.7.5 MCAN Register Manual ......................................................................................
19.7.5.1 MCAN Instance Summary ..............................................................................
19.7.5.2 MCAN Registers .........................................................................................
19.7.5.2.1 MCAN Register Summary ..........................................................................
19.7.5.2.2 MCAN Register Description ........................................................................
Gigabit Ethernet Switch (GMAC_SW) ................................................................................
19.8.1 GMAC_SW Overview .........................................................................................
19.8.1.1 Features ...................................................................................................
19.8.2 GMAC_SW Environment .....................................................................................
19.8.2.1 RGMII Interface ..........................................................................................
19.8.3 GMAC_SW Integration .......................................................................................
19.8.4 GMAC_SW Functional Description .........................................................................
19.8.4.1 Functional Block Diagram ...............................................................................
19.8.4.2 GMAC_SW Ports ........................................................................................
19.8.4.3 Clocking ...................................................................................................
19.8.4.3.1 Subsystem Clocking ................................................................................
19.8.4.3.2 Interface Clocking ...................................................................................
19.8.4.4 Software IDLE ............................................................................................
19.8.4.5 Interrupt Functionality ...................................................................................
19.8.4.5.1 Receive Packet Completion Pulse Interrupt (RX_PULSE) ....................................
19.8.4.5.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE) ....................................
19.8.4.5.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)...................................
19.8.4.5.4 Miscellaneous Pulse Interrupt (MISC_PULSE) ..................................................
19.8.4.5.5 Interrupt Pacing ......................................................................................
19.8.4.6 Reset Isolation............................................................................................
19.8.4.6.1 Reset Isolation Functional Description ...........................................................
19.8.4.7 Software Reset ...........................................................................................
19.8.4.8 CPSW_3G ................................................................................................
19.8.4.8.1 CPDMA RX and TX Interfaces ....................................................................
19.8.4.8.2 Address Lookup Engine (ALE) ....................................................................
19.8.4.8.3 Packet Priority Handling ............................................................................
19.8.4.8.4 FIFO Memory Control ...............................................................................
19.8.4.8.5 FIFO Transmit Queue Control .....................................................................
19.8.4.8.6 Audio Video Bridging ...............................................................................
19.8.4.8.7 Ethernet MAC Sliver (CPGMAC_SL) .............................................................
19.8.4.8.8 Embedded Memories ...............................................................................
19.8.4.8.9 Flow Control ..........................................................................................
19.8.4.8.10 Short Gap ...........................................................................................
19.8.4.8.11 Switch Latency .....................................................................................
19.8.4.8.12 Emulation Control ..................................................................................
19.8.4.8.13 FIFO Loopback .....................................................................................
19.8.4.8.14 Device Level Ring (DLR) Support ...............................................................
Contents
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5723
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5761
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SPRUIC6B – January 2017 – Revised October 2017
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19.8.4.8.15 Energy Efficient Ethernet Support (802.3az) ...................................................
19.8.4.8.16 CPSW_3G Network Statistics ....................................................................
19.8.4.9 Static Packet Filter (SPF) ...............................................................................
19.8.4.9.1 SPF Overview .......................................................................................
19.8.4.9.2 SPF Functional Description ........................................................................
19.8.4.9.3 Programming Guide .................................................................................
19.8.4.10 Common Platform Time Sync (CPTS) ...............................................................
19.8.4.10.1 CPTS Architecture .................................................................................
19.8.4.10.2 CPTS Initialization .................................................................................
19.8.4.10.3 Time Stamp Value .................................................................................
19.8.4.10.4 Event FIFO .........................................................................................
19.8.4.10.5 Time Sync Events .................................................................................
19.8.4.10.6 CPTS Interrupt Handling ..........................................................................
19.8.4.11 CPPI Buffer Descriptors ...............................................................................
19.8.4.11.1 TX Buffer Descriptors .............................................................................
19.8.4.11.2 RX Buffer Descriptors .............................................................................
19.8.4.12 MDIO .....................................................................................................
19.8.4.12.1 MDIO Frame Formats .............................................................................
19.8.4.12.2 MDIO Functional Description .....................................................................
19.8.5 GMAC_SW Programming Guide ............................................................................
19.8.5.1 Transmit Operation ......................................................................................
19.8.5.2 Receive Operation .......................................................................................
19.8.5.3 MDIO Software Interface ................................................................................
19.8.5.3.1 Initializing the MDIO Module .......................................................................
19.8.5.3.2 Writing Data To a PHY Register ..................................................................
19.8.5.3.3 Reading Data From a PHY Register ..............................................................
19.8.5.4 Initialization and Configuration of CPSW .............................................................
19.8.6 GMAC_SW Register Manual ................................................................................
19.8.6.1 GMAC_SW Instance Summary ........................................................................
19.8.6.2 SS Registers ..............................................................................................
19.8.6.2.1 SS Register Summary ............................................................................
19.8.6.2.2 SS Register Description ..........................................................................
19.8.6.3 PORT Registers ..........................................................................................
19.8.6.3.1 PORT Register Summary ........................................................................
19.8.6.3.2 PORT Register Description .......................................................................
19.8.6.4 CPDMA registers.........................................................................................
19.8.6.4.1 CPDMA Register Summary ......................................................................
19.8.6.4.2 CPDMA Register Description ....................................................................
19.8.6.5 STATS Registers.........................................................................................
19.8.6.5.1 STATS Register Summary ........................................................................
19.8.6.5.2 STATS Register Description ......................................................................
19.8.6.6 STATERAM Registers...................................................................................
19.8.6.6.1 STATERAM Register Summary .................................................................
19.8.6.6.2 STATERAM Register Description ...............................................................
19.8.6.7 CPTS registers ...........................................................................................
19.8.6.7.1 CPTS Register Summary .........................................................................
19.8.6.7.2 CPTS Register Description .......................................................................
19.8.6.8 ALE registers .............................................................................................
19.8.6.8.1 ALE Register Summary ...........................................................................
19.8.6.8.2 ALE Register Description .........................................................................
19.8.6.9 SL registers ...............................................................................................
19.8.6.9.1 SL Register Summary .............................................................................
19.8.6.9.2 SL Register Description ...........................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
Contents
5762
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5769
5769
5769
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5791
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5797
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5798
5798
5800
5802
5802
5802
5803
5803
5804
5804
5804
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5804
5812
5812
5814
5860
5860
5862
5890
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5891
5908
5908
5909
5924
5924
5924
5930
5930
5930
5941
5941
5942
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19.8.6.10 MDIO registers ..........................................................................................
19.8.6.10.1 MDIO Register Summary .......................................................................
19.8.6.10.2 MDIO Register Description .....................................................................
19.8.6.11 WR registers .............................................................................................
19.8.6.11.1 WR Register Summary ..........................................................................
19.8.6.11.2 WR Register Description ........................................................................
19.8.6.12 SPF Registers ...........................................................................................
19.8.6.12.1 SPF Register Summary ..........................................................................
19.8.6.12.2 SPF Register Description ........................................................................
20
SDIO Controller............................................................................................................... 5983
20.1
20.2
20.3
20.4
20.5
48
5950
5950
5950
5960
5960
5960
5969
5969
5970
SDIO Overview ..........................................................................................................
20.1.1 SDIO Features .................................................................................................
SDIO Environment ......................................................................................................
20.2.1 Protocol and Data Format ....................................................................................
20.2.1.1 Protocol....................................................................................................
20.2.1.2 Data Format ..............................................................................................
SDIO Integration .........................................................................................................
SDIO Functional Description ...........................................................................................
20.4.1 Block Diagram .................................................................................................
20.4.2 Resets ..........................................................................................................
20.4.2.1 Hardware Reset ..........................................................................................
20.4.2.2 Software Reset ...........................................................................................
20.4.3 Power Management ..........................................................................................
20.4.4 Interrupt Requests ............................................................................................
20.4.4.1 Interrupt-Driven Operation ..............................................................................
20.4.4.2 Polling .....................................................................................................
20.4.4.3 Asynchronous Interrupt..................................................................................
20.4.5 DMA Modes ....................................................................................................
20.4.5.1 Slave DMA Operations ..................................................................................
20.4.5.1.1 DMA Receive Mode .................................................................................
20.4.5.1.2 DMA Transmit Mode ................................................................................
20.4.6 Mode Selection ................................................................................................
20.4.7 Buffer Management ...........................................................................................
20.4.7.1 Data Buffer ................................................................................................
20.4.7.1.1 Memory Size, Block Length, and Buffer-Management Relationship .........................
20.4.7.1.2 Data Buffer Status ...................................................................................
20.4.8 Transfer Process ..............................................................................................
20.4.8.1 Different Types of Commands .........................................................................
20.4.8.2 Different Types of Responses ..........................................................................
20.4.9 Transfer or Command Status and Errors Reporting ......................................................
20.4.9.1 Busy Time-Out for R1b, R5b Response Type .......................................................
20.4.9.2 Busy Time-Out After Write CRC Status ...............................................................
20.4.9.3 Write CRC Status Time-Out ............................................................................
20.4.9.4 Read Data Time-Out ....................................................................................
20.4.10 Transfer Stop .................................................................................................
20.4.11 Output Signals Generation .................................................................................
20.4.11.1 Generation on Falling Edge of SDIO clock ..........................................................
20.4.11.2 Generation on Rising Edge of SDIO clock ..........................................................
20.4.12 Test Registers ................................................................................................
20.4.13 SDIO Hardware Status Features ..........................................................................
SDIO Programming Guide .............................................................................................
20.5.1 Low-Level Programming Models ............................................................................
20.5.1.1 Global Initialization .......................................................................................
Contents
5984
5984
5986
5986
5986
5987
5990
5993
5993
5993
5993
5993
5994
5997
6000
6000
6000
6000
6001
6001
6002
6003
6003
6003
6006
6007
6007
6007
6007
6008
6009
6009
6009
6010
6011
6012
6012
6012
6013
6013
6014
6014
6014
SPRUIC6B – January 2017 – Revised October 2017
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20.6
21
20.5.1.1.1 Surrounding Modules Global Initialization........................................................
20.5.1.1.2 SDIO Host Controller Initialization Flow ..........................................................
20.5.1.2 Operational Modes Configuration ......................................................................
20.5.1.2.1 Basic Operations for SDIO Host Controller ......................................................
SDIO Register Manual ..................................................................................................
20.6.1 SDIO Instance Summary .....................................................................................
20.6.2 SDIO Registers ................................................................................................
20.6.2.1 SDIO Register Summary ................................................................................
20.6.2.2 SDIO Register Description .............................................................................
6014
6014
6017
6017
6030
6030
6030
6030
6031
General-Purpose Interface................................................................................................ 6081
21.1
21.2
21.3
21.4
21.5
General-Purpose Interface Overview .................................................................................
General-Purpose Interface Environment .............................................................................
21.2.1 General-Purpose Interface as a Keyboard Interface .....................................................
21.2.2 General-Purpose Interface Signals .........................................................................
General-Purpose Interface Integration ...............................................................................
General-Purpose Interface Functional Description .................................................................
21.4.1 General-Purpose Interface Block Diagram ................................................................
21.4.2 General-Purpose Interface Interrupt and Wake-Up Features ...........................................
21.4.2.1 Synchronous Path: Interrupt Request Generation ...................................................
21.4.2.2 Asynchronous Path: Wake-Up Request Generation ................................................
21.4.2.3 Wake-Up Event Conditions During Transition To/From IDLE State ...............................
21.4.2.4 Interrupt (or Wake-Up) Line Release ..................................................................
21.4.3 General-Purpose Interface Clock Configuration ..........................................................
21.4.3.1 Clocking ...................................................................................................
21.4.4 General-Purpose Interface Hardware and Software Reset ..............................................
21.4.5 General-Purpose Interface Power Management ..........................................................
21.4.5.1 Power Domain ............................................................................................
21.4.5.2 Power Management .....................................................................................
21.4.5.2.1 Idle Scheme ..........................................................................................
21.4.5.2.2 Operating Modes ....................................................................................
21.4.5.2.3 System Power Management and Wakeup .......................................................
21.4.5.2.4 Module Power Saving ..............................................................................
21.4.6 General-Purpose Interface Interrupt and Wake-Up Requests ..........................................
21.4.6.1 Interrupt Requests Generation .........................................................................
21.4.6.2 Wake-Up Requests Generation ........................................................................
21.4.7 General-Purpose Interface Channels Description ........................................................
21.4.8 General-Purpose Interface Data Input/Output Capabilities ..............................................
21.4.9 General-Purpose Interface Set-and-Clear Protocol.......................................................
21.4.9.1 Description ................................................................................................
21.4.9.2 Clear Instruction ..........................................................................................
21.4.9.2.1 Clear Register Addresses ..........................................................................
21.4.9.2.2 Clear Instruction Example ..........................................................................
21.4.9.3 Set Instruction ............................................................................................
21.4.9.3.1 Set Register Addresses ............................................................................
21.4.9.3.2 Set Instruction Example ............................................................................
General-Purpose Interface Programming Guide ....................................................................
21.5.1 General-Purpose Interface Low-Level Programming Models ...........................................
21.5.1.1 Global Initialization .......................................................................................
21.5.1.1.1 Surrounding Modules Global Initialization........................................................
21.5.1.1.2 General-Purpose Interface Module Global Initialization ........................................
21.5.1.2 General-Purpose Interface Operational Modes Configuration .....................................
21.5.1.2.1 General-Purpose Interface Read Input Register ................................................
21.5.1.2.2 General-Purpose Interface Set Bit Function .....................................................
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
Contents
6082
6085
6085
6086
6088
6092
6092
6093
6093
6094
6095
6096
6097
6097
6097
6098
6098
6098
6098
6098
6099
6099
6101
6101
6102
6103
6103
6104
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6105
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6107
6107
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21.6
22
6108
6109
6109
6109
6109
6111
Pulse-Width Modulation Subsystem .................................................................................. 6127
22.1
22.2
50
21.5.1.2.3 General-Purpose Interface Clear Bit Function...................................................
General-Purpose Interface Register Manual ........................................................................
21.6.1 General-Purpose Interface Instance Summary ...........................................................
21.6.2 General-Purpose Interface Registers .......................................................................
21.6.2.1 General-Purpose Interface Register Summary ......................................................
21.6.2.2 General-Purpose Interface Register Description ....................................................
PWM Subsystem Resources ..........................................................................................
22.1.1 PWMSS Overview ............................................................................................
22.1.1.1 PWMSS Key Features ..................................................................................
22.1.1.2 PWMSS Unsupported Fetaures........................................................................
22.1.2 PWMSS Environment.........................................................................................
22.1.2.1 PWMSS I/O Interface....................................................................................
22.1.3 PWMSS Integration ...........................................................................................
22.1.3.1 PWMSS Module Interfaces Implementation ..........................................................
22.1.3.1.1 Device Specific PWMSS Features ................................................................
22.1.3.1.2 eHRPWM Module Time Base Clock Gating .....................................................
22.1.4 PWMSS Subsystem Power, Reset and Clock Configuration............................................
22.1.4.1 PWMSS Local Clock Management ....................................................................
22.1.4.2 PWMSS Module Local Clock Gating ..................................................................
22.1.4.3 PWMSS Software Reset ................................................................................
22.1.5 PWMSS_CFG Register Manual .............................................................................
22.1.5.1 PWMSS_CFG Instance Summary .....................................................................
22.1.5.2 PWMSS_CFG Registers ................................................................................
22.1.5.2.1 PWMSS_CFG Register Summary ...............................................................
22.1.5.2.2 PWMSS_CFG Register Description .............................................................
Enhanced PWM (ePWM) Module .....................................................................................
22.2.1 ePWM Overview...............................................................................................
22.2.2 ePWM Functional Description ...............................................................................
22.2.2.1 ePWM Submodule Features ...........................................................................
22.2.2.2 Proper ePWM Interrupt Initialization Procedure .....................................................
22.2.2.3 ePWM Time-Base (TB) Submodule ...................................................................
22.2.2.3.1 Purpose of the ePWM Time-Base Submodule ..................................................
22.2.2.3.2 Controlling and Monitoring the ePWM Time-Base Submodule ...............................
22.2.2.3.3 Calculating PWM Period and Frequency.........................................................
22.2.2.3.4 ePWM Time-Base Counter Modes and Timing Waveforms ...................................
22.2.2.4 ePWM Counter-Compare (CC) Submodule ..........................................................
22.2.2.4.1 Purpose of the ePWM Counter-Compare Submodule .........................................
22.2.2.4.2 Controlling and Monitoring the ePWM Counter-Compare Submodule .......................
22.2.2.4.3 Operational Highlights for the ePWM Counter-Compare Submodule ........................
22.2.2.4.4 ePWM Count Mode Timing Waveforms .........................................................
22.2.2.5 ePWM Action-Qualifier (AQ) Submodule .............................................................
22.2.2.5.1 Purpose of the ePWM Action-Qualifier Submodule.............................................
22.2.2.5.2 Controlling and Monitoring the ePWM Action-Qualifier Submodule ..........................
22.2.2.5.3 ePWM Action-Qualifier Event Priority.............................................................
22.2.2.5.4 Waveforms for Common ePWM Configurations ................................................
22.2.2.6 ePWM Dead-Band Generator (DB) Submodule .....................................................
22.2.2.6.1 Purpose of the ePWM Dead-Band Submodule .................................................
22.2.2.6.2 Controlling and Monitoring the ePWM Dead-Band Submodule ...............................
22.2.2.6.3 Operational Highlights for the ePWM Dead-Band Generator Submodule ...................
22.2.2.7 PWM-Chopper (PC) Submodule .......................................................................
22.2.2.7.1 Purpose of the PWM-Chopper Submodule ......................................................
22.2.2.7.2 Controlling the PWM-Chopper Submodule ......................................................
Contents
6128
6128
6128
6129
6129
6129
6132
6135
6135
6136
6136
6136
6137
6137
6137
6137
6138
6138
6138
6142
6142
6145
6145
6148
6148
6149
6150
6151
6153
6157
6158
6158
6159
6159
6162
6162
6162
6165
6166
6180
6180
6180
6181
6184
6184
6184
SPRUIC6B – January 2017 – Revised October 2017
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22.3
22.4
22.2.2.7.3 Operational Highlights for the PWM-Chopper Submodule.....................................
22.2.2.7.4 PWM Chopper Waveforms .........................................................................
22.2.2.8 ePWM Trip-Zone (TZ) Submodule.....................................................................
22.2.2.8.1 Purpose of the ePWM Trip-Zone Submodule ...................................................
22.2.2.8.2 Controlling and Monitoring the ePWM Trip-Zone Submodule .................................
22.2.2.8.3 Operational Highlights for the ePWM Trip-Zone Submodule ..................................
22.2.2.8.4 Generating ePWM Trip Event Interrupts .........................................................
22.2.2.9 ePWM Event-Trigger (ET) Submodule ................................................................
22.2.2.9.1 Purpose of the ePWM Event-Trigger Submodule ...............................................
22.2.2.9.2 Controlling and Monitoring the ePWM Event-Trigger Submodule ............................
22.2.2.9.3 Operational Overview of the ePWM Event-Trigger Submodule ...............................
22.2.2.10 High-Resolution PWM (HRPWM) Submodule ......................................................
22.2.2.10.1 Purpose of the High-Resolution PWM Submodule ............................................
22.2.2.10.2 Architecture of the High-Resolution PWM Submodule .......................................
22.2.2.10.3 Controlling and Monitoring the High-Resolution PWM Submodule .........................
22.2.2.10.4 Configuring the High-Resolution PWM Submodule ...........................................
22.2.2.10.5 Operational Highlights for the High-Resolution PWM Submodule ..........................
22.2.2.11 eHRPWM Functional Register Groups ..............................................................
22.2.3 PWMSS_EPWM Register Manual ..........................................................................
22.2.3.1 PWMSS_EPWM Instance Summary ..................................................................
22.2.3.2 PWMSS_EPWM Registers .............................................................................
22.2.3.2.1 PWMSS_EPWM Register Summary..............................................................
22.2.3.2.2 PWMSS_EPWM Register Description............................................................
Enhanced Capture (eCAP) Module ...................................................................................
22.3.1 eCAP Overview ................................................................................................
22.3.1.1 Purpose of the eCAP Peripheral ......................................................................
22.3.1.2 eCAP Features ...........................................................................................
22.3.2 eCAP Functional Description ................................................................................
22.3.2.1 Capture and APWM Operating Mode .................................................................
22.3.2.2 eCAP Capture Mode Description ......................................................................
22.3.2.2.1 eCAP Event Prescaler ..............................................................................
22.3.2.2.2 eCAP Edge Polarity Select and Qualifier ........................................................
22.3.2.2.3 eCAP Continuous/One-Shot Control .............................................................
22.3.2.2.4 eCAP 32-Bit Counter and Phase Control ........................................................
22.3.2.2.5 CAP1-CAP4 Registers ..............................................................................
22.3.2.2.6 eCAP Interrupt Control .............................................................................
22.3.2.2.7 eCAP Shadow Load and Lockout Control .......................................................
22.3.2.2.8 eCAP Module APWM Mode Operation ...........................................................
22.3.2.3 Summary of eCAP Functional Registers..............................................................
22.3.3 PWMSS_ECAP Register Manual ..........................................................................
22.3.3.1 PWMSS_ECAP Instance Summary ...................................................................
22.3.3.2 PWMSS_ECAP Registers ..............................................................................
22.3.3.2.1 PWMSS_ECAP Register Summary...............................................................
22.3.3.2.2 PWMSS_ECAP Register Description ...........................................................
Enhanced Quadrature Encoder Pulse (eQEP) Module ............................................................
22.4.1 eQEP Overview ...............................................................................................
22.4.2 eQEP Module Functional Description ......................................................................
22.4.2.1 eQEP Inputs ..............................................................................................
22.4.2.2 eQEP Quadrature Decoder Unit (QDU) ...............................................................
22.4.2.2.1 eQEP Position Counter Input Modes .............................................................
22.4.2.2.2 eQEP Input Polarity Selection .....................................................................
22.4.2.2.3 eQEP Position-Compare Sync Output ...........................................................
22.4.2.3 eQEP Position Counter and Control Unit (PCCU) ...................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
6185
6186
6188
6188
6189
6189
6190
6192
6192
6192
6193
6196
6197
6198
6198
6199
6199
6202
6204
6204
6204
6204
6204
6230
6230
6230
6230
6230
6231
6232
6233
6234
6234
6235
6236
6236
6236
6238
6239
6239
6239
6239
6239
6240
6251
6251
6254
6254
6255
6257
6259
6259
6259
51
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22.4.2.3.1 eQEP Position Counter Operating Modes .......................................................
22.4.2.3.2 eQEP Position Counter Latch .....................................................................
22.4.2.3.3 eQEP Position Counter Initialization ..............................................................
22.4.2.3.4 eQEP Position-Compare Unit ......................................................................
22.4.2.4 eQEP Edge Capture Unit ...............................................................................
22.4.2.5 eQEP Watchdog .........................................................................................
22.4.2.6 Unit Timer Base ..........................................................................................
22.4.2.7 eQEP Interrupt Structure ................................................................................
22.4.2.8 Summary of PWMSS eQEP Functional Registers ..................................................
22.4.3 PWMSS_EQEP Register Manual ..........................................................................
22.4.3.1 PWMSS_EQEP Instance Summary ...................................................................
22.4.3.2 PWMSS_EQEP Registers ..............................................................................
22.4.3.2.1 PWMSS_EQEP Register Summary ..............................................................
22.4.3.2.2 PWMSS_EQEP Register Description ............................................................
23
ADC............................................................................................................................... 6291
23.1
23.2
23.3
23.4
23.5
23.6
24
ADC Overview ...........................................................................................................
ADC Environment .......................................................................................................
23.2.1 ADC Signals ...................................................................................................
ADC Integration..........................................................................................................
ADC Functional Description............................................................................................
23.4.1 Open Delay ....................................................................................................
23.4.2 Averaging of Samples (1, 2, 4, 8, and 16) .................................................................
23.4.3 One-Shot (Single) or Continuous Mode ...................................................................
23.4.4 Interrupts .......................................................................................................
23.4.5 DMA Requests ................................................................................................
23.4.6 Power Management ..........................................................................................
23.4.7 Analog Front End (AFE) Functional Block Diagram .....................................................
23.4.8 Operational Modes ............................................................................................
ADC Programming Guide ..............................................................................................
23.5.1 ADC Low-Level Programming Models .....................................................................
23.5.1.1 Global Initialization .......................................................................................
23.5.1.1.1 Surrounding Modules Global Initialization........................................................
23.5.1.1.2 General Programming Model ......................................................................
23.5.1.2 During Operation .........................................................................................
ADC Register Manual...................................................................................................
23.6.1 ADC Instance Summary ......................................................................................
23.6.2 ADC Registers .................................................................................................
23.6.2.1 ADC Register Summary.................................................................................
23.6.2.2 ADC Register Description ..............................................................................
6292
6292
6293
6293
6295
6295
6295
6295
6295
6296
6296
6296
6297
6299
6299
6299
6299
6300
6300
6300
6300
6301
6301
6301
Real Time Interrupt Module .............................................................................................. 6320
24.1
52
6259
6262
6264
6264
6266
6269
6269
6270
6270
6271
6271
6271
6271
6273
Real Time Interrupt Module ............................................................................................
24.1.1 RTI Integration .................................................................................................
24.1.2 RTI Functional Description ...................................................................................
24.1.2.1 RTI Counter Operation ..................................................................................
24.1.2.2 RTI Digital Watchdog ....................................................................................
24.1.2.3 RTI Digital Windowed Watchdog ......................................................................
24.1.2.4 RTI Low Power Mode Operation .......................................................................
24.1.2.5 RTI Debug Mode Behavior .............................................................................
24.1.3 RTI Register Manual ..........................................................................................
24.1.3.1 RTI Instance Summary ..................................................................................
24.1.3.2 RTI registers ..............................................................................................
24.1.3.2.1 RTI Register Summary ............................................................................
24.1.3.2.2 RTI Register Description ..........................................................................
Contents
6321
6321
6325
6325
6327
6329
6330
6331
6331
6331
6331
6331
6333
SPRUIC6B – January 2017 – Revised October 2017
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25
Initialization .................................................................................................................... 6361
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
Initialization Overview ...................................................................................................
25.1.1 Terminology ....................................................................................................
25.1.2 Initialization Process ..........................................................................................
Preinitialization ...........................................................................................................
25.2.1 Power Requirements .........................................................................................
25.2.2 Interaction With the PMIC Companion ....................................................................
25.2.3 Clock, Reset, and Control ....................................................................................
25.2.3.1 Overview ..................................................................................................
25.2.3.2 Clocking Scheme ........................................................................................
25.2.3.3 Reset Configuration......................................................................................
25.2.3.3.1 ON/OFF Interconnect and Power-On-Reset .....................................................
25.2.3.3.2 Warm Reset ..........................................................................................
25.2.3.3.3 Peripheral Reset by GPIO .........................................................................
25.2.3.3.4 Warm Reset Impact on GPIOs ....................................................................
25.2.3.4 Power-Management IC Companion Control..........................................................
25.2.3.5 PMIC Request Signals ..................................................................................
25.2.4 Sysboot Configuration ........................................................................................
25.2.4.1 GPMC Configuration for XIP ...........................................................................
25.2.4.2 System Clock Speed Selection ........................................................................
25.2.4.3 Miscellaneous Sysboot Settings .......................................................................
25.2.4.4 Booting Device Order Selection ........................................................................
25.2.4.5 Sysboot Pin Mapping ....................................................................................
25.2.4.6 Boot Interface Pin Multiplexing .........................................................................
Booting Overview........................................................................................................
25.3.1 Booting Types .................................................................................................
25.3.2 ROM Code Architecture ......................................................................................
Memory Maps ............................................................................................................
25.4.1 ROM Memory Map ............................................................................................
25.4.2 RAM Memory Map ............................................................................................
25.4.3 AMMU Mapping ...............................................................................................
Overall Booting Sequence .............................................................................................
Startup and Configuration ..............................................................................................
25.6.1 Startup ..........................................................................................................
25.6.2 Control Module Configuration ...............................................................................
25.6.3 PRCM Module Mode Configuration .........................................................................
25.6.4 Clocking Configuration .......................................................................................
25.6.5 Booting Device List Setup ....................................................................................
25.6.6 Warm Reset Device Selection ...............................................................................
Peripheral Booting.......................................................................................................
25.7.1 Description .....................................................................................................
25.7.2 Initialization Phase for UART Boot ..........................................................................
Memory Booting .........................................................................................................
25.8.1 Overview .......................................................................................................
25.8.2 Non-XIP Memory ..............................................................................................
25.8.3 XIP Memory ....................................................................................................
25.8.3.1 GPMC Initialization ......................................................................................
25.8.4 SPI/QSPI Flash Devices .....................................................................................
Image Format ............................................................................................................
25.9.1 Overview .......................................................................................................
25.9.2 Configuration Header .........................................................................................
25.9.2.1 CHSETTINGS Item ......................................................................................
25.9.2.2 CHFLASH Item ...........................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Contents
6362
6362
6362
6364
6364
6365
6365
6365
6367
6367
6367
6367
6368
6368
6368
6369
6369
6370
6370
6370
6371
6371
6372
6374
6374
6374
6376
6376
6377
6378
6379
6381
6381
6382
6382
6382
6383
6384
6386
6386
6388
6389
6389
6390
6391
6392
6392
6394
6394
6394
6396
6397
53
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25.9.2.3 CHQSPI Item .............................................................................................
25.9.3 GP Header .....................................................................................................
25.9.4 Image Execution...............................................................................................
25.10 Tracing ...................................................................................................................
26
On-Chip Debug Support ................................................................................................... 6403
26.1
26.2
26.3
26.4
26.5
26.6
26.7
54
6398
6399
6399
6401
Introduction ...............................................................................................................
26.1.1 Key Features...................................................................................................
Debug Interfaces ........................................................................................................
26.2.1 IEEE1149.1 ....................................................................................................
26.2.2 Debug (Trace) Port ...........................................................................................
26.2.3 Trace Connector and Board Layout Considerations......................................................
Debugger Connection ..................................................................................................
26.3.1 ICEPick Module ...............................................................................................
26.3.2 ICEPick Boot Modes ..........................................................................................
26.3.2.1 Default Boot Mode .......................................................................................
26.3.2.2 Wait-In-Reset .............................................................................................
26.3.3 Dynamic TAP Insertion .......................................................................................
26.3.3.1 ICEPick Secondary TAPs ...............................................................................
Primary Debug Support ................................................................................................
26.4.1 Processor Native Debug Support ...........................................................................
26.4.1.1 Cortex-M4 Processor ....................................................................................
26.4.1.2 DSP C66x .................................................................................................
26.4.1.3 ARP32 .....................................................................................................
26.4.2 Cross-Triggering ...............................................................................................
26.4.2.1 SoC-Level Cross-Triggering ............................................................................
26.4.2.2 Cross-Triggering With External Device ...............................................................
26.4.3 Suspend ........................................................................................................
26.4.3.1 Debug Aware Peripherals and Host Processors .....................................................
Real-Time Debug........................................................................................................
26.5.1 Real-Time Debug Events ....................................................................................
26.5.1.1 Emulation Interrupts .....................................................................................
Power, Reset, and Clock Management Debug Support ...........................................................
26.6.1 Power and Clock Management ..............................................................................
26.6.1.1 Power and Clock Control Override From Debugger.................................................
26.6.1.1.1 Debugger Directives ................................................................................
26.6.1.1.2 Intrusive Debug Model ..............................................................................
26.6.1.2 Debug Across Power Transition .......................................................................
26.6.1.2.1 Nonintrusive Debug Model .........................................................................
26.6.1.2.2 Debug Context Save and Restore ................................................................
26.6.2 Reset Management ...........................................................................................
26.6.2.1 Debugger Directives .....................................................................................
26.6.2.1.1 Assert Reset .........................................................................................
26.6.2.1.2 Block Reset ..........................................................................................
26.6.2.1.3 Wait-In-Reset ........................................................................................
Performance Monitoring ................................................................................................
26.7.1 IPU Subsystem Performance Monitoring ..................................................................
26.7.1.1 Subsystem Counter Timer Module ....................................................................
26.7.1.2 Cache Events .............................................................................................
26.7.2 DSP Subsystem Performance Monitoring .................................................................
26.7.2.1 Advanced Event Triggering .............................................................................
26.7.3 EVE Subsystem Performance Monitoring .................................................................
26.7.3.1 EVE Subsystem Counter Timer Module ..............................................................
26.7.3.2 EVE Subsystem SCTM Events ........................................................................
Contents
6404
6405
6408
6408
6408
6409
6410
6410
6410
6411
6411
6411
6411
6413
6413
6413
6413
6413
6413
6415
6416
6416
6416
6418
6418
6418
6419
6419
6419
6419
6419
6420
6420
6420
6420
6420
6420
6420
6420
6422
6422
6422
6422
6423
6423
6424
6424
6424
SPRUIC6B – January 2017 – Revised October 2017
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Processor Trace .........................................................................................................
26.8.1 DSP Processor Trace ........................................................................................
26.8.2 Trace Export ...................................................................................................
26.8.2.1 Trace Exported to External Trace Receiver ..........................................................
26.8.2.2 Trace Captured Into On-Chip Trace Buffer ...........................................................
26.9 System Instrumentation ................................................................................................
26.9.1 MIPI STM (CT_STM) .........................................................................................
26.9.2 System Trace Export .........................................................................................
26.9.2.1 CT_STM ATB Export ....................................................................................
26.9.2.2 Trace Streams Interleaving .............................................................................
26.9.3 Software Instrumentation .....................................................................................
26.9.3.1 SoC Software Instrumentation .........................................................................
26.9.4 OCP Watchpoint...............................................................................................
26.9.4.1 OCP Target Traffic Monitoring .........................................................................
26.9.4.2 Messages Triggered from System Events ............................................................
26.9.4.3 DMA Transfer Profiling ..................................................................................
26.9.5 EVE SMSET ...................................................................................................
26.9.6 ISS Hardware Instrumentation ..............................................................................
26.9.7 L3 NOC Statistics Collector ..................................................................................
26.9.7.1 L3 Master Latency Monitoring ..........................................................................
26.9.7.1.1 STAT_COLL1 Configuration .......................................................................
26.9.7.1.2 STAT_COLL2 Configuration .......................................................................
26.9.7.1.3 STAT_COLL3 Configuration .......................................................................
26.9.7.1.4 STAT_COLL4 Configuration .......................................................................
26.9.7.1.5 Statistics Collector Alarm Mode ...................................................................
26.9.7.1.6 Statistics Collector Suspend Mode................................................................
26.9.8 PM Instrumentation ...........................................................................................
26.9.9 CM Instrumentation ...........................................................................................
26.9.10 Master-ID Encoding .........................................................................................
26.9.10.1 Software Masters .......................................................................................
26.9.10.2 Hardware Masters ......................................................................................
26.10 Concurrent Debug Modes .............................................................................................
26.11 DRM Register Manual ..................................................................................................
26.11.1 DRM Instance Summary ....................................................................................
26.11.2 DRM Registers ...............................................................................................
26.11.2.1 DRM Register Summary .............................................................................
26.11.2.2 DRM Register Description ...........................................................................
26.8
A
6426
6426
6426
6426
6426
6427
6427
6427
6427
6428
6428
6428
6428
6428
6430
6430
6431
6431
6431
6434
6434
6435
6436
6437
6438
6438
6438
6439
6439
6440
6440
6441
6442
6442
6442
6442
6443
Glossary ........................................................................................................................ 6477
SPRUIC6B – January 2017 – Revised October 2017
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Contents
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List of Figures
1-1.
DM50x Environment Diagram ........................................................................................... 318
1-2.
DM50x Block Diagram ................................................................................................... 319
2-1.
Interconnect Overview
3-1.
Clock Tree Tool (CTT) ................................................................................................... 348
3-2.
Functional and Interface Clocks ........................................................................................ 349
3-3.
Generic Clock Domain ................................................................................................... 355
3-4.
Clock Domain State Transitions ........................................................................................ 356
3-5.
Clock Domain/Slave Module Clock-Management Interaction Sequence 1
358
3-6.
Clock Domain/Slave Module Clock-Management Interaction Sequence 2
359
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
3-29.
3-30.
3-31.
3-32.
3-33.
3-34.
3-35.
3-36.
3-37.
3-38.
3-39.
3-40.
3-41.
3-42.
3-43.
3-44.
56
...................................................................................................
.......................................
.......................................
Clock Domain/Slave Module Clock-Management Interaction Sequence 3 .......................................
Sliding Window for Dynamic Dependency.............................................................................
Generic Power Domain ..................................................................................................
Power Domain Transitions...............................................................................................
Generic Voltage Domain .................................................................................................
Generic Logic Voltage Management ...................................................................................
Generic Memory Voltage Management ................................................................................
SmartReflex Static Voltage Adjustment ................................................................................
SmartReflex Voltage Control Functional Overview ...................................................................
Comparison of Energy Consumed With/Without DVFS .............................................................
Comparison of Energy Consumed With/Without DPS ...............................................................
Performance Level and Applied Power-Management Techniques .................................................
PMFW Overview ..........................................................................................................
IPU1 Power-On Reset Sequence.......................................................................................
DSP1 Subsystem Power-On Reset Sequence .......................................................................
DSP1 Subsystem Software Warm Reset Sequence .................................................................
DSP2 Subsystem Power-On Reset Sequence .......................................................................
DSP2 Subsystem Software Warm Reset Sequence .................................................................
EVE Subsystem Power-On Reset Sequence .........................................................................
EVE Subsystem Software Warm Reset Sequence ..................................................................
Global Warm Reset Sequence ..........................................................................................
PRCM Module Clock Manager Overview ..............................................................................
PRM Clock Manager Overview ........................................................................................
CM_CORE_AON Overview (a) .........................................................................................
CM_CORE_AON Overview (b) .........................................................................................
CM_CORE_AON_CLKOUTMUX Clock Manager Overview (CLKOUTMUX0) ...................................
CM_CORE_AON_CLKOUTMUX Clock Manager Overview (CLKOUTMUX1 and CLKOUTMUX2) ..........
CM_CORE_AON_TIMER1 Clock Manager Overview ...............................................................
CM_CORE_AON_TIMER2 Clock Manager Overview ...............................................................
CM_CORE_AON_MCASP Clock Manager Overview ...............................................................
CM_CORE_AON_MCASP Clock Manager Overview (AUXCLK) ..................................................
Clock Control in Control Module Overview ............................................................................
Generic DPLL Functional Diagram .....................................................................................
DPLL_PER Overview ....................................................................................................
DPLL_CORE Overview ..................................................................................................
DPLL_EVE_VID_DSP Overview........................................................................................
DPLL_GMAC_DSP Overview ...........................................................................................
DPLL_DDR Overview ....................................................................................................
List of Figures
331
360
366
368
370
372
372
373
374
374
375
376
378
380
403
404
404
405
406
406
407
408
410
412
414
416
419
421
423
423
424
425
427
429
434
436
438
440
442
SPRUIC6B – January 2017 – Revised October 2017
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3-45.
CD_WKUPAON Overview ............................................................................................... 444
3-46.
CD_DSP1 Overview ...................................................................................................... 447
3-47.
CD_DSP2 Overview ...................................................................................................... 450
3-48.
CD_CUSTEFUSE Overview
3-49.
3-50.
3-51.
3-52.
3-53.
3-54.
3-55.
3-56.
3-57.
3-58.
3-59.
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
3-67.
3-68.
3-69.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
............................................................................................ 452
CD_L4PER1 Overview ................................................................................................... 454
CD_L4PER2 Overview ................................................................................................... 465
CD_L4PER3 Overview ................................................................................................... 470
CD_L3INIT Overview ..................................................................................................... 472
CD_EMU Overview ....................................................................................................... 475
CD_DSS Overview ....................................................................................................... 476
CD_L4_CFG Overview ................................................................................................... 479
CD_L3_INSTR Overview ................................................................................................ 481
CD_L3_MAIN1 Overview ................................................................................................ 483
CD_EMIF Overview ...................................................................................................... 486
CD_IPU Overview ........................................................................................................ 488
CD_IPU1 Overview ....................................................................................................... 491
CD_CRC Overview ....................................................................................................... 493
CD_CAM Overview ....................................................................................................... 495
CD_COREAON_L4 Overview ........................................................................................... 497
CD_GMAC Overview ..................................................................................................... 498
CD_ISS Overview ........................................................................................................ 500
CD_EVE1 Overview ...................................................................................................... 502
PRM Voltage Control Architecture ...................................................................................... 520
I/O Pads Daisy-Chain Configuration ................................................................................... 525
DPLL Output-Frequency Change ....................................................................................... 529
DSP Subsystem Highlight .............................................................................................. 1378
DSP Subsystem Integration............................................................................................ 1382
DSP_SYSTEM Block Diagram ........................................................................................ 1398
Extended Duration Sleep Software and Hardware Sequence .................................................... 1402
DSP Subsystem Interrupt Management .............................................................................. 1404
ERRINT Diagram ........................................................................................................ 1407
DSP DMA Requests .................................................................................................... 1410
IPU Subsystem Overview .............................................................................................. 1470
IPU Subsystem Integration............................................................................................. 1473
IPU Subsystem Clocking Scheme .................................................................................... 1475
IPU Subsystem Reset Scheme........................................................................................ 1476
SCTM Block Diagram ................................................................................................... 1483
L1 Data ECC ............................................................................................................. 1486
L1 Tag ECC .............................................................................................................. 1486
L2 RAM ECC ............................................................................................................ 1487
IPU_WUGEN Overview ................................................................................................ 1488
IPU Power Mode Transitions .......................................................................................... 1491
Event Communication Connection in IPU Subsystem ............................................................. 1492
EVE Overview ........................................................................................................... 1530
ARP32 Versions and ISA/Feature Space ............................................................................ 1532
ARP32 CPU Block Diagram ........................................................................................... 1533
ARP32 CPU Pipeline ................................................................................................... 1538
ARP32 CPU Little Endianness ........................................................................................ 1540
Control Status Register (CSR) ........................................................................................ 1542
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Figures
57
www.ti.com
6-7.
Interrupt Enable Register (IER)........................................................................................ 1543
6-8.
Interrupt Flag Register (IFR) ........................................................................................... 1544
6-9.
Interrupt Set Register (ISR) ............................................................................................ 1545
6-10.
Interrupt Clear Register (ICR)
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
6-41.
6-42.
6-43.
6-44.
6-45.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
58
.........................................................................................
NMI Return Pointer Register (NRP) ..................................................................................
Interrupt Return Pointer Register (IRP) ..............................................................................
Stack Pointer Register (SP) ............................................................................................
Global Data Pointer Register (GDP) ..................................................................................
Link Register (LR) .......................................................................................................
Loop 0 Start Address Register (LSA0) ...............................................................................
Loop 0 End Address Register (LEA0) ................................................................................
Loop 0 Iteration Count Register (LCNT0) ............................................................................
Loop 1 Start Address Register (LSA1) ...............................................................................
Loop 1 End Address Register (LEA1) ................................................................................
Loop 1 Iteration Count Register (LCNT1) ............................................................................
Loop 0 Iteration Count Reload Value Register (LCNT0RLD) .....................................................
Shadow Control Status Register (SCSR) ............................................................................
NMI Shadow Control Status Register (NMISCSR) .................................................................
CPU Identification Register (CPUID) .................................................................................
Decode Program Counter Register (DPC) ...........................................................................
Time Stamp Counter Register - Low Half (TSCL) ..................................................................
Time Stamp Counter Register - High Half (TSCH) .................................................................
Loop Operation ..........................................................................................................
Interrupt Processing.....................................................................................................
Power-On-Reset .........................................................................................................
CPU Standby and Wakeup Procedure ...............................................................................
EVE Block Diagram .....................................................................................................
VCOP Block Diagram ...................................................................................................
EVE Memory Map .......................................................................................................
VCOP Instruction Buffering ............................................................................................
Addressing a Four-Dimensional Data Object ........................................................................
Load Word Distribution Options .......................................................................................
Load halfword Distribution Options ...................................................................................
Load Byte Distribution Options ........................................................................................
VST Rounding and Saturation Parameters ..........................................................................
Lookup Table Organization for Various Entry Size and Parallel Tables (NWAY = 8) ..........................
Example of Operation Delay Slots ....................................................................................
Binlog Function ..........................................................................................................
VMPY, VMADD and VMSUB Rounding Parameters ...............................................................
ISS Overview ............................................................................................................
ISS Integration ...........................................................................................................
ISS Interrupt Merger ....................................................................................................
ISS Local Interconnect Data Network ................................................................................
ISS Video Mux Possible connections .................................................................................
ISS Power Management ...............................................................................................
ISS CTSET Integration .................................................................................................
ISS Interfaces and Interconnects Highlight ..........................................................................
ISS Interfaces CAL_A Serial and Parallel Interface Configuration ...............................................
CPI Synchronization Signals and Frame Timing in SYNC Mode .................................................
List of Figures
1546
1547
1547
1548
1548
1548
1549
1549
1550
1551
1551
1552
1552
1553
1554
1555
1556
1556
1556
1564
1572
1722
1723
1727
1728
1730
1731
1738
1742
1743
1744
1749
1753
1762
1765
1773
1788
1792
1797
1800
1804
1808
1811
1911
1915
1918
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-11.
ISS Interfaces CPI Synchronization Signals and Data Timing in SYNC Mode ................................. 1918
7-12.
ISS Interfaces CPI SYNC Mode Clock Gating ...................................................................... 1919
7-13.
ISS Interfaces CPI Data Timing With Embedded Synchronization Signals (8-Bit Case) ...................... 1919
7-14.
ISS CSI2 PHY Diagram ................................................................................................ 1921
7-15.
ISS CSI2 Complex I/O Power FSM ................................................................................... 1922
7-16.
ISS CSI2 PHY RxMode and StopState FSM ........................................................................ 1923
7-17.
LVDS-RX Environment ................................................................................................. 1939
7-18.
LVDS Integration ........................................................................................................ 1941
7-19.
LVDS-RX Functional Block Diagram
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
.................................................................................
LVDS-RX Converting Piece-wise Compressed Output to 20-Bit Full Linear Output ...........................
LVDS-RX 12-16bit data decompression .............................................................................
CAL_A Environment ....................................................................................................
CAL_A Integration .......................................................................................................
CAL_B Integration .......................................................................................................
CAL_A Block Diagram ..................................................................................................
CAL_B Block Diagram ..................................................................................................
CAL Data Pipeline TAGs ...............................................................................................
CAL Interrupt Events Mapping to Registers .........................................................................
CSI2 Low Level Protocol Engine Block Diagram ...................................................................
CSI2 One Data-Lane Configuration ...................................................................................
CSI2 Two Data-Lane Merger Configuration .........................................................................
CSI2 Three Data-Lane Merger Configuration .......................................................................
CSI2 Four Data-Lane Merger Configuration .........................................................................
CSI2 Protocol Layer With Short and Long Packets.................................................................
CSI2 Short Packet Structure ...........................................................................................
CSI2 Long Packet Structure ...........................................................................................
CSI2 Data Identifier Structure .........................................................................................
CSI2 Virtual Channel ...................................................................................................
CSI2 General Frame Structure (Informative) ........................................................................
CSI2 Digital Interlaced Video Frame (Informative)..................................................................
CSI-2 LL Tag Generation Example - Line Mode ....................................................................
CSI-2 Packing – Example 1............................................................................................
CSI-2 Packing – Example 2............................................................................................
CSI-2 Packing – Example 3............................................................................................
CSI-2 Packing – Example 4............................................................................................
CAL Pixel Extraction ....................................................................................................
CAL_A PPI Interleaving - Physical View .............................................................................
CAL Stream Interleaving - Logical View..............................................................................
CAL Interleave FIFO reads ............................................................................................
CAL Interleaver - Example of RAW Bayer Data ....................................................................
CAL Pixel Packing ......................................................................................................
CAL MIPI RAW10 Data Packing ......................................................................................
CAL Pixel Packing – Data Storage in Memory ......................................................................
CAL Pixel Packing – Data Storage in Memory ......................................................................
Write DMA - Framing ...................................................................................................
CAL Read DMA Linear Read Mode ..................................................................................
CAL Read DMA RD2SKIP2 Read Mode .............................................................................
CAL Read DMA RD2SKIP4 Read Mode .............................................................................
CAL Read DMA YUV420 Upsampling................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Figures
1943
1944
1945
1986
1988
1989
1992
1992
1993
1997
1998
1999
2000
2001
2002
2003
2003
2004
2005
2006
2008
2009
2010
2011
2012
2012
2012
2014
2015
2016
2016
2017
2018
2019
2020
2021
2024
2027
2028
2029
2030
59
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7-60.
CAL Read DMA YUV420 Upsampling in Circular Mode ........................................................... 2031
7-61.
CAL Read DMA OCP Request Generation for Pixel Data ......................................................... 2032
7-62.
CAL Read DMA OCP Request Generation Example
7-63.
CAL Video Port and Timing Generator ............................................................................... 2034
7-64.
CAL Registers Shadowing Example .................................................................................. 2037
7-65.
ISS TCTRL Integration
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
7-100.
7-101.
7-102.
7-103.
7-104.
7-105.
7-106.
7-107.
7-108.
60
..............................................................
.................................................................................................
TCTRL Control-Signal Generation ....................................................................................
ISS TCTRL Use of cam_globalreset With Global Reset Release Camera Modules ...........................
cam_strobe Signal-Generation for Red-Eye Removal .............................................................
ISS ISP Block Diagram .................................................................................................
ISS ISP High-Level Diagram...........................................................................................
ISS ISP VP High-Level Diagram ......................................................................................
ISS ISP VP VD Pulse ...................................................................................................
ISS ISP GLBCE High-Level Diagram .................................................................................
ISS ISP GLBCE Iridix strength formula ..............................................................................
ISS ISP GLBCE Iridix f(analog gain) function .......................................................................
ISS ISP NSF3V High-Level Diagram .................................................................................
ISS ISP NSF3V High-Level Diagram .................................................................................
ISS ISP IPIPEIF High-Level Diagram ................................................................................
ISS ISP IPIPEIF Top-Level Block Diagram ..........................................................................
ISS ISP IPIPEIF Global Frame Definition in SDRAM Input Modes (Except Dark Frame) .....................
ISS ISP IPIPEIF Global Frame Definition in Dark Frame Subtract Mode .......................................
ISS ISP IPIPEIF Double-Buffer Functionality ........................................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0 Data Path.....................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1 Data Path.....................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2 Data Paths ...................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3 Data Paths: First Case .....................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3 Data Paths: Second Case .................................
ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0 Data Path.....................................................
ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0 Data Path.....................................................
ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0 Data Path.....................................................
ISS ISP IPIPEIF Timing Generator Submodule .....................................................................
ISS ISP IPIPEIF DPCM Subblock ....................................................................................
ISS ISP IPIPEIF Dark-Frame Subtraction Subblock ................................................................
ISS ISP IPIPEIF DFS/WDR sub block (WDR Mode) ...............................................................
ISS ISP IPIPEIF Resizer Offset Definition ...........................................................................
ISS ISP IPIPEIF YUV8P Settings .....................................................................................
ISS ISP IPIPE High-Level Diagram ...................................................................................
ISS ISP IPIPE Supported CFA Format ...............................................................................
ISS ISP IPIPE Module Block Diagram ...............................................................................
ISS ISP IPIPE Module Input Format ..................................................................................
ISS ISP IPIPE Module Processing Window Settings ...............................................................
ISS ISP IPIPE Defect Pixel Correction ...............................................................................
ISS ISP IPIPE Pixel Numbering in Defect Correction Algorithm ..................................................
ISS ISP IPIPE Mirroring in Defect Correction and Noise Filter....................................................
ISS ISP IPIPE Data flow of DPC Interface...........................................................................
ISS ISP IPIPE White Balance .........................................................................................
ISS ISP IPIPE YUV422 to 444 in co-sited mode ....................................................................
ISS ISP IPIPE YUV422 to 444 in co-sited mode ....................................................................
List of Figures
2033
2103
2104
2106
2110
2123
2129
2130
2132
2134
2136
2136
2143
2143
2146
2147
2148
2149
2150
2152
2153
2154
2155
2156
2157
2158
2159
2159
2160
2162
2164
2165
2167
2170
2170
2171
2172
2172
2173
2174
2174
2175
2176
2176
2177
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
....................................................................
ISS ISP IPIPE equation for YUVtoRGB conversion ...............................................................
ISS ISP IPIPE equation for YUVtoRGB conversion matrix .......................................................
ISS ISP IPIPE Gamma Correction Module Block Diagram ........................................................
ISS ISP IPIPE Gamma Curve Example ..............................................................................
ISS ISP IPIPE Gamma Table Offset and Slope Packing ..........................................................
ISS ISP IPIPE RGB2RGB Second Conversion Formula ..........................................................
ISS ISP IPIPE RGB2YCbCr Conversion Formula ..................................................................
ISS ISP IPIPE RGB2YCbCr Module Block Diagram ...............................................................
ISS ISP IPIPE Chroma Subsampling Position ......................................................................
ISS ISP IPIPE 4:2:2 Conversion Module Block Diagram ..........................................................
ISS ISP IPIPE 2D Edge-Enhancer Linear Filter .....................................................................
ISS ISP IPIPE 2D Edge-Enhancer Indexing .........................................................................
ISS ISP IPIPE 2D Edge Intensity LUT Formula .....................................................................
ISS ISP IPIPE 2D Edge-Enhancer LUT Packing ...................................................................
ISS ISP IPIPE 2D Edge-Enhancer Block Diagram .................................................................
ISS ISP IPIPE Edge Sharpener Details ..............................................................................
ISS ISP IPIPE 2D Edge-Intensity Clipping Formula ................................................................
ISS ISP IPIPE 2D Edge Enhancer and Sharpener Merger Formula .............................................
ISS ISP IPIPE 2D Edge Chroma-Suppression Coefficient Sets ..................................................
ISS ISP IPIPE 2D Edge-Brightness and Contrast Adjustments Formula ........................................
ISS ISP IPIPE Boxcar Operation (8 × 8 Block) .....................................................................
ISS ISP IPIPE Boxcar Operation (16 × 16 Block) ..................................................................
ISS ISP IPIPE Boxcar Data Packing in SDRAM ....................................................................
ISS ISP RSZ High-Level Diagram ....................................................................................
ISS ISP RSZ Top-Level Block Diagram ..............................................................................
ISS ISP RSZ MTC DMA Bandwidth Control .........................................................................
ISS ISP RSZ MTC Image Data Storage Pixel Order ...............................................................
ISS ISP RSZ Module Integration: High-Level Summary ...........................................................
ISS ISP RSZ Operating Modes .......................................................................................
ISS ISP RSZ Input Data Cropper Block Diagram ...................................................................
ISS ISP RSZ Input Data Cropping ....................................................................................
ISS ISP RSZ Averager Memory Utilization ..........................................................................
ISS ISP RSZ Averager Border Conditions ...........................................................................
ISS ISP RSZ Basic Interpolation Method ............................................................................
ISS ISP RSZ Interpolation Filtering ...................................................................................
ISS ISP RSZ-A/RSZ-B Phase Averager Effect ......................................................................
ISS ISP RSZ Chroma Position and Upsampling ....................................................................
ISS ISP RSZ and Circular Buffer Settings ...........................................................................
ISS ISP RSZ and Circular Buffer Settings – Example 1 ...........................................................
ISS ISP RSZ and Circular Buffer Settings – Example 2 ...........................................................
ISS ISP CNF High-Level Diagram ....................................................................................
ISS ISP CNF Top Level Block Diagram ..............................................................................
ISS ISP CNF original and downsampled grid, and downsample/upsample schemes .........................
ISS ISP CNF Chroma upsampling border replication scheme ....................................................
ISS ISP H3A High-Level Diagram ....................................................................................
ISS ISP H3A Top-Level Block Diagram ..............................................................................
ISS ISP H3A Frame Format Settings .................................................................................
ISS ISP H3A Red, Green, and Blue Pixel Extraction Examples ..................................................
7-109. ISS ISP IPIPE RGB2RGB Conversion Formula
2177
7-110.
2177
7-111.
7-112.
7-113.
7-114.
7-115.
7-116.
7-117.
7-118.
7-119.
7-120.
7-121.
7-122.
7-123.
7-124.
7-125.
7-126.
7-127.
7-128.
7-129.
7-130.
7-131.
7-132.
7-133.
7-134.
7-135.
7-136.
7-137.
7-138.
7-139.
7-140.
7-141.
7-142.
7-143.
7-144.
7-145.
7-146.
7-147.
7-148.
7-149.
7-150.
7-151.
7-152.
7-153.
7-154.
7-155.
7-156.
7-157.
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Figures
2177
2178
2178
2179
2179
2179
2180
2180
2180
2181
2181
2181
2182
2183
2183
2183
2184
2184
2184
2187
2187
2187
2190
2191
2192
2193
2196
2199
2200
2201
2202
2203
2204
2204
2206
2208
2210
2210
2211
2212
2213
2214
2214
2218
2219
2219
2221
61
www.ti.com
7-158. ISS ISP H3A Horizontal/Vertical FV Paxel Configuration .......................................................... 2222
7-159. ISS ISP H3A IIR Filter Model .......................................................................................... 2223
7-160. ISS ISP H3A AE/AWB Window Configurations ..................................................................... 2225
2226
7-162.
2229
7-163.
7-164.
7-165.
7-166.
7-167.
7-168.
7-169.
7-170.
7-171.
7-172.
7-173.
7-174.
7-175.
7-176.
7-177.
7-178.
7-179.
7-180.
7-181.
7-182.
7-183.
7-184.
7-185.
7-186.
7-187.
7-188.
7-189.
7-190.
7-191.
7-192.
7-193.
7-194.
7-195.
7-196.
7-197.
7-198.
7-199.
7-200.
7-201.
7-202.
7-203.
7-204.
7-205.
7-206.
62
.......................................
ISS ISP H3A AE/AWB Window and Subsample Definition ........................................................
ISS ISP ISIF High-Level Diagram .....................................................................................
ISS ISP ISIF Top-Level Block Diagram ..............................................................................
ISS ISP ISIF Interface Block Diagram ................................................................................
ISS ISP ISIF Sensor Linearization Block Diagram ..................................................................
ISS ISP ISIF Linearization LUT Memories ...........................................................................
ISS ISP ISIF Linearization Block Diagram ...........................................................................
ISS ISP ISIF Input Data Formatter Block Diagram .................................................................
ISS ISP ISIF Splits an Input Line Into Three Output Lines ........................................................
ISS ISP ISIF Input Data Formatter Area Settings ...................................................................
ISS ISP ISIF Data Formatter Output Control Example .............................................................
ISS ISP ISIF Conventional Read-Out Pattern .......................................................................
ISS ISP ISIF Conventional Read-Out Pattern With 2-tap AFE ....................................................
ISS ISP ISIF Combine Three Input Lines Into Single Line ........................................................
ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line ......................................
ISS ISP ISIF Color Space Converter Block Diagram ...............................................................
ISS ISP ISIF Color Space Converter Operation ....................................................................
ISS ISP ISIF Color Space Converter Operation: CMYG to RGBG ...............................................
ISS ISP ISIF Color Space Conversion Example ....................................................................
ISS ISP ISIF First Pixel/First Line Generation .......................................................................
ISS ISP ISIF Second Pixel/First Line Generation ...................................................................
ISS ISP ISIF Second Last Pixel/First Line Generation .............................................................
ISS ISP ISIF Last Pixel/First Line Generation .......................................................................
ISS ISP ISIF First Pixel/Last Line Generation .......................................................................
ISS ISP ISIF Second Pixel/Last Line Generation ...................................................................
ISS ISP ISIF Second Last Pixel/Last Line Generation .............................................................
ISS ISP ISIF Last Pixel/Last Line Generation .......................................................................
ISS ISP ISIF Black Clamp Block Diagram ...........................................................................
ISS ISP ISIF Clamp Value for Horizontal Direction .................................................................
ISS ISP ISIF Clamp Value for Vertical Direction Calculation ......................................................
ISS ISP ISIF Clamp Value for Vertical Direction With OB Region at the Left ...................................
ISS ISP ISIF Clamp Value for Vertical Direction With OB Region at the Right .................................
ISS ISP ISIF Vertical Line Defect Correction Block Diagram......................................................
ISS ISP ISIF Vertical Line Defects ....................................................................................
ISS ISP ISIF Vertical Line Defects ....................................................................................
ISS ISP ISIF 2D-LSC Block Diagram .................................................................................
ISS ISP ISIF 2D-LSC Active Region for ISIF Input Frame ........................................................
ISS ISP ISIF Gain and Offset Mask Upsampling via Bilinear Interpolation ......................................
ISS ISP ISIF White Balance Block Diagram .........................................................................
ISS ISP ISIF Low-Pass Filter Block Diagram ........................................................................
ISS ISP ISIF A-Law Compression Block Diagram ..................................................................
ISS ISP ISIF A-Law Table Diagram ..................................................................................
ISS ISP ISIF A-Law Table Values ....................................................................................
ISS ISP ISIF Culling Block Diagram ..................................................................................
ISS ISP ISIF Example for Decimation Pattern ......................................................................
7-161. ISS ISP H3A Black Row of Windows Before Regular Rows of Windows
List of Figures
2236
2237
2238
2239
2240
2240
2241
2242
2243
2244
2245
2246
2246
2247
2249
2250
2250
2250
2251
2251
2251
2251
2252
2252
2252
2252
2253
2254
2255
2256
2256
2257
2257
2258
2259
2260
2261
2264
2265
2266
2266
2267
2269
2269
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-207. ISS ISP ISIF Storage Formatter Block Diagram .................................................................... 2270
7-208. ISS ISP ISIF Frame Image Format Conversion ..................................................................... 2272
7-209. ISS ISP ISIF Circular Buffer control
..................................................................................
2273
7-210. ISS ISP ISIF Combination of Circular Buffer and Output Formatter .............................................. 2274
7-211. ISS ISP ISIF VDINT0/VDINT1/VDINT2 Interrupt Behavior When VDPOL = 0 .................................. 2276
7-212. ISS ISP ISIF VDINT0/VDINT1/VDINT2 Interrupt Behavior When VDPOL = 1 .................................. 2276
7-213. ISS ISP BL High-Level Diagram
......................................................................................
2278
7-214. ISS ISP BL Block Diagram ............................................................................................. 2280
7-215. ISS ISP BL Address Alignment ........................................................................................ 2281
7-216. SIMCOP Subsystem Overview ........................................................................................ 2908
7-217. SIMCOP Integration..................................................................................................... 2909
7-218. SIMCOP Interrupt Merger Overview .................................................................................. 2913
...................................................
........................................................................
SIMCOP Hardware Sequencer Overview ............................................................................
Hardware Sequencing Example .......................................................................................
Hardware Sequencer Operation Example ...........................................................................
SIMCOP Static Crossbar Overview ...................................................................................
Image Buffer Width Translation .......................................................................................
Typical Hardware Sequencer Controlled Sequencer With Pipe-Up and Pipe-Down ...........................
Pipe-Up and Pipe-Down ................................................................................................
IS DMA in the SIMCOP Subsystem ..................................................................................
DMA Engine Integration ................................................................................................
ISS SIMCOP DMA Block Diagram ....................................................................................
DMA Logical Channel States ..........................................................................................
DMA Addressing ........................................................................................................
2-Block Large Transfer Example ......................................................................................
YUV4:2:0-NV12 Read/Write Chain ...................................................................................
Temporal Channel Sequence..........................................................................................
ISS SIMCOP VTNF in the SIMCOP Subsystem ....................................................................
VTNF Engine Integration ...............................................................................................
VTNF YUV420 NV12/NV21 and YV12 data formats ...............................................................
VTNF Engine Integration ...............................................................................................
ISS SIMCOP VTNF Block Diagram ...................................................................................
ISS SIMCOP VTNF C, P, O array memory allocation constraints ................................................
ISS SIMCOP VTNF Typical lookup table contents .................................................................
ISS SIMCOP LDC Subsystem .........................................................................................
ISS SIMCOP LDC Integration .........................................................................................
ISS SIMCOP LDC Block Diagram ....................................................................................
YCbCr4:2:2 (UYVY) Format ...........................................................................................
ISS SIMCOP LDC YCbCr4:2:0 (NV12) Format .....................................................................
ISS SIMCOP LDC Supported Bayer Data Format (Starting Color) ...............................................
ISS SIMCOP LDC Supported Bayer Data Format ..................................................................
ISS SIMCOP LDC Inverse A-Law (8-Bit to 10-Bit)..................................................................
ISS SIMCOP LDC Forward A-Law (10-Bit to 8-Bit).................................................................
Example output tile of Bayer data .....................................................................................
Affine Transformation ...................................................................................................
ISS SIMCOP LDC Bicubic Interpolation for Y .......................................................................
ISS SIMCOP LDC Bilinear Interpolation for Y .......................................................................
7-219. Hardware Sequencer and Buffers in the SIMCOP Subsystem
2932
7-220. Hardware Sequencer and Buffer Integration
2933
7-221.
2936
7-222.
7-223.
7-224.
7-225.
7-226.
7-227.
7-228.
7-229.
7-230.
7-231.
7-232.
7-233.
7-234.
7-235.
7-236.
7-237.
7-238.
7-239.
7-240.
7-241.
7-242.
7-243.
7-244.
7-245.
7-246.
7-247.
7-248.
7-249.
7-250.
7-251.
7-252.
7-253.
7-254.
7-255.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Figures
2937
2938
2939
2941
2942
2943
2962
2963
2965
2967
2969
2969
2972
2973
2995
2996
2997
2998
3000
3002
3003
3016
3018
3020
3021
3021
3021
3022
3022
3023
3024
3024
3026
3026
63
www.ti.com
7-256. ISS SIMCOP LDC Bilinear Interpolation for CB/Cr in UYVY and NV12 Format ................................ 3027
7-257. ISS SIMCOP LDC Input Block Bound ................................................................................ 3028
7-258. ISS SIMCOP LDC Multiple-Pass Correction Example ............................................................. 3029
7-259. LDC and Hardware Sequencer and Buffers in the SIMCOP Subsystem ........................................ 3031
7-260. SIMCOP Static Crossbar Overview ................................................................................... 3032
7-261. SIMCOP Hardware Sequencer Overview ............................................................................ 3033
7-262. ISS SIMCOP LDC Parameters for Rotation ......................................................................... 3037
7-263. ISS SIMCOP LDC Parameters for Scaling
..........................................................................
3037
7-264. ISS SIMCOP LDC Parameters for Translation ...................................................................... 3038
VIP Overview
3054
8-2.
VIP Environment
3056
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
64
............................................................................................................
........................................................................................................
VIP Integration ...........................................................................................................
VIP Block Diagram ......................................................................................................
VIP Slice Detailed Block Diagram .....................................................................................
Input: B:YUV422; Output: B:RGB .....................................................................................
Input: A:YUV422 8/16, B:YUV422; Output: A:Scaled YUV420, B: RGB .........................................
Input: B:YUV422; Output: B:Scaled YUV420 ........................................................................
Input: A: YUV422 8/16; Output A:Scaled YUV420, B:Scaled YUV444 ..........................................
Input: A:YUV422 8/16, B:YUV422; Output: A: Scaled YUV420, B:YUV420.....................................
Input : A: YUV422 8/16, B: YUV422; Output: A: YUV420, B: YUV420 ..........................................
Bytelane Swapping Modes .............................................................................................
RAW16 to RGB565 Mapping ..........................................................................................
NTSC Analog Video Waveform for One Horizontal Line ...........................................................
Digitized Video ...........................................................................................................
Code Word Embedded Video Format ................................................................................
Digitized Video with F, V, and H Flags in EAV/SAV ................................................................
Planar Buffer Storage Description ....................................................................................
8-bit Interface Discrete Sync Pixel Multiplexing .....................................................................
16-bit Interface Discrete Sync Pixel Multiplexing ...................................................................
Discrete Sync Signals ..................................................................................................
Type 1, First Horizontal Blanking Pixel ...............................................................................
Type 1, First Vertical Ancillary Data Pixel ............................................................................
Type 1, Horizontal Blanking in Video Region ........................................................................
Type 1, First Video Pixel ...............................................................................................
4-Pin Reduced ACTVID Signaling with Vertical Ancillary Data ...................................................
4-Pin Reduced ACTVID Signaling with No Vertical Ancillary Data ...............................................
4-Pin Reduced HSYNC Signaling with Vertical Ancillary Data ....................................................
VSYNC Pre and Post Window.........................................................................................
VSYNC Equivalence When Using Transition Window .............................................................
FID Registering When Using HSYNC ................................................................................
FID Registering When Using ACTVID ................................................................................
Field ID Determination By VSYNC Skew ............................................................................
Example of 525-line FID Determination By VSYNC Skew.........................................................
Horizontal Ancillary Data Packing When HSYNC Used as Sync Signal .........................................
Interlaced Field Vertical Blanking Ancillary Data Storage..........................................................
Progressive Frame Vertical Blanking Ancillary Data Storage .....................................................
Embedded Sync Data Entry ...........................................................................................
Code Word Format Example Followed by Video Data .............................................................
Embedded Sync Packing...............................................................................................
8-1.
List of Figures
3059
3061
3063
3065
3066
3067
3068
3069
3070
3071
3071
3072
3072
3073
3074
3075
3076
3076
3076
3077
3077
3078
3078
3078
3079
3079
3080
3081
3082
3082
3083
3084
3085
3085
3086
3086
3087
3089
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
8-41.
2-Way Multiplexing ...................................................................................................... 3090
8-42.
Example of 4-Way Multiplexing........................................................................................ 3091
8-43.
Example of Line Multiplexing .......................................................................................... 3091
8-44.
8-bit Line Mux Interface
8-45.
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
8-59.
8-60.
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
8-69.
8-70.
8-71.
8-72.
8-73.
8-74.
8-75.
8-76.
8-77.
8-78.
8-79.
8-80.
8-81.
8-82.
8-83.
8-84.
8-85.
8-86.
8-87.
8-88.
8-89.
................................................................................................
16-bit Line Mux Interface ...............................................................................................
BOP/EOP Definition of a Period .......................................................................................
Channel ID Inserted Into Horizontal Blanking .......................................................................
Vertical Ancillary Data Cropping.......................................................................................
Active Video Cropping ..................................................................................................
Problematic Error Cropping Case .....................................................................................
Endline/Endframe Behavior for Error Cropping Case ..............................................................
Generic External Sync Signals ........................................................................................
vblnk and hblnk ..........................................................................................................
VBLNK and ACTID (1) ..................................................................................................
VBLNK and ACTVID(2) .................................................................................................
VBLNK and HSYNC ....................................................................................................
VSYNC and HBLNK ....................................................................................................
VSYNC and ACTIVID(1) ...............................................................................................
VSYNC and ACTIVID(2) ...............................................................................................
VSYNC and HSYNC ....................................................................................................
Ancillary and Active Video Line Determination ......................................................................
HSYNC Pixel Capture ..................................................................................................
ACTVID Pixel Capture ..................................................................................................
Matrix Format ............................................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
High Level Block Diagram..............................................................................................
SC Block Diagram .......................................................................................................
Input Image Trimming ..................................................................................................
Filter Implementation and Parameter Description...................................................................
Peaking Filter at fs/4 ....................................................................................................
Vertical Scaler Block Diagram .........................................................................................
Horizontal Scaler Block Diagram ......................................................................................
Polyphase Filtering Example ..........................................................................................
Non-linear Scaling Example ...........................................................................................
SRAM Layout for 7tap Coefficient ....................................................................................
SRAM Layout for 5tap Coefficient ....................................................................................
VPI Control I/F Coef Data Format (7tap) .............................................................................
VPI Control I/F Coef Data Format (5tap) .............................................................................
VPI Control I/F Coef Data Format (3tap) .............................................................................
VPI Control I/F Memory Map (Write) .................................................................................
VPI Control I/F Memory Map (Read) .................................................................................
Inbound Data Transfer Descriptor Format ...........................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Figures
3092
3092
3093
3095
3096
3097
3097
3098
3103
3103
3104
3104
3104
3105
3105
3106
3106
3106
3107
3107
3109
3110
3110
3110
3110
3112
3112
3113
3113
3115
3115
3116
3116
3117
3118
3119
3120
3121
3124
3124
3125
3125
3125
3125
3126
3172
65
www.ti.com
8-90.
Outbound Data Transfer Descriptor Format ......................................................................... 3172
8-91.
Y 4:4:4 (Data Type 0) ................................................................................................... 3189
8-92.
Y 4:2:2 (Data Type 1) ................................................................................................... 3190
8-93.
Y 4:2:0 (Data Type 2) ................................................................................................... 3190
8-94.
C 4:4:4 (Data Type 4)................................................................................................... 3191
8-95.
C 4:2:2 (Data Type 5)................................................................................................... 3191
8-96.
C 4:2:0 (Data Type 6)................................................................................................... 3192
8-97.
YC 4:2:2 (Data Type 7) ................................................................................................. 3192
8-98.
YC 4:4:4 (Data Type 8) ................................................................................................. 3193
8-99.
CY 4:2:2 (Data Type 23h) .............................................................................................. 3193
8-100. RGB16-565 (Data Type 0) ............................................................................................. 3194
8-101. ARGB-1555 (Data Type 1) ............................................................................................. 3195
8-102. ARGB-4444 (Data Type 2) ............................................................................................. 3195
8-103. RGBA-5551 (Data Type 3) ............................................................................................. 3196
8-104. RGBA-4444 (Data Type 4) ............................................................................................. 3196
8-105. ARGB24-6666 (Data Type 5) .......................................................................................... 3197
8-106. RGB24-888 (Data Type 6) ............................................................................................. 3197
8-107. ARGB32-8888 (Data Type 7) .......................................................................................... 3198
8-108. RGBA24-6666 (Data Type 8) .......................................................................................... 3198
8-109. RGBA32-8888 (Data Type 9) .......................................................................................... 3199
66
9-1.
Display Subsystem Overview .......................................................................................... 3468
9-2.
Display Subsystem Environment ...................................................................................... 3469
9-3.
Display Subsystem Integration ........................................................................................ 3471
9-4.
Display Subsystem Clock Tree ........................................................................................ 3472
9-5.
DISPC Overview
9-6.
DISPC VP1 Output Interfaces ......................................................................................... 3481
9-7.
DISPC VP1 Pixel Data Color-12 Active Matrix ...................................................................... 3482
9-8.
DISPC VP1 Pixel Data Color-16 Active Matrix ...................................................................... 3483
9-9.
DISPC VP1 Pixel Data Color-18 Active Matrix ...................................................................... 3483
9-10.
DISPC VP1 Pixel Data Color-24 Active Matrix ...................................................................... 3484
9-11.
DISPC Active Matrix Timing Diagram of Configuration 1 (Start of Frame) ...................................... 3485
9-12.
DISPC Active Matrix Timing Diagram of Configuration 1 (Between Lines) ...................................... 3486
9-13.
DISPC Active Matrix Timing Diagram of Configuration 1 (Between Frames) ................................... 3486
9-14.
DISPC Active Matrix Timing Diagram of Configuration 1 (End of Frame) ....................................... 3486
9-15.
DISPC Active Matrix Timing Diagram of Configuration 2 (Start of Frame) ...................................... 3487
9-16.
DISPC Active Matrix Timing Diagram of Configuration 2 (Between Lines) ...................................... 3487
9-17.
DISPC Active Matrix Timing Diagram of Configuration 2 (Between Frames) ................................... 3487
9-18.
DISPC Active Matrix Timing Diagram of Configuration 2 (End of Frame) ....................................... 3487
9-19.
DISPC Active Matrix Timing Diagram of Configuration 3 (Start of Frame) ...................................... 3488
9-20.
DISPC Active Matrix Timing Diagram of Configuration 3 (Between Lines) ...................................... 3488
9-21.
DISPC Active Matrix Timing Diagram of Configuration 3 (Between Frames) ................................... 3488
9-22.
DISPC Active Matrix Timing Diagram of Configuration 3 (End of Frame) ....................................... 3488
9-23.
DISPC Integration ....................................................................................................... 3489
9-24.
DISPC Architecture Overview ......................................................................................... 3491
9-25.
DISPC YUV4:2:2 Predecimation ...................................................................................... 3501
9-26.
DISPC Graphics Pipeline............................................................................................... 3506
9-27.
DISPC GFX CLUT Data Memory Organization ..................................................................... 3507
9-28.
DISPC Video Pipeline Configuration.................................................................................. 3508
9-29.
DISPC VID CLUT Data Memory Organization ...................................................................... 3509
List of Figures
........................................................................................................
3478
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
9-30.
DISPC VID YCbCr to RGB Registers (FULLRANGE = 0), 12-Bit Outputs ...................................... 3510
9-31.
DISPC VID YCbCr to RGB Registers (FULLRANGE = 1), 12-Bit Outputs ...................................... 3510
9-32.
DISPC VID YUV4:2:0 to RGB36 Using Scaler Unit for Resampling Chrominance............................. 3511
9-33.
DISPC VID YUV4:2:2 to RGB36 Using Scaler Unit for Resampling Chrominance............................. 3511
9-34.
DISPC Video Upsampling .............................................................................................. 3512
9-35.
DISPC VID Macro-Architecture of the Horizontal Scaling for A, R, G, B, and Y Components (5-tap
Restriction) ............................................................................................................... 3514
9-36.
DISPC VID Macro-Architecture of the Vertical Scaling for A, R, G, B, and Y Components (5 and 3 taps) . 3514
9-37.
DISPC VID Macro-Architecture of the Horizontal Scaling for Cr and Cb Components (5-tap Restriction) .. 3515
9-38.
DISPC VID Macro-Architecture of the Vertical Scaling for Cr and Cb Components (5 and 3 taps) .......... 3515
9-39.
DISPC Vertical Upsampling and Downsampling Algorithm ........................................................ 3518
9-40.
DISPC Horizontal Up/Downsampling Algorithm ..................................................................... 3519
9-41.
DISPC Write-Back Pipeline ............................................................................................ 3520
9-42.
DISPC WB RGB to YCbCr (FULLRANGE = 0) ..................................................................... 3521
9-43.
DISPC WB RGB to YCbCr (FULLRANGE = 1) ..................................................................... 3521
9-44.
DISPC WB Macro-Architecture of the Vertical Scaling for A, R, G, B, and Y Components ................... 3521
9-45.
DISPC WB Macro-Architecture of the Horizontal Scaling for A, R, G, B, and Y Components ................ 3522
9-46.
DISPC WB Macro-Architecture of the Vertical Scaling for Cr and Cb Components
9-47.
9-48.
9-49.
9-50.
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
9-72.
9-73.
9-74.
9-75.
9-76.
9-77.
...........................
DISPC WB Macro-Architecture of the Horizontal Scaling for Cr and Cb Components ........................
DISPC Overlay Example of Priority Rule: From Lower to Higher VID1, VID2, GFX ...........................
DISPC Overlay Alpha Blending Architecture With Premultiplied Alpha Support ................................
DISPC Overlay Source Transparency Color Key Example ........................................................
DISPC Overlay Destination Transparency Color Key Example ...................................................
DISPC VP1 Output Architecture.......................................................................................
DISPC Data Memory Organization for Gamma Mode in VP1 Output ............................................
DISPC VP1 CPR Matrix ................................................................................................
DISPC VP1 CPR Macro-Architecture.................................................................................
DISPC VP1 CSC RGB to YUV Registers (FullRange=0) ..........................................................
DISPC VP1 CSC RGB to YUV Registers (FullRange=1) ..........................................................
DISPC VP1 Data Mapping in BT.656 Mode .........................................................................
DISPC VP1 Data Mapping in BT.1120 Mode .......................................................................
DISPC BT Mode Bit-Assignment for the Fourth Byte of EAV/SAV Codes ......................................
DISPC VP1 TDM 8-Bit Interface Settings ............................................................................
DISPC VP1 TDM 9-Bit Interface Settings ............................................................................
DISPC VP1 TDM 12-Bit Interface Settings ..........................................................................
DISPC VP1 TDM 16-Bit Interface Settings ..........................................................................
DISPC VP1 Timing Values (Display Screen) ........................................................................
DISPC Example TV Timing Formats .................................................................................
DISPC Illustration of 3D Interleaving .................................................................................
DISPC Illustration of a Non-zero Position of 3D Window ..........................................................
Video Encoder Overview ...............................................................................................
Video Encoder Environment, Normal Mode DC-Coupling .........................................................
Video Encoder Environment, Normal Mode AC-Coupling .........................................................
Video Encoder Environment, Bypass Mode .........................................................................
Video Encoder Integration .............................................................................................
Video Encoder Architecture Overview ................................................................................
Video Encoder Closed Captioning Timing ...........................................................................
Video Encoder WSS Timing ...........................................................................................
Video SD_DAC Architecture ...........................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Figures
3522
3522
3528
3529
3532
3533
3533
3534
3534
3535
3535
3536
3536
3536
3537
3539
3540
3541
3542
3544
3544
3546
3547
3647
3649
3650
3650
3652
3654
3657
3659
3660
67
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9-78.
Video SD_DAC DC-Coupling TV Detect Waveforms for TV Connected and Disconnected .................. 3661
9-79.
Video SD_DAC AC-Coupling TV Detect Waveforms for TV Connected and Disconnected .................. 3662
9-80.
Video SD_DAC Signal Waveform Proposal for TV Detection/Disconnection in DC-Coupling Mode
9-81.
Video SD_DAC Signal Waveform Proposal for TV Detection/Disconnection in AC-Coupling Mode......... 3663
9-82.
Video SD_DAC Test Mode in Composite Video Mode ............................................................. 3664
10-1.
Interconnect Overview .................................................................................................. 3701
10-2.
L3_MAIN Interconnect Overview ...................................................................................... 3702
10-3.
Connectivity Matrix ...................................................................................................... 3708
10-4.
Bandwidth Regulator Pressure Settings.............................................................................. 3710
10-5.
Flag Muxing Scheme ................................................................................................... 3712
10-6.
L3 Interconnect Region Overlay and Priority Level Overview ..................................................... 3720
10-7.
L3_MAIN Global Error-Routing Scheme ............................................................................. 3724
10-8.
Typical Error Analysis Sequence ...................................................................................... 3727
10-9.
L4 Interconnect Overview .............................................................................................. 3844
........
3662
10-10. L4 Initiator-Target Connectivity ........................................................................................ 3850
10-11. L4 Segmentation ........................................................................................................ 3853
10-12. L4 Error Reporting
......................................................................................................
3861
10-13. Protection Violation Out-of-Band Error Reporting ................................................................... 3862
10-14. Typical Error Analysis Sequence ...................................................................................... 3864
11-1.
Memory Subsystem Functional Diagram ............................................................................. 3914
11-2.
EMIF Controller Overview .............................................................................................. 3918
11-3.
EMIF DDR2/DDR3/DDR3L Configuration Without ECC ........................................................... 3920
11-4.
EMIF DDR2/DDR3/DDR3L Configuration With ECC ............................................................... 3921
11-5.
EMIF LPDDR2 Configuration Without ECC.......................................................................... 3922
11-6.
EMIF LPDDR2 Configuration With ECC ............................................................................. 3923
11-7.
EMIF Module Integration ............................................................................................... 3926
11-8.
EMIF Block Diagram .................................................................................................... 3928
11-9.
FIFO Block Diagram .................................................................................................... 3929
11-10. Example for Using the CKE Tri-state Functionality ................................................................. 3951
11-11. GPMC Overview ......................................................................................................... 4068
11-12. GPMC to 16-Bit Address/Data-Multiplexed Memory................................................................ 4069
11-13. GPMC to 16-Bit Nonmultiplexed Memory ............................................................................ 4069
11-14. GPMC to 8-Bit Nonmultiplexed Memory ............................................................................. 4070
11-15. GPMC to 8-Bit NAND Device .......................................................................................... 4070
11-16. GPMC Integration ....................................................................................................... 4073
11-17. GPMC Block Diagram .................................................................................................. 4077
11-18. Chip-Select Address Mapping and Decoding Mask ................................................................ 4083
11-19. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ...................... 4086
11-20. Wait Behavior During a Synchronous Read Burst Access
........................................................
4088
11-21. Read-to-Read for an Address-Data Multiplexed Device, on Different Chip-Select, Without Bus
Turnaround (nCS Attached to a Fast Device) ....................................................................... 4090
11-22. Read- to-Read/Write for an Address-Data Multiplexed Device, on Different Chip-Select, With Bus
Turnaround ............................................................................................................... 4090
11-23. Read-to-Read/Write for a Address-Data or AAD-Multiplexed Device, on Same Chip-Select, With Bus
Turnaround ............................................................................................................... 4091
11-24. Asynchronous Single Read on an Address/Data-Multiplexed Device ............................................ 4100
11-25. Two Asynchronous Single-Read Accesses on an Address/Data-Multiplexed Device (32-Bit Read Split
Into 2 x 16-Bit Read) .................................................................................................... 4101
11-26. Asynchronous Single-Write on an Address/Data-Multiplexed Device ............................................ 4102
11-27. Asynchronous Single Read on an AAD-Multiplexed Device....................................................... 4104
68
List of Figures
SPRUIC6B – January 2017 – Revised October 2017
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11-28. Asynchronous Single Write on an AAD-Multiplexed Device ....................................................... 4105
11-29. Synchronous Single Read (GPMCFCLKDIVIDER = 0) ............................................................ 4107
11-30. Synchronous Single Read (GPMCFCLKDIVIDER = 1) ............................................................ 4108
11-31. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0).................................................. 4110
11-32. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1).................................................. 4111
11-33. Synchronous Single Write on an Address/Data-Multiplexed Device ............................................. 4112
11-34. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode .................................. 4113
11-35. Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode ....................... 4114
11-36. Asynchronous Single Read on an Address/Data-Nonmultiplexed Device ....................................... 4116
11-37. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device ....................................... 4117
11-38. Asynchronous Multiple (Page Mode) Read .......................................................................... 4118
11-39. NAND Command Latch Cycle ......................................................................................... 4123
11-40. NAND Address Latch Cycle
...........................................................................................
4124
11-41. NAND Data Read Cycle ................................................................................................ 4125
11-42. NAND Data Write Cycle ................................................................................................ 4125
......................................................................
Hamming Code Accumulation Algorithm (2/2) ......................................................................
ECC Computation for a 256-Byte Data Stream (Read or Write) ..................................................
ECC Computation for a 512-Byte Data Stream (Read or Write) ..................................................
128 Word16 ECC Computation .......................................................................................
256 Word16 ECC Computation .......................................................................................
Manual Mode Sequence and Mapping ...............................................................................
NAND Page Mapping and ECC: Per-Sector Schemes.............................................................
NAND Page Mapping and ECC: Pooled Spare Schemes .........................................................
NAND Page Mapping and ECC: Per-Sector Schemes, With Separate ECC ...................................
NAND Read Cycle Optimization Timing Description ...............................................................
Programming Model Top-Level Diagram .............................................................................
NOR Interfacing Timing Parameters Diagram .......................................................................
NAND Command Latch Cycle Timing Simplified Example ........................................................
Synchronous NOR Single Read Simplified Example ...............................................................
Asynchronous NOR Single Write Simplified Example ..............................................................
GPMC Connection to an External NOR Flash Memory ............................................................
Synchronous Burst Read Access (Timing Parameters in Clock Cycles) ........................................
Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ......................................
Asynchronous Single Write Access (Timing Parameters in Clock Cycles) ......................................
ELM Overview ...........................................................................................................
ELM Integration ..........................................................................................................
OCMC_RAM Overview .................................................................................................
OCMC_RAM Integration ...............................................................................................
OCMC Block Diagram ..................................................................................................
VBUF to CBUF Address Mapping ....................................................................................
EDMA Module Overview ...............................................................................................
Example of External DMA Requests Use ............................................................................
EDMA Controller Integration ...........................................................................................
EDMA Controller Block Diagram ......................................................................................
EDMA Channel Controller Block Diagram ...........................................................................
TPTC Block Diagram ...................................................................................................
Definition of ACNT, BCNT, and CCNT ..............................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)....................................................
11-43. Hamming Code Accumulation Algorithm (1/2)
11-44.
11-45.
11-46.
11-47.
11-48.
11-49.
11-50.
11-51.
11-52.
11-53.
11-54.
11-55.
11-56.
11-57.
11-58.
11-59.
11-60.
11-61.
11-62.
11-63.
11-64.
11-65.
11-66.
11-67.
11-68.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
SPRUIC6B – January 2017 – Revised October 2017
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List of Figures
4130
4131
4131
4132
4133
4133
4138
4142
4143
4144
4151
4153
4158
4162
4168
4170
4172
4174
4175
4176
4214
4215
4243
4244
4245
4254
4295
4298
4300
4311
4312
4313
4315
4315
69
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12-9.
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................. 4316
12-10. PaRAM Set ............................................................................................................... 4318
12-11. Linked Transfer .......................................................................................................... 4326
12-12. Link-to-Self Transfer .................................................................................................... 4327
12-13. DMA Channel and QDMA Channel to PaRAM Mapping........................................................... 4333
.................................................................................
Shadow Region Registers .............................................................................................
Interrupt Diagram ........................................................................................................
Error Interrupt Operation ...............................................................................................
PaRAM Set Content for Proxy Memory Protection Example ......................................................
Channel Options Parameter (OPT) Example ........................................................................
Proxy Memory Protection Example ...................................................................................
EDMA Prioritization .....................................................................................................
Block Move Example ...................................................................................................
Block Move Example PaRAM Configuration.........................................................................
Subframe Extraction Transfer .........................................................................................
Subframe Extraction Example PaRAM Configuration ..............................................................
Data Sorting Example ..................................................................................................
Data Sorting Example PaRAM Configuration .......................................................................
Servicing Incoming McASP Data Example ..........................................................................
Servicing Incoming McASP Data Example PaRAM Configuration ...............................................
Servicing Peripheral Burst Example ..................................................................................
Servicing Peripheral Burst Example PaRAM Configuration .......................................................
Servicing Continuous McASP Data Example ........................................................................
Servicing Continuous McASP Data Example PaRAM Configuration .............................................
Servicing Continuous McASP Data Example Reload PaRAM Configuration ...................................
Ping-Pong Buffering for McASP Data Example ....................................................................
Ping-Pong Buffering for McASP Example PaRAM Configuration.................................................
Ping-Pong Buffering for McASP Example Pong PaRAM Configuration .........................................
Ping-Pong Buffering for McASP Example Ping PaRAM Configuration ..........................................
Intermediate Transfer Completion Chaining Example ..............................................................
Single Large Block Transfer Example ................................................................................
Smaller Packet Data Transfers Example.............................................................................
Interrupt Controllers in the Device ....................................................................................
Interrupts From External Devices .....................................................................................
Control Module Overview Block Diagram ............................................................................
Control Module Environment ..........................................................................................
Control Module Integration .............................................................................................
Pad Configuration Register Bits .......................................................................................
Thermal Management Functional Block Diagram ...................................................................
Behavior Of The Thermal Alert Logic .................................................................................
Behavior Of The Thermal Shutdown Logic ..........................................................................
IRQ_CROSSBAR Module Functional Diagram .....................................................................
DMA_CROSSBAR Module Functional Diagram ....................................................................
Vref-Generation Cells and Their Controls ............................................................................
AVS Class 0 Procedure ................................................................................................
Combined Firewall Error Interrupt .....................................................................................
Hardware Observability Logic .........................................................................................
MAILBOX1 Integration ..................................................................................................
12-14. QDMA Channel to PaRAM Mapping
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
13-1.
13-2.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
15-1.
70
List of Figures
4334
4335
4341
4345
4350
4350
4351
4357
4360
4361
4362
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4374
4375
4375
4377
4378
4378
4554
4555
4585
4586
4587
4590
4592
4594
4595
4602
4606
4612
4614
4615
4616
4998
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
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15-2.
MAILBOX2 Integration .................................................................................................. 4998
15-3.
EVE_MBOX Integration
15-4.
Mailbox Block Diagram ................................................................................................. 5002
15-5.
Example of Communication ............................................................................................ 5006
16-1.
System MMU1 Overview ............................................................................................... 5035
16-2.
System MMU1 Integration
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
17-1.
17-2.
17-3.
17-4.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
................................................................................................
.............................................................................................
MMU Block Diagram ....................................................................................................
Translation Process .....................................................................................................
Translation Hierarchy ...................................................................................................
First-level Descriptor Address Calculation ...........................................................................
Detailed First-Level Descriptor Address Calculation................................................................
Section Translation Summary .........................................................................................
Supersection Translation Summary...................................................................................
Two-Level Translation ..................................................................................................
Small Page Translation Summary ....................................................................................
Large Page Translation Summary ....................................................................................
TLB Entry Lock Mechanism ............................................................................................
TLB Entry Structure .....................................................................................................
MMU Global Initialization ...............................................................................................
Spinlock Overview.......................................................................................................
Spinlock Integration .....................................................................................................
Lock Register State Diagram ..........................................................................................
Take and Release Spinlock ............................................................................................
Timers Overview ........................................................................................................
GP Timers Overview ....................................................................................................
GP Timers External System Interface ................................................................................
GP Timer Integration ....................................................................................................
Block Diagram of TIMER2 Through TIMER8 ........................................................................
Block Diagram of TIMER1 .............................................................................................
Wake-Up Request Generation.........................................................................................
Wake-Up Request Generation.........................................................................................
TCRR Timing Value .....................................................................................................
Block Diagram of the 1-ms Tick Module .............................................................................
Capture Wave Example for TCLR[13] CAPT_MODE = 0..........................................................
Capture Wave Example for TCLR[13] CAPT_MODE = 1..........................................................
Timing Diagram of PWM With TCLR[7] SCPWM Bit = 0 ..........................................................
Timing Diagram of PWM With TCLR[7] SCPWM Bit = 1 ..........................................................
32-kHz Synchronized Timer Block Diagram .........................................................................
Reset Resynchronization Timing Diagram ...........................................................................
CONTER_32K Block Diagram .........................................................................................
I2C Controllers ...........................................................................................................
I2C and Typical Connections to I2C Devices .........................................................................
I2C Interface Signals ....................................................................................................
I2C Data Transfer ........................................................................................................
I2C Bit Transfer on the I2C Bus ........................................................................................
I2C S and P Condition Events .........................................................................................
I2C Data Transfer Formats in F/S Mode ..............................................................................
I2C Arbitration Between Master Transmitters ........................................................................
I2C Clock Generators Synchronization ...............................................................................
SPRUIC6B – January 2017 – Revised October 2017
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List of Figures
4999
5036
5038
5039
5040
5040
5041
5042
5043
5044
5045
5046
5047
5048
5050
5077
5078
5080
5082
5089
5090
5092
5093
5097
5098
5100
5101
5102
5103
5105
5106
5107
5108
5136
5137
5138
5144
5146
5146
5147
5148
5148
5149
5150
5151
71
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19-10. I C Integration ............................................................................................................ 5152
2
19-11. I2C Block Diagram ....................................................................................................... 5154
19-12. I2C Receive FIFO Interrupt Request Generation .................................................................... 5160
19-13. I2C Transmit FIFO Interrupt Request Generation ................................................................... 5161
19-14. I2C Receive FIFO DMA Request Generation ........................................................................ 5162
19-15. I2C Transmit FIFO Request Generation (High Threshold) ......................................................... 5162
19-16. I2C Transmit FIFO Request Generation (Low Threshold) .......................................................... 5163
19-17. I2C Setup Procedure .................................................................................................... 5169
19-18. I2C Master Transmitter Mode, Polling Method, in F/S Modes ..................................................... 5170
19-19. I2C Master Receiver Mode, Polling Method, in F/S Modes ........................................................ 5172
19-20. I2C Master Transmitter Mode, Interrupt Method, in F/S Modes ................................................... 5173
19-21. HS I2C Master Receiver Mode, Interrupt Method, in F/S Modes .................................................. 5175
19-22. I2C Master Transmitter Mode, DMA Method in F/S Modes ........................................................ 5177
19-23. I2C Master Receiver Mode, DMA Method in F/S Modes ........................................................... 5179
19-24. I2C Slave Transmitter/Receiver Mode, Polling ....................................................................... 5180
19-25. I2C Slave Transmitter/Receiver Mode, Interrupt ..................................................................... 5181
19-26. UART Overview
.........................................................................................................
5213
19-27. UART Mode Bus System Overview................................................................................... 5215
19-28. UART Frame Data Format ............................................................................................. 5216
19-29. UART Integration ........................................................................................................ 5217
19-30. UART Functional Block Diagram ...................................................................................... 5220
19-31. FIFO Management Registers .......................................................................................... 5223
19-32. RX FIFO Interrupt Request Generation .............................................................................. 5225
..............................................................................
Receive FIFO DMA Request Generation (32 Characters) .........................................................
Transmit FIFO DMA Request Generation (56 Spaces) ............................................................
Transmit FIFO DMA Request Generation (8 Spaces)..............................................................
Transmit FIFO DMA Request Generation (1 Space) ...............................................................
19-33. TX FIFO Interrupt Request Generation
19-34.
19-35.
19-36.
19-37.
5226
5228
5229
5230
5230
19-38. Transmit FIFO DMA Request Generation Using Direct TX DMA Threshold Programming. (Threshold = 3;
Spaces = 8) .............................................................................................................. 5231
19-39. DMA Transmission ...................................................................................................... 5231
19-40. DMA Reception .......................................................................................................... 5232
19-41. Baud Rate Generation .................................................................................................. 5235
5275
19-43. McSPI Interface Signals in Master Mode
5276
19-44.
5277
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
72
.............................................................................................
............................................................................
McSPI Interface Signals in Slave Mode ..............................................................................
Phase and Polarity Combinations .....................................................................................
Full-Duplex Transfer Format With PHA = 0 ..........................................................................
Extended SPI Transfer With a Start-Bit (SBE = 1)..................................................................
McSPI Master Mode (Full Duplex) ....................................................................................
McSPI Master Single Mode (Receive Only) .........................................................................
McSPI Slave Mode (Full Duplex)......................................................................................
McSPI Slave Single Mode (Transmit Only) ..........................................................................
McSPI Integration .......................................................................................................
McSPI Block Diagram ..................................................................................................
SPI Full-Duplex Transmission (Example) ............................................................................
Continuous Transfers With SPIEN[x] Maintained Active (Single-Data-Pin Interface Mode) ..................
Continuous Transfers With SPIEN[x] Maintained Active (Dual-Data-Pin Interface Mode) ....................
CS (SPIEN) Timing Controls...........................................................................................
19-42. Multichannel SPI Modules
List of Figures
5279
5280
5281
5281
5282
5282
5283
5284
5288
5290
5292
5292
5293
SPRUIC6B – January 2017 – Revised October 2017
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.......................
19-59. SPI Half-Duplex Transmission (Transmit-Only Slave)..............................................................
19-60. SPI Half-Duplex Transmission (Receive-Only Slave) ..............................................................
19-61. Buffer Used in Transmit Direction Only ..............................................................................
19-62. Buffer Used in Receive Direction Only ...............................................................................
19-63. Buffer Used for Transmit and Receive Directions...................................................................
19-64. Buffer Almost Full Level (AFL).........................................................................................
19-65. Buffer Almost Empty Level (AEL) .....................................................................................
19-66. QSPI Overview ..........................................................................................................
19-67. QSPI Connected to an External Quad-SPI Flash Memory ........................................................
19-68. QSPI Integration .........................................................................................................
19-69. QSPI Block Diagram ....................................................................................................
19-70. SPI_CLKGEN Block ....................................................................................................
19-71. SPI Clock Modes ........................................................................................................
19-72. Logical Representation of the QSPI Interrupt Generation Scheme...............................................
19-73. McASP Modules Overview .............................................................................................
19-74. McASP Environment ....................................................................................................
19-75. Definition of Bit, Word, and Slot .......................................................................................
19-76. Bit Order and Word Alignment Within a Slot Examples ............................................................
19-77. Definition of Frame and Frame-Sync Width .........................................................................
19-78. TDM Format - 6 channel example ...................................................................................
19-79. I2S Format Overview ...................................................................................................
19-80. Biphase-Mark Code .....................................................................................................
19-81. S/PDIF Subframe Format ..............................................................................................
19-82. S/PDIF Frame Format ..................................................................................................
19-83. McASP Integration ......................................................................................................
19-84. McASP Module Block Diagram ........................................................................................
19-85. Transmit Clock Generator Block Diagram ...........................................................................
19-86. Receive Clock Generator Block Diagram ............................................................................
19-87. Frame Sync Generator Block Diagram ...............................................................................
19-88. Individual Serializer and Connections Within McASP ..............................................................
19-89. Transmit Format Unit ...................................................................................................
19-90. Receive Format Unit ....................................................................................................
19-91. Burst Frame Sync Mode................................................................................................
19-92. Transmit DMA Event (AXEVT) Generation in TDM Time Slots ...................................................
19-93. Service Time Upon Transmit DMA Event (AXEVT) ................................................................
19-94. CPU Service Time Upon Receive Event (AREVT) .................................................................
19-95. DMA Transmit and Receive Event in an Audio Example – One Event ..........................................
19-96. McASP Audio FIFO (AFIFO) Block Diagram ........................................................................
19-97. McASP Serializers Operation in Loopback Mode ...................................................................
19-98. Transmit Clock Failure Detection Circuit Block Diagram ...........................................................
19-99. Receive Clock Failure Detection Circuit Block Diagram ...........................................................
19-100. McASP DIT- /TDM- Transmission Polling Method ................................................................
19-101. Subsequence – DIT-/TDM- Transmission Startup Procedure ...................................................
19-102. McASP Polling Reception Method ...................................................................................
19-103. Subsequence – TDM - Reception Startup Procedure.............................................................
19-104. McASP Transmit Interrupt Events Servicing .......................................................................
19-105. McASP Receive Interrupt Events Servicing ........................................................................
19-106. McASP Transmit Error Handling .....................................................................................
19-58. Example of McSPI Slave With One Master and Multiple Slave Devices on Channel 0
SPRUIC6B – January 2017 – Revised October 2017
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List of Figures
5296
5298
5299
5300
5300
5300
5301
5302
5339
5340
5342
5343
5347
5348
5349
5370
5372
5376
5377
5378
5379
5380
5381
5382
5382
5384
5388
5390
5392
5393
5395
5397
5400
5403
5405
5410
5411
5414
5415
5420
5424
5425
5437
5439
5442
5444
5447
5448
5449
73
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19-107. McASP Receive Error Handling...................................................................................... 5450
19-108. DCAN Overview ........................................................................................................ 5509
19-109. DCAN Typical Application
............................................................................................
5511
19-110. DCAN Integration ...................................................................................................... 5513
19-111. DCAN Block Diagram ................................................................................................. 5515
19-112. Error and Status Change Interrupts ................................................................................. 5517
19-113. Message Objects Interrupts .......................................................................................... 5518
19-114. Local Power-Down Mode Flow Diagram ............................................................................ 5519
19-115. Software Handling of a FIFO Buffer (Interrupt Driven) ............................................................ 5528
19-116. Bit Timing ............................................................................................................... 5529
19-117. The Propagation Time Segment ..................................................................................... 5530
19-118. Synchronization on Late and Early Edges .......................................................................... 5532
19-119. Filtering of Short Dominant Spikes .................................................................................. 5533
19-120. Structure of the CAN Core’s CAN Protocol Controller ............................................................ 5534
19-121. Data Transfer Between IF1/IF2 Registers and Message RAM .................................................. 5537
19-122. CAN Module General Initialization Flow ............................................................................ 5545
19-123. CAN Bit-Timing Configuration ........................................................................................ 5546
19-124. CAN Core in Silent Mode ............................................................................................. 5549
19-125. CAN Core in Loopback Mode ........................................................................................ 5549
19-126. CAN Core in External Loopback Mode
.............................................................................
5550
19-127. CAN Core in Loop Back Combined With Silent Mode ............................................................ 5551
19-128. MCAN Module Overview .............................................................................................. 5608
19-129. MCAN Typical Application ............................................................................................ 5610
19-130. MCAN Integration ...................................................................................................... 5612
19-131. MCAN Block Diagram ................................................................................................. 5613
19-132. CAN Bit Timing ......................................................................................................... 5617
19-133. Transmitter Delay Measurement ..................................................................................... 5618
19-134. Connection of Signals in Bus Monitoring Mode .................................................................... 5620
19-135. Internal Loop Back Mode ............................................................................................. 5622
19-136. External Timestamp Counter Interrupt .............................................................................. 5624
19-137. Standard Message ID Filter Path .................................................................................... 5629
19-138. Extended Message ID Filter Path.................................................................................... 5630
19-139. Rx FIFO Status ......................................................................................................... 5631
19-140. Rx FIFO Overflow Handling .......................................................................................... 5632
19-141. Mixed Dedicated Tx Buffers /Tx FIFO (example) .................................................................. 5635
19-142. Mixed Dedicated Tx Buffers /Tx Queue (example) ................................................................ 5636
19-143. Message RAM Configuration ......................................................................................... 5638
19-144. Rx Buffer/Rx FIFO Element Structure ............................................................................... 5638
19-145. Tx Buffer Element Structure .......................................................................................... 5640
19-146. Tx Event FIFO Element Structure ................................................................................... 5642
19-147. Standard Message ID Filter Element Structure .................................................................... 5643
5645
19-149. GMAC_SW Overview
5723
19-150.
5726
19-151.
19-152.
19-153.
19-154.
19-155.
74
...................................................................
.................................................................................................
RGMII Interface Typical Application .................................................................................
GMAC_SW Integration ................................................................................................
GMAC_SW Top Level Block Diagram ..............................................................................
CPSW_3G Block Diagram ............................................................................................
The Network Static with AVB .........................................................................................
AVB Network & PTP Clock Entities .................................................................................
19-148. Extended Message ID Filter Element Structure
List of Figures
5730
5732
5739
5750
5752
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
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19-156. IEEE 1722 Packets .................................................................................................... 5752
19-157. Cross Time Stamping and Presentation Timestamps............................................................. 5753
19-158. AV Stream Queuing/Policing ......................................................................................... 5755
19-159. SPF Block Diagram .................................................................................................... 5770
19-160. Packet Octets as Stored in the Packet Buffer...................................................................... 5774
19-161. CPTS Block Diagram .................................................................................................. 5786
19-162. Event FIFO Misalignment Condition ................................................................................. 5788
19-163. HW1/4_TSP_PUSH Connection ..................................................................................... 5789
19-164. Partial Ethernet-II Frames Showing Register Mapping of EtherTypes for a Simple Frame (1), a Single
1Q Tag Added (2), and Two 1Q Tags Added (3) ................................................................... 5790
19-165. TX Queue Head Descriptor ........................................................................................... 5800
19-166. RX Queue Head Descriptor
..........................................................................................
5802
20-1.
SDIO Overview .......................................................................................................... 5984
20-2.
SDIO Controller Environment .......................................................................................... 5986
20-3.
Multiple Block Read Operation ........................................................................................ 5987
20-4.
Multiple Block Write Operation With Card Busy Signal ............................................................ 5987
20-5.
Command Token Format ............................................................................................... 5988
20-6.
Response Token Format (R1, R3, R4, R5, R6, R7) ................................................................ 5988
20-7.
Response Token Format (R2) ......................................................................................... 5988
20-8.
Data Token Format for 1-Bit Transfers ............................................................................... 5989
20-9.
Data Token Format for 4-Bit Transfers ............................................................................... 5989
20-10. SDIO Integration ......................................................................................................... 5990
20-11. SDIO Diagram ........................................................................................................... 5993
20-12. DMA Receive Mode ..................................................................................................... 6002
20-13. DMA Transmit Mode .................................................................................................... 6003
20-14. Buffer Management for a Write ........................................................................................ 6005
20-15. Buffer Management for a Read
.......................................................................................
6006
20-16. Busy Time-Out for R1b, R5b Response Type ....................................................................... 6009
20-17. Busy Time-Out After Write CRC Status .............................................................................. 6009
20-18. Write CRC Status Time-Out ........................................................................................... 6010
20-19. Read Data Time-Out .................................................................................................... 6010
20-20. Output Driven on Falling Edge
........................................................................................
6012
20-21. Output Driven on Rising Edge ......................................................................................... 6012
20-22. SDIO Controller Software Reset Flow ................................................................................ 6015
...................................................................................
.......................................................
SDIO Controller Card Identification and Selection – Part 2 .......................................................
SDIO Controller Read/Write Transfer Flow in DMA Slave Mode With interrupt ................................
SDIO Controller Read/Write Transfer Flow in DMA Mode With Polling ..........................................
SDIO Controller Read/Write Transfer Flow Without DMA and With Polling .....................................
SDIO Controller Suspend Flow ........................................................................................
SDIO Controller Resume Flow ........................................................................................
SDIO Controller Command Transfer Flow With Polling ............................................................
SDIO Controller Command Transfer Flow With interrupts .........................................................
SDIO Controller Clock Frequency Change Flow ....................................................................
General-Purpose Interface Overview .................................................................................
General-Purpose Interface Typical Application......................................................................
General-Purpose Interface Used as a Keyboard Interface ........................................................
GPIO1 Through GPIO4 Signal Connections ........................................................................
20-23. SDIO Controller Bus Configuration
6016
20-24. SDIO Controller Card Identification and Selection – Part 1
6017
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
21-1.
21-2.
21-3.
21-4.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Figures
6018
6019
6021
6022
6024
6025
6026
6028
6029
6083
6085
6086
6087
75
www.ti.com
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
........................................................................................................
General-Purpose Interface Block Diagram...........................................................................
Synchronous Path .......................................................................................................
Asynchronous Path .....................................................................................................
Interrupt Request Generation ..........................................................................................
Wake-Up Request Generation.........................................................................................
Wake-Up Event Conditions ............................................................................................
GPIO_CLEARDATAOUT Register Example ........................................................................
Write in GPIO_IRQSTATUS_SET_0 Register Example ...........................................................
PWMSS Block Diagram ................................................................................................
PWMSS External Interface I/Os .......................................................................................
PWMSS Integration .....................................................................................................
Submodules and Signal Connections for the ePWM Module .....................................................
ePWM Submodules and Critical Internal Signal Interconnects ...................................................
ePWM Time-Base Submodule Block Diagram ......................................................................
ePWM Time-Base Submodule Signals and Registers .............................................................
ePWM Time-Base Frequency and Period ...........................................................................
ePWM Time-Base Up-Count Mode Waveforms ....................................................................
ePWM Time-Base Down-Count Mode Waveforms .................................................................
GPIO Integration
6088
6092
6092
6093
6094
6095
6096
6105
6106
6128
6130
6133
6143
6144
6148
6150
6152
6153
6154
22-11. ePWM Time-Base Up-Down-Count Waveforms, EPWM_TBCTL[13] PHSDIR = 0 Count Down on
Synchronization Event .................................................................................................. 6155
22-12. ePWM Time-Base Up-Down Count Waveforms, EPWM_TBCTL[13] PHSDIR = 1 Count Up on
Synchronization Event .................................................................................................. 6156
22-13. ePWM Counter-Compare Submodule ................................................................................ 6157
22-14. ePWM Counter-Compare Submodule Signals and Registers ..................................................... 6158
22-15. ePWM Counter-Compare Event Waveforms in Up-Count Mode ................................................. 6160
22-16. ePWM Counter-Compare Events in Down-Count Mode ........................................................... 6160
22-17. ePWM Counter-Compare Events in Up-Down-Count Mode, EPWM_TBCTL[13] PHSDIR = 0 Count
Down on Synchronization Event ...................................................................................... 6161
22-18. ePWM Counter-Compare Events in Up-Down-Count Mode, EPWM_TBCTL[13] PHSDIR = 1 Count Up
on Synchronization Event ............................................................................................. 6161
22-19. ePWM Action-Qualifier Submodule ................................................................................... 6162
22-20. ePWM Action-Qualifier Submodule Inputs and Outputs ........................................................... 6163
22-21. Possible Action-Qualifier Actions for EPWM1A and EPWM1B Outputs ......................................... 6164
22-22. ePWM Up-Down-Count Mode Symmetrical Waveform ............................................................ 6167
22-23. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWM1A and
EPWM1B—Active High ................................................................................................. 6168
22-24. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWM1A and
EPWM1B—Active Low ................................................................................................. 6170
22-25. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWM1A ........... 6172
22-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWM1A and
EPWM1B — Active Low ................................................................................................ 6174
22-27. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWM1A and
EPWM1B — Complementary .......................................................................................... 6176
22-28. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWM1A—Active
Low ........................................................................................................................ 6178
22-29. Dead-Band Generator Submodule .................................................................................... 6180
22-30. Configuration Options for the ePWM Dead-Band Generator Submodule ....................................... 6181
22-31. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 6183
22-32. PWM-Chopper Submodule
............................................................................................
6184
22-33. PWM-Chopper Submodule Signals and Registers ................................................................. 6185
76
List of Figures
SPRUIC6B – January 2017 – Revised October 2017
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22-34. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ............................... 6186
22-35. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 6186
22-36. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 6187
22-37. ePWM Trip-Zone Submodule .......................................................................................... 6188
.................................................................
ePWM Trip-Zone Submodule Interrupt Logic ........................................................................
ePWM Event-Trigger Submodule .....................................................................................
ePWM Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ..............................
ePWM Event-Trigger Interrupt Generator ............................................................................
HRPWM System Interface .............................................................................................
Resolution Calculations for Conventionally Generated PWM .....................................................
Operating Logic Using MEP ...........................................................................................
Required PWM Waveform for a Requested Duty = 40.5% ........................................................
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ..............................
High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ..............................
Capture and APWM Modes of Operation ............................................................................
Capture Function Diagram .............................................................................................
Event Prescale Control .................................................................................................
Prescale Function Waveforms .........................................................................................
eCAP Continuous/One-shot Block Diagram .........................................................................
eCAP Counter and Synchronization Block Diagram ................................................................
Interrupts in eCAP Module .............................................................................................
PWM Waveform Details Of eCAP APWM Mode Operation .......................................................
Optical Encoder Disk ...................................................................................................
QEP Encoder Output Signal for Forward/Reverse Movement ....................................................
Index Pulse Example ...................................................................................................
Functional Block Diagram of the eQEP Peripheral .................................................................
Functional Block Diagram of Decoder Unit ..........................................................................
Quadrature Decoder State Machine ..................................................................................
Quadrature-clock and Direction Decoding ...........................................................................
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) ...............
Position Counter Underflow/Overflow (QPOSMAX = 4) ...........................................................
Software Index Marker for 1000-line Encoder (EQEP_QEPCTL[5:4] IEL = 0b01) .............................
eQEP Strobe Event Latch (EQEP_QEPCTL[6] SEL = 0b1) .......................................................
eQEP Position-compare Unit ..........................................................................................
eQEP Position-compare Event Generation Points ..................................................................
eQEP Edge Capture Unit ..............................................................................................
Unit Position Event for Low Speed Measurement (EQEP_QCAPCTL[UPPS] = 0010) ........................
eQEP Edge Capture Unit - Timing Details ...........................................................................
eQEP Watchdog Timer .................................................................................................
eQEP Unit Time Base ..................................................................................................
EQEP Interrupt Generation ............................................................................................
ADC Environment .......................................................................................................
ADC Integration..........................................................................................................
Functional Block Diagram ..............................................................................................
Sequencer FSM .........................................................................................................
Example Timing Diagram for Sequencer.............................................................................
RTI Overview ............................................................................................................
22-38. ePWM Trip-Zone Submodule Mode Control Logic
6191
22-39.
6191
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
22-51.
22-52.
22-53.
22-54.
22-55.
22-56.
22-57.
22-58.
22-59.
22-60.
22-61.
22-62.
22-63.
22-64.
22-65.
22-66.
22-67.
22-68.
22-69.
22-70.
22-71.
22-72.
22-73.
22-74.
22-75.
23-1.
23-2.
23-3.
23-4.
23-5.
24-1.
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Figures
6192
6193
6195
6196
6197
6198
6200
6202
6202
6231
6232
6233
6233
6234
6235
6237
6238
6251
6252
6252
6254
6256
6258
6258
6260
6261
6263
6264
6265
6265
6267
6267
6268
6269
6270
6270
6293
6294
6297
6298
6299
6321
77
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24-2.
RTI Counters Block diagram ........................................................................................... 6326
24-3.
RTI Compare Block Diagram .......................................................................................... 6327
24-4.
RTI Digital Watchdog Functional Block Diagram
24-5.
RTI DWD Operation..................................................................................................... 6329
24-6.
RTI Digital Windowed Watchdog Timing Example
24-7.
RTI Digital Windowed Watchdog Operation Block Diagram ....................................................... 6330
25-1.
Initialization Process .................................................................................................... 6363
25-2.
Power Supply Connections Example ................................................................................. 6364
25-3.
Clock, Reset, and Control Environment Overview .................................................................. 6366
25-4.
ROM Code Architecture ................................................................................................ 6375
25-5.
ROM Memory Map ...................................................................................................... 6376
25-6.
RAM Memory Map ...................................................................................................... 6377
25-7.
Overall Booting Sequence ............................................................................................. 6379
25-8.
ROM Code Multiprocessor Start-Up Sequence ..................................................................... 6381
25-9.
Warm Reset Wakeup Flow............................................................................................. 6385
...................................................................
.................................................................
6328
6330
25-10. Synchronization Phase for UART ..................................................................................... 6386
25-11. Peripheral Booting Procedure ......................................................................................... 6388
25-12. Memory Booting Procedure ............................................................................................ 6390
25-13. Image Shadowing on GP Device...................................................................................... 6391
25-14. Image Formats........................................................................................................... 6394
25-15. CH Format................................................................................................................ 6395
26-1.
78
Register Descriptor Tool (RDT)
List of Figures
.......................................................................................
6405
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
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List of Tables
1-1.
Device Identification Register Fields ................................................................................... 326
1-2.
DIE_ID...................................................................................................................... 326
1-3.
DM50x Part Number Identifier
1-4.
ID_CODE .................................................................................................................. 327
1-5.
Device Identification Values ............................................................................................. 327
1-6.
PROD_ID .................................................................................................................. 327
1-7.
DEVICE_TYPE ............................................................................................................ 327
2-1.
L3_MAIN Memory Map
2-2.
L3_INSTR Memory Map ................................................................................................. 334
2-3.
L4_CFG Memory Map
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
3-29.
3-30.
..........................................................................................
..................................................................................................
...................................................................................................
L4_WKUP Memory Map .................................................................................................
L4_PER1 Memory Map ..................................................................................................
L4_PER2 Memory Map ..................................................................................................
L4_PER3 Memory Map ..................................................................................................
IPU Memory Map .........................................................................................................
DSP Memory Map ........................................................................................................
EVE Memory Map ........................................................................................................
Master Module Standby Mode Settings................................................................................
Master Module Standby Status .........................................................................................
Master Module Clock Enabling Conditions ............................................................................
Module Idle Mode Settings ..............................................................................................
Slave Module Idle Status ................................................................................................
Slave Module Clock Activity Settings ..................................................................................
Slave Module Mode Settings in PRCM ................................................................................
Slave Module Interface Clock Enabling Conditions ..................................................................
Slave Module Functional Clock Enabling Conditions ................................................................
Clock Domain Functional Clock States ................................................................................
Clock Domain Interface Clock States ..................................................................................
Clock Domain Clock States .............................................................................................
Clock Domain Clock Transition Mode Settings .......................................................................
Clock Domain Wake-Up Conditions ....................................................................................
Clock Domain Sleep Conditions ........................................................................................
Device Domain Dependencies (Table 1) ..............................................................................
Device Domain Dependencies (Table 2) ..............................................................................
States of a Logic Area in a Power Domain ............................................................................
States of a Memory Area in a Power Domain ........................................................................
Power Domain Wake-Up Conditions ...................................................................................
Power Domain Sleep Conditions .......................................................................................
Power Domain Control and Status Registers .........................................................................
External Clock Signals ...................................................................................................
External Boot Signals ....................................................................................................
External Reset Signals ...................................................................................................
Voltage Sources ..........................................................................................................
PMFW Device-Level Layout .............................................................................................
PMFW Module Power Domains ........................................................................................
PMFW Module Reset Signals ...........................................................................................
PMFW Hardware Requests .............................................................................................
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
327
332
336
338
340
341
342
343
345
346
350
351
351
352
352
353
353
354
354
356
356
357
357
360
361
363
363
368
369
370
370
371
382
382
383
383
384
386
386
387
79
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3-31.
Global Reset Sources .................................................................................................... 390
3-32.
Local Reset Sources ..................................................................................................... 390
3-33.
Modules, Power Domains, and Reset Domains Association
3-34.
Reset Sources for the Reset Domains ................................................................................. 394
3-35.
Reset Domains Attributes................................................................................................ 400
3-36.
Internal Clock Sources
3-37.
3-38.
3-39.
3-40.
3-41.
3-42.
3-43.
3-44.
3-45.
3-46.
3-47.
3-48.
3-49.
3-50.
3-51.
3-52.
3-53.
3-54.
3-55.
3-56.
3-57.
3-58.
3-59.
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
3-67.
3-68.
3-69.
3-70.
3-71.
3-72.
3-73.
3-74.
3-75.
3-76.
3-77.
3-78.
3-79.
80
.......................................................
..................................................................................................
PRM Clock Division and Muxing Control ..............................................................................
CM_CORE_AON (a) Clock Division and Muxing Control ...........................................................
CM_CORE_AON (b) Clock Division and Muxing Control ...........................................................
CM_CORE_AON_CLKOUTMUX Clock Division and Muxing Control .............................................
CM_CORE_AON_TIMER Clock Division and Muxing Control .....................................................
CM_CORE_AON_MCASP Clock Division and Muxing Control ....................................................
Control Module Clock Division and Muxing Control ..................................................................
CLKOUT_M2, CLKOUTX2_M2, and CLKOUTX2_M3 Frequencies With DPLL State ..........................
CLKOUTX2_Hmn Frequencies With DPLL State ....................................................................
DPLL Power Modes ......................................................................................................
DPLL Recalibration Control Parameters ...............................................................................
DPLL Power-Down Control Parameters ...............................................................................
DPLL_PER Clock Synthesis Parameters ..............................................................................
DPLL_PER Clock Output Parameters .................................................................................
DPLL_PER Modes........................................................................................................
DPLL_PER Mode Control Parameters .................................................................................
DPLL_PER Recalibration Feature Parameters .......................................................................
DPLL_CORE Clock Synthesis Parameters ...........................................................................
DPLL_CORE Clock Output Parameters ...............................................................................
DPLL_CORE Modes .....................................................................................................
DPLL_CORE Mode Control Parameters ..............................................................................
DPLL_CORE Recalibration Feature Parameters .....................................................................
DPLL_EVE_VID_DSP Clock Synthesis Parameters .................................................................
DPLL_EVE_VID_DSP Clock Output Parameters ....................................................................
DPLL_EVE_VID_DSP Modes ...........................................................................................
DPLL_EVE_VID_DSP Mode Control Parameters ....................................................................
DPLL_EVE_VID_DSP Recalibration Feature Parameters ..........................................................
DPLL_GMAC_DSP Clock Synthesis Parameters ....................................................................
DPLL_GMAC_DSP Clock Output Parameters ........................................................................
DPLL_GMAC_DSP Modes ..............................................................................................
DPLL_GMAC_DSP Mode Control Parameters .......................................................................
DPLL_GMAC_DSP Recalibration Feature Parameters .............................................................
DPLL_DDR Clock Synthesis Parameters .............................................................................
DPLL_DDR Clock Output Parameters .................................................................................
DPLL_DDR Modes .......................................................................................................
DPLL_DDR Mode Control Parameters ................................................................................
DPLL_DDR Recalibration Feature Parameters .......................................................................
CD_WKUPAON Clock Domain Modes ................................................................................
CD_WKUPAON Control and Status Parameters .....................................................................
CD_WKUPAON Wake-Up Dependency Association Parameters..................................................
CD_WKUPAON Modules Clocks Association ........................................................................
CD_WKUPAON Modules Wake-Up Request .........................................................................
CD_WKUPAON Modules Clock-Management Modes and Control ................................................
List of Tables
391
411
412
415
418
422
424
425
428
430
430
431
433
433
434
434
435
435
435
436
436
437
437
438
439
439
439
439
439
440
440
441
441
441
442
442
442
443
443
444
444
445
445
446
446
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
3-80.
3-81.
3-82.
3-83.
3-84.
3-85.
3-86.
3-87.
3-88.
3-89.
3-90.
3-91.
3-92.
3-93.
3-94.
3-95.
3-96.
3-97.
3-98.
3-99.
3-100.
3-101.
3-102.
3-103.
3-104.
3-105.
3-106.
3-107.
3-108.
3-109.
3-110.
3-111.
3-112.
3-113.
3-114.
3-115.
3-116.
3-117.
3-118.
3-119.
3-120.
3-121.
3-122.
3-123.
3-124.
3-125.
3-126.
3-127.
3-128.
........................................
CD_DSP1 Clock Domain Modes .......................................................................................
CD_DSP1 Control and Status Parameters ............................................................................
CD_DSP1 Static Dependency Association Parameters .............................................................
CD_DSP1 Dynamic Dependency Association Parameters .........................................................
CD_DSP1 Modules Clocks Association ...............................................................................
CD_DSP1 Modules Wake-Up Request ................................................................................
CD_DSP1 Modules Clock-Management Modes and Control .......................................................
CD_DSP1 Modules Slave Clock-Management Modes and Control ...............................................
CD_DSP2 Clock Domain Modes .......................................................................................
CD_DSP2 Control and Status Parameters ............................................................................
CD_DSP2 Static Dependency Association Parameters .............................................................
CD_DSP2 Dynamic Dependency Association Parameters .........................................................
CD_DSP2 Modules Clocks Association ...............................................................................
CD_DSP2 Modules Wake-Up Request ................................................................................
CD_DSP2 Modules Clock-Management Modes and Control .......................................................
CD_DSP2 Modules Slave Clock-Management Modes and Control ...............................................
CD_CUSTEFUSE Clock Domain Modes ..............................................................................
CD_CUSTEFUSE Control and Status Parameters...................................................................
CD_CUSTEFUSE Modules Clocks Association ......................................................................
CD_CUSTEFUSE Modules Wake-Up Request .......................................................................
CD_CUSTEFUSE Modules Clock-Management Modes and Control ..............................................
CD_CUSTEFUSE Modules Slave Clock-Management Modes and Control ......................................
CD_L4PER1 Clock Domain Modes ....................................................................................
CD_L4PER1 Control and Status Parameters .........................................................................
CD_L4PER1 Dynamic Dependency Association Parameters ......................................................
CD_L4PER1 Wake-Up Dependency Association Parameters .....................................................
CD_L4PER1 Modules Clocks Association ............................................................................
CD_L4PER1 Modules Wake-Up Request .............................................................................
CD_L4PER1 Modules Clock-Management Modes and Control ....................................................
CD_L4PER1 Modules Slave Clock-Management Modes and Control ............................................
CD_L4PER2 Clock Domain Modes ....................................................................................
CD_L4PER2 Control and Status Parameters .........................................................................
CD_L4PER2 Dynamic Dependency Association Parameters ......................................................
CD_L4PER2 Wake-Up Dependency Association Parameters .....................................................
CD_L4PER2 Modules Clocks Association ............................................................................
CD_L4PER2 Modules Wake-Up Request .............................................................................
CD_L4PER2 Modules Clock-Management Modes and Control ....................................................
CD_L4PER2 Modules Slave Clock-Management Modes and Control ............................................
CD_L4PER3 Clock Domain Modes ....................................................................................
CD_L4PER3 Control and Status Parameters .........................................................................
CD_L4PER3 Dynamic Dependency Association Parameters ......................................................
CD_L4PER3 Modules Clocks Association ............................................................................
CD_L4PER3 Modules Wake-Up Request .............................................................................
CD_L4PER3 Modules Clock-Management Modes and Control ....................................................
CD_L4PER3 Modules Slave Clock-Management Modes and Control ............................................
CD_L3INIT Clock Domain Modes ......................................................................................
CD_L3INIT Control and Status Parameters ...........................................................................
CD_L3INIT Static Dependency Association Parameters ............................................................
CD_WKUPAON Modules Slave Clock-Management Modes and Control
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Tables
447
448
448
448
449
449
449
449
449
450
450
450
451
451
451
451
452
452
452
453
453
453
453
454
454
455
455
462
463
463
464
465
466
466
466
468
469
469
470
470
471
471
471
471
472
472
473
473
473
81
www.ti.com
3-129. CD_L3INIT Dynamic Dependency Association Parameters ........................................................ 473
3-130. CD_L3INIT Modules Clocks Association .............................................................................. 474
3-131. CD_L3INIT Modules Wake-Up Request ............................................................................... 474
3-132. CD_L3INIT Modules Clock-Management Modes and Control ...................................................... 474
3-133. CD_L3INIT Modules Slave Clock-Management Modes and Control .............................................. 474
475
3-135.
475
3-136.
3-137.
3-138.
3-139.
3-140.
3-141.
3-142.
3-143.
3-144.
3-145.
3-146.
3-147.
3-148.
3-149.
3-150.
3-151.
3-152.
3-153.
3-154.
3-155.
3-156.
3-157.
3-158.
3-159.
3-160.
3-161.
3-162.
3-163.
3-164.
3-165.
3-166.
3-167.
3-168.
3-169.
3-170.
3-171.
3-172.
3-173.
3-174.
3-175.
3-176.
3-177.
82
........................................................................................
CD_EMU Control and Status Parameters .............................................................................
CD_EMU Dynamic Dependency Association Parameters ..........................................................
CD_EMU Modules Clocks Association ................................................................................
CD_EMU Modules Wake-Up Request .................................................................................
CD_DSS Clock Domain Modes .........................................................................................
CD_DSS Control and Status Parameters .............................................................................
CD_DSS Static Dependency Association Parameters ..............................................................
CD_DSS Dynamic Dependency Association Parameters ...........................................................
CD_DSS Wake-Up Dependency Association Parameters ..........................................................
CD_DSS Modules Clocks Association .................................................................................
CD_DSS Modules Wake-Up Request .................................................................................
CD_DSS Modules Clock-Management Modes and Control ........................................................
CD_DSS Modules Slave Clock-Management Modes and Control .................................................
CD_L4_CFG Clock Domain Modes ....................................................................................
CD_L4_CFG Control and Status Parameters .........................................................................
CD_L4_CFG Dynamic Dependency Association Parameters ......................................................
CD_L4_CFG Modules Clocks Association ............................................................................
CD_L4_CFG Modules Wake-Up Request .............................................................................
CD_L4_CFG Modules Clock-Management Modes and Control ....................................................
CD_L4_CFG Modules Slave Clock-Management Modes and Control ............................................
CD_L3_INSTR Clock Domain Modes ..................................................................................
CD_L3_INSTR Control and Status Parameters ......................................................................
CD_L3_INSTR Modules Clocks Association ..........................................................................
CD_L3_INSTR Modules Wake-Up Request ..........................................................................
CD_L3_INSTR Modules Clock-Management Modes and Control .................................................
CD_L3_INSTR Modules Slave Clock-Management Modes and Control ..........................................
CD_L3_MAIN1 Clock Domain Modes..................................................................................
CD_L3_MAIN1 Control and Status Parameters ......................................................................
CD_L3_MAIN1 Dynamic Dependency Association Parameters....................................................
CD_L3_MAIN1 Modules Clocks Association ..........................................................................
CD_L3_MAIN1 Modules Wake-Up Request ..........................................................................
CD_L3_MAIN1 Modules Clock-Management Modes and Control .................................................
CD_L3_MAIN1 Modules Slave Clock-Management Modes and Control ..........................................
CD_EMIF Clock Domain Modes ........................................................................................
CD_EMIF Control and Status Parameters ............................................................................
CD_EMIF Modules Clocks Association ................................................................................
CD_EMIF Modules Wake-Up Request.................................................................................
CD_EMIF Modules Clock-Management Modes and Control........................................................
CD_EMIF Modules Slave Clock-Management Modes and Control ................................................
CD_IPU Clock Domain Modes ..........................................................................................
CD_IPU Control and Status Parameters ..............................................................................
CD_IPU Static Dependency Association Parameters................................................................
CD_IPU Dynamic Dependency Association Parameters ............................................................
3-134. CD_EMU Clock Domain Modes
List of Tables
475
476
476
476
477
477
477
477
478
478
478
478
479
479
479
480
480
480
480
481
481
482
482
482
483
483
484
484
484
485
485
485
486
487
487
487
487
487
488
488
489
489
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
3-178. CD_IPU Modules Clocks Association .................................................................................. 489
..................................................................................
.........................................................
CD_IPU Modules Slave Clock-Management Modes and Control ..................................................
CD_IPU1 Clock Domain Modes ........................................................................................
CD_IPU1 Control and Status Parameters .............................................................................
CD_IPU1 Static Dependency Association Parameters ..............................................................
CD_IPU1 Dynamic Dependency Association Parameters ..........................................................
CD_IPU1 Modules Clocks Association ................................................................................
CD_IPU1 Modules Wake-Up Request .................................................................................
CD_IPU1 Modules Clock-Management Modes and Control ........................................................
CD_IPU1 Modules Slave Clock-Management Modes and Control ................................................
CD_CRC Clock Domain Modes ........................................................................................
CD_CRC Control and Status Parameters .............................................................................
CD_CRC Modules Clocks Association.................................................................................
CD_CRC Modules Wake-Up Request .................................................................................
CD_CRC Modules Clock-Management Modes and Control ........................................................
CD_CRC Modules Slave Clock-Management Modes and Control.................................................
CD_CAM Clock Domain Modes ........................................................................................
CD_CAM Control and Status Parameters .............................................................................
CD_CAM Static Dependency Association Parameters ..............................................................
CD_CAM Modules Clocks Association ................................................................................
CD_CAM Modules Wake-Up Request .................................................................................
CD_CAM Modules Clock-Management Modes and Control ........................................................
CD_CAM Modules Slave Clock-Management Modes and Control ................................................
CD_COREAON_L4 Clock Domain Modes ............................................................................
CD_COREAON_L4 Control and Status Parameters .................................................................
CD_GMAC Clock Domain Modes ......................................................................................
CD_CAM Control and Status Parameters .............................................................................
CD_GMAC Static Dependency Association Parameters ............................................................
CD_GMAC Dynamic Dependency Association Parameters ........................................................
CD_GMAC Modules Clocks Association ..............................................................................
CD_GMAC Modules Wake-Up Request ...............................................................................
CD_GMAC Modules Clock-Management Modes and Control ......................................................
CD_GMAC Modules Slave Clock-Management Modes and Control ..............................................
CD_ISS Clock Domain Modes ..........................................................................................
CD_ISS Control and Status Parameters ..............................................................................
CD_ISS Static Dependency Association Parameters ................................................................
CD_ISS Wake-Up Dependency Association Parameters ...........................................................
CD_ISS Modules Clocks Association ..................................................................................
CD_ISS Modules Wake-Up Request ...................................................................................
CD_ISS Modules Clock-Management Modes and Control ..........................................................
CD_ISS Modules Slave Clock-Management Modes and Control ..................................................
CD_EVE1 Clock Domain Modes .......................................................................................
CD_EVE1 Control and Status Parameters ............................................................................
CD_EVE1 Static Dependency Association Parameters .............................................................
CD_EVE1 Wake-Up Dependency Association Parameters .........................................................
CD_EVE1 Modules Clocks Association ...............................................................................
CD_EVE1 Modules Wake-Up Request ................................................................................
3-179. CD_IPU Modules Wake-Up Request
490
3-180. CD_IPU Modules Clock-Management Modes and Control
490
3-181.
490
3-182.
3-183.
3-184.
3-185.
3-186.
3-187.
3-188.
3-189.
3-190.
3-191.
3-192.
3-193.
3-194.
3-195.
3-196.
3-197.
3-198.
3-199.
3-200.
3-201.
3-202.
3-203.
3-204.
3-205.
3-206.
3-207.
3-208.
3-209.
3-210.
3-211.
3-212.
3-213.
3-214.
3-215.
3-216.
3-217.
3-218.
3-219.
3-220.
3-221.
3-222.
3-223.
3-224.
3-225.
3-226.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
491
491
492
492
492
493
493
493
494
494
494
494
494
494
495
495
495
496
496
496
496
497
497
498
498
499
499
499
499
499
500
500
501
501
501
501
502
502
502
503
503
503
503
503
504
83
www.ti.com
3-227. CD_EVE1 Modules Clock-Management Modes and Control ....................................................... 504
504
3-229. PD_WKUPAON Modules Power Attributes
505
3-230.
506
3-231.
3-232.
3-233.
3-234.
3-235.
3-236.
3-237.
3-238.
3-239.
3-240.
3-241.
3-242.
3-243.
3-244.
3-245.
3-246.
3-247.
3-248.
3-249.
3-250.
3-251.
3-252.
3-253.
3-254.
3-255.
3-256.
3-257.
3-258.
3-259.
3-260.
3-261.
3-262.
3-263.
3-264.
3-265.
3-266.
3-267.
3-268.
3-269.
3-270.
3-271.
3-272.
3-273.
3-274.
3-275.
84
...............................................
...........................................................................
PD_WKUPAON Memory Area Power Modes .........................................................................
PD_DSP1 Modules Power Attributes ..................................................................................
PD_DSP1 Logic Area Power Modes ...................................................................................
PD_DSP1 Memory Area Power Modes................................................................................
PD_DSP1 Power Modes Control Parameters ........................................................................
PD_DSP1 Power Modes Status Parameters .........................................................................
PD_DSP2 Modules Power Attributes ..................................................................................
PD_DSP2 Logic Area Power Modes ...................................................................................
PD_DSP2 Memory Area Power Modes................................................................................
PD_DSP2 Power Modes Control Parameters ........................................................................
PD_DSP2 Power Modes Status Parameters .........................................................................
PD_CUSTEFUSE Modules Power Attributes .........................................................................
PD_CUSTEFUSE Logic Area Power Modes..........................................................................
PD_CUSTEFUSE Power Modes Control Parameters ...............................................................
PD_CUSTEFUSE Power Modes Status Parameters ................................................................
PD_IPU Module Power Attributes ......................................................................................
PD_IPU Logic Area Power Modes .....................................................................................
PD_IPU Memory Area Power Modes ..................................................................................
PD_IPU Power Modes Control Parameters ...........................................................................
PD_IPU Power Mode Status Parameters .............................................................................
PD_DSS Modules Power Attributes ....................................................................................
PD_DSS Logic Area Power Modes ....................................................................................
PD_DSS Memory Area Power Modes .................................................................................
PD_DSS Power Modes Control Parameters ..........................................................................
PD_DSS Power Modes Status Parameters ...........................................................................
PD_CAM Modules Power Attributes ...................................................................................
PD_CAM Logic Area Power Modes ....................................................................................
PD_CAM Memory Area Power Modes .................................................................................
PD_CAM Power Mode Control Parameters ...........................................................................
PD_CAM Power Modes Status Parameters ..........................................................................
PD_MMAON Module Power Attributes ................................................................................
PD_COREAON Module Power Attributes .............................................................................
PD_ISS Modules Power Attributes .....................................................................................
PD_ISS Logic Area Power Modes......................................................................................
PD_ISS Memory Area Power Modes ..................................................................................
PD_ISS Power Modes Control Parameters ...........................................................................
PD_ISS Power Modes Status Parameters ............................................................................
PD_EVE1 Modules Power Attributes ..................................................................................
PD_EVE1 Logic Area Power Modes ...................................................................................
PD_EVE1 Memory Area Power Modes ................................................................................
PD_EVE1 Power Modes Control Parameters.........................................................................
PD_EVE1 Power Modes Status Parameters..........................................................................
Wake-Up Sources During Device Low Power Mode .................................................................
Global Initialization of Surrounding Modules ..........................................................................
DPLL Global Initialization ................................................................................................
DPLL Recalibration Parameter Configuration .........................................................................
3-228. CD_EVE1 Modules Slave Clock-Management Modes and Control
List of Tables
506
506
506
507
507
507
508
508
508
509
509
509
509
510
510
510
510
511
511
511
512
512
512
512
513
513
513
513
513
514
515
516
517
517
517
517
518
518
518
518
519
524
527
527
527
SPRUIC6B – January 2017 – Revised October 2017
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3-276. DPLL Synthesized Clock Parameter Configuration .................................................................. 528
3-277. DPLL Output Clock Parameter Configuration ......................................................................... 528
3-278. Register Call Summary for Sequence DPLL Output Frequency Change ......................................... 530
3-279. Subprocess Call Summary for Sequence DPLL Output Frequency Change ..................................... 530
3-280. Global Initialization of Surrounding Modules .......................................................................... 530
3-281. Clock Domain Global Initialization ...................................................................................... 530
3-282. Slave Module Clock-Management Parameter Configuration
.......................................................
531
3-283. Clock Domain Sleep Transition and Troubleshooting ................................................................ 531
3-284. Enable/Disable Software-Programmable Static Dependency....................................................... 531
3-285. Power Domain Global Initialization ..................................................................................... 532
3-286. Forced Memory Area State Change With Power Domain ON ...................................................... 532
3-287. Forced Power Domain Low-Power State Transition ................................................................. 533
3-288. Not Supported Functionality (Registers and Bits)
...................................................................
534
3-289. PRCM Instance Summary ............................................................................................... 545
3-290. CKGEN_CM_CORE_AON Registers Mapping Summary ........................................................... 546
3-291. CM_CLKSEL_CORE ..................................................................................................... 548
3-292. Register Call Summary for Register CM_CLKSEL_CORE
.........................................................
549
3-293. CM_CLKSEL_ABE ....................................................................................................... 549
3-294. CM_DLL_CTRL ........................................................................................................... 550
3-295. Register Call Summary for Register CM_DLL_CTRL ................................................................ 550
3-296. CM_CLKMODE_DPLL_CORE .......................................................................................... 550
3-297. Register Call Summary for Register CM_CLKMODE_DPLL_CORE .............................................. 552
3-298. CM_IDLEST_DPLL_CORE.............................................................................................. 552
3-299. Register Call Summary for Register CM_IDLEST_DPLL_CORE .................................................. 553
3-300. CM_AUTOIDLE_DPLL_CORE.......................................................................................... 553
3-301. Register Call Summary for Register CM_AUTOIDLE_DPLL_CORE .............................................. 554
3-302. CM_CLKSEL_DPLL_CORE ............................................................................................. 554
3-303. Register Call Summary for Register CM_CLKSEL_DPLL_CORE ................................................. 555
3-304. CM_DIV_M2_DPLL_CORE ............................................................................................. 555
3-305. Register Call Summary for Register CM_DIV_M2_DPLL_CORE .................................................. 556
3-306. CM_DIV_M3_DPLL_CORE ............................................................................................. 556
3-307. CM_DIV_H11_DPLL_CORE ............................................................................................ 556
3-308. CM_DIV_H12_DPLL_CORE ............................................................................................ 557
3-309. Register Call Summary for Register CM_DIV_H12_DPLL_CORE ................................................. 557
3-310. CM_DIV_H13_DPLL_CORE ............................................................................................ 557
3-311. CM_DIV_H14_DPLL_CORE ............................................................................................ 558
3-312. Register Call Summary for Register CM_DIV_H14_DPLL_CORE ................................................. 559
3-313. CM_SSC_DELTAMSTEP_DPLL_CORE .............................................................................. 559
3-314. CM_SSC_MODFREQDIV_DPLL_CORE .............................................................................. 559
3-315. CM_DIV_H21_DPLL_CORE ............................................................................................ 560
3-316. CM_DIV_H22_DPLL_CORE ............................................................................................ 560
3-317. Register Call Summary for Register CM_DIV_H22_DPLL_CORE ................................................. 561
3-318. CM_DIV_H23_DPLL_CORE ............................................................................................ 561
3-319. Register Call Summary for Register CM_DIV_H23_DPLL_CORE ................................................. 561
3-320. CM_DIV_H24_DPLL_CORE ............................................................................................ 562
...........................................................................................
CM_IDLEST_DPLL_MPU ...............................................................................................
CM_AUTOIDLE_DPLL_MPU ...........................................................................................
CM_CLKSEL_DPLL_MPU ..............................................................................................
3-321. CM_CLKMODE_DPLL_MPU
3-322.
3-323.
3-324.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
562
564
565
565
85
www.ti.com
3-325. CM_DIV_M2_DPLL_MPU ............................................................................................... 566
3-326. CM_SSC_DELTAMSTEP_DPLL_MPU ................................................................................ 566
3-327. CM_SSC_MODFREQDIV_DPLL_MPU
...............................................................................
567
3-328. CM_BYPCLK_DPLL_MPU .............................................................................................. 567
3-329. CM_CLKMODE_DPLL_IVA ............................................................................................. 568
3-330. CM_IDLEST_DPLL_IVA ................................................................................................. 569
3-331. CM_AUTOIDLE_DPLL_IVA ............................................................................................. 570
3-332. CM_CLKSEL_DPLL_IVA ................................................................................................ 571
3-333. CM_DIV_M2_DPLL_IVA ................................................................................................. 572
3-334. CM_DIV_M3_DPLL_IVA ................................................................................................. 572
.................................................................................
CM_SSC_MODFREQDIV_DPLL_IVA .................................................................................
CM_BYPCLK_DPLL_IVA ................................................................................................
CM_CLKMODE_DPLL_ABE ............................................................................................
CM_IDLEST_DPLL_ABE ................................................................................................
CM_AUTOIDLE_DPLL_ABE ............................................................................................
CM_CLKSEL_DPLL_ABE ...............................................................................................
CM_DIV_M2_DPLL_ABE ................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_ABE ....................................................
CM_DIV_M3_DPLL_ABE ................................................................................................
CM_SSC_DELTAMSTEP_DPLL_ABE ................................................................................
CM_SSC_MODFREQDIV_DPLL_ABE ................................................................................
CM_CLKMODE_DPLL_DDR ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_DDR ................................................
CM_IDLEST_DPLL_DDR................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_DDR ....................................................
CM_AUTOIDLE_DPLL_DDR ...........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_DDR ................................................
CM_CLKSEL_DPLL_DDR ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_DDR ...................................................
CM_DIV_M2_DPLL_DDR ...............................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_DDR ....................................................
CM_DIV_M3_DPLL_DDR ...............................................................................................
CM_DIV_H11_DPLL_DDR ..............................................................................................
Register Call Summary for Register CM_DIV_H11_DPLL_DDR...................................................
CM_SSC_DELTAMSTEP_DPLL_DDR ................................................................................
CM_SSC_MODFREQDIV_DPLL_DDR ................................................................................
CM_CLKMODE_DPLL_DSP ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_DSP ................................................
CM_IDLEST_DPLL_DSP ................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_DSP ....................................................
CM_AUTOIDLE_DPLL_DSP ............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_DSP ................................................
CM_CLKSEL_DPLL_DSP ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_DSP ...................................................
CM_DIV_M2_DPLL_DSP................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_DSP ....................................................
CM_DIV_M3_DPLL_DSP................................................................................................
Register Call Summary for Register CM_DIV_M3_DPLL_DSP ....................................................
3-335. CM_SSC_DELTAMSTEP_DPLL_IVA
3-336.
3-337.
3-338.
3-339.
3-340.
3-341.
3-342.
3-343.
3-344.
3-345.
3-346.
3-347.
3-348.
3-349.
3-350.
3-351.
3-352.
3-353.
3-354.
3-355.
3-356.
3-357.
3-358.
3-359.
3-360.
3-361.
3-362.
3-363.
3-364.
3-365.
3-366.
3-367.
3-368.
3-369.
3-370.
3-371.
3-372.
3-373.
86
List of Tables
573
573
573
574
575
576
577
578
578
578
579
579
580
581
582
582
582
583
583
584
584
585
585
585
586
586
586
587
588
589
589
589
590
590
591
591
592
592
592
SPRUIC6B – January 2017 – Revised October 2017
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3-374. CM_SSC_DELTAMSTEP_DPLL_DSP ................................................................................ 592
3-375. CM_SSC_MODFREQDIV_DPLL_DSP ................................................................................ 593
3-376. CM_BYPCLK_DPLL_DSP ............................................................................................... 593
3-377. Register Call Summary for Register CM_BYPCLK_DPLL_DSP ................................................... 594
3-378. CM_SHADOW_FREQ_CONFIG1 ...................................................................................... 594
..........................................
CM_SHADOW_FREQ_CONFIG2 ......................................................................................
Register Call Summary for Register CM_SHADOW_FREQ_CONFIG2 ..........................................
CM_DYN_DEP_PRESCAL ..............................................................................................
Register Call Summary for Register CM_DYN_DEP_PRESCAL ..................................................
CM_RESTORE_ST.......................................................................................................
CM_CLKMODE_DPLL_EVE ............................................................................................
CM_IDLEST_DPLL_EVE ................................................................................................
CM_AUTOIDLE_DPLL_EVE ............................................................................................
CM_CLKSEL_DPLL_EVE ...............................................................................................
CM_DIV_M2_DPLL_EVE ................................................................................................
CM_DIV_M3_DPLL_EVE ................................................................................................
CM_SSC_DELTAMSTEP_DPLL_EVE ................................................................................
CM_SSC_MODFREQDIV_DPLL_EVE ................................................................................
CM_BYPCLK_DPLL_EVE ...............................................................................................
CM_CLKMODE_DPLL_GMAC .........................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_GMAC ..............................................
CM_IDLEST_DPLL_GMAC .............................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_GMAC ..................................................
CM_AUTOIDLE_DPLL_GMAC .........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_GMAC ..............................................
CM_CLKSEL_DPLL_GMAC ............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_GMAC .................................................
CM_DIV_M2_DPLL_GMAC .............................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_GMAC..................................................
CM_DIV_M3_DPLL_GMAC .............................................................................................
Register Call Summary for Register CM_DIV_M3_DPLL_GMAC..................................................
CM_DIV_H11_DPLL_GMAC ............................................................................................
Register Call Summary for Register CM_DIV_H11_DPLL_GMAC ................................................
CM_DIV_H12_DPLL_GMAC ............................................................................................
Register Call Summary for Register CM_DIV_H12_DPLL_GMAC ................................................
CM_DIV_H13_DPLL_GMAC ............................................................................................
Register Call Summary for Register CM_DIV_H13_DPLL_GMAC ................................................
CM_DIV_H14_DPLL_GMAC ............................................................................................
CM_SSC_DELTAMSTEP_DPLL_GMAC ..............................................................................
CM_SSC_MODFREQDIV_DPLL_GMAC .............................................................................
CM_CLKMODE_DPLL_GPU ............................................................................................
CM_IDLEST_DPLL_GPU................................................................................................
CM_AUTOIDLE_DPLL_GPU ...........................................................................................
CM_CLKSEL_DPLL_GPU ...............................................................................................
CM_DIV_M2_DPLL_GPU ...............................................................................................
CM_DIV_M3_DPLL_GPU ...............................................................................................
CM_SSC_DELTAMSTEP_DPLL_GPU ................................................................................
CM_SSC_MODFREQDIV_DPLL_GPU ................................................................................
3-379. Register Call Summary for Register CM_SHADOW_FREQ_CONFIG1
595
3-380.
595
3-381.
3-382.
3-383.
3-384.
3-385.
3-386.
3-387.
3-388.
3-389.
3-390.
3-391.
3-392.
3-393.
3-394.
3-395.
3-396.
3-397.
3-398.
3-399.
3-400.
3-401.
3-402.
3-403.
3-404.
3-405.
3-406.
3-407.
3-408.
3-409.
3-410.
3-411.
3-412.
3-413.
3-414.
3-415.
3-416.
3-417.
3-418.
3-419.
3-420.
3-421.
3-422.
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Tables
596
596
596
596
597
599
599
600
601
601
602
602
602
603
604
605
605
605
606
606
607
607
608
608
608
609
609
609
610
610
610
611
611
611
612
614
614
615
616
616
617
617
87
www.ti.com
3-423. DSP1_CM_CORE_AON Registers Mapping Summary ............................................................. 618
3-424. CM_DSP1_CLKSTCTRL ................................................................................................ 618
3-425. Register Call Summary for Register CM_DSP1_CLKSTCTRL ..................................................... 619
3-426. CM_DSP1_STATICDEP ................................................................................................. 619
3-427. Register Call Summary for Register CM_DSP1_STATICDEP
.....................................................
621
3-428. CM_DSP1_DYNAMICDEP .............................................................................................. 621
3-429. Register Call Summary for Register CM_DSP1_DYNAMICDEP................................................... 621
3-430. CM_DSP1_DSP1_CLKCTRL ........................................................................................... 622
3-431. Register Call Summary for Register CM_DSP1_DSP1_CLKCTRL ................................................ 622
3-432. DSP2_CM_CORE_AON Registers Mapping Summary ............................................................. 623
3-433. CM_DSP2_CLKSTCTRL ................................................................................................ 623
3-434. Register Call Summary for Register CM_DSP2_CLKSTCTRL ..................................................... 624
3-435. CM_DSP2_STATICDEP ................................................................................................. 624
626
3-437.
626
3-438.
3-439.
3-440.
3-441.
3-442.
3-443.
3-444.
3-445.
3-446.
3-447.
3-448.
3-449.
3-450.
3-451.
3-452.
3-453.
3-454.
3-455.
3-456.
3-457.
3-458.
3-459.
3-460.
3-461.
3-462.
3-463.
3-464.
3-465.
3-466.
3-467.
3-468.
3-469.
3-470.
3-471.
88
.....................................................
CM_DSP2_DYNAMICDEP ..............................................................................................
Register Call Summary for Register CM_DSP2_DYNAMICDEP...................................................
CM_DSP2_DSP2_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_DSP2_DSP2_CLKCTRL ................................................
EVE1_CM_CORE_AON Registers Mapping Summary .............................................................
CM_EVE1_CLKSTCTRL ................................................................................................
Register Call Summary for Register CM_EVE1_CLKSTCTRL .....................................................
CM_EVE1_STATICDEP .................................................................................................
Register Call Summary for Register CM_EVE1_STATICDEP......................................................
CM_EVE1_EVE1_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_EVE1_EVE1_CLKCTRL ................................................
EVE2_CM_CORE_AON Registers Mapping Summary .............................................................
CM_EVE2_CLKSTCTRL ................................................................................................
CM_EVE2_STATICDEP .................................................................................................
CM_EVE2_EVE2_CLKCTRL ...........................................................................................
EVE3_CM_CORE_AON Registers Mapping Summary .............................................................
CM_EVE3_CLKSTCTRL ................................................................................................
CM_EVE3_STATICDEP .................................................................................................
CM_EVE3_EVE3_CLKCTRL ...........................................................................................
EVE4_CM_CORE_AON Registers Mapping Summary .............................................................
CM_EVE4_CLKSTCTRL ................................................................................................
CM_EVE4_STATICDEP .................................................................................................
CM_EVE4_EVE4_CLKCTRL ...........................................................................................
INSTR_CM_CORE_AON Registers Mapping Summary ............................................................
CMI_IDENTICATION .....................................................................................................
Register Call Summary for Register CMI_IDENTICATION .........................................................
CMI_SYS_CONFIG ......................................................................................................
Register Call Summary for Register CMI_SYS_CONFIG ...........................................................
CMI_STATUS .............................................................................................................
Register Call Summary for Register CMI_STATUS ..................................................................
CMI_CONFIGURATION .................................................................................................
Register Call Summary for Register CMI_CONFIGURATION ......................................................
CMI_CLASS_FILTERING ...............................................................................................
Register Call Summary for Register CMI_CLASS_FILTERING ....................................................
CMI_TRIGGERING .......................................................................................................
3-436. Register Call Summary for Register CM_DSP2_STATICDEP
List of Tables
626
627
627
628
628
629
629
629
630
630
631
631
632
632
633
633
634
635
636
636
637
638
639
639
639
639
640
640
640
640
641
641
642
642
SPRUIC6B – January 2017 – Revised October 2017
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3-472. Register Call Summary for Register CMI_TRIGGERING ........................................................... 642
3-473. CMI_SAMPLING .......................................................................................................... 642
3-474. Register Call Summary for Register CMI_SAMPLING
..............................................................
643
3-475. IPU_CM_CORE_AON Registers Mapping Summary ................................................................ 643
3-476. CM_IPU1_CLKSTCTRL ................................................................................................. 643
3-477. Register Call Summary for Register CM_IPU1_CLKSTCTRL ...................................................... 644
3-478. CM_IPU1_STATICDEP .................................................................................................. 644
3-479. Register Call Summary for Register CM_IPU1_STATICDEP
......................................................
646
3-480. CM_IPU1_DYNAMICDEP ............................................................................................... 646
3-481. Register Call Summary for Register CM_IPU1_DYNAMICDEP .................................................... 647
3-482. CM_IPU1_IPU1_CLKCTRL ............................................................................................. 647
3-483. Register Call Summary for Register CM_IPU1_IPU1_CLKCTRL .................................................. 648
3-484. CM_IPU_CLKSTCTRL ................................................................................................... 648
.......................................................
CM_IPU_MCASP1_CLKCTRL ..........................................................................................
Register Call Summary for Register CM_IPU_MCASP1_CLKCTRL ..............................................
CM_IPU_TIMER5_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER5_CLKCTRL ...............................................
CM_IPU_TIMER6_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER6_CLKCTRL ...............................................
CM_IPU_TIMER7_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER7_CLKCTRL ...............................................
CM_IPU_TIMER8_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER8_CLKCTRL ...............................................
CM_IPU_I2C5_CLKCTRL ...............................................................................................
CM_IPU_UART6_CLKCTRL ............................................................................................
MPU_CM_CORE_AON Registers Mapping Summary ..............................................................
CM_MPU_CLKSTCTRL .................................................................................................
CM_MPU_STATICDEP ..................................................................................................
CM_MPU_DYNAMICDEP ...............................................................................................
CM_MPU_MPU_CLKCTRL .............................................................................................
CM_MPU_MPU_MPU_DBG_CLKCTRL ..............................................................................
OCP_SOCKET_CM_CORE_AON Registers Mapping Summary ..................................................
REVISION_CM_CORE_AON ...........................................................................................
Register Call Summary for Register REVISION_CM_CORE_AON................................................
CM_CM_CORE_AON_PROFILING_CLKCTRL ......................................................................
Register Call Summary for Register CM_CM_CORE_AON_PROFILING_CLKCTRL ..........................
CM_CORE_AON_DEBUG_OUT .......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_OUT ............................................
CM_CORE_AON_DEBUG_CFG0 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG0 ..........................................
CM_CORE_AON_DEBUG_CFG1 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG1 ..........................................
CM_CORE_AON_DEBUG_CFG2 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG2 ..........................................
CM_CORE_AON_DEBUG_CFG3 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG3 ..........................................
RESTORE_CM_CORE_AON Registers Mapping Summary .......................................................
CM_CLKSEL_CORE_RESTORE ......................................................................................
3-485. Register Call Summary for Register CM_IPU_CLKSTCTRL
3-486.
3-487.
3-488.
3-489.
3-490.
3-491.
3-492.
3-493.
3-494.
3-495.
3-496.
3-497.
3-498.
3-499.
3-500.
3-501.
3-502.
3-503.
3-504.
3-505.
3-506.
3-507.
3-508.
3-509.
3-510.
3-511.
3-512.
3-513.
3-514.
3-515.
3-516.
3-517.
3-518.
3-519.
3-520.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
650
650
652
652
653
653
654
655
656
656
657
657
658
659
659
660
662
662
663
664
664
665
665
665
666
666
666
666
666
667
667
667
667
668
668
668
89
www.ti.com
3-521. Register Call Summary for Register CM_CLKSEL_CORE_RESTORE ........................................... 669
3-522. CM_DIV_M2_DPLL_CORE_RESTORE ............................................................................... 669
3-523. Register Call Summary for Register CM_DIV_M2_DPLL_CORE_RESTORE ................................... 669
3-524. CM_DIV_M3_DPLL_CORE_RESTORE ............................................................................... 669
3-525. Register Call Summary for Register CM_DIV_M3_DPLL_CORE_RESTORE ................................... 669
3-526. CM_DIV_H11_DPLL_CORE_RESTORE.............................................................................. 669
3-527. Register Call Summary for Register CM_DIV_H11_DPLL_CORE_RESTORE .................................. 670
3-528. CM_DIV_H12_DPLL_CORE_RESTORE.............................................................................. 670
3-529. Register Call Summary for Register CM_DIV_H12_DPLL_CORE_RESTORE .................................. 670
3-530. CM_DIV_H13_DPLL_CORE_RESTORE.............................................................................. 670
3-531. Register Call Summary for Register CM_DIV_H13_DPLL_CORE_RESTORE .................................. 670
3-532. CM_DIV_H14_DPLL_CORE_RESTORE.............................................................................. 671
3-533. Register Call Summary for Register CM_DIV_H14_DPLL_CORE_RESTORE .................................. 671
3-534. CM_DIV_H21_DPLL_CORE_RESTORE.............................................................................. 671
3-535. Register Call Summary for Register CM_DIV_H21_DPLL_CORE_RESTORE .................................. 671
3-536. CM_DIV_H22_DPLL_CORE_RESTORE.............................................................................. 671
3-537. Register Call Summary for Register CM_DIV_H22_DPLL_CORE_RESTORE .................................. 672
3-538. CM_DIV_H23_DPLL_CORE_RESTORE.............................................................................. 672
3-539. Register Call Summary for Register CM_DIV_H23_DPLL_CORE_RESTORE .................................. 672
3-540. CM_DIV_H24_DPLL_CORE_RESTORE.............................................................................. 672
3-541. Register Call Summary for Register CM_DIV_H24_DPLL_CORE_RESTORE .................................. 672
3-542. CM_CLKSEL_DPLL_CORE_RESTORE .............................................................................. 672
3-543. Register Call Summary for Register CM_CLKSEL_DPLL_CORE_RESTORE ................................... 673
673
3-545.
673
3-546.
3-547.
3-548.
3-549.
3-550.
3-551.
3-552.
3-553.
3-554.
3-555.
3-556.
3-557.
3-558.
3-559.
3-560.
3-561.
3-562.
3-563.
3-564.
3-565.
3-566.
3-567.
3-568.
3-569.
90
...............................................................
CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE ...............................................................
CM_CLKMODE_DPLL_CORE_RESTORE ...........................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_CORE_RESTORE ................................
CM_SHADOW_FREQ_CONFIG2_RESTORE .......................................................................
Register Call Summary for Register CM_SHADOW_FREQ_CONFIG2_RESTORE ............................
CM_SHADOW_FREQ_CONFIG1_RESTORE .......................................................................
Register Call Summary for Register CM_SHADOW_FREQ_CONFIG1_RESTORE ............................
CM_AUTOIDLE_DPLL_CORE_RESTORE ...........................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_CORE_RESTORE................................
CM_MPU_CLKSTCTRL_RESTORE ...................................................................................
CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE .......................................................
Register Call Summary for Register CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE ............
CM_DYN_DEP_PRESCAL_RESTORE ...............................................................................
Register Call Summary for Register CM_DYN_DEP_PRESCAL_RESTORE ....................................
RTC_CM_CORE_AON Registers Mapping Summary ...............................................................
CM_RTC_CLKSTCTRL ..................................................................................................
CM_RTC_RTCSS_CLKCTRL ...........................................................................................
ISS_CM_CORE_AON Registers Mapping Summary ................................................................
CM_ISS_CLKSTCTRL ...................................................................................................
Register Call Summary for Register CM_ISS_CLKSTCTRL........................................................
CM_ISS_ISS_CLKCTRL.................................................................................................
Register Call Summary for Register CM_ISS_ISS_CLKCTRL .....................................................
CM_ISS_STATICDEP....................................................................................................
Register Call Summary for Register CM_ISS_STATICDEP ........................................................
CAM_CM_CORE Registers Mapping Summary......................................................................
3-544. CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE
List of Tables
673
674
674
674
674
674
675
675
675
675
676
676
676
676
676
677
678
678
679
679
680
680
681
681
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
3-570. CM_CAM_CLKSTCTRL ................................................................................................. 681
3-571. Register Call Summary for Register CM_CAM_CLKSTCTRL ...................................................... 682
3-572. CM_CAM_STATICDEP .................................................................................................. 682
......................................................
CM_CAM_VIP1_CLKCTRL .............................................................................................
Register Call Summary for Register CM_CAM_VIP1_CLKCTRL ..................................................
CM_CAM_VIP2_CLKCTRL .............................................................................................
CM_CAM_VIP3_CLKCTRL .............................................................................................
CM_CAM_LVDSRX_CLKCTRL ........................................................................................
Register Call Summary for Register CM_CAM_LVDSRX_CLKCTRL .............................................
CM_CAM_CSI1_CLKCTRL .............................................................................................
Register Call Summary for Register CM_CAM_CSI1_CLKCTRL ..................................................
CM_CAM_CSI2_CLKCTRL .............................................................................................
Register Call Summary for Register CM_CAM_CSI2_CLKCTRL ..................................................
CKGEN_CM_CORE Registers Mapping Summary ..................................................................
CM_CLKSEL_USB_60MHZ .............................................................................................
CM_CLKMODE_DPLL_PER ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_PER ................................................
CM_IDLEST_DPLL_PER ................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_PER ....................................................
CM_AUTOIDLE_DPLL_PER ............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_PER ................................................
CM_CLKSEL_DPLL_PER ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_PER ...................................................
CM_DIV_M2_DPLL_PER................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_PER ....................................................
CM_DIV_M3_DPLL_PER................................................................................................
CM_DIV_H11_DPLL_PER ..............................................................................................
Register Call Summary for Register CM_DIV_H11_DPLL_PER ...................................................
CM_DIV_H12_DPLL_PER ..............................................................................................
Register Call Summary for Register CM_DIV_H12_DPLL_PER ...................................................
CM_DIV_H13_DPLL_PER ..............................................................................................
Register Call Summary for Register CM_DIV_H13_DPLL_PER ...................................................
CM_DIV_H14_DPLL_PER ..............................................................................................
CM_SSC_DELTAMSTEP_DPLL_PER ................................................................................
Register Call Summary for Register CM_SSC_DELTAMSTEP_DPLL_PER .....................................
CM_SSC_MODFREQDIV_DPLL_PER ................................................................................
Register Call Summary for Register CM_SSC_MODFREQDIV_DPLL_PER ....................................
CM_CLKMODE_DPLL_USB ............................................................................................
CM_IDLEST_DPLL_USB ................................................................................................
CM_AUTOIDLE_DPLL_USB ............................................................................................
CM_CLKSEL_DPLL_USB ...............................................................................................
CM_DIV_M2_DPLL_USB................................................................................................
CM_SSC_DELTAMSTEP_DPLL_USB ................................................................................
CM_SSC_MODFREQDIV_DPLL_USB ................................................................................
CM_CLKDCOLDO_DPLL_USB ........................................................................................
CM_CLKMODE_DPLL_PCIE_REF ....................................................................................
CM_IDLEST_DPLL_PCIE_REF ........................................................................................
CM_AUTOIDLE_DPLL_PCIE_REF ....................................................................................
3-573. Register Call Summary for Register CM_CAM_STATICDEP
684
3-574.
684
3-575.
3-576.
3-577.
3-578.
3-579.
3-580.
3-581.
3-582.
3-583.
3-584.
3-585.
3-586.
3-587.
3-588.
3-589.
3-590.
3-591.
3-592.
3-593.
3-594.
3-595.
3-596.
3-597.
3-598.
3-599.
3-600.
3-601.
3-602.
3-603.
3-604.
3-605.
3-606.
3-607.
3-608.
3-609.
3-610.
3-611.
3-612.
3-613.
3-614.
3-615.
3-616.
3-617.
3-618.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
685
685
686
686
687
687
688
688
689
689
690
690
692
692
693
693
694
694
695
695
696
696
696
697
697
697
698
698
698
699
699
699
700
700
701
702
702
703
704
704
705
705
706
707
91
www.ti.com
3-619. CM_CLKSEL_DPLL_PCIE_REF ....................................................................................... 708
3-620. CM_DIV_M2_DPLL_PCIE_REF ........................................................................................ 708
3-621. CM_SSC_DELTAMSTEP_DPLL_PCIE_REF ......................................................................... 709
3-622. CM_SSC_MODFREQDIV_DPLL_PCIE_REF ........................................................................ 709
3-623. CM_CLKMODE_APLL_PCIE
...........................................................................................
710
3-624. CM_IDLEST_APLL_PCIE ............................................................................................... 711
3-625. CM_DIV_M2_APLL_PCIE ............................................................................................... 711
3-626. CM_CLKVCOLDO_APLL_PCIE ........................................................................................ 712
3-627. COREAON_CM_CORE Registers Mapping Summary .............................................................. 712
3-628. CM_COREAON_CLKSTCTRL .......................................................................................... 713
3-629. Register Call Summary for Register CM_COREAON_CLKSTCTRL .............................................. 714
3-630. CM_COREAON_SMARTREFLEX_MPU_CLKCTRL ................................................................ 714
3-631. CM_COREAON_SMARTREFLEX_CORE_CLKCTRL
..............................................................
715
3-632. CM_COREAON_USB_PHY1_CORE_CLKCTRL .................................................................... 716
716
3-634. CM_COREAON_SMARTREFLEX_GPU_CLKCTRL
717
3-635.
717
3-636.
3-637.
3-638.
3-639.
3-640.
3-641.
3-642.
3-643.
3-644.
3-645.
3-646.
3-647.
3-648.
3-649.
3-650.
3-651.
3-652.
3-653.
3-654.
3-655.
3-656.
3-657.
3-658.
3-659.
3-660.
3-661.
3-662.
3-663.
3-664.
3-665.
3-666.
3-667.
92
...........................................................................
................................................................
CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL ...........................................................
CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL ..............................................................
CM_COREAON_USB_PHY2_CORE_CLKCTRL ....................................................................
CM_COREAON_USB_PHY3_CORE_CLKCTRL ....................................................................
CM_COREAON_DUMMY_MODULE1_CLKCTRL ...................................................................
Register Call Summary for Register CM_COREAON_DUMMY_MODULE1_CLKCTRL .......................
CM_COREAON_DUMMY_MODULE2_CLKCTRL ...................................................................
Register Call Summary for Register CM_COREAON_DUMMY_MODULE2_CLKCTRL .......................
CM_COREAON_DUMMY_MODULE3_CLKCTRL ...................................................................
CM_COREAON_DUMMY_MODULE4_CLKCTRL ...................................................................
Register Call Summary for Register CM_COREAON_DUMMY_MODULE4_CLKCTRL .......................
CORE_CM_CORE Registers Mapping Summary ....................................................................
CM_L3MAIN1_CLKSTCTRL ............................................................................................
Register Call Summary for Register CM_L3MAIN1_CLKSTCTRL .................................................
CM_L3MAIN1_DYNAMICDEP ..........................................................................................
Register Call Summary for Register CM_L3MAIN1_DYNAMICDEP ..............................................
CM_L3MAIN1_L3_MAIN_1_CLKCTRL ................................................................................
Register Call Summary for Register CM_L3MAIN1_L3_MAIN_1_CLKCTRL ....................................
CM_L3MAIN1_GPMC_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L3MAIN1_GPMC_CLKCTRL ..........................................
CM_L3MAIN1_MMU_EDMA_CLKCTRL ..............................................................................
Register Call Summary for Register CM_L3MAIN1_MMU_EDMA_CLKCTRL ...................................
CM_L3MAIN1_MMU_PCIESS_CLKCTRL ............................................................................
CM_L3MAIN1_OCMC_RAM1_CLKCTRL .............................................................................
Register Call Summary for Register CM_L3MAIN1_OCMC_RAM1_CLKCTRL .................................
CM_L3MAIN1_TESOC_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L3MAIN1_TESOC_CLKCTRL .........................................
CM_L3MAIN1_OCMC_RAM3_CLKCTRL .............................................................................
CM_L3MAIN1_OCMC_ROM_CLKCTRL ..............................................................................
CM_L3MAIN1_TPCC_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L3MAIN1_TPCC_CLKCTRL ...........................................
CM_L3MAIN1_TPTC1_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L3MAIN1_TPTC1_CLKCTRL ..........................................
3-633. CM_COREAON_IO_SRCOMP_CLKCTRL
List of Tables
718
719
719
720
720
720
721
721
722
722
722
724
725
725
726
727
727
727
728
728
729
729
729
730
730
731
731
732
732
733
733
734
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
.....................................................................................
Register Call Summary for Register CM_L3MAIN1_TPTC2_CLKCTRL ..........................................
CM_L3MAIN1_VCP1_CLKCTRL .......................................................................................
CM_L3MAIN1_VCP2_CLKCTRL .......................................................................................
CM_L3MAIN1_SPARE_CME_CLKCTRL .............................................................................
CM_L3MAIN1_SPARE_HDMI_CLKCTRL ............................................................................
CM_L3MAIN1_SPARE_ICM_CLKCTRL ..............................................................................
CM_L3MAIN1_SPARE_IVA2_CLKCTRL..............................................................................
CM_L3MAIN1_SPARE_SATA2_CLKCTRL ...........................................................................
CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL ....................................................................
CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL ....................................................................
CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL ....................................................................
CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL .....................................................................
CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL .....................................................................
CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL .....................................................................
CM_IPU2_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_IPU2_CLKSTCTRL ......................................................
CM_IPU2_STATICDEP ..................................................................................................
Register Call Summary for Register CM_IPU2_STATICDEP ......................................................
CM_IPU2_DYNAMICDEP ...............................................................................................
Register Call Summary for Register CM_IPU2_DYNAMICDEP ....................................................
CM_IPU2_IPU2_CLKCTRL .............................................................................................
Register Call Summary for Register CM_IPU2_IPU2_CLKCTRL ..................................................
CM_DMA_CLKSTCTRL .................................................................................................
CM_DMA_STATICDEP ..................................................................................................
CM_DMA_DYNAMICDEP ...............................................................................................
CM_DMA_DMA_SYSTEM_CLKCTRL .................................................................................
CM_EMIF_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_EMIF_CLKSTCTRL .....................................................
CM_EMIF_DMM_CLKCTRL ............................................................................................
CM_EMIF_EMIF_OCP_FW_CLKCTRL ...............................................................................
Register Call Summary for Register CM_EMIF_EMIF_OCP_FW_CLKCTRL ....................................
CM_EMIF_EMIF1_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_EMIF_EMIF1_CLKCTRL ...............................................
CM_EMIF_EMIF2_CLKCTRL ...........................................................................................
CM_EMIF_EMIF_DLL_CLKCTRL ......................................................................................
Register Call Summary for Register CM_EMIF_EMIF_DLL_CLKCTRL ..........................................
CM_CRC_CRC_CLKCTRL ..............................................................................................
Register Call Summary for Register CM_CRC_CRC_CLKCTRL ..................................................
CM_CRC_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_CRC_CLKSTCTRL ......................................................
CM_L4CFG_CLKSTCTRL ...............................................................................................
Register Call Summary for Register CM_L4CFG_CLKSTCTRL ...................................................
CM_L4CFG_DYNAMICDEP ............................................................................................
Register Call Summary for Register CM_L4CFG_DYNAMICDEP .................................................
CM_L4CFG_L4_CFG_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4CFG_L4_CFG_CLKCTRL ...........................................
CM_L4CFG_SPINLOCK_CLKCTRL ...................................................................................
Register Call Summary for Register CM_L4CFG_SPINLOCK_CLKCTRL .......................................
3-668. CM_L3MAIN1_TPTC2_CLKCTRL
734
3-669.
735
3-670.
3-671.
3-672.
3-673.
3-674.
3-675.
3-676.
3-677.
3-678.
3-679.
3-680.
3-681.
3-682.
3-683.
3-684.
3-685.
3-686.
3-687.
3-688.
3-689.
3-690.
3-691.
3-692.
3-693.
3-694.
3-695.
3-696.
3-697.
3-698.
3-699.
3-700.
3-701.
3-702.
3-703.
3-704.
3-705.
3-706.
3-707.
3-708.
3-709.
3-710.
3-711.
3-712.
3-713.
3-714.
3-715.
3-716.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
735
736
736
737
737
738
739
739
740
740
741
742
742
743
744
744
746
746
747
747
748
748
748
750
750
751
752
752
753
753
753
754
754
755
756
756
757
757
758
758
759
759
760
760
761
761
761
93
www.ti.com
3-717. CM_L4CFG_MAILBOX1_CLKCTRL ................................................................................... 761
3-718. Register Call Summary for Register CM_L4CFG_MAILBOX1_CLKCTRL ........................................ 762
3-719. CM_L4CFG_SAR_ROM_CLKCTRL ................................................................................... 762
3-720. CM_L4CFG_OCP2SCP2_CLKCTRL .................................................................................. 763
3-721. CM_L4CFG_MAILBOX2_CLKCTRL ................................................................................... 763
3-722. Register Call Summary for Register CM_L4CFG_MAILBOX2_CLKCTRL ........................................ 764
3-723. CM_L4CFG_MAILBOX3_CLKCTRL ................................................................................... 764
3-724. CM_L4CFG_MAILBOX4_CLKCTRL ................................................................................... 765
3-725. CM_L4CFG_MAILBOX5_CLKCTRL ................................................................................... 765
3-726. CM_L4CFG_MAILBOX6_CLKCTRL ................................................................................... 766
3-727. CM_L4CFG_MAILBOX7_CLKCTRL ................................................................................... 767
3-728. CM_L4CFG_MAILBOX8_CLKCTRL ................................................................................... 767
3-729. CM_L4CFG_MAILBOX9_CLKCTRL ................................................................................... 768
3-730. CM_L4CFG_MAILBOX10_CLKCTRL.................................................................................. 768
3-731. CM_L4CFG_MAILBOX11_CLKCTRL.................................................................................. 769
3-732. CM_L4CFG_MAILBOX12_CLKCTRL.................................................................................. 770
3-733. CM_L4CFG_MAILBOX13_CLKCTRL.................................................................................. 770
3-734. CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL ........................................................... 771
3-735. CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL ....................................................... 771
3-736. CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL
........................................................
772
3-737. CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL ......................................................................... 773
3-738. CM_L3INSTR_CLKSTCTRL ............................................................................................ 773
3-739. Register Call Summary for Register CM_L3INSTR_CLKSTCTRL ................................................. 774
3-740. CM_L3INSTR_L3_MAIN_2_CLKCTRL ................................................................................ 774
3-741. Register Call Summary for Register CM_L3INSTR_L3_MAIN_2_CLKCTRL
....................................
775
3-742. CM_L3INSTR_L3_INSTR_CLKCTRL .................................................................................. 775
3-743. Register Call Summary for Register CM_L3INSTR_L3_INSTR_CLKCTRL ...................................... 776
3-744. CM_L3INSTR_OCP_WP_NOC_CLKCTRL ........................................................................... 776
3-745. Register Call Summary for Register CM_L3INSTR_OCP_WP_NOC_CLKCTRL................................ 777
3-746. CM_L3INSTR_DLL_AGING_CLKCTRL ............................................................................... 777
3-747. Register Call Summary for Register CM_L3INSTR_DLL_AGING_CLKCTRL.................................... 778
3-748. CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL
...........................................................
778
3-749. Register Call Summary for Register CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL ................ 778
3-750. CUSTEFUSE_CM_CORE Registers Mapping Summary ........................................................... 779
3-751. CM_CUSTEFUSE_CLKSTCTRL ....................................................................................... 779
3-752. Register Call Summary for Register CM_CUSTEFUSE_CLKSTCTRL............................................ 780
3-753. CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL............................................................... 780
3-754. Register Call Summary for Register CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL ................... 781
3-755. DSS_CM_CORE Registers Mapping Summary ...................................................................... 781
3-756. CM_DSS_CLKSTCTRL .................................................................................................. 781
......................................................
CM_DSS_STATICDEP ..................................................................................................
Register Call Summary for Register CM_DSS_STATICDEP .......................................................
CM_DSS_DYNAMICDEP................................................................................................
Register Call Summary for Register CM_DSS_DYNAMICDEP ....................................................
CM_DSS_DSS_CLKCTRL ..............................................................................................
Register Call Summary for Register CM_DSS_DSS_CLKCTRL ...................................................
CM_DSS_BB2D_CLKCTRL .............................................................................................
CM_DSS_SDVENC_CLKCTRL ........................................................................................
3-757. Register Call Summary for Register CM_DSS_CLKSTCTRL
3-758.
3-759.
3-760.
3-761.
3-762.
3-763.
3-764.
3-765.
94
List of Tables
783
783
784
784
784
785
786
786
787
SPRUIC6B – January 2017 – Revised October 2017
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www.ti.com
3-766. Register Call Summary for Register CM_DSS_SDVENC_CLKCTRL ............................................. 787
3-767. GPU_CM_CORE Registers Mapping Summary ...................................................................... 788
3-768. CM_GPU_CLKSTCTRL
.................................................................................................
788
3-769. CM_GPU_STATICDEP .................................................................................................. 789
3-770. CM_GPU_DYNAMICDEP ............................................................................................... 789
3-771. CM_GPU_GPU_CLKCTRL.............................................................................................. 790
3-772. IVA_CM_CORE Registers Mapping Summary ....................................................................... 791
3-773. CM_IVA_CLKSTCTRL ................................................................................................... 791
3-774. CM_IVA_STATICDEP.................................................................................................... 792
3-775. CM_IVA_DYNAMICDEP ................................................................................................. 793
3-776. CM_IVA_IVA_CLKCTRL................................................................................................. 793
3-777. CM_IVA_SL2_CLKCTRL ................................................................................................ 794
3-778. L3INIT_CM_CORE Registers Mapping Summary
...................................................................
795
3-779. CM_L3INIT_CLKSTCTRL ............................................................................................... 795
3-780. Register Call Summary for Register CM_L3INIT_CLKSTCTRL .................................................... 798
3-781. CM_L3INIT_STATICDEP ................................................................................................ 798
3-782. Register Call Summary for Register CM_L3INIT_STATICDEP
....................................................
799
3-783. CM_L3INIT_DYNAMICDEP ............................................................................................. 799
3-784. Register Call Summary for Register CM_L3INIT_DYNAMICDEP.................................................. 800
3-785. CM_L3INIT_MMC1_CLKCTRL ......................................................................................... 800
3-786. CM_L3INIT_MMC2_CLKCTRL ......................................................................................... 801
3-787. CM_L3INIT_USB_OTG_SS2_CLKCTRL .............................................................................. 802
3-788. CM_L3INIT_USB_OTG_SS3_CLKCTRL .............................................................................. 803
3-789. CM_L3INIT_USB_OTG_SS4_CLKCTRL .............................................................................. 804
3-790. CM_L3INIT_MLB_SS_CLKCTRL....................................................................................... 804
3-791. CM_L3INIT_IEEE1500_2_OCP_CLKCTRL ........................................................................... 805
3-792. Register Call Summary for Register CM_L3INIT_IEEE1500_2_OCP_CLKCTRL ............................... 806
3-793. CM_L3INIT_SATA_CLKCTRL .......................................................................................... 806
3-794. CM_PCIE_CLKSTCTRL ................................................................................................. 807
3-795. CM_PCIE_STATICDEP .................................................................................................. 808
3-796. CM_PCIE_PCIESS1_CLKCTRL........................................................................................ 810
3-797. CM_PCIE_PCIESS2_CLKCTRL........................................................................................ 811
3-798. CM_GMAC_CLKSTCTRL ............................................................................................... 812
3-799. Register Call Summary for Register CM_GMAC_CLKSTCTRL .................................................... 814
3-800. CM_GMAC_STATICDEP ................................................................................................ 814
....................................................
CM_GMAC_DYNAMICDEP .............................................................................................
Register Call Summary for Register CM_GMAC_DYNAMICDEP..................................................
CM_GMAC_GMAC_CLKCTRL .........................................................................................
Register Call Summary for Register CM_GMAC_GMAC_CLKCTRL ..............................................
CM_L3INIT_OCP2SCP1_CLKCTRL ...................................................................................
CM_L3INIT_OCP2SCP3_CLKCTRL ...................................................................................
CM_L3INIT_USB_OTG_SS1_CLKCTRL ..............................................................................
L4PER_CM_CORE Registers Mapping Summary ...................................................................
CM_L4PER_CLKSTCTRL ...............................................................................................
Register Call Summary for Register CM_L4PER_CLKSTCTRL ...................................................
CM_L4PER_DYNAMICDEP.............................................................................................
Register Call Summary for Register CM_L4PER_DYNAMICDEP .................................................
CM_L4PER2_L4_PER2_CLKCTRL ....................................................................................
3-801. Register Call Summary for Register CM_GMAC_STATICDEP
814
3-802.
814
3-803.
3-804.
3-805.
3-806.
3-807.
3-808.
3-809.
3-810.
3-811.
3-812.
3-813.
3-814.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
815
815
816
816
817
818
819
821
823
823
824
824
95
www.ti.com
3-815. Register Call Summary for Register CM_L4PER2_L4_PER2_CLKCTRL ........................................ 825
3-816. CM_L4PER3_L4_PER3_CLKCTRL .................................................................................... 825
3-817. Register Call Summary for Register CM_L4PER3_L4_PER3_CLKCTRL ........................................ 825
826
3-819.
826
3-820.
3-821.
3-822.
3-823.
3-824.
3-825.
3-826.
3-827.
3-828.
3-829.
3-830.
3-831.
3-832.
3-833.
3-834.
3-835.
3-836.
3-837.
3-838.
3-839.
3-840.
3-841.
3-842.
3-843.
3-844.
3-845.
3-846.
3-847.
3-848.
3-849.
3-850.
3-851.
3-852.
3-853.
3-854.
3-855.
3-856.
3-857.
3-858.
3-859.
3-860.
3-861.
3-862.
3-863.
96
....................................................................................
CM_L4PER2_PRUSS2_CLKCTRL ....................................................................................
CM_L4PER_DCC6_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L4PER_DCC6_CLKCTRL ..............................................
CM_L4PER_DCC7_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L4PER_DCC7_CLKCTRL ..............................................
CM_L4PER_TIMER2_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4PER_TIMER2_CLKCTRL ...........................................
CM_L4PER_TIMER3_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4PER_TIMER3_CLKCTRL ...........................................
CM_L4PER_TIMER4_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4PER_TIMER4_CLKCTRL ...........................................
CM_L4PER_DCC5_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L4PER_DCC5_CLKCTRL ..............................................
CM_L4PER_ELM_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_L4PER_ELM_CLKCTRL ................................................
CM_L4PER_GPIO2_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_GPIO2_CLKCTRL .............................................
CM_L4PER_GPIO3_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_GPIO3_CLKCTRL .............................................
CM_L4PER_GPIO4_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_GPIO4_CLKCTRL .............................................
CM_L4PER_GPIO5_CLKCTRL ........................................................................................
CM_L4PER_GPIO6_CLKCTRL ........................................................................................
CM_L4PER_ESM_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_L4PER_ESM_CLKCTRL ...............................................
CM_L4PER2_PWMSS2_CLKCTRL....................................................................................
CM_L4PER2_PWMSS3_CLKCTRL....................................................................................
CM_L4PER_I2C1_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_L4PER_I2C1_CLKCTRL................................................
CM_L4PER_I2C2_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_L4PER_I2C2_CLKCTRL................................................
CM_L4PER_I2C3_CLKCTRL ...........................................................................................
CM_L4PER_I2C4_CLKCTRL ...........................................................................................
CM_L4PER_L4_PER1_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L4PER_L4_PER1_CLKCTRL ..........................................
CM_L4PER2_PWMSS1_CLKCTRL....................................................................................
Register Call Summary for Register CM_L4PER2_PWMSS1_CLKCTRL ........................................
CM_L4PER3_DCC1_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER3_DCC1_CLKCTRL ............................................
CM_L4PER3_DCC2_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER3_DCC2_CLKCTRL ............................................
CM_L4PER3_DCC3_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER3_DCC3_CLKCTRL ............................................
CM_L4PER_MCSPI1_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4PER_MCSPI1_CLKCTRL ...........................................
3-818. CM_L4PER2_PRUSS1_CLKCTRL
List of Tables
827
828
828
829
830
831
831
832
832
833
833
834
834
835
835
836
836
837
837
838
838
839
840
841
841
841
842
843
843
844
844
845
845
846
846
847
847
848
848
849
850
851
851
851
SPRUIC6B – January 2017 – Revised October 2017
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www.ti.com
3-864. CM_L4PER_MCSPI2_CLKCTRL ....................................................................................... 852
3-865. Register Call Summary for Register CM_L4PER_MCSPI2_CLKCTRL ........................................... 852
3-866. CM_L4PER_MCSPI3_CLKCTRL ....................................................................................... 852
3-867. Register Call Summary for Register CM_L4PER_MCSPI3_CLKCTRL ........................................... 853
3-868. CM_L4PER_MCSPI4_CLKCTRL ....................................................................................... 853
3-869. Register Call Summary for Register CM_L4PER_MCSPI4_CLKCTRL ........................................... 854
........................................................................................
........................................................................................
CM_L4PER_MMC3_CLKCTRL .........................................................................................
CM_L4PER_MMC4_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L4PER_MMC4_CLKCTRL .............................................
CM_L4PER3_DCC4_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER3_DCC4_CLKCTRL ............................................
CM_L4PER2_QSPI_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L4PER2_QSPI_CLKCTRL .............................................
CM_L4PER_UART1_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_UART1_CLKCTRL ............................................
CM_L4PER_UART2_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_UART2_CLKCTRL ............................................
CM_L4PER_UART3_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_UART3_CLKCTRL ............................................
CM_L4PER_UART4_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_UART4_CLKCTRL ............................................
CM_L4PER2_ADC_CLKCTRL..........................................................................................
Register Call Summary for Register CM_L4PER2_ADC_CLKCTRL ..............................................
CM_L4PER2_ATL_CLKCTRL ..........................................................................................
Register Call Summary for Register CM_L4PER2_ATL_CLKCTRL ...............................................
CM_L4PER_UART5_CLKCTRL ........................................................................................
CM_L4PER2_MCASP5_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER2_MCASP5_CLKCTRL .........................................
CM_L4SEC_CLKSTCTRL ...............................................................................................
CM_L4SEC_STATICDEP ...............................................................................................
CM_L4SEC_DYNAMICDEP.............................................................................................
CM_L4PER2_MCASP8_CLKCTRL ....................................................................................
CM_L4PER2_MCASP4_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER2_MCASP4_CLKCTRL .........................................
CM_L4SEC_AES1_CLKCTRL ..........................................................................................
CM_L4SEC_AES2_CLKCTRL ..........................................................................................
CM_L4SEC_DES3DES_CLKCTRL ....................................................................................
CM_L4SEC_FPKA_CLKCTRL ..........................................................................................
CM_L4SEC_RNG_CLKCTRL ...........................................................................................
CM_L4SEC_SHA2MD51_CLKCTRL ..................................................................................
CM_L4PER2_UART7_CLKCTRL ......................................................................................
CM_L4SEC_DMA_CRYPTO_CLKCTRL ..............................................................................
CM_L4PER2_UART8_CLKCTRL ......................................................................................
CM_L4PER2_UART9_CLKCTRL ......................................................................................
CM_L4PER2_DCAN2_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER2_DCAN2_CLKCTRL ...........................................
CM_L4SEC_SHA2MD52_CLKCTRL ..................................................................................
3-870. CM_L4PER_GPIO7_CLKCTRL
854
3-871. CM_L4PER_GPIO8_CLKCTRL
855
3-872.
856
3-873.
3-874.
3-875.
3-876.
3-877.
3-878.
3-879.
3-880.
3-881.
3-882.
3-883.
3-884.
3-885.
3-886.
3-887.
3-888.
3-889.
3-890.
3-891.
3-892.
3-893.
3-894.
3-895.
3-896.
3-897.
3-898.
3-899.
3-900.
3-901.
3-902.
3-903.
3-904.
3-905.
3-906.
3-907.
3-908.
3-909.
3-910.
3-911.
3-912.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
857
858
858
859
859
860
860
861
861
862
862
863
863
864
864
866
866
867
868
868
870
870
871
871
872
873
875
875
875
876
877
877
878
879
880
880
881
882
883
883
97
www.ti.com
3-913. CM_L4PER2_CLKSTCTRL ............................................................................................. 884
3-914. Register Call Summary for Register CM_L4PER2_CLKSTCTRL .................................................. 887
3-915. CM_L4PER2_DYNAMICDEP ........................................................................................... 887
3-916. Register Call Summary for Register CM_L4PER2_DYNAMICDEP................................................ 887
3-917. CM_L4PER2_MCASP6_CLKCTRL .................................................................................... 888
3-918. Register Call Summary for Register CM_L4PER2_MCASP6_CLKCTRL ......................................... 889
3-919. CM_L4PER2_MCASP7_CLKCTRL .................................................................................... 889
3-920. Register Call Summary for Register CM_L4PER2_MCASP7_CLKCTRL ......................................... 891
3-921. CM_L4PER2_STATICDEP .............................................................................................. 891
3-922. Register Call Summary for Register CM_L4PER2_STATICDEP
..................................................
891
3-923. CM_L4PER3_CLKSTCTRL ............................................................................................. 892
3-924. Register Call Summary for Register CM_L4PER3_CLKSTCTRL .................................................. 893
3-925. CM_L4PER3_DYNAMICDEP ........................................................................................... 893
3-926. Register Call Summary for Register CM_L4PER3_DYNAMICDEP................................................ 894
3-927. OCP_SOCKET_CM_CORE Registers Mapping Summary ......................................................... 894
894
3-929.
895
3-930.
3-931.
3-932.
3-933.
3-934.
3-935.
3-936.
3-937.
3-938.
3-939.
3-940.
3-941.
3-942.
3-943.
3-944.
3-945.
3-946.
3-947.
3-948.
3-949.
3-950.
3-951.
3-952.
3-953.
3-954.
3-955.
3-956.
3-957.
3-958.
3-959.
3-960.
3-961.
98
..................................................................................................
Register Call Summary for Register REVISION_CM_CORE .......................................................
CM_CM_CORE_PROFILING_CLKCTRL .............................................................................
Register Call Summary for Register CM_CM_CORE_PROFILING_CLKCTRL ..................................
CM_CORE_DEBUG_CFG ..............................................................................................
Register Call Summary for Register CM_CORE_DEBUG_CFG ...................................................
RESTORE_CM_CORE Registers Mapping Summary...............................................................
CM_L3MAIN1_CLKSTCTRL_RESTORE..............................................................................
Register Call Summary for Register CM_L3MAIN1_CLKSTCTRL_RESTORE ..................................
CM_L4CFG_CLKSTCTRL_RESTORE ................................................................................
Register Call Summary for Register CM_L4CFG_CLKSTCTRL_RESTORE .....................................
CM_L4PER_CLKSTCTRL_RESTORE ................................................................................
Register Call Summary for Register CM_L4PER_CLKSTCTRL_RESTORE .....................................
CM_L3INIT_CLKSTCTRL_RESTORE .................................................................................
Register Call Summary for Register CM_L3INIT_CLKSTCTRL_RESTORE .....................................
CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE .................................................................
Register Call Summary for Register CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE ......................
CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE ...................................................................
Register Call Summary for Register CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE........................
CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE ............................................................
Register Call Summary for Register CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE .................
CM_CM_CORE_PROFILING_CLKCTRL_RESTORE ...............................................................
Register Call Summary for Register CM_CM_CORE_PROFILING_CLKCTRL_RESTORE ...................
CM_L3MAIN1_DYNAMICDEP_RESTORE ...........................................................................
Register Call Summary for Register CM_L3MAIN1_DYNAMICDEP_RESTORE ................................
CM_L4CFG_DYNAMICDEP_RESTORE ..............................................................................
Register Call Summary for Register CM_L4CFG_DYNAMICDEP_RESTORE ..................................
CM_L4PER_DYNAMICDEP_RESTORE ..............................................................................
Register Call Summary for Register CM_L4PER_DYNAMICDEP_RESTORE...................................
CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE .............................................................
CM_DMA_STATICDEP_RESTORE ...................................................................................
Register Call Summary for Register CM_DMA_STATICDEP_RESTORE ........................................
SMARTREFLEX_CORE Registers Mapping Summary .............................................................
SRCONFIG ................................................................................................................
3-928. REVISION_CM_CORE
List of Tables
895
895
896
896
896
897
897
897
897
897
898
898
898
898
898
898
899
899
899
899
899
900
900
900
900
900
901
901
901
901
901
902
SPRUIC6B – January 2017 – Revised October 2017
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3-962. SRSTATUS ................................................................................................................ 903
3-963. SENVAL .................................................................................................................... 903
3-964. SENMIN .................................................................................................................... 903
3-965. SENMAX ................................................................................................................... 904
3-966. SENAVG ................................................................................................................... 904
3-967. AVGWEIGHT .............................................................................................................. 904
3-968. NVALUERECIPROCAL .................................................................................................. 905
3-969. IRQ_EOI
...................................................................................................................
905
3-970. IRQSTATUS_RAW ....................................................................................................... 905
3-971. IRQSTATUS ............................................................................................................... 906
3-972. IRQENABLE_SET ........................................................................................................ 907
3-973. IRQENABLE_CLR ........................................................................................................ 907
3-974. SENERROR ............................................................................................................... 908
3-975. ERRCONFIG .............................................................................................................. 908
3-976. CAM_PRM Registers Mapping Summary ............................................................................. 909
................................................................................................
3-978. Register Call Summary for Register PM_CAM_PWRSTCTRL .....................................................
3-979. PM_CAM_PWRSTST ....................................................................................................
3-980. Register Call Summary for Register PM_CAM_PWRSTST.........................................................
3-981. PM_CAM_VIP1_WKDEP ................................................................................................
3-982. Register Call Summary for Register PM_CAM_VIP1_WKDEP.....................................................
3-983. RM_CAM_VIP1_CONTEXT .............................................................................................
3-984. Register Call Summary for Register RM_CAM_VIP1_CONTEXT .................................................
3-985. PM_CAM_VIP2_WKDEP ................................................................................................
3-986. Register Call Summary for Register PM_CAM_VIP2_WKDEP.....................................................
3-987. RM_CAM_VIP2_CONTEXT .............................................................................................
3-988. Register Call Summary for Register RM_CAM_VIP2_CONTEXT .................................................
3-989. PM_CAM_VIP3_WKDEP ................................................................................................
3-990. Register Call Summary for Register PM_CAM_VIP3_WKDEP.....................................................
3-991. RM_CAM_VIP3_CONTEXT .............................................................................................
3-992. Register Call Summary for Register RM_CAM_VIP3_CONTEXT .................................................
3-993. RM_CAM_LVDSRX_CONTEXT ........................................................................................
3-994. Register Call Summary for Register RM_CAM_LVDSRX_CONTEXT ............................................
3-995. RM_CAM_CSI1_CONTEXT .............................................................................................
3-996. Register Call Summary for Register RM_CAM_CSI1_CONTEXT .................................................
3-997. RM_CAM_CSI2_CONTEXT .............................................................................................
3-998. Register Call Summary for Register RM_CAM_CSI2_CONTEXT .................................................
3-999. CKGEN_PRM Registers Mapping Summary .........................................................................
3-1000. CM_CLKSEL_SYSCLK1 ...............................................................................................
3-1001. Register Call Summary for Register CM_CLKSEL_SYSCLK1 ....................................................
3-1002. CM_CLKSEL_WKUPAON .............................................................................................
3-1003. Register Call Summary for Register CM_CLKSEL_WKUPAON ..................................................
3-1004. CM_CLKSEL_ABE_PLL_REF .........................................................................................
3-1005. CM_CLKSEL_SYS ......................................................................................................
3-1006. Register Call Summary for Register CM_CLKSEL_SYS ..........................................................
3-1007. CM_CLKSEL_ABE_PLL_BYPAS .....................................................................................
3-1008. CM_CLKSEL_ABE_PLL_SYS .........................................................................................
3-1009. CM_CLKSEL_ABE_24M ...............................................................................................
3-1010. Register Call Summary for Register CM_CLKSEL_ABE_24M ....................................................
3-977. PM_CAM_PWRSTCTRL
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
909
910
910
911
912
913
913
913
914
915
915
915
916
917
917
917
918
918
918
919
919
919
919
921
921
921
921
922
922
922
923
923
923
924
99
www.ti.com
3-1011. CM_CLKSEL_ABE_SYS ............................................................................................... 924
3-1012. Register Call Summary for Register CM_CLKSEL_ABE_SYS.................................................... 924
3-1013. CM_CLKSEL_HDMI_MCASP_AUX
..................................................................................
924
3-1014. Register Call Summary for Register CM_CLKSEL_HDMI_MCASP_AUX ....................................... 925
3-1015. CM_CLKSEL_HDMI_TIMER........................................................................................... 925
3-1016. Register Call Summary for Register CM_CLKSEL_HDMI_TIMER ............................................... 925
3-1017. CM_CLKSEL_MCASP_SYS ........................................................................................... 926
3-1018. Register Call Summary for Register CM_CLKSEL_MCASP_SYS
...............................................
926
3-1019. CM_CLKSEL_MLBP_MCASP ......................................................................................... 926
3-1020. Register Call Summary for Register CM_CLKSEL_MLBP_MCASP
.............................................
927
3-1021. CM_CLKSEL_MLB_MCASP ........................................................................................... 927
3-1022. Register Call Summary for Register CM_CLKSEL_MLB_MCASP ............................................... 927
3-1023. CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX
.............................................................
927
3-1024. Register Call Summary for Register CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX .................. 928
3-1025. CM_CLKSEL_SYS_CLK1_32K
.......................................................................................
928
3-1026. Register Call Summary for Register CM_CLKSEL_SYS_CLK1_32K ............................................ 928
3-1027. CM_CLKSEL_TIMER_SYS ............................................................................................ 928
3-1028. Register Call Summary for Register CM_CLKSEL_TIMER_SYS................................................. 929
3-1029. CM_CLKSEL_VIDEO1_MCASP_AUX ............................................................................... 929
3-1030. Register Call Summary for Register CM_CLKSEL_VIDEO1_MCASP_AUX .................................... 929
3-1031. CM_CLKSEL_VIDEO1_TIMER........................................................................................ 930
3-1032. Register Call Summary for Register CM_CLKSEL_VIDEO1_TIMER ............................................ 930
3-1033. CM_CLKSEL_VIDEO2_MCASP_AUX ............................................................................... 930
3-1034. Register Call Summary for Register CM_CLKSEL_VIDEO2_MCASP_AUX .................................... 931
3-1035. CM_CLKSEL_VIDEO2_TIMER........................................................................................ 931
3-1036. Register Call Summary for Register CM_CLKSEL_VIDEO2_TIMER ............................................ 931
3-1037. CM_CLKSEL_CLKOUTMUX0 ......................................................................................... 932
3-1038. Register Call Summary for Register CM_CLKSEL_CLKOUTMUX0
.............................................
933
3-1039. CM_CLKSEL_CLKOUTMUX1 ......................................................................................... 934
3-1040. Register Call Summary for Register CM_CLKSEL_CLKOUTMUX1
.............................................
936
3-1041. CM_CLKSEL_CLKOUTMUX2 ......................................................................................... 936
3-1042. Register Call Summary for Register CM_CLKSEL_CLKOUTMUX2
.............................................
938
3-1043. CM_CLKSEL_HDMI_PLL_SYS ....................................................................................... 938
3-1044. CM_CLKSEL_VIDEO1_PLL_SYS .................................................................................... 938
3-1045. CM_CLKSEL_VIDEO2_PLL_SYS .................................................................................... 938
3-1046. CM_CLKSEL_ABE_CLK_DIV ......................................................................................... 939
3-1047. Register Call Summary for Register CM_CLKSEL_ABE_CLK_DIV .............................................. 939
3-1048. CM_CLKSEL_ABE_GICLK_DIV
......................................................................................
939
3-1049. Register Call Summary for Register CM_CLKSEL_ABE_GICLK_DIV ........................................... 940
3-1050. CM_CLKSEL_AESS_FCLK_DIV ...................................................................................... 940
3-1051. Register Call Summary for Register CM_CLKSEL_AESS_FCLK_DIV .......................................... 940
3-1052. CM_CLKSEL_EVE_CLK ............................................................................................... 940
3-1053. Register Call Summary for Register CM_CLKSEL_EVE_CLK .................................................... 941
3-1054. CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX ..................................................................... 941
3-1055. Register Call Summary for Register CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX .......................... 941
3-1056. CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX ........................................................... 941
3-1057. Register Call Summary for Register CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX
...............
942
3-1058. CM_CLKSEL_DSP_GFCLK_CLKOUTMUX ......................................................................... 942
3-1059. Register Call Summary for Register CM_CLKSEL_DSP_GFCLK_CLKOUTMUX
100
List of Tables
.............................
943
SPRUIC6B – January 2017 – Revised October 2017
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3-1060. CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX................................................................... 943
3-1061. Register Call Summary for Register CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX ....................... 943
3-1062. CM_CLKSEL_EMU_CLK_CLKOUTMUX ............................................................................ 943
3-1063. Register Call Summary for Register CM_CLKSEL_EMU_CLK_CLKOUTMUX ................................. 944
3-1064. CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX............................................................. 944
3-1065. Register Call Summary for Register CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX ................. 944
3-1066. CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX .................................................................. 945
3-1067. Register Call Summary for Register CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX
......................
945
3-1068. CM_CLKSEL_GPU_GCLK_CLKOUTMUX .......................................................................... 945
3-1069. Register Call Summary for Register CM_CLKSEL_GPU_GCLK_CLKOUTMUX ............................... 946
3-1070. CM_CLKSEL_HDMI_CLK_CLKOUTMUX ........................................................................... 946
3-1071. Register Call Summary for Register CM_CLKSEL_HDMI_CLK_CLKOUTMUX ................................ 946
3-1072. CM_CLKSEL_IVA_GCLK_CLKOUTMUX ............................................................................ 946
3-1073. Register Call Summary for Register CM_CLKSEL_IVA_GCLK_CLKOUTMUX ................................ 947
3-1074. CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX .............................................................. 947
3-1075. Register Call Summary for Register CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX ................... 947
3-1076. CM_CLKSEL_MPU_GCLK_CLKOUTMUX .......................................................................... 948
3-1077. Register Call Summary for Register CM_CLKSEL_MPU_GCLK_CLKOUTMUX ............................... 948
..........................................................................
Register Call Summary for Register CM_CLKSEL_PCIE1_CLK_CLKOUTMUX ...............................
CM_CLKSEL_PCIE2_CLK_CLKOUTMUX ..........................................................................
Register Call Summary for Register CM_CLKSEL_PCIE2_CLK_CLKOUTMUX ...............................
CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX .................................................................
Register Call Summary for Register CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX .....................
CM_CLKSEL_SATA_CLK_CLKOUTMUX ...........................................................................
Register Call Summary for Register CM_CLKSEL_SATA_CLK_CLKOUTMUX ................................
CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX .................................................................
Register Call Summary for Register CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX .....................
CM_CLKSEL_SYS_CLK1_CLKOUTMUX ...........................................................................
Register Call Summary for Register CM_CLKSEL_SYS_CLK1_CLKOUTMUX ................................
CM_CLKSEL_SYS_CLK2_CLKOUTMUX ...........................................................................
Register Call Summary for Register CM_CLKSEL_SYS_CLK2_CLKOUTMUX ................................
CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX ........................................................................
Register Call Summary for Register CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX .............................
CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX ........................................................................
Register Call Summary for Register CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX .............................
CM_CLKSEL_ABE_LP_CLK ..........................................................................................
Register Call Summary for Register CM_CLKSEL_ABE_LP_CLK ...............................................
CM_CLKSEL_ADC_GFCLK ...........................................................................................
CM_CLKSEL_EVE_GFCLK_CLKOUTMUX .........................................................................
Register Call Summary for Register CM_CLKSEL_EVE_GFCLK_CLKOUTMUX..............................
COREAON_PRM Registers Mapping Summary ....................................................................
PM_COREAON_SMARTREFLEX_MPU_WKDEP .................................................................
RM_COREAON_SMARTREFLEX_MPU_CONTEXT ..............................................................
PM_COREAON_SMARTREFLEX_CORE_WKDEP................................................................
RM_COREAON_SMARTREFLEX_CORE_CONTEXT ............................................................
PM_COREAON_SMARTREFLEX_GPU_WKDEP..................................................................
RM_COREAON_SMARTREFLEX_GPU_CONTEXT ..............................................................
PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP ............................................................
3-1078. CM_CLKSEL_PCIE1_CLK_CLKOUTMUX
3-1079.
3-1080.
3-1081.
3-1082.
3-1083.
3-1084.
3-1085.
3-1086.
3-1087.
3-1088.
3-1089.
3-1090.
3-1091.
3-1092.
3-1093.
3-1094.
3-1095.
3-1096.
3-1097.
3-1098.
3-1099.
3-1100.
3-1101.
3-1102.
3-1103.
3-1104.
3-1105.
3-1106.
3-1107.
3-1108.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
948
949
949
949
949
950
950
950
951
951
951
952
952
952
953
953
953
954
954
954
954
955
955
955
956
957
958
959
960
961
961
101
www.ti.com
3-1109. RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT ......................................................... 963
3-1110. PM_COREAON_SMARTREFLEX_IVAHD_WKDEP ............................................................... 963
3-1111. RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT ............................................................ 965
3-1112. RM_COREAON_DUMMY_MODULE1_CONTEXT ................................................................. 965
3-1113. RM_COREAON_DUMMY_MODULE2_CONTEXT ................................................................. 966
3-1114. RM_COREAON_DUMMY_MODULE3_CONTEXT ................................................................. 966
3-1115. RM_COREAON_DUMMY_MODULE4_CONTEXT ................................................................. 967
3-1116. CORE_PRM Registers Mapping Summary .......................................................................... 967
3-1117. PM_CORE_PWRSTCTRL ............................................................................................. 969
3-1118. Register Call Summary for Register PM_CORE_PWRSTCTRL .................................................. 970
3-1119. PM_CORE_PWRSTST ................................................................................................. 970
3-1120. Register Call Summary for Register PM_CORE_PWRSTST
.....................................................
972
3-1121. RM_L3MAIN1_L3_MAIN_1_CONTEXT .............................................................................. 972
972
3-1123.
973
3-1124.
3-1125.
3-1126.
3-1127.
3-1128.
3-1129.
3-1130.
3-1131.
3-1132.
3-1133.
3-1134.
3-1135.
3-1136.
3-1137.
3-1138.
3-1139.
3-1140.
3-1141.
3-1142.
3-1143.
3-1144.
3-1145.
3-1146.
3-1147.
3-1148.
3-1149.
3-1150.
3-1151.
3-1152.
3-1153.
3-1154.
3-1155.
3-1156.
3-1157.
102
..................................
RM_L3MAIN1_GPMC_CONTEXT ....................................................................................
Register Call Summary for Register RM_L3MAIN1_GPMC_CONTEXT ........................................
RM_L3MAIN1_MMU_EDMA_CONTEXT ............................................................................
Register Call Summary for Register RM_L3MAIN1_MMU_EDMA_CONTEXT .................................
RM_L3MAIN1_MMU_PCIESS_CONTEXT ..........................................................................
PM_L3MAIN1_OCMC_RAM1_WKDEP ..............................................................................
Register Call Summary for Register PM_L3MAIN1_OCMC_RAM1_WKDEP ..................................
RM_L3MAIN1_OCMC_RAM1_CONTEXT ...........................................................................
Register Call Summary for Register RM_L3MAIN1_OCMC_RAM1_CONTEXT ...............................
PM_L3MAIN1_TESOC_WKDEP ......................................................................................
Register Call Summary for Register PM_L3MAIN1_TESOC_WKDEP ..........................................
RM_L3MAIN1_TESOC_CONTEXT ...................................................................................
Register Call Summary for Register RM_L3MAIN1_TESOC_CONTEXT .......................................
PM_L3MAIN1_OCMC_RAM3_WKDEP ..............................................................................
RM_L3MAIN1_OCMC_RAM3_CONTEXT ...........................................................................
RM_L3MAIN1_OCMC_ROM_CONTEXT ............................................................................
PM_L3MAIN1_TPCC_WKDEP ........................................................................................
Register Call Summary for Register PM_L3MAIN1_TPCC_WKDEP ............................................
RM_L3MAIN1_TPCC_CONTEXT .....................................................................................
Register Call Summary for Register RM_L3MAIN1_TPCC_CONTEXT .........................................
PM_L3MAIN1_TPTC1_WKDEP .......................................................................................
Register Call Summary for Register PM_L3MAIN1_TPTC1_WKDEP ...........................................
RM_L3MAIN1_TPTC1_CONTEXT....................................................................................
Register Call Summary for Register RM_L3MAIN1_TPTC1_CONTEXT ........................................
PM_L3MAIN1_TPTC2_WKDEP .......................................................................................
Register Call Summary for Register PM_L3MAIN1_TPTC2_WKDEP ...........................................
RM_L3MAIN1_TPTC2_CONTEXT....................................................................................
Register Call Summary for Register RM_L3MAIN1_TPTC2_CONTEXT ........................................
RM_L3MAIN1_VCP1_CONTEXT .....................................................................................
Register Call Summary for Register RM_L3MAIN1_VCP1_CONTEXT..........................................
RM_L3MAIN1_VCP2_CONTEXT .....................................................................................
Register Call Summary for Register RM_L3MAIN1_VCP2_CONTEXT..........................................
RM_L3MAIN1_SPARE_CME_CONTEXT ...........................................................................
RM_L3MAIN1_SPARE_HDMI_CONTEXT...........................................................................
RM_L3MAIN1_SPARE_ICM_CONTEXT ............................................................................
3-1122. Register Call Summary for Register RM_L3MAIN1_L3_MAIN_1_CONTEXT
List of Tables
973
973
974
974
974
976
976
976
977
978
978
979
979
980
981
981
982
983
983
983
985
985
985
986
987
987
987
988
988
988
989
989
989
990
SPRUIC6B – January 2017 – Revised October 2017
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www.ti.com
3-1158. RM_L3MAIN1_SPARE_IVA2_CONTEXT............................................................................ 990
3-1159. RM_L3MAIN1_SPARE_SATA2_CONTEXT ......................................................................... 991
3-1160. RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT .................................................................. 991
3-1161. RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT .................................................................. 992
3-1162. RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT .................................................................. 992
3-1163. RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT ................................................................... 993
3-1164. RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT ................................................................... 993
3-1165. RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT ................................................................... 994
3-1166. RM_IPU2_RSTCTRL ................................................................................................... 994
3-1167. RM_IPU2_RSTST ....................................................................................................... 995
3-1168. RM_IPU2_IPU2_CONTEXT ........................................................................................... 996
3-1169. RM_DMA_DMA_SYSTEM_CONTEXT ............................................................................... 997
.......................................................................................... 997
............................................................................. 998
Register Call Summary for Register RM_EMIF_EMIF_OCP_FW_CONTEXT .................................. 998
RM_EMIF_EMIF1_CONTEXT ......................................................................................... 998
Register Call Summary for Register RM_EMIF_EMIF1_CONTEXT ............................................. 999
RM_EMIF_EMIF2_CONTEXT ......................................................................................... 999
Register Call Summary for Register RM_EMIF_EMIF2_CONTEXT ............................................ 1000
RM_EMIF_EMIF_DLL_CONTEXT .................................................................................. 1000
Register Call Summary for Register RM_EMIF_EMIF_DLL_CONTEXT ....................................... 1000
RM_CRC_CRC_CONTEXT .......................................................................................... 1000
Register Call Summary for Register RM_CRC_CRC_CONTEXT ............................................... 1001
RM_L4CFG_L4_CFG_CONTEXT ................................................................................... 1001
Register Call Summary for Register RM_L4CFG_L4_CFG_CONTEXT ....................................... 1002
RM_L4CFG_SPINLOCK_CONTEXT ............................................................................... 1002
Register Call Summary for Register RM_L4CFG_SPINLOCK_CONTEXT .................................... 1002
RM_L4CFG_MAILBOX1_CONTEXT ................................................................................ 1002
Register Call Summary for Register RM_L4CFG_MAILBOX1_CONTEXT .................................... 1003
RM_L4CFG_SAR_ROM_CONTEXT ................................................................................ 1003
RM_L4CFG_OCP2SCP2_CONTEXT ............................................................................... 1003
RM_L4CFG_MAILBOX2_CONTEXT ................................................................................ 1004
Register Call Summary for Register RM_L4CFG_MAILBOX2_CONTEXT .................................... 1004
RM_L4CFG_MAILBOX3_CONTEXT ................................................................................ 1005
RM_L4CFG_MAILBOX4_CONTEXT ................................................................................ 1005
RM_L4CFG_MAILBOX5_CONTEXT ................................................................................ 1006
RM_L4CFG_MAILBOX6_CONTEXT ................................................................................ 1006
RM_L4CFG_MAILBOX7_CONTEXT ................................................................................ 1007
RM_L4CFG_MAILBOX8_CONTEXT ................................................................................ 1007
RM_L4CFG_MAILBOX9_CONTEXT ................................................................................ 1008
RM_L4CFG_MAILBOX10_CONTEXT .............................................................................. 1008
RM_L4CFG_MAILBOX11_CONTEXT .............................................................................. 1009
RM_L4CFG_MAILBOX12_CONTEXT .............................................................................. 1009
RM_L4CFG_MAILBOX13_CONTEXT .............................................................................. 1010
RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT ....................................................... 1010
RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT ................................................... 1011
RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT ..................................................... 1011
RM_L4CFG_IO_DELAY_BLOCK_CONTEXT ..................................................................... 1012
RM_L3INSTR_L3_MAIN_2_CONTEXT ............................................................................ 1012
3-1170. RM_EMIF_DMM_CONTEXT
3-1171. RM_EMIF_EMIF_OCP_FW_CONTEXT
3-1172.
3-1173.
3-1174.
3-1175.
3-1176.
3-1177.
3-1178.
3-1179.
3-1180.
3-1181.
3-1182.
3-1183.
3-1184.
3-1185.
3-1186.
3-1187.
3-1188.
3-1189.
3-1190.
3-1191.
3-1192.
3-1193.
3-1194.
3-1195.
3-1196.
3-1197.
3-1198.
3-1199.
3-1200.
3-1201.
3-1202.
3-1203.
3-1204.
3-1205.
3-1206.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
103
www.ti.com
3-1207. Register Call Summary for Register RM_L3INSTR_L3_MAIN_2_CONTEXT ................................. 1013
3-1208. RM_L3INSTR_L3_INSTR_CONTEXT .............................................................................. 1013
3-1209. Register Call Summary for Register RM_L3INSTR_L3_INSTR_CONTEXT ................................... 1013
3-1210. RM_L3INSTR_OCP_WP_NOC_CONTEXT........................................................................ 1013
3-1211. Register Call Summary for Register RM_L3INSTR_OCP_WP_NOC_CONTEXT ............................ 1014
3-1212. CUSTEFUSE_PRM Registers Mapping Summary ................................................................ 1014
3-1213. PM_CUSTEFUSE_PWRSTCTRL ................................................................................... 1015
3-1214. Register Call Summary for Register PM_CUSTEFUSE_PWRSTCTRL ........................................ 1015
3-1215. PM_CUSTEFUSE_PWRSTST ....................................................................................... 1015
3-1216. Register Call Summary for Register PM_CUSTEFUSE_PWRSTST
...........................................
1016
3-1217. RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT ........................................................... 1016
3-1218. Register Call Summary for Register RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT ................ 1017
3-1219. DEVICE_PRM Registers Mapping Summary ...................................................................... 1017
1019
3-1221.
1019
3-1222.
3-1223.
3-1224.
3-1225.
3-1226.
3-1227.
3-1228.
3-1229.
3-1230.
3-1231.
3-1232.
3-1233.
3-1234.
3-1235.
3-1236.
3-1237.
3-1238.
3-1239.
3-1240.
3-1241.
3-1242.
3-1243.
3-1244.
3-1245.
3-1246.
3-1247.
3-1248.
3-1249.
3-1250.
3-1251.
3-1252.
3-1253.
3-1254.
3-1255.
104
.......................................................................................................
Register Call Summary for Register PRM_RSTCTRL ............................................................
PRM_RSTST ...........................................................................................................
Register Call Summary for Register PRM_RSTST................................................................
PRM_RSTTIME ........................................................................................................
Register Call Summary for Register PRM_RSTTIME.............................................................
PRM_CLKREQCTRL ..................................................................................................
PRM_VOLTCTRL ......................................................................................................
PRM_PWRREQCTRL .................................................................................................
PRM_PSCON_COUNT ...............................................................................................
Register Call Summary for Register PRM_PSCON_COUNT ....................................................
PRM_IO_COUNT ......................................................................................................
Register Call Summary for Register PRM_IO_COUNT ..........................................................
PRM_IO_PMCTRL ....................................................................................................
Register Call Summary for Register PRM_IO_PMCTRL .........................................................
PRM_VOLTSETUP_WARMRESET .................................................................................
PRM_VOLTSETUP_CORE_OFF ....................................................................................
PRM_VOLTSETUP_MPU_OFF .....................................................................................
PRM_VOLTSETUP_MM_OFF .......................................................................................
PRM_VOLTSETUP_CORE_RET_SLEEP .........................................................................
PRM_VOLTSETUP_MPU_RET_SLEEP ...........................................................................
PRM_VOLTSETUP_MM_RET_SLEEP .............................................................................
PRM_VP_CORE_CONFIG ...........................................................................................
PRM_VP_CORE_STATUS ...........................................................................................
PRM_VP_CORE_VLIMITTO .........................................................................................
PRM_VP_CORE_VOLTAGE .........................................................................................
PRM_VP_CORE_VSTEPMAX .......................................................................................
PRM_VP_CORE_VSTEPMIN ........................................................................................
PRM_VP_MPU_CONFIG .............................................................................................
PRM_VP_MPU_STATUS .............................................................................................
PRM_VP_MPU_VLIMITTO ...........................................................................................
PRM_VP_MPU_VOLTAGE...........................................................................................
PRM_VP_MPU_VSTEPMAX .........................................................................................
PRM_VP_MPU_VSTEPMIN..........................................................................................
PRM_VP_MM_CONFIG ..............................................................................................
PRM_VP_MM_STATUS ..............................................................................................
3-1220. PRM_RSTCTRL
List of Tables
1020
1021
1021
1022
1022
1023
1024
1025
1025
1025
1026
1026
1027
1027
1027
1028
1029
1030
1031
1032
1033
1034
1034
1035
1035
1035
1036
1037
1037
1037
1038
1038
1038
1039
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
............................................................................................
PRM_VP_MM_VOLTAGE ............................................................................................
PRM_VP_MM_VSTEPMAX ..........................................................................................
PRM_VP_MM_VSTEPMIN ...........................................................................................
PRM_VC_SMPS_CORE_CONFIG ..................................................................................
PRM_VC_SMPS_MM_CONFIG .....................................................................................
PRM_VC_SMPS_MPU_CONFIG....................................................................................
PRM_VC_VAL_CMD_VDD_CORE_L ..............................................................................
PRM_VC_VAL_CMD_VDD_MM_L ..................................................................................
PRM_VC_VAL_CMD_VDD_MPU_L ................................................................................
PRM_VC_VAL_BYPASS .............................................................................................
PRM_VC_CORE_ERRST ............................................................................................
PRM_VC_MM_ERRST................................................................................................
PRM_VC_MPU_ERRST ..............................................................................................
PRM_VC_BYPASS_ERRST .........................................................................................
PRM_VC_CFG_I2C_MODE ..........................................................................................
PRM_VC_CFG_I2C_CLK.............................................................................................
PRM_SRAM_COUNT .................................................................................................
Register Call Summary for Register PRM_SRAM_COUNT......................................................
PRM_SRAM_WKUP_SETUP ........................................................................................
PRM_SLDO_CORE_SETUP .........................................................................................
Register Call Summary for Register PRM_SLDO_CORE_SETUP .............................................
PRM_SLDO_CORE_CTRL ...........................................................................................
Register Call Summary for Register PRM_SLDO_CORE_CTRL ...............................................
PRM_SLDO_MPU_SETUP...........................................................................................
PRM_SLDO_MPU_CTRL.............................................................................................
PRM_SLDO_GPU_SETUP ...........................................................................................
PRM_SLDO_GPU_CTRL .............................................................................................
PRM_ABBLDO_MPU_SETUP .......................................................................................
PRM_ABBLDO_MPU_CTRL .........................................................................................
PRM_ABBLDO_GPU_SETUP .......................................................................................
PRM_ABBLDO_GPU_CTRL .........................................................................................
PRM_BANDGAP_SETUP ............................................................................................
Register Call Summary for Register PRM_BANDGAP_SETUP .................................................
PRM_DEVICE_OFF_CTRL ..........................................................................................
Register Call Summary for Register PRM_DEVICE_OFF_CTRL ...............................................
PRM_PHASE1_CNDP ................................................................................................
PRM_PHASE2A_CNDP ..............................................................................................
PRM_PHASE2B_CNDP ..............................................................................................
PRM_MODEM_IF_CTRL .............................................................................................
PRM_VOLTST_MPU ..................................................................................................
PRM_VOLTST_MM ...................................................................................................
PRM_SLDO_DSPEVE_SETUP ......................................................................................
Register Call Summary for Register PRM_SLDO_DSPEVE_SETUP ..........................................
PRM_SLDO_IVA_SETUP ............................................................................................
PRM_ABBLDO_DSPEVE_CTRL ....................................................................................
PRM_ABBLDO_IVA_CTRL...........................................................................................
PRM_SLDO_DSPEVE_CTRL........................................................................................
Register Call Summary for Register PRM_SLDO_DSPEVE_CTRL ............................................
3-1256. PRM_VP_MM_VLIMITTO
1039
3-1257.
1040
3-1258.
3-1259.
3-1260.
3-1261.
3-1262.
3-1263.
3-1264.
3-1265.
3-1266.
3-1267.
3-1268.
3-1269.
3-1270.
3-1271.
3-1272.
3-1273.
3-1274.
3-1275.
3-1276.
3-1277.
3-1278.
3-1279.
3-1280.
3-1281.
3-1282.
3-1283.
3-1284.
3-1285.
3-1286.
3-1287.
3-1288.
3-1289.
3-1290.
3-1291.
3-1292.
3-1293.
3-1294.
3-1295.
3-1296.
3-1297.
3-1298.
3-1299.
3-1300.
3-1301.
3-1302.
3-1303.
3-1304.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1040
1040
1041
1042
1043
1044
1044
1045
1045
1046
1047
1048
1049
1049
1050
1050
1051
1051
1051
1053
1053
1053
1053
1055
1055
1056
1057
1058
1059
1059
1060
1060
1061
1061
1061
1062
1062
1062
1063
1063
1064
1065
1065
1067
1068
1068
1069
105
www.ti.com
3-1305. PRM_SLDO_IVA_CTRL .............................................................................................. 1069
3-1306. PRM_ABBLDO_DSPEVE_SETUP .................................................................................. 1070
3-1307. PRM_ABBLDO_IVA_SETUP ......................................................................................... 1070
3-1308. DSP1_PRM Registers Mapping Summary ......................................................................... 1071
3-1309. PM_DSP1_PWRSTCTRL............................................................................................. 1071
3-1310. Register Call Summary for Register PM_DSP1_PWRSTCTRL ................................................. 1072
3-1311. PM_DSP1_PWRSTST ................................................................................................ 1072
3-1312. Register Call Summary for Register PM_DSP1_PWRSTST ..................................................... 1074
3-1313. RM_DSP1_RSTCTRL ................................................................................................. 1074
3-1314. Register Call Summary for Register RM_DSP1_RSTCTRL ..................................................... 1074
3-1315. RM_DSP1_RSTST .................................................................................................... 1074
3-1316. Register Call Summary for Register RM_DSP1_RSTST ......................................................... 1075
3-1317. RM_DSP1_DSP1_CONTEXT ........................................................................................ 1075
3-1318. Register Call Summary for Register RM_DSP1_DSP1_CONTEXT ............................................ 1076
3-1319. DSP2_PRM Registers Mapping Summary ......................................................................... 1076
3-1320. PM_DSP2_PWRSTCTRL............................................................................................. 1076
3-1321. Register Call Summary for Register PM_DSP2_PWRSTCTRL ................................................. 1077
3-1322. PM_DSP2_PWRSTST ................................................................................................ 1077
3-1323. Register Call Summary for Register PM_DSP2_PWRSTST ..................................................... 1079
3-1324. RM_DSP2_RSTCTRL ................................................................................................. 1079
3-1325. Register Call Summary for Register RM_DSP2_RSTCTRL ..................................................... 1079
3-1326. RM_DSP2_RSTST .................................................................................................... 1079
3-1327. Register Call Summary for Register RM_DSP2_RSTST ......................................................... 1080
3-1328. RM_DSP2_DSP2_CONTEXT ........................................................................................ 1080
3-1329. Register Call Summary for Register RM_DSP2_DSP2_CONTEXT ............................................ 1081
3-1330. DSS_PRM Registers Mapping Summary ........................................................................... 1081
3-1331. PM_DSS_PWRSTCTRL .............................................................................................. 1081
3-1332. Register Call Summary for Register PM_DSS_PWRSTCTRL................................................... 1082
3-1333. PM_DSS_PWRSTST .................................................................................................. 1083
3-1334. Register Call Summary for Register PM_DSS_PWRSTST ...................................................... 1084
3-1335. PM_DSS_DSS_WKDEP .............................................................................................. 1084
3-1336. Register Call Summary for Register PM_DSS_DSS_WKDEP
..................................................
1087
3-1337. RM_DSS_DSS_CONTEXT ........................................................................................... 1087
3-1338. Register Call Summary for Register RM_DSS_DSS_CONTEXT ............................................... 1088
3-1339. PM_DSS_DSS2_WKDEP
............................................................................................
1088
3-1340. RM_DSS_BB2D_CONTEXT ......................................................................................... 1090
3-1341. RM_DSS_SDVENC_CONTEXT ..................................................................................... 1091
3-1342. EMU_CM Registers Mapping Summary ............................................................................ 1092
..............................................................................................
Register Call Summary for Register CM_EMU_CLKSTCTRL ...................................................
CM_EMU_DEBUGSS_CLKCTRL ...................................................................................
Register Call Summary for Register CM_EMU_DEBUGSS_CLKCTRL ........................................
CM_EMU_DYNAMICDEP ............................................................................................
Register Call Summary for Register CM_EMU_DYNAMICDEP .................................................
CM_EMU_MPU_EMU_DBG_CLKCTRL............................................................................
Register Call Summary for Register CM_EMU_MPU_EMU_DBG_CLKCTRL ................................
EMU_PRM Registers Mapping Summary ..........................................................................
PM_EMU_PWRSTCTRL..............................................................................................
Register Call Summary for Register PM_EMU_PWRSTCTRL ..................................................
3-1343. CM_EMU_CLKSTCTRL
3-1344.
3-1345.
3-1346.
3-1347.
3-1348.
3-1349.
3-1350.
3-1351.
3-1352.
3-1353.
106
List of Tables
1092
1093
1093
1093
1093
1094
1094
1095
1095
1095
1096
SPRUIC6B – January 2017 – Revised October 2017
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3-1354. PM_EMU_PWRSTST ................................................................................................. 1096
3-1355. Register Call Summary for Register PM_EMU_PWRSTST ...................................................... 1097
3-1356. RM_EMU_DEBUGSS_CONTEXT ................................................................................... 1097
3-1357. Register Call Summary for Register RM_EMU_DEBUGSS_CONTEXT ....................................... 1097
3-1358. EVE1_PRM Registers Mapping Summary ......................................................................... 1097
3-1359. PM_EVE1_PWRSTCTRL ............................................................................................. 1098
3-1360. Register Call Summary for Register PM_EVE1_PWRSTCTRL ................................................. 1099
3-1361. PM_EVE1_PWRSTST ................................................................................................ 1099
3-1362. Register Call Summary for Register PM_EVE1_PWRSTST ..................................................... 1100
3-1363. RM_EVE1_RSTCTRL ................................................................................................. 1100
.....................................................
RM_EVE1_RSTST ....................................................................................................
Register Call Summary for Register RM_EVE1_RSTST .........................................................
PM_EVE1_EVE1_WKDEP ...........................................................................................
Register Call Summary for Register PM_EVE1_EVE1_WKDEP ................................................
RM_EVE1_EVE1_CONTEXT ........................................................................................
Register Call Summary for Register RM_EVE1_EVE1_CONTEXT.............................................
EVE2_PRM Registers Mapping Summary .........................................................................
PM_EVE2_PWRSTCTRL .............................................................................................
PM_EVE2_PWRSTST ................................................................................................
RM_EVE2_RSTCTRL .................................................................................................
RM_EVE2_RSTST ....................................................................................................
PM_EVE2_EVE2_WKDEP ...........................................................................................
RM_EVE2_EVE2_CONTEXT ........................................................................................
EVE3_PRM Registers Mapping Summary .........................................................................
PM_EVE3_PWRSTCTRL .............................................................................................
PM_EVE3_PWRSTST ................................................................................................
RM_EVE3_RSTCTRL .................................................................................................
RM_EVE3_RSTST ....................................................................................................
PM_EVE3_EVE3_WKDEP ...........................................................................................
RM_EVE3_EVE3_CONTEXT ........................................................................................
EVE4_PRM Registers Mapping Summary .........................................................................
PM_EVE4_PWRSTCTRL .............................................................................................
PM_EVE4_PWRSTST ................................................................................................
RM_EVE4_RSTCTRL .................................................................................................
RM_EVE4_RSTST ....................................................................................................
PM_EVE4_EVE4_WKDEP ...........................................................................................
RM_EVE4_EVE4_CONTEXT ........................................................................................
GPU_PRM Registers Mapping Summary ..........................................................................
PM_GPU_PWRSTCTRL ..............................................................................................
PM_GPU_PWRSTST .................................................................................................
RM_GPU_GPU_CONTEXT ..........................................................................................
INSTR_PRM Registers Mapping Summary ........................................................................
PMI_IDENTICATION ..................................................................................................
Register Call Summary for Register PMI_IDENTICATION.......................................................
PMI_SYS_CONFIG ....................................................................................................
Register Call Summary for Register PMI_SYS_CONFIG ........................................................
PMI_STATUS ..........................................................................................................
Register Call Summary for Register PMI_STATUS ...............................................................
3-1364. Register Call Summary for Register RM_EVE1_RSTCTRL
3-1365.
3-1366.
3-1367.
3-1368.
3-1369.
3-1370.
3-1371.
3-1372.
3-1373.
3-1374.
3-1375.
3-1376.
3-1377.
3-1378.
3-1379.
3-1380.
3-1381.
3-1382.
3-1383.
3-1384.
3-1385.
3-1386.
3-1387.
3-1388.
3-1389.
3-1390.
3-1391.
3-1392.
3-1393.
3-1394.
3-1395.
3-1396.
3-1397.
3-1398.
3-1399.
3-1400.
3-1401.
3-1402.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1100
1101
1101
1101
1103
1103
1103
1104
1104
1105
1106
1106
1107
1108
1109
1109
1110
1111
1111
1112
1113
1114
1114
1115
1116
1116
1117
1118
1119
1119
1120
1121
1121
1122
1122
1122
1122
1123
1123
107
www.ti.com
1123
3-1404.
1123
3-1405.
3-1406.
3-1407.
3-1408.
3-1409.
3-1410.
3-1411.
3-1412.
3-1413.
3-1414.
3-1415.
3-1416.
3-1417.
3-1418.
3-1419.
3-1420.
3-1421.
3-1422.
3-1423.
3-1424.
3-1425.
3-1426.
3-1427.
3-1428.
3-1429.
3-1430.
3-1431.
3-1432.
3-1433.
3-1434.
3-1435.
3-1436.
3-1437.
3-1438.
3-1439.
3-1440.
3-1441.
3-1442.
3-1443.
3-1444.
3-1445.
3-1446.
3-1447.
3-1448.
3-1449.
3-1450.
3-1451.
108
..............................................................................................
Register Call Summary for Register PMI_CONFIGURATION ...................................................
PMI_CLASS_FILTERING .............................................................................................
Register Call Summary for Register PMI_CLASS_FILTERING .................................................
PMI_TRIGGERING ....................................................................................................
Register Call Summary for Register PMI_TRIGGERING.........................................................
PMI_SAMPLING .......................................................................................................
Register Call Summary for Register PMI_SAMPLING ............................................................
IPU_PRM Registers Mapping Summary ............................................................................
PM_IPU_PWRSTCTRL ...............................................................................................
Register Call Summary for Register PM_IPU_PWRSTCTRL....................................................
PM_IPU_PWRSTST ...................................................................................................
Register Call Summary for Register PM_IPU_PWRSTST .......................................................
RM_IPU1_RSTCTRL ..................................................................................................
RM_IPU1_RSTST .....................................................................................................
Register Call Summary for Register RM_IPU1_RSTST ..........................................................
RM_IPU1_IPU1_CONTEXT ..........................................................................................
Register Call Summary for Register RM_IPU1_IPU1_CONTEXT ..............................................
PM_IPU_MCASP1_WKDEP .........................................................................................
Register Call Summary for Register PM_IPU_MCASP1_WKDEP ..............................................
RM_IPU_MCASP1_CONTEXT ......................................................................................
Register Call Summary for Register RM_IPU_MCASP1_CONTEXT ...........................................
PM_IPU_TIMER5_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER5_WKDEP ...............................................
RM_IPU_TIMER5_CONTEXT .......................................................................................
Register Call Summary for Register RM_IPU_TIMER5_CONTEXT ............................................
PM_IPU_TIMER6_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER6_WKDEP ...............................................
RM_IPU_TIMER6_CONTEXT .......................................................................................
Register Call Summary for Register RM_IPU_TIMER6_CONTEXT ............................................
PM_IPU_TIMER7_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER7_WKDEP ...............................................
RM_IPU_TIMER7_CONTEXT .......................................................................................
Register Call Summary for Register RM_IPU_TIMER7_CONTEXT ............................................
PM_IPU_TIMER8_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER8_WKDEP ...............................................
RM_IPU_TIMER8_CONTEXT .......................................................................................
Register Call Summary for Register RM_IPU_TIMER8_CONTEXT ............................................
PM_IPU_I2C5_WKDEP ...............................................................................................
RM_IPU_I2C5_CONTEXT ............................................................................................
PM_IPU_UART6_WKDEP ............................................................................................
RM_IPU_UART6_CONTEXT ........................................................................................
IVA_PRM Registers Mapping Summary ............................................................................
PM_IVA_PWRSTCTRL ...............................................................................................
PM_IVA_PWRSTST ...................................................................................................
RM_IVA_RSTCTRL ...................................................................................................
RM_IVA_RSTST .......................................................................................................
RM_IVA_IVA_CONTEXT .............................................................................................
RM_IVA_SL2_CONTEXT .............................................................................................
3-1403. PMI_CONFIGURATION
List of Tables
1124
1124
1124
1125
1125
1125
1125
1126
1127
1127
1128
1128
1129
1130
1130
1131
1131
1133
1133
1133
1133
1134
1135
1135
1135
1136
1137
1137
1137
1138
1139
1139
1139
1140
1141
1141
1141
1143
1143
1145
1145
1146
1147
1148
1149
1150
1150
SPRUIC6B – January 2017 – Revised October 2017
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3-1452. L3INIT_PRM Registers Mapping Summary ........................................................................ 1151
3-1453. PM_L3INIT_PWRSTCTRL
...........................................................................................
1152
3-1454. Register Call Summary for Register PM_L3INIT_PWRSTCTRL ................................................ 1153
3-1455. PM_L3INIT_PWRSTST ............................................................................................... 1153
3-1456. Register Call Summary for Register PM_L3INIT_PWRSTST.................................................... 1154
3-1457. RM_PCIESS_RSTCTRL .............................................................................................. 1154
3-1458. RM_PCIESS_RSTST
.................................................................................................
1155
3-1459. PM_L3INIT_MMC1_WKDEP ......................................................................................... 1155
3-1460. RM_L3INIT_MMC1_CONTEXT ...................................................................................... 1157
3-1461. PM_L3INIT_MMC2_WKDEP ......................................................................................... 1157
3-1462. RM_L3INIT_MMC2_CONTEXT ...................................................................................... 1159
3-1463. PM_L3INIT_USB_OTG_SS2_WKDEP
.............................................................................
1159
3-1464. RM_L3INIT_USB_OTG_SS2_CONTEXT .......................................................................... 1161
.............................................................................
RM_L3INIT_USB_OTG_SS3_CONTEXT ..........................................................................
PM_L3INIT_USB_OTG_SS4_WKDEP .............................................................................
RM_L3INIT_USB_OTG_SS4_CONTEXT ..........................................................................
RM_L3INIT_MLB_SS_CONTEXT ...................................................................................
RM_L3INIT_IEEE1500_2_OCP_CONTEXT .......................................................................
Register Call Summary for Register RM_L3INIT_IEEE1500_2_OCP_CONTEXT ............................
PM_L3INIT_SATA_WKDEP ..........................................................................................
RM_L3INIT_SATA_CONTEXT .......................................................................................
PM_PCIE_PCIESS1_WKDEP .......................................................................................
RM_PCIE_PCIESS1_CONTEXT ....................................................................................
PM_PCIE_PCIESS2_WKDEP .......................................................................................
RM_PCIE_PCIESS2_CONTEXT ....................................................................................
RM_GMAC_GMAC_CONTEXT ......................................................................................
Register Call Summary for Register RM_GMAC_GMAC_CONTEXT ..........................................
RM_L3INIT_OCP2SCP1_CONTEXT ...............................................................................
RM_L3INIT_OCP2SCP3_CONTEXT ...............................................................................
PM_L3INIT_USB_OTG_SS1_WKDEP .............................................................................
RM_L3INIT_USB_OTG_SS1_CONTEXT ..........................................................................
L4PER_PRM Registers Mapping Summary ........................................................................
PM_L4PER_PWRSTCTRL ...........................................................................................
Register Call Summary for Register PM_L4PER_PWRSTCTRL................................................
PM_L4PER_PWRSTST ...............................................................................................
Register Call Summary for Register PM_L4PER_PWRSTST ...................................................
RM_L4PER2_L4PER2_CONTEXT ..................................................................................
Register Call Summary for Register RM_L4PER2_L4PER2_CONTEXT ......................................
RM_L4PER3_L4PER3_CONTEXT ..................................................................................
Register Call Summary for Register RM_L4PER3_L4PER3_CONTEXT ......................................
RM_L4PER2_PRUSS1_CONTEXT .................................................................................
RM_L4PER2_PRUSS2_CONTEXT .................................................................................
PM_L4PER_DCC6_WKDEP .........................................................................................
RM_L4PER_DCC6_CONTEXT ......................................................................................
Register Call Summary for Register RM_L4PER_DCC6_CONTEXT ..........................................
PM_L4PER_DCC7_WKDEP .........................................................................................
RM_L4PER_DCC7_CONTEXT ......................................................................................
Register Call Summary for Register RM_L4PER_DCC7_CONTEXT ..........................................
3-1465. PM_L3INIT_USB_OTG_SS3_WKDEP
3-1466.
3-1467.
3-1468.
3-1469.
3-1470.
3-1471.
3-1472.
3-1473.
3-1474.
3-1475.
3-1476.
3-1477.
3-1478.
3-1479.
3-1480.
3-1481.
3-1482.
3-1483.
3-1484.
3-1485.
3-1486.
3-1487.
3-1488.
3-1489.
3-1490.
3-1491.
3-1492.
3-1493.
3-1494.
3-1495.
3-1496.
3-1497.
3-1498.
3-1499.
3-1500.
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
List of Tables
1161
1163
1163
1165
1165
1166
1166
1167
1168
1168
1170
1170
1172
1172
1173
1173
1174
1174
1175
1176
1179
1180
1180
1181
1181
1181
1182
1182
1182
1183
1183
1185
1185
1185
1186
1187
109
www.ti.com
3-1501. PM_L4PER_TIMER2_WKDEP....................................................................................... 1187
3-1502. Register Call Summary for Register PM_L4PER_TIMER2_WKDEP ........................................... 1188
3-1503. RM_L4PER_TIMER2_CONTEXT
...................................................................................
1188
3-1504. Register Call Summary for Register RM_L4PER_TIMER2_CONTEXT ........................................ 1189
3-1505. PM_L4PER_TIMER3_WKDEP....................................................................................... 1189
3-1506. Register Call Summary for Register PM_L4PER_TIMER3_WKDEP ........................................... 1190
3-1507. RM_L4PER_TIMER3_CONTEXT
...................................................................................
1190
3-1508. Register Call Summary for Register RM_L4PER_TIMER3_CONTEXT ........................................ 1191
3-1509. PM_L4PER_TIMER4_WKDEP....................................................................................... 1191
3-1510. Register Call Summary for Register PM_L4PER_TIMER4_WKDEP ........................................... 1192
1192
3-1512.
1193
3-1513.
3-1514.
3-1515.
3-1516.
3-1517.
3-1518.
3-1519.
3-1520.
3-1521.
3-1522.
3-1523.
3-1524.
3-1525.
3-1526.
3-1527.
3-1528.
3-1529.
3-1530.
3-1531.
3-1532.
3-1533.
3-1534.
3-1535.
3-1536.
3-1537.
3-1538.
3-1539.
3-1540.
3-1541.
3-1542.
3-1543.
3-1544.
3-1545.
3-1546.
3-1547.
3-1548.
3-1549.
110
...................................................................................
Register Call Summary for Register RM_L4PER_TIMER4_CONTEXT ........................................
PM_L4PER_DCC5_WKDEP .........................................................................................
RM_L4PER_DCC5_CONTEXT ......................................................................................
Register Call Summary for Register RM_L4PER_DCC5_CONTEXT ..........................................
RM_L4PER_ELM_CONTEXT ........................................................................................
Register Call Summary for Register RM_L4PER_ELM_CONTEXT ............................................
PM_L4PER_GPIO2_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO2_WKDEP .............................................
RM_L4PER_GPIO2_CONTEXT .....................................................................................
Register Call Summary for Register RM_L4PER_GPIO2_CONTEXT..........................................
PM_L4PER_GPIO3_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO3_WKDEP .............................................
RM_L4PER_GPIO3_CONTEXT .....................................................................................
Register Call Summary for Register RM_L4PER_GPIO3_CONTEXT..........................................
PM_L4PER_GPIO4_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO4_WKDEP .............................................
RM_L4PER_GPIO4_CONTEXT .....................................................................................
Register Call Summary for Register RM_L4PER_GPIO4_CONTEXT..........................................
PM_L4PER_GPIO5_WKDEP ........................................................................................
RM_L4PER_GPIO5_CONTEXT .....................................................................................
PM_L4PER_GPIO6_WKDEP ........................................................................................
RM_L4PER_GPIO6_CONTEXT .....................................................................................
RM_L4PER_ESM_CONTEXT .......................................................................................
Register Call Summary for Register RM_L4PER_ESM_CONTEXT ............................................
RM_L4PER2_PWMSS2_CONTEXT ................................................................................
RM_L4PER2_PWMSS3_CONTEXT ................................................................................
PM_L4PER_I2C1_WKDEP ...........................................................................................
Register Call Summary for Register PM_L4PER_I2C1_WKDEP ...............................................
RM_L4PER_I2C1_CONTEXT........................................................................................
Register Call Summary for Register RM_L4PER_I2C1_CONTEXT ............................................
PM_L4PER_I2C2_WKDEP ...........................................................................................
Register Call Summary for Register PM_L4PER_I2C2_WKDEP ...............................................
RM_L4PER_I2C2_CONTEXT........................................................................................
Register Call Summary for Register RM_L4PER_I2C2_CONTEXT ............................................
PM_L4PER_I2C3_WKDEP ...........................................................................................
RM_L4PER_I2C3_CONTEXT........................................................................................
PM_L4PER_I2C4_WKDEP ...........................................................................................
RM_L4PER_I2C4_CONTEXT........................................................................................
3-1511. RM_L4PER_TIMER4_CONTEXT
List of Tables
1193
1194
1195
1195
1195
1195
1198
1198
1198
1198
1201
1201
1201
1201
1204
1204
1204
1204
1207
1207
1209
1210
1210
1210
1211
1211
1213
1213
1214
1214
1215
1215
1216
1216
1218
1218
1220
SPRUIC6B – January 2017 – Revised October 2017
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3-1550. RM_L4PER_L4PER1_CONTEXT ................................................................................... 1220
3-1551. Register Call Summary for Register RM_L4PER_L4PER1_CONTEXT ........................................ 1221
3-1552. RM_L4PER2_PWMSS1_CONTEXT ................................................................................ 1221
3-1553. Register Call Summary for Register RM_L4PER2_PWMSS1_CONTEXT ..................................... 1221
3-1554. PM_L4PER_DCC1_WKDEP ......................................................................................... 1221
....................................................................................
Register Call Summary for Register RM_L4PER3_DCC1_CONTEXT .........................................
PM_L4PER_DCC2_WKDEP .........................................................................................
RM_L4PER3_DCC2_CONTEXT ....................................................................................
Register Call Summary for Register RM_L4PER3_DCC2_CONTEXT .........................................
PM_L4PER_DCC3_WKDEP .........................................................................................
RM_L4PER3_DCC3_CONTEXT ....................................................................................
Register Call Summary for Register RM_L4PER3_DCC3_CONTEXT .........................................
PM_L4PER_MCSPI1_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI1_WKDEP ...........................................
RM_L4PER_MCSPI1_CONTEXT ...................................................................................
Register Call Summary for Register RM_L4PER_MCSPI1_CONTEXT ........................................
PM_L4PER_MCSPI2_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI2_WKDEP ...........................................
RM_L4PER_MCSPI2_CONTEXT ...................................................................................
Register Call Summary for Register RM_L4PER_MCSPI2_CONTEXT ........................................
PM_L4PER_MCSPI3_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI3_WKDEP ...........................................
RM_L4PER_MCSPI3_CONTEXT ...................................................................................
Register Call Summary for Register RM_L4PER_MCSPI3_CONTEXT ........................................
PM_L4PER_MCSPI4_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI4_WKDEP ...........................................
RM_L4PER_MCSPI4_CONTEXT ...................................................................................
Register Call Summary for Register RM_L4PER_MCSPI4_CONTEXT ........................................
PM_L4PER_GPIO7_WKDEP ........................................................................................
RM_L4PER_GPIO7_CONTEXT .....................................................................................
PM_L4PER_GPIO8_WKDEP ........................................................................................
RM_L4PER_GPIO8_CONTEXT .....................................................................................
PM_L4PER_MMC3_WKDEP ........................................................................................
RM_L4PER_MMC3_CONTEXT .....................................................................................
PM_L4PER_MMC4_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_MMC4_WKDEP .............................................
RM_L4PER_MMC4_CONTEXT .....................................................................................
Register Call Summary for Register RM_L4PER_MMC4_CONTEXT ..........................................
PM_L4PER_DCC4_WKDEP .........................................................................................
RM_L4PER3_DCC4_CONTEXT ....................................................................................
Register Call Summary for Register RM_L4PER3_DCC4_CONTEXT .........................................
PM_L4PER2_QSPI_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER2_QSPI_WKDEP .............................................
RM_L4PER2_QSPI_CONTEXT .....................................................................................
Register Call Summary for Register RM_L4PER2_QSPI_CONTEXT ..........................................
PM_L4PER_UART1_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART1_WKDEP ............................................
RM_L4PER_UART1_CONTEXT ....................................................................................
3-1555. RM_L4PER3_DCC1_CONTEXT
1223
3-1556.
1223
3-1557.
3-1558.
3-1559.
3-1560.
3-1561.
3-1562.
3-1563.
3-1564.
3-1565.
3-1566.
3-1567.
3-1568.
3-1569.
3-1570.
3-1571.
3-1572.
3-1573.
3-1574.
3-1575.
3-1576.
3-1577.
3-1578.
3-1579.
3-1580.
3-1581.
3-1582.
3-1583.
3-1584.
3-1585.
3-1586.
3-1587.
3-1588.
3-1589.
3-1590.
3-1591.
3-1592.
3-1593.
3-1594.
3-1595.
3-1596.
3-1597.
3-1598.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1223
1225
1225
1225
1226
1227
1227
1228
1228
1229
1229
1230
1230
1231
1231
1232
1232
1233
1233
1234
1234
1235
1235
1237
1238
1240
1240
1242
1242
1244
1244
1245
1245
1246
1246
1246
1248
1248
1248
1248
1250
1250
111
www.ti.com
3-1599. Register Call Summary for Register RM_L4PER_UART1_CONTEXT ......................................... 1251
3-1600. PM_L4PER_UART2_WKDEP........................................................................................ 1251
3-1601. Register Call Summary for Register PM_L4PER_UART2_WKDEP ............................................ 1252
1252
3-1603.
1253
3-1604.
3-1605.
3-1606.
3-1607.
3-1608.
3-1609.
3-1610.
3-1611.
3-1612.
3-1613.
3-1614.
3-1615.
3-1616.
3-1617.
3-1618.
3-1619.
3-1620.
3-1621.
3-1622.
3-1623.
3-1624.
3-1625.
3-1626.
3-1627.
3-1628.
3-1629.
3-1630.
3-1631.
3-1632.
3-1633.
3-1634.
3-1635.
3-1636.
3-1637.
3-1638.
3-1639.
3-1640.
3-1641.
3-1642.
3-1643.
3-1644.
3-1645.
3-1646.
3-1647.
112
....................................................................................
Register Call Summary for Register RM_L4PER_UART2_CONTEXT .........................................
PM_L4PER_UART3_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART3_WKDEP ............................................
RM_L4PER_UART3_CONTEXT ....................................................................................
Register Call Summary for Register RM_L4PER_UART3_CONTEXT .........................................
PM_L4PER_UART4_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART4_WKDEP ............................................
RM_L4PER_UART4_CONTEXT ....................................................................................
Register Call Summary for Register RM_L4PER_UART4_CONTEXT .........................................
PM_L4PER2_ADC_WKDEP .........................................................................................
Register Call Summary for Register PM_L4PER2_ADC_WKDEP ..............................................
RM_L4PER2_ADC_CONTEXT ......................................................................................
Register Call Summary for Register RM_L4PER2_ADC_CONTEXT...........................................
PM_L4PER2_MCASP3_WKDEP ....................................................................................
RM_L4PER2_MCASP3_CONTEXT .................................................................................
PM_L4PER_UART5_WKDEP........................................................................................
RM_L4PER_UART5_CONTEXT ....................................................................................
PM_L4PER2_MCASP5_WKDEP ....................................................................................
RM_L4PER2_MCASP5_CONTEXT .................................................................................
PM_L4PER2_MCASP6_WKDEP ....................................................................................
RM_L4PER2_MCASP6_CONTEXT .................................................................................
PM_L4PER2_MCASP7_WKDEP ....................................................................................
RM_L4PER2_MCASP7_CONTEXT .................................................................................
PM_L4PER2_MCASP8_WKDEP ....................................................................................
RM_L4PER2_MCASP8_CONTEXT .................................................................................
PM_L4PER2_MCASP4_WKDEP ....................................................................................
RM_L4PER2_MCASP4_CONTEXT .................................................................................
RM_L4SEC_AES1_CONTEXT ......................................................................................
RM_L4SEC_AES2_CONTEXT ......................................................................................
RM_L4SEC_DES3DES_CONTEXT .................................................................................
RM_L4SEC_FPKA_CONTEXT ......................................................................................
RM_L4SEC_RNG_CONTEXT .......................................................................................
RM_L4SEC_SHA2MD51_CONTEXT ...............................................................................
PM_L4PER2_UART7_WKDEP ......................................................................................
RM_L4PER2_UART7_CONTEXT ...................................................................................
RM_L4SEC_DMA_CRYPTO_CONTEXT...........................................................................
PM_L4PER2_UART8_WKDEP ......................................................................................
RM_L4PER2_UART8_CONTEXT ...................................................................................
PM_L4PER2_UART9_WKDEP ......................................................................................
RM_L4PER2_UART9_CONTEXT ...................................................................................
PM_L4PER2_DCAN2_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER2_DCAN2_WKDEP ..........................................
RM_L4PER2_DCAN2_CONTEXT ...................................................................................
Register Call Summary for Register RM_L4PER2_DCAN2_CONTEXT .......................................
RM_L4SEC_SHA2MD52_CONTEXT ...............................................................................
3-1602. RM_L4PER_UART2_CONTEXT
List of Tables
1253
1254
1254
1255
1255
1256
1257
1257
1257
1259
1259
1260
1260
1261
1262
1263
1264
1265
1266
1268
1268
1270
1270
1272
1272
1274
1275
1275
1276
1276
1277
1277
1278
1279
1280
1280
1282
1282
1284
1284
1286
1286
1287
1287
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
3-1648. MPU_PRM Registers Mapping Summary .......................................................................... 1287
3-1649. PM_MPU_PWRSTCTRL.............................................................................................. 1288
3-1650. PM_MPU_PWRSTST ................................................................................................. 1289
3-1651. RM_MPU_MPU_CONTEXT .......................................................................................... 1290
3-1652. OCP_SOCKET_PRM Registers Mapping Summary .............................................................. 1291
3-1653. REVISION_PRM ....................................................................................................... 1291
3-1654. Register Call Summary for Register REVISION_PRM............................................................ 1292
3-1655. PRM_IRQSTATUS_MPU ............................................................................................. 1292
.................................................
PRM_IRQSTATUS_MPU_2 ..........................................................................................
PRM_IRQENABLE_MPU .............................................................................................
Register Call Summary for Register PRM_IRQENABLE_MPU .................................................
PRM_IRQENABLE_MPU_2 ..........................................................................................
PRM_IRQSTATUS_IPU2 .............................................................................................
PRM_IRQENABLE_IPU2 .............................................................................................
PRM_IRQSTATUS_DSP1 ............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_DSP1 ................................................
PRM_IRQENABLE_DSP1 ............................................................................................
Register Call Summary for Register PRM_IRQENABLE_DSP1 ................................................
CM_PRM_PROFILING_CLKCTRL ..................................................................................
Register Call Summary for Register CM_PRM_PROFILING_CLKCTRL ......................................
PRM_IRQENABLE_DSP2 ............................................................................................
Register Call Summary for Register PRM_IRQENABLE_DSP2 ................................................
PRM_IRQENABLE_EVE1 ............................................................................................
Register Call Summary for Register PRM_IRQENABLE_EVE1.................................................
PRM_IRQENABLE_EVE2 ............................................................................................
PRM_IRQENABLE_EVE3 ............................................................................................
PRM_IRQENABLE_EVE4 ............................................................................................
PRM_IRQENABLE_IPU1 .............................................................................................
Register Call Summary for Register PRM_IRQENABLE_IPU1 .................................................
PRM_IRQSTATUS_DSP2 ............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_DSP2 ................................................
PRM_IRQSTATUS_EVE1 ............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_EVE1.................................................
PRM_IRQSTATUS_EVE2 ............................................................................................
PRM_IRQSTATUS_EVE3 ............................................................................................
PRM_IRQSTATUS_EVE4 ............................................................................................
PRM_IRQSTATUS_IPU1 .............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_IPU1 .................................................
PRM_DEBUG_CFG1 ..................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG1 ......................................................
PRM_DEBUG_CFG2 ..................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG2 ......................................................
PRM_DEBUG_CFG3 ..................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG3 ......................................................
PRM_DEBUG_CFG ...................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG ........................................................
PRM_DEBUG_OUT ...................................................................................................
Register Call Summary for Register PRM_DEBUG_OUT ........................................................
3-1656. Register Call Summary for Register PRM_IRQSTATUS_MPU
1293
3-1657.
1294
3-1658.
3-1659.
3-1660.
3-1661.
3-1662.
3-1663.
3-1664.
3-1665.
3-1666.
3-1667.
3-1668.
3-1669.
3-1670.
3-1671.
3-1672.
3-1673.
3-1674.
3-1675.
3-1676.
3-1677.
3-1678.
3-1679.
3-1680.
3-1681.
3-1682.
3-1683.
3-1684.
3-1685.
3-1686.
3-1687.
3-1688.
3-1689.
3-1690.
3-1691.
3-1692.
3-1693.
3-1694.
3-1695.
3-1696.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1294
1296
1296
1296
1298
1299
1301
1301
1303
1303
1304
1304
1305
1306
1307
1307
1309
1310
1312
1313
1313
1315
1315
1317
1317
1319
1321
1323
1325
1325
1325
1325
1325
1326
1326
1326
1326
1326
1327
113
www.ti.com
3-1697. RTC_PRM Registers Mapping Summary ........................................................................... 1327
3-1698. PM_RTC_RTCSS_WKDEP .......................................................................................... 1327
3-1699. RM_RTC_RTCSS_CONTEXT ....................................................................................... 1329
3-1700. ISS_PRM Registers Mapping Summary ............................................................................ 1330
3-1701. PM_ISS_PWRSTCTRL ............................................................................................... 1330
3-1702. Register Call Summary for Register PM_ISS_PWRSTCTRL .................................................... 1331
3-1703. PM_ISS_PWRSTST ................................................................................................... 1331
3-1704. Register Call Summary for Register PM_ISS_PWRSTST
.......................................................
1332
3-1705. PM_ISS_ISS_WKDEP ................................................................................................ 1332
3-1706. Register Call Summary for Register PM_ISS_ISS_WKDEP ..................................................... 1333
3-1707. RM_ISS_ISS_CONTEXT ............................................................................................. 1333
3-1708. Register Call Summary for Register RM_ISS_ISS_CONTEXT .................................................. 1334
3-1709. WKUPAON_CM Registers Mapping Summary .................................................................... 1334
3-1710. CM_WKUPAON_CLKSTCTRL....................................................................................... 1335
3-1711. Register Call Summary for Register CM_WKUPAON_CLKSTCTRL ........................................... 1337
3-1712. CM_WKUPAON_L4_WKUP_CLKCTRL ............................................................................ 1337
3-1713. Register Call Summary for Register CM_WKUPAON_L4_WKUP_CLKCTRL
................................
1338
3-1714. CM_WKUPAON_WD_TIMER1_CLKCTRL......................................................................... 1338
3-1715. CM_WKUPAON_WD_TIMER2_CLKCTRL......................................................................... 1338
3-1716. CM_WKUPAON_GPIO1_CLKCTRL ................................................................................ 1339
3-1717. Register Call Summary for Register CM_WKUPAON_GPIO1_CLKCTRL ..................................... 1340
3-1718. CM_WKUPAON_TIMER1_CLKCTRL............................................................................... 1340
3-1719. Register Call Summary for Register CM_WKUPAON_TIMER1_CLKCTRL ................................... 1341
3-1720. CM_WKUPAON_TIMER12_CLKCTRL ............................................................................. 1341
3-1721. CM_WKUPAON_COUNTER_32K_CLKCTRL ..................................................................... 1342
.........................
CM_WKUPAON_SAR_RAM_CLKCTRL ...........................................................................
CM_WKUPAON_KBD_CLKCTRL ...................................................................................
CM_WKUPAON_UART10_CLKCTRL ..............................................................................
CM_WKUPAON_DCAN1_CLKCTRL ...............................................................................
Register Call Summary for Register CM_WKUPAON_DCAN1_CLKCTRL ....................................
CM_WKUPAON_SCRM_CLKCTRL.................................................................................
CM_WKUPAON_IO_SRCOMP_CLKCTRL ........................................................................
CM_WKUPAON_ADC_CLKCTRL ...................................................................................
CM_WKUPAON_SPARE_SAFETY1_CLKCTRL ..................................................................
CM_WKUPAON_RTI1_CLKCTRL ...................................................................................
Register Call Summary for Register CM_WKUPAON_RTI1_CLKCTRL .......................................
CM_WKUPAON_RTI2_CLKCTRL ...................................................................................
Register Call Summary for Register CM_WKUPAON_RTI2_CLKCTRL .......................................
CM_WKUPAON_RTI3_CLKCTRL ...................................................................................
Register Call Summary for Register CM_WKUPAON_RTI3_CLKCTRL .......................................
CM_WKUPAON_RTI4_CLKCTRL ...................................................................................
Register Call Summary for Register CM_WKUPAON_RTI4_CLKCTRL .......................................
CM_WKUPAON_RTI5_CLKCTRL ...................................................................................
Register Call Summary for Register CM_WKUPAON_RTI5_CLKCTRL .......................................
WKUPAON_PRM Registers Mapping Summary ..................................................................
RM_WKUPAON_L4_WKUP_CONTEXT ...........................................................................
Register Call Summary for Register RM_WKUPAON_L4_WKUP_CONTEXT ................................
PM_WKUPAON_WD_TIMER1_WKDEP ...........................................................................
3-1722. Register Call Summary for Register CM_WKUPAON_COUNTER_32K_CLKCTRL
3-1723.
3-1724.
3-1725.
3-1726.
3-1727.
3-1728.
3-1729.
3-1730.
3-1731.
3-1732.
3-1733.
3-1734.
3-1735.
3-1736.
3-1737.
3-1738.
3-1739.
3-1740.
3-1741.
3-1742.
3-1743.
3-1744.
3-1745.
114
List of Tables
1342
1342
1343
1344
1345
1345
1345
1346
1346
1347
1348
1348
1348
1349
1349
1350
1350
1351
1351
1351
1352
1352
1353
1353
SPRUIC6B – January 2017 – Revised October 2017
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www.ti.com
3-1746. RM_WKUPAON_WD_TIMER1_CONTEXT ........................................................................ 1354
3-1747. PM_WKUPAON_WD_TIMER2_WKDEP ........................................................................... 1355
3-1748. RM_WKUPAON_WD_TIMER2_CONTEXT ........................................................................ 1356
3-1749. PM_WKUPAON_GPIO1_WKDEP ................................................................................... 1357
3-1750. Register Call Summary for Register PM_WKUPAON_GPIO1_WKDEP ....................................... 1359
3-1751. RM_WKUPAON_GPIO1_CONTEXT ................................................................................ 1359
3-1752. Register Call Summary for Register RM_WKUPAON_GPIO1_CONTEXT .................................... 1359
3-1753. PM_WKUPAON_TIMER1_WKDEP ................................................................................. 1359
3-1754. Register Call Summary for Register PM_WKUPAON_TIMER1_WKDEP ...................................... 1361
3-1755. RM_WKUPAON_TIMER1_CONTEXT .............................................................................. 1361
..................................
3-1757. PM_WKUPAON_TIMER12_WKDEP ................................................................................
3-1758. RM_WKUPAON_TIMER12_CONTEXT ............................................................................
3-1759. RM_WKUPAON_COUNTER_32K_CONTEXT ....................................................................
3-1760. Register Call Summary for Register RM_WKUPAON_COUNTER_32K_CONTEXT .........................
3-1761. RM_WKUPAON_SAR_RAM_CONTEXT ...........................................................................
3-1762. PM_WKUPAON_KBD_WKDEP .....................................................................................
3-1763. RM_WKUPAON_KBD_CONTEXT ..................................................................................
3-1764. PM_WKUPAON_UART10_WKDEP .................................................................................
3-1765. RM_WKUPAON_UART10_CONTEXT..............................................................................
3-1766. PM_WKUPAON_DCAN1_WKDEP ..................................................................................
3-1767. Register Call Summary for Register PM_WKUPAON_DCAN1_WKDEP ......................................
3-1768. RM_WKUPAON_DCAN1_CONTEXT ...............................................................................
3-1769. Register Call Summary for Register RM_WKUPAON_DCAN1_CONTEXT ...................................
3-1770. PM_WKUPAON_ADC_WKDEP .....................................................................................
3-1771. RM_WKUPAON_ADC_CONTEXT ..................................................................................
3-1772. RM_WKUPAON_SPARE_SAFETY1_CONTEXT .................................................................
3-1773. RM_WKUPAON_RTI1_CONTEXT ..................................................................................
3-1774. Register Call Summary for Register RM_WKUPAON_RTI1_CONTEXT.......................................
3-1775. RM_WKUPAON_RTI2_CONTEXT ..................................................................................
3-1776. Register Call Summary for Register RM_WKUPAON_RTI2_CONTEXT.......................................
3-1777. RM_WKUPAON_RTI3_CONTEXT ..................................................................................
3-1778. Register Call Summary for Register RM_WKUPAON_RTI3_CONTEXT.......................................
3-1779. RM_WKUPAON_RTI4_CONTEXT ..................................................................................
3-1780. Register Call Summary for Register RM_WKUPAON_RTI4_CONTEXT.......................................
3-1781. RM_WKUPAON_RTI5_CONTEXT ..................................................................................
3-1782. Register Call Summary for Register RM_WKUPAON_RTI5_CONTEXT.......................................
4-1.
DSP Integration Attributes .............................................................................................
4-2.
DSP Clocks and Resets ................................................................................................
4-3.
DSP Hardware Requests...............................................................................................
4-4.
Summary of the DSP1 and DSP2 Hardware Resets ..............................................................
4-5.
DSP ERRINT Interrupt Mapping ......................................................................................
4-6.
DSP1_EDMA Default Request Mapping .............................................................................
4-7.
DSP2_EDMA Default Request Mapping .............................................................................
4-8.
DSP_NoC Defined Connectivities .....................................................................................
4-9.
C66x CPU View Map ...................................................................................................
4-10. DSP EDMA Controller View Map .....................................................................................
4-11. SDMA Target Port Memory Map ......................................................................................
4-12. DSP Subsystem Instance Summary ..................................................................................
3-1756. Register Call Summary for Register RM_WKUPAON_TIMER1_CONTEXT
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1361
1361
1363
1363
1364
1364
1364
1366
1366
1368
1368
1370
1370
1370
1370
1372
1372
1373
1373
1373
1374
1374
1374
1374
1375
1375
1375
1382
1383
1384
1399
1407
1411
1411
1419
1422
1423
1424
1425
115
www.ti.com
4-13.
DSP_ICFG Registers Mapping Summary............................................................................ 1426
4-14.
DSP_SYSTEM and DSP1_SYSTEM Registers Mapping Summary ............................................. 1430
4-15.
DSP2_SYSTEM Registers Mapping Summary
4-16.
DSP_SYS_REVISION .................................................................................................. 1432
4-17.
Register Call Summary for Register DSP_SYS_REVISION
4-18.
DSP_SYS_HWINFO .................................................................................................... 1432
4-19.
Register Call Summary for Register DSP_SYS_HWINFO
4-20.
DSP_SYS_SYSCONFIG ............................................................................................... 1433
4-21.
Register Call Summary for Register DSP_SYS_SYSCONFIG
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
4-39.
4-40.
4-41.
4-42.
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
4-59.
4-60.
4-61.
116
.....................................................................
......................................................
........................................................
...................................................
DSP_SYS_STAT ........................................................................................................
Register Call Summary for Register DSP_SYS_STAT ............................................................
DSP_SYS_DISC_CONFIG ............................................................................................
Register Call Summary for Register DSP_SYS_DISC_CONFIG .................................................
DSP_SYS_BUS_CONFIG .............................................................................................
Register Call Summary for Register DSP_SYS_BUS_CONFIG ..................................................
DSP_SYS_MMU_CONFIG ............................................................................................
Register Call Summary for Register DSP_SYS_MMU_CONFIG .................................................
DSP_SYS_IRQWAKEEN0 .............................................................................................
Register Call Summary for Register DSP_SYS_IRQWAKEEN0 .................................................
DSP_SYS_IRQWAKEEN1 .............................................................................................
Register Call Summary for Register DSP_SYS_IRQWAKEEN1 .................................................
DSP_SYS_DMAWAKEEN0 ............................................................................................
Register Call Summary for Register DSP_SYS_DMAWAKEEN0 ................................................
DSP_SYS_DMAWAKEEN1 ............................................................................................
Register Call Summary for Register DSP_SYS_DMAWAKEEN1 ................................................
DSP_SYS_EVTOUT_SET .............................................................................................
Register Call Summary for Register DSP_SYS_EVTOUT_SET ..................................................
DSP_SYS_EVTOUT_CLR .............................................................................................
Register Call Summary for Register DSP_SYS_EVTOUT_CLR..................................................
DSP_SYS_ERRINT_IRQSTATUS_RAW ............................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQSTATUS_RAW.................................
DSP_SYS_ERRINT_IRQSTATUS ....................................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQSTATUS ........................................
DSP_SYS_ERRINT_IRQENABLE_SET .............................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQENABLE_SET ..................................
DSP_SYS_ERRINT_IRQENABLE_CLR .............................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQENABLE_CLR .................................
DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW .....................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW .........................
DSP_SYS_EDMAWAKE0_IRQSTATUS .............................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQSTATUS .................................
DSP_SYS_EDMAWAKE0_IRQENABLE_SET ......................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQENABLE_SET ..........................
DSP_SYS_EDMAWAKE0_IRQENABLE_CLR ......................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQENABLE_CLR ..........................
DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW .....................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW .........................
DSP_SYS_EDMAWAKE1_IRQSTATUS .............................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQSTATUS .................................
List of Tables
1431
1432
1432
1434
1434
1435
1435
1436
1436
1437
1437
1438
1438
1439
1439
1439
1439
1440
1440
1440
1441
1441
1441
1442
1442
1442
1442
1443
1443
1443
1443
1444
1444
1444
1444
1445
1445
1445
1446
1446
1446
1446
1447
1447
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
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4-62.
DSP_SYS_EDMAWAKE1_IRQENABLE_SET ...................................................................... 1447
4-63.
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQENABLE_SET
4-64.
DSP_SYS_EDMAWAKE1_IRQENABLE_CLR ...................................................................... 1448
4-65.
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQENABLE_CLR .......................... 1448
4-66.
DSP_SYS_HW_DBGOUT_SEL ....................................................................................... 1448
4-67.
Register Call Summary for Register DSP_SYS_HW_DBGOUT_SEL ........................................... 1448
4-68.
DSP_SYS_HW_DBGOUT_VAL ....................................................................................... 1449
4-69.
Register Call Summary for Register DSP_SYS_HW_DBGOUT_VAL ........................................... 1449
4-70.
DSP_FW_L2_NOC_CFG and DSP1_FW_L2_NOC_CFG Registers Mapping Summary..................... 1449
4-71.
DSP2_FW_L2_NOC_CFG Registers Mapping Summary ......................................................... 1450
4-72.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0 ......................... 1451
4-73.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0 ......................... 1452
4-74.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0
4-75.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0
4-76.
..........................
1447
........
1452
........
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL ..............
1452
1452
4-77.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL .............. 1453
4-78.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1453
4-79.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1453
4-80.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1453
4-81.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1455
4-82.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1 ..................... 1455
4-83.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1 ..................... 1455
4-84.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1
........................
1455
4-85.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1
........................
1456
4-86.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
1 ........................................................................................................................... 1456
4-87.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
1 ........................................................................................................................... 1456
4-88.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_1 .......................................................................................................................... 1457
4-89.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_1 .......................................................................................................................... 1458
4-90.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0 ......................... 1458
4-91.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0 ......................... 1458
4-92.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0
4-93.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0
4-94.
4-95.
........
1458
........
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL ..............
1459
1459
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL .............. 1459
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
117
www.ti.com
4-96.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1459
4-97.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1460
4-98.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1460
4-99.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1461
4-100. DSPNOC_FLAGMUX_ID_COREID
..................................................................................
1461
4-101. Register Call Summary for Register DSPNOC_FLAGMUX_ID_COREID ....................................... 1462
4-102. DSPNOC_FLAGMUX_ID_REVISIONID
.............................................................................
1462
4-103. Register Call Summary for Register DSPNOC_FLAGMUX_ID_REVISIONID .................................. 1462
4-104. DSPNOC_FLAGMUX_FAULTEN ..................................................................................... 1462
4-105. Register Call Summary for Register DSPNOC_FLAGMUX_FAULTEN
.........................................
1462
4-106. DSPNOC_FLAGMUX_FAULTSTATUS .............................................................................. 1463
4-107. Register Call Summary for Register DSPNOC_FLAGMUX_FAULTSTATUS................................... 1463
4-108. DSPNOC_FLAGMUX_FLAGINEN0 .................................................................................. 1463
4-109. Register Call Summary for Register DSPNOC_FLAGMUX_FLAGINEN0 ....................................... 1463
4-110. DSPNOC_FLAGMUX_FLAGINSTATUS0 ........................................................................... 1464
4-111. Register Call Summary for Register DSPNOC_FLAGMUX_FLAGINSTATUS0 ................................ 1464
4-112. DSPNOC_ERRORLOG_ID_COREID ................................................................................ 1464
4-113. Register Call Summary for Register DSPNOC_ERRORLOG_ID_COREID ..................................... 1464
4-114. DSPNOC_ERRORLOG_ID_REVISIONID ........................................................................... 1464
4-115. Register Call Summary for Register DSPNOC_ERRORLOG_ID_REVISIONID................................ 1465
1465
4-117.
1465
4-118.
4-119.
4-120.
4-121.
4-122.
4-123.
4-124.
4-125.
4-126.
4-127.
4-128.
4-129.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
118
..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_FAULTEN .......................................
DSPNOC_ERRORLOG_ERRVLD ....................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRVLD ........................................
DSPNOC_ERRORLOG_ERRCLR ....................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRCLR ........................................
DSPNOC_ERRORLOG_ERRLOG0 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG0 ......................................
DSPNOC_ERRORLOG_ERRLOG1 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG1 ......................................
DSPNOC_ERRORLOG_ERRLOG3 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG3 ......................................
DSPNOC_ERRORLOG_ERRLOG5 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG5 ......................................
IPU Integration Attributes...............................................................................................
IPU Hardware Requests................................................................................................
IPU Clocks and Resets .................................................................................................
Cortex-M4 Configuration ...............................................................................................
IPU_UNICACHE Configuration ........................................................................................
IPU_UNICACHE_MMU Configuration ................................................................................
IPU_MMU Behavior on Page-Fault ...................................................................................
IPU Subsystem Power Modes .........................................................................................
IPU Subsystem Instance Summary ...................................................................................
IPU_UNICACHE_CFG Registers Mapping Summary ..............................................................
4-116. DSPNOC_ERRORLOG_FAULTEN
List of Tables
1465
1466
1466
1466
1466
1467
1467
1467
1467
1468
1468
1468
1473
1474
1474
1478
1480
1481
1485
1489
1495
1495
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
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www.ti.com
5-11.
CACHE_CONFIG ....................................................................................................... 1496
5-12.
Register Call Summary for Register CACHE_CONFIG ............................................................ 1496
5-13.
CACHE_INT
5-14.
Register Call Summary for Register CACHE_INT .................................................................. 1497
5-15.
CACHE_OCP ............................................................................................................ 1497
5-16.
Register Call Summary for Register CACHE_OCP................................................................. 1498
5-17.
CACHE_MAINT
5-18.
Register Call Summary for Register CACHE_MAINT .............................................................. 1499
5-19.
CACHE_MTSTART ..................................................................................................... 1499
5-20.
Register Call Summary for Register CACHE_MTSTART .......................................................... 1499
5-21.
CACHE_MTEND ........................................................................................................ 1499
5-22.
Register Call Summary for Register CACHE_MTEND ............................................................. 1499
5-23.
CACHE_CTADDR....................................................................................................... 1500
5-24.
Register Call Summary for Register CACHE_CTADDR ........................................................... 1500
5-25.
CACHE_CTDATA ....................................................................................................... 1500
5-26.
Register Call Summary for Register CACHE_CTDATA............................................................ 1500
5-27.
ECC_CFG ................................................................................................................ 1501
5-28.
Register Call Summary for Register ECC_CFG
1501
5-29.
L1DATA_ERR_INFO
1502
5-30.
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
5-37.
5-38.
5-39.
5-40.
5-41.
5-42.
5-43.
5-44.
5-45.
5-46.
5-47.
5-48.
5-49.
5-50.
5-51.
5-52.
5-53.
5-54.
5-55.
5-56.
5-57.
5-58.
5-59.
.............................................................................................................
.........................................................................................................
....................................................................
...................................................................................................
Register Call Summary for Register L1DATA_ERR_INFO ........................................................
L1DATA_ERR_ADDR_LOC ...........................................................................................
Register Call Summary for Register L1DATA_ERR_ADDR_LOC ................................................
L1TAG_ERR_INFO .....................................................................................................
Register Call Summary for Register L1TAG_ERR_INFO ..........................................................
L1TAG_ERR_ADDR_LOC .............................................................................................
Register Call Summary for Register L1TAG_ERR_ADDR_LOC .................................................
L2RAM_ERR_INFO .....................................................................................................
Register Call Summary for Register L2RAM_ERR_INFO .........................................................
L2RAM_ERR_ADDR_LOC ............................................................................................
Register Call Summary for Register L2RAM_ERR_ADDR_LOC .................................................
IPU_UNICACHE_SCTM Registers Mapping Summary ............................................................
CACHE_SCTM_CTCNTL ..............................................................................................
Register Call Summary for Register CACHE_SCTM_CTCNTL...................................................
CACHE_SCTM_TINTVLR_i ...........................................................................................
Register Call Summary for Register CACHE_SCTM_TINTVLR_i ................................................
CACHE_SCTM_CTDBGNUM .........................................................................................
Register Call Summary for Register CACHE_SCTM_CTDBGNUM ..............................................
CACHE_SCTM_CTGNBL ..............................................................................................
Register Call Summary for Register CACHE_SCTM_CTGNBL ..................................................
CACHE_SCTM_CTGRST..............................................................................................
Register Call Summary for Register CACHE_SCTM_CTGRST ..................................................
CACHE_SCTM_CTCR_WT_i .........................................................................................
Register Call Summary for Register CACHE_SCTM_CTCR_WT_i ..............................................
CACHE_SCTM_CTCR_WOT_j .......................................................................................
Register Call Summary for Register CACHE_SCTM_CTCR_WOT_j ............................................
CACHE_SCTM_CTCNTR_k ...........................................................................................
Register Call Summary for Register CACHE_SCTM_CTCNTR_k ...............................................
IPU_UNICACHE_MMU (AMMU) Registers Mapping Summary ..................................................
CACHE_MMU_LARGE_ADDR_i .....................................................................................
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1496
1498
1502
1502
1503
1503
1503
1504
1504
1504
1505
1505
1505
1505
1506
1507
1507
1507
1507
1507
1508
1508
1508
1508
1509
1510
1510
1511
1512
1512
1512
1513
119
www.ti.com
5-60.
Register Call Summary for Register CACHE_MMU_LARGE_ADDR_i .......................................... 1513
5-61.
CACHE_MMU_LARGE_XLTE_i
5-62.
Register Call Summary for Register CACHE_MMU_LARGE_XLTE_i ........................................... 1514
5-63.
CACHE_MMU_LARGE_POLICY_i ................................................................................... 1514
5-64.
Register Call Summary for Register CACHE_MMU_LARGE_POLICY_i ........................................ 1515
5-65.
CACHE_MMU_MED_ADDR_j ......................................................................................... 1515
5-66.
Register Call Summary for Register CACHE_MMU_MED_ADDR_j ............................................. 1515
5-67.
CACHE_MMU_MED_XLTE_j.......................................................................................... 1515
5-68.
Register Call Summary for Register CACHE_MMU_MED_XLTE_j .............................................. 1516
5-69.
CACHE_MMU_MED_POLICY_j
5-70.
Register Call Summary for Register CACHE_MMU_MED_POLICY_j ........................................... 1517
5-71.
CACHE_MMU_SMALL_ADDR_k ..................................................................................... 1517
5-72.
Register Call Summary for Register CACHE_MMU_SMALL_ADDR_k.......................................... 1517
5-73.
Reset Value for CACHE_MMU_SMALL_ADDR_k[31:12] ADDRESS
5-74.
5-75.
5-76.
5-77.
5-78.
5-79.
5-80.
5-81.
5-82.
5-83.
5-84.
5-85.
5-86.
5-87.
5-88.
5-89.
5-90.
5-91.
5-92.
5-93.
5-94.
5-95.
5-96.
5-97.
5-98.
5-99.
5-100.
5-101.
5-102.
5-103.
5-104.
5-105.
5-106.
6-1.
6-2.
120
......................................................................................
......................................................................................
...........................................
CACHE_MMU_SMALL_XLTE_k ......................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_XLTE_k ..........................................
Reset Value for CACHE_MMU_SMALL_XLTE_k[31:12] ADDRESS ............................................
CACHE_MMU_SMALL_POLICY_k ...................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_POLICY_k .......................................
CACHE_MMU_SMALL_MAINT_k ....................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_MAINT_k .........................................
CACHE_MMU_MAINT .................................................................................................
Register Call Summary for Register CACHE_MMU_MAINT ......................................................
CACHE_MMU_MTSTART .............................................................................................
Register Call Summary for Register CACHE_MMU_MTSTART ..................................................
CACHE_MMU_MTEND ................................................................................................
Register Call Summary for Register CACHE_MMU_MTEND .....................................................
CACHE_MMU_MAINTST ..............................................................................................
Register Call Summary for Register CACHE_MMU_MAINTST...................................................
CACHE_MMU_MMUCONFIG .........................................................................................
Register Call Summary for Register CACHE_MMU_MMUCONFIG .............................................
IPU_WUGEN Registers Mapping Summary .........................................................................
CORTEXM4_CTRL_REG ..............................................................................................
Register Call Summary for Register CORTEXM4_CTRL_REG ..................................................
STANDBY_CORE_SYSCONFIG .....................................................................................
Register Call Summary for Register STANDBY_CORE_SYSCONFIG ..........................................
IDLE_CORE_SYSCONFIG ............................................................................................
Register Call Summary for Register IDLE_CORE_SYSCONFIG .................................................
WUGEN_MEVT0 ........................................................................................................
Register Call Summary for Register WUGEN_MEVT0 ............................................................
WUGEN_MEVT1 ........................................................................................................
Register Call Summary for Register WUGEN_MEVT1 ............................................................
IPU_Cx_RW_TABLE Register Summary ............................................................................
CORTEXM4_RW_PID1 ................................................................................................
Register Call Summary for Register CORTEXM4_RW_PID1 .....................................................
CORTEXM4_RW_PID2 ................................................................................................
Register Call Summary for Register CORTEXM4_RW_PID2 .....................................................
Interface Signals .........................................................................................................
Interface Signals .........................................................................................................
List of Tables
1513
1516
1517
1518
1518
1518
1518
1519
1519
1520
1520
1521
1521
1521
1521
1522
1522
1522
1522
1523
1523
1523
1524
1524
1524
1525
1525
1525
1526
1526
1527
1527
1528
1528
1528
1528
1533
1534
SPRUIC6B – January 2017 – Revised October 2017
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Copyright © 2017, Texas Instruments Incorporated
www.ti.com
6-3.
ARP32 CPU Pipeline Operation ....................................................................................... 1539
6-4.
Control Registers ........................................................................................................ 1541
6-5.
Control Status Register (CSR) Field Descriptions
6-6.
Interrupt Enable Register (IER) Field Descriptions ................................................................. 1543
6-7.
Interrupt Flag Register (IFR) Field Descriptions..................................................................... 1544
6-8.
Interrupt Set Register (ISR) Field Descriptions ...................................................................... 1545
6-9.
Interrupt Clear Register (ICR) Field Descriptions ................................................................... 1546
6-10.
NMI Return Pointer Register (NRP) Field Descriptions ............................................................ 1547
6-11.
Interrupt Return Pointer Register (IRP) Field Descriptions ........................................................ 1547
6-12.
Link Register (LR) Field Descriptions ................................................................................. 1548
6-13.
Loop 0 Start Address Register (LSA0) Field Descriptions ......................................................... 1549
6-14.
Loop 0 End Address Register (LEA0) Field Descriptions .......................................................... 1549
6-15.
Loop 0 Iteration Count Register (LCNT0) Field Descriptions...................................................... 1550
6-16.
Loop 1 Start Address Register (LSA1) Field Descriptions ......................................................... 1551
6-17.
Loop 1 End Address Register (LEA1) Field Descriptions .......................................................... 1551
6-18.
Loop 1 Iteration Count Register (LCNT1) Field Descriptions...................................................... 1552
6-19.
Loop 0 Iteration Count Reload Value Register (LCNT0RLD) Field Descriptions ............................... 1552
6-20.
Shadow Control Status Register (SCSR) Field Descriptions
1553
6-21.
NMI Shadow Control Status Register (NMISCSR) Field Descriptions
1554
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
6-41.
6-42.
6-43.
6-44.
6-45.
6-46.
6-47.
6-48.
6-49.
6-50.
6-51.
.................................................................
.....................................................
..........................................
CPU Identification Register (CPUID) Field Descriptions ..........................................................
Decode Program Counter Register (DPC) Field Descriptions ....................................................
CPU Shadow Registers ................................................................................................
Hardware Loop Control Registers.....................................................................................
Example 1 of Generated Assembly Code (relevant instructions only) ...........................................
Example 2 of Generated Assembly Code (relevant instructions only) ...........................................
Example 1 of Generated Assembly Code (relevant instructions only) ...........................................
Example 2 of Generated Assembly Code (relevant instructions only) ...........................................
Example of Generated Assembly Code (relevant instructions only) .............................................
Example of Generated Assembly Code (relevant instructions only) .............................................
Interrupt Summary ......................................................................................................
cpu_inum_o Values .....................................................................................................
Interrupt Priorities .......................................................................................................
Interrupt Service Table (IST)...........................................................................................
Instruction Pseudo Code Notations ...................................................................................
Instruction Syntax and Opcode Notations ...........................................................................
Instruction Summary ...................................................................................................
CPU Reset Types .......................................................................................................
CPU Reset Modes ......................................................................................................
Performance Counter Signal List ......................................................................................
EVE Vector Data Memory Map ........................................................................................
VLD Data Distribution Options .........................................................................................
VCOP Arithmetic/Logic Operations ...................................................................................
Example of Operation Delay Slots ....................................................................................
EVE ST Data Distribution Options for NWAY = 8 ...................................................................
Lookup Constraints for 8-Way SIMD .................................................................................
Table Lookup and Histogram Hardware Resources ................................................................
Load and Store Address Alignment Constraints ...................................................................
Load and Store Buffering Example, Byte-Type Horizontal Filter ..................................................
Load and Store Buffering Example, Short-Type Horizontal Filter .................................................
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
1542
1555
1556
1558
1563
1566
1566
1567
1567
1568
1569
1570
1573
1573
1574
1583
1584
1585
1721
1721
1729
1729
1740
1745
1747
1749
1751
1756
1758
1759
1760
121
www.ti.com
6-52.
Parameter Indexed by rnd_param Field Descriptions .............................................................. 1773
6-53.
VCOP Instance Summary .............................................................................................. 1779
6-54.
VCOP_PID ............................................................................................................... 1779
6-55.
Register Call Summary for Register VCOP_PID .................................................................... 1780
6-56.
VCOP_CTRL............................................................................................................. 1780
6-57.
Register Call Summary for Register VCOP_CTRL ................................................................. 1780
6-58.
VCOP_STATUS ......................................................................................................... 1780
6-59.
Register Call Summary for Register VCOP_STATUS.............................................................. 1781
6-60.
VCOP_MAX_ITERS .................................................................................................... 1781
6-61.
Register Call Summary for Register VCOP_MAX_ITERS ......................................................... 1781
6-62.
VCOP_ERROR .......................................................................................................... 1781
6-63.
Register Call Summary for Register VCOP_ERROR
1783
6-64.
VCOP_VLOOP_PTR
1783
6-65.
6-66.
6-67.
6-68.
6-69.
6-70.
6-71.
6-72.
6-73.
6-74.
6-75.
6-76.
6-77.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
122
..............................................................
...................................................................................................
Register Call Summary for Register VCOP_VLOOP_PTR ........................................................
VCOP_PARAM_PTR ...................................................................................................
Register Call Summary for Register VCOP_PARAM_PTR ........................................................
VCOP_I0_I1 ..............................................................................................................
Register Call Summary for Register VCOP_I0_I1 ..................................................................
VCOP_I2_I3 ..............................................................................................................
Register Call Summary for Register VCOP_I2_I3 ..................................................................
VCOP_I4 .................................................................................................................
Register Call Summary for Register VCOP_I4 ......................................................................
VCOP_LD_PTR_i .......................................................................................................
Register Call Summary for Register VCOP_LD_PTR_i ............................................................
VCOP_ST_PTR_j .......................................................................................................
Register Call Summary for Register VCOP_ST_PTR_j ............................................................
ISS Integration Attributes ...............................................................................................
ISS Clocks and Resets .................................................................................................
ISS Hardware Requests ................................................................................................
ISS Local Clock Domains ..............................................................................................
ISS Interrupts ............................................................................................................
ISS ISP Interrupts .......................................................................................................
ISS SIMCOP High-Level Interrupts ...................................................................................
ISS LVDSRX Interrupts .................................................................................................
ISS Data Interconnect Connectivity Map .............................................................................
ISS Routing outside ISS boundaries .................................................................................
ISS Initiator ID ...........................................................................................................
ISS Video port summary ...............................................................................................
ISS Video Mux Connections List ......................................................................................
ISS Submodule Clock Gating ..........................................................................................
ISS Instance Summary .................................................................................................
ISS TOP Registers Mapping Summary ..............................................................................
ISS_HL_REVISION .....................................................................................................
Register Call Summary for Register ISS_HL_REVISION ..........................................................
ISS_HL_HWINFO .......................................................................................................
Register Call Summary for Register ISS_HL_HWINFO............................................................
ISS_HL_SYSCONFIG ..................................................................................................
Register Call Summary for Register ISS_HL_SYSCONFIG .......................................................
ISS_HL_IRQ_EOI .......................................................................................................
List of Tables
1783
1783
1784
1784
1784
1784
1784
1784
1785
1785
1785
1785
1786
1793
1793
1794
1795
1796
1797
1799
1799
1800
1801
1802
1804
1805
1807
1812
1812
1813
1813
1814
1814
1814
1815
1815
SPRUIC6B – January 2017 – Revised October 2017
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7-24.
Register Call Summary for Register ISS_HL_IRQ_EOI............................................................ 1815
7-25.
ISS_HL_IRQSTATUS_RAW_i ......................................................................................... 1816
7-26.
Register Call Summary for Register ISS_HL_IRQSTATUS_RAW_i ............................................. 1817
7-27.
ISS_HL_IRQSTATUS_i
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
................................................................................................
Register Call Summary for Register ISS_HL_IRQSTATUS_i .....................................................
ISS_HL_IRQENABLE_SET_i ..........................................................................................
Register Call Summary for Register ISS_HL_IRQENABLE_SET_i ..............................................
ISS_HL_IRQENABLE_CLR_i..........................................................................................
Register Call Summary for Register ISS_HL_IRQENABLE_CLR_i ..............................................
ISS_CTRL ................................................................................................................
Register Call Summary for Register ISS_CTRL ....................................................................
ISS_CLKCTRL ...........................................................................................................
Register Call Summary for Register ISS_CLKCTRL ...............................................................
ISS_CLKSTAT ...........................................................................................................
Register Call Summary for Register ISS_CLKSTAT ...............................................................
ISS_PM_STATUS .......................................................................................................
Register Call Summary for Register ISS_PM_STATUS ...........................................................
ISS_BYS..................................................................................................................
Register Call Summary for Register ISS_BYS ......................................................................
ISS_CTRL1 ..............................................................................................................
Register Call Summary for Register ISS_CTRL1 ...................................................................
ISS_VMUX ...............................................................................................................
Register Call Summary for Register ISS_VMUX ....................................................................
ISS_ROUTE1 ............................................................................................................
Register Call Summary for Register ISS_ROUTE1.................................................................
ISS_ROUTE2 ............................................................................................................
Register Call Summary for Register ISS_ROUTE2.................................................................
ISS_ROUTE3 ............................................................................................................
Register Call Summary for Register ISS_ROUTE3.................................................................
ISS_EMU_OUT ..........................................................................................................
Register Call Summary for Register ISS_EMU_OUT ..............................................................
ISS_VMUX_RESET .....................................................................................................
Register Call Summary for Register ISS_VMUX_RESET .........................................................
ISS_VMUX_IRQSTATUS_RAW ......................................................................................
Register Call Summary for Register ISS_VMUX_IRQSTATUS_RAW ...........................................
ISS_VMUX_IRQSTATUS ..............................................................................................
Register Call Summary for Register ISS_VMUX_IRQSTATUS ...................................................
ISS_VMUX_IRQENABLE_SET .......................................................................................
Register Call Summary for Register ISS_VMUX_IRQENABLE_SET ............................................
ISS_VMUX_IRQENABLE_CLR .......................................................................................
Register Call Summary for Register ISS_VMUX_IRQENABLE_CLR ............................................
ISS_ICM_A_TC_k .......................................................................................................
Register Call Summary for Register ISS_ICM_A_TC_k ...........................................................
ISS_ICM_A_CME_k ....................................................................................................
Register Call Summary for Register ISS_ICM_A_CME_k .........................................................
ISS_ICM_B_TC_k .......................................................................................................
Register Call Summary for Register ISS_ICM_B_TC_k ...........................................................
ISS_REQINFO_MAP0_7 ...............................................................................................
Register Call Summary for Register ISS_REQINFO_MAP0_7 ...................................................
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
1818
1819
1820
1821
1822
1823
1824
1825
1825
1827
1827
1829
1830
1831
1831
1832
1832
1833
1833
1835
1835
1836
1836
1837
1837
1839
1839
1840
1840
1841
1841
1842
1842
1843
1843
1844
1844
1845
1845
1845
1845
1845
1846
1846
1846
1847
123
www.ti.com
7-73.
ISS_REQINFO_MAP8_15 ............................................................................................. 1847
7-74.
Register Call Summary for Register ISS_REQINFO_MAP8_15 .................................................. 1848
7-75.
ISS_REQINFO_MAP16_23 ............................................................................................ 1848
7-76.
Register Call Summary for Register ISS_REQINFO_MAP16_23 ................................................ 1849
7-77.
ISS_REQINFO_MAP24_31 ............................................................................................ 1849
7-78.
Register Call Summary for Register ISS_REQINFO_MAP24_31 ................................................ 1849
7-79.
ISS CTSET Registers Mapping Summary ........................................................................... 1850
7-80.
CTSETIDEN
7-81.
Register Call Summary for Register CTSETIDEN .................................................................. 1853
7-82.
CTSETSYSCFG ......................................................................................................... 1853
7-83.
Register Call Summary for Register CTSETSYSCFG
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
7-100.
7-101.
7-102.
7-103.
7-104.
7-105.
7-106.
7-107.
7-108.
7-109.
7-110.
7-111.
7-112.
7-113.
7-114.
7-115.
7-116.
7-117.
7-118.
7-119.
7-120.
7-121.
124
.............................................................................................................
.............................................................
SETSTR ..................................................................................................................
Register Call Summary for Register SETSTR .......................................................................
CTSETCFG ..............................................................................................................
Register Call Summary for Register CTSETCFG ...................................................................
SETSPLREG.............................................................................................................
Register Call Summary for Register SETSPLREG .................................................................
SETEVTENBL1 ..........................................................................................................
Register Call Summary for Register SETEVTENBL1 ..............................................................
SETEVTENBL2 ..........................................................................................................
Register Call Summary for Register SETEVTENBL2 ..............................................................
SETEVTENBL3 ..........................................................................................................
Register Call Summary for Register SETEVTENBL3 ..............................................................
SETEVTENBL4 ..........................................................................................................
Register Call Summary for Register SETEVTENBL4 ..............................................................
SETEVTENBL5 ..........................................................................................................
Register Call Summary for Register SETEVTENBL5 ..............................................................
SETEVTENBL6 ..........................................................................................................
Register Call Summary for Register SETEVTENBL6 ..............................................................
SETEVTENBL7 ..........................................................................................................
Register Call Summary for Register SETEVTENBL7 ..............................................................
SETEVTENBL8 ..........................................................................................................
Register Call Summary for Register SETEVTENBL8 ..............................................................
SETMSTID ...............................................................................................................
Register Call Summary for Register SETMSTID ....................................................................
CTCNTL ..................................................................................................................
Register Call Summary for Register CTCNTL .......................................................................
CTSTMCNTL ............................................................................................................
Register Call Summary for Register CTSTMCNTL .................................................................
CTSTMMSTID ...........................................................................................................
Register Call Summary for Register CTSTMMSTID ................................................................
CTSTMINTVL ............................................................................................................
Register Call Summary for Register CTSTMINTVL ................................................................
CTSTMSEL0 .............................................................................................................
Register Call Summary for Register CTSTMSEL0 .................................................................
CTSTMSEL1 .............................................................................................................
Register Call Summary for Register CTSTMSEL1 .................................................................
TINTVLR0 ................................................................................................................
Register Call Summary for Register TINTVLR0.....................................................................
List of Tables
1852
1853
1853
1854
1854
1854
1854
1855
1855
1855
1855
1855
1855
1856
1856
1856
1856
1856
1856
1857
1857
1857
1857
1858
1858
1858
1858
1859
1859
1859
1859
1859
1860
1860
1860
1860
1860
1861
1861
1861
SPRUIC6B – January 2017 – Revised October 2017
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7-122. TINTVLR1 ................................................................................................................ 1861
7-123. Register Call Summary for Register TINTVLR1..................................................................... 1861
7-124. TINTVLR2 ................................................................................................................ 1861
7-125. Register Call Summary for Register TINTVLR2..................................................................... 1862
7-126. TINTVLR3 ................................................................................................................ 1862
7-127. Register Call Summary for Register TINTVLR3..................................................................... 1862
7-128. TINTVLR4 ................................................................................................................ 1862
7-129. Register Call Summary for Register TINTVLR4..................................................................... 1862
7-130. TINTVLR5 ................................................................................................................ 1862
7-131. Register Call Summary for Register TINTVLR5..................................................................... 1863
7-132. TINTVLR6 ................................................................................................................ 1863
7-133. Register Call Summary for Register TINTVLR6..................................................................... 1863
7-134. TINTVLR7 ................................................................................................................ 1863
7-135. Register Call Summary for Register TINTVLR7..................................................................... 1863
7-136. TINTVLR8 ................................................................................................................ 1863
7-137. Register Call Summary for Register TINTVLR8..................................................................... 1864
7-138. TINTVLR9 ................................................................................................................ 1864
7-139. Register Call Summary for Register TINTVLR9..................................................................... 1864
7-140. TINTVLR10............................................................................................................... 1864
7-141. Register Call Summary for Register TINTVLR10 ................................................................... 1864
7-142. TINTVLR11............................................................................................................... 1865
7-143. Register Call Summary for Register TINTVLR11 ................................................................... 1865
7-144. TINTVLR12............................................................................................................... 1865
7-145. Register Call Summary for Register TINTVLR12 ................................................................... 1865
7-146. TINTVLR13............................................................................................................... 1865
7-147. Register Call Summary for Register TINTVLR13 ................................................................... 1866
7-148. TINTVLR14............................................................................................................... 1866
7-149. Register Call Summary for Register TINTVLR14 ................................................................... 1866
7-150. TINTVLR15............................................................................................................... 1866
7-151. Register Call Summary for Register TINTVLR15 ................................................................... 1866
7-152. CTNUMDBG ............................................................................................................. 1866
7-153. Register Call Summary for Register CTNUMDBG .................................................................. 1867
7-154. CTDBGSGL0
............................................................................................................
1867
7-155. Register Call Summary for Register CTDBGSGL0 ................................................................. 1867
7-156. CTDBGSGL1
............................................................................................................
1867
7-157. Register Call Summary for Register CTDBGSGL1 ................................................................. 1867
7-158. CTDBGSGL2
............................................................................................................
1867
7-159. Register Call Summary for Register CTDBGSGL2 ................................................................. 1868
............................................................................................................
Register Call Summary for Register CTDBGSGL3 .................................................................
CTDBGSGL4 ............................................................................................................
Register Call Summary for Register CTDBGSGL4 .................................................................
CTDBGSGL5 ............................................................................................................
Register Call Summary for Register CTDBGSGL5 .................................................................
CTDBGSGL6 ............................................................................................................
Register Call Summary for Register CTDBGSGL6 .................................................................
CTDBGSGL7 ............................................................................................................
Register Call Summary for Register CTDBGSGL7 .................................................................
CTGNBL0 ................................................................................................................
7-160. CTDBGSGL3
7-161.
7-162.
7-163.
7-164.
7-165.
7-166.
7-167.
7-168.
7-169.
7-170.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
1868
1868
1868
1869
1869
1869
1869
1869
1869
1870
1870
125
www.ti.com
7-171. Register Call Summary for Register CTGNBL0 ..................................................................... 1870
7-172. CTGNBL1 ................................................................................................................ 1870
7-173. Register Call Summary for Register CTGNBL1 ..................................................................... 1870
7-174. CTGRST0 ................................................................................................................ 1871
7-175. Register Call Summary for Register CTGRST0 ..................................................................... 1871
7-176. CTGRST1 ................................................................................................................ 1871
7-177. Register Call Summary for Register CTGRST1 ..................................................................... 1871
7-178. CTCR0 .................................................................................................................... 1871
7-179. Register Call Summary for Register CTCR0 ........................................................................ 1872
7-180. CTCR1 .................................................................................................................... 1872
7-181. Register Call Summary for Register CTCR1 ........................................................................ 1873
7-182. CTCR2 .................................................................................................................... 1873
7-183. Register Call Summary for Register CTCR2 ........................................................................ 1873
7-184. CTCR3 .................................................................................................................... 1874
7-185. Register Call Summary for Register CTCR3 ........................................................................ 1874
7-186. CTCR4 .................................................................................................................... 1874
7-187. Register Call Summary for Register CTCR4 ........................................................................ 1875
7-188. CTCR5 .................................................................................................................... 1875
7-189. Register Call Summary for Register CTCR5 ........................................................................ 1876
7-190. CTCR6 .................................................................................................................... 1876
7-191. Register Call Summary for Register CTCR6 ........................................................................ 1876
7-192. CTCR7 .................................................................................................................... 1877
7-193. Register Call Summary for Register CTCR7 ........................................................................ 1877
7-194. CTCR8 .................................................................................................................... 1877
7-195. Register Call Summary for Register CTCR8 ........................................................................ 1878
7-196. CTCR9 .................................................................................................................... 1878
7-197. Register Call Summary for Register CTCR9 ........................................................................ 1879
7-198. CTCR10 .................................................................................................................. 1879
7-199. Register Call Summary for Register CTCR10 ....................................................................... 1879
7-200. CTCR11 .................................................................................................................. 1880
7-201. Register Call Summary for Register CTCR11 ....................................................................... 1880
7-202. CTCR12 .................................................................................................................. 1880
7-203. Register Call Summary for Register CTCR12 ....................................................................... 1881
7-204. CTCR13 .................................................................................................................. 1881
7-205. Register Call Summary for Register CTCR13 ....................................................................... 1882
7-206. CTCR14 .................................................................................................................. 1882
7-207. Register Call Summary for Register CTCR14 ....................................................................... 1882
7-208. CTCR15 .................................................................................................................. 1883
7-209. Register Call Summary for Register CTCR15 ....................................................................... 1883
7-210. CTCR16 .................................................................................................................. 1883
7-211. Register Call Summary for Register CTCR16 ....................................................................... 1884
7-212. CTCR17 .................................................................................................................. 1884
7-213. Register Call Summary for Register CTCR17 ....................................................................... 1885
7-214. CTCR18 .................................................................................................................. 1885
7-215. Register Call Summary for Register CTCR18 ....................................................................... 1885
7-216. CTCR19 .................................................................................................................. 1886
7-217. Register Call Summary for Register CTCR19 ....................................................................... 1886
7-218. CTCR20 .................................................................................................................. 1886
7-219. Register Call Summary for Register CTCR20 ....................................................................... 1887
126
List of Tables
SPRUIC6B – January 2017 – Revised October 2017
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7-220. CTCR21 .................................................................................................................. 1887
7-221. Register Call Summary for Register CTCR21 ....................................................................... 1888
7-222. CTCR22 .................................................................................................................. 1888
7-223. Register Call Summary for Register CTCR22 ....................................................................... 1888
7-224. CTCR23 .................................................................................................................. 1889
7-225. Register Call Summary for Register CTCR23 ....................................................................... 1889
7-226. CTCR24 .................................................................................................................. 1889
7-227. Register Call Summary for Register CTCR24 ....................................................................... 1890
7-228. CTCR25 .................................................................................................................. 1890
7-229. Register Call Summary for Register CTCR25 ....................................................................... 1891
7-230. CTCR26 .................................................................................................................. 1891
7-231. Register Call Summary for Register CTCR26 ....................................................................... 1891
7-232. CTCR27 .................................................................................................................. 1892
7-233. Register Call Summary for Register CTCR27 ....................................................................... 1892
7-234. CTCR28 .................................................................................................................. 1892
7-235. Register Call Summary for Register CTCR28 ....................................................................... 1893
7-236. CTCR29 .................................................................................................................. 1893
7-237. Register Call Summary for Register CTCR29 ....................................................................... 1894
7-238. CTCR30 .................................................................................................................. 1894
7-239. Register Call Summary for Register CTCR30 ....................................................................... 1894
7-240. CTCR31 .................................................................................................................. 1895
7-241. Register Call Summary for Register CTCR31 ....................................................................... 1895
7-242. CTCNTR0 ................................................................................................................ 1895
7-243. Register Call Summary for Register CTCNTR0 ..................................................................... 1896
7-244. CTCNTR1 ................................................................................................................ 1896
7-245. Register Call Summary for Register CTCNTR1 ..................................................................... 1896
7-246. CTCNTR2 ................................................................................................................ 1896
7-247. Register Call Summary for Register CTCNTR2 ..................................................................... 1896
7-248. CTCNTR3 ................................................................................................................ 1896
7-249. Register Call Summary for Register CTCNTR3 ..................................................................... 1897
7-250. CTCNTR4 ................................................................................................................ 1897
7-251. Register Call Summary for Register CTCNTR4 ..................................................................... 1897
7-252. CTCNTR5 ................................................................................................................ 1897
7-253. Register Call Summary for Register CTCNTR5 ..................................................................... 1897
7-254. CTCNTR6 ................................................................................................................ 1897
7-255. Register Call Summary for Register CTCNTR6 ..................................................................... 1898
7-256. CTCNTR7 ................................................................................................................ 1898
7-257. Register Call Summary for Register CTCNTR7 ..................................................................... 1898
7-258. CTCNTR8 ................................................................................................................ 1898
7-259. Register Call Summary for Register CTCNTR8 ..................................................................... 1898
7-260. CTCNTR9 ................................................................................................................ 1898
7-261. Register Call Summary for Register CTCNTR9 ..................................................................... 1899
7-262. CTCNTR10 ............................................................................................................... 1899
7-263. Register Call Summary for Register CTCNTR10 ................................................................... 1899
7-264. CTCNTR11 ............................................................................................................... 1899
7-265. Register Call Summary for Register CTCNTR11 ................................................................... 1899
7-266. CTCNTR12 ............................................................................................................... 1900
7-267. Register Call Summary for Register CTCNTR12 ................................................................... 1900
7-268. CTCNTR13 ............................................................................................................... 1900
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7-269. Register Call Summary for Register CTCNTR13 ................................................................... 1900
7-270. CTCNTR14 ............................................................................................................... 1900
7-271. Register Call Summary for Register CTCNTR14 ................................................................... 1901
7-272. CTCNTR15 ............................................................................................................... 1901
7-273. Register Call Summary for Register CTCNTR15 ................................................................... 1901
7-274. CTCNTR16 ............................................................................................................... 1901
7-275. Register Call Summary for Register CTCNTR16 ................................................................... 1901
7-276. CTCNTR17 ............................................................................................................... 1901
7-277. Register Call Summary for Register CTCNTR17 ................................................................... 1902
7-278. CTCNTR18 ............................................................................................................... 1902
7-279. Register Call Summary for Register CTCNTR18 ................................................................... 1902
7-280. CTCNTR19 ............................................................................................................... 1902
7-281. Register Call Summary for Register CTCNTR19 ................................................................... 1902
7-282. CTCNTR20 ............................................................................................................... 1902
7-283. Register Call Summary for Register CTCNTR20 ................................................................... 1903
7-284. CTCNTR21 ............................................................................................................... 1903
7-285. Register Call Summary for Register CTCNTR21 ................................................................... 1903
7-286. CTCNTR22 ............................................................................................................... 1903
7-287. Register Call Summary for Register CTCNTR22 ................................................................... 1903
7-288. CTCNTR23 ............................................................................................................... 1903
7-289. Register Call Summary for Register CTCNTR23 ................................................................... 1904
7-290. CTCNTR24 ............................................................................................................... 1904
7-291. Register Call Summary for Register CTCNTR24 ................................................................... 1904
7-292. CTCNTR25 ............................................................................................................... 1904
7-293. Register Call Summary for Register CTCNTR25 ................................................................... 1904
7-294. CTCNTR26 ............................................................................................................... 1905
7-295. Register Call Summary for Register CTCNTR26 ................................................................... 1905
7-296. CTCNTR27 ............................................................................................................... 1905
7-297. Register Call Summary for Register CTCNTR27 ................................................................... 1905
7-298. CTCNTR28 ............................................................................................................... 1905
7-299. Register Call Summary for Register CTCNTR28 ................................................................... 1906
7-300. CTCNTR29 ............................................................................................................... 1906
7-301. Register Call Summary for Register CTCNTR29 ................................................................... 1906
7-302. CTCNTR30 ............................................................................................................... 1906
7-303. Register Call Summary for Register CTCNTR30 ................................................................... 1906
7-304. CTCNTR31 ............................................................................................................... 1906
7-305. Register Call Summary for Register CTCNTR31 ................................................................... 1907
7-306. CTEOI..................................................................................................................... 1907
7-307. Register Call Summary for Register CTEOI ......................................................................... 1907
7-308. CTIRQSTAT_RAW ...................................................................................................... 1907
7-309. Register Call Summary for Register CTIRQSTAT_RAW .......................................................... 1907
7-310. CTIRQSTAT
.............................................................................................................
1907
7-311. Register Call Summary for Register CTIRQSTAT .................................................................. 1908
7-312. CTIRQENABLE_SET ................................................................................................... 1908
7-313. Register Call Summary for Register CTIRQENABLE_SET........................................................ 1908
7-314. CTIRQENABLE_CLR ................................................................................................... 1908
7-315. Register Call Summary for Register CTIRQENABLE_CLR
.......................................................
1908
7-316. ISS Interfaces I/O Description ......................................................................................... 1914
7-317. ISS Interfaces Connectivity Scheme Example Scenarios
128
List of Tables
.........................................................
1917
SPRUIC6B – January 2017 – Revised October 2017
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7-318. ISS Interfaces CPI Video Timing Reference Codes for SAV and EAV .......................................... 1919
7-319. ISS Interfaces CPI F, V, H Signal Descriptions ..................................................................... 1920
7-320. ISS Interfaces CPI F, V, H Protection (Error-Correction) Bits ..................................................... 1920
7-321. ISS Interfaces CPI ITU-R BT.656 Mode Data Format in SDRAM ................................................ 1920
7-322. ISS CSI2 PHY Possible Time-Out Value for RxMode Counter ................................................... 1923
7-323. ISS CSI2 PHY Instance Summary .................................................................................... 1928
7-324. ISS CSI2 PHY Registers Mapping Summary........................................................................ 1928
7-325. REG0
.....................................................................................................................
1928
7-326. Register Call Summary for Register REG0 .......................................................................... 1929
7-327. REG1
.....................................................................................................................
1929
7-328. Register Call Summary for Register REG1 .......................................................................... 1930
7-329. REG2
.....................................................................................................................
1931
7-330. Register Call Summary for Register REG2 .......................................................................... 1931
.....................................................................................................................
Register Call Summary for Register REG3 ..........................................................................
REG6 .....................................................................................................................
Register Call Summary for Register REG6 ..........................................................................
REG7 .....................................................................................................................
Register Call Summary for Register REG7 ..........................................................................
REG8 .....................................................................................................................
Register Call Summary for Register REG8 ..........................................................................
REG9 .....................................................................................................................
Register Call Summary for Register REG9 ..........................................................................
REG10 ....................................................................................................................
Register Call Summary for Register REG10 ........................................................................
LVDS-RX CSI2_PHY1 I/O Description ...............................................................................
LVDS-RX Parallel Interface I/O Description .........................................................................
LVDS-RX Integration Attributes .......................................................................................
LVDS-RX Clocks and Resets ..........................................................................................
LVDS-RX Hardware Requests ........................................................................................
LVDS-RX 12-16bit data decompression register configuration ...................................................
.............................................................................................................................
ISS LVDS-RX Instance Summary.....................................................................................
ISS LVDS-RX Registers Mapping Summary ........................................................................
LVDSRX_REVISION....................................................................................................
Register Call Summary for Register LVDSRX_REVISION ........................................................
LVDSRX_SYSCONFIG.................................................................................................
Register Call Summary for Register LVDSRX_SYSCONFIG .....................................................
LVDSRX_CAMCFG .....................................................................................................
Register Call Summary for Register LVDSRX_CAMCFG .........................................................
LVDSRX_IRQ_EOI......................................................................................................
Register Call Summary for Register LVDSRX_IRQ_EOI ..........................................................
LVDSRX_IRQSTATUS_RAW_0 ......................................................................................
Register Call Summary for Register LVDSRX_IRQSTATUS_RAW_0 ...........................................
LVDSRX_IRQSTATUS_0 ..............................................................................................
Register Call Summary for Register LVDSRX_IRQSTATUS_0...................................................
LVDSRX_IRQENABLE_SET_0 .......................................................................................
Register Call Summary for Register LVDSRX_IRQENABLE_SET_0 ............................................
LVDSRX_IRQENABLE_CLR_0 .......................................................................................
7-331. REG3
1932
7-332.
1933
7-333.
7-334.
7-335.
7-336.
7-337.
7-338.
7-339.
7-340.
7-341.
7-342.
7-343.
7-344.
7-345.
7-346.
7-347.
7-348.
7-349.
7-350.
7-351.
7-352.
7-353.
7-354.
7-355.
7-356.
7-357.
7-358.
7-359.
7-360.
7-361.
7-362.
7-363.
7-364.
7-365.
7-366.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
1933
1934
1934
1935
1935
1936
1937
1938
1938
1938
1939
1940
1942
1942
1942
1945
1945
1947
1947
1949
1949
1949
1950
1950
1951
1951
1951
1951
1952
1952
1953
1953
1954
1954
129
www.ti.com
7-367. Register Call Summary for Register LVDSRX_IRQENABLE_CLR_0 ............................................ 1955
7-368. LVDSRX_IRQSTATUS_RAW_1 ...................................................................................... 1955
7-369. Register Call Summary for Register LVDSRX_IRQSTATUS_RAW_1 ........................................... 1956
7-370. LVDSRX_IRQSTATUS_1 .............................................................................................. 1956
7-371. Register Call Summary for Register LVDSRX_IRQSTATUS_1................................................... 1957
7-372. LVDSRX_IRQENABLE_SET_1 ....................................................................................... 1957
7-373. Register Call Summary for Register LVDSRX_IRQENABLE_SET_1 ............................................ 1958
7-374. LVDSRX_IRQENABLE_CLR_1 ....................................................................................... 1958
7-375. Register Call Summary for Register LVDSRX_IRQENABLE_CLR_1 ............................................ 1959
7-376. LVDSRX_IRQSTATUS_RAW2_2 ..................................................................................... 1959
7-377. Register Call Summary for Register LVDSRX_IRQSTATUS_RAW2_2 ......................................... 1960
7-378. LVDSRX_IRQSTATUS_2 .............................................................................................. 1960
7-379. Register Call Summary for Register LVDSRX_IRQSTATUS_2................................................... 1961
7-380. LVDSRX_IRQENABLE_SET_2 ....................................................................................... 1961
7-381. Register Call Summary for Register LVDSRX_IRQENABLE_SET_2 ............................................ 1962
7-382. LVDSRX_IRQENABLE_CLR_2 ....................................................................................... 1962
7-383. Register Call Summary for Register LVDSRX_IRQENABLE_CLR_2 ............................................ 1963
7-384. LVDSRX_IRQSTATUS_RAW_3 ...................................................................................... 1963
7-385. Register Call Summary for Register LVDSRX_IRQSTATUS_RAW_3 ........................................... 1964
7-386. LVDSRX_IRQSTATUS_3 .............................................................................................. 1964
7-387. Register Call Summary for Register LVDSRX_IRQSTATUS_3................................................... 1965
7-388. LVDSRX_IRQENABLE_SET_3 ....................................................................................... 1965
7-389. Register Call Summary for Register LVDSRX_IRQENABLE_SET_3 ............................................ 1966
7-390. LVDSRX_IRQENABLE_CLR_3 ....................................................................................... 1966
7-391. Register Call Summary for Register LVDSRX_IRQENABLE_CLR_3 ............................................ 1967
7-392. LVDSRX_CAM1_CFG .................................................................................................. 1967
7-393. Register Call Summary for Register LVDSRX_CAM1_CFG ...................................................... 1968
7-394. LVDSRX_CAM1_FRMSIZE ............................................................................................ 1968
7-395. Register Call Summary for Register LVDSRX_CAM1_FRMSIZE ................................................ 1969
7-396. LVDSRX_CAM1_MAXWIDTH ......................................................................................... 1969
7-397. Register Call Summary for Register LVDSRX_CAM1_MAXWIDTH ............................................. 1969
7-398. LVDSRX_CAM1_SYNCSOF
..........................................................................................
1969
7-399. Register Call Summary for Register LVDSRX_CAM1_SYNCSOF ............................................... 1969
1970
7-401.
1970
7-402.
7-403.
7-404.
7-405.
7-406.
7-407.
7-408.
7-409.
7-410.
7-411.
7-412.
7-413.
7-414.
7-415.
130
..........................................................................................
Register Call Summary for Register LVDSRX_CAM1_SYNCEOF ...............................................
LVDSRX_CAM1_SYNCSOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM1_SYNCSOL ...............................................
LVDSRX_CAM1_SYNCEOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM1_SYNCEOL ...............................................
LVDSRX_CAM1_SYNCSOV ..........................................................................................
Register Call Summary for Register LVDSRX_CAM1_SYNCSOV ...............................................
LVDSRX_CAM2_CFG ..................................................................................................
Register Call Summary for Register LVDSRX_CAM2_CFG ......................................................
LVDSRX_CAM2_FRMSIZE ............................................................................................
Register Call Summary for Register LVDSRX_CAM2_FRMSIZE ................................................
LVDSRX_CAM2_MAXWIDTH .........................................................................................
Register Call Summary for Register LVDSRX_CAM2_MAXWIDTH .............................................
LVDSRX_CAM2_SYNCSOF ..........................................................................................
Register Call Summary for Register LVDSRX_CAM2_SYNCSOF ...............................................
7-400. LVDSRX_CAM1_SYNCEOF
List of Tables
1970
1970
1970
1971
1971
1971
1971
1972
1972
1972
1973
1973
1973
1973
SPRUIC6B – January 2017 – Revised October 2017
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..........................................................................................
Register Call Summary for Register LVDSRX_CAM2_SYNCEOF ...............................................
LVDSRX_CAM2_SYNCSOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM2_SYNCSOL ...............................................
LVDSRX_CAM2_SYNCEOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM2_SYNCEOL ...............................................
LVDSRX_CAM2_SYNCSOV ..........................................................................................
Register Call Summary for Register LVDSRX_CAM2_SYNCSOV ...............................................
LVDSRX_CAM3_CFG ..................................................................................................
Register Call Summary for Register LVDSRX_CAM3_CFG ......................................................
LVDSRX_CAM3_FRMSIZE ............................................................................................
Register Call Summary for Register LVDSRX_CAM3_FRMSIZE ................................................
LVDSRX_CAM3_MAXWIDTH .........................................................................................
Register Call Summary for Register LVDSRX_CAM3_MAXWIDTH .............................................
LVDSRX_CAM3_SYNCSOF ..........................................................................................
Register Call Summary for Register LVDSRX_CAM3_SYNCSOF ...............................................
LVDSRX_CAM3_SYNCEOF ..........................................................................................
Register Call Summary for Register LVDSRX_CAM3_SYNCEOF ...............................................
LVDSRX_CAM3_SYNCSOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM3_SYNCSOL ...............................................
LVDSRX_CAM3_SYNCEOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM3_SYNCEOL ...............................................
LVDSRX_CAM3_SYNCSOV ..........................................................................................
Register Call Summary for Register LVDSRX_CAM3_SYNCSOV ...............................................
LVDSRX_CAM4_CFG ..................................................................................................
Register Call Summary for Register LVDSRX_CAM4_CFG ......................................................
LVDSRX_CAM4_FRMSIZE ............................................................................................
Register Call Summary for Register LVDSRX_CAM4_FRMSIZE ................................................
LVDSRX_CAM4_MAXWIDTH .........................................................................................
Register Call Summary for Register LVDSRX_CAM4_MAXWIDTH .............................................
LVDSRX_CAM4_SYNCSOF ..........................................................................................
Register Call Summary for Register LVDSRX_CAM4_SYNCSOF ...............................................
LVDSRX_CAM4_SYNCEOF ..........................................................................................
Register Call Summary for Register LVDSRX_CAM4_SYNCEOF ...............................................
LVDSRX_CAM4_SYNCSOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM4_SYNCSOL ...............................................
LVDSRX_CAM4_SYNCEOL...........................................................................................
Register Call Summary for Register LVDSRX_CAM4_SYNCEOL ...............................................
LVDSRX_CAM4_SYNCSOV ..........................................................................................
Register Call Summary for Register LVDSRX_CAM4_SYNCSOV ...............................................
LVDSRX_WDRCFG ....................................................................................................
Register Call Summary for Register LVDSRX_WDRCFG .........................................................
LVDSRX_WDRGN ......................................................................................................
Register Call Summary for Register LVDSRX_WDRGN...........................................................
LVDSRX_WDRKP1 .....................................................................................................
Register Call Summary for Register LVDSRX_WDRKP1 .........................................................
LVDSRX_WDRKP2 .....................................................................................................
Register Call Summary for Register LVDSRX_WDRKP2 .........................................................
LVDSRX_TEST1 ........................................................................................................
7-416. LVDSRX_CAM2_SYNCEOF
1973
7-417.
1974
7-418.
7-419.
7-420.
7-421.
7-422.
7-423.
7-424.
7-425.
7-426.
7-427.
7-428.
7-429.
7-430.
7-431.
7-432.
7-433.
7-434.
7-435.
7-436.
7-437.
7-438.
7-439.
7-440.
7-441.
7-442.
7-443.
7-444.
7-445.
7-446.
7-447.
7-448.
7-449.
7-450.
7-451.
7-452.
7-453.
7-454.
7-455.
7-456.
7-457.
7-458.
7-459.
7-460.
7-461.
7-462.
7-463.
7-464.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
1974
1974
1974
1974
1975
1975
1975
1976
1976
1976
1976
1976
1977
1977
1977
1977
1977
1978
1978
1978
1978
1978
1979
1979
1980
1980
1980
1980
1980
1981
1981
1981
1981
1981
1982
1982
1982
1982
1982
1983
1983
1983
1983
1983
1983
1984
1984
131
www.ti.com
7-465. Register Call Summary for Register LVDSRX_TEST1 ............................................................. 1984
7-466. LVDSRX_TEST2 ........................................................................................................ 1984
7-467. Register Call Summary for Register LVDSRX_TEST2 ............................................................. 1984
7-468. LVDSRX_TEST3 ........................................................................................................ 1985
7-469. Register Call Summary for Register LVDSRX_TEST3 ............................................................. 1985
7-470. LVDSRX_TEST4 ........................................................................................................ 1985
7-471. Register Call Summary for Register LVDSRX_TEST4 ............................................................. 1985
7-472. CAL_A I/O Description.................................................................................................. 1986
7-473. CAL Integration Attributes .............................................................................................. 1990
7-474. CAL Clocks and Resets ................................................................................................ 1990
7-475. CAL Hardware Requests ............................................................................................... 1990
7-476. CAL Video Port Signals
................................................................................................
1991
7-477. CSI2 Low Level Protocol Interrupts ................................................................................... 1995
7-478. CSI2 Complex I/O Interrupts ........................................................................................... 1995
1996
7-480. CAL Line Number Interrupt
1996
7-481.
7-482.
7-483.
7-484.
7-485.
7-486.
7-487.
7-488.
7-489.
7-490.
7-491.
7-492.
7-493.
7-494.
7-495.
7-496.
7-497.
7-498.
7-499.
7-500.
7-501.
7-502.
7-503.
7-504.
7-505.
7-506.
7-507.
7-508.
7-509.
7-510.
7-511.
7-512.
7-513.
132
.............................................................................................
............................................................................................
CAL Video Port EOF Interrupt .........................................................................................
CSI2_PHY1 I/O Description............................................................................................
CSI2 Long Packet Structure Description .............................................................................
CSI2 ECC Event Logging ..............................................................................................
CSI2 Synchronization Codes ..........................................................................................
CAL DPCM Formats ....................................................................................................
Write DMA - Line Start Address Computation .......................................................................
CAL Supported Read DMA Mode Combinations ...................................................................
CAL Read DMA .........................................................................................................
CAL Registers Shadowing .............................................................................................
CAL Instance Summary ................................................................................................
CAL Registers Mapping Summary ....................................................................................
CAL_HL_REVISION ....................................................................................................
Register Call Summary for Register CAL_HL_REVISION .........................................................
CAL_HL_HWINFO ......................................................................................................
Register Call Summary for Register CAL_HL_HWINFO ...........................................................
CAL_HL_SYSCONFIG .................................................................................................
Register Call Summary for Register CAL_HL_SYSCONFIG ......................................................
CAL_HL_IRQ_EOI ......................................................................................................
Register Call Summary for Register CAL_HL_IRQ_EOI ...........................................................
CAL_HL_IRQSTATUS_RAW_j ........................................................................................
Register Call Summary for Register CAL_HL_IRQSTATUS_RAW_j ............................................
CAL_HL_IRQSTATUS_j................................................................................................
Register Call Summary for Register CAL_HL_IRQSTATUS_j ....................................................
CAL_HL_IRQENABLE_SET_j .........................................................................................
Register Call Summary for Register CAL_HL_IRQENABLE_SET_j .............................................
CAL_HL_IRQENABLE_CLR_j .........................................................................................
Register Call Summary for Register CAL_HL_IRQENABLE_CLR_j .............................................
CAL_PIX_PROC_i ......................................................................................................
Register Call Summary for Register CAL_PIX_PROC_i ...........................................................
CAL_CTRL ...............................................................................................................
Register Call Summary for Register CAL_CTRL....................................................................
CAL_CTRL1 .............................................................................................................
7-479. CAL Write DMA Interrupts
List of Tables
1996
1999
2004
2005
2006
2015
2023
2025
2026
2036
2038
2038
2041
2041
2041
2042
2042
2043
2043
2043
2044
2047
2048
2051
2052
2055
2056
2059
2060
2061
2061
2062
2062
SPRUIC6B – January 2017 – Revised October 2017
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7-514. Register Call Summary for Register CAL_CTRL1 .................................................................. 2063
7-515. CAL_LINE_NUMBER_EVT ............................................................................................ 2063
7-516. Register Call Summary for Register CAL_LINE_NUMBER_EVT ................................................. 2064
7-517. CAL_VPORT_CTRL1 ................................................................................................... 2064
7-518. Register Call Summary for Register CAL_VPORT_CTRL1 ....................................................... 2064
7-519. CAL_VPORT_CTRL2 ................................................................................................... 2065
7-520. Register Call Summary for Register CAL_VPORT_CTRL2 ....................................................... 2065
7-521. CAL_BYS_CTRL1....................................................................................................... 2066
7-522. Register Call Summary for Register CAL_BYS_CTRL1 ........................................................... 2066
7-523. CAL_BYS_CTRL2....................................................................................................... 2066
7-524. Register Call Summary for Register CAL_BYS_CTRL2 ........................................................... 2067
7-525. CAL_RD_DMA_CTRL .................................................................................................. 2067
7-526. Register Call Summary for Register CAL_RD_DMA_CTRL ....................................................... 2068
7-527. CAL_RD_DMA_PIX_ADDR ............................................................................................ 2068
7-528. Register Call Summary for Register CAL_RD_DMA_PIX_ADDR ................................................ 2068
7-529. CAL_RD_DMA_PIX_OFST ............................................................................................ 2069
7-530. Register Call Summary for Register CAL_RD_DMA_PIX_OFST ................................................. 2069
7-531. CAL_RD_DMA_XSIZE
.................................................................................................
2069
7-532. Register Call Summary for Register CAL_RD_DMA_XSIZE ...................................................... 2069
7-533. CAL_RD_DMA_YSIZE
.................................................................................................
2070
7-534. Register Call Summary for Register CAL_RD_DMA_YSIZE ...................................................... 2070
7-535. CAL_RD_DMA_INIT_ADDR ........................................................................................... 2070
...............................................
...........................................................................................
Register Call Summary for Register CAL_RD_DMA_INIT_OFST ................................................
CAL_RD_DMA_CTRL2.................................................................................................
Register Call Summary for Register CAL_RD_DMA_CTRL2 .....................................................
CAL_WR_DMA_CTRL_k ...............................................................................................
Register Call Summary for Register CAL_WR_DMA_CTRL_k ...................................................
CAL_WR_DMA_ADDR_k ..............................................................................................
Register Call Summary for Register CAL_WR_DMA_ADDR_k...................................................
CAL_WR_DMA_OFST_k ..............................................................................................
Register Call Summary for Register CAL_WR_DMA_OFST_k ...................................................
CAL_WR_DMA_XSIZE_k ..............................................................................................
Register Call Summary for Register CAL_WR_DMA_XSIZE_k ..................................................
CAL_CSI2_PPI_CTRL_l................................................................................................
Register Call Summary for Register CAL_CSI2_PPI_CTRL_l ....................................................
CAL_CSI2_COMPLEXIO_CFG_l .....................................................................................
Register Call Summary for Register CAL_CSI2_COMPLEXIO_CFG_l ..........................................
CAL_CSI2_COMPLEXIO_IRQSTATUS_l ...........................................................................
Register Call Summary for Register CAL_CSI2_COMPLEXIO_IRQSTATUS_l ................................
CAL_CSI2_SHORT_PACKET_l .......................................................................................
Register Call Summary for Register CAL_CSI2_SHORT_PACKET_l ...........................................
CAL_CSI2_COMPLEXIO_IRQENABLE_l ...........................................................................
Register Call Summary for Register CAL_CSI2_COMPLEXIO_IRQENABLE_l ................................
CAL_CSI2_TIMING_l ...................................................................................................
Register Call Summary for Register CAL_CSI2_TIMING_l........................................................
CAL_CSI2_VC_IRQENABLE_l ........................................................................................
Register Call Summary for Register CAL_CSI2_VC_IRQENABLE_l ............................................
7-536. Register Call Summary for Register CAL_RD_DMA_INIT_ADDR
2070
7-537. CAL_RD_DMA_INIT_OFST
2071
7-538.
7-539.
7-540.
7-541.
7-542.
7-543.
7-544.
7-545.
7-546.
7-547.
7-548.
7-549.
7-550.
7-551.
7-552.
7-553.
7-554.
7-555.
7-556.
7-557.
7-558.
7-559.
7-560.
7-561.
7-562.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
2071
2071
2072
2072
2074
2074
2074
2074
2075
2075
2075
2076
2076
2077
2078
2079
2082
2082
2082
2083
2085
2085
2086
2086
2088
133
www.ti.com
7-563. CAL_CSI2_VC_IRQSTATUS_l ........................................................................................ 2088
7-564. Register Call Summary for Register CAL_CSI2_VC_IRQSTATUS_l ............................................ 2091
7-565. CAL_CSI2_CTX0_l...................................................................................................... 2091
7-566. Register Call Summary for Register CAL_CSI2_CTX0_l .......................................................... 2092
7-567. CAL_CSI2_CTX1_l...................................................................................................... 2092
7-568. Register Call Summary for Register CAL_CSI2_CTX1_l .......................................................... 2093
7-569. CAL_CSI2_CTX2_l...................................................................................................... 2093
7-570. Register Call Summary for Register CAL_CSI2_CTX2_l .......................................................... 2094
7-571. CAL_CSI2_CTX3_l...................................................................................................... 2094
7-572. Register Call Summary for Register CAL_CSI2_CTX3_l .......................................................... 2094
7-573. CAL_CSI2_CTX4_l...................................................................................................... 2095
7-574. Register Call Summary for Register CAL_CSI2_CTX4_l .......................................................... 2095
7-575. CAL_CSI2_CTX5_l...................................................................................................... 2096
7-576. Register Call Summary for Register CAL_CSI2_CTX5_l .......................................................... 2096
7-577. CAL_CSI2_CTX6_l...................................................................................................... 2097
7-578. Register Call Summary for Register CAL_CSI2_CTX6_l .......................................................... 2097
7-579. CAL_CSI2_CTX7_l...................................................................................................... 2098
7-580. Register Call Summary for Register CAL_CSI2_CTX7_l .......................................................... 2098
7-581. CAL_CSI2_STATUS0_l ................................................................................................ 2099
7-582. Register Call Summary for Register CAL_CSI2_STATUS0_l ..................................................... 2099
7-583. CAL_CSI2_STATUS1_l ................................................................................................ 2099
7-584. Register Call Summary for Register CAL_CSI2_STATUS1_l ..................................................... 2099
7-585. CAL_CSI2_STATUS2_l ................................................................................................ 2100
7-586. Register Call Summary for Register CAL_CSI2_STATUS2_l ..................................................... 2100
7-587. CAL_CSI2_STATUS3_l ................................................................................................ 2100
7-588. Register Call Summary for Register CAL_CSI2_STATUS3_l ..................................................... 2100
7-589. CAL_CSI2_STATUS4_l ................................................................................................ 2101
7-590. Register Call Summary for Register CAL_CSI2_STATUS4_l ..................................................... 2101
7-591. CAL_CSI2_STATUS5_l ................................................................................................ 2101
7-592. Register Call Summary for Register CAL_CSI2_STATUS5_l ..................................................... 2101
7-593. CAL_CSI2_STATUS6_l ................................................................................................ 2102
7-594. Register Call Summary for Register CAL_CSI2_STATUS6_l ..................................................... 2102
7-595. CAL_CSI2_STATUS7_l ................................................................................................ 2102
7-596. Register Call Summary for Register CAL_CSI2_STATUS7_l ..................................................... 2102
7-597. ISS TCTRL Control-Signal Generator: CNTCLK Frequencies .................................................... 2105
7-598. ISS TCTRL Enabling the Control-Signal Generation in First Configuration ..................................... 2107
7-599. ISS TCTRL Enabling the Control-Signal Generation in Second Configuration ................................. 2108
7-600. ISS TCTRL Instance Summary........................................................................................ 2110
7-601. ISS TCTRL Registers Mapping Summary ........................................................................... 2110
7-602. TCTRL_REVISION ...................................................................................................... 2111
7-603. Register Call Summary for Register TCTRL_REVISION .......................................................... 2111
7-604. TCTRL_SYSCONFIG ................................................................................................... 2111
7-605. Register Call Summary for Register TCTRL_SYSCONFIG ....................................................... 2112
7-606. TCTRL_SYSSTATUS................................................................................................... 2112
7-607. Register Call Summary for Register TCTRL_SYSSTATUS ....................................................... 2112
7-608. TCTRL_STRB_LENGTH ............................................................................................... 2113
7-609. Register Call Summary for Register TCTRL_STRB_LENGTH
...................................................
2113
7-610. TCTRL_PSTRB_LENGTH ............................................................................................. 2113
7-611. Register Call Summary for Register TCTRL_PSTRB_LENGTH .................................................. 2113
134
List of Tables
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7-612. TCTRL_SHUT_LENGTH ............................................................................................... 2114
7-613. Register Call Summary for Register TCTRL_SHUT_LENGTH
...................................................
2114
7-614. TCTRL_GRESET_LENGTH ........................................................................................... 2114
7-615. Register Call Summary for Register TCTRL_GRESET_LENGTH................................................ 2114
7-616. TCTRL_STRB_DELAY ................................................................................................. 2115
7-617. Register Call Summary for Register TCTRL_STRB_DELAY...................................................... 2115
7-618. TCTRL_PSTRB_DELAY ............................................................................................... 2115
7-619. Register Call Summary for Register TCTRL_PSTRB_DELAY .................................................... 2115
7-620. TCTRL_SHUT_DELAY ................................................................................................. 2116
7-621. Register Call Summary for Register TCTRL_SHUT_DELAY
.....................................................
2116
7-622. TCTRL_CTRL............................................................................................................ 2116
7-623. Register Call Summary for Register TCTRL_CTRL ................................................................ 2118
7-624. TCTRL_PSTRB_REPLAY
.............................................................................................
2118
7-625. Register Call Summary for Register TCTRL_PSTRB_REPLAY .................................................. 2118
7-626. TCTRL_FRAME ......................................................................................................... 2119
7-627. Register Call Summary for Register TCTRL_FRAME .............................................................. 2119
..........................................................................................
..........................................................................................
ISS ISP VP GCK_MMR to PCLK Clock Resynchronization .......................................................
ISS ISP GLBCE Core Key Parameters ..............................................................................
ISS ISP GLBCE Memories .............................................................................................
7-628. ISS ISP Interrupt Tree Table
2125
7-629. ISS ISP VP Format Mapping
2131
7-630.
2133
7-631.
7-632.
2135
2140
7-633. ISS ISP IPIPEIF IPIPEIF_CFG1[15:14] INPSRC1 and IPIPEIF_CFG1[3:2] INPSRC2 Possible
Combinations ............................................................................................................ 2150
7-634. ISS ISP IPIPEIF DPCM Block Possible Configuration ............................................................. 2161
7-635. ISS ISP IPIPEIF DFS Modes Supported ............................................................................. 2163
7-636. ISS ISP IPIPEIF Averaging Filter Conditions for YUV4:2:2 Data ................................................. 2164
7-637. ISS ISP IPIPE Input and Output Selections ......................................................................... 2172
7-638. ISS ISP IPIPE Defect Information Packing .......................................................................... 2173
7-639. ISS ISP IPIPE Correction Method Description ...................................................................... 2173
7-640. ISS ISP IPIPE DPC_CLK .............................................................................................. 2175
7-641. ISS ISP IPIPE Edge-Enhancer LUT Mapping ....................................................................... 2182
7-642. ISS ISP IPIPE Histogram memory mapping ......................................................................... 2185
7-643. ISS ISP RSZ VP Supported Formats ................................................................................. 2191
7-644. ISS ISP RSZ CNF Data Interfaces (CNF output to RSZ) .......................................................... 2193
7-645. ISS ISP RSZ ICM Handshake Interfaces ............................................................................ 2194
7-646. ISS ISP RSZ Data Flow vs. Input Data Format Constraints ....................................................... 2197
7-647. ISS ISP RSZ Module Modes: Register Settings .................................................................... 2197
7-648. ISS ISP RSZ Module Input Control: Register Settings ............................................................. 2198
7-649. ISS ISP RSZ-A/RSZ-B Output Format Selection
...................................................................
2198
7-650. ISS ISP RSZ Output Interface: Data Formats ....................................................................... 2208
7-651. ISS ISP RSZ Circular Buffer ........................................................................................... 2209
7-652. ISS ISP CNF CNF image width/height configuration examples................................................... 2216
....................................................................
ISS ISP H3A AE/AWB Window Register Field Descriptions ......................................................
ISS ISP H3A AE/AWB Window With Additional Black Row Register Field Descriptions ......................
ISS ISP H3A AF Packet Format With Vertical AF Disabled .......................................................
ISS ISP H3A AF Packet Format With Vertical AF Enabled........................................................
ISS ISP H3A AE/AWB Packet Format for Sum of Square Mode .................................................
ISS ISP H3A AE/AWB Packet Format for Minimum-Maximum Mode ............................................
7-653. ISS ISP H3A Paxel Register Field Descriptions
2222
7-654.
2226
7-655.
7-656.
7-657.
7-658.
7-659.
SPRUIC6B – January 2017 – Revised October 2017
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List of Tables
2226
2227
2228
2229
2231
135
www.ti.com
7-660. ISS ISP H3A AE/AWB Packet Format for Sum-Only Mode ....................................................... 2233
7-661. ISS ISP ISIF Input Interface Signals .................................................................................. 2238
2238
7-663. ISS ISP ISIF Raw Data Connection: Selects MSB Position of Input Data
2239
7-664.
2240
7-665.
7-666.
7-667.
7-668.
7-669.
7-670.
7-671.
7-672.
7-673.
7-674.
7-675.
7-676.
7-677.
7-678.
7-679.
7-680.
7-681.
7-682.
7-683.
7-684.
7-685.
7-686.
7-687.
7-688.
7-689.
7-690.
7-691.
7-692.
7-693.
7-694.
7-695.
7-696.
7-697.
7-698.
7-699.
7-700.
7-701.
7-702.
7-703.
7-704.
7-705.
7-706.
7-707.
7-708.
136
.....................................................................................
......................................
ISS ISP ISIF Linearization LUT .......................................................................................
ISS ISP ISIF LUT Memory Region ....................................................................................
ISS ISP ISIF Input Data Formatter Area Setting Registers ........................................................
ISS ISP ISIF Output Data Formatter Area Setting Registers ......................................................
ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line: Register Setting Example......
ISS ISP ISIF Vertical Line Defect Table in Memory ................................................................
ISS ISP ISIF Supported On-the-Fly LSC Configurations ..........................................................
ISS ISP ISIF RAW Data Shifting ......................................................................................
ISS ISP ISIF SDRAM Data Format ...................................................................................
ISS ISP ISIF SDRAM Data Format for 12-bit Packed ..............................................................
ISS ISP ISIF Memory Output Format for YUV Data ................................................................
ISP ISIF ISIF Module: Write Port Bandwidth ........................................................................
ISS ISP ISIF Read Port Bandwidth ...................................................................................
ISS ISP BL cpriority to MFlag With ISP5_CTRL[21] MFLAG = 1 .................................................
ISS ISP BL MFlag Write Low- and High-Level Priority Thresholds ...............................................
ISS ISP BL MFlag Read Low- and High-Level Priority Thresholds...............................................
ISS ISP Memory Mapping..............................................................................................
ISS ISP Instance Summary ............................................................................................
ISS ISP6P5_SYS1 Registers Mapping Summary ..................................................................
ISP5_REVISION.........................................................................................................
Register Call Summary for Register ISP5_REVISION .............................................................
ISP5_HWINFO1 .........................................................................................................
Register Call Summary for Register ISP5_HWINFO1..............................................................
ISP5_HWINFO2 .........................................................................................................
Register Call Summary for Register ISP5_HWINFO2..............................................................
ISP5_SYSCONFIG......................................................................................................
Register Call Summary for Register ISP5_SYSCONFIG ..........................................................
ISP5_IRQ_EOI ..........................................................................................................
Register Call Summary for Register ISP5_IRQ_EOI ...............................................................
ISP5_IRQSTATUS_RAW ..............................................................................................
Register Call Summary for Register ISP5_IRQSTATUS_RAW ...................................................
ISP5_IRQSTATUS ......................................................................................................
Register Call Summary for Register ISP5_IRQSTATUS...........................................................
ISP5_IRQENABLE_SET ...............................................................................................
Register Call Summary for Register ISP5_IRQENABLE_SET ....................................................
ISP5_IRQENABLE_CLR ...............................................................................................
Register Call Summary for Register ISP5_IRQENABLE_CLR ....................................................
ISP5_IRQSTATUS_RAW_1 ...........................................................................................
Register Call Summary for Register ISP5_IRQSTATUS_RAW_1 ................................................
ISP5_IRQSTATUS_1 ...................................................................................................
Register Call Summary for Register ISP5_IRQSTATUS_1........................................................
ISP5_IRQENABLE_SET_1 ............................................................................................
Register Call Summary for Register ISP5_IRQENABLE_SET_1 .................................................
ISP5_IRQENABLE_CLR_1 ............................................................................................
Register Call Summary for Register ISP5_IRQENABLE_CLR_1 .................................................
7-662. ISS ISP ISIF Data Input Formats
List of Tables
2240
2243
2243
2247
2258
2264
2271
2271
2271
2274
2275
2276
2282
2282
2283
2283
2285
2285
2286
2287
2287
2287
2287
2287
2288
2289
2289
2289
2289
2292
2293
2295
2296
2298
2299
2301
2301
2304
2305
2307
2307
2310
2310
2313
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-709. ISP5_IRQSTATUS_RAW_2 ........................................................................................... 2313
7-710. Register Call Summary for Register ISP5_IRQSTATUS_RAW_2 ................................................ 2316
7-711. ISP5_IRQSTATUS_2 ................................................................................................... 2317
7-712. Register Call Summary for Register ISP5_IRQSTATUS_2........................................................ 2319
7-713. ISP5_IRQENABLE_SET_2 ............................................................................................ 2319
7-714. Register Call Summary for Register ISP5_IRQENABLE_SET_2 ................................................. 2322
7-715. ISP5_IRQENABLE_CLR_2 ............................................................................................ 2322
7-716. Register Call Summary for Register ISP5_IRQENABLE_CLR_2 ................................................. 2325
7-717. ISP5_IRQSTATUS_RAW_3 ........................................................................................... 2325
7-718. Register Call Summary for Register ISP5_IRQSTATUS_RAW_3 ................................................ 2328
7-719. ISP5_IRQSTATUS_3 ................................................................................................... 2329
7-720. Register Call Summary for Register ISP5_IRQSTATUS_3........................................................ 2331
7-721. ISP5_IRQENABLE_SET_3 ............................................................................................ 2331
7-722. Register Call Summary for Register ISP5_IRQENABLE_SET_3 ................................................. 2334
7-723. ISP5_IRQENABLE_CLR_3 ............................................................................................ 2334
7-724. Register Call Summary for Register ISP5_IRQENABLE_CLR_3 ................................................. 2337
7-725. ISP5_DMAENABLE_SET .............................................................................................. 2337
7-726. Register Call Summary for Register ISP5_DMAENABLE_SET................................................... 2338
7-727. ISP5_DMAENABLE_CLR .............................................................................................. 2338
..................................................
..............................................................................................................
Register Call Summary for Register ISP5_CTRL ...................................................................
ISP5_PG..................................................................................................................
Register Call Summary for Register ISP5_PG ......................................................................
ISP5_PG_PULSE_CTRL ...............................................................................................
Register Call Summary for Register ISP5_PG_PULSE_CTRL ...................................................
ISP5_PG_FRAME_SIZE ...............................................................................................
Register Call Summary for Register ISP5_PG_FRAME_SIZE ....................................................
ISP5_MPSR ..............................................................................................................
Register Call Summary for Register ISP5_MPSR ..................................................................
ISP5_BL_MTC_1 ........................................................................................................
Register Call Summary for Register ISP5_BL_MTC_1 ............................................................
ISP5_BL_MTC_2 ........................................................................................................
Register Call Summary for Register ISP5_BL_MTC_2 ............................................................
ISP5_BL_VBUSM .......................................................................................................
Register Call Summary for Register ISP5_BL_VBUSM............................................................
ISS ISP6P5_SYS2 Registers Mapping Summary ..................................................................
ISP5_KEY_EN1 .........................................................................................................
Register Call Summary for Register ISP5_KEY_EN1 ..............................................................
ISP5_KEY_EN2 .........................................................................................................
Register Call Summary for Register ISP5_KEY_EN2 ..............................................................
ISP5_KEY_EN3 .........................................................................................................
Register Call Summary for Register ISP5_KEY_EN3 ..............................................................
ISP5_KEY_EN4 .........................................................................................................
Register Call Summary for Register ISP5_KEY_EN4 ..............................................................
ISP5_KEY_EN5 .........................................................................................................
Register Call Summary for Register ISP5_KEY_EN5 ..............................................................
ISP5_KEY_EN6 .........................................................................................................
Register Call Summary for Register ISP5_KEY_EN6 ..............................................................
7-728. Register Call Summary for Register ISP5_DMAENABLE_CLR
2339
7-729. ISP5_CTRL
2339
7-730.
2343
7-731.
7-732.
7-733.
7-734.
7-735.
7-736.
7-737.
7-738.
7-739.
7-740.
7-741.
7-742.
7-743.
7-744.
7-745.
7-746.
7-747.
7-748.
7-749.
7-750.
7-751.
7-752.
7-753.
7-754.
7-755.
7-756.
7-757.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2343
2344
2344
2344
2344
2345
2345
2348
2348
2348
2348
2349
2349
2349
2349
2350
2350
2350
2351
2351
2351
2351
2352
2352
2352
2352
2353
137
www.ti.com
7-758. ISS ISP6P5_RESIZER Registers Mapping Summary.............................................................. 2353
7-759. RSZ_REVISION ......................................................................................................... 2355
7-760. Register Call Summary for Register RSZ_REVISION.............................................................. 2355
7-761. RSZ_SYSCONFIG ...................................................................................................... 2356
7-762. Register Call Summary for Register RSZ_SYSCONFIG........................................................... 2356
7-763. RSZ_SYSSTATUS ...................................................................................................... 2356
7-764. Register Call Summary for Register RSZ_SYSSTATUS
..........................................................
2357
7-765. RSZ_IN_FIFO_CTRL ................................................................................................... 2357
7-766. Register Call Summary for Register RSZ_IN_FIFO_CTRL........................................................ 2357
7-767. RSZ_GNC ................................................................................................................ 2357
....................................................................
RSZ_FRACDIV ..........................................................................................................
Register Call Summary for Register RSZ_FRACDIV...............................................................
RSZ_SRC_EN ...........................................................................................................
Register Call Summary for Register RSZ_SRC_EN ...............................................................
RSZ_SRC_MODE.......................................................................................................
Register Call Summary for Register RSZ_SRC_MODE ...........................................................
RSZ_SRC_FMT0 ........................................................................................................
Register Call Summary for Register RSZ_SRC_FMT0 ............................................................
RSZ_SRC_FMT1 ........................................................................................................
Register Call Summary for Register RSZ_SRC_FMT1 ............................................................
RSZ_SRC_VPS .........................................................................................................
Register Call Summary for Register RSZ_SRC_VPS ..............................................................
RSZ_SRC_VSZ .........................................................................................................
Register Call Summary for Register RSZ_SRC_VSZ ..............................................................
RSZ_SRC_HPS .........................................................................................................
Register Call Summary for Register RSZ_SRC_HPS ..............................................................
RSZ_SRC_HSZ .........................................................................................................
Register Call Summary for Register RSZ_SRC_HSZ ..............................................................
RSZ_DMA_RZA .........................................................................................................
Register Call Summary for Register RSZ_DMA_RZA..............................................................
RSZ_DMA_RZB .........................................................................................................
Register Call Summary for Register RSZ_DMA_RZB..............................................................
RSZ_DMA_STA .........................................................................................................
Register Call Summary for Register RSZ_DMA_STA ..............................................................
RSZ_GCK_MMR ........................................................................................................
Register Call Summary for Register RSZ_GCK_MMR .............................................................
RSZ_GCK_SDR .........................................................................................................
Register Call Summary for Register RSZ_GCK_SDR .............................................................
RSZ_IRQ_RZA ..........................................................................................................
Register Call Summary for Register RSZ_IRQ_RZA ...............................................................
RSZ_IRQ_RZB ..........................................................................................................
Register Call Summary for Register RSZ_IRQ_RZB ...............................................................
RSZ_YUV_Y_MIN.......................................................................................................
Register Call Summary for Register RSZ_YUV_Y_MIN ...........................................................
RSZ_YUV_Y_MAX ......................................................................................................
Register Call Summary for Register RSZ_YUV_Y_MAX ..........................................................
RSZ_YUV_C_MIN ......................................................................................................
Register Call Summary for Register RSZ_YUV_C_MIN ...........................................................
7-768. Register Call Summary for Register RSZ_GNC
7-769.
7-770.
7-771.
7-772.
7-773.
7-774.
7-775.
7-776.
7-777.
7-778.
7-779.
7-780.
7-781.
7-782.
7-783.
7-784.
7-785.
7-786.
7-787.
7-788.
7-789.
7-790.
7-791.
7-792.
7-793.
7-794.
7-795.
7-796.
7-797.
7-798.
7-799.
7-800.
7-801.
7-802.
7-803.
7-804.
7-805.
7-806.
138
List of Tables
2358
2358
2358
2358
2359
2359
2359
2360
2360
2360
2361
2361
2361
2362
2362
2362
2362
2363
2363
2363
2363
2363
2364
2364
2364
2364
2365
2365
2365
2366
2367
2367
2368
2368
2369
2369
2369
2369
2370
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-807. RSZ_YUV_C_MAX...................................................................................................... 2370
7-808. Register Call Summary for Register RSZ_YUV_C_MAX .......................................................... 2370
7-809. RSZ_YUV_PHS ......................................................................................................... 2370
7-810. Register Call Summary for Register RSZ_YUV_PHS .............................................................. 2371
7-811. RSZ_SEQ ................................................................................................................ 2371
7-812. Register Call Summary for Register RSZ_SEQ ..................................................................... 2372
7-813. RZA_EN .................................................................................................................. 2372
7-814. Register Call Summary for Register RZA_EN ....................................................................... 2372
7-815. RZA_MODE .............................................................................................................. 2372
7-816. Register Call Summary for Register RZA_MODE .................................................................. 2372
.................................................................................................................
Register Call Summary for Register RZA_420 ......................................................................
RZA_I_VPS ..............................................................................................................
Register Call Summary for Register RZA_I_VPS ...................................................................
RZA_I_HPS ..............................................................................................................
Register Call Summary for Register RZA_I_HPS ...................................................................
RZA_O_VSZ .............................................................................................................
Register Call Summary for Register RZA_O_VSZ..................................................................
RZA_O_HSZ .............................................................................................................
Register Call Summary for Register RZA_O_HSZ .................................................................
RZA_V_PHS_Y ..........................................................................................................
Register Call Summary for Register RZA_V_PHS_Y ..............................................................
RZA_V_PHS_C..........................................................................................................
Register Call Summary for Register RZA_V_PHS_C ..............................................................
RZA_V_DIF ..............................................................................................................
Register Call Summary for Register RZA_V_DIF ...................................................................
RZA_V_TYP .............................................................................................................
Register Call Summary for Register RZA_V_TYP ..................................................................
RZA_V_LPF ..............................................................................................................
Register Call Summary for Register RZA_V_LPF ..................................................................
RZA_H_PHS .............................................................................................................
Register Call Summary for Register RZA_H_PHS .................................................................
RZA_H_PHS_ADJ ......................................................................................................
Register Call Summary for Register RZA_H_PHS_ADJ ...........................................................
RZA_H_DIF ..............................................................................................................
Register Call Summary for Register RZA_H_DIF ...................................................................
RZA_H_TYP .............................................................................................................
Register Call Summary for Register RZA_H_TYP ..................................................................
RZA_H_LPF .............................................................................................................
Register Call Summary for Register RZA_H_LPF ..................................................................
RZA_DWN_EN ..........................................................................................................
Register Call Summary for Register RZA_DWN_EN ...............................................................
RZA_DWN_AV ..........................................................................................................
Register Call Summary for Register RZA_DWN_AV ...............................................................
RZA_RGB_EN ...........................................................................................................
Register Call Summary for Register RZA_RGB_EN ...............................................................
RZA_RGB_TYP .........................................................................................................
Register Call Summary for Register RZA_RGB_TYP ..............................................................
RZA_RGB_BLD .........................................................................................................
7-817. RZA_420
2373
7-818.
2373
7-819.
7-820.
7-821.
7-822.
7-823.
7-824.
7-825.
7-826.
7-827.
7-828.
7-829.
7-830.
7-831.
7-832.
7-833.
7-834.
7-835.
7-836.
7-837.
7-838.
7-839.
7-840.
7-841.
7-842.
7-843.
7-844.
7-845.
7-846.
7-847.
7-848.
7-849.
7-850.
7-851.
7-852.
7-853.
7-854.
7-855.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2373
2374
2374
2374
2374
2374
2375
2375
2375
2375
2376
2376
2376
2376
2376
2377
2377
2377
2377
2378
2378
2378
2378
2379
2379
2379
2379
2380
2380
2380
2380
2381
2381
2381
2381
2382
2382
139
www.ti.com
7-856. Register Call Summary for Register RZA_RGB_BLD .............................................................. 2382
7-857. RZA_SDR_Y_BAD_H
..................................................................................................
2382
7-858. Register Call Summary for Register RZA_SDR_Y_BAD_H ....................................................... 2383
7-859. RZA_SDR_Y_BAD_L ................................................................................................... 2383
2383
7-861. RZA_SDR_Y_SAD_H
2383
7-862.
7-863.
7-864.
7-865.
7-866.
7-867.
7-868.
7-869.
7-870.
7-871.
7-872.
7-873.
7-874.
7-875.
7-876.
7-877.
7-878.
7-879.
7-880.
7-881.
7-882.
7-883.
7-884.
7-885.
7-886.
7-887.
7-888.
7-889.
7-890.
7-891.
7-892.
7-893.
7-894.
7-895.
7-896.
7-897.
7-898.
7-899.
7-900.
7-901.
7-902.
7-903.
7-904.
140
.......................................................
..................................................................................................
Register Call Summary for Register RZA_SDR_Y_SAD_H .......................................................
RZA_SDR_Y_SAD_L ...................................................................................................
Register Call Summary for Register RZA_SDR_Y_SAD_L .......................................................
RZA_SDR_Y_OFT ......................................................................................................
Register Call Summary for Register RZA_SDR_Y_OFT...........................................................
RZA_SDR_Y_PTR_S ...................................................................................................
Register Call Summary for Register RZA_SDR_Y_PTR_S .......................................................
RZA_SDR_Y_PTR_E ...................................................................................................
Register Call Summary for Register RZA_SDR_Y_PTR_E .......................................................
RZA_SDR_C_BAD_H ..................................................................................................
Register Call Summary for Register RZA_SDR_C_BAD_H .......................................................
RZA_SDR_C_BAD_L ...................................................................................................
Register Call Summary for Register RZA_SDR_C_BAD_L .......................................................
RZA_SDR_C_SAD_H ..................................................................................................
Register Call Summary for Register RZA_SDR_C_SAD_H .......................................................
RZA_SDR_C_SAD_L ...................................................................................................
Register Call Summary for Register RZA_SDR_C_SAD_L .......................................................
RZA_SDR_C_OFT ......................................................................................................
Register Call Summary for Register RZA_SDR_C_OFT ..........................................................
RZA_SDR_C_PTR_S...................................................................................................
Register Call Summary for Register RZA_SDR_C_PTR_S .......................................................
RZA_SDR_C_PTR_E...................................................................................................
Register Call Summary for Register RZA_SDR_C_PTR_E .......................................................
RZB_EN ..................................................................................................................
Register Call Summary for Register RZB_EN .......................................................................
RZB_MODE ..............................................................................................................
Register Call Summary for Register RZB_MODE ..................................................................
RZB_420 .................................................................................................................
Register Call Summary for Register RZB_420 ......................................................................
RZB_I_VPS ..............................................................................................................
Register Call Summary for Register RZB_I_VPS ...................................................................
RZB_I_HPS ..............................................................................................................
Register Call Summary for Register RZB_I_HPS ...................................................................
RZB_O_VSZ .............................................................................................................
Register Call Summary for Register RZB_O_VSZ..................................................................
RZB_O_HSZ .............................................................................................................
Register Call Summary for Register RZB_O_HSZ .................................................................
RZB_V_PHS_Y ..........................................................................................................
Register Call Summary for Register RZB_V_PHS_Y ..............................................................
RZB_V_PHS_C..........................................................................................................
Register Call Summary for Register RZB_V_PHS_C ..............................................................
RZB_V_DIF ..............................................................................................................
Register Call Summary for Register RZB_V_DIF ...................................................................
7-860. Register Call Summary for Register RZA_SDR_Y_BAD_L
List of Tables
2384
2384
2384
2385
2385
2385
2385
2386
2386
2386
2386
2386
2387
2387
2387
2387
2388
2388
2388
2388
2389
2389
2389
2389
2390
2390
2390
2390
2391
2391
2391
2391
2392
2392
2392
2392
2393
2393
2393
2393
2394
2394
2394
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-905. RZB_V_TYP ............................................................................................................. 2394
7-906. Register Call Summary for Register RZB_V_TYP .................................................................. 2395
7-907. RZB_V_LPF .............................................................................................................. 2395
7-908. Register Call Summary for Register RZB_V_LPF .................................................................. 2395
7-909. RZB_H_PHS ............................................................................................................. 2395
.................................................................
RZB_H_PHS_ADJ ......................................................................................................
Register Call Summary for Register RZB_H_PHS_ADJ ...........................................................
RZB_H_DIF ..............................................................................................................
Register Call Summary for Register RZB_H_DIF ...................................................................
RZB_H_TYP .............................................................................................................
Register Call Summary for Register RZB_H_TYP ..................................................................
RZB_H_LPF .............................................................................................................
Register Call Summary for Register RZB_H_LPF ..................................................................
RZB_DWN_EN ..........................................................................................................
Register Call Summary for Register RZB_DWN_EN ...............................................................
RZB_DWN_AV ..........................................................................................................
Register Call Summary for Register RZB_DWN_AV ...............................................................
RZB_RGB_EN ...........................................................................................................
Register Call Summary for Register RZB_RGB_EN ...............................................................
RZB_RGB_TYP .........................................................................................................
Register Call Summary for Register RZB_RGB_TYP ..............................................................
RZB_RGB_BLD .........................................................................................................
Register Call Summary for Register RZB_RGB_BLD ..............................................................
RZB_SDR_Y_BAD_H ..................................................................................................
Register Call Summary for Register RZB_SDR_Y_BAD_H .......................................................
RZB_SDR_Y_BAD_L ...................................................................................................
Register Call Summary for Register RZB_SDR_Y_BAD_L .......................................................
RZB_SDR_Y_SAD_H ..................................................................................................
Register Call Summary for Register RZB_SDR_Y_SAD_H .......................................................
RZB_SDR_Y_SAD_L ...................................................................................................
Register Call Summary for Register RZB_SDR_Y_SAD_L .......................................................
RZB_SDR_Y_OFT ......................................................................................................
Register Call Summary for Register RZB_SDR_Y_OFT...........................................................
RZB_SDR_Y_PTR_S ...................................................................................................
Register Call Summary for Register RZB_SDR_Y_PTR_S .......................................................
RZB_SDR_Y_PTR_E ...................................................................................................
Register Call Summary for Register RZB_SDR_Y_PTR_E .......................................................
RZB_SDR_C_BAD_H ..................................................................................................
Register Call Summary for Register RZB_SDR_C_BAD_H .......................................................
RZB_SDR_C_BAD_L ...................................................................................................
Register Call Summary for Register RZB_SDR_C_BAD_L .......................................................
RZB_SDR_C_SAD_H ..................................................................................................
Register Call Summary for Register RZB_SDR_C_SAD_H .......................................................
RZB_SDR_C_SAD_L ...................................................................................................
Register Call Summary for Register RZB_SDR_C_SAD_L .......................................................
RZB_SDR_C_OFT ......................................................................................................
Register Call Summary for Register RZB_SDR_C_OFT ..........................................................
RZB_SDR_C_PTR_S...................................................................................................
7-910. Register Call Summary for Register RZB_H_PHS
2396
7-911.
2396
7-912.
7-913.
7-914.
7-915.
7-916.
7-917.
7-918.
7-919.
7-920.
7-921.
7-922.
7-923.
7-924.
7-925.
7-926.
7-927.
7-928.
7-929.
7-930.
7-931.
7-932.
7-933.
7-934.
7-935.
7-936.
7-937.
7-938.
7-939.
7-940.
7-941.
7-942.
7-943.
7-944.
7-945.
7-946.
7-947.
7-948.
7-949.
7-950.
7-951.
7-952.
7-953.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2396
2396
2396
2397
2397
2397
2397
2397
2398
2398
2398
2398
2399
2399
2399
2400
2400
2400
2400
2400
2401
2401
2401
2402
2402
2402
2403
2403
2403
2403
2404
2404
2404
2404
2405
2405
2405
2405
2406
2406
2406
2406
141
www.ti.com
7-954. Register Call Summary for Register RZB_SDR_C_PTR_S ....................................................... 2407
7-955. RZB_SDR_C_PTR_E................................................................................................... 2407
7-956. Register Call Summary for Register RZB_SDR_C_PTR_E ....................................................... 2407
..................................................................
7-958. IPIPE_SRC_EN .........................................................................................................
7-959. Register Call Summary for Register IPIPE_SRC_EN ..............................................................
7-960. IPIPE_SRC_MODE .....................................................................................................
7-961. Register Call Summary for Register IPIPE_SRC_MODE ..........................................................
7-962. IPIPE_SRC_FMT ........................................................................................................
7-963. Register Call Summary for Register IPIPE_SRC_FMT ............................................................
7-964. IPIPE_SRC_COL ........................................................................................................
7-965. Register Call Summary for Register IPIPE_SRC_COL ............................................................
7-966. IPIPE_SRC_VPS ........................................................................................................
7-967. Register Call Summary for Register IPIPE_SRC_VPS ............................................................
7-968. IPIPE_SRC_VSZ ........................................................................................................
7-969. Register Call Summary for Register IPIPE_SRC_VSZ ............................................................
7-970. IPIPE_SRC_HPS ........................................................................................................
7-971. Register Call Summary for Register IPIPE_SRC_HPS ............................................................
7-972. IPIPE_SRC_HSZ ........................................................................................................
7-973. Register Call Summary for Register IPIPE_SRC_HSZ ............................................................
7-974. IPIPE_SEL_SBU ........................................................................................................
7-975. Register Call Summary for Register IPIPE_SEL_SBU .............................................................
7-976. IPIPE_SRC_STA ........................................................................................................
7-977. Register Call Summary for Register IPIPE_SRC_STA ............................................................
7-978. IPIPE_GCK_MMR.......................................................................................................
7-979. Register Call Summary for Register IPIPE_GCK_MMR ...........................................................
7-980. IPIPE_GCK_PIX .........................................................................................................
7-981. Register Call Summary for Register IPIPE_GCK_PIX .............................................................
7-982. IPIPE_DPC_LUT_EN ...................................................................................................
7-983. Register Call Summary for Register IPIPE_DPC_LUT_EN .......................................................
7-984. IPIPE_DPC_LUT_SEL .................................................................................................
7-985. Register Call Summary for Register IPIPE_DPC_LUT_SEL ......................................................
7-986. IPIPE_DPC_LUT_ADR .................................................................................................
7-987. Register Call Summary for Register IPIPE_DPC_LUT_ADR .....................................................
7-988. IPIPE_DPC_LUT_SIZ ..................................................................................................
7-989. Register Call Summary for Register IPIPE_DPC_LUT_SIZ .......................................................
7-990. IPIPE_DPC_OTF_EN...................................................................................................
7-991. Register Call Summary for Register IPIPE_DPC_OTF_EN .......................................................
7-992. IPIPE_DPC_OTF_TYP .................................................................................................
7-993. Register Call Summary for Register IPIPE_DPC_OTF_TYP......................................................
7-994. IPIPE_DPC_OTF_2_D_THR_R .......................................................................................
7-995. Register Call Summary for Register IPIPE_DPC_OTF_2_D_THR_R ...........................................
7-996. IPIPE_DPC_OTF_2_D_THR_GR .....................................................................................
7-997. Register Call Summary for Register IPIPE_DPC_OTF_2_D_THR_GR .........................................
7-998. IPIPE_DPC_OTF_2_D_THR_GB .....................................................................................
7-999. Register Call Summary for Register IPIPE_DPC_OTF_2_D_THR_GB .........................................
7-1000. IPIPE_DPC_OTF_2_D_THR_B ......................................................................................
7-1001. Register Call Summary for Register IPIPE_DPC_OTF_2_D_THR_B ..........................................
7-1002. IPIPE_DPC_OTF_2_C_THR_R .....................................................................................
7-957. ISS ISP6P5_IPIPE Registers Mapping Summary
142
List of Tables
2407
2415
2416
2416
2416
2416
2417
2417
2418
2418
2419
2419
2419
2419
2420
2420
2420
2420
2420
2421
2421
2421
2421
2422
2422
2422
2423
2423
2423
2423
2424
2424
2424
2424
2425
2425
2425
2425
2425
2426
2426
2426
2426
2426
2427
2427
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1003. Register Call Summary for Register IPIPE_DPC_OTF_2_C_THR_R .......................................... 2427
7-1004. IPIPE_DPC_OTF_2_C_THR_GR
...................................................................................
2427
7-1005. Register Call Summary for Register IPIPE_DPC_OTF_2_C_THR_GR ........................................ 2427
7-1006. IPIPE_DPC_OTF_2_C_THR_GB.................................................................................... 2428
7-1007. Register Call Summary for Register IPIPE_DPC_OTF_2_C_THR_GB ........................................ 2428
7-1008. IPIPE_DPC_OTF_2_C_THR_B ...................................................................................... 2428
7-1009. Register Call Summary for Register IPIPE_DPC_OTF_2_C_THR_B .......................................... 2428
7-1010. IPIPE_DPC_OTF_3_SHF............................................................................................. 2428
7-1011. Register Call Summary for Register IPIPE_DPC_OTF_3_SHF ................................................. 2429
7-1012. IPIPE_DPC_OTF_3_D_THR ......................................................................................... 2429
.............................................
IPIPE_DPC_OTF_3_D_SPL .........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_D_SPL ..............................................
IPIPE_DPC_OTF_3_D_MIN..........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_D_MIN ..............................................
IPIPE_DPC_OTF_3_D_MAX .........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_D_MAX .............................................
IPIPE_DPC_OTF_3_C_THR .........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_C_THR .............................................
IPIPE_DPC_OTF_3_C_SLP .........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_C_SLP ..............................................
IPIPE_DPC_OTF_3_C_MIN..........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_C_MIN ..............................................
IPIPE_DPC_OTF_3_C_MAX .........................................................................................
Register Call Summary for Register IPIPE_DPC_OTF_3_C_MAX .............................................
IPIPE_LSC_VOFT .....................................................................................................
Register Call Summary for Register IPIPE_LSC_VOFT..........................................................
IPIPE_LSC_VA2 .......................................................................................................
Register Call Summary for Register IPIPE_LSC_VA2 ............................................................
IPIPE_LSC_VA1 .......................................................................................................
Register Call Summary for Register IPIPE_LSC_VA1 ............................................................
IPIPE_LSC_VS .........................................................................................................
Register Call Summary for Register IPIPE_LSC_VS .............................................................
IPIPE_LSC_HOFT .....................................................................................................
Register Call Summary for Register IPIPE_LSC_HOFT .........................................................
IPIPE_LSC_HA2 .......................................................................................................
Register Call Summary for Register IPIPE_LSC_HA2............................................................
IPIPE_LSC_HA1 .......................................................................................................
Register Call Summary for Register IPIPE_LSC_HA1............................................................
IPIPE_LSC_HS ........................................................................................................
Register Call Summary for Register IPIPE_LSC_HS .............................................................
IPIPE_LSC_GAN_R ...................................................................................................
Register Call Summary for Register IPIPE_LSC_GAN_R .......................................................
IPIPE_LSC_GAN_GR .................................................................................................
Register Call Summary for Register IPIPE_LSC_GAN_GR .....................................................
IPIPE_LSC_GAN_GB .................................................................................................
Register Call Summary for Register IPIPE_LSC_GAN_GB......................................................
IPIPE_LSC_GAN_B ...................................................................................................
Register Call Summary for Register IPIPE_LSC_GAN_B ........................................................
7-1013. Register Call Summary for Register IPIPE_DPC_OTF_3_D_THR
7-1014.
7-1015.
7-1016.
7-1017.
7-1018.
7-1019.
7-1020.
7-1021.
7-1022.
7-1023.
7-1024.
7-1025.
7-1026.
7-1027.
7-1028.
7-1029.
7-1030.
7-1031.
7-1032.
7-1033.
7-1034.
7-1035.
7-1036.
7-1037.
7-1038.
7-1039.
7-1040.
7-1041.
7-1042.
7-1043.
7-1044.
7-1045.
7-1046.
7-1047.
7-1048.
7-1049.
7-1050.
7-1051.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2429
2429
2430
2430
2430
2430
2430
2431
2431
2431
2431
2431
2432
2432
2432
2432
2433
2433
2433
2433
2434
2434
2434
2434
2434
2435
2435
2435
2435
2435
2436
2436
2436
2436
2437
2437
2437
2437
2437
143
www.ti.com
...................................................................................................
Register Call Summary for Register IPIPE_LSC_OFT_R ........................................................
IPIPE_LSC_OFT_GR .................................................................................................
Register Call Summary for Register IPIPE_LSC_OFT_GR ......................................................
IPIPE_LSC_OFT_GB .................................................................................................
Register Call Summary for Register IPIPE_LSC_OFT_GB ......................................................
IPIPE_LSC_OFT_B....................................................................................................
Register Call Summary for Register IPIPE_LSC_OFT_B ........................................................
IPIPE_LSC_SHF .......................................................................................................
Register Call Summary for Register IPIPE_LSC_SHF ...........................................................
IPIPE_LSC_MAX ......................................................................................................
Register Call Summary for Register IPIPE_LSC_MAX ...........................................................
IPIPE_D2F_1ST_EN ..................................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_EN .......................................................
IPIPE_D2F_1ST_TYP .................................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_TYP .....................................................
IPIPE_D2F_1ST_THR_00 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_00 ................................................
IPIPE_D2F_1ST_THR_01 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_01 ................................................
IPIPE_D2F_1ST_THR_02 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_02 ................................................
IPIPE_D2F_1ST_THR_03 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_03 ................................................
IPIPE_D2F_1ST_THR_04 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_04 ................................................
IPIPE_D2F_1ST_THR_05 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_05 ................................................
IPIPE_D2F_1ST_THR_06 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_06 ................................................
IPIPE_D2F_1ST_THR_07 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_THR_07 ................................................
IPIPE_D2F_1ST_STR_00 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_00.................................................
IPIPE_D2F_1ST_STR_01 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_01.................................................
IPIPE_D2F_1ST_STR_02 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_02.................................................
IPIPE_D2F_1ST_STR_03 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_03.................................................
IPIPE_D2F_1ST_STR_04 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_04.................................................
IPIPE_D2F_1ST_STR_05 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_05.................................................
IPIPE_D2F_1ST_STR_06 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_06.................................................
IPIPE_D2F_1ST_STR_07 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_STR_07.................................................
IPIPE_D2F_1ST_SPR_00 ............................................................................................
7-1052. IPIPE_LSC_OFT_R
7-1053.
7-1054.
7-1055.
7-1056.
7-1057.
7-1058.
7-1059.
7-1060.
7-1061.
7-1062.
7-1063.
7-1064.
7-1065.
7-1066.
7-1067.
7-1068.
7-1069.
7-1070.
7-1071.
7-1072.
7-1073.
7-1074.
7-1075.
7-1076.
7-1077.
7-1078.
7-1079.
7-1080.
7-1081.
7-1082.
7-1083.
7-1084.
7-1085.
7-1086.
7-1087.
7-1088.
7-1089.
7-1090.
7-1091.
7-1092.
7-1093.
7-1094.
7-1095.
7-1096.
7-1097.
7-1098.
7-1099.
7-1100.
144
List of Tables
2437
2438
2438
2438
2438
2438
2439
2439
2439
2439
2439
2440
2440
2440
2440
2441
2441
2441
2441
2442
2442
2442
2442
2442
2442
2443
2443
2443
2443
2443
2444
2444
2444
2444
2444
2445
2445
2445
2445
2445
2446
2446
2446
2446
2446
2447
2447
2447
2447
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
................................................
IPIPE_D2F_1ST_SPR_01 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_01 ................................................
IPIPE_D2F_1ST_SPR_02 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_02 ................................................
IPIPE_D2F_1ST_SPR_03 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_03 ................................................
IPIPE_D2F_1ST_SPR_04 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_04 ................................................
IPIPE_D2F_1ST_SPR_05 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_05 ................................................
IPIPE_D2F_1ST_SPR_06 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_06 ................................................
IPIPE_D2F_1ST_SPR_07 ............................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_SPR_07 ................................................
IPIPE_D2F_1ST_EDG_MIN ..........................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_EDG_MIN ..............................................
IPIPE_D2F_1ST_EDG_MAX .........................................................................................
Register Call Summary for Register IPIPE_D2F_1ST_EDG_MAX .............................................
IPIPE_D2F_2ND_EN ..................................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_EN ......................................................
IPIPE_D2F_2ND_TYP ................................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_TYP .....................................................
IPIPE_D2F_2ND_THR00 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR00 .................................................
IPIPE_D2F_2ND_THR01 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR01 .................................................
IPIPE_D2F_2ND_THR02 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR02 .................................................
IPIPE_D2F_2ND_THR03 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR03 .................................................
IPIPE_D2F_2ND_THR04 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR04 .................................................
IPIPE_D2F_2ND_THR05 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR05 .................................................
IPIPE_D2F_2ND_THR06 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR06 .................................................
IPIPE_D2F_2ND_THR07 .............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_THR07 .................................................
IPIPE_D2F_2ND_STR_00 ............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_STR_00 ................................................
IPIPE_D2F_2ND_STR_01 ............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_STR_01 ................................................
IPIPE_D2F_2ND_STR_02 ............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_STR_02 ................................................
IPIPE_D2F_2ND_STR_03 ............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_STR_03 ................................................
IPIPE_D2F_2ND_STR_04 ............................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_STR_04 ................................................
7-1101. Register Call Summary for Register IPIPE_D2F_1ST_SPR_00
7-1102.
7-1103.
7-1104.
7-1105.
7-1106.
7-1107.
7-1108.
7-1109.
7-1110.
7-1111.
7-1112.
7-1113.
7-1114.
7-1115.
7-1116.
7-1117.
7-1118.
7-1119.
7-1120.
7-1121.
7-1122.
7-1123.
7-1124.
7-1125.
7-1126.
7-1127.
7-1128.
7-1129.
7-1130.
7-1131.
7-1132.
7-1133.
7-1134.
7-1135.
7-1136.
7-1137.
7-1138.
7-1139.
7-1140.
7-1141.
7-1142.
7-1143.
7-1144.
7-1145.
7-1146.
7-1147.
7-1148.
7-1149.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2447
2448
2448
2448
2448
2448
2449
2449
2449
2449
2449
2450
2450
2450
2450
2450
2451
2451
2451
2451
2451
2452
2452
2452
2452
2453
2453
2453
2453
2453
2454
2454
2454
2454
2454
2455
2455
2455
2455
2455
2456
2456
2456
2456
2456
2457
2457
2457
2457
145
www.ti.com
7-1150. IPIPE_D2F_2ND_STR_05 ............................................................................................ 2457
7-1151. Register Call Summary for Register IPIPE_D2F_2ND_STR_05 ................................................ 2458
7-1152. IPIPE_D2F_2ND_STR_06 ............................................................................................ 2458
7-1153. Register Call Summary for Register IPIPE_D2F_2ND_STR_06 ................................................ 2458
7-1154. IPIPE_D2F_2ND_STR_07 ............................................................................................ 2458
7-1155. Register Call Summary for Register IPIPE_D2F_2ND_STR_07 ................................................ 2458
7-1156. IPIPE_D2F_2ND_SPR_00
...........................................................................................
2459
7-1157. Register Call Summary for Register IPIPE_D2F_2ND_SPR_00 ................................................ 2459
2459
7-1159.
2459
7-1160.
7-1161.
7-1162.
7-1163.
7-1164.
7-1165.
7-1166.
7-1167.
7-1168.
7-1169.
7-1170.
7-1171.
7-1172.
7-1173.
7-1174.
7-1175.
7-1176.
7-1177.
7-1178.
7-1179.
7-1180.
7-1181.
7-1182.
7-1183.
7-1184.
7-1185.
7-1186.
7-1187.
7-1188.
7-1189.
7-1190.
7-1191.
7-1192.
7-1193.
7-1194.
7-1195.
7-1196.
7-1197.
7-1198.
146
...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_01 ................................................
IPIPE_D2F_2ND_SPR_02 ...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_02 ................................................
IPIPE_D2F_2ND_SPR_03 ...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_03 ................................................
IPIPE_D2F_2ND_SPR_04 ...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_04 ................................................
IPIPE_D2F_2ND_SPR_05 ...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_05 ................................................
IPIPE_D2F_2ND_SPR_06 ...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_06 ................................................
IPIPE_D2F_2ND_SPR_07 ...........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_SPR_07 ................................................
IPIPE_D2F_2ND_EDG_MIN .........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_EDG_MIN ..............................................
IPIPE_D2F_2ND_EDG_MAX ........................................................................................
Register Call Summary for Register IPIPE_D2F_2ND_EDG_MAX .............................................
IPIPE_GIC_EN .........................................................................................................
Register Call Summary for Register IPIPE_GIC_EN .............................................................
IPIPE_GIC_TYP .......................................................................................................
Register Call Summary for Register IPIPE_GIC_TYP ............................................................
IPIPE_GIC_GAN .......................................................................................................
Register Call Summary for Register IPIPE_GIC_GAN ...........................................................
IPIPE_GIC_NFGAIN ..................................................................................................
Register Call Summary for Register IPIPE_GIC_NFGAIN .......................................................
IPIPE_GIC_THR .......................................................................................................
Register Call Summary for Register IPIPE_GIC_THR ............................................................
IPIPE_GIC_SLP ........................................................................................................
Register Call Summary for Register IPIPE_GIC_SLP ............................................................
IPIPE_WB2_OFT_R ...................................................................................................
Register Call Summary for Register IPIPE_WB2_OFT_R .......................................................
IPIPE_WB2_OFT_GR .................................................................................................
Register Call Summary for Register IPIPE_WB2_OFT_GR .....................................................
IPIPE_WB2_OFT_GB .................................................................................................
Register Call Summary for Register IPIPE_WB2_OFT_GB .....................................................
IPIPE_WB2_OFT_B ...................................................................................................
Register Call Summary for Register IPIPE_WB2_OFT_B .......................................................
IPIPE_WB2_WGN_R ..................................................................................................
Register Call Summary for Register IPIPE_WB2_WGN_R ......................................................
IPIPE_WB2_WGN_GR................................................................................................
7-1158. IPIPE_D2F_2ND_SPR_01
List of Tables
2459
2460
2460
2460
2460
2460
2461
2461
2461
2461
2461
2462
2462
2462
2462
2462
2463
2463
2463
2463
2464
2464
2464
2464
2464
2465
2465
2465
2465
2465
2466
2466
2466
2466
2466
2467
2467
2467
2467
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1199. Register Call Summary for Register IPIPE_WB2_WGN_GR .................................................... 2468
7-1200. IPIPE_WB2_WGN_GB ................................................................................................ 2468
7-1201. Register Call Summary for Register IPIPE_WB2_WGN_GB .................................................... 2468
7-1202. IPIPE_WB2_WGN_B .................................................................................................. 2468
7-1203. Register Call Summary for Register IPIPE_WB2_WGN_B ...................................................... 2468
7-1204. IPIPE_CFA_MODE .................................................................................................... 2469
7-1205. Register Call Summary for Register IPIPE_CFA_MODE......................................................... 2469
7-1206. IPIPE_CFA_2DIR_HPF_THR ........................................................................................ 2469
7-1207. Register Call Summary for Register IPIPE_CFA_2DIR_HPF_THR............................................. 2469
7-1208. IPIPE_CFA_2DIR_HPF_SLP
........................................................................................
2470
7-1209. Register Call Summary for Register IPIPE_CFA_2DIR_HPF_SLP ............................................. 2470
7-1210. IPIPE_CFA_2DIR_MIX_THR ......................................................................................... 2470
7-1211. Register Call Summary for Register IPIPE_CFA_2DIR_MIX_THR ............................................. 2470
7-1212. IPIPE_CFA_2DIR_MIX_SLP ......................................................................................... 2470
7-1213. Register Call Summary for Register IPIPE_CFA_2DIR_MIX_SLP.............................................. 2471
7-1214. IPIPE_CFA_2DIR_DIR_TRH ......................................................................................... 2471
7-1215. Register Call Summary for Register IPIPE_CFA_2DIR_DIR_TRH ............................................. 2471
7-1216. IPIPE_CFA_2DIR_DIR_SLP ......................................................................................... 2471
7-1217. Register Call Summary for Register IPIPE_CFA_2DIR_DIR_SLP .............................................. 2471
7-1218. IPIPE_CFA_2DIR_NDWT
............................................................................................
2472
7-1219. Register Call Summary for Register IPIPE_CFA_2DIR_NDWT ................................................. 2472
7-1220. IPIPE_CFA_MONO_HUE_FRA ...................................................................................... 2472
7-1221. Register Call Summary for Register IPIPE_CFA_MONO_HUE_FRA .......................................... 2472
7-1222. IPIPE_CFA_MONO_EDG_THR ..................................................................................... 2472
7-1223. Register Call Summary for Register IPIPE_CFA_MONO_EDG_THR .......................................... 2473
7-1224. IPIPE_CFA_MONO_THR_MIN ...................................................................................... 2473
7-1225. Register Call Summary for Register IPIPE_CFA_MONO_THR_MIN ........................................... 2473
7-1226. IPIPE_CFA_MONO_THR_SLP ...................................................................................... 2473
7-1227. Register Call Summary for Register IPIPE_CFA_MONO_THR_SLP........................................... 2473
7-1228. IPIPE_CFA_MONO_SLP_MIN ....................................................................................... 2474
7-1229. Register Call Summary for Register IPIPE_CFA_MONO_SLP_MIN ........................................... 2474
7-1230. IPIPE_CFA_MONO_SLP_SLP....................................................................................... 2474
7-1231. Register Call Summary for Register IPIPE_CFA_MONO_SLP_SLP ........................................... 2474
7-1232. IPIPE_CFA_MONO_LPWT ........................................................................................... 2474
7-1233. Register Call Summary for Register IPIPE_CFA_MONO_LPWT ............................................... 2475
7-1234. IPIPE_RGB1_MUL_RR ............................................................................................... 2475
7-1235. Register Call Summary for Register IPIPE_RGB1_MUL_RR.................................................... 2475
7-1236. IPIPE_RGB1_MUL_GR ............................................................................................... 2475
...................................................
IPIPE_RGB1_MUL_BR ...............................................................................................
Register Call Summary for Register IPIPE_RGB1_MUL_BR ....................................................
IPIPE_RGB1_MUL_RG ...............................................................................................
Register Call Summary for Register IPIPE_RGB1_MUL_RG ...................................................
IPIPE_RGB1_MUL_GG ...............................................................................................
Register Call Summary for Register IPIPE_RGB1_MUL_GG ...................................................
IPIPE_RGB1_MUL_BG ...............................................................................................
Register Call Summary for Register IPIPE_RGB1_MUL_BG....................................................
IPIPE_RGB1_MUL_RB ...............................................................................................
Register Call Summary for Register IPIPE_RGB1_MUL_RB ....................................................
7-1237. Register Call Summary for Register IPIPE_RGB1_MUL_GR
7-1238.
7-1239.
7-1240.
7-1241.
7-1242.
7-1243.
7-1244.
7-1245.
7-1246.
7-1247.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2476
2476
2476
2476
2476
2476
2477
2477
2477
2477
2477
147
www.ti.com
7-1248. IPIPE_RGB1_MUL_GB ............................................................................................... 2478
7-1249. Register Call Summary for Register IPIPE_RGB1_MUL_GB.................................................... 2478
7-1250. IPIPE_RGB1_MUL_BB
...............................................................................................
2478
7-1251. Register Call Summary for Register IPIPE_RGB1_MUL_BB .................................................... 2478
7-1252. IPIPE_RGB1_OFT_OR ............................................................................................... 2478
7-1253. Register Call Summary for Register IPIPE_RGB1_OFT_OR .................................................... 2479
7-1254. IPIPE_RGB1_OFT_OG ............................................................................................... 2479
7-1255. Register Call Summary for Register IPIPE_RGB1_OFT_OG.................................................... 2479
2479
7-1257.
2480
7-1258.
7-1259.
7-1260.
7-1261.
7-1262.
7-1263.
7-1264.
7-1265.
7-1266.
7-1267.
7-1268.
7-1269.
7-1270.
7-1271.
7-1272.
7-1273.
7-1274.
7-1275.
7-1276.
7-1277.
7-1278.
7-1279.
7-1280.
7-1281.
7-1282.
7-1283.
7-1284.
7-1285.
7-1286.
7-1287.
7-1288.
7-1289.
7-1290.
7-1291.
7-1292.
7-1293.
7-1294.
7-1295.
7-1296.
148
...............................................................................................
Register Call Summary for Register IPIPE_RGB1_OFT_OB ....................................................
IPIPE_GMM_CFG .....................................................................................................
Register Call Summary for Register IPIPE_GMM_CFG ..........................................................
IPIPE_RGB2_MUL_RR ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_RR....................................................
IPIPE_RGB2_MUL_GR ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_GR ...................................................
IPIPE_RGB2_MUL_BR ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_BR ....................................................
IPIPE_RGB2_MUL_RG ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_RG ...................................................
IPIPE_RGB2_MUL_GG ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_GG ...................................................
IPIPE_RGB2_MUL_BG ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_BG....................................................
IPIPE_RGB2_MUL_RB ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_RB ....................................................
IPIPE_RGB2_MUL_GB ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_GB....................................................
IPIPE_RGB2_MUL_BB ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_MUL_BB ....................................................
IPIPE_RGB2_OFT_OR ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_OFT_OR ....................................................
IPIPE_RGB2_OFT_OG ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_OFT_OG....................................................
IPIPE_RGB2_OFT_OB ...............................................................................................
Register Call Summary for Register IPIPE_RGB2_OFT_OB ....................................................
IPIPE_3DLUT_EN .....................................................................................................
Register Call Summary for Register IPIPE_3DLUT_EN ..........................................................
IPIPE_YUV_ADJ .......................................................................................................
Register Call Summary for Register IPIPE_YUV_ADJ ...........................................................
IPIPE_YUV_MUL_RY .................................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_RY......................................................
IPIPE_YUV_MUL_GY .................................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_GY .....................................................
IPIPE_YUV_MUL_BY .................................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_BY ......................................................
IPIPE_YUV_MUL_RCB ...............................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_RCB....................................................
IPIPE_YUV_MUL_GCB ...............................................................................................
7-1256. IPIPE_RGB1_OFT_OB
List of Tables
2480
2480
2481
2481
2481
2481
2481
2482
2482
2482
2482
2482
2483
2483
2483
2483
2483
2484
2484
2484
2484
2484
2485
2485
2485
2485
2485
2486
2486
2486
2486
2487
2487
2487
2487
2487
2488
2488
2488
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
...................................................
IPIPE_YUV_MUL_BCB ...............................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_BCB ....................................................
IPIPE_YUV_MUL_RCR ...............................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_RCR ...................................................
IPIPE_YUV_MUL_GCR ...............................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_GCR ...................................................
IPIPE_YUV_MUL_BCR ...............................................................................................
Register Call Summary for Register IPIPE_YUV_MUL_BCR....................................................
IPIPE_YUV_OFT_Y ...................................................................................................
Register Call Summary for Register IPIPE_YUV_OFT_Y ........................................................
IPIPE_YUV_OFT_CB .................................................................................................
Register Call Summary for Register IPIPE_YUV_OFT_CB ......................................................
IPIPE_YUV_OFT_CR .................................................................................................
Register Call Summary for Register IPIPE_YUV_OFT_CR ......................................................
IPIPE_YUV_PHS ......................................................................................................
Register Call Summary for Register IPIPE_YUV_PHS ...........................................................
IPIPE_GBCE_EN ......................................................................................................
Register Call Summary for Register IPIPE_GBCE_EN ...........................................................
IPIPE_GBCE_TYP .....................................................................................................
Register Call Summary for Register IPIPE_GBCE_TYP .........................................................
IPIPE_YEE_EN ........................................................................................................
Register Call Summary for Register IPIPE_YEE_EN .............................................................
IPIPE_YEE_TYP .......................................................................................................
Register Call Summary for Register IPIPE_YEE_TYP ...........................................................
IPIPE_YEE_SHF .......................................................................................................
Register Call Summary for Register IPIPE_YEE_SHF ...........................................................
IPIPE_YEE_MUL_00 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_00 ......................................................
IPIPE_YEE_MUL_01 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_01 ......................................................
IPIPE_YEE_MUL_02 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_02 ......................................................
IPIPE_YEE_MUL_10 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_10 ......................................................
IPIPE_YEE_MUL_11 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_11 ......................................................
IPIPE_YEE_MUL_12 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_12 ......................................................
IPIPE_YEE_MUL_20 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_20 ......................................................
IPIPE_YEE_MUL_21 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_21 ......................................................
IPIPE_YEE_MUL_22 ..................................................................................................
Register Call Summary for Register IPIPE_YEE_MUL_22 ......................................................
IPIPE_YEE_THR.......................................................................................................
Register Call Summary for Register IPIPE_YEE_THR ...........................................................
IPIPE_YEE_E_GAN ...................................................................................................
Register Call Summary for Register IPIPE_YEE_E_GAN .......................................................
7-1297. Register Call Summary for Register IPIPE_YUV_MUL_GCB
7-1298.
7-1299.
7-1300.
7-1301.
7-1302.
7-1303.
7-1304.
7-1305.
7-1306.
7-1307.
7-1308.
7-1309.
7-1310.
7-1311.
7-1312.
7-1313.
7-1314.
7-1315.
7-1316.
7-1317.
7-1318.
7-1319.
7-1320.
7-1321.
7-1322.
7-1323.
7-1324.
7-1325.
7-1326.
7-1327.
7-1328.
7-1329.
7-1330.
7-1331.
7-1332.
7-1333.
7-1334.
7-1335.
7-1336.
7-1337.
7-1338.
7-1339.
7-1340.
7-1341.
7-1342.
7-1343.
7-1344.
7-1345.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2488
2488
2489
2489
2489
2489
2489
2490
2490
2490
2490
2490
2491
2491
2491
2491
2492
2492
2492
2493
2493
2493
2493
2493
2494
2494
2494
2494
2495
2495
2495
2495
2496
2496
2496
2496
2496
2496
2497
2497
2497
2497
2497
2498
2498
2498
2498
2498
2499
149
www.ti.com
7-1346. IPIPE_YEE_E_THR_1 ................................................................................................ 2499
7-1347. Register Call Summary for Register IPIPE_YEE_E_THR_1 ..................................................... 2499
7-1348. IPIPE_YEE_E_THR_2 ................................................................................................ 2499
7-1349. Register Call Summary for Register IPIPE_YEE_E_THR_2 ..................................................... 2500
7-1350. IPIPE_YEE_G_GAN ................................................................................................... 2500
7-1351. Register Call Summary for Register IPIPE_YEE_G_GAN ....................................................... 2500
7-1352. IPIPE_YEE_G_OFT ................................................................................................... 2500
7-1353. Register Call Summary for Register IPIPE_YEE_G_OFT ........................................................ 2500
7-1354. IPIPE_CAR_EN ........................................................................................................ 2501
7-1355. Register Call Summary for Register IPIPE_CAR_EN............................................................. 2501
7-1356. IPIPE_CAR_TYP....................................................................................................... 2501
7-1357. Register Call Summary for Register IPIPE_CAR_TYP ........................................................... 2502
7-1358. IPIPE_CAR_SW
.......................................................................................................
2502
7-1359. Register Call Summary for Register IPIPE_CAR_SW ............................................................ 2502
7-1360. IPIPE_CAR_HPF_TYP ................................................................................................ 2502
7-1361. Register Call Summary for Register IPIPE_CAR_HPF_TYP .................................................... 2502
7-1362. IPIPE_CAR_HPF_SHF................................................................................................ 2503
7-1363. Register Call Summary for Register IPIPE_CAR_HPF_SHF .................................................... 2503
2503
7-1365.
2503
7-1366.
7-1367.
7-1368.
7-1369.
7-1370.
7-1371.
7-1372.
7-1373.
7-1374.
7-1375.
7-1376.
7-1377.
7-1378.
7-1379.
7-1380.
7-1381.
7-1382.
7-1383.
7-1384.
7-1385.
7-1386.
7-1387.
7-1388.
7-1389.
7-1390.
7-1391.
7-1392.
7-1393.
7-1394.
150
...............................................................................................
Register Call Summary for Register IPIPE_CAR_HPF_THR ....................................................
IPIPE_CAR_GN1_GAN ...............................................................................................
Register Call Summary for Register IPIPE_CAR_GN1_GAN ...................................................
IPIPE_CAR_GN1_SHF ...............................................................................................
Register Call Summary for Register IPIPE_CAR_GN1_SHF ....................................................
IPIPE_CAR_GN1_MIN ................................................................................................
Register Call Summary for Register IPIPE_CAR_GN1_MIN ....................................................
IPIPE_CAR_GN2_GAN ...............................................................................................
Register Call Summary for Register IPIPE_CAR_GN2_GAN ...................................................
IPIPE_CAR_GN2_SHF ...............................................................................................
Register Call Summary for Register IPIPE_CAR_GN2_SHF ....................................................
IPIPE_CAR_GN2_MIN ................................................................................................
Register Call Summary for Register IPIPE_CAR_GN2_MIN ....................................................
IPIPE_CGS_EN ........................................................................................................
Register Call Summary for Register IPIPE_CGS_EN ............................................................
IPIPE_CGS_GN1_L_THR ............................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_L_THR.................................................
IPIPE_CGS_GN1_L_GAIN ...........................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_L_GAIN................................................
IPIPE_CGS_GN1_L_SHF ............................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_L_SHF .................................................
IPIPE_CGS_GN1_L_MIN .............................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_L_MIN .................................................
IPIPE_CGS_GN1_H_THR ............................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_H_THR ................................................
IPIPE_CGS_GN1_H_GAIN...........................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_H_GAIN ...............................................
IPIPE_CGS_GN1_H_SHF ............................................................................................
Register Call Summary for Register IPIPE_CGS_GN1_H_SHF ................................................
IPIPE_CGS_GN1_H_MIN ............................................................................................
7-1364. IPIPE_CAR_HPF_THR
List of Tables
2503
2504
2504
2504
2504
2504
2505
2505
2505
2505
2505
2506
2506
2506
2506
2506
2507
2507
2507
2507
2507
2508
2508
2508
2508
2508
2509
2509
2509
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1395. Register Call Summary for Register IPIPE_CGS_GN1_H_MIN ................................................. 2509
7-1396. IPIPE_CGS_GN2_L_THR ............................................................................................ 2509
7-1397. Register Call Summary for Register IPIPE_CGS_GN2_L_THR................................................. 2510
7-1398. IPIPE_CGS_GN2_L_GAIN ........................................................................................... 2510
7-1399. Register Call Summary for Register IPIPE_CGS_GN2_L_GAIN................................................ 2510
7-1400. IPIPE_CGS_GN2_L_SHF ............................................................................................ 2510
7-1401. Register Call Summary for Register IPIPE_CGS_GN2_L_SHF ................................................. 2510
7-1402. IPIPE_CGS_GN2_L_MIN ............................................................................................. 2511
7-1403. Register Call Summary for Register IPIPE_CGS_GN2_L_MIN ................................................. 2511
7-1404. IPIPE_BOX_EN ........................................................................................................ 2511
7-1405. Register Call Summary for Register IPIPE_BOX_EN............................................................. 2511
7-1406. IPIPE_BOX_MODE .................................................................................................... 2511
7-1407. Register Call Summary for Register IPIPE_BOX_MODE ........................................................ 2512
7-1408. IPIPE_BOX_TYP....................................................................................................... 2512
7-1409. Register Call Summary for Register IPIPE_BOX_TYP ........................................................... 2512
......................................................................................................
Register Call Summary for Register IPIPE_BOX_SHF ...........................................................
IPIPE_BOX_SDR_SAD_H ............................................................................................
Register Call Summary for Register IPIPE_BOX_SDR_SAD_H ................................................
IPIPE_BOX_SDR_SAD_L ............................................................................................
Register Call Summary for Register IPIPE_BOX_SDR_SAD_L.................................................
IPIPE_HST_EN ........................................................................................................
Register Call Summary for Register IPIPE_HST_EN .............................................................
IPIPE_HST_MODE ....................................................................................................
Register Call Summary for Register IPIPE_HST_MODE.........................................................
IPIPE_HST_SEL .......................................................................................................
Register Call Summary for Register IPIPE_HST_SEL............................................................
IPIPE_HST_PARA .....................................................................................................
Register Call Summary for Register IPIPE_HST_PARA .........................................................
IPIPE_HST_0_VPS ....................................................................................................
Register Call Summary for Register IPIPE_HST_0_VPS ........................................................
IPIPE_HST_0_VSZ ....................................................................................................
Register Call Summary for Register IPIPE_HST_0_VSZ ........................................................
IPIPE_HST_0_HPS....................................................................................................
Register Call Summary for Register IPIPE_HST_0_HPS ........................................................
IPIPE_HST_0_HSZ ....................................................................................................
Register Call Summary for Register IPIPE_HST_0_HSZ ........................................................
IPIPE_HST_1_VPS ....................................................................................................
Register Call Summary for Register IPIPE_HST_1_VPS ........................................................
IPIPE_HST_1_VSZ ....................................................................................................
Register Call Summary for Register IPIPE_HST_1_VSZ ........................................................
IPIPE_HST_1_HPS....................................................................................................
Register Call Summary for Register IPIPE_HST_1_HPS ........................................................
IPIPE_HST_1_HSZ ....................................................................................................
Register Call Summary for Register IPIPE_HST_1_HSZ ........................................................
IPIPE_HST_2_VPS ....................................................................................................
Register Call Summary for Register IPIPE_HST_2_VPS ........................................................
IPIPE_HST_2_VSZ ....................................................................................................
Register Call Summary for Register IPIPE_HST_2_VSZ ........................................................
7-1410. IPIPE_BOX_SHF
2512
7-1411.
2513
7-1412.
7-1413.
7-1414.
7-1415.
7-1416.
7-1417.
7-1418.
7-1419.
7-1420.
7-1421.
7-1422.
7-1423.
7-1424.
7-1425.
7-1426.
7-1427.
7-1428.
7-1429.
7-1430.
7-1431.
7-1432.
7-1433.
7-1434.
7-1435.
7-1436.
7-1437.
7-1438.
7-1439.
7-1440.
7-1441.
7-1442.
7-1443.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2513
2513
2513
2514
2514
2514
2514
2515
2515
2515
2515
2516
2516
2517
2517
2517
2518
2518
2518
2519
2519
2519
2519
2520
2520
2520
2520
2521
2521
2521
2522
2522
151
www.ti.com
7-1444. IPIPE_HST_2_HPS.................................................................................................... 2522
7-1445. Register Call Summary for Register IPIPE_HST_2_HPS ........................................................ 2523
7-1446. IPIPE_HST_2_HSZ .................................................................................................... 2523
7-1447. Register Call Summary for Register IPIPE_HST_2_HSZ ........................................................ 2523
7-1448. IPIPE_HST_3_VPS .................................................................................................... 2523
7-1449. Register Call Summary for Register IPIPE_HST_3_VPS ........................................................ 2524
7-1450. IPIPE_HST_3_VSZ .................................................................................................... 2524
7-1451. Register Call Summary for Register IPIPE_HST_3_VSZ
........................................................
2524
7-1452. IPIPE_HST_3_HPS.................................................................................................... 2524
7-1453. Register Call Summary for Register IPIPE_HST_3_HPS ........................................................ 2525
7-1454. IPIPE_HST_3_HSZ .................................................................................................... 2525
7-1455. Register Call Summary for Register IPIPE_HST_3_HSZ ........................................................ 2525
7-1456. IPIPE_HST_TBL ....................................................................................................... 2526
7-1457. Register Call Summary for Register IPIPE_HST_TBL ............................................................ 2526
7-1458. IPIPE_HST_MUL_R ................................................................................................... 2526
2527
7-1460.
2527
7-1461.
7-1462.
7-1463.
7-1464.
7-1465.
7-1466.
7-1467.
7-1468.
7-1469.
7-1470.
7-1471.
7-1472.
7-1473.
7-1474.
7-1475.
7-1476.
7-1477.
7-1478.
7-1479.
7-1480.
7-1481.
7-1482.
7-1483.
7-1484.
7-1485.
7-1486.
7-1487.
7-1488.
7-1489.
7-1490.
7-1491.
7-1492.
152
.......................................................
IPIPE_HST_MUL_GR .................................................................................................
Register Call Summary for Register IPIPE_HST_MUL_GR .....................................................
IPIPE_HST_MUL_GB .................................................................................................
Register Call Summary for Register IPIPE_HST_MUL_GB......................................................
IPIPE_HST_MUL_B ...................................................................................................
Register Call Summary for Register IPIPE_HST_MUL_B ........................................................
IPIPE_BSC_EN ........................................................................................................
Register Call Summary for Register IPIPE_BSC_EN .............................................................
IPIPE_BSC_MODE ....................................................................................................
Register Call Summary for Register IPIPE_BSC_MODE ........................................................
IPIPE_BSC_TYP .......................................................................................................
Register Call Summary for Register IPIPE_BSC_TYP ...........................................................
IPIPE_BSC_ROW_VCT ..............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_VCT ...................................................
IPIPE_BSC_ROW_SHF ..............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_SHF ...................................................
IPIPE_BSC_ROW_VPOS ............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_VPOS .................................................
IPIPE_BSC_ROW_VNUM ............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_VNUM ................................................
IPIPE_BSC_ROW_VSKIP ............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_VSKIP ................................................
IPIPE_BSC_ROW_HPOS ............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_HPOS .................................................
IPIPE_BSC_ROW_HNUM ............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_HNUM ................................................
IPIPE_BSC_ROW_HSKIP ............................................................................................
Register Call Summary for Register IPIPE_BSC_ROW_HSKIP ................................................
IPIPE_BSC_COL_VCT ...............................................................................................
Register Call Summary for Register IPIPE_BSC_COL_VCT ....................................................
IPIPE_BSC_COL_SHF ...............................................................................................
Register Call Summary for Register IPIPE_BSC_COL_SHF ....................................................
IPIPE_BSC_COL_VPOS .............................................................................................
7-1459. Register Call Summary for Register IPIPE_HST_MUL_R
List of Tables
2527
2527
2527
2527
2528
2528
2528
2528
2529
2529
2529
2529
2530
2530
2530
2530
2531
2531
2531
2531
2531
2532
2532
2532
2532
2533
2533
2533
2533
2533
2534
2534
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1493. Register Call Summary for Register IPIPE_BSC_COL_VPOS .................................................. 2534
7-1494. IPIPE_BSC_COL_VNUM ............................................................................................. 2534
7-1495. Register Call Summary for Register IPIPE_BSC_COL_VNUM
.................................................
2535
7-1496. IPIPE_BSC_COL_VSKIP ............................................................................................. 2535
7-1497. Register Call Summary for Register IPIPE_BSC_COL_VSKIP
.................................................
2535
7-1498. IPIPE_BSC_COL_HPOS ............................................................................................. 2535
7-1499. Register Call Summary for Register IPIPE_BSC_COL_HPOS .................................................. 2536
7-1500. IPIPE_BSC_COL_HNUM ............................................................................................. 2536
7-1501. Register Call Summary for Register IPIPE_BSC_COL_HNUM ................................................. 2536
7-1502. IPIPE_BSC_COL_HSKIP ............................................................................................. 2536
7-1503. Register Call Summary for Register IPIPE_BSC_COL_HSKIP ................................................. 2536
7-1504. IPIPE_YUV_INP_OFST_Y
...........................................................................................
2537
7-1505. Register Call Summary for Register IPIPE_YUV_INP_OFST_Y ................................................ 2537
7-1506. IPIPE_YUV_INP_OFST_CB.......................................................................................... 2537
7-1507. Register Call Summary for Register IPIPE_YUV_INP_OFST_CB .............................................. 2537
.........................................................................................
Register Call Summary for Register IPIPE_YUV_INP_OFST_CR ..............................................
ISS ISP6P5_ISIF Registers Mapping Summary ...................................................................
ISIF_SYNCEN ..........................................................................................................
Register Call Summary for Register ISIF_SYNCEN ..............................................................
ISIF_MODESET ........................................................................................................
Register Call Summary for Register ISIF_MODESET ............................................................
ISIF_HDW ..............................................................................................................
Register Call Summary for Register ISIF_HDW ...................................................................
ISIF_VDW ...............................................................................................................
Register Call Summary for Register ISIF_VDW ...................................................................
ISIF_PPLN ..............................................................................................................
Register Call Summary for Register ISIF_PPLN ..................................................................
ISIF_LPFR ..............................................................................................................
Register Call Summary for Register ISIF_LPFR...................................................................
ISIF_SPH ...............................................................................................................
Register Call Summary for Register ISIF_SPH ....................................................................
ISIF_LNH................................................................................................................
Register Call Summary for Register ISIF_LNH ....................................................................
ISIF_SLV0 ..............................................................................................................
Register Call Summary for Register ISIF_SLV0 ...................................................................
ISIF_SLV1 ..............................................................................................................
Register Call Summary for Register ISIF_SLV1 ...................................................................
ISIF_LNV ................................................................................................................
Register Call Summary for Register ISIF_LNV ....................................................................
ISIF_CULH ..............................................................................................................
Register Call Summary for Register ISIF_CULH ..................................................................
ISIF_CULV ..............................................................................................................
Register Call Summary for Register ISIF_CULV ..................................................................
ISIF_HSIZE .............................................................................................................
Register Call Summary for Register ISIF_HSIZE..................................................................
ISIF_SDOFST ..........................................................................................................
Register Call Summary for Register ISIF_SDOFST...............................................................
ISIF_CADU .............................................................................................................
7-1508. IPIPE_YUV_INP_OFST_CR
2537
7-1509.
2538
7-1510.
7-1511.
7-1512.
7-1513.
7-1514.
7-1515.
7-1516.
7-1517.
7-1518.
7-1519.
7-1520.
7-1521.
7-1522.
7-1523.
7-1524.
7-1525.
7-1526.
7-1527.
7-1528.
7-1529.
7-1530.
7-1531.
7-1532.
7-1533.
7-1534.
7-1535.
7-1536.
7-1537.
7-1538.
7-1539.
7-1540.
7-1541.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2538
2541
2541
2541
2543
2543
2543
2543
2544
2544
2544
2544
2545
2545
2545
2545
2546
2546
2546
2546
2547
2547
2547
2547
2548
2548
2548
2548
2549
2549
2550
2551
153
www.ti.com
7-1542. Register Call Summary for Register ISIF_CADU .................................................................. 2551
7-1543. ISIF_CADL .............................................................................................................. 2551
7-1544. Register Call Summary for Register ISIF_CADL .................................................................. 2551
7-1545. ISIF_LINCFG0.......................................................................................................... 2551
7-1546. Register Call Summary for Register ISIF_LINCFG0 .............................................................. 2552
7-1547. ISIF_LINCFG1.......................................................................................................... 2552
7-1548. Register Call Summary for Register ISIF_LINCFG1 .............................................................. 2553
7-1549. ISIF_CCOLP ............................................................................................................ 2553
7-1550. Register Call Summary for Register ISIF_CCOLP ................................................................ 2554
7-1551. ISIF_CRGAIN
..........................................................................................................
2554
7-1552. Register Call Summary for Register ISIF_CRGAIN ............................................................... 2555
7-1553. ISIF_CGRGAIN
........................................................................................................
2555
7-1554. Register Call Summary for Register ISIF_CGRGAIN ............................................................. 2555
2555
7-1556.
2555
7-1557.
7-1558.
7-1559.
7-1560.
7-1561.
7-1562.
7-1563.
7-1564.
7-1565.
7-1566.
7-1567.
7-1568.
7-1569.
7-1570.
7-1571.
7-1572.
7-1573.
7-1574.
7-1575.
7-1576.
7-1577.
7-1578.
7-1579.
7-1580.
7-1581.
7-1582.
7-1583.
7-1584.
7-1585.
7-1586.
7-1587.
7-1588.
7-1589.
7-1590.
154
........................................................................................................
Register Call Summary for Register ISIF_CGBGAIN .............................................................
ISIF_CBGAIN ...........................................................................................................
Register Call Summary for Register ISIF_CBGAIN ...............................................................
ISIF_COFSTA ..........................................................................................................
Register Call Summary for Register ISIF_COFSTA...............................................................
ISIF_FLSHCFG0 .......................................................................................................
Register Call Summary for Register ISIF_FLSHCFG0 ...........................................................
ISIF_FLSHCFG1 .......................................................................................................
Register Call Summary for Register ISIF_FLSHCFG1 ...........................................................
ISIF_FLSHCFG2 .......................................................................................................
Register Call Summary for Register ISIF_FLSHCFG2 ...........................................................
ISIF_VDINT0 ...........................................................................................................
Register Call Summary for Register ISIF_VDINT0 ................................................................
ISIF_VDINT1 ...........................................................................................................
Register Call Summary for Register ISIF_VDINT1 ................................................................
ISIF_VDINT2 ...........................................................................................................
Register Call Summary for Register ISIF_VDINT2 ................................................................
ISIF_MISC ..............................................................................................................
Register Call Summary for Register ISIF_MISC ...................................................................
ISIF_CGAMMAWD ....................................................................................................
Register Call Summary for Register ISIF_CGAMMAWD .........................................................
ISIF_REC656IF ........................................................................................................
Register Call Summary for Register ISIF_REC656IF .............................................................
ISIF_CCDCFG .........................................................................................................
Register Call Summary for Register ISIF_CCDCFG ..............................................................
ISIF_DFCCTL ..........................................................................................................
Register Call Summary for Register ISIF_DFCCTL ...............................................................
ISIF_VDFSATLV .......................................................................................................
Register Call Summary for Register ISIF_VDFSATLV............................................................
ISIF_DFCMEMCTL ....................................................................................................
Register Call Summary for Register ISIF_DFCMEMCTL.........................................................
ISIF_DFCMEM0 ........................................................................................................
Register Call Summary for Register ISIF_DFCMEM0 ............................................................
ISIF_DFCMEM1 ........................................................................................................
Register Call Summary for Register ISIF_DFCMEM1 ............................................................
7-1555. ISIF_CGBGAIN
List of Tables
2556
2556
2556
2556
2556
2557
2557
2557
2557
2558
2558
2558
2558
2559
2559
2559
2559
2560
2560
2561
2561
2562
2562
2563
2564
2564
2564
2565
2565
2565
2566
2566
2566
2566
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1591. ISIF_DFCMEM2 ........................................................................................................ 2567
7-1592. Register Call Summary for Register ISIF_DFCMEM2 ............................................................ 2567
7-1593. ISIF_DFCMEM3 ........................................................................................................ 2567
7-1594. Register Call Summary for Register ISIF_DFCMEM3 ............................................................ 2567
7-1595. ISIF_DFCMEM4 ........................................................................................................ 2567
7-1596. Register Call Summary for Register ISIF_DFCMEM4 ............................................................ 2568
7-1597. ISIF_CLAMPCFG ...................................................................................................... 2568
..........................................................
......................................................................................................
Register Call Summary for Register ISIF_CLDCOFST ...........................................................
ISIF_CLSV ..............................................................................................................
Register Call Summary for Register ISIF_CLSV ..................................................................
ISIF_CLHWIN0 .........................................................................................................
Register Call Summary for Register ISIF_CLHWIN0 .............................................................
ISIF_CLHWIN1 .........................................................................................................
Register Call Summary for Register ISIF_CLHWIN1 .............................................................
ISIF_CLHWIN2 .........................................................................................................
Register Call Summary for Register ISIF_CLHWIN2 .............................................................
ISIF_CLVRV ............................................................................................................
Register Call Summary for Register ISIF_CLVRV ................................................................
ISIF_CLVWIN0 .........................................................................................................
Register Call Summary for Register ISIF_CLVWIN0 .............................................................
ISIF_CLVWIN1 .........................................................................................................
Register Call Summary for Register ISIF_CLVWIN1 .............................................................
ISIF_CLVWIN2 .........................................................................................................
Register Call Summary for Register ISIF_CLVWIN2 .............................................................
ISIF_CLVWIN3 .........................................................................................................
Register Call Summary for Register ISIF_CLVWIN3 .............................................................
ISIF_LSCHOFST.......................................................................................................
Register Call Summary for Register ISIF_LSCHOFST ...........................................................
ISIF_LSCVOFST .......................................................................................................
Register Call Summary for Register ISIF_LSCVOFST ...........................................................
ISIF_LSCHVAL .........................................................................................................
Register Call Summary for Register ISIF_LSCHVAL .............................................................
ISIF_LSCVVAL .........................................................................................................
Register Call Summary for Register ISIF_LSCVVAL .............................................................
ISIF_2DLSCCFG.......................................................................................................
Register Call Summary for Register ISIF_2DLSCCFG ...........................................................
ISIF_2DLSCOFST .....................................................................................................
Register Call Summary for Register ISIF_2DLSCOFST..........................................................
ISIF_2DLSCINI .........................................................................................................
Register Call Summary for Register ISIF_2DLSCINI .............................................................
ISIF_2DLSCGRBU ....................................................................................................
Register Call Summary for Register ISIF_2DLSCGRBU .........................................................
ISIF_2DLSCGRBL .....................................................................................................
Register Call Summary for Register ISIF_2DLSCGRBL .........................................................
ISIF_2DLSCGROF ....................................................................................................
Register Call Summary for Register ISIF_2DLSCGROF .........................................................
ISIF_2DLSCORBU ....................................................................................................
7-1598. Register Call Summary for Register ISIF_CLAMPCFG
2569
7-1599. ISIF_CLDCOFST
2569
7-1600.
2569
7-1601.
7-1602.
7-1603.
7-1604.
7-1605.
7-1606.
7-1607.
7-1608.
7-1609.
7-1610.
7-1611.
7-1612.
7-1613.
7-1614.
7-1615.
7-1616.
7-1617.
7-1618.
7-1619.
7-1620.
7-1621.
7-1622.
7-1623.
7-1624.
7-1625.
7-1626.
7-1627.
7-1628.
7-1629.
7-1630.
7-1631.
7-1632.
7-1633.
7-1634.
7-1635.
7-1636.
7-1637.
7-1638.
7-1639.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2569
2570
2570
2571
2571
2571
2571
2572
2572
2572
2572
2573
2573
2573
2574
2574
2574
2574
2575
2575
2575
2575
2575
2576
2576
2576
2576
2579
2579
2579
2580
2580
2580
2580
2581
2581
2581
2581
2581
155
www.ti.com
7-1640. Register Call Summary for Register ISIF_2DLSCORBU ......................................................... 2582
7-1641. ISIF_2DLSCORBL ..................................................................................................... 2582
2582
7-1643. ISIF_2DLSCOROF
2582
7-1644.
2583
7-1645.
7-1646.
7-1647.
7-1648.
7-1649.
7-1650.
7-1651.
7-1652.
7-1653.
7-1654.
7-1655.
7-1656.
7-1657.
7-1658.
7-1659.
7-1660.
7-1661.
7-1662.
7-1663.
7-1664.
7-1665.
7-1666.
7-1667.
7-1668.
7-1669.
7-1670.
7-1671.
7-1672.
7-1673.
7-1674.
7-1675.
7-1676.
7-1677.
7-1678.
7-1679.
7-1680.
7-1681.
7-1682.
7-1683.
7-1684.
7-1685.
7-1686.
7-1687.
7-1688.
156
.........................................................
....................................................................................................
Register Call Summary for Register ISIF_2DLSCOROF .........................................................
ISIF_2DLSCIRQEN ....................................................................................................
Register Call Summary for Register ISIF_2DLSCIRQEN ........................................................
ISIF_2DLSCIRQST ....................................................................................................
Register Call Summary for Register ISIF_2DLSCIRQST.........................................................
ISIF_FMTCFG ..........................................................................................................
Register Call Summary for Register ISIF_FMTCFG ..............................................................
ISIF_FMTPLEN ........................................................................................................
Register Call Summary for Register ISIF_FMTPLEN .............................................................
ISIF_FMTSPH ..........................................................................................................
Register Call Summary for Register ISIF_FMTSPH ..............................................................
ISIF_FMTLNH ..........................................................................................................
Register Call Summary for Register ISIF_FMTLNH...............................................................
ISIF_FMTLSV ..........................................................................................................
Register Call Summary for Register ISIF_FMTLSV ...............................................................
ISIF_FMTLNV ..........................................................................................................
Register Call Summary for Register ISIF_FMTLNV ...............................................................
ISIF_FMTRLEN ........................................................................................................
Register Call Summary for Register ISIF_FMTRLEN .............................................................
ISIF_FMTHCNT ........................................................................................................
Register Call Summary for Register ISIF_FMTHCNT ............................................................
ISIF_FMTAPTR0 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR0 ...........................................................
ISIF_FMTAPTR1 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR1 ...........................................................
ISIF_FMTAPTR2 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR2 ...........................................................
ISIF_FMTAPTR3 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR3 ...........................................................
ISIF_FMTAPTR4 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR4 ...........................................................
ISIF_FMTAPTR5 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR5 ...........................................................
ISIF_FMTAPTR6 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR6 ...........................................................
ISIF_FMTAPTR7 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR7 ...........................................................
ISIF_FMTAPTR8 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR8 ...........................................................
ISIF_FMTAPTR9 .......................................................................................................
Register Call Summary for Register ISIF_FMTAPTR9 ...........................................................
ISIF_FMTAPTR10 .....................................................................................................
Register Call Summary for Register ISIF_FMTAPTR10 ..........................................................
ISIF_FMTAPTR11 .....................................................................................................
Register Call Summary for Register ISIF_FMTAPTR11 ..........................................................
7-1642. Register Call Summary for Register ISIF_2DLSCORBL
List of Tables
2583
2584
2584
2585
2585
2586
2586
2586
2586
2587
2587
2587
2587
2587
2588
2588
2588
2588
2588
2589
2589
2589
2589
2590
2590
2590
2590
2591
2591
2591
2591
2592
2592
2592
2592
2593
2593
2593
2593
2594
2594
2594
2594
2595
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1689. ISIF_FMTAPTR12 ..................................................................................................... 2595
7-1690. Register Call Summary for Register ISIF_FMTAPTR12 .......................................................... 2595
7-1691. ISIF_FMTAPTR13 ..................................................................................................... 2595
7-1692. Register Call Summary for Register ISIF_FMTAPTR13 .......................................................... 2596
7-1693. ISIF_FMTAPTR14 ..................................................................................................... 2596
7-1694. Register Call Summary for Register ISIF_FMTAPTR14 .......................................................... 2596
7-1695. ISIF_FMTAPTR15 ..................................................................................................... 2596
7-1696. Register Call Summary for Register ISIF_FMTAPTR15 .......................................................... 2597
7-1697. ISIF_FMTPGMVF0 .................................................................................................... 2597
7-1698. Register Call Summary for Register ISIF_FMTPGMVF0 ......................................................... 2598
7-1699. ISIF_FMTPGMVF1 .................................................................................................... 2598
7-1700. Register Call Summary for Register ISIF_FMTPGMVF1 ......................................................... 2600
7-1701. ISIF_FMTPGMAPU0 .................................................................................................. 2600
7-1702. Register Call Summary for Register ISIF_FMTPGMAPU0 ....................................................... 2601
7-1703. ISIF_FMTPGMAPU1 .................................................................................................. 2601
7-1704. Register Call Summary for Register ISIF_FMTPGMAPU1 ....................................................... 2603
7-1705. ISIF_FMTPGMAPS0
..................................................................................................
2603
7-1706. Register Call Summary for Register ISIF_FMTPGMAPS0 ....................................................... 2603
..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS1 .......................................................
ISIF_FMTPGMAPS2 ..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS2 .......................................................
ISIF_FMTPGMAPS3 ..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS3 .......................................................
ISIF_FMTPGMAPS4 ..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS4 .......................................................
ISIF_FMTPGMAPS5 ..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS5 .......................................................
ISIF_FMTPGMAPS6 ..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS6 .......................................................
ISIF_FMTPGMAPS7 ..................................................................................................
Register Call Summary for Register ISIF_FMTPGMAPS7 .......................................................
ISIF_CSCCTL ..........................................................................................................
Register Call Summary for Register ISIF_CSCCTL ...............................................................
ISIF_CSCM0 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM0 ................................................................
ISIF_CSCM1 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM1 ................................................................
ISIF_CSCM2 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM2 ................................................................
ISIF_CSCM3 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM3 ................................................................
ISIF_CSCM4 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM4 ................................................................
ISIF_CSCM5 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM5 ................................................................
ISIF_CSCM6 ...........................................................................................................
Register Call Summary for Register ISIF_CSCM6 ................................................................
ISIF_CSCM7 ...........................................................................................................
7-1707. ISIF_FMTPGMAPS1
2603
7-1708.
2604
7-1709.
7-1710.
7-1711.
7-1712.
7-1713.
7-1714.
7-1715.
7-1716.
7-1717.
7-1718.
7-1719.
7-1720.
7-1721.
7-1722.
7-1723.
7-1724.
7-1725.
7-1726.
7-1727.
7-1728.
7-1729.
7-1730.
7-1731.
7-1732.
7-1733.
7-1734.
7-1735.
7-1736.
7-1737.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2604
2604
2604
2605
2605
2605
2605
2606
2606
2606
2606
2607
2607
2607
2607
2607
2608
2608
2608
2608
2608
2609
2609
2609
2609
2610
2610
2610
2610
157
www.ti.com
7-1738. Register Call Summary for Register ISIF_CSCM7 ................................................................ 2611
7-1739. ISIF_OBWIN0 .......................................................................................................... 2611
7-1740. Register Call Summary for Register ISIF_OBWIN0 ............................................................... 2611
7-1741. ISIF_OBWIN1 .......................................................................................................... 2611
7-1742. Register Call Summary for Register ISIF_OBWIN1 ............................................................... 2611
7-1743. ISIF_OBWIN2 .......................................................................................................... 2611
7-1744. Register Call Summary for Register ISIF_OBWIN2 ............................................................... 2612
7-1745. ISIF_OBWIN3 .......................................................................................................... 2612
7-1746. Register Call Summary for Register ISIF_OBWIN3 ............................................................... 2612
7-1747. ISIF_OBVAL0
..........................................................................................................
2612
7-1748. Register Call Summary for Register ISIF_OBVAL0 ............................................................... 2612
7-1749. ISIF_OBVAL1
..........................................................................................................
2613
7-1750. Register Call Summary for Register ISIF_OBVAL1 ............................................................... 2613
2613
7-1752.
2613
7-1753.
7-1754.
7-1755.
7-1756.
7-1757.
7-1758.
7-1759.
7-1760.
7-1761.
7-1762.
7-1763.
7-1764.
7-1765.
7-1766.
7-1767.
7-1768.
7-1769.
7-1770.
7-1771.
7-1772.
7-1773.
7-1774.
7-1775.
7-1776.
7-1777.
7-1778.
7-1779.
7-1780.
7-1781.
7-1782.
7-1783.
7-1784.
7-1785.
7-1786.
158
..........................................................................................................
Register Call Summary for Register ISIF_OBVAL2 ...............................................................
ISIF_OBVAL3 ..........................................................................................................
Register Call Summary for Register ISIF_OBVAL3 ...............................................................
ISIF_OBVAL4 ..........................................................................................................
Register Call Summary for Register ISIF_OBVAL4 ...............................................................
ISIF_OBVAL5 ..........................................................................................................
Register Call Summary for Register ISIF_OBVAL5 ...............................................................
ISIF_OBVAL6 ..........................................................................................................
Register Call Summary for Register ISIF_OBVAL6 ...............................................................
ISIF_OBVAL7 ..........................................................................................................
Register Call Summary for Register ISIF_OBVAL7 ...............................................................
ISIF_CLKCTL ...........................................................................................................
Register Call Summary for Register ISIF_CLKCTL ...............................................................
ISIF_CBN ...............................................................................................................
Register Call Summary for Register ISIF_CBN ....................................................................
ISS ISP6P5_IPIPEIF Registers Mapping Summary ..............................................................
IPIPEIF_ENABLE ......................................................................................................
Register Call Summary for Register IPIPEIF_ENABLE ..........................................................
IPIPEIF_CFG1 .........................................................................................................
Register Call Summary for Register IPIPEIF_CFG1 ..............................................................
IPIPEIF_PPLN..........................................................................................................
Register Call Summary for Register IPIPEIF_PPLN ..............................................................
IPIPEIF_LPFR ..........................................................................................................
Register Call Summary for Register IPIPEIF_LPFR ..............................................................
IPIPEIF_HNUM ........................................................................................................
Register Call Summary for Register IPIPEIF_HNUM .............................................................
IPIPEIF_VNUM .........................................................................................................
Register Call Summary for Register IPIPEIF_VNUM .............................................................
IPIPEIF_ADDRU .......................................................................................................
Register Call Summary for Register IPIPEIF_ADDRU............................................................
IPIPEIF_ADDRL .......................................................................................................
Register Call Summary for Register IPIPEIF_ADDRL ............................................................
IPIPEIF_ADOFS .......................................................................................................
Register Call Summary for Register IPIPEIF_ADOFS ............................................................
IPIPEIF_RSZ ...........................................................................................................
7-1751. ISIF_OBVAL2
List of Tables
2613
2614
2614
2614
2614
2614
2614
2615
2615
2615
2615
2616
2616
2616
2616
2619
2619
2619
2621
2622
2622
2622
2623
2623
2623
2623
2623
2624
2624
2624
2624
2624
2625
2625
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1787. Register Call Summary for Register IPIPEIF_RSZ ................................................................ 2625
7-1788. IPIPEIF_GAIN .......................................................................................................... 2625
7-1789. Register Call Summary for Register IPIPEIF_GAIN............................................................... 2626
7-1790. IPIPEIF_DPCM ......................................................................................................... 2626
7-1791. Register Call Summary for Register IPIPEIF_DPCM ............................................................. 2626
.........................................................................................................
Register Call Summary for Register IPIPEIF_CFG2 ..............................................................
IPIPEIF_INIRSZ ........................................................................................................
Register Call Summary for Register IPIPEIF_INIRSZ ............................................................
IPIPEIF_OCLIP ........................................................................................................
Register Call Summary for Register IPIPEIF_OCLIP .............................................................
IPIPEIF_DTUDF .......................................................................................................
Register Call Summary for Register IPIPEIF_DTUDF ............................................................
IPIPEIF_CLKDIV .......................................................................................................
Register Call Summary for Register IPIPEIF_CLKDIV ...........................................................
IPIPEIF_DPC1 .........................................................................................................
Register Call Summary for Register IPIPEIF_DPC1 ..............................................................
IPIPEIF_DPC2 .........................................................................................................
Register Call Summary for Register IPIPEIF_DPC2 ..............................................................
IPIPEIF_DFSGVL ......................................................................................................
Register Call Summary for Register IPIPEIF_DFSGVL ..........................................................
IPIPEIF_DFSGTH .....................................................................................................
Register Call Summary for Register IPIPEIF_DFSGTH ..........................................................
IPIPEIF_RSZ3A ........................................................................................................
Register Call Summary for Register IPIPEIF_RSZ3A ............................................................
IPIPEIF_INIRSZ3A ....................................................................................................
Register Call Summary for Register IPIPEIF_INIRSZ3A .........................................................
IPIPEIF_CFG3 .........................................................................................................
Register Call Summary for Register IPIPEIF_CFG3 ..............................................................
IPIPEIF_CFG4 .........................................................................................................
Register Call Summary for Register IPIPEIF_CFG4 ..............................................................
IPIPEIF_WDRAF .......................................................................................................
Register Call Summary for Register IPIPEIF_WDRAF ...........................................................
IPIPEIF_WDRBF .......................................................................................................
Register Call Summary for Register IPIPEIF_WDRBF ...........................................................
IPIPEIF_WDRGAIN....................................................................................................
Register Call Summary for Register IPIPEIF_WDRGAIN ........................................................
IPIPEIF_WDRTHR .....................................................................................................
Register Call Summary for Register IPIPEIF_WDRTHR .........................................................
IPIPEIF_RSVD1 ........................................................................................................
Register Call Summary for Register IPIPEIF_RSVD1 ............................................................
IPIPEIF_RSVD2 ........................................................................................................
Register Call Summary for Register IPIPEIF_RSVD2 ............................................................
IPIPEIF_WDRLBK1....................................................................................................
Register Call Summary for Register IPIPEIF_WDRLBK1 ........................................................
IPIPEIF_WDRLBK2....................................................................................................
Register Call Summary for Register IPIPEIF_WDRLBK2 ........................................................
IPIPEIF_WDRSBK1 ...................................................................................................
Register Call Summary for Register IPIPEIF_WDRSBK1 ........................................................
7-1792. IPIPEIF_CFG2
2627
7-1793.
2628
7-1794.
7-1795.
7-1796.
7-1797.
7-1798.
7-1799.
7-1800.
7-1801.
7-1802.
7-1803.
7-1804.
7-1805.
7-1806.
7-1807.
7-1808.
7-1809.
7-1810.
7-1811.
7-1812.
7-1813.
7-1814.
7-1815.
7-1816.
7-1817.
7-1818.
7-1819.
7-1820.
7-1821.
7-1822.
7-1823.
7-1824.
7-1825.
7-1826.
7-1827.
7-1828.
7-1829.
7-1830.
7-1831.
7-1832.
7-1833.
7-1834.
7-1835.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2628
2628
2629
2629
2629
2631
2631
2631
2631
2632
2632
2632
2632
2633
2633
2633
2633
2634
2634
2634
2635
2635
2635
2636
2636
2637
2637
2637
2637
2637
2638
2638
2638
2638
2638
2639
2639
2639
2639
2639
2640
2640
159
www.ti.com
7-1836. IPIPEIF_WDRSBK2 ................................................................................................... 2640
7-1837. Register Call Summary for Register IPIPEIF_WDRSBK2 ........................................................ 2640
7-1838. IPIPEIF_WDRMA ...................................................................................................... 2640
7-1839. Register Call Summary for Register IPIPEIF_WDRMA ........................................................... 2641
7-1840. IPIPEIF_WDRSAT_VP ................................................................................................ 2641
2641
7-1842.
2641
7-1843.
7-1844.
7-1845.
7-1846.
7-1847.
7-1848.
7-1849.
7-1850.
7-1851.
7-1852.
7-1853.
7-1854.
7-1855.
7-1856.
7-1857.
7-1858.
7-1859.
7-1860.
7-1861.
7-1862.
7-1863.
7-1864.
7-1865.
7-1866.
7-1867.
7-1868.
7-1869.
7-1870.
7-1871.
7-1872.
7-1873.
7-1874.
7-1875.
7-1876.
7-1877.
7-1878.
7-1879.
7-1880.
7-1881.
7-1882.
7-1883.
7-1884.
160
....................................................
IPIPEIF_WDRSAT_VP2 ..............................................................................................
Register Call Summary for Register IPIPEIF_WDRSAT_VP2 ...................................................
IPIPEIF_WDRSAT_ISIF ..............................................................................................
Register Call Summary for Register IPIPEIF_WDRSAT_ISIF ...................................................
IPIPEIF_WDRSAT_ISIF2 .............................................................................................
Register Call Summary for Register IPIPEIF_WDRSAT_ISIF2 .................................................
IPIPEIF_WDRSAT_SD ................................................................................................
Register Call Summary for Register IPIPEIF_WDRSAT_SD ....................................................
IPIPEIF_WDRSAT_SD2 ..............................................................................................
Register Call Summary for Register IPIPEIF_WDRSAT_SD2 ...................................................
IPIPEIF_WDRLWB1 ...................................................................................................
Register Call Summary for Register IPIPEIF_WDRLWB1 .......................................................
IPIPEIF_WDRLWB2 ...................................................................................................
Register Call Summary for Register IPIPEIF_WDRLWB2 .......................................................
IPIPEIF_WDRSWB1...................................................................................................
Register Call Summary for Register IPIPEIF_WDRSWB1 .......................................................
IPIPEIF_WDRSWB2...................................................................................................
Register Call Summary for Register IPIPEIF_WDRSWB2 .......................................................
IPIPEIF_VPDCMPXTHR1 ............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPXTHR1 .................................................
IPIPEIF_VPDCMPXTHR2 ............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPXTHR2 .................................................
IPIPEIF_VPDCMPXTHR3 ............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPXTHR3 .................................................
IPIPEIF_VPDCMPYTHR1 ............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPYTHR1 .................................................
IPIPEIF_VPDCMPYTHR2 ............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPYTHR2 .................................................
IPIPEIF_VPDCMPYTHR3 ............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPYTHR3 .................................................
IPIPEIF_VPDCMPSLOPE1...........................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPSLOPE1 ...............................................
IPIPEIF_VPDCMPSLOPE2...........................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPSLOPE2 ...............................................
IPIPEIF_VPDCMPSLOPE3...........................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPSLOPE3 ...............................................
IPIPEIF_VPDCMPSLOPE4...........................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPSLOPE4 ...............................................
IPIPEIF_VPDCMPCFG ...............................................................................................
Register Call Summary for Register IPIPEIF_VPDCMPCFG ....................................................
IPIPEIF_SDDCMPXTHR1 ............................................................................................
Register Call Summary for Register IPIPEIF_SDDCMPXTHR1.................................................
IPIPEIF_SDDCMPXTHR2 ............................................................................................
7-1841. Register Call Summary for Register IPIPEIF_WDRSAT_VP
List of Tables
2642
2642
2642
2642
2643
2643
2643
2643
2644
2644
2644
2644
2645
2645
2645
2645
2646
2646
2646
2646
2647
2647
2647
2647
2647
2648
2648
2648
2648
2648
2649
2649
2649
2649
2649
2650
2650
2650
2650
2651
2651
2651
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
www.ti.com
7-1885. Register Call Summary for Register IPIPEIF_SDDCMPXTHR2................................................. 2651
7-1886. IPIPEIF_SDDCMPXTHR3 ............................................................................................ 2651
7-1887. Register Call Summary for Register IPIPEIF_SDDCMPXTHR3................................................. 2652
7-1888. IPIPEIF_SDDCMPYTHR1 ............................................................................................ 2652
7-1889. Register Call Summary for Register IPIPEIF_SDDCMPYTHR1................................................. 2652
7-1890. IPIPEIF_SDDCMPYTHR2 ............................................................................................ 2652
7-1891. Register Call Summary for Register IPIPEIF_SDDCMPYTHR2................................................. 2652
7-1892. IPIPEIF_SDDCMPYTHR3 ............................................................................................ 2653
7-1893. Register Call Summary for Register IPIPEIF_SDDCMPYTHR3................................................. 2653
7-1894. IPIPEIF_SDDCMPSLOPE1
..........................................................................................
2653
7-1895. Register Call Summary for Register IPIPEIF_SDDCMPSLOPE1 ............................................... 2653
7-1896. IPIPEIF_SDDCMPSLOPE2
..........................................................................................
2653
7-1897. Register Call Summary for Register IPIPEIF_SDDCMPSLOPE2 ............................................... 2654
..........................................................................................
Register Call Summary for Register IPIPEIF_SDDCMPSLOPE3 ...............................................
IPIPEIF_SDDCMPSLOPE4 ..........................................................................................
Register Call Summary for Register IPIPEIF_SDDCMPSLOPE4 ...............................................
IPIPEIF_SDDCMPCFG ...............................................................................................
Register Call Summary for Register IPIPEIF_SDDCMPCFG ....................................................
IPIPEIF_WDRCMPXTHR1 ...........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPXTHR1 ................................................
IPIPEIF_WDRCMPXTHR2 ...........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPXTHR2 ................................................
IPIPEIF_WDRCMPXTHR3 ...........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPXTHR3 ................................................
IPIPEIF_WDRCMPYTHR1 ...........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPYTHR1 ................................................
IPIPEIF_WDRCMPYTHR2 ...........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPYTHR2 ................................................
IPIPEIF_WDRCMPYTHR3 ...........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPYTHR3 ................................................
IPIPEIF_WDRCMPSLOPE1 ..........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPSLOPE1 ..............................................
IPIPEIF_WDRCMPSLOPE2 ..........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPSLOPE2 ..............................................
IPIPEIF_WDRCMPSLOPE3 ..........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPSLOPE3 ..............................................
IPIPEIF_WDRCMPSLOPE4 ..........................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPSLOPE4 ..............................................
IPIPEIF_WDRCMPCFG ..............................................................................................
Register Call Summary for Register IPIPEIF_WDRCMPCFG ...................................................
IPIPEIF_WDRMRGCFG ..............................................................................................
Register Call Summary for Register IPIPEIF_WDRMRGCFG ...................................................
ISS ISP6P5_H3A Registers Mapping Summary ...................................................................
H3A_PID ................................................................................................................
Register Call Summary for Register H3A_PID .....................................................................
H3A_PCR ...............................................................................................................
Register Call Summary for Register H3A_PCR ...................................................................
H3A_AFPAX1 ..........................................................................................................
7-1898. IPIPEIF_SDDCMPSLOPE3
2654
7-1899.
2654
7-1900.
7-1901.
7-1902.
7-1903.
7-1904.
7-1905.
7-1906.
7-1907.
7-1908.
7-1909.
7-1910.
7-1911.
7-1912.
7-1913.
7-1914.
7-1915.
7-1916.
7-1917.
7-1918.
7-1919.
7-1920.
7-1921.
7-1922.
7-1923.
7-1924.
7-1925.
7-1926.
7-1927.
7-1928.
7-1929.
7-1930.
7-1931.
7-1932.
7-1933.
SPRUIC6B – January 2017 – Revised October 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
List of Tables
2654
2654
2655
2655
2655
2655
2656
2656
2656
2656
2656
2657
2657
2657
2657
2657
2658
2658
2658
2658
2658
2659
2659
2659
2659
2660
2660
2660
2660
2661
2661
2662
2663
2663
161
www.ti.com
7-1934. Register Call Summary for Register H3A_AFPAX1 ............................................................... 2663
7-1935. H3A_AFPAX2 .......................................................................................................... 2664
7-1936. Register Call Summary for Register H3A_AFPAX2 ............................................................... 2664
7-1937. H3A_AFPAXSTART ................................................................................................... 2664
7-1938. Register Call Summary for Register H3A_AFPAXSTART
.......................................................
2665
7-1939. H3A_AFIIRSH .......................................................................................................... 2665
7-1940. Register Call Summary for Register H3A_AFIIRSH............................................................... 2665
7-1941. H3A_AFBUFST
........................................................................................................
2665
7-1942. Register Call Summary for Register H3A_AFBUFST ............................................................. 2666
7-1943. H3A_AFCOEF010 ..................................................................................................... 2666
7-1944. Register Call Summary for Register H3A_AFCOEF010 .......................................................... 2666
7-1945. H3A_AFCOEF032 ..................................................................................................... 2666
7-1946. Register Call Summary for Register H3A_AFCOEF032 .......................................................... 2667
7-1947. H3A_AFCOEF054 ..................................................................................................... 2667
7-1948. Register Call Summary for Register H3A_AFCOEF054 .......................................................... 2667
7-1949. H3A_AFCOEF076 ..................................................................................................... 2667
7-1950. Register Call Summary for Register H3A_AFCOEF076 .......................................................... 2668
7-1951. H3A_AFCOEF098 ..................................................................................................... 2668
7-1952. Register Call Summary for Register H3A_AFCOEF098 .......................................................... 2668
7-1953. H3A_AFCOEF0010 .................................................................................................... 2668
7-1954. Register Call Summary for Register H3A_AFCOEF0010 ........................................................ 2668
7-1955. H3A_AFCOEF110 ..................................................................................................... 2669
7-1956. Register Call Summary for Regist