Texas Instruments | Powering the AM335x, AM437x, and AM438x with TPS65218 (Rev. A) | User Guides | Texas Instruments Powering the AM335x, AM437x, and AM438x with TPS65218 (Rev. A) User guides

Texas Instruments Powering the AM335x, AM437x, and AM438x with TPS65218 (Rev. A) User guides
User's Guide
SLVUAA9A – August 2014 – Revised August 2017
Powering the AM335x, AM437x, and AM438x With
TPS65218
This user's guide is a reference for connectivity between the TPS65218 power management IC (PMIC)
and the AM335x, AM437x, or AM438x processor. For detailed information about the TPS65218, AM335x,
AM437x, or AM438x, see their respective data sheets.
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Contents
TPS65218 Overview ........................................................................................................ 1
Connection Diagram for TPS65218 and AM335x ....................................................................... 2
Power Rails for TPS65218 and AM335x ................................................................................. 3
Connection Diagram for TPS65218 and AM437x ....................................................................... 4
Power Rails Connections for TPS65218 and AM437x ................................................................. 5
Connection Diagram for TPS65218 and AM438x ....................................................................... 6
Power Rails Connections for TPS65218 and AM438x ................................................................. 7
Power-Up and Power-Down Sequence for TPS65218 ................................................................. 8
Memory Voltage Selection .................................................................................................. 9
Using LPDDR2 Memory ................................................................................................... 10
Warm Reset ................................................................................................................. 12
Pullup Resistors ............................................................................................................ 12
List of Figures
1
Connection Diagram for TPS65218 and AM335x ....................................................................... 2
2
Connection Diagram for TPS65218 and AM437x ....................................................................... 4
3
Connection Diagram for TPS65218 and AM438x ....................................................................... 6
4
TPS65218 Sequence Timing Diagram.................................................................................... 8
5
Connection Diagram for TPS65218, AM437x, and LPDDR2 Memory .............................................. 10
6
Connection Diagram for TPS65218, AM438x, and LPDDR2 Memory .............................................. 11
7
Warm Reset Functionality ................................................................................................. 12
List of Tables
1
Power Rails for TPS65218 and AM335x ................................................................................. 3
2
Power Rails for TPS65218 and AM437x ................................................................................. 5
3
Power Rails for TPS65218 and AM438x ................................................................................. 7
4
TPS65218 Power-Up Sequence ........................................................................................... 8
5
DCDC3 Voltage Selection .................................................................................................. 9
Trademarks
All trademarks are the property of their respective owners.
1
TPS65218 Overview
The TPS65218 is an optimized and highly integrated power management solution for the AM335x,
AM437x, and AM438x processor. Features of the TPS65218 include:
• Three DC-DC step-down converters
• One LDO
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1
Connection Diagram for TPS65218 and AM335x
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Three load switches
Two micro-power DC-DC step-down converters
Power path management for battery backup of the processor RTC
Integrated voltage supervisor
Connection Diagram for TPS65218 and AM335x
The block diagram shown in Figure 1 shows the connections between the TPS65218 and the AM335x.
Power rails and digital and analog signals are shown. The power rails may be used to power additional
parts of the system.
VDDSHVx
DCDC6 for GPIOx VDDSHV3
System
System
Power (5.5 V) Power (5.5 V)
Push Button
nWAKEUP
RTC_WAKEUP
PB
nINT
GPIOx
PGOOD
Digital
PWRONRSTn
PWR_EN
RTC_PMIC_EN
SCL/SDA
AC_DET
I2C0_SCL/SDA
GPIO3
WARMRSTn
PGOOD_BU
10
Coin
Cell
CC
+
±
IN_BU
Battery Backup
Supplies
DCDC5
DCDC6
RTC_PWRONRSTn
IN_nCC
1.0V
CAP_VDD_RTC
1.8V
IN_LDO1
LDO1
2.7-V to 5.5-V
system power
VDDS_RTC
1.8V
1.8V Analog and I/O
AM335x
IN_DCDC1
DCDC1 (buck)
IN_DCDC2
DCDC2 (buck)
IN_DCDC3
DCDC3 (buck)
IN_DCDC4
DCDC4 (buck-boost)
0.95/1.1V
VDD_CORE
0.95/1.1/1.2/1.26/1.325V
VDD_MPU
1.35/1.5V
3.3V
3.3V Analog and I/O
IN_BIAS
BIAS
DDR_RESETn
From
DCDC3
LS1
IN_LS1
LS1
VDDS_DDR
TPS65218
DDR3/L Memory
Copyright © 2017, Texas Instruments Incorporated
Figure 1. Connection Diagram for TPS65218 and AM335x
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Power Rails for TPS65218 and AM335x
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3
Power Rails for TPS65218 and AM335x
Table 1 matches the AM335x power terminals with the appropriate power rail from the TPS65218.
Table 1. Power Rails for TPS65218 and AM335x
TPS65218
Voltage (V)
AM335x
DCDC1
0.95/1.1
VDD_CORE
DCDC2
0.95/1.1/1.2/1.26/1.325
VDD_MPU
DCDC3
1.35/1.5
DDR3L/DDR3
Memory
VDDS_DDR
DCDC4
3.3
DCDC5
1.0
CAP_VDD_RTC
DCDC6
1.8
VDDS_RTC
VDDSHVx (3.3 V)
VDDA3P3V_USB0/1
VDDS
VDDSHVx (1.8 V)
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
LDO1
1.8
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_OSC
VDDA1P8V_USB0/1
VDDA_ADC
DCDC3 voltage is initially selected through the choice of resistor on the DC34_SEL pin. Each output
voltage can be changed dynamically while the TPS65218 is in active mode. This requires the use of I2C
commands to the TPS65218.
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Connection Diagram for TPS65218 and AM437x
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Connection Diagram for TPS65218 and AM437x
The block diagram shown in Figure 2 shows the connections between the TPS65218 and AM437x. Power
rails and digital and analog signals are shown. The power rails may be used to power additional parts of
the system.
VDDSHVx
DCDC6 for GPIOx VDDSHV3
System
System
Power (5.5 V) Power (5.5 V)
Push Button
nWAKEUP
RTC_WAKEUP
PB
nINT
GPIOx
PGOOD
Digital
PWRONRSTn
PWR_EN
RTC_PMIC_EN
SCL/SDA
AC_DET
I2C0_SCL/SDA
GPIO3
PGOOD_BU
10
Coin
Cell
CC
+
±
IN_BU
Battery Backup
Supplies
DCDC5
DCDC6
RTC_PWRONRSTn
IN_nCC
1.0V (DCDC5)
CAP_VDD_RTC
1.8V (DCDC6)
IN_LDO1
LDO1
2.7-V to 5.5-V
system power
VDDS_RTC
1.8V
1.8V Analog and I/O
AM437x
IN_DCDC1
DCDC1 (buck)
IN_DCDC2
DCDC2 (buck)
IN_DCDC3
DCDC3 (buck)
IN_DCDC4
DCDC4 (buck-boost)
0.95/1.1V
VDD_CORE
0.95/1.1/1.2/1.26/1.325V
VDD_MPU
1.35/1.5V
3.3V
3.3V Analog and I/O
IN_BIAS
BIAS
DDR_RESETn
From
DCDC3
LS1
IN_LS1
LS1
VDDS_DDR
TPS65218
DDR3/L Memory
Copyright © 2017, Texas Instruments Incorporated
Figure 2. Connection Diagram for TPS65218 and AM437x
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Power Rails Connections for TPS65218 and AM437x
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5
Power Rails Connections for TPS65218 and AM437x
Table 2 matches the AM437x power terminals with the appropriate power rail from the TPS65218.
Table 2. Power Rails for TPS65218 and AM437x
TPS65218
Voltage (V)
AM437x
DCDC1
0.95/1.1
VDD_CORE
DCDC2
0.95/1.1/1.2/1.26/1.325
VDD_MPU
DCDC3
1.2/1.35/1.5
LPDDR2/DDR3L/DDR3 Memory
VDDSHVx(3.3 V)
DCDC4
3.3
VDDA3P3V_USB0/1
DCDC5
1.0
CAP_VDD_RTC
DCDC6
1.8
VDDS_RTC
VDDS3P3V_IOLDO
VDDS
VDDSHVx(1.8 V)
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
LDO1
1.8
VDDS_PLL_CORE_LCD
VDDS_OSC
VDDA1P8V_USB0/1
VDDA_ADC0/1
VDDS_PLL_MPU
VDDS_CLKOUT
LS1
1.2/1.35/1.5 (Tied to DCDC3)
VDDS_DDR
DCDC3 voltage is initially selected through the choice of resistor on the DC34_SEL pin. Each output
voltage can be changed dynamically while the TPS65218 is in active mode. This requires use of I2C
commands to the TPS65218.
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Connection Diagram for TPS65218 and AM438x
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Connection Diagram for TPS65218 and AM438x
The block diagram shown in Figure 3 shows the connections between the TPS65218 and AM438x. Power
rails and digital and analog signals are shown. The power rails may be used to power additional parts of
the system.
VDDSHVx
DCDC6 for GPIOx VDDSHV3
System
System
Power (5.5 V) Power (5.5 V)
Push Button
nWAKEUP
TPM_WAKEUP
PB
nINT
NMin
PGOOD
Digital
PORZn
PWR_EN
TPM_PMIC_EN
SCL/SDA
AC_DET
I2C0_SCL/SDA
GPIO3
PGOOD_BU
10
Coin
Cell
CC
+
±
IN_BU
Battery Backup
Supplies
DCDC5
DCDC6
PMU_PORZn
IN_nCC
PMU_HIBZ
1.0V (DCDC5)
VDD_TPM
1.8V (DCDC6)
IN_LDO1
LDO1
2.7-V to 5.5-V
system power
VDDS_TPM
1.8V
1.8V Analog and I/O
AM438x
IN_DCDC1
DCDC1 (buck)
IN_DCDC2
DCDC2 (buck)
IN_DCDC3
DCDC3 (buck)
IN_DCDC4
DCDC4 (buck-boost)
0.95/1.1V
VDD_CORE
0.95/1.1/1.2/1.26/1.325V
VDD_MPU
1.35/1.5V
3.3V
3.3V Analog and I/O
IN_BIAS
Reference System
DDR_RESETn
From
DCDC3
IN_LS1
LS1
LS1
VDDS_DDR
TPS65218D0
DDR3/L Memory
Copyright © 2017, Texas Instruments Incorporated
Figure 3. Connection Diagram for TPS65218 and AM438x
6
Powering the AM335x, AM437x, and AM438x With TPS65218
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Power Rails Connections for TPS65218 and AM438x
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7
Power Rails Connections for TPS65218 and AM438x
Table 3 matches the AM438x power terminals with the appropriate power rail from the TPS65218.
Table 3. Power Rails for TPS65218 and AM438x
TPS65218D0
Voltage (V)
AM438x
DCDC1
0.95/1.1
VDD_CORE
DCDC2
0.95/1.1/1.2/1.26/1.325
VDD_MPU
DCDC3
1.2/1.35/1.5
LPDDR2/DDR3L/DDR3 Memory
VDDSHVx(3.3V)
DCDC4
3.3
VDDA3P3V_USB0/1
DCDC5
1.0
VDD_TPM
DCDC6
1.8
VDDS_TPM
VDDS3P3V_IOLDO
VDDS
VDDSHVx(1.8V)
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
LDO1
1.8
VDDS_PLL_CORE_LCD
VDDS_OSC
VDDA_1P8V_USB0/1
VDDA_ADC0/1
VDDS_PLL_MPU
VDDS_CLKOUT
LS1
1.2/1.35/1.5 (Tied to DCDC3)
VDDS_DDR
DCDC3 voltage is initially selected through the choice of resistor on the DC34_SEL pin. Each output
voltage can be changed dynamically while the TPS65218 is in active mode. This requires use of I2C
commands to the TPS65218.
NOTE: The TPS65218D0 device should be used for AM438x processor.
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Power-Up and Power-Down Sequence for TPS65218
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Power-Up and Power-Down Sequence for TPS65218
Figure 4 describes the power-up and power-down sequence of the TPS65218. This sequence is
specifically optimized for the AM335x, AM437x, and AM438x processor.
Software power-down command
VSYS
5 s maximum
PB
nWAKEUP
PWR_EN
(deglitched)
DCDC6
DCDC5
LDO1
DCDC5 and DCDC6 remain up if FSEAL = 1
2 ms
2 ms
GPIO1
DCDC3
LS1
DCDC4
40 ms
4 ms
20 ms
2 ms
20 ms
2 ms
20 ms
2 ms
DCDC1
20 ms
2 ms
DCDC2
PGOOD
20 ms
Figure 4. TPS65218 Sequence Timing Diagram
The power-up sequence is defined by a series of ten strobes and nine delay times. Each output rail is
assigned to a strobe to determine the order in which the rails are enabled. The delay time in-between
strobes is 2 ms by default. Table 4 lists the default strobe assignments for TPS65218.
Table 4. TPS65218 Power-Up Sequence
Strobe 1
DCDC6
Strobe 2
DCDC5
LDO1
Strobe 3
GPIO1
Strobe 4
Strobe 5
DCDC3
Strobe 6
Strobe 7
DCDC4
Strobe 8
DCDC1
Strobe 9
DCDC2
Strobe 10
8
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Memory Voltage Selection
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Memory Voltage Selection
DCDC3 can be configured to support a variety of DDR memory voltages. The desired voltage can be
selected by placing a 1% resistor to ground on the DC34_SEL pin. Table 5 lists the available memory
voltages and the needed resistor for each.
Table 5. DCDC3 Voltage Selection
Memory
DCDC3 Voltage (V)
Resistor (kΩ)
LPDDR2
1.2
0 (tie to ground)
DDR3L
1.35
12.1
DDR3
1.5
20
DDR2
1.8
31.6
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Using LPDDR2 Memory
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Using LPDDR2 Memory
If LPDDR2 memory is used, an additional 1.8 V LDO is required. GPIO1 is programmed to properly
sequence the additional LDO and should be tied to the LDO enable pin as seen in Figure 5.
VDD_18 VDDSHVx
(BBD) for GPIOx VDDSHV3
System
Power (5.5 V)
nWAKEUP
RTC_WAKEUP
PB
nINT
GPIOx
PGOOD
PWRONRSTn
Digital
PWR_EN
RTC_PMIC_EN
SCL/SDA
I2C0_SCL/SDA
PGOOD_BU
RTC_PWRONRSTn
10
Coin
Cell
IN_nCC
CC
+
±
Battery Backup
Supplies
VDD_10
IN_BU
CAP_VDD_RTC
VDD_18
VDDS_RTC
IN_DCDC3
1.2V
DCDC3 (buck)
AM437x
IN_BIAS
2.7-V to 5.5-V
system power
INT_LDO
BIAS
From
DCDC3
IN_LS1
100 nF
LS1
LS1
VDDS_DDR
External Memory IF (EMIF)
INT_LDO
TPS65218D0
GPIO1
OD
GPIO1
LPDDR2 Memory
ENABLE
LDO
1.8V
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Connection Diagram for TPS65218, AM437x, and LPDDR2 Memory
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Using LPDDR2 Memory
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VDDSHVx
DCDC6 for GPIOx VDDSHV3
System
Power (5.5 V)
nWAKEUP
TPM_WAKEUP
PB
nINT
NMIn
PGOOD
PORZn
Digital
PWR_EN
TPM_PMIC_EN
SCL/SDA
I2C0_SCL/SDA
PGOOD_BU
PMU_PORZn
10
IN_nCC
CC
PMU_HIBZ
Coin
Cell
+
±
Battery Backup
Supplies
1.0V (DCDC5)
IN_BU
VDD_TPM
1.8V (DCDC6)
VDDS_TPM
IN_DCDC3
1.2V
DCDC3 (buck)
AM438x
IN_BIAS
2.7-V to 5.5-V
system power
INT_LDO
BIAS
From
DCDC3
IN_LS1
1 …F
LS1
LS1
VDDS_DDR
External Memory IF (EMIF)
INT_LDO
TPS65218D0
GPIO1
OD
GPIO1
LPDDR2 Memory
ENABLE
LDO
1.8V
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Figure 6. Connection Diagram for TPS65218, AM438x, and LPDDR2 Memory
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Warm Reset
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Warm Reset
The TPS65218 supports warm reset functionality with the AM335x processor. This functionality is enabled
on the TPS65218 by default, and can be disabled through I2C. When enabled, GPIO3 acts as the warm
reset input to the PMIC. Asserting GPIO3 low causes DCDC1 and DCDC2 to slew back to their default
value of 1.1 V.
Digital
GPIO3
WARMRSTn
Reset
Deglitch
2.7-V to 5.5-V
system power
IN_DCDC1
DCDC1 (Buck)
VDD_CORE
DCDC2 (Buck)
VDD_MPU
IN_DCDC2
TPS65218
AM335x
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Warm Reset Functionality
12
Pullup Resistors
There are several pullup resistors needed for operating the TPS65218 with the AM335x, AM437x, or
AM438x processor. PB should be pulled up to VSYS. nWakeup should be pulled to DCDC6 so that the
pullup source is present even during SUSPEND and OFF mode. A 100-kΩ pullup resistor should be used
for nWakeup to minimize the current load on DCDC6. nINT, PGOOD, SCL, and SDA should be pulled up
to the same supply that powers VDDSHVx for each signal. SCL and SDA use lower value pullups
resistors in order to decrease rise time of these nodes during I2C communication.
12
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2014) to A Revision ..................................................................................................... Page
•
Added the TPS65218D0 and AM438x connection.................................................................................... 6
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Revision History
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