Texas Instruments | TMS320C6745/C6747 DSP (Rev. D) | User Guides | Texas Instruments TMS320C6745/C6747 DSP (Rev. D) User guides

Texas Instruments TMS320C6745/C6747 DSP (Rev. D) User guides
TMS320C6745/C6747 DSP
Technical Reference Manual
Literature Number: SPRUH91D
March 2013 – Revised September 2016
Contents
Preface....................................................................................................................................... 64
1
Overview ........................................................................................................................... 65
1.1
2
DSP Subsystem ................................................................................................................. 68
2.1
2.2
2.3
2.4
3
Introduction .................................................................................................................. 77
System Interconnect Block Diagram ..................................................................................... 78
Introduction .................................................................................................................. 80
DSP Memories.............................................................................................................. 80
Peripherals .................................................................................................................. 81
Memory Protection Unit (MPU) ............................................................................................. 82
5.1
5.2
5.3
2
69
70
70
70
74
74
74
75
System Memory ................................................................................................................. 79
4.1
4.2
4.3
5
Introduction ..................................................................................................................
TMS320C674x Megamodule .............................................................................................
2.2.1 Internal Memory Controllers .....................................................................................
2.2.2 Internal Peripherals ...............................................................................................
Memory Map ................................................................................................................
2.3.1 DSP Internal Memory .............................................................................................
2.3.2 External Memory ..................................................................................................
Advanced Event Triggering (AET) .......................................................................................
System Interconnect ........................................................................................................... 76
3.1
3.2
4
Introduction .................................................................................................................. 66
Introduction ..................................................................................................................
5.1.1 Purpose of the MPU ..............................................................................................
5.1.2 Features ............................................................................................................
5.1.3 Block Diagram .....................................................................................................
5.1.4 MPU Default Configuration.......................................................................................
Architecture .................................................................................................................
5.2.1 Privilege Levels ....................................................................................................
5.2.2 Memory Protection Ranges ......................................................................................
5.2.3 Permission Structures ............................................................................................
5.2.4 Protection Check ..................................................................................................
5.2.5 DSP L1/L2 Cache Controller Accesses ........................................................................
5.2.6 MPU Register Protection .........................................................................................
5.2.7 Invalid Accesses and Exceptions ...............................................................................
5.2.8 Reset Considerations .............................................................................................
5.2.9 Interrupt Support ..................................................................................................
5.2.10 Emulation Considerations .......................................................................................
MPU Registers..............................................................................................................
5.3.1 Revision Identification Register (REVID) .......................................................................
5.3.2 Configuration Register (CONFIG) ...............................................................................
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ..............................................................
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ...........................................................
5.3.5 Interrupt Enable Set Register (IENSET) .......................................................................
5.3.6 Interrupt Enable Clear Register (IENCLR) .....................................................................
5.3.7 Fixed Range Start Address Register (FXD_MPSAR) ........................................................
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5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
6
Device Clocking................................................................................................................ 103
6.1
6.2
6.3
7
Overview ...................................................................................................................
Frequency Flexibility ......................................................................................................
Peripheral Clocking .......................................................................................................
6.3.1 USB Clocking.....................................................................................................
6.3.2 EMIFB Clocking ..................................................................................................
6.3.3 EMIFA Clocking ..................................................................................................
6.3.4 EMAC Clocking ..................................................................................................
6.3.5 I/O Domains ......................................................................................................
104
105
107
107
109
111
112
114
Phase-Locked Loop Controller (PLLC) ................................................................................ 115
7.1
7.2
7.3
7.4
8
Fixed Range End Address Register (FXD_MPEAR) ......................................................... 95
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ................................. 96
Programmable Range n Start Address Registers (PROGn_MPSAR) .................................... 97
Programmable Range n End Address Registers (PROGn_MPEAR) ..................................... 98
Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) .............. 99
Fault Address Register (FLTADDRR) ........................................................................ 100
Fault Status Register (FLTSTAT)............................................................................. 101
Fault Clear Register (FLTCLR) ............................................................................... 102
Introduction ................................................................................................................
PLL0 Control ..............................................................................................................
7.2.1 Device Clock Generation .......................................................................................
7.2.2 Steps for Changing PLL0 Domain Frequency ...............................................................
Locking/Unlocking PLL Register Access ..............................................................................
PLLC Registers ...........................................................................................................
7.4.1 Revision Identification Register (REVID) .....................................................................
7.4.2 Reset Type Status Register (RSTYPE) .......................................................................
7.4.3 PLL Control Register (PLLCTL) ................................................................................
7.4.4 OBSCLK Select Register (OCSEL) ...........................................................................
7.4.5 PLL Multiplier Control Register (PLLM) .......................................................................
7.4.6 PLL Pre-Divider Control Register (PREDIV) .................................................................
7.4.7 PLL Controller Divider 1 Register (PLLDIV1) ................................................................
7.4.8 PLL Controller Divider 2 Register (PLLDIV2) ................................................................
7.4.9 PLL Controller Divider 3 Register (PLLDIV3) ................................................................
7.4.10 PLL Controller Divider 4 Register (PLLDIV4) ...............................................................
7.4.11 PLL Controller Divider 5 Register (PLLDIV5) ...............................................................
7.4.12 PLL Controller Divider 6 Register (PLLDIV6) ...............................................................
7.4.13 PLL Controller Divider 7 Register (PLLDIV7) ...............................................................
7.4.14 Oscillator Divider 1 Register (OSCDIV) ......................................................................
7.4.15 PLL Post-Divider Control Register (POSTDIV) .............................................................
7.4.16 PLL Controller Command Register (PLLCMD) .............................................................
7.4.17 PLL Controller Status Register (PLLSTAT) .................................................................
7.4.18 PLL Controller Clock Align Control Register (ALNCTL) ...................................................
7.4.19 PLLDIV Ratio Change Status Register (DCHANGE) ......................................................
7.4.20 Clock Enable Control Register (CKEN) ......................................................................
7.4.21 Clock Status Register (CKSTAT) .............................................................................
7.4.22 SYSCLK Status Register (SYSTAT) .........................................................................
7.4.23 Emulation Performance Counter 0 Register (EMUCNT0) .................................................
7.4.24 Emulation Performance Counter 1 Register (EMUCNT1) .................................................
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124
125
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127
127
128
128
129
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132
133
134
135
136
137
138
138
Power and Sleep Controller (PSC) ...................................................................................... 139
8.1
8.2
Introduction ................................................................................................................
Power Domain and Module Topology ..................................................................................
8.2.1 Power Domain States ...........................................................................................
8.2.2 Module States ....................................................................................................
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8.3
8.4
8.5
8.6
9
9.6
9.7
9.8
Introduction ................................................................................................................
Power Consumption Overview ..........................................................................................
PSC and PLLC Overview ................................................................................................
Features ....................................................................................................................
Clock Management .......................................................................................................
9.5.1 Module Clock ON/OFF ..........................................................................................
9.5.2 Module Clock Frequency Scaling ..............................................................................
9.5.3 PLL Bypass and Power Down .................................................................................
DSP Sleep Mode Management .........................................................................................
9.6.1 C674x DSP CPU Sleep Mode .................................................................................
9.6.2 C674x Megamodule Sleep Mode ..............................................................................
RTC-Only Mode ...........................................................................................................
Additional Peripheral Power Management Considerations..........................................................
9.8.1 USB PHY Power Down Control ...............................................................................
9.8.2 EMIFB Memory Clock Gating ..................................................................................
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166
167
167
167
167
168
168
168
168
169
169
169
System Configuration (SYSCFG) Module ............................................................................. 170
10.1
10.2
10.3
10.4
4
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144
144
145
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145
146
147
148
149
149
150
150
151
151
152
152
153
154
155
156
157
158
159
160
161
162
163
Power Management........................................................................................................... 164
9.1
9.2
9.3
9.4
9.5
10
Executing State Transitions .............................................................................................
8.3.1 Power Domain State Transitions ..............................................................................
8.3.2 Module State Transitions .......................................................................................
IcePick Emulation Support in the PSC .................................................................................
PSC Interrupts.............................................................................................................
8.5.1 Interrupt Events ..................................................................................................
8.5.2 Interrupt Registers ...............................................................................................
8.5.3 Interrupt Handling ................................................................................................
PSC Registers.............................................................................................................
8.6.1 Revision Identification Register (REVID) .....................................................................
8.6.2 Interrupt Evaluation Register (INTEVAL) .....................................................................
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ...................................
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ...................................
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ......................................
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ......................................
8.6.7 Power Error Pending Register (PERRPR) ...................................................................
8.6.8 Power Error Clear Register (PERRCR) .......................................................................
8.6.9 Power Domain Transition Command Register (PTCMD)...................................................
8.6.10 Power Domain Transition Status Register (PTSTAT)......................................................
8.6.11 Power Domain 0 Status Register (PDSTAT0) ..............................................................
8.6.12 Power Domain 1 Status Register (PDSTAT1) ..............................................................
8.6.13 Power Domain 0 Control Register (PDCTL0) ...............................................................
8.6.14 Power Domain 1 Control Register (PDCTL1) ...............................................................
8.6.15 Power Domain 0 Configuration Register (PDCFG0) .......................................................
8.6.16 Power Domain 1 Configuration Register (PDCFG1) .......................................................
8.6.17 Module Status n Register (MDSTATn).......................................................................
8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................
8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................
Introduction ................................................................................................................
Protection ..................................................................................................................
10.2.1 Requirements to Access SYSCFG Registers ...............................................................
Master Priority Control ...................................................................................................
Interrupt Support ..........................................................................................................
10.4.1 Interrupt Events and Requests................................................................................
10.4.2 Interrupt Multiplexing ...........................................................................................
10.4.3 Host-DSP Communication Interrupts ........................................................................
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10.5
11
SYSCFG Registers .......................................................................................................
10.5.1 Revision Identification Register (REVID) ....................................................................
10.5.2 Device Identification Register 0 (DEVIDR0).................................................................
10.5.3 Boot Configuration Register (BOOTCFG) ...................................................................
10.5.4 Silicon Revision Identification Register (CHIPREVID) .....................................................
10.5.5 Kick Registers (KICK0R-KICK1R) ............................................................................
10.5.6 Host 1 Configuration Register (HOST1CFG) ...............................................................
10.5.7 Interrupt Registers ..............................................................................................
10.5.8 Fault Registers ..................................................................................................
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2) ............................................................
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) .............................................
10.5.11 Suspend Source Register (SUSPSRC) ....................................................................
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) ..............................................................
10.5.14 Chip Configuration 0 Register (CFGCHIP0) ...............................................................
10.5.15 Chip Configuration 1 Register (CFGCHIP1) ...............................................................
10.5.16 Chip Configuration 2 Register (CFGCHIP2) ...............................................................
10.5.17 Chip Configuration 3 Register (CFGCHIP3) ...............................................................
10.5.18 Chip Configuration 4 Register (CFGCHIP4) ...............................................................
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177
177
178
178
179
180
181
184
186
189
226
228
229
230
231
235
237
238
Boot Considerations ......................................................................................................... 239
11.1
Introduction ................................................................................................................ 240
12
Programmable Real-Time Unit Subsystem (PRUSS) .............................................................. 241
13
Enhanced Capture (eCAP) Module ...................................................................................... 243
13.1
13.2
13.3
13.4
14
Introduction ................................................................................................................
13.1.1 Purpose of the Peripheral .....................................................................................
13.1.2 Features..........................................................................................................
Architecture ................................................................................................................
13.2.1 Capture and APWM Operating Mode ........................................................................
13.2.2 Capture Mode Description .....................................................................................
Applications ...............................................................................................................
13.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example .........................................
13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ...........................
13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example .......................................
13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example .........................
13.3.5 Application of the APWM Mode ..............................................................................
Registers ...................................................................................................................
13.4.1 Time-Stamp Counter Register (TSCTR) .....................................................................
13.4.2 Counter Phase Control Register (CTRPHS) ................................................................
13.4.3 Capture 1 Register (CAP1) ....................................................................................
13.4.4 Capture 2 Register (CAP2) ....................................................................................
13.4.5 Capture 3 Register (CAP3) ....................................................................................
13.4.6 Capture 4 Register (CAP4) ....................................................................................
13.4.7 ECAP Control Register 1 (ECCTL1) .........................................................................
13.4.8 ECAP Control Register 2 (ECCTL2) .........................................................................
13.4.9 ECAP Interrupt Enable Register (ECEINT) .................................................................
13.4.10 ECAP Interrupt Flag Register (ECFLG) ....................................................................
13.4.11 ECAP Interrupt Clear Register (ECCLR) ...................................................................
13.4.12 ECAP Interrupt Forcing Register (ECFRC) ................................................................
13.4.13 Revision ID Register (REVID) ...............................................................................
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244
244
245
246
247
254
255
257
259
261
263
270
270
271
271
272
272
273
273
275
276
278
279
280
281
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 282
14.1
Introduction ................................................................................................................ 283
14.1.1 Introduction ...................................................................................................... 283
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14.2
14.3
14.4
15
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287
288
288
291
292
301
306
324
328
332
336
340
347
347
348
349
352
355
358
362
363
368
371
371
375
378
382
385
386
390
393
Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 396
15.1
15.2
15.3
6
14.1.2 Submodule Overview ..........................................................................................
14.1.3 Register Mapping ...............................................................................................
Architecture ................................................................................................................
14.2.1 Overview .........................................................................................................
14.2.2 Proper Interrupt Initialization Procedure .....................................................................
14.2.3 Time-Base (TB) Submodule ...................................................................................
14.2.4 Counter-Compare (CC) Submodule ..........................................................................
14.2.5 Action-Qualifier (AQ) Submodule .............................................................................
14.2.6 Dead-Band Generator (DB) Submodule .....................................................................
14.2.7 PWM-Chopper (PC) Submodule..............................................................................
14.2.8 Trip-Zone (TZ) Submodule ....................................................................................
14.2.9 Event-Trigger (ET) Submodule ...............................................................................
14.2.10 High-Resolution PWM (HRPWM) Submodule.............................................................
Applications to Power Topologies ......................................................................................
14.3.1 Overview of Multiple Modules ................................................................................
14.3.2 Key Configuration Capabilities ................................................................................
14.3.3 Controlling Multiple Buck Converters With Independent Frequencies ...................................
14.3.4 Controlling Multiple Buck Converters With Same Frequencies ...........................................
14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ......................................................
14.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................
14.3.7 Practical Applications Using Phase Control Between PWM Modules ...................................
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ......................................................
14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter......................................
Registers ...................................................................................................................
14.4.1 Time-Base Submodule Registers ............................................................................
14.4.2 Counter-Compare Submodule Registers ....................................................................
14.4.3 Action-Qualifier Submodule Registers .......................................................................
14.4.4 Dead-Band Generator Submodule Registers ...............................................................
14.4.5 PWM-Chopper Submodule Register .........................................................................
14.4.6 Trip-Zone Submodule Registers ..............................................................................
14.4.7 Event-Trigger Submodule Registers .........................................................................
14.4.8 High-Resolution PWM Submodule Registers ...............................................................
Introduction ................................................................................................................
Architecture ................................................................................................................
15.2.1 EQEP Inputs.....................................................................................................
15.2.2 Functional Description .........................................................................................
15.2.3 Quadrature Decoder Unit (QDU) .............................................................................
15.2.4 Position Counter and Control Unit (PCCU)..................................................................
15.2.5 eQEP Edge Capture Unit ......................................................................................
15.2.6 eQEP Watchdog ................................................................................................
15.2.7 Unit Timer Base .................................................................................................
15.2.8 eQEP Interrupt Structure ......................................................................................
eQEP Registers ...........................................................................................................
15.3.1 eQEP Position Counter Register (QPOSCNT) .............................................................
15.3.2 eQEP Position Counter Initialization Register (QPOSINIT) ...............................................
15.3.3 eQEP Maximum Position Count Register (QPOSMAX) ...................................................
15.3.4 eQEP Position-Compare Register (QPOSCMP) ...........................................................
15.3.5 eQEP Index Position Latch Register (QPOSILAT) .........................................................
15.3.6 eQEP Strobe Position Latch Register (QPOSSLAT) ......................................................
15.3.7 eQEP Position Counter Latch Register (QPOSLAT).......................................................
15.3.8 eQEP Unit Timer Register (QUTMR) ........................................................................
15.3.9 eQEP Unit Period Register (QUPRD)........................................................................
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15.3.10
15.3.11
15.3.12
15.3.13
15.3.14
15.3.15
15.3.16
15.3.17
15.3.18
15.3.19
15.3.20
15.3.21
15.3.22
15.3.23
15.3.24
15.3.25
16
eQEP Watchdog Timer Register (QWDTMR) .............................................................
eQEP Watchdog Period Register (QWDPRD) ............................................................
QEP Decoder Control Register (QDECCTL) ..............................................................
eQEP Control Register (QEPCTL) .........................................................................
eQEP Capture Control Register (QCAPCTL) .............................................................
eQEP Position-Compare Control Register (QPOSCTL) .................................................
eQEP Interrupt Enable Register (QEINT) ..................................................................
eQEP Interrupt Flag Register (QFLG) ......................................................................
eQEP Interrupt Clear Register (QCLR) ....................................................................
eQEP Interrupt Force Register (QFRC) ....................................................................
eQEP Status Register (QEPSTS) ...........................................................................
eQEP Capture Timer Register (QCTMR) ..................................................................
eQEP Capture Period Register (QCPRD) .................................................................
eQEP Capture Timer Latch Register (QCTMRLAT) ......................................................
eQEP Capture Period Latch Register (QCPRDLAT) .....................................................
eQEP Revision ID Register (REVID) .......................................................................
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422
423
423
426
427
428
429
430
432
433
434
434
434
435
435
Enhanced Direct Memory Access (EDMA3) Controller ........................................................... 436
16.1
16.2
16.3
16.4
16.5
Introduction ................................................................................................................
16.1.1 Overview .........................................................................................................
16.1.2 Features..........................................................................................................
16.1.3 Functional Block Diagram .....................................................................................
16.1.4 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
16.2.1 Functional Overview ............................................................................................
16.2.2 Types of EDMA3 Transfers ...................................................................................
16.2.3 Parameter RAM (PaRAM) .....................................................................................
16.2.4 Initiating a DMA Transfer ......................................................................................
16.2.5 Completion of a DMA Transfer................................................................................
16.2.6 Event, Channel, and PaRAM Mapping ......................................................................
16.2.7 EDMA3 Channel Controller Regions .........................................................................
16.2.8 Chaining EDMA3 Channels ...................................................................................
16.2.9 EDMA3 Interrupts ...............................................................................................
16.2.10 Event Queue(s) ................................................................................................
16.2.11 EDMA3 Transfer Controller (EDMA3TC)...................................................................
16.2.12 Event Dataflow ................................................................................................
16.2.13 EDMA3 Prioritization ..........................................................................................
16.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................
16.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................
16.2.16 Reset Considerations .........................................................................................
16.2.17 Power Management ..........................................................................................
16.2.18 Emulation Considerations ....................................................................................
Transfer Examples........................................................................................................
16.3.1 Block Move Example ...........................................................................................
16.3.2 Subframe Extraction Example ................................................................................
16.3.3 Data Sorting Example ..........................................................................................
16.3.4 Peripheral Servicing Example .................................................................................
Registers ...................................................................................................................
16.4.1 Parameter RAM (PaRAM) Entries ............................................................................
16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................
16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ........................................................
Tips .........................................................................................................................
16.5.1 Debug Checklist ................................................................................................
16.5.2 Miscellaneous Programming/Debug Tips ...................................................................
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.................................................................................................... 569
EMAC/MDIO Module .......................................................................................................... 570
17.1 Introduction ................................................................................................................ 571
17.1.1 Purpose of the Peripheral ..................................................................................... 571
17.1.2 Features.......................................................................................................... 571
17.1.3 Functional Block Diagram ..................................................................................... 572
17.1.4 Industry Standard(s) Compliance Statement................................................................ 573
17.1.5 Terminology ..................................................................................................... 573
17.2 Architecture ................................................................................................................ 574
17.2.1 Clock Control .................................................................................................... 574
17.2.2 Memory Map .................................................................................................... 575
17.2.3 Signal Descriptions ............................................................................................. 575
17.2.4 Ethernet Protocol Overview ................................................................................... 578
17.2.5 Programming Interface ......................................................................................... 579
17.2.6 EMAC Control Module ......................................................................................... 590
17.2.7 MDIO Module ................................................................................................... 591
17.2.8 EMAC Module ................................................................................................... 596
17.2.9 MAC Interface ................................................................................................... 598
17.2.10 Packet Receive Operation ................................................................................... 602
17.2.11 Packet Transmit Operation .................................................................................. 607
17.2.12 Receive and Transmit Latency .............................................................................. 608
17.2.13 Transfer Node Priority ........................................................................................ 608
17.2.14 Reset Considerations ......................................................................................... 609
17.2.15 Initialization ..................................................................................................... 610
17.2.16 Interrupt Support .............................................................................................. 612
17.2.17 Power Management .......................................................................................... 616
17.2.18 Emulation Considerations .................................................................................... 616
17.3 Registers ................................................................................................................... 617
17.3.1 EMAC Control Module Registers ............................................................................. 617
17.3.2 MDIO Registers ................................................................................................. 631
17.3.3 EMAC Module Registers....................................................................................... 644
External Memory Interface A (EMIFA) .................................................................................. 694
18.1 Introduction ................................................................................................................ 695
18.1.1 Purpose of the Peripheral ..................................................................................... 695
18.1.2 Features.......................................................................................................... 695
18.1.3 Functional Block Diagram ..................................................................................... 695
18.2 Architecture ................................................................................................................ 695
18.2.1 Clock Control .................................................................................................... 696
18.2.2 EMIFA Requests ................................................................................................ 696
18.2.3 Pin Descriptions ................................................................................................. 696
18.2.4 SDRAM Controller and Interface ............................................................................. 698
18.2.5 Asynchronous Controller and Interface ...................................................................... 710
18.2.6 Data Bus Parking ............................................................................................... 729
18.2.7 Reset and Initialization Considerations ...................................................................... 729
18.2.8 Interrupt Support ................................................................................................ 730
18.2.9 EDMA Event Support .......................................................................................... 731
18.2.10 Pin Multiplexing ................................................................................................ 731
18.2.11 Memory Map ................................................................................................... 731
18.2.12 Priority and Arbitration ........................................................................................ 732
18.2.13 System Considerations ....................................................................................... 733
18.2.14 Power Management .......................................................................................... 734
18.2.15 Emulation Considerations .................................................................................... 735
18.3 Example Configuration ................................................................................................... 736
16.6
17
18
8
Setting Up a Transfer
Contents
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18.4
19
18.3.1 Hardware Interface .............................................................................................
18.3.2 Software Configuration .........................................................................................
Registers ...................................................................................................................
18.4.1 Module ID Register (MIDR) ...................................................................................
18.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) ...............................................
18.4.3 SDRAM Configuration Register (SDCR) ....................................................................
18.4.4 SDRAM Refresh Control Register (SDRCR) ................................................................
18.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
18.4.6 SDRAM Timing Register (SDTIMR) ..........................................................................
18.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ..................................................
18.4.8 EMIFA Interrupt Raw Register (INTRAW) ...................................................................
18.4.9 EMIFA Interrupt Masked Register (INTMSK) ...............................................................
18.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET).......................................................
18.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ....................................................
18.4.12 NAND Flash Control Register (NANDFCR) ...............................................................
18.4.13 NAND Flash Status Register (NANDFSR) .................................................................
18.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ..........................................
18.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) .......................................
18.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..................................................
18.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..................................................
18.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..................................................
18.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..................................................
18.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) .................................
18.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) .................................
18.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1).....................................
18.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2).....................................
736
736
758
759
759
761
763
764
766
767
768
769
770
771
772
774
775
776
777
777
778
778
779
779
780
780
External Memory Interface B (EMIFB) .................................................................................. 781
19.1
19.2
19.3
19.4
Introduction ................................................................................................................
19.1.1 Purpose of the Peripheral .....................................................................................
19.1.2 Features..........................................................................................................
19.1.3 Functional Block Diagram .....................................................................................
Architecture ................................................................................................................
19.2.1 Clock Control ....................................................................................................
19.2.2 EMIF Requests..................................................................................................
19.2.3 Pin Descriptions .................................................................................................
19.2.4 Pin Multiplexing .................................................................................................
19.2.5 Memory Map ....................................................................................................
19.2.6 SDRAM Controller and Interface .............................................................................
19.2.7 Reset and Initialization Considerations ......................................................................
19.2.8 Interrupt Support ................................................................................................
19.2.9 Power Management ............................................................................................
19.2.10 Emulation Considerations ....................................................................................
Example Configuration ...................................................................................................
Registers ...................................................................................................................
19.4.1 SDRAM Configuration Register (SDCFG) ..................................................................
19.4.2 SDRAM Refresh Control Register (SDRFC) ................................................................
19.4.3 SDRAM Timing 1 Register (SDTIM1) ........................................................................
19.4.4 SDRAM Timing 2 Register (SDTIM2) ........................................................................
19.4.5 Peripheral Bus Burst Priority Register (BPRIO) ............................................................
19.4.6 Performance Counter 1 Register (PC1) .....................................................................
19.4.7 Performance Counter 2 Register (PC2) .....................................................................
19.4.8 Performance Counter Configuration Register (PCC) ......................................................
19.4.9 Performance Counter Master Region Select Register (PCMRS) ........................................
SPRUH91D – March 2013 – Revised September 2016
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Contents
782
782
782
782
783
783
783
783
784
784
784
802
802
803
805
805
809
810
812
813
814
816
817
817
818
820
9
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19.4.10
19.4.11
19.4.12
19.4.13
20
20.2
20.3
821
822
823
823
Introduction ................................................................................................................
20.1.1 Purpose of the Peripheral .....................................................................................
20.1.2 Features..........................................................................................................
20.1.3 Functional Block Diagram .....................................................................................
20.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
20.2.1 Clock Control ....................................................................................................
20.2.2 Signal Descriptions .............................................................................................
20.2.3 Pin Multiplexing .................................................................................................
20.2.4 Endianness Considerations ...................................................................................
20.2.5 GPIO Register Structure .......................................................................................
20.2.6 Using a GPIO Signal as an Output ...........................................................................
20.2.7 Using a GPIO Signal as an Input .............................................................................
20.2.8 Reset Considerations ..........................................................................................
20.2.9 Initialization ......................................................................................................
20.2.10 Interrupt Support ..............................................................................................
20.2.11 EDMA Event Support .........................................................................................
20.2.12 Power Management ..........................................................................................
20.2.13 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
20.3.1 Revision ID Register (REVID) .................................................................................
20.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ......................................................
20.3.3 GPIO Direction Registers (DIRn) .............................................................................
20.3.4 GPIO Output Data Registers (OUT_DATAn) ...............................................................
20.3.5 GPIO Set Data Registers (SET_DATAn) ....................................................................
20.3.6 GPIO Clear Data Registers (CLR_DATAn) .................................................................
20.3.7 GPIO Input Data Registers (IN_DATAn) ....................................................................
20.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) ...........................................
20.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ........................................
20.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................
20.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) .....................................
20.3.12 GPIO Interrupt Status Registers (INTSTATn) .............................................................
825
825
825
825
825
826
826
826
826
826
827
830
831
831
832
832
833
833
833
834
835
836
837
839
841
843
845
847
849
851
853
855
Host Port Interface (HPI) .................................................................................................... 857
21.1
21.2
10
Raw Register (IRR) ................................................................................
Mask Register (IMR) ...............................................................................
Mask Set Register (IMSR) ........................................................................
Mask Clear Register (IMCR) ......................................................................
General-Purpose Input/Output (GPIO) ................................................................................. 824
20.1
21
Interrupt
Interrupt
Interrupt
Interrupt
Introduction ................................................................................................................
21.1.1 Purpose of the Peripheral .....................................................................................
21.1.2 Features..........................................................................................................
21.1.3 Functional Block Diagram .....................................................................................
21.1.4 Industry Standard(s) Compliance Statement................................................................
21.1.5 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
21.2.1 Clock Control ....................................................................................................
21.2.2 Memory Map ....................................................................................................
21.2.3 Signal Descriptions .............................................................................................
21.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks ................................................
21.2.5 Protocol Description ............................................................................................
21.2.6 Operation ........................................................................................................
21.2.7 Reset Considerations ..........................................................................................
21.2.8 Initialization ......................................................................................................
Contents
858
858
858
859
860
860
861
861
861
861
862
863
863
878
878
SPRUH91D – March 2013 – Revised September 2016
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21.3
22
21.2.9 Interrupt Support ................................................................................................
21.2.10 EDMA Event Support .........................................................................................
21.2.11 Power Management ..........................................................................................
21.2.12 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
21.3.1 Revision Identification Register (REVID) ....................................................................
21.3.2 Power and Emulation Management Register (PWREMU_MGMT) ......................................
21.3.3 GPIO Enable Register (GPIO_EN) ..........................................................................
21.3.4 GPIO Direction 1 Register (GPIO_DIR1) ....................................................................
21.3.5 GPIO Data 1 Register (GPIO_DAT1) ........................................................................
21.3.6 GPIO Direction 2 Register (GPIO_DIR2) ....................................................................
21.3.7 GPIO Data 2 Register (GPIO_DAT2) ........................................................................
21.3.8 Host Port Interface Control Register (HPIC) ................................................................
21.3.9 Host Port Interface Write Address Register (HPIAW) .....................................................
21.3.10 Host Port Interface Read Address Register (HPIAR) ....................................................
Inter-Integrated Circuit (I2C) Module
22.1
22.2
22.3
879
880
880
881
881
882
882
883
884
884
885
886
887
889
889
................................................................................... 890
Introduction ................................................................................................................
22.1.1 Purpose of the Peripheral .....................................................................................
22.1.2 Features..........................................................................................................
22.1.3 Functional Block Diagram .....................................................................................
22.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
22.2.1 Bus Structure ....................................................................................................
22.2.2 Clock Generation ...............................................................................................
22.2.3 Clock Synchronization .........................................................................................
22.2.4 Signal Descriptions .............................................................................................
22.2.5 START and STOP Conditions ................................................................................
22.2.6 Serial Data Formats ............................................................................................
22.2.7 Operating Modes ...............................................................................................
22.2.8 NACK Bit Generation...........................................................................................
22.2.9 Arbitration ........................................................................................................
22.2.10 Reset Considerations .........................................................................................
22.2.11 Initialization .....................................................................................................
22.2.12 Interrupt Support ..............................................................................................
22.2.13 DMA Events Generated by the I2C Peripheral ............................................................
22.2.14 Power Management ..........................................................................................
22.2.15 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
22.3.1 I2C Own Address Register (ICOAR) .........................................................................
22.3.2 I2C Interrupt Mask Register (ICIMR) .........................................................................
22.3.3 I2C Interrupt Status Register (ICSTR) ......................................................................
22.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) .......................................................
22.3.5 I2C Data Count Register (ICCNT) ............................................................................
22.3.6 I2C Data Receive Register (ICDRR) .........................................................................
22.3.7 I2C Slave Address Register (ICSAR) ........................................................................
22.3.8 I2C Data Transmit Register (ICDXR) ........................................................................
22.3.9 I2C Mode Register (ICMDR) ..................................................................................
22.3.10 I2C Interrupt Vector Register (ICIVR) ......................................................................
22.3.11 I2C Extended Mode Register (ICEMDR) ...................................................................
22.3.12 I2C Prescaler Register (ICPSC).............................................................................
22.3.13 I2C Revision Identification Register (REVID1) ............................................................
22.3.14 I2C Revision Identification Register (REVID2) ...........................................................
22.3.15 I2C DMA Control Register (ICDMAC) ......................................................................
SPRUH91D – March 2013 – Revised September 2016
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Contents
891
891
891
892
892
893
893
894
895
895
896
897
899
900
901
902
902
903
904
904
904
905
906
907
908
911
912
913
914
915
916
920
921
922
923
923
924
11
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22.3.16
22.3.17
22.3.18
22.3.19
22.3.20
22.3.21
23
23.2
23.3
925
926
927
928
929
930
Introduction ................................................................................................................
23.1.1 Purpose of the Peripheral .....................................................................................
23.1.2 Features..........................................................................................................
23.1.3 Terminology .....................................................................................................
Architecture ................................................................................................................
23.2.1 Clocking ..........................................................................................................
23.2.2 LCD External I/O Signals ......................................................................................
23.2.3 DMA Engine .....................................................................................................
23.2.4 LIDD Controller..................................................................................................
23.2.5 Raster Controller ................................................................................................
Registers ...................................................................................................................
23.3.1 LCD Revision Identification Register (REVID) ..............................................................
23.3.2 LCD Control Register (LCD_CTRL) ..........................................................................
23.3.3 LCD Status Register (LCD_STAT) ...........................................................................
23.3.4 LCD LIDD Control Register (LIDD_CTRL) ..................................................................
23.3.5 LCD LIDD CSn Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF) ................
23.3.6 LCD LIDD CSn Address Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR) ........
23.3.7 LCD LIDD CSn Data Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA) .............
23.3.8 LCD Raster Control Register (RASTER_CTRL) ............................................................
23.3.9 LCD Raster Timing Register 0 (RASTER_TIMING_0) ....................................................
23.3.10 LCD Raster Timing Register 1 (RASTER_TIMING_1) ...................................................
23.3.11 LCD Raster Timing Register 2 (RASTER_TIMING_2) ...................................................
23.3.12 LCD Raster Subpanel Display Register (RASTER_SUBPANEL) ......................................
23.3.13 LCD DMA Control Register (LCDDMA_CTRL) ............................................................
23.3.14 LCD DMA Frame Buffer n Base Address Registers
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE) ........................................................
23.3.15 LCD DMA Frame Buffer n Ceiling Address Registers
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING) .................................................
932
932
933
933
933
933
935
936
937
939
949
949
950
952
955
957
958
959
960
967
969
973
977
979
980
980
Multichannel Audio Serial Port (McASP) .............................................................................. 981
24.1
12
Function Register (ICPFUNC) ....................................................................
Direction Register (ICPDIR) .......................................................................
Data In Register (ICPDIN) .........................................................................
Data Out Register (ICPDOUT) ....................................................................
Data Set Register (ICPDSET) ....................................................................
Data Clear Register (ICPDCLR) ..................................................................
Liquid Crystal Display Controller (LCDC) ............................................................................. 931
23.1
24
I2C Pin
I2C Pin
I2C Pin
I2C Pin
I2C Pin
I2C Pin
24.0.16 Features ....................................................................................................... 982
24.0.17 Protocols Supported ......................................................................................... 983
24.0.18 Functional Block Diagram .................................................................................... 984
24.0.19 Definition of Terms ........................................................................................... 992
24.0.20 Overview ....................................................................................................... 995
24.0.21 Clock and Frame Sync Generators ........................................................................ 995
24.0.22 Reset Considerations ....................................................................................... 1035
24.0.23 EDMA Event Support ....................................................................................... 1035
24.0.24 Power Management ......................................................................................... 1035
Registers ................................................................................................................. 1036
24.1.1 Register Bit Restrictions ...................................................................................... 1039
24.1.2 Revision Identification Register (REV) ..................................................................... 1040
24.1.3 Pin Function Register (PFUNC) ............................................................................. 1041
24.1.4 Pin Direction Register (PDIR) ............................................................................... 1043
24.1.5 Pin Data Output Register (PDOUT) ........................................................................ 1045
24.1.6 Pin Data Input Register (PDIN).............................................................................. 1047
24.1.7 Pin Data Set Register (PDSET) ............................................................................. 1049
Contents
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24.1.8
24.1.9
24.1.10
24.1.11
24.1.12
24.1.13
24.1.14
24.1.15
24.1.16
24.1.17
24.1.18
24.1.19
24.1.20
24.1.21
24.1.22
24.1.23
24.1.24
24.1.25
24.1.26
24.1.27
24.1.28
24.1.29
24.1.30
24.1.31
24.1.32
24.1.33
24.1.34
24.1.35
24.1.36
24.1.37
24.1.38
24.1.39
24.1.40
24.1.41
24.1.42
24.1.43
24.1.44
24.1.45
24.1.46
24.1.47
24.1.48
25
Pin Data Clear Register (PDCLR) ..........................................................................
Global Control Register (GBLCTL) .........................................................................
Audio Mute Control Register (AMUTE) ...................................................................
Digital Loopback Control Register (DLBCTL) ............................................................
Digital Mode Control Register (DITCTL) ..................................................................
Receiver Global Control Register (RGBLCTL)...........................................................
Receive Format Unit Bit Mask Register (RMASK) ......................................................
Receive Bit Stream Format Register (RFMT) ............................................................
Receive Frame Sync Control Register (AFSRCTL) .....................................................
Receive Clock Control Register (ACLKRCTL) ...........................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) .....................................
Receive TDM Time Slot Register (RTDM) ...............................................................
Receiver Interrupt Control Register (RINTCTL) .........................................................
Receiver Status Register (RSTAT) ........................................................................
Current Receive TDM Time Slot Registers (RSLOT) ...................................................
Receive Clock Check Control Register (RCLKCHK)....................................................
Receiver DMA Event Control Register (REVTCTL) .....................................................
Transmitter Global Control Register (XGBLCTL) ........................................................
Transmit Format Unit Bit Mask Register (XMASK) ......................................................
Transmit Bit Stream Format Register (XFMT) ...........................................................
Transmit Frame Sync Control Register (AFSXCTL) ....................................................
Transmit Clock Control Register (ACLKXCTL) ..........................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ....................................
Transmit TDM Time Slot Register (XTDM) ...............................................................
Transmitter Interrupt Control Register (XINTCTL) ......................................................
Transmitter Status Register (XSTAT) .....................................................................
Current Transmit TDM Time Slot Register (XSLOT) ....................................................
Transmit Clock Check Control Register (XCLKCHK) ...................................................
Transmitter DMA Event Control Register (XEVTCTL) ..................................................
Serializer Control Registers (SRCTLn) ...................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ..........................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ........................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) .....................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ...................................
Transmit Buffer Registers (XBUFn) .......................................................................
Receive Buffer Registers (RBUFn) ........................................................................
AFIFO Revision Identification Register (AFIFOREV) ...................................................
Write FIFO Control Register (WFIFOCTL) ...............................................................
Write FIFO Status Register (WFIFOSTS) ................................................................
Read FIFO Control Register (RFIFOCTL) ................................................................
Read FIFO Status Register (RFIFOSTS).................................................................
1051
1053
1055
1057
1058
1059
1060
1061
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1086
1087
1087
1088
1088
1089
1090
1091
1092
1093
Multimedia Card (MMC)/Secure Digital (SD) Card Controller ................................................. 1094
25.1
25.2
Introduction ...............................................................................................................
25.1.1 Purpose of the Peripheral ....................................................................................
25.1.2 Features ........................................................................................................
25.1.3 Functional Block Diagram ....................................................................................
25.1.4 Supported Use Case Statement ............................................................................
25.1.5 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
25.2.1 Clock Control ..................................................................................................
25.2.2 Signal Descriptions............................................................................................
25.2.3 Protocol Descriptions .........................................................................................
25.2.4 Data Flow in the Input/Output FIFO ........................................................................
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Contents
1095
1095
1095
1095
1095
1096
1096
1097
1098
1099
1100
13
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25.3
25.4
26
1102
1103
1105
1105
1107
1110
1111
1111
1111
1112
1112
1115
1117
1117
1119
1119
1121
1121
1123
1123
1124
1125
1126
1127
1129
1130
1132
1133
1134
1135
1135
1136
1136
1137
1139
1140
1142
1142
1143
1144
1145
1145
1146
Real-Time Clock (RTC) ..................................................................................................... 1147
26.1
26.2
14
25.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ...........................................
25.2.6 FIFO Operation During Card Read Operation.............................................................
25.2.7 FIFO Operation During Card Write Operation .............................................................
25.2.8 Reset Considerations .........................................................................................
25.2.9 Initialization .....................................................................................................
25.2.10 Interrupt Support .............................................................................................
25.2.11 DMA Event Support .........................................................................................
25.2.12 Power Management .........................................................................................
25.2.13 Emulation Considerations ..................................................................................
Procedures for Common Operations .................................................................................
25.3.1 Card Identification Operation ................................................................................
25.3.2 MMC/SD Mode Single-Block Write Operation Using CPU ..............................................
25.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ........................................
25.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ..........................................
25.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ............................................
25.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU .............................................
25.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA...........................................
25.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................
25.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA ..........................................
25.3.10 SDIO Card Function .........................................................................................
Registers .................................................................................................................
25.4.1 MMC Control Register (MMCCTL) ..........................................................................
25.4.2 MMC Memory Clock Control Register (MMCCLK) .......................................................
25.4.3 MMC Status Register 0 (MMCST0) .........................................................................
25.4.4 MMC Status Register 1 (MMCST1) .........................................................................
25.4.5 MMC Interrupt Mask Register (MMCIM) ...................................................................
25.4.6 MMC Response Time-Out Register (MMCTOR) ..........................................................
25.4.7 MMC Data Read Time-Out Register (MMCTOD) .........................................................
25.4.8 MMC Block Length Register (MMCBLEN) .................................................................
25.4.9 MMC Number of Blocks Register (MMCNBLK) ...........................................................
25.4.10 MMC Number of Blocks Counter Register (MMCNBLC) ...............................................
25.4.11 MMC Data Receive Register (MMCDRR) ................................................................
25.4.12 MMC Data Transmit Register (MMCDXR) ...............................................................
25.4.13 MMC Command Register (MMCCMD) ...................................................................
25.4.14 MMC Argument Register (MMCARGHL) .................................................................
25.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ...................................................
25.4.16 MMC Data Response Register (MMCDRSP) ............................................................
25.4.17 MMC Command Index Register (MMCCIDX) ............................................................
25.4.18 SDIO Control Register (SDIOCTL) ........................................................................
25.4.19 SDIO Status Register 0 (SDIOST0) .......................................................................
25.4.20 SDIO Interrupt Enable Register (SDIOIEN) ..............................................................
25.4.21 SDIO Interrupt Status Register (SDIOIST) ...............................................................
25.4.22 MMC FIFO Control Register (MMCFIFOCTL) ...........................................................
Introduction ...............................................................................................................
26.1.1 Purpose of the Peripheral ....................................................................................
26.1.2 Features ........................................................................................................
26.1.3 Block Diagram .................................................................................................
Architecture ..............................................................................................................
26.2.1 Clock Source ...................................................................................................
26.2.2 Signal Descriptions............................................................................................
26.2.3 Isolated Power Supply ........................................................................................
26.2.4 Operation .......................................................................................................
Contents
1148
1148
1148
1148
1149
1149
1149
1149
1150
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26.3
27
26.2.5 Interrupt Requests ............................................................................................
26.2.6 Register Protection Against Spurious Writes ..............................................................
26.2.7 General-Purpose Scratch Registers ........................................................................
26.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) ..............................
26.2.9 Emulation Modes of the Real-Time Clock .................................................................
26.2.10 Reset Considerations .......................................................................................
Registers .................................................................................................................
26.3.1 Second Register (SECOND).................................................................................
26.3.2 Minute Register (MINUTE) ...................................................................................
26.3.3 Hour Register (HOUR) .......................................................................................
26.3.4 Day of the Month Register (DAY) ...........................................................................
26.3.5 Month Register (MONTH) ....................................................................................
26.3.6 Year Register (YEAR) ........................................................................................
26.3.7 Day of the Week Register (DOTW) .........................................................................
26.3.8 Alarm Second Register (ALARMSECOND) ...............................................................
26.3.9 Alarm Minute Register (ALARMMINUTE) ..................................................................
26.3.10 Alarm Hour Register (ALARMHOUR) .....................................................................
26.3.11 Alarm Day of the Month Register (ALARMDAY) ........................................................
26.3.12 Alarm Month Register (ALARMMONTH) .................................................................
26.3.13 Alarm Year Register (ALARMYEAR)......................................................................
26.3.14 Control Register (CTRL) ....................................................................................
26.3.15 Status Register (STATUS) .................................................................................
26.3.16 Interrupt Register (INTERRUPT) ..........................................................................
26.3.17 Compensation (LSB) Register (COMPLSB) .............................................................
26.3.18 Compensation (MSB) Register (COMPMSB) ............................................................
26.3.19 Oscillator Register (OSC) ...................................................................................
26.3.20 Scratch Registers (SCRATCH0-SCRATCH2) ...........................................................
26.3.21 Kick Registers (KICK0R, KICK1R) ........................................................................
1152
1153
1154
1154
1154
1154
1155
1156
1156
1157
1158
1158
1159
1159
1160
1160
1161
1162
1163
1163
1164
1165
1166
1167
1168
1169
1170
1170
Serial Peripheral Interface (SPI) ........................................................................................ 1171
27.1
27.2
Introduction ...............................................................................................................
27.1.1 Purpose of the Peripheral ....................................................................................
27.1.2 Features ........................................................................................................
27.1.3 Functional Block Diagram ....................................................................................
27.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
27.2.1 Clock ............................................................................................................
27.2.2 Signal Descriptions............................................................................................
27.2.3 Operation Modes ..............................................................................................
27.2.4 Programmable Registers .....................................................................................
27.2.5 Master Mode Settings ........................................................................................
27.2.6 Slave Mode Settings ..........................................................................................
27.2.7 SPI Operation: 3-Pin Mode ..................................................................................
27.2.8 SPI Operation: 4-Pin with Chip Select Mode .............................................................
27.2.9 SPI Operation: 4-Pin with Enable Mode ...................................................................
27.2.10 SPI Operation: 5-Pin Mode .................................................................................
27.2.11 Data Formats .................................................................................................
27.2.12 Interrupt Support .............................................................................................
27.2.13 DMA Events Support ........................................................................................
27.2.14 Robustness Features .......................................................................................
27.2.15 Reset Considerations .......................................................................................
27.2.16 Power Management .........................................................................................
27.2.17 General-Purpose I/O Pin....................................................................................
27.2.18 Emulation Considerations ..................................................................................
SPRUH91D – March 2013 – Revised September 2016
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Contents
1172
1172
1172
1173
1173
1174
1174
1174
1174
1175
1176
1178
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1180
1182
1184
1186
1189
1190
1190
1192
1192
1193
1193
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27.3
28
27.2.19 Initialization ...................................................................................................
27.2.20 Timing Diagrams .............................................................................................
Registers .................................................................................................................
27.3.1 SPI Global Control Register 0 (SPIGCR0) .................................................................
27.3.2 SPI Global Control Register 1 (SPIGCR1) .................................................................
27.3.3 SPI Interrupt Register (SPIINT0) ............................................................................
27.3.4 SPI Interrupt Level Register (SPILVL) ......................................................................
27.3.5 SPI Flag Register (SPIFLG) .................................................................................
27.3.6 SPI Pin Control Register 0 (SPIPC0) ......................................................................
27.3.7 SPI Pin Control Register 1 (SPIPC1) .......................................................................
27.3.8 SPI Pin Control Register 2 (SPIPC2) .......................................................................
27.3.9 SPI Pin Control Register 3 (SPIPC3) .......................................................................
27.3.10 SPI Pin Control Register 4 (SPIPC4) .....................................................................
27.3.11 SPI Pin Control Register 5 (SPIPC5) .....................................................................
27.3.12 SPI Transmit Data Register 0 (SPIDAT0) ................................................................
27.3.13 SPI Transmit Data Register 1 (SPIDAT1) ................................................................
27.3.14 SPI Receive Buffer Register (SPIBUF) ...................................................................
27.3.15 SPI Emulation Register (SPIEMU) ........................................................................
27.3.16 SPI Delay Register (SPIDELAY) ..........................................................................
27.3.17 SPI Default Chip Select Register (SPIDEF) ..............................................................
27.3.18 SPI Data Format Registers (SPIFMTn) ...................................................................
27.3.19 SPI Interrupt Vector Register 1 (INTVEC1) ..............................................................
64-Bit Timer Plus
28.1
28.2
1193
1194
1200
1200
1201
1203
1205
1206
1208
1209
1210
1211
1212
1213
1214
1215
1216
1218
1219
1222
1223
1225
............................................................................................................ 1226
Introduction ...............................................................................................................
28.1.1 Purpose of the Peripheral ....................................................................................
28.1.2 Features ........................................................................................................
28.1.3 Block Diagram .................................................................................................
28.1.4 Industry Standard Compatibility Statement ................................................................
28.1.5 Architecture – General-Purpose Timer Mode .............................................................
28.1.6 Architecture – Watchdog Timer Mode ......................................................................
28.1.7 Reset Considerations .........................................................................................
28.1.8 Interrupt Support ..............................................................................................
28.1.9 DMA Event Support ...........................................................................................
28.1.10 TM64P_OUT Event Support ...............................................................................
28.1.11 Interrupt/DMA Event Generation Control and Status ...................................................
28.1.12 Power Management .........................................................................................
28.1.13 Emulation Considerations ..................................................................................
Registers .................................................................................................................
28.2.1 Revision ID Register (REVID) ...............................................................................
28.2.2 Emulation Management Register (EMUMGT) .............................................................
28.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ............................................
28.2.4 GPIO Data and Direction Register (GPDATGPDIR) .....................................................
28.2.5 Timer Counter Registers (TIM12 and TIM34) .............................................................
28.2.6 Timer Period Registers (PRD12 and PRD34) .............................................................
28.2.7 Timer Control Register (TCR) ...............................................................................
28.2.8 Timer Global Control Register (TGCR).....................................................................
28.2.9 Watchdog Timer Control Register (WDTCR) ..............................................................
28.2.10 Timer Reload Register 12 (REL12) .......................................................................
28.2.11 Timer Reload Register 34 (REL34) .......................................................................
28.2.12 Timer Capture Register 12 (CAP12) ......................................................................
28.2.13 Timer Capture Register 34 (CAP34) ......................................................................
28.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) ..........................................
29
Universal Asynchronous Receiver/Transmitter (UART)
16
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1257
1258
....................................................... 1260
SPRUH91D – March 2013 – Revised September 2016
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29.1
29.2
29.3
30
Introduction ...............................................................................................................
29.1.1 Purpose of the Peripheral ....................................................................................
29.1.2 Features ........................................................................................................
29.1.3 Functional Block Diagram ....................................................................................
29.1.4 Industry Standard(s) Compliance Statement ..............................................................
Peripheral Architecture .................................................................................................
29.2.1 Clock Generation and Control ...............................................................................
29.2.2 Signal Descriptions............................................................................................
29.2.3 Pin Multiplexing ................................................................................................
29.2.4 Protocol Description ..........................................................................................
29.2.5 Operation .......................................................................................................
29.2.6 Reset Considerations .........................................................................................
29.2.7 Initialization .....................................................................................................
29.2.8 Interrupt Support ..............................................................................................
29.2.9 DMA Event Support ...........................................................................................
29.2.10 Power Management .........................................................................................
29.2.11 Emulation Considerations ..................................................................................
29.2.12 Exception Processing .......................................................................................
Registers .................................................................................................................
29.3.1 Receiver Buffer Register (RBR) .............................................................................
29.3.2 Transmitter Holding Register (THR) ........................................................................
29.3.3 Interrupt Enable Register (IER) .............................................................................
29.3.4 Interrupt Identification Register (IIR) ........................................................................
29.3.5 FIFO Control Register (FCR) ................................................................................
29.3.6 Line Control Register (LCR) .................................................................................
29.3.7 Modem Control Register (MCR) .............................................................................
29.3.8 Line Status Register (LSR) ..................................................................................
29.3.9 Modem Status Register (MSR) ..............................................................................
29.3.10 Scratch Pad Register (SCR) ...............................................................................
29.3.11 Divisor Latches (DLL and DLH) ............................................................................
29.3.12 Revision Identification Registers (REVID1 and REVID2) ..............................................
29.3.13 Power and Emulation Management Register (PWREMU_MGMT) ...................................
29.3.14 Mode Definition Register (MDR) ...........................................................................
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1261
1261
1261
1261
1263
1263
1265
1265
1265
1267
1271
1271
1271
1273
1273
1273
1273
1274
1275
1276
1277
1278
1279
1281
1283
1284
1287
1288
1288
1290
1291
1292
Universal Serial Bus OHCI Host Controller ......................................................................... 1293
30.1
30.2
30.3
Introduction ...............................................................................................................
30.1.1 Purpose of the Peripheral ....................................................................................
Architecture ..............................................................................................................
30.2.1 Clock and Reset ..............................................................................................
30.2.2 Open Host Controller Interface Functionality ..............................................................
30.2.3 Differences From OHCI Specification for USB ............................................................
30.2.4 Implementation of OHCI Specification for USB1.1 .......................................................
30.2.5 OHCI Interrupts ................................................................................................
30.2.6 USB1.1 Host Controller Access to System Memory ......................................................
30.2.7 Physical Addressing ..........................................................................................
Registers .................................................................................................................
30.3.1 OHCI Revision Number Register (HCREVISION) ........................................................
30.3.2 HC Operating Mode Register (HCCONTROL) ............................................................
30.3.3 HC Command and Status Register (HCCOMMANDSTATUS)..........................................
30.3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) ...........................................
30.3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) ...............................................
30.3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) ..............................................
30.3.7 HC HCAA Address Register (HCHCCA) ...................................................................
30.3.8 HC Current Periodic Register (HCPERIODCURRENTED) ..............................................
SPRUH91D – March 2013 – Revised September 2016
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Contents
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30.3.9
30.3.10
30.3.11
30.3.12
30.3.13
30.3.14
30.3.15
30.3.16
30.3.17
30.3.18
30.3.19
30.3.20
30.3.21
30.3.22
30.3.23
31
Universal Serial Bus 2.0 (USB) Controller
31.1
31.2
31.3
31.4
18
HC Head Control Register (HCCONTROLHEADED) ....................................................
HC Current Control Register (HCCONTROLCURRENTED)...........................................
HC Head Bulk Register (HCBULKHEADED) ............................................................
HC Current Bulk Register (HCBULKCURRENTED) ....................................................
HC Head Done Register (HCDONEHEAD) ..............................................................
HC Frame Interval Register (HCFMINTERVAL) .........................................................
HC Frame Remaining Register (HCFMREMAINING) ..................................................
HC Frame Number Register (HCFMNUMBER) .........................................................
HC Periodic Start Register (HCPERIODICSTART) .....................................................
HC Low-Speed Threshold Register (HCLSTHRESHOLD) .............................................
HC Root Hub A Register (HCRHDESCRIPTORA) ......................................................
HC Root Hub B Register (HCRHDESCRIPTORB) ......................................................
HC Root Hub Status Register (HCRHSTATUS) .........................................................
HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .....................................
HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .....................................
.......................................................................... 1319
Introduction ...............................................................................................................
31.1.1 Purpose of the Peripheral ....................................................................................
31.1.2 Features ........................................................................................................
31.1.3 Functional Block Diagram ....................................................................................
31.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
31.2.1 Clock Control ..................................................................................................
31.2.2 Signal Descriptions............................................................................................
31.2.3 Indexed and Non-Indexed Registers .......................................................................
31.2.4 USB PHY Initialization ........................................................................................
31.2.5 VBUS Voltage Sourcing Control ............................................................................
31.2.6 Dynamic FIFO Sizing .........................................................................................
31.2.7 USB Controller Host and Peripheral Modes Operation ..................................................
31.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ............................
31.2.9 Test Modes.....................................................................................................
31.2.10 Reset Considerations .......................................................................................
31.2.11 Interrupt Support .............................................................................................
31.2.12 DMA Event Support .........................................................................................
31.2.13 Power Management .........................................................................................
Use Cases................................................................................................................
31.3.1 User Case 1: Example of How to Initialize the USB Controller .........................................
31.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode .................
31.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode........................
31.3.4 User Case 4: Example of How to Program the USB DMA Controller ..................................
Registers .................................................................................................................
31.4.1 Revision Identification Register (REVID) ...................................................................
31.4.2 Control Register (CTRLR)....................................................................................
31.4.3 Status Register (STATR) .....................................................................................
31.4.4 Emulation Register (EMUR) .................................................................................
31.4.5 Mode Register (MODE) ......................................................................................
31.4.6 Auto Request Register (AUTOREQ) .......................................................................
31.4.7 SRP Fix Time Register (SRPFIXTIME) ....................................................................
31.4.8 Teardown Register (TEARDOWN)..........................................................................
31.4.9 USB Interrupt Source Register (INTSRCR) ...............................................................
31.4.10 USB Interrupt Source Set Register (INTSETR)..........................................................
31.4.11 USB Interrupt Source Clear Register (INTCLRR) .......................................................
31.4.12 USB Interrupt Mask Register (INTMSKR) ................................................................
Contents
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1307
1308
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SPRUH91D – March 2013 – Revised September 2016
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31.4.13
31.4.14
31.4.15
31.4.16
31.4.17
31.4.18
31.4.19
31.4.20
31.4.21
31.4.22
31.4.23
31.4.24
31.4.25
31.4.26
31.4.27
31.4.28
31.4.29
31.4.30
31.4.31
31.4.32
31.4.33
31.4.34
31.4.35
31.4.36
31.4.37
31.4.38
31.4.39
31.4.40
31.4.41
31.4.42
31.4.43
31.4.44
31.4.45
31.4.46
31.4.47
31.4.48
31.4.49
31.4.50
31.4.51
31.4.52
31.4.53
31.4.54
31.4.55
31.4.56
31.4.57
31.4.58
31.4.59
31.4.60
31.4.61
31.4.62
31.4.63
31.4.64
31.4.65
USB Interrupt Mask Set Register (INTMSKSETR) ......................................................
USB Interrupt Mask Clear Register (INTMSKCLRR) ...................................................
USB Interrupt Source Masked Register (INTMASKEDR) ..............................................
USB End of Interrupt Register (EOIR) ....................................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) .................................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) .................................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) .................................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) .................................................
Function Address Register (FADDR) .....................................................................
Power Management Register (POWER) .................................................................
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .............................................
Interrupt Enable Register for INTRTX (INTRTXE) ......................................................
Interrupt Enable Register for INTRRX (INTRRXE) ......................................................
Interrupt Register for Common USB Interrupts (INTRUSB)............................................
Interrupt Enable Register for INTRUSB (INTRUSBE) ..................................................
Frame Number Register (FRAME) ........................................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)..................
Register to Enable the USB 2.0 Test Modes (TESTMODE) ...........................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)...........................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..........................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...............................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ..........................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...............................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ...........................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..........................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...............................
Count 0 Register (COUNT0) ...............................................................................
Receive Count Register (RXCOUNT) .....................................................................
Type Register (Host mode only) (HOST_TYPE0) ......................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) .........................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ..........................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .........................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................
Configuration Data Register (CONFIGDATA) ...........................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .........................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .........................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .........................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .........................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .........................................
Device Control Register (DEVCTL) .......................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ)...............................................................
Receive Endpoint FIFO Size (RXFIFOSZ) ...............................................................
Transmit Endpoint FIFO Address (TXFIFOADDR) ......................................................
Receive Endpoint FIFO Address (RXFIFOADDR) ......................................................
Hardware Version Register (HWVERS) ..................................................................
Transmit Function Address (TXFUNCADDR) ............................................................
Transmit Hub Address (TXHUBADDR) ...................................................................
Transmit Hub Port (TXHUBPORT) ........................................................................
Receive Function Address (RXFUNCADDR) ............................................................
Receive Hub Address (RXHUBADDR) ...................................................................
Receive Hub Port (RXHUBPORT) ........................................................................
SPRUH91D – March 2013 – Revised September 2016
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Contents
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31.4.66 CDMA Revision Identification Register (DMAREVID) ..................................................
31.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ................................
31.4.68 CDMA Emulation Control Register (DMAEMU) .........................................................
31.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3]) ...............
31.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3]) ...............
31.4.71 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]RXHPCRA[3]) ...................................................................................................
31.4.72 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]RXHPCRB[3]) ...................................................................................................
31.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL) ............................................
31.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63]) ...................................
31.4.75 Queue Manager Revision Identification Register (QMGRREVID) ....................................
31.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................
31.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ...................
31.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ...................
31.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ...................
31.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ...................
31.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ..................
31.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ..............................
31.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ..................
31.4.84 Queue Manager Queue Pending Register 0 (PEND0) .................................................
31.4.85 Queue Manager Queue Pending Register 1 (PEND1) .................................................
31.4.86 Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]QMEMRBASE[15]) .............................................................................................
31.4.87 Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ...
31.4.88 Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]) ..............................
31.4.89 Queue Manager Queue N Status Register A (QSTATA[0]-QSTATA[63]) ...........................
31.4.90 Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) ...........................
31.4.91 Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) ...........................
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1456
1457
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1469
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Revision History ...................................................................................................................... 1471
20
Contents
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
2-1.
TMS320C674x Megamodule Block Diagram ........................................................................... 69
3-1.
System Interconnect Block Diagram ..................................................................................... 78
5-1.
MPU Block Diagram
5-2.
Permission Fields
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
6-1.
6-2.
6-3.
6-4.
6-5.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
....................................................................................................... 83
.......................................................................................................... 86
Revision ID Register (REVID) ............................................................................................ 91
Configuration Register (CONFIG) ........................................................................................ 91
Interrupt Raw Status/Set Register (IRAWSTAT) ....................................................................... 92
Interrupt Enable Status/Clear Register (IENSTAT) .................................................................... 93
Interrupt Enable Set Register (IENSET) ................................................................................ 94
Interrupt Enable Clear Register (IENCLR) .............................................................................. 94
Fixed Range Start Address Register (FXD_MPSAR) ................................................................. 95
Fixed Range End Address Register (FXD_MPEAR) .................................................................. 95
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .......................................... 96
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) ....................................... 97
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) ....................................... 97
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) ........................................ 98
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ........................................ 98
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) .......................... 99
Fault Address Register (FLTADDRR) .................................................................................. 100
Fault Status Register (FLTSTAT) ....................................................................................... 101
Fault Clear Register (FLTCLR) ......................................................................................... 102
Overall Clocking Diagram................................................................................................ 105
USB Clocking Diagram................................................................................................... 107
EMIFB Clocking Diagram ................................................................................................ 110
EMIFA Clocking Diagram ................................................................................................ 111
EMAC Clocking Diagram ................................................................................................ 112
PLL0 Structure ............................................................................................................ 117
Revision Identification Register (REVID) .............................................................................. 122
Reset Type Status Register (RSTYPE) ................................................................................ 122
PLL Control Register (PLLCTL) ......................................................................................... 123
OBSCLK Select Register (OCSEL) .................................................................................... 124
PLL Multiplier Control Register (PLLM) ................................................................................ 125
PLL Pre-Divider Control Register (PREDIV) .......................................................................... 125
PLL Controller Divider 1 Register (PLLDIV1) ......................................................................... 126
PLL Controller Divider 2 Register (PLLDIV2) ........................................................................ 126
PLL Controller Divider 3 Register (PLLDIV3) ........................................................................ 127
PLL Controller Divider 4 Register (PLLDIV4) ......................................................................... 127
PLL Controller Divider 5 Register (PLLDIV5) ......................................................................... 128
PLL Controller Divider 6 Register (PLLDIV6) ......................................................................... 128
PLL Controller Divider 7 Register (PLLDIV7) ......................................................................... 129
Oscillator Divider 1 Register (OSCDIV) ................................................................................ 130
PLL Post-Divider Control Register (POSTDIV) ....................................................................... 131
PLL Controller Command Register (PLLCMD) ....................................................................... 131
PLL Controller Status Register (PLLSTAT) ........................................................................... 132
PLL Controller Clock Align Control Register (ALNCTL) ............................................................. 133
PLLDIV Ratio Change Status Register (DCHANGE) ................................................................ 134
Clock Enable Control Register (CKEN) ................................................................................ 135
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
21
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7-22.
Clock Status Register (CKSTAT) ....................................................................................... 136
7-23.
SYSCLK Status Register (SYSTAT) ................................................................................... 137
7-24.
Emulation Performance Counter 0 Register (EMUCNT0) ........................................................... 138
7-25.
Emulation Performance Counter 1 Register (EMUCNT1) ........................................................... 138
8-1.
Revision Identification Register (REVID) .............................................................................. 149
8-2.
Interrupt Evaluation Register (INTEVAL) .............................................................................. 149
8-3.
PSC0 Module Error Pending Register 0 (MERRPR0) ............................................................... 150
8-4.
PSC1 Module Error Pending Register 0 (MERRPR0) ............................................................... 150
8-5.
PSC0 Module Error Clear Register 0 (MERRCR0)
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
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10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
22
..................................................................
PSC1 Module Error Clear Register 0 (MERRCR0) ..................................................................
Power Error Pending Register (PERRPR) ............................................................................
Power Error Clear Register (PERRCR) ................................................................................
Power Domain Transition Command Register (PTCMD)............................................................
Power Domain Transition Status Register (PTSTAT) ................................................................
Power Domain 0 Status Register (PDSTAT0) ........................................................................
Power Domain 1 Status Register (PDSTAT1) ........................................................................
Power Domain 0 Control Register (PDCTL0) .........................................................................
Power Domain 1 Control Register (PDCTL1) .........................................................................
Power Domain 0 Configuration Register (PDCFG0) .................................................................
Power Domain 1 Configuration Register (PDCFG1) .................................................................
Module Status n Register (MDSTATn) .................................................................................
PSC0 Module Control n Register (MDCTLn) .........................................................................
PSC1 Module Control n Register (MDCTLn) .........................................................................
Revision Identification Register (REVID) ..............................................................................
Device Identification Register 0 (DEVIDR0) ...........................................................................
Boot Configuration Register (BOOTCFG) .............................................................................
Silicon Revision Identification Register (CHIPREVID) ...............................................................
Kick 0 Register (KICK0R) ................................................................................................
Kick 1 Register (KICK1R) ................................................................................................
Host 1 Configuration Register (HOST1CFG) .........................................................................
Interrupt Raw Status/Set Register (IRAWSTAT) .....................................................................
Interrupt Enable Status/Clear Register (IENSTAT)...................................................................
Interrupt Enable Register (IENSET) ....................................................................................
Interrupt Enable Clear Register (IENCLR) ............................................................................
End of Interrupt Register (EOI) .........................................................................................
Fault Address Register (FLTADDRR) ..................................................................................
Fault Status Register (FLTSTAT) .......................................................................................
Master Priority 0 Register (MSTPRI0) .................................................................................
Master Priority 1 Register (MSTPRI1) .................................................................................
Master Priority 2 Register (MSTPRI2) .................................................................................
Pin Multiplexing Control 0 Register (PINMUX0) ......................................................................
Pin Multiplexing Control 1 Register (PINMUX1) ......................................................................
Pin Multiplexing Control 2 Register (PINMUX2) ......................................................................
Pin Multiplexing Control 3 Register (PINMUX3) ......................................................................
Pin Multiplexing Control 4 Register (PINMUX4) ......................................................................
Pin Multiplexing Control 5 Register (PINMUX5) ......................................................................
Pin Multiplexing Control 6 Register (PINMUX6) ......................................................................
Pin Multiplexing Control 7 Register (PINMUX7) ......................................................................
Pin Multiplexing Control 8 Register (PINMUX8) ......................................................................
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10-27. Pin Multiplexing Control 9 Register (PINMUX9) ...................................................................... 205
10-28. Pin Multiplexing Control 10 Register (PINMUX10) ................................................................... 207
10-29. Pin Multiplexing Control 11 Register (PINMUX11) ................................................................... 209
10-30. Pin Multiplexing Control 12 Register (PINMUX12) ................................................................... 211
10-31. Pin Multiplexing Control 13 Register (PINMUX13) ................................................................... 213
10-32. Pin Multiplexing Control 14 Register (PINMUX14) ................................................................... 215
10-33. Pin Multiplexing Control 15 Register (PINMUX15) ................................................................... 217
10-34. Pin Multiplexing Control 16 Register (PINMUX16) ................................................................... 219
10-35. Pin Multiplexing Control 17 Register (PINMUX17) ................................................................... 221
10-36. Pin Multiplexing Control 18 Register (PINMUX18) ................................................................... 223
10-37. Pin Multiplexing Control 19 Register (PINMUX19) ................................................................... 225
10-38. Suspend Source Register (SUSPSRC) ................................................................................ 226
10-39. Chip Signal Register (CHIPSIG) ........................................................................................ 228
10-40. Chip Signal Clear Register (CHIPSIG_CLR) .......................................................................... 229
..........................................................................
..........................................................................
Chip Configuration 2 Register (CFGCHIP2) ..........................................................................
Chip Configuration 3 Register (CFGCHIP3) ..........................................................................
Chip Configuration 4 Register (CFGCHIP4) ..........................................................................
Multiple eCAP Modules ..................................................................................................
Capture and APWM Modes of Operation..............................................................................
Capture Function Diagram...............................................................................................
Event Prescale Control...................................................................................................
Prescale Function Waveforms ..........................................................................................
Continuous/One-shot Block Diagram ..................................................................................
Counter and Synchronization Block Diagram .........................................................................
Interrupts in eCAP Module ..............................................................................................
PWM Waveform Details Of APWM Mode Operation ................................................................
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ................................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ..................................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect .............................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ...............................
PWM Waveform Details of APWM Mode Operation .................................................................
Multichannel PWM Example Using 4 eCAP Modules................................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules .......................................
Time-Stamp Counter Register (TSCTR) ...............................................................................
Counter Phase Control Register (CTRPHS) .........................................................................
Capture 1 Register (CAP1) .............................................................................................
Capture 2 Register (CAP2) ..............................................................................................
Capture 3 Register (CAP3) ..............................................................................................
Capture 4 Register (CAP4) ..............................................................................................
ECAP Control Register 1 (ECCTL1) ...................................................................................
ECAP Control Register 2 (ECCTL2) ...................................................................................
ECAP Interrupt Enable Register (ECEINT)............................................................................
ECAP Interrupt Flag Register (ECFLG)................................................................................
ECAP Interrupt Clear Register (ECCLR) ..............................................................................
ECAP Interrupt Forcing Register (ECFRC)............................................................................
Revision ID Register (REVID) ...........................................................................................
Multiple ePWM Modules .................................................................................................
10-41. Chip Configuration 0 Register (CFGCHIP0)
230
10-42. Chip Configuration 1 Register (CFGCHIP1)
231
10-43.
235
10-44.
10-45.
13-1.
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13-25.
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13-27.
13-28.
13-29.
14-1.
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
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14-2.
Submodules and Signal Connections for an ePWM Module........................................................ 285
14-3.
ePWM Submodules and Critical Internal Signal Interconnects ..................................................... 286
14-4.
Time-Base Submodule Block Diagram
14-5.
Time-Base Submodule Signals and Registers ........................................................................ 293
14-6.
Time-Base Frequency and Period ...................................................................................... 295
14-7.
Time-Base Counter Synchronization Scheme 1 ...................................................................... 296
14-8.
Time-Base Up-Count Mode Waveforms ............................................................................... 298
14-9.
Time-Base Down-Count Mode Waveforms
................................................................................
...........................................................................
292
299
14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event ..... 299
14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event
........
300
14-12. Counter-Compare Submodule .......................................................................................... 301
14-13. Counter-Compare Submodule Signals and Registers ............................................................... 301
14-14. Counter-Compare Event Waveforms in Up-Count Mode ............................................................ 304
14-15. Counter-Compare Events in Down-Count Mode
.....................................................................
304
14-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................... 305
14-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ....................................................................................................................... 305
14-18. Action-Qualifier Submodule
.............................................................................................
306
14-19. Action-Qualifier Submodule Inputs and Outputs ...................................................................... 307
14-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ........................................... 308
14-21. Up-Down-Count Mode Symmetrical Waveform ....................................................................... 311
14-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................. 312
14-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................... 314
14-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............. 316
14-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................. 318
14-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ........................................................................................... 320
14-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ......................................................................................................................... 322
14-28. Dead-Band Generator Submodule ..................................................................................... 324
14-29. Configuration Options for the Dead-Band Generator Submodule .................................................. 325
14-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................... 327
14-31. PWM-Chopper Submodule .............................................................................................. 328
14-32. PWM-Chopper Submodule Signals and Registers ................................................................... 329
14-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................ 330
14-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
.......
330
14-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ...................................................................................................................... 331
14-36. Trip-Zone Submodule .................................................................................................... 332
14-37. Trip-Zone Submodule Mode Control Logic ............................................................................ 335
14-38. Trip-Zone Submodule Interrupt Logic .................................................................................. 335
14-39. Event-Trigger Submodule
...............................................................................................
336
14-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller ............................................... 337
14-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ........................................ 337
14-42. Event-Trigger Interrupt Generator ...................................................................................... 339
14-43. HRPWM System Interface ............................................................................................... 340
14-44. Resolution Calculations for Conventionally Generated PWM ....................................................... 341
24
List of Figures
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14-45. Operating Logic Using MEP ............................................................................................. 342
14-46. Required PWM Waveform for a Requested Duty = 40.5%
.........................................................
344
14-47. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ................................ 346
14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ................................ 346
14-49. Simplified ePWM Module ................................................................................................ 347
......................................
Control of Four Buck Stages. (Note: FPWM1≠ FPWM2≠ FPWM3≠ FPWM4) ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .........................................................
Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) .............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1).............................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) ...........................................................
Half-H Bridge Waveforms for (Note: FPWM2 = FPWM1) ..................................................................
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ...............................
3-Phase Inverter Waveforms for (Only One Inverter Shown) .......................................................
Configuring Two PWM Modules for Phase Control ..................................................................
Timing Waveforms Associated With Phase Control Between 2 Modules .........................................
Control of a 3-Phase Interleaved DC/DC Converter .................................................................
3-Phase Interleaved DC/DC Converter Waveforms for .............................................................
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1 ) ....................................................................
ZVS Full-H Bridge Waveforms ..........................................................................................
Time-Base Control Register (TBCTL) ..................................................................................
Time-Base Status Register (TBSTS) ...................................................................................
Time-Base Phase Register (TBPHS) ..................................................................................
Time-Base Counter Register (TBCNT) ................................................................................
Time-Base Period Register (TBPRD) ..................................................................................
Counter-Compare Control Register (CMPCTL) .......................................................................
Counter-Compare A Register (CMPA) ................................................................................
Counter-Compare B Register (CMPB) .................................................................................
Action-Qualifier Output A Control Register (AQCTLA)...............................................................
Action-Qualifier Output B Control Register (AQCTLB)...............................................................
Action-Qualifier Software Force Register (AQSFRC) ................................................................
Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................
Dead-Band Generator Control Register (DBCTL) ....................................................................
Dead-Band Generator Rising Edge Delay Register (DBRED) ......................................................
Dead-Band Generator Falling Edge Delay Register (DBFED) .....................................................
PWM-Chopper Control Register (PCCTL) .............................................................................
Trip-Zone Select Register (TZSEL) ....................................................................................
Trip-Zone Control Register (TZCTL) ...................................................................................
Trip-Zone Enable Interrupt Register (TZEINT) ........................................................................
Trip-Zone Flag Register (TZFLG).......................................................................................
Trip-Zone Clear Register (TZCLR) .....................................................................................
Trip-Zone Force Register (TZFRC).....................................................................................
Event-Trigger Selection Register (ETSEL) ............................................................................
Event-Trigger Prescale Register (ETPS) ..............................................................................
Event-Trigger Flag Register (ETFLG) ..................................................................................
Event-Trigger Clear Register (ETCLR) ................................................................................
Event-Trigger Force Register (ETFRC) ................................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) ..........................................................
Counter-Compare A High-Resolution Register (CMPAHR) .........................................................
14-50. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
348
14-51.
349
14-52.
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14-88.
14-89.
14-90.
14-91.
14-92.
14-93.
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
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14-94. HRPWM Configuration Register (HRCNFG) .......................................................................... 395
15-1.
Optical Encoder Disk ..................................................................................................... 397
15-2.
QEP Encoder Output Signal for Forward/Reverse Movement ...................................................... 398
15-3.
Index Pulse Example ..................................................................................................... 398
15-4.
Functional Block Diagram of the eQEP Peripheral ................................................................... 401
15-5.
Functional Block Diagram of Decoder Unit ............................................................................ 402
15-6.
Quadrature Decoder State Machine.................................................................................... 404
15-7.
Quadrature-clock and Direction Decoding ............................................................................. 404
15-8.
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
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15-45.
16-1.
16-2.
16-3.
26
................
Position Counter Underflow/Overflow (QPOSMAX = 4) ............................................................
Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) .................................................
Strobe Event Latch (QEPCTL[SEL] = 1)...............................................................................
eQEP Position-compare Unit ............................................................................................
eQEP Position-compare Event Generation Points ...................................................................
eQEP Position-compare Sync Output Pulse Stretcher ..............................................................
eQEP Edge Capture Unit ................................................................................................
Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ..................................
eQEP Edge Capture Unit - Timing Details ............................................................................
eQEP Watchdog Timer ..................................................................................................
eQEP Unit Time Base ....................................................................................................
EQEP Interrupt Generation ..............................................................................................
eQEP Position Counter Register (QPOSCNT) .......................................................................
eQEP Position Counter Initialization Register (QPOSINIT) .........................................................
eQEP Maximum Position Count Register (QPOSMAX) .............................................................
eQEP Position-Compare Register (QPOSCMP) .....................................................................
eQEP Index Position Latch Register (QPOSILAT) ...................................................................
eQEP Strobe Position Latch Register (QPOSSLAT) ................................................................
eQEP Position Counter Latch Register (QPOSLAT) .................................................................
eQEP Unit Timer Register (QUTMR) ..................................................................................
eQEP Unit Period Register (QUPRD) ..................................................................................
eQEP Watchdog Timer Register (QWDTMR).........................................................................
eQEP Watchdog Period Register (QWDPRD) ........................................................................
QEP Decoder Control Register (QDECCTL) ..........................................................................
eQEP Control Register (QEPCTL) ....................................................................................
eQEP Capture Control Register (QCAPCTL) .........................................................................
eQEP Position-Compare Control Register (QPOSCTL) .............................................................
eQEP Interrupt Enable Register (QEINT) .............................................................................
eQEP Interrupt Flag Register (QFLG) .................................................................................
eQEP Interrupt Clear Register (QCLR) ................................................................................
eQEP Interrupt Force Register (QFRC) ...............................................................................
eQEP Status Register (QEPSTS) ......................................................................................
eQEP Capture Timer Register (QCTMR) ..............................................................................
eQEP Capture Period Register (QCPRD) .............................................................................
eQEP Capture Timer Latch Register (QCTMRLAT) .................................................................
eQEP Capture Period Latch Register (QCPRDLAT) ................................................................
eQEP Revision ID Register (REVID) ...................................................................................
EDMA3 Controller Block Diagram ......................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram ...........................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................
List of Figures
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16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
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................................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................
PaRAM Set ................................................................................................................
Linked Transfer Example ................................................................................................
Link-to-Self Transfer Example ..........................................................................................
QDMA Channel to PaRAM Mapping ...................................................................................
Shadow Region Registers ...............................................................................................
Interrupt Diagram .........................................................................................................
Error Interrupt Operation .................................................................................................
EDMA3 Prioritization .....................................................................................................
Block Move Example .....................................................................................................
Block Move Example PaRAM Configuration ..........................................................................
Subframe Extraction Example ..........................................................................................
Subframe Extraction Example PaRAM Configuration................................................................
Data Sorting Example ....................................................................................................
Data Sorting Example PaRAM Configuration .........................................................................
Servicing Incoming McBSP Data Example ............................................................................
Servicing Incoming McBSP Data Example PaRAM ..................................................................
Servicing Peripheral Burst Example ....................................................................................
Servicing Peripheral Burst Example PaRAM..........................................................................
Servicing Continuous McBSP Data Example .........................................................................
Servicing Continuous McBSP Data Example PaRAM ...............................................................
Servicing Continuous McBSP Data Example Reload PaRAM ......................................................
Ping-Pong Buffering for McBSP Data Example ......................................................................
Ping-Pong Buffering for McBSP Example PaRAM ...................................................................
Ping-Pong Buffering for McBSP Example Pong PaRAM ............................................................
Ping-Pong Buffering for McBSP Example Ping PaRAM .............................................................
Intermediate Transfer Completion Chaining Example ...............................................................
Single Large Block Transfer Example .................................................................................
Smaller Packet Data Transfers Example ..............................................................................
Channel Options Parameter (OPT).....................................................................................
Channel Source Address Parameter (SRC) ..........................................................................
A Count/B Count Parameter (A_B_CNT) ..............................................................................
Channel Destination Address Parameter (DST) ......................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ...............................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) ......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ...............................................
C Count Parameter (CCNT) .............................................................................................
Revision ID Register (REVID) ...........................................................................................
EDMA3CC Configuration Register (CCCFG) .........................................................................
QDMA Channel n Mapping Register (QCHMAPn) ...................................................................
DMA Channel Queue Number Register n (DMAQNUMn) ...........................................................
QDMA Channel Queue Number Register (QDMAQNUM) ..........................................................
Event Missed Register (EMR)...........................................................................................
Event Missed Clear Register (EMCR) .................................................................................
QDMA Event Missed Register (QEMR)................................................................................
QDMA Event Missed Clear Register (QEMCR) ......................................................................
EDMA3CC Error Register (CCERR) ...................................................................................
Definition of ACNT, BCNT, and CCNT
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
444
445
446
447
455
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16-53. EDMA3CC Error Clear Register (CCERRCLR)....................................................................... 520
16-54. Error Evaluate Register (EEVAL) ....................................................................................... 521
16-55. DMA Region Access Enable Register for Region m (DRAEm) ..................................................... 522
16-56. QDMA Region Access Enable for Region m (QRAEm) ............................................................. 523
16-57. Event Queue Entry Registers (QxEy) .................................................................................. 524
...................................................................................
16-59. Queue Watermark Threshold A Register (QWMTHRA) .............................................................
16-60. EDMA3CC Status Register (CCSTAT) ................................................................................
16-61. Event Register (ER) ......................................................................................................
16-62. Event Clear Register (ECR) .............................................................................................
16-63. Event Set Register (ESR)................................................................................................
16-64. Chained Event Register (CER) .........................................................................................
16-65. Event Enable Register (EER) ...........................................................................................
16-66. Event Enable Clear Register (EECR) ..................................................................................
16-67. Event Enable Set Register (EESR) ....................................................................................
16-68. Secondary Event Register (SER) .......................................................................................
16-69. Secondary Event Clear Register (SECR) .............................................................................
16-70. Interrupt Enable Register (IER) .........................................................................................
16-71. Interrupt Enable Clear Register (IECR) ................................................................................
16-72. Interrupt Enable Set Register (IESR) ..................................................................................
16-73. Interrupt Pending Register (IPR)........................................................................................
16-74. Interrupt Clear Register (ICR) ...........................................................................................
16-75. Interrupt Evaluate Register (IEVAL) ....................................................................................
16-76. QDMA Event Register (QER) ...........................................................................................
16-77. QDMA Event Enable Register (QEER) ................................................................................
16-78. QDMA Event Enable Clear Register (QEECR) .......................................................................
16-79. QDMA Event Enable Set Register (QEESR) .........................................................................
16-80. QDMA Secondary Event Register (QSER) ............................................................................
16-81. QDMA Secondary Event Clear Register (QSECR) ..................................................................
16-82. Revision ID Register (REVID) ...........................................................................................
16-83. EDMA3TC Configuration Register (TCCFG) ..........................................................................
16-84. EDMA3TC Channel Status Register (TCSTAT) ......................................................................
16-85. Error Status Register (ERRSTAT) ......................................................................................
16-86. Error Enable Register (ERREN) ........................................................................................
16-87. Error Clear Register (ERRCLR) ........................................................................................
16-88. Error Details Register (ERRDET) .......................................................................................
16-89. Error Interrupt Command Register (ERRCMD) .......................................................................
16-90. Read Command Rate Register (RDRATE)............................................................................
16-91. Source Active Options Register (SAOPT) .............................................................................
16-92. Source Active Source Address Register (SASRC) ...................................................................
16-93. Source Active Count Register (SACNT) ...............................................................................
16-94. Source Active Destination Address Register (SADST) ..............................................................
16-95. Source Active B-Index Register (SABIDX) ............................................................................
16-96. Source Active Memory Protection Proxy Register (SAMPPRXY) ..................................................
16-97. Source Active Count Reload Register (SACNTRLD) ................................................................
16-98. Source Active Source Address B-Reference Register (SASRCBREF) ............................................
16-99. Source Active Destination Address B-Reference Register (SADSTBREF) .......................................
16-100. Destination FIFO Set Count Reload Register (DFCNTRLD) ......................................................
16-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) ..................................
16-58. Queue n Status Register (QSTATn)
28
List of Figures
525
526
527
529
530
531
532
533
534
534
535
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536
537
537
538
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540
541
542
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555
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560
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562
SPRUH91D – March 2013 – Revised September 2016
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www.ti.com
16-102. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) ............................. 562
16-103. Destination FIFO Options Register n (DFOPTn) .................................................................... 563
16-104. Destination FIFO Source Address Register n (DFSRCn) .......................................................... 564
16-105. Destination FIFO Count Register n (DFCNTn) ...................................................................... 564
16-106. Destination FIFO Destination Address Register n (DFDSTn) ..................................................... 565
16-107. Destination FIFO B-Index Register n (DFBIDXn) ................................................................... 565
16-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) ......................................... 566
17-1.
EMAC and MDIO Block Diagram ....................................................................................... 572
17-2.
Ethernet Configuration—MII Connections ............................................................................. 575
17-3.
Ethernet Configuration—RMII Connections ........................................................................... 577
17-4.
Ethernet Frame Format .................................................................................................. 578
17-5.
Basic Descriptor Format ................................................................................................. 579
17-6.
Typical Descriptor Linked List ........................................................................................... 580
17-7.
Transmit Buffer Descriptor Format ..................................................................................... 583
17-8.
Receive Buffer Descriptor Format ...................................................................................... 586
17-9.
EMAC Control Module Block Diagram ................................................................................. 590
17-10. MDIO Module Block Diagram ........................................................................................... 592
17-11. EMAC Module Block Diagram
..........................................................................................
596
17-12. EMAC Control Module Revision ID Register (REVID) ............................................................... 618
17-13. EMAC Control Module Software Reset Register (SOFTRESET)
..................................................
619
17-14. EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................ 620
17-15. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 621
17-16. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 622
17-17. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 623
17-18. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 624
17-19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 625
17-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 626
17-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 627
.........
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .......
MDIO Revision ID Register (REVID) ...................................................................................
MDIO Control Register (CONTROL) ...................................................................................
PHY Acknowledge Status Register (ALIVE) ..........................................................................
PHY Link Status Register (LINK) .......................................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ......................................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .....................................
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) .............................
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)............................
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ..........................
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ....................
MDIO User Access Register 0 (USERACCESS0) ...................................................................
MDIO User PHY Select Register 0 (USERPHYSEL0) ...............................................................
MDIO User Access Register 1 (USERACCESS1) ...................................................................
MDIO User PHY Select Register 1 (USERPHYSEL1) ...............................................................
Transmit Revision ID Register (TXREVID) ............................................................................
Transmit Control Register (TXCONTROL) ............................................................................
17-22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
628
629
630
631
632
633
633
634
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17-41. Transmit Teardown Register (TXTEARDOWN) ...................................................................... 648
17-42. Receive Revision ID Register (RXREVID)
............................................................................
649
17-43. Receive Control Register (RXCONTROL) ............................................................................. 649
17-44. Receive Teardown Register (RXTEARDOWN) ....................................................................... 650
17-45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)............................................... 651
17-46. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ............................................. 652
17-47. Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 653
17-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)..................................................... 654
.......................................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ...............................................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) .............................................
Receive Interrupt Mask Set Register (RXINTMASKSET) ...........................................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .....................................................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ...............................................
MAC Interrupt Mask Set Register (MACINTMASKSET) .............................................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................................
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......................
Receive Unicast Enable Set Register (RXUNICASTSET) ..........................................................
Receive Unicast Clear Register (RXUNICASTCLEAR) .............................................................
Receive Maximum Length Register (RXMAXLEN) ...................................................................
Receive Buffer Offset Register (RXBUFFEROFFSET) ..............................................................
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ..............................
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) .....................................
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ............................................
MAC Control Register (MACCONTROL) ..............................................................................
MAC Status Register (MACSTATUS) ..................................................................................
Emulation Control Register (EMCONTROL) ..........................................................................
FIFO Control Register (FIFOCONTROL) ..............................................................................
MAC Configuration Register (MACCONFIG) .........................................................................
Soft Reset Register (SOFTRESET) ....................................................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO)...................................................
MAC Source Address High Bytes Register (MACSRCADDRHI) ...................................................
MAC Hash Address Register 1 (MACHASH1) ........................................................................
MAC Hash Address Register 2 (MACHASH2) ........................................................................
Back Off Random Number Generator Test Register (BOFFTEST) ................................................
Transmit Pacing Algorithm Test Register (TPACETEST) ...........................................................
Receive Pause Timer Register (RXPAUSE) ..........................................................................
Transmit Pause Timer Register (TXPAUSE)..........................................................................
MAC Address Low Bytes Register (MACADDRLO)..................................................................
MAC Address High Bytes Register (MACADDRHI) ..................................................................
MAC Index Register (MACINDEX) .....................................................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ..........................................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) ..........................................
Transmit Channel n Completion Pointer Register (TXnCP) .........................................................
Receive Channel n Completion Pointer Register (RXnCP) .........................................................
Statistics Register .........................................................................................................
EMIFA Functional Block Diagram ......................................................................................
17-49. MAC Input Vector Register (MACINVECTOR)
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
17-88.
18-1.
30
List of Figures
655
656
657
658
659
660
661
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662
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669
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683
683
684
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685
695
SPRUH91D – March 2013 – Revised September 2016
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18-2.
Timing Waveform of SDRAM PRE Command ........................................................................ 699
18-3.
EMIFA to 2M × 16 × 4 bank SDRAM Interface ....................................................................... 700
18-4.
EMIFA to 512K × 16 × 2 bank SDRAM Interface
18-5.
Timing Waveform for Basic SDRAM Read Operation ............................................................... 707
18-6.
Timing Waveform for Basic SDRAM Write Operation
18-7.
EMIFA Asynchronous Interface ......................................................................................... 710
18-8.
EMIFA to 8-bit/16-bit Memory Interface................................................................................ 711
18-9.
Common Asynchronous Interface ...................................................................................... 711
....................................................................
...............................................................
700
708
18-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 716
18-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode .............................................. 718
18-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...................................... 720
18-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 722
18-14. EMIFA to NAND Flash Interface ........................................................................................ 724
18-15. ECC Value for 8-Bit NAND Flash ....................................................................................... 726
18-16. EMIFA Reset Block Diagram ............................................................................................ 729
18-17. EMIFA PSC Block Diagram ............................................................................................. 734
18-18. Example Configuration Interface ........................................................................................ 737
18-19. SDRAM Timing Register (SDTIMR) .................................................................................... 738
18-20. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 739
18-21. SDRAM Refresh Control Register (SDRCR) .......................................................................... 739
18-22. SDRAM Configuration Register (SDCR)............................................................................... 740
................................................................................
................................................................................
Timing Waveform of an ASRAM Read with PCB Delays............................................................
Timing Waveform of an ASRAM Write with PCB Delays ............................................................
Timing Waveform of a NAND Flash Read ............................................................................
Timing Waveform of a NAND Flash Command Write ...............................................................
Timing Waveform of a NAND Flash Address Write .................................................................
Timing Waveform of a NAND Flash Data Write .....................................................................
Module ID Register (MIDR)..............................................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) .......................................................
SDRAM Configuration Register (SDCR)...............................................................................
SDRAM Refresh Control Register (SDRCR) ..........................................................................
Asynchronous n Configuration Register (CEnCFG) ..................................................................
SDRAM Timing Register (SDTIMR) ....................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................
EMIFA Interrupt Raw Register (INTRAW) .............................................................................
EMIFA Interrupt Mask Register (INTMSK) ............................................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) ..................................................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) ................................................................
NAND Flash Control Register (NANDFCR) ...........................................................................
NAND Flash Status Register (NANDFSR) ............................................................................
NAND Flash n ECC Register (NANDFnECC) ........................................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ..................................................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..............................................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..............................................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..............................................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..............................................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1).............................................
18-23. Timing Waveform of an ASRAM Read
742
18-24. Timing Waveform of an ASRAM Write
743
18-25.
745
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
746
751
753
753
754
759
759
761
763
764
766
767
768
769
770
771
772
774
775
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18-51. NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2)............................................. 779
18-52. NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ................................................ 780
18-53. NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ................................................ 780
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
32
......................................................................................
Timing Waveform of SDRAM PRE Command ........................................................................
EMIFB to 2M × 16 × 4 bank SDRAM Interface .......................................................................
EMIFB to 2M × 32 × 4 bank SDRAM Interface .......................................................................
EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface .................................................................
Timing Waveform for Basic SDRAM Read Operation ...............................................................
Timing Waveform for Basic SDRAM Write Operation ...............................................................
EMIFB Memory Controller FIFO Block Diagram ......................................................................
EMIFB Memory Controller Reset Block Diagram .....................................................................
EMIFB Memory Controller Power and Sleep Controller Diagram ..................................................
Connecting EMIFB Memory Controller for 32-bit Connection.......................................................
Connecting EMIFB Memory Controller for 16-bit Connection.......................................................
Revision ID Register (REVID) ...........................................................................................
SDRAM Configuration Register (SDCFG) .............................................................................
SDRAM Refresh Control Register (SDRFC) ..........................................................................
SDRAM Timing 1 Register (SDTIM1) ..................................................................................
SDRAM Timing 2 Register (SDTIM2) ..................................................................................
SDRAM Configuration 2 Register (SDCFG2) .........................................................................
Peripheral Bus Burst Priority Register (BPRIO) ......................................................................
Performance Counter 1 Register (PC1) ...............................................................................
Performance Counter 2 Register (PC2) ...............................................................................
Performance Counter Configuration Register (PCC) ................................................................
Performance Counter Master Region Select Register (PCMRS) ..................................................
Performance Counter Time Register (PCT) ...........................................................................
Interrupt Raw Register (IRR) ............................................................................................
Interrupt Mask Register (IMR)...........................................................................................
Interrupt Mask Set Register (IMSR) ....................................................................................
Interrupt Mask Clear Register (IMCR) .................................................................................
GPIO Block Diagram .....................................................................................................
Revision ID Register (REVID) ...........................................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) ................................................................
GPIO Banks 0 and 1 Direction Register (DIR01) .....................................................................
GPIO Banks 2 and 3 Direction Register (DIR23) .....................................................................
GPIO Banks 4 and 5 Direction Register (DIR45) .....................................................................
GPIO Banks 6 and 7 Direction Register (DIR67) .....................................................................
GPIO Bank 8 Direction Register (DIR8) ...............................................................................
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) .......................................................
GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) .......................................................
GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) .......................................................
GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) .......................................................
GPIO Bank 8 Output Data Register (OUT_DATA8) .................................................................
GPIO Banks 0 and 1 Set Data Register (SET_DATA01)............................................................
GPIO Banks 2 and 3 Set Data Register (SET_DATA23)............................................................
GPIO Banks 4 and 5 Set Data Register (SET_DATA45)............................................................
GPIO Banks 6 and 7 Set Data Register (SET_DATA67)............................................................
GPIO Bank 8 Set Data Register (SET_DATA8) ......................................................................
EMIFB Functional Block Diagram
List of Figures
782
785
786
786
787
795
796
799
802
803
806
806
809
810
812
813
814
815
816
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837
837
837
838
839
839
839
839
840
841
841
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841
842
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
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20-19. GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) ......................................................... 843
20-20. GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) ......................................................... 843
20-21. GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) ......................................................... 843
20-22. GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) ......................................................... 843
20-23. GPIO Bank 8 Clear Data Register (CLR_DATA8)
...................................................................
844
20-24. GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ............................................................ 845
20-25. GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ............................................................ 845
20-26. GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ............................................................ 845
20-27. GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ............................................................ 845
20-28. GPIO Bank 8 Input Data Register (IN_DATA8)....................................................................... 846
20-29. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01) ............................................. 847
20-30. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) ............................................. 847
20-31. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) ............................................. 847
20-32. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) ............................................. 847
20-33. GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) ........................................................ 848
20-34. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ........................................... 849
20-35. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) ........................................... 849
20-36. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ........................................... 849
20-37. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ........................................... 849
20-38. GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) ..................................................... 850
20-39. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) ............................................. 851
20-40. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) ............................................. 851
20-41. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) ............................................. 851
20-42. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) ............................................. 851
20-43. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8) ....................................................... 852
20-44. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) .......................................... 853
20-45. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) .......................................... 853
20-46. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) .......................................... 853
20-47. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) .......................................... 853
20-48. GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) ..................................................... 854
20-49. GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ...................................................... 855
20-50. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ...................................................... 855
20-51. GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) ...................................................... 855
20-52. GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) ...................................................... 855
20-53. GPIO Bank 8 Interrupt Status Register (INTSTAT8) ................................................................. 856
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
.......................................................................................................
Example of Host-Processor Signal Connections .....................................................................
HPI Strobe and Select Logic ............................................................................................
Multiplexed-Mode Host Read Cycle ....................................................................................
Multiplexed-Mode Host Write Cycle ....................................................................................
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) ...................................................
UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode .........................
HPI Block Diagram
859
864
866
868
869
870
871
21-8.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle) .......................................................... 871
21-9.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles) .............................................................. 871
21-10. UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode ................................... 872
21-11. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1:
No Autoincrementing) .................................................................................................... 872
21-12. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2:
SPRUH91D – March 2013 – Revised September 2016
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Autoincrementing Selected, FIFO Empty Before Write) ............................................................. 872
21-13. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 3:
Autoincrementing Selected, FIFO Not Empty Before Write) ........................................................ 873
21-14. FIFOs in the HPI .......................................................................................................... 874
21-15. Host-to-CPU Interrupt State Diagram .................................................................................. 879
21-16. CPU-to-Host Interrupt State Diagram .................................................................................. 880
21-17. Revision Identification Register (REVID) .............................................................................. 882
................................................
GPIO Enable Register (GPIO_EN) .....................................................................................
GPIO Direction 1 Register (GPIO_DIR1) ..............................................................................
GPIO Data 1 Register (GPIO_DAT1) ..................................................................................
GPIO Direction 2 Register (GPIO_DIR2) ..............................................................................
GPIO Data 2 Register (GPIO_DAT2) ..................................................................................
Host Port Interface Control Register (HPIC)–Host Access Permissions ..........................................
Host Port Interface Control Register (HPIC)–CPU Access Permissions ..........................................
Host Port Interface Write Address Register (HPIAW)................................................................
Host Port Interface Read Address Register (HPIAR) ................................................................
I2C Peripheral Block Diagram...........................................................................................
Multiple I2C Modules Connected .......................................................................................
Clocking Diagram for the I2C Peripheral ..............................................................................
Synchronization of Two I2C Clock Generators During Arbitration .................................................
Bit Transfer on the I2C-Bus .............................................................................................
I2C Peripheral START and STOP Conditions ........................................................................
I2C Peripheral Data Transfer ............................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) ............................................
21-18. Power and Emulation Management Register (PWREMU_MGMT)
882
21-19.
883
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
884
884
885
886
887
887
889
889
892
893
894
895
896
896
897
897
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR)......................................................................................................... 898
22-10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR) .............................................................. 898
22-11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR)
...
898
22-12. Arbitration Procedure Between Two Master-Transmitters........................................................... 901
22-13. I2C Own Address Register (ICOAR) ................................................................................... 906
22-14. I2C Interrupt Mask Register (ICIMR) ................................................................................... 907
22-15. I2C Interrupt Status Register (ICSTR) ................................................................................. 908
22-16. I2C Clock Low-Time Divider Register (ICCLKL) ...................................................................... 911
22-17. I2C Clock High-Time Divider Register (ICCLKH) ..................................................................... 911
22-18. I2C Data Count Register (ICCNT) ...................................................................................... 912
22-19. I2C Data Receive Register (ICDRR) ................................................................................... 913
22-20. I2C Slave Address Register (ICSAR) .................................................................................. 914
22-21. I2C Data Transmit Register (ICDXR)
..................................................................................
915
22-22. I2C Mode Register (ICMDR) ............................................................................................ 916
22-23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit .................................... 919
22-24. I2C Interrupt Vector Register (ICIVR) .................................................................................. 920
22-25. I2C Extended Mode Register (ICEMDR) .............................................................................. 921
22-26. I2C Prescaler Register (ICPSC) ........................................................................................ 922
923
22-28. I2C Revision Identification Register 2 (REVID2)
923
22-29.
924
22-30.
22-31.
34
.....................................................................
.....................................................................
I2C DMA Control Register (ICDMAC) ..................................................................................
I2C Pin Function Register (ICPFUNC) .................................................................................
I2C Pin Direction Register (ICPDIR) ...................................................................................
22-27. I2C Revision Identification Register 1 (REVID1)
List of Figures
925
926
SPRUH91D – March 2013 – Revised September 2016
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22-32. I2C Pin Data In Register (ICPDIN) ..................................................................................... 927
22-33. I2C Pin Data Out Register (ICPDOUT) ................................................................................ 928
22-34. I2C Pin Data Set Register (ICPDSET) ................................................................................. 929
22-35. I2C Pin Data Clear Register (ICPDCLR) .............................................................................. 930
............................................................................................................
23-1.
LCD Controller
23-2.
Input and Output Clocks ................................................................................................. 933
23-3.
Logical Data Path for Raster Controller ................................................................................ 940
23-4.
Frame Buffer Structure ................................................................................................... 941
23-5.
16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP) ................................................................ 942
23-6.
256-Entry Palette/Buffer Format (8 BPP) .............................................................................. 943
23-7.
16-BPP Data Memory Organization (TFT Mode Only)—Little Endian ............................................. 943
23-8.
12-BPP Data Memory Organization—Little Endian .................................................................. 944
23-9.
8-BPP Data Memory Organization
....................................................................................
932
944
23-10. 4-BPP Data Memory Organization ..................................................................................... 944
23-11. 2-BPP Data Memory Organization ..................................................................................... 945
23-12. 1-BPP Data Memory Organization ..................................................................................... 945
23-13. Monochrome and Color Output ......................................................................................... 947
23-14. Raster Mode Display Format ............................................................................................ 948
23-15. LCD Revision Identification Register (REVID) ........................................................................ 949
23-16. LCD Control Register (LCD_CTRL) .................................................................................... 950
23-17. LCD Status Register (LCD_STAT) ..................................................................................... 952
23-18. LCD LIDD Control Register (LIDD_CTRL) ............................................................................ 955
23-19. LCD LIDD CSn Configuration Register (LIDD_CSn_CONF)........................................................ 957
...............................................
LCD LIDD CSn Data Read/Write Register (LIDD_CSn_DATA) ....................................................
LCD Raster Control Register (RASTER_CTRL) ......................................................................
Monochrome Passive Mode Pixel Clock and Data Pin Timing .....................................................
Color Passive Mode Pixel Clock and Data Pin Timing ..............................................................
Active Mode Pixel Clock and Data Pin Timing ........................................................................
TFT Alternate Signal Mapping Output .................................................................................
12-Bit STN Data in Frame Buffer .......................................................................................
16-Bit STN Data in Frame Buffer .......................................................................................
16-BPP STN Mode .......................................................................................................
LCD Raster Timing Register 0 (RASTER_TIMING_0)...............................................................
LCD Raster Timing Register 1 (RASTER_TIMING_1)...............................................................
Vertical Synchronization Pulse Width (VSW) - Active Mode ........................................................
Vertical Front Porch (VFP) ..............................................................................................
Vertical Back Porch (VBP) ...............................................................................................
LCD Raster Timing Register 2 (RASTER_TIMING_2)...............................................................
SYNC_CTRL = 0, IPC = 1 in TFT Mode...............................................................................
SYNC_CTRL = 1, SYNC_EDGE = 0, and IPC = 1...................................................................
LCD Raster Subpanel Display Register (RASTER_SUBPANEL) ..................................................
Subpanel Display: SPEN = 1, HOLS = 1 .............................................................................
Subpanel Display: SPEN = 1, HOLS = 0 .............................................................................
LCD DMA Control Register (LCDDMA_CTRL) .......................................................................
LCD DMA Frame Buffer n Base Address Register (LCDDMA_FBn_BASE) .....................................
LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) ................................
McASP Block Diagram ...................................................................................................
McASP to Parallel 2-Channel DACs ..................................................................................
23-20. LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR)
958
23-21.
959
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
24-1.
24-2.
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
960
963
963
964
965
966
966
966
967
969
970
971
972
973
975
976
977
978
978
979
980
980
984
985
35
www.ti.com
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
24-51.
36
..................................................................... 985
McASP to Digital Amplifier ............................................................................................... 986
McASP as Digital Audio Encoder ...................................................................................... 986
TDM Format–6 Channel TDM Example ............................................................................... 987
TDM Format Bit Delays from Frame Sync ............................................................................ 988
Inter-IC Sound (I2S) Format ............................................................................................. 988
Biphase-Mark Code (BMC) .............................................................................................. 989
S/PDIF Subframe Format ................................................................................................ 990
S/PDIF Frame Format .................................................................................................... 991
Definition of Bit, Word, and Slot ........................................................................................ 992
Bit Order and Word Alignment Within a Slot Examples ............................................................. 993
Definition of Frame and Frame Sync Width ........................................................................... 994
Transmit Clock Generator Block Diagram ............................................................................. 996
Receive Clock Generator Block Diagram .............................................................................. 997
Frame Sync Generator Block Diagram ............................................................................... 998
Individual Serializer and Connections Within McASP ................................................................ 999
Receive Format Unit .................................................................................................... 1000
Transmit Format Unit ................................................................................................... 1001
McASP I/O Pin Control Block Diagram ............................................................................... 1003
McASP I/O Pin to Control Register Mapping ........................................................................ 1004
Burst Frame Sync Mode................................................................................................ 1009
Transmit DMA Event (AXEVT) Generation in TDM Time Slots ................................................... 1012
DSP Service Time Upon Transmit DMA Event (AXEVT) .......................................................... 1017
DSP Service Time Upon Receive DMA Event (AREVT) ........................................................... 1018
DMA Events in an Audio Example–Two Events .................................................................... 1020
McASP Audio FIFO (AFIFO) Block Diagram ........................................................................ 1021
Data Flow Through Transmit Format Unit ........................................................................... 1024
Data Flow Through Receive Format Unit ............................................................................ 1026
Audio Mute (AMUTE) Block Diagram ................................................................................. 1028
Transmit Clock Failure Detection Circuit Block Diagram ........................................................... 1032
Receive Clock Failure Detection Circuit Block Diagram ........................................................... 1033
Serializers in Loopback Mode ......................................................................................... 1034
Revision Identification Register (REV) ............................................................................... 1040
Pin Function Register (PFUNC) ....................................................................................... 1041
Pin Direction Register (PDIR).......................................................................................... 1043
Pin Data Output Register (PDOUT)................................................................................... 1045
Pin Data Input Register (PDIN) ........................................................................................ 1047
Pin Data Set Register (PDSET) ....................................................................................... 1049
Pin Data Clear Register (PDCLR)..................................................................................... 1051
Global Control Register (GBLCTL).................................................................................... 1053
Audio Mute Control Register (AMUTE) ............................................................................... 1055
Digital Loopback Control Register (DLBCTL) ....................................................................... 1057
Digital Mode Control Register (DITCTL) ............................................................................. 1058
Receiver Global Control Register (RGBLCTL) ...................................................................... 1059
Receive Format Unit Bit Mask Register (RMASK) .................................................................. 1060
Receive Bit Stream Format Register (RFMT) ....................................................................... 1061
Receive Frame Sync Control Register (AFSRCTL) ................................................................ 1063
Receive Clock Control Register (ACLKRCTL) ...................................................................... 1064
Receive High-Frequency Clock Control Register (AHCLKRCTL) ................................................ 1065
McASP to 6-Channel DAC and 2-Channel DAC
List of Figures
SPRUH91D – March 2013 – Revised September 2016
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24-52. Receive TDM Time Slot Register (RTDM) ........................................................................... 1066
24-53. Receiver Interrupt Control Register (RINTCTL) ..................................................................... 1067
...................................................................................
..............................................................
Receive Clock Check Control Register (RCLKCHK) ...............................................................
Receiver DMA Event Control Register (REVTCTL) ................................................................
Transmitter Global Control Register (XGBLCTL) ...................................................................
Transmit Format Unit Bit Mask Register (XMASK) .................................................................
Transmit Bit Stream Format Register (XFMT) .......................................................................
Transmit Frame Sync Control Register (AFSXCTL) ................................................................
Transmit Clock Control Register (ACLKXCTL) ......................................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ................................................
Transmit TDM Time Slot Register (XTDM) ..........................................................................
Transmitter Interrupt Control Register (XINTCTL) ..................................................................
Transmitter Status Register (XSTAT).................................................................................
Current Transmit TDM Time Slot Register (XSLOT) ...............................................................
Transmit Clock Check Control Register (XCLKCHK)...............................................................
Transmitter DMA Event Control Register (XEVTCTL)..............................................................
Serializer Control Registers (SRCTLn) ...............................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .....................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ....................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5).................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ...............................................
Transmit Buffer Registers (XBUFn) ...................................................................................
Receive Buffer Registers (RBUFn) ...................................................................................
AFIFO Revision Identification Register (AFIFOREV) ...............................................................
Write FIFO Control Register (WFIFOCTL) ...........................................................................
Write FIFO Status Register (WFIFOSTS) ............................................................................
Read FIFO Control Register (RFIFOCTL) ...........................................................................
Read FIFO Status Register (RFIFOSTS) ............................................................................
MMC/SD Card Controller Block Diagram ............................................................................
MMC/SD Controller Interface Diagram ...............................................................................
MMC Configuration and SD Configuration Diagram ................................................................
MMC/SD Controller Clocking Diagram ...............................................................................
MMC/SD Mode Write Sequence Timing Diagram ..................................................................
MMC/SD Mode Read Sequence Timing Diagram ..................................................................
FIFO Operation Diagram ...............................................................................................
Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA......................................
FIFO Operation During Card Read Diagram ........................................................................
FIFO Operation During Card Write Diagram ........................................................................
MMC Card Identification Procedure ..................................................................................
SD Card Identification Procedure .....................................................................................
MMC/SD Mode Single-Block Write Operation .......................................................................
MMC/SD Mode Single-Block Read Operation.......................................................................
MMC/SD Multiple-Block Write Operation ............................................................................
MMC/SD Mode Multiple-Block Read Operation .....................................................................
MMC Control Register (MMCCTL) ....................................................................................
MMC Memory Clock Control Register (MMCCLK)..................................................................
MMC Status Register 0 (MMCST0) ...................................................................................
24-54. Receiver Status Register (RSTAT)
1068
24-55. Current Receive TDM Time Slot Registers (RSLOT)
1069
24-56.
1070
24-57.
24-58.
24-59.
24-60.
24-61.
24-62.
24-63.
24-64.
24-65.
24-66.
24-67.
24-68.
24-69.
24-70.
24-71.
24-72.
24-73.
24-74.
24-75.
24-76.
24-77.
24-78.
24-79.
24-80.
24-81.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
1071
1072
1073
1074
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1086
1087
1087
1088
1088
1089
1090
1091
1092
1093
1095
1096
1097
1098
1099
1100
1101
1102
1104
1106
1113
1114
1116
1118
1120
1122
1125
1126
1127
37
www.ti.com
25-20. MMC Status Register 1 (MMCST1) ................................................................................... 1129
25-21. MMC Interrupt Mask Register (MMCIM)
.............................................................................
1130
25-22. MMC Response Time-Out Register (MMCTOR) .................................................................... 1132
25-23. MMC Data Read Time-Out Register (MMCTOD) ................................................................... 1133
25-24. MMC Block Length Register (MMCBLEN) ........................................................................... 1134
25-25. MMC Number of Blocks Register (MMCNBLK) ..................................................................... 1135
25-26. MMC Number of Blocks Counter Register (MMCNBLC) ........................................................... 1135
25-27. MMC Data Receive Register (MMCDRR)............................................................................ 1136
25-28. MMC Data Transmit Register (MMCDXR) ........................................................................... 1136
25-29. MMC Command Register (MMCCMD) ............................................................................... 1137
25-30. Command Format ....................................................................................................... 1138
25-31. MMC Argument Register (MMCARGHL) ............................................................................. 1139
25-32. MMC Response Register 0 and 1 (MMCRSP01) ................................................................... 1140
25-33. MMC Response Register 2 and 3 (MMCRSP23) ................................................................... 1140
25-34. MMC Response Register 4 and 5 (MMCRSP45) ................................................................... 1140
25-35. MMC Response Register 6 and 7 (MMCRSP67) ................................................................... 1140
1142
25-37. MMC Command Index Register (MMCCIDX)
1142
25-38.
1143
25-39.
25-40.
25-41.
25-42.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
27-1.
27-2.
38
.......................................................................
.......................................................................
SDIO Control Register (SDIOCTL)....................................................................................
SDIO Status Register 0 (SDIOST0) ..................................................................................
SDIO Interrupt Enable Register (SDIOIEN)..........................................................................
SDIO Interrupt Status Register (SDIOIST) ...........................................................................
MMC FIFO Control Register (MMCFIFOCTL) .......................................................................
Real-Time Clock Block Diagram ......................................................................................
32-kHz Oscillator Counter Compensation............................................................................
Kick State Machine......................................................................................................
Second Register (SECOND) ...........................................................................................
Minute Register (MINUTE) .............................................................................................
Hour Register (HOUR)..................................................................................................
Days Register (DAY) ....................................................................................................
Month Register (MONTH) ..............................................................................................
Year Register (YEAR) ..................................................................................................
Day of the Week Register (DOTW) ...................................................................................
Alarm Second Register (ALARMSECOND) .........................................................................
Alarm Minute Register (ALARMMINUTE) ............................................................................
Alarm Hour Register (ALARMHOUR) ................................................................................
Alarm Day Register (ALARMDAY) ....................................................................................
Alarm Month Register (ALARMMONTH) .............................................................................
Alarm Year Register (ALARMYEAR) .................................................................................
Control Register (CTRL)................................................................................................
Status Register (STATUS) .............................................................................................
Interrupt Register (INTERRUPT) ......................................................................................
Compensation (LSB) Register (COMPLSB) .........................................................................
Compensation (MSB) Register (COMPMSB)........................................................................
Oscillator Register (OSC) ..............................................................................................
Scratch Registers (SCRATCHn) ......................................................................................
Kick Registers (KICKnR) ...............................................................................................
SPI Block Diagram ......................................................................................................
SPI 3-Pin Option.........................................................................................................
25-36. MMC Data Response Register (MMCDRSP)
List of Figures
1144
1145
1145
1146
1148
1152
1153
1156
1156
1157
1158
1158
1159
1159
1160
1160
1161
1162
1163
1163
1164
1165
1166
1167
1168
1169
1170
1170
1173
1179
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
27-28.
27-29.
27-30.
27-31.
27-32.
27-33.
27-34.
27-35.
27-36.
27-37.
27-38.
27-39.
27-40.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
..................................................................................
SPI 4-Pin Option with SPIx_ENA .....................................................................................
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ...............................................................
Format for Transmitting 12-Bit Word..................................................................................
Format for 10-Bit Received Word .....................................................................................
Clock Mode with POLARITY = 0 and PHASE = 0 ..................................................................
Clock Mode with POLARITY = 0 and PHASE = 1 ..................................................................
Clock Mode with POLARITY = 1 and PHASE = 0 ..................................................................
Clock Mode with POLARITY = 1 and PHASE = 1 ..................................................................
Five Bits per Character (5-Pin Option) ...............................................................................
SPI 3-Pin Master Mode with WDELAY ...............................................................................
SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY .............................
SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY ....................................
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY .......................................
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY ....................................................
SPI Global Control Register 0 (SPIGCR0) ...........................................................................
SPI Global Control Register 1 (SPIGCR1) ...........................................................................
SPI Interrupt Register (SPIINT0) ......................................................................................
SPI Interrupt Level Register (SPILVL) ................................................................................
SPI Flag Register (SPIFLG) ...........................................................................................
SPI Pin Control Register 0 (SPIPC0) .................................................................................
SPI Pin Control Register 1 (SPIPC1) .................................................................................
SPI Pin Control Register 2 (SPIPC2) .................................................................................
SPI Pin Control Register 3 (SPIPC3) .................................................................................
SPI Pin Control Register 4 (SPIPC4) .................................................................................
SPI Pin Control Register 5 (SPIPC5) .................................................................................
SPI Data Register 0 (SPIDAT0) .......................................................................................
SPI Data Register 1 (SPIDAT1) .......................................................................................
SPI Buffer Register (SPIBUF) .........................................................................................
SPI Emulation Register (SPIEMU) ....................................................................................
SPI Delay Register (SPIDELAY) ......................................................................................
Example: tC2TDELAY = 8 SPI Module Clock Cycles ....................................................................
Example: tT2CDELAY = 4 SPI Module Clock Cycles ....................................................................
Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout ...........................................................
Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout...........................................................
SPI Default Chip Select Register (SPIDEF) .........................................................................
SPI Data Format Register (SPIFMTn) ................................................................................
SPI Interrupt Vector Register 1 (INTVEC1) ..........................................................................
Timer Block Diagram ...................................................................................................
Timer Clock Source Block Diagram...................................................................................
64-Bit Timer Mode Block Diagram ....................................................................................
Dual 32-Bit Timers Chained Mode Block Diagram .................................................................
Dual 32-Bit Timers Chained Mode Example .........................................................................
Dual 32-Bit Timers Unchained Mode Block Diagram ...............................................................
Dual 32-Bit Timers Unchained Mode Example ......................................................................
32-Bit Timer Counter Overflow Example .............................................................................
Watchdog Timer Mode Block Diagram ...............................................................................
Watchdog Timer Operation State Diagram ..........................................................................
Timer Operation in Pulse Mode (CPn = 0) ...........................................................................
SPI 4-Pin Option with SPIx_SCS[n]
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
1181
1183
1185
1186
1186
1187
1188
1188
1188
1189
1194
1195
1196
1198
1199
1200
1201
1203
1205
1206
1208
1209
1210
1211
1212
1213
1214
1215
1216
1218
1219
1220
1221
1221
1221
1222
1223
1225
1228
1229
1230
1233
1233
1235
1236
1239
1241
1241
1243
39
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28-12. Timer Operation in Clock Mode (CPn = 1) ........................................................................... 1243
28-13. Revision ID Register (REVID) ......................................................................................... 1247
28-14. Emulation Management Register (EMUMGT) ....................................................................... 1247
28-15. GPIO Interrupt Control and Enable Register (GPINTGPEN) ...................................................... 1248
28-16. GPIO Data and Direction Register (GPDATGPDIR)
...............................................................
1249
28-17. Timer Counter Register 12 (TIM12)................................................................................... 1250
28-18. Timer Counter Register 34 (TIM34)................................................................................... 1250
28-19. Timer Period Register 12 (PRD12) ................................................................................... 1251
28-20. Timer Period Register 34 (PRD34) ................................................................................... 1251
28-21. Timer Control Register (TCR)
.........................................................................................
1252
28-22. Timer Global Control Register (TGCR) ............................................................................... 1254
28-23. Watchdog Timer Control Register (WDTCR) ........................................................................ 1255
28-24. Timer Reload Register 12 (REL12) ................................................................................... 1256
28-25. Timer Reload Register 34 (REL34) ................................................................................... 1256
28-26. Timer Capture Register 12 (CAP12) .................................................................................. 1257
28-27. Timer Capture Register 34 (CAP34) .................................................................................. 1257
28-28. Timer Interrupt Control and Status Register (INTCTLSTAT) ...................................................... 1258
28-29. Timer Compare Register (CMPn) ..................................................................................... 1259
29-1.
UART Block Diagram ................................................................................................... 1262
29-2.
UART Clock Generation Diagram ..................................................................................... 1263
29-3.
Relationships Between Data Bit, BCLK, and UART Input Clock .................................................. 1264
29-4.
UART Protocol Formats ................................................................................................ 1266
29-5.
UART Interface Using Autoflow Diagram ............................................................................ 1269
29-6.
Autoflow Functional Timing Waveforms for UARTn_RTS
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
40
........................................................
Autoflow Functional Timing Waveforms for UARTn_CTS ........................................................
UART Interrupt Request Enable Paths ...............................................................................
Receiver Buffer Register (RBR) .......................................................................................
Transmitter Holding Register (THR) ..................................................................................
Interrupt Enable Register (IER)........................................................................................
Interrupt Identification Register (IIR) ..................................................................................
FIFO Control Register (FCR) ..........................................................................................
Line Control Register (LCR) ...........................................................................................
Modem Control Register (MCR) .......................................................................................
Line Status Register (LSR).............................................................................................
Modem Status Register (MSR) ........................................................................................
Scratch Pad Register (SCR) ...........................................................................................
Divisor LSB Latch (DLL) ................................................................................................
Divisor MSB Latch (DLH) ..............................................................................................
Revision Identification Register 1 (REVID1) .........................................................................
Revision Identification Register 2 (REVID2) .........................................................................
Power and Emulation Management Register (PWREMU_MGMT) ...............................................
Mode Definition Register (MDR) ......................................................................................
Relationships Between Virtual Address Physical Address.........................................................
OHCI Revision Number Register (HCREVISION) ..................................................................
HC Operating Mode Register (HCCONTROL) ......................................................................
HC Command and Status Register (HCCOMMANDSTATUS) ....................................................
HC Interrupt and Status Register (HCINTERRUPTSTATUS) .....................................................
HC Interrupt Enable Register (HCINTERRUPTENABLE) .........................................................
HC Interrupt Disable Register (HCINTERRUPTDISABLE) ........................................................
List of Figures
1270
1270
1272
1275
1276
1277
1278
1280
1281
1283
1284
1287
1288
1289
1289
1290
1290
1291
1292
1298
1300
1300
1302
1303
1304
1305
SPRUH91D – March 2013 – Revised September 2016
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30-8.
HC HCAA Address Register (HCHCCA) ............................................................................. 1306
30-9.
HC Current Periodic Register (HCPERIODCURRENTED) ........................................................ 1306
30-10. HC Head Control Register (HCCONTROLHEADED) .............................................................. 1307
30-11. HC Current Control Register (HCCONTROLCURRENTED) ...................................................... 1307
30-12. HC Head Bulk Register (HCBULKHEADED) ........................................................................ 1308
30-13. HC Current Bulk Register (HCBULKCURRENTED) ................................................................ 1308
30-14. HC Head Done Register (HCDONEHEAD) .......................................................................... 1309
30-15. HC Frame Interval Register (HCFMINTERVAL) .................................................................... 1309
30-16. HC Frame Remaining Register (HCFMREMAINING) .............................................................. 1310
30-17. HC Frame Number Register (HCFMNUMBER) ..................................................................... 1310
30-18. HC Periodic Start Register (HCPERIODICSTART)................................................................. 1311
30-19. HC Low-Speed Threshold Register (HCLSTHRESHOLD)
........................................................
1311
30-20. HC Root Hub A Register (HCRHDESCRIPTORA) ................................................................. 1312
30-21. HC Root Hub B Register (HCRHDESCRIPTORB) ................................................................. 1313
30-22. HC Root Hub Status Register (HCRHSTATUS) .................................................................... 1314
30-23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) ................................................. 1315
30-24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2) ................................................. 1317
31-1.
Functional Block Diagram .............................................................................................. 1320
31-2.
USB Clocking Diagram ................................................................................................. 1321
31-3.
Interrupt Service Routine Flow Chart ................................................................................. 1326
31-4.
CPU Actions at Transfer Phases ...................................................................................... 1331
31-5.
Sequence of Transfer ................................................................................................... 1331
31-6.
Service Endpoint 0 Flow Chart ........................................................................................ 1333
31-7.
IDLE Mode Flow Chart ................................................................................................. 1334
31-8.
TX Mode Flow Chart .................................................................................................... 1335
31-9.
RX Mode Flow Chart.................................................................................................... 1336
31-10. Setup Phase of a Control Transaction Flow Chart.................................................................. 1346
31-11. IN Data Phase Flow Chart ............................................................................................. 1348
31-12. OUT Data Phase Flow Chart .......................................................................................... 1350
31-13. Completion of SETUP or OUT Data Phase Flow Chart ............................................................ 1352
31-14. Completion of IN Data Phase Flow Chart ............................................................................ 1354
31-15. USB Controller Block Diagram ........................................................................................ 1361
31-16. Host Packet Descriptor Layout ........................................................................................ 1364
31-17. Host Buffer Descriptor Layout ......................................................................................... 1367
31-18. Teardown Descriptor Layout ........................................................................................... 1369
31-19. Relationship Between Memory Regions and Linking RAM ........................................................ 1372
31-20. High-Level Transmit and Receive Data Transfer Example ........................................................ 1378
31-21. Transmit Descriptors and Queue Status Configuration ............................................................ 1379
31-22. Transmit USB Data Flow Example (Initialization) ................................................................... 1380
31-23. Transmit USB Data Flow Example (Completion)
...................................................................
1381
31-24. Receive Descriptors and Queue Status Configuration ............................................................. 1382
31-25. Receive USB Data Flow Example (Initialization) .................................................................... 1382
31-26. Receive USB Data Flow Example (Completion) .................................................................... 1383
31-27. Revision Identification Register (REVID) ............................................................................. 1407
31-28. Control Register (CTRLR) .............................................................................................. 1407
31-29. Status Register (STATR) ............................................................................................... 1408
...........................................................................................
................................................................................................
Auto Request Register (AUTOREQ)..................................................................................
31-30. Emulation Register (EMUR)
1408
31-31. Mode Register (MODE)
1409
31-32.
1411
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
41
www.ti.com
..............................................................................
Teardown Register (TEARDOWN)....................................................................................
USB Interrupt Source Register (INTSRCR)..........................................................................
USB Interrupt Source Set Register (INTSETR) .....................................................................
USB Interrupt Source Clear Register (INTCLRR) ...................................................................
USB Interrupt Mask Register (INTMSKR)............................................................................
USB Interrupt Mask Set Register (INTMSKSETR) .................................................................
USB Interrupt Mask Clear Register (INTMSKCLRR) ...............................................................
USB Interrupt Source Masked Register (INTMASKEDR) ..........................................................
USB End of Interrupt Register (EOIR) ................................................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1)..............................................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2)..............................................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3)..............................................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4)..............................................................
Function Address Register (FADDR) .................................................................................
Power Management Register (POWER) .............................................................................
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ...........................................
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ........................................................
Interrupt Enable Register for INTRTX (INTRTXE) ..................................................................
Interrupt Enable Register for INTRRX (INTRRXE) .................................................................
Interrupt Register for Common USB Interrupts (INTRUSB) .......................................................
Interrupt Enable Register for INTRUSB (INTRUSBE) ..............................................................
Frame Number Register (FRAME) ....................................................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX) .............................
Register to Enable the USB 2.0 Test Modes (TESTMODE) ......................................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ......................................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ......................................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...........................................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .....................................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...........................................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP).......................................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ......................................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...........................................
Count 0 Register (COUNT0) ...........................................................................................
Receive Count Register (RXCOUNT) ................................................................................
Type Register (Host mode only) (HOST_TYPE0) ..................................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) .....................................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ......................................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ............................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .....................................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL).............................................
Configuration Data Register (CONFIGDATA) .......................................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .....................................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .....................................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .....................................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .....................................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .....................................................
Device Control Register (DEVCTL) ...................................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ) ..........................................................................
31-33. SRP Fix Time Register (SRPFIXTIME)
31-34.
31-35.
31-36.
31-37.
31-38.
31-39.
31-40.
31-41.
31-42.
31-43.
31-44.
31-45.
31-46.
31-47.
31-48.
31-49.
31-50.
31-51.
31-52.
31-53.
31-54.
31-55.
31-56.
31-57.
31-58.
31-59.
31-60.
31-61.
31-62.
31-63.
31-64.
31-65.
31-66.
31-67.
31-68.
31-69.
31-70.
31-71.
31-72.
31-73.
31-74.
31-75.
31-76.
31-77.
31-78.
31-79.
31-80.
31-81.
42
List of Figures
1412
1412
1413
1414
1415
1416
1417
1418
1419
1420
1420
1421
1421
1422
1422
1423
1424
1425
1426
1426
1427
1428
1428
1429
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1438
1439
1439
1440
1440
1441
1442
1443
1444
1444
1445
1445
1446
1446
1447
SPRUH91D – March 2013 – Revised September 2016
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31-82. Receive Endpoint FIFO Size (RXFIFOSZ) ........................................................................... 1447
31-83. Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................. 1448
31-84. Receive Endpoint FIFO Address (RXFIFOADDR) .................................................................. 1448
31-85. Hardware Version Register (HWVERS) .............................................................................. 1449
31-86. Transmit Function Address (TXFUNCADDR) ....................................................................... 1450
..............................................................................
31-88. Transmit Hub Port (TXHUBPORT)....................................................................................
31-89. Receive Function Address (RXFUNCADDR) ........................................................................
31-90. Receive Hub Address (RXHUBADDR) ...............................................................................
31-91. Receive Hub Port (RXHUBPORT) ....................................................................................
31-92. CDMA Revision Identification Register (DMAREVID) ..............................................................
31-93. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ...........................................
31-94. CDMA Emulation Control Register (DMAEMU) .....................................................................
31-95. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) ........................................
31-96. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) ........................................
31-97. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) ....................................
31-98. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) ....................................
31-99. CDMA Scheduler Control Register (DMA_SCHED_CTRL) .......................................................
31-100. CDMA Scheduler Table Word n Registers (WORD[n]) ...........................................................
31-101. Queue Manager Revision Identification Register (QMGRREVID) ...............................................
31-102. Queue Manager Queue Diversion Register (DIVERSION).......................................................
31-103. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) .............................
31-104. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) .............................
31-105. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) .............................
31-106. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) .............................
31-107. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) .............................
31-108. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .........................................
31-109. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) .............................
31-110. Queue Manager Queue Pending Register 0 (PEND0) ...........................................................
31-111. Queue Manager Queue Pending Register 1 (PEND1) ...........................................................
31-112. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) ............................
31-113. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) ....................................
31-114. Queue Manager Queue N Control Register D (CTRLD[N]) ......................................................
31-115. Queue Manager Queue N Status Register A (QSTATA[N]) .....................................................
31-116. Queue Manager Queue N Status Register B (QSTATB[N]) .....................................................
31-117. Queue Manager Queue N Status Register C (QSTATC[N]) .....................................................
31-87. Transmit Hub Address (TXHUBADDR)
SPRUH91D – March 2013 – Revised September 2016
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List of Figures
1450
1450
1451
1451
1451
1452
1452
1453
1453
1454
1455
1456
1457
1457
1459
1459
1460
1461
1462
1463
1463
1464
1464
1465
1465
1466
1467
1468
1469
1469
1470
43
www.ti.com
List of Tables
2-1.
DSP Interrupt Map ......................................................................................................... 70
3-1.
TMS320C6745/C6747 DSP System Interconnect Matrix ............................................................. 77
5-1.
MPU Memory Regions..................................................................................................... 84
5-2.
MPU Default Configuration................................................................................................ 84
5-3.
Device Master Settings .................................................................................................... 85
5-4.
Request Type Access Controls........................................................................................... 86
5-5.
MPU_BOOTCFG_ERR Interrupt Sources .............................................................................. 88
5-6.
Memory Protection Unit 1 (MPU1) Registers ........................................................................... 89
5-7.
Memory Protection Unit 2 (MPU2) Registers ........................................................................... 89
5-8.
Revision ID Register (REVID) Field Descriptions ...................................................................... 91
5-9.
Configuration Register (CONFIG) Field Descriptions
5-10.
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions................................................. 92
5-11.
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions .............................................. 93
5-12.
Interrupt Enable Set Register (IENSET) Field Descriptions .......................................................... 94
5-13.
Interrupt Enable Clear Register (IENCLR) Field Descriptions ........................................................ 94
5-14.
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions ................... 96
5-15.
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................. 97
5-16.
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................. 97
5-17.
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions .................. 98
5-18.
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions .................. 98
5-19.
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions .... 99
5-20.
Fault Address Register (FLTADDRR) Field Descriptions
5-21.
5-22.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
44
.................................................................
...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Fault Clear Register (FLTCLR) Field Descriptions ...................................................................
Device Clock Inputs ......................................................................................................
System Clock Domains ..................................................................................................
Example PLL Frequencies ..............................................................................................
USB Clock Multiplexing Options ........................................................................................
EMIFB MCLK Frequencies ..............................................................................................
EMIFA Frequencies ......................................................................................................
EMAC Reference Clock Frequencies ..................................................................................
Peripherals .................................................................................................................
System PLLC0 Output Clocks ..........................................................................................
PLL Controller (PLLC) Registers .......................................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Reset Type Status Register (RSTYPE) Field Descriptions .........................................................
PLL Control Register (PLLCTL) Field Descriptions ..................................................................
OBSCLK Select Register (OCSEL) Field Descriptions ..............................................................
PLL Multiplier Control Register (PLLM) Field Descriptions..........................................................
PLL Pre-Divider Control Register (PREDIV) Field Descriptions ....................................................
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions ...................................................
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions ...................................................
PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions ...................................................
PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions ...................................................
PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions ...................................................
PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions ...................................................
PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions ...................................................
List of Tables
91
100
101
102
104
104
106
108
110
111
113
114
118
121
122
122
123
124
125
125
126
126
127
127
128
128
129
SPRUH91D – March 2013 – Revised September 2016
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www.ti.com
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
9-1.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
.........................................................
PLL Post-Divider Control Register (POSTDIV) Field Descriptions .................................................
PLL Controller Command Register (PLLCMD) Field Descriptions .................................................
PLL Controller Status Register (PLLSTAT) Field Descriptions .....................................................
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions .......................................
PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ..........................................
Clock Enable Control Register (CKEN) Field Descriptions..........................................................
Clock Status Register (CKSTAT) Field Descriptions .................................................................
SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions ....................................
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions ....................................
PSC0 Default Module Configuration ...................................................................................
PSC1 Default Module Configuration ...................................................................................
Module States .............................................................................................................
IcePick Emulation Commands ..........................................................................................
PSC Interrupt Events .....................................................................................................
Power and Sleep Controller 0 (PSC0) Registers .....................................................................
Power and Sleep Controller 1 (PSC1) Registers .....................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions ........................................................
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions .........................................
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ............................................
Power Error Pending Register (PERRPR) Field Descriptions ......................................................
Power Error Clear Register (PERRCR) Field Descriptions .........................................................
Power Domain Transition Command Register (PTCMD) Field Descriptions .....................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions .........................................
Power Domain 0 Status Register (PDSTAT0) Field Descriptions ..................................................
Power Domain 1 Status Register (PDSTAT1) Field Descriptions ..................................................
Power Domain 0 Control Register (PDCTL0) Field Descriptions ...................................................
Power Domain 1 Control Register (PDCTL1) Field Descriptions ...................................................
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ...........................................
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ...........................................
Module Status n Register (MDSTATn) Field Descriptions ..........................................................
PSC0 Module Control n Register (MDCTLn) Field Descriptions ...................................................
PSC1 Module Control n Register (MDCTLn) Field Descriptions ...................................................
Power Management Features ...........................................................................................
System Configuration (SYSCFG) Module Register Access .........................................................
Master IDs .................................................................................................................
Default Master Priority ...................................................................................................
System Configuration Module (SYSCFG) Registers .................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Device Identification Register 0 (DEVIDR0) Field Descriptions ....................................................
Boot Configuration Register (BOOTCFG) Field Descriptions .......................................................
Silicon Revision Identification Register (CHIPREVID) Field Descriptions .........................................
Kick 0 Register (KICK0R) Field Descriptions .........................................................................
Kick 1 Register (KICK1R) Field Descriptions .........................................................................
Host 1 Configuration Register (HOST1CFG) Field Descriptions ...................................................
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ...............................................
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................
Oscillator Divider 1 Register (OSCDIV) Field Descriptions
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
130
131
131
132
133
134
135
136
137
138
138
140
141
143
145
145
148
148
149
149
150
151
152
152
153
154
155
156
157
158
159
160
161
162
163
166
172
174
175
176
177
177
178
178
179
179
180
181
182
45
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10-14. Interrupt Enable Register (IENSET) Field Descriptions.............................................................. 183
10-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions ...................................................... 183
10-16. End of Interrupt Register (EOI) Field Descriptions ................................................................... 184
...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Master Priority 0 Register (MSTPRI0) Field Descriptions ...........................................................
Master Priority 1 Register (MSTPRI1) Field Descriptions ...........................................................
Master Priority 2 Register (MSTPRI2) Field Descriptions ...........................................................
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ................................................
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ................................................
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ................................................
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ................................................
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ................................................
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ................................................
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ................................................
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ................................................
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ................................................
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ................................................
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions .............................................
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions .............................................
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions .............................................
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions .............................................
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions .............................................
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions .............................................
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions .............................................
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions .............................................
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions .............................................
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions .............................................
Suspend Source Register (SUSPSRC) Field Descriptions .........................................................
Chip Signal Register (CHIPSIG) Field Descriptions..................................................................
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ...................................................
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ....................................................
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ....................................................
Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ....................................................
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ....................................................
Chip Configuration 4 Register (CFGCHIP4) Field Descriptions ....................................................
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger...........................................
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ............................
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ...............................................
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers ...............................
ECAP Initialization for APWM Mode ...................................................................................
ECAP1 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP2 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP3 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP4 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP1 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP2 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP3 Initialization for Multichannel PWM Generation with Phase Control .....................................
Control and Status Register Set ........................................................................................
10-17. Fault Address Register (FLTADDRR) Field Descriptions
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
46
List of Tables
184
185
186
187
188
189
191
193
195
196
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
226
228
229
230
232
235
237
238
256
258
260
262
264
266
266
266
266
269
269
269
270
SPRUH91D – March 2013 – Revised September 2016
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........................................................
Counter Phase Control Register (CTRPHS) Field Descriptions ....................................................
Capture 1 Register (CAP1) Field Descriptions........................................................................
Capture 2 Register (CAP2) Field Descriptions........................................................................
Capture 3 Register (CAP3) Field Descriptions........................................................................
Capture 4 Register (CAP4) Field Descriptions........................................................................
ECAP Control Register 1 (ECCTL1) Field Descriptions .............................................................
ECAP Control Register 2 (ECCTL2) Field Descriptions .............................................................
ECAP Interrupt Enable Register (ECEINT) Field Descriptions .....................................................
ECAP Interrupt Flag Register (ECFLG) Field Descriptions .........................................................
ECAP Interrupt Clear Register (ECCLR) Field Descriptions .......................................................
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions .....................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
ePWM Module Control and Status Registers Grouped by Submodule ............................................
Submodule Configuration Parameters .................................................................................
Time-Base Submodule Registers.......................................................................................
Key Time-Base Signals ..................................................................................................
Counter-Compare Submodule Registers .............................................................................
Counter-Compare Submodule Key Signals ...........................................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Submodule Possible Input Events ..................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode ...........................................................
Action-Qualifier Event Priority for Up-Count Mode ...................................................................
Action-Qualifier Event Priority for Down-Count Mode ................................................................
Behavior if CMPA/CMPB is Greater than the Period ................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
Dead-Band Generator Submodule Registers .........................................................................
Classical Dead-Band Operating Modes ...............................................................................
PWM-Chopper Submodule Registers ..................................................................................
Trip-Zone Submodule Registers ........................................................................................
Possible Actions On a Trip Event.......................................................................................
Event-Trigger Submodule Registers ..................................................................................
Resolution for PWM and HRPWM......................................................................................
HRPWM Submodule Registers .........................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution .............................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ........................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
13-14. Time-Stamp Counter Register (TSCTR) Field Descriptions
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
270
271
271
272
272
273
273
275
277
278
279
280
281
287
288
293
294
302
302
306
307
309
309
309
310
313
313
315
315
317
317
319
319
321
321
323
323
324
326
328
333
334
336
341
342
343
344
351
351
47
www.ti.com
351
14-38.
354
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
14-81.
14-82.
14-83.
14-84.
14-85.
48
.................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
Submodule Registers ....................................................................................................
Time-Base Submodule Registers.......................................................................................
Time-Base Control Register (TBCTL) Field Descriptions ...........................................................
Time-Base Status Register (TBSTS) Field Descriptions ............................................................
Time-Base Phase Register (TBPHS) Field Descriptions ............................................................
Time-Base Counter Register (TBCNT) Field Descriptions ..........................................................
Time-Base Period Register (TBPRD) Field Descriptions ............................................................
Counter-Compare Submodule Registers ..............................................................................
Counter-Compare Control Register (CMPCTL) Field Descriptions ................................................
Counter-Compare A Register (CMPA) Field Descriptions...........................................................
Counter-Compare B Register (CMPB) Field Descriptions...........................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .......................................
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .......................................
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions ..........................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions .........................
Dead-Band Generator Submodule Registers .........................................................................
Dead-Band Generator Control Register (DBCTL) Field Descriptions..............................................
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions ...............................
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ...............................
PWM-Chopper Control Register (PCCTL) Bit Descriptions .........................................................
Trip-Zone Submodule Registers ........................................................................................
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ...............................................
Trip-Zone Control Register (TZCTL) Field Descriptions .............................................................
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions .................................................
Trip-Zone Flag Register (TZFLG) Field Descriptions ................................................................
Trip-Zone Clear Register (TZCLR) Field Descriptions ..............................................................
Trip-Zone Force Register (TZFRC) Field Descriptions ..............................................................
Event-Trigger Submodule Registers ...................................................................................
Event-Trigger Selection Register (ETSEL) Field Descriptions .....................................................
Event-Trigger Prescale Register (ETPS) Field Descriptions .......................................................
Event-Trigger Flag Register (ETFLG) Field Descriptions ...........................................................
Event-Trigger Clear Register (ETCLR) Field Descriptions ..........................................................
Event-Trigger Force Register (ETFRC) Field Descriptions .........................................................
High-Resolution PWM Submodule Registers .........................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions ....................................
14-37. EPWM3 Initialization for
List of Tables
354
357
357
360
360
361
366
366
367
370
370
371
371
372
373
374
374
375
375
376
377
378
378
379
380
381
382
382
383
384
384
385
386
386
387
387
388
389
389
390
390
391
392
392
393
393
394
SPRUH91D – March 2013 – Revised September 2016
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14-86. Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions ................................... 394
14-87. HRPWM Configuration Register (HRCNFG) Field Descriptions .................................................... 395
......................................................................................
15-1.
Quadrature Decoder Truth Table
15-2.
eQEP Registers ........................................................................................................... 418
403
15-3.
eQEP Position Counter Register (QPOSCNT) Field Descriptions ................................................. 419
15-4.
eQEP Position Counter Initialization Register (QPOSINIT) Field Descriptions ................................... 419
15-5.
eQEP Maximum Position Count Register (QPOSMAX) Field Descriptions ....................................... 419
15-6.
eQEP Position-Compare Register (QPOSCMP) Field Descriptions ............................................... 420
15-7.
eQEP Index Position Latch Register (QPOSILAT) Field Descriptions............................................. 420
15-8.
eQEP Strobe Position Latch Register (QPOSSLAT) Field Descriptions .......................................... 420
15-9.
eQEP Position Counter Latch Register (QPOSLAT) Field Descriptions .......................................... 421
15-10. eQEP Unit Timer Register (QUTMR) Field Descriptions ............................................................ 421
15-11. eQEP Unit Period Register (QUPRD) Field Descriptions
...........................................................
421
15-12. eQEP Watchdog Timer Register (QWDTMR) Field Descriptions .................................................. 422
15-13. eQEP Watchdog Period Register (QWDPRD) Field Description ................................................... 422
.................................................
eQEP Control Register (QEPCTL) Field Descriptions ...............................................................
eQEP Capture Control Register (QCAPCTL) Field Descriptions ...................................................
eQEP Position-Compare Control Register (QPOSCTL) Field Descriptions.......................................
eQEP Interrupt Enable Register (QEINT) Field Descriptions .......................................................
eQEP Interrupt Flag Register (QFLG) Field Descriptions ...........................................................
eQEP Interrupt Clear Register (QCLR) Field Descriptions ..........................................................
eQEP Interrupt Force Register (QFRC) Field Descriptions .........................................................
eQEP Status Register (QEPSTS) Field Descriptions ...............................................................
eQEP Capture Time Register (QCTMR) Field Descriptions ........................................................
eQEP Capture Period Register (QCPRD) Field Descriptions.......................................................
eQEP Capture Timer Latch Register (QCTMRLAT) Field Descriptions ...........................................
eQEP Capture Period Latch Register (QCPRDLAT) Field Descriptions ..........................................
eQEP Revision ID Register (REVID) Field Descriptions ............................................................
EDMA3 Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ....................................................................................
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .....................................
Expected Number of Transfers for Non-Null Transfer ...............................................................
EDMA3 DMA Channel to PaRAM Mapping ...........................................................................
Shadow Region Registers ...............................................................................................
Chain Event Triggers .....................................................................................................
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping .................................................
Number of Interrupts .....................................................................................................
Read/Write Command Optimization Rules ............................................................................
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries.....................................
Channel Options Parameters (OPT) Field Descriptions .............................................................
Channel Source Address Parameter (SRC) Field Descriptions ....................................................
A Count/B Count Parameter (A_B_CNT) Field Descriptions .......................................................
Channel Destination Address Parameter (DST) Field Descriptions ...............................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .........................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ........................
C Count Parameter (CCNT) Field Descriptions.......................................................................
EDMA3 Channel Controller (EDMA3CC) Registers ..................................................................
15-14. eQEP Decoder Control Register (QDECCTL) Field Descriptions
423
15-15.
424
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
SPRUH91D – March 2013 – Revised September 2016
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List of Tables
426
427
428
429
430
432
433
434
434
434
435
435
448
451
452
460
462
464
466
467
468
481
500
501
503
503
504
504
505
506
506
507
49
www.ti.com
....................................................................
EDMA3CC Configuration Register (CCCFG) Field Descriptions ...................................................
QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions .............................................
DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ....................................
Bits in DMAQNUMn ......................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ....................................
Event Missed Register (EMR) Field Descriptions ....................................................................
Event Missed Clear Register (EMCR) Field Descriptions ...........................................................
QDMA Event Missed Register (QEMR) Field Descriptions .........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................
EDMA3CC Error Register (CCERR) Field Descriptions .............................................................
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................
Error Evaluate Register (EEVAL) Field Descriptions.................................................................
DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions ..............................
QDMA Region Access Enable for Region m (QRAEm) Field Descriptions .......................................
Event Queue Entry Registers (QxEy) Field Descriptions ............................................................
Queue n Status Register (QSTATn) Field Descriptions .............................................................
Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions .......................................
EDMA3CC Status Register (CCSTAT) Field Descriptions ..........................................................
Event Register (ER) Field Descriptions ................................................................................
Event Clear Register (ECR) Field Descriptions .......................................................................
Event Set Register (ESR) Field Descriptions .........................................................................
Chained Event Register (CER) Field Descriptions ...................................................................
Event Enable Register (EER) Field Descriptions .....................................................................
Event Enable Clear Register (EECR) Field Descriptions ............................................................
Event Enable Set Register (EESR) Field Descriptions .............................................................
Secondary Event Register (SER) Field Descriptions ................................................................
Secondary Event Clear Register (SECR) Field Descriptions .......................................................
Interrupt Enable Register (IER) Field Descriptions ...................................................................
Interrupt Enable Clear Register (IECR) Field Descriptions..........................................................
Interrupt Enable Set Register (IESR) Field Descriptions ............................................................
Interrupt Pending Register (IPR) Field Descriptions .................................................................
Interrupt Clear Register (ICR) Field Descriptions.....................................................................
Interrupt Evaluate Register (IEVAL) Field Descriptions .............................................................
QDMA Event Register (QER) Field Descriptions .....................................................................
QDMA Event Enable Register (QEER) Field Descriptions ..........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions .................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ...................................................
QDMA Secondary Event Register (QSER) Field Descriptions .....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................
EDMA3 Transfer Controller (EDMA3TC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................
Error Status Register (ERRSTAT) Field Descriptions ...............................................................
Error Enable Register (ERREN) Field Descriptions ..................................................................
Error Clear Register (ERRCLR) Field Descriptions ..................................................................
Error Details Register (ERRDET) Field Descriptions ................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions.................................................
16-21. Revision ID Register (REVID) Field Descriptions
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
50
List of Tables
510
511
512
513
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
529
530
531
532
533
534
534
535
535
536
537
537
538
539
540
541
542
543
543
544
545
546
547
548
549
550
551
552
553
554
SPRUH91D – March 2013 – Revised September 2016
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16-70. Read Command Rate Register (RDRATE) Field Descriptions ..................................................... 555
16-71. Source Active Options Register (SAOPT) Field Descriptions....................................................... 556
16-72. Source Active Source Address Register (SASRC) Field Descriptions
............................................
557
16-73. Source Active Count Register (SACNT) Field Descriptions ......................................................... 557
16-74. Source Active Destination Address Register (SADST) Field Descriptions ........................................ 558
16-75. Source Active B-Index Register (SABIDX) Field Descriptions ...................................................... 558
16-76. Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................ 559
16-77. Source Active Count Reload Register (SACNTRLD) Field Descriptions .......................................... 560
16-78. Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions ..................... 560
16-79. Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ................. 561
16-80. Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions ................................. 561
16-81. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions ............. 562
16-82. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions ........ 562
16-83. Destination FIFO Options Register n (DFOPTn) Field Descriptions ............................................... 563
16-84. Destination FIFO Source Address Register n (DFSRCn) Field Descriptions ..................................... 564
16-85. Destination FIFO Count Register n (DFCNTn) Field Descriptions ................................................. 564
16-86. Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions ................................ 565
16-87. Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions .............................................. 565
16-88. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions .................... 566
16-89. Debug List ................................................................................................................. 567
17-1.
EMAC and MDIO Signals for MII Interface ............................................................................ 576
17-2.
EMAC and MDIO Signals for RMII Interface .......................................................................... 577
17-3.
Ethernet Frame Description ............................................................................................. 578
17-4.
Basic Descriptor Description ............................................................................................ 580
17-5.
Receive Frame Treatment Summary
17-6.
Middle of Frame Overrun Treatment ................................................................................... 606
17-7.
Emulation Control ......................................................................................................... 616
17-8.
EMAC Control Module Registers ....................................................................................... 617
17-9.
EMAC Control Module Revision ID Register (REVID) Field Descriptions ......................................... 618
..................................................................................
17-10. EMAC Control Module Software Reset Register (SOFTRESET)
..................................................
605
619
17-11. EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................ 620
17-12. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 621
17-13. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 622
17-14. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 623
17-15. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 624
17-16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 625
17-17. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 626
17-18. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 627
.........
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .......
Management Data Input/Output (MDIO) Registers...................................................................
MDIO Revision ID Register (REVID) Field Descriptions.............................................................
MDIO Control Register (CONTROL) Field Descriptions .............................................................
PHY Acknowledge Status Register (ALIVE) Field Descriptions ....................................................
PHY Link Status Register (LINK) Field Descriptions .................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................
17-19. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
628
629
630
631
631
632
633
633
634
51
www.ti.com
..............
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions .......
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions .....
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ....
17-28. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
17-29.
17-30.
17-31.
635
636
637
638
17-32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ............................................................................................................... 639
17-33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................. 640
17-34. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ........................................ 641
17-35. MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................. 642
17-36. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ........................................ 643
17-37. Ethernet Media Access Controller (EMAC) Registers ............................................................... 644
17-38. Transmit Revision ID Register (TXREVID) Field Descriptions ...................................................... 647
17-39. Transmit Control Register (TXCONTROL) Field Descriptions ...................................................... 647
17-40. Transmit Teardown Register (TXTEARDOWN) Field Descriptions ................................................ 648
17-41. Receive Revision ID Register (RXREVID) Field Descriptions ...................................................... 649
17-42. Receive Control Register (RXCONTROL) Field Descriptions ...................................................... 649
17-43. Receive Teardown Register (RXTEARDOWN) Field Descriptions
................................................
650
17-44. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ........................ 651
17-45. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions....................... 652
17-46. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
....................................
653
17-47. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions .............................. 654
17-48. MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................. 655
17-49. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions .................................. 656
17-50. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ......................... 657
17-51. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ....................... 658
17-52. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ..................................... 659
17-53. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................... 660
17-54. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .......................... 661
17-55. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions......................... 661
17-56. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...................................... 662
17-57. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................ 662
17-58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 663
17-59. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 666
17-60. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 667
17-61. Receive Maximum Length Register (RXMAXLEN) Field Descriptions
............................................
668
17-62. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions........................................ 668
17-63. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 669
17-64. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............... 669
17-65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ...................... 670
17-66. MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 671
673
17-68.
675
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
52
...........................................................
Emulation Control Register (EMCONTROL) Field Descriptions ....................................................
FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................
MAC Configuration Register (MACCONFIG) Field Descriptions ...................................................
Soft Reset Register (SOFTRESET) Field Descriptions ..............................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions.............................
MAC Hash Address Register 1 (MACHASH1) Field Descriptions .................................................
MAC Hash Address Register 2 (MACHASH2) Field Descriptions .................................................
17-67. MAC Status Register (MACSTATUS) Field Descriptions
List of Tables
675
676
676
677
677
678
678
SPRUH91D – March 2013 – Revised September 2016
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17-76. Back Off Test Register (BOFFTEST) Field Descriptions ............................................................ 679
17-77. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................... 679
17-78. Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................... 680
17-79. Transmit Pause Timer Register (TXPAUSE) Field Descriptions ................................................... 680
17-80. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........................................... 681
17-81. MAC Address High Bytes Register (MACADDRHI) Field Descriptions............................................ 682
17-82. MAC Index Register (MACINDEX) Field Descriptions ............................................................... 682
17-83. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions .................... 683
17-84. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions .................... 683
17-85. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions .................................. 684
17-86. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ................................... 684
18-1.
EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories........................................ 696
18-2.
EMIFA Pins Specific to SDRAM ........................................................................................ 697
18-3.
EMIFA Pins Specific to Asynchronous Memory ...................................................................... 697
18-4.
EMIFA SDRAM Commands ............................................................................................. 698
18-5.
Truth Table for SDRAM Commands ................................................................................... 698
18-6.
16-bit EMIFA Address Pin Connections ............................................................................... 700
18-7.
Description of the SDRAM Configuration Register (SDCR) ......................................................... 701
18-8.
Description of the SDRAM Refresh Control Register (SDRCR) .................................................... 701
18-9.
Description of the SDRAM Timing Register (SDTIMR) .............................................................. 702
18-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ...................................... 702
18-11. SDRAM LOAD MODE REGISTER Command ........................................................................ 703
.................................................................................................
.................................................
Normal Mode vs. Select Strobe Mode .................................................................................
Description of the Asynchronous m Configuration Register (CEnCFG) ...........................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..................................
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ............................................
Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) ..........................................
Asynchronous Read Operation in Normal Mode .....................................................................
Asynchronous Write Operation in Normal Mode .....................................................................
Asynchronous Read Operation in Select Strobe Mode ..............................................................
Asynchronous Write Operation in Select Strobe Mode ..............................................................
Description of the NAND Flash Control Register (NANDFCR) .....................................................
Reset Sources.............................................................................................................
Interrupt Monitor and Control Bit Fields ................................................................................
SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface ................................................
SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface ..................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface ..........................................
EMIFA Input Timing Requirements .....................................................................................
ASRAM Output Timing Characteristics ................................................................................
ASRAM Input Timing Requirement for a Read .......................................................................
ASRAM Input Timing Requirements for a Write .....................................................................
ASRAM Timing Requirements With PCB Delays.....................................................................
EMIFA Timing Requirements for TC5516100FT-12 Example .....................................................
ASRAM Timing Requirements for TC5516100FT-12 Example .....................................................
Measured PCB Delays for TC5516100FT-12 Example .............................................................
18-12. Refresh Urgency Levels
704
18-13. Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM
709
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
SPRUH91D – March 2013 – Revised September 2016
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List of Tables
710
712
713
715
715
715
717
719
721
723
729
731
736
738
739
739
740
741
741
741
742
744
747
747
747
53
www.ti.com
749
18-40.
749
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
18-63.
18-64.
18-65.
18-66.
18-67.
18-68.
18-69.
18-70.
18-71.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
54
...............................................................
Recommended Margins..................................................................................................
EMIFA Read Timing Requirements ....................................................................................
NAND Flash Read Timing Requirements .............................................................................
NAND Flash Write Timing Requirements .............................................................................
EMIFA Timing Requirements for HY27UA081G1M Example .......................................................
NAND Flash Timing Requirements for HY27UA081G1M Example ................................................
Configuring CE2CFG for HY27UA081G1M Example ................................................................
Configuring NANDFCR for HY27UA081G1M Example..............................................................
External Memory Interface (EMIFA) Registers .......................................................................
Module ID Register (MIDR) Field Descriptions .......................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions .................................
SDRAM Configuration Register (SDCR) Field Descriptions ........................................................
SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
Asynchronous n Configuration Register (CEnCFG) Field Descriptions ...........................................
SDRAM Timing Register (SDTIMR) Field Descriptions..............................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ......................................
EMIFA Interrupt Raw Register (INTRAW) Field Descriptions.......................................................
EMIFA Interrupt Mask Register (INTMSK) Field Descriptions ......................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ............................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions .........................................
NAND Flash Control Register (NANDFCR) Field Descriptions .....................................................
NAND Flash Status Register (NANDFSR) Field Descriptions ......................................................
NAND Flash n ECC Register (NANDFnECC) Field Descriptions ..................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ............................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions ........................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ......................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ......................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions ..........................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions ..........................
EMIF Pins Used to Access SDRAM ...................................................................................
EMIF SDRAM Commands ...............................................................................................
Truth Table for SDRAM Commands ...................................................................................
Example of 32-bit EMIFB Address Pin Connections .................................................................
Example of 16-bit EMIFB Address Pin Connections .................................................................
Description of the SDRAM Configuration Register (SDCFG) .......................................................
Description of the SDRAM Refresh Control Register (SDRFC) ....................................................
Description of the SDRAM Timing 1 Register (SDTIM1) ............................................................
Description of the SDRAM Timing 2 Register (SDTIM2) ............................................................
Description of the SDRAM Configuration 2 Register (SDCFG2) ...................................................
mobile SDRAM LOAD MODE REGISTER Command ...............................................................
SDRAM/mobile SDRAM LOAD MODE REGISTER Command ....................................................
Refresh Urgency Levels .................................................................................................
Example Mapping from Logical Address to EMIFB Pins for 32-bit SDRAM ......................................
Example Mapping from Logical Address to EMIFB Pins for 16-bit SDRAM ......................................
Example Mapping from Logical Address to EMIFB Pins for mobile SDRAM .....................................
18-39. Configuring CE3CFG for TC5516100FT-12 Example
List of Tables
750
750
752
755
755
757
757
758
759
760
761
763
764
766
767
768
769
770
771
772
774
775
776
777
777
778
778
779
779
780
780
783
784
785
787
788
788
789
789
789
790
790
791
792
797
798
798
SPRUH91D – March 2013 – Revised September 2016
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www.ti.com
19-17. SDRAM Memory Controller FIFO Description ........................................................................ 799
19-18. Reset Sources............................................................................................................. 802
19-19. SDCFG Configuration .................................................................................................... 807
19-20. SDRFC Configuration .................................................................................................... 807
19-21. SDTIM1 Configuration.................................................................................................... 808
19-22. SDTIM2 Configuration.................................................................................................... 808
......................................................................................
....................................................................
SDRAM Configuration Register (SDCFG) Field Descriptions ......................................................
SDRAM Refresh Control Register (SDRFC) Field Descriptions ....................................................
SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................
SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................
SDRAM Configuration 2 Register (SDCFG2) Field Description ....................................................
Peripheral Bus Burst Priority Register (BPRIO) Field Descriptions ................................................
Performance Counter 1 Register (PC1) Field Descriptions .........................................................
Performance Counter 2 Register (PC2) Field Descriptions .........................................................
Performance Counter Configuration Register (PCC) Field Descriptions ..........................................
Performance Counter Filter Configuration .............................................................................
Performance Counter Master Region Select Register (PCMRS) Field Descriptions ............................
Performance Counter Time Register (PCT) Field Description ......................................................
Interrupt Raw Register (IRR) Field Descriptions ......................................................................
Interrupt Mask Register (IMR) Field Descriptions ....................................................................
Interrupt Mask Set Register (IMSR) Field Descriptions ..............................................................
Interrupt Mask Clear Register (IMCR) Field Descriptions ...........................................................
GPIO Register Bits and Banks Associated With GPIO Signals ....................................................
GPIO Registers ...........................................................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ..........................................
GPIO Direction Register (DIRn) Field Descriptions ..................................................................
GPIO Output Data Register (OUT_DATAn) Field Descriptions ....................................................
GPIO Set Data Register (SET_DATAn) Field Descriptions .........................................................
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ......................................................
GPIO Input Data Register (IN_DATAn) Field Descriptions..........................................................
GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions ......................
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions .............................
GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions .....................
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions ............................
GPIO Interrupt Status Register (INTSTATn) Field Descriptions ....................................................
HPI Pins ....................................................................................................................
Value on Optional Pins when Configured as General-Purpose I/O ................................................
Options for Connecting Host and HPI Data Strobe Pins ............................................................
Access Types Selectable With the UHPI_HCNTL Signals ..........................................................
Cycle Types Selectable With the UHPI_HCNTL and UHPI_HR/W Signals.......................................
HPI Registers..............................................................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ..........................
GPIO Enable Register (GPIO_EN) Field Descriptions...............................................................
GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions ........................................................
GPIO Data 1 Register (GPIO_DAT1) Field Descriptions ............................................................
19-23. EMIFB Base Controller Registers
809
19-24. Revision ID Register (REVID) Field Descriptions
809
19-25.
810
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
812
813
814
815
816
817
817
818
819
820
821
821
822
823
823
827
834
835
836
838
840
842
844
846
848
850
852
854
856
861
862
866
867
867
881
882
882
883
884
884
55
www.ti.com
21-12. GPIO Direction 2 Register (GPIO_DIR2) Field Descriptions ........................................................ 885
21-13. GPIO Data 2 Register (GPIO_DAT2) Field Descriptions ............................................................ 886
21-14. Host Port Interface Control Register (HPIC) Field Descriptions .................................................... 888
21-15. Host Port Interface Write Address Register (HPIAW) Field Descriptions ......................................... 889
21-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions .......................................... 889
22-1.
Operating Modes of the I2C Peripheral ................................................................................ 899
22-2.
Ways to Generate a NACK Bit .......................................................................................... 900
22-3.
Descriptions of the I2C Interrupt Events ............................................................................... 904
22-4.
Inter-Integrated Circuit (I2C) Registers
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
56
................................................................................
I2C Own Address Register (ICOAR) Field Descriptions .............................................................
I2C Interrupt Mask Register (ICIMR) Field Descriptions.............................................................
I2C Interrupt Status Register (ICSTR) Field Descriptions ...........................................................
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions ...............................................
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ..............................................
I2C Data Count Register (ICCNT) Field Descriptions................................................................
I2C Data Receive Register (ICDRR) Field Descriptions .............................................................
I2C Slave Address Register (ICSAR) Field Descriptions ............................................................
I2C Data Transmit Register (ICDXR) Field Descriptions ............................................................
I2C Mode Register (ICMDR) Field Descriptions ......................................................................
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ..................................
How the MST and FDF Bits Affect the Role of TRX Bit .............................................................
I2C Interrupt Vector Register (ICIVR) Field Descriptions ............................................................
I2C Extended Mode Register (ICEMDR) Field Descriptions ........................................................
I2C Prescaler Register (ICPSC) Field Descriptions ..................................................................
I2C Revision Identification Register 1 (REVID1) Field Descriptions ...............................................
I2C Revision Identification Register 2 (REVID2) Field Descriptions ...............................................
I2C DMA Control Register (ICDMAC) Field Descriptions ...........................................................
I2C Pin Function Register (ICPFUNC) Field Descriptions ..........................................................
I2C Pin Direction Register (ICPDIR) Field Descriptions .............................................................
I2C Pin Data In Register (ICPDIN) Field Descriptions ...............................................................
I2C Pin Data Out Register (ICPDOUT) Field Descriptions ..........................................................
I2C Pin Data Set Register (ICPDSET) Field Descriptions...........................................................
I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ........................................................
LCD External I/O Signals ................................................................................................
Register Configuration for DMA Engine Programming ..............................................................
LIDD I/O Name Map ......................................................................................................
Operation Modes Supported by Raster Controller ...................................................................
Bits-Per-Pixel Encoding for Palette Entry 0 Buffer ...................................................................
Frame Buffer Size According to BPP ..................................................................................
Color/Grayscale Intensities and Modulation Rates ...................................................................
Number of Colors/Shades of Gray Available on Screen ............................................................
LCD Controller (LCDC) Registers ......................................................................................
LCD Revision Identification Register (REVID) Field Descriptions ..................................................
LCD Control Register (LCD_CTRL) Field Descriptions ..............................................................
Pixel Clock Frequency Programming Limitations .....................................................................
LCD Status Register (LCD_STAT) Field Descriptions ...............................................................
LCD LIDD Control Register (LIDD_CTRL) Field Descriptions ......................................................
LCD LIDD CSn Configuration Register (LIDD_CSn_CONF) Field Descriptions .................................
LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR) Field Descriptions .........................
List of Tables
905
906
907
908
911
911
912
913
914
915
916
918
918
920
921
922
923
923
924
925
926
927
928
929
930
935
936
938
939
941
942
946
946
949
949
950
951
952
955
957
958
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
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23-17. LCD LIDD CSn Data Read/Write Register (LIDD_CSn_DATA) Field Descriptions .............................. 959
23-18. LCD Raster Control Register (RASTER_CTRL) Field Descriptions
...............................................
960
23-19. LCD Controller Data Pin Utilization for Mono/Color Passive/Active Panels....................................... 962
23-20. LCD Raster Timing Register 0 (RASTER_TIMING_0) Field Descriptions ........................................ 967
23-21. LCD Raster Timing Register 1 (RASTER_TIMING_1) Field Descriptions ........................................ 969
23-22. LCD Raster Timing Register 2 (RASTER_TIMING_2) Field Descriptions ........................................ 973
23-23. LCD Raster Subpanel Display Register (RASTER_SUBPANEL) Field Descriptions ............................ 977
23-24. LCD DMA Control Register (LCDDMA_CTRL) Field Descriptions ................................................. 979
23-25. LCD DMA Frame Buffer n Base Address Register (LCDDMA_FBn_BASE) Field Descriptions ............... 980
23-26. LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) Field Descriptions
.........
980
24-1.
Biphase-Mark Encoder ................................................................................................... 989
24-2.
Preamble Codes .......................................................................................................... 990
24-3.
Channel Status and User Data for Each DIT Block
24-4.
Transmit Bitstream Data Alignment ................................................................................... 1023
24-5.
Receive Bitstream Data Alignment.................................................................................... 1025
24-6.
EDMA Events - McASP
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
................................................................
................................................................................................
McASP Registers Accessed by CPU/EDMA Through Peripheral Configuration Port ..........................
McASP Registers Accessed by CPU/EDMA Through DMA Port .................................................
McASP AFIFO Registers Accessed Through Peripheral Configuration Port ....................................
Revision Identification Register (REV) Field Descriptions .........................................................
Pin Function Register (PFUNC) Field Descriptions .................................................................
Pin Direction Register (PDIR) Field Descriptions ...................................................................
Pin Data Output Register (PDOUT) Field Descriptions ............................................................
Pin Data Input Register (PDIN) Field Descriptions .................................................................
Pin Data Set Register (PDSET) Field Descriptions .................................................................
Pin Data Clear Register (PDCLR) Field Descriptions ..............................................................
Global Control Register (GBLCTL) Field Descriptions .............................................................
Audio Mute Control Register (AMUTE) Field Descriptions ........................................................
Digital Loopback Control Register (DLBCTL) Field Descriptions .................................................
Digital Mode Control Register (DITCTL) Field Descriptions .......................................................
Receiver Global Control Register (RGBLCTL) Field Descriptions ................................................
Receive Format Unit Bit Mask Register (RMASK) Field Descriptions ...........................................
Receive Bit Stream Format Register (RFMT) Field Descriptions .................................................
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions ..........................................
Receive Clock Control Register (ACLKRCTL) Field Descriptions ................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ..........................
Receive TDM Time Slot Register (RTDM) Field Descriptions.....................................................
Receiver Interrupt Control Register (RINTCTL) Field Descriptions ...............................................
Receiver Status Register (RSTAT) Field Descriptions .............................................................
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions ........................................
Receive Clock Check Control Register (RCLKCHK) Field Descriptions .........................................
Receiver DMA Event Control Register (REVTCTL) Field Descriptions ..........................................
Transmitter Global Control Register (XGBLCTL) Field Descriptions .............................................
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ...........................................
Transmit Bit Stream Format Register (XFMT) Field Descriptions ................................................
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions .........................................
Transmit Clock Control Register (ACLKXCTL) Field Descriptions................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions..........................
Transmit TDM Time Slot Register (XTDM) Field Descriptions ....................................................
SPRUH91D – March 2013 – Revised September 2016
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List of Tables
1016
1035
1036
1039
1039
1040
1042
1044
1046
1048
1050
1052
1053
1055
1057
1058
1059
1060
1061
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1076
1077
1078
1079
57
www.ti.com
24-40. Transmitter Interrupt Control Register (XINTCTL) Field Descriptions ............................................ 1080
24-41. Transmitter Status Register (XSTAT) Field Descriptions .......................................................... 1081
24-42. Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions ......................................... 1082
24-43. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ........................................ 1083
24-44. Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions ....................................... 1084
24-45. Serializer Control Registers (SRCTLn) Field Descriptions......................................................... 1085
1089
24-47. Write FIFO Control Register (WFIFOCTL) Field Descriptions
1090
24-48.
1091
24-49.
24-50.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
58
........................................
....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions .....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions ......................................................
MMC/SD Controller Pins Used in Each Mode .......................................................................
MMC/SD Mode Write Sequence ......................................................................................
MMC/SD Mode Read Sequence ......................................................................................
Description of MMC/SD Interrupt Requests .........................................................................
Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers...........................................
MMC Control Register (MMCCTL) Field Descriptions..............................................................
MMC Memory Clock Control Register (MMCCLK) Field Descriptions ...........................................
MMC Status Register 0 (MMCST0) Field Descriptions ............................................................
MMC Status Register 1 (MMCST1) Field Descriptions ............................................................
MMC Interrupt Mask Register (MMCIM) Field Descriptions .......................................................
MMC Response Time-Out Register (MMCTOR) Field Descriptions .............................................
MMC Data Read Time-Out Register (MMCTOD) Field Descriptions .............................................
MMC Block Length Register (MMCBLEN) Field Descriptions .....................................................
MMC Number of Blocks Register (MMCNBLK) Field Descriptions ...............................................
MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions ....................................
MMC Data Receive Register (MMCDRR) Field Descriptions .....................................................
MMC Data Transmit Register (MMCDXR) Field Descriptions .....................................................
MMC Command Register (MMCCMD) Field Descriptions .........................................................
Command Format .......................................................................................................
MMC Argument Register (MMCARGHL) Field Descriptions ......................................................
R1, R3, R4, R5, or R6 Response (48 Bits) ..........................................................................
R2 Response (136 Bits) ................................................................................................
MMC Data Response Register (MMCDRSP) Field Descriptions .................................................
MMC Command Index Register (MMCCIDX) Field Descriptions .................................................
SDIO Control Register (SDIOCTL) Field Descriptions .............................................................
SDIO Status Register 0 (SDIOST0) Field Descriptions ............................................................
SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions ...................................................
SDIO Interrupt Status Register (SDIOIST) Field Descriptions ....................................................
MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions ................................................
Real-Time Clock Signals ...............................................................................................
Real-Time Clock (RTC) Registers ....................................................................................
Second Register (SECOND) Field Descriptions ....................................................................
Minute Register (MINUTE) Field Descriptions.......................................................................
Hour Register (HOUR) Field Descriptions ...........................................................................
Day Register (DAY) Field Descriptions ...............................................................................
Month Register (MONTH) Field Descriptions ........................................................................
Year Register (YEAR) Field Descriptions ............................................................................
Day of the Week Register (DOTW) Field Descriptions .............................................................
24-46. AFIFO Revision Identification Register (AFIFOREV) Field Descriptions
List of Tables
1092
1093
1098
1099
1100
1110
1124
1125
1126
1127
1129
1130
1132
1133
1134
1135
1135
1136
1136
1137
1138
1139
1141
1141
1142
1142
1143
1144
1145
1145
1146
1149
1155
1156
1156
1157
1158
1158
1159
1159
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
26-10. Alarm Second Register (ALARMSECOND) Field Descriptions ................................................... 1160
26-11. Alarm Minute Register (ALARMMINUTE) Field Descriptions
.....................................................
1160
26-12. Alarm Hour Register (ALARMHOUR) Field Descriptions .......................................................... 1161
26-13. Alarm Day Register (ALARMDAY) Field Descriptions.............................................................. 1162
26-14. Alarm Month Register (ALARMMONTH) Field Descriptions
......................................................
1163
26-15. Alarm Years Register (ALARMYEARS) Field Descriptions ........................................................ 1163
26-16. Control Register (CTRL) Field Descriptions ......................................................................... 1164
26-17. Status Register (STATUS) Field Descriptions ....................................................................... 1165
26-18. Interrupt Register (INTERRUPT) Field Descriptions................................................................ 1166
26-19. Compensations Register (COMPLSB) Field Descriptions ......................................................... 1167
26-20. Compensations Register (COMPMSB) Field Descriptions ........................................................ 1168
26-21. Oscillator Register (OSC) Field Descriptions ........................................................................ 1169
26-22. Scratch Registers (SCRATCHn) Field Descriptions ................................................................ 1170
26-23. Kick Registers (KICKnR) Field Descriptions ......................................................................... 1170
..................................................................................................................
27-1.
SPI Pins
27-2.
SPI Registers ............................................................................................................ 1175
27-3.
SPI Register Settings Defining Master Modes
27-4.
Allowed SPI Register Settings in Master Modes .................................................................... 1176
27-5.
SPI Register Settings Defining Slave Modes ........................................................................ 1178
27-6.
Allowed SPI Register Settings in Slave Modes
27-7.
Clocking Modes.......................................................................................................... 1187
27-8.
SPI Registers ............................................................................................................ 1200
27-9.
SPI Global Control Register 0 (SPIGCR0) Field Descriptions
1200
27-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions
1201
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
......................................................................
.....................................................................
....................................................
....................................................
SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................
SPI Interrupt Level Register (SPILVL) Field Descriptions .........................................................
SPI Flag Register (SPIFLG) Field Descriptions .....................................................................
SPI Pin Control Register 0 (SPIPC0) Field Descriptions...........................................................
SPI Pin Control Register 1 (SPIPC1) Field Descriptions...........................................................
SPI Pin Control Register 2 (SPIPC2) Field Descriptions...........................................................
SPI Pin Control Register 3 (SPIPC3) Field Descriptions...........................................................
SPI Pin Control Register 4 (SPIPC4) Field Descriptions...........................................................
SPI Pin Control Register 5 (SPIPC5) Field Descriptions...........................................................
SPI Data Register 0 (SPIDAT0) Field Descriptions.................................................................
SPI Data Register 1 (SPIDAT1) Field Descriptions.................................................................
SPI Buffer Register (SPIBUF) Field Descriptions ...................................................................
SPI Emulation Register (SPIEMU) Field Descriptions..............................................................
SPI Delay Register (SPIDELAY) Field Descriptions ................................................................
SPI Default Chip Select Register (SPIDEF) Field Descriptions ...................................................
SPI Data Format Register (SPIFMTn) Field Descriptions .........................................................
SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions ...................................................
Timer Clock Source Selection .........................................................................................
64-Bit Timer Configurations ............................................................................................
32-Bit Timer Chained Mode Configurations .........................................................................
32-Bit Timer Unchained Mode Configurations.......................................................................
Counter and Period Registers Used in GP Timer Modes ..........................................................
TSTAT Parameters in Pulse and Clock Modes .....................................................................
Timer Emulation Modes Selection ....................................................................................
Timer Registers ..........................................................................................................
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1174
1176
1178
1203
1205
1206
1208
1209
1210
1211
1212
1213
1214
1215
1216
1218
1219
1222
1223
1225
1229
1231
1234
1237
1239
1243
1245
1245
59
www.ti.com
28-9.
................................................
...............................
GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions .........................................
Timer Counter Register 12 (TIM12) Field Descriptions ............................................................
Timer Counter Register 34 (TIM34) Field Descriptions ............................................................
Timer Period Register (PRD12) Field Descriptions .................................................................
Timer Period Register (PRD34) Field Descriptions .................................................................
Timer Control Register (TCR) Field Descriptions ...................................................................
Timer Global Control Register (TGCR) Field Descriptions ........................................................
Watchdog Timer Control Register (WDTCR) Field Descriptions ..................................................
Timer Reload Register 12 (REL12) Field Descriptions .............................................................
Timer Reload Register 34 (REL34) Field Descriptions .............................................................
Timer Capture Register 12 (CAP12) Field Descriptions ...........................................................
Timer Capture Register 34 (CAP34) Field Descriptions ...........................................................
Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ................................
Timer Compare Register (CMPn) Field Descriptions ...............................................................
Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode ........................
Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode ........................
UART Signal Descriptions .............................................................................................
Character Time for Word Lengths ....................................................................................
UART Interrupt Requests Descriptions ...............................................................................
UART Registers .........................................................................................................
Receiver Buffer Register (RBR) Field Descriptions .................................................................
Transmitter Holding Register (THR) Field Descriptions ............................................................
Interrupt Enable Register (IER) Field Descriptions .................................................................
Interrupt Identification Register (IIR) Field Descriptions............................................................
Interrupt Identification and Interrupt Clearing Information .........................................................
FIFO Control Register (FCR) Field Descriptions ....................................................................
Line Control Register (LCR) Field Descriptions .....................................................................
Relationship Between ST, EPS, and PEN Bits in LCR.............................................................
Number of STOP Bits Generated .....................................................................................
Modem Control Register (MCR) Field Descriptions ................................................................
Line Status Register (LSR) Field Descriptions ......................................................................
Modem Status Register (MSR) Field Descriptions..................................................................
Scratch Pad Register (MSR) Field Descriptions ....................................................................
Divisor LSB Latch (DLL) Field Descriptions .........................................................................
Divisor MSB Latch (DLH) Field Descriptions ........................................................................
Revision Identification Register 1 (REVID1) Field Descriptions ...................................................
Revision Identification Register 2 (REVID2) Field Descriptions ...................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions .........................
Mode Definition Register (MDR) Field Descriptions ................................................................
USB1.1 Host Controller Registers ....................................................................................
OHCI Revision Number Register (HCREVISION) Field Descriptions ............................................
HC Operating Mode Register (HCCONTROL) Field Descriptions ................................................
HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions .............................
HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions...............................
HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions ...................................
HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions ..................................
28-10. Emulation Management Register (EMUMGT) Field Descriptions
1247
28-11. GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions
1248
28-12.
1249
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
28-25.
29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
60
Revision ID Register (REVID) Field Descriptions ................................................................... 1247
List of Tables
1250
1250
1251
1251
1252
1254
1255
1256
1256
1257
1257
1258
1259
1264
1264
1265
1268
1272
1274
1275
1276
1277
1278
1279
1280
1281
1282
1282
1283
1284
1287
1288
1289
1289
1290
1290
1291
1292
1299
1300
1301
1302
1303
1304
1305
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
30-8.
HC HCAA Address Register (HCHCCA) Field Descriptions....................................................... 1306
30-9.
HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions.................................. 1306
30-10. HC Head Control Register (HCCONTROLHEADED) Field Descriptions ........................................ 1307
30-11. HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions ................................ 1307
30-12. HC Head Bulk Register (HCBULKHEADED) Field Descriptions .................................................. 1308
.........................................
HC Head Done Register (HCDONEHEAD) Field Descriptions ...................................................
HC Frame Interval Register (HCFMINTERVAL) Field Descriptions ..............................................
HC Frame Remaining Register (HCFMREMAINING) Field Descriptions ........................................
HC Frame Number Register (HCFMNUMBER) Field Descriptions ...............................................
HC Periodic Start Register (HCPERIODICSTART) Field Descriptions ..........................................
HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions ..................................
HC Root Hub A Register (HCRHDESCRIPTORA) Field Descriptions ...........................................
HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions ...........................................
HC Root Hub Status Register (HCRHSTATUS) Field Descriptions ..............................................
HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions ..........................
HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions ..........................
USB Clock Multiplexing Options.......................................................................................
PHY PLL Clock Frequencies Supported .............................................................................
USB Terminal Functions ...............................................................................................
PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ..............................................
PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ...........................................
PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions .....................................
PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ..................................
Host Packet Descriptor Word 0 (HPD Word 0) ......................................................................
Host Packet Descriptor Word 1 (HPD Word 1) ......................................................................
Host Packet Descriptor Word 2 (HPD Word 2) ......................................................................
Host Packet Descriptor Word 3 (HPD Word 3) ......................................................................
Host Packet Descriptor Word 4 (HPD Word 4) ......................................................................
Host Packet Descriptor Word 5 (HPD Word 5) ......................................................................
Host Packet Descriptor Word 6 (HPD Word 6) ......................................................................
Host Packet Descriptor Word 7 (HPD Word 7) ......................................................................
Host Buffer Descriptor Word 0 (HBD Word 0) .......................................................................
Host Buffer Descriptor Word 1 (HBD Word 1) .......................................................................
Host Buffer Descriptor Word 2 (HBD Word 2) .......................................................................
Host Buffer Descriptor Word 3 (HBD Word 3) .......................................................................
Host Buffer Descriptor Word 4 (HBD Word 4) .......................................................................
Host Buffer Descriptor Word 5 (HBD Word 5) .......................................................................
Host Buffer Descriptor Word 6 (HBD Word 6) .......................................................................
Host Buffer Descriptor Word 7 (HBD Word 7) .......................................................................
Teardown Descriptor Word 0 ..........................................................................................
Teardown Descriptor Words 1-7 ......................................................................................
Allocation of Queues ....................................................................................................
Interrupts Generated by the USB Controller .........................................................................
USB Interrupt Conditions ...............................................................................................
USB Interrupts ...........................................................................................................
Universal Serial Bus OTG (USB0) Registers ........................................................................
Revision Identification Register (REVID) Field Descriptions ......................................................
Control Register (CTRLR) Field Descriptions .......................................................................
30-13. HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
31-1.
31-2.
31-3.
31-4.
31-5.
31-6.
31-7.
31-8.
31-9.
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
31-19.
31-20.
31-21.
31-22.
31-23.
31-24.
31-25.
31-26.
31-27.
31-28.
31-29.
31-30.
31-31.
31-32.
SPRUH91D – March 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1308
1309
1309
1310
1310
1311
1311
1312
1313
1314
1315
1317
1322
1322
1323
1338
1339
1341
1343
1364
1364
1365
1365
1365
1365
1366
1366
1367
1367
1367
1367
1368
1368
1368
1368
1369
1369
1370
1384
1384
1387
1400
1407
1407
61
www.ti.com
31-33. Status Register (STATR) Field Descriptions......................................................................... 1408
31-34. Emulation Register (EMUR) Field Descriptions ..................................................................... 1408
31-35. Mode Register (MODE) Field Descriptions .......................................................................... 1409
31-36. Auto Request Register (AUTOREQ) Field Descriptions ........................................................... 1411
31-37. SRP Fix Time Register (SRPFIXTIME) Field Descriptions ........................................................ 1412
31-38. Teardown Register (TEARDOWN) Field Descriptions ............................................................. 1412
31-39. USB Interrupt Source Register (INTSRCR) Field Descriptions ................................................... 1413
31-40. USB Interrupt Source Set Register (INTSETR) Field Descriptions ............................................... 1414
31-41. USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................ 1415
31-42. USB Interrupt Mask Register (INTMSKR) Field Descriptions ..................................................... 1416
31-43. USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions ........................................... 1417
31-44. USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions......................................... 1418
31-45. USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ................................... 1419
31-46. USB End of Interrupt Register (EOIR) Field Descriptions ......................................................... 1420
31-47. Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions ....................................... 1420
31-48. Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions ....................................... 1421
31-49. Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions ....................................... 1421
31-50. Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions ....................................... 1422
31-51. Function Address Register (FADDR) Field Descriptions ........................................................... 1422
31-52. Power Management Register (POWER) Field Descriptions ....................................................... 1423
..............
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ..................................
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ...........................................
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions .......................................
Frame Number Register (FRAME) Field Descriptions .............................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)Field Descriptions ........
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions ................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions .....................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ...............
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions .....................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions ................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions .....................
Count 0 Register (COUNT0) Field Descriptions ....................................................................
Receive Count Register (RXCOUNT) Field Descriptions ..........................................................
Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ...............................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ......................
Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions ...............................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions ......................
Configuration Data Register (CONFIGDATA) Field Descriptions .................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions ..............................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions ..............................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions ..............................
31-53. Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)Field Descriptions
31-54.
31-55.
31-56.
31-57.
31-58.
31-59.
31-60.
31-61.
31-62.
31-63.
31-64.
31-65.
31-66.
31-67.
31-68.
31-69.
31-70.
31-71.
31-72.
31-73.
31-74.
31-75.
31-76.
31-77.
31-78.
31-79.
31-80.
31-81.
62
List of Tables
1424
1425
1426
1426
1427
1428
1428
1429
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1438
1439
1439
1440
1440
1441
1442
1443
1444
1444
1445
SPRUH91D – March 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
31-82. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions .............................. 1445
31-83. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions .............................. 1446
31-84. Device Control Register (DEVCTL) Field Descriptions ............................................................. 1446
31-85. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions .................................................... 1447
31-86. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions .................................................... 1447
31-87. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions ........................................... 1448
31-88. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions
...........................................
1448
31-89. Hardware Version Register (HWVERS) Field Descriptions........................................................ 1449
31-90. Transmit Function Address (TXFUNCADDR) Field Descriptions ................................................. 1450
31-91. Transmit Hub Address (TXHUBADDR) Field Descriptions ........................................................ 1450
31-92. Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................. 1450
31-93. Receive Function Address (RXFUNCADDR) Field Descriptions
.................................................
1451
31-94. Receive Hub Address (RXHUBADDR) Field Descriptions......................................................... 1451
31-95. Receive Hub Port (RXHUBPORT) Field Descriptions .............................................................. 1451
31-96. CDMA Revision Identification Register (DMAREVID) Field Descriptions ........................................ 1452
31-97. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ..................... 1452
31-98. CDMA Emulation Control Register (DMAEMU) Field Descriptions ............................................... 1453
.................
................
Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ............
Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ............
CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions ................................
CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions .....................................
Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions ........................
Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions .......
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions ......
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ...................
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions ......
Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions .....................................
Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions .....................................
Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions .....
Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions ..............
Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions ................................
Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions ...............................
Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions ...............................
Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions ...............................
31-99. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions
1453
31-100. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions
1454
31-101.
1455
31-102.
31-103.
31-104.
31-105.
31-106.
31-107.
31-108.
31-109.
31-110.
31-111.
31-112.
31-113.
31-114.
31-115.
31-116.
31-117.
31-118.
31-119.
31-120.
31-121.
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List of Tables
1456
1457
1457
1459
1459
1460
1461
1462
1463
1463
1464
1464
1465
1465
1466
1467
1468
1469
1469
1470
63
Preface
SPRUH91D – March 2013 – Revised September 2016
Read This First
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components
• DSP subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box provided at www.ti.com.
The current documentation that describes related peripherals and other technical collateral, is available in
the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
Code Composer Studio is a trademark of Texas Instruments.
SD is a trademark of SanDisk Corporation.
64
Read This First
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Chapter 1
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Overview
Topic
1.1
...........................................................................................................................
Page
Introduction ....................................................................................................... 66
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Introduction
1.1
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Introduction
The C6745/C6747 DSP efficiently handles communication and audio processing tasks. The C6745/C6747
DSP consists of the following primary components:
• DSP subsystem and associated memories
• A set of I/O peripherals
• A powerful DMA subsystem and SDRAM EMIF interface
Block Diagram
A block diagram for the C6745 DSP is shown in TMS320C6745 DSP Block Diagram. A block diagram for
the C6747 DSP is shown in TMS320C6747 DSP Block Diagram.
DSP Subsystem
The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks of
internal memory (L1P, L1D, and L2). The DSP Subsystem chapter describes the DSPSS components.
DMA Subsystem
The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more
information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter.
TMS320C6745 DSP Block Diagram
JTAG Interface
DSP Subsystem
System Control
Input
Clock(s)
C674x
DSP CPU
PLL/Clock
Generator
w/OSC
Memory
Protection
GeneralPurpose
Timer
GeneralPurpose
Timer
(Watchdog)
AET
32KB
L1 Pgm
Power/Sleep
Controller
32KB
L1 RAM
256KB L2 RAM
Pin
Multiplexing
BOOT ROM
Switched Central Resource (SCR)
Peripherals
GPIO
DMA
Audio Ports
EDMA3
McASP
w/FIFO
(2)
eCAP
(3)
I2C
(2)
SPI
(2)
UART
(3)
PRU
Subsystem
Connectivity
Control Timers
eHRPWM
(3)
Serial Interfaces
eQEP
(2)
USB2.0
OTG Ctlr
PHY
(10/100)
EMAC
(RMII)
MDIO
External Memory Interfaces
MMC/SD
(8b)
EMIFA(8b)
NAND/Flash
EMIFB
SDRAM Only
(16b)
Note: Not all peripherals are available at the same time due to multiplexing.
66
Overview
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TMS320C6747 DSP Block Diagram
JTAG Interface
DSP Subsystem
System Control
PLL/Clock
Generator
w/OSC
Input
Clock(s)
GeneralPurpose
Timer
GeneralPurpose
Timer
(Watchdog)
C674x
DSP CPU
Memory
Protection
Power/Sleep
Controller
AET
32KB
L1 Pgm
32KB
L1 RAM
256KB L2 RAM
RTC/
32-kHz
OSC
Pin
Multiplexing
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
McASP
w/FIFO
(3)
EDMA3
GPIO
I2C
(2)
eCAP
(3)
SPI
(2)
UART
(3)
Internal Memory
LCD
Ctlr
Connectivity
Control Timers
eHRPWM
(3)
Display
Serial Interfaces
Audio Ports
eQEP
(2)
USB2.0
OTG Ctlr
PHY
USB1.1
OHCI Ctlr
PHY
(10/100)
EMAC
(RMII)
MDIO
128KB
RAM
PRU
Subsystem
External Memory Interfaces
HPI
MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
Note: Not all peripherals are available at the same time due to multiplexing.
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Chapter 2
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DSP Subsystem
Topic
2.1
2.2
2.3
2.4
68
...........................................................................................................................
Introduction .......................................................................................................
TMS320C674x Megamodule .................................................................................
Memory Map ......................................................................................................
Advanced Event Triggering (AET) ........................................................................
DSP Subsystem
Page
69
70
74
75
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2.1
Introduction
The DSP subsystem (Figure 2-1) includes TI’s standard TMS320C674x megamodule and several blocks
of internal memory (L1P, L1D, and L2). This document provides an overview of the DSP subsystem and
the following considerations associated with it:
• Memory mapping
• Interrupts
• Power management
For more information, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5), the
TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8), and the TMS320C674x DSP
Cache User’s Guide (SPRUG82).
Figure 2-1. TMS320C674x Megamodule Block Diagram
32K bytes
L1P RAM/
cache
256K bytes
L2 RAM
256
256
1M bytes
L2 ROM
256
256
Cache control
Memory protect
Bandwidth Mgmt
Cache control
Memory protect
Bandwidth Mgmt
L1P
256
256
256
256
Instruction fetch
Register
file B
64
64
Bandwidth Mgmt
Memory protect
Cache control
Power down
Interrupt
Controller
C674x
Fixed/floating point CPU
Register
file A
L2
IDMA
256
CFG
EMC
L1D
MDMA
8x32
64
32K bytes
L1D RAM/
cache
64
32
Configuration
peripherals
bus
SDMA
64
64
High performance
switch fabric
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TMS320C674x Megamodule
2.2
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TMS320C674x Megamodule
The C674x megamodule (Figure 2-1) consists of the following components:
• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)
2.2.1 Internal Memory Controllers
The C674x megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory (L1) is split into separate program memory (L1P memory) and data
memory (L1D memory). L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also
be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory
locations. The internal direct memory access controller (IDMA) manages DMA among the L1P, L1D, and
L2 memories.
For more information about each of these controllers, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5).
2.2.2 Internal Peripherals
The C674x megamodule includes the following internal peripherals:
• DSP interrupt controller (INTC)
• DSP power-down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA) controller
This section briefly describes the INTC, PDC, BWM, and IDMA controller. For more information on these
internal peripherals, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
2.2.2.1
Interrupt Controller (INTC)
The C674x megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps DSP device events to 12 CPU interrupts. All DSP device events are listed in Table 2-1. The INTC is
fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
Table 2-1. DSP Interrupt Map
Event
70
Interrupt Name
Source
0
EVT0
C674x Interrupt Control 0
1
EVT1
C674x Interrupt Control 1
2
EVT2
C674x Interrupt Control 2
3
EVT3
C674x Interrupt Control 3
4
T64P0_TINT12
Timer64P0 - TINT12
5
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
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Table 2-1. DSP Interrupt Map (continued)
Event
(1)
(2)
Interrupt Name
Source
6
—
Reserved
7
EHRPWM0
HiResTimer/PWM0 Interrupt
8
TPCC0_INT1
TPCC0 Region 1 Interrupt
9
EMU-DTDMA
C674x-ECM
10
EHRPWM0TZ
HiResTimer/PWM0 Trip Zone Interrupt
11
EMU-RTDXRX
C674x-RTDX
12
EMU-RTDXTX
C674x-RTDX
13
IDMAINT0
C674x-EMC
14
IDMAINT1
C674x-EMC
15
MMCSD_INT0
MMCSD MMC/SD Interrupt
16
MMCSD_INT1
MMCSD SDIO Interrupt
17
—
Reserved
18
EHRPWM1
HiResTimer/PWM1 Interrupt
19
USB0_INT
USB0 (USB2.0) Interrupt
20
USB1_HCINT (1)
USB1 (USB1.1) OHCI Host Controller Interrupt
(1)
21
USB1_R/WAKEUP
22
—
Reserved
23
EHRPWM1TZ
HiResTimer/PWM1 Trip Zone Interrupt
24
EHRPWM2
HiResTimer/PWM2 Interrupt
25
EHRPWM2TZ
HiResTimer/PWM2 Trip Zone Interrupt
26
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
27
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
28
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
29
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
30
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
31
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
32
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
33
EMAC_C1MISC
(2)
USB1 (USB1.1) Remote Wakeup Interrupt
EMAC - Core 1 Miscellaneous Interrupt
34
UHPI_DSPINT
35
—
HPI DSP Interrupt
Reserved
36
IIC0_INT
I2C0
37
SPI0_INT
SPI0
38
UART0_INT
UART0
39
—
Reserved
40
T64P1_TINT12
Timer64P1 Interrupt 12
41
GPIO_B1INT
GPIO Bank 1 Interrupt
42
IIC1_INT
I2C1
43
SPI1_INT
SPI1
44
—
Reserved
45
ECAP0
ECAP0
46
UART_INT1
UART1
47
ECAP1
ECAP1
48
T64P1_TINT34
Timer64P1 Interrupt 34
49
GPIO_B2INT
GPIO Bank 2 Interrupt
50
—
Reserved
51
ECAP2
ECAP2
This peripheral is not supported on the C6745 DSP.
This peripheral is not supported on the C6745 DSP.
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Table 2-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
52
GPIO_B3INT
GPIO Bank 3 Interrupt
53
EQEP1
EQEP1
54
GPIO_B4INT
GPIO Bank 4 Interrupt
55
EMIFA_INT
EMIFA
56
EDMA3_CC0_ERRINT
EDMA3 Channel Controller 0
57
EDMA3_TC0_ERRINT
EDMA3 Transfer Controller 0
58
EDMA3_TC1_ERRINT
EDMA3 Transfer Controller 1
59
GPIO_B5INT
GPIO Bank 5 Interrupt
60
EMIFB_INT
EMIFB Memory Error Interrupt
61
MCASP_INT
McASP0,1,2 Combined RX/TX Interrupts
62
GPIO_B6INT
GPIO Bank 6 Interrupt
63
RTC_IRQS
(2)
64
T64P0_TINT34
Timer64P0 Interrupt 34
65
GPIO_B0INT
GPIO Bank 0 Interrupt
66
—
Reserved
67
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
68
EQEP0
EQEP0
69
UART2_INT
UART2
70
PSC0_ALLINT
PSC0
71
PSC1_ALLINT
PSC1
72
GPIO_B7INT
GPIO Bank 7 Interrupt
73
LCDC_INT
(2)
74
MPU_BOOTCFG_ERR
MPU Shared Interrupt
—
Reserved
78
T64P0_CMPINT0
Timer64P0 - Compare 0
79
T64P0_CMPINT1
Timer64P0 - Compare 1
80
T64P0_CMPINT2
Timer64P0 - Compare 2
81
T64P0_CMPINT3
Timer64P0 - Compare 3
82
T64P0_CMPINT4
Timer64P0 - Compare 4
83
T64P0_CMPINT5
Timer64P0 - Compare 5
84
T64P0_CMPINT6
Timer64P0 - Compare 6
85
T64P0_CMPINT7
Timer64P0 - Compare 7
86
T64P1_CMPINT0
Timer64P1 - Compare 0
87
T64P1_CMPINT1
Timer64P1 - Compare 1
88
T64P1_CMPINT2
Timer64P1 - Compare 2
89
T64P1_CMPINT3
Timer64P1 - Compare 3
90
T64P1_CMPINT4
Timer64P1 - Compare 4
91
T64P1_CMPINT5
Timer64P1 - Compare 5
92
T64P1_CMPINT6
Timer64P1 - Compare 6
93
T64P1_CMPINT7
Timer64P1 - Compare 7
—
Reserved
96
INTERR
C674x-Interrupt Control
97
EMC_IDMAERR
C674x-EMC
—
Reserved
PMC_ED
C674x-PMC
—
Reserved
UMC_ED1
C674x-UMC
75-77
94-95
98-112
113
114-115
116
72
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Table 2-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
C674x-SYS
120
PMC_CMPA
C674x-PMC
121
PMC_CMPA
C674x-PMC
122
DMC_CMPA
C674x-DMC
123
DMC_CMPA
C674x-DMC
124
UMC_CMPA
C674x-UMC
125
UMC_CMPA
C674x-UMC
126
EMC_CMPA
C674x-EMC
127
EMC_BUSERR
C674x-EMC
2.2.2.1.1 Interrupt Controller Registers
For more information on the DSP interrupt controller (INTC) registers, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.1.2 NMI Interrupt
In addition to the interrupts listed in Table 2-1, the DSP also supports a special interrupt that behaves
more like an exception, non-maskable interrupt (NMI). The NMI interrupt is controlled by two registers in
the System Configuration Module, the chip signal register (CHIPSIG) and the chip signal clear register
(CHIPSIG_CLR).
The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. The NMI interrupt is cleared
by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. For more information on the System Configuration
Module, CHIPSIG, and CHIPSIG_CLR, see the System Configuration (SYSCFG) Module chapter.
2.2.2.2
Power-Down Controller (PDC)
The C674x megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C674x megamodule and internal memories of the DSP subsystem:
• C674x CPU
• Level 1 program memory controller (PMC)
• Level 1 data memory controller (DMC)
• Level 2 unified memory controller (UMC)
• Extended memory controller (EMC)
• Internal Direct Memory Access controller (IDMA)
• L1P memory
• L1D memory
• L2 memory
This device supports the static power-down feature from the C674x megamodule. The TMS320C674x
DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail.
• Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and
all internal memories immediately upon command from software.
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Static power-down (clock gating) affects all components of the C674x megamodule and all internal
memories. Software can initiate static power-down by way of a register bit in the power-down controller
command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.3
Bandwidth Manager (BWM)
The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA3-initiated DMA transfers (and resulting coherency operations)
• DSP subsystem IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of the C674x megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA, IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The programmable priority
level has a single meaning throughout the system. There are a total of nine priority levels, where priority
zero is the highest priority and priority eight is the lowest priority. When requests for a single resource
contend, access is granted to the highest-priority requestor. When the contention occurs for multiple
successive cycles, a contention counter assures that the lower-priority requestor gets access to the
resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1 represents a
transfer whose priority has been increased due to expiration of the contention counter or a transfer that is
fixed as the highest-priority transfer to a given resource.
2.2.2.4
Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) memory. The IDMA cannot
transfer data to or from the internal DSP memory-mapped register space. The IDMA is fully described in
the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
2.3
Memory Map
Refer to your device-specific data manual for memory-map information.
2.3.1 DSP Internal Memory
See the System Memory chapter for a description of the DSP internal memory.
2.3.2 External Memory
See the System Interconnect chapter and the System Memory chapter for a description of the additional
system memory and peripherals that the DSP has access to.
74
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2.4
Advanced Event Triggering (AET)
The C674x megamodule supports advanced event triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides
the following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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System Interconnect
Topic
3.1
3.2
76
...........................................................................................................................
Page
Introduction ....................................................................................................... 77
System Interconnect Block Diagram ..................................................................... 78
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3.1
Introduction
The DSP, the EDMA3 transfer controllers, and the device peripherals are interconnected through a switch
fabric architecture (see Section 3.2). The switch fabric is composed of multiple switched central resources
(SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals
and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Through SCR, the DSP can send data to the EMIF without affecting a data
transfer between a device peripheral and internal shared memory. Bridges are mainly used to perform
bus-width conversion as well as bus operating frequency conversion.
The DSP, the EDMA3 transfer controllers, and the various device peripherals can be classified into two
categories: master peripherals and slave peripherals.
Master peripherals are typically capable of initiating read and write transfers in the system and do not rely
on the EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include
the DSP, the EDMA3 transfer controllers, EMAC, HPI, LCDC, and USB. Not all master peripherals may
connect to all slave peripherals. The supported connections are designated by an X in Table 3-1.
Table 3-1. TMS320C6745/C6747 DSP System Interconnect Matrix
Masters
Master
Slaves
Default
Priority
DSP
SDMA
EMIFA
EMIFB
128 kB RAM
EDMA3TC
Group (1)
Peripheral
Group (2)
EDMA3CC0
0
EDMA3TC0
0
X
X
X
X
X
X
EDMA3TC1
0
X
X
X
X
X
X
PRU0
0
X
X
X
X
X
X
PRU1
0
X
X
X
X
X
X
DSP CFG
2
X
X
DSP MDMA
2
EMAC
4
USB2.0
4
USB1.1 (3)
4
LCDC
HPI (3)
(1)
(2)
(3)
(4)
(3)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5
6
X
X
X
X
X (4)
EDMA3TC group: EDMA3TC0, EDMA3TC1
Peripheral group: SYSCFG, EMAC, eCAP0, eCAP1, eCAP2, eHRPWM0, eHRPWM1, eHRPWM2, GPIO, I2C0, I2C1, LCDC,
McASP0, McASP1, McASP2, MDIO, MMC/SD, PLLC, PRU RAM0, PRU RAM1, PRU Config, PSC0, PSC1, RTC, SPI0, SPI1,
TIMER64P0, TIMER64P1, EDMA3CC0, UART0, UART1, UART2, HPI, USB0 (USB2.0), USB1 (USB1.1). The LCDC and
McASP2 are not supported on the C6745 DSP.
This peripheral is not supported on the C6745 DSP.
The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level.
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System Interconnect Block Diagram
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System Interconnect Block Diagram
Figure 3-1 shows a system interconnect block diagram.
Figure 3-1. System Interconnect Block Diagram
(A)
HPI
BR9
USB0
BR10
USB0
BR11
EMAC
BR13
DSP SDMA (L1D/L2)
SCR7
BR12
BR13
(A)
128k Shared RAM (A)
BR19
SCR8
USB1
MPU1
SCR9
BR15
MPU2
EMIFB
BR20
(A)
LCDC
BR14
DSP MDMA
EDMA3 TC0
EDMA3 TC1
USB0 Cfg
rd
SCR1
HPI Cfg
wr
Clock Domain: SYSCLK4
[CPU/4 Synchronous]
wr
SCR12
(A)
SPI1
(A)
LCDC
PSC0
rd
SCR5
BR5
PLLC
Clock Domain: SYSCLK4
[CPU/4 Synchronous]
SYSCFG
EMAC
Async 2 Clock Domain
BR3
BR4
SCR6
EMAC MDIO
S
Timer64P0
S
Timer64P1
S
I2C0
S
RTC
SCR13
USB1 Cfg
(A)
GPIO
PSC1
(A)
BR18
I2C1
BR6
DSP CFG
UART1
Async 1 Clock Domain
UART2
PRU0
EMIFA
BR7
SCR11
PRU1
McASP0
McASP1
McASP2
PRU Cfg
(A)
Legend:
SCR2
32-Bit BUS
64-Bit BUS
eHRPWM0
MMC/SD0
SCR4
IP Module
eHRPWM1
SPI0
eHRPWM2
UART0
Synchronous Bridge
Asynchronous Bridge
EDMA3 TC0
SCR
EDMA3 TC1
SCR10
eCAP0
eCAP1
eCAP2
Paths with dashed lines cross the subchip boundary
eQEP0
eQEP1
EDMA3 CC
A
78
EDMA3 CC
This peripheral is not supported on the C6745 DSP.
System Interconnect
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Chapter 4
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System Memory
Topic
4.1
4.2
4.3
...........................................................................................................................
Page
Introduction ....................................................................................................... 80
DSP Memories ................................................................................................... 80
Peripherals ........................................................................................................ 81
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Introduction
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Introduction
This device has multiple on-chip/off-chip memories and several external device interfaces associated with
the DSP and various subsystems. To help simplify software development, a unified memory-map is used
wherever possible to maintain a consistent view of device resources across all masters (CPU and master
peripherals).
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
4.2
DSP Memories
The DSP internal memories are accessible by the DSP and other master peripherals (as dictated by the
connectivity matrix) via the system interconnect through the DSP SDMA port. The accesses by the DSP to
its internal memory are internal to the DSP subsystem and do not go out on the system interconnect.
The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
• L1P memory includes 32 kB of RAM. The DSP program memory controller (PMC) allows you to
configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache
sizes of 0 kB, 4 kB, 8 kB, 16 kB, or 32 kB of the 32 kB of RAM. The default configuration is 32 kB
cache.
• L1D memory includes 32 kB of RAM. The DSP data memory controller (DMC) allows you to configure
part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 kB, 4 kB, 8
kB, 16 kB, or 32 kB of the 32 kB of RAM. The default configuration is 32 kB cache.
• L2 memory includes 256 kB of RAM. The DSP unified memory controller (UMC) allows you to
configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of
0 kB, 4 kB, 8 kB, 16 kB, 32 kB, 64 kB, 128 kB, or 256 kB of the 256 kB of RAM. The default
configuration is 256 kB normal RAM.
• L2 memory also includes 1024 kB of ROM.
Shared RAM
This device also offers an on-chip 128-kB shared RAM, apart from the DSP level 1 and level 2 internal
memories. This shared RAM is accessible by the DSP and also is accessible by several master
peripherals. The 128-kB shared RAM is not supported on the C6745 DSP.
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIFA:
– 8/16-bit wide (package dependent) asynchronous EMIF module that supports asynchronous
devices such as ASRAM, NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide (package dependent) NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space (package dependent)
• EMIFB: 32/16-bit SDRAM (package dependent) with up to 256-MB SDRAM address space
Internal Peripherals
The following peripherals are internal to the DSP subsystem and are only accessible to the DSP:
• DSP interrupt controller (INTC)
• DSP power down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA)
For more information on these internal peripherals, see the TMS320C674x DSP Megamodule Reference
Guide (SPRUFK5).
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4.3
Peripherals
The DSP has access to all peripherals on the device. See the device-specific data manual for the
complete list of peripherals supported on your device.
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Memory Protection Unit (MPU)
Topic
5.1
5.2
5.3
82
...........................................................................................................................
Page
Introduction ....................................................................................................... 83
Architecture....................................................................................................... 84
MPU Registers ................................................................................................... 89
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5.1
Introduction
This device supports two memory protection units (MPU1 and MPU2). MPU1 supports the 128 kB shared
RAM and MPU2 supports the EMIFB. The MPU1 is not supported on the C6745 DSP.
5.1.1 Purpose of the MPU
The memory protection unit (MPU) is provided to manage access to memory. The MPU allows you to
define multiple ranges and limit access to system masters based on their privilege ID. The MPU can
record a detected fault, or invalid access, and notify the system through an interrupt.
5.1.2 Features
The MPU supports the following features:
• Supports multiple programmable address ranges
• Supports 0 or 1 fixed range
• Supports read, write, and execute access privileges
• Supports privilege ID associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• Supports L1/L2 cache accesses
• Supports protection of its own registers
5.1.3 Block Diagram
Figure 5-1 shows a block diagram of the MPU. An access to a protected memory must pass through the
MPU. During an access, the MPU checks the memory address on the input data bus against fixed and
programmable ranges. If allowed, the transfer is passed unmodified to the output data bus. If the transfer
fails the protection check then the MPU does not pass the transfer to the output bus but rather services
the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor
as well as generating an interrupt about the fault. The MPU generates two interrupts: an address error
interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).
Figure 5-1. MPU Block Diagram
MPU
Input
Data
Bus
Protection
Checks
Output
Data
Bus
MPU_ADDR_ERR_INT
MMRs
MPU_PROT_ERR_INT
MPU Register Bus
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5.1.4 MPU Default Configuration
Two MPUs are supported on the device, one for the 128 kB shared RAM and one for the EMIFB. Table 51 shows the memory regions protected by each MPU. Table 5-2 shows the configuration of each MPU.
Table 5-1. MPU Memory Regions
Memory Region
Unit
MPU1
Memory Protection
128 kB Shared RAM
MPU2
(1)
EMIFB
(1)
Start Address
End Address
8000 0000h
8001 FFFFh
C000 0000h
DFFF FFFFh
The 128 kB shared RAM is not supported on the C6745 DSP; therefore, the MPU1 is not supported.
Table 5-2. MPU Default Configuration
Setting
Default permission
MPU2
Assume allowed
Assume allowed
Number of allowed IDs supported
12
12
Number of fixed ranges supported
1
0
Number of programmable ranges supported
Compare width
(1)
5.2
MPU1 (1)
6
12
1 kB granularity
64 kB granularity
MPU1 is not supported on the C6745 DSP.
Architecture
5.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
DSP CPU instruction and data accesses have a privilege level associated with them. The privilege level is
inherited from the code running on the CPU. See the TMS320C674x DSP CPU and Instruction Set
Reference Guide (SPRUFE8) for more details on privilege levels of the DSP CPU.
Although master peripherals like the EMAC do not execute code, they still have a privilege level
associated with them. Unlike the DSP CPU , the privilege level of this peripheral is fixed.
Table 5-3 shows the privilege ID of the CPU and every mastering peripheral. Table 5-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.
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Table 5-3. Device Master Settings
Master
Privilege Level
Access Type
EDMA3CC
Privilege ID
Inherited
Inherited
DMA
EDMA3TC0 and TC1
Inherited
Inherited
DMA
DSP
1
Software dependant
Software dependant
PRU0/PRU1
2
Supervisor
DMA
HPI (1)
3
User
DMA
EMAC
4
Supervisor
Data/DMA
USB1.1 (1)
5
Supervisor
DMA
USB2.0
6
Supervisor
DMA
7
Supervisor
DMA
LCD Controller
(1)
(1)
This peripheral is not supported on the C6745 DSP.
5.2.2 Memory Protection Ranges
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the “unpopulated” memory range must be protected in order to prevent
unintended/disallowed “aliased” access to protected memory. One of the programmable
address ranges could be used to detect accesses to this “unpopulated” memory.
The MPU divides its assigned memory into address ranges. Each MPU can support one fixed address
range and multiple programmable address ranges. The fixed address range is configured to an exact
address. The programmable address range allows software to program the start and end addresses.
Each address range has the following set of registers:
• Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending
address of the address range.
• Memory protection page attribute register (MPPA): Use to program the permission settings of the
address range.
It is allowed to configure ranges such that they overlap each other. In this case, all the overlapped ranges
must allow the access, otherwise the access is not allowed. The final permissions given to the access are
the lowest of each type of permission from any hit range.
Addresses not covered by a range are either allowed or disallowed based on the configuration of the
MPU. The MPU can be configured for “assumed allowed” or “assumed disallowed” mode as dictated by
the ASSUME_ALLOWED bit in the configuration register (CONFIG).
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5.2.3 Permission Structures
The MPU defines a per-range permission structure with three permission fields in a 32-bit permission
entry. Figure 5-2 shows the structure of a permission entry.
Figure 5-2. Permission Fields
31
22
21
20
Reserved
15
14
13
12
11
10
9
8
Allowed IDs
AID5
AID4
5.2.3.1
AID3
AID2
6
AID11
AID10
5
4
Reserved
AID1
AID0
19
18
17
16
Allowed IDs
AIX
AID9
AID8
AID7
AID6
3
2
1
0
UW
UX
Access Types
SR
SW
SX
UR
Requestor-ID Based Access Controls
Each master on the device has an N-bit code associated with it that identifies it for privilege purposes.
This privilege ID accompanies all memory accesses made on behalf of that master. That is, when a
master triggers a memory access command, the privilege ID will be carried alongside the command.
Each memory protection range has an allowed ID (AID) field associated with it that indicates which
requestors may access the given address range. The MPU maps the privilege IDs of all the possible
requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA).
• AID0 through AID11 are used to specify the allowed privilege IDs.
• An additional allowed ID bit, AIDX, captures access made by all privilege IDs not covered by AID0
through AID11.
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies
access to the corresponding requestor.
5.2.3.2
Request-Type Based Permissions
The memory protection model defines three fundamental functional access types: read, write, and
execute. Read and write refer to data accesses -- accesses originating via the load/store units on the CPU
or via a master peripheral. Execute refers to accesses associated with an instruction fetch.
The memory protection model allows controlling read, write, and execute permissions independently for
both user and supervisor mode. This results in six permission bits, listed in Table 5-4. For each bit, a 1
permits the access type and a 0 denies access. For example, UX = 1 means that User Mode may execute
from the given page. The memory protection unit allows you to specify all six of these bits separately; 64
different encodings are permitted altogether, although programs might not use all of them.
Table 5-4. Request Type Access Controls
86
Bit
Field
Description
5
SR
Supervisor may read
4
SW
Supervisor may write
3
SX
Supervisor may execute
2
UR
User may read
1
UW
User may write
0
UX
User may execute
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5.2.4 Protection Check
During a memory access, the MPU checks if the address range of the input transfer overlaps one of the
address ranges. When the input transfer address is within a range the transfer parameters are checked
against the address range permissions.
The MPU first checks the transfer’s privilege ID against the AID settings. If the AID bit is 0, then the range
will not be checked; if the AID bit is 1, then the transfer parameters are checked against the memory
protection page attribute register (MPPA) values to detect an allowed access.
For non-debug accesses, the read, write, and execute permissions are also checked. There is a set of
permissions for supervisor mode and a set for user mode. For supervisor mode accesses, the SR, SW,
and SX bits are checked. For user mode accesses, the UR, UW, and UX bits are checked.
If the transfer address range does not match any address range then the transfer is either allowed or
disallowed based on the configuration of the MPU. The MPU can be configured for “assumed allowed” or
“assumed disallowed” mode as dictated by the ASSUME_ALLOWED bit in the configuration register
(CONFIG).
In the case that a transfer spans multiple address ranges, all the overlapped ranges must allow the
access, otherwise the access is not allowed. The final permissions given to the access are the lowest of
each type of permission from any hit range. Therefore, if a transfer matches 2 ranges, one that is RW and
one that is RX, then the final permission is just R.
The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses, see
Section 5.2.5 for more details.
5.2.5 DSP L1/L2 Cache Controller Accesses
A memory read access that originates from the DSP L1/L2 cache is treated differently to allow memory
protection to be enforced by the DSP level. This is because a subsequent memory access that hits in the
cache does not pass through the MPU. Instead the memory access is serviced directly by the L1/L2
memory controllers.
During a cache memory read, the permission settings stored in the memory protection page attribute
registers (MPPA) are passed to the L1/L2 memory controllers along with the read data. The permissions
settings returned by the MPU are taken from MPPA that covers the address range of the original
request—only the SR, SW, SX, UR, UW, and UX bits are passed. If the request address is covered by
multiple address ranges, then the returned value is the logical-AND of all MPPA permissions. If the
transfer address range is not covered by an address range then the transfer is either allowed or
disallowed based on the configuration of the MPU.
5.2.6 MPU Register Protection
Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page
attribute registers (MPPA) is also protected. All non-debug writes must be by a supervisor entity. A
protection fault can occur from a register write with invalid permissions and this triggers an interrupt just
like a memory access.
Faults are not recorded (nor interrupts generated) for debug accesses.
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5.2.7 Invalid Accesses and Exceptions
When a transfer fails the protection check, the MPU does not pass the transfer to the output bus. The
MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.
The behavior of the MPU depends on whether the access was a read or a write:
• For a read: The MPU returns 0s, a permission value is 0 (no access allowed), a protection error status.
• For a write: The MPU receives all the write data and returns a protection error status.
The MPU captures system faults due to addressing or protection violations in its registers. The MPU can
store the fault information for only one fault, so the first detected fault is recorded into the fault registers
and an interrupt is generated. Software must use the fault clear register (FLTCLR) to clear the fault status
so that another fault can be recorded. The MPU will not record another fault nor generate another interrupt
until the existing fault has been cleared. Also, additional faults will be ignored. Faults are not recorded (no
interrupts generated) for debug accesses.
5.2.8 Reset Considerations
After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection
features.
5.2.9 Interrupt Support
5.2.9.1
Interrupt Events and Requests
The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection
interrupt (MPU_PROT_ERR_INT). The MPU_ADDR_ERR_INT is generated when there is an addressing
violation due to an access to a non-existent location in the MPU register space. The
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined
ranges or to the MPU registers.
The transfer parameters that caused the violation are saved in the MPU registers.
5.2.9.2
Interrupt Multiplexing
The interrupts from both MPUs are combined with the boot configuration module into a single interrupt
called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt controller. Table 5-5
shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR.
Table 5-5. MPU_BOOTCFG_ERR Interrupt Sources
Interrupt
MPU1_ADDR_ERR_INT
Source
(1)
MPU1 address error interrupt
MPU1_PROT_ERR_INT (1)
MPU1 protection interrupt
MPU2_ADDR_ERR_INT
MPU2 address error interrupt
MPU2_PROT_ERR_INT
MPU2 protection interrupt
BOOTCFG_ADDR_ERR
Boot configuration address error
BOOTCFG_PROT_ERR
Boot configuration protection error
(1)
MPU1 is not supported on the C6745 DSP.
5.2.10 Emulation Considerations
Memory and MPU registers are not protected against emulation accesses.
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5.3
MPU Registers
There are two MPUs on the device. Each MPU contains a set of memory-mapped registers.
Table 5-6 lists the memory-mapped registers for the MPU1. Table 5-7 lists the memory-mapped registers
for the MPU2.
Table 5-6. Memory Protection Unit 1 (MPU1) Registers
Address
Acronym
Register Description
Section
01E1 4000h
REVID
Revision identification register
Section 5.3.1
01E1 4004h
CONFIG
Configuration register
Section 5.3.2
01E1 4010h
IRAWSTAT
Interrupt raw status/set register
Section 5.3.3
01E1 4014h
IENSTAT
Interrupt enable status/clear register
Section 5.3.4
01E1 4018h
IENSET
Interrupt enable set register
Section 5.3.5
01E1 401Ch
IENCLR
Interrupt enable clear register
01E1 4200h
PROG1_MPSAR
Programmable range 1 start address register
Section 5.3.10.1
01E1 4204h
PROG1_MPEAR
Programmable range 1 end address register
Section 5.3.11.1
01E1 4208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 4210h
PROG2_MPSAR
Programmable range 2 start address register
Section 5.3.10.1
01E1 4214h
PROG2_MPEAR
Programmable range 2 end address register
Section 5.3.11.1
01E1 4218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 4220h
PROG3_MPSAR
Programmable range 3 start address register
Section 5.3.10.1
01E1 4224h
PROG3_MPEAR
Programmable range 3 end address register
Section 5.3.11.1
01E1 4228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 4230h
PROG4_MPSAR
Programmable range 4 start address register
Section 5.3.10.1
01E1 4234h
PROG4_MPEAR
Programmable range 4 end address register
Section 5.3.11.1
01E1 4238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 4240h
PROG5_MPSAR
Programmable range 5 start address register
Section 5.3.10.1
01E1 4244h
PROG5_MPEAR
Programmable range 5 end address register
Section 5.3.11.1
01E1 4248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 4250h
PROG6_MPSAR
Programmable range 6 start address register
Section 5.3.10.1
01E1 4254h
PROG6_MPEAR
Programmable range 6 end address register
Section 5.3.11.1
01E1 4258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
Section 5.3.12
01E1 4300h
FLTADDRR
Fault address register
Section 5.3.13
01E1 4304h
FLTSTAT
Fault status register
Section 5.3.14
01E1 4308h
FLTCLR
Fault clear register
Section 5.3.15
Section 5.3.6
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Table 5-7. Memory Protection Unit 2 (MPU2) Registers
Address
Acronym
Register Description
01E1 5000h
REVID
Revision identification register
Section 5.3.1
01E1 5004h
CONFIG
Configuration register
Section 5.3.2
01E1 5010h
IRAWSTAT
Interrupt raw status/set register
Section 5.3.3
01E1 5014h
IENSTAT
Interrupt enable status/clear register
Section 5.3.4
01E1 5018h
IENSET
Interrupt enable set register
Section 5.3.5
01E1 501Ch
IENCLR
Interrupt enable clear register
Section 5.3.6
01E1 5100h
FXD_MPSAR
Fixed range start address register
Section 5.3.7
01E1 5104h
FXD_MPEAR
Fixed range end address register
Section 5.3.8
01E1 5108h
FXD_MPPA
Fixed range memory protection page attributes register
Section 5.3.9
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Table 5-7. Memory Protection Unit 2 (MPU2) Registers (continued)
90
Address
Acronym
Register Description
01E1 5200h
PROG1_MPSAR
Programmable range 1 start address register
Section 5.3.10.2
01E1 5204h
PROG1_MPEAR
Programmable range 1 end address register
Section 5.3.11.2
01E1 5208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 5210h
PROG2_MPSAR
Programmable range 2 start address register
Section 5.3.10.2
01E1 5214h
PROG2_MPEAR
Programmable range 2 end address register
Section 5.3.11.2
01E1 5218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 5220h
PROG3_MPSAR
Programmable range 3 start address register
Section 5.3.10.2
01E1 5224h
PROG3_MPEAR
Programmable range 3 end address register
Section 5.3.11.2
01E1 5228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 5230h
PROG4_MPSAR
Programmable range 4 start address register
Section 5.3.10.2
01E1 5234h
PROG4_MPEAR
Programmable range 4 end address register
Section 5.3.11.2
01E1 5238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 5240h
PROG5_MPSAR
Programmable range 5 start address register
Section 5.3.10.2
01E1 5244h
PROG5_MPEAR
Programmable range 5 end address register
Section 5.3.11.2
01E1 5248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 5250h
PROG6_MPSAR
Programmable range 6 start address register
Section 5.3.10.2
01E1 5254h
PROG6_MPEAR
Programmable range 6 end address register
Section 5.3.11.2
01E1 5258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
01E1 5260h
PROG7_MPSAR
Programmable range 7 start address register
Section 5.3.10.2
01E1 5274h
PROG7_MPEAR
Programmable range 7 end address register
Section 5.3.11.2
01E1 5268h
PROG7_MPPA
Programmable range 7 memory protection page attributes register
01E1 5270h
PROG8_MPSAR
Programmable range 8 start address register
Section 5.3.10.2
01E1 5274h
PROG8_MPEAR
Programmable range 8 end address register
Section 5.3.11.2
01E1 5278h
PROG8_MPPA
Programmable range 8 memory protection page attributes register
01E1 5280h
PROG9_MPSAR
Programmable range 9 start address register
Section 5.3.10.2
01E1 5284h
PROG9_MPEAR
Programmable range 9 end address register
Section 5.3.11.2
01E1 5288h
PROG9_MPPA
Programmable range 9 memory protection page attributes register
01E1 5290h
PROG10_MPSAR
Programmable range 10 start address register
Section 5.3.10.2
01E1 5294h
PROG10_MPEAR
Programmable range 10 end address register
Section 5.3.11.2
01E1 5298h
PROG10_MPPA
Programmable range 10 memory protection page attributes register
01E1 52A0h
PROG11_MPSAR
Programmable range 11 start address register
Section 5.3.10.2
01E1 52A4h
PROG11_MPEAR
Programmable range 11 end address register
Section 5.3.11.2
01E1 52A8h
PROG11_MPPA
Programmable range 11 memory protection page attributes register
01E1 52B0h
PROG12_MPSAR
Programmable range 12 start address register
Section 5.3.10.2
01E1 52B4h
PROG12_MPEAR
Programmable range 12 end address register
Section 5.3.11.2
01E1 52B8h
PROG12_MPPA
Programmable range 12 memory protection page attributes register
Section 5.3.12
01E1 5300h
FLTADDRR
Fault address register
Section 5.3.13
01E1 5304h
FLTSTAT
Fault status register
Section 5.3.14
01E1 5308h
FLTCLR
Fault clear register
Section 5.3.15
Memory Protection Unit (MPU)
Section
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
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5.3.1 Revision Identification Register (REVID)
The revision ID register (REVID) contains the MPU revision. The REVID is shown in Figure 5-3 and
described in Table 5-8.
Figure 5-3. Revision ID Register (REVID)
31
0
REV
R-4E81 0101h
LEGEND: R = Read only; -n = value after reset
Table 5-8. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E81 0101h
Description
Revision ID of the MPU.
5.3.2 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown
in Figure 5-4 and described in Table 5-9.
NOTE: Although the NUM_AIDS bit defaults to 12 (Ch), not all AIDs may be supported on your
device. Unsupported AIDs should be cleared to 0 in the memory page protection attributes
registers (MPPA). See Table 5-3 for a list of AIDs supported on your device.
Figure 5-4. Configuration Register (CONFIG)
31
24
15
23
20
19
16
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-0 (1) or 6h (2)
R-0 (1) or 1 (2)
R-6h (1) or Ch (2)
12
11
1
0
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-Ch
R-0
R-1
LEGEND: R = Read only; -n = value after reset
(1)
(2)
For MPU1.
For MPU2.
Table 5-9. Configuration Register (CONFIG) Field Descriptions
Field
Value
Description
31-24
Bit
ADDR_WIDTH
0-FFh
Address alignment (2n kByte alignment) for range checking.
23-20
NUM_FIXED
0-Fh
Number of fixed address ranges.
19-16
NUM_PROG
0-Fh
Number of programmable address ranges.
15-12
NUM_AIDS
0-Fh
Number of supported AIDs.
11-1
Reserved
0
0
ASSUME_ALLOWED
Reserved
Assume allowed. When an address is not covered by any MPU protection range, this bit
determines whether the transfer is assumed to be allowed or not allowed.
0
Assume is disallowed.
1
Assume is allowed.
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5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 5-5 and described in Table 5-10.
Figure 5-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
92
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 5-6 and described in Table 511.
Figure 5-6. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.5 Interrupt Enable Set Register (IENSET)
Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Software can
write to IENSET to enable an interrupt. Writes of 0 have no effect. The IENSET is shown in Figure 5-7 and
described in Table 5-12.
Figure 5-7. Interrupt Enable Set Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-12. Interrupt Enable Set Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved
Address violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
PROTERR_EN
Protection violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
5.3.6 Interrupt Enable Clear Register (IENCLR)
Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Software can
write to IENCLR to clear/disable an interrupt. Writes of 0 have no effect. The IENCLR is shown in
Figure 5-8 and described in Table 5-13.
Figure 5-8. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-13. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
94
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved
Address violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
PROTERR_CLR
Protection violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
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5.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the EMIFB control registers (B000 0000h–B000 7FFFh).
However, these addresses are not indicated in FXD_MPSAR and the fixed range end address register
(FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in Figure 5-9.
Figure 5-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
5.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the EMIFB control registers (B000 0000h–B000 7FFFh). However,
these addresses are not indicated in FXD_MPEAR and the fixed range start address register
(FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 5-10.
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 5-11
and described in Table 5-14.
Figure 5-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-14. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
96
Controls access from ID = n.
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR)
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory, especially memory. One of the
programmable address ranges could be used to detect accesses to this unpopulated
memory.
The programmable range n start address register (PROGn_MPSAR) holds the start address for the range
n. The PROGn_MPSAR is writeable by a supervisor entity only.
The start address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 kBbyte; the page size for MPU2 is 64 kBytes. The size of the page determines
the width of the address field in PROGn_MPSAR and the programmable range n end address register
(PROGn_MPEAR). For example, to protect a 64-kB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
5.3.10.1 MPU1 Programmable Range n Start Address Register (PROG1_MPSAR-PROG6_MPSAR)
The PROGn_MPSAR for MPU1 is shown in Figure 5-12 and described in Table 5-15.
Figure 5-12. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
Reserved
R/W-20 0000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-15. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
START_ADDR
Reserved
20 0000h–
20 007Fh
0
Description
Start address for range N.
Reserved
5.3.10.2 MPU2 Programmable Range n Start Address Register (PROG1_MPSAR-PROG12_MPSAR)
The PROGn_MPSAR for MPU2 is shown in Figure 5-13 and described in Table 5-16.
Figure 5-13. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
31
16 15
0
START_ADDR
Reserved
R/W-C000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
Field
31-16
START_ADDR
15-0
Reserved
Value
C000h–DFFFh
0
Description
Start address for range N.
Reserved
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5.3.11 Programmable Range n End Address Registers (PROGn_MPEAR)
The programmable range n end address register (PROGn_MPEAR) holds the end address for the range
n. This register is writeable by a supervisor entity only.
The end address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 kByte; the page size for MPU2 is 64 kBytes. The size of the page determines the
width of the address field in the programmable range n start address register (PROGn_MPSAR) and
PROGn_MPEAR. For example, to protect a 64-kB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
5.3.11.1 MPU1 Programmable Range n End Address Register (PROG1_MPEAR-PROG6_MPEAR)
The PROGn_MPEAR for MPU1 is shown in Figure 5-14 and described in Table 5-17.
Figure 5-14. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
Reserved
R/W-20 007Fh
R-3FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-17. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
END_ADDR
Reserved
20 0000h–
20 007Fh
3FFh
Description
End address for range N.
Reserved
5.3.11.2 MPU2 Programmable Range n End Address Register (PROG1_MPEAR-PROG12_MPEAR)
The PROGn_MPEAR for MPU2 is shown in Figure 5-15 and described in Table 5-18.
Figure 5-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
31
16 15
0
END_ADDR
Reserved
R/W-DFFFh
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
Field
31-16
END_ADDR
15-0
Reserved
98
Value
C000h–DFFFh
FFFFh
Memory Protection Unit (MPU)
Description
Start address for range N.
Reserved
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5.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA)
The programmable range n memory protection page attributes register (PROGn_MPPA) holds the
permissions for the region n. This register is writeable only by a supervisor entity. The PROGn_MPPA is
shown in Figure 5-16 and described in Table 5-19.
Figure 5-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-19. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Controls access from ID = n.
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.13 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) holds the address of the first protection fault transfer. The
FLTADDRR is shown in Figure 5-17 and described in Table 5-20.
Figure 5-17. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-20. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
100
Field
FLTADDR
Value
0-FFFF FFFFh
Memory Protection Unit (MPU)
Description
Memory address of fault.
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5.3.14 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in Figure 5-18 and described in Table 5-21.
Figure 5-18. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
Reserved
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-21. Fault Status Register (FLTSTAT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MSTID
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
Value
0
0-FFh
0
0-Fh
0
0-3Fh
Description
Reserved
Master ID of fault transfer.
Reserved
Privilege ID of fault transfer.
Reserved
Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).
0
No fault.
1h
User execute fault.
2h
User write fault.
3h
Reserved
4h
User read fault.
5h-7h
8h
9h-Fh
Reserved
Supervisor execute fault.
Reserved
10h
Supervisor write fault.
11h
Reserved
12h
Relaxed cache write back fault.
13h-1Fh
20h
21h-3Eh
3Fh
Reserved
Supervisor read fault.
Reserved
Relaxed cache line fill fault.
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5.3.15 Fault Clear Register (FLTCLR)
The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured
in the fault status register (FLTSTAT) as well as produce an interrupt. Only the TYPE bit field in FLTSTAT
is cleared when a 1 is written to the CLEAR bit. The FLTCLR is shown in Figure 5-19 and described in
Table 5-22.
Figure 5-19. Fault Clear Register (FLTCLR)
31
16
Reserved
R-0
15
1
0
Reserved
CLEAR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 5-22. Fault Clear Register (FLTCLR) Field Descriptions
Bit
31-1
0
102
Field
Reserved
Value
0
CLEAR
Description
Reserved
Command to clear the current fault. Writing 0 has no effect.
0
No effect.
1
Clear the current fault.
Memory Protection Unit (MPU)
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Chapter 6
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Device Clocking
Topic
6.1
6.2
6.3
...........................................................................................................................
Page
Overview ......................................................................................................... 104
Frequency Flexibility ......................................................................................... 105
Peripheral Clocking .......................................................................................... 107
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Overview
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Overview
This device requires two primary reference clocks:
• One reference clock is required for the phase-locked loop controller (PLLC)
• One reference clock is required for the real-time clock (RTC) module. The RTC is not supported on the
C6745 DSP.
These reference clocks may be sourced from either a crystal input or by an external oscillator. For detailed
specifications on clock frequency and voltage requirements, see the device-specific data manual.
In addition to the reference clocks required for the PLLC and RTC module, some peripherals, such as the
USB, may also require an input reference clock to be supplied. All possible input clocks are described in
Table 6-1. The CPU and the majority of the device peripherals operate at fixed ratios of the primary
system/CPU clock frequency, as listed in Table 6-2. However, there are three system clock domains that
do not require a fixed ratio to the CPU clock frequency, these are SYSCLK3, SYSCLK5, and SYSCLK7.
Figure 6-1 shows the clocking architecture.
Table 6-1. Device Clock Inputs
Peripheral
Input Clock Signal Name
Oscillator/PLL
OSCIN
RTC (1)
RTC_XI
JTAG
TCK
EMAC
RMII_MHZ_50_CLK
USB2.0 and USB1.1 (1)
USB_REFCLKIN
McASPs (2)
ACLKRn, AHCLKRn, ACLKXn, AHCLKXn
I2Cs
I2Cn_SCL
SPIs
SPIn_CLK
Timer0
TM64P0_IN12
(1)
(2)
This peripheral is not supported on the C6745 DSP.
McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745
DSP.
Table 6-2. System Clock Domains
CPU/Device Peripherals
System Clock Domain
Fixed Ratio to
CPU Clock Required?
Default Ratio to
CPU Clock
DSP
SYSCLK1
Yes
1:1
PRU, UARTs, EDMA, SPIs, MMC/SD, Shared RAM (1),
eCAPs, eQEPs, eHRPWMs, LCDC (1), HPI (1),
McASPs (2), USB2.0, EMIFB
SYSCLK2
Yes
1:2
EMIFA
SYSCLK3
No
1:3
SYSCFG, PSCs, I2C1, USB1.1 (1), EMAC/MDIO, GPIO
SYSCLK4
Yes
1:4
EMIFB I/O Clock
SYSCLK5
No
1:3
EMAC
SYSCLK7
No
1:6
I2C0, Timers, McASP serial clock (2) , RTC (1), USB2.0
AUXCLK
Not Applicable
PLL Bypass
Clock
(1)
(2)
104
This peripheral is not supported on the C6745 DSP.
McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745 DSP.
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Figure 6-1. Overall Clocking Diagram
PLL Multiplier Out
PRU
Div 4.5
DSP
SYSCLK1 (/1)
EDMA
EMIFA
SYSCLK3 (/3)
SYSCLK4 (/4)
SPIs
System CFG
MMC/SD
PSCs
Shared RAM
I2C1
PLL
Ref Clk
PLL
Controller
UARTs
USB 1.1
(A)
EMAC/MDIO
USB REFCLKIN
From USB 2.0
Ref Clk 50 MHz
(A)
eCAPs
eQEPs
eHRPWMs
GPIO
SYSCLK7 (/6)
LCDC
SYSCLK2 (/2)
(A)
(A)
HPI
I2C0
AUXCLK
McASPs
Timers
RTC
(A)
SYSCLK5 (/n)
32 kHz
Reference
Clock
(B)
USB 2.0
USB
REFCLKIN
EMIFB
PLL Multiplier Out
6.2
Div 4.5
A
This peripheral is not supported on the C6745 DSP.
B
McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745 DSP.
Frequency Flexibility
There are two clocking modes:
• PLL Bypass that can serve as a power savings mode
• PLL Active where the PLL is enabled and multiplies the input clock up to the desired operating
frequency
When the PLL is in Bypass mode, the reference clock supplied on OSCIN serves as the clock source from
which all of the system clocks (SYSCLK1-SYSCLK7) are derived. This means, when the PLL is in Bypass
mode, the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that creates
each of the system clocks. When the PLL operates in Active mode, the PLL is enabled and the PLL
multiplier setting is used to multiply the input clock frequency supplied on the OSCIN pin up to the desired
frequency. It is this multiplied frequency that all system clocks are derived from in PLL Active mode.
The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the
system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1-SYSCLK7). Each
SYSCLK has a PLLDIV block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter
for more details on the PLL.
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The combination of the PLL multiplier, POSTDIV, and PLLDIV blocks provides flexibility in the frequencies
that the system clock domains support. This flexibility does have limitations, as follows:
• OSCIN input frequency is limited to a supported range.
• The output of the PLL Multiplier must be within the range specified in the device-specific data manual.
• The output of each PLLDIV block must be less than or equal to the maximum device frequency
specified in the device-specific data manual.
NOTE: The above limitations are provided here as an example and are used to illustrate the
recommended configuration of the PLL controller. These limitations may vary based on core
voltage and between devices. See the device-specific data manual for more details.
Table 6-3 shows examples of possible PLL multiplier settings, along with the available PLL post-divider
modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL
post-divider control register (POSTDIV). For Div1, Div2, Div3, and Div4 modes, the RATIO field would be
programmed to 0, 1, 2, and 3, respectively. The Div1, Div2, Div3, and Div4 modes are shown here as an
example. Additional post-divider modes are supported and are documented in the Phase-Locked Loop
Controller (PLLC) chapter.
NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases.
To decrease PLL power consumption, the lowest PLL multiplier (PLLM) setting should be
chosen that achieves the desired frequency. For example, if 200 MHz is the desired CPU
operating frequency and the OSCIN frequency is 25 MHz; lower power consumption is
achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2
instead of a PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these
modes would result in a CPU frequency of 200 MHz.
Table 6-3. Example PLL Frequencies
106
PLL Multiplier
Multiplier
Frequency
(MHz)
Div1
Div2
Div3
Div4
20
30
600
600
300
200
150
24
25
600
600
300
200
150
25
24
600
600
300
200
150
30
20
600
600
300
200
150
20
25
500
500
250
167
125
24
20
480
480
240
160
120
25
18
450
450
225
150
112.5
30
14
420
420
210
140
105
25
16
400
400
200
133
100
OSCIN
Frequency
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6.3
Peripheral Clocking
6.3.1 USB Clocking
Figure 6-2 displays the clock connections for the USB2.0 module. The USB2.0 subsystem requires a
reference clock for its internal PLL. This reference clock can be sourced from either the USB_REFCLKIN
pin or from the AUXCLK of the system PLL. The reference clock input to the USB2.0 subsystem is
selected by programming the USB0PHYCLKMUX bit in the chip configuration 2 register (CFGCHIP2) of
the System Configuration Module. The USB_REFCLKIN source should be selected when it is not possible
(such as when specific audio rates are required) to operate the device at one of the allowed input
frequencies to the USB2.0 subsystem. The USB2.0 subsystem peripheral bus clock is sourced from
SYSCLK2.
The USB1.1 subsystem requires both a 48 MHz (CLK48) and a 12 MHz (CLK12) clock input. The 12 MHz
clock is derived from the 48 MHz clock. The 48 MHz clock required by the USB1.1 subsystem can be
sourced from either the USB_REFCLKIN or from the 48 MHz clock provided by the USB2.0 PHY. The
CLK48 source is selected by programming the USB1PHYCLKMUX bit in CFGCHIP2 of the System
Configuration Module. The USB1.1 subsystem peripheral bus clock is sourced from SYSCLK4. See
Table 6-4.
NOTE:
If the USB1.1 subsystem is used and the 48 MHz clock input is sourced from the USB2.0
PHY, then the USB2.0 must be configured to always generate the 48 MHz clock. The
USB0PHY_PLLON bit in CFGCHIP2 controls the USB2.0 PHY, allowing or preventing it from
stopping the 48 MHz clock during USB SUSPEND. When the USB0PHY_PLLON bit is set to
1, the USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND;
when the USB0PHY_PLLON bit is cleared to 0, the USB2.0 PHY is allowed to stop the
48 MHz clock during USB SUSPEND.
Figure 6-2. USB Clocking Diagram
USB_
AUXCLK REFCLKIN
CFGCHIP2[USB0PHYCLKMUX]
1
0
USB 2.0
Subsystem
(USB0)
CLK48MHz From
USB2.0 PHY
0
1
CFGCHIP2[USB1PHYCLKMUX]
/4
CLK12
CLK48
USB 1.1
Subsystem
(USB1)
Note: The USB1.1 is not supported on the C6745 DSP.
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Table 6-4. USB Clock Multiplexing Options
CFGCHIP2.
CFGCHIP2.
USB0PHYCLKMUX USB1PHYCLKMUX
bit
bit
108
USB2.0
Clock
Source
USB1.1
Clock
Source
Additional Conditions
0
0
USB_REFCLKIN
CLK48MHZ output
from USB2.0 PHY
USB_REFCLKIN must be 12, 24, 48,
19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies.
0
1
USB_REFCLKIN
USB_REFCLKIN
USB_REFCLKIN must be 48 MHz. The
PLL inside the USB2.0 PHY can be
configured to accept this input clock
frequency.
1
0
PLL0_AUXCLK
CLK48MHZ output
from USB2.0 PHY
PLL0_AUXCLK must be 12, 24, 48, 19.2,
38.4, 13, 26, 20, or 40 MHz. The PLL
inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies.
1
1
PLL0_AUXCLK
USB_REFCLKIN
PLL0_AUXCLK must be 12, 24, 48, 19.2,
38.4, 13, 26, 20, or 40 MHz. The PLL
inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies. USB_REFCLKIN must
be 48 MHz.
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6.3.2 EMIFB Clocking
The EMIFB requires two input clocks to source VCLK and MCLK (see Figure 6-3):
• VCLK is sourced from SYSCLK2 that clocks the peripheral bus interface of EMIFB
• MCLK, which sets the clock rate for the I/O clock (EMB_CLK), is sourced from either SYSCLK5 or
DIV4P5. The EMB_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the System
Configuration Module controls whether SYSCLK5 or DIV4P5 is selected as the clock source for MCLK.
Selecting the appropriate clock source for MCLK is determined by the desired clock rate of the memory
clock, EMB_CLK. Table 6-5 shows example PLL register settings and the resulting DIV4P5 and SYSCLK5
frequencies based on the OSCIN reference clock frequency of 25 MHz. From these example
configurations, the following observations can be made:
• To achieve the maximum frequency (133 MHz) supported by EMIFB and the typical CPU frequency of
300 MHz, the output of the PLL multiplier should be set to be 600 MHz and the EMB_CLK source
should be set to DIV4P5.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV5 block that sets the divider ratio for SYSCLK5 can be changed to achieve various clock
frequencies.
• For certain PLL multiplier and PLL post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK5 as the clock source for MCLK.
As shown in Figure 6-3, the EMIFB output clock, EMB_CLK, can be sourced from either the output of the
EMIFB LPSC (CLK1 in Figure 6-3) or directly from the output of the clock multiplexer selecting either
DIV4P5 or SYSCLK5 (CLK2 in Figure 6-3). The PINMUX0_15_12 bits in the pin multiplexing control 0
register (PINMUX0) of the SCM control this clock selection.
The purpose in providing two clock sources for EMB_CLK is to support the ability to generate a free
running clock that could be used by an FPGA or for some other purpose. The difference between CLK1
and CLK2 is that if LPSC #6 is configured to clock gate the EMIFB, then CLK1 will also be clock gated,
but CLK2 will not be clock gated. Therefore, if EMIFB is being used to interface to an SDRAM memory, it
is best practice to choose CLK1 as the source for EMB_CLK. This will allow the maximum power savings
when the LPSC is used to clock gate the EMIFB clock. If EMIFB is not in use and the EMB_CLK is used
in the application as a free running clock, then CLK2 should be used as the source for EMB_CLK. This will
allow clock gating of the majority of the logic in EMIFB via the LPSC while still providing a clock on the
EMB_CLK.
NOTE: EMB_CLK is only an output clock. EMIFB does not support an externally provided input
clock.
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Figure 6-3. EMIFB Clocking Diagram
On Chip
PLL Controller
EMIFB
SYSCLK2
VCLK
SYSCLK5
LPSC #6
EMB_CLK
Signal
SDRAM_IN_CLK
0
DIV4P5 CLK
MCLK
1
CLK1
CFGCHIP3[EMB_CLKSRC]
0001
CLK2
0010
PINMUX0[15:12]
Table 6-5. EMIFB MCLK Frequencies
OSCIN
Frequency
PLL Multiplier Multiplier
Register
Frequency
Setting
(MHz)
Post Divider
Mode (1)
POSTDIV
Output
Frequency
25
24
Div2
Div3
25
18
25
(1)
110
16
600
450
400
DIV4P5
PLLDIV5
Register
Setting
SYSCLK5
300 MHz
133 MHz
2
100 MHz
200 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
Div2
225 MHz
100 MHz
2
75 MHz
1
112.5 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
2
66.6 MHz
Div2
200 MHz
89 MHz
1
100 MHz
Div3
133 MHz
89 MHz
0
133 MHz
Div4
100 MHz
89 MHz
0
133 MHz
See Section 6.2 for an explanation of POSTDIV divider modes.
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6.3.3 EMIFA Clocking
EMIFA requires a single input clock source. The EMIFA clock can be sourced from either SYSCLK3 or
DIV4P5 (see Figure 6-4). The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the
System Configuration Module controls whether SYSCLK3 or DIV4P5 is selected as the clock source for
EMIFA.
Selecting the appropriate clock source for EMIFA is determined by the desired clock rate. Table 6-6 shows
example PLL register settings and the resulting DIV4P5 and SYSCLK3 frequencies based on the OSCIN
reference clock frequency of 25 MHz. From these example configurations, the following observations can
be made:
• To achieve a typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300
MHz, the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be
set to SYSCLK3 with the PLLDIV3 register set to 3.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV3 block that sets the divider ratio for SYSCLK3 can be changed to achieve various clock
frequencies.
Figure 6-4. EMIFA Clocking Diagram
LPSC
PLL Controller
SYSCLK3
0
DIV4P5 CLK
1
EMIFA
CFGCHIP3[EMA_CLKSRC]
Table 6-6. EMIFA Frequencies
OSCIN
Frequency
PLL Multiplier Multiplier
Register
Frequency
Setting
(MHz)
Post Divider
Mode (1)
POSTDIV
Output
Frequency
25
24
Div2
300 MHz
Div3
200 MHz
25
25
(1)
18
16
600
450
400
DIV4P5
PLLDIV3
Register
Setting
SYSCLK3
133 MHz
2
100 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
Div2
225 MHz
100 MHz
3
56.3 MHz
2
75 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
2
66.6 MHz
1
100 MHz
Div2
200 MHz
89 MHz
Div3
133 MHz
89 MHz
1
66.5 MHz
Div4
100 MHz
89 MHz
0
100 MHz
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.4 EMAC Clocking
The EMAC module sources its peripheral bus interface reference clock from SYSCLK4 that is at a fixed
ratio of the CPU clock. The external clock requirement for EMAC varies with the interface used. When the
MII interface is active, the MII_TXCLK and MII_RXCLK signals must be provided from an external source.
When the RMII interface is active, the RMII 50 MHz reference clock is sourced either from an external
clock on the RMII_MHZ_50_CLK pin or from SYSCLK7 (as shown in Figure 6-5). The PINMUX9_23_20
bits in the pin multiplexing control 9 register (PINMUX9) of the System Configuration Module control this
clock selection:
• PINMUX9_23_20 = 0: enables sourcing of the 50 MHz reference clock from an external source on the
RMII_MHZ_50_CLK pin.
• PINMUX9_23_20 = 2h: enables sourcing of the 50 MHz reference clock from SYSCLK7. Also,
SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin.
Table 6-7 shows example PLL register settings and the resulting SYSCLK7 frequencies based on the
OSCIN reference clock frequency of 25 MHz.
Figure 6-5. EMAC Clocking Diagram
On Chip
PLL Controller
LPSC
EMAC
SYSCLK4
SYSCLK7
50 MHz Reference Clock
PINMUX9[23:20]
0010 0000
3-State
0000 0010
RMII_MHZ_50_CLK
Signal
NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of
50 MHz +/-50 ppm.
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Table 6-7. EMAC Reference Clock Frequencies
OSCIN
Frequency
PLL Multiplier
Register Setting
Multiplier
Post Divider
Frequency (MHz) Mode (1)
POSTDIV Output
Frequency
PLLDIV7
Register Setting
SYSCLK7
25
24
600
Div2
300 MHz
5
50 MHz
Div3
200 MHz
3
50 MHz
Div4
150 MHz
2
50 MHz
Div2
225 MHz
Div3
150 MHz
Div4
112.5 MHz
25
(1)
(2)
18
450
Not Applicable (2)
2
50 MHz
Not Applicable (2)
See Section 6.2 for explanation of POSTDIV divider modes.
Certain PLL configurations do not support a 50 MHz clock on SYSCLK7.
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6.3.5 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
Peripherals can be divided into 4 groups, depending upon their clock requirements, as shown in
Table 6-8.
Table 6-8. Peripherals
Peripheral Group
Peripheral Group Definition
Peripherals Contained
within Group
—
RTC
Operates off of a dedicated
32 kHz crystal oscillator.
RTC
Fixed-Frequency Peripherals
As the name suggests, fixedfrequency peripherals have a
fixed-frequency. They are fed the
AUXCLK directly from the
oscillator input.
Timers
—
I2C0
—
Synchronous peripherals have
their frequencies derived from the
CPU clock frequency. The
peripheral system clock frequency
changes accordingly, if the PLL1
frequency changes. Most
synchronous peripherals have
internal dividers so they can
generate their required clock
frequencies.
eCAP
—
eQEP
—
eHRPWM
—
MMC/SD
—
UARTs
—
GPIO
—
Synchronous Peripherals
HPI (1)
LCDC
Asynchronous Peripherals
Synchronous/Asynchronous
Peripherals
(1)
(2)
114
Source of Peripheral Clock
(1)
—
(1)
Asynchronous peripherals are not EMIFA
required to operate at a fixed ratio
EMIFB
of the CPU clock.
Synchronous/asynchronous
peripherals can be run with either
internally generated synchronous
clocks, or externally generated
asynchronous clocks.
—
DIV4P5 or SYSCLK3
DIV4P4 or SYSCLK5
McASPs (2)
AUXCLK or
Peripheral Serial Clocks
SPIs
SYSCLK2 or
Peripheral Serial Clock
I2C1
SYSCLK4 or
Peripheral Serial Clock
USB (1)
USB_REF_CLK or AUXCLK
EMAC
SYSCLK7 or
RMII_MHZ_50_CLK
This peripheral is not supported on the C6745 DSP.
McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745 DSP.
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Chapter 7
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Phase-Locked Loop Controller (PLLC)
Topic
...........................................................................................................................
7.1
7.2
7.3
7.4
Introduction .....................................................................................................
PLL0 Control ....................................................................................................
Locking/Unlocking PLL Register Access .............................................................
PLLC Registers ................................................................................................
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116
120
121
115
Introduction
7.1
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Introduction
This device has one phase-locked loop (PLL) controller, PLL0, that provides a clock to different parts of
the system. PLL0 provides clocks (through various dividers) to most of the components of the device.
The PLL0 provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power-down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
• Pre-PLL Divider: PREDIV
• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, …, Dn
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
7.2
PLL0 Control
PLL0 supplies the primary system clock. Software controls the PLL0 operation through the system PLL
controller 0 (PLLC0) registers. Figure 7-1 shows the PLL0 in the device.
AUXCLK is the clock provided to the fixed clock domain.
The PLL0 multiplier is controlled by the PLLM bits in the PLL multiplier control register (PLLM) and is set
to a default value of 0000 0013h at power-up, resulting in a PLL multiplier of 20×. The PLL0 output clock
may be divided-down for slower device operation using the PLLC0 post-divider. This divider defaults to a
/2 value, but may be modified by software (RATIO bit in POSTDIV) to achieve lower power device
operation. These default settings yield a 300-MHz PLL output clock when using a 30-MHz clock source.
The PLL0 multiplier may be modified by software.
At power-up, PLL0 is powered-down/disabled and must be powered-up by software through the
PLLPWRDN bit in the PLL control register (PLLCTL). The system operates in bypass mode by default and
the system clock (OSCIN) is provided directly from an input reference clock (square wave or internal
oscillator) selected by the CLKMODE bit in PLLCTL. Once the PLL is powered-up and locked, software
can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
Registers used in PLLC0 are listed in Section 7.4.
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Figure 7-1. PLL0 Structure
CLKMODE
OSCIN
PLLEN
Square
Wave
1
Crystal
0
Pre-Div
PLL
Post-Div
PLLM
1
PLLDIV1 (/1)
SYSCLK1
0
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
AUXCLK
0
DIV4.5
1
EMIFA
Internal
Clock
Source
CFGCHIP3[EMA_CLKSRC]
DIV4.5
1
0
EMIFB
Internal
Clock
Source
CFGCHIP3[EMB_CLKSRC]
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
OSCDIV(A)
OBSCLK Pin
OCSEL[OCSRC]
A
This register is not supported on the C6745 DSP.
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7.2.1 Device Clock Generation
PLL0 is controlled by PLL controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
PLLC0 generates several clocks from the PLL0 output clock for use by the various processors and
modules. These are summarized in Table 7-1. The output clock divider values SYSCLK1 to SYSCLKn are
fixed. This maintains the clock ratios between the various device components no matter what reference
clock (PLL or bypass) or PLL frequency is used.
Table 7-1. System PLLC0 Output Clocks
Output
Clock
Used by
Default Ratio (relative
to SYSCLK1)
SYSCLK1
Notes
DSP
/1
Fixed Ratio
SYSCLK2
EDMA, DSP ports, EMIFB (bus ports), eCAPs, eHRPWMs,
eQEPs, Shared RAM (1), LCDC (1), McASPs (2), SPIs, MMC/SD,
HPI (1), USB2.0, UARTs, PRU
/2
Fixed Ratio
SYSCLK3
EMIFA
/3
No Required Ratio
SYSCLK4
System configuration (SYSCFG), PLLC0, PSCs, EMAC/MDIO,
GPIO, I2C1, USB1.1 (1)
/4
Fixed Ratio
SYSCLK5
EMIFB
/3
No Required Ratio
SYSCLK7
RMII clock to EMAC
/6
No Required Ratio
AUXCLK
McASP serial clock (2), Timers, I2C0, RTC (1), USB2.0
PLL Bypass Clock
Not Applicable
Pin configurable
Not Applicable
OBSCLK
(1)
(2)
(3)
•
•
•
118
(3)
Observation clock (OBSCLK) source
This peripheral is not supported on the C6745 DSP.
McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745 DSP.
This is not supported on the C6745 DSP. On the C6747 DSP, this is only available on the ZKB device package type.
The divide values in PLL controller 0 for SYSCLK1/SYSCLK6, SYSCLK2, and SYSCLK4 are not fixed
so that you can change the divide values for power saving reasons. But you are responsible to assure
that the divide ratios between these clock domains must be fixed to 1:2:4.
PLL controller supports post-divider value n = 4.5. When 4.5 divide values are used, the duty cycle of
the resulting clock will not be 50%. In this case, the duty cycle will be 44.4%. For EMIF clock
generation, see the next note.
The DIV4P5 (/4.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL
clock for use as clocks to the EMIFs. See Figure 7-1.
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7.2.2 Steps for Changing PLL0 Domain Frequency
Refer to the appropriate subsection on how to program the PLL0/Core Domain clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 7.2.2.1 to initialize the PLL.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 7.2.2.2 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers,
follow the sequence in Section 7.2.2.3.
Note that the PLL is powered down after a Power-on Reset (POR). The PLL is not powered down after a
Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the PLLDIVx
registers are reset to default values.
7.2.2.1
Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Clear the PLLEN bit in PLLCTL to 0 (select PLL Bypass mode) and reset the PLL by clearing PLLRST
bit in PLLCTL. Wait for 4 OSCIN cycles to ensure PLLC switches to bypass mode properly.
2. Select the clock mode by programming the CLKMODE bit in PLLCTL.
(a) Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
(b) PLLCTL.EXTCLKSRC should be left to 0.
3. Clear the PLLRST bit in PLLCTL to 0 (reset PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
5. Program the required multiplier value in PLLM. If desired to scale all the SYSCLK frequencies of a
given PLLC, program the POSTDIV ratio.
6. If necessary, program PLLDIVn registers to change the SYSCLK0 to SYSCLKn divide values:
(a) Check for GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
(b) Program the RATIO field in PLLDIVx with the desired divide factors.
(c) Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).
7. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
8. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
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7.2.2.2
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Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), perform the following
procedure to change PLL0 multiplier.
1. Before changing the PLL frequency, switch to PLL bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
(b) Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
(c) Wait for 4 OSCIN cycles to ensure PLLC switches to bypass mode properly.
2. Clear the PLLRST bit in PLLCTL to 0 (reset PLL).
3. Program the required multiplier value in PLLM. If desired to scale all the SYSCLK frequencies of a
given PLLC, program the POSTDIV ratio.
4. If necessary, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Program the RATIO field in PLLDIVn with the desired divide factors.
(b) Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
(c) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).
5. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
6. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
7. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
7.2.2.3
Changing SYSCLK Dividers
This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider
change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in
PLLCMD) to initiate the divider change.
1. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
2. Program the RATIO field in PLLDIVn with the desired divide factors.
3. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7.3
Locking/Unlocking PLL Register Access
A lock mechanism is present on the device that can prevent inadvertent reconfiguration of the PLLC
registers. This primarily provides protection for the watchdog timer that runs on the AUXCLK output of
PLL0. The PLL has a bit that is capable of disabling AUXCLK and therefore capable of stopping the
watchdog timer.
To prevent this, when the PLL_MASTER_LOCK bit of the chip configuration 0 register (CFGCHIP0) in the
System Configuration Module is set, writes to any PLLC registers are locked. The PLL_MASTER_LOCK
bit is protected as type "Priv" and it is also protected by the Kick0 and Kick1 registers in the System
Configuration Module. The master writing to the Kick0/Kick1/CFGCHIP0 registers needs to have
appropriate privilege, and write the correct key values to the Kick0 and Kick 1 registers before writing to
the PLLC registers. See the System Configuration (SYSCFG) Module chapter for information on privilege
type and the Kick0 and Kick1 registers.
To
1.
2.
3.
4.
modify the PLLC registers, use the following sequence:
Write the correct key values to Kick0 and Kick1 registers.
Clear the PLL_MASTER_LOCK bit in CFGCHIP0.
Configure the desired PLLC register values.
Write an incorrect key value to the Kick registers.
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 defaults to unlocked after reset, so the above
procedure is only required after the PLL_MASTER_LOCK bit has been locked (set to 1).
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7.4
PLLC Registers
Table 7-2 lists the memory-mapped registers for the PLLC.
Table 7-2. PLL Controller (PLLC) Registers
Address
Acronym
Register Description
01C1 1000h
REVID
Revision Identification Register
Section 7.4.1
01C1 10E4h
RSTYPE
Reset Type Status Register
Section 7.4.2
01C1 1100h
PLLCTL
PLL Control Register
Section 7.4.3
(1)
Section
01C1 1104h
OCSEL
OBSCLK Select Register
Section 7.4.4
01C1 1110h
PLLM
PLL Multiplier Control Register
Section 7.4.5
01C1 1114h
PREDIV
PLL Pre-Divider Control Register
Section 7.4.6
01C1 1118h
PLLDIV1
PLL Controller Divider 1 Register
Section 7.4.7
01C1 111Ch
PLLDIV2
PLL Controller Divider 2 Register
Section 7.4.8
01C1 1120h
PLLDIV3
PLL Controller Divider 3 Register
Section 7.4.9
(1)
01C1 1124h
OSCDIV
Oscillator Divider 1 Register (OBSCLK)
Section 7.4.14
01C1 1128h
POSTDIV
PLL Post-Divider Control Register
Section 7.4.15
01C1 1138h
PLLCMD
PLL Controller Command Register
Section 7.4.16
01C1 113Ch
PLLSTAT
PLL Controller Status Register
Section 7.4.17
01C1 1140h
ALNCTL
PLL Controller Clock Align Control Register
Section 7.4.18
01C1 1144h
DCHANGE
PLLDIV Ratio Change Status Register
Section 7.4.19
01C1 1148h
CKEN
Clock Enable Control Register
Section 7.4.20
01C1 114Ch
CKSTAT
Clock Status Register
Section 7.4.21
01C1 1150h
SYSTAT
SYSCLK Status Register
Section 7.4.22
01C1 1160h
PLLDIV4
PLL Controller Divider 4 Register
Section 7.4.10
01C1 1164h
PLLDIV5
PLL Controller Divider 5 Register
Section 7.4.11
01C1 1168h
PLLDIV6
PLL Controller Divider 6 Register
Section 7.4.12
01C1 116Ch
PLLDIV7
PLL Controller Divider 7 Register
Section 7.4.13
01C1 11F0h
EMUCNT0
Emulation Performance Counter 0 Register
Section 7.4.23
01C1 11F4h
EMUCNT1
Emulation Performance Counter 1 Register
Section 7.4.24
(1)
This register is not supported on the C6745 DSP.
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7.4.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 7-2 and described in Table 7-3.
Figure 7-2. Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -n = value after reset
Table 7-3. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 3C00h
Description
Peripheral revision ID.
7.4.2 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) is shown in Figure 7-3 and described in Table 7-4. RSTYPE
latches the cause of the last reset. If multiple reset sources are asserted simultaneously, RSTYPE records
the reset source that deasserts last. If multiple reset sources are asserted and deasserted simultaneously,
RSTYPE latches the highest priority reset source.
Figure 7-3. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
PLLSWRST
XWRST
POR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-4. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-3
2
1
0
122
Field
Reserved
Value
0
PLLSWRST
Description
Reserved
PLL software reset.
0
PLL soft reset was not the last reset to occur.
1
PLL soft was the last reset to occur.
XWRST
External warm reset.
0
External warm reset was not the last reset to occur.
1
External warm reset was the last reset to occur.
POR
Power on reset.
0
Power On Reset (POR) was not the last reset to occur.
1
Power On Reset (POR) was the last reset to occur.
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7.4.3 PLL Control Register (PLLCTL)
The PLL control register (PLLCTL) is shown in Figure 7-4 and described in Table 7-5.
Figure 7-4. PLL Control Register (PLLCTL)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
9
CLKMODE
8
Reserved
7
6
PLLENSRC
Reserved
PLLRST
Rsvd
PLLPWRDN
PLLEN
R-0
R/W-0
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-5. PLL Control Register (PLLCTL) Field Descriptions
Bit
31-9
8
Field
Reserved
Value
0
CLKMODE
Description
Reserved
Reference Clock Selection
0
Internal oscillator (crystal)
1
Square wave
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before PLLEN will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
7-6
2
Reserved
1
PLLPWRDN
0
Asserts RESET to PLL if supported.
0
PLL reset is asserted
1
PLL reset is not asserted
0
Reserved
PLL power-down.
0
PLL operation
1
PLL power-down
PLLEN
PLL mode enables.
0
Bypass mode
1
PLL mode, not bypassed
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7.4.4 OBSCLK Select Register (OCSEL)
NOTE: This register is not supported on the C6745 DSP.
The OBSCLK select register (OCSEL) controls which clock is output on the OBSCLK pin so that it may be
used for test and debug purposes (in addition to its normal function of being a direct input clock divider).
The OCSEL is shown in Figure 7-5 and described in Table 7-6.
Figure 7-5. OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-6. OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
OBSCLK source. Output on OBSCLK pin.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
124
17h
PLLC0 SYSCLK1
18h
PLLC0 SYSCLK2
19h
PLLC0 SYSCLK3
1Ah
PLLC0 SYSCLK4
1Bh
PLLC0 SYSCLK5
1Ch
PLLC0 SYSCLK6
1Dh
PLLC0 SYSCLK7
1Eh
Reserved
1Fh
Disabled
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7.4.5 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 7-6 and described in Table 7-7.
Figure 7-6. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PLLM
Value
0
0-1Fh
Description
Reserved
PLL Multiplier Select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
7.4.6 PLL Pre-Divider Control Register (PREDIV)
The PLL pre-divider control register (PREDIV) is shown in Figure 7-7 and described in Table 7-8.
Figure 7-7. PLL Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-8. PLL Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-14
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Pre_Divider enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
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7.4.7 PLL Controller Divider 1 Register (PLLDIV1)
The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-8 and described in Table 7-9.
Divider 1 controls the divider for SYSCLK1.
Figure 7-8. PLL Controller Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-9. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.4.8 PLL Controller Divider 2 Register (PLLDIV2)
The PLL controller divider 2 register (PLLDIV2) is shown in Figure 7-9 and described in Table 7-10.
Divider 2 controls the divider for SYSCLK2.
Figure 7-9. PLL Controller Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-10. PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D2EN
14-5
Reserved
4-0
RATIO
126
Value
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
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7.4.9 PLL Controller Divider 3 Register (PLLDIV3)
The PLL controller divider 3 register (PLLDIV3) is shown in Figure 7-10 and described in Table 7-11.
Divider 3 controls the divider for SYSCLK3.
Figure 7-10. PLL Controller Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-11. PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
7.4.10 PLL Controller Divider 4 Register (PLLDIV4)
The PLL controller divider 4 register (PLLDIV4) is shown inFigure 7-11 and described in Table 7-12.
Divider 4 controls the divider for SYSCLK4.
Figure 7-11. PLL Controller Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D4EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4).
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7.4.11 PLL Controller Divider 5 Register (PLLDIV5)
The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-12 and described in Table 7-13.
Divider 5 controls the divider for SYSCLK5.
Figure 7-12. PLL Controller Divider 5 Register (PLLDIV5)
31
16
Reserved
R-0
15
14
5
4
0
D5EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D5EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
7.4.12 PLL Controller Divider 6 Register (PLLDIV6)
The PLL controller divider 6 register (PLLDIV6) is shown in Figure 7-13 and described in Table 7-14.
Divider 6 controls the divider for SYSCLK6.
Figure 7-13. PLL Controller Divider 6 Register (PLLDIV6)
31
16
Reserved
R-0
15
14
5
4
0
D6EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-14. PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D6EN
14-5
Reserved
4-0
RATIO
128
Value
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
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7.4.13 PLL Controller Divider 7 Register (PLLDIV7)
The PLL controller divider 7 register (PLLDIV7) is shown in Figure 7-14 and described in Table 7-15.
Divider 7 controls the divider for SYSCLK7.
Figure 7-14. PLL Controller Divider 7 Register (PLLDIV7)
31
16
Reserved
R-0
15
14
5
4
0
D7EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15. PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D7EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider Enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).
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7.4.14 Oscillator Divider 1 Register (OSCDIV)
NOTE: This register is not supported on the C6745 DSP.
The oscillator divider 1 register (OSCDIV) controls the divider for OBSCLK, dividing down the clock
selected as the OBSCLK source from the OBSCLK select register (OCSEL). The OBSCLK is connected
to the OBSCLK pin. The OSCDIV is shown in Figure 7-15 and described in Table 7-16.
Figure 7-15. Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16. Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
31-16
15
Field
Reserved
0
OD1EN
14-5
Reserved
4-0
RATIO
130
Value
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in the
clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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7.4.15 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 7-16 and described in Table 7-17.
Figure 7-16. PLL Post-Divider Control Register (POSTDIV)
31
16
Reserved
R-0
15
14
5
4
0
POSTDEN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-17. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
POSTDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Post_Divider enable.
0
Disable
1
Enable
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
7.4.16 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) is shown in Figure 7-17 and described in Table 7-18.
contains command bits for various operations. Writes of 1 initiate command; writes of 0 clear the bit, but
have no effect.
Figure 7-17. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 7-18. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for SYSCLKx phase alignment.
0
Clear bit (no effect)
1
Phase alignment
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7.4.17 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 7-18 and described in Table 7-19.
Figure 7-18. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
STABLE
Reserved
GOSTAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-19. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
132
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation. If 1, indicates GO operation is in progress.
0
GO operation is not in progress.
1
GO operation is in progress.
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7.4.18 PLL Controller Clock Align Control Register (ALNCTL)
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-19 and described in Table 720. Indicates which SYSCLKs need to be aligned for proper device operation.
Figure 7-19. PLL Controller Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-20. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
0
ALN7
Description
Reserved
SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN6
SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN5
SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN4
SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN3
SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.4.19 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLDIV ratio change status register (DCHANGE) is shown in Figure 7-20 and described in Table 721. Indicates if SYSCLK divide ratio has been modified.
Figure 7-20. PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-21. PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
134
Field
Reserved
Value
0
SYS7
Description
Reserved
SYSCLK7 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS6
SYSCLK6 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS5
SYSCLK5 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS4
SYSCLK4 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS3
SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.4.20 Clock Enable Control Register (CKEN)
The clock enable control register (CKEN) is shown in Figure 7-21 and described in Table 7-22. Clock
enable control for miscellaneous output clocks.
Figure 7-21. Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN (1)
AUXEN
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Table 7-22. Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK enable. Actual OBSCLK status is shown in the clock status register (CKSTAT). This bit is not
supported and is Reserved on the C6745 DSP. Write the default value when modifying this register.
0
OBSCLK is disabled.
1
OBSCLK is enabled. For OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in the oscillator
divider 1 register (OSCDIV) must be set to 1.
AUXEN
AUXCLK enable. Actual AUXCLK status is shown in the clock status register (CKSTAT).
0
AUXCLK is disabled.
1
AUXCLK is enabled.
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7.4.21 Clock Status Register (CKSTAT)
The clock status register (CKSTAT) is shown in Figure 7-22 and described in Table 7-23. Clock status for
all clocks, except SYSCLKn.
Figure 7-22. Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
OBSON (1)
AUXEN
R-0
R-1
R-1
LEGEND: R = Read only; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Table 7-23. Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
136
Field
Reserved
Value
0
OBSON
Description
Reserved
OBSCLK on status. OBSCLK is controlled in the oscillator divider 1 register (OSCDIV) and by the
OBSEN bit in the clock enable control register (CKEN). This bit is not supported and is Reserved on the
C6745 DSP.
0
OBSCLK is off.
1
OBSCLK is on.
AUXEN
AUXCLK on status. AUXCLK is controlled by the AUXEN bit in the clock enable control register
(CKEN).
0
AUXCLK is off.
1
AUXCLK is on.
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7.4.22 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) is shown in Figure 7-23 and described in Table 7-24. Indicates
SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on the
DnEN bit in PLLDIVn default.
Figure 7-23. SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-0
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-24. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-7
Reserved
6
SYS7ON
5
4
3
2
1
0
Value
0
Description
Reserved
SYSCLK7 on status
0
Off
1
On
SYS6ON
SYSCLK6 on status
0
Off
1
On
SYS5ON
SYSCLK5 on status
0
Off
1
On
SYS4ON
SYSCLK4 on status
0
Off
1
On
SYS3ON
SYSCLK3 on status
0
Off
1
On
SYS2ON
SYSCLK2 on status
0
Off
1
On
SYS1ON
SYSCLK1 on status
0
Off
1
On
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7.4.23 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 7-24 and described in
Table 7-25. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 7-24. Emulation Performance Counter 0 Register (EMUCNT0)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-25. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit
31-0
Field
Value
COUNT
0-FFFF FFFFh
Description
Counter value for lower 64-bits.
7.4.24 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 7-25 and described in
Table 7-26. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 7-25. Emulation Performance Counter 1 Register (EMUCNT1)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-26. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit
31-0
138
Field
COUNT
Value
0-FFFF FFFFh
Description
Counter value for upper 64-bits.
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Chapter 8
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Power and Sleep Controller (PSC)
Topic
...........................................................................................................................
8.1
8.2
8.3
8.4
8.5
8.6
Introduction .....................................................................................................
Power Domain and Module Topology ..................................................................
Executing State Transitions ...............................................................................
IcePick Emulation Support in the PSC ................................................................
PSC Interrupts..................................................................................................
PSC Registers ..................................................................................................
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140
144
145
145
148
139
Introduction
8.1
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Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control. Many of the operations of the PSC are transparent to user
(software), such as power on and reset control. However, the PSC module(s) also provide you with
interface to control several important power, clock and reset operations. The module level power, clock
and reset operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for DSP memories and L3 RAM)
• Supports IcePick emulation features: power, clock and reset
8.2
Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of an Always On power domain and
an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in the
DSP subsystem and the L3 RAM , respectively.
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 8-1 and Table 8-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 8.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have a LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
Table 8-1. PSC0 Default Module Configuration
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
0
EDMA3 Channel Controller
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4
SPI0
AlwaysON (PD0)
SwRstDisable
—
5
MMC/SD0
AlwaysON (PD0)
SwRstDisable
—
6-8
Not Used
—
—
—
9
UART0
AlwaysON (PD0)
SwRstDisable
—
10
Not Used
—
—
—
11
SCR1 (BR4)
AlwaysON (PD0)
Enable
Yes
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Table 8-1. PSC0 Default Module Configuration (continued)
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
12
SCR2 (BR3, BR5, BR6)
AlwaysON (PD0)
Enable
Yes
13
PRU
AlwaysON (PD0)
SwRstDisable
—
14
Not Used
—
—
—
15
DSP
PD_DSP (PD1)
Enable
—
Table 8-2. PSC1 Default Module Configuration
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
0
Not Used
—
—
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
USB1 (USB1.1) (1)
AlwaysON (PD0)
SwRstDisable
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
HPI
(1)
AlwaysON (PD0)
SwRstDisable
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
EMIFB (BR20)
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 (+ McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8
McASP1 (+ McASP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
9
McASP2 (+ McASP2 FIFO) (1)
AlwaysON (PD0)
SwRstDisable
—
10
SPI1
AlwaysON (PD0)
SwRstDisable
—
11
I2C1
AlwaysON (PD0)
SwRstDisable
—
12
UART1
AlwaysON (PD0)
SwRstDisable
—
13
UART2
AlwaysON (PD0)
SwRstDisable
—
14-15
Not Used
—
—
—
16
LCDC (1)
AlwaysON (PD0)
SwRstDisable
—
17
eHRPWM0/1/2
AlwaysON (PD0)
SwRstDisable
—
18-19
Not Used
—
—
—
20
eCAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
eQEP0/1
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR8 (BR15)
AlwaysON (PD0)
Enable
Yes
25
SCR7 (BR12)
AlwaysON (PD0)
Enable
Yes
26
SCR12 (BR18)
AlwaysON (PD0)
Enable
Yes
27-30
Not Used
—
—
—
31
Shared RAM (BR13) (1)
PD_SHRAM
Enable
Yes
(1)
This peripheral is not supported on the C6745 DSP.
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8.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In this device, for both PSC0 and PSC1, the Always ON domain (or PD0 power domain), is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state (See details on
PDCTL register).
Additionally, for both PSC0 and PSC1, the PD1 power domains, the internal/pseudo power domain can
either be in the ON state or OFF state. Furthermore, for these power domains the transition from ON to
OFF state is further qualified by the PSC0/1.PDCTL1.PDMODE settings. The PDCTL1.PDMODE settings
determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
• On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128 kB Shared RAM
NOTE: Currently programming the PD1 power domain state to OFF is not supported. You should
leave both the PDCTL1.NEXT and PDCTL1.PDMODE values at default/power on reset
values.
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of
the device. There is no capability to individually remove voltage/power from the DSP or
Shared RAM power domains.
8.2.2 Module States
The PSC defines several possible states for a module. This various states are essentially a combination of
the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The various
module states are defined in Table 8-3.
The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in
Auto Sleep mode, it will transition back to the clock disabled state (automatically sleep) after servicing the
internal read/write access request where as in Auto Wake mode, on receiving the first internal read/write
access request, the module will permanently transition from the clock disabled to clock enabled state
(automatically wake).
When the module state is programmed to Disable, SwRstDisable, Auto Sleep or Auto Wake modes,
where in the module clocks are off/disabled, an external event or I/O request cannot enable the clocks.
For the module to appropriately respond to such external request, it would need to be reconfigured to the
Enable state.
8.2.2.1
Auto Sleep/Wake Only Configurations and Limitation
NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes. If the
module clocks need to gated/disabled for power savings, you should program the module
state to Disable. For Auto Sleep/Auto Wake Only modules, disabling the clock is not
supported and they should be kept in their default “Enable” state.
Table 8-1 and Table 8-2 each have a column to indicate whether or not the LPSC configuration for a
module is Auto Sleep/Wake Only. Modules that have a “Yes” marked for the Auto Sleep/Wake Only
column can be programmed in software to be in Enable, Auto Sleep and Auto Wake states only; that is, if
the software tries to program these modules to Disable, SyncReset, or SwRstDisable state the power
sleep controller ignores these transition requests and transitions the module state to Enable.
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Table 8-3. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. This device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data. See Section 8.2.2.1 for additional
considerations, constraints, limitations around this mode.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data. See Section 8.2.2.1 for
additional considerations, constraints, limitations around this mode.
8.2.2.2
Local Reset
In addition to module reset, some modules can be reset using a special local reset that is also a part of
the PSC module control for resets. The modules that support the local reset are:
• DSP: When the DSP local reset is asserted the DSP internal memories (L1P, L1D and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of DSP subsystem, as the DSP
module reset would. Local Reset is useful in cases where the DSP is in enable or disable state; since
when module is in SyncReset or SwRstDisable state the module reset is asserted, and the module
reset takes precedence over the local reset.
The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the
module that supports local reset):
1. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset.
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset.
If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted.
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Executing State Transitions
This section describes how to execute the state transitions modules.
8.3.1 Power Domain State Transitions
This device consists of 2 types of domain (in each PSC controller): the Always On Domain(s) and the
pseudo/RAM power domain(s). The Always On power domains are always in the ON state when the chip
is powered on. You are not allowed to change the power domain state to OFF.
The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with
these domains (L1/L2 for PD_DSP in PSC0 and Shared RAM for PD_SHRAM in PSC1) so that these
RAMs can run in lower power sleep modes via the power sleep controller.
NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported;
therefore, these domains and the RAM should be left in their default power on state.
As mentioned in Section 8.2, the pseudo/RAM power domains are powered down internally,
and in this context powering down does not imply removing the core voltage from pins
externally.
8.3.2 Module State Transitions
This section describes the procedure for transitioning the module state (clock and reset control). Note that
some peripherals have special programming requirements and additional recommended steps you must
take before you can invoke the PSC module state transition. See the individual peripheral user guides for
more details. For example, the external memory controller requires that you first place the SDRAM
memory in self-refresh mode before you invoke the PSC module state transitions, if you want to maintain
the memory contents.
The following procedure is directly applicable for all modules that are controlled via the PSC (shown in
Table 8-1 and Table 8-2), except for the core(s). To transition the DSP module state, there are additional
system considerations and constraints that you should be aware of. These system considerations and the
procedure for transitioning the DSP module state are described in details in the Power Management
chapter.
NOTE: In the following procedure, x is 0 for modules in PD0 (Power Domain 0 or Always On
domain) and x is 1 for modules in PD1 (Power Domain 1) . See Table 8-1 and Table 8-2 for
power domain associations.
The procedure for module state transitions is:
1. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), Enable (3h), Auto
Sleep (4h) or Auto Wake (5h).
NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[x] bit in PTCMD in a later step.
3. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
after the GOSTAT[x] bit in PTSTAT is cleared to 0.
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8.4
IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the
state of power domains and modules. This IcePick support only applies to the following modules:
• DSP [MDCTL15]
In particular, Table 8-4 shows IcePick emulation commands recognized by the PSC.
Table 8-4. IcePick Emulation Commands
Power On and
Enable Features
Power On and Enable Descriptions
Reset Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the
module’s local reset.
Force Power
Allows emulation to force the power domain into
an on state. Not applicable as AlwaysOn power
domain is always on.
Wait Reset
Allows emulation to keep local
reset asserted for an extended
period of time after software
initiates local reset de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block
software initiated local and
module resets.
NOTE: When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in
MDCTLn, as set by software.
8.5
PSC Interrupts
The PSC has an interrupt that is tied to the core interrupt controller. This interrupt is named PSCINT in the
interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.
8.5.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Power Domain Emulation Event (applies to pseudo/RAM power domain only)
• Module State Emulation event
• Module Local Reset Emulation event
These interrupt events are summarized in Table 8-5 and described in more detail in this section.
Table 8-5. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Enable Bit
Interrupt Condition
PDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the power domain state
MDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the module state
MDCTLn
EMURSTIE
Interrupt occurs when the emulation tries to alter the module’s local reset
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the userprogrammed state in the NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the
modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed.
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Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTATn. In particular, a power
domain emulation event occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
• When force power is asserted by emulation and power domain is not already in the on state
• When force active is asserted by emulation and power domain is not already in the on state
NOTE:
8.5.1.2
Putting the pseudo/RAM power domain associated with DSP (PD_DSP) to off state is
currently not supported.
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTATn). In particular, a module state emulation event
occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
• When force active is asserted by emulation and module is not already in the enable state
8.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTATn). In particular, a module local reset emulation
event occurs under the following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset
• When wait reset is asserted by emulation
• When block reset is asserted by emulation and software attempts to change the state of local reset
8.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support, as specified in
Section 8.4).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled in the DSP interrupt controller. For details on the DSP
interrupt controller, see the DSP Subsystem chapter.
The PSC interrupt status bits are:
• For DSP:
– The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).
– The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain
associated with DSP memories.
The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.
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The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register. When set, this bit forces the
PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set)
when the ALLEV bit in the INTEVAL is set to 1, the PSC interrupt is re-asserted to the interrupt controller.
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do
not miss any PSC interrupts.
See Section 8.6 for a description of the PSC registers.
8.5.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt:
1. Set the EMUIHBIE bit in PDCTLn, the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the
interrupt events that you want.
NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event
becomes active.
2. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. To
interrupt the CPU, PSCn_ALLINT must be enabled in the device interrupt controller. See the DSP
Subsystem chapter for more information on interrupts.
The CPU enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the P[n] bit in PERRPR, and/or the M[n] bit in MERRPR0, the M[n] bit in MERRPR1, to
determine the source of the interrupt(s).
2. For each active event that you want to service:
(a) Read the event status bits in PDSTATn and MDSTATn, depending on the status bits read in the
previous step to determine the event that caused the interrupt.
(b) Service the interrupt as required by your application.
(c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status.
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt
controller, if there are still any active interrupt events.
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PSC Registers
Table 8-6 lists the memory-mapped registers for the PSC0 and Table 8-7 lists the memory-mapped
registers for the PSC1.
Table 8-6. Power and Sleep Controller 0 (PSC0) Registers
Address
Acronym
Register Description
01C1 0000h
REVID
Revision Identification Register
Section 8.6.1
Section
01C1 0018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01C1 0040h
MERRPR0
Module Error Pending Register 0 (module 0-15)
Section 8.6.3
01C1 0050h
MERRCR0
Module Error Clear Register 0 (module 0-15)
Section 8.6.5
01C1 0060h
PERRPR
Power Error Pending Register
Section 8.6.7
01C1 0068h
PERRCR
Power Error Clear Register
Section 8.6.8
01C1 0120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01C1 0128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01C1 0200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01C1 0204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01C1 0300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01C1 0304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01C1 0400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01C1 0404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01C1 0800h01C1 083Ch
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15)
Section 8.6.17
01C1 0A00h01C1 0A3Ch
MDCTL0MDCTL15
Module Control n Register (modules 0-15)
Section 8.6.18
Table 8-7. Power and Sleep Controller 1 (PSC1) Registers
148
Address
Acronym
Register Description
01E2 7000h
REVID
Revision Identification Register
Section 8.6.1
01E2 7018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01E2 7040h
MERRPR0
Module Error Pending Register 0 (module 0-31)
Section 8.6.4
01E2 7050h
MERRCR0
Module Error Clear Register 0 (module 0-31)
Section 8.6.6
01E2 7060h
PERRPR
Power Error Pending Register
Section 8.6.7
01E2 7068h
PERRCR
Power Error Clear Register
Section 8.6.8
01E2 7120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01E2 7128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01E2 7200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01E2 7204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01E2 7300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01E2 7304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01E2 7400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01E2 7404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01E2 7800h01E2 787Ch
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31)
Section 8.6.17
01E2 7A00h01E2 7A7Ch
MDCTL0MDCTL31
Module Control n Register (modules 0-31)
Section 8.6.19
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8.6.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 8-1 and described in Table 8-8.
Figure 8-1. Revision Identification Register (REVID)
31
0
REV
R-4482 3A00h
LEGEND: R = Read only; -n = value after reset
Table 8-8. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4482 3A00h
Description
Peripheral revision ID.
8.6.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 8-2 and described in Table 8-9.
Figure 8-2. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 8-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt (PSCn_ALLINT).
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 8-3 and described in
Table 8-10.
Figure 8-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31
16
Reserved
R-0
15
14
0
M[15]
Reserved
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit
31-16
15
14-0
Field
Reserved
Value
0
M[15]
Reserved
Description
Reserved
Module interrupt status bit for module 15 (DSP).
0
Module 15 does not have an error condition.
1
Module 15 has an error condition. See the module status 15 register (MDSTAT15) for the error
condition.
0
Reserved
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 8-4.
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 8-5 and described in Table 8-11.
Figure 8-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31
16
Reserved
R-0
15
14
0
M[15]
Reserved
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit
31-16
15
14-0
Field
Reserved
Value
0
M[15]
Reserved
Description
Reserved
Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 15 register (MDSTAT15).
0
A write of 0 has no effect.
1
A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15.
0
Reserved
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 8-6.
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 8-7 and described in Table 8-12.
Figure 8-7. Power Error Pending Register (PERRPR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
RAM/Pseudo (PD1) power domain interrupt status.
0
RAM/Pseudo power domain does not have an error condition.
1
RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0
Reserved
8.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 8-8 and described in Table 8-13.
Figure 8-8. Power Error Clear Register (PERRCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit
31-2
1
0
152
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0
A write of 0 has no effect.
1
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0
Reserved
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8.6.9 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 8-9 and described in
Table 8-14.
Figure 8-9. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-14. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GO[1]
Description
Reserved
RAM/Pseudo (PD1) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
PDCTL.NEXT for this domain, and MDCTL.NEXT for all the modules residing on this domain). If any of
the NEXT fields are not matching the corresponding current state (PDSTAT.STATE, MDSTAT.STATE),
the PSC will transition those respective domain/modules to the new NEXT state.
GO[0]
Always ON (PD0) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching
the corresponding current state (MDSTAT.STATE), the PSC will transition those respective
domain/modules to the new NEXT state.
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8.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 8-10 and described in
Table 8-15 .
Figure 8-10. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
154
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
RAM/Pseudo (PD1) power domain transition status.
0
No transition in progress.
1
RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
GOSTAT[0]
Always ON (PD0) power domain transition status.
0
No transition in progress.
1
Modules in Always ON power domain are transitioning. Always On power domain is transitioning.
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8.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 8-11 and described in Table 8-16.
Figure 8-11. Power Domain 0 Status Register (PDSTAT0)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Reserved
Emulation alters domain state.
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.12 Power Domain 1 Status Register (PDSTAT1)
The power domain 1 status register (PDSTAT1) is shown in Figure 8-12 and described in Table 8-17.
Figure 8-12. Power Domain 1 Status Register (PDSTAT1)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Emulation alters domain state.
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
156
Reserved
0
POR
7-5
Description
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.13 Power Domain 0 Control Register (PDCTL0)
The power domain 0 control register (PDCTL0) is shown in Figure 8-13 and described in Table 8-18.
Figure 8-13. Power Domain 0 Control Register (PDCTL0)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
Reserved
9
EMUIHBIE
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
0-Fh
Power down mode.
0-Eh
Reserved
Fh
11-10
Description
0
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
NEXT
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect
since internally this power domain always remains in the on state.
0
Power domain off.
1
Power domain on.
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8.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 8-14 and described in Table 8-19.
Figure 8-14. Power Domain 1 Control Register (PDCTL1)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
0-Fh
Core off, RAM array retention, RAM periphery off (deep sleep).
Reserved
4h
Core retention, RAM array off, RAM periphery off.
5h
Core retention, RAM array retention, RAM periphery off (deep sleep).
Reserved
8h
Core on, RAM array off, RAM periphery off.
9h
Core on, RAM array retention, RAM periphery off (deep sleep).
Ah
Core on, RAM array retention, RAM periphery off (light sleep).
Bh
Core on, RAM array retention, RAM periphery on.
Fh
EMUIHBIE
Power down mode.
Core off, RAM array off, RAM periphery off.
Ch-Eh
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
1h
6h-7h
9
Reserved
0
2h-3h
11-10
Description
0
Reserved
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
158
NEXT
User-desired power domain next state.
0
Power domain off.
1
Power domain on.
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8.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 8-15 and described in
Table 8-20.
Figure 8-15. Power Domain 0 Configuration Register (PDCFG0)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.16 Power Domain 1 Configuration Register (PDCFG1)
The power domain 1 configuration register (PDCFG1) is shown in Figure 8-16 and described in
Table 8-21.
Figure 8-16. Power Domain 1 Configuration Register (PDCFG1)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
160
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.17 Module Status n Register (MDSTATn)
The module status n register (MDSTATn) is shown in Figure 8-17 and described in Table 8-22.
Figure 8-17. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
Reserved
MCKOUT
Rsvd
MRST
LRSTDONE
LRST
Reserved
7
6
5
STATE
0
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-22. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in the module control
15 register (MDCTL15).
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL15. If you desire to
generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL15.
Emulation alters module reset. This bit applies to DSP module (module 15). This field is 0 for all
other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state. If you desire to generate a PSCINT upon this
event, you must set the EMURSTIE bit in the module control 15 register (MDCTL15).
0
Reserved
Module clock output status. Shows status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to DSP module (module 15). This field is 1 for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Reserved
0
LRSTDONE
7-6
Description
Emulation alters module state. This bit applies to DSP module (module 15). This field is 0 for all
other modules.
EMURST
15-13
9
Value
Module local reset status. This bit applies to DSP module (module 15).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
Module state status: indicates current module status.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
Indicates transition
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8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)
The PSC0 module control n register (MDCTLn) is shown in Figure 8-18 and described in Table 8-23.
Figure 8-18. PSC0 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
10
9
8
Reserved
11
EMUIHBIE
EMURSTIE
LRST
7
Reserved
3
2
NEXT
0
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 15
register (MDCTL15), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-11
Reserved
10
EMUIHBIE
9
8
Force is disabled.
1
Force is enabled.
0
Reserved
Interrupt enable for emulation alters module state. This bit applies to DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
EMURSTIE
Interrupt enable for emulation alters reset. This bit applies to DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
LRST
7-3
Reserved
2-0
NEXT
162
0
Module local reset control. This bit applies to DSP module (module 15).
0
Assert local reset
1
De-assert local reset
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn)
The PSC1 module control n register (MDCTLn) is shown in Figure 8-19 and described in Table 8-24.
Figure 8-19. PSC1 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
3
2
0
Reserved
NEXT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 15
register (MDCTL15), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-3
Reserved
2-0
NEXT
0
Force is disabled.
1
Force is enabled.
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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Chapter 9
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Power Management
164
Topic
...........................................................................................................................
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Introduction .....................................................................................................
Power Consumption Overview ...........................................................................
PSC and PLLC Overview ...................................................................................
Features ..........................................................................................................
Clock Management ...........................................................................................
DSP Sleep Mode Management............................................................................
RTC-Only Mode ................................................................................................
Additional Peripheral Power Management Considerations.....................................
Power Management
Page
165
165
165
166
167
168
168
169
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9.1
Introduction
Power management is an important aspect for most embedded applications. For several applications and
target markets, there may be a specific power budget and requirements to minimize power consumption
for both power supply sizing and battery life considerations. Additionally, lower power consumption results
in more optimal and efficient designs from cost, design, and energy perspectives. This device has several
means of managing the power consumption. This chapter discusses the various power management
features.
9.2
Power Consumption Overview
Power consumed by semiconductor devices has two components: dynamic and static. This can be shown
as:
Ptotal = Pdynamic + Pstatic
The dynamic power is the power consumed to perform work when the device is in active modes (clocks
applied, busses, and I/O switching), that is, analog circuits changing states. The dynamic power is defined
by:
Pdynamic = Capacitance × Voltage2 × Frequency
From the above formula, the dynamic power scales with the clock frequency (device/module frequency for
core operations and switching frequency for I/O). Dynamic power can be reduced by controlling the clocks
in such a way as to either operate at a clock setting just high enough to complete the required operation in
the required timeline or to run at a clock setting until the work is complete and then drastically reduce the
clock frequency or cut off the clocks until additional work must be performed.
In the formula, the dynamic power varies with the voltage squared, so the voltage of operations has
significant impact on overall power consumption and, thus, on the battery life. Dynamic power can be
reduced by scaling the operating voltage, when the performance requirements are not that high and the
device can be operated at a corresponding lower frequency.
The capacitance is the capacitance of the switching nodes, or the load capacitances on the switching I/O
pins.
The static power, as the name suggests, is independent of the switching frequency of the logic. It can be
shown as:
Pstatic = f(leakage current)
It is essentially a function of the “leakage”, or the power consumed by the logic when it is not switching or
is not performing any work. Leakage current is dependent mostly on the manufacturing process used, the
size of the die, etc. Leakage current is unavoidable while power is applied and scales roughly with the
operating junction temperatures. Leakage power can only be avoided by removing power completely from
a device or subsystem. The static power consumption plays a significant role in the Standby Modes (when
the application is not running and in a dormant state) and plays an important role in the battery life for
portable applications, etc.
9.3
PSC and PLLC Overview
The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling
of the clocks to the core and various peripheral modules. The PSC provides a granular support to turn
on/off clocks on a module by module basis. Similarly, the PLL controller (PLLC) plays an important role in
device and module clock generation, and manages the frequency scaling operations for the device.
Together, both of these modules play a significant role in managing the clocks from a power management
feature standpoint. For detailed information on the PSC, see the Power and Sleep Controller (PSC)
chapter. For detailed information on the PLLC, see the Device Clocking chapter and the Phase-Locked
Loop Controller (PLLC) chapter.
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Features
9.4
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Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 9-1 describes the power management features.
Table 9-1. Power Management Features
Power Management
Description
Features
PLL power-down
The PLL can be powered-down and run in bypass
modes when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON/OFF
Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic/switching power
consumption of the core and I/O (if any free
running I/O clocks).
Core/module clock
frequency scaling
The device can be run at a lower frequency using
the PLLM/PLL dividers. Many modules have
internal clock dividers to scale module/IO
frequency.
Reduces the dynamic/switching power
consumption of core and I/O.
Clock Management
Core Sleep Management
DSP subsystem
sleep mode
The DSP CPU can be put in sleep (IDLE) mode.
Reduces the dynamic power.
Voltage Management
RTC-only mode
(1)
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Peripheral I/O Power Management
USB Phy power-down
(1)
166
The USB2.0 Phy can be powered-down.
Minimizes USB2.0 I/O power consumption when
not in use.
This peripheral is not supported on the C6745 DSP.
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9.5
Clock Management
9.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
Furthermore, special consideration must be given to DSP clock on/off. The procedure to turn the core
clock on/off is further described in .
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module , when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
9.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
9.5.3 PLL Bypass and Power Down
You can bypass the PLL in the device. Bypassing the PLL sends the PLL reference clock (OSCIN) instead
of the PLL VCO output (PLLOUT) to the system clocks of the PLLC. The PLL OSCIN is typically, at most,
up to 50 MHz. You can use this mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity, this again can lower
the overall dynamic/switching power consumption, which is linearly proportional to the frequency.
Furthermore, you can also power-down the PLL when bypassing it to minimize the overall power
consumed by the PLL module.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
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DSP Sleep Mode Management
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DSP Sleep Mode Management
9.6.1 C674x DSP CPU Sleep Mode
The DSP CPU can be put in a low-power state by executing the IDLE instruction. For information on the
IDLE instruction, see the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8).
9.6.2 C674x Megamodule Sleep Mode
The IDLE instruction is used as part of the procedure for shutting down the entire C674x megamodule, by
the power-down controller (PDC) module. In shutting down the entire C674x megamodule, the PDC can
internally clock gate off the following components of the megamodule and internal memories of the DSP
subsystem:
• C674x CPU
• Level 1 Program Memory Controller (PMC)
• Level 1 Data Memory Controller (DMC)
• Level 2 Unified Memory Controller (UMC)
• Extended Memory Controller (EMC)
• L1P Memory
• L1D Memory
• L2 Memory
Putting the entire C674x megamodule into the low-power sleep mode is typically more useful and saves a
lot more power, as compared to just executing the IDLE instruction to put only the CPU in idle mode.
For information on putting the C674x megamodule in the low-power mode using the PDC, see the
TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
9.7
RTC-Only Mode
NOTE: To put the device in RTC-only mode, there is no software control sequence. You can put the
device in the RTC-only mode by removing the power supply from all core and I/O logic,
except for the RTC core logic supply (RTC_CVDD).
When the rest of device is powered off, there is no up mechanism from the RTC logic to
wake-up the rest of the chip or signal the external power supply on when to reapply the
power. If the device is put in the RTC-only mode, then external control/decision making logic
would be required to reapply power to the device.
In real-time clock (RTC)-only mode, the RTC is powered on and the rest of the device can be completely
powered off (core and I/O voltage removed). In this mode, the RTC is fully functional and keeps track of
date, hours, minutes, and seconds. In this mode, the overall power consumption would be significantly
lower, as voltage from the rest of the core and I/O logic can be completely removed, eliminating most of
the active and static power of the device, except for what is consumed by the RTC module, running at
32 kHz.
NOTE: The RTC is not supported on the C6745 DSP.
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9.8
Additional Peripheral Power Management Considerations
This section lists additional power management features and considerations that might be part of other
chip-level or peripheral logic, apart from the features supported by the core, PLL controller (PLLC), and
power and sleep controller (PSC).
9.8.1 USB PHY Power Down Control
The USB modules can be clock gated using the PSC; however, this does not power down/clock gate the
PHY logic. You can put the USB2.0 PHY and OTG module in the lowest power state, when not in use, by
writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the chip configuration 2 register
(CFGCHIP2) of the system configuration (SYSCFG) module.
NOTE: If the USB1.1 subsystem is used and the 48 MHz clock input is sourced from the
USB2.0 PHY, then the USB2.0 PHY should not be powered down.
9.8.2 EMIFB Memory Clock Gating
As discussed in the Device Clocking chapter, the EMIFB output clock (EMB_CLK) can be sourced from
either the output of the EMIFB LPSC (CLK1) or directly from the output of the clock multiplexer (CLK2). If
the EMB_CLK is not intended to be used as a free-running clock and the EMIFB is being used as an
SDRAM interface, it is recommended to use CLK1 as the source, as it allows maximal power savings
(clock gating both VCLK/MCLK and EMB_CLK signal) via the PSC.
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Chapter 10
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System Configuration (SYSCFG) Module
Topic
10.1
10.2
10.3
10.4
10.5
170
...........................................................................................................................
Introduction .....................................................................................................
Protection ........................................................................................................
Master Priority Control ......................................................................................
Interrupt Support ..............................................................................................
SYSCFG Registers ............................................................................................
System Configuration (SYSCFG) Module
Page
171
172
174
175
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10.1 Introduction
The system configuration (SYSCFG) module is a system-level module containing status and top level
control logic required by the device. The system configuration module consists of a set of memorymapped status and control registers, accessible by the CPU, supporting all of the following system
features, and miscellaneous functions and operations.
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device Boot Configuration Status
• Master Priority Control
– Controls the system priority for all master peripherals (including EDMA3TC)
• Emulation Control
– Emulation suspend control for peripherals that support the feature
• Special Peripheral Status and Control
– Locking of PLL control settings
– Default burst size configuration for EDMA3 transfer controllers
– Event source selection for the eCAP peripheral input capture
– McASP AMUTEIN selection and clearing of AMUTE
– USB PHY Control
– Clock source selection for EMIFA and EMIFB
– HPI Control (this peripheral is not supported on the C6745 DSP)
The system configuration module controls several global operations of the device; therefore, the module
supports protection against erroneous and illegal accesses to the registers in its memory-map. The
protection mechanisms that are present in the module are:
• A special key sequence that needs to be written into a set of registers in the system configuration
module, to allow write ability to the rest of registers in the system configuration module.
• Several registers in the module are only accessible when the CPU requesting read/write access is in
privileged mode.
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10.2 Protection
Table 10-1 provides the list of registers in the SYSCFG module; it also indicates whether a particular
register can be accessed only when the CPU is in privileged mode. See Section 10.5 for a description of
these registers.
Table 10-1. System Configuration (SYSCFG) Module Register Access
Offset
Acronym
Register Description
REVID
Revision Identification Register
—
DIEIDR0-DIEIDR3
Die Identification 0-3 Registers
—
18h
DEVIDR0
Device Identification Register 0
—
20h
BOOTCFG
Boot Configuration Register
Privileged mode
24h
CHIPREVID
Silicon Revision Identification Register
Privileged mode
38h
KICK0R
Kick 0 Register
Privileged mode
3Ch
KICK1R
Kick 1 Register
Privileged mode
44h
HOST1CFG
Host 1 Configuration Register
E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
E4h
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
E8h
IENSET
Interrupt Enable Register
Privileged mode
ECh
IENCLR
Interrupt Enable Clear Register
Privileged mode
F0h
EOI
End of Interrupt Register
Privileged mode
F4h
FLTADDRR
Fault Address Register
Privileged mode
F8h
FLTSTAT
Fault Status Register
110h-118h
MSTPRI0-MSTPRI2
Master Priority 0-2 Registers
Privileged mode
120h-16Ch
0h
8h-14h
—
—
PINMUX0-PINMUX19
Pin Multiplexing Control 0-19 Registers
Privileged mode
170h
SUSPSRC
Suspend Source Register
Privileged mode
174h
CHIPSIG
Chip Signal Register
178h
CHIPSIG_CLR
Chip Signal Clear Register
CFGCHIP0-CFGCHIP4
Chip Configuration 0-4 Registers
17Ch-18Ch
172
Access
System Configuration (SYSCFG) Module
—
—
Privileged mode
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10.2.1 Requirements to Access SYSCFG Registers
As mentioned previously, the SYSCFG module controls several global operations of the device; therefore,
it has protection mechanism that prevents spurious and illegal accesses to the registers in its memory
map. The protection mechanism enables accesses to these registers only if certain conditions are met.
The protection mechanisms that are present in the module are described in the following sections.
10.2.1.1 Privilege Mode Protection
The CPU supports two privilege levels: Supervisor and User. Several registers in the SYSCFG memorymap can only be accessed when the accessing host (CPU or master peripheral) is operating in privileged
mode, that is, in Supervisor mode. The registers that can only be accessed in privileged mode are listed in
Section 10.5. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for
details on privilege levels.
10.2.1.2 Kicker Mechanism Protection
NOTE: The Kick 0 and Kick 1 registers can only be accessed in privileged mode (the host needs to
be in Supervisor mode). Any number of accesses may be performed to the SYSCFG
module, while the module is unlocked.
The SYSCFG module remains unlocked after the unlock sequence, until locked again.
Locking the module is accomplished by writing any value other then the key values to either
KICK0 or KICK1.
To access any registers in the SYSCFG module, it is required to follow a special sequence of writes to the
Kick registers (Kick0 and Kick1) with correct key values. Writing the correct key value to the kick registers
unlocks the registers in the SYSCFG memory-map. In order to access the SYSCFG registers, the
following unlock sequence needs to be executed in software:
1. Write the key value of 83E7 0B13h to Kick 0 register.
2. Write the key value of 95A4 F1E0h to Kick 1 register.
After steps 1 and 2, the SYSCFG module registers are accessible and can be configured as per the
application requirements.
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10.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the DSP, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or EDMA3 for
initiating the data transfer to/from them. In order to determine allowed connection between masters and
slave, each master request source must have a unique master ID (mstid) associated with it. The master ID
is shown in Table 10-2. See the device-specific data manual to determine the masters present on your
device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 10-3. Application software is expected to modify these values
to obtain the desired performance.
Table 10-2. Master IDs
Master ID
0-1
DSP MDMA
3
DSP CFG
4-7
Reserved
8
PRU0
9
PRU1
10
TPCC0
Reserved
16
TPTC0 - read
17
TPTC0 - write
18
TPTC1 - read
19
TPTC1 - write
20-33
Reserved
34
USB2.0 CFG
35
USB2.0 DMA
36
Reserved
37
HPI (1)
38-63
Reserved
64
EMAC
65
USB1.1 (1)
66-95
Reserved
96
97-255
174
Reserved
2
11-15
(1)
Peripheral
LCDC (1)
Reserved
This peripheral is not supported on the C6745 DSP.
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Table 10-3. Default Master Priority
Master
Default Priority (1)
Master Priority Register
PRU0
0
MSTPRI1
PRU1
0
MSTPRI1
EDMA3TC0
(2)
0
MSTPRI1
EDMA3TC1
0
MSTPRI1
DSP MDMA (3)
2
MSTPRI0
DSP CFG
(4)
2
MSTPRI0
EMAC
4
MSTPRI2
USB2.0 CFG
4
MSTPRI2
USB2.0 DMA
4
MSTPRI2
USB1.1 (5)
4
MSTPRI2
LCDC (5)
5
MSTPRI2
6
MSTPRI2
(6)
HPI (5)
(1)
(2)
(3)
(4)
(5)
(6)
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
The priority for EDMA3TC0 and EDMA3TC1 is configurable through fields in MSTPRI1, not the EDMA3CC QUEPRI register.
The priority for DSP MDMA and DSP CFG is controlled by fields in MSTPRI0 and not DSP.MDMAARBE.PRI
(DSP Bandwidth manager module).
The priority for DSP MDMA and DSP CFG is controlled by fields in MSTPRI0 and not DSP.MDMAARBE.PRI
(DSP Bandwidth manager module).
This peripheral is not supported on the C6745 DSP.
LCDC traffic is typically real-time sensitive, therefore, the default priority of 5, which is lower as compared to the default priority of
several masters, is not recommended. You should reconfigure LCDC priority to the highest or equal to other high-priority masters
in an application to ensure that throughput/latency requirements for LCDC are met.
10.4 Interrupt Support
10.4.1 Interrupt Events and Requests
The SYSCFG module generates two interrupts: an address error interrupt (BOOTCFG_ADDR_ERR) and
a protection interrupt (BOOTCFG_PROT_ERR). The BOOTCFG_ADDR_ERR is generated when there is
an addressing violation due to an access to a non-existent location in the SYSCFG register space. The
BOOTCFG_PROT_ERR interrupt is generated when there is a protection violation of either in the defined
ranges or to the SYSCFG registers. It is required to write a value of 0 to the end of interrupt register (EOI)
after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of completion
of the SYSCFG interrupt so that the module can reliably generate subsequent interrupts.
The transfer parameters that caused the violation are saved in the fault address register (FLTADDRR) and
the fault status register (FLTSTAT).
10.4.2 Interrupt Multiplexing
The interrupts from the SYSCFG module are combined with the interrupts from the MPU module into a
single interrupt called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt
controller.
10.4.3 Host-DSP Communication Interrupts
The SYSCFG module also has a set of registers, the chip signal register (CHIPSIG) and the chip signal
clear register (CHIPSIG_CLR), to facilitate host-to-processor communication. This is generally used to
allow an external host and the DSP to coordinate.
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other
processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller.
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10.5 SYSCFG Registers
Table 10-4 lists the memory-mapped registers for the system configuration module (SYSCFG).
Table 10-4. System Configuration Module (SYSCFG) Registers
Address
Acronym
Register Description
01C1 4000h
REVID
Revision Identification Register
01C1 4008h
DIEIDR0 (1)
Die Identification Register 0
—
01C1 400Ch
DIEIDR1 (1)
Die Identification Register 1
—
01C1 4010h
DIEIDR2 (1)
Die Identification Register 2
—
01C1 4014h
DIEIDR3
(1)
Die Identification Register 3
01C1 4018h
DEVIDR0
Device Identification Register 0
Section 10.5.2
01C1 4020h
BOOTCFG
Boot Configuration Register
Section 10.5.3
01C1 4024h
CHIPREVID
Silicon Revision Identification Register
01C1 4038h
KICK0R
Kick 0 Register
Section 10.5.5.1
01C1 403Ch
KICK1R
Kick 1 Register
Section 10.5.5.2
01C1 4044h
HOST1CFG
Host 1 Configuration Register
01C1 40E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Section 10.5.7.1
01C1 40E4h
IENSTAT
Interrupt Enable Status/Clear Register
Section 10.5.7.2
01C1 40E8h
IENSET
Interrupt Enable Register
Section 10.5.7.3
01C1 40ECh
IENCLR
Interrupt Enable Clear Register
Section 10.5.7.4
01C1 40F0h
EOI
End of Interrupt Register
Section 10.5.7.5
01C1 40F4h
FLTADDRR
Fault Address Register
Section 10.5.8.1
01C1 40F8h
FLTSTAT
Fault Status Register
Section 10.5.8.2
01C1 4110h
MSTPRI0
Master Priority 0 Register
Section 10.5.9.1
01C1 4114h
MSTPRI1
Master Priority 1 Register
Section 10.5.9.2
01C1 4118h
MSTPRI2
Master Priority 2 Register
Section 10.5.9.3
01C1 4120h
PINMUX0
Pin Multiplexing Control 0 Register
Section 10.5.10.1
01C1 4124h
PINMUX1
Pin Multiplexing Control 1 Register
Section 10.5.10.2
01C1 4128h
PINMUX2
Pin Multiplexing Control 2 Register
Section 10.5.10.3
01C1 412Ch
PINMUX3
Pin Multiplexing Control 3 Register
Section 10.5.10.4
01C1 4130h
PINMUX4
Pin Multiplexing Control 4 Register
Section 10.5.10.5
01C1 4134h
PINMUX5
Pin Multiplexing Control 5 Register
Section 10.5.10.6
01C1 4138h
PINMUX6
Pin Multiplexing Control 6 Register
Section 10.5.10.7
01C1 413Ch
PINMUX7
Pin Multiplexing Control 7 Register
Section 10.5.10.8
01C1 4140h
PINMUX8
Pin Multiplexing Control 8 Register
Section 10.5.10.9
01C1 4144h
PINMUX9
Pin Multiplexing Control 9 Register
Section 10.5.10.10
01C1 4148h
PINMUX10
Pin Multiplexing Control 10 Register
Section 10.5.10.11
01C1 414Ch
PINMUX11
Pin Multiplexing Control 11 Register
Section 10.5.10.12
01C1 4150h
PINMUX12
Pin Multiplexing Control 12 Register
Section 10.5.10.13
01C1 4154h
PINMUX13
Pin Multiplexing Control 13 Register
Section 10.5.10.14
01C1 4158h
PINMUX14
Pin Multiplexing Control 14 Register
Section 10.5.10.15
01C1 415Ch
PINMUX15
Pin Multiplexing Control 15 Register
Section 10.5.10.16
01C1 4160h
PINMUX16
Pin Multiplexing Control 16 Register
Section 10.5.10.17
01C1 4164h
PINMUX17
Pin Multiplexing Control 17 Register
Section 10.5.10.18
01C1 4168h
PINMUX18
Pin Multiplexing Control 18 Register
Section 10.5.10.19
01C1 416Ch
PINMUX19
Pin Multiplexing Control 19 Register
Section 10.5.10.20
01C1 4170h
SUSPSRC
Suspend Source Register
(1)
Section
Section 10.5.1
—
Section 10.5.4
Section 10.5.6
Section 10.5.11
This register is for internal-use only.
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Table 10-4. System Configuration Module (SYSCFG) Registers (continued)
Address
Acronym
Register Description
01C1 4174h
CHIPSIG
Chip Signal Register
Section 10.5.12
Section
01C1 4178h
CHIPSIG_CLR
Chip Signal Clear Register
Section 10.5.13
01C1 417Ch
CFGCHIP0
Chip Configuration 0 Register
Section 10.5.14
01C1 4180h
CFGCHIP1
Chip Configuration 1 Register
Section 10.5.15
01C1 4184h
CFGCHIP2
Chip Configuration 2 Register
Section 10.5.16
01C1 4188h
CFGCHIP3
Chip Configuration 3 Register
Section 10.5.17
01C1 418Ch
CFGCHIP4
Chip Configuration 4 Register
Section 10.5.18
10.5.1 Revision Identification Register (REVID)
The revision identification register (REVID) provides the revision information for the SYSCFG module. The
REVID is shown in Figure 10-1 and described in Table 10-5.
Figure 10-1. Revision Identification Register (REVID)
31
0
REV
R-4E84 0102h
LEGEND: R = Read only; -n = value after reset
Table 10-5. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E84 0102h
Description
Revision ID. Revision information for the SYSCFG module.
10.5.2 Device Identification Register 0 (DEVIDR0)
The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID
device. Software can use this register to determine the version of the device on which it is executing. The
DEVIDR0 is shown in Figure 10-2 and described in Table 10-6.
Figure 10-2. Device Identification Register 0 (DEVIDR0)
31
0
DEVID0
R-0B7D F02Fh
LEGEND: R = Read only; -n = value after reset
Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions
Bit
31-0
Field
DEVID0
Value
R-0B7D F02Fh
Description
Device identification.
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10.5.3 Boot Configuration Register (BOOTCFG)
The device boot and configuration settings are latched at device reset, and captured in the boot
configuration register (BOOTCFG). See the device-specific data manual and the Boot Considerations
chapter for details on boot and configuration settings. The BOOTCFG is shown in Figure 10-3 and
described in Table 10-7.
Figure 10-3. Boot Configuration Register (BOOTCFG)
31
16
Reserved
R-0
15
0
BOOTMODE
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-7. Boot Configuration Register (BOOTCFG) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
BOOTMODE
0
0-FFFFh
Description
Reserved
Boot Mode. This reflects the state of the boot mode pins.
10.5.4 Silicon Revision Identification Register (CHIPREVID)
The silicon revision identification register (CHIPREVID) provides software-readable silicon revision
information for the device. The CHIPREVID is shown in Figure 10-4 and described in Table 10-8.
Figure 10-4. Silicon Revision Identification Register (CHIPREVID)
31
16
Reserved
R-x
15
4
3
0
Reserved
CHIPREV
R-x
R-4h
LEGEND: R = Read only; -n = value after reset; x = value is indeterminate after reset
Table 10-8. Silicon Revision Identification Register (CHIPREVID) Field Descriptions
Bit
Field
31-4
Reserved
3-0
CHIPREV
Value
0
Reserved
Identifies silicon revision of device.
0-3h
4h
178
Description
Older silicon revision
Silicon revision 3.0
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10.5.5 Kick Registers (KICK0R-KICK1R)
The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of
the modules memory-mapped registers. At power-on reset, none of the SYSCFG module registers are
writeable (they are readable). To allow writing to the registers in the module, it is required to “unlock” the
registers by writing to two memory-mapped registers in the SYSCFG module, Kick0 and Kick1, with exact
data values. Once these values are written, then all the registers in the SYSCFG module that are
writeable can be written to. See Section 10.2.1.2 for the exact key values and sequence of steps. Writing
any other data value to either of these kick registers will cause the memory mapped registers to be
“locked” again and block out any write accesses to registers in the SYSCFG module.
10.5.5.1 Kick 0 Register (KICK0R)
The KICK0R is shown in Figure 10-5 and described in Table 10-9.
Figure 10-5. Kick 0 Register (KICK0R)
31
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-9. Kick 0 Register (KICK0R) Field Descriptions
Bit
Field
Value
Description
31-0
KICK0
0-FFFF FFFFh
KICK0R allows writing to unlock the kick0 data. The written data must be 83E7 0B13h to unlock
this register. It must be written before writing to the kick1 register. Writing any other value will lock
the other MMRs.
10.5.5.2 Kick 1 Register (KICK1R)
The KICK1R is shown in Figure 10-6 and described in Table 10-10.
Figure 10-6. Kick 1 Register (KICK1R)
31
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-10. Kick 1 Register (KICK1R) Field Descriptions
Bit
Field
Value
31-0
KICK1
0-FFFF FFFFh
Description
KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written
before writing to the kick1 register. Writing any other value will lock the other MMRs.
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10.5.6 Host 1 Configuration Register (HOST1CFG)
The host 1 configuration register (HOST1CFG) provides information on the DSP boot address value at
power-on reset. The boot address defaults to 0070 0000h (DSP ROM) on power-up. The address field is
read/writeable after reset and can be modified to allow execution from an alternate location after a module
level or local reset on the DSP. The HOST1CFG is shown in Figure 10-7 and described in Table 10-11.
Figure 10-7. Host 1 Configuration Register (HOST1CFG)
31
16
DSP_ISTP_RST_VAL
R/W-0 1C00h
15
10
9
1
0
DSP_ISTP_RST_VAL
Reserved
BOOTRDY
R/W-0 1C00h
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions
Bit
Field
31-10 DSP_ISTP_RST_VAL
9-1
0
180
Reserved
Value
0-3F FFFFh
0
Description
DSP boot address vector.
Reserved
BOOTRDY
DSP boot ready bit allowing DSP to boot.
0
DSP held in reset mode.
1
DSP released from wait in reset mode.
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10.5.7 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
10.5.7.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 10-8 and described in
Table 10-12.
Figure 10-8. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
PROTERR
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
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10.5.7.2 Interrupt Enable Status/Clear Register (IENSTAT)
The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows
clearing of the interrupt status. The IENSTAT is shown in Figure 10-9 and described in Table 10-13.
Figure 10-9. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
182
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
PROTERR
Protection violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
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10.5.7.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 10-10 and described in Table 10-14.
Figure 10-10. Interrupt Enable Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-14. Interrupt Enable Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
PROTERR_EN
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
10.5.7.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 10-11 and described in Table 10-15.
Figure 10-11. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
PROTERR_CLR
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
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10.5.7.5 End of Interrupt Register (EOI)
The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of
the SYSCFG interrupt (for address/protection violation). It is required to write a value of 0 to the EOI
register after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of
completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts.
The EOI is shown in Figure 10-12 and described in Table 10-16.
Figure 10-12. End of Interrupt Register (EOI)
31
16
Reserved
R-0
15
8
7
0
Reserved
EOIVECT
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 10-16. End of Interrupt Register (EOI) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
EOIVECT
0-FFh
Description
Reserved. Always read 0.
EOI vector value. Write the interrupt distribution value of the chip.
10.5.8 Fault Registers
The fault registers are a group of registers responsible for capturing the details on the faulty
(address/protection violation errors) accesses, such as address and type of error.
10.5.8.1 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) captures the address of the first transfer that causes the address
or memory violation error. The FLTADDRR is shown in Figure 10-13 and described in Table 10-17.
Figure 10-13. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
184
Field
FLTADDR
Value
0-FFFF FFFFh
Description
Fault address for the first fault transfer.
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10.5.8.2 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous
transaction. This includes things like the master id for the master that caused the address/memory
violation error, details on whether it is a user or supervisor level read/write or execute fault. The FLTSTAT
is shown in Figure 10-14 and described in Table 10-18.
Figure 10-14. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
ID
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-18. Fault Status Register (FLTSTAT) Field Descriptions
Field
Value
Description
31-24
Bit
ID
0-FFh
Transfer ID of the first fault transfer.
23-16
MSTID
0-FFh
Master ID of the first fault transfer.
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
0
0-Fh
0
Reserved. Always read 0
Privilege ID of the first fault transfer.
Reserved. Always read 0
Fault type of first fault transfer.
0
No transfer fault
1h
User execute fault
2h
User write fault
3h
Reserved
4h
User read fault
5h-7h
8h
9h-Fh
10h
11h-1Fh
20h
21h-3Fh
Reserved
Supervisor execute fault
Reserved
Supervisor write fault
Reserved
Supervisor read fault
Reserved
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10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)
10.5.9.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 10-15 and described in Table 10-19.
Figure 10-15. Master Priority 0 Register (MSTPRI0)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
DSP_CFG
Rsvd
DSP_MDMA
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-19. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
4h
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
15
Reserved
0
14-12
DSP_CFG
0-7h
11
Reserved
0
10-8
DSP_MDMA
0-7h
DSP CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
DSP DMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Always read as 0.
6-4
Reserved
2h
Reserved. Write the default value when modifying this register.
3
Reserved
0
Reserved. Always read as 0.
2-0
Reserved
2h
Reserved. Write the default value when modifying this register.
186
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10.5.9.2 Master Priority 1 Register (MSTPRI1)
The master priority 1 register (MSTPRI1) is shown in Figure 10-16 and described in Table 10-20.
Figure 10-16. Master Priority 1 Register (MSTPRI1)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
EDMATC1
Rsvd
EDMATC0
Rsvd
PRU1
Rsvd
PRU0
R/W-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-20. Master Priority 1 Register (MSTPRI1) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
4h
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
15
Reserved
0
14-12
EDMATC1
0-7h
11
Reserved
0
10-8
EDMATC0
0-7h
7
Reserved
0
6-4
3
2-0
PRU1
Reserved
PRU0
0-7h
0
0-7h
EDMA3TC1 priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
EDMA3TC0 priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU1 priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU0 priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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10.5.9.3 Master Priority 2 Register (MSTPRI2)
The master priority 2 register (MSTPRI2) is shown in Figure 10-17 and described in Table 10-21.
Figure 10-17. Master Priority 2 Register (MSTPRI2)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
LCDC (1)
Rsvd
USB1 (1)
Rsvd
UHPI (1)
Rsvd
Reserved
R/W-0
R/W-5h
R/W-0
R/W-4h
R/W-0
R/W-6h
R/W-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
USB0CDMA
Rsvd
USB0CFG
Rsvd
Reserved
Rsvd
EMAC
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-0
R/W-0
R/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Table 10-21. Master Priority 2 Register (MSTPRI2) Field Descriptions
Bit
Field
31
Reserved
30-28
27
26-24
23
22-20
LCDC
Reserved
USB1
Reserved
UHPI
Value
0
0-7h
0
0-7h
0
0-7h
Description
Reserved. Write the default value when modifying this register.
LCDC priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). This peripheral is not
supported on the C6745 DSP.
Reserved. Write the default value when modifying this register.
USB1 (USB1.1) priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). This peripheral is not
supported on the C6745 DSP.
Reserved. Write the default value when modifying this register.
HPI priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). This peripheral is not supported
on the C6745 DSP.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
0
Reserved. Write the default value when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
USB0CDMA
0-7h
USB0 (USB2.0) CDMA priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
11
Reserved
0
10-8
USB0CFG
0-7h
7
Reserved
0
Reserved. Write the default value when modifying this register.
6-4
Reserved
0
Reserved. Write the default value when modifying this register.
3
Reserved
0
Reserved. Write the default value when modifying this register.
2-0
188
EMAC
0-7h
Reserved. Write the default value when modifying this register.
USB0 (USB2.0) CFG priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
EMAC priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
NOTE: The C6745 DSP does not support all of the pins documented in the following subsections.
See the TMS320C6745/C6747 DSP Data Manual (SPRS377) for the peripherals supported.
Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the
smallest possible package. On the device, pin multiplexing can be controlled on a pin by pin basis. This is
done by the pin multiplexing registers (PINMUX0-PINMUX19). Each pin that is multiplexed with several
different functions has a corresponding 4-bit field in PINMUXn. Pin multiplexing selects which of several
peripheral pin functions control the pins IO buffer output data and output enable values only. Note that the
input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers
have no effect on input from a pin. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used. Detailed information about the pin
multiplexing and control is covered in the device-specific data manual. Access to the pin multiplexing utility
is available in OMAP-L137, TMS320C6747/6745/6743 Pin Multiplexing Utility Application Report
(SPRAB06).
10.5.10.1 Pin Multiplexing Control 0 Register (PINMUX0)
Figure 10-18. Pin Multiplexing Control 0 Register (PINMUX0)
31
28
27
24
23
20
19
16
PINMUX0_31_28
PINMUX0_27_24
PINMUX0_23_20
PINMUX0_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX0_15_12
PINMUX0_11_8
PINMUX0_7_4
PINMUX0_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX0_31_28
K15
59
Value
EMB_WE Control
0
Pin is 3-stated.
1h
Selects Function EMB_WE
2h-Fh
27-24
PINMUX0_27_24
A8
110
PINMUX0_23_20
L13
EMB_RAS Control
Pin is 3-stated.
1h
Selects Function EMB_RAS
57
PINMUX0_19_16
D9
EMB_CAS Control
Pin is 3-stated.
1h
Selects Function EMB_CAS
108
(2)
Reserved
EMB_CS[0] Control
0
Pin is 3-stated.
1h
Selects Function EMB_CS[0]
2h-Fh
(1)
Reserved
0
2h-Fh
19-16
Reserved
0
2h-Fh
23-20
Description
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX0_15_12
C14
86
Value
EMB_CLK Control
0
Pin is 3-stated.
1h
Selects Function EMB_CLK from EMIFB LPSC (CLK1)
2h
Selects Function EMB_CLK from PLL DIV4P5 or SYSCLK5 (CLK2)
3h-Fh
11-8
PINMUX0_11_8
C13
88
PINMUX0_7_4
J5
EMB_SDCKE Control
Pin is 3-stated.
1h
Selects Function EMB_SDCKE
—
0
Pin is 3-stated.
1h
Selects Function GP7[15]
8h
9h-Fh
PINMUX0_3_0
K1
157
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Reserved
Selects Function EMU[0]
Reserved
GP7[14] Control. GP7[14] is initially configured as a reserved function after
reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. You should carefully
consider the system implications of this pin being in an unknown state after
reset.
0
Reserved
1h
Selects Function GP7[14]
2h-Fh
190
Reserved
GP7[15]/EMU[0] Control
2h-7h
3-0
Reserved
0
2h-Fh
7-4
Description
Reserved
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10.5.10.2 Pin Multiplexing Control 1 Register (PINMUX1)
Figure 10-19. Pin Multiplexing Control 1 Register (PINMUX1)
31
28
27
24
23
20
19
16
PINMUX1_31_28
PINMUX1_27_24
PINMUX1_23_20
PINMUX1_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX1_15_12
PINMUX1_11_8
PINMUX1_7_4
PINMUX1_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX1_31_28
C11
97
Value
EMB_A[5]/GP7[7] Control
0
Pin is 3-stated.
1h
Selects Function EMB_A[5]
2h-7h
8h
9h-Fh
27-24
PINMUX1_27_24
D11
98
Pin is 3-stated.
Selects Function EMB_A[4]
100
Pin is 3-stated.
Selects Function EMB_A[3]
101
Pin is 3-stated.
Selects Function EMB_A[2]
102
Selects Function GP7[4]
Reserved
EMB_A[1]/GP7[3] Control
Pin is 3-stated.
1h
Selects Function EMB_A[1]
8h
9h-Fh
(2)
Reserved
0
2h-7h
(1)
Reserved
0
9h-Fh
C10
Selects Function GP7[5]
1h
8h
PINMUX1_15_12
Reserved
EMB_A[2]/GP7[4] Control
2h-7h
15-12
Reserved
0
8h
B10
Selects Function GP7[6]
1h
9h-Fh
PINMUX1_19_16
Reserved
EMB_A[3]/GP7[5] Control
2h-7h
19-16
Reserved
1h
9h-Fh
A10
Selects Function GP7[7]
EMB_A[4]/GP7[6] Control
8h
PINMUX1_23_20
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP7[3]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued)
Bit
11-8
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX1_11_8
D10
103
Value
EMB_A[0]/GP7[2] Control
0
Pin is 3-stated.
1h
Selects Function EMB_A[0]
2h-7h
8h
9h-Fh
7-4
PINMUX1_7_4
C9
107
Pin is 3-stated.
Selects Function EMB_BA[0]
106
Selects Function GP7[1]
Reserved
EMB_BA[1]/GP7[0] Control
Pin is 3-stated.
1h
Selects Function EMB_BA[1]
8h
9h-Fh
System Configuration (SYSCFG) Module
Reserved
0
2h-7h
192
Reserved
0
8h
B9
Selects Function GP7[2]
1h
9h-Fh
PINMUX1_3_0
Reserved
EMB_BA[0]/GP7[1] Control
2h-7h
3-0
Description
Reserved
Selects Function GP7[0]
Reserved
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10.5.10.3 Pin Multiplexing Control 2 Register (PINMUX2)
Figure 10-20. Pin Multiplexing Control 2 Register (PINMUX2)
31
28
27
24
23
20
19
16
PINMUX2_31_28
PINMUX2_27_24
PINMUX2_23_20
PINMUX2_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX2_15_12
PINMUX2_11_8
PINMUX2_7_4
PINMUX2_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX2_31_28
G14
—
Value
EMB_D[31] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[31]
2h-Fh
27-24
PINMUX2_27_24
B15
89
EMB_A[12]/GP3[13] Control
Pin is 3-stated.
1h
Selects Function EMB_A[12]
8h
9h-Fh
PINMUX2_23_20
B12
91
Pin is 3-stated.
Selects Function EMB_A[11]
105
1h
Selects Function EMB_A[10]
92
Selects Function GP7[12]
Reserved
EMB_A[9]/GP7[11] Control
Pin is 3-stated.
1h
Selects Function EMB_A[9]
8h
9h-Fh
(2)
Reserved
0
2h-7h
(1)
Reserved
Pin is 3-stated.
9h-Fh
C12
Selects Function GP7[13]
EMB_A[10]/GP7[12] Control
8h
PINMUX2_15_12
Reserved
0
2h-7h
15-12
Reserved
0
8h
A9
Selects Function GP3[13]
1h
9h-Fh
PINMUX2_19_16
Reserved
EMB_A[11]/GP7[13] Control
2h-7h
19-16
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP7[11]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
SPRUH91D – March 2013 – Revised September 2016
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Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued)
Bit
11-8
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX2_11_8
D12
94
Value
EMB_A[8]/GP7[10] Control
0
Pin is 3-stated.
1h
Selects Function EMB_A[8]
2h-7h
8h
9h-Fh
7-4
PINMUX2_7_4
A11
95
Pin is 3-stated.
Selects Function EMB_A[7]
96
Reserved
Selects Function GP7[9]
Reserved
EMB_A[6]/GP7[8] Control
0
Pin is 3-stated.
1h
Selects Function EMB_A[6]
2h-7h
8h
9h-Fh
194
Reserved
0
8h
B11
Selects Function GP7[10]
1h
9h-Fh
PINMUX2_3_0
Reserved
EMB_A[7]/GP7[9] Control
2h-7h
3-0
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP7[8]
Reserved
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10.5.10.4 Pin Multiplexing Control 3 Register (PINMUX3)
Figure 10-21. Pin Multiplexing Control 3 Register (PINMUX3)
31
28
27
24
23
20
19
16
PINMUX3_31_28
PINMUX3_27_24
PINMUX3_23_20
PINMUX3_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX3_15_12
PINMUX3_11_8
PINMUX3_7_4
PINMUX3_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX3_31_28
L15
—
Value
EMB_D[23] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[23]
2h-Fh
27-24
PINMUX3_27_24
A13
—
PINMUX3_23_20
B14
EMB_D[24] Control
Pin is 3-stated.
1h
Selects Function EMB_D[24]
—
PINMUX3_19_16
A14
0
Pin is 3-stated.
1h
Selects Function EMB_D[25]
—
PINMUX3_15_12
E14
0
Pin is 3-stated.
1h
Selects Function EMB_D[26]
—
PINMUX3_11_8
E15
EMB_D[27] Control
Pin is 3-stated.
1h
Selects Function EMB_D[27]
—
PINMUX3_7_4
F14
EMB_D[28] Control
Pin is 3-stated.
1h
Selects Function EMB_D[28]
—
PINMUX3_3_0
F15
EMB_D[29] Control
Pin is 3-stated.
1h
Selects Function EMB_D[29]
—
(2)
Reserved
EMB_D[30] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[30]
2h-Fh
(1)
Reserved
0
2h-Fh
3-0
Reserved
0
2h-Fh
7-4
Reserved
0
2h-Fh
11-8
Reserved
EMB_D[26] Control
2h-Fh
15-12
Reserved
EMB_D[25] Control
2h-Fh
19-16
Reserved
0
2h-Fh
23-20
Description
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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10.5.10.5 Pin Multiplexing Control 4 Register (PINMUX4)
Figure 10-22. Pin Multiplexing Control 4 Register (PINMUX4)
31
28
27
24
23
20
19
16
PINMUX4_31_28
PINMUX4_27_24
PINMUX4_23_20
PINMUX4_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX4_15_12
PINMUX4_11_8
PINMUX4_7_4
PINMUX4_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX4_31_28
A12
—
Value
EMB_WE_DQM[3] Control
0
Pin is 3-stated.
1h
Selects Function EMB_WE_DQM[3]
2h-Fh
27-24
PINMUX4_27_24
G15
—
PINMUX4_23_20
H14
EMB_D[16] Control
Pin is 3-stated.
1h
Selects Function EMB_D[16]
—
PINMUX4_19_16
H15
0
Pin is 3-stated.
1h
Selects Function EMB_D[17]
—
PINMUX4_15_12
J14
0
Pin is 3-stated.
1h
Selects Function EMB_D[18]
—
PINMUX4_11_8
K13
EMB_D[19] Control
Pin is 3-stated.
1h
Selects Function EMB_D[19]
—
PINMUX4_7_4
K16
EMB_D[20] Control
Pin is 3-stated.
1h
Selects Function EMB_D[20]
—
PINMUX4_3_0
L14
EMB_D[21] Control
Pin is 3-stated.
1h
Selects Function EMB_D[21]
—
(2)
196
Reserved
EMB_D[22] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[22]
2h-Fh
(1)
Reserved
0
2h-Fh
3-0
Reserved
0
2h-Fh
7-4
Reserved
0
2h-Fh
11-8
Reserved
EMB_D[18] Control
2h-Fh
15-12
Reserved
EMB_D[17] Control
2h-Fh
19-16
Reserved
0
2h-Fh
23-20
Description
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
System Configuration (SYSCFG) Module
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10.5.10.6 Pin Multiplexing Control 5 Register (PINMUX5)
Figure 10-23. Pin Multiplexing Control 5 Register (PINMUX5)
31
28
27
24
23
20
19
16
PINMUX5_31_28
PINMUX5_27_24
PINMUX5_23_20
PINMUX5_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX5_15_12
PINMUX5_11_8
PINMUX5_7_4
PINMUX5_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX5_31_28
J15
63
Value
EMB_D[6]/GP6[6] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[6]
2h-7h
8h
9h-Fh
27-24
PINMUX5_27_24
J13
64
Pin is 3-stated.
Selects Function EMB_D[5]
66
Pin is 3-stated.
Selects Function EMB_D[4]
68
Pin is 3-stated.
Selects Function EMB_D[3]
70
Selects Function GP6[3]
Reserved
EMB_D[2]/GP6[2] Control
Pin is 3-stated.
1h
Selects Function EMB_D[2]
8h
9h-Fh
(2)
Reserved
0
2h-7h
(1)
Reserved
0
9h-Fh
G16
Selects Function GP6[4]
1h
8h
PINMUX5_15_12
Reserved
EMB_D[3]/GP6[3] Control
2h-7h
15-12
Reserved
0
8h
H13
Selects Function GP6[5]
1h
9h-Fh
PINMUX5_19_16
Reserved
EMB_D[4]/GP6[4] Control
2h-7h
19-16
Reserved
1h
9h-Fh
H16
Selects Function GP6[6]
EMB_D[5]/GP6[5] Control
8h
PINMUX5_23_20
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP6[2]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued)
Bit
11-8
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX5_11_8
G13
72
Value
EMB_D[1]/GP6[1] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[1]
2h-7h
8h
9h-Fh
7-4
PINMUX5_7_4
F16
73
Pin is 3-stated.
Selects Function EMB_D[0]
—
Reserved
Selects Function GP6[0]
Reserved
EMB_WE_DQM[2] Control
0
Pin is 3-stated.
1h
Selects Function EMB_WE_DQM[2]
2h-Fh
198
Reserved
0
8h
B13
Selects Function GP6[1]
1h
9h-Fh
PINMUX5_3_0
Reserved
EMB_D[0]/GP6[0] Control
2h-7h
3-0
Description
System Configuration (SYSCFG) Module
Reserved
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10.5.10.7 Pin Multiplexing Control 6 Register (PINMUX6)
Figure 10-24. Pin Multiplexing Control 6 Register (PINMUX6)
31
28
27
24
23
20
19
16
PINMUX6_31_28
PINMUX6_27_24
PINMUX6_23_20
PINMUX6_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX6_15_12
PINMUX6_11_8
PINMUX6_7_4
PINMUX6_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX6_31_28
E16
76
Value
EMB_D[14]/GP6[14] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[14]
2h-7h
8h
9h-Fh
27-24
PINMUX6_27_24
E13
78
Pin is 3-stated.
Selects Function EMB_D[13]
79
Pin is 3-stated.
Selects Function EMB_D[12]
80
Pin is 3-stated.
Selects Function EMB_D[11]
82
Selects Function GP6[11]
Reserved
EMB_D[10]/GP6[10] Control
Pin is 3-stated.
1h
Selects Function EMB_D[10]
8h
9h-Fh
(2)
Reserved
0
2h-7h
(1)
Reserved
0
9h-Fh
D14
Selects Function GP6[12]
1h
8h
PINMUX6_15_12
Reserved
EMB_D[11]/GP6[11] Control
2h-7h
15-12
Reserved
0
8h
D15
Selects Function GP6[13]
1h
9h-Fh
PINMUX6_19_16
Reserved
EMB_D[12]/GP6[12] Control
2h-7h
19-16
Reserved
1h
9h-Fh
D16
Selects Function GP6[14]
EMB_D[13]/GP6[13] Control
8h
PINMUX6_23_20
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP6[10]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued)
Bit
11-8
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX6_11_8
D13
83
Value
EMB_D[9]/GP6[9] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[9]
2h-7h
8h
9h-Fh
7-4
PINMUX6_7_4
C16
84
Pin is 3-stated.
Selects Function EMB_D[8]
62
Reserved
Selects Function GP6[8]
Reserved
EMB_D[7]/GP6[7] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[7]
2h-7h
8h
9h-Fh
200
Reserved
0
8h
J16
Selects Function GP6[9]
1h
9h-Fh
PINMUX6_3_0
Reserved
EMB_D[8]/GP6[8] Control
2h-7h
3-0
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP6[7]
Reserved
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10.5.10.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 10-25. Pin Multiplexing Control 7 Register (PINMUX7)
31
28
27
24
23
20
19
16
PINMUX7_31_28
PINMUX7_27_24
PINMUX7_23_20
PINMUX7_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX7_15_12
PINMUX7_11_8
PINMUX7_7_4
PINMUX7_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX7_31_28
N4
9
Value
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[0]
2h
Selects Function UART0_RTS
3h
Reserved
4h
Selects Function EQEP0B
5h-7h
8h
9h-Fh
27-24
PINMUX7_27_24
R5
12
Pin is 3-stated.
Selects Function SPI0_ENA
2h
Selects Function UART0_CTS
3h
Reserved
4h
Selects Function EQEP0A
11
Pin is 3-stated.
Selects Function SPI0_CLK
2h
Selects Function EQEP1I
18
Selects Function GP5[2]
Reserved
0
Pin is 3-stated.
1h
Selects Function SPI0_SIMO[0]
2h
Selects Function EQEP0S
8h
9h-Fh
(2)
Reserved
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] Control
3h-7h
(1)
Reserved
0
8h
P6
Selects Function GP5[3]
1h
9h-Fh
PINMUX7_19_16
Reserved
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] Control
3h-7h
19-16
Reserved
1h
8h
T5
Selects Function GP5[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] Control
9h-Fh
PINMUX7_23_20
Reserved
0
5h-7h
23-20
Description
Reserved
Selects Function GP5[1]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX7_15_12
R6
17
Value
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SOMI[0]
2h
Selects Function EQEP0I
3h-7h
8h
9h-Fh
11-8
PINMUX7_11_8
K14
60
Pin is 3-stated.
Selects Function EMB_WE_DQM[0]
85
Pin is 3-stated.
Selects Function EMB_WE_DQM[1]
74
Reserved
Selects Function GP5[14]
Reserved
EMB_D[15]/GP6[15] Control
0
Pin is 3-stated.
1h
Selects Function EMB_D[15]
2h-7h
8h
9h-Fh
202
Reserved
0
8h
F13
Selects Function GP5[15]
1h
9h-Fh
PINMUX7_3_0
Reserved
EMB_WE_DQM[1]/GP5[14] Control
2h-7h
3-0
Reserved
1h
9h-Fh
C15
Selects Function GP5[0]
EMB_WE_DQM[0]/GP5[15] Control
8h
PINMUX7_7_4
Reserved
0
2h-7h
7-4
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP6[15]
Reserved
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10.5.10.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 10-26. Pin Multiplexing Control 8 Register (PINMUX8)
31
28
27
24
23
20
19
16
PINMUX8_31_28
PINMUX8_27_24
PINMUX8_23_20
PINMUX8_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX8_15_12
PINMUX8_11_8
PINMUX8_7_4
PINMUX8_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX8_31_28
R4
7
Value
SPI1_ENA/UART2_RXD/GP5[12] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_ENA
2h
Selects Function UART2_RXD
3h-7h
8h
9h-Fh
27-24
PINMUX8_27_24
T4
6
1h
Selects Function AXR1[11]
4
Pin is 3-stated.
Selects Function AXR1[10]
3
Selects Function GP5[10]
Reserved
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] Control
Pin is 3-stated.
1h
Selects Function UART0_TXD
2h
Selects Function I2C0_SCL
3h
Reserved
4h
Selects Function TM64P0_OUT12
8h
9h-Fh
(2)
Reserved
0
5h-7h
(1)
Reserved
1h
9h-Fh
P3
Selects Function GP5[11]
AXR1[10]/GP5[10] Control
8h
PINMUX8_19_16
Reserved
0
2h-7h
19-16
Reserved
Pin is 3-stated.
9h-Fh
N3
Selects Function GP5[12]
AXR1[11]/GP5[11] Control
8h
PINMUX8_23_20
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP5[9]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX8_15_12
R3
2
Value
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] Control
0
Pin is 3-stated.
1h
Selects Function UART0_RXD
2h
Selects Function I2C0_SDA
3h
Reserved
4h
Selects Function TM64P0_IN12
5h-7h
8h
9h-Fh
11-8
PINMUX8_11_8
T6
16
Pin is 3-stated.
Selects Function SPI1_CLK
2h
Selects Function EQEP1S
14
Pin is 3-stated.
Selects Function SPI1_SIMO[0]
2h
Selects Function I2C1_SDA
13
Reserved
Selects Function GP5[6]
Reserved
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SOMI[0]
2h
Selects Function I2C1_SCL
3h-7h
8h
9h-Fh
204
Reserved
0
9h-Fh
P5
Selects Function GP5[7]
1h
8h
PINMUX8_3_0
Reserved
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] Control
3h-7h
3-0
Reserved
0
8h
N5
Selects Function GP5[8]
1h
9h-Fh
PINMUX8_7_4
Reserved
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] Control
3h-7h
7-4
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP5[5]
Reserved
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10.5.10.10 Pin Multiplexing Control 9 Register (PINMUX9)
Figure 10-27. Pin Multiplexing Control 9 Register (PINMUX9)
31
28
27
24
23
20
19
16
PINMUX9_31_28
PINMUX9_27_24
PINMUX9_23_20
PINMUX9_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX9_15_12
PINMUX9_11_8
PINMUX9_7_4
PINMUX9_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX9_31_28
C4
131
Value
AFSR0/GP3[12] Control
0
Pin is 3-stated.
1h
Selects Function AFSR0
2h-7h
8h
9h-Fh
27-24
PINMUX9_27_24
B4
130
Pin is 3-stated.
Selects Function ACLKR0
2h
Selects Function ECAP1/APWM1
129
1h
Selects Function AHCLKR0
2h
Selects Function RMII_MHZ_50_CLK. Enables sourcing of the EMAC
50 MHz reference clock from PLL SYSCLK7. Also, SYSCLK7 is driven out on
the RMII_MHZ_50_CLK pin.
127
Selects Function GP2[14]
Reserved
AFSX0/GP2[13]/BOOT[10] Control
Pin is 3-stated.
1h
Selects Function AFSX0
8h
9h-Fh
(2)
Reserved
0
2h-7h
(1)
Reserved
Pin is 3-stated. Enables sourcing of the EMAC 50 MHz reference clock from
an external source on the RMII_MHZ_50_CLK pin.
9h-Fh
D5
Selects Function GP2[15]
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] Control
8h
PINMUX9_19_16
Reserved
0
3h-7h
19-16
Reserved
1h
9h-Fh
A4
Selects Function GP3[12]
ACLKR0/ECAP1/APWM1/GP2[15] Control
8h
PINMUX9_23_20
Reserved
0
3h-7h
23-20
Description
Reserved
Selects Function GP2[13]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX9_15_12
C5
126
Value
ACLKX0/ECAP0/APWM0/GP2[12] Control
0
Pin is 3-stated.
1h
Selects Function ACLKX0
2h
Selects Function ECAP0/APWM0
3h-7h
8h
9h-Fh
11-8
PINMUX9_11_8
B5
125
Pin is 3-stated.
Selects Function AHCLKX0
2h
Selects Function AHCLKX2
3h
Reserved
4h
Selects Function USB_REFCLKIN
—
Pin is 3-stated.
Selects Function USB0_DRVVBUS
8
Reserved
Selects Function GP4[15]
Reserved
SPI1_SCS[0]/UART2_TXD/GP5[13] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[0]
2h
Selects Function UART2_TXD
3h-7h
8h
9h-Fh
206
Reserved
0
8h
P4
Selects Function GP2[11]
1h
9h-Fh
PINMUX9_3_0
Reserved
USB0_DRVVBUS/GP4[15] Control
2h-7h
3-0
Reserved
1h
8h
E4
Selects Function GP2[12]
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] Control
9h-Fh
PINMUX9_7_4
Reserved
0
5h-7h
7-4
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP5[13]
Reserved
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10.5.10.11 Pin Multiplexing Control 10 Register (PINMUX10)
Figure 10-28. Pin Multiplexing Control 10 Register (PINMUX10)
31
28
27
24
23
20
19
16
PINMUX10_31_28
PINMUX10_27_24
PINMUX10_23_20
PINMUX10_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX10_15_12
PINMUX10_11_8
PINMUX10_7_4
PINMUX10_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX10_31_28
D7
118
Value
AXR0[6]/RMII_RXER[0]/ACLKR2/GP3[6] Control
0
Pin is 3-stated.
1h
Selects Function AXR0[6]
2h
Selects Function RMII_RXER[0]
3h
Reserved
4h
Selects Function ACLKR2
5h-7h
8h
9h-Fh
27-24
PINMUX10_27_24
C7
117
Pin is 3-stated.
Selects Function AXR0[5]
2h
Selects Function RMII_RXD[1]
3h
Reserved
4h
Selects Function AFSX2
116
Selects Function GP3[5]
Reserved
0
Pin is 3-stated.
1h
Selects Function AXR0[4]
2h
Selects Function RMII_RXD[0]
3h
Reserved
4h
Selects Function AXR2[1]
8h
9h-Fh
(2)
Reserved
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] Control
5h-7h
(1)
Reserved
1h
8h
B7
Selects Function GP3[6]
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] Control
9h-Fh
PINMUX10_23_20
Reserved
0
5h-7h
23-20
Description
Reserved
Selects Function GP3[4]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued)
Bit
19-16
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX10_19_16
A7
115
Value
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR0[3]
2h
Selects Function RMII_CRS_DV
3h
Reserved
4h
Selects Function AXR2[2]
5h-7h
8h
9h-Fh
15-12
PINMUX10_15_12
D8
113
Pin is 3-stated.
Selects Function AXR0[2]
2h
Selects Function RMII_TXEN
3h
Reserved
4h
Selects Function AXR2[3]
112
1h
Selects Function AXR0[1]
2h
Selects Function RMII_TXD[1]
3h
Reserved
4h
Selects Function ACLKX2
111
Pin is 3-stated.
Selects Function AXR0[0]
2h
Selects Function RMII_TXD[0]
3h
Reserved
4h
Selects Function AFSR2
—
Reserved
Selects Function GP3[0]
Reserved
AMUTE0/RESETOUT Control
0
Selects Function RESETOUT
1h
Selects Function AMUTE0
2h-7h
8h
9h-Fh
208
Reserved
1h
8h
L4
Selects Function GP3[1]
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] Control
9h-Fh
PINMUX10_3_0
Reserved
0
5h-7h
3-0
Reserved
Pin is 3-stated.
9h-Fh
B8
Selects Function GP3[2]
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] Control
8h
PINMUX10_7_4
Reserved
0
5h-7h
7-4
Reserved
0
9h-Fh
C8
Selects Function GP3[3]
1h
8h
PINMUX10_11_8
Reserved
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] Control
5h-7h
11-8
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function RESETOUT
Reserved
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10.5.10.12 Pin Multiplexing Control 11 Register (PINMUX11)
Figure 10-29. Pin Multiplexing Control 11 Register (PINMUX11)
31
28
27
24
23
20
19
16
PINMUX11_31_28
PINMUX11_27_24
PINMUX11_23_20
PINMUX11_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX11_15_12
PINMUX11_11_8
PINMUX11_7_4
PINMUX11_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX11_31_28
K4
163
Value
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10] Control
0
Pin is 3-stated.
1h
Selects Function AFSX1
2h
Selects Function EPWMSYNCI
3h
Reserved
4h
Selects Function EPWMSYNC0
5h-7h
8h
9h-Fh
27-24
PINMUX11_27_24
K3
162
Pin is 3-stated.
Selects Function ACLKX1
2h
Selects Function EPWM0A
160
Pin is 3-stated.
Selects Function AHCLKX1
2h
Selects Function EPWM0B
124
Selects Function GP3[14]
Reserved
AXR0[11]/AXR2[0]/GP3[11] Control
Pin is 3-stated.
1h
Selects Function AXR0[11]
4h
5h-7h
8h
9h-Fh
(2)
Reserved
0
2h-3h
(1)
Reserved
1h
9h-Fh
A5
Selects Function GP3[15]
AHCLKX1/EPWM0B/GP3[14] Control
8h
PINMUX11_19_16
Reserved
0
3h-7h
19-16
Reserved
1h
9h-Fh
K2
Selects Function GP4[10]
ACLKX1/EPWM0A/GP3[15] Control
8h
PINMUX11_23_20
Reserved
0
3h-7h
23-20
Description
Reserved
Selects Function AXR2[0]
Reserved
Selects Function GP3[11]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX11_15_12
D6
123
Value
UART1_TXD/AXR0[10]/GP3[10] Control
0
Pin is 3-stated.
1h
Selects Function UART1_TXD
2h
Selects Function AXR0[10]
3h-7h
8h
9h-Fh
11-8
PINMUX11_11_8
C6
122
Pin is 3-stated.
Selects Function UART1_RXD
2h
Selects Function AXR0[9]
121
Pin is 3-stated.
Selects Function AXR0[8]
2h
Selects Function MDIO_D
120
Selects Function GP3[8]
Reserved
AXR0[7]/MDIO_CLK/GP3[7] Control
Pin is 3-stated.
1h
Selects Function AXR0[7]
2h
Selects Function MDIO_CLK
8h
9h-Fh
System Configuration (SYSCFG) Module
Reserved
0
3h-7h
210
Reserved
1h
9h-Fh
A6
Selects Function GP3[9]
AXR0[8]/MDIO_D/GP3[8] Control
8h
PINMUX11_3_0
Reserved
0
3h-7h
3-0
Reserved
1h
9h-Fh
B6
Selects Function GP3[10]
UART1_RXD/AXR0[9]/GP3[9] Control
8h
PINMUX11_7_4
Reserved
0
3h-7h
7-4
Description
Reserved
Selects Function GP3[7]
Reserved
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10.5.10.13 Pin Multiplexing Control 12 Register (PINMUX12)
Figure 10-30. Pin Multiplexing Control 12 Register (PINMUX12)
31
28
27
24
23
20
19
16
PINMUX12_31_28
PINMUX12_27_24
PINMUX12_23_20
PINMUX12_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX12_15_12
PINMUX12_11_8
PINMUX12_7_4
PINMUX12_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX12_31_28
P1
174
Value
AXR1[3]/EQEP1A/GP4[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR1[3]
2h
Selects Function EQEP1A
3h-7h
8h
9h-Fh
27-24
PINMUX12_27_24
P2
175
1h
Selects Function AXR1[2]
176
Pin is 3-stated.
Selects Function AXR1[1]
1
Pin is 3-stated.
Selects Function AXR1[0]
132
Selects Function GP4[0]
Reserved
0
Pin is 3-stated.
1h
Selects Function AMUTE1
2h
Selects Function EHRPWMTZ
8h
9h-Fh
(2)
Reserved
AMUTE1/EHRPWMTZ/GP4[14] Control
3h-7h
(1)
Reserved
1h
8h
D4
Selects Function GP4[1]
AXR1[0]/GP4[0] Control
9h-Fh
PINMUX12_15_12
Reserved
0
2h-7h
15-12
Reserved
1h
9h-Fh
T3
Selects Function GP4[2]
AXR1[1]/GP4[1] Control
8h
PINMUX12_19_16
Reserved
0
2h-7h
19-16
Reserved
Pin is 3-stated.
9h-Fh
R2
Selects Function GP4[3]
AXR1[2]/GP4[2] Control
8h
PINMUX12_23_20
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP4[14]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued)
Bit
11-8
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX12_11_8
L3
166
Value
AFSR1/GP4[13] Control
0
Pin is 3-stated.
1h
Selects Function AFSR1
2h-7h
8h
9h-Fh
7-4
PINMUX12_7_4
L2
165
Pin is 3-stated.
Selects Function ACLKR1
2h
Selects Function ECAP2/APWM2
—
Reserved
Selects Function GP4[12]
Reserved
AHCLKR1/GP4[11] Control
0
Pin is 3-stated.
1h
Selects Function AHCLKR1
2h-7h
8h
9h-Fh
212
Reserved
0
9h-Fh
L1
Selects Function GP4[13]
1h
8h
PINMUX12_3_0
Reserved
ACLKR1/ECAP2/APWM2/GP4[12] Control
3h-7h
3-0
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP4[11]
Reserved
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10.5.10.14 Pin Multiplexing Control 13 Register (PINMUX13)
Figure 10-31. Pin Multiplexing Control 13 Register (PINMUX13)
31
28
27
24
23
20
19
16
PINMUX13_31_28
PINMUX13_27_24
PINMUX13_23_20
PINMUX13_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX13_15_12
PINMUX13_11_8
PINMUX13_7_4
PINMUX13_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX13_31_28
R15
45
Value
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[1]
2h
Selects Function MMCSD_DAT[1]
3h
Reserved
4h
Selects Function UHPI_HD[1]
5h-7h
8h
9h-Fh
27-24
PINMUX13_27_24
T13
44
Pin is 3-stated.
Selects Function EMA_D[0]
2h
Selects Function MMCSD_DAT[0]
3h
Reserved
4h
Selects Function UHPI_HD[0]
—
Pin is 3-stated.
Selects Function AXR1[9]
168
Selects Function GP4[9]
Reserved
AXR1[8]/EPWM1A/GP4[8] Control
Pin is 3-stated.
1h
Selects Function AXR1[8]
2h
Selects Function EPWM1A
8h
9h-Fh
(2)
Reserved
0
3h-7h
(1)
Reserved
0
9h-Fh
M2
Selects Function GP0[0]
1h
8h
PINMUX13_19_16
Reserved
AXR1[9]/GP4[9] Control
2h-7h
19-16
Reserved
1h
8h
M1
Selects Function GP0[1]
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] Control
9h-Fh
PINMUX13_23_20
Reserved
0
5h-7h
23-20
Description
Reserved
Selects Function GP4[8]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
SPRUH91D – March 2013 – Revised September 2016
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Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX13_15_12
M3
169
Value
AXR1[7]/EPWM1B/GP4[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR1[7]
2h
Selects Function EPWM1B
3h-7h
8h
9h-Fh
11-8
PINMUX13_11_8
M4
170
Pin is 3-stated.
Selects Function AXR1[6]
2h
Selects Function EPWM2A
171
Pin is 3-stated.
Selects Function AXR1[5]
2h
Selects Function EPWM2B
173
Selects Function GP4[5]
Reserved
AXR1[4]/EQEP1B/GP4[4] Control
Pin is 3-stated.
1h
Selects Function AXR1[4]
2h
Selects Function EQEP1B
8h
9h-Fh
System Configuration (SYSCFG) Module
Reserved
0
3h-7h
214
Reserved
1h
9h-Fh
N2
Selects Function GP4[6]
AXR1[5]/EPWM2B/GP4[5] Control
8h
PINMUX13_3_0
Reserved
0
3h-7h
3-0
Reserved
1h
9h-Fh
N1
Selects Function GP4[7]
AXR1[6]/EPWM2A/GP4[6] Control
8h
PINMUX13_7_4
Reserved
0
3h-7h
7-4
Description
Reserved
Selects Function GP4[4]
Reserved
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10.5.10.15 Pin Multiplexing Control 14 Register (PINMUX14)
Figure 10-32. Pin Multiplexing Control 14 Register (PINMUX14)
31
28
27
24
23
20
19
16
PINMUX14_31_28
PINMUX14_27_24
PINMUX14_23_20
PINMUX14_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX14_15_12
PINMUX14_11_8
PINMUX14_7_4
PINMUX14_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX14_31_28
T14
—
Value
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[9]
2h
Selects Function UHPI_HD[9]
3h
Reserved
4h
Selects Function LCD_D[9]
5h-7h
8h
9h-Fh
27-24
PINMUX14_27_24
N12
—
Pin is 3-stated.
Selects Function EMA_D[8]
2h
Selects Function UHPI_HD[8]
3h
Reserved
4h
Selects Function LCD_D[8]
54
Selects Function GP0[8]
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_D[7]
2h
Selects Function MMCSD_DAT[7]
3h
Reserved
4h
Selects Function UHPI_HD[7]
8h
9h-Fh
(2)
Reserved
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] Control
5h-7h
(1)
Reserved
1h
8h
M15
Selects Function GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] Control
9h-Fh
PINMUX14_23_20
Reserved
0
5h-7h
23-20
Description
Reserved
Selects Function GP0[7]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued)
Bit
19-16
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX14_19_16
N13
52
Value
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[6]
2h
Selects Function MMCSD_DAT[6]
3h
Reserved
4h
Selects Function UHPI_HD[6]
5h-7h
8h
9h-Fh
15-12
PINMUX14_15_12
N15
51
Pin is 3-stated.
Selects Function EMA_D[5]
2h
Selects Function MMCSD_DAT[5]
3h
Reserved
4h
Selects Function UHPI_HD[5]
49
1h
Selects Function EMA_D[4]
2h
Selects Function MMCSD_DAT[4]
3h
Reserved
4h
Selects Function UHPI_HD[4]
48
Pin is 3-stated.
Selects Function EMA_D[3]
2h
Selects Function MMCSD_DAT[3]
3h
Reserved
4h
Selects Function UHPI_HD[3]
46
Reserved
Selects Function GP0[3]
Reserved
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[2]
2h
Selects Function MMCSD_DAT[2]
3h
Reserved
4h
Selects Function UHPI_HD[2]
5h-7h
8h
9h-Fh
216
Reserved
1h
8h
R13
Selects Function GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] Control
9h-Fh
PINMUX14_3_0
Reserved
0
5h-7h
3-0
Reserved
Pin is 3-stated.
9h-Fh
P15
Selects Function GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] Control
8h
PINMUX14_7_4
Reserved
0
5h-7h
7-4
Reserved
0
9h-Fh
P13
Selects Function GP0[6]
1h
8h
PINMUX14_11_8
Reserved
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] Control
5h-7h
11-8
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP0[2]
Reserved
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10.5.10.16 Pin Multiplexing Control 15 Register (PINMUX15)
Figure 10-33. Pin Multiplexing Control 15 Register (PINMUX15)
31
28
27
24
23
20
19
16
PINMUX15_31_28
PINMUX15_27_24
PINMUX15_23_20
PINMUX15_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX15_15_12
PINMUX15_11_8
PINMUX15_7_4
PINMUX15_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX15_31_28
R9
30
Value
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[1]
2h
Selects Function MMCSD_CLK
3h
Reserved
4h
Selects Function UHPI_HCNTL0
5h-7h
8h
9h-Fh
27-24
PINMUX15_27_24
T9
29
Pin is 3-stated.
Selects Function EMA_A[0]
2h
Selects Function LCD_D[7]
—
Selects Function GP1[0]
Reserved
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] Control
Pin is 3-stated.
1h
Selects Function EMA_D[15]
2h
Selects Function UHPI_HD[15]
3h
Reserved
4h
Selects Function LCD_D[15]
8h
9h-Fh
(2)
Reserved
0
5h-7h
(1)
Reserved
1h
9h-Fh
M16
Selects Function GP1[1]
EMA_A[0]/LCD_D[7]/GP1[0] Control
8h
PINMUX15_23_20
Reserved
0
3h-7h
23-20
Description
Reserved
Selects Function GP0[15]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
19-16
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX15_19_16
N14
—
Value
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[14]
2h
Selects Function UHPI_HD[14]
3h
Reserved
4h
Selects Function LCD_D[14]
5h-7h
8h
9h-Fh
15-12
PINMUX15_15_12
N16
—
Pin is 3-stated.
Selects Function EMA_D[13]
2h
Selects Function UHPI_HD[13]
3h
Reserved
4h
Selects Function LCD_D[13]
—
1h
Selects Function EMA_D[12]
2h
Selects Function UHPI_HD[12]
3h
Reserved
4h
Selects Function LCD_D[12]
—
Pin is 3-stated.
Selects Function EMA_D[11]
2h
Selects Function UHPI_HD[11]
3h
Reserved
4h
Selects Function LCD_D[11]
—
Reserved
Selects Function GP0[11]
Reserved
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[10]
2h
Selects Function UHPI_HD[10]
3h
Reserved
4h
Selects Function LCD_D[10]
5h-7h
8h
9h-Fh
218
Reserved
1h
8h
R14
Selects Function GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] Control
9h-Fh
PINMUX15_3_0
Reserved
0
5h-7h
3-0
Reserved
Pin is 3-stated.
9h-Fh
P16
Selects Function GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] Control
8h
PINMUX15_7_4
Reserved
0
5h-7h
7-4
Reserved
0
9h-Fh
P14
Selects Function GP0[14]
1h
8h
PINMUX15_11_8
Reserved
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] Control
5h-7h
11-8
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP0[10]
Reserved
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10.5.10.17 Pin Multiplexing Control 16 Register (PINMUX16)
Figure 10-34. Pin Multiplexing Control 16 Register (PINMUX16)
31
28
27
24
23
20
19
16
PINMUX16_31_28
PINMUX16_27_24
PINMUX16_23_20
PINMUX16_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX16_15_12
PINMUX16_11_8
PINMUX16_7_4
PINMUX16_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX16_31_28
R11
40
Value
EMA_A[9]/LCD_HSYNC/GP1[9] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[9]
2h
Selects Function LCD_HSYNC
3h-7h
8h
9h-Fh
27-24
PINMUX16_27_24
T11
39
1h
Selects Function EMA_A[8]
2h
Selects Function LCD_PCLK
37
1h
Selects Function EMA_A[7]
2h
Selects Function LCD_D[0]
36
Selects Function GP1[7]
Reserved
EMA_A[6]/LCD_D[1]/GP1[6] Control
Pin is 3-stated.
1h
Selects Function EMA_A[6]
2h
Selects Function LCD_D[1]
8h
9h-Fh
(2)
Reserved
0
3h-7h
(1)
Reserved
Pin is 3-stated.
8h
P10
Selects Function GP1[8]
EMA_A[7]/LCD_D[0]/GP1[7] Control
9h-Fh
PINMUX16_19_16
Reserved
0
3h-7h
19-16
Reserved
Pin is 3-stated.
9h-Fh
N10
Selects Function GP1[9]
EMA_A[8]/LCD_PCLK/GP1[8] Control
8h
PINMUX16_23_20
Reserved
0
3h-7h
23-20
Description
Reserved
Selects Function GP1[6]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX16_15_12
R10
35
Value
EMA_A[5]/LCD_D[2]/GP1[5] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[5]
2h
Selects Function LCD_D[2]
3h-7h
8h
9h-Fh
11-8
PINMUX16_11_8
T10
34
Pin is 3-stated.
Selects Function EMA_A[4]
2h
Selects Function LCD_D[3]
32
Pin is 3-stated.
Selects Function EMA_A[3]
2h
Selects Function LCD_D[6]
31
Reserved
Selects Function GP1[3]
Reserved
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[2]
2h
Selects Function MMCSD_CMD
3h
Reserved
4h
Selects Function UHPI_HCNTL1
5h-7h
8h
9h-Fh
220
Reserved
1h
9h-Fh
P9
Selects Function GP1[4]
EMA_A[3]/LCD_D[6]/GP1[3] Control
8h
PINMUX16_3_0
Reserved
0
3h-7h
3-0
Reserved
1h
9h-Fh
N9
Selects Function GP1[5]
EMA_A[4]/LCD_D[3]/GP1[4] Control
8h
PINMUX16_7_4
Reserved
0
3h-7h
7-4
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP1[2]
Reserved
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10.5.10.18 Pin Multiplexing Control 17 Register (PINMUX17)
Figure 10-35. Pin Multiplexing Control 17 Register (PINMUX17)
31
28
27
24
23
20
19
16
PINMUX17_31_28
PINMUX17_27_24
PINMUX17_23_20
PINMUX17_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX17_15_12
PINMUX17_11_8
PINMUX17_7_4
PINMUX17_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX17_31_28
L16
—
Value
EMA_CAS/EMA_CS[4]/GP2[1] Control
0
Pin is 3-stated.
1h
Selects Function EMA_CAS
2h
Selects Function EMA_CS[4]
3h-7h
8h
9h-Fh
27-24
PINMUX17_27_24
T12
—
1h
Selects Function EMA_SDCKE
—
Pin is 3-stated.
Selects Function EMA_CLK
2h
Selects Function OBSCLK.
3h
Reserved
4h
Selects Function AHCLKR2
25
Selects Function GP1[15]
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_BA[0]
2h
Selects Function LCD_D[4]
8h
9h-Fh
(2)
Reserved
EMA_BA[0]/LCD_D[4]/GP1[14] Control
3h-7h
(1)
Reserved
1h
9h-Fh
R8
Selects Function GP2[0]
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] Control
8h
PINMUX17_19_16
Reserved
0
5h-7h
19-16
Reserved
Pin is 3-stated.
9h-Fh
R12
Selects Function GP2[1]
EMA_SDCKE/GP2[0] Control
8h
PINMUX17_23_20
Reserved
0
2h-7h
23-20
Description
Reserved
Selects Function GP1[14]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued)
Bit
15-12
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX17_15_12
P8
26
Value
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] Control
0
Pin is 3-stated.
1h
Selects Function EMA_BA[1]
2h
Selects Function LCD_D[5]
3h
Reserved
4h
Selects Function UHPI_HHWIL
5h-7h
8h
9h-Fh
11-8
PINMUX17_11_8
N11
42
Pin is 3-stated.
Selects Function EMA_A[12]
2h
Selects Function LCD_MCLK
41
Pin is 3-stated.
Selects Function EMA_A[11]
2h
Selects Function LCD_AC_ENB_CS
27
Reserved
Selects Function GP1[11]
Reserved
EMA_A[10]/LCD_VSYNC/GP1[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[10]
2h
Selects Function LCD_VSYNC
3h-7h
8h
9h-Fh
222
Reserved
0
9h-Fh
N8
Selects Function GP1[12]
1h
8h
PINMUX17_3_0
Reserved
EMA_A[11]/LCD_AC_ENB_CS/GP1[11] Control
3h-7h
3-0
Reserved
0
8h
P11
Selects Function GP1[13]
1h
9h-Fh
PINMUX17_7_4
Reserved
EMA_A[12]/LCD_MCLK/GP1[12] Control
3h-7h
7-4
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP1[10]
Reserved
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10.5.10.19 Pin Multiplexing Control 18 Register (PINMUX18)
Figure 10-36. Pin Multiplexing Control 18 Register (PINMUX18)
31
28
27
24
23
20
19
16
PINMUX18_31_28
PINMUX18_27_24
PINMUX18_23_20
PINMUX18_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX18_15_12
PINMUX18_11_8
PINMUX18_7_4
PINMUX18_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
Bit
31-28
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX18_31_28
M14
—
Value
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] Control
0
Pin is 3-stated.
1h
Selects Function EMA_WE_DQM[0]
2h
Selects Function UHPI_HINT
3h
Reserved
4h
Selects Function AXR0[15]
5h-7h
8h
9h-Fh
27-24
PINMUX18_27_24
P12
—
Pin is 3-stated.
Selects Function EMA_WE_DQM[1]
2h
Selects Function UHPI_HDS2
3h
Reserved
4h
Selects Function AXR0[14]
22
Selects Function GP2[8]
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_OE
2h
Selects Function UHPI_HDS1
3h
Reserved
4h
Selects Function AXR0[13]
8h
9h-Fh
(2)
Reserved
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] Control
5h-7h
(1)
Reserved
1h
8h
R7
Selects Function GP2[9]
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] Control
9h-Fh
PINMUX18_23_20
Reserved
0
5h-7h
23-20
Description
Reserved
Selects Function GP2[7]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued)
Bit
19-16
Field
ZKB
Ball (1)
PTP
Pin (2)
PINMUX18_19_16
T7
21
Value
EMA_CS[3]/AMUTE2/GP2[6] Control
0
Pin is 3-stated.
1h
Selects Function EMA_CS[3]
2h-3h
4h
5h-7h
8h
9h-Fh
15-12
PINMUX18_15_12
P7
23
Selects Function EMA_CS[2]
Selects Function UHPI_HCS
—
1h
Selects Function EMA_CS[0]
2h
Selects Function UHPI_HAS
55
Selects Function GP2[4]
Reserved
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] Control
Pin is 3-stated.
1h
Selects Function EMA_WE
2h
Selects Function UHPI_HRW
3h
Reserved
4h
Selects Function AXR0[12]
—
Reserved
Selects Function GP2[3]
Reserved
EMA_RAS/EMA_CS[5]/GP2[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_RAS
2h
Selects Function EMA_CS[5]
3h-7h
8h
9h-Fh
224
Reserved
0
9h-Fh
N7
Reserved
Pin is 3-stated.
8h
PINMUX18_3_0
Selects Function GP2[5]
EMA_CS[0]/UHPI_HAS/GP2[4] Control
5h-7h
3-0
Reserved
0
8h
M13
Reserved
2h
9h-Fh
PINMUX18_7_4
Selects Function GP2[6]
1h
3h-7h
7-4
Reserved
Pin is 3-stated.
9h-Fh
T8
Selects Function AMUTE2
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] Control
8h
PINMUX18_11_8
Reserved
0
3h-7h
11-8
Description
System Configuration (SYSCFG) Module
Reserved
Selects Function GP2[2]
Reserved
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10.5.10.20 Pin Multiplexing Control 19 Register (PINMUX19)
Figure 10-37. Pin Multiplexing Control 19 Register (PINMUX19)
31
16
Reserved
R/W-0
15
4
3
0
Reserved
PINMUX19_3_0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
Field
ZKB
Ball (1)
PTP
Pin (2)
31-4
Reserved
—
—
3-0
PINMUX19_3_0
N6
19
Bit
Value
0
EMA_WAIT[0]/UHPI_HRDY/GP2[10] Control
Pin is 3-stated.
1h
Selects Function EMA_WAIT[0]
2h
Selects Function UHPI_HRDY
8h
9h-Fh
(2)
Reserved
0
3h-7h
(1)
Description
Reserved
Selects Function GP2[10]
Reserved
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
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10.5.11 Suspend Source Register (SUSPSRC)
The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals
that support emulation suspend. A value of 1 (default) for a SUSPSRC bit corresponding to the peripheral,
indicates that the DSP emulator controls the peripheral's emulation suspend signal. You should maintain
this register with its default values.
The SUSPSRC is shown in Figure 10-38 and described in Table 10-42.
Figure 10-38. Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
Reserved
Reserved
Reserved
TIMER64_1SRC
TIMER64_0SRC
Reserved
EPWM2SRC
EPWM1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
23
22
21
20
19
18
17
16
EPWM0SRC
SPI1SRC
SPI0SRC
UART2SRC
UART1SRC
UART0SRC
I2C1SRC
I2C0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
HPISRC (1)
Reserved
Reserved
USB0SRC
Reserved
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
Reserved
PRUSRC
EMACSRC
EQEP1SRC
EQEP0SRC
ECAP2SRC
ECAP1SRC
ECAP0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions
Bit
31-29
28
27
Field
Reserved
Reserved
EPWM2SRC
22
21
226
Description
Reserved. Write the default value to all bits when modifying this register.
Timer1 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64_0SRC
25
23
1
TIMER64_1SRC
26
24
Value
Timer0 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
EPWM2 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EPWM1SRC
EPWM1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EPWM0SRC
EPWM0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
SPI1SRC
SPI1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
SPI0SRC
SPI0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
Field
20
UART2SRC
19
18
17
16
11-10
Reserved
9
USB0SRC
8-7
Reserved
6
PRUSRC
2
1
0
DSP is the source of the emulation suspend.
UART1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
UART0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
I2C1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
I2C0SRC
HPISRC
3
No emulation suspend.
1
I2C1SRC
Reserved
4
0
UART0SRC
12
Description
UART2 Emulation Suspend Source.
UART1SRC
15-13
5
Value
I2C0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
HPI Emulation Suspend Source. This peripheral is not supported on the C6745 DSP.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
USB0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
PRU Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EMACSRC
EMAC Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EQEP1SRC
EQEP1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EQEP0SRC
EQEP0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP2SRC
ECAP2 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP1SRC
ECAP1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP0SRC
ECAP0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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10.5.12 Chip Signal Register (CHIPSIG)
The interrupts to the DSP can be generated by setting one of the two CHIPSIG[3-2] bits or an NMI
interrupt by setting the CHIPSIG[4] bit in the chip signal register (CHIPSIG). Writing a 1 to these bits sets
the interrupts, writing a 0 has no effect. Reads return the value of these bits and can also be used as
status bits. The CHIPSIG is shown in Figure 10-39 and described in Table 10-43.
Figure 10-39. Chip Signal Register (CHIPSIG)
31
16
Reserved
R-0
15
4
3
2
Reserved
5
CHIPSIG4
CHIPSIG3
CHIPSIG2
Reserved
1
0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-43. Chip Signal Register (CHIPSIG) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1-0
228
Value
0
Reserved
Asserts DSP NMI interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG3
Asserts SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG2
Reserved
Description
Asserts SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Asserts interrupt
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.13 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 10-40 and described in Table 10-44.
For more information on DSP interrupts, see the DSP Subsystem chapter.
Figure 10-40. Chip Signal Clear Register (CHIPSIG_CLR)
31
16
Reserved
R-0
15
4
3
2
Reserved
5
CHIPSIG4
CHIPSIG3
CHIPSIG2
Reserved
1
0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1-0
Value
0
Reserved
Clears DSP NMI interrupt.
0
No effect
1
Clears interrupt
CHIPSIG3
Clears SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG2
Reserved
Description
Clears SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Clears interrupt
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.14 Chip Configuration 0 Register (CFGCHIP0)
The chip configuration 0 register (CFGCHIP0) controls the following functions:
• PLL Controller memory-mapped register lock: Used to lock out writes to the PLL controller memorymapped registers (MMRs) to prevent any erroneous writes in software to the PLL controller register
space.
• EDMA3 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP0
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3 transfers. Additionally, it also facilitates
preemption at a system level, as all transfer requests are internally broken down by the transfer
controller up to DBS size byte chunks and on a system level, each master’s priority (configured by the
MSTPRI register) is evaluated at burst size boundaries. The DBS value can significantly impact the
standalone throughput performance depending on the source and destination (bus
width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size configuration
should be carefully analyzed to meet the system’s throughput/performance requirements.
The CFGCHIP0 is shown in Figure 10-41 and described in Table 10-45.
Figure 10-41. Chip Configuration 0 Register (CFGCHIP0)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PLL_MASTER_LOCK
TC1DBS
TC0DBS
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
Bit
31-5
4
3-2
1-0
230
Field
Reserved
Value
0
PLL_MASTER_LOCK
Description
Reserved
PLL MMRs lock.
0
PLLC MMRs are freely accessible.
1
All PLLC MMRs are locked.
TC1DBS
TC1 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
TC0DBS
TC0 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
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10.5.15 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• eCAP0/1/2 event input source: Allows using McASP TX/RX events or various EMAC TX/RX threshold,
pulse, or miscellaneous interrupt events as eCAP event input sources.
• HPI Control: Allows HPIEN bit control that determines whether or not the HPI module has control over
the HPI pins (multiplexed with other peripheral pins). It also provides configurability to select whether
the host address is a word address or a byte address mode.
• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
• McASP AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP AMUTEIN signal. CFGCHIP1 provides this signal source control for all McASPs
on the device.
The CFGCHIP1 is shown in Figure 10-42 and described in Table 10-46.
Figure 10-42. Chip Configuration 1 Register (CFGCHIP1)
31
27
15
26
22
21
17
16
CAP2SRC
CAP1SRC
CAP0SRC
HPIBYTEAD (1)
R/W-0
R/W-0
R/W-0
R/W-0
14
13
12
11
8
HPIENA(1)
Reserved
TBCLKSYNC
AMUTESEL2(1)
R/W-0
R-0
R/W-0
R/W-0
7
4
3
0
AMUTESEL1
AMUTESEL0(1)
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
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Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
Bit
31-27
Field
Value
CAP2SRC
Selects the eCAP2 module event input.
0
eCAP2 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h
McASP1 TX DMA Event
4h
McASP1 RX DMA Event
5h
McASP2 TX DMA Event. This peripheral is not supported on the C6745 DSP.
6h
McASP2 RX DMA Event. This peripheral is not supported on the C6745 DSP.
7h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
26-22
CAP1SRC
Reserved
Selects the eCAP1 module event input.
0
eCAP1 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h
McASP1 TX DMA Event
4h
McASP1 RX DMA Event
5h
McASP2 TX DMA Event. This peripheral is not supported on the C6745 DSP.
6h
McASP2 RX DMA Event. This peripheral is not supported on the C6745 DSP.
7h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
232
Description
Reserved
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Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued)
Bit
21-17
Field
Value
CAP0SRC
Selects the eCAP0 module event input.
0
eCAP0 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h
McASP1 TX DMA Event
4h
McASP1 RX DMA Event
5h
McASP2 TX DMA Event. This peripheral is not supported on the C6745 DSP.
6h
McASP2 RX DMA Event. This peripheral is not supported on the C6745 DSP.
7h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
16
15
14-13
12
11-8
HPIBYTEAD
Reserved
HPI Byte/Word Address Mode select. This peripheral is not supported on the C6745 DSP.
0
Host address is a word address.
1
Host address is a byte address.
HPIENA
Reserved
Description
HPI Enable Bit. This peripheral is not supported on the C6745 DSP.
0
HPI is disabled.
1
HPI is enabled.
0
Reserved. Always read as 0.
TBCLKSYNC
eHRPWM Module Time Base Clock (TBCLK) Synchronization. Allows you to globally
synchronize all enabled eHRPWM modules to the time base clock (TBCLK).
0
Time base clock (TBCLK) within each enabled eHRPWM module is stopped.
1
All enabled eHRPWM module clocks are started with the first rising edge of TBCLK aligned. For
perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each eHRPWM
module must be set identically.
AMUTESEL2
Selects the source of McASP2 AMUTEIN signal. This peripheral is not supported on the
C6745 DSP.
0
Drive McASP2 AMUTEIN signal low
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
Reserved
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Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued)
Bit
Field
7-4
AMUTESEL1
Value
Selects the source of McASP1 AMUTEIN signal.
0
Drive McASP1 AMUTEIN signal low
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
3-0
AMUTESEL0
Reserved
Selects the source of McASP0 AMUTEIN signal. The AMUTE0 signal is not supported on the
C6745 DSP.
0
Drive McASP0 AMUTEIN signal low
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
234
Description
Reserved
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10.5.16 Chip Configuration 2 Register (CFGCHIP2)
The chip configuration 2 register (CFGCHIP2) controls the following functions:
• USB1.1 OHCI (this peripheral is not supported on the C6745 DSP.)
• USB2.0 OTG PHY
The CFGCHIP2 is shown in Figure 10-43 and described in Table 10-47.
Figure 10-43. Chip Configuration 2 Register (CFGCHIP2)
31
24
Reserved
R-0
23
18
15
14
17
16
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
R-0
R-0
R-0
12
11
10
9
8
RESET
USB0OTGMODE
13
USB1PHYCLKMUX (1)
USB0PHYCLKMUX
USB0PHYPWDN
USB0OTGPWRDN
USB0DATPOL
R/W-1
R/W-3h
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
3
7
6
5
4
USB1SUSPENDM(1)
USB0PHY_PLLON
USB0SESNDEN
USB0VBDTCTEN
USB0REF_FREQ
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
Bit
31-18
17
16
15
14-13
12
11
Field
Reserved
Value
0
USB0PHYCLKGD
Description
Reserved
Status of USB2.0 PHY.
0
Clock is not present, power is not good, and PLL has not locked.
1
Clock is present, power is good, and PLL has locked.
USB0VBUSSENSE
Status of USB2.0 PHY VBUS sense.
0
PHY is not sensing voltage presence on the VBUS pin.
1
PHY is sensing voltage presence on the VBUS pin.
RESET
USB2.0 PHY reset.
0
Not in reset
1
USB2.0 PHY in reset
USB0OTGMODE
USB2.0 OTG subsystem mode.
0
No override. PHY drive signals to controller based on its comparators for VBUS and ID pins.
1h
Override phy values to force USB host operation.
2h
Override phy values to force USB device operation.
3h
Override phy values to force USB host operation with VBUS low.
USB1PHYCLKMUX
USB1.1 PHY reference clock input mux. Controls clock mux to USB1.1. This peripheral is
not supported on the C6745 DSP.
0
USB1.1 PHY reference clock is sourced by output of USB2.0 PHY.
1
USB1.1 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
USB0PHYCLKMUX
USB2.0 PHY reference clock input mux.
0
USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
1
USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL.
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Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions (continued)
Bit
Field
10
USB0PHYPWDN
9
8
7
6
5
4
3-0
Value
USB2.0 PHY operation state control.
0
USB2.0 PHY is enabled and is in operating state (normal operation).
1
USB2.0 PHY is disabled and powered down.
USB0OTGPWRDN
USB2.0 OTG subsystem (SS) operation state control.
0
OTG SS is enabled and is in operating state (normal operation).
1
OTG SS is disabled and is powered down.
USB0DATPOL
USB2.0 differential data lines polarity selector.
0
Differential data polarities are inverted (USB_DP is connected to D- and USB_DM is
connected to D+).
1
Differential data polarity are not altered (USB_DP is connected to D+ and USB_DM is
connected to D-).
USB1SUSPENDM
USB1.1 suspend mode. This peripheral is not supported on the C6745 DSP.
0
Needs to be 0 whenever USB1.1 PHY is unpowered
1
Enable USB1.1 PHY
USB0PHY_PLLON
Drives USB2.0 PHY, allowing or preventing it from stopping the 48 MHz clock during
USB SUSPEND.
0
USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND.
1
USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND
USB0SESNDEN
USB2.0 Session End comparator enable.
0
Session End comparator is disabled.
1
Session End comparator is enabled.
USB0VBDTCTEN
USB2.0 VBUS line comparators enable.
0
All VBUS line comparators are disabled.
1
All VBUS line comparators are enabled.
USB0REF_FREQ
USB2.0 PHY reference clock input frequencies.
0
Reserved
1h
12 MHz
2h
24 MHz
3h
48 MHz
4h
19.2 MHz
5h
38.4 MHz
6h
13 MHz
7h
26 MHz
8h
20 MHz
9h
40 MHz
Ah-Fh
236
Description
Reserved
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10.5.17 Chip Configuration 3 Register (CFGCHIP3)
The CFGCHIP3 register controls the following peripheral/module functions:
• DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.5) hardware clock divider is provided to generate
133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this
clock divider.
• EMIFA Module Clock Source Control: Allows control for the source for the EMIFA module clock.
• EMIFB Memory Clock Source Control: Allows control for the source for the EMIFB SDRAM memory
clock.
The CFGCHIP3 is shown in Figure 10-44 and described in Table 10-48.
Figure 10-44. Chip Configuration 3 Register (CFGCHIP3)
31
16
Reserved
R-0
15
2
1
0
Reserved
8
7
Reserved
3
DIV4P5ENA
EMA_CLKSRC
EMB_CLKSRC
R/W-FFh
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-8
Reserved
FFh
7-3
Reserved
0
2
1
0
DIV4P5ENA
Description
Reserved
Reserved. Write the default value when modifying this register.
Reserved. Write the default value to all bits when modifying this register.
Controls the fixed DIV4.5 divider in the PLL controller.
0
Divide by 4.5 is disabled.
1
Divide by 4.5 is enabled.
EMA_CLKSRC
Clock source for EMIFA clock domain.
0
Clock driven by PLLC SYSCLK3
1
Clock driven by DIV4.5 PLL output
EMB_CLKSRC
Clock source for EMIFB clock domain.
0
Clock driven by PLLC SYSCLK5
1
Clock driven by DIV4.5 PLL output
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10.5.18 Chip Configuration 4 Register (CFGCHIP4)
The CFGCHIP4 register is used for clearing the AMUNTEIN signal for the McASPs. Writing a 1 causes a
single pulse that clears the ‘latched’ GPIO interrupt for AMUTEIN of McASP if it was previously set. Reads
always return a value of 0. The register has individual bits for each McASP supported on the device. The
CFGCHIP4 is shown in Figure 10-45 and described in Table 10-49.
Figure 10-45. Chip Configuration 4 Register (CFGCHIP4)
31
16
Reserved
R-0
15
2
1
0
Reserved
8
7
Reserved
3
AMUTECLR2 (1)
AMUTECLR1
AMUTECLR0 (1)
R/W-FFh
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Table 10-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-8
Reserved
FFh
7-3
Reserved
0
2
1
0
238
AMUTECLR2
Description
Reserved
Reserved. Write the default value when modifying this register.
Reserved. Write the default value to all bits when modifying this register.
Clears the 'latched' GPIO interrupt for AMUTEIN of McASP2 when set to 1. This peripheral is
not supported on the C6745 DSP.
0
No effect
1
Clears interrupt
AMUTECLR1
Clears the 'latched' GPIO interrupt for AMUTEIN of McASP1 when set to 1.
0
No effect
1
Clears interrupt
AMUTECLR0
Clears the 'latched' GPIO interrupt for AMUTEIN of McASP0 when set to 1. The AMUTE0
signal is not supported on the C6745 DSP.
0
No effect
1
Clears interrupt
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Chapter 11
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Boot Considerations
Topic
11.1
...........................................................................................................................
Page
Introduction ..................................................................................................... 240
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11.1 Introduction
This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot
– NOR Legacy boot
– NOR AIS boot
• HPI Boot (this peripheral is not supported on the C6745 DSP.)
• I2C0/I2C1 Boot
– Master boot
– Slave boot
• SPI0/SPI1 Boot
– Master boot
– Slave boot
• UART0/1/2 Boot
See Using the C6747/45/43 Bootloader Application Report (SPRABB1) for more details on the ROM Boot
Loader, a list of boot pins used, and the complete list of supported boot modes.
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Chapter 12
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Programmable Real-Time Unit Subsystem (PRUSS)
Topic
...........................................................................................................................
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241
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The Programmable Real-Time Unit Subsystem (PRUSS) consists of:
• Two programmable real-time units (PRU0 and PRU1) and their associated memories.
• An interrupt controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The two PRUs
can also work in coordination with the device level host CPU. This is determined by the nature of the
program that is loaded into the two PRUs instruction memory. Several different signaling mechanisms are
available between the two PRUs and the device level host CPU.
The two PRUs are optimized for performing embedded tasks that require manipulation of packed memorymapped data structures, handling of system events that have tight real-time constraints and interfacing
with systems external to the device.
The PRUSS documentation (peripheral guide) is on the external wiki: Programmable_Realtime_Unit.
242
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Chapter 13
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Enhanced Capture (eCAP) Module
The enhanced capture (eCAP) module is essential in systems where accurate timing of external events is
important. This chapter describes the eCAP module.
Topic
13.1
13.2
13.3
13.4
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Applications ....................................................................................................
Registers .........................................................................................................
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244
245
254
270
243
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13.1 Introduction
13.1.1 Purpose of the Peripheral
Uses for eCAP include:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
13.1.2 Features
The eCAP module includes the following features:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event time-stamps
• Continuous mode capture of time-stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All above resources dedicated to a single input pin
• When not used in capture mode, the ECAP module can be configured as a single channel PWM output
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13.2 Architecture
The eCAP module represents one complete capture channel that can be instantiated multiple times
depending on the target device. In the context of this guide, one eCAP channel has the following
independent key resources:
• Dedicated input capture pin
• 32-bit time base counter
• 4 × 32-bit time-stamp capture registers (CAP1-CAP4)
• 4-stage sequencer (Modulo4 counter) that is synchronized to external events, ECAP pin rising/falling
edges.
• Independent edge polarity (rising/falling edge) selection for all 4 events
• Input capture signal prescaling (from 2-62)
• One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events
• Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme
• Interrupt capabilities on any of the 4 capture events
Multiple identical eCAP modules can be contained in a system as shown in Figure 13-1. The number of
modules is device-dependent and is based on target application needs. In this chapter, the letter x within a
signal or module name is used to indicate a generic eCAP instance on a device.
Figure 13-1. Multiple eCAP Modules
VBus32
From EPWM
SyncIn
ECAP1
module
ECAP1
ECAP1INT
SyncOut
SyncIn
Interrupt
Controller
ECAP2/
APWM2
module
ECAP2
GPIO
MUX
ECAP2INT
SyncOut
SyncIn
ECAPx/
APWMx
module
ECAPx
ECAPxINT
SyncOut
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13.2.1 Capture and APWM Operating Mode
You can use the eCAP module resources to implement a single-channel PWM generator (with 32 bit
capabilities) when it is not being used for input captures. The counter operates in count-up mode,
providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The CAP1 and CAP2
registers become the active period and compare registers, respectively, while CAP3 and CAP4 registers
become the period and capture shadow registers, respectively. Figure 13-2 is a high-level view of both the
capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 13-2. Capture and APWM Modes of Operation
SyncIn
Counter (”timer”)
Capture
mode
32
Note:
Same pin
depends on
operating
mode
CAP1 reg
CAP2 reg
CAP3 reg
Sequencing
Edge detection
Edge polarity
Prescale
ECAPx
pin
CAP4 reg
ECAPxINT
Interrupt I/F
Or
SyncIn
Counter (”timer”)
APWM
mode
32
Syncout
Period reg
(active) (”CAP1”)
Compare reg
(active) (”CAP2”)
Period reg
(shadow) (”CAP3”)
PWM
Compare logic
APWMx
pin
Compare reg
(shadow) (”CAP4”)
ECAPxINT
246
Interrupt I/F
(1)
A single pin is shared between CAP and APWM functions. In capture mode, it is an input; in APWM mode, it
is an output.
(2)
In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 invokes the shadow mode.
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13.2.2 Capture Mode Description
Figure 13-3 shows the various components that implement the capture function.
Figure 13-3. Capture Function Diagram
ECCTL2[SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
SYNC
CTRPHS
(phase register-32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
TSCTR
(counter-32 bit)
SYNCOut
PRD [0-31]
Delta-mode
RST
CTR [0-31]
PWM
compare
logic
CMP [0-31]
32
CTR=PRD
CTR [0-31]
CTR=CMP
32
PRD [0-31]
ECCTL1 [ CAPLDEN, CTRRSTx]
CAP1
(APRD active)
APRD
shadow
32
32
Polarity
select
LD2
Polarity
select
32
CMP [0-31]
32
CAP2
(ACMP active)
LD
32
32
LD1
LD
MODE SELECT
ECAPx
32
Event
qualifier
ACMP
shadow
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Event
Prescale
Polarity
select
LD3
LD4
ECCTL1[EVTPS]
Polarity
select
4
Capture events
Edge Polarity Select
ECCTL1[CAPxPOL]
4
CEVT[1:4]
to Interrupt
Controller
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
ECCTL2 [ RE-ARM, CONT/ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
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13.2.2.1 Event Prescaler
An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the
prescaler. This is useful when very high frequency signals are used as inputs. Figure 13-4 shows a
functional diagram and Figure 13-5 shows the operation of the prescale function.
Figure 13-4. Event Prescale Control
Event prescaler
0
PSout
1
By−pass
ECAPx pin
(from GPIO)
/n
5
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)
(1)
When a prescale value of 1 is chosen (ECCTL1[13:9] = 0000) the input capture signal by-passes the
prescale logic completely.
Figure 13-5. Prescale Function Waveforms
ECAPx
PSout
div 2
PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10
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13.2.2.2 Edge Polarity Select and Qualifier
• Four independent edge polarity (rising edge/falling edge) selection multiplexers are used, one for each
capture event.
• Each edge (up to 4) is event qualified by the Modulo4 sequencer.
• The edge event is gated to its respective CAPn register by the Mod4 counter. The CAPn register is
loaded on the falling edge.
13.2.2.3
•
•
•
Continuous/One-Shot Control
The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.
The continuous/one-shot block (Figure 13-6) controls the start/stop and reset (zero) functions of the Mod4
counter via a mono-shot type of action that can be triggered by the stop-value comparator and re-armed
via software control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both
the Mod4 counter and contents of CAP1-4 registers (time-stamps).
Re-arming prepares the eCAP module for another capture sequence. Also re-arming clears (to zero) the
Mod4 counter and permits loading of CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored,
and capture values continue to be written to CAP1-4 in a circular buffer sequence.
Figure 13-6. Continuous/One-shot Block Diagram
0 1 2 3
2:4 MUX
2
CEVT1
CEVT2
CEVT3
CEVT4
CLK
Modulo 4
counter Stop
RST
Mod_eq
One−shot
control logic
Stop value (2b)
ECCTL2[STOP_WRAP]
ECCTL2[RE−ARM]
ECCTL2[CONT/ONESHT]
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13.2.2.4 32-Bit Counter and Phase Control
This counter (Figure 13-7) provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.
Figure 13-7. Counter and Synchronization Block Diagram
SYNC
ECCTL2[SWSYNC]
ECCTL2[SYNCOSEL]
SYNCI
CTR=PRD
Disable
Disable
ECCTL2[SYNCI_EN]
SYNCO
Sync out
select
CTRPHS
LD_CTRPHS
Delta−mode
RST
TSCTR
(counter 32b)
SYSCLK
CLK
CTR−OVF
OVF
CTR[31−0]
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13.2.2.5 CAP1-CAP4 Registers
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a timestamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this
bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.
CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and
CAP2 during APWM operation.
13.2.2.6 Interrupt Control
An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events
(CTR = PRD, CTR = CMP). See Figure 13-8.
A counter overflow event (FFFF FFFFh->0000 0000h) is also provided as an interrupt source (CTROVF).
The capture events are edge and sequencer qualified (that is, ordered in time) by the polarity select and
Mod4 gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPn module) going to the
interrupt controller.
Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR = PRD, CTR = CMP) can be
generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated to the interrupt controller only if any of the
interrupt events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must
clear the global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR) before any
other interrupt pulses are generated. You can force an interrupt event via the interrupt force register
(ECFRC). This is useful for test purposes.
13.2.2.7 Shadow Load and Lockout Control
In capture mode, this logic inhibits (locks out) any shadow loading of CAP1 or CAP2 from APRD and
ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
• Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value.
• On period equal, CTR[31:0] = PRD[31:0]
NOTE: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode
(ECCTL2[CAP/APWM == 0]). The CTR = PRD, CTR = CMP flags are only valid in APWM
mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes.
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Figure 13-8. Interrupts in eCAP Module
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT1
ECFLG
Clear
ECCLR
ECFRC
Latch
ECFLG
ECEINT
ECCLR
Set
ECFLG
Clear
Clear
Latch
ECEINT
Generate
interrupt
pulse when
input=1
ECCLR
ECFRC
Latch
Set
ECAPxINT
CEVT2
1
Set
CEVT3
ECFLG
0
Clear
0
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT4
ECFLG
Clear
ECCLR
ECFRC
Latch
CTROVF
Set
ECEINT
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
PRDEQ
Set
ECFLG
Clear
Latch
ECEINT
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Set
ECCLR
ECFRC
CMPEQ
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13.2.2.8 APWM Mode Operation
Main operating highlights of the APWM section:
• The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
• When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
• Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers either immediately upon a write, or on a CTR = PRD
trigger.
• In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
• During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates,
during run-time, you only need to use the shadow registers.
Figure 13-9. PWM Waveform Details Of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
The behavior of APWM active-high mode (APWMPOL == 0) is:
CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle (<100% duty)
CMP = PERIOD+1, output high for complete period (100% duty)
CMP > PERIOD+1, output high for complete period
The behavior of APWM active-low mode (APWMPOL == 1) is:
CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle (<100% duty)
CMP = PERIOD+1, output low for complete period (100% duty)
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CMP > PERIOD+1, output low for complete period
13.3 Applications
The following sections will provide Applications examples and code snippets to show how to configure and
operate the eCAP module. For clarity and ease of use, below are useful #defines which will help in the
understanding of the examples.
254
// ECCTL1 ( ECAP Control Reg 1)
//==========================
// CAPxPOL bits
#define
EC_RISING
#define
EC_FALLING
0x0
0x1
// CTRRSTx bits
#define
EC_ABS_MODE
#define
EC_DELTA_MODE
0x0
0x1
// PRESCALE bits
#define
EC_BYPASS
#define
EC_DIV1
#define
EC_DIV2
#define
EC_DIV4
#define
EC_DIV6
#define
EC_DIV8
#define
EC_DIV10
0x0
0x0
0x1
0x2
0x3
0x4
0x5
// ECCTL2 ( ECAP Control Reg 2)
//==========================
// CONT/ONESHOT bit
#define
EC_CONTINUOUS
#define
EC_ONESHOT
0x0
0x1
// STOPVALUE bit
#define
EC_EVENT1
#define
EC_EVENT2
#define
EC_EVENT3
#define
EC_EVENT4
0x0
0x1
0x2
0x3
// RE-ARM bit
#define
EC_ARM
0x1
// TSCTRSTOP bit
#define
EC_FREEZE
#define
EC_RUN
0x0
0x1
// SYNCO_SEL bit
#define
EC_SYNCIN
#define
EC_CTR_PRD
#define
EC_SYNCO_DIS
0x0
0x1
0x2
// CAP/APWM mode bit
#define
EC_CAP_MODE
#define
EC_APWM_MODE
0x0
0x1
// APWMPOL bit
#define
EC_ACTV_HI
#define
EC_ACTV_LO
0x0
0x1
// Generic
#define
EC_DISABLE
#define
EC_ENABLE
#define
EC_FORCE
0x0
0x1
0x1
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13.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
Figure 13-10 shows an example of continuous capture operation (Mod4 counter wraps around). In this
figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this
gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the
next state. When the TSCTR reaches FFFF FFFFh (maximum value), it wraps around to 0000 0000h (not
shown in Figure 13-10), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
time-stamps are valid at the point indicated by the diagram, after the 4th event, hence event CEVT4 can
conveniently be used to trigger an interrupt and the CPU can read data from the CAPn registers.
Figure 13-10. Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
CEVT1
CEVT2
CEVT3
CEVT4
CEVT1
CAPx pin
t5
t4
FFFFFFFF
t3
t2
t1
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
0
1
2
XX
3
0
1
t5
t1
XX
t2
XX
CAP3
t3
XX
CAP4
t4
t
Polarity selection
Capture registers [1−4]
All capture values valid
(can be read) at this time
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Table 13-1. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_RISING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_RISING
ECCTL1
CTRRST1
EC_ABS_MODE
ECCTL1
CTRRST2
EC_ABS_MODE
ECCTL1
CTRRST3
EC_ABS_MODE
ECCTL1
CTRRST4
EC_ABS_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-1. Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising edge trigger
// Run Time ( e.g. CEVT4 triggered ISR call)
//==========================================
TSt1 = ECAPxRegs.CAP1;
// Fetch Time-Stamp
TSt2 = ECAPxRegs.CAP2;
// Fetch Time-Stamp
TSt3 = ECAPxRegs.CAP3;
// Fetch Time-Stamp
TSt4 = ECAPxRegs.CAP4;
// Fetch Time-Stamp
Period1 = TSt2-TSt1;
Period2 = TSt3-TSt2;
Period3 = TSt4-TSt3;
256
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captured
captured
captured
captured
at
at
at
at
t1
t2
t3
t4
// Calculate 1st period
// Calculate 2nd period
// Calculate 3rd period
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13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
In Figure 13-11 the eCAP operating mode is almost the same as in the previous section except capture
events are qualified as either rising or falling edge, this now gives both period and duty cycle information:
Period1 = t3 – t1, Period2 = t5 – t3, …etc. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x 100%, etc. Duty
Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, etc.
Figure 13-11. Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
CEVT2
CEVT4
CEVT1
CEVT2
CEVT3
CEVT1
CEVT4
CEVT1
CEVT3
CAPx pin
FFFFFFFF
t6
t5
CTR[0−31]
t3
t9
t8
t7
t4
t2
t1
00000000
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
0
1
2
XX
3
0
1
t1
XX
0
t6
t3
XX
3
t5
t2
XX
2
t7
t4
t8
tt
Polarity selection
Capture registers [1−4]
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Table 13-2. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_FALLING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_FALLING
ECCTL1
CTRRST1
EC_ABS_MODE
ECCTL1
CTRRST2
EC_ABS_MODE
ECCTL1
CTRRST3
EC_ABS_MODE
ECCTL1
CTRRST4
EC_ABS_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-2. Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising & Falling edge triggers
// Run Time ( e.g. CEVT4 triggered ISR call)
//==========================================
TSt1 = ECAPxRegs.CAP1;
// Fetch Time-Stamp
TSt2 = ECAPxRegs.CAP2;
// Fetch Time-Stamp
TSt3 = ECAPxRegs.CAP3;
// Fetch Time-Stamp
TSt4 = ECAPxRegs.CAP4;
// Fetch Time-Stamp
Period1 = TSt3-TSt1;
DutyOnTime1 = TSt2-TSt1;
DutyOffTime1 = TSt3-TSt2;
258
Enhanced Capture (eCAP) Module
captured
captured
captured
captured
at
at
at
at
t1
t2
t3
t4
// Calculate 1st period
// Calculate On time
// Calculate Off time
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13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
Figure 13-12 shows how the eCAP module can be used to collect Delta timing data from pulse train
waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4 counter
wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event. Here
Capture events are qualified as Rising edge only. On an event, TSCTR contents (time-stamp) is captured
first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If TSCTR
reaches FFFF FFFFh (maximum value), before the next event, it wraps around to 0000 0000h and
continues, a CNTOVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage
of Delta-time Mode is that the CAPn contents directly give timing data without the need for CPU
calculations: Period1 = T1, Period2 = T2,…etc. As shown in Figure 13-12, the CEVT1 event is a good
trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Figure 13-12. Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
CEVT1
CEVT3
CEVT2
CEVT4
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T2
T4
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
CAP3
0
1
2
XX
3
0
1
CTR value at CEVT1
t4
XX
t1
XX
t2
XX
CAP4
t3
t
Polarity selection
Capture registers [1−4]
All capture values valid
(can be read) at this time
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Table 13-3. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_RISING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_RISING
ECCTL1
CTRRST1
EC_DELTA_MODE
ECCTL1
CTRRST2
EC_DELTA_MODE
ECCTL1
CTRRST3
EC_DELTA_MODE
ECCTL1
CTRRST4
EC_DELTA_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-3. Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
// Code snippet for CAP mode Delta Time, Rising edge trigger
// Run Time ( e.g. CEVT1 triggered ISR call)
//==========================================
// Note: here Time-stamp directly represents the Period value.
Period4 = ECAPxRegs.CAP1;
// Fetch Time-Stamp captured at
Period1 = ECAPxRegs.CAP2;
// Fetch Time-Stamp captured at
Period2 = ECAPxRegs.CAP3;
// Fetch Time-Stamp captured at
Period3 = ECAPxRegs.CAP4;
// Fetch Time-Stamp captured at
260
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T1
T2
T3
T4
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13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
In Figure 13-13 the eCAP operating mode is almost the same as in previous section except Capture
events are qualified as either Rising or Falling edge, this now gives both Period and Duty cycle
information: Period1 = T1 + T2, Period2 = T3 + T4, …etc Duty Cycle1 (on-time %) = T1 / Period1 × 100%,
etc Duty Cycle1 (off-time %) = T2 / Period1 × 100%, etc
During initialization, you must write to the active registers for both period and compare. This will then
automatically copy the init values into the shadow values. For subsequent compare updates, that is,
during run-time, only the shadow registers must be used.
Figure 13-13. Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
CEVT2
CEVT4
CEVT1
CEVT2
CEVT3
CEVT4
CEVT5
CEVT3
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T5
T8
T2
T6
T4
T7
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
0
1
XX
2
3
0
1
2
t5
t1
XX
t2
XX
0
t4
CTR value at CEVT1
XX
3
t6
t3
t7
t
Polarity selection
Capture registers [1−4]
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Table 13-4. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_FALLING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_FALLING
ECCTL1
CTRRST1
EC_DELTA_MODE
ECCTL1
CTRRST2
EC_DELTA_MODE
ECCTL1
CTRRST3
EC_DELTA_MODE
ECCTL1
CTRRST4
EC_DELTA_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-4. Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
// Code snippet for CAP mode Delta Time, Rising and Falling edge triggers
// Run Time ( e.g. CEVT1 triggered ISR call)
//==========================================
// Note: here Time-stamp directly represents the Duty cycle values.
DutyOnTime1 = ECAPxRegs.CAP2;
// Fetch Time-Stamp captured at
DutyOffTime1 = ECAPxRegs.CAP3;
// Fetch Time-Stamp captured at
DutyOnTime2 = ECAPxRegs.CAP4;
// Fetch Time-Stamp captured at
DutyOffTime2 = ECAPxRegs.CAP1;
// Fetch Time-Stamp captured at
T2
T3
T4
T1
Period1 = DutyOnTime1 + DutyOffTime1;
Period2 = DutyOnTime2 + DutyOffTime2;
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13.3.5
13.3.5.1
Application of the APWM Mode
Simple PWM Generation (Independent Channel/s) Example
In this example, the eCAP module is configured to operate as a PWM generator. Here a very simple
single channel PWM waveform is generated from output pin APWMn. The PWM polarity is active high,
which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high
level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value
represents the off-time.
Figure 13-14. PWM Waveform Details of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
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Table 13-5. ECAP Initialization for APWM Mode
Register
Bit
Value
CAP1
CAP1
0x1000
CTRPHS
CTRPHS
0x0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-5. Code Snippet for APWM Mode
// Code snippet for APWM mode Example 1
// Run Time (Instant 1, e.g. ISR call)
//======================
ECAPxRegs.CAP2 = 0x300;
// Set Duty cycle i.e. compare value
// Run Time (Instant 2, e.g. another ISR call)
//======================
ECAPxRegs.CAP2 = 0x500;
// Set Duty cycle i.e. compare value
13.3.5.2
Multichannel PWM Generation with Synchronization Example
Figure 13-15 takes advantage of the synchronization feature between eCAP modules. Here 4 independent
PWM channels are required with different frequencies, but at integer multiples of each other to avoid
"beat" frequencies. Hence one eCAP module is configured as the Master and the remaining 3 are Slaves
all receiving their synch pulse (CTR = PRD) from the master. Note the Master is chosen to have the lower
frequency (F1 = 1/20,000) requirement. Here Slave2 Freq = 2 × F1, Slave3 Freq = 4 × F1 and Slave4
Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is
shown.
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Figure 13-15. Multichannel PWM Example Using 4 eCAP Modules
DC bus
Motor
dc
brush
APWM1
Motor
dc
brush
APWM2
Motor
dc
brush
APWM3
Motor
dc
brush
APWM4
TSCTR
FFFF FFFFh
Master APWM(1) module
20,000
APRD(1)
ACMP(1)
0000 0000
7,000
APWM1
(o/p pin)
CTR=PRD
(SyncOut)
Time
Phase = 0°
Slave APWM(2−4) module/s
10,000
APRD(2)
0
5,000
APRD(3)
0
4,000
APRD(4)
Time
0
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Table 13-6. ECAP1 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
20000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_CTR_PRD
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-7. ECAP2 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
10000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-8. ECAP3 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
5000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-9. ECAP4 Initialization for Multichannel PWM Generation with Synchronization
266
Register
Bit
Value
CAP1
CAP1
4000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
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Example 13-6. Code Snippet for Multichannel PWM Generation with Synchronization
// Code snippet for APWM mode Example 2
// Run Time (Note: Example execution of one run-time instant)
//============================================================
ECAP1Regs.CAP2 = 7000;
// Set Duty cycle i.e., compare value
ECAP2Regs.CAP2 = 2000;
// Set Duty cycle i.e., compare value
ECAP3Regs.CAP2 = 550;
// Set Duty cycle i.e., compare value
ECAP4Regs.CAP2 = 6500;
// Set Duty cycle i.e., compare value
13.3.5.3
=
=
=
=
7000
2000
550
6500
Multichannel PWM Generation with Phase Control Example
In Figure 13-16, the Phase control feature of the APWM mode is used to control a 3 phase Interleaved
DC/DC converter topology. This topology requires each phase to be off-set by 120° from each other.
Hence if “Leg” 1 (controlled by APWM1) is the reference Leg (or phase), that is, 0°, then Leg 2 need 120°
off-set and Leg 3 needs 240° off-set. The waveforms in Figure 13-16 show the timing relationship between
each of the phases (Legs). Note eCAP1 module is the Master and issues a sync out pulse to the slaves
(modules 2, 3) whenever TSCTR = Period value.
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Figure 13-16. Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules
Comple−
mentary
and
deadband
logic
Comple−
mentary
and
deadband
logic
Comple−
mentary
and
deadband
logic
APWM1
APWM2
APWM3
Vout
TSCTR
APRD(1)
APRD(1)
1200
700
SYNCO pulse
(CTR=PRD)
APWM1
Φ2=120°
CTRPHS(2)=800
APWM2
Φ3=240°
CTRPHS(3)=400
APWM3
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Table 13-10. ECAP1 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_CTR_PRD
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-11. ECAP2 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
800
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-12. ECAP3 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
400
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-7. Code Snippet for Multichannel PWM Generation with Phase Control
// Code snippet for APWM mode Example 3
// Run Time (Note: Example execution of one run-time instant)
//============================================================
// All phases are set to the same duty cycle
ECAP1Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
ECAP2Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
ECAP3Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
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13.4 Registers
Table 13-13 shows the eCAP module control and status register set. All 32-bit registers are aligned on
even address boundaries and are organized in little-endian mode. The 16 least-significant bits of a 32-bit
register are located on lowest address (even address).
NOTE:
In APWM mode, writing to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the
shadow registers CAP3/CAP4 invokes the shadow mode.
Table 13-13. Control and Status Register Set
Offset
Acronym
0h
TSCTR
4h
CTRPHS
Description
Size (×16)
Section
Time-Stamp Counter Register
2
Section 13.4.1
Counter Phase Offset Value Register
2
Section 13.4.2
8h
CAP1
Capture 1 Register
2
Section 13.4.3
Ch
CAP2
Capture 2 Register
2
Section 13.4.4
10h
CAP3
Capture 3 Register
2
Section 13.4.5
14h
CAP4
Capture 4 Register
2
Section 13.4.6
28h
ECCTL1
Capture Control Register 1
1
Section 13.4.7
2Ah
ECCTL2
Capture Control Register 2
1
Section 13.4.8
2Ch
ECEINT
Capture Interrupt Enable Register
1
Section 13.4.9
2Eh
ECFLG
Capture Interrupt Flag Register
1
Section 13.4.10
30h
ECCLR
Capture Interrupt Clear Register
1
Section 13.4.11
32h
ECFRC
Capture Interrupt Force Register
1
Section 13.4.12
5Ch
REVID
Revision ID Register
2
Section 13.4.13
13.4.1 Time-Stamp Counter Register (TSCTR)
The time-stamp counter register (TSCTR) is shown in Figure 13-17 and described in Table 13-14.
Figure 13-17. Time-Stamp Counter Register (TSCTR)
31
0
TSCTR
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-14. Time-Stamp Counter Register (TSCTR) Field Descriptions
Bit
31-0
270
Field
TSCTR
Value
0-FFFF FFFFh
Enhanced Capture (eCAP) Module
Description
Active 32-bit counter register that is used as the capture time-base
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13.4.2 Counter Phase Control Register (CTRPHS)
The counter phase control register (CTRPHS) is shown in Figure 13-18 and described in Table 13-15.
Figure 13-18. Counter Phase Control Register (CTRPHS)
31
0
CTRPHS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-15. Counter Phase Control Register (CTRPHS) Field Descriptions
Bit
31-0
Field
CTRPHS
Value
0-FFFF FFFFh
Description
Counter phase value register that can be programmed for phase lag/lead. This register
shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a
control bit. Used to achieve phase control synchronization with respect to other eCAP and
EPWM time-bases.
13.4.3 Capture 1 Register (CAP1)
The capture 1 register (CAP1) is shown in Figure 13-19 and described in Table 13-16.
Figure 13-19. Capture 1 Register (CAP1)
31
0
CAP1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-16. Capture 1 Register (CAP1) Field Descriptions
Bit
Field
Value
31-0
CAP1
0-FFFF FFFFh
Description
This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• APRD active register when used in APWM mode
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13.4.4 Capture 2 Register (CAP2)
The capture 2 register (CAP2) is shown in Figure 13-20 and described in Table 13-17.
Figure 13-20. Capture 2 Register (CAP2)
31
0
CAP2
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-17. Capture 2 Register (CAP2) Field Descriptions
Bit
Field
Value
31-0
CAP2
0-FFFF FFFFh
Description
This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• ACMP active register when used in APWM mode
13.4.5 Capture 3 Register (CAP3)
The capture 3 register (CAP3) is shown in Figure 13-21 and described in Table 13-18.
Figure 13-21. Capture 3 Register (CAP3)
31
0
CAP3
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-18. Capture 3 Register (CAP3) Field Descriptions
Bit
Field
Value
31-0
CAP3
0-FFFF FFFFh
272
Enhanced Capture (eCAP) Module
Description
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow
(APRD) register. You update the PWM period value through this register. In this mode, CAP3
shadows CAP1.
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13.4.6 Capture 4 Register (CAP4)
The capture 4 register (CAP4) is shown in Figure 13-22 and described in Table 13-19.
Figure 13-22. Capture 4 Register (CAP4)
31
0
CAP4
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-19. Capture 4 Register (CAP4) Field Descriptions
Bit
Field
Value
31-0
CAP4
0-FFFF FFFFh
Description
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare
shadow (ACMP) register. You update the PWM compare value through this register. In this
mode, CAP4 shadows CAP2.
13.4.7 ECAP Control Register 1 (ECCTL1)
The ECAP control register 1 (ECCTL1) is shown in Figure 13-23 and described in Table 13-20.
Figure 13-23. ECAP Control Register 1 (ECCTL1)
15
14
13
9
8
FREE/SOFT
PRESCALE
CAPLDEN
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CTRRST4
CAP4POL
CTRRST3
CAP3POL
CTRRST2
CAP2POL
CTRRST1
CAP1POL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-20. ECAP Control Register 1 (ECCTL1) Field Descriptions
Bit
15-14
13-9
Field
FREE/SOFT
PRESCALE
Value
0-3h
Description
Emulation Control
0
TSCTR counter stops immediately on emulation suspend
1h
TSCTR counter runs until = 0
2h-3h
TSCTR counter is unaffected by emulation suspend (Run Free)
0-1Fh
Event Filter prescale select
0
Divide by 1 (i.e,. no prescale, by-pass the prescaler)
1
Divide by 2
2h
Divide by 4
3h
Divide by 6
4h
Divide by 8
5h
Divide by 10
...
8
1Eh
Divide by 60
1Fh
Divide by 62
CAPLDEN
Enable Loading of CAP1-4 registers on a capture event
0
Disable CAP1-4 register loads at capture event time.
1
Enable CAP1-4 register loads at capture event time.
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Table 13-20. ECAP Control Register 1 (ECCTL1) Field Descriptions (continued)
Bit
7
6
5
4
3
2
1
0
274
Field
Value
CTRRST4
Description
Counter Reset on Capture Event 4
0
Do not reset counter on Capture Event 4 (absolute time stamp operation)
1
Reset counter after Capture Event 4 time-stamp has been captured
(used in difference mode operation)
CAP4POL
Capture Event 4 Polarity select
0
Capture Event 4 triggered on a rising edge (RE)
1
Capture Event 4 triggered on a falling edge (FE)
CTRRST3
Counter Reset on Capture Event 3
0
Do not reset counter on Capture Event 3 (absolute time stamp)
1
Reset counter after Event 3 time-stamp has been captured
(used in difference mode operation)
CAP3POL
Capture Event 3 Polarity select
0
Capture Event 3 triggered on a rising edge (RE)
1
Capture Event 3 triggered on a falling edge (FE)
CTRRST2
Counter Reset on Capture Event 2
0
Do not reset counter on Capture Event 2 (absolute time stamp)
1
Reset counter after Event 2 time-stamp has been captured
(used in difference mode operation)
CAP2POL
Capture Event 2 Polarity select
0
Capture Event 2 triggered on a rising edge (RE)
1
Capture Event 2 triggered on a falling edge (FE)
CTRRST1
Counter Reset on Capture Event 1
0
Do not reset counter on Capture Event 1 (absolute time stamp)
1
Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)
CAP1POL
Capture Event 1 Polarity select
0
Capture Event 1 triggered on a rising edge (RE)
1
Capture Event 1 triggered on a falling edge (FE)
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13.4.8 ECAP Control Register 2 (ECCTL2)
The ECAP control register 2 (ECCTL2) is shown in Figure 13-24 and described in Table 13-21.
Figure 13-24. ECAP Control Register 2 (ECCTL2)
15
11
7
10
9
8
Reserved
APWMPOL
CAP/APWM
SWSYNC
R-0
R/W-0
R/W-0
R/W-0
2
1
5
4
3
SYNCO_SEL
6
SYNCI_EN
TSCTRSTOP
RE-ARM
STOP_WRAP
CONT/ONESHT
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-21. ECAP Control Register 2 (ECCTL2) Field Descriptions
Bit
15-11
10
9
Field
Reserved
Value
0
APWMPOL
Description
Reserved
APWM output polarity select. This is applicable only in APWM operating mode
0
Output is active high (Compare value defines high time)
1
Output is active low (Compare value defines low time)
CAP/APWM
CAP/APWM operating mode select
0
ECAP module operates in capture mode. This mode forces the following configuration:
•
•
•
•
1
ECAP module operates in APWM mode. This mode forces the following configuration:
•
•
•
•
8
SWSYNC
Inhibits TSCTR resets via CTR = PRD event
Inhibits shadow loads on CAP1 and 2 registers
Permits user to enable CAP1-4 register load
ECAPn/APWMn pin operates as a capture input
Resets TSCTR on CTR = PRD event (period boundary
Permits shadow loading on CAP1 and 2 registers
Disables loading of time-stamps into CAP1-4 registers
ECAPn/APWMn pin operates as a APWM output
Software-forced Counter (TSCTR) Synchronizing. This provides a convenient software method to
synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via
the CTR = PRD event.
0
Writing a zero has no effect. Reading always returns a zero
1
Writing a one forces a TSCTR shadow load of current ECAP module and any ECAP modules
down-stream providing the SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a zero.
Note: Selection CTR = PRD is meaningful only in APWM mode; however, you can choose it in CAP
mode if you find doing so useful.
7-6
5
4
SYNCO_SEL
0-3h
Sync-Out Select
0
Select sync-in event to be the sync-out signal (pass through)
1h
Select CTR = PRD event to be the sync-out signal
2h
Disable sync out signal
3h
Disable sync out signal
SYNCI_EN
Counter (TSCTR) Sync-In select mode
0
Disable sync-in option
1
Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W
force event.
TSCTRSTOP
Time Stamp (TSCTR) Counter Stop (freeze) Control
0
TSCTR stopped
1
TSCTR free-running
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Table 13-21. ECAP Control Register 2 (ECCTL2) Field Descriptions (continued)
Bit
3
2-1
Field
Value
RE-ARM
STOP_WRAP
Description
One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one
shot or continuous mode.
0
Has no effect (reading always returns a 0)
1
Arms the one-shot sequence as follows:
1) Resets the Mod4 counter to zero
2) Unfreezes the Mod4 counter
3) Enables capture register loads
0-3h
Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur
before the CAP(1-4) registers are frozen, that is, capture sequence is stopped.
Wrap value for continuous mode. This is the number (between 1-4) of the capture register in which
the circular buffer wraps around and starts again.
0
Stop after Capture Event 1 in one-shot mode.
Wrap after Capture Event 1 in continuous mode.
1h
Stop after Capture Event 2 in one-shot mode.
Wrap after Capture Event 2 in continuous mode.
2h
Stop after Capture Event 3 in one-shot mode.
Wrap after Capture Event 3 in continuous mode.
3h
Stop after Capture Event 4 in one-shot mode.
Wrap after Capture Event 4 in continuous mode.
Notes: STOP_WRAP is compared to Mod4 counter and, when equal, 2 actions occur:
• Mod4 counter is stopped (frozen)
• Capture register loads are inhibited
In one-shot mode, further interrupt events are blocked until re-armed.
0
CONT/ONESHT
Continuous or one-shot mode control (applicable only in capture mode)
0
Operate in continuous mode
1
Operate in one-shot mode
13.4.9 ECAP Interrupt Enable Register (ECEINT)
The ECAP interrupt enable register (ECEINT) is shown in Figure 13-25 and described in Table 13-22.
The interrupt enable bits (CEVTn) block any of the selected events from generating an interrupt. Events
will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR
registers.
The proper procedure for configuring peripheral modes and interrupts is:
1. Disable global interrupts
2. Stop eCAP counter
3. Disable eCAP interrupts
4. Configure peripheral registers
5. Clear spurious eCAP interrupt flags
6. Enable eCAP interrupts
7. Start eCAP counter
8. Enable global interrupts
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Figure 13-25. ECAP Interrupt Enable Register (ECEINT)
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CEVT3
CEVT2
CETV1
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-22. ECAP Interrupt Enable Register (ECEINT) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
Value
0
Reserved
Counter Equal Compare Interrupt Enable
0
Disable Compare Equal as an Interrupt source
1
Enable Compare Equal as an Interrupt source
CTR=PRD
Counter Equal Period Interrupt Enable
0
Disable Period Equal as an Interrupt source
1
Enable Period Equal as an Interrupt source
CTROVF
Counter Overflow Interrupt Enable
0
Disable counter Overflow as an Interrupt source
1
Enable counter Overflow as an Interrupt source
CEVT4
Capture Event 4 Interrupt Enable
0
Disable Capture Event 4 as an Interrupt source
1
Enable Capture Event 4 as an Interrupt source
CEVT3
Capture Event 3 Interrupt Enable
0
Disable Capture Event 3 as an Interrupt source
1
Enable Capture Event 3 as an Interrupt source
CEVT2
Capture Event 2 Interrupt Enable
0
Disable Capture Event 2 as an Interrupt source
1
Enable Capture Event 2 as an Interrupt source
CEVT1
Reserved
Description
Capture Event 1 Interrupt Enable
0
Disable Capture Event 1 as an Interrupt source
1
Enable Capture Event 1 as an Interrupt source
0
Reserved
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13.4.10 ECAP Interrupt Flag Register (ECFLG)
The ECAP interrupt flag register (ECFLG) is shown in Figure 13-26 and described in Table 13-23.
Figure 13-26. ECAP Interrupt Flag Register (ECFLG)
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CETV3
CEVT2
CETV1
INT
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-23. ECAP Interrupt Flag Register (ECFLG) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
278
Value
0
Description
Reserved
Compare Equal Compare Status Flag. This flag is only active in APWM mode.
0
Indicates no event occurred
1
Indicates the counter (TSCTR) reached the compare register value (ACMP)
CTR=PRD
Counter Equal Period Status Flag. This flag is only active in APWM mode.
0
Indicates no event occurred
1
Indicates the counter (TSCTR) reached the period register value (APRD) and was reset.
CTROVF
Counter Overflow Status Flag. This flag is active in CAP and APWM mode.
0
Indicates no event occurred.
1
Indicates the counter (TSCTR) has made the transition from 0xFFFFFFFF to 0x00000000
CEVT4
Capture Event 4 Status Flag This flag is only active in CAP mode.
0
Indicates no event occurred
1
Indicates the fourth event occurred at ECAPn pin
CEVT3
Capture Event 3 Status Flag. This flag is active only in CAP mode.
0
Indicates no event occurred.
1
Indicates the third event occurred at ECAPn pin.
CEVT2
Capture Event 2 Status Flag. This flag is only active in CAP mode.
0
Indicates no event occurred.
1
Indicates the second event occurred at ECAPn pin.
CEVT1
Capture Event 1 Status Flag. This flag is only active in CAP mode.
0
Indicates no event occurred.
1
Indicates the first event occurred at ECAPn pin.
INT
Global Interrupt Status Flag
0
Indicates no interrupt generated.
1
Indicates that an interrupt was generated.
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13.4.11 ECAP Interrupt Clear Register (ECCLR)
The ECAP interrupt clear register (ECCLR) is shown in Figure 13-27 and described in Table 13-24.
Figure 13-27. ECAP Interrupt Clear Register (ECCLR)
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CETV3
CETV2
CETV1
INT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-24. ECAP Interrupt Clear Register (ECCLR) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
Value
0
Description
Reserved
Counter Equal Compare Status Flag
0
Writing a 0 has no effect. Always reads back a 0
1
Writing a 1 clears the CTR=CMP flag condition
CTR=PRD
Counter Equal Period Status Flag
0
Writing a 0 has no effect. Always reads back a 0
1
Writing a 1 clears the CTR=PRD flag condition
CTROVF
Counter Overflow Status Flag
0
Writing a 0 has no effect. Always reads back a 0
1
Writing a 1 clears the CTROVF flag condition
CEVT4
Capture Event 4 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the CEVT3 flag condition.
CEVT3
Capture Event 3 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the CEVT3 flag condition.
CEVT2
Capture Event 2 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
0
Writing a 1 clears the CEVT2 flag condition.
CEVT1
Capture Event 1 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the CEVT1 flag condition.
INT
Global Interrupt Clear Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are
set to 1.
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13.4.12 ECAP Interrupt Forcing Register (ECFRC)
The ECAP interrupt forcing register (ECFRC) is shown in Figure 13-28 and described in Table 13-25.
Figure 13-28. ECAP Interrupt Forcing Register (ECFRC)
15
14
13
12
11
10
9
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CETV3
CETV2
CETV1
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-25. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
280
Value
0
Reserved
Force Counter Equal Compare Interrupt
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CTR=CMP flag bit.
CTR=PRD
Force Counter Equal Period Interrupt
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CTR=PRD flag bit.
CTROVF
Force Counter Overflow
0
No effect. Always reads back a 0.
1
Writing a 1 to this bit sets the CTROVF flag bit.
CEVT4
Force Capture Event 4
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT4 flag bit
CEVT3
Force Capture Event 3
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT3 flag bit
CEVT2
Force Capture Event 2
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT2 flag bit.
CEVT1
Reserved
Description
Force Capture Event 1
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT1 flag bit.
0
Reserved
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13.4.13 Revision ID Register (REVID)
The revision ID register (REVID) is shown in Figure 13-29 and described in Table 13-26.
Figure 13-29. Revision ID Register (REVID)
31
0
REV
R-44D2 2100h
LEGEND: R = Read only; -n = value after reset
Table 13-26. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
Description
31-0
REV
44D2 2100h
Revision ID.
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Chapter 14
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Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM)
This chapter describes the enhanced high-resolution pulse-width modulator (eHRPWM).
Topic
14.1
14.2
14.3
14.4
282
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Applications to Power Topologies ......................................................................
Registers .........................................................................................................
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Page
283
288
347
371
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14.1 Introduction
14.1.1 Introduction
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
In this chapter, the letter x within a signal or module name is used to indicate a generic ePWM instance on
a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the ePWMx
instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and, likewise, EPWM4A and EPWM4B belong
to ePWM4.
14.1.2 Submodule Overview
The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA
and EPWMxB. Multiple ePWM modules are instanced within a device as shown in Figure 14-1. Each
ePWM instance is identical with one exception. Some instances include a hardware extension that allows
more precise control of the PWM outputs. This extension is the high-resolution pulse width modulator
(HRPWM) and is described in Section 14.2.10. See your device-specific data manual to determine which
ePWM instances include this feature. Each ePWM module is indicated by a numerical value starting with
1. For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx
indicates any instance.
The ePWM modules are chained together via a clock synchronization scheme that allows them to operate
as a single system when required. Additionally, this synchronization scheme can be extended to the
capture peripheral modules (eCAP). The number of modules is device-dependent and based on target
application needs. Modules can also operate stand-alone.
Each ePWM module supports the following features:
• Dedicated 16-bit time-base counter with period and frequency control
• Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations::
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
• Asynchronous override control of PWM signals through software.
• Programmable phase-control support for lag or lead operation relative to other ePWM modules.
• Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
• Dead-band generation with independent rising and falling edge delay control.
• Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
• A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
• Programmable event prescaling minimizes CPU overhead on interrupts.
• PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
Each ePWM module is connected to the input/output signals shown in Figure 14-1. The signals are
described in detail in subsequent sections.
The order in which the ePWM modules are connected may differ from what is shown in Figure 14-1. See
Section 14.2.3.3.2 for the synchronization scheme for a particular device. Each ePWM module consists of
seven submodules and is connected within a system via the signals shown in Figure 14-2.
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Figure 14-1. Multiple ePWM Modules
xSYNCI
SYNCI
EPWM1INT
EPWM1A
ePWM1 module
EPWM1B
TZ1 to TZn
SYNCO
xSYNCO
To eCAP1
SYNCI
EPWM2INT
Interrupt
Controller
EPWM2A
ePWM2 module
EPWM2B
GPIO
MUX
TZ1 to TZn
SYNCO
SYNCI
EPWMxINT
EPWMxA
ePWMx module
EPWMxB
TZ1 to TZn
SYNCO
Peripheral
Frame 1
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Figure 14-2. Submodules and Signal Connections for an ePWM Module
ePWM module
EPWMxSYNCI
EPWMxSYNCO
Time-base (TB) module
Counter-compare (CC) module
Interrupt
controller
EPWMxTZINT
EPWMxINT
Action-qualifier (AQ) module
Dead-band (DB) module
PWM-chopper (PC) module
TZ1 to TZn
EPWMxA
EPWMxB
GPIO
MUX
Event-trigger (ET) module
Trip-zone (TZ) module
Peripheral bus
Figure 14-3 shows more internal details of a single ePWM module. The main signals used by the ePWM
module are:
• PWM output signals (EPWMxA and EPWMxB). The PWM output signals are made available
external to the device through the GPIO peripheral described in the system control and interrupts guide
for your device.
• Trip-zone signals (TZ1 to TZn). These input signals alert the ePWM module of an external fault
condition. Each module on a device can be configured to either use or ignore any of the trip-zone
signals. The trip-zone signal can be configured as an asynchronous input through the GPIO peripheral.
See your device-specific data manual to determine how many trip-zone pins are available in the
device.
• Time-base synchronization input (EPWMxSYNCI) and output (EPWMxSYNCO) signals. The
synchronization signals daisy chain the ePWM modules together. Each module can be configured to
either use or ignore its synchronization input. The clock synchronization input and output signal are
brought out to pins only for ePWM1 (ePWM module #1). The synchronization output for ePWM1
(EPWM1SYNCO) is also connected to the SYNCI of the first enhanced capture module (eCAP1).
• Peripheral Bus. The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the
ePWM register file.
Figure 14-3 also shows the key internal submodule interconnect signals. Each submodule is described in
detail in Section 14.2.
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Figure 14-3. ePWM Submodules and Critical Internal Signal Interconnects
Time−base (TB)
Sync
in/out
select
Mux
CTR = 0
CTR = CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR = PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR = 0
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
CTR = PRD
CTR = 0
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
control
Counter compare (CC)
CTR = CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxA
CMPA shadow (24)
Dead
band
(DB)
CTR = CMPB
16
PWM
chopper
(PC)
EPWMB
EPWMxB
CMPB active (16)
EPWMxTZINT
CMPB shadow (16)
286
Trip
zone
(TZ)
CTR = 0
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TZ1 to TZn
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14.1.3 Register Mapping
Table 14-1 shows the complete ePWM module control and status register set grouped by submodule.
Each register set is duplicated for each instance of the ePWM module. The start address for each ePWM
register file instance on a device is specified in the appropriate data manual.
Table 14-1. ePWM Module Control and Status Registers Grouped by Submodule
Acronym
Offset (1)
Size
(×16)
Shadow Register Description
Time-Base Submodule Registers
TBCTL
0h
1
No
Time-Base Control Register
TBSTS
2h
1
No
Time-Base Status Register
TBPHSHR
4h
1
No
Extension for HRPWM Phase Register
TBPHS
6h
1
No
Time-Base Phase Register
TBCNT
8h
1
No
Time-Base Counter Register
TBPRD
Ah
1
Yes
Time-Base Period Register
(2)
Counter-Compare Submodule Registers
CMPCTL
Eh
1
No
Counter-Compare Control Register
CMPAHR
10h
1
No
Extension for HRPWM Counter-Compare A Register
CMPA
12h
1
Yes
Counter-Compare A Register
CMPB
14h
1
Yes
Counter-Compare B Register
(2)
Action-Qualifier Submodule Registers
AQCTLA
16h
1
No
Action-Qualifier Control Register for Output A (EPWMxA)
AQCTLB
18h
1
No
Action-Qualifier Control Register for Output B (EPWMxB)
AQSFRC
1Ah
1
No
Action-Qualifier Software Force Register
AQCSFRC
1Ch
1
Yes
Action-Qualifier Continuous S/W Force Register Set
Dead-Band Generator Submodule Registers
DBCTL
1Eh
1
No
Dead-Band Generator Control Register
DBRED
20h
1
No
Dead-Band Generator Rising Edge Delay Count Register
DBFED
22h
1
No
Dead-Band Generator Falling Edge Delay Count Register
No
PWM-Chopper Control Register
PWM-Chopper Submodule Registers
PCCTL
3Ch
1
Trip-Zone Submodule Registers
TZSEL
24h
1
No
Trip-Zone Select Register
TZCTL
28h
1
No
Trip-Zone Control Register
TZEINT
2Ah
1
No
Trip-Zone Enable Interrupt Register
TZFLG
2Ch
1
No
Trip-Zone Flag Register
TZCLR
2Eh
1
No
Trip-Zone Clear Register
TZFRC
30h
1
No
Trip-Zone Force Register
Event-Trigger Submodule Registers
ETSEL
32h
1
No
Event-Trigger Selection Register
ETPS
34h
1
No
Event-Trigger Pre-Scale Register
ETFLG
36h
1
No
Event-Trigger Flag Register
ETCLR
38h
1
No
Event-Trigger Clear Register
ETFRC
3Ah
1
No
Event-Trigger Force Register
High-Resolution PWM (HRPWM) Submodule Registers
HRCNFG
(1)
(2)
1040h
1
No
HRPWM Configuration Register
(2)
Locations not shown are reserved.
These registers are only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise,
these locations are reserved. See your device-specific data manual to determine which instances include the HRPWM.
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14.2 Architecture
Seven submodules are included in every ePWM peripheral. There are some instances that include a highresolution submodule that allows more precise control of the PWM outputs. Each of these submodules
performs specific tasks that can be configured by software.
14.2.1 Overview
Table 14-2 lists the eight key submodules together with a list of their main configuration parameters. For
example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the
counter-compare submodule in Section 14.2.4 for relevant details.
Table 14-2. Submodule Configuration Parameters
Submodule
Time-base (TB)
Configuration Parameter or Option
Reference
• Scale the time-base clock (TBCLK) relative to the system clock
(SYSCLKOUT).
• Configure the PWM time-base counter (TBCNT) frequency or period.
• Set the mode for the time-base counter:
•
•
•
•
•
–
count-up mode: used for asymmetric PWM
–
count-down mode: used for asymmetric PWM
Section 14.2.3
– count-up-and-down mode: used for symmetric PWM
Configure the time-base phase relative to another ePWM module.
Synchronize the time-base counter between modules through hardware
or software.
Configure the direction (up or down) of the time-base counter after a
synchronization event.
Configure how the time-base counter will behave when the device is
halted by an emulator.
Specify the source for the synchronization output of the ePWM module:
–
Synchronization input signal
–
Time-base counter equal to zero
–
Time-base counter equal to counter-compare B (CMPB)
–
No output synchronization signal generated.
Counter-compare (CC)
• Specify the PWM duty cycle for output EPWMxA and/or output EPWMxB
• Specify the time at which switching events occur on the EPWMxA or
EPWMxB output
Section 14.2.4
Action-qualifier (AQ)
• Specify the type of action taken when a time-base or counter-compare
submodule event occurs:
Section 14.2.5
–
No action taken
–
Output EPWMxA and/or EPWMxB switched high
–
Output EPWMxA and/or EPWMxB switched low
– Output EPWMxA and/or EPWMxB toggled
• Force the PWM output state through software control
• Configure and control the PWM dead-band through software
Dead-band (DB)
• Control of traditional complementary dead-band relationship between
upper and lower switches
• Specify the output rising-edge-delay value
• Specify the output falling-edge delay value
• Bypass the dead-band module entirely. In this case the PWM waveform
is passed through without modification.
Section 14.2.6
PWM-chopper (PC)
•
•
•
•
Section 14.2.7
Create a chopping (carrier) frequency.
Pulse width of the first pulse in the chopped pulse train.
Duty cycle of the second and subsequent pulses.
Bypass the PWM-chopper module entirely. In this case the PWM
waveform is passed through without modification.
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Table 14-2. Submodule Configuration Parameters (continued)
Submodule
Trip-zone (TZ)
Configuration Parameter or Option
• Configure the ePWM module to react to one, all, or none of the trip-zone
pins.
• Specify the tripping action taken when a fault occurs:
–
Force EPWMxA and/or EPWMxB high
–
Force EPWMxA and/or EPWMxB low
–
Force EPWMxA and/or EPWMxB to a high-impedance state
Reference
Section 14.2.8
– Configure EPWMxA and/or EPWMxB to ignore any trip condition.
• Configure how often the ePWM will react to each trip-zone pin:
–
One-shot
– Cycle-by-cycle
• Enable the trip-zone to initiate an interrupt.
• Bypass the trip-zone module entirely.
Event-trigger (ET)
• Enable the ePWM events that will trigger an interrupt.
• Specify the rate at which events cause triggers (every occurrence or
every second or third occurrence)
• Poll, set, or clear event flags
Section 14.2.9
High-Resolution PWM
(HRPWM)
• Enable extended time resolution capabilities
• Configure finer time granularity control or edge positioning
Section 14.2.10
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Code examples are provided in the remainder of this chapter that show how to implement various ePWM
module configurations. These examples use the constant definitions shown in Example 14-1.
Example 14-1. Constant Definitions Used in the Code Examples
// TBCTL (Time-Base Control)
// = = = = = = = = = = = = = = = = = =
// TBCNT MODE bit
#define
TB_COUNT_UP
0x0
#define
TB_COUNT_DOWN
0x1
#define
TB_COUNT_UPDOWN
0x2
#define
TB_FREEZE
0x3
// PHSEN bit
#define
TB_DISABLE
0x0
#define
TB_ENABLE
0x1
// PRDLD bit
#define
TB_SHADOW
0x0
#define
TB_IMMEDIATE
0x1
// SYNCOSEL bit
#define
TB_SYNC_IN
0x0
#define
TB_CTR_ZERO
0x1
#define
TB_CTR_CMPB
0x2
#define
TB_SYNC_DISABLE
0x3
// HSPCLKDIV and CLKDIV bits
#define
TB_DIV1
0x0
#define
TB_DIV2
0x1
#define
TB_DIV4
0x2
// PHSDIR bit
#define
TB_DOWN
0x0
#define
TB_UP
0x1
// CMPCTL (Compare Control)
// = = = = = = = = = = = = = = = = = =
// LOADAMODE and LOADBMODE bits
#define
CC_CTR_ZERO
0x0
#define
CC_CTR_PRD
0x1
#define
CC_CTR_ZERO_PRD
0x2
#define
CC_LD_DISABLE
0x3
// SHDWAMODE and SHDWBMODE bits
#define
CC_SHADOW
0x0
#define
CC_IMMEDIATE
0x1
// AQCTLA and AQCTLB (Action-qualifier
// = = = = = = = = = = = = = = = = = =
// ZRO, PRD, CAU, CAD, CBU, CBD bits
#define
AQ_NO_ACTION
0x0
#define
AQ_CLEAR
0x1
#define
AQ_SET
0x2
#define
AQ_TOGGLE
0x3
// DBCTL (Dead-Band Control)
// = = = = = = = = = = = = = = = = = =
// MODE bit
#define
DB_DISABLE
0x0
#define
DBA_ENABLE
0x1
#define
DBB_ENABLE
0x2
#define
DB_FULL_ENABLE
0x3
// POLSEL bit
#define
DB_ACTV_HI
0x0
#define
DB_ACTV_LOC
0x1
#define
DB_ACTV_HIC
0x2
#define
DB_ACTV_LO
0x3
// PCCTL (chopper control)
// = = = = = = = = = = = = = = = = = =
// CHPEN bit
#define
CHP_DISABLE
0x0
#define
CHP_ENABLE
0x1
290
= = = = = = = =
= = = = = = = =
Control)
= = = = = = = =
= = = = = = = =
= = = = = = = =
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Example 14-1. Constant Definitions Used in the Code Examples (continued)
// CHPFREQ bit
#define
CHP_DIV1
#define
CHP_DIV2
#define
CHP_DIV3
#define
CHP_DIV4
#define
CHP_DIV5
#define
CHP_DIV6
#define
CHP_DIV7
#define
CHP_DIV8
// CHPDUTY bit
#define
CHP1_8TH
#define
CHP2_8TH
#define
CHP3_8TH
#define
CHP4_8TH
#define
CHP5_8TH
#define
CHP6_8TH
#define
CHP7_8TH
// TZSEL (Trip-zone Select)
// = = = = = = = = = = = = = = =
// CBCn and OSHTn bits
#define
TZ_DISABLE
#define
TZ_ENABLE
// TZCTL (Trip-zone Control)
// = = = = = = = = = = = = = = =
// TZA and TZB bits
#define
TZ_HIZ
#define
TZ_FORCE_HI
#define
TZ_FORCE_LO
#define
TZ_NONE
// ETSEL (Event-trigger Select)
// = = = = = = = = = = = = = = =
// INTSEL bit
#define
ET_CTR_ZERO
#define
ET_CTR_PRD
#define
ET_CTRU_CMPA
#define
ET_CTRD_CMPA
#define
ET_CTRU_CMPB
#define
ET_CTRD_CMPB
// ETPS (Event-trigger Prescale)
// = = = = = = = = = = = = = = =
// INTPRD bit
#define
ET_DISABLE
#define
ET_1ST
#define
ET_2ND
#define
ET_3RD
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
= = = = = = = = = = =
0x0
0x1
= = = = = = = = = = =
0x0
0x1
0x2
0x3
= = = = = = = = = = =
0x1
0x2
0x4
0x5
0x6
0x7
= = = = = = = = = = =
0x0
0x1
0x2
0x3
14.2.2 Proper Interrupt Initialization Procedure
When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to
spurious events due to the ePWM registers not being properly initialized. The proper procedure for
initializing the ePWM peripheral is:
1. Disable global interrupts (CPU INTM flag)
2. Disable ePWM interrupts
3. Initialize peripheral registers
4. Clear any spurious ePWM flags
5. Enable ePWM interrupts
6. Enable global interrupts
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14.2.3 Time-Base (TB) Submodule
Each ePWM module has its own time-base submodule that determines all of the event timing for the
ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work
together as a single system. Figure 14-4 illustrates the time-base module's place within the ePWM.
Figure 14-4. Time-Base Submodule Block Diagram
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
CTR = 0
Interrupt
controller
(ET)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.3.1 Purpose of the Time-Base Submodule
You can configure the time-base submodule for the following:
• Specify the ePWM time-base counter (TBCNT) frequency or period to control how often events occur.
• Manage time-base synchronization with other ePWM modules.
• Maintain a phase relationship with other ePWM modules.
• Set the time-base counter to count-up, count-down, or count-up-and-down mode.
• Generate the following events:
– CTR = PRD: Time-base counter equal to the specified period (TBCNT = TBPRD) .
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h).
• Configure the rate of the time-base clock; a prescaled version of the CPU system clock
(SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate.
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14.2.3.2 Controlling and Monitoring the Time-Base Submodule
Table 14-3 lists the registers used to control and monitor the time-base submodule.
Table 14-3. Time-Base Submodule Registers
Acronym
Register Description
Address Offset
Shadowed
TBCTL
Time-Base Control Register
0h
No
TBSTS
Time-Base Status Register
2h
No
(1)
TBPHSHR
HRPWM extension Phase Register
4h
No
TBPHS
Time-Base Phase Register
6h
No
TBCNT
Time-Base Counter Register
8h
No
TBPRD
Time-Base Period Register
Ah
Yes
(1)
This register is available only on ePWM instances that include the high-resolution extension (HRPWM). On ePWM modules that
do not include the HRPWM, this location is reserved. See your device-specific data manual to determine which ePWM instances
include this feature.
Figure 14-5 shows the critical signals and registers of the time-base submodule. Table 14-4 provides
descriptions of the key signals associated with the time-base submodule.
Figure 14-5. Time-Base Submodule Signals and Registers
TBPRD
Period Shadow
TBCTL[PRDLD]
TBPRD
Period Active
TBCTL[SWFSYNC]
16
CTR = PRD
TBCNT
EPWMxSYNCI
16
CTR = 0
CTR_dir
CTR_max
TBCLK
Reset
Zero Counter
Mode
Dir UP/DOWN
Load
Max
clk
TBCNT
Counter Active Reg
TBCTL[CTRMODE]
CTR = 0
TBCTL[PHSEN] CTR = CMPB
Disable
X
Sync
Out
Select
EPWMxSYNCO
16
TBPHS
Phase Active Reg
SYSCLKOUT
Clock
Prescale
TBCTL[SYNCOSEL]
TBCLK
TBCTL[HSPCLKDIV]
TBCTL[CLKDIV]
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Table 14-4. Key Time-Base Signals
Signal
Description
EPWMxSYNCI
Time-base synchronization input.
Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the
synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM
module (EPWM1) this signal comes from a device pin. For subsequent ePWM modules this signal is passed
from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral,
EPWM3SYNCI is generated by ePWM2 and so forth. See Section 14.2.3.3.2 for information on the
synchronization order of a particular device.
EPWMxSYNCO
Time-base synchronization output.
This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain.
The ePWM module generates this signal from one of three event sources:
1.
2.
3.
CTR = PRD
EPWMxSYNCI (Synchronization input pulse)
CTR = 0: The time-base counter equal to zero (TBCNT = 0000h).
CTR = CMPB: The time-base counter equal to the counter-compare B (TBCNT = CMPB) register.
Time-base counter equal to the specified period.
This signal is generated whenever the counter value is equal to the active period register value. That is when
TBCNT = TBPRD.
CTR = 0
Time-base counter equal to zero.
This signal is generated whenever the counter value is zero. That is when TBCNT equals 0000h.
CTR = CMPB
Time-base counter equal to active counter-compare B register (TBCNT = CMPB).
This event is generated by the counter-compare submodule and used by the synchronization out logic.
CTR_dir
Time-base counter direction.
Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is
increasing and low when it is decreasing.
CTR_max
Time-base counter equal max value. (TBCNT = FFFFh)
Generated event when the TBCNT value reaches its maximum value. This signal is only used only as a status
bit.
TBCLK
Time-base clock.
This is a prescaled version of the system clock (SYSCLKOUT) and is used by all submodules within the
ePWM. This clock determines the rate at which time-base counter increments or decrements.
14.2.3.3 Calculating PWM Period and Frequency
The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the
time-base counter. Figure 14-6 shows the period (Tpwm) and frequency (Fpwm) relationships for the upcount, down-count, and up-down-count time-base counter modes when when the period is set to 4
(TBPRD = 4). The time increment for each step is defined by the time-base clock (TBCLK) which is a
prescaled version of the system clock (SYSCLKOUT).
The time-base counter has three modes of operation selected by the time-base control register (TBCTL):
• Up-Down-Count Mode: In up-down-count mode, the time-base counter starts from zero and
increments until the period (TBPRD) value is reached. When the period value is reached, the timebase counter then decrements until it reaches zero. At this point the counter repeats the pattern and
begins to increment.
• Up-Count Mode: In this mode, the time-base counter starts from zero and increments until it reaches
the value in the period register (TBPRD). When the period value is reached, the time-base counter
resets to zero and begins to increment once again.
• Down-Count Mode: In down-count mode, the time-base counter starts from the period (TBPRD) value
and decrements until it reaches zero. When it reaches zero, the time-base counter is reset to the
period value and it begins to decrement once again.
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Figure 14-6. Time-Base Frequency and Period
TPWM
4
PRD
4
4
3
3
2
3
2
1
2
1
0
Z 1
0
0
For Up Count and Down Count
TPWM
4
4
3
TPWM = (TBPRD + 1) x TTBCLK
FPWM = 1/ (TPWM)
PRD
4
3
2
3
2
1
2
1
0
1 Z
0
0
TPWM
TPWM
4
3
3
3
2
2
1
14.2.3.3.1
3
2
2
1
0
CTR_dir
1
1
0
Up
For Up and Down Count
TPWM = 2 x TBPRD x TTBCLK
FPWM = 1 / (TPWM)
4
Down
0
Up
Down
Time-Base Period Shadow Register
The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to
be synchronized with the hardware. The following definitions are used to describe all shadow registers in
the ePWM module:
• Active Register: The active register controls the hardware and is responsible for actions that the
hardware causes or invokes.
• Shadow Register: The shadow register buffers or provides a temporary holding location for the active
register. It has no direct effect on any control hardware. At a strategic point in time the shadow
register's content is transferred to the active register. This prevents corruption or spurious operation
due to the register being asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is
written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD
shadow register as follows:
•
•
Time-Base Period Shadow Mode: The TBPRD shadow register is enabled when TBCTL[PRDLD] =
0. Reads from and writes to the TBPRD memory address go to the shadow register. The shadow
register contents are transferred to the active register (TBPRD (Active) ← TBPRD (shadow)) when the
time-base counter equals zero (TBCNT = 0000h). By default the TBPRD shadow register is enabled.
Time-Base Period Immediate Load Mode: If immediate load mode is selected (TBCTL[PRDLD] = 1),
then a read from or a write to the TBPRD memory address goes directly to the active register.
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Time-Base Counter Synchronization
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM
module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The
input synchronization for the first instance (ePWM1) comes from an external pin. The possible
synchronization connections for the remaining ePWM modules is shown in Figure 14-7.
Figure 14-7. Time-Base Counter Synchronization Scheme 1
GPIO MUX
EPWM1SYNCI
ePWM1
EPWM1SYNCO
EPWM2SYNCI
ePWM2
EPWM2SYNCO
EPWM3SYNCI
ePWM3
EPWM3SYNCO
EPWMxSYNCI
ePWMx
EPWMxSYNCO
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Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN]
bit is set, then the time-base counter (TBCNT) of the ePWM module will be automatically loaded with the
phase register (TBPHS) contents when one of the following conditions occur:
• EPWMxSYNCI: Synchronization Input Pulse: The value of the phase register is loaded into the
counter register when an input synchronization pulse is detected (TBPHS → TBCNT). This operation
occurs on the next valid time-base clock (TBCLK) edge.
• Software Forced Synchronization Pulse: Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a
software forced synchronization. This pulse is ORed with the synchronization input signal, and
therefore has the same effect as a pulse on EPWMxSYNCI.
This feature enables the ePWM module to be automatically synchronized to the time base of another
ePWM module. Lead or lag phase control can be added to the waveforms generated by different ePWM
modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the direction of
the time-base counter immediately after a synchronization event. The new direction is independent of the
direction prior to the synchronization event. The TBPHS bit is ignored in count-up or count-down modes.
See Figure 14-8 through Figure 14-11 for examples.
Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse. The
synchronization pulse can still be allowed to flow-through to the EPWMxSYNCO and be used to
synchronize other ePWM modules. In this way, you can set up a master time-base (for example, ePWM1)
and downstream modules (ePWM2 - ePWMx) may elect to run in synchronization with the master.
14.2.3.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit in the chip configuration register 1 (CFGCHIP1) in the System Module can be used
to globally synchronize the time-base clocks of all enabled ePWM modules on a device. The TBCLKSYNC
bit is part of the chip configuration registers and is described in the device-specific data manual. When
TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped (default). When TBCLKSYNC = 1,
all ePWM time-base clocks are started with the rising edge of TBCLK aligned. For perfectly synchronized
TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The
proper procedure for enabling the ePWM clocks is as follows:
1. Enable the ePWM module clocks.
2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Set TBCLKSYNC = 1.
14.2.3.5 Time-Base Counter Modes and Timing Waveforms
The time-base counter operates in one of four modes:
• Up-count mode which is asymmetrical.
• Down-count mode which is asymmetrical.
• Up-down-count which is symmetrical.
• Frozen where the time-base counter is held constant at the current value.
To illustrate the operation of the first three modes, Figure 14-8 to Figure 14-11 show when events are
generated and how the time-base responds to an EPWMxSYNCI signal.
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Figure 14-8. Time-Base Up-Count Mode Waveforms
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR_dir
CTR = 0
CTR = PRD
CNT_max
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Figure 14-9. Time-Base Down-Count Mode Waveforms
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR_dir
CTR = 0
CTR = PRD
CNT_max
Figure 14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
UP
UP
UP
UP
CTR_dir
DOWN
DOWN
DOWN
CTR = 0
CTR = PRD
CNT_max
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Figure 14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
UP
UP
UP
CTR_dir
DOWN
DOWN
DOWN
CTR = 0
CTR = PRD
CNT_max
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14.2.4 Counter-Compare (CC) Submodule
Figure 14-12 illustrates the counter-compare submodule within the ePWM. Figure 14-13 shows the basic
structure of the counter-compare submodule.
Figure 14-12. Counter-Compare Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
MUX
EPWMxB
CTR = 0
TZ1 to TZn
EPWMxTZINT
Interrupt
controller
Figure 14-13. Counter-Compare Submodule Signals and Registers
Time
Base
(TB)
Module
TBCNT
CTR = CMPA
CMPA
CTR = PRD
CTR =0
16
Shadow
load
16
CMPA
Compare A Active Reg.
CMPA
Compare A Shadow Reg.
CMPCTL[LOADAMODE]
TBCNT
Digital
comparator A
CMPCTL
[SHDWAFULL]
CMPCTL
[SHDWAMODE]
Action
Qualifier
(AQ)
Module
16
CTR = CMPB
CMPB
CTR = PRD
CTR = 0
Shadow
load
16
Digital
comparator B
CMPB
Compare B Active Reg.
CMPB
Compare B Shadow Reg.
CMPCTL[SHDWBFULL]
CMPCTL[SHDWBMODE]
CMPCTL[LOADBMODE]
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14.2.4.1 Purpose of the Counter-Compare Submodule
The counter-compare submodule takes as input the time-base counter value. This value is continuously
compared to the counter-compare A (CMPA) and counter-compare B (CMPB) registers. When the timebase counter is equal to one of the compare registers, the counter-compare unit generates an appropriate
event.
The counter-compare submodule:
• Generates events based on programmable time stamps using the CMPA and CMPB registers
– CTR = CMPA: Time-base counter equals counter-compare A register (TBCNT = CMPA).
– CTR = CMPB: Time-base counter equals counter-compare B register (TBCNT = CMPB)
• Controls the PWM duty cycle if the action-qualifier submodule is configured appropriately
• Shadows new compare values to prevent corruption or glitches during the active PWM cycle
14.2.4.2 Controlling and Monitoring the Counter-Compare Submodule
Table 14-5 lists the registers used to control and monitor the counter-compare submodule. Table 14-6 lists
the key signals associated with the counter-compare submodule.
Table 14-5. Counter-Compare Submodule Registers
Acronym
Register Description
CMPCTL
Counter-Compare Control Register.
(1)
Address Offset
Shadowed
Eh
No
CMPAHR
HRPWM Counter-Compare A Extension Register
10h
Yes
CMPA
Counter-Compare A Register
12h
Yes
CMPB
Counter-Compare B Register
14h
Yes
(1)
This register is available only on ePWM modules with the high-resolution extension (HRPWM). On ePWM modules that do not
include the HRPWM, this location is reserved. Refer to the device-specific data manual to determine which ePWM instances
include this feature.
Table 14-6. Counter-Compare Submodule Key Signals
302
Signal
Description of Event
Registers Compared
CTR = CMPA
Time-base counter equal to the active counter-compare A value
TBCNT = CMPA
CTR = CMPB
Time-base counter equal to the active counter-compare B value
TBCNT = CMPB
CTR = PRD
Time-base counter equal to the active period.
TBCNT = TBPRD
Used to load active counter-compare A and B registers from the shadow register
CTR = 0
Time-base counter equal to zero.
TBCNT = 0000h
Used to load active counter-compare A and B registers from the shadow register
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14.2.4.3 Operational Highlights for the Counter-Compare Submodule
The counter-compare submodule is responsible for generating two independent compare events based on
two compare registers:
1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCNT = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCNT = CMPB).
For up-count or down-count mode, each event occurs only once per cycle. For up-down-count mode each
event occurs twice per cycle, if the compare value is between 0000h and TBPRD; and occurs once per
cycle, if the compare value is equal to 0000h or equal to TBPRD. These events are fed into the actionqualifier submodule where they are qualified by the counter direction and converted into actions if
enabled. Refer to Section 14.2.5.1 for more details.
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occurs at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. Which register is written to or read from is determined
by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the
CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:
•
•
Shadow Mode: The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE]
bit and the shadow register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow
mode is enabled by default for both CMPA and CMPB.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events:
– CTR = PRD: Time-base counter equal to the period (TBCNT = TBPRD).
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
– Both CTR = PRD and CTR = 0
Which of these three events is specified by the CMPCTL[LOADAMODE] and CMPCTL[LOADBMODE]
register bits. Only the active register contents are used by the counter-compare submodule to generate
events to be sent to the action-qualifier.
Immediate Load Mode: If immediate load mode is selected (TBCTL[SHADWAMODE] = 1 or
TBCTL[SHADWBMODE] = 1), then a read from or a write to the register will go directly to the active
register.
14.2.4.4 Count Mode Timing Waveforms
The counter-compare module can generate compare events in all three count modes:
• Up-count mode: used to generate an asymmetrical PWM waveform.
• Down-count mode: used to generate an asymmetrical PWM waveform.
• Up-down-count mode: used to generate a symmetrical PWM waveform.
To best illustrate the operation of the first three modes, the timing diagrams in Figure 14-14 to Figure 1417 show when events are generated and how the EPWMxSYNCI signal interacts.
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Figure 14-14. Counter-Compare Event Waveforms in Up-Count Mode
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
NOTE: An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCNT count
sequence. This can lead to a compare event being skipped. This skipping is considered normal operation and
must be taken into account.
Figure 14-15. Counter-Compare Events in Down-Count Mode
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
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Figure 14-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPB
CTR = CMPA
Figure 14-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPB
CTR = CMPA
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14.2.5 Action-Qualifier (AQ) Submodule
Figure 14-18 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. The
action-qualifier submodule has the most important role in waveform construction and PWM generation. It
decides which events are converted into various action types, thereby producing the required switched
waveforms at the EPWMxA and EPWMxB outputs.
Figure 14-18. Action-Qualifier Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
CTR = 0
Interrupt
controller
(ET)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.5.1 Purpose of the Action-Qualifier Submodule
The action-qualifier submodule is responsible for the following:
• Qualifying and generating actions (set, clear, toggle) based on the following events:
– CTR = PRD: Time-base counter equal to the period (TBCNT = TBPRD)
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
– CTR = CMPA: Time-base counter equal to the counter-compare A register (TBCNT = CMPA)
– CTR = CMPB: Time-base counter equal to the counter-compare B register (TBCNT = CMPB)
• Managing priority when these events occur concurrently
• Providing independent control of events when the time-base counter is increasing and when it is
decreasing.
14.2.5.2 Controlling and Monitoring the Action-Qualifier Submodule
Table 14-7 lists the registers used to control and monitor the action-qualifier submodule.
Table 14-7. Action-Qualifier Submodule Registers
306
Acronym
Register Description
AQCTLA
Action-Qualifier Control Register For Output A (EPWMxA)
Address Offset
Shadowed
16h
No
AQCTLB
AQSFRC
Action-Qualifier Control Register For Output B (EPWMxB)
18h
No
Action-Qualifier Software Force Register
1Ah
AQCSFRC
No
Action-Qualifier Continuous Software Force
1Ch
Yes
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The action-qualifier submodule is based on event-driven logic. It can be thought of as a programmable
cross switch with events at the input and actions at the output, all of which are software controlled via the
set of registers shown in Figure 14-19. The possible input events are summarized again in Table 14-8.
Figure 14-19. Action-Qualifier Submodule Inputs and Outputs
Action-qualifier (AQ) Module
TBCLK
AQCTLA[15:0]
Action-qualifier control A
EPWMA
CTR = PRD
AQCTLB[15:0]
Action-qualifier control B
CTR = 0
CTR = CMPA
AQSFRC[15:0]
Action-qualifier S/W force
CTR = CMPB
EPWMB
AQCSFRC[3:0] (shadow)
continuous S/W force
CTR_dir
AQCSFRC[3:0] (active)
continuous S/W force
Table 14-8. Action-Qualifier Submodule Possible Input Events
Signal
Description
Registers Compared
CTR = PRD
Time-base counter equal to the period value
TBCNT = TBPRD
CTR = 0
Time-base counter equal to zero
TBCNT = 0000h
CTR = CMPA
Time-base counter equal to the counter-compare A
TBCNT = CMPA
CTR = CMPB
Time-base counter equal to the counter-compare B
TBCNT = CMPB
Software forced event
Asynchronous event initiated by software
The software forced action is a useful asynchronous event. This control is handled by registers AQSFRC
and AQCSFRC.
The action-qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a
particular event occurs. The event inputs to the action-qualifier submodule are further qualified by the
counter direction (up or down). This allows for independent action on outputs on both the count-up and
count-down phases.
The possible actions imposed on outputs EPWMxA and EPWMxB are:
• Set High: Set output EPWMxA or EPWMxB to a high level.
• Clear Low: Set output EPWMxA or EPWMxB to a low level.
• Toggle: If EPWMxA or EPWMxB is currently pulled high, then pull the output low. If EPWMxA or
EPWMxB is currently pulled low, then pull the output high.
• Do Nothing: Keep outputs EPWMxA and EPWMxB at same level as currently set. Although the "Do
Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this
event can still trigger interrupts. See the event-trigger submodule description in Section 14.2.9 for
details.
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Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be
configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can
operate on output EPWMxA. All qualifier actions are configured via the control registers found at the end
of this section.
For clarity, the drawings in this chapter use a set of symbolic actions. These symbols are summarized in
Figure 14-20. Each symbol represents an action as a marker in time. Some actions are fixed in time (zero
and period) while the CMPA and CMPB actions are moveable and their time positions are programmed
via the counter-compare A and B registers, respectively. To turn off or disable an action, use the "Do
Nothing option"; it is the default at reset.
Figure 14-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
TB Counter equals:
Actions
S/W
force
Zero
Comp
A
Comp
B
Period
SW
Z
CA
CB
P
SW
Z
CA
CB
P
SW
Z
CA
CB
P
Do Nothing
Clear Low
Set High
SW
T
308
Z
T
CA
T
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CB
T
P
T
Toggle
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14.2.5.3 Action-Qualifier Event Priority
It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case
events are assigned a priority by the hardware. The general rule is events occurring later in time have a
higher priority and software forced events always have the highest priority. The event priority levels for updown-count mode are shown in Table 14-9. A priority level of 1 is the highest priority and level 7 is the
lowest. The priority changes slightly depending on the direction of TBCNT.
Table 14-9. Action-Qualifier Event Priority for Up-Down-Count Mode
Event if TBCNT is Incrementing
TBCNT = 0 up to TBCNT = TBPRD
Event if TBCNT is Decrementing
TBCNT = TBPRD down to TBCNT = 1
Software forced event
Software forced event
2
Counter equals CMPB on up-count (CBU)
Counter equals CMPB on down-count (CBD)
3
Counter equals CMPA on up-count (CAU)
Counter equals CMPA on down-count (CAD)
4
Counter equals zero
Priority Level
1 (Highest)
5
6 (Lowest)
(1)
Counter equals period (TBPRD)
Counter equals CMPB on down-count (CBD)
(1)
Counter equals CMPB on up-count (CBU)
(1)
Counter equals CMPA on down-count (CAD)
(1)
Counter equals CMPA on up-count (CBU)
(1)
To maintain symmetry for up-down-count mode, both up-events (CAU/CBU) and down-events (CAD/CBD) can be generated for
TBPRD. Otherwise, up-events can occur only when the counter is incrementing and down-events can occur only when the
counter is decrementing.
Table 14-10 shows the action-qualifier priority for up-count mode. In this case, the counter direction is
always defined as up and thus down-count events will never be taken.
Table 14-10. Action-Qualifier Event Priority for Up-Count Mode
Priority Level
Event
1 (Highest)
Software forced event
2
Counter equal to period (TBPRD)
3
Counter equal to CMPB on up-count (CBU)
4
Counter equal to CMPA on up-count (CAU)
5 (Lowest)
Counter equal to Zero
Table 14-11 shows the action-qualifier priority for down-count mode. In this case, the counter direction is
always defined as down and thus up-count events will never be taken.
Table 14-11. Action-Qualifier Event Priority for Down-Count Mode
Priority Level
Event
1 (Highest)
Software forced event
2
Counter equal to Zero
3
Counter equal to CMPB on down-count (CBD)
4
Counter equal to CMPA on down-count (CAD)
5 (Lowest)
Counter equal to period (TBPRD)
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It is possible to set the compare value greater than the period. In this case the action will take place as
shown in Table 14-12.
Table 14-12. Behavior if CMPA/CMPB is Greater than the Period
Counter Mode
Compare on Up-Count Event CAU/CBU
Compare on Down-Count Event CAU/CBU
Up-Count Mode
If CMPA/CMPB ≤ TBPRD period, then the event
occurs on a compare match (TBCNT = CMPA or
CMPB).
Never occurs.
If CMPA/CMPB > TBPRD, then the event will not
occur.
Down-Count Mode
Never occurs.
If CMPA/CMPB < TBPRD, the event will occur on a
compare match (TBCNT = CMPA or CMPB).
If CMPA/CMPB ≥ TBPRD, the event will occur on a
period match (TBCNT = TBPRD).
Up-Down-Count
Mode
If CMPA/CMPB < TBPRD and the counter is
incrementing, the event occurs on a compare match
(TBCNT = CMPA or CMPB).
If CMPA/CMPB < TBPRD and the counter is
decrementing, the event occurs on a compare match
(TBCNT = CMPA or CMPB).
If CMPA/CMPB is ≥ TBPRD, the event will occur on a If CMPA/CMPB ≥ TBPRD, the event occurs on a
period match (TBCNT = TBPRD).
period match (TBCNT = TBPRD).
14.2.5.4 Waveforms for Common Configurations
NOTE:
The waveforms in this chapter show the ePWMs behavior for a static compare register
value. In a running system, the active compare registers (CMPA and CMPB) are typically
updated from their respective shadow registers once every period. The user specifies when
the update will take place; either when the time-base counter reaches zero or when the timebase counter reaches period. There are some cases when the action based on the new
value can be delayed by one period or the action based on the old value can take effect for
an extra period. Some PWM configurations avoid this situation. These include, but are not
limited to, the following:
Use up-down-count mode to generate a symmetric PWM:
•
•
If you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or
equal to 1.
If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD - 1.
This means there will always be a pulse of at least one TBCLK cycle in a PWM
period which, when very short, tend to be ignored by the system.
Use up-down-count mode to generate an asymmetric PWM:
•
To achieve 50%-0% asymmetric PWM use the following configuration: Load
CMPA/CMPB on period and use the period action to clear the PWM and a
compare-up action to set the PWM. Modulate the compare value from 0 to
TBPRD to achieve 50%-0% PWM duty.
When using up-count mode to generate an asymmetric PWM:
•
310
To achieve 0-100% asymmetric PWM use the following configuration: Load
CMPA/CMPB on TBPRD. Use the Zero action to set the PWM and a compareup action to clear the PWM. Modulate the compare value from 0 to TBPRD+1 to
achieve 0-100% PWM duty.
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Figure 14-21 shows how a symmetric PWM waveform can be generated using the up-down-count mode
of the TBCNT. In this mode 0%-100% DC modulation is achieved by using equal compare matches on the
up count and down count portions of the waveform. In the example shown, CMPA is used to make the
comparison. When the counter is incrementing the CMPA match will pull the PWM output high. Likewise,
when the counter is decrementing the compare match will pull the PWM signal low. When CMPA = 0, the
PWM signal is low for the entire period giving the 0% duty waveform. When CMPA = TBPRD, the PWM
signal is high achieving 100% duty.
When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values
greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period
which, when very short, tend to be ignored by the system.
Figure 14-21. Up-Down-Count Mode Symmetrical Waveform
4
4
Mode: Up-Down Count
TBPRD = 4
CAU = SET, CAD = CLEAR
0% - 100% Duty
3
3
3
2
1
1
1
1
TBCNT
2
2
2
3
0
0
0
TBCTR Direction
DOWN
UP
UP
DOWN
Case 1:
CMPA = 4, 0% Duty
EPWMxA/EPWMxB
Case 2:
CMPA = 3, 25% Duty
EPWMxA/EPWMxB
Case 3:
CMPA = 2, 50% Duty
EPWMxA/EPWMxB
Case 3:
CMPA = 1, 75% Duty
EPWMxA/EPWMxB
Case 4:
CMPA = 0, 100% Duty
EPWMxA/EPWMxB
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The PWM waveforms in Figure 14-22 through Figure 14-27 show some common action-qualifier
configurations. Some conventions used in the figures are as follows:
• TBPRD, CMPA, and CMPB refer to the value written in their respective registers. The active register,
not the shadow register, is used by the hardware.
• CMPx, refers to either CMPA or CMPB.
• EPWMxA and EPWMxB refer to the output signals from ePWMx
• Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count
mode
• Sym = Symmetric, Asym = Asymmetric
Table 14-13 and Table 14-14 contains initialization and runtime register configurations for the waveforms
in Figure 14-22.
Figure 14-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High
TBCNT
TBPRD
(value)
Z
P
CB
CA
Z
P
CB
CA
Z
P
Z
P
CB
CA
Z
P
CB
CA
Z
P
EPWMxA
EPWMxB
(1)
PWM period = (TBPRD + 1 ) × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to
CMPA).
(3)
Duty modulation for EPWMxB is set by CMPB and is active high (that is, high time duty proportional to
CMPB).
(4)
The "Do Nothing" actions ( X ) are shown for completeness, but will not be shown on subsequent diagrams.
(5)
Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK
period. TBCNT wraps from period to 0000h.
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Table 14-13. EPWMx Initialization for Figure 14-22
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
350 (15Eh)
Compare A = 350 TBCLK counts
CMPB
CMPB
200 (C8h)
Compare B = 200 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
CAU
AQ_CLEAR
ZRO
AQ_SET
CBU
AQ_CLEAR
AQCTLA
AQCTLB
Table 14-14. EPWMx Run Time Changes for Figure 14-22
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-15 and Table 14-16 contains initialization and runtime register configurations for the waveforms
in Figure 14-23.
Figure 14-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low
TBCNT
TBPRD
(value)
P
CA
P
CA
P
EPWMxA
P
CB
CB
P
P
EPWMxB
(1)
PWM period = (TBPRD + 1 ) × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to
CMPA).
(3)
Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to
CMPB).
(4)
The Do Nothing actions ( X ) are shown for completeness here, but will not be shown on subsequent
diagrams.
(5)
Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK
period. TBCNT wraps from period to 0000h.
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Table 14-15. EPWMx Initialization for Figure 14-23
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
350 (15Eh)
Compare A = 350 TBCLK counts
CMPB
CMPB
200 (C8h)
Compare B = 200 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
PRD
AQ_CLEAR
CBU
AQ_SET
AQCTLA
AQCTLB
Table 14-16. EPWMx Run Time Changes for Figure 14-23
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-17 and Table 14-18 contains initialization and runtime register configurations for the waveforms
Figure 14-24. Use the code in Example 14-1 to define the headers.
Figure 14-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on
EPWMxA
TBCNT
TBPRD
(value)
CA
CB
CA
CB
EPWMxA
Z
T
Z
T
Z
T
EPWMxB
(1)
PWM frequency = 1/( (TBPRD + 1 ) × TTBCLK )
(2)
Pulse can be placed anywhere within the PWM cycle (0000h - TBPRD)
(3)
High time duty proportional to (CMPB - CMPA)
(4)
EPWMxB can be used to generate a 50% duty square wave with frequency = 1/2 × ((TBPRD + 1) × TBCLK)
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Table 14-17. EPWMx Initialization for Figure 14-24
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
200 (C8h)
Compare A = 200 TBCLK counts
CMPB
CMPB
400 (190h)
Compare B = 400 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CBU
AQ_CLEAR
ZRO
AQ_TOGGLE
AQCTLA
AQCTLB
Table 14-18. EPWMx Run Time Changes for Figure 14-24
Register
Bit
Value
Comments
CMPA
CMPA
EdgePosA
Adjust duty for output EPWM1A
CMPB
CMPB
EdgePosB
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Table 14-19 and Table 14-20 contains initialization and runtime register configurations for the waveforms
in Figure 14-25. Use the code in Example 14-1 to define the headers.
Figure 14-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Active Low
TBCNT
TBPRD
(value)
CA
CA
CA
CA
EPWMxA
CB
CB
CB
CB
EPWMxB
(1)
PWM period = 2 x TBPRD × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to
CMPA).
(3)
Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to
CMPB).
(4)
Outputs EPWMxA and EPWMxB can drive independent power switches
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Table 14-19. EPWMx Initialization for Figure 14-25
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
400 (190h)
Compare A = 400 TBCLK counts
CMPB
CMPB
500 (1F4h)
Compare B = 500 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CAD
AQ_CLEAR
CBU
AQ_SET
CBD
AQ_CLEAR
AQCTLA
AQCTLB
Table 14-20. EPWMx Run Time Changes for Figure 14-25
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-21 and Table 14-22 contains initialization and runtime register configurations for the waveforms
in Figure 14-26. Use the code in Example 14-1 to define the headers.
Figure 14-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Complementary
TBCNT
TBPRD
(value)
CA
CA
CA
CA
EPWMxA
CB
CB
CB
CB
EPWMxB
(1)
PWM period = 2 × TBPRD × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active low, i.e., low time duty proportional to CMPA
(3)
Duty modulation for EPWMxB is set by CMPB and is active high, i.e., high time duty proportional to CMPB
(4)
Outputs EPWMx can drive upper/lower (complementary) power switches
(5)
Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module
is also available if the more classical edge delay method is required.
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Table 14-21. EPWMx Initialization for Figure 14-26
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
350 (15Eh)
Compare A = 350 TBCLK counts
CMPB
CMPB
400 (190h)
Compare B = 400 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CAD
AQ_CLEAR
CBU
AQ_CLEAR
CBD
AQ_SET
AQCTLA
AQCTLB
Table 14-22. EPWMx Run Time Changes for Figure 14-26
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-23 and Table 14-24 contains initialization and runtime register configurations for the waveforms
in Figure 14-27. Use the code in Example 14-1 to define the headers.
Figure 14-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on
EPWMxA—Active Low
TBCNT
CA
CA
CB
CB
EPWMxA
Z
P
Z
P
EPWMxB
(1)
PWM period = 2 × TBPRD × TBCLK
(2)
Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse
placement techniques.
(3)
Duty modulation for EPWMxA is set by CMPA and CMPB.
(4)
Low time duty for EPWMxA is proportional to (CMPA + CMPB).
(5)
To change this example to active high, CMPA and CMPB actions need to be inverted (i.e., Set ! Clear and
Clear Set).
(6)
Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB)
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Table 14-23. EPWMx Initialization for Figure 14-27
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
250 (FAh)
Compare A = 250 TBCLK counts
CMPB
CMPB
450 (1C2h)
Compare B = 450 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CBD
AQ_CLEAR
ZRO
AQ_CLEAR
PRD
AQ_SET
AQCTLA
AQCTLB
Table 14-24. EPWMx Run Time Changes for Figure 14-27
Register
Bit
Value
Comments
CMPA
CMPA
EdgePosA
Adjust duty for output EPWM1A
CMPB
CMPB
EdgePosB
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14.2.6 Dead-Band Generator (DB) Submodule
Figure 14-28 illustrates the dead-band generator submodule within the ePWM module.
Figure 14-28. Dead-Band Generator Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
Action
Qualifier
(AQ)
CTR = PRD
Time-Base
(TB)
CTR_Dir
CTR = 0
Interrupt
controller
(ET)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.6.1 Purpose of the Dead-Band Submodule
The "Action-qualifier (AQ) Module" section discussed how it is possible to generate the required deadband by having full control over edge placement using both the CMPA and CMPB resources of the ePWM
module. However, if the more classical edge delay-based dead-band with polarity control is required, then
the dead-band generator submodule should be used.
The key functions of the dead-band generator submodule are:
• Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a
single EPWMxA input
• Programming signal pairs for:
– Active high (AH)
– Active low (AL)
– Active high complementary (AHC)
– Active low complementary (ALC)
• Adding programmable delay to rising edges (RED)
• Adding programmable delay to falling edges (FED)
• Can be totally bypassed from the signal path (note dotted lines in diagram)
14.2.6.2 Controlling and Monitoring the Dead-Band Submodule
The dead-band generator submodule operation is controlled and monitored via the following registers:
Table 14-25. Dead-Band Generator Submodule Registers
324
Acronym
Register Description
Address Offset
Shadowed
DBCTL
Dead-Band Control Register
1Eh
No
DBRED
Dead-Band Rising Edge Delay Count Register
20h
No
DBFED
Dead-Band Falling Edge Delay Count Register
22h
No
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14.2.6.3 Operational Highlights for the Dead-Band Generator Submodule
The following sections provide the operational highlights.
The dead-band submodule has two groups of independent selection options as shown in Figure 14-29.
• Input Source Selection: The input signals to the dead-band module are the EPWMxA and EPWMxB
output signals from the action-qualifier. In this section they will be referred to as EPWMxA In and
EPWMxB In. Using the DBCTL[IN_MODE) control bits, the signal source for each delay, falling-edge or
rising-edge, can be selected:
– EPWMxA In is the source for both falling-edge and rising-edge delay. This is the default mode.
– EPWMxA In is the source for falling-edge delay, EPWMxB In is the source for rising-edge delay.
– EPWMxA In is the source for rising edge delay, EPWMxB In is the source for falling-edge delay.
– EPWMxB In is the source for both falling-edge and rising-edge delay.
• Output Mode Control: The output mode is configured by way of the DBCTL[OUT_MODE] bits. These
bits determine if the falling-edge delay, rising-edge delay, neither, or both are applied to the input
signals.
• Polarity Control: The polarity control (DBCTL[POLSEL]) allows you to specify whether the rising-edge
delayed signal and/or the falling-edge delayed signal is to be inverted before being sent out of the
dead-band submodule.
Figure 14-29. Configuration Options for the Dead-Band Generator Submodule
EPWMxA in
0 S4
Rising edge
delay
In
0 S1
EPWMxA
RED
Out
1
1
1
0 S5
0 S2
(10-bit
counter)
Falling edge
delay
In
0 S3
(10-bit
counter)
DBCTL[IN_MODE]
1 S0
EPWMxB
Out
1
1
FED
DBCTL[POLSEL]
0
DBCTL[OUT_MODE]
EPWMxB in
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Although all combinations are supported, not all are typical usage modes. Table 14-26 lists some classical
dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such that
EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional modes
can be achieved by changing the input signal source. The modes shown in Table 14-26 fall into the
following categories:
• Mode 1: Bypass both falling-edge delay (FED) and rising-edge delay (RED) Allows you to fully
disable the dead-band submodule from the PWM signal path.
• Mode 2-5: Classical Dead-Band Polarity Settings These represent typical polarity configurations that
should address all the active high/low modes required by available industry power switch gate drivers.
The waveforms for these typical cases are shown in Figure 14-30. Note that to generate equivalent
waveforms to Figure 14-30, configure the action-qualifier submodule to generate the signal as shown
for EPWMxA.
• Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay Finally the last two
entries in Table 14-26 show combinations where either the falling-edge-delay (FED) or rising-edgedelay (RED) blocks are bypassed.
Table 14-26. Classical Dead-Band Operating Modes
DBCTL[POLSEL]
Mode
Mode Description
(1)
S3
DBCTL[OUT_MODE]
S2
S1
S0
1
EPWMxA and EPWMxB Passed Through (No Delay)
x
x
0
0
2
Active High Complementary (AHC)
1
0
1
1
3
Active Low Complementary (ALC)
0
1
1
1
4
Active High (AH)
0
0
1
1
5
Active Low (AL)
1
1
1
1
6
EPWMxA Out = EPWMxA In (No Delay)
0 or 1
0 or 1
0 or 1
0 or 1
EPWMxB Out = EPWMxA In with Falling Edge Delay
7
EPWMxA Out = EPWMxA In with Rising Edge Delay
0
1
1
0
EPWMxB Out = EPWMxB In with No Delay
(1)
326
These are classical dead-band modes and assume that DBCTL[IN_MODE] = 0,0. That is, EPWMxA in is the source for both the
falling-edge and rising-edge delays. Enhanced, non-traditional modes can be achieved by changing the IN_MODE configuration.
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Figure 14-30 shows waveforms for typical cases where 0% < duty < 100%.
Figure 14-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
Period
Original
(outA)
RED
Rising Edge
Delayed (RED)
FED
Falling Edge
Delayed (FED)
Active High
Complementary
(AHC)
Active Low
Complementary
(ALC)
Active High
(AH)
Active Low
(AL)
The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is
delayed by. For example, the formula to calculate falling-edge-delay and rising-edge-delay are:
FED = DBFED × TTBCLK
RED = DBRED × TTBCLK
Where TTBCLK is the period of TBCLK, the prescaled version of SYSCLKOUT.
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14.2.7 PWM-Chopper (PC) Submodule
Figure 14-31 illustrates the PWM-chopper (PC) submodule within the ePWM module. The PWM-chopper
submodule allows a high-frequency carrier signal to modulate the PWM waveform generated by the
action-qualifier and dead-band submodules. This capability is important if you need pulse transformerbased gate drivers to control the power switching elements.
Figure 14-31. PWM-Chopper Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
CTR = 0
Interrupt
controller
(ET)
CTR_Dir
EPWMxA
EPWMxB
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxA
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.7.1 Purpose of the PWM-Chopper Submodule
The key functions of the PWM-chopper submodule are:
• Programmable chopping (carrier) frequency
• Programmable pulse width of first pulse
• Programmable duty cycle of second and subsequent pulses
• Can be fully bypassed if not required
14.2.7.2 Controlling the PWM-Chopper Submodule
The PWM-chopper submodule operation is controlled via the register in Table 14-27.
Table 14-27. PWM-Chopper Submodule Registers
328
Acronym
Register Description
PCCTL
PWM-chopper Control Register
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Address Offset
Shadowed
3Ch
No
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14.2.7.3 Operational Highlights for the PWM-Chopper Submodule
Figure 14-32 shows the operational details of the PWM-chopper submodule. The carrier clock is derived
from SYSCLKOUT. Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in
the PCCTL register. The one-shot block is a feature that provides a high energy first pulse to ensure hard
and fast power switch turn on, while the subsequent pulses sustain pulses, ensuring the power switch
remains on. The one-shot width is programmed via the OSHTWTH bits. The PWM-chopper submodule
can be fully disabled (bypassed) via the CHPEN bit.
Figure 14-32. PWM-Chopper Submodule Signals and Registers
Bypass
0
EPWMxA
EPWMxA
Start
One
shot
OSHT
PWMA_ch
1
Clk
Pulse-width
SYSCLKOUT
/8
PCCTL
[OSHTWTH]
PCCTL
[OSHTWTH]
Pulse-width
Divider and
duty control
PCCTL
[CHPEN]
PSCLK
PCCTL[CHPFREQ]
PCCTL[CHPDUTY]
Clk
One
shot
EPWMxB
PWMB_ch
1
OSHT
EPWMxA
Start
Bypass
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14.2.7.4 Waveforms
Figure 14-33 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are
not shown. Details of the one-shot and duty-cycle control are discussed in the following sections.
Figure 14-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
EPWMxA
EPWMxB
PSCLK
EPWMxA
EPWMxB
14.2.7.4.1
One-Shot Pulse
The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or
period of the first pulse is given by:
T1stpulse = TSYSCLKOUT × 8 × OSHTWTH
Where TSYSCLKOUT is the period of the system clock (SYSCLKOUT) and OSHTWTH is the four control bits
(value from 1 to 16)
Figure 14-34 shows the first and subsequent sustaining pulses.
Figure 14-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and
Subsequent Sustaining Pulses
Start OSHT pulse
EPWMxA in
PSCLK
Prog. pulse width
(OSHTWTH)
OSHT
EPWMxA out
Sustaining pulses
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14.2.7.4.2
Duty Cycle Control
Pulse transformer-based gate drive designs need to comprehend the magnetic properties or
characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist
the gate drive designer, the duty cycles of the second and subsequent pulses have been made
programmable. These sustaining pulses ensure the correct drive strength and polarity is maintained on the
power switch gate during the on period, and hence a programmable duty cycle allows a design to be
tuned or optimized via software control.
Figure 14-35 shows the duty cycle control that is possible by programming the CHPDUTY bits. One of
seven possible duty ratios can be selected ranging from 12.5% to 87.5%.
Figure 14-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of
Sustaining Pulses
PSCLK
PSCLK
period
75%
50%
25%
62.5% 37.5%
87.5%
12.5%
PSCLK Period
Duty
1/8
Duty
2/8
Duty
3/8
Duty
4/8
Duty
5/8
Duty
6/8
Duty
7/8
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14.2.8 Trip-Zone (TZ) Submodule
Figure 14-36 shows how the trip-zone (TZ) submodule fits within the ePWM module. Each ePWM module
is connected to every TZ signal that are sourced from the GPIO MUX. These signals indicates external
fault or trip conditions, and the ePWM outputs can be programmed to respond accordingly when faults
occur. See your device-specific data manual to determine the number of trip-zone pins available for the
device.
Figure 14-36. Trip-Zone Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
CTR = 0
Interrupt
controller
(ET)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.8.1 Purpose of the Trip-Zone Submodule
The key functions of the trip-zone submodule are:
• Trip inputs TZ1 to TZn can be flexibly mapped to any ePWM module.
• Upon a fault condition, outputs EPWMxA and EPWMxB can be forced to one of the following:
– High
– Low
– High-impedance
– No action taken
• Support for one-shot trip (OSHT) for major short circuits or over-current conditions.
• Support for cycle-by-cycle tripping (CBC) for current limiting operation.
• Each trip-zone input pin can be allocated to either one-shot or cycle-by-cycle operation.
• Interrupt generation is possible on any trip-zone pin.
• Software-forced tripping is also supported.
• The trip-zone submodule can be fully bypassed if it is not required.
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14.2.8.2 Controlling and Monitoring the Trip-Zone Submodule
The trip-zone submodule operation is controlled and monitored through the following registers:
Table 14-28. Trip-Zone Submodule Registers
Acronym
Register Description
Address Offset
Shadowed
TZSEL
Trip-Zone Select Register
24h
No
TZCTL
Trip-Zone Control Register
28h
No
TZEINT
Trip-Zone Enable Interrupt Register
2Ah
No
TZFLG
Trip-Zone Flag Register
2Ch
No
TZCLR
Trip-Zone Clear Register
2Eh
No
TZFRC
Trip-Zone Force Register
30h
No
14.2.8.3 Operational Highlights for the Trip-Zone Submodule
The following sections describe the operational highlights and configuration options for the trip-zone
submodule.
The trip-zone signals at pin TZ1 to TZn is an active-low input signal. When the pin goes low, it indicates
that a trip event has occurred. Each ePWM module can be individually configured to ignore or use each of
the trip-zone pins. Which trip-zone pins are used by a particular ePWM module is determined by the
TZSEL register for that specific ePWM module. The trip-zone signal may or may not be synchronized to
the system clock (SYSCLKOUT). A minimum of 1 SYSCLKOUT low pulse on the TZ n inputs is sufficient
to trigger a fault condition in the ePWM module. The asynchronous trip makes sure that if clocks are
missing for any reason, the outputs can still be tripped by a valid event present on the TZn inputs.
The TZ n input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for a
ePWM module. The configuration is determined by the TZSEL[CBCn] and TZSEL[OSHTn] bits (where n
corresponds to the trip pin) respectively.
•
•
Cycle-by-Cycle (CBC): When a cycle-by-cycle trip event occurs, the action specified in the TZCTL
register is carried out immediately on the EPWMxA and/or EPWMxB output. Table 14-29 lists the
possible actions. In addition, the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a
EPWMxTZINT interrupt is generated if it is enabled in the TZEINT register.
The specified condition on the pins is automatically cleared when the ePWM time-base counter
reaches zero (TBCNT = 0000h) if the trip event is no longer present. Therefore, in this mode, the trip
event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually
cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the
TZFLG[CBC] bit is cleared, then it will again be immediately set.
One-Shot (OSHT): When a one-shot trip event occurs, the action specified in the TZCTL register is
carried out immediately on the EPWMxA and/or EPWMxB output. Table 14-29 lists the possible
actions. In addition, the one-shot trip event flag (TZFLG[OST]) is set and a EPWMxTZINT interrupt is
generated if it is enabled in the TZEINT register. The one-shot trip condition must be cleared manually
by writing to the TZCLR[OST] bit.
The action taken when a trip event occurs can be configured individually for each of the ePWM output
pins by way of the TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in
Table 14-29, can be taken on a trip event.
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Table 14-29. Possible Actions On a Trip Event
TZCTL[TZA]
and/or
TZCTL[TZB]
EPWMxA
and/or
EPWMxB
Comment
0
High-Impedance
Tripped
1h
Force to High State
Tripped
2h
Force to Low State
Tripped
3h
No Change
Do Nothing. No change is made to the output.
Example 14-2. Trip-Zone Configurations
Scenario A:
A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B
high.
• Configure the ePWM1 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ as a one-shot event source for ePWM2
– TZCTL[TZA] = 1: EPWM2A will be forced high on a trip event.
– TZCTL[TZB] = 1: EPWM2B will be forced high on a trip event.
Scenario B:
A cycle-by-cycle event on TZ5 pulls both EPWM1A, EPWM1B low.
A one-shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state.
• Configure the ePWM1 registers as follows:
– TZSEL[CBC5] = 1: enables TZ5 as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM2
– TZSEL[OSHT6] = 1: enables TZ6 as a one-shot event source for ePWM1
– TZCTL[TZA] = 0: EPWM1A will be put into a high-impedance state on a trip event.
– TZCTL[TZB] = 3: EPWM1B will ignore the trip event.
14.2.8.4 Generating Trip Event Interrupts
Figure 14-37 and Figure 14-38 illustrate the trip-zone submodule control and interrupt logic, respectively.
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Figure 14-37. Trip-Zone Submodule Mode Control Logic
TZCTL[TZB]
TZCTL[TZA]
EPWMxA
EPWMxB
Trip
logic
CTR = 0
Clear
Latch
cyc−by-cyc
mode
(CBC)
TZFRC[CBC]
Trip
EPWMxA
EPWMxB
CBC
trip event
Set
TZ1
Set
Sync
TZFLG[CBC]
TZn
TZCLR[CBC]
Clear
TZSEL[CBC1 to CBCn]
TZCLR[OST]
Clear
Latch
one-shot
mode
(OSHT)
Set
TZFRC[OSHT]
Trip
OSHT
trip event
TZ1
Sync
Async Trip
TZn
TZSEL[OSHT1 to OSHTn]
Set
TZFLG[OST]
Clear
Figure 14-38. Trip-Zone Submodule Interrupt Logic
TZFLG[INT]
TZCLR[INT]
TZFLG[CBC]
Clear
Clear
Latch
TZCLR[CBC]
Latch
Set
Set
TZEINT[CBC]
CBC
trip event
TZFLG[OST]
EPWMxTZINT
(Interrupt controller)
Generate
interrupt
pulse when
input=1
Clear
TZEINT[OST]
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TZCLR[OST]
Latch
Set
OSHT
trip event
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14.2.9 Event-Trigger (ET) Submodule
Figure 14-39 shows the event-trigger (ET) submodule in the ePWM system. The event-trigger submodule
manages the events generated by the time-base submodule and the counter-compare submodule to
generate an interrupt to the CPU.
Figure 14-39. Event-Trigger Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
CTR = 0
EPWMxINT
(ET)
CTR_Dir
EPWMxA
EPWMA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
CTR = CMPB
PWMchopper
(PC)
Trip
Zone
(TZ)
EPWMxB
EPWMB
CTR = 0
TZ1 to TZn
EPWMxTZINT
14.2.9.1 Purpose of the Event-Trigger Submodule
The key functions of the event-trigger submodule are:
• Receives event inputs generated by the time-base and counter-compare submodules
• Uses the time-base direction information for up/down event qualification
• Uses prescaling logic to issue interrupt requests at:
– Every event
– Every second event
– Every third event
• Provides full visibility of event generation via event counters and flags
14.2.9.2 Controlling and Monitoring the Event-Trigger Submodule
The key registers used to configure the event-trigger submodule are shown in Table 14-30:
Table 14-30. Event-Trigger Submodule Registers
336
Acronym
Register Description
Address Offset
Shadowed
ETSEL
Event-Trigger Selection Register
32h
No
ETPS
Event-Trigger Prescale Register
34h
No
ETFLG
Event-Trigger Flag Register
36h
No
ETCLR
Event-Trigger Clear Register
38h
No
ETFRC
Event-Trigger Force Register
3Ah
No
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14.2.9.3 Operational Overview of the Event-Trigger Submodule
The following sections describe the event-trigger submodule's operational highlights.
Each ePWM module has one interrupt request line connected to the interrupt controller as shown in
Figure 14-40.
Figure 14-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
EPWM1INT
EPWM1
module
EPWM2INT
EPWM2
module
Interrupt
controller
EPWMxINT
EPWMx
module
The event-trigger submodule monitors various event conditions (the left side inputs to event-trigger
submodule shown in Figure 14-41) and can be configured to prescale these events before issuing an
Interrupt request. The event-trigger prescaling logic can issue Interrupt requests at:
• Every event
• Every second event
• Every third event
Figure 14-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
clear
CTR = 0
Event Trigger
Module Logic
CTR = PRD
EPWMxINT
Interrupt
controller
count
CTRU=CMPA
CTR = CMPA
clear
ETSEL reg
CTRD=CMPA
Direction
qualifier
CTR = CMPB
/n
CTRU=CMPB
CTRD=CMPB
/n
ETPS reg
count
ETFLG reg
clear
ETCLR reg
CTR_dir
/n
ETFRC reg
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•
•
•
•
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ETSEL—This selects which of the possible events will trigger an interrupt.
ETPS—This programs the event prescaling options previously mentioned.
ETFLG—These are flag bits indicating status of the selected and prescaled events.
ETCLR—These bits allow you to clear the flag bits in the ETFLG register via software.
ETFRC—These bits allow software forcing of an event. Useful for debugging or software intervention.
A more detailed look at how the various register bits interact with the Interrupt is shown in Figure 14-42.
Figure 14-42 shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD])
bits specify the number of events required to cause an interrupt pulse to be generated. The choices
available are:
• Do not generate an interrupt
• Generate an interrupt on every event
• Generate an interrupt on every second event
• Generate an interrupt on every third event
An interrupt cannot be generated on every fourth or more events.
Which event can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) bits. The
event can be one of the following:
• Time-base counter equal to zero (TBCNT = 0000h).
• Time-base counter equal to period (TBCNT = TBPRD).
• Time-base counter equal to the compare A register (CMPA) when the timer is incrementing.
• Time-base counter equal to the compare A register (CMPA) when the timer is decrementing.
• Time-base counter equal to the compare B register (CMPB) when the timer is incrementing.
• Time-base counter equal to the compare B register (CMPB) when the timer is decrementing.
The number of events that have occurred can be read from the interrupt event counter (ETPS[INTCNT])
register bits. That is, when the specified event occurs the ETPS[INTCNT] bits are incremented until they
reach the value specified by ETPS[INTPRD]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops
counting and its output is set. The counter is only cleared when an interrupt is sent to the interrupt
controller.
When ETPS[INTCNT] reaches ETPS[INTPRD], one of the following behaviors will occur:
• If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an
interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is
cleared ETPS[INTCNT] = 0. The counter will begin counting events again.
• If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter
stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
• If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high
until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.
Writing to the INTPRD bits will automatically clear the counter INTCNT = 0 and the counter output will be
reset (so no interrupts are generated). Writing a 1 to the ETFRC[INT] bit will increment the event counter
INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the
counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored.
338
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Figure 14-42. Event-Trigger Interrupt Generator
ETCLR[INT]
Clear
Set
Latch
ETFLG[INT]
ETPS[INTCNT]
EPWMxINT
Generate
interrupt
pulse
when
input = 1
1
ETSEL[INTSEL]
0
Clear CNT
2-bit
Counter
0
ETFRC[INT]
Inc CNT
ETSEL[INT]
ETPS[INTPRD]
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000
001
010
011
100
101
101
111
0
CTR=0
CTR=PRD
0
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
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14.2.10 High-Resolution PWM (HRPWM) Submodule
Figure 14-43 shows the high-resolution PWM (HRPWM) submodule in the ePWM system. Some devices
include the high-resolution PWM submodule, see your device-specific data manual to determine which
ePWM instances include this feature.
Figure 14-43. HRPWM System Interface
Time−base (TB)
Sync
in/out
select
Mux
CTR = 0
CTR = CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR = PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR = 0
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
CTR = PRD
CTR = 0
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
control
Counter compare (CC)
CTR = CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxA
CMPA shadow (24)
Dead
band
(DB)
CTR = CMPB
16
PWM
chopper
(PC)
EPWMB
EPWMxB
CMPB active (16)
EPWMxTZINT
CMPB shadow (16)
340
Trip
zone
(TZ)
CTR = 0
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TZ1 to TZn
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14.2.10.1 Purpose of the High-Resolution PWM Submodule
The enhanced high-resolution pulse-width modulator (eHRPWM) extends the time resolution capabilities
of the conventionally derived digital pulse-width modulator (PWM). HRPWM is typically used when PWM
resolution falls below ~9-10 bits. The key features of HRPWM are:
• Extended time resolution capability
• Used in both duty cycle and phase-shift control methods
• Finer time granularity control or edge positioning using extensions to the Compare A and Phase
registers
• Implemented using the A signal path of PWM, that is, on the EPWMxA output. EPWMxB output has
conventional PWM capabilities
The ePWM peripheral is used to perform a function that is mathematically equivalent to a digital-to-analog
converter (DAC). As shown in Figure 14-44, the effective resolution for conventionally generated PWM is
a function of PWM frequency (or period) and system clock frequency.
Figure 14-44. Resolution Calculations for Conventionally Generated PWM
TPWM
PWM resolution (%) = FPWM/FSYSCLKOUT x 100%
PWM resolution (bits) = Log2 (FPWM/FSYSCLKOUT)
PWM
t
TSYSCLK
If the required PWM operating frequency does not offer sufficient resolution in PWM mode, you may want
to consider HRPWM. As an example of improved performance offered by HRPWM, Table 14-31 shows
resolution in bits for various PWM frequencies. Table 14-31 values assume a MEP step size of 180 ps.
See your device-specific data manual for typical and maximum performance specifications for the MEP.
Table 14-31. Resolution for PWM and HRPWM
Regular Resolution (PWM)
High Resolution (HRPWM)
PWM Frequency (kHz)
Bits
%
Bits
%
20
12.3
0.0
18.1
0.000
50
11.0
0.0
16.8
0.001
100
10.0
0.1
15.8
0.002
150
9.4
0.2
15.2
0.003
200
9.0
0.2
14.8
0.004
250
8.6
0.3
14.4
0.005
500
7.6
0.5
13.8
0.007
1000
6.6
1.0
12.4
0.018
1500
6.1
1.5
11.9
0.027
2000
5.6
2.0
11.4
0.036
Although each application may differ, typical low-frequency PWM operation (below 250 kHz) may not
require HRPWM. HRPWM capability is most useful for high-frequency PWM requirements of power
conversion topologies such as:
• Single-phase buck, boost, and flyback
• Multi-phase buck, boost, and flyback
• Phase-shifted full bridge
• Direct modulation of D-Class power amplifiers
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14.2.10.2 Architecture of the High-Resolution PWM Submodule
The HRPWM is based on micro edge positioner (MEP) technology. MEP logic is capable of positioning an
edge very finely by sub-dividing one coarse system clock of a conventional PWM generator. The time step
accuracy is on the order of 150 ps. The HRPWM also has a self-check software diagnostics mode to
check if the MEP logic is running optimally, under all operating conditions.
Figure 14-45 shows the relationship between one coarse system clock and edge position in terms of MEP
steps, which are controlled via an 8-bit field in the Compare A extension register (CMPAHR).
Figure 14-45. Operating Logic Using MEP
PWM period (N CPU cycles)
PWM duty
(0 to 1.0 in Q15 format)
MEP scale factor
Number of MEP steps
in one coarse step
Coarse step size
MEP step
Number of coarse steps = integer(PWMduty * PWMperiod)
Number of MEP steps
= fraction(PWMduty * PWMperiod) * (MEPScaleFactor)
16−bit CMPA register value
= number of coarse steps
16−bit CMPAHR register value = (number of MEP steps) << 8 + 0x180 (rounding) (A)
A
For MEP range and rounding adjustment.
To generate an HRPWM waveform, configure the TBM, CCM, and AQM registers as you would to
generate a conventional PWM of a given frequency and polarity. The HRPWM works together with the
TBM, CCM, and AQM registers to extend edge resolution, and should be configured accordingly. Although
many programming combinations are possible, only a few are needed and practical.
14.2.10.3 Controlling and Monitoring the High-Resolution PWM Submodule
The MEP of the HRPWM is controlled by two extension registers, each 8-bits wide. These two HRPWM
registers are concatenated with the 16-bit TBPHS and CMPA registers used to control PWM operation.
• TBPHSHR - Time-Base Phase High-Resolution Register
• CMPAHR - Counter-Compare A High-Resolution Register
Table 14-32 lists the registers used to control and monitor the high-resolution PWM submodule.
Table 14-32. HRPWM Submodule Registers
342
Acronym
Register Description
TBPHSHR
Extension Register for HRPWM Phase
CMPAHR
Extension Register for HRPWM Duty
HRCNFG
HRPWM Configuration Register
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Address Offset
Shadowed
4h
No
10h
Yes
1040h
No
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14.2.10.4 Configuring the High-Resolution PWM Submodule
Once the ePWM has been configured to provide conventional PWM of a given frequency and polarity, the
HRPWM is configured by programming the HRCNFG register located at offset address 1040h. This
register provides configuration options for the following key operating modes:
• Edge Mode: The MEP can be programmed to provide precise position control on the rising edge (RE),
falling edge (FE), or both edges (BE) at the same time. FE and RE are used for power topologies
requiring duty cycle control, while BE is used for topologies requiring phase shifting, for example,
phase shifted full bridge.
• Control Mode: The MEP is programmed to be controlled either from the CMPAHR register (duty cycle
control) or the TBPHSHR register (phase control). RE or FE control mode should be used with
CMPAHR register. BE control mode should be used with TBPHSHR register.
• Shadow Mode: This mode provides the same shadowing (double buffering) option as in regular PWM
mode. This option is valid only when operating from the CMPAHR register and should be chosen to be
the same as the regular load option for the CMPA register. If TBPHSHR is used, then this option has
no effect.
14.2.10.5 Operational Highlights for the High-Resolution PWM Submodule
The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps, each of which has
a time resolution on the order of 150 ps. The MEP works with the TBM and CCM registers to be certain
that time steps are optimally applied and that edge placement accuracy is maintained over a wide range of
PWM frequencies, system clock frequencies and other operating conditions. Table 14-33 shows the
typical range of operating frequencies supported by the HRPWM.
Table 14-33. Relationship Between MEP Steps, PWM Frequency and Resolution
System
(MHz)
(1)
(2)
(3)
(4)
(5)
MEP Steps Per
SYSCLKOUT (1) (2)
(3)
PWM Minimum
(Hz) (4)
PWM Maximum
(MHz)
Resolution at
Maximum
(Bits) (5)
50.0
111
763
2.50
11.1
60.0
93
916
3.00
10.9
70.0
79
1068
3.50
10.6
80.0
69
1221
4.00
10.4
90.0
62
1373
4.50
10.3
100.0
56
1526
5.00
10.1
System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT
Table data based on a MEP time resolution of 180 ps (this is an example value)
MEP steps applied = TSYSCLKOUT/180 ps in this example.
PWM minimum frequency is based on a maximum period value, TBPRD = 65 535. PWM mode is asymmetrical up-count.
Resolution in bits is given for the maximum PWM frequency stated.
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14.2.10.5.1 Edge Positioning
In a typical power control loop (switch modes, digital motor control (DMC), uninterruptible power supply
(UPS)), a digital controller (PID, 2pole/2zero, lag/lead, etc.) issues a duty command, usually expressed in
a per unit or percentage terms.
In the following example, assume that for a particular operating point, the demanded duty cycle is 0.405 or
40.5% on-time and the required converter PWM frequency is 1.25 MHz. In conventional PWM generation
with a system clock of 100 MHz, the duty cycle choices are in the vicinity of 40.5%. In Figure 14-46, a
compare value of 32 counts (duty = 40%) is the closest to 40.5% that you can attain. This is equivalent to
an edge position of 320 ns instead of the desired 324 ns. This data is shown in Table 14-34.
By utilizing the MEP, you can achieve an edge position much closer to the desired point of 324 ns.
Table 14-34 shows that in addition to the CMPA value, 22 steps of the MEP (CMPAHR register) will
position the edge at 323.96 ns, resulting in almost zero error. In this example, it is assumed that the MEP
has a step resolution of 180 ns.
Figure 14-46. Required PWM Waveform for a Requested Duty = 40.5%
Tpwm = 800 ns
324 ns
Demanded
duty (40.5%)
10 ns steps
0
30 31 32 33 34
79
EPWM1A
37.5%
40.0%
38.8%
42.5%
41.3%
Table 14-34. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)
CMPA
(count) (1) (2)
DUTY
(%)
High Time
(ns)
CMPA
(count)
CMPAHR
(count)
Duty
(%)
High Time
(ns)
28
35.0
280
32
18
40.405
323.24
29
36.3
290
32
19
40.428
323.42
30
37.5
300
32
20
40.450
323.60
31
38.8
310
32
21
40.473
323.78
32
40.0
320
32
22
40.495
323.96
33
41.3
330
32
23
40.518
324.14
34
42.5
340
32
24
40.540
324.32
32
25
40.563
324.50
32
26
40.585
324.68
32
27
40.608
324.86
(3)
Required
32.40
(1)
(2)
(3)
344
40.5
324
System clock, SYSCLKOUT and TBCLK = 100 MHz, 10 ns
For a PWM Period register value of 80 counts, PWM Period = 80 × 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz
Assumed MEP step size for the above example = 180 ps
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14.2.10.5.2 Scaling Considerations
The mechanics of how to position an edge precisely in time has been demonstrated using the resources
of the standard (CMPA) and MEP (CMPAHR) registers. In a practical application, however, it is necessary
to seamlessly provide the CPU a mapping function from a per-unit (fractional) duty cycle to a final integer
(non-fractional) representation that is written to the [CMPA:CMPAHR] register combination.
To do this, first examine the scaling or mapping steps involved. It is common in control software to
express duty cycle in a per-unit or percentage basis. This has the advantage of performing all needed
math calculations without concern for the final absolute duty cycle, expressed in clock counts or high time
in ns. Furthermore, it makes the code more transportable across multiple converter types running different
PWM frequencies.
To implement the mapping scheme, a two-step scaling procedure is required.
Assumptions for this example:
System clock, SYSCLKOUT
PWM frequency
Required PWM duty cycle, PWMDuty
PWM period in terms of coarse steps,
PWMperiod (800 ns/10 ns)
Number of MEP steps per coarse step at
180 ps (10 ns/180 ps), MEP_SF
Value to keep CMPAHR within the range
of 1-255 and fractional rounding constant
(default value)
=
=
=
=
10 ns (100 MHz)
1.25 MHz (1/800 ns)
0.405 (40.5%)
80
= 55
= 180h
Step 1: Percentage Integer Duty value conversion for CMPA register
CMPA register value
=
=
=
=
CMPA register value
int(PWMDuty × PWMperiod); int means integer part
int(0.405 × 80)
int(32.4)
32 (20h)
Step 2: Fractional value conversion for CMPAHR register
CMPAHR register value
= (frac(PWMDuty × PWMperiod) × MEP_SF) << 8) +
180h; frac means fractional part
= (frac(32.4) × 55 <<8) + 180h; Shift is to move the
value as CMPAHR high byte
= ((0.4 × 55) <<8) + 180h
= (22 <<8) + 180h
= 22 × 256 + 180h ; Shifting left by 8 is the same
multiplying by 256.
= 5632 + 180h
= 1600h + 180h
= 1780h; CMPAHR value = 1700h, lower 8 bits will be
ignored by hardware.
CMPAHR value
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14.2.10.5.3 Duty Cycle Range Limitation
In high resolution mode, the MEP is not active for 100% of the PWM period. It becomes operational
3 SYSCLK cycles after the period starts.
Duty cycle range limitations are illustrated in Figure 14-47. This limitation imposes a lower duty cycle limit
on the MEP. For example, precision edge control is not available all the way down to 0% duty cycle.
Although for the first 3 or 6 cycles, the HRPWM capabilities are not available, regular PWM duty control is
still fully operational down to 0% duty. In most applications this should not be an issue as the controller
regulation point is usually not designed to be close to 0% duty cycle.
Figure 14-47. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
TPWM
0
3
6
100
EPWM1A
If the application demands HRPWM operation in the low percent duty cycle region, then the HRPWM can
be configured to operate in count-down mode with the rising edge position (REP) controlled by the MEP.
This is illustrated in Figure 14-48. In this case low percent duty limitation is no longer an issue.
Figure 14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
Tpwm
0
3
100
6
EPWM1A
346
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14.3 Applications to Power Topologies
An ePWM module has all the local resources necessary to operate completely as a standalone module or
to operate in synchronization with other identical ePWM modules.
14.3.1 Overview of Multiple Modules
Previously in this user's guide, all discussions have described the operation of a single module. To
facilitate the understanding of multiple modules working together in a system, the ePWM module
described in reference is represented by the more simplified block diagram shown in Figure 14-49. This
simplified ePWM block shows only the key resources needed to explain how a multiswitch power topology
is controlled with multiple ePWM modules working together.
Figure 14-49. Simplified ePWM Module
SyncIn
Phase reg
EN
EPWMxA
Φ=0°
EPWMxB
CTR = 0
CTR=CMPB
X
SyncOut
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14.3.2 Key Configuration Capabilities
The key configuration choices available to each module are as follows:
• Options for SyncIn
– Load own counter with phase register on an incoming sync strobe—enable (EN) switch closed
– Do nothing or ignore incoming sync strobe—enable switch open
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to
CTR = CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
• Options for SyncOut
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to
CTR = CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
For each choice of SyncOut, a module may also choose to load its own counter with a new phase value
on a SyncIn strobe input or choose to ignore it, i.e., via the enable switch. Although various combinations
are possible, the two most common—master module and slave module modes—are shown in Figure 1450.
Figure 14-50. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
Ext SyncIn
(optional)
Master
Slave
Phase reg
SyncIn
Phase reg EN
Φ=0°
EN
348
EPWM2A
Φ=0°
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
SyncIn
2
SyncOut
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EPWM2B
CTR=0
CTR=CMPB
X
SyncOut
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14.3.3 Controlling Multiple Buck Converters With Independent Frequencies
One of the simplest power converter topologies is the buck. A single ePWM module configured as a
master can control two buck stages with the same PWM frequency. If independent frequency control is
required for each buck converter, then one ePWM module must be allocated for each converter stage.
Figure 14-51 shows four buck stages, each running at independent frequencies. In this case, all four
ePWM modules are configured as Masters and no synchronization is used. Figure 14-52 shows the
waveforms generated by the setup shown in Figure 14-51; note that only three waveforms are shown,
although there are four stages.
Figure 14-51. Control of Four Buck Stages. (Note: FPWM1≠ FPWM2≠ FPWM3≠ FPWM4)
Ext SyncIn
(optional)
Master1
Phase reg
SyncIn
En
Vin1
Φ=X
Vout1
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
Buck #1
EPWM1A
SyncOut
Master2
Phase reg
SyncIn
Vin2
Vout2
En
EPWM2A
Φ=X
2
Buck #2
EPWM2B
CTR=0
CTR=CMPB
X
EPWM2A
SyncOut
Master3
Phase reg
SyncIn
Vin3
En
Vout3
EPWM3A
Φ=X
3
Buck #3
EPWM3B
CTR=0
CTR=CMPB
X
EPWM3A
SyncOut
Master4
Phase reg
Vin4
SyncIn
Vout4
En
EPWM4A
Φ=X
EPWM4B
CTR=0
CTR=CMPB
X
3
Buck #4
EPWM4A
SyncOut
NOTE: Θ = X indicates value in phase register is a "don't care"
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Figure 14-52. Buck Waveforms for Figure 14-51 (Note: Only three bucks shown here)
P
I
P
I
700
P
P
I
1200
CA
P
CA
P
EPWM1A
700
P
1400
CA
P
CA
EPWM2A
500
CA
P
CA
800
P
CA
P
EPWM3A
P
I
Indicates this event triggers an interrupt
350 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
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Table 14-35. EPWM1 Initialization for Figure 14-52
Register
Bit
Value
Comments
TBPRD
TBPRD
1200 (4B0h)
Period = 1201 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
CMPCTL
AQCTLA
Phase loading disabled
Table 14-36. EPWM2 Initialization for Figure 14-52
Register
Bit
Value
Comments
TBPRD
TBPRD
1400 (578h)
Period = 1401 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
CMPCTL
AQCTLA
Phase loading disabled
Table 14-37. EPWM3 Initialization for Figure 14-52
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 801 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
CMPCTL
AQCTLA
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Example 14-3. Configuration for Example in Figure 14-52
// Run Time (Note: Example execution of one run-time instance)
//=========================================================
EPwm1Regs.CMPA.half.CMPA = 700;
// adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 700;
// adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 500;
// adjust duty for output EPWM3A
14.3.4 Controlling Multiple Buck Converters With Same Frequencies
If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at
integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules
remain locked. Figure 14-53 shows such a configuration; Figure 14-54 shows the waveforms generated by
the configuration.
Figure 14-53. Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1)
Vin1
Buck #1
Ext SyncIn
(optional)
Master
Phase reg
Vout1
EPWM1A
SyncIn
En
EPWM1A
Φ=0°
Vin2
Vout2
EPWM1B
CTR=0
CTR=CMPB
Buck #2
EPWM1B
X
SyncOut
Vin3
Vout3
Buck #3
Slave
Phase reg
EPWM2A
SyncIn
En
EPWM2A
Φ=X
EPWM2B
CTR=0
CTR=CMPB
X
Vout4
Buck #4
SyncOut
352
Vin4
EPWM2B
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Figure 14-54. Buck Waveforms for Figure 14-53 (Note: FPWM2 = FPWM1)
600
Z
I
400
Z
I
Z
I
400
200
200
CA
P
A
CA
CA
P
A
CA
EPWM1A
CB
CB
CB
CB
EPWM1B
500
500
300
300
CA
CA
CA
CA
EPWM2A
CB
CB
CB
CB
EPWM2B
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Table 14-38. EPWM1 Initialization for Figure 14-53
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM1A
CAD
AQ_CLEAR
CBU
AQ_SET
CBD
AQ_CLEAR
CMPCTL
AQCTLA
AQCTLB
Phase loading disabled
Sync down-stream module
Set actions for EPWM1B
Table 14-39. EPWM2 Initialization for Figure 14-53
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM2A
CAD
AQ_CLEAR
CBU
AQ_SET
CBD
AQ_CLEAR
CMPCTL
AQCTLA
AQCTLB
Phase loading enabled
Sync flow-through
Set actions for EPWM2B
Example 14-4. Code Snippet for Configuration in Figure 14-53
// Run Time (Note: Example execution of one run-time instance)
//===========================================================
EPwm1Regs.CMPA.half.CMPA = 400;
// adjust duty for output
EPwm1Regs.CMPB = 200;
// adjust duty for output
EPwm2Regs.CMPA.half.CMPA = 500;
// adjust duty for output
EPwm2Regs.CMPB = 300;
// adjust duty for output
354
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
EPWM1A
EPWM1B
EPWM2A
EPWM2B
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14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
Topologies that require control of multiple switching elements can also be addressed with these same
ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control
can be extended to multiple stages. Figure 14-55 shows control of two synchronized Half-H bridge stages
where stage 2 can operate at integer multiple (N) frequencies of stage 1. Figure 14-56 shows the
waveforms generated by the configuration shown in Figure 14-55.
Module 2 (slave) is configured for Sync flow-through; if required, this configuration allows for a third Half-H
bridge to be controlled by PWM module 3 and also, most importantly, to remain in synchronization with
master module 1.
Figure 14-55. Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1)
VDC_bus
Ext SyncIn
(optional)
Master
Phase reg
En
Φ=0°
SyncIn
EPWM1A
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
EPWM1B
SyncOut
Slave
Phase reg
En
Φ=0°
Vout1
SyncIn
VDC_bus
EPWM2A
Vout2
EPWM2B
CTR=0
CTR=CMPB
X
EPWM2A
SyncOut
EPWM2B
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Figure 14-56. Half-H Bridge Waveforms for Figure 14-55 (Note: FPWM2 = FPWM1)
Z
I
Z
I
600
400
400
200
200
Z
CB
A
Z
I
Z
CA
CB
A
CA
EPWM1A
CA
CB
A
Z
CA
CB
A
Z
CA
CB
A
Z
EPWM1B
Pulse Center
500
500
250
Z
CB
A
250
CA
Z
CB
A
CA
EPWM2A
CA
CB
A
Z
EPWM2B
Pulse Center
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Table 14-40. EPWM1 Initialization for Figure 14-55
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM1A
CAU
AQ_CLEAR
ZRO
AQ_CLEAR
CAD
AQ_SET
CMPCTL
AQCTLA
AQCTLB
Phase loading disabled
Sync down-stream module
Set actions for EPWM1B
Table 14-41. EPWM2 Initialization for Figure 14-55
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM2A
CAU
AQ_CLEAR
ZRO
AQ_CLEAR
CAD
AQ_SET
CMPCTL
AQCTLA
AQCTLB
Phase loading enabled
Sync flow-through
Set actions for EPWM2B
Example 14-5. Code Snippet for Configuration in Figure 14-55
// Run Time (Note: Example execution of one run-time instance)
//===========================================================
EPwm1Regs.CMPA.half.CMPA = 400; // adjust duty for output
EPwm1Regs.CMPB = 200;
// adjust duty for output
EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output
EPwm2Regs.CMPB = 250;
// adjust duty for output
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EPWM1B
EPWM2A
EPWM2B
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14.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
The idea of multiple modules controlling a single power stage can be extended to the 3-phase Inverter
case. In such a case, six switching elements can be controlled using three PWM modules, one for each
leg of the inverter. Each leg must switch at the same frequency and all legs must be synchronized. A
master + two slaves configuration can easily address this requirement. Figure 14-57 shows how six PWM
modules can control two independent 3-phase Inverters; each running a motor.
As in the cases shown in the previous sections, we have a choice of running each inverter at a different
frequency (module 1 and module 4 are masters as in Figure 14-57), or both inverters can be synchronized
by using one master (module 1) and five slaves. In this case, the frequency of modules 4, 5, and 6 (all
equal) can be integer multiples of the frequency for modules 1, 2, 3 (also all equal).
Figure 14-57. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
Ext SyncIn
(optional)
Master
Phase reg
En
SyncIn
EPWM1A
Φ=0°
CTR=0
CTR=CMPB
X
1
SyncOut
Slave
Phase reg
En
EPWM1B
EPWM1A
SyncIn
EPWM2A
Φ=0°
CTR=0
CTR=CMPB
X
2
SyncOut
Slave
Phase reg
En
EPWM2A
EPWM3A
VAB
VCD
EPWM2B
VEF
EPWM1B
EPWM2B
EPWM3B
3 phase motor
SyncIn
Φ=0°
EPWM3A
CTR=0
CTR=CMPB
X
3
SyncOut
3 phase inverter #1
EPWM3B
Slave
Phase reg
SyncIn
En
Φ=0°
EPWM4A
CTR=0
CTR=CMPB
X
4
SyncOut
Slave
Phase reg
En
EPWM4B
EPWM4A
SyncIn
Φ=0°
VEF
EPWM4B
X
EPWM5B
EPWM6B
SyncOut
3 phase motor
SyncIn
Φ=0°
CTR=0
CTR=CMPB
X
6
SyncOut
358
VCD
EPWM5B
CTR=0
Slave
Phase reg
En
EPWM6A
VAB
EPWM5A
CTR=CMPB
5
EPWM5A
EPWM6A
3 phase inverter #2
EPWM6B
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Figure 14-58. 3-Phase Inverter Waveforms for Figure 14-57 (Only One Inverter Shown)
Z
I
Z
I
800
500
500
CA
CA
P
A
EPWM1A
CA
CA
P
A
RED
RED
EPWM1B
FED
FED
Φ2=0
600
600
CA
CA
CA
CA
EPWM2A
RED
EPWM2B
FED
700
700
Φ3=0
CA
EPWM3A
CA
CA
CA
RED
EPWM3B
FED
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Table 14-42. EPWM1 Initialization for Figure 14-57
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 1600 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM1A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
50
RED = 50 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Phase loading disabled
Sync down-stream module
Table 14-43. EPWM2 Initialization for Figure 14-57
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 1600 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM2A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
50
RED = 50 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
360 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Slave module
Sync flow-through
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Table 14-44. EPWM3 Initialization for Figure 14-57
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 1600 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM3A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
50
RED = 50 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Slave module
Sync flow-through
Example 14-6. Code Snippet for Configuration in Figure 14-57
// Run Time (Note: Example execution of one run-time instance)
//=========================================================
EPwm1Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A
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14.3.7 Practical Applications Using Phase Control Between PWM Modules
So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero
or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple
PWM modules can address another class of power topologies that rely on phase relationship between
legs (or stages) for correct operation. As described in the TB module section, a PWM module can be
configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCNT register. To
illustrate this concept, Figure 14-59 shows a master and slave module with a phase relationship of 120°,
that is, the slave leads the master.
Figure 14-59. Configuring Two PWM Modules for Phase Control
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
En
EPWM1A
Φ=0°
EPWM1B
CTR=0
CTR=CMPB
X
1
SyncOut
Slave
Phase reg
SyncIn
En
EPWM2A
Φ=120°
EPWM2B
CTR=0
CTR=CMPB
X
2
SyncOut
Figure 14-60 shows the associated timing waveforms for this configuration. Here, TBPRD = 600 for both
master and slave. For the slave, TBPHS = 200 (200/600 × 360° = 120°). Whenever the master generates
a SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCNT register so the
slave time-base is always leading the master's time-base by 120°.
362
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Figure 14-60. Timing Waveforms Associated With Phase Control Between 2 Modules
FFFFh
TBCNT
Master Module
600
600
TBPRD
0000h
CTR = PRD
(SycnOut)
FFFFh
time
TBCNT
Phase = 120°
Φ2
Slave Module
TBPRD
600
600
200
200
TBPHS
0000h
SyncIn
time
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter
A popular power topology that makes use of phase-offset between modules is shown in Figure 14-61. This
system uses three PWM modules, with module 1 configured as the master. To work, the phase
relationship between adjacent modules must be F = 120°. This is achieved by setting the slave TBPHS
registers 2 and 3 with values of 1/3 and 2/3 of the period value, respectively. For example, if the period
register is loaded with a value of 600 counts, then TBPHS (slave 2) = 200 and TBPHS (slave 3) = 400.
Both slave modules are synchronized to the master 1 module.
This concept can be extended to four or more phases, by setting the TBPHS values appropriately. The
following formula gives the TBPHS values for N phases:
TBPHS(N,M) = (TBPRD/N) × (M - 1)
Where:
N = number of phases
M = PWM module number
For example, for the 3-phase case (N = 3), TBPRD = 600,
TBPHS(3,2) = (600/3) × (2 - 1) = 200 × 1 = 200 (Phase value for Slave module 2)
TBPHS(3,3) = (600/3) × (3 - 1) = 200 × 2 = 400 (Phase value for Slave module 3)
Figure 14-62 shows the waveforms for the configuration in Figure 14-61.
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Figure 14-61. Control of a 3-Phase Interleaved DC/DC Converter
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
VIN
En
Φ=0°
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
EPWM1A
EPWM2A
EPWM3A
EPWM1B
EPWM2B
EPWM3B
SyncOut
Slave
Phase reg
SyncIn
VOUT
En
EPWM2A
Φ=120°
EPWM2B
CTR=0
CTR=CMPB
X
2
SyncOut
Slave
Phase reg
SyncIn
En
EPWM3A
Φ=240°
EPWM3B
CTR=0
CTR=CMPB
X
3
364
SyncOut
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Figure 14-62. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 14-61
Z
I
285
CA
EPWM1A
285
P
A
CA
CA
RED
P
A
FED
Z
I
CA
CA
RED
EPWM1B
300
Z
I
Z
I
450
P
A
CA
RED
FED
FED
Φ2=120°
TBPHS
(=300)
EPWM2A
EPWM2B
300
Φ2=120°
TBPHS
(=300)
EPWM3A
EPWM3B
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Table 14-45. EPWM1 Initialization for Figure 14-61
Register
Bit
Value
Comments
TBPRD
TBPRD
450 (1C2h)
Period = 900 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM1A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
20
FED = 20 TBCLKs
DBRED
20
RED = 20 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Phase loading disabled
Sync down-stream module
Table 14-46. EPWM2 Initialization for Figure 14-61
Register
Bit
Value
Comments
TBPRD
TBPRD
450 (1C2h)
Period = 900 TBCLK counts
TBPHS
TBPHS
300
Phase = (300/900) × 360 = 120°
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
Sync flow-through
PHSDIR
TB_DOWN
Count DOWN on sync
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM2A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
20
FED = 20 TBCLKs
DBRED
20
RED = 20 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
366 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Slave module
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Table 14-47. EPWM3 Initialization for Figure 14-61
Register
Bit
Value
Comments
TBPRD
TBPRD
450 (1C2h)
Period = 900 TBCLK counts
TBPHS
TBPHS
300
Phase = (300/900) × 360 = 120°
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
Sync flow-through
PHSDIR
TB_UP
Count UP on sync
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM3A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
20
FED = 20 TBCLKs
DBRED
20
RED = 20 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Slave module
Example 14-7. Code Snippet for Configuration in Figure 14-61
// Run Time (Note: Example execution of one run-time instance)
//===========================================================
EPwm1Regs.CMPA.half.CMPA = 285;
// adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 285;
// adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 285;
// adjust duty for output EPWM3A
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14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
The example given in Figure 14-63 assumes a static or constant phase relationship between legs
(modules). In such a case, control is achieved by modulating the duty cycle. It is also possible to
dynamically change the phase value on a cycle-by-cycle basis. This feature lends itself to controlling a
class of power topologies known as phase-shifted full bridge, or zero voltage switched full bridge. Here the
controlled parameter is not duty cycle (this is kept constant at approximately 50 percent); instead it is the
phase relationship between legs. Such a system can be implemented by allocating the resources of two
PWM modules to control a single power stage, which in turn requires control of four switching elements.
Figure 14-64 shows a master/slave module combination synchronized together to control a full H-bridge.
In this case, both master and slave modules are required to switch at the same PWM frequency. The
phase is controlled by using the slave's phase register (TBPHS). The master's phase register is not used
and therefore can be initialized to zero.
Figure 14-63. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1 )
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
En
Φ=0°
EPWM1A
CTR=0
CTR=CMPB
X
EPWM1B
Slave
Phase reg
SyncOut
Vout
VDC_bus
EPWM1A
EPWM2A
EPWM1B
EPWM2B
SyncIn
En
EPWM2A
Φ=Var°
CTR=0
CTR=CMPB
X
EPWM2B
SyncOut
Var = Variable
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Figure 14-64. ZVS Full-H Bridge Waveforms
Z
I
Z
I
Z
I
1200
600
200
Z
CB
A
CA
Z
CB
A
CA
Z
RED
ZVS transition
EPWM1A
Power phase
FED
ZVS transition
EPWM1B
300
TBPHS
=(1200−Φ2)
Φ2=variable
CB
A
Z
CA
CB
A
Z
Z
CA
RED
EPWM2A
EPWM2B
FED
Power phase
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Table 14-48. EPWM1 Initialization for Figure 14-63
Register
Bit
Value
Comments
TBPRD
TBPRD
1200 (4B0h)
Period = 1201 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
Phase loading disabled
SYNCOSEL
TB_CTR_ZERO
Sync down-stream module
CMPA
CMPA
600 (258h)
Set 50% duty for EPWM1A
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM1A
CAU
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
70
RED = 70 TBCLKs
AQCTLA
DBCTL
DBFED
Table 14-49. EPWM2 Initialization for Figure 14-63
Register
Bit
Value
Comments
TBPRD
TBPRD
1200 (4B0h)
Period = 1201 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
Sync flow-through
CMPA
CMPA
600 (258h)
Set 50% duty for EPWM2A
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM2A
CAU
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
30
FED = 30 TBCLKs
DBRED
40
RED = 40 TBCLKs
AQCTLA
DBCTL
DBFED
Slave module
Example 14-8. Code Snippet for Configuration in Figure 14-63
// Run Time (Note: Example execution of one run-time instance)
//============================================================
EPwm2Regs.TBPHS = 1200-300;
// Set Phase reg to 300/1200 * 360 = 90 deg
EPwm1Regs.DBFED = FED1_NewValue;
// Update ZVS transition interval
EPwm1Regs.DBRED = RED1_NewValue;
// Update ZVS transition interval
EPwm2Regs.DBFED = FED2_NewValue;
// Update ZVS transition interval
EPwm2Regs.DBRED = RED2_NewValue;
// Update ZVS transition interval
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14.4 Registers
This section includes the registers for the submodules.
Table 14-50. Submodule Registers
Submodule
Section
Time-Base Submodule Registers
Section 14.4.1
Counter-Compare Submodule Registers
Section 14.4.2
Action-Qualifier Submodule Registers
Section 14.4.3
Dead-Band Generator Submodule Registers
Section 14.4.4
PWM-Chopper Submodule Registers
Section 14.4.5
Trip-Zone Submodule Registers
Section 14.4.6
Event-Trigger Submodule Registers
Section 14.4.7
High-Resolution PWM Registers
Section 14.4.8
14.4.1 Time-Base Submodule Registers
Table 14-51 lists the memory-mapped registers for the time-base submodule. See your device-specific
data manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-51 should be considered as reserved locations and the register contents should not be modified.
Table 14-51. Time-Base Submodule Registers
Offset
(1)
Acronym
Register Description
Section
0h
TBCTL
Time-Base Control Register
Section 14.4.1.1
2h
TBSTS
Time-Base Status Register
Section 14.4.1.2
4h
TBPHSHR
Time-Base Phase High-Resolution Register (1)
Section 14.4.8.1
6h
TBPHS
Time-Base Phase Register
Section 14.4.1.3
8h
TBCNT
Time-Base Counter Register
Section 14.4.1.4
Ah
TBPRD
Time-Base Period Register
Section 14.4.1.5
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved. See your device-specific data manual to determine which instances include the HRPWM.
14.4.1.1 Time-Base Control Register (TBCTL)
The time-base control register (TBCTL) is shown in Figure 14-65 and described in Table 14-52.
Figure 14-65. Time-Base Control Register (TBCTL)
15
14
13
12
10
9
8
FREE, SOFT
PHSDIR
CLKDIV
HSPCLKDIV
R/W-0
R/W-0
R/W-0
R/W-0
7
6
HSPCLKDIV
SWFSYNC
R/W-1
R/W-0
5
4
3
2
1
0
SYNCOSEL
PRDLD
PHSEN
CTRMODE
R/W-0
R/W-0
R/W-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 14-52. Time-Base Control Register (TBCTL) Field Descriptions
Bit
15-14
Field
FREE, SOFT
Value
0-3h
Description
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
0
Stop after the next time-base counter increment or decrement
1h
Stop when counter completes a whole cycle:
• Up-count mode: stop when the time-base counter = period (TBCNT = TBPRD)
• Down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
• Up-down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
2h-3h
13
PHSDIR
Free run
Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-downcount mode. The PHSDIR bit indicates the direction the time-base counter (TBCNT) will count after
a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register.
This is irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
12:10
9-7
CLKDIV
HSPCLKDIV
0
Count down after the synchronization event.
1
Count up after the synchronization event.
0-7h
Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value.
TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
0
/1 (default on reset)
1h
/2
2h
/4
3h
/8
4h
/16
5h
/32
6h
/64
7h
/128
0-7h
High-Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock
prescale value.
TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager
(EV) peripheral.
6
0
/1
1h
/2 (default on reset)
2h
/4
3h
/6
4h
/8
5h
/10
6h
/12
7h
/14
SWFSYNC
Software Forced Synchronization Pulse
0
Writing a 0 has no effect and reads always return a 0.
1
Writing a 1 forces a one-time synchronization pulse to be generated.
This event is ORed with the EPWMxSYNCI input of the ePWM module.
SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.
5-4
372
SYNCOSEL
0-3h
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
0
EPWMxSYNC:
1h
CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
2h
CTR = CMPB : Time-base counter equal to counter-compare B (TBCNT = CMPB)
3h
Disable EPWMxSYNCO signal
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Table 14-52. Time-Base Control Register (TBCTL) Field Descriptions (continued)
Bit
3
Field
Value
PRDLD
Description
Active Period Register Load From Shadow Register Select
0
The period register (TBPRD) is loaded from its shadow register when the time-base counter,
TBCNT, is equal to zero.
A write or read to the TBPRD register accesses the shadow register.
1
Load the TBPRD register immediately without using a shadow register.
A write or read to the TBPRD register directly accesses the active register.
2
1-0
PHSEN
Counter Register Load From Phase Register Enable
CTRMODE
0
Do not load the time-base counter (TBCNT) from the time-base phase register (TBPHS)
1
Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or
when a software synchronization is forced by the SWFSYNC bit.
0-3h
Counter Mode. The time-base counter mode is normally configured once and not changed during
normal operation. If you change the mode of the counter, the change will take effect at the next
TBCLK edge and the current counter value shall increment or decrement from the value before the
mode change.
These bits set the time-base counter mode of operation as follows:
0
Up-count mode
1h
Down-count mode
2h
Up-down-count mode
3h
Stop-freeze counter operation (default on reset)
14.4.1.2 Time-Base Status Register (TBSTS)
The time-base status register (TBSTS) is shown in Figure 14-66 and described in Table 14-53.
Figure 14-66. Time-Base Status Register (TBSTS)
15
2
1
0
Reserved
3
CTRMAX
SYNCI
CTRDIR
R-0
R/W1C-0
R/W1C-0
R-1
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to clear; -n = value after reset
Table 14-53. Time-Base Status Register (TBSTS) Field Descriptions
Bit
Field
15-3
Reserved
2
CTRMAX
1
0
Value
0
Description
Reserved
Time-Base Counter Max Latched Status Bit
0
Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no
effect.
1
Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing a 1
to this bit will clear the latched event.
SYNCI
Input Synchronization Latched Status Bit
0
Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred.
1
Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI).
Writing a 1 to this bit will clear the latched event.
CTRDIR
Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no
meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL[CTRMODE].
0
Time-Base Counter is currently counting down.
1
Time-Base Counter is currently counting up.
14.4.1.3 Time-Base Phase Register (TBPHS)
The time-base phase register (TBPHS) is shown in Figure 14-67 and described in Table 14-54.
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Figure 14-67. Time-Base Phase Register (TBPHS)
15
0
TBPHS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-54. Time-Base Phase Register (TBPHS) Field Descriptions
Bits
Name
15-0
TBPHS
Value
0-FFFFh
Description
These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying
the synchronization input signal.
• If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is not
loaded with the phase.
• If TBCTL[PHSEN] = 1, then the time-base counter (TBCNT) will be loaded with the phase (TBPHS)
when a synchronization event occurs. The synchronization event can be initiated by the input
synchronization signal (EPWMxSYNCI) or by a software forced synchronization.
14.4.1.4 Time-Base Counter Register (TBCNT)
The time-base counter register (TBCNT) is shown in Figure 14-68 and described in Table 14-55.
Figure 14-68. Time-Base Counter Register (TBCNT)
15
0
TBCNT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-55. Time-Base Counter Register (TBCNT) Field Descriptions
Bits
Name
15-0
TBCNT
Value
0-FFFFh
Description
Reading these bits gives the current time-base counter value.
Writing to these bits sets the current time-base counter value. The update happens as soon as the write
occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not
shadowed.
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14.4.1.5 Time-Base Period Register (TBPRD)
The time-base period register (TBPRD) is shown in Figure 14-69 and described in Table 14-56.
Figure 14-69. Time-Base Period Register (TBPRD)
15
0
TBPRD
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-56. Time-Base Period Register (TBPRD) Field Descriptions
Bits
Name
15-0
TBPRD
Value
0-FFFFh
Description
These bits determine the period of the time-base counter. This sets the PWM frequency.
Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is
shadowed.
• If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the
shadow register. In this case, the active register will be loaded from the shadow register when the
time-base counter equals zero.
• If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active
register, that is the register actively controlling the hardware.
• The active and shadow registers share the same memory map address.
14.4.2 Counter-Compare Submodule Registers
Table 14-57 lists the memory-mapped registers for the counter-compare submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-57 should be considered as reserved locations and the register contents should not be
modified.
Table 14-57. Counter-Compare Submodule Registers
Offset
(1)
Acronym
Register Description
Section
Eh
CMPCTL
Counter-Compare Control Register
Section 14.4.2.1
10h
CMPAHR
Counter-Compare A High-Resolution Register (1)
Section 14.4.8.2
12h
CMPA
Counter-Compare A Register
Section 14.4.2.2
14h
CMPB
Counter-Compare B Register
Section 14.4.2.3
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved. See your device-specific data manual to determine which instances include the HRPWM.
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14.4.2.1 Counter-Compare Control Register (CMPCTL)
The counter-compare control register (CMPCTL) is shown in Figure 14-70 and described in Table 14-58.
Figure 14-70. Counter-Compare Control Register (CMPCTL)
15
10
9
8
Reserved
SHDWBFULL
SHDWAFULL
R-0
R-0
R-0
1
0
7
6
5
4
3
2
Reserved
SHDWBMODE
Reserved
SHDWAMODE
LOADBMODE
LOADAMODE
R-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-58. Counter-Compare Control Register (CMPCTL) Field Descriptions
Bits
Name
15-10 Reserved
9
8
6
SHDWBMODE
5
Reserved
4
SHDWAMODE
376
LOADBMODE
LOADAMODE
Reserved
Counter-compare B (CMPB) Shadow Register Full Status Flag. This bit self clears once a load-strobe
occurs.
0
CMPB shadow FIFO not full yet
1
Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value.
SHDWAFULL
Reserved
1-0
0
SHDWBFULL
7
3-2
Value Description
Counter-compare A (CMPA) Shadow Register Full Status Flag. The flag bit is set when a 32-bit write to
CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register
will not affect the flag. This bit self clears once a load-strobe occurs.
0
CMPA shadow FIFO not full yet
1
Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value.
0
Reserved
Counter-compare B (CMPB) Register Operating Mode
0
Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1
Immediate mode. Only the active compare B register is used. All writes and reads directly access the
active register for immediate compare action.
Reserved
Counter-compare A (CMPA) Register Operating Mode
0
Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1
Immediate mode. Only the active compare register is used. All writes and reads directly access the
active register for immediate compare action
0-3h
Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWBMODE] = 1).
0
Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h
Load on either CTR = 0 or CTR = PRD
3h
Freeze (no loads possible)
0-3h
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWAMODE] = 1).
0
Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h
Load on either CTR = 0 or CTR = PRD
3h
Freeze (no loads possible)
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14.4.2.2 Counter-Compare A Register (CMPA)
The counter-compare A register (CMPA) is shown in Figure 14-71 and described in Table 14-59.
Figure 14-71. Counter-Compare A Register (CMPA)
15
0
CMPA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-59. Counter-Compare A Register (CMPA) Field Descriptions
Bits
Name
Value
15-0
CMPA
0-FFFFh
Description
The value in the active CMPA register is continuously compared to the time-base counter (TBCNT).
When the values are equal, the counter-compare module generates a "time-base counter equal to
counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it
into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output
depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined
in the AQCTLA and AQCTLB registers include:
•
•
•
•
Do nothing; the event is ignored.
Clear: Pull the EPWMxA and/or EPWMxB signal low
Set: Pull the EPWMxA and/or EPWMxB signal high
Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this
register is shadowed.
• If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically
go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event
will load the active register from the shadow register.
• Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is
currently full.
• If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go
directly to the active register, that is the register actively controlling the hardware.
• In either mode, the active and shadow registers share the same memory map address.
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14.4.2.3 Counter-Compare B Register (CMPB)
The counter-compare B register (CMPB) is shown in Figure 14-72 and described in Table 14-60.
Figure 14-72. Counter-Compare B Register (CMPB)
15
0
CMPB
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-60. Counter-Compare B Register (CMPB) Field Descriptions
Bits
Name
Value
15-0
CMPB
0-FFFFh
Description
The value in the active CMPB register is continuously compared to the time-base counter (TBCNT).
When the values are equal, the counter-compare module generates a "time-base counter equal to
counter compare B" event. This event is sent to the action-qualifier where it is qualified and converted it
into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output
depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined
in the AQCTLA and AQCTLB registers include:
•
•
•
•
Do nothing. event is ignored.
Clear: Pull the EPWMxA and/or EPWMxB signal low
Set: Pull the EPWMxA and/or EPWMxB signal high
Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit. By default this
register is shadowed.
• If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically
go to the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event
will load the active register from the shadow register:
• Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is
currently full.
• If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go
directly to the active register, that is the register actively controlling the hardware.
• In either mode, the active and shadow registers share the same memory map address.
14.4.3 Action-Qualifier Submodule Registers
Table 14-61 lists the memory-mapped registers for the action-qualifier submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-61 should be considered as reserved locations and the register contents should not be
modified.
Table 14-61. Action-Qualifier Submodule Registers
378
Offset
Acronym
Register Description
16h
AQCTLA
Action-Qualifier Output A Control Register
Section 14.4.3.1
Section
18h
AQCTLB
Action-Qualifier Output B Control Register
Section 14.4.3.2
1Ah
AQSFRC
Action-Qualifier Software Force Register
Section 14.4.3.3
1Ch
AQCSFRC
Action-Qualifier Continuous Software Force Register
Section 14.4.3.4
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14.4.3.1 Action-Qualifier Output A Control Register (AQCTLA)
The action-qualifier output A control register (AQCTLA) is shown in Figure 14-73 and described in
Table 14-62.
Figure 14-73. Action-Qualifier Output A Control Register (AQCTLA)
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CBD
CBU
CAD
CAU
PRD
ZRO
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-62. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions
Bits
Name
15-12
Reserved
11-10
CBD
9-8
7-6
5-4
3-2
CBU
CAD
CAU
PRD
Value
0
0-3h
Description
Reserved
Action when the time-base counter equals the active CMPB register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPB register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the period.
Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0
or counting down.
1-0
ZRO
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when counter equals zero.
Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or
counting up.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
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14.4.3.2 Action-Qualifier Output B Control Register (AQCTLB)
The action-qualifier output B control register (AQCTLB) is shown in Figure 14-74 and described in
Table 14-63.
Figure 14-74. Action-Qualifier Output B Control Register (AQCTLB)
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CBD
CBU
CAD
CAU
PRD
ZRO
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-63. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
Bits
Name
15-12
Reserved
11-10
CBD
9-8
7-6
5-4
3-2
CBU
CAD
CAU
PRD
Value
0
0-3h
Description
Reserved
Action when the counter equals the active CMPB register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPB register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the period.
Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0
or counting down.
1-0
ZRO
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when counter equals zero.
Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or
counting up.
380
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
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14.4.3.3 Action-Qualifier Software Force Register (AQSFRC)
The action-qualifier software force register (AQSFRC) is shown in Figure 14-75 and described in
Table 14-64.
Figure 14-75. Action-Qualifier Software Force Register (AQSFRC)
15
8
7
6
5
4
3
2
1
0
Reserved
RLDCSF
OTSFB
ACTSFB
OTSFA
ACTSFA
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-64. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
Bit
Field
Value
15-8
Reserved
0
7-6
RLDCSF
0-3h
5
Description
Reserved
AQCSFRC Active Register Reload From Shadow Options
0
Load on event counter equals zero
1h
Load on event counter equals period
2h
Load on event counter equals zero or counter equals period
3h
Load immediately (the active register is directly accessed by the CPU and is not loaded from the
shadow register).
OTSFB
One-Time Software Forced Event on Output B
0
Writing a 0 (zero) has no effect. Always reads back a 0
This bit is auto cleared once a write to this register is complete, that is, a forced event is initiated.)
This is a one-shot forced event. It can be overridden by another subsequent event on output B.
1
4-3
ACTSFB
0-3h
Initiates a single s/w forced event
Action when One-Time Software Force B Is invoked
0
Does nothing (action disabled)
1h
Clear (low)
2h
Set (high)
3h
Toggle (Low -> High, High -> Low)
Note: This action is not qualified by counter direction (CNT_dir)
2
OTSFA
One-Time Software Forced Event on Output A
0
Writing a 0 (zero) has no effect. Always reads back a 0.
This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated).
1
1-0
ACTSFA
0-3h
Initiates a single software forced event
Action When One-Time Software Force A Is Invoked
0
Does nothing (action disabled)
1h
Clear (low)
2h
Set (high)
3h
Toggle (Low → High, High → Low)
Note: This action is not qualified by counter direction (CNT_dir)
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14.4.3.4 Action-Qualifier Continuous Software Force Register (AQCSFRC)
The action-qualifier continuous software force register (AQCSFRC) is shown in Figure 14-76 and
described in Table 14-65.
Figure 14-76. Action-Qualifier Continuous Software Force Register (AQCSFRC)
15
4
3
2
1
0
Reserved
CSFB
CSFA
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-65. Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
Bits
Name
15-4
Reserved
3-2
CSFB
Value
0
0-3h
Description
Reserved
Continuous Software Force on Output B
In immediate mode, a continuous force takes effect on the next TBCLK edge.
In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the
active register. To configure shadow mode, use AQSFRC[RLDCSF].
1-0
CSFA
0
Forcing disabled, that is, has no effect
1h
Forces a continuous low on output B
2h
Forces a continuous high on output B
3h
Software forcing is disabled and has no effect
0-3h
Continuous Software Force on Output A
In immediate mode, a continuous force takes effect on the next TBCLK edge.
In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the
active register.
0
Forcing disabled, that is, has no effect
1h
Forces a continuous low on output A
2h
Forces a continuous high on output A
3h
Software forcing is disabled and has no effect
14.4.4 Dead-Band Generator Submodule Registers
Table 14-66 lists the memory-mapped registers for the dead-band generator submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-66 should be considered as reserved locations and the register contents should not be
modified.
Table 14-66. Dead-Band Generator Submodule Registers
382
Offset
Acronym
1Eh
DBCTL
Register Description
Dead-Band Generator Control Register
Section 14.4.4.1
20h
DBRED
Dead-Band Generator Rising Edge Delay Register
Section 14.4.4.2
22h
DBFED
Dead-Band Generator Falling Edge Delay Register
Section 14.4.4.3
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14.4.4.1 Dead-Band Generator Control Register (DBCTL)
The dead-band generator control register (DBCTL) is shown in Figure 14-77 and described in
Table 14-67.
Figure 14-77. Dead-Band Generator Control Register (DBCTL)
15
6
5
4
3
2
1
0
Reserved
IN_MODE
POLSEL
OUT_MODE
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-67. Dead-Band Generator Control Register (DBCTL) Field Descriptions
Bits
Name
15-6
Reserved
Value
0
5-4
IN_MODE
0-3h
Description
Reserved
Dead Band Input Mode Control. Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in
Figure 14-29. This allows you to select the input source to the falling-edge and rising-edge delay.
To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and
rising-edge delays.
0
EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
1h
EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
2h
EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
3-2
POLSEL
3h
EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed
signal.
0-3h
Polarity Select Control. Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 1429. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band
submodule.
The following descriptions correspond to classical upper/lower switch control as found in one leg of a
digital motor control inverter.
These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other enhanced modes
are also possible, but not regarded as typical usage modes.
1-0
OUT_MODE
0
Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
1h
Active low complementary (ALC) mode. EPWMxA is inverted.
2h
Active high complementary (AHC). EPWMxB is inverted.
3h
Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.
0-3h
Dead-band Output Mode Control. Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in
Figure 14-29. This allows you to selectively enable or bypass the dead-band generation for the fallingedge and rising-edge delay.
0
Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and
EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule.
In this mode, the POLSEL and IN_MODE bits have no effect.
1h
Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to
the EPWMxA input of the PWM-chopper submodule.
The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined
by DBCTL[IN_MODE].
2h
Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to
the EPWMxB input of the PWM-chopper submodule.
The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined
by DBCTL[IN_MODE].
3h
Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on
output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE].
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14.4.4.2 Dead-Band Generator Rising Edge Delay Register (DBRED)
The dead-band generator rising edge delay register (DBRED) is shown in Figure 14-78 and described in
Table 14-68.
Figure 14-78. Dead-Band Generator Rising Edge Delay Register (DBRED)
15
10
9
0
Reserved
DEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-68. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
Bits
15-10
9-0
Name
Value
Reserved
0
DEL
0-3FFh
Description
Reserved
Rising Edge Delay Count. 10-bit counter.
14.4.4.3 Dead-Band Generator Falling Edge Delay Register (DBFED)
The dead-band generator falling edge delay register (DBFED) is shown in Figure 14-79 and described in
Table 14-69.
Figure 14-79. Dead-Band Generator Falling Edge Delay Register (DBFED)
15
10
9
0
Reserved
DEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-69. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
Bits
15-10
9-0
384
Name
Reserved
DEL
Value
0
0-3FFh
Description
Reserved
Falling Edge Delay Count. 10-bit counter
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14.4.5 PWM-Chopper Submodule Register
The PWM-chopper control register (PCCTL) is shown in Figure 14-80 and described in Table 14-70.
Figure 14-80. PWM-Chopper Control Register (PCCTL)
15
11
10
8
7
5
4
1
0
Reserved
CHPDUTY
CHPFREQ
OSHTWTH
CHPEN
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-70. PWM-Chopper Control Register (PCCTL) Bit Descriptions
Bits
Name
Value
15-11
Reserved
0
10-8
CHPDUTY
0-7h
7-5
4-1
CHPFREQ
OSHTWTH
Reserved
Chopping Clock Duty Cycle
0
Duty = 1/8 (12.5%)
1h
Duty = 2/8 (25.0%)
2h
Duty = 3/8 (37.5%)
3h
Duty = 4/8 (50.0%)
4h
Duty = 5/8 (62.5%)
5h
Duty = 6/8 (75.0%)
6h
Duty = 7/8 (87.5%)
7h
Reserved
0-7h
Chopping Clock Frequency
0
Divide by 1 (no prescale)
1h
Divide by 2
2h
Divide by 3
3h-7h
Divide by 4 to divide by 8
0-Fh
One-Shot Pulse Width
0
1 × SYSCLKOUT/8 wide
1h
2 × SYSCLKOUT/8 wide
2h
3 × SYSCLKOUT/8 wide
3h-Fh
0
Description
CHPEN
4 × SYSCLKOUT/8 wide to 16 × SYSCLKOUT/8 wide
PWM-chopping Enable
0
Disable (bypass) PWM chopping function
1
Enable chopping function
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14.4.6 Trip-Zone Submodule Registers
Table 14-71 lists the memory-mapped registers for the trip-zone submodule. See your device-specific data
manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-71 should be considered as reserved locations and the register contents should not be modified.
Table 14-71. Trip-Zone Submodule Registers
Offset
Acronym
24h
TZSEL
Register Description
Trip-Zone Select Register
Section 14.4.6.1
Section
28h
TZCTL
Trip-Zone Control Register
Section 14.4.6.2
2Ah
TZEINT
Trip-Zone Enable Interrupt Register
Section 14.4.6.3
2Ch
TZFLG
Trip-Zone Flag Register
Section 14.4.6.4
2Eh
TZCLR
Trip-Zone Clear Register
Section 14.4.6.5
30h
TZFRC
Trip-Zone Force Register
Section 14.4.6.6
14.4.6.1 Trip-Zone Select Register (TZSEL)
The trip-zone select register (TZSEL) is shown in Figure 14-81 and described in Table 14-72.
Figure 14-81. Trip-Zone Select Register (TZSEL)
15
9
Reserved/OSHTn
(1)
8
OSHT1
R/W-0
7
1
Reserved/CBCn
R/W-0
(1)
R/W-0
0
CBC1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
(1)
Number of register bits depends on how many trip-zone pins are available in the device. See your device-specific data manual.
Table 14-72. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
Bits
Name
15-8
OSHTn
7-0
386
Value
Description
Trip-zone n (TZn) select. One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go
low, a one-shot trip event occurs for this ePWM module. When the event occurs, the action defined in
the TZCTL register (Section 14.4.6.2) is taken on the EPWMxA and EPWMxB outputs. The one-shot
trip condition remains latched until you clear the condition via the TZCLR register (Section 14.4.6.5).
0
Disable TZn as a one-shot trip source for this ePWM module.
1
Enable TZn as a one-shot trip source for this ePWM module.
CBCn
Trip-zone n (TZn) select. Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins
go low, a cycle-by-cycle trip event occurs for this ePWM module. When the event occurs, the action
defined in the TZCTL register (Section 14.4.6.2) is taken on the EPWMxA and EPWMxB outputs. A
cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero.
0
Disable TZn as a CBC trip source for this ePWM module.
1
Enable TZn as a CBC trip source for this ePWM module.
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14.4.6.2 Trip-Zone Control Register (TZCTL)
The trip-zone control register (TZCTL) is shown in Figure 14-82 and described in Table 14-73.
Figure 14-82. Trip-Zone Control Register (TZCTL)
15
4
3
2
1
0
Reserved
TZB
TZA
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-73. Trip-Zone Control Register (TZCTL) Field Descriptions
Bits
Name
15–4
Reserved
3–2
TZB
1–0
TZA
Value
0
0-3h
Description
Reserved
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can
cause an event is defined in the TZSEL register (Section 14.4.6.1).
0
High impedance (EPWMxB = High-impedance state)
1h
Force EPWMxB to a high state
2h
Force EPWMxB to a low state
3h
Do nothing, no action is taken on EPWMxB.
0-3h
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can
cause an event is defined in the TZSEL register (Section 14.4.6.1).
0
High impedance (EPWMxA = High-impedance state)
1h
Force EPWMxA to a high state
2h
Force EPWMxA to a low state
3h
Do nothing, no action is taken on EPWMxA.
14.4.6.3 Trip-Zone Enable Interrupt Register (TZEINT)
The trip-zone enable interrupt register (TZEINT) is shown in Figure 14-83 and described in Table 14-74.
Figure 14-83. Trip-Zone Enable Interrupt Register (TZEINT)
15
2
1
0
Reserved
3
OST
CBC
Rsvd
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-74. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
Bits
Name
15-3
Reserved
2
1
0
Value
0
OST
Reserved
Trip-zone One-Shot Interrupt Enable
0
Disable one-shot interrupt generation
1
Enable Interrupt generation; a one-shot trip event will cause a EPWMxTZINT interrupt.
CBC
Reserved
Description
Trip-zone Cycle-by-Cycle Interrupt Enable
0
Disable cycle-by-cycle interrupt generation.
1
Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt.
0
Reserved
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14.4.6.4 Trip-Zone Flag Register (TZFLG)
The trip-zone flag register (TZFLG) is shown in Figure 14-84 and described in Table 14-75.
Figure 14-84. Trip-Zone Flag Register (TZFLG)
15
3
2
1
0
Reserved
OST
CBC
INT
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-75. Trip-Zone Flag Register (TZFLG) Field Descriptions
Bits
Name
15-3
Reserved
2
Value
0
OST
Description
Reserved
Latched Status Flag for A One-Shot Trip Event.
0
No one-shot trip event has occurred.
1
Indicates a trip event has occurred on a pin selected as a one-shot trip source.
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5).
1
CBC
Latched Status Flag for Cycle-By-Cycle Trip Event
0
No cycle-by-cycle trip event has occurred.
1
Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The TZFLG[CBC]
bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present
when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the
pins is automatically cleared when the ePWM time-base counter reaches zero (TBCNT = 0000h) if the
trip condition is no longer present. The condition on the pins is only cleared when the TBCNT = 0000h
no matter where in the cycle the CBC flag is cleared.
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5).
0
INT
Latched Trip Interrupt Status Flag
0
Indicates no interrupt has been generated.
1
Indicates an EPWMxTZINT interrupt was generated because of a trip condition.
No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the interrupt flag is
cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag
bits will prevent further interrupts.
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5).
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14.4.6.5 Trip-Zone Clear Register (TZCLR)
The trip-zone clear register (TZCLR) is shown in Figure 14-85 and described in Table 14-76.
Figure 14-85. Trip-Zone Clear Register (TZCLR)
15
3
2
1
0
Reserved
OST
CBC
INT
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-76. Trip-Zone Clear Register (TZCLR) Field Descriptions
Bits
Name
15-3
Reserved
2
1
0
Value
0
OST
Description
Reserved
Clear Flag for One-Shot Trip (OST) Latch
0
Has no effect. Always reads back a 0.
1
Clears this Trip (set) condition.
CBC
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0
Has no effect. Always reads back a 0.
1
Clears this Trip (set) condition.
INT
Global Interrupt Clear Flag
0
Has no effect. Always reads back a 0.
1
Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the TZFLG[INT]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated.
Clearing all flag bits will prevent further interrupts.
14.4.6.6 Trip-Zone Force Register (TZFRC)
The trip-zone force register (TZFRC) is shown in Figure 14-86 and described in Table 14-77.
Figure 14-86. Trip-Zone Force Register (TZFRC)
15
2
1
0
Reserved
3
OST
CBC
Rsvd
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-77. Trip-Zone Force Register (TZFRC) Field Descriptions
Bits
Name
15-3
Reserved
2
1
0
Value
0
OST
Reserved
Force a One-Shot Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a one-shot trip event and sets the TZFLG[OST] bit.
CBC
Reserved
Description
Force a Cycle-by-Cycle Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
0
Reserved
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14.4.7 Event-Trigger Submodule Registers
Table 14-78 lists the memory-mapped registers for the event-trigger submodule. See your device-specific
data manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-78 should be considered as reserved locations and the register contents should not be modified.
Table 14-78. Event-Trigger Submodule Registers
Offset
Acronym
32h
ETSEL
Register Description
Event-Trigger Selection Register
Section 14.4.7.1
Section
34h
ETPS
Event-Trigger Prescale Register
Section 14.4.7.2
36h
ETFLG
Event-Trigger Flag Register
Section 14.4.7.3
38h
ETCLR
Event-Trigger Clear Register
Section 14.4.7.4
3Ah
ETFRC
Event-Trigger Force Register
Section 14.4.7.5
14.4.7.1 Event-Trigger Selection Register (ETSEL)
The event-trigger selection register (ETSEL) is shown in Figure 14-87 and described in Table 14-79.
Figure 14-87. Event-Trigger Selection Register (ETSEL)
15
4
3
2
0
Reserved
INTEN
INTSEL
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-79. Event-Trigger Selection Register (ETSEL) Field Descriptions
Bits
Name
15-4
Reserved
3
2-0
390
Value
0
INTEN
INTSEL
Description
Reserved
Enable ePWM Interrupt (EPWMx_INT) Generation
0
Disable EPWMx_INT generation
1
Enable EPWMx_INT generation
0-7h
ePWM Interrupt (EPWMx_INT) Selection Options
0
Reserved
1h
Enable event time-base counter equal to zero. (TBCNT = 0000h)
2h
Enable event time-base counter equal to period (TBCNT = TBPRD)
3h
Reserved
4h
Enable event time-base counter equal to CMPA when the timer is incrementing.
5h
Enable event time-base counter equal to CMPA when the timer is decrementing.
6h
Enable event: time-base counter equal to CMPB when the timer is incrementing.
7h
Enable event: time-base counter equal to CMPB when the timer is decrementing.
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14.4.7.2 Event-Trigger Prescale Register (ETPS)
The event-trigger prescale register (ETPS) is shown in Figure 14-88 and described in Table 14-80.
Figure 14-88. Event-Trigger Prescale Register (ETPS)
15
4
3
2
1
0
Reserved
INTCNT
INTPRD
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-80. Event-Trigger Prescale Register (ETPS) Field Descriptions
Bits
Name
15-4
Reserved
3-2
INTCNT
1-0
INTPRD
Value
0
0-3h
Description
Reserved
ePWM Interrupt Event (EPWMx_INT) Counter Register. These bits indicate how many selected
ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is
generated. If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the
counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
0
No events have occurred.
1h
1 event has occurred.
2h
2 events have occurred.
3h
3 events have occurred.
0-3h
ePWM Interrupt (EPWMx_INT) Period Select. These bits determine how many selected
ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated, the interrupt
must be enabled (ETSEL[INT] = 1). If the interrupt status flag is set from a previous interrupt
(ETFLG[INT] = 1) then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit.
This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is
generated, the ETPS[INTCNT] bits will automatically be cleared.
Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is
enabled and the status flag is clear.
Writing a INTPRD value that is less than the current counter value will result in an undefined state.
If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the
counter is incremented.
0
Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
1h
Generate an interrupt on the first event INTCNT = 01 (first event)
2h
Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
3h
Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
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14.4.7.3 Event-Trigger Flag Register (ETFLG)
The event-trigger flag register (ETFLG) is shown in Figure 14-89 and described in Table 14-81.
Figure 14-89. Event-Trigger Flag Register (ETFLG)
15
1
0
Reserved
INT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-81. Event-Trigger Flag Register (ETFLG) Field Descriptions
Bits
Name
15-1
Reserved
0
Value
0
INT
Description
Reserved
Latched ePWM Interrupt (EPWMx_INT) Status Flag
0
Indicates no event occurred
1
Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated
until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit is still set. If an
interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared. Refer to Figure 1442.
14.4.7.4 Event-Trigger Clear Register (ETCLR)
The event-trigger clear register (ETCLR) is shown in Figure 14-90 and described in Table 14-82.
Figure 14-90. Event-Trigger Clear Register (ETCLR)
15
1
0
Reserved
INT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-82. Event-Trigger Clear Register (ETCLR) Field Descriptions
Bits
Name
15-1
Reserved
0
392
Value
0
INT
Description
Reserved
ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0
Writing a 0 has no effect. Always reads back a 0.
1
Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated.
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14.4.7.5 Event-Trigger Force Register (ETFRC)
The event-trigger force register (ETFRC) is shown in Figure 14-91 and described in Table 14-83.
Figure 14-91. Event-Trigger Force Register (ETFRC)
15
1
0
Reserved
INT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-83. Event-Trigger Force Register (ETFRC) Field Descriptions
Bits
Name
15-1
Reserved
0
Value
0
INT
Description
Reserved
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The
INT flag bit will be set regardless.
0
Writing 0 to this bit will be ignored. Always reads back a 0.
1
Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.
14.4.8 High-Resolution PWM Submodule Registers
Table 14-84 lists the memory-mapped registers for the high-resolution PWM submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-84 should be considered as reserved locations and the register contents should not be
modified.
Table 14-84. High-Resolution PWM Submodule Registers
Offset
Acronym
Register Description
Section
4h
TBPHSHR
Time-Base Phase High-Resolution Register
Section 14.4.8.1
10h
CMPAHR
Counter-Compare A High-Resolution Register
Section 14.4.8.2
1040h
HRCNFG
HRPWM Configuration Register
Section 14.4.8.3
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14.4.8.1 Time-Base Phase High-Resolution Register (TBPHSHR)
The time-base phase high-resolution register (TBPHSHR) is shown in Figure 14-92 and described in
Table 14-85.
Figure 14-92. Time-Base Phase High-Resolution Register (TBPHSHR)
15
8
7
0
TBPHSH
Reserved
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-85. Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions
Bit
Field
Value
Description
15-8
TBPHSH
0-FFh
Time-base phase high-resolution bits
7-0
Reserved
0
Reserved
14.4.8.2 Counter-Compare A High-Resolution Register (CMPAHR)
The counter-compare A high-resolution register (CMPAHR) is shown in Figure 14-93 and described in
Table 14-86.
Figure 14-93. Counter-Compare A High-Resolution Register (CMPAHR)
15
8
7
0
CMPAHR
Reserved
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-86. Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions
Field
Value
Description
15-8
Bit
CMPAHR
1-FFh
Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to
enable HRPWM capabilities. Valid MEP range of operation 1-255h.
7-0
Reserved
0
394
Reserved
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14.4.8.3 HRPWM Configuration Register (HRCNFG)
The HRPWM configuration register (HRCNFG) is shown in Figure 14-94 and described in Table 14-87.
Figure 14-94. HRPWM Configuration Register (HRCNFG)
15
4
3
2
1
0
Reserved
HRLOAD
CTLMODE
EDGMODE
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-87. HRPWM Configuration Register (HRCNFG) Field Descriptions
Bit
Field
15-4
Reserved
3
HRLOAD
Value
0
Description
ReserveD
Shadow mode bit: Selects the time event that loads the CMPAHR shadow value into the active register:
0
CTR = 0 (counter equals zero)
1
CTR = PRD (counter equal period)
Note: Load mode selection is valid only if CTLMODE = 0 has been selected. You should select this event
to match the selection of the CMPA load mode (CMPCTL[LOADMODE] bits) in the EPWM module as
follows:
2
1-0
CTLMODE
EDGMODE
0
Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h
Load on either CTR = 0 or CTR = PRD (should not be used with HRPWM)
3h
Freeze (no loads possible – should not be used with HRPWM)
Control Mode Bits: Selects the register (CMP or TBPHS) that controls the MEP:
0
CMPAHR(8) Register controls the edge position (this is duty control mode). (default on reset)
1
TBPHSHR(8) Register controls the edge position (this is phase control mode).
0-3h
Edge Mode Bits: Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic:
0
HRPWM capability is disabled (default on reset)
1h
MEP control of rising edge
2h
MEP control of falling edge
3h
MEP control of both edges
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Chapter 15
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Enhanced Quadrature Encoder Pulse (eQEP) Module
The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary
incremental encoder to get position, direction, and speed information from a rotating machine for use in a
high-performance motion and position-control system. This chapter describes the eQEP.
Topic
15.1
15.2
15.3
396
...........................................................................................................................
Page
Introduction ..................................................................................................... 397
Architecture ..................................................................................................... 400
eQEP Registers ................................................................................................ 418
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15.1 Introduction
A single track of slots patterns the periphery of an incremental encoder disk, as shown in Figure 15-1.
These slots create an alternating pattern of dark and light lines. The disk count is defined as the number
of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to
generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an
absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position, and zero reference.
Figure 15-1. Optical Encoder Disk
QEPA
QEPB
QEPI
To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of
phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The
clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB
channel and vise versa as shown in Figure 15-2.
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at
a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from
the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can
determine the velocity of the motor.
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Figure 15-2. QEP Encoder Output Signal for Forward/Reverse Movement
T0
Clockwise shaft rotation/forward movement
0
1
2
3
4
5
6
7
N−6 N−5 N−4 N−3 N−2 N−1
0
QEPA
QEPB
QEPI
T0
Anti-clockwise shaft rotation/reverse movement
0
N−1 N−2 N−3 N−4 N−5 N−6 N−7
6
5
4
3
2
1
0
N−1 N−2
QEPA
QEPB
QEPI
Legend: N = lines per revolution
Quadrature encoders from different manufacturers come with two forms of index pulse (gated index pulse
or ungated index pulse) as shown in Figure 15-3. A nonstandard form of index pulse is ungated. In the
ungated configuration, the index edges are not necessarily coincident with A and B signals. The gated
index pulse is aligned to any of the four quadrature edges and width of the index pulse and can be equal
to a quarter, half, or full period of the quadrature signal.
Figure 15-3. Index Pulse Example
T0
QEPA
QEPB
0.25T0 ±0.1T0
QEPI
(gated to
A and B)
0.5T0 ±0.1T0
QEPI
(gated to A)
T0 ±0.5T0
QEPI
(ungated)
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Some typical applications of shaft encoders include robotics and even computer input in the form of a
mouse. Inside your mouse you can see where the mouse ball spins a pair of axles (a left/right, and an
up/down axle). These axles are connected to optical shaft encoders that effectively tell the computer how
fast and in what direction the mouse is moving.
General Issues: Estimating velocity from a digital position sensor is a cost-effective strategy in motor
control. Two different first order approximations for velocity may be written as:
x(k) * x(k * 1)
v(k) [
+ DX
T
T
X
v(k) [
+ X
t(k) * t(k * 1)
DT
(1)
(2)
where
v(k): Velocity at time instant k
x(k): Position at time instant k
x(k-1): Position at time instant k - 1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
t(k): Time instant "k"
t(k-1): Time instant "k - 1"
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement.
Equation 1 is the conventional approach to velocity estimation and it requires a time base to provide unit
time event for velocity calculation. Unit time is basically the inverse of the velocity calculation rate.
The encoder count (position) is read once during each unit time event. The quantity [x(k) - x(k-1)] is
formed by subtracting the previous reading from the current reading. Then the velocity estimate is
computed by multiplying by the known constant 1/T (where T is the constant time between unit time
events and is known in advance).
Estimation based on Equation 1 has an inherent accuracy limit directly related to the resolution of the
position sensor and the unit time period T. For example, consider a 500-line per revolution quadrature
encoder with a velocity calculation rate of 400 Hz. When used for position the quadrature encoder gives a
four-fold increase in resolution, in this case, 2000 counts per revolution. The minimum rotation that can be
detected is therefore 0.0005 revolutions, which gives a velocity resolution of 12 rpm when sampled at 400
Hz. While this resolution may be satisfactory at moderate or high speeds, for example, 1% error at
1200 rpm, it would clearly prove inadequate at low speeds. In fact, at speeds below 12 rpm, the speed
estimate would erroneously be zero much of the time.
At low speed, Equation 2 provides a more accurate approach. It requires a position sensor that outputs a
fixed interval pulse train, such as the aforementioned quadrature encoder. The width of each pulse is
defined by motor speed for a given sensor resolution. Equation 2 can be used to calculate motor speed by
measuring the elapsed time between successive quadrature pulse edges. However, this method suffers
from the opposite limitation, as does Equation 1. A combination of relatively large motor speeds and high
sensor resolution makes the time interval ΔT small, and thus more greatly influenced by the timer
resolution. This can introduce considerable error into high-speed estimates.
For systems with a large speed range (that is, speed estimation is needed at both low and high speeds),
one approach is to use Equation 2 at low speed and have the DSP software switch over to Equation 1
when the motor speed rises above some specified threshold.
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15.2 Architecture
This section provides the eQEP inputs and functional description.
NOTE: Multiple identical eQEP modules can be contained in a system. The number of modules is
device-dependent and is based on target application needs. In this document, the letter x
within a signal or module name is used to indicate a generic eQEP instance on a device.
15.2.1 EQEP Inputs
The eQEP inputs include two pins for quadrature-clock mode or direction-count mode, an index (or 0
marker), and a strobe input.
• QEPA/XCLK and QEPB/XDIR: These two pins can be used in quadrature-clock mode or directioncount mode.
– Quadrature-clock Mode: The eQEP encoders provide two square wave signals (A and B) 90
electrical degrees out of phase whose phase relationship is used to determine the direction of
rotation of the input shaft and number of eQEP pulses from the index position to derive the relative
position information. For forward or clockwise rotation, QEPA signal leads QEPB signal and vice
versa. The quadrature decoder uses these two inputs to generate quadrature-clock and direction
signals.
– Direction-count Mode: In direction-count mode, direction and clock signals are provided directly
from the external source. Some position encoders have this type of output instead of quadrature
output. The QEPA pin provides the clock input and the QEPB pin provides the direction input.
• QEPI: Index or Zero Marker: The eQEP encoder uses an index signal to assign an absolute start
position from which position information is incrementally encoded using quadrature pulses. This pin is
connected to the index output of the eQEP encoder to optionally reset the position counter for each
revolution. This signal can be used to initialize or latch the position counter on the occurrence of a
desired event on the index pin.
• QEPS: Strobe Input: This general-purpose strobe signal can initialize or latch the position counter on
the occurrence of a desired event on the strobe pin. This signal is typically connected to a sensor or
limit switch to notify that the motor has reached a defined position.
15.2.2 Functional Description
The eQEP peripheral contains the following major functional units (as shown in Figure 15-4):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
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Figure 15-4. Functional Block Diagram of the eQEP Peripheral
System
control registers
To CPU
EQEPxENCLK
Data bus
SYSCLKOUT
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
Registers
used by
multiple units
QWDTMR
QWDPRD
32
QEPCTL
QEPSTS
QFLG
UTIME
16
UTOUT
QDECCTL
QWDOG
16
WDTOUT
Interrupt
Controller
EQEPxINT
32
QCLK
QDIR
QI
QS
PHE
Position counter/
control unit
(PCCU)
QPOSLAT
QPOSSLAT
QPOSILAT
Quadrature
decoder
(QDU)
PCSOUT
32
QPOSCNT
QPOSINIT
QPOSMAX
32
QPOSCMP
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
EQEPxA/XCLK
EQEPxB/XDIR
GPIO
MUX
EQEPxI
EQEPxS
16
QEINT
QFRC
QCLR
QPOSCTL
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15.2.3 Quadrature Decoder Unit (QDU)
Figure 15-5 shows a functional block diagram of the QDU.
Figure 15-5. Functional Block Diagram of Decoder Unit
QFLG:PHE
QEPSTS:QDF
QDECCTL:SWAP
QDECCTL:QAP
PHE
00
01
QCLK
10
11
iCLK
xCLK
xCLK
xCLK
QA
QDIR
10
11
EQEPxAIN
0
1
1
Quadrature
decoder
EQEPB
QB
00
01
0
EQEPA
EQEPxBIN
0
0
1
iDIR
xDIR
1
QDECCTL:QBP
1
0
x1
x2
x1, x2
2
QDECCTL:XCR
QDECCTL:QSRC
QDECCTL:QIP
EQEPxIIN
0
0
QI
1
1
QDECCTL:IGATE
EQEPxSIN
0
QS
1
QDECCTL:QSP
QDECCTL:SPSEL
EQEPxIOUT
0
PCSOUT
EQEPxSOUT
1
QDECCTL:SPSEL
EQEPxIOE
0
QDECCTL:SOEN
EQEPxSOE
1
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15.2.3.1 Position Counter Input Modes
Clock and direction input to position counter is selected using the QSRC bit in the eQEP decoder control
register (QDECCTL), based on interface input requirement as follows:
• Quadrature-count mode
• Direction-count mode
• UP-count mode
• DOWN-count mode
15.2.3.1.1 Quadrature Count Mode
The quadrature decoder generates the direction and clock to the position counter in quadrature count
mode.
Direction Decoding— The direction decoding logic of the eQEP circuit determines which one of the
sequences (QEPA, QEPB) is the leading sequence and accordingly updates the direction
information in the QDF bit in the eQEP status register (QEPSTS). Table 15-1 and Figure 15-6 show
the direction decoding logic in truth table and state machine form. Both edges of the QEPA and
QEPB signals are sensed to generate count pulses for the position counter. Therefore, the
frequency of the clock generated by the eQEP logic is four times that of each input sequence.
Figure 15-7 shows the direction decoding and clock generation from the eQEP input signals.
Phase Error Flag— In normal operating conditions, quadrature inputs QEPA and QEPB will be 90
degrees out of phase. The phase error flag (PHE) is set in the QFLG register when edge transition
is detected simultaneously on the QEPA and QEPB signals to optionally generate interrupts. State
transitions marked by dashed lines in Figure 15-6 are invalid transitions that generate a phase
error.
Count Multiplication— The eQEP position counter provides 4x times the resolution of an input clock by
generating a quadrature-clock (QCLK) on the rising/falling edges of both eQEP input clocks (QEPA
and QEPB) as shown in Figure 15-7.
Reverse Count— In normal quadrature count operation, QEPA input is fed to the QA input of the
quadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder. Reverse
counting is enabled by setting the SWAP bit in the eQEP decoder control register (QDECCTL). This
will swap the input to the quadrature decoder thereby reversing the counting direction.
Table 15-1. Quadrature Decoder Truth Table
Previous Edge
Present Edge
QDIR
QPOSCNT
QA↑
QB↑
UP
Increment
QB↓
DOWN
Decrement
QA↓
TOGGLE
QB↓
UP
Increment
QB↑
DOWN
Decrement
QA↑
TOGGLE
QA↑
DOWN
Increment
QA↓
UP
Decrement
QB↓
TOGGLE
QA↓
DOWN
Increment
QA↑
UP
Decrement
QB↑
TOGGLE
QA↓
QB↑
QB↓
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Figure 15-6. Quadrature Decoder State Machine
(A,B)=
(00)
Increment
counter
(11)
(10)
Increment
counter
10
(01)
Decrement
counter
QEPA
Decrement
counter
00
QEPB
11
Decrement
counter
Decrement
counter
01
eQEP signals
Increment
counter
Increment
counter
Figure 15-7. Quadrature-clock and Direction Decoding
QA
QB
QCLK
QDIR
QPOSCNT
+1 +1 +1 +1 +1 +1
+1
−1 −1 −1 −1 −1 −1 −1 −1 −1 −1
−1
+1 +1 +1
−1 −1 −1 −1 −1 −1
−1
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1
+1
−1 −1 −1
QA
QB
QCLK
QDIR
QPOSCNT
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15.2.3.1.2 Direction-count Mode
Some position encoders provide direction and clock outputs, instead of quadrature outputs. In such cases,
direction-count mode can be used. QEPA input will provide the clock for position counter and the QEPB
input will have the direction information. The position counter is incremented on every rising edge of a
QEPA input when the direction input is high and decremented when the direction input is low.
15.2.3.1.3 Up-Count Mode
The counter direction signal is hard-wired for up count and the position counter is used to measure the
frequency of the QEPA input. Setting of the XCR bit in the eQEP decoder control register (QDECCTL)
enables clock generation to the position counter on both edges of the QEPA input, thereby increasing the
measurement resolution by 2× factor.
15.2.3.1.4 Down-Count Mode
The counter direction signal is hardwired for a down count and the position counter is used to measure the
frequency of the QEPA input. Setting of the XCR bit in the eQEP decoder control register (QDECCTL)
enables clock generation to the position counter on both edges of a QEPA input, thereby increasing the
measurement resolution by 2× factor.
15.2.3.2 eQEP Input Polarity Selection
Each eQEP input can be inverted using the in the eQEP decoder control register (QDECCTL[8:5]) control
bits. As an example, setting of the QIP bit in QDECCTL inverts the index input.
15.2.3.3 Position-Compare Sync Output
The eQEP peripheral includes a position-compare unit that is used to generate the position-compare sync
signal on compare match between the position counter register (QPOSCNT) and the position-compare
register (QPOSCMP). This sync signal can be output using an index pin or strobe pin of the EQEP
peripheral.
Setting the SOEN bit in the eQEP decoder control register (QDECCTL) enables the position-compare
sync output and the SPSEL bit in QDECCTL selects either an eQEP index pin or an eQEP strobe pin.
15.2.4 Position Counter and Control Unit (PCCU)
The position counter and control unit provides two configuration registers (QEPCTL and QPOSCTL) for
setting up position counter operational modes, position counter initialization/latch modes and positioncompare logic for sync signal generation.
15.2.4.1 Position Counter Operating Modes
Position counter data may be captured in different manners. In some systems, the position counter is
accumulated continuously for multiple revolutions and the position counter value provides the position
information with respect to the known reference. An example of this is the quadrature encoder mounted on
the motor controlling the print head in the printer. Here the position counter is reset by moving the print
head to the home position and then position counter provides absolute position information with respect to
home position.
In other systems, the position counter is reset on every revolution using index pulse and position counter
provides rotor angle with respect to index pulse position.
Position counter can be configured to operate in following four modes
• Position Counter Reset on Index Event
• Position Counter Reset on Maximum Position
• Position Counter Reset on the first Index Event
• Position Counter Reset on Unit Time Out Event (Frequency Measurement)
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In all the above operating modes, position counter is reset to 0 on overflow and to QPOSMAX register
value on underflow. Overflow occurs when the position counter counts up after QPOSMAX value.
Underflow occurs when position counter counts down after "0". Interrupt flag is set to indicate
overflow/underflow in QFLG register.
15.2.4.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
If the index event occurs during the forward movement, then position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to
the value in the QPOSMAX register on the next eQEP clock.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index
marker so that same relative quadrature transition is used for index event reset operation.
For example, if the first reset operation occurs on the falling edge of QEPB during the forward direction,
then all the subsequent reset must be aligned with the falling edge of QEPB for the forward rotation and
on the rising edge of QEPB for the reverse rotation as shown in Figure 15-8.
The position-counter value is latched to the QPOSILAT register and direction information is recorded in
the QEPSTS[QDLF] bit on every index event marker. The position-counter error flag (QEPSTS[PCEF])
and error interrupt flag (QFLG[PCE]) are set if the latched value is not equal to 0 or QPOSMAX. The
position-counter error flag (QEPSTS[PCEF]) is updated on every index event marker and an interrupt flag
(QFLG[PCE]) will be set on error that can be cleared only through software.
The index event latch configuration QEPCTL[IEL] bits are ignored in this mode and position counter error
flag/interrupt flag are generated only in index event reset mode.
Figure 15-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)
QA
QB
QI
QCLK
QEPSTS:QDF
F9F
F9D
QPOSCNT F9C
Index interrupt/
index event
marker
F9F
0
1
2
3
4
5
4
3
2
1
F9D
F9E
F9E
QPOSILAT
F9B
F99
F97
0
F9F
F9C
F9A
F98
0
QEPSTS:QDLF
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15.2.4.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
If the position counter is equal to QPOSMAX, then the position counter is reset to 0 on the next eQEP
clock for forward movement and position counter overflow flag is set. If the position counter is equal to
ZERO, then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement and
position counter underflow flag is set. Figure 15-9 shows the position counter reset operation in this mode.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in the QEPSTS registers; it also remembers the quadrature edge on the first
index marker so that the same relative quadrature transition is used for the software index marker
(QEPCTL[IEL]=11).
Figure 15-9. Position Counter Underflow/Overflow (QPOSMAX = 4)
QA
QB
QCLK
QDIR
QPOSCNT
1
2
3
4
0
1
2
1
0
4
3
2
1
0
4
3
2
1
2
3
4
1
0
4
3
2
1
0
1
2
3
4
0
1
2
3
4
0
1
0
4
3
0
OV/UF
QA
QB
QCLK
QDIR
QPOSCNT
OV/UF
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15.2.4.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
If the index event occurs during forward movement, then the position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to
the value in the QPOSMAX register on the next eQEP clock. Note that this is done only on the first
occurrence and subsequently the position counter value is not reset on an index event; rather, it is reset
based on maximum position as described in Section 15.2.4.1.2.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in QEPSTS registers. It also remembers the quadrature edge on the first index
marker so that same relative quadrature transition is used for software index marker (QEPCTL[IEL]=11).
15.2.4.1.4 Position Counter Reset on Unit Time out Event (QEPCTL[PCRM] = 11)
In this mode, the QPOSCNT value is latched to the QPOSLAT register and then the QPOSCNT is reset
(to 0 or QPOSMAX, depending on the direction mode selected by QDECCTL[QSRC] bits on a unit time
event). This is useful for frequency measurement.
15.2.4.2 Position Counter Latch
The eQEP index and strobe input can be configured to latch the position counter (QPOSCNT) into
QPOSILAT and QPOSSLAT, respectively, on occurrence of a definite event on these pins.
15.2.4.2.1 Index Event Latch
In some applications, it may not be desirable to reset the position counter on every index event and
instead it may be required to operate the position counter in full 32-bit mode (QEPCTL[PCRM] = 01 and
QEPCTL[PCRM] = 10 modes).
In such cases, the eQEP position counter can be configured to latch on the following events and direction
information is recorded in the QEPSTS[QDLF] bit on every index event marker.
• Latch on Rising edge (QEPCTL[IEL] = 01)
• Latch on Falling edge (QEPCTL[IEL] = 10)
• Latch on Index Event Marker (QEPCTL[IEL] = 11)
This is particularly useful as an error checking mechanism to check if the position counter accumulated
the correct number of counts between index events. As an example, the 1000-line encoder must count
4000 times when moving in the same direction between the index events.
The index event latch interrupt flag (QFLG[IEL]) is set when the position counter is latched to the
QPOSILAT register. The index event latch configuration bits (QEPCTZ[IEL]) are ignored when
QEPCTL[PCRM] = 00.
Latch on Rising Edge (QEPCTL[IEL] = 01)— The position counter value (QPOSCNT) is latched to the
QPOSILAT register on every rising edge of an index input.
Latch on Falling Edge (QEPCTL[IEL] = 10)— The position counter value (QPOSCNT) is latched to the
QPOSILAT register on every falling edge of index input.
Latch on Index Event Marker/Software Index Marker (QEPCTL[IEL] = 11)— The first index marker is
defined as the quadrature edge following the first index edge. The eQEP peripheral records the
occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker
(QEPSTS[FIDF]) in the QEPSTS registers. It also remembers the quadrature edge on the first
index marker so that same relative quadrature transition is used for latching the position counter
(QEPCTL[IEL] = 11).
Figure 15-10 shows the position counter latch using an index event marker.
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Figure 15-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)
QA
QB
QI
QCLK
QEPSTS:QDF
F9D
F9F
FA1
FA3
FA4
QPOSCNT F9C
FA2
FA0
F9E
F9C
F9A
F98
FA5
F9E
FA0
FA2
FA4
F97
FA3
FA1
F9F
F9D
F9B
F99
Index interrupt/
index event
marker
QPOSILAT
F9F
0
QEPSTS:QDLF
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15.2.4.2.2 Strobe Event Latch
The position-counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by
clearing the QEPCTL[SEL] bit.
If the QEPCTL[SEL] bit is set, then the position counter value is latched to the QPOSSLAT register on the
rising edge of the strobe input for forward direction and on the falling edge of the strobe input for reverse
direction as shown in Figure 15-11.
The strobe event latch interrupt flag (QFLG[SEL]) is set when the position counter is latched to the
QPOSSLAT register.
Figure 15-11. Strobe Event Latch (QEPCTL[SEL] = 1)
QA
QB
QS
QCLK
QEPST:QDF
F9D
F9F
FA1
FA3
FA4
QPOSCNT F9C
F9E
FA0
FA2
FA4
QIPOSSLAT
410
FA2
FA0
F9E
F9C
F9A
F98
FA5
F97
FA3
FA1
F9F
F9F
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F9B
F99
F9F
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15.2.4.3 Position Counter Initialization
The position counter can be initialized using following events:
• Index event
• Strobe event
• Software initialization
Index Event Initialization (IEI)— The QEPI index input can be used to trigger the initialization of the
position counter at the rising or falling edge of the index input.
If the QEPCTL[IEI] bits are 10, then the position counter (QPOSCNT) is initialized with a value in
the QPOSINIT register on the rising edge of strobe input for forward direction and on the falling
edge of strobe input for reverse direction.
The index event initialization interrupt flag (QFLG[IEI]) is set when the position counter is initialized
with a value in the QPOSINIT register.
Strobe Event Initialization (SEI)— If the QEPCTL[SEI] bits are 10, then the position counter is initialized
with a value in the QPOSINIT register on the rising edge of strobe input.
If the QEPCTL[SEL] bits are 11, then the position counter (QPOSCNT) is initialized with a value in
the QPOSINIT register on the rising edge of strobe input for forward direction and on the falling
edge of strobe input for reverse direction.
The strobe event initialization interrupt flag (QFLG[SEI]) is set when the position counter is
initialized with a value in the QPOSINIT register.
Software Initialization (SWI)— The position counter can be initialized in software by writing a 1 to the
QEPCTL[SWI] bit, which will automatically be cleared after initialization.
15.2.4.4 eQEP Position-compare Unit
The eQEP peripheral includes a position-compare unit that is used to generate a sync output and/or
interrupt on a position-compare match. Figure 15-12 shows a diagram. The position-compare
(QPOSCMP) register is shadowed and shadow mode can be enabled or disabled using the
QPOSCTL[PSSHDW] bit. If the shadow mode is not enabled, the CPU writes directly to the active position
compare register.
Figure 15-12. eQEP Position-compare Unit
QPOSCTL:PCSHDW
QPOSCTL:PCLOAD
QPOSCMP
QFLG:PCR
QFLG:PCM
QPOSCTL:PCSPW
QPOSCTL:PCPOL
8
32
PCEVENT
Pulse
stretcher
0
32
PCSOUT
1
QPOSCNT
In shadow mode, you can configure the position-compare unit (QPOSCTL[PCLOAD]) to load the shadow
register value into the active register on the following events and to generate the position-compare ready
(QFLG[PCR]) interrupt after loading.
• Load on compare match
• Load on position-counter zero event
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The position-compare match (QFLG[PCM]) is set when the position-counter value (QPOSCNT) matches
with the active position-compare register (QPOSCMP) and the position-compare sync output of the
programmable pulse width is generated on compare match to trigger an external device.
For example, if QPOSCMP = 2, the position-compare unit generates a position-compare event on 1 to 2
transitions of the eQEP position counter for forward counting direction and on 3 to 2 transitions of the
eQEP position counter for reverse counting direction (see Figure 15-13).
Figure 15-35 shows the layout of the eQEP Position-Compare Control Register (QPOSCTL) and Table 1517 describes the QPOSCTL bit fields.
Figure 15-13. eQEP Position-compare Event Generation Points
4
3
3
2
eQEP counter
4
3
2
1
1
0
3
2
2
1
POSCMP=2
1
0
0
PCEVNT
PCSOUT (active HIGH)
PCSPW
PCSOUT (active LOW)
The pulse stretcher logic in the position-compare unit generates a programmable position-compare sync
pulse output on the position-compare match. In the event of a new position-compare match while a
previous position-compare pulse is still active, then the pulse stretcher generates a pulse of specified
duration from the new position-compare event as shown in Figure 15-14.
Figure 15-14. eQEP Position-compare Sync Output Pulse Stretcher
DIR
QPOSCMP
QPOSCNT
PCEVNT
PCSPW
PCSPW
PCSPW
PCSOUT (active HIGH)
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15.2.5 eQEP Edge Capture Unit
The eQEP peripheral includes an integrated edge capture unit to measure the elapsed time between the
unit position events as shown in Figure 15-15. This feature is typically used for low speed measurement
using the following equation:
X
v(k) +
+ X
t(k) * t(k * 1)
DT
(3)
where,
• X - Unit position is defined by integer multiple of quadrature edges (see Figure 15-16)
• ΔT - Elapsed time between unit position events
• v(k) - Velocity at time instant "k"
The eQEP capture timer (QCTMR) runs from prescaled SYSCLKOUT and the prescaler is programmed
by the QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register
(QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
QEPSTS[UPEVNT] to indicate that new value is latched into the QCPRD register. Software can check this
status flag before reading the period register for low speed measurement and clear the flag by writing 1.
Time measurement (ΔT) between unit position events will be correct if the following conditions are met:
• No more than 65,535 counts have occurred between unit position events.
• No direction change between unit position events.
The capture unit sets the eQEP overflow error flag (QEPSTS[COEF]) in the event of capture timer
overflow between unit position events. If a direction change occurs between the unit position events, then
an error flag is set in the status register (QEPSTS[CDEF]).
Capture Timer (QCTMR) and Capture period register (QCPRD) can be configured to latch on following
events.
• CPU read of QPOSCNT register
• Unit time-out event
If the QEPCTL[QCLM] bit is cleared, then the capture timer and capture period values are latched into the
QCTMRLAT and QCPRDLAT registers, respectively, when the CPU reads the position counter
(QPOSCNT).
If the QEPCTL[QCLM] bit is set, then the position counter, capture timer, and capture period values are
latched into the QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out.
Figure 15-17 shows the capture unit operation along with the position counter.
NOTE:
The QCAPCTL register should not be modified dynamically (such as switching CAPCLK
prescaling mode from QCLK/4 to QCLK/8). The capture unit must be disabled before
changing the prescaler.
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Figure 15-15. eQEP Edge Capture Unit
16
0xFFFF
QEPSTS:COEF
16
QCTMR
QCPRD
QCAPCTL:CCPS
16
3
SYSCLKOUT
3-bit binary
divider
x1, 1/2, 1/4...,
1/128
CAPCLK
16
Capture timer
control unit
(CTCU)
QCAPCTL:CEN
QCAPCTL:UPPS
QCTMRLAT
QCPRDLAT
QEPSTS:UPEVNT
UPEVNT
QEPSTS:CDEF
4
4-bit binary
divider
x1, 1/2, 1/4...,
1/2048
Rising/falling
edge detect
QCLK
QDIR
UTIME
QEPCTL:UTE
SYSCLKOUT
QFLG:UTO
QUTMR
UTOUT
QUPRD
Figure 15-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
P
QA
QB
QCLK
UPEVNT
X=N x P
N - Number of quadrature periods selected using QCAPCTL[UPPS] bits
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Figure 15-17. eQEP Edge Capture Unit - Timing Details
QEPA
QEPB
QCLK
QPOSCNT
x(k)
∆X
x(k−1)
UPEVNT
t(k)
∆T
QCTMR
t(k−1)
T
UTOUT
Velocity Calculation Equations:
x(k) * x(k * 1)
v(k) +
+ DX or
T
T
(4)
where
v(k): Velocity at time instant k
x(k): Position at time instant k
x(k-1): Position at time instant k - 1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement
t(k): Time instant "k"
t(k-1): Time instant "k - 1"
Unit time (T) and unit period (X) are configured using the QUPRD and QCAPCTL[UPPS] registers.
Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT
registers.
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Parameter
Relevant Register to Configure or Read the Information
T
Unit Period Register (QUPRD)
Incremental Position = QPOSLAT(k) - QPOSLAT(K - 1)
ΔX
X
Fixed unit position defined by sensor resolution and ZCAPCTL[UPPS] bits
Capture Period Latch (QCPRDLAT)
ΔT
15.2.6 eQEP Watchdog
The eQEP peripheral contains a 16-bit watchdog timer that monitors the quadrature-clock to indicate
proper operation of the motion-control system. The eQEP watchdog timer is clocked from
SYSCLKOUT/64 and the quadrate clock event (pulse) resets the watchdog timer. If no quadrature-clock
event is detected until a period match (QWDPRD = QWDTMR), then the watchdog timer will time out and
the watchdog interrupt flag will be set (QFLG[WTO]). The time-out value is programmable through the
watchdog period register (QWDPRD).
Figure 15-18. eQEP Watchdog Timer
QWDOG
QEPCTL:WDE
SYSCLKOUT
/64
SYSCLKOUT
QWDTMR
16
QCLK
RESET
WDTOUT
16
QWDPRD
416
Enhanced Quadrature Encoder Pulse (eQEP) Module
QFLG:WTO
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15.2.7 Unit Timer Base
The eQEP peripheral includes a 32-bit timer (QUTMR) that is clocked by SYSCLKOUT to generate
periodic interrupts for velocity calculations. The unit time out interrupt is set (QFLG[UTO]) when the unit
timer (QUTMR) matches the unit period register (QUPRD).
The eQEP peripheral can be configured to latch the position counter, capture timer, and capture period
values on a unit time out event so that latched values are used for velocity calculation as described in
Section Section 15.2.5.
Figure 15-19. eQEP Unit Time Base
UTIME
QEPCTL:UTE
SYSCLKOUT
QUTMR
32
UTOUT
32
QUPRD
QFLG:UTO
15.2.8 eQEP Interrupt Structure
Figure 15-20 shows how the interrupt mechanism works in the EQEP module.
Figure 15-20. EQEP Interrupt Generation
Set
Clr
Latch
QEINT:PCE
QCLR:INT
Clr
QFLG:INT
QCLR:PCE
Latch
Set
EQEPxINT
Pulse
generator
when
input=1
0
0
QFRC:PCE
PCE
QFLG:PCE
1
QEINT:UTO
clr
QCLR:UTO
Latch
set
QFRC:UTO
UTO
QFLG:UTO
Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL, and UTO) can be
generated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated only to the interrupt controller if any of the
interrupt events is enabled, the flag bit is 1 and the INT flag bit is 0. The interrupt service routine will need
to clear the global interrupt flag bit and the serviced event, via the interrupt clear register (QCLR), before
any other interrupt pulses are generated. You can force an interrupt event by way of the interrupt force
register (QFRC), which is useful for test purposes.
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15.3 eQEP Registers
Table 15-2 lists the registers with their memory locations, sizes, and reset values.
Table 15-2. eQEP Registers
Offset
418
Acronym
Register Description
Size(×16)/ #shadow
Section
0h
QPOSCNT
eQEP Position Counter Register
2/0
Section 15.3.1
4h
QPOSINIT
eQEP Position Counter Initialization Register
2/0
Section 15.3.2
8h
QPOSMAX
eQEP Maximum Position Count Register
2/0
Section 15.3.3
Ch
QPOSCMP
eQEP Position-Compare Register
2/1
Section 15.3.4
10h
QPOSILAT
eQEP Index Position Latch Register
2/0
Section 15.3.5
14h
QPOSSLAT
eQEP Strobe Position Latch Register
2/0
Section 15.3.6
18h
QPOSLAT
eQEP Position Counter Latch Register
2/0
Section 15.3.7
1Ch
QUTMR
eQEP Unit Timer Register
2/0
Section 15.3.8
20h
QUPRD
eQEP Unit Period Register
2/0
Section 15.3.9
24h
QWDTMR
eQEP Watchdog Timer Register
1/0
Section 15.3.10
26h
QWDPRD
eQEP Watchdog Period Register
1/0
Section 15.3.11
28h
QDECCTL
eQEP Decoder Control Register
1/0
Section 15.3.12
2Ah
QEPCTL
eQEP Control Register
1/0
Section 15.3.13
2Ch
QCAPCTL
eQEP Capture Control Register
1/0
Section 15.3.14
2Eh
QPOSCTL
eQEP Position-Compare Control Register
1/0
Section 15.3.15
30h
QEINT
eQEP Interrupt Enable Register
1/0
Section 15.3.16
32h
QFLG
eQEP Interrupt Flag Register
1/0
Section 15.3.17
34h
QCLR
eQEP Interrupt Clear Register
1/0
Section 15.3.18
36h
QFRC
eQEP Interrupt Force Register
1/0
Section 15.3.19
38h
QEPSTS
eQEP Status Register
1/0
Section 15.3.20
3Ah
QCTMR
eQEP Capture Timer Register
1/0
Section 15.3.21
3Ch
QCPRD
eQEP Capture Period Register
1/0
Section 15.3.22
3Eh
QCTMRLAT
eQEP Capture Timer Latch Register
1/0
Section 15.3.23
40h
QCPRDLAT
eQEP Capture Period Latch Register
1/0
Section 15.3.24
5Ch
REVID
eQEP Revision ID Register
2/0
Section 15.3.25
Enhanced Quadrature Encoder Pulse (eQEP) Module
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15.3.1 eQEP Position Counter Register (QPOSCNT)
Figure 15-21. eQEP Position Counter Register (QPOSCNT)
31
0
QPOSCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-3. eQEP Position Counter Register (QPOSCNT) Field Descriptions
Bits
Name
31-0
QPOSCNT
Value
0-FFFF FFFFh
Description
This 32-bit position counter register counts up/down on every eQEP pulse based on direction
input. This counter acts as a position integrator whose count value is proportional to position
from a give reference point.
15.3.2 eQEP Position Counter Initialization Register (QPOSINIT)
Figure 15-22. eQEP Position Counter Initialization Register (QPOSINIT)
31
0
QPOSINIT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-4. eQEP Position Counter Initialization Register (QPOSINIT) Field Descriptions
Bits
Name
31-0
QPOSINIT
Value
0-FFFF FFFFh
Description
This register contains the position value that is used to initialize the position counter based on
external strobe or index event. The position counter can be initialized through software.
15.3.3 eQEP Maximum Position Count Register (QPOSMAX)
Figure 15-23. eQEP Maximum Position Count Register (QPOSMAX)
31
0
QPOSMAX
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-5. eQEP Maximum Position Count Register (QPOSMAX) Field Descriptions
Bits
Name
31-0
QPOSMAX
Value
0-FFFF FFFFh
Description
This register contains the maximum position counter value.
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15.3.4 eQEP Position-Compare Register (QPOSCMP)
Figure 15-24. eQEP Position-Compare Register (QPOSCMP)
31
0
QPOSCMP
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-6. eQEP Position-C