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Texas Instruments TMS320C6746 DSP (Rev. C) User guides
TMS320C6746 DSP
Technical Reference Manual
Literature Number: SPRUH80C
April 2013 – Revised September 2016
Contents
Preface....................................................................................................................................... 72
1
Overview ........................................................................................................................... 73
1.1
1.2
2
DSP Subsystem ................................................................................................................. 75
2.1
2.2
2.3
2.4
3
Introduction .................................................................................................................. 84
System Interconnect Block Diagram ..................................................................................... 85
Introduction .................................................................................................................. 87
DSP Memories.............................................................................................................. 87
Peripherals .................................................................................................................. 87
Memory Protection Unit (MPU) ............................................................................................. 88
5.1
5.2
5.3
2
76
77
77
77
82
82
82
82
System Memory ................................................................................................................. 86
4.1
4.2
4.3
5
Introduction ..................................................................................................................
TMS320C674x Megamodule .............................................................................................
2.2.1 Internal Memory Controllers .....................................................................................
2.2.2 Internal Peripherals ...............................................................................................
Memory Map ................................................................................................................
2.3.1 DSP Internal Memory .............................................................................................
2.3.2 External Memory ..................................................................................................
Advanced Event Triggering (AET) .......................................................................................
System Interconnect ........................................................................................................... 83
3.1
3.2
4
Introduction .................................................................................................................. 74
DSP Subsystem ............................................................................................................ 74
Introduction .................................................................................................................. 89
5.1.1 Purpose of the MPU .............................................................................................. 89
5.1.2 Features ............................................................................................................ 89
5.1.3 Block Diagram ..................................................................................................... 89
5.1.4 MPU Default Configuration....................................................................................... 90
Architecture ................................................................................................................. 90
5.2.1 Privilege Levels .................................................................................................... 90
5.2.2 Memory Protection Ranges ...................................................................................... 91
5.2.3 Permission Structures ............................................................................................ 91
5.2.4 Protection Check .................................................................................................. 93
5.2.5 DSP L1/L2 Cache Controller Accesses ........................................................................ 93
5.2.6 MPU Register Protection ......................................................................................... 93
5.2.7 Invalid Accesses and Exceptions ............................................................................... 94
5.2.8 Reset Considerations ............................................................................................. 94
5.2.9 Interrupt Support .................................................................................................. 94
5.2.10 Emulation Considerations ....................................................................................... 94
MPU Registers.............................................................................................................. 95
5.3.1 Revision Identification Register (REVID) ....................................................................... 96
5.3.2 Configuration Register (CONFIG) ............................................................................... 97
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) .............................................................. 98
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ........................................................... 99
5.3.5 Interrupt Enable Set Register (IENSET) ...................................................................... 100
5.3.6 Interrupt Enable Clear Register (IENCLR) ................................................................... 100
Contents
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5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
6
101
101
102
103
104
105
106
107
108
Device Clocking................................................................................................................ 109
6.1
6.2
6.3
7
Fixed Range Start Address Register (FXD_MPSAR) .......................................................
Fixed Range End Address Register (FXD_MPEAR) ........................................................
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ...............................
Programmable Range n Start Address Registers (PROGn_MPSAR) ...................................
Programmable Range n End Address Registers (PROGn_MPEAR) ....................................
Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA).............
Fault Address Register (FLTADDRR) ........................................................................
Fault Status Register (FLTSTAT).............................................................................
Fault Clear Register (FLTCLR) ...............................................................................
Overview ...................................................................................................................
Frequency Flexibility ......................................................................................................
Peripheral Clocking .......................................................................................................
6.3.1 USB Clocking.....................................................................................................
6.3.2 DDR2/mDDR Memory Controller Clocking ...................................................................
6.3.3 EMIFA Clocking ..................................................................................................
6.3.4 EMAC Clocking ..................................................................................................
6.3.5 uPP Clocking .....................................................................................................
6.3.6 McASP Clocking .................................................................................................
6.3.7 I/O Domains ......................................................................................................
110
112
113
113
114
116
117
119
120
121
Phase-Locked Loop Controller (PLLC) ................................................................................ 122
7.1
7.2
7.3
Introduction ................................................................................................................
PLL Controllers ............................................................................................................
7.2.1 Device Clock Generation .......................................................................................
7.2.2 Steps for Programming the PLLs ..............................................................................
PLLC Registers ...........................................................................................................
7.3.1 PLLC0 Revision Identification Register (REVID) ............................................................
7.3.2 PLLC1 Revision Identification Register (REVID) ............................................................
7.3.3 Reset Type Status Register (RSTYPE) .......................................................................
7.3.4 PLLC0 Reset Control Register (RSCTRL) ...................................................................
7.3.5 PLLC0 Control Register (PLLCTL) ............................................................................
7.3.6 PLLC1 Control Register (PLLCTL) ............................................................................
7.3.7 PLLC0 OBSCLK Select Register (OCSEL) ..................................................................
7.3.8 PLLC1 OBSCLK Select Register (OCSEL) ..................................................................
7.3.9 PLL Multiplier Control Register (PLLM) .......................................................................
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV) .............................................................
7.3.11 PLLC0 Divider 1 Register (PLLDIV1) ........................................................................
7.3.12 PLLC1 Divider 1 Register (PLLDIV1) ........................................................................
7.3.13 PLLC0 Divider 2 Register (PLLDIV2) ........................................................................
7.3.14 PLLC1 Divider 2 Register (PLLDIV2) ........................................................................
7.3.15 PLLC0 Divider 3 Register (PLLDIV3) ........................................................................
7.3.16 PLLC1 Divider 3 Register (PLLDIV3) ........................................................................
7.3.17 PLLC0 Divider 4 Register (PLLDIV4) ........................................................................
7.3.18 PLLC0 Divider 5 Register (PLLDIV5) ........................................................................
7.3.19 PLLC0 Divider 6 Register (PLLDIV6) ........................................................................
7.3.20 PLLC0 Divider 7 Register (PLLDIV7) ........................................................................
7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV).............................................................
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV).............................................................
7.3.23 PLL Post-Divider Control Register (POSTDIV) .............................................................
7.3.24 PLL Controller Command Register (PLLCMD) .............................................................
7.3.25 PLL Controller Status Register (PLLSTAT) .................................................................
7.3.26 PLLC0 Clock Align Control Register (ALNCTL) ............................................................
7.3.27 PLLC1 Clock Align Control Register (ALNCTL) ............................................................
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Contents
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7.3.28
7.3.29
7.3.30
7.3.31
7.3.32
7.3.33
7.3.34
7.3.35
7.3.36
7.3.37
8
8.3
8.4
8.5
8.6
Introduction ................................................................................................................
Power Domain and Module Topology ..................................................................................
8.2.1 Power Domain States ...........................................................................................
8.2.2 Module States ....................................................................................................
Executing State Transitions .............................................................................................
8.3.1 Power Domain State Transitions ..............................................................................
8.3.2 Module State Transitions .......................................................................................
IcePick Emulation Support in the PSC .................................................................................
PSC Interrupts.............................................................................................................
8.5.1 Interrupt Events ..................................................................................................
8.5.2 Interrupt Registers ...............................................................................................
8.5.3 Interrupt Handling ................................................................................................
PSC Registers.............................................................................................................
8.6.1 Revision Identification Register (REVID) .....................................................................
8.6.2 Interrupt Evaluation Register (INTEVAL) .....................................................................
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ...................................
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ...................................
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ......................................
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ......................................
8.6.7 Power Error Pending Register (PERRPR) ...................................................................
8.6.8 Power Error Clear Register (PERRCR) .......................................................................
8.6.9 Power Domain Transition Command Register (PTCMD)...................................................
8.6.10 Power Domain Transition Status Register (PTSTAT)......................................................
8.6.11 Power Domain 0 Status Register (PDSTAT0) ..............................................................
8.6.12 Power Domain 1 Status Register (PDSTAT1) ..............................................................
8.6.13 Power Domain 0 Control Register (PDCTL0) ...............................................................
8.6.14 Power Domain 1 Control Register (PDCTL1) ...............................................................
8.6.15 Power Domain 0 Configuration Register (PDCFG0) .......................................................
8.6.16 Power Domain 1 Configuration Register (PDCFG1) .......................................................
8.6.17 Module Status n Register (MDSTATn).......................................................................
8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................
8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................
156
156
158
159
161
161
161
162
162
162
163
164
165
166
166
167
167
168
168
169
169
170
171
172
173
174
175
176
177
178
179
180
Power Management........................................................................................................... 181
9.1
9.2
9.3
9.4
9.5
9.6
4
147
148
149
149
150
151
152
153
154
154
Power and Sleep Controller (PSC) ...................................................................................... 155
8.1
8.2
9
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .............................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .............................................
PLLC0 Clock Enable Control Register (CKEN) .............................................................
PLLC1 Clock Enable Control Register (CKEN) .............................................................
PLLC0 Clock Status Register (CKSTAT) ....................................................................
PLLC1 Clock Status Register (CKSTAT) ....................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ................................................................
Emulation Performance Counter 0 Register (EMUCNT0) .................................................
Emulation Performance Counter 1 Register (EMUCNT1) .................................................
Introduction ................................................................................................................
Power Consumption Overview ..........................................................................................
PSC and PLLC Overview ................................................................................................
Features ....................................................................................................................
Clock Management .......................................................................................................
9.5.1 Module Clock ON/OFF ..........................................................................................
9.5.2 Module Clock Frequency Scaling ..............................................................................
9.5.3 PLL Bypass and Power Down .................................................................................
DSP Sleep Mode Management .........................................................................................
Contents
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9.7
9.8
9.9
9.10
10
185
185
185
187
187
188
189
189
189
190
191
192
192
192
192
193
193
System Configuration (SYSCFG) Module ............................................................................. 194
10.1
10.2
10.3
10.4
10.5
11
9.6.1 C674x DSP CPU Sleep Mode .................................................................................
9.6.2 C674x Megamodule Sleep Mode ..............................................................................
9.6.3 C674x Megamodule Clock ON/OFF...........................................................................
RTC-Only Mode ...........................................................................................................
Dynamic Voltage and Frequency Scaling (DVFS) ...................................................................
9.8.1 Frequency Scaling Considerations ............................................................................
9.8.2 Voltage Scaling Considerations ................................................................................
Deep Sleep Mode.........................................................................................................
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ..............................
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up .....................................
9.9.3 Deep Sleep Sequence ..........................................................................................
9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ........................................
Additional Peripheral Power Management Considerations..........................................................
9.10.1 USB PHY Power Down Control ..............................................................................
9.10.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode ................................
9.10.3 LVCMOS I/O Buffer Receiver Disable .......................................................................
9.10.4 Pull-Up/Pull-Down Disable.....................................................................................
Introduction ................................................................................................................
Protection ..................................................................................................................
10.2.1 Privilege Mode Protection .....................................................................................
10.2.2 Kicker Mechanism Protection .................................................................................
Master Priority Control ...................................................................................................
Interrupt Support ..........................................................................................................
10.4.1 Interrupt Events and Requests................................................................................
10.4.2 Interrupt Multiplexing ...........................................................................................
10.4.3 Host-DSP Communication Interrupts ........................................................................
SYSCFG Registers .......................................................................................................
10.5.1 Revision Identification Register (REVID) ....................................................................
10.5.2 Device Identification Register 0 (DEVIDR0).................................................................
10.5.3 Boot Configuration Register (BOOTCFG) ...................................................................
10.5.4 Chip Revision Identification Register (CHIPREVIDR) .....................................................
10.5.5 Kick Registers (KICK0R-KICK1R) ............................................................................
10.5.6 Host 1 Configuration Register (HOST1CFG) ...............................................................
10.5.7 Interrupt Registers ..............................................................................................
10.5.8 Fault Registers ..................................................................................................
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2) ............................................................
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) .............................................
10.5.11 Suspend Source Register (SUSPSRC) ....................................................................
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) ..............................................................
10.5.14 Chip Configuration 0 Register (CFGCHIP0) ...............................................................
10.5.15 Chip Configuration 1 Register (CFGCHIP1) ...............................................................
10.5.16 Chip Configuration 2 Register (CFGCHIP2) ...............................................................
10.5.17 Chip Configuration 3 Register (CFGCHIP3) ...............................................................
10.5.18 Chip Configuration 4 Register (CFGCHIP4) ...............................................................
10.5.19 VTP I/O Control Register (VTPIO_CTL) ...................................................................
10.5.20 DDR Slew Register (DDR_SLEW) ..........................................................................
10.5.21 Deep Sleep Register (DEEPSLEEP) .......................................................................
10.5.22 Pullup/Pulldown Enable Register (PUPD_ENA) ..........................................................
10.5.23 Pullup/Pulldown Select Register (PUPD_SEL) ............................................................
10.5.24 RXACTIVE Control Register (RXACTIVE) .................................................................
195
195
195
196
196
197
197
198
198
198
200
200
201
201
202
203
204
207
209
212
253
256
257
258
259
262
264
265
266
268
269
270
270
272
Boot Considerations ......................................................................................................... 273
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11.1
12
Programmable Real-Time Unit Subsystem (PRUSS) .............................................................. 275
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
13
Overview ...................................................................................................................
Description .................................................................................................................
Constants Table...........................................................................................................
PRU Module Interface ....................................................................................................
12.4.1 Event Out Mapping (R31): PRU System Events ...........................................................
12.4.2 Status Mapping (R31): Interrupt Events Input ..............................................................
12.4.3 General Purpose Inputs (R31) ................................................................................
12.4.4 General Purpose Outputs (R30) ..............................................................................
Instruction Set .............................................................................................................
Instruction Formats .......................................................................................................
PRU Interrupt Controller .................................................................................................
12.7.1 Introduction ......................................................................................................
12.7.2 Interrupt Mapping ...............................................................................................
12.7.3 PRUSS System Events ........................................................................................
12.7.4 ARM and DSP Interrupt Controller Mapping ................................................................
12.7.5 INTC Methodology ..............................................................................................
Registers ...................................................................................................................
12.8.1 PRUSS Memory Map ..........................................................................................
12.8.2 INTC Registers ..................................................................................................
276
278
279
280
280
280
280
280
281
284
302
302
302
303
305
306
309
310
317
DDR2/mDDR Memory Controller ......................................................................................... 328
13.1
13.2
13.3
13.4
6
Introduction ................................................................................................................ 274
Introduction ................................................................................................................
13.1.1 Purpose of the Peripheral .....................................................................................
13.1.2 Features..........................................................................................................
13.1.3 Functional Block Diagram .....................................................................................
13.1.4 Supported Use Case Statement ..............................................................................
13.1.5 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
13.2.1 Clock Control ....................................................................................................
13.2.2 Signal Descriptions .............................................................................................
13.2.3 Protocol Description(s) .........................................................................................
13.2.4 Memory Width and Byte Alignment ..........................................................................
13.2.5 Address Mapping ...............................................................................................
13.2.6 DDR2/mDDR Memory Controller Interface ..................................................................
13.2.7 Refresh Scheduling .............................................................................................
13.2.8 Self-Refresh Mode ..............................................................................................
13.2.9 Partial Array Self Refresh for Mobile DDR ..................................................................
13.2.10 Power-Down Mode ............................................................................................
13.2.11 Reset Considerations .........................................................................................
13.2.12 VTP IO Buffer Calibration ....................................................................................
13.2.13 Auto-Initialization Sequence .................................................................................
13.2.14 Interrupt Support ..............................................................................................
13.2.15 DMA Event Support ...........................................................................................
13.2.16 Power Management ..........................................................................................
13.2.17 Emulation Considerations ....................................................................................
Supported Use Cases ....................................................................................................
Registers ...................................................................................................................
13.4.1 SDRAM Status Register (SDRSTAT) ........................................................................
13.4.2 SDRAM Configuration Register (SDCR) ....................................................................
13.4.3 SDRAM Refresh Control Register (SDRCR) ................................................................
13.4.4 SDRAM Timing Register 1 (SDTIMR1) ......................................................................
13.4.5 SDRAM Timing Register 2 (SDTIMR2) ......................................................................
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331
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13.4.6
13.4.7
13.4.8
13.4.9
13.4.10
13.4.11
13.4.12
13.4.13
13.4.14
13.4.15
13.4.16
13.4.17
14
372
373
374
374
375
377
378
379
379
380
381
382
Enhanced Capture (eCAP) Module ...................................................................................... 383
14.1
14.2
14.3
14.4
15
SDRAM Configuration Register 2 (SDCR2) .................................................................
Peripheral Bus Burst Priority Register (PBBPR)............................................................
Performance Counter 1 Register (PC1) .....................................................................
Performance Counter 2 Register (PC2) .....................................................................
Performance Counter Configuration Register (PCC) .....................................................
Performance Counter Master Region Select Register (PCMRS) .......................................
DDR PHY Reset Control Register (DRPYRCR) ..........................................................
Interrupt Raw Register (IRR) ................................................................................
Interrupt Masked Register (IMR) ............................................................................
Interrupt Mask Set Register (IMSR) ........................................................................
Interrupt Mask Clear Register (IMCR) ......................................................................
DDR PHY Control Register (DRPYC1R) ...................................................................
Introduction ................................................................................................................
14.1.1 Purpose of the Peripheral .....................................................................................
14.1.2 Features..........................................................................................................
Architecture ................................................................................................................
14.2.1 Capture and APWM Operating Mode ........................................................................
14.2.2 Capture Mode Description .....................................................................................
Applications ...............................................................................................................
14.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example .........................................
14.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ...........................
14.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example .......................................
14.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example .........................
14.3.5 Application of the APWM Mode ..............................................................................
Registers ...................................................................................................................
14.4.1 Time-Stamp Counter Register (TSCTR) .....................................................................
14.4.2 Counter Phase Control Register (CTRPHS) ................................................................
14.4.3 Capture 1 Register (CAP1) ....................................................................................
14.4.4 Capture 2 Register (CAP2) ....................................................................................
14.4.5 Capture 3 Register (CAP3) ....................................................................................
14.4.6 Capture 4 Register (CAP4) ....................................................................................
14.4.7 ECAP Control Register 1 (ECCTL1) .........................................................................
14.4.8 ECAP Control Register 2 (ECCTL2) .........................................................................
14.4.9 ECAP Interrupt Enable Register (ECEINT) .................................................................
14.4.10 ECAP Interrupt Flag Register (ECFLG) ....................................................................
14.4.11 ECAP Interrupt Clear Register (ECCLR) ...................................................................
14.4.12 ECAP Interrupt Forcing Register (ECFRC) ................................................................
14.4.13 Revision ID Register (REVID) ...............................................................................
384
384
384
385
386
387
394
395
397
399
401
403
410
410
411
411
412
412
413
413
415
416
418
419
420
421
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 422
15.1
15.2
Introduction ................................................................................................................
15.1.1 Introduction ......................................................................................................
15.1.2 Submodule Overview ..........................................................................................
15.1.3 Register Mapping ...............................................................................................
Architecture ................................................................................................................
15.2.1 Overview .........................................................................................................
15.2.2 Proper Interrupt Initialization Procedure .....................................................................
15.2.3 Time-Base (TB) Submodule ...................................................................................
15.2.4 Counter-Compare (CC) Submodule ..........................................................................
15.2.5 Action-Qualifier (AQ) Submodule .............................................................................
15.2.6 Dead-Band Generator (DB) Submodule .....................................................................
15.2.7 PWM-Chopper (PC) Submodule..............................................................................
15.2.8 Trip-Zone (TZ) Submodule ....................................................................................
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15.3
15.4
16
476
480
487
487
488
489
492
495
498
502
503
508
511
511
515
518
522
525
526
530
533
Enhanced Direct Memory Access (EDMA3) Controller ........................................................... 536
16.1
16.2
16.3
16.4
8
15.2.9 Event-Trigger (ET) Submodule ...............................................................................
15.2.10 High-Resolution PWM (HRPWM) Submodule.............................................................
Applications to Power Topologies ......................................................................................
15.3.1 Overview of Multiple Modules ................................................................................
15.3.2 Key Configuration Capabilities ................................................................................
15.3.3 Controlling Multiple Buck Converters With Independent Frequencies ...................................
15.3.4 Controlling Multiple Buck Converters With Same Frequencies ...........................................
15.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ......................................................
15.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................
15.3.7 Practical Applications Using Phase Control Between PWM Modules ...................................
15.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ......................................................
15.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter......................................
Registers ...................................................................................................................
15.4.1 Time-Base Submodule Registers ............................................................................
15.4.2 Counter-Compare Submodule Registers ....................................................................
15.4.3 Action-Qualifier Submodule Registers .......................................................................
15.4.4 Dead-Band Generator Submodule Registers ...............................................................
15.4.5 PWM-Chopper Submodule Register .........................................................................
15.4.6 Trip-Zone Submodule Registers ..............................................................................
15.4.7 Event-Trigger Submodule Registers .........................................................................
15.4.8 High-Resolution PWM Submodule Registers ...............................................................
Introduction ................................................................................................................
16.1.1 Overview .........................................................................................................
16.1.2 Features..........................................................................................................
16.1.3 Functional Block Diagram .....................................................................................
16.1.4 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
16.2.1 Functional Overview ............................................................................................
16.2.2 Types of EDMA3 Transfers ...................................................................................
16.2.3 Parameter RAM (PaRAM) .....................................................................................
16.2.4 Initiating a DMA Transfer ......................................................................................
16.2.5 Completion of a DMA Transfer................................................................................
16.2.6 Event, Channel, and PaRAM Mapping ......................................................................
16.2.7 EDMA3 Channel Controller Regions .........................................................................
16.2.8 Chaining EDMA3 Channels ...................................................................................
16.2.9 EDMA3 Interrupts ...............................................................................................
16.2.10 Event Queue(s) ................................................................................................
16.2.11 EDMA3 Transfer Controller (EDMA3TC)...................................................................
16.2.12 Event Dataflow ................................................................................................
16.2.13 EDMA3 Prioritization ..........................................................................................
16.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................
16.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................
16.2.16 Reset Considerations .........................................................................................
16.2.17 Power Management ..........................................................................................
16.2.18 Emulation Considerations ....................................................................................
Transfer Examples........................................................................................................
16.3.1 Block Move Example ...........................................................................................
16.3.2 Subframe Extraction Example ................................................................................
16.3.3 Data Sorting Example ..........................................................................................
16.3.4 Peripheral Servicing Example .................................................................................
Registers ...................................................................................................................
16.4.1 Parameter RAM (PaRAM) Entries ............................................................................
Contents
537
537
537
540
540
542
542
545
548
558
561
562
565
567
568
575
577
580
581
583
584
584
584
585
585
585
587
588
590
602
602
SPRUH80C – April 2013 – Revised September 2016
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16.5
16.6
17
609
648
669
669
670
671
EMAC/MDIO Module .......................................................................................................... 672
17.1
17.2
17.3
18
16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................
16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ........................................................
Tips .........................................................................................................................
16.5.1 Debug Checklist ................................................................................................
16.5.2 Miscellaneous Programming/Debug Tips ...................................................................
Setting Up a Transfer ....................................................................................................
Introduction ................................................................................................................
17.1.1 Purpose of the Peripheral .....................................................................................
17.1.2 Features..........................................................................................................
17.1.3 Functional Block Diagram .....................................................................................
17.1.4 Industry Standard(s) Compliance Statement................................................................
17.1.5 Terminology .....................................................................................................
Architecture ................................................................................................................
17.2.1 Clock Control ....................................................................................................
17.2.2 Memory Map ....................................................................................................
17.2.3 Signal Descriptions .............................................................................................
17.2.4 Ethernet Protocol Overview ...................................................................................
17.2.5 Programming Interface .........................................................................................
17.2.6 EMAC Control Module .........................................................................................
17.2.7 MDIO Module ...................................................................................................
17.2.8 EMAC Module ...................................................................................................
17.2.9 MAC Interface ...................................................................................................
17.2.10 Packet Receive Operation ...................................................................................
17.2.11 Packet Transmit Operation ..................................................................................
17.2.12 Receive and Transmit Latency ..............................................................................
17.2.13 Transfer Node Priority ........................................................................................
17.2.14 Reset Considerations .........................................................................................
17.2.15 Initialization .....................................................................................................
17.2.16 Interrupt Support ..............................................................................................
17.2.17 Power Management ..........................................................................................
17.2.18 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
17.3.1 EMAC Control Module Registers .............................................................................
17.3.2 MDIO Registers .................................................................................................
17.3.3 EMAC Module Registers.......................................................................................
673
673
673
674
675
675
676
676
677
677
680
681
692
693
698
700
704
709
710
710
711
712
714
718
718
719
719
733
746
External Memory Interface A (EMIFA) .................................................................................. 796
18.1
18.2
Introduction ................................................................................................................
18.1.1 Purpose of the Peripheral .....................................................................................
18.1.2 Features..........................................................................................................
18.1.3 Functional Block Diagram .....................................................................................
Architecture ................................................................................................................
18.2.1 Clock Control ....................................................................................................
18.2.2 EMIFA Requests ................................................................................................
18.2.3 Pin Descriptions .................................................................................................
18.2.4 SDRAM Controller and Interface .............................................................................
18.2.5 Asynchronous Controller and Interface ......................................................................
18.2.6 Data Bus Parking ...............................................................................................
18.2.7 Reset and Initialization Considerations ......................................................................
18.2.8 Interrupt Support ................................................................................................
18.2.9 EDMA Event Support ..........................................................................................
18.2.10 Pin Multiplexing ................................................................................................
18.2.11 Memory Map ...................................................................................................
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Contents
797
797
797
797
797
798
798
798
800
812
831
831
832
833
833
833
9
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18.3
18.4
19
834
835
836
837
838
838
838
860
861
861
863
865
866
868
869
870
871
872
873
874
876
877
878
879
879
880
880
881
881
882
882
General-Purpose Input/Output (GPIO) ................................................................................. 883
19.1
19.2
19.3
10
18.2.12 Priority and Arbitration ........................................................................................
18.2.13 System Considerations .......................................................................................
18.2.14 Power Management ..........................................................................................
18.2.15 Emulation Considerations ....................................................................................
Example Configuration ...................................................................................................
18.3.1 Hardware Interface .............................................................................................
18.3.2 Software Configuration .........................................................................................
Registers ...................................................................................................................
18.4.1 Module ID Register (MIDR) ...................................................................................
18.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) ...............................................
18.4.3 SDRAM Configuration Register (SDCR) ....................................................................
18.4.4 SDRAM Refresh Control Register (SDRCR) ................................................................
18.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
18.4.6 SDRAM Timing Register (SDTIMR) ..........................................................................
18.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ..................................................
18.4.8 EMIFA Interrupt Raw Register (INTRAW) ...................................................................
18.4.9 EMIFA Interrupt Masked Register (INTMSK) ...............................................................
18.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET).......................................................
18.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ....................................................
18.4.12 NAND Flash Control Register (NANDFCR) ...............................................................
18.4.13 NAND Flash Status Register (NANDFSR) .................................................................
18.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ..........................................
18.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) .......................................
18.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..................................................
18.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..................................................
18.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..................................................
18.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..................................................
18.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) .................................
18.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) .................................
18.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1).....................................
18.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2).....................................
Introduction ................................................................................................................
19.1.1 Purpose of the Peripheral .....................................................................................
19.1.2 Features..........................................................................................................
19.1.3 Functional Block Diagram .....................................................................................
19.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
19.2.1 Clock Control ....................................................................................................
19.2.2 Signal Descriptions .............................................................................................
19.2.3 Pin Multiplexing .................................................................................................
19.2.4 Endianness Considerations ...................................................................................
19.2.5 GPIO Register Structure .......................................................................................
19.2.6 Using a GPIO Signal as an Output ...........................................................................
19.2.7 Using a GPIO Signal as an Input .............................................................................
19.2.8 Reset Considerations ..........................................................................................
19.2.9 Initialization ......................................................................................................
19.2.10 Interrupt Support ..............................................................................................
19.2.11 EDMA Event Support .........................................................................................
19.2.12 Power Management ..........................................................................................
19.2.13 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
19.3.1 Revision ID Register (REVID) .................................................................................
Contents
884
884
884
884
884
885
885
885
885
885
886
889
890
890
891
891
892
892
892
893
894
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19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.3.10
19.3.11
19.3.12
20
895
896
898
900
902
904
906
908
910
912
914
Host Port Interface (HPI) .................................................................................................... 916
20.1
20.2
20.3
21
GPIO Interrupt Per-Bank Enable Register (BINTEN) ......................................................
GPIO Direction Registers (DIRn) .............................................................................
GPIO Output Data Registers (OUT_DATAn) ...............................................................
GPIO Set Data Registers (SET_DATAn) ....................................................................
GPIO Clear Data Registers (CLR_DATAn) .................................................................
GPIO Input Data Registers (IN_DATAn) ....................................................................
GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) ...........................................
GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ........................................
GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................
GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) .....................................
GPIO Interrupt Status Registers (INTSTATn) .............................................................
Introduction ................................................................................................................
20.1.1 Purpose of the Peripheral .....................................................................................
20.1.2 Features..........................................................................................................
20.1.3 Functional Block Diagram .....................................................................................
20.1.4 Industry Standard(s) Compliance Statement................................................................
20.1.5 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
20.2.1 Clock Control ....................................................................................................
20.2.2 Memory Map ....................................................................................................
20.2.3 Signal Descriptions .............................................................................................
20.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks ................................................
20.2.5 Protocol Description ............................................................................................
20.2.6 Operation ........................................................................................................
20.2.7 Reset Considerations ..........................................................................................
20.2.8 Initialization ......................................................................................................
20.2.9 Interrupt Support ................................................................................................
20.2.10 EDMA Event Support .........................................................................................
20.2.11 Power Management ..........................................................................................
20.2.12 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
20.3.1 Revision Identification Register (REVID) ....................................................................
20.3.2 Power and Emulation Management Register (PWREMU_MGMT) ......................................
20.3.3 GPIO Enable Register (GPIO_EN) ..........................................................................
20.3.4 GPIO Direction 1 Register (GPIO_DIR1) ....................................................................
20.3.5 GPIO Data 1 Register (GPIO_DAT1) ........................................................................
20.3.6 GPIO Direction 2 Register (GPIO_DIR2) ....................................................................
20.3.7 GPIO Data 2 Register (GPIO_DAT2) ........................................................................
20.3.8 Host Port Interface Control Register (HPIC) ................................................................
20.3.9 Host Port Interface Write Address Register (HPIAW) .....................................................
20.3.10 Host Port Interface Read Address Register (HPIAR) ....................................................
Inter-Integrated Circuit (I2C) Module
21.1
21.2
917
917
917
918
919
919
920
920
920
920
921
922
922
937
937
938
939
939
940
940
941
941
942
943
943
944
945
946
948
948
................................................................................... 949
Introduction ................................................................................................................
21.1.1 Purpose of the Peripheral .....................................................................................
21.1.2 Features..........................................................................................................
21.1.3 Functional Block Diagram .....................................................................................
21.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
21.2.1 Bus Structure ....................................................................................................
21.2.2 Clock Generation ...............................................................................................
21.2.3 Clock Synchronization .........................................................................................
21.2.4 Signal Descriptions .............................................................................................
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Contents
950
950
950
951
951
952
952
953
954
954
11
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21.3
22
955
956
958
959
960
961
961
962
963
963
963
964
965
966
967
970
971
972
973
974
975
979
980
981
982
982
983
984
985
986
987
988
989
Multichannel Audio Serial Port (McASP) .............................................................................. 990
22.1
12
21.2.5 START and STOP Conditions ................................................................................
21.2.6 Serial Data Formats ............................................................................................
21.2.7 Operating Modes ...............................................................................................
21.2.8 NACK Bit Generation...........................................................................................
21.2.9 Arbitration ........................................................................................................
21.2.10 Reset Considerations .........................................................................................
21.2.11 Initialization .....................................................................................................
21.2.12 Interrupt Support ..............................................................................................
21.2.13 DMA Events Generated by the I2C Peripheral ............................................................
21.2.14 Power Management ..........................................................................................
21.2.15 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
21.3.1 I2C Own Address Register (ICOAR) .........................................................................
21.3.2 I2C Interrupt Mask Register (ICIMR) .........................................................................
21.3.3 I2C Interrupt Status Register (ICSTR) ......................................................................
21.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) .......................................................
21.3.5 I2C Data Count Register (ICCNT) ............................................................................
21.3.6 I2C Data Receive Register (ICDRR) .........................................................................
21.3.7 I2C Slave Address Register (ICSAR) ........................................................................
21.3.8 I2C Data Transmit Register (ICDXR) ........................................................................
21.3.9 I2C Mode Register (ICMDR) ..................................................................................
21.3.10 I2C Interrupt Vector Register (ICIVR) ......................................................................
21.3.11 I2C Extended Mode Register (ICEMDR) ...................................................................
21.3.12 I2C Prescaler Register (ICPSC).............................................................................
21.3.13 I2C Revision Identification Register (REVID1) ............................................................
21.3.14 I2C Revision Identification Register (REVID2) ...........................................................
21.3.15 I2C DMA Control Register (ICDMAC) ......................................................................
21.3.16 I2C Pin Function Register (ICPFUNC) ....................................................................
21.3.17 I2C Pin Direction Register (ICPDIR) .......................................................................
21.3.18 I2C Pin Data In Register (ICPDIN) .........................................................................
21.3.19 I2C Pin Data Out Register (ICPDOUT) ....................................................................
21.3.20 I2C Pin Data Set Register (ICPDSET) ....................................................................
21.3.21 I2C Pin Data Clear Register (ICPDCLR) ..................................................................
22.0.22 Features ....................................................................................................... 991
22.0.23 Protocols Supported ......................................................................................... 992
22.0.24 Functional Block Diagram .................................................................................... 993
22.0.25 Definition of Terms .......................................................................................... 1001
22.0.26 Overview ..................................................................................................... 1004
22.0.27 Clock and Frame Sync Generators ....................................................................... 1004
22.0.28 Reset Considerations ....................................................................................... 1045
22.0.29 EDMA Event Support ....................................................................................... 1045
22.0.30 Power Management ......................................................................................... 1045
Registers ................................................................................................................. 1046
22.1.1 Register Bit Restrictions ...................................................................................... 1049
22.1.2 Revision Identification Register (REV) ..................................................................... 1050
22.1.3 Pin Function Register (PFUNC) ............................................................................. 1051
22.1.4 Pin Direction Register (PDIR) ............................................................................... 1053
22.1.5 Pin Data Output Register (PDOUT) ........................................................................ 1055
22.1.6 Pin Data Input Register (PDIN).............................................................................. 1057
22.1.7 Pin Data Set Register (PDSET) ............................................................................. 1059
22.1.8 Pin Data Clear Register (PDCLR) .......................................................................... 1061
22.1.9 Global Control Register (GBLCTL) ......................................................................... 1063
Contents
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22.1.10
22.1.11
22.1.12
22.1.13
22.1.14
22.1.15
22.1.16
22.1.17
22.1.18
22.1.19
22.1.20
22.1.21
22.1.22
22.1.23
22.1.24
22.1.25
22.1.26
22.1.27
22.1.28
22.1.29
22.1.30
22.1.31
22.1.32
22.1.33
22.1.34
22.1.35
22.1.36
22.1.37
22.1.38
22.1.39
22.1.40
22.1.41
22.1.42
22.1.43
22.1.44
22.1.45
22.1.46
22.1.47
22.1.48
23
Audio Mute Control Register (AMUTE) ...................................................................
Digital Loopback Control Register (DLBCTL) ............................................................
Digital Mode Control Register (DITCTL) ..................................................................
Receiver Global Control Register (RGBLCTL)...........................................................
Receive Format Unit Bit Mask Register (RMASK) ......................................................
Receive Bit Stream Format Register (RFMT) ............................................................
Receive Frame Sync Control Register (AFSRCTL) .....................................................
Receive Clock Control Register (ACLKRCTL) ...........................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) .....................................
Receive TDM Time Slot Register (RTDM) ...............................................................
Receiver Interrupt Control Register (RINTCTL) .........................................................
Receiver Status Register (RSTAT) ........................................................................
Current Receive TDM Time Slot Registers (RSLOT) ...................................................
Receive Clock Check Control Register (RCLKCHK)....................................................
Receiver DMA Event Control Register (REVTCTL) .....................................................
Transmitter Global Control Register (XGBLCTL) ........................................................
Transmit Format Unit Bit Mask Register (XMASK) ......................................................
Transmit Bit Stream Format Register (XFMT) ...........................................................
Transmit Frame Sync Control Register (AFSXCTL) ....................................................
Transmit Clock Control Register (ACLKXCTL) ..........................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ....................................
Transmit TDM Time Slot Register (XTDM) ...............................................................
Transmitter Interrupt Control Register (XINTCTL) ......................................................
Transmitter Status Register (XSTAT) .....................................................................
Current Transmit TDM Time Slot Register (XSLOT) ....................................................
Transmit Clock Check Control Register (XCLKCHK) ...................................................
Transmitter DMA Event Control Register (XEVTCTL) ..................................................
Serializer Control Registers (SRCTLn) ...................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ..........................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ........................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) .....................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ...................................
Transmit Buffer Registers (XBUFn) .......................................................................
Receive Buffer Registers (RBUFn) ........................................................................
AFIFO Revision Identification Register (AFIFOREV) ...................................................
Write FIFO Control Register (WFIFOCTL) ...............................................................
Write FIFO Status Register (WFIFOSTS) ................................................................
Read FIFO Control Register (RFIFOCTL) ................................................................
Read FIFO Status Register (RFIFOSTS).................................................................
1065
1067
1068
1069
1070
1071
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1096
1097
1097
1098
1098
1099
1100
1101
1102
1103
Multichannel Buffered Serial Port (McBSP) ........................................................................ 1104
23.1
23.2
Introduction ...............................................................................................................
23.1.1 Purpose of the Peripheral ....................................................................................
23.1.2 Features ........................................................................................................
23.1.3 Functional Block Diagram ....................................................................................
23.1.4 Industry Standard Compliance Statement .................................................................
Architecture ..............................................................................................................
23.2.1 Clock Control ..................................................................................................
23.2.2 Signal Descriptions............................................................................................
23.2.3 Pin Multiplexing ................................................................................................
23.2.4 Endianness Considerations ..................................................................................
23.2.5 Clock, Frames, and Data .....................................................................................
23.2.6 McBSP Buffer FIFO (BFIFO) ................................................................................
23.2.7 McBSP Standard Operation .................................................................................
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Contents
1105
1105
1105
1106
1106
1107
1107
1107
1107
1107
1108
1122
1122
13
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23.3
24
1136
1138
1146
1146
1147
1151
1152
1153
1153
1154
1155
1155
1156
1158
1160
1162
1163
1167
1169
1171
1173
1174
1175
1176
1177
Multimedia Card (MMC)/Secure Digital (SD) Card Controller ................................................. 1178
24.1
24.2
24.3
14
23.2.8 μ-Law/A-Law Companding Hardware Operation ..........................................................
23.2.9 Multichannel Selection Modes ...............................................................................
23.2.10 SPI Operation Using the Clock Stop Mode ..............................................................
23.2.11 Resetting the Serial Port: RRST, XRST, GRST, and RESET .........................................
23.2.12 McBSP Initialization Procedure ............................................................................
23.2.13 Interrupt Support .............................................................................................
23.2.14 EDMA Event Support .......................................................................................
23.2.15 Power Management .........................................................................................
23.2.16 Emulation Considerations ..................................................................................
Registers .................................................................................................................
23.3.1 Data Receive Register (DRR) ...............................................................................
23.3.2 Data Transmit Register (DXR)...............................................................................
23.3.3 Serial Port Control Register (SPCR)........................................................................
23.3.4 Receive Control Register (RCR) ............................................................................
23.3.5 Transmit Control Register (XCR)............................................................................
23.3.6 Sample Rate Generator Register (SRGR) .................................................................
23.3.7 Multichannel Control Register (MCR) ......................................................................
23.3.8 Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) ..................................
23.3.9 Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) ..................................
23.3.10 Pin Control Register (PCR) .................................................................................
23.3.11 BFIFO Revision Identification Register (BFIFOREV) ...................................................
23.3.12 Write FIFO Control Register (WFIFOCTL) ...............................................................
23.3.13 Write FIFO Status Register (WFIFOSTS) ................................................................
23.3.14 Read FIFO Control Register (RFIFOCTL) ................................................................
23.3.15 Read FIFO Status Register (RFIFOSTS).................................................................
Introduction ...............................................................................................................
24.1.1 Purpose of the Peripheral ....................................................................................
24.1.2 Features ........................................................................................................
24.1.3 Functional Block Diagram ....................................................................................
24.1.4 Supported Use Case Statement ............................................................................
24.1.5 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
24.2.1 Clock Control ..................................................................................................
24.2.2 Signal Descriptions............................................................................................
24.2.3 Protocol Descriptions .........................................................................................
24.2.4 Data Flow in the Input/Output FIFO ........................................................................
24.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ...........................................
24.2.6 FIFO Operation During Card Read Operation.............................................................
24.2.7 FIFO Operation During Card Write Operation .............................................................
24.2.8 Reset Considerations .........................................................................................
24.2.9 Initialization .....................................................................................................
24.2.10 Interrupt Support .............................................................................................
24.2.11 DMA Event Support .........................................................................................
24.2.12 Power Management .........................................................................................
24.2.13 Emulation Considerations ..................................................................................
Procedures for Common Operations .................................................................................
24.3.1 Card Identification Operation ................................................................................
24.3.2 MMC/SD Mode Single-Block Write Operation Using CPU ..............................................
24.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ........................................
24.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ..........................................
24.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ............................................
24.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU .............................................
Contents
1179
1179
1179
1179
1179
1180
1180
1181
1182
1183
1184
1186
1187
1189
1189
1191
1194
1195
1195
1195
1196
1196
1199
1201
1201
1203
1203
SPRUH80C – April 2013 – Revised September 2016
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24.4
25
24.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA...........................................
24.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................
24.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA ..........................................
24.3.10 SDIO Card Function .........................................................................................
Registers .................................................................................................................
24.4.1 MMC Control Register (MMCCTL) ..........................................................................
24.4.2 MMC Memory Clock Control Register (MMCCLK) .......................................................
24.4.3 MMC Status Register 0 (MMCST0) .........................................................................
24.4.4 MMC Status Register 1 (MMCST1) .........................................................................
24.4.5 MMC Interrupt Mask Register (MMCIM) ...................................................................
24.4.6 MMC Response Time-Out Register (MMCTOR) ..........................................................
24.4.7 MMC Data Read Time-Out Register (MMCTOD) .........................................................
24.4.8 MMC Block Length Register (MMCBLEN) .................................................................
24.4.9 MMC Number of Blocks Register (MMCNBLK) ...........................................................
24.4.10 MMC Number of Blocks Counter Register (MMCNBLC) ...............................................
24.4.11 MMC Data Receive Register (MMCDRR) ................................................................
24.4.12 MMC Data Transmit Register (MMCDXR) ...............................................................
24.4.13 MMC Command Register (MMCCMD) ...................................................................
24.4.14 MMC Argument Register (MMCARGHL) .................................................................
24.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ...................................................
24.4.16 MMC Data Response Register (MMCDRSP) ............................................................
24.4.17 MMC Command Index Register (MMCCIDX) ............................................................
24.4.18 SDIO Control Register (SDIOCTL) ........................................................................
24.4.19 SDIO Status Register 0 (SDIOST0) .......................................................................
24.4.20 SDIO Interrupt Enable Register (SDIOIEN) ..............................................................
24.4.21 SDIO Interrupt Status Register (SDIOIST) ...............................................................
24.4.22 MMC FIFO Control Register (MMCFIFOCTL) ...........................................................
1205
1205
1207
1207
1208
1209
1210
1211
1213
1214
1216
1217
1218
1219
1219
1220
1220
1221
1223
1224
1226
1226
1227
1228
1229
1229
1230
Real-Time Clock (RTC) ..................................................................................................... 1231
25.1
25.2
25.3
Introduction ...............................................................................................................
25.1.1 Purpose of the Peripheral ....................................................................................
25.1.2 Features ........................................................................................................
25.1.3 Block Diagram .................................................................................................
Architecture ..............................................................................................................
25.2.1 Clock Source ...................................................................................................
25.2.2 Signal Descriptions............................................................................................
25.2.3 Isolated Power Supply ........................................................................................
25.2.4 Operation .......................................................................................................
25.2.5 Interrupt Requests ............................................................................................
25.2.6 Register Protection Against Spurious Writes ..............................................................
25.2.7 General-Purpose Scratch Registers ........................................................................
25.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) ..............................
25.2.9 Emulation Modes of the Real-Time Clock .................................................................
25.2.10 Reset Considerations .......................................................................................
Registers .................................................................................................................
25.3.1 Second Register (SECOND).................................................................................
25.3.2 Minute Register (MINUTE) ...................................................................................
25.3.3 Hour Register (HOUR) .......................................................................................
25.3.4 Day of the Month Register (DAY) ...........................................................................
25.3.5 Month Register (MONTH) ....................................................................................
25.3.6 Year Register (YEAR) ........................................................................................
25.3.7 Day of the Week Register (DOTW) .........................................................................
25.3.8 Alarm Second Register (ALARMSECOND) ...............................................................
25.3.9 Alarm Minute Register (ALARMMINUTE) ..................................................................
SPRUH80C – April 2013 – Revised September 2016
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Contents
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25.3.10
25.3.11
25.3.12
25.3.13
25.3.14
25.3.15
25.3.16
25.3.17
25.3.18
25.3.19
25.3.20
25.3.21
26
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1254
Serial Peripheral Interface (SPI) ........................................................................................ 1255
26.1
26.2
26.3
16
Alarm Hour Register (ALARMHOUR) .....................................................................
Alarm Day of the Month Register (ALARMDAY) ........................................................
Alarm Month Register (ALARMMONTH) .................................................................
Alarm Year Register (ALARMYEAR)......................................................................
Control Register (CTRL) ....................................................................................
Status Register (STATUS) .................................................................................
Interrupt Register (INTERRUPT) ..........................................................................
Compensation (LSB) Register (COMPLSB) .............................................................
Compensation (MSB) Register (COMPMSB) ............................................................
Oscillator Register (OSC) ...................................................................................
Scratch Registers (SCRATCH0-SCRATCH2) ...........................................................
Kick Registers (KICK0R, KICK1R) ........................................................................
Introduction ...............................................................................................................
26.1.1 Purpose of the Peripheral ....................................................................................
26.1.2 Features ........................................................................................................
26.1.3 Functional Block Diagram ....................................................................................
26.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
26.2.1 Clock ............................................................................................................
26.2.2 Signal Descriptions............................................................................................
26.2.3 Operation Modes ..............................................................................................
26.2.4 Programmable Registers .....................................................................................
26.2.5 Master Mode Settings ........................................................................................
26.2.6 Slave Mode Settings ..........................................................................................
26.2.7 SPI Operation: 3-Pin Mode ..................................................................................
26.2.8 SPI Operation: 4-Pin with Chip Select Mode .............................................................
26.2.9 SPI Operation: 4-Pin with Enable Mode ...................................................................
26.2.10 SPI Operation: 5-Pin Mode .................................................................................
26.2.11 Data Formats .................................................................................................
26.2.12 Interrupt Support .............................................................................................
26.2.13 DMA Events Support ........................................................................................
26.2.14 Robustness Features .......................................................................................
26.2.15 Reset Considerations .......................................................................................
26.2.16 Power Management .........................................................................................
26.2.17 General-Purpose I/O Pin....................................................................................
26.2.18 Emulation Considerations ..................................................................................
26.2.19 Initialization ...................................................................................................
26.2.20 Timing Diagrams .............................................................................................
Registers .................................................................................................................
26.3.1 SPI Global Control Register 0 (SPIGCR0) .................................................................
26.3.2 SPI Global Control Register 1 (SPIGCR1) .................................................................
26.3.3 SPI Interrupt Register (SPIINT0) ............................................................................
26.3.4 SPI Interrupt Level Register (SPILVL) ......................................................................
26.3.5 SPI Flag Register (SPIFLG) .................................................................................
26.3.6 SPI Pin Control Register 0 (SPIPC0) ......................................................................
26.3.7 SPI Pin Control Register 1 (SPIPC1) .......................................................................
26.3.8 SPI Pin Control Register 2 (SPIPC2) .......................................................................
26.3.9 SPI Pin Control Register 3 (SPIPC3) .......................................................................
26.3.10 SPI Pin Control Register 4 (SPIPC4) .....................................................................
26.3.11 SPI Pin Control Register 5 (SPIPC5) .....................................................................
26.3.12 SPI Transmit Data Register 0 (SPIDAT0) ................................................................
26.3.13 SPI Transmit Data Register 1 (SPIDAT1) ................................................................
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SPRUH80C – April 2013 – Revised September 2016
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26.3.14
26.3.15
26.3.16
26.3.17
26.3.18
26.3.19
27
64-Bit Timer Plus
27.1
27.2
28
SPI Receive Buffer Register (SPIBUF) ...................................................................
SPI Emulation Register (SPIEMU) ........................................................................
SPI Delay Register (SPIDELAY) ..........................................................................
SPI Default Chip Select Register (SPIDEF) ..............................................................
SPI Data Format Registers (SPIFMTn) ...................................................................
SPI Interrupt Vector Register 1 (INTVEC1) ..............................................................
............................................................................................................ 1310
Introduction ...............................................................................................................
27.1.1 Purpose of the Peripheral ....................................................................................
27.1.2 Features ........................................................................................................
27.1.3 Block Diagram .................................................................................................
27.1.4 Industry Standard Compatibility Statement ................................................................
27.1.5 Architecture – General-Purpose Timer Mode .............................................................
27.1.6 Architecture – Watchdog Timer Mode ......................................................................
27.1.7 Reset Considerations .........................................................................................
27.1.8 Interrupt Support ..............................................................................................
27.1.9 DMA Event Support ...........................................................................................
27.1.10 TM64P_OUT Event Support ...............................................................................
27.1.11 Interrupt/DMA Event Generation Control and Status ...................................................
27.1.12 Power Management .........................................................................................
27.1.13 Emulation Considerations ..................................................................................
Registers .................................................................................................................
27.2.1 Revision ID Register (REVID) ...............................................................................
27.2.2 Emulation Management Register (EMUMGT) .............................................................
27.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ............................................
27.2.4 GPIO Data and Direction Register (GPDATGPDIR) .....................................................
27.2.5 Timer Counter Registers (TIM12 and TIM34) .............................................................
27.2.6 Timer Period Registers (PRD12 and PRD34) .............................................................
27.2.7 Timer Control Register (TCR) ...............................................................................
27.2.8 Timer Global Control Register (TGCR).....................................................................
27.2.9 Watchdog Timer Control Register (WDTCR) ..............................................................
27.2.10 Timer Reload Register 12 (REL12) .......................................................................
27.2.11 Timer Reload Register 34 (REL34) .......................................................................
27.2.12 Timer Capture Register 12 (CAP12) ......................................................................
27.2.13 Timer Capture Register 34 (CAP34) ......................................................................
27.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) ..........................................
Universal Asynchronous Receiver/Transmitter (UART)
28.1
28.2
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....................................................... 1344
Introduction ...............................................................................................................
28.1.1 Purpose of the Peripheral ....................................................................................
28.1.2 Features ........................................................................................................
28.1.3 Functional Block Diagram ....................................................................................
28.1.4 Industry Standard(s) Compliance Statement ..............................................................
Peripheral Architecture .................................................................................................
28.2.1 Clock Generation and Control ...............................................................................
28.2.2 Signal Descriptions............................................................................................
28.2.3 Pin Multiplexing ................................................................................................
28.2.4 Protocol Description ..........................................................................................
28.2.5 Operation .......................................................................................................
28.2.6 Reset Considerations .........................................................................................
28.2.7 Initialization .....................................................................................................
28.2.8 Interrupt Support ..............................................................................................
28.2.9 DMA Event Support ...........................................................................................
28.2.10 Power Management .........................................................................................
SPRUH80C – April 2013 – Revised September 2016
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28.3
29
Universal Parallel Port (uPP)
29.1
29.2
29.3
18
28.2.11 Emulation Considerations ..................................................................................
28.2.12 Exception Processing .......................................................................................
Registers .................................................................................................................
28.3.1 Receiver Buffer Register (RBR) .............................................................................
28.3.2 Transmitter Holding Register (THR) ........................................................................
28.3.3 Interrupt Enable Register (IER) .............................................................................
28.3.4 Interrupt Identification Register (IIR) ........................................................................
28.3.5 FIFO Control Register (FCR) ................................................................................
28.3.6 Line Control Register (LCR) .................................................................................
28.3.7 Modem Control Register (MCR) .............................................................................
28.3.8 Line Status Register (LSR) ..................................................................................
28.3.9 Modem Status Register (MSR) ..............................................................................
28.3.10 Scratch Pad Register (SCR) ...............................................................................
28.3.11 Divisor Latches (DLL and DLH) ............................................................................
28.3.12 Revision Identification Registers (REVID1 and REVID2) ..............................................
28.3.13 Power and Emulation Management Register (PWREMU_MGMT) ...................................
28.3.14 Mode Definition Register (MDR) ...........................................................................
............................................................................................ 1377
Introduction ...............................................................................................................
29.1.1 Purpose of the Peripheral ....................................................................................
29.1.2 Features ........................................................................................................
29.1.3 Functional Block Diagram ....................................................................................
Architecture ..............................................................................................................
29.2.1 Clock Generation and Control ...............................................................................
29.2.2 Signal Description .............................................................................................
29.2.3 Pin Multiplexing ................................................................................................
29.2.4 Internal DMA Controller Description ........................................................................
29.2.5 Protocol Description ..........................................................................................
29.2.6 Initialization and Operation ...................................................................................
29.2.7 Reset Considerations .........................................................................................
29.2.8 Interrupt Support ..............................................................................................
29.2.9 Power Management ..........................................................................................
29.2.10 Emulation Considerations ..................................................................................
29.2.11 Transmit and Receive FIFOs...............................................................................
Registers .................................................................................................................
29.3.1 uPP Peripheral Identification Register (UPPID) ...........................................................
29.3.2 uPP Peripheral Control Register (UPPCR) ................................................................
29.3.3 uPP Digital Loopback Register (UPDLB) ..................................................................
29.3.4 uPP Channel Control Register (UPCTL) ...................................................................
29.3.5 uPP Interface Configuration Register (UPICR)............................................................
29.3.6 uPP Interface Idle Value Register (UPIVR) ................................................................
29.3.7 uPP Threshold Configuration Register (UPTCR) .........................................................
29.3.8 uPP Interrupt Raw Status Register (UPISR) ..............................................................
29.3.9 uPP Interrupt Enabled Status Register (UPIER) ..........................................................
29.3.10 uPP Interrupt Enable Set Register (UPIES) ..............................................................
29.3.11 uPP Interrupt Enable Clear Register (UPIEC) ...........................................................
29.3.12 uPP End of Interrupt Register (UPEOI) ...................................................................
29.3.13 uPP DMA Channel I Descriptor 0 Register (UPID0) ....................................................
29.3.14 uPP DMA Channel I Descriptor 1 Register (UPID1) ....................................................
29.3.15 uPP DMA Channel I Descriptor 2 Register (UPID2) ....................................................
29.3.16 uPP DMA Channel I Status 0 Register (UPIS0) .........................................................
29.3.17 uPP DMA Channel I Status 1 Register (UPIS1) .........................................................
29.3.18 uPP DMA Channel I Status 2 Register (UPIS2) .........................................................
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SPRUH80C – April 2013 – Revised September 2016
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29.3.19
29.3.20
29.3.21
29.3.22
29.3.23
29.3.24
30
uPP DMA
uPP DMA
uPP DMA
uPP DMA
uPP DMA
uPP DMA
Channel
Channel
Channel
Channel
Channel
Channel
Q Descriptor 0 Register (UPQD0) .................................................
Q Descriptor 1 Register (UPQD1) .................................................
Q Descriptor 2 Register (UPQD2) .................................................
Q Status 0 Register (UPQS0) ......................................................
Q Status 1 Register (UPQS1) ......................................................
Q Status 2 Register (UPQS2) ......................................................
Universal Serial Bus 2.0 (USB) Controller
30.1
30.2
30.3
30.4
1419
1419
1420
1421
1421
1422
.......................................................................... 1423
Introduction ...............................................................................................................
30.1.1 Purpose of the Peripheral ....................................................................................
30.1.2 Features ........................................................................................................
30.1.3 Functional Block Diagram ....................................................................................
30.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
30.2.1 Clock Control ..................................................................................................
30.2.2 Signal Descriptions............................................................................................
30.2.3 Indexed and Non-Indexed Registers .......................................................................
30.2.4 USB PHY Initialization ........................................................................................
30.2.5 VBUS Voltage Sourcing Control ............................................................................
30.2.6 Dynamic FIFO Sizing .........................................................................................
30.2.7 USB Controller Host and Peripheral Modes Operation ..................................................
30.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ............................
30.2.9 Test Modes.....................................................................................................
30.2.10 Reset Considerations .......................................................................................
30.2.11 Interrupt Support .............................................................................................
30.2.12 DMA Event Support .........................................................................................
30.2.13 Power Management .........................................................................................
Use Cases................................................................................................................
30.3.1 User Case 1: Example of How to Initialize the USB Controller .........................................
30.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode .................
30.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode........................
30.3.4 User Case 4: Example of How to Program the USB DMA Controller ..................................
Registers .................................................................................................................
30.4.1 Revision Identification Register (REVID) ...................................................................
30.4.2 Control Register (CTRLR)....................................................................................
30.4.3 Status Register (STATR) .....................................................................................
30.4.4 Emulation Register (EMUR) .................................................................................
30.4.5 Mode Register (MODE) ......................................................................................
30.4.6 Auto Request Register (AUTOREQ) .......................................................................
30.4.7 SRP Fix Time Register (SRPFIXTIME) ....................................................................
30.4.8 Teardown Register (TEARDOWN)..........................................................................
30.4.9 USB Interrupt Source Register (INTSRCR) ...............................................................
30.4.10 USB Interrupt Source Set Register (INTSETR)..........................................................
30.4.11 USB Interrupt Source Clear Register (INTCLRR) .......................................................
30.4.12 USB Interrupt Mask Register (INTMSKR) ................................................................
30.4.13 USB Interrupt Mask Set Register (INTMSKSETR) ......................................................
30.4.14 USB Interrupt Mask Clear Register (INTMSKCLRR) ...................................................
30.4.15 USB Interrupt Source Masked Register (INTMASKEDR) ..............................................
30.4.16 USB End of Interrupt Register (EOIR) ....................................................................
30.4.17 Generic RNDIS EP1 Size Register (GENRNDISSZ1) .................................................
30.4.18 Generic RNDIS EP2 Size Register (GENRNDISSZ2) .................................................
30.4.19 Generic RNDIS EP3 Size Register (GENRNDISSZ3) .................................................
30.4.20 Generic RNDIS EP4 Size Register (GENRNDISSZ4) .................................................
30.4.21 Function Address Register (FADDR) .....................................................................
SPRUH80C – April 2013 – Revised September 2016
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30.4.22 Power Management Register (POWER) .................................................................
30.4.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................
30.4.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .............................................
30.4.25 Interrupt Enable Register for INTRTX (INTRTXE) ......................................................
30.4.26 Interrupt Enable Register for INTRRX (INTRRXE) ......................................................
30.4.27 Interrupt Register for Common USB Interrupts (INTRUSB)............................................
30.4.28 Interrupt Enable Register for INTRUSB (INTRUSBE) ..................................................
30.4.29 Frame Number Register (FRAME) ........................................................................
30.4.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX)..................
30.4.31 Register to Enable the USB 2.0 Test Modes (TESTMODE) ...........................................
30.4.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)...........................
30.4.33 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..........................
30.4.34 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...............................
30.4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ..........................
30.4.36 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...............................
30.4.37 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ...........................
30.4.38 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..........................
30.4.39 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...............................
30.4.40 Count 0 Register (COUNT0) ...............................................................................
30.4.41 Receive Count Register (RXCOUNT) .....................................................................
30.4.42 Type Register (Host mode only) (HOST_TYPE0) ......................................................
30.4.43 Transmit Type Register (Host mode only) (HOST_TXTYPE) .........................................
30.4.44 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ..........................................
30.4.45 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................
30.4.46 Receive Type Register (Host mode only) (HOST_RXTYPE) .........................................
30.4.47 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................
30.4.48 Configuration Data Register (CONFIGDATA) ...........................................................
30.4.49 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .........................................
30.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .........................................
30.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .........................................
30.4.52 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .........................................
30.4.53 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .........................................
30.4.54 Device Control Register (DEVCTL) .......................................................................
30.4.55 Transmit Endpoint FIFO Size (TXFIFOSZ)...............................................................
30.4.56 Receive Endpoint FIFO Size (RXFIFOSZ) ...............................................................
30.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR) ......................................................
30.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) ......................................................
30.4.59 Hardware Version Register (HWVERS) ..................................................................
30.4.60 Transmit Function Address (TXFUNCADDR) ............................................................
30.4.61 Transmit Hub Address (TXHUBADDR) ...................................................................
30.4.62 Transmit Hub Port (TXHUBPORT) ........................................................................
30.4.63 Receive Function Address (RXFUNCADDR) ............................................................
30.4.64 Receive Hub Address (RXHUBADDR) ...................................................................
30.4.65 Receive Hub Port (RXHUBPORT) ........................................................................
30.4.66 CDMA Revision Identification Register (DMAREVID) ..................................................
30.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ................................
30.4.68 CDMA Emulation Control Register (DMAEMU) .........................................................
30.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3]) ...............
30.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3]) ...............
30.4.71 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]RXHPCRA[3]) ...................................................................................................
30.4.72 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]RXHPCRB[3]) ...................................................................................................
30.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL) ............................................
20
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SPRUH80C – April 2013 – Revised September 2016
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30.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63]) ...................................
30.4.75 Queue Manager Revision Identification Register (QMGRREVID) ....................................
30.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................
30.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ...................
30.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ...................
30.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ...................
30.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ...................
30.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ..................
30.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ..............................
30.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ..................
30.4.84 Queue Manager Queue Pending Register 0 (PEND0) .................................................
30.4.85 Queue Manager Queue Pending Register 1 (PEND1) .................................................
30.4.86 Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]QMEMRBASE[15]) .............................................................................................
30.4.87 Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ...
30.4.88 Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]) ..............................
30.4.89 Queue Manager Queue N Status Register A (QSTATA[0]-QSTATA[63]) ...........................
30.4.90 Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) ...........................
30.4.91 Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) ...........................
31
1560
1562
1562
1563
1564
1565
1566
1566
1567
1567
1568
1568
1569
1570
1571
1572
1572
1573
Video Port Interface (VPIF) ............................................................................................... 1574
31.1
31.2
31.3
Introduction ...............................................................................................................
31.1.1 Overview .......................................................................................................
31.1.2 Features ........................................................................................................
31.1.3 Features Not Supported ......................................................................................
31.1.4 Functional Block Diagram ....................................................................................
Architecture ..............................................................................................................
31.2.1 Clock Control ..................................................................................................
31.2.2 Signal Descriptions............................................................................................
31.2.3 Memory Interface ..............................................................................................
31.2.4 Video Transmit ................................................................................................
31.2.5 Video Receive .................................................................................................
31.2.6 Raw Data Capture ............................................................................................
31.2.7 VBI Ancillary Data .............................................................................................
31.2.8 Reset Considerations .........................................................................................
31.2.9 Initialization .....................................................................................................
31.2.10 Interrupt Support .............................................................................................
Registers .................................................................................................................
31.3.1 VPIF Revision Register ID (REVID) ........................................................................
31.3.2 Channel 0 Control Register (C0CTRL) .....................................................................
31.3.3 Channel 1 Control Register (C1CTRL) .....................................................................
31.3.4 Channel 2 Control Register (C2CTRL) .....................................................................
31.3.5 Channel 3 Control Register (C3CTRL) .....................................................................
31.3.6 Interrupt Enable Register (INTEN) ..........................................................................
31.3.7 Interrupt Enable Set Register (INTSET)....................................................................
31.3.8 Interrupt Enable Clear Register (INTCLR) .................................................................
31.3.9 Interrupt Status Register (INTSTAT) .......................................................................
31.3.10 Interrupt Status Clear Register (INTSTATCLR) .........................................................
31.3.11 Emulation Suspend Control Register (EMUCTRL) ......................................................
31.3.12 DMA Size Control Register (REQSIZE) ..................................................................
31.3.13 Channel n Top Field Luminance Address Register (CnTLUMA) ......................................
31.3.14 Channel n Bottom Field Luminance Address Register (CnBLUMA) ..................................
31.3.15 Channel n Top Field Chrominance Address Register (CnTCHROMA) ...............................
31.3.16 Channel n Bottom Field Chrominance Address Register (CnBCHROMA)...........................
SPRUH80C – April 2013 – Revised September 2016
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Contents
1575
1575
1576
1576
1576
1579
1579
1579
1581
1583
1584
1585
1588
1590
1591
1591
1600
1603
1603
1605
1606
1608
1610
1611
1612
1613
1614
1615
1615
1616
1616
1617
1617
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31.3.17 Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) ............................
31.3.18 Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) ........................
31.3.19 Channel n Top Field Vertical Ancillary Address Register (CnTVANC) ...............................
31.3.20 Channel n Bottom Field Vertical Ancillary Address Register (CnBVANC) ...........................
31.3.21 Channel n Image Address Offset Register (CnIMGOFFSET) .........................................
31.3.22 Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) .......................
31.3.23 Channel n Horizontal Size Configuration Register (C0HCFG and C1HCFG) .......................
31.3.24 Channel n Vertical Size Configuration 0 Register (C0VCFG0 and C1VCFG0) .....................
31.3.25 Channel n Vertical Size Configuration 1 Register (C0VCFG1 and C1VCFG1) .....................
31.3.26 Channel n Vertical Size Configuration 2 Register (C0VCFG2 and C1VCFG2) .....................
31.3.27 Channel n Vertical Image Size Register (C0VSIZE and C1VSIZE) ...................................
31.3.28 Channel n Horizontal Size Configuration Register (C2HCFG and C3HCFG) .......................
31.3.29 Channel n Vertical Size Configuration 0 Register (C2VCFG0 and C3VCFG0) .....................
31.3.30 Channel n Vertical Size Configuration 1 Register (C2VCFG1 and C3VCFG1) .....................
31.3.31 Channel n Vertical Size Configuration 2 Register (C2VCFG2 and C3VCFG2) .....................
31.3.32 Channel n Vertical Image Size Register (C2VSIZE and C3VSIZE) ...................................
31.3.33 Channel n Top Field Horizontal Ancillary Position Register (C2THANCPOS and
C3THANCPOS) ................................................................................................
31.3.34 Channel n Top Field Horizontal Ancillary Size Register (C2THANCSIZE and C3THANCSIZE) ..
31.3.35 Channel n Bottom Field Horizontal Ancillary Position Register (C2BHANCPOS and
C3BHANCPOS) ................................................................................................
31.3.36 Channel n Bottom Field Horizontal Ancillary Size Register (C2BHANCSIZE and
C3BHANCSIZE) ................................................................................................
31.3.37 Channel n Top Field Vertical Ancillary Position Register (C2TVANCPOS and C3TVANCPOS) .
31.3.38 Channel n Top Field Vertical Ancillary Size Register (C2TVANCSIZE and C3TVANCSIZE) .....
31.3.39 Channel n Bottom Field Vertical Ancillary Position Register (C2BVANCPOS and
C3BVANCPOS) ................................................................................................
31.3.40 Channel n Bottom Field Vertical Ancillary Size Register (C2BVANCSIZE and C3BVANCSIZE) .
1618
1618
1619
1619
1620
1620
1621
1622
1622
1623
1623
1624
1625
1625
1626
1626
1627
1628
1629
1630
1631
1632
1633
1634
Revision History ...................................................................................................................... 1635
22
Contents
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
1-1.
TMS320C6746 DSP Block Diagram ..................................................................................... 74
2-1.
TMS320C674x Megamodule Block Diagram ........................................................................... 76
3-1.
System Interconnect Block Diagram ..................................................................................... 85
5-1.
MPU Block Diagram
5-2.
Permission Fields
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
....................................................................................................... 89
.......................................................................................................... 91
Revision ID Register (REVID) ............................................................................................ 96
Configuration Register (CONFIG) ........................................................................................ 97
Interrupt Raw Status/Set Register (IRAWSTAT) ....................................................................... 98
Interrupt Enable Status/Clear Register (IENSTAT) .................................................................... 99
Interrupt Enable Set Register (IENSET) ............................................................................... 100
Interrupt Enable Clear Register (IENCLR) ............................................................................ 100
Fixed Range Start Address Register (FXD_MPSAR) ................................................................ 101
Fixed Range End Address Register (FXD_MPEAR) ................................................................. 101
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ........................................ 102
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) ...................................... 103
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ....................................... 104
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) ......................... 105
Fault Address Register (FLTADDRR) .................................................................................. 106
Fault Status Register (FLTSTAT) ....................................................................................... 107
Fault Clear Register (FLTCLR) ......................................................................................... 108
Overall Clocking Diagram................................................................................................ 111
USB Clocking Diagram................................................................................................... 113
DDR2/mDDR Memory Controller Clocking Diagram ................................................................. 115
EMIFA Clocking Diagram ................................................................................................ 116
EMAC Clocking Diagram ................................................................................................ 117
uPP Clocking Diagram ................................................................................................... 119
McASP Clocking Diagram ............................................................................................... 120
PLLC Structure ............................................................................................................ 124
PLLC0 Revision Identification Register (REVID) ..................................................................... 129
PLLC1 Revision Identification Register (REVID) ..................................................................... 130
Reset Type Status Register (RSTYPE) ................................................................................ 130
Reset Control Register (RSCTRL) ..................................................................................... 131
PLLC0 Control Register (PLLCTL) ..................................................................................... 132
PLLC1 Control Register (PLLCTL) ..................................................................................... 133
PLLC0 OBSCLK Select Register (OCSEL) ........................................................................... 134
PLLC1 OBSCLK Select Register (OCSEL) ........................................................................... 135
PLL Multiplier Control Register (PLLM) ................................................................................ 136
PLLC0 Pre-Divider Control Register (PREDIV) ....................................................................... 136
PLLC0 Divider 1 Register (PLLDIV1) .................................................................................. 137
PLLC1 Divider 1 Register (PLLDIV1) .................................................................................. 137
PLLC0 Divider 2 Register (PLLDIV2) ................................................................................. 138
PLLC1 Divider 2 Register (PLLDIV2) ................................................................................. 138
PLLC0 Divider 3 Register (PLLDIV3) ................................................................................. 139
PLLC1 Divider 3 Register (PLLDIV3) ................................................................................. 139
PLLC0 Divider 4 Register (PLLDIV4) .................................................................................. 140
PLLC0 Divider 5 Register (PLLDIV5) .................................................................................. 140
PLLC0 Divider 6 Register (PLLDIV6) .................................................................................. 141
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
23
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7-21.
PLLC0 Divider 7 Register (PLLDIV7) .................................................................................. 141
7-22.
PLLC0 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 142
7-23.
PLLC1 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 142
7-24.
PLL Post-Divider Control Register (POSTDIV) ....................................................................... 143
7-25.
PLL Controller Command Register (PLLCMD)
143
7-26.
PLL Controller Status Register (PLLSTAT)
144
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
9-1.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
24
.......................................................................
...........................................................................
PLLC0 Clock Align Control Register (ALNCTL) ......................................................................
PLLC1 Clock Align Control Register (ALNCTL) ......................................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC0 Clock Enable Control Register (CKEN) .......................................................................
PLLC1 Clock Enable Control Register (CKEN) .......................................................................
PLLC0 Clock Status Register (CKSTAT) ..............................................................................
PLLC1 Clock Status Register (CKSTAT) ..............................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ..........................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ..........................................................................
Emulation Performance Counter 0 Register (EMUCNT0) ...........................................................
Emulation Performance Counter 1 Register (EMUCNT1) ...........................................................
Revision Identification Register (REVID) ..............................................................................
Interrupt Evaluation Register (INTEVAL) ..............................................................................
PSC0 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC1 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC0 Module Error Clear Register 0 (MERRCR0) ..................................................................
PSC1 Module Error Clear Register 0 (MERRCR0) ..................................................................
Power Error Pending Register (PERRPR) ............................................................................
Power Error Clear Register (PERRCR) ................................................................................
Power Domain Transition Command Register (PTCMD)............................................................
Power Domain Transition Status Register (PTSTAT) ................................................................
Power Domain 0 Status Register (PDSTAT0) ........................................................................
Power Domain 1 Status Register (PDSTAT1) ........................................................................
Power Domain 0 Control Register (PDCTL0) .........................................................................
Power Domain 1 Control Register (PDCTL1) .........................................................................
Power Domain 0 Configuration Register (PDCFG0) .................................................................
Power Domain 1 Configuration Register (PDCFG1) .................................................................
Module Status n Register (MDSTATn) .................................................................................
PSC0 Module Control n Register (MDCTLn) .........................................................................
PSC1 Module Control n Register (MDCTLn) .........................................................................
Deep Sleep Mode Sequence ............................................................................................
Revision Identification Register (REVID) ..............................................................................
Device Identification Register 0 (DEVIDR0) ...........................................................................
Boot Configuration Register (BOOTCFG) .............................................................................
Chip Revision Identification Register (CHIPREVIDR)................................................................
Kick 0 Register (KICK0R) ................................................................................................
Kick 1 Register (KICK1R) ................................................................................................
Host 1 Configuration Register (HOST1CFG) .........................................................................
Interrupt Raw Status/Set Register (IRAWSTAT) .....................................................................
Interrupt Enable Status/Clear Register (IENSTAT)...................................................................
Interrupt Enable Register (IENSET) ....................................................................................
Interrupt Enable Clear Register (IENCLR) ............................................................................
List of Figures
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146
147
148
149
149
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151
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153
154
154
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167
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169
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171
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191
200
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204
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SPRUH80C – April 2013 – Revised September 2016
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.........................................................................................
Fault Address Register (FLTADDRR) ..................................................................................
Fault Status Register (FLTSTAT) .......................................................................................
Master Priority 0 Register (MSTPRI0) .................................................................................
Master Priority 1 Register (MSTPRI1) .................................................................................
Master Priority 2 Register (MSTPRI2) .................................................................................
Pin Multiplexing Control 0 Register (PINMUX0) ......................................................................
Pin Multiplexing Control 1 Register (PINMUX1) ......................................................................
Pin Multiplexing Control 2 Register (PINMUX2) ......................................................................
Pin Multiplexing Control 3 Register (PINMUX3) ......................................................................
Pin Multiplexing Control 4 Register (PINMUX4) ......................................................................
Pin Multiplexing Control 5 Register (PINMUX5) ......................................................................
Pin Multiplexing Control 6 Register (PINMUX6) ......................................................................
Pin Multiplexing Control 7 Register (PINMUX7) ......................................................................
Pin Multiplexing Control 8 Register (PINMUX8) ......................................................................
Pin Multiplexing Control 9 Register (PINMUX9) ......................................................................
Pin Multiplexing Control 10 Register (PINMUX10) ...................................................................
Pin Multiplexing Control 11 Register (PINMUX11) ...................................................................
Pin Multiplexing Control 12 Register (PINMUX12) ...................................................................
Pin Multiplexing Control 13 Register (PINMUX13) ...................................................................
Pin Multiplexing Control 14 Register (PINMUX14) ...................................................................
Pin Multiplexing Control 15 Register (PINMUX15) ...................................................................
Pin Multiplexing Control 16 Register (PINMUX16) ...................................................................
Pin Multiplexing Control 17 Register (PINMUX17) ...................................................................
Pin Multiplexing Control 18 Register (PINMUX18) ...................................................................
Pin Multiplexing Control 19 Register (PINMUX19) ...................................................................
Suspend Source Register (SUSPSRC) ................................................................................
Chip Signal Register (CHIPSIG) ........................................................................................
Chip Signal Clear Register (CHIPSIG_CLR) ..........................................................................
Chip Configuration 0 Register (CFGCHIP0) ..........................................................................
Chip Configuration 1 Register (CFGCHIP1) ..........................................................................
Chip Configuration 2 Register (CFGCHIP2) ..........................................................................
Chip Configuration 3 Register (CFGCHIP3) ..........................................................................
Chip Configuration 4 Register (CFGCHIP4) ..........................................................................
VTP I/O Control Register (VTPIO_CTL) ...............................................................................
DDR Slew Register (DDR_SLEW) .....................................................................................
Deep Sleep Register (DEEPSLEEP) ...................................................................................
Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................................
Pullup/Pulldown Select Register (PUPD_SEL) .......................................................................
RXACTIVE Control Register (RXACTIVE) ............................................................................
PRU Block Diagram ......................................................................................................
Format 1a: (All Arithmetic and Logical Functions – Register Op2).................................................
Format 1b: (All Arithmetic and Logical Functions – Immediate Op2) ..............................................
Format 2 ...................................................................................................................
Format 2a: (JMP,JAL – Register Op2) .................................................................................
Format 2b: (JMP, JAL – Immediate Op2) .............................................................................
Format 2c: (LDI)...........................................................................................................
Format 2d: (LMBD - Leftmost Bit Detect - Register Op2) ...........................................................
Format 2e: (LMBD - Immediate Op2) ..................................................................................
10-12. End of Interrupt Register (EOI)
207
10-13.
207
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
208
209
210
211
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240
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253
256
257
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292
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293
12-11.
294
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
26
.....................................................................................
Format 2g: (SCAN - Immediate Op2) ..................................................................................
Format 2h: (HALT) ........................................................................................................
Format 2i: (SLP) ..........................................................................................................
Format 4a: (Quick Arithmetic Test and Branch – Register Op2) ...................................................
Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2).................................................
Format 5a: (Quick Bit Test and Branch – Register Op2) ............................................................
Format 5b: (Quick Bit Test and Branch – Immediate Op2) .........................................................
Format 6a: (LBBO/SBBO - Register Offset)...........................................................................
Format 6b: (LBBO/SBBO - Immediate Offset) ........................................................................
Format 6c: (LBCO/SBCO - Register Offset) ..........................................................................
Format 6d: (LBCO/SBCO - Immediate Offset) ........................................................................
..............................................................................................................................
..............................................................................................................................
CONTROL Register ......................................................................................................
STATUS Register .........................................................................................................
WAKEUP Register ........................................................................................................
CYCLECNT Register .....................................................................................................
STALLCNT Register ......................................................................................................
CONTABBLKIDX0 Register .............................................................................................
CONTABPROPTR0 Register ...........................................................................................
CONTABPROPTR1 Register ...........................................................................................
INTGPR0 to INTGPR31 Register .......................................................................................
INTCTER0 to INTCTER31 Register ....................................................................................
Data Paths to DDR2/mDDR Memory Controller ......................................................................
DDR2/mDDR Memory Controller Clock Block Diagram .............................................................
DDR2/mDDR Memory Controller Signals .............................................................................
Refresh Command........................................................................................................
DCAB Command..........................................................................................................
DEAC Command..........................................................................................................
ACTV Command ..........................................................................................................
DDR2/mDDR READ Command.........................................................................................
DDR2/mDDR WRT Command ..........................................................................................
DDR2/mDDR MRS and EMRS Command ............................................................................
Byte Alignment ............................................................................................................
DDR2/mDDR SDRAM Column, Row, and Bank Access ............................................................
Address Mapping Diagram (IBANKPOS = 1) .........................................................................
SDRAM Column, Row, Bank Access (IBANKPOS = 1) .............................................................
DDR2/mDDR Memory Controller FIFO Block Diagram ..............................................................
DDR2/mDDR Memory Controller Reset Block Diagram .............................................................
DDR2/mDDR Memory Controller Power Sleep Controller Diagram ...............................................
Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory .........................................
Revision ID Register (REVID) ...........................................................................................
SDRAM Status Register (SDRSTAT) .................................................................................
SDRAM Configuration Register (SDCR) ..............................................................................
SDRAM Refresh Control Register (SDRCR) .........................................................................
SDRAM Timing Register 1 (SDTIMR1) ................................................................................
SDRAM Timing Register 2 (SDTIMR2) ................................................................................
SDRAM Configuration Register 2 (SDCR2) ..........................................................................
12-10. Format 2f: (SCAN - Register Op2)
List of Figures
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306
311
313
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314
315
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SPRUH80C – April 2013 – Revised September 2016
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13-26. Peripheral Bus Burst Priority Register (PBBPR) ...................................................................... 373
...............................................................................
...............................................................................
Performance Counter Configuration Register (PCC) ................................................................
Performance Counter Master Region Select Register (PCMRS) ..................................................
Performance Counter Time Register (PCT) ...........................................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) ............................................................................................
Interrupt Masked Register (IMR)........................................................................................
Interrupt Mask Set Register (IMSR) ....................................................................................
Interrupt Mask Clear Register (IMCR) .................................................................................
DDR PHY Control Register 1 (DRPYC1R) ............................................................................
Multiple eCAP Modules ..................................................................................................
Capture and APWM Modes of Operation..............................................................................
Capture Function Diagram...............................................................................................
Event Prescale Control...................................................................................................
Prescale Function Waveforms ..........................................................................................
Continuous/One-shot Block Diagram ..................................................................................
Counter and Synchronization Block Diagram .........................................................................
Interrupts in eCAP Module ..............................................................................................
PWM Waveform Details Of APWM Mode Operation ................................................................
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ................................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ..................................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect .............................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ...............................
PWM Waveform Details of APWM Mode Operation .................................................................
Multichannel PWM Example Using 4 eCAP Modules................................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules .......................................
Time-Stamp Counter Register (TSCTR) ...............................................................................
Counter Phase Control Register (CTRPHS) .........................................................................
Capture 1 Register (CAP1) .............................................................................................
Capture 2 Register (CAP2) ..............................................................................................
Capture 3 Register (CAP3) ..............................................................................................
Capture 4 Register (CAP4) ..............................................................................................
ECAP Control Register 1 (ECCTL1) ...................................................................................
ECAP Control Register 2 (ECCTL2) ...................................................................................
ECAP Interrupt Enable Register (ECEINT)............................................................................
ECAP Interrupt Flag Register (ECFLG)................................................................................
ECAP Interrupt Clear Register (ECCLR) ..............................................................................
ECAP Interrupt Forcing Register (ECFRC)............................................................................
Revision ID Register (REVID) ...........................................................................................
Multiple ePWM Modules .................................................................................................
Submodules and Signal Connections for an ePWM Module........................................................
ePWM Submodules and Critical Internal Signal Interconnects .....................................................
Time-Base Submodule Block Diagram ................................................................................
Time-Base Submodule Signals and Registers ........................................................................
Time-Base Frequency and Period ......................................................................................
Time-Base Counter Synchronization Scheme 1 ......................................................................
Time-Base Up-Count Mode Waveforms ...............................................................................
13-27. Performance Counter 1 Register (PC1)
374
13-28. Performance Counter 2 Register (PC2)
374
13-29.
375
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
377
378
378
379
379
380
381
382
385
386
387
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392
393
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15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
...........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event .....
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ........
Counter-Compare Submodule ..........................................................................................
Counter-Compare Submodule Signals and Registers ...............................................................
Counter-Compare Event Waveforms in Up-Count Mode ............................................................
Counter-Compare Events in Down-Count Mode .....................................................................
Time-Base Down-Count Mode Waveforms
439
439
440
441
441
444
444
15-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................... 445
15-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ....................................................................................................................... 445
15-18. Action-Qualifier Submodule
.............................................................................................
446
15-19. Action-Qualifier Submodule Inputs and Outputs ...................................................................... 447
15-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ........................................... 448
15-21. Up-Down-Count Mode Symmetrical Waveform ....................................................................... 451
15-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................. 452
15-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................... 454
15-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............. 456
15-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................. 458
15-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ........................................................................................... 460
15-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ......................................................................................................................... 462
15-28. Dead-Band Generator Submodule ..................................................................................... 464
15-29. Configuration Options for the Dead-Band Generator Submodule .................................................. 465
15-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................... 467
15-31. PWM-Chopper Submodule .............................................................................................. 468
15-32. PWM-Chopper Submodule Signals and Registers ................................................................... 469
15-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................ 470
15-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
.......
470
15-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ...................................................................................................................... 471
15-36. Trip-Zone Submodule .................................................................................................... 472
15-37. Trip-Zone Submodule Mode Control Logic ............................................................................ 475
15-38. Trip-Zone Submodule Interrupt Logic .................................................................................. 475
476
15-40.
477
15-41.
15-42.
15-43.
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
28
...............................................................................................
Event-Trigger Submodule Inter-Connectivity to Interrupt Controller ...............................................
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ........................................
Event-Trigger Interrupt Generator ......................................................................................
HRPWM System Interface ...............................................................................................
Resolution Calculations for Conventionally Generated PWM .......................................................
Operating Logic Using MEP .............................................................................................
Required PWM Waveform for a Requested Duty = 40.5% .........................................................
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ................................
High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ................................
Simplified ePWM Module ................................................................................................
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ......................................
Control of Four Buck Stages. (Note: FPWM1≠ FPWM2≠ FPWM3≠ FPWM4) ..................................................
15-39. Event-Trigger Submodule
List of Figures
477
479
480
481
482
484
486
486
487
488
489
SPRUH80C – April 2013 – Revised September 2016
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15-52. Buck Waveforms for (Note: Only three bucks shown here) ......................................................... 490
15-53. Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) ............................................................. 492
15-54. Buck Waveforms for (Note: FPWM2 = FPWM1)............................................................................. 493
15-55. Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) ........................................................... 495
15-56. Half-H Bridge Waveforms for (Note: FPWM2 = FPWM1) .................................................................. 496
15-57. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................... 498
15-58. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ....................................................... 499
15-59. Configuring Two PWM Modules for Phase Control .................................................................. 502
15-60. Timing Waveforms Associated With Phase Control Between 2 Modules ......................................... 503
15-61. Control of a 3-Phase Interleaved DC/DC Converter ................................................................. 504
.............................................................
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1 ) ....................................................................
ZVS Full-H Bridge Waveforms ..........................................................................................
Time-Base Control Register (TBCTL) ..................................................................................
Time-Base Status Register (TBSTS) ...................................................................................
Time-Base Phase Register (TBPHS) ..................................................................................
Time-Base Counter Register (TBCNT) ................................................................................
Time-Base Period Register (TBPRD) ..................................................................................
Counter-Compare Control Register (CMPCTL) .......................................................................
Counter-Compare A Register (CMPA) ................................................................................
Counter-Compare B Register (CMPB) .................................................................................
Action-Qualifier Output A Control Register (AQCTLA)...............................................................
Action-Qualifier Output B Control Register (AQCTLB)...............................................................
Action-Qualifier Software Force Register (AQSFRC) ................................................................
Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................
Dead-Band Generator Control Register (DBCTL) ....................................................................
Dead-Band Generator Rising Edge Delay Register (DBRED) ......................................................
Dead-Band Generator Falling Edge Delay Register (DBFED) .....................................................
PWM-Chopper Control Register (PCCTL) .............................................................................
Trip-Zone Select Register (TZSEL) ....................................................................................
Trip-Zone Control Register (TZCTL) ...................................................................................
Trip-Zone Enable Interrupt Register (TZEINT) ........................................................................
Trip-Zone Flag Register (TZFLG).......................................................................................
Trip-Zone Clear Register (TZCLR) .....................................................................................
Trip-Zone Force Register (TZFRC).....................................................................................
Event-Trigger Selection Register (ETSEL) ............................................................................
Event-Trigger Prescale Register (ETPS) ..............................................................................
Event-Trigger Flag Register (ETFLG) ..................................................................................
Event-Trigger Clear Register (ETCLR) ................................................................................
Event-Trigger Force Register (ETFRC) ................................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) ..........................................................
Counter-Compare A High-Resolution Register (CMPAHR) .........................................................
HRPWM Configuration Register (HRCNFG) ..........................................................................
EDMA3 Controller Block Diagram ......................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram ...........................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................
Definition of ACNT, BCNT, and CCNT ................................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................
15-62. 3-Phase Interleaved DC/DC Converter Waveforms for
505
15-63.
508
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
15-72.
15-73.
15-74.
15-75.
15-76.
15-77.
15-78.
15-79.
15-80.
15-81.
15-82.
15-83.
15-84.
15-85.
15-86.
15-87.
15-88.
15-89.
15-90.
15-91.
15-92.
15-93.
15-94.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
509
511
513
514
514
515
516
517
518
519
520
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16-7.
PaRAM Set ................................................................................................................ 548
16-8.
Linked Transfer Example ................................................................................................ 556
16-9.
Link-to-Self Transfer Example
..........................................................................................
557
16-10. QDMA Channel to PaRAM Mapping ................................................................................... 564
16-11. Shadow Region Registers ............................................................................................... 566
16-12. Interrupt Diagram ......................................................................................................... 571
16-13. Error Interrupt Operation ................................................................................................. 574
16-14. EDMA3 Prioritization ..................................................................................................... 581
16-15. Block Move Example ..................................................................................................... 585
16-16. Block Move Example PaRAM Configuration .......................................................................... 586
..........................................................................................
Subframe Extraction Example PaRAM Configuration................................................................
Data Sorting Example ....................................................................................................
Data Sorting Example PaRAM Configuration .........................................................................
Servicing Incoming McBSP Data Example ............................................................................
Servicing Incoming McBSP Data Example PaRAM ..................................................................
Servicing Peripheral Burst Example ....................................................................................
Servicing Peripheral Burst Example PaRAM..........................................................................
Servicing Continuous McBSP Data Example .........................................................................
Servicing Continuous McBSP Data Example PaRAM ...............................................................
Servicing Continuous McBSP Data Example Reload PaRAM ......................................................
Ping-Pong Buffering for McBSP Data Example ......................................................................
Ping-Pong Buffering for McBSP Example PaRAM ...................................................................
Ping-Pong Buffering for McBSP Example Pong PaRAM ............................................................
Ping-Pong Buffering for McBSP Example Ping PaRAM .............................................................
Intermediate Transfer Completion Chaining Example ...............................................................
Single Large Block Transfer Example .................................................................................
Smaller Packet Data Transfers Example ..............................................................................
Channel Options Parameter (OPT).....................................................................................
Channel Source Address Parameter (SRC) ..........................................................................
A Count/B Count Parameter (A_B_CNT) ..............................................................................
Channel Destination Address Parameter (DST) ......................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ...............................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) ......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ...............................................
C Count Parameter (CCNT) .............................................................................................
Revision ID Register (REVID) ...........................................................................................
EDMA3CC Configuration Register (CCCFG) .........................................................................
QDMA Channel n Mapping Register (QCHMAPn) ...................................................................
DMA Channel Queue Number Register n (DMAQNUMn) ...........................................................
QDMA Channel Queue Number Register (QDMAQNUM) ..........................................................
Event Missed Register (EMR)...........................................................................................
Event Missed Clear Register (EMCR) .................................................................................
QDMA Event Missed Register (QEMR)................................................................................
QDMA Event Missed Clear Register (QEMCR) ......................................................................
EDMA3CC Error Register (CCERR) ...................................................................................
EDMA3CC Error Clear Register (CCERRCLR).......................................................................
Error Evaluate Register (EEVAL) .......................................................................................
DMA Region Access Enable Register for Region m (DRAEm) .....................................................
16-17. Subframe Extraction Example
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
30
List of Figures
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587
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620
621
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624
SPRUH80C – April 2013 – Revised September 2016
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16-56. QDMA Region Access Enable for Region m (QRAEm) ............................................................. 625
16-57. Event Queue Entry Registers (QxEy) .................................................................................. 626
16-58. Queue n Status Register (QSTATn)
...................................................................................
627
16-59. Queue Watermark Threshold A Register (QWMTHRA) ............................................................. 628
16-60. EDMA3CC Status Register (CCSTAT)
................................................................................
629
16-61. Event Register (ER) ...................................................................................................... 631
16-62. Event Clear Register (ECR) ............................................................................................. 632
16-63. Event Set Register (ESR)................................................................................................ 633
.........................................................................................
16-65. Event Enable Register (EER) ...........................................................................................
16-66. Event Enable Clear Register (EECR) ..................................................................................
16-67. Event Enable Set Register (EESR) ....................................................................................
16-68. Secondary Event Register (SER) .......................................................................................
16-69. Secondary Event Clear Register (SECR) .............................................................................
16-70. Interrupt Enable Register (IER) .........................................................................................
16-71. Interrupt Enable Clear Register (IECR) ................................................................................
16-72. Interrupt Enable Set Register (IESR) ..................................................................................
16-73. Interrupt Pending Register (IPR)........................................................................................
16-74. Interrupt Clear Register (ICR) ...........................................................................................
16-75. Interrupt Evaluate Register (IEVAL) ....................................................................................
16-76. QDMA Event Register (QER) ...........................................................................................
16-77. QDMA Event Enable Register (QEER) ................................................................................
16-78. QDMA Event Enable Clear Register (QEECR) .......................................................................
16-79. QDMA Event Enable Set Register (QEESR) .........................................................................
16-80. QDMA Secondary Event Register (QSER) ............................................................................
16-81. QDMA Secondary Event Clear Register (QSECR) ..................................................................
16-82. Revision ID Register (REVID) ...........................................................................................
16-83. EDMA3TC Configuration Register (TCCFG) ..........................................................................
16-84. EDMA3TC Channel Status Register (TCSTAT) ......................................................................
16-85. Error Status Register (ERRSTAT) ......................................................................................
16-86. Error Enable Register (ERREN) ........................................................................................
16-87. Error Clear Register (ERRCLR) ........................................................................................
16-88. Error Details Register (ERRDET) .......................................................................................
16-89. Error Interrupt Command Register (ERRCMD) .......................................................................
16-90. Read Command Rate Register (RDRATE)............................................................................
16-91. Source Active Options Register (SAOPT) .............................................................................
16-92. Source Active Source Address Register (SASRC) ...................................................................
16-93. Source Active Count Register (SACNT) ...............................................................................
16-94. Source Active Destination Address Register (SADST) ..............................................................
16-95. Source Active B-Index Register (SABIDX) ............................................................................
16-96. Source Active Memory Protection Proxy Register (SAMPPRXY) ..................................................
16-97. Source Active Count Reload Register (SACNTRLD) ................................................................
16-98. Source Active Source Address B-Reference Register (SASRCBREF) ............................................
16-99. Source Active Destination Address B-Reference Register (SADSTBREF) .......................................
16-100. Destination FIFO Set Count Reload Register (DFCNTRLD) ......................................................
16-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) ..................................
16-102. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) .............................
16-103. Destination FIFO Options Register n (DFOPTn) ....................................................................
16-104. Destination FIFO Source Address Register n (DFSRCn) ..........................................................
16-64. Chained Event Register (CER)
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
634
635
636
636
637
637
638
639
639
640
641
642
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644
645
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16-105. Destination FIFO Count Register n (DFCNTn) ...................................................................... 666
16-106. Destination FIFO Destination Address Register n (DFDSTn) ..................................................... 667
16-107. Destination FIFO B-Index Register n (DFBIDXn) ................................................................... 667
16-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) ......................................... 668
17-1.
EMAC and MDIO Block Diagram ....................................................................................... 674
17-2.
Ethernet Configuration—MII Connections ............................................................................. 677
17-3.
Ethernet Configuration—RMII Connections ........................................................................... 679
17-4.
Ethernet Frame Format .................................................................................................. 680
17-5.
Basic Descriptor Format ................................................................................................. 681
17-6.
Typical Descriptor Linked List ........................................................................................... 682
17-7.
Transmit Buffer Descriptor Format ..................................................................................... 685
17-8.
Receive Buffer Descriptor Format ...................................................................................... 688
17-9.
EMAC Control Module Block Diagram ................................................................................. 692
17-10. MDIO Module Block Diagram ........................................................................................... 694
17-11. EMAC Module Block Diagram
..........................................................................................
698
17-12. EMAC Control Module Revision ID Register (REVID) ............................................................... 720
17-13. EMAC Control Module Software Reset Register (SOFTRESET)
..................................................
721
17-14. EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................ 722
17-15. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 723
17-16. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 724
17-17. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 725
17-18. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 726
17-19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 727
17-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 728
17-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 729
.........
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .......
MDIO Revision ID Register (REVID) ...................................................................................
MDIO Control Register (CONTROL) ...................................................................................
PHY Acknowledge Status Register (ALIVE) ..........................................................................
PHY Link Status Register (LINK) .......................................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ......................................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .....................................
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) .............................
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)............................
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ..........................
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ....................
MDIO User Access Register 0 (USERACCESS0) ...................................................................
MDIO User PHY Select Register 0 (USERPHYSEL0) ...............................................................
MDIO User Access Register 1 (USERACCESS1) ...................................................................
MDIO User PHY Select Register 1 (USERPHYSEL1) ...............................................................
Transmit Revision ID Register (TXREVID) ............................................................................
Transmit Control Register (TXCONTROL) ............................................................................
Transmit Teardown Register (TXTEARDOWN) ......................................................................
Receive Revision ID Register (RXREVID) ............................................................................
Receive Control Register (RXCONTROL) .............................................................................
17-22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
32
List of Figures
730
731
732
733
734
735
735
736
737
738
739
740
741
742
743
744
745
749
749
750
751
751
SPRUH80C – April 2013 – Revised September 2016
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17-44. Receive Teardown Register (RXTEARDOWN) ....................................................................... 752
17-45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)............................................... 753
17-46. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ............................................. 754
17-47. Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 755
17-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)..................................................... 756
.......................................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ...............................................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) .............................................
Receive Interrupt Mask Set Register (RXINTMASKSET) ...........................................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .....................................................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ...............................................
MAC Interrupt Mask Set Register (MACINTMASKSET) .............................................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................................
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......................
Receive Unicast Enable Set Register (RXUNICASTSET) ..........................................................
Receive Unicast Clear Register (RXUNICASTCLEAR) .............................................................
Receive Maximum Length Register (RXMAXLEN) ...................................................................
Receive Buffer Offset Register (RXBUFFEROFFSET) ..............................................................
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ..............................
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) .....................................
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ............................................
MAC Control Register (MACCONTROL) ..............................................................................
MAC Status Register (MACSTATUS) ..................................................................................
Emulation Control Register (EMCONTROL) ..........................................................................
FIFO Control Register (FIFOCONTROL) ..............................................................................
MAC Configuration Register (MACCONFIG) .........................................................................
Soft Reset Register (SOFTRESET) ....................................................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO)...................................................
MAC Source Address High Bytes Register (MACSRCADDRHI) ...................................................
MAC Hash Address Register 1 (MACHASH1) ........................................................................
MAC Hash Address Register 2 (MACHASH2) ........................................................................
Back Off Random Number Generator Test Register (BOFFTEST) ................................................
Transmit Pacing Algorithm Test Register (TPACETEST) ...........................................................
Receive Pause Timer Register (RXPAUSE) ..........................................................................
Transmit Pause Timer Register (TXPAUSE)..........................................................................
MAC Address Low Bytes Register (MACADDRLO)..................................................................
MAC Address High Bytes Register (MACADDRHI) ..................................................................
MAC Index Register (MACINDEX) .....................................................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ..........................................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) ..........................................
Transmit Channel n Completion Pointer Register (TXnCP) .........................................................
Receive Channel n Completion Pointer Register (RXnCP) .........................................................
Statistics Register .........................................................................................................
EMIFA Functional Block Diagram ......................................................................................
Timing Waveform of SDRAM PRE Command ........................................................................
EMIFA to 2M × 16 × 4 bank SDRAM Interface .......................................................................
EMIFA to 512K × 16 × 2 bank SDRAM Interface ....................................................................
17-49. MAC Input Vector Register (MACINVECTOR)
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
17-88.
18-1.
18-2.
18-3.
18-4.
SPRUH80C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
757
758
759
760
761
762
763
763
764
764
765
768
769
770
770
771
771
772
773
775
777
777
778
778
779
779
780
780
781
781
782
782
783
784
784
785
785
786
786
787
797
801
802
802
33
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18-5.
Timing Waveform for Basic SDRAM Read Operation ............................................................... 809
18-6.
Timing Waveform for Basic SDRAM Write Operation
18-7.
EMIFA Asynchronous Interface ......................................................................................... 812
18-8.
EMIFA to 8-bit/16-bit Memory Interface................................................................................ 813
18-9.
Common Asynchronous Interface ...................................................................................... 813
...............................................................
810
18-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 818
18-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode .............................................. 820
18-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...................................... 822
18-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 824
18-14. EMIFA to NAND Flash Interface ........................................................................................ 826
18-15. ECC Value for 8-Bit NAND Flash ....................................................................................... 828
18-16. EMIFA Reset Block Diagram ............................................................................................ 831
18-17. EMIFA PSC Block Diagram ............................................................................................. 836
18-18. Example Configuration Interface ........................................................................................ 839
18-19. SDRAM Timing Register (SDTIMR) .................................................................................... 840
18-20. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 841
18-21. SDRAM Refresh Control Register (SDRCR) .......................................................................... 841
18-22. SDRAM Configuration Register (SDCR)............................................................................... 842
................................................................................
Timing Waveform of an ASRAM Write ................................................................................
Timing Waveform of an ASRAM Read with PCB Delays............................................................
Timing Waveform of an ASRAM Write with PCB Delays ............................................................
Timing Waveform of a NAND Flash Read ............................................................................
Timing Waveform of a NAND Flash Command Write ...............................................................
Timing Waveform of a NAND Flash Address Write .................................................................
Timing Waveform of a NAND Flash Data Write .....................................................................
Module ID Register (MIDR)..............................................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) .......................................................
SDRAM Configuration Register (SDCR)...............................................................................
SDRAM Refresh Control Register (SDRCR) ..........................................................................
Asynchronous n Configuration Register (CEnCFG) ..................................................................
SDRAM Timing Register (SDTIMR) ....................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................
EMIFA Interrupt Raw Register (INTRAW) .............................................................................
EMIFA Interrupt Mask Register (INTMSK) ............................................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) ..................................................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) ................................................................
NAND Flash Control Register (NANDFCR) ...........................................................................
NAND Flash Status Register (NANDFSR) ............................................................................
NAND Flash n ECC Register (NANDFnECC) ........................................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ..................................................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..............................................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..............................................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..............................................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..............................................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1).............................................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2).............................................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ................................................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ................................................
18-23. Timing Waveform of an ASRAM Read
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
34
List of Figures
844
845
847
848
853
855
855
856
861
861
863
865
866
868
869
870
871
872
873
874
876
877
878
879
879
880
880
881
881
882
882
SPRUH80C – April 2013 – Revised September 2016
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www.ti.com
19-1.
GPIO Block Diagram ..................................................................................................... 885
19-2.
Revision ID Register (REVID) ........................................................................................... 894
19-3.
GPIO Interrupt Per-Bank Enable Register (BINTEN) ................................................................ 895
19-4.
GPIO Banks 0 and 1 Direction Register (DIR01) ..................................................................... 896
19-5.
GPIO Banks 2 and 3 Direction Register (DIR23) ..................................................................... 896
19-6.
GPIO Banks 4 and 5 Direction Register (DIR45) ..................................................................... 896
19-7.
GPIO Banks 6 and 7 Direction Register (DIR67) ..................................................................... 896
19-8.
GPIO Bank 8 Direction Register (DIR8) ............................................................................... 897
19-9.
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) ....................................................... 898
19-10. GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) ....................................................... 898
19-11. GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) ....................................................... 898
19-12. GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) ....................................................... 898
19-13. GPIO Bank 8 Output Data Register (OUT_DATA8)
.................................................................
899
19-14. GPIO Banks 0 and 1 Set Data Register (SET_DATA01)............................................................ 900
19-15. GPIO Banks 2 and 3 Set Data Register (SET_DATA23)............................................................ 900
19-16. GPIO Banks 4 and 5 Set Data Register (SET_DATA45)............................................................ 900
19-17. GPIO Banks 6 and 7 Set Data Register (SET_DATA67)............................................................ 900
19-18. GPIO Bank 8 Set Data Register (SET_DATA8) ...................................................................... 901
19-19. GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) ......................................................... 902
19-20. GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) ......................................................... 902
19-21. GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) ......................................................... 902
19-22. GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) ......................................................... 902
19-23. GPIO Bank 8 Clear Data Register (CLR_DATA8)
...................................................................
903
19-24. GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ............................................................ 904
19-25. GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ............................................................ 904
19-26. GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ............................................................ 904
19-27. GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ............................................................ 904
19-28. GPIO Bank 8 Input Data Register (IN_DATA8)....................................................................... 905
19-29. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01) ............................................. 906
19-30. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) ............................................. 906
19-31. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) ............................................. 906
19-32. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) ............................................. 906
19-33. GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) ........................................................ 907
19-34. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ........................................... 908
19-35. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) ........................................... 908
19-36. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ........................................... 908
19-37. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ........................................... 908
19-38. GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) ..................................................... 909
19-39. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) ............................................. 910
19-40. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) ............................................. 910
19-41. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) ............................................. 910
19-42. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) ............................................. 910
19-43. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8) ....................................................... 911
19-44. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) .......................................... 912
19-45. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) .......................................... 912
19-46. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) .......................................... 912
19-47. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) .......................................... 912
19-48. GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) ..................................................... 913
19-49. GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ...................................................... 914
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
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19-50. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ...................................................... 914
19-51. GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) ...................................................... 914
19-52. GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) ...................................................... 914
19-53. GPIO Bank 8 Interrupt Status Register (INTSTAT8) ................................................................. 915
.......................................................................................................
20-1.
HPI Block Diagram
20-2.
Example of Host-Processor Signal Connections ..................................................................... 923
918
20-3.
HPI Strobe and Select Logic ............................................................................................ 925
20-4.
Multiplexed-Mode Host Read Cycle .................................................................................... 927
20-5.
Multiplexed-Mode Host Write Cycle .................................................................................... 928
20-6.
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) ................................................... 929
20-7.
UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode ......................... 930
20-8.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle) .......................................................... 930
20-9.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles) .............................................................. 930
20-10. UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode ................................... 931
20-11. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1:
No Autoincrementing) .................................................................................................... 931
20-12. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2:
Autoincrementing Selected, FIFO Empty Before Write) ............................................................. 931
20-13. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 3:
Autoincrementing Selected, FIFO Not Empty Before Write) ........................................................ 932
20-14. FIFOs in the HPI .......................................................................................................... 933
20-15. Host-to-CPU Interrupt State Diagram .................................................................................. 938
20-16. CPU-to-Host Interrupt State Diagram .................................................................................. 939
20-17. Revision Identification Register (REVID) .............................................................................. 941
................................................
GPIO Enable Register (GPIO_EN) .....................................................................................
GPIO Direction 1 Register (GPIO_DIR1) ..............................................................................
GPIO Data 1 Register (GPIO_DAT1) ..................................................................................
GPIO Direction 2 Register (GPIO_DIR2) ..............................................................................
GPIO Data 2 Register (GPIO_DAT2) ..................................................................................
Host Port Interface Control Register (HPIC)–Host Access Permissions ..........................................
Host Port Interface Control Register (HPIC)–CPU Access Permissions ..........................................
Host Port Interface Write Address Register (HPIAW)................................................................
Host Port Interface Read Address Register (HPIAR) ................................................................
I2C Peripheral Block Diagram...........................................................................................
Multiple I2C Modules Connected .......................................................................................
Clocking Diagram for the I2C Peripheral ..............................................................................
Synchronization of Two I2C Clock Generators During Arbitration .................................................
Bit Transfer on the I2C-Bus .............................................................................................
I2C Peripheral START and STOP Conditions ........................................................................
I2C Peripheral Data Transfer ............................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) ............................................
20-18. Power and Emulation Management Register (PWREMU_MGMT)
941
20-19.
942
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
943
943
944
945
946
946
948
948
951
952
953
954
955
955
956
956
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR)......................................................................................................... 957
21-10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR) .............................................................. 957
21-11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR)
...
957
21-12. Arbitration Procedure Between Two Master-Transmitters........................................................... 960
21-13. I2C Own Address Register (ICOAR) ................................................................................... 965
36
List of Figures
SPRUH80C – April 2013 – Revised September 2016
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21-14. I2C Interrupt Mask Register (ICIMR) ................................................................................... 966
21-15. I2C Interrupt Status Register (ICSTR) ................................................................................. 967
21-16. I2C Clock Low-Time Divider Register (ICCLKL) ...................................................................... 970
21-17. I2C Clock High-Time Divider Register (ICCLKH) ..................................................................... 970
21-18. I2C Data Count Register (ICCNT) ...................................................................................... 971
21-19. I2C Data Receive Register (ICDRR) ................................................................................... 972
21-20. I2C Slave Address Register (ICSAR) .................................................................................. 973
21-21. I2C Data Transmit Register (ICDXR)
..................................................................................
974
21-22. I2C Mode Register (ICMDR) ............................................................................................ 975
21-23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit .................................... 978
21-24. I2C Interrupt Vector Register (ICIVR) .................................................................................. 979
21-25. I2C Extended Mode Register (ICEMDR) .............................................................................. 980
21-26. I2C Prescaler Register (ICPSC) ........................................................................................ 981
..................................................................... 982
I2C Revision Identification Register 2 (REVID2) ..................................................................... 982
I2C DMA Control Register (ICDMAC) .................................................................................. 983
I2C Pin Function Register (ICPFUNC) ................................................................................. 984
I2C Pin Direction Register (ICPDIR) ................................................................................... 985
I2C Pin Data In Register (ICPDIN) ..................................................................................... 986
I2C Pin Data Out Register (ICPDOUT) ................................................................................ 987
I2C Pin Data Set Register (ICPDSET) ................................................................................. 988
I2C Pin Data Clear Register (ICPDCLR) .............................................................................. 989
McASP Block Diagram ................................................................................................... 993
McASP to Parallel 2-Channel DACs .................................................................................. 994
McASP to 6-Channel DAC and 2-Channel DAC ..................................................................... 994
McASP to Digital Amplifier ............................................................................................... 995
McASP as Digital Audio Encoder ...................................................................................... 995
TDM Format–6 Channel TDM Example ............................................................................... 996
TDM Format Bit Delays from Frame Sync ............................................................................ 997
Inter-IC Sound (I2S) Format ............................................................................................. 997
Biphase-Mark Code (BMC) .............................................................................................. 998
S/PDIF Subframe Format ................................................................................................ 999
S/PDIF Frame Format .................................................................................................. 1000
Definition of Bit, Word, and Slot ....................................................................................... 1001
Bit Order and Word Alignment Within a Slot Examples ............................................................ 1002
Definition of Frame and Frame Sync Width ......................................................................... 1003
Transmit Clock Generator Block Diagram ........................................................................... 1005
Receive Clock Generator Block Diagram ............................................................................ 1006
Frame Sync Generator Block Diagram .............................................................................. 1007
Individual Serializer and Connections Within McASP .............................................................. 1008
Receive Format Unit .................................................................................................... 1009
Transmit Format Unit ................................................................................................... 1010
McASP I/O Pin Control Block Diagram ............................................................................... 1012
McASP I/O Pin to Control Register Mapping ........................................................................ 1013
Burst Frame Sync Mode................................................................................................ 1018
Transmit DMA Event (AXEVT) Generation in TDM Time Slots ................................................... 1021
DSP Service Time Upon Transmit DMA Event (AXEVT) .......................................................... 1026
DSP Service Time Upon Receive DMA Event (AREVT) ........................................................... 1028
DMA Events in an Audio Example–Two Events .................................................................... 1030
21-27. I2C Revision Identification Register 1 (REVID1)
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
37
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22-28. McASP Audio FIFO (AFIFO) Block Diagram ........................................................................ 1031
22-29. Data Flow Through Transmit Format Unit
...........................................................................
1034
22-30. Data Flow Through Receive Format Unit ............................................................................ 1036
22-31. Audio Mute (AMUTE) Block Diagram ................................................................................. 1038
22-32. Transmit Clock Failure Detection Circuit Block Diagram ........................................................... 1042
1043
22-34.
1044
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
22-51.
22-52.
22-53.
22-54.
22-55.
22-56.
22-57.
22-58.
22-59.
22-60.
22-61.
22-62.
22-63.
22-64.
22-65.
22-66.
22-67.
22-68.
22-69.
22-70.
22-71.
22-72.
22-73.
22-74.
22-75.
22-76.
38
...........................................................
Serializers in Loopback Mode .........................................................................................
Revision Identification Register (REV) ...............................................................................
Pin Function Register (PFUNC) .......................................................................................
Pin Direction Register (PDIR)..........................................................................................
Pin Data Output Register (PDOUT)...................................................................................
Pin Data Input Register (PDIN) ........................................................................................
Pin Data Set Register (PDSET) .......................................................................................
Pin Data Clear Register (PDCLR).....................................................................................
Global Control Register (GBLCTL)....................................................................................
Audio Mute Control Register (AMUTE) ...............................................................................
Digital Loopback Control Register (DLBCTL) .......................................................................
Digital Mode Control Register (DITCTL) .............................................................................
Receiver Global Control Register (RGBLCTL) ......................................................................
Receive Format Unit Bit Mask Register (RMASK) ..................................................................
Receive Bit Stream Format Register (RFMT) .......................................................................
Receive Frame Sync Control Register (AFSRCTL) ................................................................
Receive Clock Control Register (ACLKRCTL) ......................................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ................................................
Receive TDM Time Slot Register (RTDM) ...........................................................................
Receiver Interrupt Control Register (RINTCTL) .....................................................................
Receiver Status Register (RSTAT) ...................................................................................
Current Receive TDM Time Slot Registers (RSLOT) ..............................................................
Receive Clock Check Control Register (RCLKCHK) ...............................................................
Receiver DMA Event Control Register (REVTCTL) ................................................................
Transmitter Global Control Register (XGBLCTL) ...................................................................
Transmit Format Unit Bit Mask Register (XMASK) .................................................................
Transmit Bit Stream Format Register (XFMT) .......................................................................
Transmit Frame Sync Control Register (AFSXCTL) ................................................................
Transmit Clock Control Register (ACLKXCTL) ......................................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ................................................
Transmit TDM Time Slot Register (XTDM) ..........................................................................
Transmitter Interrupt Control Register (XINTCTL) ..................................................................
Transmitter Status Register (XSTAT).................................................................................
Current Transmit TDM Time Slot Register (XSLOT) ...............................................................
Transmit Clock Check Control Register (XCLKCHK)...............................................................
Transmitter DMA Event Control Register (XEVTCTL)..............................................................
Serializer Control Registers (SRCTLn) ...............................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .....................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ....................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5).................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ...............................................
Transmit Buffer Registers (XBUFn) ...................................................................................
Receive Buffer Registers (RBUFn) ...................................................................................
22-33. Receive Clock Failure Detection Circuit Block Diagram
List of Figures
1050
1051
1053
1055
1057
1059
1061
1063
1065
1067
1068
1069
1070
1071
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1096
1097
1097
1098
1098
SPRUH80C – April 2013 – Revised September 2016
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22-77. AFIFO Revision Identification Register (AFIFOREV) ............................................................... 1099
22-78. Write FIFO Control Register (WFIFOCTL) ........................................................................... 1100
22-79. Write FIFO Status Register (WFIFOSTS) ............................................................................ 1101
22-80. Read FIFO Control Register (RFIFOCTL) ........................................................................... 1102
22-81. Read FIFO Status Register (RFIFOSTS) ............................................................................ 1103
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
.................................................................................................
Clock and Frame Generation ..........................................................................................
Transmit Data Clocking .................................................................................................
Receive Data Clocking .................................................................................................
Sample Rate Generator Block Diagram ..............................................................................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ...........................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ...........................
Digital Loopback Mode .................................................................................................
Programmable Frame Period and Width .............................................................................
Dual-Phase Frame Example ...........................................................................................
Single-Phase Frame of Four 8-Bit Elements ........................................................................
Single-Phase Frame of One 32-Bit Element.........................................................................
Data Delay ...............................................................................................................
2-Bit Data Delay Used to Discard Framing Bit ......................................................................
McBSP Standard Operation ...........................................................................................
Receive Operation ......................................................................................................
Transmit Operation ......................................................................................................
Maximum Frame Frequency for Transmit and Receive ............................................................
Unexpected Frame Synchronization With (R/X)FIG = 0 ...........................................................
Unexpected Frame Synchronization With (R/X)FIG = 1 ...........................................................
Maximum Frame Frequency Operation With 8-Bit Data ...........................................................
Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ................................................
Serial Port Receive Overrun ...........................................................................................
Serial Port Receive Overrun Avoided ................................................................................
Decision Tree Response to Receive Frame Synchronization Pulse .............................................
Unexpected Receive Frame Synchronization Pulse ................................................................
Transmit With Data Overwrite .........................................................................................
Transmit Empty ..........................................................................................................
Transmit Empty Avoided ...............................................................................................
Decision Tree Response to Transmit Frame Synchronization Pulse.............................................
Unexpected Transmit Frame Synchronization Pulse ...............................................................
McBSP Buffer FIFO (BFIFO) Block Diagram ........................................................................
Companding Flow .......................................................................................................
Companding Data Formats ............................................................................................
Transmit Data Companding Format in DXR .........................................................................
Companding of Internal Data ..........................................................................................
DX Timing for Multichannel Operation................................................................................
Alternating Between the Channels of Partition A and the Channels of Partition B .............................
Reassigning Channel Blocks Throughout a McBSP Data Transfer ..............................................
McBSP Data Transfer in the 8-Partition Mode ......................................................................
Activity on McBSP Pins for the Possible Values of XMCM ........................................................
Data Receive Register (DRR) .........................................................................................
Data Transmit Register (DXR) .........................................................................................
Serial Port Control Register (SPCR) ..................................................................................
McBSP Block Diagram
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
1106
1108
1109
1109
1110
1113
1113
1114
1116
1118
1119
1120
1120
1121
1122
1123
1123
1124
1125
1126
1126
1127
1128
1128
1129
1130
1130
1131
1131
1133
1133
1134
1136
1136
1136
1137
1139
1141
1141
1142
1145
1155
1155
1156
39
www.ti.com
23-45. Receive Control Register (RCR) ...................................................................................... 1158
23-46. Transmit Control Register (XCR) ...................................................................................... 1160
23-47. Sample Rate Generator Register (SRGR) ........................................................................... 1162
23-48. Multichannel Control Registers (MCR) ............................................................................... 1163
23-49. Enhanced Receive Channel Enable Register n (RCEREn) ....................................................... 1167
23-50. Enhanced Transmit Channel Enable Register n (XCEREn) ....................................................... 1169
23-51. Pin Control Register (PCR) ............................................................................................ 1171
23-52. BFIFO Revision Identification Register (BFIFOREV) ............................................................... 1173
23-53. Write FIFO Control Register (WFIFOCTL) ........................................................................... 1174
23-54. Write FIFO Status Register (WFIFOSTS) ............................................................................ 1175
23-55. Read FIFO Control Register (RFIFOCTL) ........................................................................... 1176
23-56. Read FIFO Status Register (RFIFOSTS) ............................................................................ 1177
24-1.
MMC/SD Card Controller Block Diagram ............................................................................ 1179
24-2.
MMC/SD Controller Interface Diagram ............................................................................... 1180
24-3.
MMC Configuration and SD Configuration Diagram ................................................................ 1181
24-4.
MMC/SD Controller Clocking Diagram ............................................................................... 1182
24-5.
MMC/SD Mode Write Sequence Timing Diagram .................................................................. 1183
24-6.
MMC/SD Mode Read Sequence Timing Diagram .................................................................. 1184
24-7.
FIFO Operation Diagram ............................................................................................... 1185
24-8.
Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA...................................... 1186
24-9.
FIFO Operation During Card Read Diagram ........................................................................ 1188
1190
24-11. MMC Card Identification Procedure
1197
24-12.
1198
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
40
........................................................................
..................................................................................
SD Card Identification Procedure .....................................................................................
MMC/SD Mode Single-Block Write Operation .......................................................................
MMC/SD Mode Single-Block Read Operation.......................................................................
MMC/SD Multiple-Block Write Operation ............................................................................
MMC/SD Mode Multiple-Block Read Operation .....................................................................
MMC Control Register (MMCCTL) ....................................................................................
MMC Memory Clock Control Register (MMCCLK)..................................................................
MMC Status Register 0 (MMCST0) ...................................................................................
MMC Status Register 1 (MMCST1) ...................................................................................
MMC Interrupt Mask Register (MMCIM) .............................................................................
MMC Response Time-Out Register (MMCTOR) ....................................................................
MMC Data Read Time-Out Register (MMCTOD) ...................................................................
MMC Block Length Register (MMCBLEN) ...........................................................................
MMC Number of Blocks Register (MMCNBLK) .....................................................................
MMC Number of Blocks Counter Register (MMCNBLC) ...........................................................
MMC Data Receive Register (MMCDRR)............................................................................
MMC Data Transmit Register (MMCDXR) ...........................................................................
MMC Command Register (MMCCMD) ...............................................................................
Command Format .......................................................................................................
MMC Argument Register (MMCARGHL) .............................................................................
MMC Response Register 0 and 1 (MMCRSP01) ...................................................................
MMC Response Register 2 and 3 (MMCRSP23) ...................................................................
MMC Response Register 4 and 5 (MMCRSP45) ...................................................................
MMC Response Register 6 and 7 (MMCRSP67) ...................................................................
MMC Data Response Register (MMCDRSP) .......................................................................
MMC Command Index Register (MMCCIDX) .......................................................................
24-10. FIFO Operation During Card Write Diagram
List of Figures
1200
1202
1204
1206
1209
1210
1211
1213
1214
1216
1217
1218
1219
1219
1220
1220
1221
1222
1223
1224
1224
1224
1224
1226
1226
SPRUH80C – April 2013 – Revised September 2016
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www.ti.com
24-38. SDIO Control Register (SDIOCTL).................................................................................... 1227
24-39. SDIO Status Register 0 (SDIOST0)
..................................................................................
1228
24-40. SDIO Interrupt Enable Register (SDIOIEN).......................................................................... 1229
24-41. SDIO Interrupt Status Register (SDIOIST) ........................................................................... 1229
24-42. MMC FIFO Control Register (MMCFIFOCTL) ....................................................................... 1230
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
......................................................................................
32-kHz Oscillator Counter Compensation............................................................................
Kick State Machine......................................................................................................
Second Register (SECOND) ...........................................................................................
Minute Register (MINUTE) .............................................................................................
Hour Register (HOUR)..................................................................................................
Days Register (DAY) ....................................................................................................
Month Register (MONTH) ..............................................................................................
Year Register (YEAR) ..................................................................................................
Day of the Week Register (DOTW) ...................................................................................
Alarm Second Register (ALARMSECOND) .........................................................................
Alarm Minute Register (ALARMMINUTE) ............................................................................
Alarm Hour Register (ALARMHOUR) ................................................................................
Alarm Day Register (ALARMDAY) ....................................................................................
Alarm Month Register (ALARMMONTH) .............................................................................
Alarm Year Register (ALARMYEAR) .................................................................................
Control Register (CTRL)................................................................................................
Status Register (STATUS) .............................................................................................
Interrupt Register (INTERRUPT) ......................................................................................
Compensation (LSB) Register (COMPLSB) .........................................................................
Compensation (MSB) Register (COMPMSB)........................................................................
Oscillator Register (OSC) ..............................................................................................
Scratch Registers (SCRATCHn) ......................................................................................
Kick Registers (KICKnR) ...............................................................................................
SPI Block Diagram ......................................................................................................
SPI 3-Pin Option.........................................................................................................
SPI 4-Pin Option with SPIx_SCS[n] ..................................................................................
SPI 4-Pin Option with SPIx_ENA .....................................................................................
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ...............................................................
Format for Transmitting 12-Bit Word..................................................................................
Format for 10-Bit Received Word .....................................................................................
Clock Mode with POLARITY = 0 and PHASE = 0 ..................................................................
Clock Mode with POLARITY = 0 and PHASE = 1 ..................................................................
Clock Mode with POLARITY = 1 and PHASE = 0 ..................................................................
Clock Mode with POLARITY = 1 and PHASE = 1 ..................................................................
Five Bits per Character (5-Pin Option) ...............................................................................
SPI 3-Pin Master Mode with WDELAY ...............................................................................
SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY .............................
SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY ....................................
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY .......................................
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY ....................................................
SPI Global Control Register 0 (SPIGCR0) ...........................................................................
SPI Global Control Register 1 (SPIGCR1) ...........................................................................
SPI Interrupt Register (SPIINT0) ......................................................................................
Real-Time Clock Block Diagram
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
1232
1236
1237
1240
1240
1241
1242
1242
1243
1243
1244
1244
1245
1246
1247
1247
1248
1249
1250
1251
1252
1253
1254
1254
1257
1263
1265
1267
1269
1270
1270
1271
1272
1272
1272
1273
1278
1279
1280
1282
1283
1284
1285
1287
41
www.ti.com
26-21. SPI Interrupt Level Register (SPILVL) ................................................................................ 1289
26-22. SPI Flag Register (SPIFLG) ........................................................................................... 1290
26-23. SPI Pin Control Register 0 (SPIPC0) ................................................................................. 1292
26-24. SPI Pin Control Register 1 (SPIPC1) ................................................................................. 1293
26-25. SPI Pin Control Register 2 (SPIPC2) ................................................................................. 1294
26-26. SPI Pin Control Register 3 (SPIPC3) ................................................................................. 1295
26-27. SPI Pin Control Register 4 (SPIPC4) ................................................................................. 1296
26-28. SPI Pin Control Register 5 (SPIPC5) ................................................................................. 1297
26-29. SPI Data Register 0 (SPIDAT0) ....................................................................................... 1298
26-30. SPI Data Register 1 (SPIDAT1) ....................................................................................... 1299
26-31. SPI Buffer Register (SPIBUF) ......................................................................................... 1300
26-32. SPI Emulation Register (SPIEMU) .................................................................................... 1302
26-33. SPI Delay Register (SPIDELAY) ...................................................................................... 1303
26-34. Example: tC2TDELAY = 8 SPI Module Clock Cycles .................................................................... 1304
26-35. Example: tT2CDELAY = 4 SPI Module Clock Cycles .................................................................... 1305
26-36. Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout ........................................................... 1305
26-37. Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout........................................................... 1305
26-38. SPI Default Chip Select Register (SPIDEF) ......................................................................... 1306
26-39. SPI Data Format Register (SPIFMTn) ................................................................................ 1307
26-40. SPI Interrupt Vector Register 1 (INTVEC1) .......................................................................... 1309
27-1.
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
27-28.
27-29.
42
...................................................................................................
Timer Clock Source Block Diagram...................................................................................
64-Bit Timer Mode Block Diagram ....................................................................................
Dual 32-Bit Timers Chained Mode Block Diagram .................................................................
Dual 32-Bit Timers Chained Mode Example .........................................................................
Dual 32-Bit Timers Unchained Mode Block Diagram ...............................................................
Dual 32-Bit Timers Unchained Mode Example ......................................................................
32-Bit Timer Counter Overflow Example .............................................................................
Watchdog Timer Mode Block Diagram ...............................................................................
Watchdog Timer Operation State Diagram ..........................................................................
Timer Operation in Pulse Mode (CPn = 0) ...........................................................................
Timer Operation in Clock Mode (CPn = 1) ...........................................................................
Revision ID Register (REVID) .........................................................................................
Emulation Management Register (EMUMGT) .......................................................................
GPIO Interrupt Control and Enable Register (GPINTGPEN) ......................................................
GPIO Data and Direction Register (GPDATGPDIR) ...............................................................
Timer Counter Register 12 (TIM12)...................................................................................
Timer Counter Register 34 (TIM34)...................................................................................
Timer Period Register 12 (PRD12) ...................................................................................
Timer Period Register 34 (PRD34) ...................................................................................
Timer Control Register (TCR) .........................................................................................
Timer Global Control Register (TGCR) ...............................................................................
Watchdog Timer Control Register (WDTCR) ........................................................................
Timer Reload Register 12 (REL12) ...................................................................................
Timer Reload Register 34 (REL34) ...................................................................................
Timer Capture Register 12 (CAP12) ..................................................................................
Timer Capture Register 34 (CAP34) ..................................................................................
Timer Interrupt Control and Status Register (INTCTLSTAT) ......................................................
Timer Compare Register (CMPn) .....................................................................................
Timer Block Diagram
List of Figures
1312
1313
1314
1317
1317
1319
1320
1323
1325
1325
1327
1327
1331
1331
1332
1333
1334
1334
1335
1335
1336
1338
1339
1340
1340
1341
1341
1342
1343
SPRUH80C – April 2013 – Revised September 2016
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www.ti.com
28-1.
UART Block Diagram ................................................................................................... 1346
28-2.
UART Clock Generation Diagram ..................................................................................... 1347
28-3.
Relationships Between Data Bit, BCLK, and UART Input Clock .................................................. 1348
28-4.
UART Protocol Formats ................................................................................................ 1350
28-5.
UART Interface Using Autoflow Diagram ............................................................................ 1353
28-6.
Autoflow Functional Timing Waveforms for UARTn_RTS
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
........................................................
Autoflow Functional Timing Waveforms for UARTn_CTS ........................................................
UART Interrupt Request Enable Paths ...............................................................................
Receiver Buffer Register (RBR) .......................................................................................
Transmitter Holding Register (THR) ..................................................................................
Interrupt Enable Register (IER)........................................................................................
Interrupt Identification Register (IIR) ..................................................................................
FIFO Control Register (FCR) ..........................................................................................
Line Control Register (LCR) ...........................................................................................
Modem Control Register (MCR) .......................................................................................
Line Status Register (LSR).............................................................................................
Modem Status Register (MSR) ........................................................................................
Scratch Pad Register (SCR) ...........................................................................................
Divisor LSB Latch (DLL) ................................................................................................
Divisor MSB Latch (DLH) ..............................................................................................
Revision Identification Register 1 (REVID1) .........................................................................
Revision Identification Register 2 (REVID2) .........................................................................
Power and Emulation Management Register (PWREMU_MGMT) ...............................................
Mode Definition Register (MDR) ......................................................................................
uPP Functional Block Diagram ........................................................................................
Data Flow for Single-Channel Receive Mode .......................................................................
Data Flow for Single-Channel Transmit Mode ......................................................................
Data Flow for Digital Loopback (DLB) Mode (Duplex Mode 0)....................................................
Data Flow for Single-Channel Transmit with Data Interleave .....................................................
Clock Generation for a Channel Configured in Transmit Mode ...................................................
Clock Generation for a Channel Configured in Receive Mode ....................................................
Structure of DMA Window and Lines in Memory....................................................................
Signal Timing for uPP Channel in Receive Mode with Single Data Rate ........................................
Signal Timing for uPP Channel in Transmit Mode with Single Data Rate .......................................
Signal Timing for uPP Channel in Receive Mode with Double Data Rate .......................................
Signal Timing for uPP Channel in Transmit Mode with Double Data Rate ......................................
1354
1354
1356
1359
1360
1361
1362
1364
1365
1367
1368
1371
1372
1373
1373
1374
1374
1375
1376
1379
1379
1379
1380
1380
1381
1381
1384
1387
1388
1388
1388
29-13. Signal Timing for uPP Channel in Receive Mode with Double Data Rate and Data Interleave Enabled
(via UPCTL.DDRDEMUX).............................................................................................. 1389
29-14. Signal Timing for uPP Channel in Transmit Mode with Double Data Rate and Data Interleave Enabled
(via UPCTL.DDRDEMUX).............................................................................................. 1389
29-15. Signal Timing for uPP Channel in Transmit Mode with Single Data Rate and Data Interleave Enabled
(via UPCTL.SDRTXIL) .................................................................................................. 1389
29-16. uPP Peripheral Identification Register (UPPID) ..................................................................... 1398
29-17. uPP Peripheral Control Register (UPPCR) .......................................................................... 1399
............................................................................
uPP Channel Control Register (UPCTL) .............................................................................
uPP Interface Configuration Register (UPICR) ......................................................................
uPP Interface Idle Value Register (UPIVR) ..........................................................................
uPP Threshold Configuration Register (UPTCR) ...................................................................
uPP Interrupt Raw Status Register (UPISR) ........................................................................
29-18. uPP Digital Loopback Register (UPDLB)
1400
29-19.
1401
29-20.
29-21.
29-22.
29-23.
SPRUH80C – April 2013 – Revised September 2016
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List of Figures
1403
1405
1406
1407
43
www.ti.com
29-24. uPP Interrupt Enabled Status Register (UPIER) .................................................................... 1409
29-25. uPP Interrupt Enable Set Register (UPIES) ......................................................................... 1411
29-26. uPP Interrupt Enable Clear Register (UPIEC) ....................................................................... 1413
29-27. uPP End of Interrupt Register (UPEOI) .............................................................................. 1415
29-28. uPP DMA Channel I Descriptor 0 Register (UPID0) ................................................................ 1415
29-29. uPP DMA Channel I Descriptor 1 Register (UPID1) ................................................................ 1416
29-30. uPP DMA Channel I Descriptor 2 Register (UPID2) ................................................................ 1416
1417
29-32. uPP DMA Channel I Status 1 Register (UPIS1)
1417
29-33.
29-34.
29-35.
29-36.
29-37.
29-38.
29-39.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
44
....................................................................
....................................................................
uPP DMA Channel I Status 2 Register (UPIS2) ....................................................................
uPP DMA Channel Q Descriptor 0 Register (UPQD0) .............................................................
uPP DMA Channel Q Descriptor 1 Register (UPQD1) .............................................................
uPP DMA Channel Q Descriptor 2 Register (UPID2) ..............................................................
uPP DMA Channel Q Status 0 Register (UPQS0) ..................................................................
uPP DMA Channel Q Status 1 Register (UPQS1) ..................................................................
uPP DMA Channel Q Status 2 Register (UPQS2) ..................................................................
Functional Block Diagram ..............................................................................................
USB Clocking Diagram .................................................................................................
Interrupt Service Routine Flow Chart .................................................................................
CPU Actions at Transfer Phases ......................................................................................
Sequence of Transfer ...................................................................................................
Service Endpoint 0 Flow Chart ........................................................................................
IDLE Mode Flow Chart .................................................................................................
TX Mode Flow Chart ....................................................................................................
RX Mode Flow Chart....................................................................................................
Setup Phase of a Control Transaction Flow Chart..................................................................
IN Data Phase Flow Chart .............................................................................................
OUT Data Phase Flow Chart ..........................................................................................
Completion of SETUP or OUT Data Phase Flow Chart ............................................................
Completion of IN Data Phase Flow Chart ............................................................................
USB Controller Block Diagram ........................................................................................
Host Packet Descriptor Layout ........................................................................................
Host Buffer Descriptor Layout .........................................................................................
Teardown Descriptor Layout ...........................................................................................
Relationship Between Memory Regions and Linking RAM ........................................................
High-Level Transmit and Receive Data Transfer Example ........................................................
Transmit Descriptors and Queue Status Configuration ............................................................
Transmit USB Data Flow Example (Initialization) ...................................................................
Transmit USB Data Flow Example (Completion) ...................................................................
Receive Descriptors and Queue Status Configuration .............................................................
Receive USB Data Flow Example (Initialization) ....................................................................
Receive USB Data Flow Example (Completion) ....................................................................
Revision Identification Register (REVID) .............................................................................
Control Register (CTRLR) ..............................................................................................
Status Register (STATR) ...............................................................................................
Emulation Register (EMUR) ...........................................................................................
Mode Register (MODE) ................................................................................................
Auto Request Register (AUTOREQ)..................................................................................
SRP Fix Time Register (SRPFIXTIME) ..............................................................................
29-31. uPP DMA Channel I Status 0 Register (UPIS0)
List of Figures
1418
1419
1419
1420
1421
1421
1422
1424
1425
1429
1434
1434
1436
1437
1438
1439
1449
1451
1453
1455
1457
1464
1467
1470
1472
1475
1481
1482
1483
1484
1485
1485
1486
1510
1510
1511
1511
1512
1514
1515
SPRUH80C – April 2013 – Revised September 2016
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30-34. Teardown Register (TEARDOWN).................................................................................... 1515
30-35. USB Interrupt Source Register (INTSRCR).......................................................................... 1516
30-36. USB Interrupt Source Set Register (INTSETR) ..................................................................... 1517
30-37. USB Interrupt Source Clear Register (INTCLRR) ................................................................... 1518
30-38. USB Interrupt Mask Register (INTMSKR)............................................................................ 1519
.................................................................
USB Interrupt Mask Clear Register (INTMSKCLRR) ...............................................................
USB Interrupt Source Masked Register (INTMASKEDR) ..........................................................
USB End of Interrupt Register (EOIR) ................................................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1)..............................................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2)..............................................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3)..............................................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4)..............................................................
Function Address Register (FADDR) .................................................................................
Power Management Register (POWER) .............................................................................
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ...........................................
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ........................................................
Interrupt Enable Register for INTRTX (INTRTXE) ..................................................................
Interrupt Enable Register for INTRRX (INTRRXE) .................................................................
Interrupt Register for Common USB Interrupts (INTRUSB) .......................................................
Interrupt Enable Register for INTRUSB (INTRUSBE) ..............................................................
Frame Number Register (FRAME) ....................................................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX) .............................
Register to Enable the USB 2.0 Test Modes (TESTMODE) ......................................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ......................................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ......................................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...........................................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .....................................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...........................................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP).......................................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ......................................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...........................................
Count 0 Register (COUNT0) ...........................................................................................
Receive Count Register (RXCOUNT) ................................................................................
Type Register (Host mode only) (HOST_TYPE0) ..................................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) .....................................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ......................................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ............................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .....................................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL).............................................
Configuration Data Register (CONFIGDATA) .......................................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .....................................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .....................................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .....................................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .....................................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .....................................................
Device Control Register (DEVCTL) ...................................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ) ..........................................................................
Receive Endpoint FIFO Size (RXFIFOSZ) ...........................................................................
30-39. USB Interrupt Mask Set Register (INTMSKSETR)
1520
30-40.
1521
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
30-47.
30-48.
30-49.
30-50.
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
30-61.
30-62.
30-63.
30-64.
30-65.
30-66.
30-67.
30-68.
30-69.
30-70.
30-71.
30-72.
30-73.
30-74.
30-75.
30-76.
30-77.
30-78.
30-79.
30-80.
30-81.
30-82.
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1522
1523
1523
1524
1524
1525
1525
1526
1527
1528
1529
1529
1530
1531
1531
1532
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1541
1542
1542
1543
1543
1544
1545
1546
1547
1547
1548
1548
1549
1549
1550
1550
45
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30-83. Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................. 1551
30-84. Receive Endpoint FIFO Address (RXFIFOADDR) .................................................................. 1551
30-85. Hardware Version Register (HWVERS) .............................................................................. 1552
30-86. Transmit Function Address (TXFUNCADDR) ....................................................................... 1553
30-87. Transmit Hub Address (TXHUBADDR)
..............................................................................
1553
30-88. Transmit Hub Port (TXHUBPORT).................................................................................... 1553
30-89. Receive Function Address (RXFUNCADDR) ........................................................................ 1554
30-90. Receive Hub Address (RXHUBADDR) ............................................................................... 1554
30-91. Receive Hub Port (RXHUBPORT) .................................................................................... 1554
30-92. CDMA Revision Identification Register (DMAREVID) .............................................................. 1555
...........................................
30-94. CDMA Emulation Control Register (DMAEMU) .....................................................................
30-95. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) ........................................
30-96. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) ........................................
30-97. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) ....................................
30-98. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) ....................................
30-99. CDMA Scheduler Control Register (DMA_SCHED_CTRL) .......................................................
30-100. CDMA Scheduler Table Word n Registers (WORD[n]) ...........................................................
30-101. Queue Manager Revision Identification Register (QMGRREVID) ...............................................
30-102. Queue Manager Queue Diversion Register (DIVERSION).......................................................
30-103. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) .............................
30-104. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) .............................
30-105. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) .............................
30-106. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) .............................
30-107. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) .............................
30-108. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .........................................
30-109. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) .............................
30-110. Queue Manager Queue Pending Register 0 (PEND0) ...........................................................
30-111. Queue Manager Queue Pending Register 1 (PEND1) ...........................................................
30-112. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) ............................
30-113. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) ....................................
30-114. Queue Manager Queue N Control Register D (CTRLD[N]) ......................................................
30-115. Queue Manager Queue N Status Register A (QSTATA[N]) .....................................................
30-116. Queue Manager Queue N Status Register B (QSTATB[N]) .....................................................
30-117. Queue Manager Queue N Status Register C (QSTATC[N]) .....................................................
31-1. Input and Output Channels of VPIF ..................................................................................
31-2. Video Port Interface (VPIF) Block Diagram ..........................................................................
31-3. VPIF Architecture Block Diagram .....................................................................................
31-4. Interlaced Video .........................................................................................................
31-5. Progressive Video .......................................................................................................
31-6. Memory Storage Modes for Interlaced Video........................................................................
31-7. Functional Image of Raw Data Capturing Mode ....................................................................
31-8. Raw Capture Progressive Mode ......................................................................................
31-9. Raw Capture Interlaced Mode .........................................................................................
31-10. Stuffing Manner in Storage Memory ..................................................................................
31-11. VBI Result Data Transmit Image for Interlaced Image .............................................................
31-12. Module Performance with Emulation Suspend Signal .............................................................
31-13. Emulation Suspend Function on Channels 2 and 3 (Transmit) ...................................................
31-14. Method for Turning off Module Channel..............................................................................
30-93. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)
46
List of Figures
1555
1556
1556
1557
1558
1559
1560
1560
1562
1562
1563
1564
1565
1566
1566
1567
1567
1568
1568
1569
1570
1571
1572
1572
1573
1575
1576
1577
1580
1581
1582
1585
1586
1587
1587
1588
1593
1594
1595
SPRUH80C – April 2013 – Revised September 2016
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31-15. Clock Control on Video Input and Output with SDTV Encoding .................................................. 1596
31-16. Clock Control on Video Input and Output with HDTV Encoding .................................................. 1598
31-17. Clock Control on Video Input and Output with HDTV Encoding .................................................. 1599
..................................................................................
Channel 0 Control Register (C0CTRL) ...............................................................................
Channel 1 Control Register (C1CTRL) ...............................................................................
Channel 2 Control Register (C2CTRL) ...............................................................................
Channel 3 Control Register (C3CTRL) ...............................................................................
Interrupt Enable Register (INTEN) ....................................................................................
Interrupt Enable Set Register (INTSET) ..............................................................................
Interrupt Enable Clear Register (INTCLR) ...........................................................................
Interrupt Status Register (INTSTAT)..................................................................................
Interrupt Status Clear Register (INTSTATCLR) .....................................................................
Emulation Suspend Control Register (EMUCTRL) .................................................................
DMA Size Control Register (REQSIZE) ..............................................................................
Channel n Top Field Luminance Address Register (CnTLUMA)..................................................
Channel n Bottom Field Luminance Address Register (CnBLUMA) .............................................
Channel n Top Field Chrominance Address Register (CnTCHROMA) ..........................................
Channel n Bottom Field Chrominance Address Register (CnBCHROMA) ......................................
Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) .......................................
Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) ...................................
Channel n Top Field Vertical Ancillary Address Register (CnTVANC) ...........................................
Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register (CnBVANC) ..................
Channel n Image Address Offset Register (CnIMGOFFSET) .....................................................
Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET)...................................
Channel n Horizontal Size Configuration Register (CnHCFG) ....................................................
Channel n Vertical Size Configuration 0 Register (CnVCFG0) ...................................................
Channel n Vertical Data Size Configuration 1 Register (CnVCFG1) .............................................
Channel n Vertical Size Configuration 2 Register (CnVCFG2) ...................................................
Channel n Vertical Image Size Register (CnVSIZE)................................................................
Channel n Horizontal Size Configuration Register (CnHCFG) ....................................................
Channel n Vertical Size Configuration 0 Register (CnVCFG0) ...................................................
Channel n Vertical Size Configuration 1 Register (CnVCFG1) ...................................................
Channel n Vertical Size Configuration 2 Register (CnVCFG2) ...................................................
Channel n Vertical Image Size Register (CnVSIZE)................................................................
Channel n Top Field Horizontal Ancillary Position Register (CnTHANCPOS) ..................................
Channel n Top Field Horizontal Ancillary Size Register (CnTHANCSIZE) ......................................
Channel n Bottom Field Horizontal Ancillary Position Register (CnBHANCPOS) ..............................
Channel n Bottom Field Horizontal Ancillary Size Register (CnBHANCSIZE) ..................................
Channel n Top Field Vertical Ancillary Position Register (CnTVANCPOS) .....................................
Channel n Top Field Vertical Ancillary Size Register (CnTVANCSIZE) .........................................
Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) .................................
Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) .....................................
31-18. VPIF Revision ID Register (REVID)
1603
31-19.
1603
31-20.
31-21.
31-22.
31-23.
31-24.
31-25.
31-26.
31-27.
31-28.
31-29.
31-30.
31-31.
31-32.
31-33.
31-34.
31-35.
31-36.
31-37.
31-38.
31-39.
31-40.
31-41.
31-42.
31-43.
31-44.
31-45.
31-46.
31-47.
31-48.
31-49.
31-50.
31-51.
31-52.
31-53.
31-54.
31-55.
31-56.
31-57.
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1605
1606
1608
1610
1611
1612
1613
1614
1615
1615
1616
1616
1617
1617
1618
1618
1619
1619
1620
1620
1621
1622
1622
1623
1623
1624
1625
1625
1626
1626
1627
1628
1629
1630
1631
1632
1633
1634
47
www.ti.com
List of Tables
2-1.
DSP Interrupt Map ......................................................................................................... 77
3-1.
TMS320C6746 DSP System Interconnect Matrix ...................................................................... 84
5-1.
MPU Memory Regions..................................................................................................... 90
5-2.
MPU2 Default Configuration .............................................................................................. 90
5-3.
Device Master Settings .................................................................................................... 90
5-4.
Request Type Access Controls........................................................................................... 92
5-5.
MPU_BOOTCFG_ERR Interrupt Sources .............................................................................. 94
5-6.
Memory Protection Unit 2 (MPU2) Registers ........................................................................... 95
5-7.
Revision ID Register (REVID) Field Descriptions ...................................................................... 96
5-8.
Configuration Register (CONFIG) Field Descriptions
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
48
................................................................. 97
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions................................................. 98
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions .............................................. 99
Interrupt Enable Set Register (IENSET) Field Descriptions ......................................................... 100
Interrupt Enable Clear Register (IENCLR) Field Descriptions ...................................................... 100
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions .................. 102
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................ 103
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions................. 104
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions ... 105
Fault Address Register (FLTADDRR) Field Descriptions ........................................................... 106
Fault Status Register (FLTSTAT) Field Descriptions ................................................................ 107
Fault Clear Register (FLTCLR) Field Descriptions ................................................................... 108
Device Clock Inputs ...................................................................................................... 110
System Clock Domains .................................................................................................. 110
Example PLL Frequencies .............................................................................................. 113
USB Clock Multiplexing Options ........................................................................................ 113
DDR2/mDDR Memory Controller MCLK Frequencies ............................................................... 115
EMIFA Frequencies ...................................................................................................... 116
EMAC Reference Clock Frequencies .................................................................................. 118
uPP Transmit Clock Selection .......................................................................................... 119
Peripherals ................................................................................................................. 121
System PLLC Output Clocks ............................................................................................ 125
PLL Controller 0 (PLLC0) Registers .................................................................................... 128
PLL Controller 1 (PLLC1) Registers .................................................................................... 129
PLLC0 Revision Identification Register (REVID) Field Descriptions ............................................... 129
PLLC1 Revision Identification Register (REVID) Field Descriptions ............................................... 130
Reset Type Status Register (RSTYPE) Field Descriptions ......................................................... 130
Reset Control Register (RSCTRL) Field Descriptions ............................................................... 131
PLLC0 Control Register (PLLCTL) Field Descriptions ............................................................... 132
PLLC1 Control Register (PLLCTL) Field Descriptions ............................................................... 133
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions ..................................................... 134
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions ..................................................... 135
PLL Multiplier Control Register (PLLM) Field Descriptions.......................................................... 136
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................................................ 136
PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................ 137
PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................ 137
PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................ 138
PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................ 138
List of Tables
SPRUH80C – April 2013 – Revised September 2016
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7-18.
PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................ 139
7-19.
PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................ 139
7-20.
PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions ............................................................ 140
7-21.
PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ............................................................ 140
7-22.
PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ............................................................ 141
7-23.
PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ............................................................ 141
7-24.
PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
7-25.
PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
9-1.
10-1.
................................................
................................................
PLL Post-Divider Control Register (POSTDIV) Field Descriptions .................................................
PLL Controller Command Register (PLLCMD) Field Descriptions .................................................
PLL Controller Status Register (PLLSTAT) Field Descriptions .....................................................
PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC0 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC0 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC1 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions ....................................
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions ....................................
PSC0 Default Module Configuration ...................................................................................
PSC1 Default Module Configuration ...................................................................................
Module States .............................................................................................................
IcePick Emulation Commands ..........................................................................................
PSC Interrupt Events .....................................................................................................
Power and Sleep Controller 0 (PSC0) Registers .....................................................................
Power and Sleep Controller 1 (PSC1) Registers .....................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions ........................................................
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions .........................................
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ............................................
Power Error Pending Register (PERRPR) Field Descriptions ......................................................
Power Error Clear Register (PERRCR) Field Descriptions .........................................................
Power Domain Transition Command Register (PTCMD) Field Descriptions .....................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions .........................................
Power Domain 0 Status Register (PDSTAT0) Field Descriptions ..................................................
Power Domain 1 Status Register (PDSTAT1) Field Descriptions ..................................................
Power Domain 0 Control Register (PDCTL0) Field Descriptions ...................................................
Power Domain 1 Control Register (PDCTL1) Field Descriptions ...................................................
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ...........................................
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ...........................................
Module Status n Register (MDSTATn) Field Descriptions ..........................................................
PSC0 Module Control n Register (MDCTLn) Field Descriptions ...................................................
PSC1 Module Control n Register (MDCTLn) Field Descriptions ...................................................
Power Management Features ...........................................................................................
Master IDs .................................................................................................................
SPRUH80C – April 2013 – Revised September 2016
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List of Tables
142
142
143
143
144
145
146
147
148
149
149
150
151
152
153
154
154
157
157
160
162
162
165
165
166
166
167
168
169
169
170
171
172
173
174
175
176
177
178
179
180
183
196
49
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10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
50
...................................................................................................
System Configuration Module 0 (SYSCFG0) Registers .............................................................
System Configuration Module 1 (SYSCFG1) Registers .............................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Device Identification Register 0 (DEVIDR0) Field Descriptions ....................................................
Boot Configuration Register (BOOTCFG) Field Descriptions .......................................................
Chip Revision Identification Register (CHIPREVIDR) Field Descriptions .........................................
Kick 0 Register (KICK0R) Field Descriptions .........................................................................
Kick 1 Register (KICK1R) Field Descriptions .........................................................................
Host 1 Configuration Register (HOST1CFG) Field Descriptions ...................................................
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ...............................................
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................
Interrupt Enable Register (IENSET) Field Descriptions..............................................................
Interrupt Enable Clear Register (IENCLR) Field Descriptions ......................................................
End of Interrupt Register (EOI) Field Descriptions ...................................................................
Fault Address Register (FLTADDRR) Field Descriptions ...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Master Priority 0 Register (MSTPRI0) Field Descriptions ...........................................................
Master Priority 1 Register (MSTPRI1) Field Descriptions ...........................................................
Master Priority 2 Register (MSTPRI2) Field Descriptions ...........................................................
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ................................................
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ................................................
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ................................................
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ................................................
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ................................................
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ................................................
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ................................................
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ................................................
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ................................................
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ................................................
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions .............................................
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions .............................................
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions .............................................
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions .............................................
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions .............................................
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions .............................................
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions .............................................
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions .............................................
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions .............................................
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions .............................................
Suspend Source Register (SUSPSRC) Field Descriptions .........................................................
Chip Signal Register (CHIPSIG) Field Descriptions..................................................................
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ...................................................
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ....................................................
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ....................................................
Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ....................................................
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ....................................................
Chip Configuration 4 Register (CFGCHIP4) Field Descriptions ....................................................
VTP I/O Control Register (VTPIO_CTL) Field Descriptions .........................................................
Default Master Priority
List of Tables
197
198
199
200
200
201
201
202
202
203
204
205
206
206
207
207
208
209
210
211
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
245
247
249
251
253
256
257
258
260
262
264
265
266
SPRUH80C – April 2013 – Revised September 2016
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10-51. DDR Slew Register (DDR_SLEW) Field Descriptions ............................................................... 268
10-52. Deep Sleep Register (DEEPSLEEP) Field Descriptions ............................................................ 269
10-53. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions................................................ 270
10-54. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions ................................................. 270
10-55. Pullup/Pulldown Select Register (PUPD_SEL) Default Values ..................................................... 271
10-56. RXACTIVE Control Register (RXACTIVE) Field Descriptions ...................................................... 272
12-1.
Constants Table........................................................................................................... 279
12-2.
Abbreviations for Instruction Descriptions ............................................................................. 281
12-3.
Load/Store Instructions
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
12-42.
12-43.
..................................................................................................
Arithmetic Instructions ....................................................................................................
Logical Instructions .......................................................................................................
Program Flow Control Instructions .....................................................................................
Format 1a: (All Arithmetic and Logical Functions – Register Op2).................................................
Format 1b: (All Arithmetic and Logical Functions – Immediate Op2) ..............................................
Format 2 ...................................................................................................................
Format 2a: (JMP,JAL – Register Op2) .................................................................................
Format 2b: (JMP, JAL – Immediate Op2) .............................................................................
Format 2c: (LDI)...........................................................................................................
Format 2d: (LMBD - Leftmost Bit Detect - Register Op2) ...........................................................
Format 2e: (LMBD - Immediate Op2) ..................................................................................
Format 2f: (SCAN - Register Op2) .....................................................................................
Format 2g: (SCAN - Immediate Op2) ..................................................................................
Format 2h: (HALT) ........................................................................................................
Format 2i: (SLP) ..........................................................................................................
Format 4a: (Quick Arithmetic Test and Branch – Register Op2) ...................................................
Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2).................................................
Format 5a: (Quick Bit Test and Branch – Register Op2) ............................................................
Format 5b: (Quick Bit Test and Branch – Immediate Op2) .........................................................
Format 6a: (LBBO/SBBO - Register Offset)...........................................................................
Format 6b: (LBBO/SBBO - Immediate Offset) ........................................................................
Format 6c: (LBCO/SBCO - Register Offset) ..........................................................................
Format 6d: (LBCO/SBCO - Immediate Offset) ........................................................................
PRUSS System Events [0:31] Assignments ..........................................................................
ARM Interrupt Controller Mapping ......................................................................................
DSP Interrupt Controller Mapping ......................................................................................
Local Instruction Space Memory Map .................................................................................
Local Data Space Memory Map ........................................................................................
Subsystem Global Memory Map ........................................................................................
PRU Control/Status Register Memory Map ..........................................................................
CONTROL Register Field Descriptions ................................................................................
STATUS Register Field Descriptions ..................................................................................
WAKEUP Register Field Descriptions .................................................................................
CYCLECNT Register Field Descriptions...............................................................................
STALLCNT Register Field Descriptions ...............................................................................
CONTABBLKIDX0 Register Field Descriptions .......................................................................
CONTABPROPTR0 Register Field Descriptions .....................................................................
CONTABPROPTR1 Register Field Descriptions .....................................................................
INTGPR0 to INTGPR31 Register Field Descriptions ................................................................
INTCTER0 to INTCTER31 Register Field Descriptions .............................................................
SPRUH80C – April 2013 – Revised September 2016
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List of Tables
281
281
282
283
284
286
287
288
289
290
291
292
293
294
294
294
295
296
297
298
299
300
301
302
304
305
305
310
310
310
311
311
313
313
314
314
315
315
315
316
316
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12-44. Instruction RAM Memory Region ....................................................................................... 317
12-45. PRUSS Interrupt Controller (INTC) Registers......................................................................... 317
12-46. REVID Register ........................................................................................................... 318
12-47. REVID Register Field Descriptions ..................................................................................... 318
12-48. CONTROL Register ...................................................................................................... 318
12-49. CONTROL Register Field Descriptions ................................................................................ 318
12-50. GLBLEN Register ......................................................................................................... 318
319
12-52. GLBLNSTLVL Register
319
12-53.
319
12-54.
12-55.
12-56.
12-57.
12-58.
12-59.
12-60.
12-61.
12-62.
12-63.
12-64.
12-65.
12-66.
12-67.
12-68.
12-69.
12-70.
12-71.
12-72.
12-73.
12-74.
12-75.
12-76.
12-77.
12-78.
12-79.
12-80.
12-81.
12-82.
12-83.
12-84.
12-85.
12-86.
12-87.
12-88.
12-89.
12-90.
12-91.
12-92.
52
..................................................................................
..................................................................................................
GLBLNSTLVL Register Field Descriptions ............................................................................
STATIDXSET Register ...................................................................................................
STATIDXSET Register Field Descriptions ............................................................................
STATIDXCLR Register ...................................................................................................
STATIDXCLR Register Field Descriptions ............................................................................
ENIDXSET Register ......................................................................................................
ENIDXSET Register Field Descriptions ................................................................................
ENIDXCLR Register ......................................................................................................
ENIDXCLR Register Field Descriptions ...............................................................................
HSTINTENIDXSET Register ............................................................................................
HSTINTENIDXSET Register Field Descriptions ......................................................................
HSTINTENIDXCLR Register ............................................................................................
HSTINTENIDXCLR Register Field Descriptions ......................................................................
GLBLPRIIDX Register....................................................................................................
GLBLPRIIDX Register Field Descriptions .............................................................................
STATESETINT0 Register ................................................................................................
STATESETINT0 Register Field Descriptions .........................................................................
STATESETINT1 Register ................................................................................................
STATESETINT1 Register Field Descriptions .........................................................................
STATCLRINT0 Register .................................................................................................
STATCLRINT0 Register Field Descriptions ...........................................................................
STATCLRINT1 Register .................................................................................................
STATCLRINT1 Register Field Descriptions ...........................................................................
ENABLESET0 Register ..................................................................................................
ENABLESET0 Register Field Descriptions ............................................................................
ENABLESET1 Register ..................................................................................................
ENABLESET1 Register Field Descriptions ............................................................................
ENABLECLR0 Register ..................................................................................................
ENABLECLR0 Register Field Descriptions............................................................................
ENABLECLR1 Register ..................................................................................................
ENABLECLR1 Register Field Descriptions............................................................................
CHANMAP0 to CHANMAP15 Register ................................................................................
CHANMAP0 to CHANMAP15 Register Field Descriptions ..........................................................
HOSTMAP0 to HOSTMAP2 Register ..................................................................................
HOSTMAP0 to HOSTMAP2 Register Field Descriptions............................................................
HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register ...................................................................
HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register Field Descriptions.............................................
POLARITY0 Register.....................................................................................................
POLARITY0 Register Field Descriptions ..............................................................................
POLARITY1 Register.....................................................................................................
12-51. GLBLEN Register Field Descriptions
List of Tables
319
319
320
320
320
320
320
320
321
321
321
321
321
321
322
322
322
322
322
322
323
323
323
323
323
323
324
324
324
324
324
324
325
325
325
325
325
326
326
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
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12-93. POLARITY1 Register Field Descriptions .............................................................................. 326
12-94. TYPE0 Register ........................................................................................................... 326
12-95. TYPE0 Register Field Descriptions..................................................................................... 326
12-96. TYPE1 Register ........................................................................................................... 326
12-97. TYPE1 Register Field Descriptions..................................................................................... 327
................................................................
12-99. HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register Field Descriptions ..........................................
12-100. HOSTINTEN Register ..................................................................................................
12-101. HOSTINTEN Register Field Descriptions ............................................................................
13-1. DDR2/mDDR SDRAM Commands .....................................................................................
13-2. Truth Table for DDR2/mDDR SDRAM Commands .................................................................
13-3. Addressable Memory Ranges ...........................................................................................
13-4. Configuration Register Fields for Address Mapping..................................................................
13-5. Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM .....................................
13-6. Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) ...................................................
13-7. DDR2/mDDR Memory Controller FIFO Description ..................................................................
13-8. Refresh Urgency Levels .................................................................................................
13-9. Configuration Bit Field for Partial Array Self-refresh .................................................................
13-10. Reset Sources.............................................................................................................
13-11. DDR2 SDRAM Configuration by MRS Command ....................................................................
13-12. DDR2 SDRAM Configuration by EMRS(1) Command ...............................................................
13-13. Mobile DDR SDRAM Configuration by MRS Command.............................................................
13-14. Mobile DDR SDRAM Configuration by EMRS(1) Command .......................................................
13-15. SDCR Configuration ......................................................................................................
13-16. DDR2 Memory Refresh Specification .................................................................................
13-17. SDRCR Configuration ....................................................................................................
13-18. SDTIMR1 Configuration..................................................................................................
13-19. SDTIMR2 Configuration..................................................................................................
13-20. DRPYC1R Configuration.................................................................................................
13-21. DDR2/mDDR Memory Controller Registers ...........................................................................
13-22. Revision ID Register (REVID) Field Descriptions ....................................................................
13-23. SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................
13-24. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................
13-25. SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
13-26. SDRAM Timing Register 1 (SDTIMR1) Field Descriptions ..........................................................
13-27. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ..........................................................
13-28. SDRAM Configuration Register 2 (SDCR2) Field Descriptions ....................................................
13-29. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ...............................................
13-30. Performance Counter 1 Register (PC1) Field Descriptions .........................................................
13-31. Performance Counter 2 Register (PC2) Field Descriptions .........................................................
13-32. Performance Counter Configuration Register (PCC) Field Descriptions ..........................................
13-33. Performance Counter Filter Configuration .............................................................................
13-34. Performance Counter Master Region Select Register (PCMRS) Field Descriptions ............................
13-35. Performance Counter Time Register (PCT) Field Description ......................................................
13-36. DDR PHY Reset Control Register (DRPYRCR) ......................................................................
13-37. Interrupt Raw Register (IRR) Field Descriptions ......................................................................
13-38. Interrupt Masked Register (IMR) Field Descriptions .................................................................
13-39. Interrupt Mask Set Register (IMSR) Field Descriptions ..............................................................
13-40. Interrupt Mask Clear Register (IMCR) Field Descriptions ...........................................................
12-98. HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
327
327
327
327
333
334
341
342
343
345
347
350
351
352
354
354
354
355
360
361
361
362
362
363
364
364
365
366
369
370
371
372
373
374
374
375
376
377
378
378
379
379
380
381
53
www.ti.com
13-41. DDR PHY Control Register 1 (DRPYC1R) Field Descriptions ...................................................... 382
14-1.
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger........................................... 396
14-2.
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
14-3.
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ............................................... 400
14-4.
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers ............................... 402
14-5.
ECAP Initialization for APWM Mode ................................................................................... 404
14-6.
ECAP1 Initialization for Multichannel PWM Generation with Synchronization
406
14-7.
ECAP2 Initialization for Multichannel PWM Generation with Synchronization
406
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
54
............................
...................................
...................................
ECAP3 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP4 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP1 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP2 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP3 Initialization for Multichannel PWM Generation with Phase Control .....................................
Control and Status Register Set ........................................................................................
Time-Stamp Counter Register (TSCTR) Field Descriptions ........................................................
Counter Phase Control Register (CTRPHS) Field Descriptions ....................................................
Capture 1 Register (CAP1) Field Descriptions........................................................................
Capture 2 Register (CAP2) Field Descriptions........................................................................
Capture 3 Register (CAP3) Field Descriptions........................................................................
Capture 4 Register (CAP4) Field Descriptions........................................................................
ECAP Control Register 1 (ECCTL1) Field Descriptions .............................................................
ECAP Control Register 2 (ECCTL2) Field Descriptions .............................................................
ECAP Interrupt Enable Register (ECEINT) Field Descriptions .....................................................
ECAP Interrupt Flag Register (ECFLG) Field Descriptions .........................................................
ECAP Interrupt Clear Register (ECCLR) Field Descriptions .......................................................
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions .....................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
ePWM Module Control and Status Registers Grouped by Submodule ............................................
Submodule Configuration Parameters .................................................................................
Time-Base Submodule Registers.......................................................................................
Key Time-Base Signals ..................................................................................................
Counter-Compare Submodule Registers .............................................................................
Counter-Compare Submodule Key Signals ...........................................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Submodule Possible Input Events ..................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode ...........................................................
Action-Qualifier Event Priority for Up-Count Mode ...................................................................
Action-Qualifier Event Priority for Down-Count Mode ................................................................
Behavior if CMPA/CMPB is Greater than the Period ................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
List of Tables
398
406
406
409
409
409
410
410
411
411
412
412
413
413
415
417
418
419
420
421
427
428
433
434
442
442
446
447
449
449
449
450
453
453
455
455
457
457
459
459
461
461
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
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.................................................................................................
EPWMx Run Time Changes for ........................................................................................
Dead-Band Generator Submodule Registers .........................................................................
Classical Dead-Band Operating Modes ...............................................................................
PWM-Chopper Submodule Registers ..................................................................................
Trip-Zone Submodule Registers ........................................................................................
Possible Actions On a Trip Event.......................................................................................
Event-Trigger Submodule Registers ..................................................................................
Resolution for PWM and HRPWM......................................................................................
HRPWM Submodule Registers .........................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution .............................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ........................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
Submodule Registers ....................................................................................................
Time-Base Submodule Registers.......................................................................................
Time-Base Control Register (TBCTL) Field Descriptions ...........................................................
Time-Base Status Register (TBSTS) Field Descriptions ............................................................
Time-Base Phase Register (TBPHS) Field Descriptions ............................................................
Time-Base Counter Register (TBCNT) Field Descriptions ..........................................................
Time-Base Period Register (TBPRD) Field Descriptions ............................................................
Counter-Compare Submodule Registers ..............................................................................
Counter-Compare Control Register (CMPCTL) Field Descriptions ................................................
Counter-Compare A Register (CMPA) Field Descriptions...........................................................
Counter-Compare B Register (CMPB) Field Descriptions...........................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .......................................
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .......................................
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions ..........................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions .........................
Dead-Band Generator Submodule Registers .........................................................................
Dead-Band Generator Control Register (DBCTL) Field Descriptions..............................................
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions ...............................
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ...............................
PWM-Chopper Control Register (PCCTL) Bit Descriptions .........................................................
Trip-Zone Submodule Registers ........................................................................................
15-23. EPWMx Initialization for
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
SPRUH80C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
463
463
464
466
468
473
474
476
481
482
483
484
491
491
491
494
494
497
497
500
500
501
506
506
507
510
510
511
511
512
513
514
514
515
515
516
517
518
518
519
520
521
522
522
523
524
524
525
526
55
www.ti.com
526
15-73.
527
15-74.
15-75.
15-76.
15-77.
15-78.
15-79.
15-80.
15-81.
15-82.
15-83.
15-84.
15-85.
15-86.
15-87.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
56
...............................................
Trip-Zone Control Register (TZCTL) Field Descriptions .............................................................
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions .................................................
Trip-Zone Flag Register (TZFLG) Field Descriptions ................................................................
Trip-Zone Clear Register (TZCLR) Field Descriptions ..............................................................
Trip-Zone Force Register (TZFRC) Field Descriptions ..............................................................
Event-Trigger Submodule Registers ...................................................................................
Event-Trigger Selection Register (ETSEL) Field Descriptions .....................................................
Event-Trigger Prescale Register (ETPS) Field Descriptions .......................................................
Event-Trigger Flag Register (ETFLG) Field Descriptions ...........................................................
Event-Trigger Clear Register (ETCLR) Field Descriptions ..........................................................
Event-Trigger Force Register (ETFRC) Field Descriptions .........................................................
High-Resolution PWM Submodule Registers .........................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions ....................................
Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions ...................................
HRPWM Configuration Register (HRCNFG) Field Descriptions ....................................................
EDMA3 Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ....................................................................................
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .....................................
Expected Number of Transfers for Non-Null Transfer ...............................................................
EDMA3 DMA Channel to PaRAM Mapping ...........................................................................
Shadow Region Registers ...............................................................................................
Chain Event Triggers .....................................................................................................
EDMA3 Transfer Completion Interrupts ...............................................................................
EDMA3 Error Interrupts ..................................................................................................
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping .................................................
Number of Interrupts .....................................................................................................
EDMA3 Transfer Controller Configurations ...........................................................................
Read/Write Command Optimization Rules ............................................................................
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries.....................................
Channel Options Parameters (OPT) Field Descriptions .............................................................
Channel Source Address Parameter (SRC) Field Descriptions ....................................................
A Count/B Count Parameter (A_B_CNT) Field Descriptions .......................................................
Channel Destination Address Parameter (DST) Field Descriptions ...............................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .........................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ........................
C Count Parameter (CCNT) Field Descriptions.......................................................................
EDMA3 Channel Controller (EDMA3CC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3CC Configuration Register (CCCFG) Field Descriptions ...................................................
QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions .............................................
DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ....................................
Bits in DMAQNUMn ......................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ....................................
Event Missed Register (EMR) Field Descriptions ....................................................................
Event Missed Clear Register (EMCR) Field Descriptions ...........................................................
QDMA Event Missed Register (QEMR) Field Descriptions .........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................
15-72. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
List of Tables
527
528
529
529
530
530
531
532
532
533
533
534
534
535
549
552
553
561
563
565
568
568
568
569
570
577
583
602
603
605
605
606
606
607
608
608
609
612
613
614
615
615
616
617
618
619
620
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
16-34. EDMA3CC Error Register (CCERR) Field Descriptions ............................................................. 621
16-35. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................ 622
16-36. Error Evaluate Register (EEVAL) Field Descriptions................................................................. 623
16-37. DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions .............................. 624
16-38. QDMA Region Access Enable for Region m (QRAEm) Field Descriptions ....................................... 625
16-39. Event Queue Entry Registers (QxEy) Field Descriptions ............................................................ 626
16-40. Queue n Status Register (QSTATn) Field Descriptions ............................................................. 627
16-41. Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................... 628
16-42. EDMA3CC Status Register (CCSTAT) Field Descriptions .......................................................... 629
16-43. Event Register (ER) Field Descriptions ................................................................................ 631
16-44. Event Clear Register (ECR) Field Descriptions ....................................................................... 632
16-45. Event Set Register (ESR) Field Descriptions ......................................................................... 633
16-46. Chained Event Register (CER) Field Descriptions ................................................................... 634
16-47. Event Enable Register (EER) Field Descriptions ..................................................................... 635
16-48. Event Enable Clear Register (EECR) Field Descriptions ............................................................ 636
.............................................................
Secondary Event Register (SER) Field Descriptions ................................................................
Secondary Event Clear Register (SECR) Field Descriptions .......................................................
Interrupt Enable Register (IER) Field Descriptions ...................................................................
Interrupt Enable Clear Register (IECR) Field Descriptions..........................................................
Interrupt Enable Set Register (IESR) Field Descriptions ............................................................
Interrupt Pending Register (IPR) Field Descriptions .................................................................
Interrupt Clear Register (ICR) Field Descriptions.....................................................................
Interrupt Evaluate Register (IEVAL) Field Descriptions .............................................................
QDMA Event Register (QER) Field Descriptions .....................................................................
QDMA Event Enable Register (QEER) Field Descriptions ..........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions .................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ...................................................
QDMA Secondary Event Register (QSER) Field Descriptions .....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................
EDMA3 Transfer Controller (EDMA3TC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................
Error Status Register (ERRSTAT) Field Descriptions ...............................................................
Error Enable Register (ERREN) Field Descriptions ..................................................................
Error Clear Register (ERRCLR) Field Descriptions ..................................................................
Error Details Register (ERRDET) Field Descriptions ................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions.................................................
Read Command Rate Register (RDRATE) Field Descriptions .....................................................
Source Active Options Register (SAOPT) Field Descriptions.......................................................
Source Active Source Address Register (SASRC) Field Descriptions ............................................
Source Active Count Register (SACNT) Field Descriptions .........................................................
Source Active Destination Address Register (SADST) Field Descriptions ........................................
Source Active B-Index Register (SABIDX) Field Descriptions ......................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................
Source Active Count Reload Register (SACNTRLD) Field Descriptions ..........................................
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions .....................
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions .................
16-49. Event Enable Set Register (EESR) Field Descriptions
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
16-70.
16-71.
16-72.
16-73.
16-74.
16-75.
16-76.
16-77.
16-78.
16-79.
16-80.
16-81.
16-82.
SPRUH80C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
636
637
637
638
639
639
640
641
642
643
644
645
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
659
660
660
661
662
662
663
57
www.ti.com
16-83. Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions ................................. 663
16-84. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions ............. 664
16-85. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions ........ 664
16-86. Destination FIFO Options Register n (DFOPTn) Field Descriptions ............................................... 665
16-87. Destination FIFO Source Address Register n (DFSRCn) Field Descriptions ..................................... 666
16-88. Destination FIFO Count Register n (DFCNTn) Field Descriptions ................................................. 666
16-89. Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions ................................ 667
16-90. Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions .............................................. 667
16-91. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions .................... 668
16-92. Debug List ................................................................................................................. 669
17-1.
EMAC and MDIO Signals for MII Interface ............................................................................ 678
17-2.
EMAC and MDIO Signals for RMII Interface .......................................................................... 679
17-3.
Ethernet Frame Description ............................................................................................. 680
17-4.
Basic Descriptor Description ............................................................................................ 682
17-5.
Receive Frame Treatment Summary
17-6.
Middle of Frame Overrun Treatment ................................................................................... 708
17-7.
Emulation Control ......................................................................................................... 718
17-8.
EMAC Control Module Registers ....................................................................................... 719
17-9.
EMAC Control Module Revision ID Register (REVID) Field Descriptions ......................................... 720
..................................................................................
17-10. EMAC Control Module Software Reset Register (SOFTRESET)
..................................................
707
721
17-11. EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................ 722
17-12. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 723
17-13. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 724
17-14. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 725
17-15. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 726
17-16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 727
17-17. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 728
17-18. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 729
.........
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .......
Management Data Input/Output (MDIO) Registers...................................................................
MDIO Revision ID Register (REVID) Field Descriptions.............................................................
MDIO Control Register (CONTROL) Field Descriptions .............................................................
PHY Acknowledge Status Register (ALIVE) Field Descriptions ....................................................
PHY Link Status Register (LINK) Field Descriptions .................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ..............
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions .......
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions .....
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ....
17-19. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
730
731
732
733
733
734
735
735
736
737
738
739
740
17-32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ............................................................................................................... 741
17-33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................. 742
17-34. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ........................................ 743
17-35. MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................. 744
17-36. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ........................................ 745
17-37. Ethernet Media Access Controller (EMAC) Registers ............................................................... 746
58
List of Tables
SPRUH80C – April 2013 – Revised September 2016
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17-38. Transmit Revision ID Register (TXREVID) Field Descriptions ...................................................... 749
17-39. Transmit Control Register (TXCONTROL) Field Descriptions ...................................................... 749
17-40. Transmit Teardown Register (TXTEARDOWN) Field Descriptions ................................................ 750
17-41. Receive Revision ID Register (RXREVID) Field Descriptions ...................................................... 751
17-42. Receive Control Register (RXCONTROL) Field Descriptions ...................................................... 751
................................................
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ........................
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions.......................
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ....................................
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ..............................
MAC Input Vector Register (MACINVECTOR) Field Descriptions .................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ..................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .........................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions .......................
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions .....................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ...............................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ..........................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions.........................
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ......................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................
17-43. Receive Teardown Register (RXTEARDOWN) Field Descriptions
752
17-44.
753
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
754
755
756
757
758
759
760
761
762
763
763
764
764
17-58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 765
17-59. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 768
17-60. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 769
............................................
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions........................................
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions .......
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ...............
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ......................
MAC Control Register (MACCONTROL) Field Descriptions ........................................................
MAC Status Register (MACSTATUS) Field Descriptions ...........................................................
Emulation Control Register (EMCONTROL) Field Descriptions ....................................................
FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................
MAC Configuration Register (MACCONFIG) Field Descriptions ...................................................
Soft Reset Register (SOFTRESET) Field Descriptions ..............................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions.............................
MAC Hash Address Register 1 (MACHASH1) Field Descriptions .................................................
MAC Hash Address Register 2 (MACHASH2) Field Descriptions .................................................
Back Off Test Register (BOFFTEST) Field Descriptions ............................................................
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions .....................................
Receive Pause Timer Register (RXPAUSE) Field Descriptions ....................................................
Transmit Pause Timer Register (TXPAUSE) Field Descriptions ...................................................
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ...........................................
MAC Address High Bytes Register (MACADDRHI) Field Descriptions............................................
MAC Index Register (MACINDEX) Field Descriptions ...............................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ....................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ....................
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions ..................................
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ...................................
17-61. Receive Maximum Length Register (RXMAXLEN) Field Descriptions
770
17-62.
770
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
SPRUH80C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
771
771
772
773
775
777
777
778
778
779
779
780
780
781
781
782
782
783
784
784
785
785
786
786
59
www.ti.com
18-1.
EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories........................................ 798
18-2.
EMIFA Pins Specific to SDRAM ........................................................................................ 799
18-3.
EMIFA Pins Specific to Asynchronous Memory ...................................................................... 799
18-4.
EMIFA SDRAM Commands ............................................................................................. 800
18-5.
Truth Table for SDRAM Commands ................................................................................... 800
18-6.
16-bit EMIFA Address Pin Connections ............................................................................... 802
18-7.
Description of the SDRAM Configuration Register (SDCR) ......................................................... 803
18-8.
Description of the SDRAM Refresh Control Register (SDRCR) .................................................... 803
18-9.
Description of the SDRAM Timing Register (SDTIMR) .............................................................. 804
18-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ...................................... 804
18-11. SDRAM LOAD MODE REGISTER Command ........................................................................ 805
806
18-13. Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM
811
18-14.
812
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
60
.................................................................................................
.................................................
Normal Mode vs. Select Strobe Mode .................................................................................
Description of the Asynchronous m Configuration Register (CEnCFG) ...........................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..................................
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ............................................
Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) ..........................................
Asynchronous Read Operation in Normal Mode .....................................................................
Asynchronous Write Operation in Normal Mode .....................................................................
Asynchronous Read Operation in Select Strobe Mode ..............................................................
Asynchronous Write Operation in Select Strobe Mode ..............................................................
Description of the NAND Flash Control Register (NANDFCR) .....................................................
Reset Sources.............................................................................................................
Interrupt Monitor and Control Bit Fields ................................................................................
SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface ................................................
SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface ..................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface ..........................................
EMIFA Input Timing Requirements .....................................................................................
ASRAM Output Timing Characteristics ................................................................................
ASRAM Input Timing Requirement for a Read .......................................................................
ASRAM Input Timing Requirements for a Write .....................................................................
ASRAM Timing Requirements With PCB Delays.....................................................................
EMIFA Timing Requirements for TC5516100FT-12 Example .....................................................
ASRAM Timing Requirements for TC5516100FT-12 Example .....................................................
Measured PCB Delays for TC5516100FT-12 Example .............................................................
Configuring CE3CFG for TC5516100FT-12 Example ...............................................................
Recommended Margins..................................................................................................
EMIFA Read Timing Requirements ....................................................................................
NAND Flash Read Timing Requirements .............................................................................
NAND Flash Write Timing Requirements .............................................................................
EMIFA Timing Requirements for HY27UA081G1M Example .......................................................
NAND Flash Timing Requirements for HY27UA081G1M Example ................................................
Configuring CE2CFG for HY27UA081G1M Example ................................................................
Configuring NANDFCR for HY27UA081G1M Example..............................................................
External Memory Interface (EMIFA) Registers .......................................................................
Module ID Register (MIDR) Field Descriptions .......................................................................
18-12. Refresh Urgency Levels
List of Tables
814
815
817
817
817
819
821
823
825
831
833
838
840
841
841
842
843
843
843
844
846
849
849
849
851
851
852
852
854
857
857
859
859
860
861
SPRUH80C – April 2013 – Revised September 2016
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www.ti.com
18-50. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ................................. 862
18-51. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................ 863
18-52. SDRAM Refresh Control Register (SDRCR) Field Descriptions
...................................................
865
18-53. Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... 866
18-54. SDRAM Timing Register (SDTIMR) Field Descriptions.............................................................. 868
18-55. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ...................................... 869
18-56. EMIFA Interrupt Raw Register (INTRAW) Field Descriptions....................................................... 870
18-57. EMIFA Interrupt Mask Register (INTMSK) Field Descriptions ...................................................... 871
18-58. EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ............................................ 872
18-59. EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions ......................................... 873
18-60. NAND Flash Control Register (NANDFCR) Field Descriptions ..................................................... 874
18-61. NAND Flash Status Register (NANDFSR) Field Descriptions ...................................................... 876
18-62. NAND Flash n ECC Register (NANDFnECC) Field Descriptions .................................................. 877
18-63. NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ............................ 878
18-64. NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions ........................................ 879
18-65. NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions ........................................ 879
18-66. NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions ........................................ 880
18-67. NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions ........................................ 880
18-68. NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ...................... 881
18-69. NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ...................... 881
18-70. NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions .......................... 882
18-71. NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions .......................... 882
19-1.
GPIO Register Bits and Banks Associated With GPIO Signals .................................................... 886
19-2.
GPIO Registers
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
...........................................................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ..........................................
GPIO Direction Register (DIRn) Field Descriptions ..................................................................
GPIO Output Data Register (OUT_DATAn) Field Descriptions ....................................................
GPIO Set Data Register (SET_DATAn) Field Descriptions .........................................................
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ......................................................
GPIO Input Data Register (IN_DATAn) Field Descriptions..........................................................
GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions ......................
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions .............................
GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions .....................
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions ............................
GPIO Interrupt Status Register (INTSTATn) Field Descriptions ....................................................
HPI Pins ....................................................................................................................
Value on Optional Pins when Configured as General-Purpose I/O ................................................
Options for Connecting Host and HPI Data Strobe Pins ............................................................
Access Types Selectable With the UHPI_HCNTL Signals ..........................................................
Cycle Types Selectable With the UHPI_HCNTL and UHPI_HR/W Signals.......................................
HPI Registers..............................................................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ..........................
GPIO Enable Register (GPIO_EN) Field Descriptions...............................................................
GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions ........................................................
GPIO Data 1 Register (GPIO_DAT1) Field Descriptions ............................................................
GPIO Direction 2 Register (GPIO_DIR2) Field Descriptions ........................................................
GPIO Data 2 Register (GPIO_DAT2) Field Descriptions ............................................................
SPRUH80C – April 2013 – Revised September 2016
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List of Tables
893
894
895
897
899
901
903
905
907
909
911
913
915
920
921
925
926
926
940
941
941
942
943
943
944
945
61
www.ti.com
20-14. Host Port Interface Control Register (HPIC) Field Descriptions .................................................... 947
20-15. Host Port Interface Write Address Register (HPIAW) Field Descriptions ......................................... 948
20-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions .......................................... 948
21-1.
Operating Modes of the I2C Peripheral ................................................................................ 958
21-2.
Ways to Generate a NACK Bit .......................................................................................... 959
21-3.
Descriptions of the I2C Interrupt Events ............................................................................... 963
21-4.
Inter-Integrated Circuit (I2C) Registers
21-5.
I2C Own Address Register (ICOAR) Field Descriptions ............................................................. 965
21-6.
I2C Interrupt Mask Register (ICIMR) Field Descriptions............................................................. 966
21-7.
I2C Interrupt Status Register (ICSTR) Field Descriptions ........................................................... 967
21-8.
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
62
................................................................................
964
............................................... 970
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions .............................................. 970
I2C Data Count Register (ICCNT) Field Descriptions................................................................ 971
I2C Data Receive Register (ICDRR) Field Descriptions ............................................................. 972
I2C Slave Address Register (ICSAR) Field Descriptions ............................................................ 973
I2C Data Transmit Register (ICDXR) Field Descriptions ............................................................ 974
I2C Mode Register (ICMDR) Field Descriptions ...................................................................... 975
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits .................................. 977
How the MST and FDF Bits Affect the Role of TRX Bit ............................................................. 977
I2C Interrupt Vector Register (ICIVR) Field Descriptions ............................................................ 979
I2C Extended Mode Register (ICEMDR) Field Descriptions ........................................................ 980
I2C Prescaler Register (ICPSC) Field Descriptions .................................................................. 981
I2C Revision Identification Register 1 (REVID1) Field Descriptions ............................................... 982
I2C Revision Identification Register 2 (REVID2) Field Descriptions ............................................... 982
I2C DMA Control Register (ICDMAC) Field Descriptions ........................................................... 983
I2C Pin Function Register (ICPFUNC) Field Descriptions .......................................................... 984
I2C Pin Direction Register (ICPDIR) Field Descriptions ............................................................. 985
I2C Pin Data In Register (ICPDIN) Field Descriptions ............................................................... 986
I2C Pin Data Out Register (ICPDOUT) Field Descriptions .......................................................... 987
I2C Pin Data Set Register (ICPDSET) Field Descriptions........................................................... 988
I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ........................................................ 989
Biphase-Mark Encoder ................................................................................................... 998
Preamble Codes .......................................................................................................... 999
Channel Status and User Data for Each DIT Block ................................................................ 1025
Transmit Bitstream Data Alignment ................................................................................... 1033
Receive Bitstream Data Alignment.................................................................................... 1035
EDMA Events - McASP ................................................................................................ 1045
McASP Registers Accessed by CPU/EDMA Through Peripheral Configuration Port .......................... 1046
McASP Registers Accessed by CPU/EDMA Through DMA Port ................................................. 1049
McASP AFIFO Registers Accessed Through Peripheral Configuration Port .................................... 1049
Revision Identification Register (REV) Field Descriptions ......................................................... 1050
Pin Function Register (PFUNC) Field Descriptions ................................................................. 1052
Pin Direction Register (PDIR) Field Descriptions ................................................................... 1054
Pin Data Output Register (PDOUT) Field Descriptions ............................................................ 1056
Pin Data Input Register (PDIN) Field Descriptions ................................................................. 1058
Pin Data Set Register (PDSET) Field Descriptions ................................................................. 1060
Pin Data Clear Register (PDCLR) Field Descriptions .............................................................. 1062
Global Control Register (GBLCTL) Field Descriptions ............................................................. 1063
Audio Mute Control Register (AMUTE) Field Descriptions ........................................................ 1065
List of Tables
SPRUH80C – April 2013 – Revised September 2016
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22-19. Digital Loopback Control Register (DLBCTL) Field Descriptions ................................................. 1067
22-20. Digital Mode Control Register (DITCTL) Field Descriptions ....................................................... 1068
22-21. Receiver Global Control Register (RGBLCTL) Field Descriptions ................................................ 1069
...........................................
Receive Bit Stream Format Register (RFMT) Field Descriptions .................................................
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions ..........................................
Receive Clock Control Register (ACLKRCTL) Field Descriptions ................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ..........................
Receive TDM Time Slot Register (RTDM) Field Descriptions.....................................................
Receiver Interrupt Control Register (RINTCTL) Field Descriptions ...............................................
Receiver Status Register (RSTAT) Field Descriptions .............................................................
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions ........................................
Receive Clock Check Control Register (RCLKCHK) Field Descriptions .........................................
Receiver DMA Event Control Register (REVTCTL) Field Descriptions ..........................................
Transmitter Global Control Register (XGBLCTL) Field Descriptions .............................................
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ...........................................
Transmit Bit Stream Format Register (XFMT) Field Descriptions ................................................
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions .........................................
Transmit Clock Control Register (ACLKXCTL) Field Descriptions................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions..........................
Transmit TDM Time Slot Register (XTDM) Field Descriptions ....................................................
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions ............................................
Transmitter Status Register (XSTAT) Field Descriptions ..........................................................
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions .........................................
Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ........................................
Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions .......................................
Serializer Control Registers (SRCTLn) Field Descriptions.........................................................
AFIFO Revision Identification Register (AFIFOREV) Field Descriptions ........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions .....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions ......................................................
McBSP Interface Signals ...............................................................................................
Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits ..............
Receive Clock Selection................................................................................................
Transmit Clock Selection ...............................................................................................
Receive Frame Synchronization Selection...........................................................................
Transmit Frame Synchronization Selection ..........................................................................
RCR/XCR Fields Controlling Elements per Frame and Bits per Element .......................................
Receive/Transmit Frame Length Configuration .....................................................................
Receive/Transmit Element Length Configuration ...................................................................
Effect of RJUST Bit Values With 12-Bit Example Data ABCh.....................................................
Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh .................................................
Justification of Expanded Data in DRR...............................................................................
Receive Channel Assignment and Control When Two Receive Partitions are Used ..........................
Transmit Channel Assignment and Control When Two Transmit Partitions are Used .........................
Receive Channel Assignment and Control When Eight Receive Partitions are Used .........................
Transmit Channel Assignment and Control When Eight Transmit Partitions are Used ........................
Selecting a Transmit Multichannel Selection Mode With the XMCM Bits........................................
22-22. Receive Format Unit Bit Mask Register (RMASK) Field Descriptions
1070
22-23.
1071
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
SPRUH80C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1099
1100
1101
1102
1103
1107
1111
1114
1115
1116
1117
1118
1118
1119
1121
1121
1137
1140
1140
1142
1142
1143
63
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23-18. Reset State of McBSP Pins ............................................................................................ 1146
1147
23-20. Transmitter Clock and Frame Configurations
1147
23-21.
1153
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
64
..........................................................................
.......................................................................
McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR ................................
McBSP Registers........................................................................................................
Data Receive Register (DRR) Field Descriptions ...................................................................
Data Transmit Register (DXR) Field Descriptions ..................................................................
Serial Port Control Register (SPCR) Field Descriptions ...........................................................
Receive Control Register (RCR) Field Descriptions ...............................................................
Transmit Control Register (XCR) Field Descriptions ..............................................................
Sample Rate Generator Register (SRGR) Field Descriptions .....................................................
Multichannel Control Register (MCR) Field Descriptions ..........................................................
Enhanced Receive Channel Enable Register n (RCEREn) Field Descriptions .................................
Use of the Receive Channel Enable Registers......................................................................
Enhanced Transmit Channel Enable Register n (XCEREn) Field Descriptions ................................
Use of the Transmit Channel Enable Registers .....................................................................
Pin Control Register (PCR) Field Descriptions ......................................................................
BFIFO Revision Identification Register (BFIFOREV) Field Descriptions ........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions .....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions ......................................................
MMC/SD Controller Pins Used in Each Mode .......................................................................
MMC/SD Mode Write Sequence ......................................................................................
MMC/SD Mode Read Sequence ......................................................................................
Description of MMC/SD Interrupt Requests .........................................................................
Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers...........................................
MMC Control Register (MMCCTL) Field Descriptions..............................................................
MMC Memory Clock Control Register (MMCCLK) Field Descriptions ...........................................
MMC Status Register 0 (MMCST0) Field Descriptions ............................................................
MMC Status Register 1 (MMCST1) Field Descriptions ............................................................
MMC Interrupt Mask Register (MMCIM) Field Descriptions .......................................................
MMC Response Time-Out Register (MMCTOR) Field Descriptions .............................................
MMC Data Read Time-Out Register (MMCTOD) Field Descriptions .............................................
MMC Block Length Register (MMCBLEN) Field Descriptions .....................................................
MMC Number of Blocks Register (MMCNBLK) Field Descriptions ...............................................
MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions ....................................
MMC Data Receive Register (MMCDRR) Field Descriptions .....................................................
MMC Data Transmit Register (MMCDXR) Field Descriptions .....................................................
MMC Command Register (MMCCMD) Field Descriptions .........................................................
Command Format .......................................................................................................
MMC Argument Register (MMCARGHL) Field Descriptions ......................................................
R1, R3, R4, R5, or R6 Response (48 Bits) ..........................................................................
R2 Response (136 Bits) ................................................................................................
MMC Data Response Register (MMCDRSP) Field Descriptions .................................................
MMC Command Index Register (MMCCIDX) Field Descriptions .................................................
SDIO Control Register (SDIOCTL) Field Descriptions .............................................................
SDIO Status Register 0 (SDIOST0) Field Descriptions ............................................................
SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions ...................................................
23-19. Receiver Clock and Frame Configurations
List of Tables
1154
1155
1155
1156
1158
1160
1162
1163
1167
1168
1169
1170
1171
1173
1174
1175
1176
1177
1182
1183
1184
1194
1208
1209
1210
1211
1213
1214
1216
1217
1218
1219
1219
1220
1220
1221
1222
1223
1225
1225
1226
1226
1227
1228
1229
SPRUH80C – April 2013 – Revised September 2016
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www.ti.com
24-28. SDIO Interrupt Status Register (SDIOIST) Field Descriptions .................................................... 1229
24-29. MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions
................................................
1230
25-1.
Real-Time Clock Signals ............................................................................................... 1233
25-2.
Real-Time Clock (RTC) Registers
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
....................................................................................
Second Register (SECOND) Field Descriptions ....................................................................
Minute Register (MINUTE) Field Descriptions.......................................................................
Hour Register (HOUR) Field Descriptions ...........................................................................
Day Register (DAY) Field Descriptions ...............................................................................
Month Register (MONTH) Field Descriptions ........................................................................
Year Register (YEAR) Field Descriptions ............................................................................
Day of the Week Register (DOTW) Field Descriptions .............................................................
Alarm Second Register (ALARMSECOND) Field Descriptions ...................................................
Alarm Minute Register (ALARMMINUTE) Field Descriptions .....................................................
Alarm Hour Register (ALARMHOUR) Field Descriptions ..........................................................
Alarm Day Register (ALARMDAY) Field Descriptions..............................................................
Alarm Month Register (ALARMMONTH) Field Descriptions ......................................................
Alarm Years Register (ALARMYEARS) Field Descriptions ........................................................
Control Register (CTRL) Field Descriptions .........................................................................
Status Register (STATUS) Field Descriptions .......................................................................
Interrupt Register (INTERRUPT) Field Descriptions................................................................
Compensations Register (COMPLSB) Field Descriptions .........................................................
Compensations Register (COMPMSB) Field Descriptions ........................................................
Oscillator Register (OSC) Field Descriptions ........................................................................
Scratch Registers (SCRATCHn) Field Descriptions ................................................................
Kick Registers (KICKnR) Field Descriptions .........................................................................
SPI Pins ..................................................................................................................
SPI Registers ............................................................................................................
SPI Register Settings Defining Master Modes ......................................................................
Allowed SPI Register Settings in Master Modes ....................................................................
SPI Register Settings Defining Slave Modes ........................................................................
Allowed SPI Register Settings in Slave Modes .....................................................................
Clocking Modes..........................................................................................................
SPI Registers ............................................................................................................
SPI Global Control Register 0 (SPIGCR0) Field Descriptions ....................................................
SPI Global Control Register 1 (SPIGCR1) Field Descriptions ....................................................
SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................
SPI Interrupt Level Register (SPILVL) Field Descriptions .........................................................
SPI Flag Register (SPIFLG) Field Descriptions .....................................................................
SPI Pin Control Register 0 (SPIPC0) Field Descriptions...........................................................
SPI Pin Control Register 1 (SPIPC1) Field Descriptions...........................................................
SPI Pin Control Register 2 (SPIPC2) Field Descriptions...........................................................
SPI Pin Control Register 3 (SPIPC3) Field Descriptions...........................................................
SPI Pin Control Register 4 (SPIPC4) Field Descriptions...........................................................
SPI Pin Control Register 5 (SPIPC5) Field Descriptions...........................................................
SPI Data Register 0 (SPIDAT0) Field Descriptions.................................................................
SPI Data Register 1 (SPIDAT1) Field Descriptions.................................................................
SPI Buffer Register (SPIBUF) Field Descriptions ...................................................................
SPI Emulation Register (SPIEMU) Field Descriptions..............................................................
SPI Delay Register (SPIDELAY) Field Descriptions ................................................................
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1239
1240
1240
1241
1242
1242
1243
1243
1244
1244
1245
1246
1247
1247
1248
1249
1250
1251
1252
1253
1254
1254
1258
1259
1260
1260
1262
1262
1271
1284
1284
1285
1287
1289
1290
1292
1293
1294
1295
1296
1297
1298
1299
1300
1302
1303
65
www.ti.com
26-25. SPI Default Chip Select Register (SPIDEF) Field Descriptions ................................................... 1306
1307
26-27. SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions
1309
27-1.
1313
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
66
.........................................................
...................................................
Timer Clock Source Selection .........................................................................................
64-Bit Timer Configurations ............................................................................................
32-Bit Timer Chained Mode Configurations .........................................................................
32-Bit Timer Unchained Mode Configurations.......................................................................
Counter and Period Registers Used in GP Timer Modes ..........................................................
TSTAT Parameters in Pulse and Clock Modes .....................................................................
Timer Emulation Modes Selection ....................................................................................
Timer Registers ..........................................................................................................
Revision ID Register (REVID) Field Descriptions ...................................................................
Emulation Management Register (EMUMGT) Field Descriptions ................................................
GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions ...............................
GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions .........................................
Timer Counter Register 12 (TIM12) Field Descriptions ............................................................
Timer Counter Register 34 (TIM34) Field Descriptions ............................................................
Timer Period Register (PRD12) Field Descriptions .................................................................
Timer Period Register (PRD34) Field Descriptions .................................................................
Timer Control Register (TCR) Field Descriptions ...................................................................
Timer Global Control Register (TGCR) Field Descriptions ........................................................
Watchdog Timer Control Register (WDTCR) Field Descriptions ..................................................
Timer Reload Register 12 (REL12) Field Descriptions .............................................................
Timer Reload Register 34 (REL34) Field Descriptions .............................................................
Timer Capture Register 12 (CAP12) Field Descriptions ...........................................................
Timer Capture Register 34 (CAP34) Field Descriptions ...........................................................
Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ................................
Timer Compare Register (CMPn) Field Descriptions ...............................................................
Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode ........................
Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode ........................
UART Signal Descriptions .............................................................................................
Character Time for Word Lengths ....................................................................................
UART Interrupt Requests Descriptions ...............................................................................
UART Registers .........................................................................................................
Receiver Buffer Register (RBR) Field Descriptions .................................................................
Transmitter Holding Register (THR) Field Descriptions ............................................................
Interrupt Enable Register (IER) Field Descriptions .................................................................
Interrupt Identification Register (IIR) Field Descriptions............................................................
Interrupt Identification and Interrupt Clearing Information .........................................................
FIFO Control Register (FCR) Field Descriptions ....................................................................
Line Control Register (LCR) Field Descriptions .....................................................................
Relationship Between ST, EPS, and PEN Bits in LCR.............................................................
Number of STOP Bits Generated .....................................................................................
Modem Control Register (MCR) Field Descriptions ................................................................
Line Status Register (LSR) Field Descriptions ......................................................................
Modem Status Register (MSR) Field Descriptions..................................................................
Scratch Pad Register (MSR) Field Descriptions ....................................................................
Divisor LSB Latch (DLL) Field Descriptions .........................................................................
Divisor MSB Latch (DLH) Field Descriptions ........................................................................
26-26. SPI Data Format Register (SPIFMTn) Field Descriptions
List of Tables
1315
1318
1321
1323
1327
1329
1329
1331
1331
1332
1333
1334
1334
1335
1335
1336
1338
1339
1340
1340
1341
1341
1342
1343
1348
1348
1349
1352
1356
1358
1359
1360
1361
1362
1363
1364
1365
1366
1366
1367
1368
1371
1372
1373
1373
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
28-22. Revision Identification Register 1 (REVID1) Field Descriptions ................................................... 1374
28-23. Revision Identification Register 2 (REVID2) Field Descriptions ................................................... 1374
28-24. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ......................... 1375
28-25. Mode Definition Register (MDR) Field Descriptions ................................................................ 1376
29-1.
I/O Clock Speeds for Channel in Transmit Mode Given 150 MHz Transmit Clock ............................. 1382
29-2.
uPP Signal Descriptions ................................................................................................ 1382
29-3.
DATA and XDATA Pin Assignments to Channels A and B According to Operating Mode .................... 1383
29-4.
Interface and DMA Channel Mapping for Various Operating Modes ............................................. 1385
29-5.
Required Signals for Various Modes
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
29-26.
29-27.
29-28.
29-29.
29-30.
29-31.
29-32.
29-33.
29-34.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
.................................................................................
Data Packing Examples for 12-Bit Data Words .....................................................................
Basic Operating Mode Selection ......................................................................................
Sample uPP Parameters for Duplex Mode 0 .......................................................................
uPP Parameters Useful for System Tuning .........................................................................
uPP Registers ...........................................................................................................
uPP Peripheral Identification Register (UPPID) Field Descriptions ...............................................
uPP Peripheral Control Register (UPPCR) Field Descriptions ....................................................
uPP Digital Loopback Register (UPDLB) Field Descriptions ......................................................
uPP Channel Control Register (UPCTL) Field Descriptions .......................................................
uPP Interface Configuration Register (UPICR) Field Descriptions ...............................................
uPP Interface Idle Value Register (UPIVR) Field Descriptions ...................................................
uPP Threshold Configuration Register (UPTCR) Field Descriptions .............................................
uPP Interrupt Raw Status Register (UPISR) Field Descriptions ..................................................
uPP Interrupt Enabled Status Register (UPIER) Field Descriptions ..............................................
uPP Interrupt Enable Set Register (UPIES) Field Descriptions ...................................................
uPP Interrupt Enable Clear Register (UPIEC) Field Descriptions ................................................
uPP End of Interrupt Register (UPEOI) Field Descriptions ........................................................
uPP DMA Channel I Descriptor 0 Register (UPID0) Field Descriptions .........................................
uPP DMA Channel I Descriptor 1 Register (UPID1) Field Descriptions .........................................
uPP DMA Channel I Descriptor 2 Register (UPID2) Field Descriptions .........................................
uPP DMA Channel I Status 0 Register (UPIS0) Field Descriptions ..............................................
uPP DMA Channel I Status 1 Register (UPIS1) Field Descriptions ..............................................
uPP DMA Channel I Status 2 Register (UPIS2) Field Descriptions ..............................................
uPP DMA Channel Q Descriptor 0 Register (UPQD0) Field Descriptions .......................................
uPP DMA Channel Q Descriptor 1 Register (UPQD1) Field Descriptions .......................................
uPP DMA Channel Q Descriptor 2 Register (UPID2) Field Descriptions ........................................
uPP DMA Channel Q Status 0 Register (UPQS0) Field Descriptions ...........................................
uPP DMA Channel Q Status 1 Register (UPQS1) Field Descriptions ...........................................
uPP DMA Channel Q Status 2 Register (UPQS2) Field Descriptions ...........................................
USB Clock Multiplexing Options.......................................................................................
PHY PLL Clock Frequencies Supported .............................................................................
USB Terminal Functions ...............................................................................................
PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ..............................................
PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ...........................................
PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions .....................................
PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ..................................
Host Packet Descriptor Word 0 (HPD Word 0) ......................................................................
Host Packet Descriptor Word 1 (HPD Word 1) ......................................................................
Host Packet Descriptor Word 2 (HPD Word 2) ......................................................................
Host Packet Descriptor Word 3 (HPD Word 3) ......................................................................
SPRUH80C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1386
1390
1392
1393
1394
1398
1398
1399
1400
1401
1403
1405
1406
1407
1409
1411
1413
1415
1415
1416
1416
1417
1417
1418
1419
1419
1420
1421
1421
1422
1425
1426
1426
1441
1442
1444
1446
1467
1467
1468
1468
67
www.ti.com
30-12. Host Packet Descriptor Word 4 (HPD Word 4) ...................................................................... 1468
30-13. Host Packet Descriptor Word 5 (HPD Word 5) ...................................................................... 1468
30-14. Host Packet Descriptor Word 6 (HPD Word 6) ...................................................................... 1469
30-15. Host Packet Descriptor Word 7 (HPD Word 7) ...................................................................... 1469
30-16. Host Buffer Descriptor Word 0 (HBD Word 0) ....................................................................... 1470
30-17. Host Buffer Descriptor Word 1 (HBD Word 1) ....................................................................... 1470
30-18. Host Buffer Descriptor Word 2 (HBD Word 2) ....................................................................... 1470
30-19. Host Buffer Descriptor Word 3 (HBD Word 3) ....................................................................... 1470
30-20. Host Buffer Descriptor Word 4 (HBD Word 4) ....................................................................... 1471
30-21. Host Buffer Descriptor Word 5 (HBD Word 5) ....................................................................... 1471
30-22. Host Buffer Descriptor Word 6 (HBD Word 6) ....................................................................... 1471
30-23. Host Buffer Descriptor Word 7 (HBD Word 7) ....................................................................... 1471
30-24. Teardown Descriptor Word 0 .......................................................................................... 1472
......................................................................................
Allocation of Queues ....................................................................................................
Interrupts Generated by the USB Controller .........................................................................
USB Interrupt Conditions ...............................................................................................
USB Interrupts ...........................................................................................................
Universal Serial Bus OTG (USB0) Registers ........................................................................
Revision Identification Register (REVID) Field Descriptions ......................................................
Control Register (CTRLR) Field Descriptions .......................................................................
Status Register (STATR) Field Descriptions.........................................................................
Emulation Register (EMUR) Field Descriptions .....................................................................
Mode Register (MODE) Field Descriptions ..........................................................................
Auto Request Register (AUTOREQ) Field Descriptions ...........................................................
SRP Fix Time Register (SRPFIXTIME) Field Descriptions ........................................................
Teardown Register (TEARDOWN) Field Descriptions .............................................................
USB Interrupt Source Register (INTSRCR) Field Descriptions ...................................................
USB Interrupt Source Set Register (INTSETR) Field Descriptions ...............................................
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................
USB Interrupt Mask Register (INTMSKR) Field Descriptions .....................................................
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions ...........................................
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions.........................................
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ...................................
USB End of Interrupt Register (EOIR) Field Descriptions .........................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions .......................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions .......................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions .......................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions .......................................
Function Address Register (FADDR) Field Descriptions ...........................................................
Power Management Register (POWER) Field Descriptions .......................................................
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)Field Descriptions ..............
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ..................................
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ...........................................
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions .......................................
Frame Number Register (FRAME) Field Descriptions .............................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)Field Descriptions ........
30-25. Teardown Descriptor Words 1-7
30-26.
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
30-34.
30-35.
30-36.
30-37.
30-38.
30-39.
30-40.
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
30-47.
30-48.
30-49.
30-50.
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
68
List of Tables
1472
1473
1487
1487
1490
1503
1510
1510
1511
1511
1512
1514
1515
1515
1516
1517
1518
1519
1520
1521
1522
1523
1523
1524
1524
1525
1525
1526
1527
1528
1529
1529
1530
1531
1531
1532
SPRUH80C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
30-61. Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions ................................ 1532
30-62. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................ 1533
30-63. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions................ 1534
30-64. Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions ..................... 1535
30-65. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ............... 1536
30-66. Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions ..................... 1537
30-67. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions ................ 1538
30-68. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions................ 1539
30-69. Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions ..................... 1540
30-70. Count 0 Register (COUNT0) Field Descriptions
....................................................................
1541
30-71. Receive Count Register (RXCOUNT) Field Descriptions .......................................................... 1541
30-72. Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................ 1542
30-73. Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ............................... 1542
30-74. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................ 1543
30-75. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ...................... 1543
30-76. Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions ............................... 1544
30-77. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions ...................... 1545
30-78. Configuration Data Register (CONFIGDATA) Field Descriptions ................................................. 1546
30-79. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions .............................. 1547
30-80. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions .............................. 1547
30-81. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions .............................. 1548
30-82. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions .............................. 1548
30-83. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions .............................. 1549
30-84. Device Control Register (DEVCTL) Field Descriptions ............................................................. 1549
30-85. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions .................................................... 1550
30-86. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions .................................................... 1550
30-87. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions ........................................... 1551
30-88. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions
...........................................
1551
30-89. Hardware Version Register (HWVERS) Field Descriptions........................................................ 1552
30-90. Transmit Function Address (TXFUNCADDR) Field Descriptions ................................................. 1553
30-91. Transmit Hub Address (TXHUBADDR) Field Descriptions ........................................................ 1553
30-92. Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................. 1553
30-93. Receive Function Address (RXFUNCADDR) Field Descriptions
.................................................
1554
30-94. Receive Hub Address (RXHUBADDR) Field Descriptions......................................................... 1554
30-95. Receive Hub Port (RXHUBPORT) Field Descriptions .............................................................. 1554
30-96. CDMA Revision Identification Register (DMAREVID) Field Descriptions ........................................ 1555
30-97. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ..................... 1555
30-98. CDMA Emulation Control Register (DMAEMU) Field Descriptions ............................................... 1556
.................
CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions ................
Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ............
Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ............
CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions ................................
CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions .....................................
Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions ........................
Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions .......
30-99. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions
30-100.
30-101.
30-102.
30-103.
30-104.
30-105.
30-106.
30-107.
30-108.
30-109.
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1556
1557
1558
1559
1560
1560
1562
1562
1563
1564
1565
69
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30-110. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions ....... 1566
30-111. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions
......
1566
30-112. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ................... 1567
......
30-114. Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions .....................................
30-115. Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions .....................................
30-116. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions .....
30-117. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions ..............
30-118. Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions ................................
30-119. Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions ...............................
30-120. Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions ...............................
30-121. Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions ...............................
31-1. Supported Formats on VPIF ...........................................................................................
31-2. Input and Output Usage Combinations on VPIF ....................................................................
31-3. Receive Pin Multiplexing Control ......................................................................................
31-4. Transmit Pin Multiplexing Control .....................................................................................
31-5. Video Port Interface (VPIF) Registers ................................................................................
31-6. VPIF Revision ID Register (REVID) Field Descriptions ............................................................
31-7. Channel 0 Control Register (C0CTRL) Field Descriptions .........................................................
31-8. Channel 1 Control Register (C1CTRL) Field Descriptions .........................................................
31-9. Channel 2 Control Register (C2CTRL) Field Descriptions .........................................................
31-10. Channel 3 Control Register (C3CTRL) Field Descriptions .........................................................
31-11. Interrupt Enable Register (INTEN) Field Descriptions ..............................................................
31-12. Interrupt Enable Set Register (INTSET) Field Descriptions .......................................................
31-13. Interrupt Enable Clear Register (INTCLR) Field Descriptions .....................................................
31-14. Interrupt Status Register (INTSTAT) Field Descriptions ...........................................................
31-15. Interrupt Status Clear Register (INTSTATCLR) Field Descriptions ...............................................
31-16. Emulation Suspend Control Register (EMUCTRL) Field Descriptions ...........................................
31-17. DMA Size Control Register (REQSIZE) Field Descriptions ........................................................
31-18. Channel n Top Field Luminance Address Register (CnTLUMA) Field Descriptions ...........................
31-19. Channel n Bottom Field Luminance Address Register (CnBLUMA) Field Descriptions .......................
31-20. Channel n Top Field Chrominance Address Register (CnTCHROMA) Field Descriptions ....................
31-21. Channel n Bottom Field Chrominance Address Register (CnBCHROMA) Field Descriptions ................
31-22. Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) Field Descriptions .................
31-23. Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) Field Descriptions .............
31-24. Channel n Top Field Vertical Ancillary Address Register (CnTVANC) Field Descriptions ....................
30-113. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions
1567
1568
1568
1569
1570
1571
1572
1572
1573
1578
1578
1579
1579
1600
1603
1603
1605
1606
1608
1610
1611
1612
1613
1614
1615
1615
1616
1616
1617
1617
1618
1618
1619
31-25. Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register (CnBVANC) Field
Descriptions .............................................................................................................. 1619
31-26. Channel n Image Address Offset Register (CnIMGOFFSET) Field Descriptions
..............................
1620
31-27. Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) Field Descriptions ............ 1620
31-28. Channel n Horizontal Size Configuration Register (CnHCFG) Field Descriptions .............................. 1621
31-29. Channel n Vertical Size Configuration 0 Register (CnVCFG0) Field Descriptions ............................. 1622
31-30. Channel n Vertical Size Configuration 1 Register (CnVCFG1) Field Descriptions ............................. 1622
31-31. Channel n Vertical Size Configuration 2 Register (CnVCFG2) Field Descriptions ............................. 1623
31-32. Channel n Vertical Image Size Register (CnVSIZE) Field Descriptions ......................................... 1623
31-33. Channel n Horizontal Size Configuration Register (CnHCFG) Field Descriptions .............................. 1624
31-34. Channel n Vertical Size Configuration 0 Register (CnVCFG0) Field Descriptions ............................. 1625
31-35. Channel n Vertical Size Configuration 1 Register (CnVCFG1) Field Descriptions ............................. 1625
31-36. Channel n Vertical Size Configuration 2 Register (CnVCFG2) Field Descriptions ............................. 1626
70
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31-37. Channel n Vertical Image Size Register (CnVSIZE) Field Descriptions ......................................... 1626
31-38. Channel n Top Field Horizontal Ancillary Position Register (CnTHANCPOS) Field Descriptions ............ 1627
31-39. Channel n Top Field Horizontal Ancillary Size Register (CnTHANCSIZE) Field Descriptions ................ 1628
31-40. Channel n Bottom Field Horizontal Ancillary Position Register (CnBHANCPOS) Field Descriptions ........ 1629
31-41. Channel n Bottom Field Horizontal Ancillary Size Register (CnBHANCSIZE) Field Descriptions ............ 1630
31-42. Channel n Top Field Vertical Ancillary Position Register (CnTVANCPOS) Field Descriptions ............... 1631
31-43. Channel n Top Field Vertical Ancillary Size Register (CnTVANCSIZE) Field Descriptions ................... 1632
31-44. Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) Field Descriptions ........... 1633
31-45. Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) Field Descriptions ............... 1634
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71
Preface
SPRUH80C – April 2013 – Revised September 2016
Read This First
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components
• DSP subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box provided at www.ti.com.
The current documentation that describes related peripherals and other technical collateral, is available in
the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
Code Composer Studio is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc..
SD is a trademark of SanDisk Corporation.
72
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Chapter 1
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Overview
Topic
1.1
1.2
...........................................................................................................................
Page
Introduction ....................................................................................................... 74
DSP Subsystem ................................................................................................. 74
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Introduction
1.1
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Introduction
The C6746 DSP efficiently handles communication and audio processing tasks. The C6746 DSP consists
of the following primary components:
• DSP subsystem and associated memories
• A set of I/O peripherals
• A powerful DMA subsystem and SDRAM EMIF interface
Block Diagram
A block diagram for the C6746 DSP is shown in Figure 1-1.
1.2
DSP Subsystem
The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks of
internal memory (L1P, L1D, and L2). The DSP Subsystem chapter describes the DSPSS components.
Figure 1-1. TMS320C6746 DSP Block Diagram
DSP Subsystem
JTAG Interface
System Control
PLL/Clock
Generator
w/OSC
Input
Clock(s)
C674x™
DSP CPU
Memory Protection
GeneralPurpose
Timer (x4)
AET
32KB
L1 Pgm
Power/Sleep
Controller
32KB
L1 RAM
256KB L2 RAM
RTC/
32-kHz
OSC
Pin
Multiplexing
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
EDMA3
(x2)
McASP
w/FIFO
Serial Interfaces
McBSP
(x2)
I2C
(x2)
eCAP
(x3)
UART
(x3)
Parallel
Port
VPIF
uPP
Connectivity
Control Timers
eHRPWM
(x2)
SPI
(x2)
Video
USB2.0
OTG Ctlr
PHY
EMAC
10/100
(MII/RMII)
MDIO
Customizable
Interface
PRU
Subsystem
External Memory Interfaces
HPI
MMC/SD
(8b)
(x2)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/mDDR
Memory
Controller
Note: Not all peripherals are available at the same time due to multiplexing.
DMA Subsystem
The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more
information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter.
74
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Chapter 2
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DSP Subsystem
Topic
2.1
2.2
2.3
2.4
...........................................................................................................................
Introduction .......................................................................................................
TMS320C674x Megamodule .................................................................................
Memory Map ......................................................................................................
Advanced Event Triggering (AET) ........................................................................
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76
77
82
82
75
Introduction
2.1
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Introduction
The DSP subsystem (Figure 2-1) includes TI’s standard TMS320C674x megamodule and several blocks
of internal memory (L1P, L1D, and L2). This chapter provides an overview of the DSP subsystem and the
following considerations associated with it:
• Memory mapping
• Interrupts
• Power management
For more information on the TMS320C674x megamodule, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5), the TMS320C674x DSP CPU and Instruction Set Reference Guide
(SPRUFE8), and the TMS320C674x DSP Cache User’s Guide (SPRUG82).
Figure 2-1. TMS320C674x Megamodule Block Diagram
32K bytes
L1P RAM/
cache
256K bytes
L2 RAM
256
256
1M bytes
L2 ROM
256
256
Cache control
Memory protect
Bandwidth Mgmt
Cache control
Memory protect
Bandwidth Mgmt
L1P
256
256
256
256
Instruction fetch
Power down
Interrupt
Controller
C674x
Fixed/floating point CPU
Register
file A
Register
file B
64
64
Bandwidth Mgmt
Memory protect
Cache control
8x32
76
DSP Subsystem
IDMA
256
Port
EMC
L1D
MDMA Port
64
32K bytes
L1D RAM/
cache
L2
64
32
Configuration
peripherals
bus
SDMA Port
64
64
High performance
switch fabric
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2.2
TMS320C674x Megamodule
The C674x megamodule (Figure 2-1) consists of the following components:
• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)
For more information about each of these controllers, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5).
2.2.1 Internal Memory Controllers
The C674x megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory (L1) is split into separate program memory (L1P memory) and data
memory (L1D memory). L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also
be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory
locations. The internal direct memory access controller (IDMA) manages DMA among the L1P, L1D, and
L2 memories.
2.2.2 Internal Peripherals
The C674x megamodule includes the following internal peripherals:
• DSP interrupt controller (INTC)
• DSP power-down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA) controller
This section briefly describes the INTC, PDC, BWM, and IDMA controller. For more information on these
internal peripherals, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
2.2.2.1
Interrupt Controller (INTC)
The C674x megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps DSP device events to 12 CPU interrupts. All DSP device events are listed in Table 2-1. The INTC is
fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
Table 2-1. DSP Interrupt Map
Event
Interrupt Name
Source
0
EVT0
C674x Interrupt Control 0
1
EVT1
C674x Interrupt Control 1
2
EVT2
C674x Interrupt Control 2
3
EVT3
C674x Interrupt Control 3
4
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
5
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
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Table 2-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
6
PRU_EVTOUT0
PRUSS Interrupt
7
EHRPWM0
HiResTimer/PWM0 Interrupt
8
EDMA3_0_CC0_INT1
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
9
EMU-DTDMA
C674x-ECM
10
EHRPWM0TZ
HiResTimer/PWM0 Trip Zone Interrupt
11
EMU-RTDXRX
C674x-RTDX
12
EMU-RTDXTX
C674x-RTDX
13
IDMAINT0
C674x-EMC
14
IDMAINT1
C674x-EMC
15
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
16
MMCSD0_INT1
MMCSD0 SDIO Interrupt
17
PRU_EVTOUT1
PRUSS Interrupt
18
EHRPWM1
HiResTimer/PWM1 Interrupt
19
USB0_INT
USB0 (USB2.0) Interrupt
20-21
78
—
Reserved
22
PRU_EVTOUT2
PRUSS Interrupt
23
EHRPWM1TZ
HiResTimer/PWM1 Trip Zone Interrupt
24
—
Reserved
25
T64P2_TINTALL
Timer64P2 Combined Interrupt (TINT12 and TINT34)
26
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
27
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
28
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
29
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
30
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
31
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
32
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
33
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
34
UHPI_DSPINT
HPI DSP Interrupt
35
PRU_EVTOUT3
PRUSS Interrupt
36
IIC0_INT
I2C0 Interrupt
37
SPI0_INT
SPI0 Interrupt
38
UART0_INT
UART0 Interrupt
39
PRU_EVTOUT5
PRUSS Interrupt
40
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
41
GPIO_B1INT
GPIO Bank 1 Interrupt
42
IIC1_INT
I2C1 Interrupt
43
SPI1_INT
SPI1 Interrupt
44
PRU_EVTOUT6
PRUSS Interrupt
45
ECAP0
ECAP0 Interrupt
46
UART_INT1
UART1 Interrupt
47
ECAP1
ECAP1 Interrupt
48
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
49
GPIO_B2INT
GPIO Bank 2 Interrupt
50
PRU_EVTOUT7
PRUSS Interrupt
51
ECAP2
ECAP2 Interrupt
52
GPIO_B3INT
GPIO Bank 3 Interrupt
53
MMCSD1_INT1
MMCSD1 SDIO Interrupt
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Table 2-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
54
GPIO_B4INT
GPIO Bank 4 Interrupt
55
EMIFA_INT
EMIFA Interrupt
56
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrrupt
57
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrrupt
58
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrrupt
59
GPIO_B5INT
GPIO Bank 5 Interrupt
60
DDR2_MEMERR
DDR2 Memory Error Interrupt
61
MCASP0_INT
McASP0 Combined RX/TX Interrupt
62
GPIO_B6INT
GPIO Bank 6 Interrupt
63
RTC_IRQS
RTC Combined Interrupt
64
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
65
GPIO_B0INT
GPIO Bank 0 Interrupt
66
PRU_EVTOUT4
PRUSS Interrupt
67
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
68
MMCSD1_INT0
MMCSD1 MMC/SD Interrupt
69
UART2_INT
UART2 Interrupt
70
PSC0_ALLINT
PSC0
71
PSC1_ALLINT
PSC1
72
GPIO_B7INT
GPIO Bank 7 Interrupt
73
—
Reserved
74
PROTERR
SYSCFG Protection Shared Interrupt
75
GPIO_B8INT
GPIO Bank 8 Interrupt
—
Reserved
78
T64P2_CMPINT0
Timer64P2 - Compare Interrupt 0
79
T64P2_CMPINT1
Timer64P2 - Compare Interrupt 1
80
T64P2_CMPINT2
Timer64P2 - Compare Interrupt 2
81
T64P2_CMPINT3
Timer64P2 - Compare Interrupt 3
82
T64P2_CMPINT4
Timer64P2 - Compare Interrupt 4
83
T64P2_CMPINT5
Timer64P2 - Compare Interrupt 5
84
T64P2_CMPINT6
Timer64P2 - Compare Interrupt 6
85
T64P2_CMPINT7
Timer64P2 - Compare Interrupt 7
86
T64P3_TINTALL
Timer64P3 Combined Interrupt (TINT12 and TINT34)
87
MCBSP0_RINT
McBSP0 Receive Interrupt
88
MCBSP0_XINT
McBSP0 Transmit Interrupt
89
MCBSP1_RINT
McBSP1 Receive Interrupt
90
MCBSP1_XINT
McBSP1 Transmit Interrupt
91
EDMA3_1_CC0_INT1
EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
92
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrrupt
93
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrrupt
94
UPP_INT
uPP Combined Interrupt
95
VPIF_INT
VPIF Combined Interrupt
96
INTERR
C674x-Interrupt Control
97
EMC_IDMAERR
C674x-EMC
—
Reserved
PMC_ED
C674x-PMC
—
Reserved
UMC_ED1
C674x-UMC
76-77
98-112
113
114-115
116
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Table 2-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
C674x-SYS
120
PMC_CMPA
C674x-PMC
121
PMC_CMPA
C674x-PMC
122
DMC_CMPA
C674x-DMC
123
DMC_CMPA
C674x-DMC
124
UMC_CMPA
C674x-UMC
125
UMC_CMPA
C674x-UMC
126
EMC_CMPA
C674x-EMC
127
EMC_BUSERR
C674x-EMC
2.2.2.1.1 Interrupt Controller Registers
For more information on the DSP interrupt controller (INTC) registers, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.1.2 NMI Interrupt
In addition to the interrupts listed in Table 2-1, the DSP also supports a special interrupt that behaves
more like an exception, non-maskable interrupt (NMI). The NMI interrupt is controlled by two registers in
the System Configuration Module, the chip signal register (CHIPSIG) and the chip signal clear register
(CHIPSIG_CLR).
The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. The NMI interrupt is cleared
by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. For more information on CHIPSIG and
CHIPSIG_CLR, see the System Configuration (SYSCFG) Module chapter.
2.2.2.2
Power-Down Controller (PDC)
The C674x megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C674x megamodule and internal memories of the DSP subsystem:
• C674x CPU
• Level 1 program memory controller (PMC)
• Level 1 data memory controller (DMC)
• Level 2 unified memory controller (UMC)
• Extended memory controller (EMC)
• Internal direct memory access (IDMA) controller
• L1P memory
• L1D memory
• L2 memory
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This device supports the static power-down feature from the C674x megamodule. The TMS320C674x
DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail.
• Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and
all internal memories immediately upon command from software.
Static power-down (clock gating) affects all components of the C674x megamodule and all internal
memories. Software can initiate static power-down by way of a register bit in the power-down controller
command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.3
Bandwidth Manager (BWM)
The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA3-initiated DMA transfers (and resulting coherency operations)
• DSP subsystem IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of the C674x megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA3, DSP subsystem IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The
programmable priority level has a single meaning throughout the system. There are a total of nine priority
levels, where priority zero is the highest priority and priority eight is the lowest priority. When requests for
a single resource contend, access is granted to the highest-priority requestor. When the contention occurs
for multiple successive cycles, a contention counter assures that the lower-priority requestor gets access
to the resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1
represents a transfer whose priority has been increased due to expiration of the contention counter or a
transfer that is fixed as the highest-priority transfer to a given resource.
2.2.2.4
Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) port. The IDMA cannot
transfer data to or from the internal DSP memory-mapped register space. The IDMA is fully described in
the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
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Memory Map
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Memory Map
Refer to your device-specific data manual for the addresses of the memory-map registers.
2.3.1 DSP Internal Memory
See the System Memory chapter for a description of the DSP internal memory.
2.3.2 External Memory
See the System Interconnect chapter and the System Memory chapter for a description of the additional
memory and peripherals that the DSP has access to.
2.4
Advanced Event Triggering (AET)
The C674x megamodule supports advanced event triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides
the following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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System Interconnect
Topic
3.1
3.2
...........................................................................................................................
Page
Introduction ....................................................................................................... 84
System Interconnect Block Diagram ..................................................................... 85
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Introduction
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Introduction
The DSP, the Programmable Real-Time Unit (PRU) subsystem, the EDMA3 transfer controllers, and the
device peripherals are interconnected through a switch fabric architecture (see Section 3.2). The switch
fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs
establish low-latency connectivity between master peripherals and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Through the SCRs, the DSP can send data to the EMIF without affecting a
data transfer between a device peripheral and internal shared memory. Bridges are mainly used to
perform bus-width conversion as well as bus operating frequency conversion.
The DSP, the PRU subsystem, the EDMA3 transfer controllers, and the various device peripherals can be
classified into two categories: master peripherals and slave peripherals. Master peripherals are typically
capable of initiating read and write transfers in the system and do not rely on the EDMA3 or on a CPU to
perform transfers to and from them. The system master peripherals include the DSP, the EDMA3 transfer
controllers, EMAC, PRU subsystem, USB2.0, uPP, VPIF, and HPI. Not all master peripherals may connect
to all slave peripherals. The supported connections are designated by an X in Table 3-1.
Table 3-1. TMS320C6746 DSP System Interconnect Matrix
Masters
Master
DSP
SDMA
EMIFA
DDR2/
mDDR
EDMA3_0_TC0/
TC1
EDMA3_1_TC0
Peripheral
Group (1)
EDMA3_0_CC0
0
EDMA3_1_CC0
0
EDMA3_0_TC0
0
X
X
X
X
X
X
EDMA3_0_TC1
0
X
X
X
X
X
X
PRU0/PRU1
0
X
X
X
X
X
X
DSP CFG
2
X
X
X
DSP MDMA
2
X
EDMA3_1_TC0
4
X
X
X
EMAC
4
uPP
X
X
X
X
X
X
X
X
X
4
X
X
X
USB2.0
4
X
X
X
VPIF
4
X
X
X
HPI
6
X
X
X
(1)
(2)
84
Slaves
Default
Priority
X (2)
Peripheral group: SYSCFG, EMAC, eCAP0, eCAP1, eCAP2, eHRPWM0, eHRPWM1, GPIO, I2C0, I2C1, McASP0, McBSP0,
McBSP1, MDIO, MMC/SD0, MMC/SD1, PLLC0, PLLC1, PRU RAM0, PRU RAM1, PRU Config, PSC0, PSC1, RTC, SPI0, SPI1,
TIMER64P0, TIMER64P1, TIMER64P2, TIMER64P3, EDMA3_0_CC0, EDMA3_1_CC0, UART0, UART1, UART2, HPI, USB0
(USB2.0), uPP, VPIF.
The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level.
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3.2
System Interconnect Block Diagram
Figure 3-1 shows a system interconnect block diagram.
Figure 3-1. System Interconnect Block Diagram
HPI
USB0 VBUSP
DSP SDMA (L1D/L2)
USB0 CDMA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
SCR F1
EMAC
SCR F0
BR F0
BR F1
SCR F3
MPU2
DDR2/mDDR
DSP MDMA
EDMA3_0_TC0
EDMA3_0_TC1
EDMA3_1_TC0
rd
EDMA3_1_CC0
wr
SCR1
EDMA3_1_CC0
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
rd
EDMA3_1_TC0
wr
USB0 Cfg
rd
PSC0
SCR5
wr
HPI
SCR F5
PLLC0
uPP
SYSCFG0
VPIF
MMC/SD1
uPP DMA
VPIF DMA0
BR5
SCR F2
VPIF DMA1
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 2 Clock Domain
BR3
SYSCFG1
Timer64P0
BR4
EMAC
Timer64P1
SCR6
DSP CFG
EMAC MDIO
I2C0
SCR F6
RTC
BR6
GPIO
PSC1
PRU0
I2C1
PLLC1
PRU1
Async 1 Clock Domain
BR7
BR F3
EMIFA
Async 3 [PLL1] Clock Domain
PRU CFG
McBSP0
McBSP1
MMC/SD0
SCR2
SCR4
BR F4
SCR F7
UART1
SPI0
UART2
UART0
McASP0
Legend:
32-bit BUS
64-bit BUS
EDMA3_0_TC0
eHRPWM0
EDMA3_0_TC1
eHRPWM1
IP Module
Synchronous Bridge
Asynchronous Bridge
SCR
Timer64P2
BR F5
SCR F8
Timer64P3
eCAP0
eCAP1
Paths with dashed lines cross the subchip boundary
eCAP2
SPI1
EDMA3_0_CC0
EDMA3_0_CC0
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System Memory
Topic
4.1
4.2
4.3
86
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Introduction ....................................................................................................... 87
DSP Memories ................................................................................................... 87
Peripherals ........................................................................................................ 87
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4.1
Introduction
This device has multiple on-chip/off-chip memories and several external device interfaces associated with
the DSP and various subsystems. To help simplify software development, a unified memory-map is used
wherever possible to maintain a consistent view of device resources across all masters.
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
4.2
DSP Memories
The DSP internal memories are accessible by the DSP and other master peripherals (as dictated by the
connectivity matrix) via the system interconnect through the DSP SDMA port.
The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
• L1P memory includes 32 KB of RAM. The DSP program memory controller (PMC) allows you to
configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache
sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB
cache.
• L1D memory includes 32 KB of RAM. The DSP data memory controller (DMC) allows you to configure
part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB,
8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB cache.
• L2 memory includes 256 KB of RAM. The DSP unified memory controller (UMC) allows you to
configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0
KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, or 256 KB of the 256 KB of RAM. The default
configuration is 256 KB normal RAM.
• L2 memory also includes 1024 KB of ROM.
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIF:
– 8/16-bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM,
NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space
• DDR2/mDDR memory controller:
– 16-bit DDR2 with up to 256-MB memory address space
– 16-bit mDDR with up to 256-MB memory address space
Internal Peripherals
The following peripherals are internal to the DSP subsystem and are only accessible to the DSP:
• DSP interrupt controller (INTC)
• DSP power down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA)
For more information on the internal peripherals, see the TMS320C674x DSP Megamodule Reference
Guide (SPRUFK5).
4.3
Peripherals
The DSP has access to all peripherals. See the device-specific data manual for the complete list of
peripherals supported on your device.
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Memory Protection Unit (MPU)
Topic
5.1
5.2
5.3
88
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Introduction ....................................................................................................... 89
Architecture....................................................................................................... 90
MPU Registers ................................................................................................... 95
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5.1
Introduction
This device supports one memory protection unit (MPU2). MPU2 supports the DDR2/mDDR SDRAM.
5.1.1 Purpose of the MPU
The memory protection unit (MPU) is provided to manage access to memory. The MPU allows you to
define multiple ranges and limit access to system masters based on their privilege ID. The MPU can
record a detected fault, or invalid access, and notify the system through an interrupt.
5.1.2 Features
The MPU supports the following features:
• Supports multiple programmable address ranges
• Supports 0 or 1 fixed range
• Supports read, write, and execute access privileges
• Supports privilege ID associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• Supports L1/L2 cache accesses
• Supports protection of its own registers
5.1.3 Block Diagram
Figure 5-1 shows a block diagram of the MPU. An access to a protected memory must pass through the
MPU. During an access, the MPU checks the memory address on the input data bus against fixed and
programmable ranges. If allowed, the transfer is passed unmodified to the output data bus. If the transfer
fails the protection check then the MPU does not pass the transfer to the output bus but rather services
the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor
as well as generating an interrupt about the fault. The MPU generates two interrupts: an address error
interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).
Figure 5-1. MPU Block Diagram
MPU
Input
Data
Bus
Protection
Checks
Output
Data
Bus
MPU_ADDR_ERR_INT
MMRs
MPU_PROT_ERR_INT
MPU Register Bus
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5.1.4 MPU Default Configuration
Table 5-1 shows the memory region protected by the MPU2. Table 5-2 shows the configuration of the
MPU2.
Table 5-1. MPU Memory Regions
Memory Region
Unit
Memory Protection
Start Address
End Address
MPU2
DDR2/mDDR SDRAM
C000 0000h
DFFF FFFFh
Table 5-2. MPU2 Default Configuration
Setting
MPU2
Default permission
Assume allowed
Number of allowed IDs supported
12
Number of fixed ranges supported
0
Number of programmable ranges supported
12
Compare width
5.2
64 KB granularity
Architecture
5.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
DSP CPU instruction and data accesses have a privilege level associated with them. The privilege level is
inherited from the code running on the CPU. See the TMS320C674x DSP CPU and Instruction Set
Reference Guide (SPRUFE8) for more details on privilege levels of the DSP CPU.
Although master peripherals like the HPI do not execute code, they still have a privilege level associated
with them. Unlike the DSP CPU, the privilege level of this peripheral is fixed.
Table 5-3 shows the privilege ID of the CPU and every mastering peripheral. Table 5-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.
Table 5-3. Device Master Settings
Master
90
Privilege Level
Access Type
EDMA3_0_CC0
Privilege ID
Inherited
Inherited
DMA
EDMA3_0_TC0 and EDMA3_0_TC1
Inherited
Inherited
DMA
EDMA3_1_CC0
Inherited
Inherited
DMA
EDMA3_1_TC0
Inherited
Inherited
DMA
DSP
1
Software dependant
Software dependant
PRU0/PRU1
2
Supervisor
DMA
HPI
3
User
DMA
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Table 5-3. Device Master Settings (continued)
Master
Privilege ID
Privilege Level
Access Type
EMAC
4
Supervisor
Data/DMA
USB2.0
6
Supervisor
DMA
uPP
8
Supervisor
DMA
VPIF DMA0
10
Supervisor
DMA
VPIF DMA1
11
Supervisor
DMA
5.2.2 Memory Protection Ranges
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory. One of the programmable
address ranges could be used to detect accesses to this unpopulated memory.
The MPU divides its assigned memory into address ranges. Each MPU can support one fixed address
range and multiple programmable address ranges. The fixed address range is configured to an exact
address. The programmable address range allows software to program the start and end addresses.
Each address range has the following set of registers:
• Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending
address of the address range.
• Memory protection page attribute register (MPPA): Use to program the permission settings of the
address range.
It is allowed to configure ranges such that they overlap each other. In this case, all the overlapped ranges
must allow the access, otherwise the access is not allowed. The final permissions given to the access are
the lowest of each type of permission from any hit range.
Addresses not covered by a range are either allowed or disallowed based on the configuration of the
MPU. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the
ASSUME_ALLOWED bit in the configuration register (CONFIG).
5.2.3 Permission Structures
The MPU defines a per-range permission structure with three permission fields in a 32-bit permission
entry. Figure 5-2 shows the structure of a permission entry.
Figure 5-2. Permission Fields
31
22
21
20
19
AID11
AID10
AID9
5
4
3
Reserved
15
14
13
12
11
10
AID4
AID3
AID2
9
8
6
Reserved
AID1
AID0
17
16
AID8
AID7
AID6
2
1
0
UW
UX
Allowed IDs
Allowed IDs
AID5
18
AIX
Access Types
SR
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SX
UR
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Requestor-ID Based Access Controls
Each master on the device has an N-bit code associated with it that identifies it for privilege purposes.
This privilege ID accompanies all memory accesses made on behalf of that master. That is, when a
master triggers a memory access command, the privilege ID will be carried alongside the command.
Each memory protection range has an allowed ID (AID) field associated with it that indicates which
requestors may access the given address range. The MPU maps the privilege IDs of all the possible
requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA).
• AID0 through AID11 are used to specify the allowed privilege IDs.
• An additional allowed ID bit, AIDX, captures access made by all privilege IDs not covered by AID0
through AID11.
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies
access to the corresponding requestor.
5.2.3.2
Request-Type Based Permissions
The memory protection model defines three fundamental functional access types: read, write, and
execute. Read and write refer to data accesses -- accesses originating via the load/store units on the CPU
or via a master peripheral. Execute refers to accesses associated with an instruction fetch.
The memory protection model allows controlling read, write, and execute permissions independently for
both user and supervisor mode. This results in six permission bits, listed in Table 5-4. For each bit, a 1
permits the access type and a 0 denies access. For example, UX = 1 means that User Mode may execute
from the given page. The memory protection unit allows you to specify all six of these bits separately; 64
different encodings are permitted altogether, although programs might not use all of them.
Table 5-4. Request Type Access Controls
92
Bit
Field
Description
5
SR
Supervisor may read
4
SW
Supervisor may write
3
SX
Supervisor may execute
2
UR
User may read
1
UW
User may write
0
UX
User may execute
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5.2.4 Protection Check
During a memory access, the MPU checks if the address range of the input transfer overlaps one of the
address ranges. When the input transfer address is within a range the transfer parameters are checked
against the address range permissions.
The MPU first checks the transfers privilege ID against the AID settings. If the AID bit is 0, then the range
will not be checked; if the AID bit is 1, then the transfer parameters are checked against the memory
protection page attribute register (MPPA) values to detect an allowed access.
For non-debug accesses, the read, write, and execute permissions are also checked. There is a set of
permissions for supervisor mode and a set for user mode. For supervisor mode accesses, the SR, SW,
and SX bits are checked. For user mode accesses, the UR, UW, and UX bits are checked.
If the transfer address range does not match any address range then the transfer is either allowed or
disallowed based on the configuration of the MPU. The MPU can be configured for assumed allowed or
assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register
(CONFIG).
In the case that a transfer spans multiple address ranges, all the overlapped ranges must allow the
access, otherwise the access is not allowed. The final permissions given to the access are the lowest of
each type of permission from any hit range. Therefore, if a transfer matches 2 ranges, one that is RW and
one that is RX, then the final permission is just R.
The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses, see
Section 5.2.5 for more details.
5.2.5 DSP L1/L2 Cache Controller Accesses
A memory read access that originates from the DSP L1/L2 cache is treated differently to allow memory
protection to be enforced by the DSP level. This is because a subsequent memory access that hits in the
cache does not pass through the MPU. Instead the memory access is serviced directly by the L1/L2
memory controllers.
During a cache memory read, the permission settings stored in the memory protection page attribute
registers (MPPA) are passed to the L1/L2 memory controllers along with the read data. The permissions
settings returned by the MPU are taken from MPPA that covers the address range of the original
request—only the SR, SW, SX, UR, UW, and UX bits are passed. If the request address is covered by
multiple address ranges, then the returned value is the logical-AND of all MPPA permissions. If the
transfer address range is not covered by an address range then the transfer is either allowed or
disallowed based on the configuration of the MPU.
5.2.6 MPU Register Protection
Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page
attribute registers (MPPA) is also protected. All non-debug writes must be by a supervisor entity. A
protection fault can occur from a register write with invalid permissions and this triggers an interrupt just
like a memory access.
Faults are not recorded (nor interrupts generated) for debug accesses.
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5.2.7 Invalid Accesses and Exceptions
When a transfer fails the protection check, the MPU does not pass the transfer to the output bus. The
MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.
The behavior of the MPU depends on whether the access was a read or a write:
• For a read: The MPU returns 0s, a permission value is 0 (no access allowed), a protection error status.
• For a write: The MPU receives all the write data and returns a protection error status.
The MPU captures system faults due to addressing or protection violations in its registers. The MPU can
store the fault information for only one fault, so the first detected fault is recorded into the fault registers
and an interrupt is generated. Software must use the fault clear register (FLTCLR) to clear the fault status
so that another fault can be recorded. The MPU will not record another fault nor generate another interrupt
until the existing fault has been cleared. Also, additional faults will be ignored. Faults are not recorded (no
interrupts generated) for debug accesses.
5.2.8 Reset Considerations
After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection
features.
5.2.9 Interrupt Support
5.2.9.1
Interrupt Events and Requests
The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection
interrupt (MPU_PROT_ERR_INT). The MPU_ADDR_ERR_INT is generated when there is an addressing
violation due to an access to a non-existent location in the MPU register space. The
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined
ranges or to the MPU registers.
The transfer parameters that caused the violation are saved in the MPU registers.
5.2.9.2
Interrupt Multiplexing
The interrupts from both MPUs are combined with the boot configuration module into a single interrupt
called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt controller. Table 5-5
shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR.
Table 5-5. MPU_BOOTCFG_ERR Interrupt Sources
Interrupt
Source
MPU2_ADDR_ERR_INT
MPU2 address error interrupt
MPU2_PROT_ERR_INT
MPU2 protection interrupt
BOOTCFG_ADDR_ERR
Boot configuration address error
BOOTCFG_PROT_ERR
Boot configuration protection error
5.2.10 Emulation Considerations
Memory and MPU registers are not protected against emulation accesses.
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5.3
MPU Registers
Table 5-6 lists the memory-mapped registers for the MPU2.
Table 5-6. Memory Protection Unit 2 (MPU2) Registers
Address
Acronym
Register Description
01E1 5000h
REVID
Revision identification register
Section 5.3.1
01E1 5004h
CONFIG
Configuration register
Section 5.3.2
01E1 5010h
IRAWSTAT
Interrupt raw status/set register
Section 5.3.3
01E1 5014h
IENSTAT
Interrupt enable status/clear register
Section 5.3.4
01E1 5018h
IENSET
Interrupt enable set register
Section 5.3.5
01E1 501Ch
IENCLR
Interrupt enable clear register
Section 5.3.6
01E1 5100h
FXD_MPSAR
Fixed range start address register
Section 5.3.7
01E1 5104h
FXD_MPEAR
Fixed range end address register
Section 5.3.8
01E1 5108h
FXD_MPPA
Fixed range memory protection page attributes register
Section 5.3.9
01E1 5200h
PROG1_MPSAR
Programmable range 1 start address register
Section 5.3.10
01E1 5204h
PROG1_MPEAR
Programmable range 1 end address register
Section 5.3.11
01E1 5208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
Section 5.3.12
01E1 5210h
PROG2_MPSAR
Programmable range 2 start address register
Section 5.3.10
01E1 5214h
PROG2_MPEAR
Programmable range 2 end address register
Section 5.3.11
01E1 5218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
Section 5.3.12
01E1 5220h
PROG3_MPSAR
Programmable range 3 start address register
Section 5.3.10
01E1 5224h
PROG3_MPEAR
Programmable range 3 end address register
Section 5.3.11
01E1 5228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
Section 5.3.12
01E1 5230h
PROG4_MPSAR
Programmable range 4 start address register
Section 5.3.10
01E1 5234h
PROG4_MPEAR
Programmable range 4 end address register
Section 5.3.11
01E1 5238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
Section 5.3.12
01E1 5240h
PROG5_MPSAR
Programmable range 5 start address register
Section 5.3.10
01E1 5244h
PROG5_MPEAR
Programmable range 5 end address register
Section 5.3.11
01E1 5248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
Section 5.3.12
01E1 5250h
PROG6_MPSAR
Programmable range 6 start address register
Section 5.3.10
01E1 5254h
PROG6_MPEAR
Programmable range 6 end address register
Section 5.3.11
01E1 5258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
Section 5.3.12
01E1 5260h
PROG7_MPSAR
Programmable range 7 start address register
Section 5.3.10
01E1 5274h
PROG7_MPEAR
Programmable range 7 end address register
Section 5.3.11
01E1 5268h
PROG7_MPPA
Programmable range 7 memory protection page attributes register
Section 5.3.12
01E1 5270h
PROG8_MPSAR
Programmable range 8 start address register
Section 5.3.10
01E1 5274h
PROG8_MPEAR
Programmable range 8 end address register
Section 5.3.11
01E1 5278h
PROG8_MPPA
Programmable range 8 memory protection page attributes register
Section 5.3.12
01E1 5280h
PROG9_MPSAR
Programmable range 9 start address register
Section 5.3.10
01E1 5284h
PROG9_MPEAR
Programmable range 9 end address register
Section 5.3.11
01E1 5288h
PROG9_MPPA
Programmable range 9 memory protection page attributes register
Section 5.3.12
01E1 5290h
PROG10_MPSAR
Programmable range 10 start address register
Section 5.3.10
01E1 5294h
PROG10_MPEAR
Programmable range 10 end address register
Section 5.3.11
01E1 5298h
PROG10_MPPA
Programmable range 10 memory protection page attributes register
Section 5.3.12
01E1 52A0h
PROG11_MPSAR
Programmable range 11 start address register
Section 5.3.10
01E1 52A4h
PROG11_MPEAR
Programmable range 11 end address register
Section 5.3.11
01E1 52A8h
PROG11_MPPA
Programmable range 11 memory protection page attributes register
Section 5.3.12
01E1 52B0h
PROG12_MPSAR
Programmable range 12 start address register
Section 5.3.10
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Table 5-6. Memory Protection Unit 2 (MPU2) Registers (continued)
Address
Acronym
Register Description
01E1 52B4h
PROG12_MPEAR
Programmable range 12 end address register
Section 5.3.11
Section
01E1 52B8h
PROG12_MPPA
Programmable range 12 memory protection page attributes register
Section 5.3.12
01E1 5300h
FLTADDRR
Fault address register
Section 5.3.13
01E1 5304h
FLTSTAT
Fault status register
Section 5.3.14
01E1 5308h
FLTCLR
Fault clear register
Section 5.3.15
5.3.1 Revision Identification Register (REVID)
The revision ID register (REVID) contains the MPU revision. The REVID is shown in Figure 5-3 and
described in Table 5-7.
Figure 5-3. Revision ID Register (REVID)
31
0
REV
R-4E81 0101h
LEGEND: R = Read only; -n = value after reset
Table 5-7. Revision ID Register (REVID) Field Descriptions
96
Bit
Field
Value
31-0
REV
4E81 0101h
Memory Protection Unit (MPU)
Description
Revision ID of the MPU.
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5.3.2 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown
in Figure 5-4 and described in Table 5-8.
NOTE: Although the NUM_AIDS bit defaults to 12 (Ch), not all AIDs may be supported on your
device. Unsupported AIDs should be cleared to 0 in the memory page protection attributes
registers (MPPA). See for a list of AIDs supported on your device.
Figure 5-4. Configuration Register (CONFIG)
31
24
15
23
20
19
16
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-6h
R-1
R-Ch
12
11
1
0
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-Ch
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 5-8. Configuration Register (CONFIG) Field Descriptions
Field
Value
Description
31-24
Bit
ADDR_WIDTH
0-FFh
Address alignment (2n KByte alignment) for range checking.
23-20
NUM_FIXED
0-Fh
Number of fixed address ranges.
19-16
NUM_PROG
0-Fh
Number of programmable address ranges.
15-12
NUM_AIDS
0-Fh
Number of supported AIDs.
11-1
Reserved
0
0
ASSUME_ALLOWED
Reserved
Assume allowed. When an address is not covered by any MPU protection range, this bit
determines whether the transfer is assumed to be allowed or not allowed.
0
Assume is disallowed.
1
Assume is allowed.
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5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 5-5 and described in Table 5-9.
Figure 5-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-9. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
98
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 5-6 and described in Table 510.
Figure 5-6. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.5 Interrupt Enable Set Register (IENSET)
Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Software can
write to IENSET to enable an interrupt. Writes of 0 have no effect. The IENSET is shown in Figure 5-7 and
described in Table 5-11.
Figure 5-7. Interrupt Enable Set Register (IENSET)
31
16
Reserved
R-0
15
2
1
0
ADDRERR_EN
PROTERR_EN
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Interrupt Enable Set Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved
Address violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
PROTERR_EN
Protection violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
5.3.6 Interrupt Enable Clear Register (IENCLR)
Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Software can
write to IENCLR to clear/disable an interrupt. Writes of 0 have no effect. The IENCLR is shown in
Figure 5-8 and described in Table 5-12.
Figure 5-8. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-12. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
100
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved
Address violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
PROTERR_CLR
Protection violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
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5.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPSAR and the fixed range end
address register (FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in Figure 5-9.
Figure 5-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
5.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPEAR and the fixed range start
address register (FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 5-10.
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 5-11
and described in Table 5-13.
Figure 5-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-13. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
102
Controls access from ID = n.
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR)
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory, especially memory. One of the
programmable address ranges could be used to detect accesses to this unpopulated
memory.
The programmable range n start address register (PROGn_MPSAR) holds the start address for the range
n. The PROGn_MPSAR is writeable by a supervisor entity only.
The start address must be aligned on a page boundary. The page size for MPU2 is 64 KBytes. The size of
the page determines the width of the address field in PROGn_MPSAR and the programmable range n end
address register (PROGn_MPEAR). For example, to protect a 64-KB page starting at byte address
8001 0000h, write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
The PROGn_MPSAR for MPU2 is shown in Figure 5-12 and described in Table 5-14.
Figure 5-12. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
31
16 15
0
START_ADDR
Reserved
R/W-C000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-14. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
Field
31-16
START_ADDR
15-0
Reserved
Value
C000h–DFFFh
0
Description
Start address for range N.
Reserved
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5.3.11 Programmable Range n End Address Registers (PROGn_MPEAR)
The programmable range n end address register (PROGn_MPEAR) holds the end address for the range
n. This register is writeable by a supervisor entity only.
The end address must be aligned on a page boundary. The page size for MPU2 is 64 KBytes. The size of
the page determines the width of the address field in the programmable range n start address register
(PROGn_MPSAR) and PROGn_MPEAR. For example, to protect a 64-KB page starting at byte address
8001 0000h, write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
The PROGn_MPEAR for MPU2 is shown in Figure 5-13 and described in Table 5-15.
Figure 5-13. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
31
16 15
0
END_ADDR
Reserved
R/W-DFFFh
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
Field
31-16
END_ADDR
15-0
Reserved
104
Value
C000h–DFFFh
FFFFh
Memory Protection Unit (MPU)
Description
Start address for range N.
Reserved
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5.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA)
The programmable range n memory protection page attributes register (PROGn_MPPA) holds the
permissions for the region n. This register is writeable only by a supervisor entity. The PROGn_MPPA is
shown in Figure 5-14 and described in Table 5-16.
Figure 5-14. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Controls access from ID = n.
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.13 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) holds the address of the first protection fault transfer. The
FLTADDRR is shown in Figure 5-15 and described in Table 5-17.
Figure 5-15. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
106
Field
FLTADDR
Value
0-FFFF FFFFh
Memory Protection Unit (MPU)
Description
Memory address of fault.
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5.3.14 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in Figure 5-16 and described in Table 5-18.
Figure 5-16. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
Reserved
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-18. Fault Status Register (FLTSTAT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MSTID
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
Value
0
0-FFh
0
0-Fh
0
0-3Fh
Description
Reserved
Master ID of fault transfer.
Reserved
Privilege ID of fault transfer.
Reserved
Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).
0
No fault.
1h
User execute fault.
2h
User write fault.
3h
Reserved
4h
User read fault.
5h-7h
8h
9h-Fh
Reserved
Supervisor execute fault.
Reserved
10h
Supervisor write fault.
11h
Reserved
12h
Relaxed cache write back fault.
13h-1Fh
20h
21h-3Eh
3Fh
Reserved
Supervisor read fault.
Reserved
Relaxed cache line fill fault.
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5.3.15 Fault Clear Register (FLTCLR)
The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured
in the fault status register (FLTSTAT) as well as produce an interrupt. Only the TYPE bit field in FLTSTAT
is cleared when a 1 is written to the CLEAR bit. The FLTCLR is shown in Figure 5-17 and described in
Table 5-19.
Figure 5-17. Fault Clear Register (FLTCLR)
31
16
Reserved
R-0
15
1
0
Reserved
CLEAR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 5-19. Fault Clear Register (FLTCLR) Field Descriptions
Bit
31-1
0
108
Field
Reserved
Value
0
CLEAR
Description
Reserved
Command to clear the current fault. Writing 0 has no effect.
0
No effect.
1
Clear the current fault.
Memory Protection Unit (MPU)
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Chapter 6
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Device Clocking
Topic
6.1
6.2
6.3
...........................................................................................................................
Page
Overview ......................................................................................................... 110
Frequency Flexibility ......................................................................................... 112
Peripheral Clocking .......................................................................................... 113
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Overview
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Overview
This device requires two primary reference clocks:
• One reference clock is required for the phase-locked loop controllers (PLLCs)
• One reference clock is required for the real-time clock (RTC) module.
These reference clocks may be sourced from either the on-board oscillator via an externally supplied
crystal or by a direct external oscillator input. For detailed specifications on clock frequency and voltage
requirements, see the electrical specifications in your device-specific data manual.
In addition to the reference clocks required for the PLLCs and RTC module, some peripherals, such as the
USB, may also require an input reference clock to be supplied. All possible input clocks are described in
Table 6-1. The CPU and the majority of the device peripherals operate at fixed ratios of the primary
system/CPU clock frequency, as listed in Table 6-2. However, there are two system clock domains that do
not require a fixed ratio to the CPU, these are PLL0_SYSCLK3 and PLL0_SYSCLK7. Figure 6-1 shows
the clocking architecture.
Table 6-1. Device Clock Inputs
Peripheral
Input Clock Signal Name
Oscillator/PLL
OSCIN
RTC
RTC_XI
JTAG
TCK
EMAC RMII
RMII_MHZ_50_CLK
EMAC MII
MII_TXCLK, MII_RXCLK
USB2.0
USB_REFCLKIN
I2Cs
I2Cn_SCL
Timers
TM64Pn_IN12
SPIs
SPIn_CLK
uPP
UPP_CHn_CLK
VPIF
VPIF_CLKINn
McBSPs
CLKSn, CLKRn, CLKXn
McASP0
ACLKR, AHCLKR, ACLKX, AHCLKX
Table 6-2. System Clock Domains
110
CPU/Device Peripherals
System Clock Domain
Fixed Ratio to
CPU Clock Required?
Default Ratio to
CPU Clock
DSP
PLL0_SYSCLK1
Yes
1:1
DSP ports, UART0, EDMA, SPI0, MMC/SDs, VPIF,
uPP, DDR2/mDDR (bus ports), USB2.0, HPI, PRU
subsystem
PLL0_SYSCLK2
Yes
1:2
EMIFA
PLL0_SYSCLK3
No
1:3
System configuration (SYSCFG), GPIO, PLLCs, PSCs, PLL0_SYSCLK4
I2C1, EMAC/MDIO
Yes
1:4
EMAC RMII clock
PLL0_SYSCLK7
No
1:6
I2C0, Timer64P0/P1, RTC, USB2.0 PHY, McASP0
serial clock
PLL0_AUXCLK
Not Applicable
Not Applicable
DDR2/mDDR PHY
PLL1_SYSCLK1
Not Applicable
Not Applicable
PLL0 input reference clock
(not configured by default)
PLL1_SYSCLK3
Not Applicable
Not Applicable
ECAPs, UART1/2, Timer64P2/3, eHRPWMs, McBSPs,
McASP0, SPI1
ASYNC3
Not Applicable
Not Applicable
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Figure 6-1. Overall Clocking Diagram
PLL0 Multiplier Out
Div 4.5
1
EMIFA (C)
0+
SYSCLK3 (/3)
EDMA
SYSCLK1 (/1)
DSP
CFGCHIP3[EMA_CLKSRC]
SPI0
MMC/SDs
System CFG
SYSCLK4 (/4)
HPI
PSCs
PLL0
Controller
USB2.0
I2C1
CLKSRC
uPP
EMAC/MDIO (D)
(E)
UART0
GPIO
EXTCLKSRC
(A)
VPIF
DDR2/mDDR (B)
I2C0
AUXCLK
PRU
Timers0/1
RTC
PLL
Ref CLK
Timers2/3
SYSCLK2 (/2)
0+
1
SYSCLK2 (/2)
PLL1
Controller
CFGCHIP3[ASYNC3_CLKSRC]
SYSCLK3 (/3)
UART1/2
McASP0
(F)
McBSPs
eHRPWMs
+ Default Mux Selection
eCAPs
CLKSRC
SPI1
A
See Section 6.3.1 for USB clocking.
B
See Section 6.3.2 for DDR2/mDDR clocking.
C
See Section 6.3.3 for EMIFA clocking.
D
See Section 6.3.4 for EMAC clocking.
E
See Section 6.3.5 for uPP clocking.
F
See Section 6.3.6 for McASP clocking.
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Frequency Flexibility
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Frequency Flexibility
There are two PLLs on the device with similar architecture and behavior. Each PLL has two clocking
modes:
• PLL Bypass
• PLL Active
When the PLL is in Bypass mode, the reference clock supplied on OSCIN serves as the clock source from
which all of the system clocks (SYSCLK1 to SYSCLK7) are derived. This means that when the PLL is in
Bypass mode, the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that
creates each of the system clocks. For PLL0 only, the EXTCLKSRC bit in PLLCTL can be configured to
use PLL1_SYSCLK3 as the Bypass mode reference clock.
When the PLL operates in Active mode, the PLL is enabled and the PLL multiplier setting is used to
multiply the input clock frequency supplied on the OSCIN pin up to the desired frequency. It is this
multiplied frequency that all system clocks are derived from in PLL Active mode.
The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the
system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1 to SYSCLK7). Each
SYSCLKn has a PLLDIVn block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter
for more details on the PLL.
The combination of the PLL multiplier, POSTDIV, and PLLDIV blocks provides flexibility in the frequencies
that the system clock domains support. This flexibility does have limitations, as follows:
• OSCIN input frequency is limited to a supported range.
• The output of the PLL Multiplier must be within the range specified in the device-specific data manual.
• The output of each PLLDIV block must be less than or equal to the maximum device frequency
specified in the device-specific data manual.
NOTE: The above limitations are provided here as an example and are used to illustrate the
recommended configuration of the PLL controller. These limitations may vary based on core
voltage and between devices. See the device-specific data manual for more details.
Table 6-3 shows examples of possible PLL multiplier settings, along with the available PLL post-divider
modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL
post-divider control register (POSTDIV). For Div1, Div2, Div3, and Div4 modes, the RATIO field would be
programmed to 0, 1, 2, and 3, respectively. The Div1, Div2, Div3, and Div4 modes are shown here as an
example. Additional post-divider modes are supported and are documented in the Phase-Locked Loop
Controller (PLLC) chapter.
NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases.
To decrease PLL power consumption, the lowest PLL multiplier (PLLM) setting should be
chosen that achieves the desired frequency. For example, if 200 MHz is the desired CPU
operating frequency and the OSCIN frequency is 25 MHz; lower power consumption is
achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2
instead of a PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these
modes would result in a CPU frequency of 200 MHz.
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Table 6-3. Example PLL Frequencies
6.3
OSCIN
Frequency
PLL Multiplier
Multiplier
Frequency
Div1
Div2
Div3
Div4
20
30
600 MHz
600
300
200
150
24
25
600 MHz
600
300
200
150
25
24
600 MHz
600
300
200
150
30
20
600 MHz
600
300
200
150
20
25
500 MHz
500
250
167
125
24
20
480 MHz
480
240
160
120
25
18
450 MHz
450
225
150
112.5
30
14
420 MHz
420
210
140
105
25
16
400 MHz
400
200
133
100
Peripheral Clocking
6.3.1 USB Clocking
Figure 6-2 shows the clock connections for the USB2.0 module. Note that there is no built-in oscillator.
The USB2.0 subsystem requires a reference clock for its internal PLL. This reference clock can be
sourced from either the USB_REFCLKIN pin or from the AUXCLK of the system PLL. The reference clock
input to the USB2.0 subsystem is selected by programming the USB0PHYCLKMUX bit in the chip
configuration 2 register (CFGCHIP2) of the System Configuration Module. The USB_REFCLKIN source
should be selected when it is not possible (such as when specific audio rates are required) to operate the
device at one of the allowed input frequencies to the USB2.0 subsystem. The USB2.0 subsystem
peripheral bus clock is sourced from PLL0_SYSCLK2. Table 6-4 determines the source origination as well
as the source input frequency to the USB 2.0 PHY. Once the clock source origination (internal/external)
and its frequency is determined, the firmware should program the PHY PLL with the correct input
frequency via CFGCHIP2.USB0REF_FREQ.
Figure 6-2. USB Clocking Diagram
USB_
AUXCLK REFCLKIN
CFGCHIP2[USB0PHYCLKMUX]
1
0
USB 2.0
Subsystem
(USB0)
Table 6-4. USB Clock Multiplexing Options
CFGCHIP2.
USB0PHYCLKMUX
bit
USB2.0
Clock
Source
0
USB_REFCLKIN
USB_REFCLKIN must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be configured to accept any of these input
clock frequencies.
1
PLL0_AUXCLK
PLL0_AUXCLK must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be configured to accept any of these input
clock frequencies.
Additional Conditions
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6.3.2 DDR2/mDDR Memory Controller Clocking
The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see
Figure 6-3):
• VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO, write FIFO, and read FIFO of
the DDR2/mDDR memory controller. From this, VCLK drives the interface to the peripheral bus.
• 2X_CLK is sourced from PLL1_SYSCLK1.
2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
Table 6-5 shows example PLL register settings based on the OSCIN reference clock frequency of
25 MHz. From these example configurations, the following observations are made:
• To achieve the maximum frequency (150 MHz) supported by the DDR2/mDDR memory controller and
the typical CPU frequency of 300 MHz, the output of the PLL multiplier should be set to be 300 MHz
and the DDR_CLK source should be set to PLL1_SYSCLK1.
• The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier
block.
• The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock
frequencies.
• For certain PLL1 multiplier and PLL1 post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK1 as the clock source for 2X_CLK.
If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the
application as a free running clock that could be used by an FPGA or for some other purpose, then
2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. This
allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while
still providing a clock on the DDR_CLK and DDR_CLK.
NOTE: DDR_CLK and DDR_CLK are output clock signals.
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Figure 6-3. DDR2/mDDR Memory Controller Clocking Diagram
On Chip
PLL0_SYSCLK2/2
DDR2/mDDR
Memory
Controller
LPSC #6
DDR_CLK
DDR_CLK
VCLK
PLL1_SYSCLK1
2X_CLK
DDR
PHY
MCLK
Table 6-5. DDR2/mDDR Memory Controller MCLK Frequencies
OSCIN
Frequency
PLL1
Multiplier
Register
Setting
PLL1
Multiplier
Frequency
PLL1 Post
Divider
Mode (1)
PLL1
POSTDIV
Output
Frequency
PLL1
PLLDIV1
Register
Setting
PLL1_SYSCLK1
MCLK
24
18h
600 MHz
Div2
300 MHz
8000h
300 MHz
150 MHz
24
15h
528 MHz
Div2
264 MHz
8000h
264 MHz
132 MHz
24
14h
504 MHz
Div2
252 MHz
8000h
252 MHz
126 MHz
(1)
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.3 EMIFA Clocking
EMIFA requires a single input clock source. The EMIFA clock can be sourced from either PLL0_SYSCLK3
or DIV4P5 (see Figure 6-4). The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the
System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock
source for EMIFA.
Selecting the appropriate clock source for EMIFA is determined by the desired clock rate. Table 6-6 shows
example PLL register settings and the resulting DIV4P5 and PLL0_SYSCLK3 frequencies based on the
OSCIN reference clock frequency of 25 MHz. From these example configurations, the following
observations can be made:
• To achieve a typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300
MHz, the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be
set to PLL0_SYSCLK3 with the PLLDIV3 register set to 3.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV3 block that sets the divider ratio for PLL0_SYSCLK3 can be changed to achieve various
clock frequencies.
Figure 6-4. EMIFA Clocking Diagram
LPSC
PLL Controller
SYSCLK3
0
DIV4P5 CLK
1
EMIFA
CFGCHIP3[EMA_CLKSRC]
Table 6-6. EMIFA Frequencies
OSCIN
Frequency
PLL Multiplier
Register
Multiplier
Setting
Frequency
Post Divider
Mode (1)
POSTDIV
Output
Frequency
25
24
Div2
300 MHz
Div3
200 MHz
25
18
25
(1)
116
16
600 MHz
450 MHz
400 MHz
DIV4P5
PLLDIV3
Register
Setting
PLL0_SYSCLK3
133 MHz
2
100 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
Div2
225 MHz
100 MHz
3
56.3 MHz
2
75 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
Div2
200 MHz
89 MHz
2
66.6 MHz
1
100 MHz
Div3
133 MHz
89 MHz
1
66.5 MHz
Div4
100 MHz
89 MHz
0
100 MHz
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.4 EMAC Clocking
The EMAC module sources its peripheral bus interface reference clock from PLL0_SYSCLK4 that is at a
fixed ratio of the CPU clock. The external clock requirement for EMAC varies with the interface used.
When the MII interface is active, the MII_TXCLK and MII_RXCLK signals must be provided from an
external source. When the RMII interface is active, the RMII 50 MHz reference clock is sourced either
from an external clock on the RMII_MHZ_50_CLK pin or from PLL0_SYSCLK7 (as shown in Figure 6-5).
The PINMUX15_3_0 bits in the pin multiplexing control 15 register (PINMUX15) of the System
Configuration Module control this clock selection:
• PINMUX15_3_0 = 0: enables sourcing of the 50 MHz reference clock from an external source on the
RMII_MHZ_50_CLK pin.
• PINMUX15_3_0 = 8h: enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7. Also,
PLL0_SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin.
Table 6-7 shows example PLL register settings and the resulting PLL0_SYSCLK7 frequencies based on
the OSCIN reference clock frequency of 25 MHz.
Figure 6-5. EMAC Clocking Diagram
On Chip
PLL Controller 0
LPSC
EMAC
SYSCLK4
SYSCLK7
50 MHz Reference Clock
PINMUX15[3:0]
1000 0000
3-State
0000 1000
RMII_MHZ_50_CLK
Signal
NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of
50 MHz +/-50 ppm.
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Table 6-7. EMAC Reference Clock Frequencies
OSCIN
Frequency
PLL Multiplier
Register Setting
Multiplier
Frequency
Post Divider
Mode (1)
POSTDIV Output
Frequency
PLLDIV7
Register
Setting
PLL0_SYSCLK7
25
24
600 MHz
Div2
300 MHz
5
50 MHz
Div3
200 MHz
3
50 MHz
Div4
150 MHz
2
50 MHz
Div2
225 MHz
Div3
150 MHz
Div4
112.5 MHz
25
(1)
(2)
118
18
450 MHz
Not Applicable (2)
2
50 MHz
Not Applicable (2)
See Section 6.2 for explanation of POSTDIV divider modes.
Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7.
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6.3.5 uPP Clocking
Figure 6-6 displays the clock connections for the uPP module. The uPP subsystem requires a module
clock to drive its internal logic and a transmit clock to drive I/O signals in transmit mode. The module clock
is always sourced by PLL0_SYSCLK2. The transmit clock is sourced by three different clocks:
PLL0_SYSCLK2 (default), PLL1_SYSCLK2, or the externally driven UPP_2xTXCLK pin. The transmit
clock source is selected by the UPP_TX_CLKSRC and ASYNC3_CLKSRC bits in the chip configuration 3
register (CFGCHIP3) of the System Configuration Module. Table 6-8 lists the register values that select
each of the three possible clock sources.
Regardless of the source, the uPP transmit clock speed cannot exceed the uPP module clock speed. The
module clock speed must be greater than or equal to the transmit clock speed.
Figure 6-6. uPP Clocking Diagram
Module
Clock
LPSC
PLL0_SYSCLK2
CFGCHIP3[UPP_TX_CLKSRC]
uPP
PLL0_SYSCLK2
0
0
1
PLL1_SYSCLK2
Transmit
Clock
1
CFGCHIP3[ASYNC3_CLKSRC]
UPP_2xTXCLK pin
Table 6-8. uPP Transmit Clock Selection
CFGCHIP3.UPP_TX_CLKSRC bit
CFGCHIP3.ASYNC3_CLKSRC bit
uPP Transmit Clock Source
0
0
PLL0_SYSCLK2
0
1
PLL1_SYSCLK2
1
x
UPP_2xTXCLK pin
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6.3.6 McASP Clocking
As shown in Figure 6-7, the McASP peripheral requires multiple clock sources. Internally, the module
clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC
bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module.
The transmit and receive clocks are sourced internally or externally by configuring the McASP clock
control registers ACLKRCTL, AHCLKRCTL, ACLKXCTL, and AHCLKXCTL. If an external clock is driven
into a high-frequency master clock (AHCLKX or AHCLKR), the McASP module allows for a mixed clock
mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the highfrequency master clock through a programmable divider.
When the internal clock source option is selected, the transmit and receive clocks are derived from the
PLL0_AUXCLK clock through programmable dividers.
Figure 6-7. McASP Clocking Diagram
On Chip
CFGCHIP3[ASYNC3_CLKSRC]
PLL0_SYSCLK2
0
PLL1_SYSCLK2
1
LPSC
Module
Clock
McASP0
PLL0_AUXCLK
TX/RX
Reference
Clock
Clock
Generator
Frame Sync
Generator
ACLKX
AHCLKX
AFSX
AFSR
ACLKR
AHCLKR
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6.3.7 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
The peripherals can be divided into the following groups, depending upon their clock requirements, as
shown in Table 6-9.
Table 6-9. Peripherals
Peripherals
Contained
within Group
Source of Peripheral Clock
RTC
—
Peripheral Group
Peripheral Group Definition
RTC
Operates off of a dedicated 32 kHz
crystal oscillator.
Fixed-Frequency Peripherals
As the name suggests, fixedTimer64P0/P1
frequency peripherals have a fixedI2C0
frequency. They are fed the
AUXCLK directly from the oscillator
input.
—
Synchronous peripherals have their
frequencies derived from the CPU
clock frequency. The peripheral
system clock frequency changes
accordingly, if the PLL0 frequency
changes. Most synchronous
peripherals have internal dividers
so they can generate their required
clock frequencies.
MMC/SDs
PLL0_SYSCLK2
HPI
PLL0_SYSCLK2
UART0
PLL0_SYSCLK2
GPIO
PLL0_SYSCLK4
Asynchronous peripherals are not
required to operate at a fixed ratio
of the CPU clock.
eCAPs
ASYNC3
eHRPWMs
ASYNC3
UART1/2
ASYNC3
Timer64P2/P3
ASYNC3
EMIFA
DIV_4P5 or PLL0_SYSCLK3
DDR2/mDDR
PLL1_SYSCLK1 or
PLL1 Direct Output
McASP0
ASYNC3 or
Peripheral Serial Clock
McBSPs
ASYNC3 or
Peripheral Serial Clock
SPI0
PLL0_SYSCLK2 or
Peripheral Serial Clock
SPI1
ASYNC3 or
Peripheral Serial Clock
I2C1
PLL0_SYSCLK4 or
Peripheral Serial Clock
EMAC
PLL0_SYSCLK4 or
RMII_MHZ_50_CLK
uPP
PLL0_SYSCLK2 or
Peripheral Serial Clock
VPIF
PLL0_SYSCLK2 or
Peripheral Serial Clock
USB2.0
USB_REFCLKIN or AUXCLK
Synchronous Peripherals
Asynchronous Peripherals
Synchronous/Asynchronous
Peripherals
Synchronous/asynchronous
peripherals can be run with either
internally generated synchronous
clocks, or externally generated
asynchronous clocks.
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Chapter 7
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Phase-Locked Loop Controller (PLLC)
Topic
7.1
7.2
7.3
122
...........................................................................................................................
Page
Introduction ..................................................................................................... 123
PLL Controllers ................................................................................................ 123
PLLC Registers ................................................................................................ 128
Phase-Locked Loop Controller (PLLC)
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7.1
Introduction
This device has two phase-locked loop (PLL) controllers, PLLC0 and PLLC1. These PLL controllers
provide clock signals to most of the components of the device through various clock dividers.
Both PLL0 and PLL1 provide the following:
• Glitch-free transitions when clock settings are changed
• Domain clock alignment
• Clock gating
• PLL power-down
The clock outputs generated by the PLL controllers are:
• Domain clocks: PLL0_SYSCLK[1-7] and PLL1_SYSCLK[1-3]
• Auxiliary clock (PLL0_AUXCLK) from the PLLC0 reference clock source
Dividers that can be used for the PLL controllers are:
• Pre-PLL divider: PREDIV
• Post-PLL divider: POSTDIV
• SYSCLK divider: D1, …, Dn
Various other control signals supported are:
• PLL multiplier: PLLM
• Software-programmable PLL bypass: PLLEN
7.2
PLL Controllers
PLL0 and PLL1 share the same internal architecture so they also share the same approach for mode
configuration.
PLL0 provides the primary system clock to the device. PLL0 operations are software programmable
through the PLL controller 0 (PLLC0) registers.
PLL1 provides the reference clocks to various peripherals (including DDR2/mDDR) and may generate
clocks that are asynchronous to the PLL0 clocks. PLL1 operations are software programmable through the
PLL controller 1 (PLLC1) registers.
Figure 7-1 shows the PLLC0 and PLLC1 architecture.
The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register (PLLM).
The PLLM defaults to a multiplier value of 13h at power-up, which results in a PLL multiplier of 20×. The
PLL0 and PLL1 output clocks may be divided-down for slower device operation using the PLL post-divider
control register (POSTDIV). The POSTDIV has a default value of /2, but may be modified through
software (using the RATIO field in POSTDIV) to achieve lower device operation frequencies. The default
PLLM and POSTDIV settings produce a 300-MHz PLL output clock when given a 30-MHz clock source.
At power-up, PLL0 and PLL1 are powered-down/disabled and must be powered-up by software through
the PLLPWRDN bit in their respective PLL control register (PLLCTL). Before each PLL completes the
power-up and frequency-lock sequence, the system operates in bypass mode by default and the system
clock (OSCIN) is provided directly from an input reference clock (square wave or internal oscillator)
selected by the CLKMODE bit in PLLCTL. After the power-up and frequency-lock sequences are
complete, software can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
The PLL controller registers are listed in Section 7.3.
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Figure 7-1. PLLC Structure
PLL Controller 0
PLLCTL[EXTCLKSRC]
PLL1_SYSCLK3
PLLCTL[CLKMODE]
1
PLLCTL[PLLEN]
0
OSCIN
0
Square
Wave
1
Crystal
0
PREDIV
POSTDIV
PLL
1
PLLM
DEEPSLEEP
Enable
PLLDIV1 (/1)
SYSCLK1
PLLDIV2 (/2)
SYSCLK2
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
PLLDIV3 (/3)
SYSCLK3
EMIFA
Internal
Clock
Source
0
1
DIV4.5
CFGCHIP3[EMA_CLKSRC]
AUXCLK
PLLC0 OBSCLK
(CLKOUT Pin)
DIV4.5
OSCDIV
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
PLLC1 OBSCLK
OCSEL[OCSRC]
PLLCTL[PLLEN]
0
POSTDIV
PLL
1
PLLM
SYSCLK1
SYSCLK2
SYSCLK3
PLL Controller 1
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV1 (/1)
SYSCLK1
DDR2/mDDR
Internal
Clock
Source
14h
17h
18h
19h
OSCDIV
PLLC1 OBSCLK
OCSEL[OCSRC]
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7.2.1 Device Clock Generation
The PLL controllers (PLLC0 and PLLC1) manage the clock ratios, alignment, and gating for the device
system clocks. Various PLL mode attributes such as pre-division, multiplier, and post-division are software
programmable through the PLL controller registers. Additionally, the reset controller in PLLC0 manages
reset propagation through the device, clock alignment, and test points.
The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the
SYSCLK dividers can handle. The POSTDIV stage should be programmed to keep the input to the
SYSCLK dividers within operating limits. See the device datasheet for the maximum operating
frequencies.
PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. These
reference clocks are summarized in Table 7-1. Some output clock dividers require fixed values so that
clock ratios between various device components are maintained regardless of PLL or bypass frequency.
Table 7-1. System PLLC Output Clocks
Output Clock
Used by
Default Ratio
(relative to PLLn_SYSCLK1)
Fixed Clock
Ratio
PLLC0 (1)
PLL0_SYSCLK1
DSP
/1
Yes
PLL0_SYSCLK2
DSP ports, UART0, EDMA, SPI0, MMC/SDs,
VPIF, uPP, DDR2/mDDR (bus ports),
USB2.0, HPI, PRU
/2
Yes
PLL0_SYSCLK3 (2)
EMIFA
/3
No
PLL0_SYSCLK4
System configuration (SYSCFG), GPIO,
PLLCs, PSCs, I2C1, EMAC/MDIO
/4
Yes
PLL0_SYSCLK5
Not used
/3
No
PLL0_SYSCLK6
Not used
/1
Yes
PLL0_SYSCLK7
EMAC RMII clock
PLL0_AUXCLK
I2C0, Timer64P0/P1, RTC, USB2.0 PHY,
McASP0 serial clock
PLL0_OBSCLK
Observation clock (OBSCLK) source
/6
No
PLL bypass clock
No
Pin configurable
No
PLLC1
PLL1_SYSCLK1
DDR2/mDDR PHY
/1 or disabled
No
PLL1_SYSCLK2 (3)
ECAPs, UART1/2, Timer64P2/3, eHRPWMs,
McBSPs, McASP0, SPI1 (all these modules
use PLL0_SYSCLK2 by default)
/2 or disabled
No
PLL1_SYSCLK3 (4)
PLL0 input reference clock
(not configured by default)
/3 or disabled
No
(1)
(2)
(3)
(4)
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
PLLC0 supports an additional post-divider value of /4.5 that can be used for EMIFA clock generation. When this /4.5 value is
used, the resulting clock will not have a 50% duty cycle. Instead, the duty cycle will be 44.4%. The EMIFA uses PLL0_SYSCLK3
by default, but can be configured to use a /4.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the
EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG)
module.
The ASYNC3 modules use PLL0_SYSCLK2 by default, but all these modules can be configured as a group to use
PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system
configuration (SYSCFG) module.
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit
in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN.
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7.2.2 Steps for Programming the PLLs
Note that there is a lock mechanism implemented to protect the PLL controller registers. See
Section 7.2.2.1 for information on unlocking the PLL controller registers.
Refer to the appropriate subsection on how to program the PLL clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 7.2.2.2.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 7.2.2.3 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and only the SYSCLK dividers will be updated,
follow the sequence in Section 7.2.2.4.
Note that the PLLs are powered down after a Power-on Reset (POR). The PLLs are not powered down
after a Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the
PLLDIVx registers are reset to default values.
7.2.2.1
Locking/Unlocking PLL Register Access
A lock mechanism is implemented on the device to prevent inadvertent writes to the PLL controller
registers. This provides protection from stopping modules when the module clocks are disabled. For
example, the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally
disabled.
The PLL lock bits are located within the system configuration (SYSCFG) module:
• When set, the PLL_MASTER_LOCK bit in the chip configuration 0 register (CFGCHIP0) locks PLLC0.
• When set, the PLL1_MASTER_LOCK bit in the chip configuration 3 register (CFGCHIP3) locks PLLC1.
Because the SYSCFG module has its own lock mechanism, the SYSCFG module must be unlocked first
by writing to the KICK0R and KICK1R registers before the PLL lock bits can be cleared. Like the KICK
registers, the PLL lock bits can only be modified while in a privileged mode. See the System Configuration
(SYSCFG) Module chapter for information on privilege type and the KICK0R and KICK1R registers.
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 and the PLL1_MASTER_LOCK bit in
CFGCHIP3 default to unlocked after reset, so the following procedure is only required if the
PLLs have been locked (set to 1).
To modify the PLL controller registers, use the following sequence:
1. Write the correct key values to KICK0R and KICK1R registers.
2. Clear the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
3. Configure the desired PLL controller register values.
4. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
5. Write an incorrect key value to the KICK0R and KICK1R registers.
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7.2.2.2
Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Program the CLKMODE bit in PLLC0 PLLCTL.
2. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
3. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 (brings PLL out of power-down mode).
5. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
6. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
8. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
7.2.2.3
Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), perform the following
procedure to change the PLL multiplier:
1. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
2. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
3. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
4. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
5. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
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Changing SYSCLK Dividers
If the PLL is already operating at the desired multiplier mode, perform the following procedure to change
the SYSCLK divider values:
1. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress).
2. Program the RATIO field in PLLDIVn.
3. Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7.3
PLLC Registers
Table 7-2 lists the memory-mapped registers for the PLLC0 and Table 7-3 lists the memory-mapped
registers for the PLLC1.
Table 7-2. PLL Controller 0 (PLLC0) Registers
Address
Acronym
Register Description
01C1 1000h
REVID
PLLC0 Revision Identification Register
Section 7.3.1
01C1 10E4h
RSTYPE
PLLC0 Reset Type Status Register
Section 7.3.3
01C1 10E8h
RSCTRL
PLLC0 Reset Control Register
Section 7.3.4
01C1 1100h
PLLCTL
PLLC0 Control Register
Section 7.3.5
01C1 1104h
OCSEL
PLLC0 OBSCLK Select Register
Section 7.3.7
01C1 1110h
PLLM
PLLC0 PLL Multiplier Control Register
Section 7.3.9
01C1 1114h
PREDIV
PLLC0 Pre-Divider Control Register
Section 7.3.10
01C1 1118h
PLLDIV1
PLLC0 Divider 1 Register
Section 7.3.11
01C1 111Ch
PLLDIV2
PLLC0 Divider 2 Register
Section 7.3.13
01C1 1120h
PLLDIV3
PLLC0 Divider 3 Register
Section 7.3.15
01C1 1124h
OSCDIV
PLLC0 Oscillator Divider 1 Register
Section 7.3.21
01C1 1128h
POSTDIV
PLLC0 PLL Post-Divider Control Register
Section 7.3.23
01C1 1138h
PLLCMD
PLLC0 PLL Controller Command Register
Section 7.3.24
01C1 113Ch
PLLSTAT
PLLC0 PLL Controller Status Register
Section 7.3.25
01C1 1140h
ALNCTL
PLLC0 Clock Align Control Register
Section 7.3.26
01C1 1144h
DCHANGE
PLLC0 PLLDIV Ratio Change Status Register
Section 7.3.28
01C1 1148h
CKEN
PLLC0 Clock Enable Control Register
Section 7.3.30
01C1 114Ch
CKSTAT
PLLC0 Clock Status Register
Section 7.3.32
01C1 1150h
SYSTAT
PLLC0 SYSCLK Status Register
Section 7.3.34
01C1 1160h
PLLDIV4
PLLC0 Divider 4 Register
Section 7.3.17
01C1 1164h
PLLDIV5
PLLC0 Divider 5 Register
Section 7.3.18
01C1 1168h
PLLDIV6
PLLC0 Divider 6 Register
Section 7.3.19
01C1 116Ch
PLLDIV7
PLLC0 Divider 7 Register
Section 7.3.20
01C1 11F0h
EMUCNT0
PLLC0 Emulation Performance Counter 0 Register
Section 7.3.36
01C1 11F4h
EMUCNT1
PLLC0 Emulation Performance Counter 1 Register
Section 7.3.37
128 Phase-Locked Loop Controller (PLLC)
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Table 7-3. PLL Controller 1 (PLLC1) Registers
Address
Acronym
Register Description
01E1 A000h
REVID
PLLC1 Revision Identification Register
Section 7.3.2
Section
01E1 A100h
PLLCTL
PLLC1 Control Register
Section 7.3.6
01E1 A104h
OCSEL
PLLC1 OBSCLK Select Register
Section 7.3.8
01E1 A110h
PLLM
PLLC1 PLL Multiplier Control Register
Section 7.3.9
01E1 A118h
PLLDIV1
PLLC1 Divider 1 Register
Section 7.3.12
01E1 A11Ch
PLLDIV2
PLLC1 Divider 2 Register
Section 7.3.14
01E1 A120h
PLLDIV3
PLLC1 Divider 3 Register
Section 7.3.16
01E1 A124h
OSCDIV
PLLC1 Oscillator Divider 1 Register
Section 7.3.22
01E1 A128h
POSTDIV
PLLC1 PLL Post-Divider Control Register
Section 7.3.23
01E1 A138h
PLLCMD
PLLC1 PLL Controller Command Register
Section 7.3.24
01E1 A13Ch
PLLSTAT
PLLC1 PLL Controller Status Register
Section 7.3.25
01E1 A140h
ALNCTL
PLLC1 Clock Align Control Register
Section 7.3.27
01E1 A144h
DCHANGE
PLLC1 PLLDIV Ratio Change Status Register
Section 7.3.29
01E1 A148h
CKEN
PLLC1 Clock Enable Control Register
Section 7.3.31
01E1 A14Ch
CKSTAT
PLLC1 Clock Status Register
Section 7.3.33
01E1 A150h
SYSTAT
PLLC1 SYSCLK Status Register
Section 7.3.35
01E1 A1F0h
EMUCNT0
PLLC1 Emulation Performance Counter 0 Register
Section 7.3.36
01E1 A1F4h
EMUCNT1
PLLC1 Emulation Performance Counter 1 Register
Section 7.3.37
7.3.1 PLLC0 Revision Identification Register (REVID)
The PLLC0 revision identification register (REVID) is shown in Figure 7-2 and described in Table 7-4.
Figure 7-2. PLLC0 Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -n = value after reset
Table 7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 3C00h
Description
Peripheral revision ID for PLLC0.
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7.3.2 PLLC1 Revision Identification Register (REVID)
The PLLC1 revision identification register (REVID) is shown in Figure 7-3 and described in Table 7-5.
Figure 7-3. PLLC1 Revision Identification Register (REVID)
31
0
REV
R-4481 4400h
LEGEND: R = Read only; -n = value after reset
Table 7-5. PLLC1 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 4400h
Description
Peripheral revision ID for PLLC1.
7.3.3 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) latches the cause of the last reset. If multiple reset sources are
asserted simultaneously, RSTYPE records the reset source that deasserts last. If multiple reset sources
are asserted and deasserted simultaneously, RSTYPE latches the highest priority reset source. RSTYPE
is shown in Figure 7-4 and described in Table 7-6.
Figure 7-4. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
PLLSWRST
XWRST
POR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-3
2
1
0
130
Field
Reserved
Value
0
PLLSWRST
Description
Reserved
PLL software reset.
0
PLL soft reset was not the last reset to occur.
1
PLL soft was the last reset to occur.
XWRST
External warm reset.
0
External warm reset was not the last reset to occur.
1
External warm reset was the last reset to occur.
POR
Power on reset.
0
Power On Reset (POR) was not the last reset to occur.
1
Power On Reset (POR) was the last reset to occur.
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7.3.4 PLLC0 Reset Control Register (RSCTRL)
The reset control register (RSCTRL) allows the device to perform a software-initiated reset. Before writing
to the SWRST bit, the register must be unlocked by writing the key value of 5A69h to the KEY bit field.
The KEY bit field reads back as Ch when the register is unlocked; any other key value is invalid and
indicates that the register is locked. Any write to the register following a successful unlock relocks the
register. RSCTRL is shown in Figure 7-5 and described in Table 7-7.
Figure 7-5. Reset Control Register (RSCTRL)
31
17
16
Reserved
SWRST
R-0
R/W-1
15
0
KEY
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7. Reset Control Register (RSCTRL) Field Descriptions
Bit
31-17
16
15-0
Field
Reserved
Value
0
SWRST
KEY
Description
Reserved
PLL software reset. Register must be unlocked before writing to this bit. Writes are possible only
when qualified with a valid key.
0
In software reset
1
Not in software reset
0-FFFFh
RSCTRL unlock key. Key used to enable writes to RSCTRL.
3h
Register is locked when read value is 3h.
Ch
Register is unlocked when read value is Ch.
5A69h
RSCTRL unlock key
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7.3.5 PLLC0 Control Register (PLLCTL)
The PLLC0 control register (PLLCTL) is shown in Figure 7-6 and described in Table 7-8.
Figure 7-6. PLLC0 Control Register (PLLCTL)
31
16
Reserved
R-0
15
10
7
6
9
8
Reserved
EXTCLKSRC
CLKMODE
R-0
R/W-0
R/W-0
5
4
3
2
1
0
Reserved
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-8. PLLC0 Control Register (PLLCTL) Field Descriptions
Bit
31-10
9
8
Reserved
Value
0
EXTCLKSRC
Description
Reserved
External clock source selection.
0
Use OSCIN for the PLL bypass clock.
1
Use PLL1_SYSCLK3 for the PLL bypass clock.
CLKMODE
Reference clock selection.
0
Internal oscillator (crystal)
1
Square wave
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
7-6
2
Reserved
1
PLLPWRDN
0
132
Field
PLL0 reset.
0
PLL0 reset is asserted.
1
PLL0 reset is not asserted.
0
Reserved
PLL0 power-down.
0
PLL0 is operating.
1
PLL0 is powered-down.
PLLEN
PLL0 mode enables.
0
PLL0 is in bypass mode.
1
PLL0 mode is enabled, not bypassed.
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7.3.6 PLLC1 Control Register (PLLCTL)
The PLLC1 control register (PLLCTL) is shown in Figure 7-7 and described in Table 7-9.
Figure 7-7. PLLC1 Control Register (PLLCTL)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
6
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-9. PLLC1 Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
2
Reserved
1
PLLPWRDN
0
PLL1 reset.
0
PLL1 reset is asserted.
1
PLL1 reset is not asserted.
0
Reserved
PLL1 power-down.
0
PLL1 is operating.
1
PLL1 is powered-down.
PLLEN
PLL1 mode enables.
0
PLL1 is in bypass mode.
1
PLL1 mode is enabled, not bypassed.
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7.3.7 PLLC0 OBSCLK Select Register (OCSEL)
The PLLC0 OBSCLK select register (OCSEL) controls which clock is output on the CLKOUT pin so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 7-8 and described in Table 7-10.
Figure 7-8. PLLC0 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-10. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC0 OBSCLK source. Output on CLKOUT pin.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
134
17h
PLL0_SYSCLK1
18h
PLL0_SYSCLK2
19h
PLL0_SYSCLK3
1Ah
PLL0_SYSCLK4
1Bh
PLL0_SYSCLK5
1Ch
PLL0_SYSCLK6
1Dh
PLL0_SYSCLK7
1Eh
PLLC1 OBSCLK
1Fh
Disabled
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7.3.8 PLLC1 OBSCLK Select Register (OCSEL)
The PLLC1 OBSCLK select register (OCSEL) controls which clock is output on PLLC1 OBSCLK so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 7-9 and described in Table 7-11.
Figure 7-9. PLLC1 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC1 OBSCLK source.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL1_SYSCLK1
18h
PLL1_SYSCLK2
19h
PLL1_SYSCLK3
1A-1Fh Reserved
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7.3.9 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 7-10 and described in Table 7-12.
Figure 7-10. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PLLM
Value
0
0-1Fh
Description
Reserved
PLL multiplier select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV)
The PLLC0 pre-divider control register (PREDIV) is shown in Figure 7-11 and described in Table 7-13.
Figure 7-11. PLLC0 Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-14
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
136
Value
0
Description
Reserved
PLLC0 pre-divider enable.
0
PLLC0 pre-divider is disabled. Clock output from the PREDIV stage is disabled.
1
PLLC0 pre-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
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7.3.11 PLLC0 Divider 1 Register (PLLDIV1)
The PLLC0 divider 1 register (PLLDIV1) controls the divider for PLL0_SYSCLK1. PLLDIV1 is shown in
Figure 7-12 and described in Table 7-14.
Figure 7-12. PLLC0 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-14. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.3.12 PLLC1 Divider 1 Register (PLLDIV1)
The PLLC1 divider 1 register (PLLDIV1) controls the divider for PLL1_SYSCLK1. PLLDIV1 is shown in
Figure 7-13 and described in Table 7-15.
Figure 7-13. PLLC1 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
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7.3.13 PLLC0 Divider 2 Register (PLLDIV2)
The PLLC0 divider 2 register (PLLDIV2) controls the divider for PLL0_SYSCLK2. PLLDIV2 is shown in
Figure 7-14 and described in Table 7-16.
Figure 7-14. PLLC0 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
7.3.14 PLLC1 Divider 2 Register (PLLDIV2)
The PLLC1 divider 2 register (PLLDIV2) controls the divider for PLL1_SYSCLK2. PLLDIV2 is shown in
Figure 7-15 and described in Table 7-17.
Figure 7-15. PLLC1 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-17. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D2EN
14-5
Reserved
4-0
RATIO
138
Value
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
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7.3.15 PLLC0 Divider 3 Register (PLLDIV3)
The PLLC0 divider 3 register (PLLDIV3) controls the divider for PLL0_SYSCLK3. PLLDIV3 is shown in
Figure 7-16 and described in Table 7-18.
Figure 7-16. PLLC0 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-18. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
7.3.16 PLLC1 Divider 3 Register (PLLDIV3)
The PLLC1 divider 3 register (PLLDIV3) controls the divider for PLL1_SYSCLK3. PLLDIV3 is shown in
Figure 7-17 and described in Table 7-19.
Figure 7-17. PLLC1 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-0
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-19. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
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7.3.17 PLLC0 Divider 4 Register (PLLDIV4)
The PLLC0 divider 4 register (PLLDIV4) controls the divider for PLL0_SYSCLK4. PLLDIV4 is shown
inFigure 7-18 and described in Table 7-20.
Figure 7-18. PLLC0 Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-20. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D4EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 4 enable.
0
Divider 4 is disabled.
1
Divider 4 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4).
7.3.18 PLLC0 Divider 5 Register (PLLDIV5)
The PLLC0 divider 5 register (PLLDIV5) controls the divider for PLL0_SYSCLK5. PLLDIV5 is shown in
Figure 7-19 and described in Table 7-21.
Figure 7-19. PLLC0 Divider 5 Register (PLLDIV5)
31
16
Reserved
R-0
15
14
5
4
0
D5EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-21. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D5EN
14-5
Reserved
4-0
RATIO
140
Value
Description
Reserved
Divider 5 enable.
0
Divider 5 is disabled.
1
Divider 5 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
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7.3.19 PLLC0 Divider 6 Register (PLLDIV6)
The PLLC0 divider 6 register (PLLDIV6) controls the divider for PLL0_SYSCLK6. PLLDIV6 is shown in
Figure 7-20 and described in Table 7-22.
Figure 7-20. PLLC0 Divider 6 Register (PLLDIV6)
31
16
Reserved
R-0
15
14
5
4
0
D6EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-22. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D6EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 6 enable.
0
Divider 6 is disabled.
1
Divider 6 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.3.20 PLLC0 Divider 7 Register (PLLDIV7)
The PLLC0 divider 7 register (PLLDIV7) controls the divider for PLL0_SYSCLK7. PLLDIV7 is shown in
Figure 7-21 and described in Table 7-23.
Figure 7-21. PLLC0 Divider 7 Register (PLLDIV7)
31
16
Reserved
R-0
15
14
5
4
0
D7EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-23. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D7EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 7 enable.
0
Divider 7 is disabled.
1
Divider 7 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).
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7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)
The PLLC0 oscillator divider 1 register (OSCDIV) controls the divider for PLLC0 OBSCLK, dividing down
the clock selected as the PLLC0 OBSCLK source. The PLLC0 OBSCLK is connected to the CLKOUT pin.
The OSCDIV is shown in Figure 7-22 and described in Table 7-24.
Figure 7-22. PLLC0 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-24. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC0 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC0 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)
The PLLC1 oscillator divider 1 register (OSCDIV) controls the divider for PLLC1 OBSCLK, dividing down
the clock selected as the PLLC1 OBSCLK source. The PLLC1 OBSCLK signal may be selected as the
output on the CLKOUT pin. The OSCDIV is shown in Figure 7-23 and described in Table 7-25.
Figure 7-23. PLLC1 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-25. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
31-16
15
Field
Reserved
0
OD1EN
14-5
Reserved
4-0
RATIO
142
Value
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC1 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC1 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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7.3.23 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 7-24 and described in Table 7-26.
Figure 7-24. PLL Post-Divider Control Register (POSTDIV)
31
16
Reserved
R-0
15
14
5
4
0
POSTDEN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
POSTDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Post-divider enable.
0
Post-divider is disabled.
1
Post-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
7.3.24 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) contains the command bit for phase alignment. A write of
1 initiates the command; a write of 0 clears the bit, but has no effect. PLLCMD is shown in Figure 7-25
and described in Table 7-27.
Figure 7-25. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 7-27. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for phase alignment.
0
Clear bit (no effect)
1
Phase alignment
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7.3.25 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 7-26 and described in Table 7-28.
Figure 7-26. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
STABLE
Reserved
GOSTAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-28. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
144
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation. If 1, indicates GO operation is in progress.
0
GO operation is not in progress.
1
GO operation is in progress.
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7.3.26 PLLC0 Clock Align Control Register (ALNCTL)
The PLLC0 clock align control register (ALNCTL) indicates which PLL0_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 7-27 and described in Table 7-29.
Figure 7-27. PLLC0 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-3h
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-29. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
3h
ALN7
Description
Reserved
PLL0_SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN6
PLL0_SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN5
PLL0_SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN4
PLL0_SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN3
PLL0_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL0_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL0_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.3.27 PLLC1 Clock Align Control Register (ALNCTL)
The PLLC1 clock align control register (ALNCTL) indicates which PLL1_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 7-28 and described in Table 7-30.
Figure 7-28. PLLC1 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-30. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-3
2
1
0
146
Field
Reserved
Value
0
ALN3
Description
Reserved
PLL1_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL1_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL1_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC0 PLLDIV ratio change status register (DCHANGE) indicates if the PLL0_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 7-29 and described in Table 7-31.
Figure 7-29. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-31. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
0
SYS7
Description
Reserved
PLL0_SYSCLK7 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS6
PLL0_SYSCLK6 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS5
PLL0_SYSCLK5 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS4
PLL0_SYSCLK4 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS3
PLL0_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL0_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL0_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC1 PLLDIV ratio change status register (DCHANGE) indicates if the PLL1_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 7-30 and described in Table 7-32.
Figure 7-30. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-32. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-3
2
1
0
148
Field
Reserved
Value
0
SYS3
Description
Reserved
PLL1_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL1_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL1_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.3.30 PLLC0 Clock Enable Control Register (CKEN)
The PLLC0 clock enable control register (CKEN) controls the PLLC0 OBSCLK and AUXCLK clock. CKEN
is shown in Figure 7-31 and described in Table 7-33.
Figure 7-31. PLLC0 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-33. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK enable. Actual PLLC0 OBSCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 OBSCLK is disabled.
1
PLLC0 OBSCLK is enabled. For PLLC0 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC0 oscillator divider 1 register (OSCDIV) must be set to 1.
AUXEN
AUXCLK enable. Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 AUXCLK is disabled.
1
PLLC0 AUXCLK is enabled.
7.3.31 PLLC1 Clock Enable Control Register (CKEN)
The PLLC1 clock enable control register (CKEN) controls the PLLC1 OBSCLK clock. CKEN is shown in
Figure 7-32 and described in Table 7-34.
Figure 7-32. PLLC1 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-34. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK enable. Actual PLLC1 OBSCLK status is shown in the PLLC1 clock status register (CKSTAT).
0
PLLC1 OBSCLK is disabled.
1
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1.
0
Reserved
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7.3.32 PLLC0 Clock Status Register (CKSTAT)
The PLLC0 clock status register (CKSTAT) indicates the PLLC0 OBSCLK and AUXCLK on/off status. The
PLL0_SYSCLK status is shown in the PLLC0 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 7-33 and described in Table 7-35.
Figure 7-33. PLLC0 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R-1
R-1
LEGEND: R = Read only; -n = value after reset
Table 7-35. PLLC0 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
150
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK on status. PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC0 clock enable control register (CKEN).
0
PLLC0 OBSCLK is off.
1
PLLC0 OBSCLK is on.
AUXEN
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control
register (CKEN).
0
PLLC0 AUXCLK is off.
1
PLLC0 AUXCLK is on.
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7.3.33 PLLC1 Clock Status Register (CKSTAT)
The PLLC1 clock status register (CKSTAT) indicates the PLLC1 OBSCLK on/off status. The
PLL1_SYSCLK status is shown in the PLLC1 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 7-34 and described in Table 7-36.
Figure 7-34. PLLC1 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-2h
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-36. PLLC1 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK on status. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC1 clock enable control register (CKEN).
0
PLLC1 OBSCLK is off.
1
PLLC1 OBSCLK is on.
0
Reserved
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7.3.34 PLLC0 SYSCLK Status Register (SYSTAT)
The PLLC0 SYSCLK status register (SYSTAT) indicates the PLL0_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC0 PLLDIVn.
SYSTAT is shown in Figure 7-35 and described in Table 7-37.
Figure 7-35. PLLC0 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-1
7
6
5
4
3
2
1
0
Reserved
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-37. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-7
Reserved
6
SYS7ON
5
4
3
2
1
0
152
Value
3h
Description
Reserved
PLL0_SYSCLK7 on status.
0
Off
1
On
SYS6ON
PLL0_SYSCLK6 on status.
0
Off
1
On
SYS5ON
PLL0_SYSCLK5 on status.
0
Off
1
On
SYS4ON
PLL0_SYSCLK4 on status.
0
Off
1
On
SYS3ON
PLL0_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL0_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL0_SYSCLK1 on status.
0
Off
1
On
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7.3.35 PLLC1 SYSCLK Status Register (SYSTAT)
The PLLC1 SYSCLK status register (SYSTAT) indicates the PLL1_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC1 PLLDIVn.
SYSTAT is shown in Figure 7-36 and described in Table 7-38.
Figure 7-36. PLLC1 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-0
7
2
1
0
Reserved
3
SYS3ON
SYS2ON
SYS1ON
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
SYS3ON
1
0
Value
0
Description
Reserved
PLL1_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL1_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL1_SYSCLK1 on status.
0
Off
1
On
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7.3.36 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 7-37 and described in
Table 7-39. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 7-37. Emulation Performance Counter 0 Register (EMUCNT0)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-39. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit
31-0
Field
Value
COUNT
0-FFFF FFFFh
Description
Counter value for lower 64-bits.
7.3.37 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 7-38 and described in
Table 7-40. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 7-38. Emulation Performance Counter 1 Register (EMUCNT1)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit
31-0
154
Field
COUNT
Value
0-FFFF FFFFh
Description
Counter value for upper 64-bits.
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Chapter 8
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Power and Sleep Controller (PSC)
Topic
...........................................................................................................................
8.1
8.2
8.3
8.4
8.5
8.6
Introduction .....................................................................................................
Power Domain and Module Topology ..................................................................
Executing State Transitions ...............................................................................
IcePick Emulation Support in the PSC ................................................................
PSC Interrupts..................................................................................................
PSC Registers ..................................................................................................
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156
156
161
162
162
165
155
Introduction
8.1
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Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupts, a state machine for each
peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and
provides clock and reset control. Many of the operations of the PSC are transparent to user (software),
such as power on and reset control. However, the PSC module(s) also provide you with interface to
control several important power, clock and reset operations. The module level power, clock and reset
operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for DSP memories)
• Supports IcePick emulation features: power, clock and reset
8.2
Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of:
• an Always On power domain
• an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in
the DSP subsystem
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 8-1 and Table 8-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 8.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have an LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
NOTE: There are no LPSCs for peripherals in the Async2 clock domain (this includes RTC,
Timer64P0/P1, and I2C0); from a power savings stand point, clock-gating these peripherals
does not result in significant power savings.
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Table 8-1. PSC0 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_0 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3_0 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3_0 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
6-8
Not Used
—
—
—
9
UART0
AlwaysON (PD0)
SwRstDisable
—
10
Not Used
—
—
—
11
SCR1 (BR4)
AlwaysON (PD0)
Enable
Yes
12
SCR2 (BR3, BR5, BR6)
AlwaysON (PD0)
Enable
Yes
13
PRU
AlwaysON (PD0)
SwRstDisable
—
14
Not Used
—
—
—
15
DSP
PD_DSP (PD1)
Enable
—
Table 8-2. PSC1 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_1 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
Not Used
—
—
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
HPI
AlwaysON (PD0)
SwRstDisable
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
DDR2/mDDR
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 (+ McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8
Not Used
—
—
—
9
VPIF
AlwaysON (PD0)
SwRstDisable
—
10
SPI1
AlwaysON (PD0)
SwRstDisable
—
11
I2C1
AlwaysON (PD0)
SwRstDisable
—
12
UART1
AlwaysON (PD0)
SwRstDisable
—
13
UART2
AlwaysON (PD0)
SwRstDisable
—
14
McBSP0 (+ McBSP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
15
McBSP1 (+ McBSP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
16
Not Used
—
—
—
17
eHRPWM0/1
AlwaysON (PD0)
SwRstDisable
—
18
MMC/SD1
AlwaysON (PD0)
SwRstDisable
—
19
uPP
AlwaysON (PD0)
SwRstDisable
—
20
eCAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
EDMA3_1 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR F0
AlwaysON (PD0)
Enable
Yes
25
SCR F1
AlwaysON (PD0)
Enable
Yes
26
SCR F2
AlwaysON (PD0)
Enable
Yes
27
SCR F6
AlwaysON (PD0)
Enable
Yes
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Table 8-2. PSC1 Default Module Configuration (continued)
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
28
SCR F7
AlwaysON (PD0)
Enable
Yes
29
SCR F8
AlwaysON (PD0)
Enable
Yes
30-31
Not Used
—
—
—
8.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In this device, for both PSC0 and PSC1, the Always ON domain (or PD0 power domain), is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state (See details on
PDCTL register).
Additionally, for both PSC0 and PSC1, the PD1 power domains, the internal/pseudo power domain can
either be in the ON state or OFF state. Furthermore, for these power domains the transition from ON to
OFF state is further qualified by the PSC0/1.PDCTL1.PDMODE settings. The PDCTL1.PDMODE settings
determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
NOTE: Currently programming the PD1 power domain state to OFF is not supported. You should
leave both the PDCTL1.NEXT and PDCTL1.PDMODE values at default/power on reset
values.
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of
the device. There is no capability to individually remove voltage/power from the DSP power
domains .
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8.2.2 Module States
The PSC defines several possible states for a module. This various states are essentially a combination of
the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The various
module states are defined in Table 8-3.
The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in
Auto Sleep mode, it will transition back to the clock disabled state (automatically sleep) after servicing the
internal read/write access request where as in Auto Wake mode, on receiving the first internal read/write
access request, the module will permanently transition from the clock disabled to clock enabled state
(automatically wake).
When the module state is programmed to Disable, SwRstDisable, Auto Sleep or Auto Wake modes,
where in the module clocks are off/disabled, an external event or I/O request cannot enable the clocks.
For the module to appropriately respond to such external request, it would need to be reconfigured to the
Enable state.
8.2.2.1
Auto Sleep/Wake Only Configurations and Limitation
NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes. If the
module clocks need to gated/disabled for power savings, you should program the module
state to Disable. For Auto Sleep/Auto Wake Only modules, disabling the clock is not
supported and they should be kept in their default “Enable” state.
Table 8-1 and Table 8-2 each have a column to indicate whether or not the LPSC configuration for a
module is Auto Sleep/Wake Only. Modules that have a “Yes” marked for the Auto Sleep/Wake Only
column can be programmed in software to be in Enable, Auto Sleep and Auto Wake states only; that is, if
the software tries to program these modules to Disable, SyncReset, or SwRstDisable state the power
sleep controller ignores these transition requests and transitions the module state to Enable.
8.2.2.2
Local Reset
In addition to module reset, the following module can be reset using a special local reset that is also a part
of the PSC module control for resets.
• DSP: When the DSP local reset is asserted the DSP internal memories (L1P, L1D and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of DSP subsystem, as the DSP
module reset would. Local Reset is useful in cases where the DSP is in enable or disable state; since
when module is in SyncReset or SwRstDisable state the module reset is asserted, and the module
reset takes precedence over the local reset.
The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the
module that supports local reset):
1. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset.
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset.
If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted.
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Table 8-3. Module States
160
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has
its clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has
its module clock off. This state is typically used for disabling a module
clock to save power. This device is designed in full static CMOS, so when
you stop a module clock, it retains the module’s state. When the clock is
restarted, the module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it
has its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it
has its clock disabled. After initial power-on, several modules come up in
the SwRstDisable state. Generally, software is not expected to initiate this
state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it
can “automatically” transition to “Enable” state whenever there is an
internal read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re deasserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data. See Section 8.2.2.1 for
additional considerations, constraints, limitations around this mode.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from
then on (with module reset re de-asserted and module clock on), without
any software intervention. The transition from sleep to enabled state has
some cycle latency associated with it. It is not envisioned to use this mode
when peripherals are fully operational and moving data. See
Section 8.2.2.1 for additional considerations, constraints, limitations around
this mode.
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8.3
Executing State Transitions
This section describes how to execute the state transitions modules.
8.3.1 Power Domain State Transitions
This device consists of two types of domain (in each PSC controller):
• Always On domain(s)
• pseudo/RAM power domain(s)
The Always On power domains are always in the ON state when the chip is powered on. You are not
allowed to change the power domain state to OFF.
The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with
these domains (L1/L2 for PD_DSP in PSC0) so that these RAMs can run in lower power sleep modes via
the power sleep controller.
NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported;
therefore, these domains and the RAM should be left in their default power on state.
As mentioned in Section 8.2, the pseudo/RAM power domains are powered down internally,
and in this context powering down does not imply removing the core voltage from pins
externally.
8.3.2 Module State Transitions
This section describes the procedure for transitioning the module state (clock and reset control). Note that
some peripherals have special programming requirements and additional recommended steps you must
take before you can invoke the PSC module state transition. See the individual peripheral user guides for
more details. For example, the external memory controller requires that you first place the SDRAM
memory in self-refresh mode before you invoke the PSC module state transitions, if you want to maintain
the memory contents.
The following procedure is directly applicable for all modules that are controlled via the PSC (shown in
Table 8-1 and Table 8-2), except for the core(s). To transition the DSP module state, there are additional
system considerations and constraints that you should be aware of. These system considerations and the
procedure for transitioning the DSP module state are described in details in the Power Management
chapter.
NOTE: In the following procedure, x is 0 for modules in PD0 (Power Domain 0 or Always On
domain) and x is 1 for modules in PD1 (Power Domain 1). See Table 8-1 and Table 8-2 for
power domain associations.
The procedure for module state transitions is:
1. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), Enable (3h), Auto
Sleep (4h) or Auto Wake (5h).
NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[x] bit in PTCMD in a later step.
3. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
after the GOSTAT[x] bit in PTSTAT is cleared to 0.
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IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the
state of power domains and modules. This IcePick support only applies to the following module:
• DSP [MDCTL15]
In particular, Table 8-4 shows IcePick emulation commands recognized by the PSC.
Table 8-4. IcePick Emulation Commands
Power On and
Enable Features
Power On and Enable Descriptions
Reset Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the
module’s local reset.
Force Power
Allows emulation to force the power domain into
an on state. Not applicable as AlwaysOn power
domain is always on.
Wait Reset
Allows emulation to keep local
reset asserted for an extended
period of time after software
initiates local reset de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block
software initiated local and
module resets.
NOTE: When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in
MDCTLn, as set by software.
8.5
PSC Interrupts
The PSC has an interrupt that is tied to the core interrupt controller. This interrupt is named PSCINT in the
interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.
8.5.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Power Domain Emulation Event (applies to pseudo/RAM power domain only)
• Module State Emulation event
• Module Local Reset Emulation event
These interrupt events are summarized in Table 8-5 and described in more detail in this section.
Table 8-5. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Enable Bit
Interrupt Condition
PDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the power domain state
MDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the module state
MDCTLn
EMURSTIE
Interrupt occurs when the emulation tries to alter the module’s local reset
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the userprogrammed state in the NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the
modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed.
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8.5.1.1
Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTATn. In particular, a power
domain emulation event occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
• When force power is asserted by emulation and power domain is not already in the on state
• When force active is asserted by emulation and power domain is not already in the on state
NOTE:
8.5.1.2
Putting the pseudo/RAM power domain associated with the DSP (PD_DSP) to the off state
currently is not supported.
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTATn). In particular, a module state emulation event
occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
• When force active is asserted by emulation and module is not already in the enable state
8.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTATn). In particular, a module local reset emulation
event occurs under the following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset
• When wait reset is asserted by emulation
• When block reset is asserted by emulation and software attempts to change the state of local reset
8.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support, as specified in
Section 8.4).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled in the DSP interrupt controller. For details on the DSP
interrupt controller, see the DSP Subsystem chapter.
The PSC interrupt status bits are:
• For DSP:
– The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).
– The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain
associated with DSP memories.
The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.
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The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register. When set, this bit forces the
PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set)
when the ALLEV bit in the INTEVAL is set to 1, the PSC interrupt is re-asserted to the interrupt controller.
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do
not miss any PSC interrupts.
See Section 8.6 for a description of the PSC registers.
8.5.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt:
1. Set the EMUIHBIE bit in PDCTLn, the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the
interrupt events that you want.
NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event
becomes active.
2. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. To
interrupt the CPU, PSCn_ALLINT must be enabled in the device interrupt controller. See the DSP
Subsystem chapter for more information on interrupts.
The CPU enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the P[n] bit in PERRPR, and/or the M[n] bit in MERRPR0, the M[n] bit in MERRPR1, to
determine the source of the interrupt(s).
2. For each active event that you want to service:
(a) Read the event status bits in PDSTATn and MDSTATn, depending on the status bits read in the
previous step to determine the event that caused the interrupt.
(b) Service the interrupt as required by your application.
(c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status.
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt
controller, if there are still any active interrupt events.
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8.6
PSC Registers
Table 8-6 lists the memory-mapped registers for the PSC0 and Table 8-7 lists the memory-mapped
registers for the PSC1.
Table 8-6. Power and Sleep Controller 0 (PSC0) Registers
Address
Acronym
Register Description
01C1 0000h
REVID
Revision Identification Register
Section 8.6.1
Section
01C1 0018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01C1 0040h
MERRPR0
Module Error Pending Register 0 (module 0-15)
Section 8.6.3
01C1 0050h
MERRCR0
Module Error Clear Register 0 (module 0-15)
Section 8.6.5
01C1 0060h
PERRPR
Power Error Pending Register
Section 8.6.7
01C1 0068h
PERRCR
Power Error Clear Register
Section 8.6.8
01C1 0120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01C1 0128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01C1 0200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01C1 0204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01C1 0300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01C1 0304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01C1 0400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01C1 0404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01C1 0800h01C1 083Ch
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15)
Section 8.6.17
01C1 0A00h01C1 0A3Ch
MDCTL0MDCTL15
Module Control n Register (modules 0-15)
Section 8.6.18
Table 8-7. Power and Sleep Controller 1 (PSC1) Registers
Address
Acronym
Register Description
01E2 7000h
REVID
Revision Identification Register
Section 8.6.1
01E2 7018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01E2 7040h
MERRPR0
Module Error Pending Register 0 (module 0-31)
Section 8.6.4
01E2 7050h
MERRCR0
Module Error Clear Register 0 (module 0-31)
Section 8.6.6
01E2 7060h
PERRPR
Power Error Pending Register
Section 8.6.7
01E2 7068h
PERRCR
Power Error Clear Register
Section 8.6.8
01E2 7120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01E2 7128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01E2 7200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01E2 7204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01E2 7300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01E2 7304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01E2 7400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01E2 7404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01E2 7800h01E2 787Ch
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31)
Section 8.6.17
01E2 7A00h01E2 7A7Ch
MDCTL0MDCTL31
Module Control n Register (modules 0-31)
Section 8.6.19
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8.6.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 8-1 and described in Table 8-8.
Figure 8-1. Revision Identification Register (REVID)
31
0
REV
R-4482 5A00h
LEGEND: R = Read only; -n = value after reset
Table 8-8. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4482 5A00h
Description
Peripheral revision ID.
8.6.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 8-2 and described in Table 8-9.
Figure 8-2. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 8-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
166
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt (PSCn_ALLINT).
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 8-3 and described in Table 810.
Figure 8-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31
16
Reserved
R-0
15
14
0
M[15]
Reserved
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit
31-16
15
14-0
Field
Reserved
Value
0
M[15]
Reserved
Description
Reserved
Module interrupt status bit for module 15 (DSP).
0
Module 15 does not have an error condition.
1
Module 15 has an error condition. See the module status 15 register (MDSTAT15) for the error
condition.
0
Reserved
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 8-4.
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 8-5 and described in Table 8-11.
Figure 8-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31
16
Reserved
R-0
15
14
0
M[15]
Reserved
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit
31-16
15
14-0
Field
Reserved
Value
0
M[15]
Reserved
Description
Reserved
Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 15 register (MDSTAT15).
0
A write of 0 has no effect.
1
A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15.
0
Reserved
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 8-6.
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 8-7 and described in Table 8-12.
Figure 8-7. Power Error Pending Register (PERRPR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
RAM/Pseudo (PD1) power domain interrupt status.
0
RAM/Pseudo power domain does not have an error condition.
1
RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0
Reserved
8.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 8-8 and described in Table 8-13.
Figure 8-8. Power Error Clear Register (PERRCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0
A write of 0 has no effect.
1
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0
Reserved
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8.6.9 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 8-9 and described in Table 814.
Figure 8-9. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-14. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
170
Field
Reserved
Value
0
GO[1]
Description
Reserved
RAM/Pseudo (PD1) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
PDCTL.NEXT for this domain, and MDCTL.NEXT for all the modules residing on this domain). If any of
the NEXT fields are not matching the corresponding current state (PDSTAT.STATE, MDSTAT.STATE),
the PSC will transition those respective domain/modules to the new NEXT state.
GO[0]
Always ON (PD0) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching
the corresponding current state (MDSTAT.STATE), the PSC will transition those respective
domain/modules to the new NEXT state.
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8.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 8-10 and described in Table 815 .
Figure 8-10. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
RAM/Pseudo (PD1) power domain transition status.
0
No transition in progress.
1
RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
GOSTAT[0]
Always ON (PD0) power domain transition status.
0
No transition in progress.
1
Modules in Always ON power domain are transitioning. Always On power domain is transitioning.
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8.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 8-11 and described in Table 8-16.
Figure 8-11. Power Domain 0 Status Register (PDSTAT0)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Emulation alters domain state.
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
172
Reserved
0
POR
7-5
Description
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.12 Power Domain 1 Status Register (PDSTAT1)
The power domain 1 status register (PDSTAT1) is shown in Figure 8-12 and described in Table 8-17.
Figure 8-12. Power Domain 1 Status Register (PDSTAT1)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Reserved
Emulation alters domain state.
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.13 Power Domain 0 Control Register (PDCTL0)
The power domain 0 control register (PDCTL0) is shown in Figure 8-13 and described in Table 8-18.
Figure 8-13. Power Domain 0 Control Register (PDCTL0)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
Reserved
9
EMUIHBIE
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
0-Fh
Power down mode.
0-Eh
Reserved
Fh
11-10
Description
0
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
174
NEXT
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect
since internally this power domain always remains in the on state.
0
Power domain off.
1
Power domain on.
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8.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 8-14 and described in Table 8-19.
Figure 8-14. Power Domain 1 Control Register (PDCTL1)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
0-Fh
Core off, RAM array retention, RAM periphery off (deep sleep).
Reserved
4h
Core retention, RAM array off, RAM periphery off.
5h
Core retention, RAM array retention, RAM periphery off (deep sleep).
Reserved
8h
Core on, RAM array off, RAM periphery off.
9h
Core on, RAM array retention, RAM periphery off (deep sleep).
Ah
Core on, RAM array retention, RAM periphery off (light sleep).
Bh
Core on, RAM array retention, RAM periphery on.
Fh
EMUIHBIE
Power down mode.
Core off, RAM array off, RAM periphery off.
Ch-Eh
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
1h
6h-7h
9
Reserved
0
2h-3h
11-10
Description
0
Reserved
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
NEXT
User-desired power domain next state.
0
Power domain off.
1
Power domain on.
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8.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 8-15 and described in Table 820.
Figure 8-15. Power Domain 0 Configuration Register (PDCFG0)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
176
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.16 Power Domain 1 Configuration Register (PDCFG1)
The power domain 1 configuration register (PDCFG1) is shown in Figure 8-16 and described in Table 821.
Figure 8-16. Power Domain 1 Configuration Register (PDCFG1)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.17 Module Status n Register (MDSTATn)
The module status n register (MDSTATn) is shown in Figure 8-17 and described in Table 8-22.
Figure 8-17. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
Reserved
MCKOUT
Rsvd
MRST
LRSTDONE
LRST
Reserved
7
6
5
STATE
0
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-22. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in the module control
15 register (MDCTL15).
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL15. If you desire to
generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL15.
Emulation alters module reset. This bit applies to DSP module (module 15). This field is 0 for all
other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state. If you desire to generate a PSCINT upon this
event, you must set the EMURSTIE bit in the module control 15 register (MDCTL15).
0
Reserved
Module clock output status. Shows status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to DSP module (module 15). This field is 1 for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Module local reset status. This bit applies to DSP module (module 15).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
Module state status: indicates current module status.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
178
Reserved
0
LRSTDONE
7-6
Description
Emulation alters module state. This bit applies to DSP module (module 15). This field is 0 for all
other modules.
EMURST
15-13
9
Value
Indicates transition
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8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)
The PSC0 module control n register (MDCTLn) is shown in Figure 8-18 and described in Table 8-23.
Figure 8-18. PSC0 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
10
9
8
Reserved
11
EMUIHBIE
EMURSTIE
LRST
7
Reserved
3
2
NEXT
0
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 15
register (MDCTL15), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-11
Reserved
10
EMUIHBIE
9
8
0
Force is disabled.
1
Force is enabled.
0
Reserved
Interrupt enable for emulation alters module state. This bit applies to DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
EMURSTIE
Interrupt enable for emulation alters reset. This bit applies to DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
LRST
7-3
Reserved
2-0
NEXT
Module local reset control. This bit applies to DSP module (module 15).
0
Assert local reset
1
De-assert local reset
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn)
The PSC1 module control n register (MDCTLn) is shown in Figure 8-19 and described in Table 8-24.
Figure 8-19. PSC1 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
3
2
0
Reserved
NEXT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 15
register (MDCTL15), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-3
Reserved
2-0
NEXT
180
0
Force is disabled.
1
Force is enabled.
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
Power and Sleep Controller (PSC)
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Chapter 9
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Power Management
Topic
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
...........................................................................................................................
Introduction .....................................................................................................
Power Consumption Overview ...........................................................................
PSC and PLLC Overview ...................................................................................
Features ..........................................................................................................
Clock Management ...........................................................................................
DSP Sleep Mode Management............................................................................
RTC-Only Mode ................................................................................................
Dynamic Voltage and Frequency Scaling (DVFS)..................................................
Deep Sleep Mode ..............................................................................................
Additional Peripheral Power Management Considerations.....................................
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182
182
182
183
184
185
187
187
189
192
181
Introduction
9.1
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Introduction
Power management is an important aspect for most embedded applications. For several applications and
target markets, there may be a specific power budget and requirements to minimize power consumption
for both power supply sizing and battery life considerations. Additionally, lower power consumption results
in more optimal and efficient designs from cost, design, and energy perspectives. This device has several
means of managing the power consumption. This chapter discusses the various power management
features.
9.2
Power Consumption Overview
Power consumed by semiconductor devices has two components: dynamic and static. This can be shown
as:
Ptotal = Pdynamic + Pstatic
The dynamic power is the power consumed to perform work when the device is in active modes (clocks
applied, busses, and I/O switching), that is, analog circuits changing states. The dynamic power is defined
by:
Pdynamic = Capacitance × Voltage2 × Frequency
From the above formula, the dynamic power scales with the clock frequency (device/module frequency for
core operations and switching frequency for I/O). Dynamic power can be reduced by controlling the clocks
in such a way as to either operate at a clock setting just high enough to complete the required operation in
the required timeline or to run at a clock setting until the work is complete and then drastically reduce the
clock frequency or cut off the clocks until additional work must be performed.
In the formula, the dynamic power varies with the voltage squared, so the voltage of operations has
significant impact on overall power consumption and, thus, on the battery life. Dynamic power can be
reduced by scaling the operating voltage, when the performance requirements are not that high and the
device can be operated at a corresponding lower frequency.
The capacitance is the capacitance of the switching nodes, or the load capacitances on the switching I/O
pins.
The static power, as the name suggests, is independent of the switching frequency of the logic. It can be
shown as:
Pstatic = f(leakage current)
It is essentially a function of the “leakage”, or the power consumed by the logic when it is not switching or
is not performing any work. Leakage current is dependent mostly on the manufacturing process used, the
size of the die, etc. Leakage current is unavoidable while power is applied and scales roughly with the
operating junction temperatures. Leakage power can only be avoided by removing power completely from
a device or subsystem. The static power consumption plays a significant role in the Standby Modes (when
the application is not running and in a dormant state) and plays an important role in the battery life for
portable applications, etc.
9.3
PSC and PLLC Overview
The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling
of the clocks to the core and various peripheral modules. The PSC provides a granular support to turn
on/off clocks on a module by module basis. Similarly, the two PLL controllers (PLLC0 and PLLC1) play an
important role in device and module clock generation, and manage the frequency scaling operations for
the device. Together these modules play a significant role in managing the clocks from a power
management feature standpoint. For detailed information on the PSC, see the Power and Sleep Controller
(PSC) chapter. For detailed information on the PLLC0 and PLLC1, see the Device Clocking chapter and
the Phase-Locked Loop Controller (PLLC) chapter.
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Features
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9.4
Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 9-1 describes the power management features.
Table 9-1. Power Management Features
Power Management
Description
Features
PLL bypass and powerdown
Both PLLs can be powered-down and run in
bypass mode when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON
Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic power consumption of the
core and I/O (if any free running I/O clocks).
DSP subsystem
sleep mode
The DSP CPU can be put in sleep (IDLE) mode.
RTC-only mode
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Dynamic Voltage and
Frequency Scaling
(DVFS)
The operating voltage and frequency of the device
can be dynamically scaled to meet the
requirements of the application.
Clock Management
Core Sleep Management
Reduces the dynamic power consumption.
Voltage Management
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Dynamic Voltage and Frequency Scaling
Reduces the dynamic power consumption of the
core and I/O as well as standby power
System/Device Sleep Management
Deep Sleep Mode
All internal clocks of the device can be turned
on/off at the OSCIN level. The deep sleep function
can be controlled externally through the
DEESLEEP pin or internally through the
RTC_ALARM pin.
Reduces the dynamic power consumption of the
core and I/O.
USB PHY power-down
The USB2.0 PHY can be powered-down.
Minimizes the USB2.0 I/O power consumption
when not in use.
DDR2/mDDR selfrefresh mode
Allows memory to retain its contents while the rest
of the system is powered down.
mDDR and DDR2 can be clock gated to reduce the
dynamic power consumption or the entire device
can be powered down to reduce the static power
consumption.
LVCMOS I/O buffer
receiver disable
LVCMOS I/O buffer receivers are disabled.
Minimizes the I/O power consumption.
Internal pull-up and pulldown resistor control
The internal pull-ups and pull-downs are
enabled/disabled by groups.
Reduces the I/O leakage power.
Peripheral I/O Power Management
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9.5
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Clock Management
9.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
NOTE: To preserve the state of the module, the module state in the PSC must be set to Disable. In
this state, the module reset is not asserted and only the module clock is turned off.
Furthermore, special consideration must be given to DSP clock on/off. The procedure to turn the core
clock on/off is further described in Section 9.6.3.
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module, when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
9.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
9.5.3 PLL Bypass and Power Down
You can bypass each PLL in this device. Bypassing the PLL sends a bypass clock instead of the PLL
VCO output (PLLOUT) to the system clocks of the PLLC. For PLLC0, the bypass clock is selected from
either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. For PLLC1, the bypass clock is always
OSCIN. The OSCIN frequency is typically, at most, up to 50 MHz.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. This can lower the
overall dynamic power consumption, which is linearly proportional to the frequency.
When the PLL controller is placed in bypass mode, the PLL retains its frequency lock. This allows you to
switch between bypass mode and PLL mode without having to wait for the PLL to relock. However,
keeping the PLL locked consumes power. You can also power-down the PLL when bypassing it to
minimize the overall power consumed by the PLL module. The advantage of bypassing the PLL without
powering it down is that you do not have to incur the PLL lock time when switching back to a normal
operating level.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
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9.6
DSP Sleep Mode Management
9.6.1 C674x DSP CPU Sleep Mode
The DSP CPU can be put in a low-power state by executing the IDLE instruction. For information on the
IDLE instruction, see the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8).
9.6.2 C674x Megamodule Sleep Mode
The IDLE instruction is used as part of the procedure for shutting down the entire C674x megamodule, by
the power-down controller (PDC) module. In shutting down the entire C674x megamodule, the PDC can
internally clock gate off the following components of the megamodule and internal memories of the DSP
subsystem:
• C674x CPU
• Level 1 Program Memory Controller (PMC)
• Level 1 Data Memory Controller (DMC)
• Level 2 Unified Memory Controller (UMC)
• Extended Memory Controller (EMC)
• L1P Memory
• L1D Memory
• L2 Memory
Putting the entire C674x megamodule into the low-power sleep mode is typically more useful and saves a
lot more power, as compared to just executing the IDLE instruction to put only the CPU in idle mode.
For information on putting the C674x megamodule in the low-power mode using the PDC, see the
TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
9.6.3 C674x Megamodule Clock ON/OFF
The C674x megamodule can clock gate its own components to save power. Additional power saving can
be achieved by stopping the clock sourced (PLL output) to the C674x megamodule by programming the
power and sleep controller (PSC) module to place the megamodule in the Disable state. The DSP cannot
perform this programming task on its own, because the DSP will not be able to complete the PSC
programming sequence if its clock source is gated in the middle of the process.
If additional power saving is desired (more then just power savings obtained by using the power down
controller), then you can choose to disable the clock to the DSP using the PSC. The ARM is responsible
for programming the PSC to disable the clock going to the C674x megamodule at the root level (stopping
PLL0_SYSCLK1 at the PLL output). By clock gating the megamodule at the root, this enables saving
additional clock tree power (for the path from the PLL to the megamodule boundary). The ARM is also
responsible for programming the PSC to enable the C674x megamodule.
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9.6.3.1
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C674x Megamodule Clock OFF
The software must be structured such that no peripheral is allowed to access the DSP resources before
disabling the DSP clocks. The DSP must check for the completion of all its master peripheral initiated
requests (that is, IDMA, MDMA, EDMA, cache operations, etc.).
1. The ARM stops all masters from accessing the DSP and DSP memory.
2. The ARM polls all masters for write-completion status (or wait n number of cycles, if the transfer
completion status is not implemented).
3. The DSP must have the power-down controller interrupt PDC_INT (DSP interrupt #118) enabled and
the PDC interrupt service routine (ISR) set up before the Host initiates the following DSP clock
shutdown procedure.
(a) Initiate the DSP clock off sequence by issuing the DSP clock stop command (PSC DISABLE
Command) to the DSP subsystem by writing a 2h to the NEXT bit field in the DSP local power
sleep controller (LPSC) module control register (PSC0.MDCTL15).
(b) Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP
module. This generates the PDC_INT interrupt to the DSP.
(c) Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT)
for power transition sequence completion. The GOSTAT[1] bit transitions to 0 when the DSP
executes the IDLE instruction from inside its interrupt service routine (ISR).
(d) Check (poll for 2h) the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15)
indicating the DSP clock stop sequence completion (STATE: Disable).
The following sequence should be executed by the DSP within the PDC interrupt ISR:
1. Check for completion of all DSP master requests (the DSP polls transfer completion statuses of all
Master peripherals).
2. Enable the interrupt to be used as “wake-up” interrupt (for example, one of the CHIPSIG interrupts
controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module
chapter—CHIPSIG[2], CHIPSIG[3], or CHIPSIG[4]/NMI interrupt) that will be used to wake-up the DSP
during the DSP clock-on sequence.
NOTE: The power-down command register (PDCCMD) in the power-down controller (PDC) can only
be written while the DSP is in Supervisor mode.
3. Write a 0001 5555h to PDCCMD.
4. Execute the IDLE instruction.
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9.6.3.2
C674x Megamodule Clock ON
The C674x megamodule defaults to the Enable state; therefore, the DSP subsystem clock is on, and the
following sequence is typically not needed. This clock on sequence is only required to wake-up the DSP, if
the ARM put the DSP in a clock off state. Perform the following sequence for the ARM to enable clocks to
the DSP:
1. Wait for the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) to clear to
0. You must wait for the power domain to finish any previously initiated transitions before initiating a
new transition.
2. Write a 3h to the NEXT bit field in the DSP local power sleep controller (LPSC) module control register
(PSC0.MDCTL15) to prepare the DSP module for an enable transition.
3. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP module.
4. Check (poll for 0) the GOSTAT[1] bit in PSC0.PTSTAT for power transition sequence completion. The
domain is only safely in the new state after the GOSTAT[1] bit is cleared to 0.
5. Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
NOTE: This only applies if you are transitioning from the Disable state. If previously in the Disable
state, a wake-up interrupt must be triggered in order to wake the DSP. This example
assumes that the DSP enabled this interrupt before entering its IDLE state. See the DSP
Subsystem chapter for more information on DSP interrupts.
For the ARM to wake the DSP if transitioning from the Disable state, trigger a DSP interrupt that has
previously been configured as a wake-up interrupt.
9.7
RTC-Only Mode
In real-time clock (RTC)-only mode, the RTC is powered on and the rest of the device is completely
powered off (all supplies except the RTC supply are removed). In this mode, the RTC is fully functional
and keeps track of date, hours, minutes, and seconds. In this mode, the overall power consumption would
be significantly lower, as voltage from the rest of the core and I/O logic can be completely removed,
eliminating most of the active and static power of the device, except for what is consumed by the RTC
module, running at 32 kHz.
NOTE: To put the device in RTC-only mode, there is no software control sequence. You can put the
device in the RTC-only mode by removing the power supply from all core and I/O logic,
except for the RTC core logic supply (RTC_CVDD). During wake up, all power sequencing
requirements described in the device-specific data manual must be followed.
Some limitations apply in the RTC-only mode. First, the RTC_ALARM pin is not available as an option for
use as a control to signal an external power supply to reapply power to the rest of the device. This is
because the RTC_ALARM pin is powered by the I/O supply that is powered down in RTC-only mode.
Second, in RTC-only mode, only the RTC register contents are preserved, all other internal memory and
register contents are lost. Mobile DDR and DDR2 contents can be preserved through the use of selfrefresh (see Section 9.9.2). However, software must be in place to restore the context of the device, for
example, reinitialize internal registers, setup cache memory configurations, interrupt vectors, etc.
9.8
Dynamic Voltage and Frequency Scaling (DVFS)
Dynamic voltage and frequency scaling (DVFS) consists of minimizing the idle time of the system. The
DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a task to be
performed in the required amount of time. This reduces the total power consumption of the device while
still meeting task requirements. DVFS requires control over the clock frequency and the operating voltage
of the device elements. By intelligently switching these elements to their optimal operating points, it is
possible to minimize the power consumption of the device for a given task.
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For reasons related to the device (clock architecture, process, etc.), DVFS is used only for a few discrete
steps, not over a continuum of voltage and frequency values. Each step, or operating performance point
(OPP), is composed of a voltage and frequency pair. For an OPP, the frequency corresponds to the
maximum frequency allowed at a voltage, or reciprocally; the voltage corresponds to the minimum voltage
allowed for a frequency. See your device data manual for a list of the OPPs supported by the device.
When applying DVFS, a processor or system always runs at the lowest OPP that meets the performance
requirement at a given time. You determine the optimal OPP for a given task and then switch to that OPP
to save power.
9.8.1 Frequency Scaling Considerations
The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1).
Through a series of multipliers and dividers you can change the frequencies of various clocks throughout
the device. See the Device Clocking chapter for information on the clock architecture of the device and
see the Phase-Locked Loop Controller (PLLC) chapter for information on the PLL controllers. A few things
must be noted when changing the various internal frequencies of the device:
• Changing the SYSCLK frequency
The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier. A series of dividers
divide PLLOUT to generate the various device SYSCLKs.
To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK
divider ratio. When changing the PLL multiplier, you must put the PLL controller in bypass mode while
the PLL multiplier value is modified and a lock on the new frequency is reached. The lock time is given
in the device data manual. When changing the divider ratios it is not required to put the PLL controller
in bypass mode.
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the
PLL. However, the SYSCLK frequency will depend solely on the divider ratios used.
• SYSCLK domain fixed ratios
Certain SYSCLK domains need to operate at a fixed ratio with respect to the CPU clock. Care should
be taken to ensure that these fixed ratios are maintained. For additional details, see the Device
Clocking chapter.
• PLLC0 bypass clock
When switching the PLL multiplier, the PLL controller must be placed in bypass mode. Bypassing the
PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of
the PLL controller.
For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or
PLL1_SYSCLK3. For PLLC1, the bypass clock is always OSCIN. The OSCIN frequency is typically, at
most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity.
It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved
bandwidth during frequency scaling transitions. For this reason, the PLLC0 bypass clock can be set to
PLL1_SYSCLK3. This selection is made through the EXTCLKSRC bit in the PLLCTL register of
PLLC0.
• Peripheral immunity from CPU clock frequency changes
Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency.
The PLL0_AUXCLK is derived from OSCIN.
Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2.
Furthermore, PLL0_SYSCLK2 must always be /2 of the CPU clock frequency. To keep these
peripherals immune from changes in PLL0 frequency (such as when the CPU frequency is modified),
you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. PLL1 is mainly used to
clock the DDR2/mDDR memory controller.
When peripherals are immune to changes in the CPU clock frequency, their internal clock dividers do
not have to be adjusted for changes in their input clock frequencies.
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9.8.2 Voltage Scaling Considerations
The operating voltage of the device must be totally controlled through mechanisms outside the device. I2C
ports on the device can be used to communicate with external power management chips. A few things
must be noted when changing the operating voltage of the device:
• Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating
performance point (OPP) transitions. See the device data manual for ramp rate specifications.
• Switching to a lower voltage: When switching to a lower voltage, the maximum operating frequency
changes. Care must be taken such that the maximum operating frequency supported at the new
voltage is not violated. For this reason, it is recommended to change the operating frequency before
switching the operating voltage.
9.9
Deep Sleep Mode
This device supports a Deep Sleep mode where all device clocks are stopped and the on-chip oscillator is
shut down to save power. Registers and memory contents are preserved, thus, upon recovery, the
program may continue from where it left off with minimal overhead involved.
The Deep Sleep mode is initiated when the DEEPSLEEP pin is driven low. The device wakes up from
Deep Sleep mode when the DEEPSLEEP pin is driven high. The DEEPSLEEP pin can be driven by an
external controller or it can be driven internally by the real-time clock (RTC). The RTC method allows for
automatic wake-up at a programmed time.
NOTE: Due to pin multiplexing, the DEEPSLEEP pin can only be driven by an external controller or
its internal real-time clock (RTC). The DEEPSLEEP pin cannot be driven by both an external
controller and its internal real-time clock at the same time.
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
9.9.1.1
Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep mode if an external signal is used to wake-up the
device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 9.10.1).
3. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
4. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
5. Configure the DEEPSLEEP pin as input-only using the PINMUX0_31_28 bits in the PINMUX0 register
in the System Configuration (SYSCFG) Module chapter.
6. The external controller should drive the DEEPSLEEP pin high (not in Deep Sleep).
7. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
9. Begin polling the SLEEPCOMPLETE bit until it is set to 1. This bit is set once the device is woken up
from Deep Sleep mode.
10. The external controller drives the DEEPSLEEP pin low to initiate Deep Sleep mode.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
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Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if an external signal is used to wake-up the
device:
1. The external controller drives the DEEPSLEEP pin high.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 7.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
9.9.2.1
Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep state if the RTC is used to wake-up the device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 9.10.1).
3. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
4. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
5. Configure the desired wake-up time as an alarm in the RTC.
6. Configure the DEEPSLEEP/RTC_ALARM pin to output RTC_ALARM using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. The pin is driven low
since the alarm has not yet occurred.
7. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
Also, the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.2.2
Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if the RTC is used to wake-up the device:
1. The RTC alarm occurs and the RTC_ALARM pin is driven high (which is internally connected to the
DEEPSLEEP pin). This causes the Deep Sleep logic to exit the Deep Sleep mode.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
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3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 7.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.3 Deep Sleep Sequence
Figure 9-1 illustrates the Deep Sleep sequence:
1. Software sets the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System
Configuration (SYSCFG) Module chapter.
2. The DEEPSLEEP pin is driven low by either an external device or the RTC_ALARM pin. The Deep
Sleep mode begins.
3. The PLL controller reference clock is gated.
4. The on-chip oscillator is disabled. If the device is being clocked by an external source, this clock may
stay enabled; the power savings from turning off this clock is minimal.
5. The DEEPSLEEP pin is driven high and the on-chip oscillator is enabled.
6. The Deep Sleep counter beings counting valid clock cycles.
7. The count has reached the number specified in the SLEEPCOUNT bit field and the
SLEEPCOMPLETE bit is set. The PLL reference clock is enabled and the Deep Sleep mode ends.
8. Software clears the SLEEPENABLE bit. The SLEEPCOMPLETE bit is automatically cleared.
Figure 9-1. Deep Sleep Mode Sequence
See Note:
1
2
3
4
5
6
7
8
SLEEPENABLE
(internal)
DEEPSLEEP
CLKGATE
(internal)
PLLC Ref Clk
(internal)
OSC_GZ
(internal)
OSCIN
SLEEPCOMPLETE
(internal)
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9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking
Entering the Deep Sleep mode stops all of the clocks to the device so it is the responsibility of the
software to ensure that all peripheral accesses have been completed and peripheral interfaces
appropriately configured for clocks to stop. Therefore, before an external controller drives the
DEESPLEEP pin, a handshaking mechanism must be in place to give software time to prepare the device
for Deep Sleep mode. The implementation of the handshake mechanism is up to the system designer.
9.9.4.1
Entering Deep Sleep Mode
The following example sequence can be used to activate the Deep Sleep mode using a handshaking
mechanism between your device and an external device:
1. Clear the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter to 0. The DEEPSLEEP pin has no effect until software running on the
device sets this bit.
2. Configure the GP0[8]/DEEPSLEEP/RTC_ALARM pin to output GP0[8] using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. When the pin is
configured for GPIO functionality, the internal DEEPSLEEP signal is still driven by the value on the pin.
3. Configure the GP0[8] pin to generate interrupts on the falling edge of the GPIO signal.
4. An external device drives the GP0[8] pin low.
5. Software prepares the device for Deep Sleep mode.
6. Set the SLEEPENABLE bit in DEEPSLEEP to 1. The Deep Sleep mode is immediately started and all
device clocks are stopped. Also, the SLEEPCOMPLETE bit is automatically cleared.
9.9.4.2
Exiting Deep Sleep Mode
To exit the Deep Sleep mode, follow this sequence:
1. An external device drives the GP0[8] pin high.
2. The device exits the Deep Sleep mode. When the SLEEPCOUNT delay is complete, the Deep Sleep
logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register
(DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.
9.10 Additional Peripheral Power Management Considerations
This section lists additional power management features and considerations that might be part of other
chip-level or peripheral logic, apart from the features supported by the core, PLL controller (PLLC), and
power and sleep controller (PSC).
9.10.1 USB PHY Power Down Control
The USB modules can be clock gated using the PSC; however, this does not power down/clock gate the
PHY logic. You can put the USB2.0 PHY and OTG module in the lowest power state, when not in use, by
writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the Chip Configuration 2 Register
(CFGCHIP2) in the System Configuration (SYSCFG) Module chapter.
9.10.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode
The DDR2/mDDR memory controller supports different methods for reducing its power consumption
including self-refresh mode, power-down mode, and clock gating. Additionally, the DDR2/mDDR memory
controller DLL, PHY, and the receivers at the I/O pins can be disabled. Even if the PHY is active, the
receivers can be configured to disable whenever writes are in progress and the receivers are not needed.
Self-refresh mode can be used to preserve the contents of DDR2/mDDR memory when the DDR2/mDDR
memory controller is clock gated or when the device is placed in RTC-only mode. However, in the RTConly mode, care must be taken to correctly take the DDR2/mDDR out of self-refresh mode.
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NOTE: To preserve the contents of the external memory while the DDR2/mDDR memory controller
is clock gated, its self-refresh mode must be enabled before the DDR2/mDDR memory
controller clock is turned off.
In RTC-only mode, all portions of the device except for the RTC are powered down, including the
DDR2/mDDR memory controller. During power-up, the DDR2/mDDR memory controller defaults to its
reset state. When the DDR2/mDDR memory controller is taken out of reset, it automatically runs its
memory initialization routine; the self-refresh state of the memory is ignored. This hardware sequence
cannot be stopped by software running on the device.
To correctly take the memory out of self-refresh after coming back from RTC-only mode, follow these
steps:
1. Before going into RTC-only mode, disconnect the DDR2/mDDR memory controller CKE output pin
from the memory; ensure the memory’s CKE input pin continues to be driven low.
2. After coming back from RTC-only mode, configure the device to the desired operating state.
3. Program the DDR2/mDDR memory controller following the normal sequence.
4. Enable the self-refresh mode of the DDR2/mDDR memory controller.
5. Connect the DDR2/mDDR memory controller CKE output pin to the memory.
6. Disable the self-refresh mode of the DDR2/mDDR memory controller.
After this sequence, the DDR2/mDDR memory controller is ready for use. Note that hardware logic is
needed to disconnect the CKE output pin from the memory and to drive the memory’s CKE input pin low.
For more details on the power management features of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.10.3 LVCMOS I/O Buffer Receiver Disable
This device supports two types of LVCMOS I/Os: 1.8V I/Os and low-static current dual-voltage I/Os that
operate at either 1.8V or 3.3V. The receivers on the LCVMOS I/Os are enabled and disabled by software
(see the RXACTIVE Control Register (RXACTIVE) in the System Configuration (SYSCFG) Module
chapter). In the event that certain receivers are not used (such as in a low-power state), they can be
disabled to conserve power.
9.10.4 Pull-Up/Pull-Down Disable
In general, you must ensure that all input pins are always pulled to a logic-high or a logic-low voltage level.
A floating input pin can consume a small amount of I/O leakage current. The I/O leakage current can be
greatly multiplied in the case of several floating inputs pins.
This device includes internal pull-up and pull-down resistors that prevent floating input pins. These internal
resistors are generally very weak and their use is intended for pins that are not connected on the board
design. For pins that are connected, external pull-up and pull-down resistors are recommended.
When an input pin is externally driven to a valid logic level, through an external pull-up resistor or by an
external device for example, it is recommended to disable the internal resistor. Opposing an internal pullup or pull-down resistor can consume a small amount of current. Internal resistors are disabled through
the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module chapter.
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System Configuration (SYSCFG) Module
Topic
10.1
10.2
10.3
10.4
10.5
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Introduction .....................................................................................................
Protection ........................................................................................................
Master Priority Control ......................................................................................
Interrupt Support ..............................................................................................
SYSCFG Registers ............................................................................................
System Configuration (SYSCFG) Module
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10.1 Introduction
The system configuration (SYSCFG) module is a system-level module containing status and top level
control logic required by the device. The system configuration module consists of a set of memorymapped status and control registers, accessible by the CPU, supporting all of the following system
features, and miscellaneous functions and operations.
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device Boot Configuration Status
• Master Priority Control
– Controls the system priority for all master peripherals (including EDMA3TC)
• Emulation Control
– Emulation suspend control for peripherals that support the feature
• Special Peripheral Status and Control
– Locking of PLL control settings
– Default burst size configuration for EDMA3 transfer controllers
– Event source selection for the eCAP peripheral input capture
– McASP0 AMUTEIN selection and clearing of AMUTE
– USB PHY Control
– Clock source selection for EMIFA and DDR2/mDDR
– HPI Control
The system configuration module controls several global operations of the device; therefore, the module
supports protection against erroneous and illegal accesses to the registers in its memory-map. The
protection mechanisms that are present in the module are:
• A special key sequence that needs to be written into a set of registers in the system configuration
module, to allow write ability to the rest of registers in the system configuration module.
• Several registers in the module are only accessible when the CPU requesting read/write access is in
privileged mode.
10.2 Protection
The SYSCFG module controls several global operations of the device; therefore, it has a protection
mechanism that prevents spurious and illegal accesses to the registers in its memory map. The protection
mechanism enables accesses to these registers only if certain conditions are met.
10.2.1 Privilege Mode Protection
The CPU supports two privilege levels: Supervisor and User. Several registers in the SYSCFG memorymap can only be accessed when the accessing host (CPU or master peripheral) is operating in privileged
mode, that is, in Supervisor mode. The registers that can only be accessed in privileged mode are listed in
Section 10.5. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for
details on privilege levels.
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10.2.2 Kicker Mechanism Protection
NOTE: The Kick registers are disabled in silicon revision 2 and later. The SYSCFG registers are
always unlocked and writes to the Kick registers have no functional effect.
The Kick registers (KICK0R and KICK1R) can only be accessed in privileged mode (the host
needs to be in Supervisor mode). Any number of accesses may be performed to the
SYSCFG module, while the module is unlocked.
The SYSCFG module remains unlocked after the unlock sequence, until locked again.
Locking the module is accomplished by writing any value other then the key values to either
KICK0R or KICK1R.
To access any registers in the SYSCFG module, it is required to follow a special sequence of writes to the
Kick registers (KICK0R and KICK1R) with correct key values. Writing the correct key value to the kick
registers unlocks the registers in the SYSCFG memory-map. In order to access the SYSCFG registers,
the following unlock sequence needs to be executed in software:
1. Write the key value of 83E7 0B13h to KICK0R.
2. Write the key value of 95A4 F1E0h to KICK1R.
After steps 1 and 2, the SYSCFG module registers are accessible and can be configured as per the
application requirements.
10.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the DSP, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or EDMA3 for
initiating the data transfer to/from them. In order to determine allowed connection between masters and
slave, each master request source must have a unique master ID (mstid) associated with it. The master ID
is shown in Table 10-1. See the device-specific data manual to determine the masters present on your
device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 10-2. Application software is expected to modify these values
to obtain the desired performance.
Table 10-1. Master IDs
Master ID
0-1
Reserved
2
DSP MDMA
3
DSP CFG
4-7
Reserved
8
PRU0
9
PRU1
10
EDMA3_0_CC0
11
EDMA3_1_CC0
12-15
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Peripheral
Reserved
16
EDMA3_0_TC0 - read
17
EDMA3_0_TC0 - write
18
EDMA3_0_TC1 - read
19
EDMA3_0_TC1 - write
20
EDMA3_1_TC0 – read
21
EDMA3_1_TC0 – write
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Table 10-1. Master IDs (continued)
Master ID
Peripheral
22-33
Reserved
34
USB2.0 CFG
35
USB2.0 DMA
36
Reserved
37
HPI
38
EMAC
39-65
Reserved
66
uPP
67
SATA
67
Reserved
68
VPIF DMA0
69
VPIF DMA1
70-255
Reserved
Table 10-2. Default Master Priority
Master
Default Priority (1)
Master Priority Register
PRU0
0
MSTPRI1
PRU1
0
MSTPRI1
EDMA3_0_TC0 (2)
0
MSTPRI1
EDMA3_0_TC1 (2)
0
MSTPRI1
DSP MDMA
(3)
2
MSTPRI0
DSP CFG (3)
2
MSTPRI0
uPP
4
MSTPRI0
EDMA3_1_TC0
(1)
(2)
(3)
(2)
4
MSTPRI1
VPIF DMA0
4
MSTPRI1
VPIF DMA1
4
MSTPRI1
EMAC
4
MSTPRI2
USB2.0 CFG
4
MSTPRI2
USB2.0 DMA
4
MSTPRI2
HPI
6
MSTPRI2
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
The priority for EDMA3_0_TC0, EDMA3_0_TC1, and EDMA3_1_TC0 is configurable through fields in the master priority 1
register (MSTPRI1), not the EDMA3CC QUEPRI register.
The priority for DSP MDMA and DSP CFG is controlled by fields in the master priority 0 register (MSTPRI0) and not
DSP.MDMAARBE.PRI (DSP Bandwidth manager module).
10.4 Interrupt Support
10.4.1 Interrupt Events and Requests
The SYSCFG module generates two interrupts: an address error interrupt (BOOTCFG_ADDR_ERR) and
a protection interrupt (BOOTCFG_PROT_ERR). The BOOTCFG_ADDR_ERR is generated when there is
an addressing violation due to an access to a non-existent location in the SYSCFG register space. The
BOOTCFG_PROT_ERR interrupt is generated when there is a protection violation of either in the defined
ranges or to the SYSCFG registers. It is required to write a value of 0 to the end of interrupt register (EOI)
after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of completion
of the SYSCFG interrupt so that the module can reliably generate subsequent interrupts.
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The transfer parameters that caused the violation are saved in the fault address register (FLTADDRR) and
the fault status register (FLTSTAT).
10.4.2 Interrupt Multiplexing
The interrupts from the SYSCFG module are combined with the interrupts from the MPU module into a
single interrupt called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt
controller.
10.4.3 Host-DSP Communication Interrupts
The SYSCFG module also has a set of registers, the chip signal register (CHIPSIG) and the chip signal
clear register (CHIPSIG_CLR), to facilitate host-to-processor communication. This is generally used to
allow an external host and the DSP to coordinate.
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other
processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller.
10.5 SYSCFG Registers
Table 10-3 lists the memory-mapped registers for the system configuration module 0 (SYSCFG0) and
Table 10-4 lists the memory-mapped registers for the system configuration module 1 (SYSCFG1). These
tables also indicate whether a particular register can be accessed only when the CPU is in privileged
mode.
Table 10-3. System Configuration Module 0 (SYSCFG0) Registers
Address
Acronym
Register Description
Access
01C1 4000h
REVID
Revision Identification Register
—
Section 10.5.1
01C1 4008h
DIEIDR0 (1)
Die Identification Register 0
—
—
01C1 400Ch
DIEIDR1 (1)
Die Identification Register 1
—
—
01C1 4010h
DIEIDR2 (1)
Die Identification Register 2
—
—
01C1 4014h
DIEIDR3
(1)
Die Identification Register 3
—
01C1 4018h
DEVIDR0
Device Identification Register 0
Privileged mode
Section 10.5.2
01C1 4020h
BOOTCFG
Boot Configuration Register
Privileged mode
Section 10.5.3
01C1 4024h
CHIPREVIDR
Chip Revision Identification Register
Privileged mode
Section 10.5.4
01C1 4038h
KICK0R
Kick 0 Register
Privileged mode
Section 10.5.5.1
01C1 403Ch
KICK1R
Kick 1 Register
Privileged mode
Section 10.5.5.2
01C1 4044h
HOST1CFG
Host 1 Configuration Register
—
01C1 40E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
Section 10.5.7.1
01C1 40E4h
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
Section 10.5.7.2
01C1 40E8h
IENSET
Interrupt Enable Register
Privileged mode
Section 10.5.7.3
01C1 40ECh
IENCLR
Interrupt Enable Clear Register
Privileged mode
Section 10.5.7.4
01C1 40F0h
EOI
End of Interrupt Register
Privileged mode
Section 10.5.7.5
01C1 40F4h
FLTADDRR
Fault Address Register
Privileged mode
Section 10.5.8.1
01C1 40F8h
FLTSTAT
Fault Status Register
—
Section 10.5.8.2
01C1 4110h
MSTPRI0
Master Priority 0 Register
Privileged mode
Section 10.5.9.1
01C1 4114h
MSTPRI1
Master Priority 1 Register
Privileged mode
Section 10.5.9.2
01C1 4118h
MSTPRI2
Master Priority 2 Register
Privileged mode
Section 10.5.9.3
01C1 4120h
PINMUX0
Pin Multiplexing Control 0 Register
Privileged mode
Section 10.5.10.1
01C1 4124h
PINMUX1
Pin Multiplexing Control 1 Register
Privileged mode
Section 10.5.10.2
01C1 4128h
PINMUX2
Pin Multiplexing Control 2 Register
Privileged mode
Section 10.5.10.3
01C1 412Ch
PINMUX3
Pin Multiplexing Control 3 Register
Privileged mode
Section 10.5.10.4
(1)
Section
—
Section 10.5.6
This register is for internal-use only.
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Table 10-3. System Configuration Module 0 (SYSCFG0) Registers (continued)
Address
Acronym
Register Description
Access
01C1 4130h
PINMUX4
Pin Multiplexing Control 4 Register
Privileged mode
Section 10.5.10.5
Section
01C1 4134h
PINMUX5
Pin Multiplexing Control 5 Register
Privileged mode
Section 10.5.10.6
01C1 4138h
PINMUX6
Pin Multiplexing Control 6 Register
Privileged mode
Section 10.5.10.7
01C1 413Ch
PINMUX7
Pin Multiplexing Control 7 Register
Privileged mode
Section 10.5.10.8
01C1 4140h
PINMUX8
Pin Multiplexing Control 8 Register
Privileged mode
Section 10.5.10.9
01C1 4144h
PINMUX9
Pin Multiplexing Control 9 Register
Privileged mode
Section 10.5.10.10
01C1 4148h
PINMUX10
Pin Multiplexing Control 10 Register
Privileged mode
Section 10.5.10.11
01C1 414Ch
PINMUX11
Pin Multiplexing Control 11 Register
Privileged mode
Section 10.5.10.12
01C1 4150h
PINMUX12
Pin Multiplexing Control 12 Register
Privileged mode
Section 10.5.10.13
01C1 4154h
PINMUX13
Pin Multiplexing Control 13 Register
Privileged mode
Section 10.5.10.14
01C1 4158h
PINMUX14
Pin Multiplexing Control 14 Register
Privileged mode
Section 10.5.10.15
01C1 415Ch
PINMUX15
Pin Multiplexing Control 15 Register
Privileged mode
Section 10.5.10.16
01C1 4160h
PINMUX16
Pin Multiplexing Control 16 Register
Privileged mode
Section 10.5.10.17
01C1 4164h
PINMUX17
Pin Multiplexing Control 17 Register
Privileged mode
Section 10.5.10.18
01C1 4168h
PINMUX18
Pin Multiplexing Control 18 Register
Privileged mode
Section 10.5.10.19
01C1 416Ch
PINMUX19
Pin Multiplexing Control 19 Register
Privileged mode
Section 10.5.10.20
01C1 4170h
SUSPSRC
Suspend Source Register
Privileged mode
Section 10.5.11
01C1 4174h
CHIPSIG
Chip Signal Register
—
Section 10.5.12
01C1 4178h
CHIPSIG_CLR
Chip Signal Clear Register
—
Section 10.5.13
01C1 417Ch
CFGCHIP0
Chip Configuration 0 Register
Privileged mode
Section 10.5.14
01C1 4180h
CFGCHIP1
Chip Configuration 1 Register
Privileged mode
Section 10.5.15
01C1 4184h
CFGCHIP2
Chip Configuration 2 Register
Privileged mode
Section 10.5.16
01C1 4188h
CFGCHIP3
Chip Configuration 3 Register
Privileged mode
Section 10.5.17
01C1 418Ch
CFGCHIP4
Chip Configuration 4 Register
Privileged mode
Section 10.5.18
Table 10-4. System Configuration Module 1 (SYSCFG1) Registers
Address
Acronym
Register Description
Access
01E2 C000h
VTPIO_CTL
VTP I/O Control Register
Privileged mode
Section 10.5.19
01E2 C004h
DDR_SLEW
DDR Slew Register
Privileged mode
Section 10.5.20
01E2 C008h
DEEPSLEEP
Deep Sleep Register
Privileged mode
Section 10.5.21
01E2 C00Ch
PUPD_ENA
Pullup/Pulldown Enable Register
Privileged mode
Section 10.5.22
01E2 C010h
PUPD_SEL
Pullup/Pulldown Selection Register
Privileged mode
Section 10.5.23
01E2 C014h
RXACTIVE
RXACTIVE Control Register
Privileged mode
Section 10.5.24
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10.5.1 Revision Identification Register (REVID)
The revision identification register (REVID) provides the revision information for the SYSCFG module. The
REVID is shown in Figure 10-1 and described in Table 10-5.
Figure 10-1. Revision Identification Register (REVID)
31
0
REV
R-4E84 0102h
LEGEND: R = Read only; -n = value after reset
Table 10-5. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E84 0102h
Description
Revision ID. Revision information for the SYSCFG module.
10.5.2 Device Identification Register 0 (DEVIDR0)
The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID
device. Software can use this register to determine the version of the device on which it is executing. The
DEVIDR0 is shown in Figure 10-2 and described in Table 10-6.
Figure 10-2. Device Identification Register 0 (DEVIDR0)
31
0
DEVID0
R-1B7D 102Fh
LEGEND: R = Read only; -n = value after reset
Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions
Bit
31-0
200
Field
DEVID0
Value
1B7D 102Fh
Description
Device identification.
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10.5.3 Boot Configuration Register (BOOTCFG)
The device boot and configuration settings are latched at device reset, and captured in the boot
configuration register (BOOTCFG). See your device-specific data manual and the Boot Considerations
chapter for details on boot and configuration settings. The BOOTCFG is shown in Figure 10-3 and
described in Table 10-7.
Figure 10-3. Boot Configuration Register (BOOTCFG)
31
16
Reserved
R-0
15
0
BOOTMODE
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-7. Boot Configuration Register (BOOTCFG) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
BOOTMODE
0
Description
Reserved
0-FFFFh
Boot Mode. This reflects the state of the boot mode pins.
10.5.4 Chip Revision Identification Register (CHIPREVIDR)
The chip revision identification register (CHIPREVIDR) provides the software-readable silicon revision
information for the device. The CHIPREVID is shown in Figure 10-4 and described in Table 10-8.
Figure 10-4. Chip Revision Identification Register (CHIPREVIDR)
31
16
Reserved
R-x
15
6
5
0
Reserved
CHIPREVID
R-x
R-4h
LEGEND: R = Read only; -n = value after reset; x = value is indeterminate after reset
Table 10-8. Chip Revision Identification Register (CHIPREVIDR) Field Descriptions
Bit
Field
31-6
Reserved
5-0
CHIPREVID
Value
0
Description
Reserved
Identifies silicon revision of device.
0-3h
4h
Older silicon revision
Silicon revision 2.2
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10.5.5 Kick Registers (KICK0R-KICK1R)
NOTE: The kick registers are disabled in silicon revision 2 and later. The SYSCFG registers are
always unlocked and writes to the kick registers have no functional effect.
The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of
the modules memory-mapped registers. At power-on reset, none of the SYSCFG module registers are
writeable (they are readable). To allow writing to the registers in the module, it is required to “unlock” the
registers by writing to two memory-mapped registers in the SYSCFG module, Kick0 and Kick1, with exact
data values. Once these values are written, then all the registers in the SYSCFG module that are
writeable can be written to. See Section 10.2.2 for the exact key values and sequence of steps. Writing
any other data value to either of these kick registers will cause the memory mapped registers to be
“locked” again and block out any write accesses to registers in the SYSCFG module.
10.5.5.1 Kick 0 Register (KICK0R)
The KICK0R is shown in Figure 10-5 and described in Table 10-9.
Figure 10-5. Kick 0 Register (KICK0R)
31
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-9. Kick 0 Register (KICK0R) Field Descriptions
Bit
Field
Value
31-0
KICK0
0-FFFF FFFFh
Description
KICK0R allows writing to unlock the kick0 data. The written data must be 83E7 0B13h to unlock
this register. It must be written before writing to the kick1 register. Writing any other value will lock
the other MMRs.
10.5.5.2 Kick 1 Register (KICK1R)
The KICK1R is shown in Figure 10-6 and described in Table 10-10.
Figure 10-6. Kick 1 Register (KICK1R)
31
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-10. Kick 1 Register (KICK1R) Field Descriptions
Bit
Field
Value
31-0
KICK1
0-FFFF FFFFh
202
Description
KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written
before writing to the kick1 register. Writing any other value will lock the other MMRs.
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10.5.6 Host 1 Configuration Register (HOST1CFG)
The host 1 configuration register (HOST1CFG) provides information on the DSP boot address value at
power-on reset. The boot address defaults to 0070 0000h (DSP ROM) on power-up. The address field is
read/writeable after reset and can be modified to allow execution from an alternate location after a module
level or local reset on the DSP. The HOST1CFG is shown in Figure 10-7 and described in Table 10-11.
Figure 10-7. Host 1 Configuration Register (HOST1CFG)
31
16
DSP_ISTP_RST_VAL
R/W-0070h
15
10
9
0
DSP_ISTP_RST_VAL
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions
Bit
Field
31-10 DSP_ISTP_RST_VAL
9-0
Reserved
Value
0-3F FFFFh
0
Description
DSP boot address vector.
Reserved
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10.5.7 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
10.5.7.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 10-8 and described in
Table 10-12.
Figure 10-8. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
204
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
PROTERR
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
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10.5.7.2 Interrupt Enable Status/Clear Register (IENSTAT)
The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows
clearing of the interrupt status. The IENSTAT is shown in Figure 10-9 and described in Table 10-13.
Figure 10-9. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
PROTERR
Protection violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
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10.5.7.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 10-10 and described in Table 10-14.
Figure 10-10. Interrupt Enable Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-14. Interrupt Enable Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
PROTERR_EN
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
10.5.7.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 10-11 and described in Table 10-15.
Figure 10-11. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
206
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
PROTERR_CLR
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
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10.5.7.5 End of Interrupt Register (EOI)
The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of
the SYSCFG interrupt (for address/protection violation). It is required to write a value of 0 to the EOI
register after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of
completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts.
The EOI is shown in Figure 10-12 and described in Table 10-16.
Figure 10-12. End of Interrupt Register (EOI)
31
16
Reserved
R-0
15
8
7
0
Reserved
EOIVECT
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 10-16. End of Interrupt Register (EOI) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
EOIVECT
0-FFh
Description
Reserved. Always read 0.
EOI vector value. Write the interrupt distribution value of the chip.
10.5.8 Fault Registers
The fault registers are a group of registers responsible for capturing the details on the faulty
(address/protection violation errors) accesses, such as address and type of error.
10.5.8.1 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) captures the address of the first transfer that causes the address
or memory violation error. The FLTADDRR is shown in Figure 10-13 and described in Table 10-17.
Figure 10-13. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
Field
FLTADDR
Value
0-FFFF FFFFh
Description
Fault address for the first fault transfer.
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10.5.8.2 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous
transaction. This includes things like the master id for the master that caused the address/memory
violation error, details on whether it is a user or supervisor level read/write or execute fault. The FLTSTAT
is shown in Figure 10-14 and described in Table 10-18.
Figure 10-14. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
ID
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-18. Fault Status Register (FLTSTAT) Field Descriptions
Field
Value
Description
31-24
Bit
ID
0-FFh
Transfer ID of the first fault transfer.
23-16
MSTID
0-FFh
Master ID of the first fault transfer.
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
0
0-Fh
0
Privilege ID of the first fault transfer.
Reserved. Always read 0
Fault type of first fault transfer.
0
No transfer fault
1h
User execute fault
2h
User write fault
3h
Reserved
4h
User read fault
5h-7h
8h
9h-Fh
10h
11h-1Fh
20h
21h-3Fh
208
Reserved. Always read 0
Reserved
Supervisor execute fault
Reserved
Supervisor write fault
Reserved
Supervisor read fault
Reserved
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10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)
10.5.9.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 10-15 and described in Table 10-19.
Figure 10-15. Master Priority 0 Register (MSTPRI0)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
UPP
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
DSP_CFG
Rsvd
DSP_MDMA
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-19. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
UPP
0-7h
15
Reserved
0
14-12
DSP_CFG
0-7h
11
Reserved
0
10-8
DSP_MDMA
0-7h
uPP port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
DSP CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
DSP DMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Always read as 0.
6-4
Reserved
2h
Reserved. Write the default value when modifying this register.
3
Reserved
0
Reserved. Always read as 0.
2-0
Reserved
2h
Reserved. Write the default value when modifying this register.
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10.5.9.2 Master Priority 1 Register (MSTPRI1)
The master priority 1 register (MSTPRI1) is shown in Figure 10-16 and described in Table 10-20.
Figure 10-16. Master Priority 1 Register (MSTPRI1)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
VPIF_DMA_1
Rsvd
VPIF_DMA_0
Rsvd
Reserved
Rsvd
EDMA31TC0
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
EDMA30TC1
Rsvd
EDMA30TC0
Rsvd
PRU1
Rsvd
PRU0
R/W-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-20. Master Priority 1 Register (MSTPRI1) Field Descriptions
Bit
Field
31
Reserved
30-28
27
26-24
VPIF_DMA_1
Reserved
VPIF_DMA_0
Value
0
0-7h
0
0-7h
Description
Reserved. Write the default value when modifying this register.
VPIF DMA1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
VPIF DMA0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
15
14-12
11
10-8
7
6-4
3
2-0
210
EDMA31TC0
Reserved
EDMA30TC1
Reserved
EDMA30TC0
Reserved
PRU1
Reserved
PRU0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
EDMA3_1_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
EDMA3_0_TC1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
EDMA3_0_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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10.5.9.3 Master Priority 2 Register (MSTPRI2)
The master priority 2 register (MSTPRI2) is shown in Figure 10-17 and described in Table 10-21.
Figure 10-17. Master Priority 2 Register (MSTPRI2)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
UHPI
Rsvd
Reserved
R/W-0
R/W-5h
R/W-0
R/W-4h
R/W-0
R/W-6h
R/W-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
USB0CDMA
Rsvd
USB0CFG
Rsvd
Reserved
Rsvd
EMAC
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-0
R/W-0
R/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-21. Master Priority 2 Register (MSTPRI2) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
5h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
UHPI
0-7h
HPI port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
USB0CDMA
0-7h
11
Reserved
0
10-8
USB0CFG
0-7h
USB0 (USB2.0) CDMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
USB0 (USB2.0) CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Write the default value when modifying this register.
2-0
EMAC
0-7h
EMAC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the
smallest possible package. On the device, pin multiplexing can be controlled on a pin by pin basis. This is
done by the pin multiplexing registers (PINMUX0-PINMUX19). Each pin that is multiplexed with several
different functions has a corresponding 4-bit field in PINMUXn. Pin multiplexing selects which of several
peripheral pin functions control the pins I/O buffer output data and output enable values only. Note that the
input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers
have no effect on input from a pin. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used. Detailed information about the pin
multiplexing and control is covered in the device-specific data manual. Access to the pin multiplexing utility
is available in OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility Application Report
(SPRAB63).
10.5.10.1 Pin Multiplexing Control 0 Register (PINMUX0)
Figure 10-18. Pin Multiplexing Control 0 Register (PINMUX0)
31
28
27
24
23
20
19
16
PINMUX0_31_28
PINMUX0_27_24
PINMUX0_23_20
PINMUX0_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX0_15_12
PINMUX0_11_8
PINMUX0_7_4
PINMUX0_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
Bit
Field
31-28
Value
PINMUX0_31_28
RTC_ALARM/UART2_CTS/GP0[8]/DEEPSLEEP Control
0
Selects Function DEEPSLEEP
I
1h
Reserved
X
2h
Selects Function RTC_ALARM
O
3h
Reserved
X
4h
Selects Function UART2_CTS
I
5h-7h
8h
9h-Fh
27-24
PINMUX0_27_24
X
Selects Function GP0[8]
I/O
Reserved
X
AMUTE/PRU0_R30[16]/UART2_RTS/GP0[9]/PRU0_R31[16] Control
Selects Function PRU0_R31[16]
1h
Selects Function AMUTE
I/O
2h
Selects Function PRU0_R30[16]
O
3h
Reserved
X
4h
Selects Function UART2_RTS
O
Reserved
X
8h
9h-Fh
212
Reserved
0
5h-7h
(1)
Type (1)
Description
I
Selects Function GP0[9]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit
23-20
Field
Value
PINMUX0_23_20
AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10]/PRU0_R31[17] Control
0
Selects Function PRU0_R31[17]
1h
Selects Function AHCLKX
2h
Selects Function USB_REFCLKIN
I
3h
Reserved
X
4h
Selects Function UART1_CTS
I
Reserved
X
5h-7h
8h
9h-Fh
19-16
PINMUX0_19_16
Reserved
X
1h
Selects Function AHCLKR
I/O
2h
Selects Function PRU0_R30[18]
O
3h
Reserved
X
4h
Selects Function UART1_RTS
O
PINMUX0_15_12
I
Reserved
X
Selects Function GP0[11]
I/O
Reserved
X
AFSX/GP0[12]/PRU0_R31[19] Control
0
Selects Function PRU0_R31[19]
1h
Selects Function AFSX
2h-7h
8h
9h-Fh
PINMUX0_11_8
I
I/O
Reserved
X
Selects Function GP0[12]
I/O
Reserved
X
AFSR/GP0[13]/PRU0_R31[20] Control
0
Selects Function PRU0_R31[20]
1h
Selects Function AFSR
2h-7h
8h
9h-Fh
PINMUX0_7_4
I
I/O
Reserved
X
Selects Function GP0[13]
I/O
Reserved
X
ACLKX/PRU0_R30[19]/GP0[14]/PRU0_R31[21] Control
0
Selects Function PRU0_R31[21]
1h
Selects Function ACLKX
2h-3h
4h
5h-7h
8h
9h-Fh
3-0
I/O
Selects Function PRU0_R31[18]
9h-Fh
7-4
Selects Function GP0[10]
0
8h
11-8
I
I/O
AHCLKR/PRU0_R30[18]/UART1_RTS/GP0[11]/PRU0_R31[18] Control
5h-7h
15-12
Type (1)
Description
PINMUX0_3_0
I
I/O
Reserved
X
Selects Function PRU0_R30[19]
O
Reserved
X
Selects Function GP0[14]
I/O
Reserved
X
ACLKR/PRU0_R30[20]/GP0[15]/PRU0_R31[22] Control
0
Selects Function PRU0_R31[22]
1h
Selects Function ACLKR
2h-3h
4h
5h-7h
8h
9h-Fh
I
I/O
Reserved
X
Selects Function PRU0_R30[20]
O
Reserved
X
Selects Function GP0[15]
I/O
Reserved
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10.5.10.2 Pin Multiplexing Control 1 Register (PINMUX1)
Figure 10-19. Pin Multiplexing Control 1 Register (PINMUX1)
31
28
27
24
23
20
19
16
PINMUX1_31_28
PINMUX1_27_24
PINMUX1_23_20
PINMUX1_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX1_15_12
PINMUX1_11_8
PINMUX1_7_4
PINMUX1_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
Bit
Field
31-28
Value
PINMUX1_31_28
AXR8/CLKS1/ECAP1_APWM1/GP0[0]/PRU0_R31[8] Control
0
Selects Function PRU0_R31[8]
1h
Selects Function AXR8
2h
Selects Function CLKS1
I
3h
Reserved
X
4h
Selects Function ECAP1_APWM1
5h-7h
8h
9h-Fh
27-24
PINMUX1_27_24
Selects Function GP0[0]
I/O
Reserved
X
Pin is 3-stated.
Selects Function AXR9
I/O
2h
Selects Function DX1
O
PINMUX1_23_20
Z
Reserved
X
Selects Function GP0[1]
I/O
Reserved
X
AXR10/DR1/GP0[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR10
2h
Selects Function DR1
3h-7h
8h
9h-Fh
PINMUX1_19_16
Z
I/O
I
Reserved
X
Selects Function GP0[2]
I/O
Reserved
X
AXR11/FSX1/GP0[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR11
I/O
2h
Selects Function FSX1
I/O
3h-7h
8h
9h-Fh
214
X
0
9h-Fh
(1)
I/O
Reserved
1h
8h
19-16
I
I/O
AXR9/DX1/GP0[1] Control
3h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP0[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX1_15_12
AXR12/FSR1/GP0[4] Control
0
Pin is 3-stated.
1h
Selects Function AXR12
I/O
2h
Selects Function FSR1
I/O
3h-7h
8h
9h-Fh
11-8
PINMUX1_11_8
Reserved
X
Selects Function GP0[4]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function AXR13
I/O
2h
Selects Function CLKX1
I/O
8h
9h-Fh
PINMUX1_7_4
Z
Reserved
X
Selects Function GP0[5]
I/O
Reserved
X
AXR14/CLKR1/GP0[6] Control
0
Pin is 3-stated.
1h
Selects Function AXR14
I/O
2h
Selects Function CLKR1
I/O
3h-7h
8h
9h-Fh
3-0
Z
AXR13/CLKX1/GP0[5] Control
3h-7h
7-4
Type (1)
Description
PINMUX1_3_0
Z
Reserved
X
Selects Function GP0[6]
I/O
Reserved
X
AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR15
2h
Selects Function EPWM0TZ[0]
3h
Reserved
4h
Selects Function ECAP2_APWM2
5h-7h
8h
9h-Fh
Z
I/O
I
X
I/O
Reserved
X
Selects Function GP0[7]
I/O
Reserved
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10.5.10.3 Pin Multiplexing Control 2 Register (PINMUX2)
Figure 10-20. Pin Multiplexing Control 2 Register (PINMUX2)
31
28
27
24
23
20
19
16
PINMUX2_31_28
PINMUX2_27_24
PINMUX2_23_20
PINMUX2_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX2_15_12
PINMUX2_11_8
PINMUX2_7_4
PINMUX2_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
Type
Bit
Field
3128
PINMUX2
_31_28
Value
0
Selects Function CLKS0
I
1h
Selects Function AXR0
I/O
2h
Selects Function ECAP0_APWM0
I/O
3h
Reserved
4h
Selects Function GP8[7]
8h
9h-Fh
PINMUX2
_27_24
X
Selects Function MII_TXD[0]
O
Reserved
X
0
Pin is 3-stated.
Selects Function AXR1
I/O
2h
Selects Function DX0
O
3h
Reserved
4h
Selects Function GP1[9]
9h-Fh
PINMUX2
_23_20
Z
X
I/O
Reserved
X
Selects Function MII_TXD[1]
O
Reserved
X
AXR2/DR0/GP1[10]/MII_TXD[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR2
2h
Selects Function DR0
I
3h
Reserved
X
4h
Selects Function GP1[10]
5h-7h
8h
9h-Fh
216
Reserved
1h
8h
(1)
X
I/O
AXR1/DX0/GP1[9]/MII_TXD[1] Control
5h-7h
2320
(1)
AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLK
S0 Control
5h-7h
2724
Description
Z
I/O
I/O
Reserved
X
Selects Function MII_TXD[2]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued)
Type
Bit
Field
1916
PINMUX2
_19_16
Value
AXR3/FSX0/GP1[11]/MII_TXD[3] Control
Pin is 3-stated.
1h
Selects Function AXR3
I/O
2h
Selects Function FSX0
I/O
3h
Reserved
4h
Selects Function GP1[11]
8h
9h-Fh
PINMUX2
_15_12
Reserved
X
Selects Function MII_TXD[3]
O
Reserved
X
0
Pin is 3-stated.
Selects Function AXR4
I/O
2h
Selects Function FSR0
I/O
3h
Reserved
4h
Selects Function GP1[12]
9h-Fh
Z
X
I/O
Reserved
X
Selects Function MII_COL
I
Reserved
X
AXR5/CLKX0/GP1[13]/MII_TXCLK Control
0
Pin is 3-stated.
1h
Selects Function AXR5
I/O
2h
Selects Function CLKX0
I/O
3h
Reserved
4h
Selects Function GP1[13]
5h-7h
8h
9h-Fh
PINMUX2
_7_4
Reserved
Z
X
I/O
X
Selects Function MII_TXCLK
I
Reserved
X
AXR6/CLKR0/GP1[14]/MII_TXEN/PRU0_R31[6]
Control
0
Selects Function PRU0_R31[6]
1h
Selects Function AXR6
I/O
2h
Selects Function CLKR0
I/O
3h
Reserved
4h
Selects Function GP1[14]
5h-7h
8h
9h-Fh
3-0
X
I/O
1h
8h
7-4
Z
AXR4/FSR0/GP1[12]/MII_COL Control
5h-7h
11-8 PINMUX2
_11_8
(1)
0
5h-7h
1512
Description
PINMUX2
_3_0
I
X
I/O
Reserved
X
Selects Function MII_TXEN
O
Reserved
X
AXR7/EPWM1TZ[0]/PRU0_R30[17]/GP1[15]/PR
U0_R31[7] Control
0
Selects Function PRU0_R31[7]
1h
Selects Function AXR7
2h
Selects Function EPWM1TZ[0]
I
3h
Reserved
X
4h
Selects Function PRU0_R30[17]
O
5h-7h
8h
9h-Fh
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Reserved
Selects Function GP1[15]
Reserved
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I
I/O
X
I/O
X
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10.5.10.4 Pin Multiplexing Control 3 Register (PINMUX3)
Figure 10-21. Pin Multiplexing Control 3 Register (PINMUX3)
31
28
27
24
23
20
19
16
PINMUX3_31_28
PINMUX3_27_24
PINMUX3_23_20
PINMUX3_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX3_15_12
PINMUX3_11_8
PINMUX3_7_4
PINMUX3_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
Bit
Field
31-28
Value
PINMUX3_31_28
SPI0_SCS[2]/UART0_RTS/GP8[1]/MII_RXD[0] Control
0
Reserved
1h
Selects Function SPI0_SCS[2]
I/O
2h
Selects Function UART0_RTS
O
3h
Reserved
4h
Selects Function GP8[1]
5h-7h
8h
9h-Fh
27-24
PINMUX3_27_24
Reserved
X
Selects Function MII_RXD[0]
I
Reserved
X
0
Reserved
Selects Function SPI0_SCS[3]
I/O
2h
Selects Function UART0_CTS
I
3h
Reserved
4h
Selects Function GP8[2]
9h-Fh
PINMUX3_23_20
X
X
I/O
Reserved
X
Selects Function MII_RXD[1]
I
Reserved
X
SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[4]
I/O
2h
Selects Function UART0_TXD
O
3h
Reserved
X
4h
Selects Function GP8[3]
5h-7h
8h
9h-Fh
218
X
I/O
1h
8h
(1)
X
SPI0_SCS[3]/UART0_CTS/GP8[2]/MII_RXD[1] Control
5h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function MII_RXD[2]
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX3_19_16
SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[5]
2h
Selects Function UART0_RXD
I
3h
Reserved
X
4h
Selects Function GP8[4]
5h-7h
8h
9h-Fh
15-12
PINMUX3_15_12
X
Selects Function MII_RXD[3]
I
Reserved
X
Pin is 3-stated.
1h
Selects Function SPI0_SIMO
I/O
2h
Selects Function EPWMSYNCO
O
3h
Reserved
4h
Selects Function GP8[5]
9h-Fh
PINMUX3_11_8
Z
X
I/O
Reserved
X
Selects Function MII_CRS
I
Reserved
X
SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SOMI
2h
Selects Function EPWMSYNCI
I
3h
Reserved
X
4h
Selects Function GP8[6]
5h-7h
8h
9h-Fh
PINMUX3_7_4
Z
I/O
I/O
Reserved
X
Selects Function MII_RXER
I
Reserved
X
SPI0_ENA/EPWM0B/PRU0_R30[6]/MII_RXDV Control
0
Pin is 3-stated.
1h
Selects Function SPI0_ENA
I/O
2h
Selects Function EPWM0B
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[6]
O
Reserved
X
Selects Function MII_RXDV
I
Reserved
X
5h-7h
8h
9h-Fh
3-0
I/O
Reserved
0
8h
7-4
Z
I/O
SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS Control
5h-7h
11-8
Type (1)
Description
PINMUX3_3_0
Z
SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK Control
0
Pin is 3-stated.
1h
Selects Function SPI0_CLK
I/O
2h
Selects Function EPWM0A
I/O
3h
Reserved
4h
Selects Function GP1[8]
5h-7h
8h
9h-Fh
Z
X
I/O
Reserved
X
Selects Function MII_RXCLK
I
Reserved
X
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10.5.10.5 Pin Multiplexing Control 4 Register (PINMUX4)
Figure 10-22. Pin Multiplexing Control 4 Register (PINMUX4)
31
28
27
24
23
20
19
16
PINMUX4_31_28
PINMUX4_27_24
PINMUX4_23_20
PINMUX4_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX4_15_12
PINMUX4_11_8
PINMUX4_7_4
PINMUX4_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
Bit
Field
31-28
Value
PINMUX4_31_28
SP1_SCS[2]/UART1_TXD/GP1[0] Control
0
Pin is 3-stated.
1h
Selects Function SP1_SCS[2]
I/O
2h
Selects Function UART1_TXD
O
3h-7h
8h
9h-Fh
27-24
PINMUX4_27_24
I/O
Reserved
X
Pin is 3-stated.
Selects Function SPI1_SCS[3]
2h
Selects Function UART1_RXD
I
Reserved
X
PINMUX4_23_20
Z
I/O
Selects Function GP1[1]
I/O
Reserved
X
SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[4]
I/O
2h
Selects Function UART2_TXD
O
3h
Reserved
4h
Selects Function I2C1_SDA
5h-7h
8h
9h-Fh
PINMUX4_19_16
Z
X
I/O
Reserved
X
Selects Function GP1[2]
I/O
Reserved
X
SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[5]
I/O
2h
Selects Function UART2_RXD
I
3h
Reserved
4h
Selects Function I2C1_SCL
5h-7h
8h
9h-Fh
220
X
Selects Function GP1[0]
1h
9h-Fh
(1)
Reserved
SPI1_SCS[3]/UART1_RXD/GP1[1] Control
8h
19-16
Z
0
3h-7h
23-20
Type (1)
Description
Z
X
I/O
Reserved
X
Selects Function GP1[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX4_15_12
SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[6]
I/O
2h
Selects Function I2C0_SDA
I/O
3h
Reserved
X
4h
Selects Function TM64P3_OUT12
O
5h-7h
8h
9h-Fh
11-8
PINMUX4_11_8
Reserved
X
Selects Function GP1[4]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[7]
I/O
2h
Selects Function I2C0_SCL
I/O
3h
Reserved
X
4h
Selects Function TM64P2_OUT12
O
8h
9h-Fh
PINMUX4_7_4
Z
Reserved
X
Selects Function GP1[5]
I/O
Reserved
X
SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 Control
0
Selects Function TM64P1_IN12
I
1h
Selects Function SPI0_SCS[0]
I/O
2h
Selects Function TM64P1_OUT12
O
3h
Reserved
4h
Selects Function GP1[6]
5h-7h
8h
9h-Fh
3-0
Z
SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] Control
5h-7h
7-4
Type (1)
Description
PINMUX4_3_0
X
I/O
Reserved
X
Selects Function MDIO_D
I/O
Reserved
X
SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 Control
0
Selects Function TM64P0_IN12
I
1h
Selects Function SPI0_SCS[1]
I/O
2h
Selects Function TM64P0_OUT12
O
3h
Reserved
4h
Selects Function GP1[7]
5h-7h
8h
9h-Fh
X
I/O
Reserved
X
Selects Function MDIO_CLK
O
Reserved
X
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10.5.10.6 Pin Multiplexing Control 5 Register (PINMUX5)
Figure 10-23. Pin Multiplexing Control 5 Register (PINMUX5)
31
28
27
24
23
20
19
16
PINMUX5_31_28
PINMUX5_27_24
PINMUX5_23_20
PINMUX5_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX5_15_12
PINMUX5_11_8
PINMUX5_7_4
PINMUX5_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
Bit
Field
31-28
Value
PINMUX5_31_28
EMA_BA[0]/GP2[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_BA[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX5_27_24
X
Z
Selects Function EMA_BA[1]
O
Reserved
X
PINMUX5_23_20
Selects Function GP2[9]
I/O
Reserved
X
SPI1_SIMO/GP2[10] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SIMO
8h
9h-Fh
PINMUX5_19_16
Z
I/O
Reserved
X
Selects Function GP2[10]
I/O
Reserved
X
SPI1_SOMI/GP2[11] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SOMI
2h-7h
8h
9h-Fh
PINMUX5_15_12
Z
I/O
Reserved
X
Selects Function GP2[11]
I/O
Reserved
X
SPI1_ENA/GP2[12] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_ENA
2h-7h
8h
9h-Fh
222
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP2[8]
1h
9h-Fh
19-16
Reserved
EMA_BA[1]/GP2[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP2[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX5_11_8
SPI1_CLK/GP2[13] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_CLK
2h-7h
8h
9h-Fh
7-4
PINMUX5_7_4
Z
I/O
Reserved
X
Selects Function GP2[13]
I/O
Reserved
X
SPI1_SCS[0]/EPWM1B/PRU0_R30[7]/GP2[14]/TM64P3_IN12 Control
0
Selects Function TM64P3_IN12
I
1h
Selects Function SPI1_SCS[0]
I/O
2h
Selects Function EPWM1B
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[7]
O
5h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX5_3_0
Reserved
X
Selects Function GP2[14]
I/O
Reserved
X
SPI1_SCS[1]/EPWM1A/PRU0_R30[8]/GP2[15]/TM64P2_IN12 Control
0
Selects Function TM64P2_IN12
I
1h
Selects Function SPI1_SCS[1]
I/O
2h
Selects Function EPWM1A
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[8]
O
5h-7h
8h
9h-Fh
Reserved
X
Selects Function GP2[15]
I/O
Reserved
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X
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10.5.10.7 Pin Multiplexing Control 6 Register (PINMUX6)
Figure 10-24. Pin Multiplexing Control 6 Register (PINMUX6)
31
28
27
24
23
20
19
16
PINMUX6_31_28
PINMUX6_27_24
PINMUX6_23_20
PINMUX6_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX6_15_12
PINMUX6_11_8
PINMUX6_7_4
PINMUX6_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
Bit
Field
31-28
Value
PINMUX6_31_28
EMA_CS[0]/GP2[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX6_27_24
X
Selects Function EMA_WAIT[1]
I
Reserved
X
Selects Function PRU0_R30[1]
O
9h-Fh
PINMUX6_23_20
I
Reserved
X
Selects Function GP2[1]
I/O
Reserved
X
EMA_WE_DQM[1]/GP2[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[1]
O
2h-7h
8h
9h-Fh
PINMUX6_19_16
Reserved
X
Selects Function GP2[2]
I/O
Reserved
X
EMA_WE_DQM[0]/GP2[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[0]
O
2h-7h
8h
9h-Fh
PINMUX6_15_12
Reserved
X
Selects Function GP2[3]
I/O
Reserved
X
EMA_CAS/PRU0_R30[2]/GP2[4]/PRU0_R31[2] Control
0
Selects Function PRU0_R31[2]
I
1h
Selects Function EMA_CAS
O
Reserved
X
Selects Function PRU0_R30[2]
O
2h-3h
4h
5h-7h
8h
9h-Fh
224
Reserved
Selects Function PRU0_R31[1]
8h
(1)
I/O
0
4h
15-12
X
Selects Function GP2[0]
1h
5h-7h
19-16
Reserved
EMA_WAIT[1]/PRU0_R30[1]/GP2[1]/PRU0_R31[1] Control
2h-3h
23-20
Type (1)
Description
Reserved
X
Selects Function GP2[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX6_11_8
EMA_RAS/PRU0_R30[3]/GP2[5]/PRU0_R31[3] Control
0
Selects Function PRU0_R31[3]
I
1h
Selects Function EMA_RAS
O
2h-3h
4h
5h-7h
8h
9h-Fh
7-4
PINMUX6_7_4
Reserved
X
Selects Function PRU0_R30[3]
O
Reserved
X
Selects Function GP2[5]
I/O
Reserved
X
EMA_SDCKE/PRU0_R30[4]/GP2[6]/PRU0_R31[4] Control
0
Selects Function PRU0_R31[4]
I
1h
Selects Function EMA_SDCKE
O
2h-3h
4h
5h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX6_3_0
Reserved
X
Selects Function PRU0_R30[4]
O
Reserved
X
Selects Function GP2[6]
I/O
Reserved
X
EMA_CLK/PRU0_R30[5]/GP2[7]/PRU0_R31[5] Control
0
Selects Function PRU0_R31[5]
I
1h
Selects Function EMA_CLK
O
2h-3h
4h
5h-7h
8h
9h-Fh
Reserved
X
Selects Function PRU0_R30[5]
O
Reserved
X
Selects Function GP2[7]
I/O
Reserved
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X
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10.5.10.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 10-25. Pin Multiplexing Control 7 Register (PINMUX7)
31
28
27
24
23
20
19
16
PINMUX7_31_28
PINMUX7_27_24
PINMUX7_23_20
PINMUX7_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX7_15_12
PINMUX7_11_8
PINMUX7_7_4
PINMUX7_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit
Field
31-28
Value
PINMUX7_31_28
EMA_WAIT[0]/PRU0_R30[0]/GP3[8]/PRU0_R31[0] Control
0
Selects Function PRU0_R31[0]
I
1h
Selects Function EMA_WAIT[0]
I
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX7_27_24
X
Selects Function GP3[8]
I/O
Reserved
X
1h
Selects Function EMA_A_RW
O
PINMUX7_23_20
Reserved
X
Selects Function GP3[9]
I/O
Reserved
X
EMA_OE/GP3[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_OE
O
8h
9h-Fh
PINMUX7_19_16
Reserved
X
Selects Function GP3[10]
I/O
Reserved
X
EMA_WE/GP3[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE
O
2h-7h
8h
9h-Fh
PINMUX7_15_12
Reserved
X
Selects Function GP3[11]
I/O
Reserved
X
EMA_CS[5]/GP3[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[5]
O
Reserved
X
2h-7h
8h
9h-Fh
226
Reserved
Z
2h-7h
(1)
O
Pin is 3-stated.
9h-Fh
15-12
X
Selects Function PRU0_R30[0]
0
8h
19-16
Reserved
EMA_A_RW/GP3[9] Control
2h-7h
23-20
Type (1)
Description
Selects Function GP3[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX7_11_8
EMA_CS[4]/GP3[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[4]
O
2h-7h
8h
9h-Fh
7-4
PINMUX7_7_4
Reserved
X
Selects Function GP3[13]
I/O
Reserved
X
EMA_CS[3]/GP3[14] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[3]
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX7_3_0
Reserved
X
Selects Function GP3[14]
I/O
Reserved
X
EMA_CS[2]/GP3[15] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[2]
O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP3[15]
I/O
Reserved
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10.5.10.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 10-26. Pin Multiplexing Control 8 Register (PINMUX8)
31
28
27
24
23
20
19
16
PINMUX8_31_28
PINMUX8_27_24
PINMUX8_23_20
PINMUX8_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX8_15_12
PINMUX8_11_8
PINMUX8_7_4
PINMUX8_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit
Field
31-28
Value
PINMUX8_31_28
EMA_D[8]/GP3[0] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[8]
2h-7h
8h
9h-Fh
27-24
PINMUX8_27_24
Selects Function EMA_D[9]
PINMUX8_23_20
X
Z
I/O
Reserved
X
Selects Function GP3[1]
I/O
Reserved
X
EMA_D[10]/GP3[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[10]
8h
9h-Fh
PINMUX8_19_16
Z
I/O
Reserved
X
Selects Function GP3[2]
I/O
Reserved
X
EMA_D[11]/GP3[3] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[11]
2h-7h
8h
9h-Fh
PINMUX8_15_12
Z
I/O
Reserved
X
Selects Function GP3[3]
I/O
Reserved
X
EMA_D[12]/GP3[4] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[12]
2h-7h
8h
9h-Fh
228
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP3[0]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[9]/GP3[1] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP3[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX8_11_8
EMA_D[13]/GP3[5] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[13]
2h-7h
8h
9h-Fh
7-4
PINMUX8_7_4
Z
I/O
Reserved
X
Selects Function GP3[5]
I/O
Reserved
X
EMA_D[14]/GP3[6] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[14]
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX8_3_0
Z
I/O
Reserved
X
Selects Function GP3[6]
I/O
Reserved
X
EMA_D[15]/GP3[7] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[15]
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP3[7]
I/O
Reserved
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10.5.10.10 Pin Multiplexing Control 9 Register (PINMUX9)
Figure 10-27. Pin Multiplexing Control 9 Register (PINMUX9)
31
28
27
24
23
20
19
16
PINMUX9_31_28
PINMUX9_27_24
PINMUX9_23_20
PINMUX9_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX9_15_12
PINMUX9_11_8
PINMUX9_7_4
PINMUX9_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
Bit
Field
31-28
Value
PINMUX9_31_28
EMA_D[0]/GP4[8] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[0]
2h-7h
8h
9h-Fh
27-24
PINMUX9_27_24
Selects Function EMA_D[1]
PINMUX9_23_20
X
Z
I/O
Reserved
X
Selects Function GP4[9]
I/O
Reserved
X
EMA_D[2]/GP4[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[2]
8h
9h-Fh
PINMUX9_19_16
Z
I/O
Reserved
X
Selects Function GP4[10]
I/O
Reserved
X
EMA_D[3]/GP4[11] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[3]
2h-7h
8h
9h-Fh
PINMUX9_15_12
Z
I/O
Reserved
X
Selects Function GP4[11]
I/O
Reserved
X
EMA_D[4]/GP4[12] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[4]
2h-7h
8h
9h-Fh
230
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP4[8]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[1]/GP4[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP4[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX9_11_8
EMA_D[5]/GP4[13] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[5]
2h-7h
8h
9h-Fh
7-4
PINMUX9_7_4
Z
I/O
Reserved
X
Selects Function GP4[13]
I/O
Reserved
X
EMA_D[6]/GP4[14] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[6]
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX9_3_0
Z
I/O
Reserved
X
Selects Function GP4[14]
I/O
Reserved
X
EMA_D[7]/GP4[15] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[7]
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP4[15]
I/O
Reserved
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10.5.10.11 Pin Multiplexing Control 10 Register (PINMUX10)
Figure 10-28. Pin Multiplexing Control 10 Register (PINMUX10)
31
28
27
24
23
20
19
16
PINMUX10_31_28
PINMUX10_27_24
PINMUX10_23_20
PINMUX10_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX10_15_12
PINMUX10_11_8
PINMUX10_7_4
PINMUX10_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
Bit
Field
31-28
Value
PINMUX10_31_28
EMA_A[16]/MMCSD0_DAT[5]/PRU1_R30[24]/GP4[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[16]
O
2h
Selects Function MMCSD0_DAT[5]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[24]
O
Reserved
X
5h-7h
8h
9h-Fh
27-24
PINMUX10_27_24
X
0
Pin is 3-stated.
Z
Selects Function EMA_A[17]
O
2h
Selects Function MMCSD0_DAT[4]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[25]
O
9h-Fh
PINMUX10_23_20
Reserved
X
Selects Function GP4[1]
I/O
Reserved
X
EMA_A[18]/MMCSD0_DAT[3]/PRU1_R30[26]/GP4[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[18]
O
2h
Selects Function MMCSD0_DAT[3]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[26]
O
5h-7h
8h
9h-Fh
232
I/O
Reserved
1h
8h
(1)
Selects Function GP4[0]
EMA_A[17]/MMCSD0_DAT[4]/PRU1_R30[25]/GP4[1] Control
5h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP4[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX10_19_16
EMA_A[19]/MMCSD0_DAT[2]/PRU1_R30[27]/GP4[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[19]
O
2h
Selects Function MMCSD0_DAT[2]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[27]
O
5h-7h
8h
9h-Fh
15-12
PINMUX10_15_12
I/O
Reserved
X
Pin is 3-stated.
1h
Selects Function EMA_A[20]
O
2h
Selects Function MMCSD0_DAT[1]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[28]
O
9h-Fh
PINMUX10_11_8
Z
Reserved
X
Selects Function GP4[4]
I/O
Reserved
X
EMA_A[21]/MMCSD0_DAT[0]/PRU1_R30[29]/GP4[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[21]
O
2h
Selects Function MMCSD0_DAT[0]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[29]
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX10_7_4
Selects Function GP4[5]
I/O
Reserved
X
EMA_A[22]/MMCSD0_CMD/PRU1_R30[30]/GP4[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[22]
O
2h
Selects Function MMCSD0_CMD
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[30]
O
5h-7h
8h
9h-Fh
3-0
X
Selects Function GP4[3]
0
8h
7-4
Reserved
EMA_A[20]/MMCSD0_DAT[1]/PRU1_R30[28]/GP4[4] Control
5h-7h
11-8
Type (1)
Description
PINMUX10_3_0
Reserved
X
Selects Function GP4[6]
I/O
Reserved
X
MMCSD0_CLK/PRU1_R30[31]/GP4[7] Control
0
Pin is 3-stated.
1h
Reserved
X
2h
Selects Function MMCSD0_CLK
O
3h
Reserved
X
4h
Selects Function PRU1_R30[31]
O
5h-7h
8h
9h-Fh
Z
Reserved
X
Selects Function GP4[7]
I/O
Reserved
X
10.5.10.12 Pin Multiplexing Control 11 Register (PINMUX11)
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Figure 10-29. Pin Multiplexing Control 11 Register (PINMUX11)
31
28
27
24
23
20
19
16
PINMUX11_31_28
PINMUX11_27_24
PINMUX11_23_20
PINMUX11_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX11_15_12
PINMUX11_11_8
PINMUX11_7_4
PINMUX11_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
Bit
Field
31-28
Value
PINMUX11_31_28
EMA_A[8]/PRU1_R30[16]/GP5[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[8]
O
Reserved
X
Selects Function PRU1_R30[16]
O
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX11_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_A[9]
O
8h
9h-Fh
PINMUX11_23_20
Reserved
X
Selects Function PRU1_R30[17]
O
Reserved
X
Selects Function GP5[9]
I/O
Reserved
X
EMA_A[10]/PRU1_R30[18]/GP5[10]/PRU1_R31[18] Control
0
Selects Function PRU1_R31[18]
I
1h
Selects Function EMA_A[10]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX11_19_16
Reserved
X
Selects Function PRU1_R30[18]
O
Reserved
X
Selects Function GP5[10]
I/O
Reserved
X
EMA_A[11]/PRU1_R30[19]/GP5[11]/PRU1_R31[19] Control
0
Selects Function PRU1_R31[19]
I
1h
Selects Function EMA_A[11]
O
2h-3h
4h
5h-7h
8h
9h-Fh
234
I/O
0
5h-7h
(1)
X
Selects Function GP5[8]
1h
4h
19-16
Reserved
EMA_A[9]/PRU1_R30[17]/GP5[9] Control
2h-3h
23-20
Type (1)
Description
Reserved
X
Selects Function PRU1_R30[19]
O
Reserved
X
Selects Function GP5[11]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX11_15_12
EMA_A[12]/PRU1_R30[20]/GP5[12]/PRU1_R31[20] Control
0
Selects Function PRU1_R31[20]
I
1h
Selects Function EMA_A[12]
O
2h-3h
4h
5h-7h
8h
9h-Fh
11-8
PINMUX11_11_8
X
Selects Function PRU1_R30[20]
O
Reserved
X
Selects Function GP5[12]
I/O
Reserved
X
EMA_A[13]/PRU0_R30[21]/PRU1_R30[21]/GP5[13]/PRU1_R31[21] Control
Selects Function PRU1_R31[21]
I
1h
Selects Function EMA_A[13]
O
2h
Selects Function PRU0_R30[21]
O
3h
Reserved
X
4h
Selects Function PRU1_R30[21]
O
Reserved
X
8h
9h-Fh
PINMUX11_7_4
Selects Function GP5[13]
I/O
Reserved
X
EMA_A[14]/MMCSD0_DAT[7]/PRU1_R30[22]/GP5[14]/PRU1_R31[22] Control
0
Selects Function PRU1_R31[22]
I
1h
Selects Function EMA_A[14]
O
2h
Selects Function MMCSD0_DAT[7]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[22]
O
5h-7h
8h
9h-Fh
3-0
Reserved
0
5h-7h
7-4
Type (1)
Description
PINMUX11_3_0
Reserved
X
Selects Function GP5[14]
I/O
Reserved
X
EMA_A[15]/MMCSD0_DAT[6]/PRU1_R30[23]/GP5[15]/PRU1_R31[23] Control
0
Selects Function PRU1_R31[23]
1h
Selects Function EMA_A[15]
O
2h
Selects Function MMCSD0_DAT[6]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[23]
O
5h-7h
8h
9h-Fh
I
Reserved
X
Selects Function GP5[15]
I/O
Reserved
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10.5.10.13 Pin Multiplexing Control 12 Register (PINMUX12)
Figure 10-30. Pin Multiplexing Control 12 Register (PINMUX12)
31
28
27
24
23
20
19
16
PINMUX12_31_28
PINMUX12_27_24
PINMUX12_23_20
PINMUX12_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX12_15_12
PINMUX12_11_8
PINMUX12_7_4
PINMUX12_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
Bit
Field
31-28
Value
PINMUX12_31_28
EMA_A[0]/GP5[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX12_27_24
X
Z
Selects Function EMA_A[1]
O
Reserved
X
PINMUX12_23_20
Selects Function GP5[1]
I/O
Reserved
X
EMA_A[2]/GP5[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[2]
O
8h
9h-Fh
PINMUX12_19_16
Reserved
X
Selects Function GP5[2]
I/O
Reserved
X
EMA_A[3]/GP5[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[3]
O
2h-7h
8h
9h-Fh
PINMUX12_15_12
Reserved
X
Selects Function GP5[3]
I/O
Reserved
X
EMA_A[4]/GP5[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[4]
O
2h-7h
8h
9h-Fh
236
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP5[0]
1h
9h-Fh
19-16
Reserved
EMA_A[1]/GP5[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP5[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX12_11_8
EMA_A[5]/GP5[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[5]
O
2h-7h
8h
9h-Fh
7-4
PINMUX12_7_4
Reserved
X
Selects Function GP5[5]
I/O
Reserved
X
EMA_A[6]/GP5[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[6]
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX12_3_0
Reserved
X
Selects Function GP5[6]
I/O
Reserved
X
EMA_A[7]/PRU1_R30[15]/GP5[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[7]
O
2h-3h
4h
5h-7h
8h
9h-Fh
Reserved
X
Selects Function PRU1_R30[15]
O
Reserved
X
Selects Function GP5[7]
I/O
Reserved
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10.5.10.14 Pin Multiplexing Control 13 Register (PINMUX13)
Figure 10-31. Pin Multiplexing Control 13 Register (PINMUX13)
31
28
27
24
23
20
19
16
PINMUX13_31_28
PINMUX13_27_24
PINMUX13_23_20
PINMUX13_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX13_15_12
PINMUX13_11_8
PINMUX13_7_4
PINMUX13_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
Bit
Field
31-28
Value
PINMUX13_31_28
PRU0_R30[26]/ UHPI_HRW/UPP_CHA_WAIT/GP6[8]/PRU1_R31[17] Control
0
Selects Function PRU1_R31[17]
I
1h
Selects Function PRU0_R30[26]
O
2h
Selects Function UHPI_HRW
I
3h
Reserved
X
4h
Selects Function UPP_CHA_WAIT
5h-7h
8h
9h-Fh
27-24
PINMUX13_27_24
Selects Function GP6[8]
I/O
Reserved
X
0
Pin is 3-stated.
Z
Selects Function PRU0_R30[27]
O
2h
Selects Function UHPI_HHWIL
I
3h
Reserved
4h
Selects Function UPP_CHA_ENABLE
9h-Fh
PINMUX13_23_20
X
I/O
Reserved
X
Selects Function GP6[9]
I/O
Reserved
X
PRU0_R30[28]/UHPI_HCNTL1/UPP_CHA_START/GP6[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[28]
O
2h
Selects Function UHPI_HCNTL1
I
3h
Reserved
X
4h
Selects Function UPP_CHA_START
5h-7h
8h
9h-Fh
238
X
1h
8h
(1)
I/O
Reserved
PRU0_R30[27]/UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9] Control
5h-7h
23-20
Type (1)
Description
I/O
Reserved
X
Selects Function GP6[10]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX13_19_16
PRU0_R30[29]/UHPI_HCNTL0/UPP_CHA_CLOCK/GP6[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[29]
O
2h
Selects Function UHPI_HCNTL0
I
3h
Reserved
X
4h
Selects Function UPP_CHA_CLOCK
5h-7h
8h
9h-Fh
15-12
PINMUX13_15_12
I/O
Reserved
X
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[30]
O
2h
Selects Function UHPI_HINT
O
3h
Reserved
X
4h
Selects Function PRU1_R30[11]
O
9h-Fh
PINMUX13_11_8
Reserved
X
Selects Function GP6[12]
I/O
Reserved
X
PRU0_R30[31]/UHPI_HRDY/PRU1_R30[12]/GP6[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[31]
O
2h
Selects Function UHPI_HRDY
O
3h
Reserved
X
4h
Selects Function PRU1_R30[12]
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX13_7_4
Selects Function GP6[13]
I/O
Reserved
X
CLKOUT/UHPI_HDS2/PRU1_R30[13]/GP6[14] Control
0
Pin is 3-stated.
Z
1h
Selects Function CLKOUT
O
2h
Selects Function UHPI_HDS2
I
3h
Reserved
X
4h
Selects Function PRU1_R30[13]
O
5h-7h
8h
9h-Fh
3-0
X
Selects Function GP6[11]
0
8h
7-4
I/O
Reserved
PRU0_R30[30]/UHPI_HINT/PRU1_R30[11]/GP6[12] Control
5h-7h
11-8
Type (1)
Description
PINMUX13_3_0
Reserved
X
Selects Function GP6[14]
I/O
Reserved
X
RESETOUT/UHPI_HAS/PRU1_R30[14]/GP6[15] Control
0
Selects Function RESETOUT
O
1h
Selects Function RESETOUT
O
2h
Selects Function UHPI_HAS
I
3h
Reserved
X
4h
Selects Function PRU1_R30[14]
O
5h-7h
8h
9h-Fh
Reserved
X
Selects Function GP6[15]
I/O
Reserved
X
10.5.10.15 Pin Multiplexing Control 14 Register (PINMUX14)
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Figure 10-32. Pin Multiplexing Control 14 Register (PINMUX14)
31
28
27
24
23
20
19
16
PINMUX14_31_28
PINMUX14_27_24
PINMUX14_23_20
PINMUX14_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX14_15_12
PINMUX14_11_8
PINMUX14_7_4
PINMUX14_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
Bit
Field
31-28
Value
PINMUX14_31_28
VP_DIN[2]/UHPI_HD[10]/UPP_D[10]/RMII_RXER/PRU0_R31[24] Control
0
Selects Function PRU0_R31[24]
1h
Selects Function VP_DIN[2]
2h
Selects Function UHPI_HD[10]
3h
Reserved
4h
Selects Function UPP_D[10]
5h-7h
8h
9h-Fh
27-24
PINMUX14_27_24
X
I/O
X
Selects Function RMII_RXER
I
Reserved
X
Selects Function PRU0_R31[25]
1h
Selects Function VP_DIN[3]
2h
Selects Function UHPI_HD[11]
3h
Reserved
4h
Selects Function UPP_D[11]
9h-Fh
PINMUX14_23_20
I
I
I/O
X
I/O
Reserved
X
Selects Function RMII_RXD[0]
I
Reserved
X
VP_DIN[4]/UHPI_HD[12]/UPP_D[12]/RMII_RXD[1]/PRU0_R31[26] Control
0
Selects Function PRU0_R31[26]
I
1h
Selects Function VP_DIN[4]
I
2h
Selects Function UHPI_HD[12]
3h
Reserved
4h
Selects Function UPP_D[12]
5h-7h
8h
9h-Fh
240
I
I/O
VP_DIN[3]/UHPI_HD[11]/UPP_D[11]/RMII_RXD[0]/PRU0_R31[25] Control
8h
(1)
I
Reserved
0
5h-7h
23-20
Type (1)
Description
I/O
X
I/O
Reserved
X
Selects Function RMII_RXD[1]
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX14_19_16
VP_DIN[5]/UHPI_HD[13]/UPP_D[13]/RMII_TXEN/PRU0_R31[27] Control
0
Selects Function PRU0_R31[27]
1h
Selects Function VP_DIN[5]
2h
Selects Function UHPI_HD[13]
3h
Reserved
4h
Selects Function UPP_D[13]
5h-7h
8h
9h-Fh
15-12
PINMUX14_15_12
X
I/O
X
Selects Function RMII_TXEN
O
Reserved
X
Selects Function PRU0_R31[28]
1h
Selects Function VP_DIN[6]
2h
Selects Function UHPI_HD[14]
3h
Reserved
4h
Selects Function UPP_D[14]
9h-Fh
PINMUX14_11_8
I
I
I/O
X
I/O
Reserved
X
Selects Function RMII_TXD[0]
O
Reserved
X
VP_DIN[7]/UHPI_HD[15]/UPP_D[15]/RMII_TXD[1]/PRU0_R31[29] Control
0
Selects Function PRU0_R31[29]
I
1h
Selects Function VP_DIN[7]
I
2h
Selects Function UHPI_HD[15]
3h
Reserved
4h
Selects Function UPP_D[15]
5h-7h
8h
9h-Fh
PINMUX14_7_4
I/O
X
I/O
Reserved
X
Selects Function RMII_TXD[1]
O
Reserved
X
VP_CLKIN1/UHPI_HDS1/PRU1_R30[9]/GP6[6]/PRU1_R31[16] Control
0
Selects Function PRU1_R31[16]
I
1h
Selects Function VP_CLKIN1
I
2h
Selects Function UHPI_HDS1
I
3h
Reserved
X
4h
Selects Function PRU1_R30[9]
O
5h-7h
8h
9h-Fh
3-0
I
I/O
Reserved
0
8h
7-4
I
VP_DIN[6]/UHPI_HD[14]/UPP_D[14]/RMII_TXD[0]/PRU0_R31[28] Control
5h-7h
11-8
Type (1)
Description
PINMUX14_3_0
Reserved
X
Selects Function GP6[6]
I/O
Reserved
X
VP_CLKIN0/UHPI_HCS/PRU1_R30[10]/GP6[7]/UPP_2xTXCLK Control
0
Selects Function UPP_2xTXCLK
I
1h
Selects Function VP_CLKIN0
I
2h
Selects Function UHPI_HCS
I
3h
Reserved
X
4h
Selects Function PRU1_R30[10]
O
5h-7h
8h
9h-Fh
Reserved
X
Selects Function GP6[7]
I/O
Reserved
X
10.5.10.16 Pin Multiplexing Control 15 Register (PINMUX15)
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Figure 10-33. Pin Multiplexing Control 15 Register (PINMUX15)
31
28
27
24
23
20
19
16
PINMUX15_31_28
PINMUX15_27_24
PINMUX15_23_20
PINMUX15_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX15_15_12
PINMUX15_11_8
PINMUX15_7_4
PINMUX15_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
Bit
Field
31-28
Value
PINMUX15_31_28
VP_DIN[10]/UHPI_HD[2]/UPP_D[2]/PRU0_R30[10]/PRU0_R31[10] Control
0
Selects Function PRU0_R31[10]
1h
Selects Function VP_DIN[10]
I
2h
Selects Function UHPI_HD[2]
I/O
3h
Reserved
4h
Selects Function UPP_D[2]
5h-7h
8h
9h-Fh
27-24
PINMUX15_27_24
Reserved
X
Selects Function PRU0_R30[10]
O
Reserved
X
Selects Function PRU0_R31[11]
1h
Selects Function VP_DIN[11]
I
2h
Selects Function UHPI_HD[3]
I/O
3h
Reserved
4h
Selects Function UPP_D[3]
9h-Fh
PINMUX15_23_20
I
X
I/O
Reserved
X
Selects Function PRU0_R30[11]
O
Reserved
X
VP_DIN[12]/UHPI_HD[4]/UPP_D[4]/PRU0_R30[12]/PRU0_R31[12] Control
0
Selects Function PRU0_R31[12]
I
1h
Selects Function VP_DIN[12]
I
2h
Selects Function UHPI_HD[4]
I/O
3h
Reserved
4h
Selects Function UPP_D[4]
5h-7h
8h
9h-Fh
242
X
I/O
0
8h
(1)
I
VP_DIN[11]/UHPI_HD[3]/UPP_D[3]/PRU0_R30[11]/PRU0_R31[11] Control
5h-7h
23-20
Type (1)
Description
X
I/O
Reserved
X
Selects Function PRU0_R30[12]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX15_19_16
VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_D[5]/PRU0_R30[13]/PRU0_R31[13] Control
0
Selects Function PRU0_R31[13]
1h
Selects Function VP_DIN[13]_FIELD
2h
Selects Function UHPI_HD[5]
3h
Reserved
4h
Selects Function UPP_D[5]
5h-7h
8h
9h-Fh
15-12
PINMUX15_15_12
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[13]
O
Reserved
X
0
Selects Function PRU0_R31[14]
1h
Selects Function VP_DIN[14]_HSYNC
2h
Selects Function UHPI_HD[6]
3h
Reserved
4h
Selects Function UPP_D[6]
8h
9h-Fh
PINMUX15_11_8
I
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[14]
O
Reserved
X
VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_D[7]/PRU0_R30[15]/PRU0_R31[15]
Control
0
Selects Function PRU0_R31[15]
1h
Selects Function VP_DIN[15]_VSYNC
2h
Selects Function UHPI_HD[7]
3h
Reserved
4h
Selects Function UPP_D[7]
5h-7h
8h
9h-Fh
7-4
I
VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_D[6]/PRU0_R30[14]/PRU0_R31[14]
Control
5h-7h
11-8
Type (1)
Description
PINMUX15_7_4
I
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[15]
O
Reserved
X
VP_DIN[0]/UHPI_HD[8]/UPP_D[8]/RMII_CRS_DV/PRU1_R31[29] Control
0
Selects Function PRU1_R31[29]
I
1h
Selects Function VP_DIN[0]
I
2h
Selects Function UHPI_HD[8]
3h
Reserved
4h
Selects Function UPP_D[8]
5h-7h
8h
9h-Fh
I/O
X
I/O
Reserved
X
Selects Function RMII_CRS_DV
I
Reserved
X
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Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
Field
3-0
PINMUX15_3_0
Value
VP_DIN[1]/UHPI_HD[9]/UPP_D[9]/RMII_MHZ_50_CLK/PRU0_R31[23] Control
0
Selects Function PRU0_R31[23]. Enables sourcing of the 50 MHz reference clock
from an external source on the RMII_MHZ_50_CLK pin to the EMAC.
1h
Selects Function VP_DIN[1]
2h
Selects Function UHPI_HD[9]
3h
Reserved
4h
Selects Function UPP_D[9]
5h-7h
8h
9h-Fh
244
Type (1)
Description
I
I
I/O
X
I/O
Reserved
X
Selects Function RMII_MHZ_50_CLK. Enables sourcing of the 50 MHz reference
clock from PLL0_SYSCLK7 to the EMAC. Also, PLL0_SYSCLK7 is driven out on the
RMII_MHZ_50_CLK pin. Note that the SYSCLK7 output clock does not meet the
RMII reference clock specification of 50 MHz +/-50 ppm. See Section 6.3.4 for more
information.
O
Reserved
X
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10.5.10.17 Pin Multiplexing Control 16 Register (PINMUX16)
Figure 10-34. Pin Multiplexing Control 16 Register (PINMUX16)
31
28
27
24
23
20
19
16
PINMUX16_31_28
PINMUX16_27_24
PINMUX16_23_20
PINMUX16_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX16_15_12
PINMUX16_11_8
PINMUX16_7_4
PINMUX16_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
Bit
31-28
Field
Value
PINMUX16_31_28
VP_DOUT[2]/UPP_XD[10]/GP7[10]/PRU1_R31[10] Control
0
Selects Function PRU1_R31[10]
I
1h
Selects Function VP_DOUT[2]
O
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX16_27_24
X
Selects Function UPP_XD[10]
I/O
Reserved
X
Selects Function GP7[10]
I/O
Reserved
X
0
Selects Function PRU1_R31[11]
I
1h
Selects Function VP_DOUT[3]
O
4h
5h-7h
8h
9h-Fh
PINMUX16_23_20
Reserved
X
Selects Function UPP_XD[11]
I/O
Reserved
X
Selects Function GP7[11]
I/O
Reserved
X
VP_DOUT[4]/UPP_XD[12]/GP7[12]/PRU1_R31[12] Control
0
Selects Function PRU1_R31[12]
I
1h
Selects Function VP_DOUT[4]
O
Reserved
X
2h-3h
4h
5h-7h
8h
9h-Fh
(1)
Reserved
VP_DOUT[3]/UPP_XD[11]/GP7[11]/PRU1_R31[11] Control
2h-3h
23-20
Type (1)
Description
Selects Function UPP_XD[12]
I/O
Reserved
X
Selects Function GP7[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX16_19_16
VP_DOUT[5]/UPP_XD[13]/GP7[13]/PRU1_R31[13] Control
0
Selects Function PRU1_R31[13]
I
1h
Selects Function VP_DOUT[5]
O
2h-3h
4h
5h-7h
8h
9h-Fh
15-12
PINMUX16_15_12
Reserved
X
Selects Function GP7[13]
I/O
Reserved
X
Selects Function PRU1_R31[14]
I
Selects Function VP_DOUT[6]
O
8h
9h-Fh
PINMUX16_11_8
Reserved
X
Selects Function UPP_XD[14]
I/O
Reserved
X
Selects Function GP7[14]
I/O
Reserved
X
VP_DOUT[7]/UPP_XD[15]/GP7[15]/PRU1_R31[15] Control
0
Selects Function PRU1_R31[15]
I
1h
Selects Function VP_DOUT[7]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX16_7_4
Reserved
X
Selects Function UPP_XD[15]
I/O
Reserved
X
Selects Function GP7[15]
I/O
Reserved
X
VP_DIN[8]/UHPI_HD[0]/UPP_D0/GP6[5]/PRU1_R31[0] Control
0
Selects Function PRU1_R31[0]
1h
Selects Function VP_DIN[8]
2h
Selects Function UHPI_HD[0]
3h
Reserved
4h
Selects Function UPP_D[0]
5h-7h
8h
9h-Fh
PINMUX16_3_0
I
I
I/O
X
I/O
Reserved
X
Selects Function GP6[5]
I/O
Reserved
X
VP_DIN[9]/UHPI_HD[1]/UPP_D[1]/PRU0_R30[9]/PRU0_R31[9] Control
0
Selects Function PRU0_R31[9]
1h
Selects Function VP_DIN[9]
2h
Selects Function UHPI_HD[1]
3h
Reserved
4h
Selects Function UPP_D[1]
5h-7h
8h
9h-Fh
246
I/O
1h
5h-7h
3-0
X
Selects Function UPP_XD[13]
VP_DOUT[6]/UPP_XD[14]/GP7[14]/PRU1_R31[14] Control
4h
7-4
Reserved
0
2h-3h
11-8
Type (1)
Description
I
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[9]
O
Reserved
X
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10.5.10.18 Pin Multiplexing Control 17 Register (PINMUX17)
Figure 10-35. Pin Multiplexing Control 17 Register (PINMUX17)
31
28
27
24
23
20
19
16
PINMUX17_31_28
PINMUX17_27_24
PINMUX17_23_20
PINMUX17_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX17_15_12
PINMUX17_11_8
PINMUX17_7_4
PINMUX17_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
Bit
31-28
Field
Value
PINMUX17_31_28
VP_DOUT[10]/UPP_XD[2]/GP7[2]/BOOT[2] Control
0
Selects Function BOOT[2]
I
1h
Selects Function VP_DOUT[10]
O
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX17_27_24
X
Selects Function UPP_XD[2]
I/O
Reserved
X
Selects Function GP7[2]
I/O
Reserved
X
0
Selects Function BOOT[3]
I
1h
Selects Function VP_DOUT[11]
O
4h
5h-7h
8h
9h-Fh
PINMUX17_23_20
Reserved
X
Selects Function UPP_XD[3]
I/O
Reserved
X
Selects Function GP7[3]
I/O
Reserved
X
VP_DOUT[12]/UPP_XD[4]/GP7[4]/BOOT[4] Control
0
Selects Function BOOT[4]
I
1h
Selects Function VP_DOUT[12]
O
Reserved
X
2h-3h
4h
5h-7h
8h
9h-Fh
(1)
Reserved
VP_DOUT[11]/UPP_XD[3]/GP7[3]/BOOT[3] Control
2h-3h
23-20
Type (1)
Description
Selects Function UPP_XD[4]
I/O
Reserved
X
Selects Function GP7[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX17_19_16
VP_DOUT[13]/UPP_XD[5]/GP7[5]/BOOT[5] Control
0
Selects Function BOOT[5]
I
1h
Selects Function VP_DOUT[13]
O
2h-3h
4h
5h-7h
8h
9h-Fh
15-12
PINMUX17_15_12
Reserved
X
Selects Function GP7[5]
I/O
Reserved
X
Selects Function BOOT[6]
I
Selects Function VP_DOUT[14]
O
8h
9h-Fh
PINMUX17_11_8
Reserved
X
Selects Function UPP_XD[6]
I/O
Reserved
X
Selects Function GP7[6]
I/O
Reserved
X
VP_DOUT[15]/UPP_XD[7]/GP7[7]/BOOT[7] Control
0
Selects Function BOOT[7]
I
1h
Selects Function VP_DOUT[15]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX17_7_4
Reserved
X
Selects Function UPP_XD[7]
I/O
Reserved
X
Selects Function GP7[7]
I/O
Reserved
X
VP_DOUT[0]/UPP_XD[8]/GP7[8]/PRU1_R31[8] Control
0
Selects Function PRU1_R31[8]
I
1h
Selects Function VP_DOUT[0]
O
Reserved
X
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX17_3_0
Selects Function UPP_XD[8]
I/O
Reserved
X
Selects Function GP7[8]
I/O
Reserved
X
VP_DOUT[1]/UPP_XD[9]/GP7[9]/PRU1_R31[9] Control
0
Selects Function PRU1_R31[9]
I
1h
Selects Function VP_DOUT[1]
O
2h-3h
4h
5h-7h
8h
9h-Fh
248
I/O
1h
5h-7h
3-0
X
Selects Function UPP_XD[5]
VP_DOUT[14]/UPP_XD[6]/GP7[6]/BOOT[6] Control
4h
7-4
Reserved
0
2h-3h
11-8
Type (1)
Description
Reserved
X
Selects Function UPP_XD[9]
I/O
Reserved
X
Selects Function GP7[9]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.19 Pin Multiplexing Control 18 Register (PINMUX18)
Figure 10-36. Pin Multiplexing Control 18 Register (PINMUX18)
31
28
27
24
23
20
19
16
PINMUX18_31_28
PINMUX18_27_24
PINMUX18_23_20
PINMUX18_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX18_15_12
PINMUX18_11_8
PINMUX18_7_4
PINMUX18_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
Bit
31-28
Field
Value
PINMUX18_31_28
MMCSD1_DAT[6]/PRU1_R30[6]/GP8[10]/PRU1_R31[7] Control
0
Selects Function PRU1_R31[7]
1h
Selects Function MMCSD1_DAT[6]
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX18_27_24
Reserved
X
Selects Function PRU1_R30[6]
O
Reserved
X
Selects Function GP8[10]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function MMCSD1_DAT[7]
4h
5h-7h
8h
9h-Fh
PINMUX18_23_20
X
Z
I/O
Reserved
X
Selects Function PRU1_R30[7]
O
Reserved
X
Selects Function GP8[11]
I/O
Reserved
X
PRU0_R30[22]/PRU1_R30[8]/UPP_CHB_WAIT/GP8[12]/PRU1_R31[24] Control
0
Selects Function PRU1_R31[24]
I
1h
Selects Function PRU0_R30[22]
O
2h
Selects Function PRU1_R30[8]
O
3h
Reserved
4h
Selects Function UPP_CHB_WAIT
5h-7h
8h
9h-Fh
(1)
I
I/O
MMCSD1_DAT[7]/PRU1_R30[7]/GP8[11] Control
2h-3h
23-20
Type (1)
Description
X
I/O
Reserved
X
Selects Function GP8[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX18_19_16
PRU0_R30[23]/MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13]/PRU1_R31[25]
Control
0
Selects Function PRU1_R31[25]
I
1h
Selects Function PRU0_R30[23]
O
2h
Selects Function MMCSD1_CMD
I/O
3h
Reserved
4h
Selects Function UPP_CHB_ENABLE
5h-7h
8h
9h-Fh
15-12
PINMUX18_15_12
Selects Function GP8[13]
I/O
Reserved
X
Selects Function PRU1_R31[26]
I
Selects Function PRU0_R30[24]
O
2h
Selects Function MMCSD1_CLK
O
3h
Reserved
4h
Selects Function UPP_CHB_START
PINMUX18_11_8
X
I/O
Reserved
X
Selects Function GP8[14]
I/O
Reserved
X
PRU0_R30[25]/MMCSD1_DAT[0]/UPP_CHB_CLOCK/GP8[15]/PRU1_R31[27]
Control
0
Selects Function PRU1_R31[27]
I
1h
Selects Function PRU0_R30[25]
O
2h
Selects Function MMCSD1_DAT[0]
I/O
3h
Reserved
4h
Selects Function UPP_CHB_CLOCK
5h-7h
8h
9h-Fh
PINMUX18_7_4
X
I/O
Reserved
X
Selects Function GP8[15]
I/O
Reserved
X
VP_DOUT[8]/UPP_XD[0]/GP7[0]/BOOT[0] Control
0
Selects Function BOOT[0]
I
1h
Selects Function VP_DOUT[8]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX18_3_0
Reserved
X
Selects Function UPP_XD[0]
I/O
Reserved
X
Selects Function GP7[0]
I/O
Reserved
X
VP_DOUT[9]/UPP_XD[1]/GP7[1]/BOOT[1] Control
0
Selects Function BOOT[1]
I
1h
Selects Function VP_DOUT[9]
O
Reserved
X
2h-3h
4h
5h-7h
8h
9h-Fh
250
X
0
8h
3-0
Reserved
1h
9h-Fh
7-4
X
I/O
PRU0_R30[24]/MMCSD1_CLK/UPP_CHB_START/GP8[14]/PRU1_R31[26]
Control
5h-7h
11-8
Type (1)
Description
Selects Function UPP_XD[1]
I/O
Reserved
X
Selects Function GP7[1]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.20 Pin Multiplexing Control 19 Register (PINMUX19)
Figure 10-37. Pin Multiplexing Control 19 Register (PINMUX19)
31
28
27
24
23
20
19
16
PINMUX19_31_28
PINMUX19_27_24
PINMUX19_23_20
PINMUX19_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX19_15_12
PINMUX19_11_8
PINMUX19_7_4
PINMUX19_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
Bit
31-28
Field
Value
PINMUX19_31_28
GP8[0] Control. GP8[0] is initially configured as a reserved function after reset and
will not be in a predictable state. This signal will only be stable after the GPIO
configuration for this pin has been completed. You should carefully consider the
system implications of this pin being in an unknown state after reset.
0-7h
8h
9h-Fh
27-24
PINMUX19_27_24
1h-7h
8h
9h-Fh
PINMUX19_23_20
I/O
Reserved
X
Selects Function PRU1_R31[28]
I
Reserved
X
Selects Function GP6[0]
I/O
Reserved
X
0
Selects Function PRU1_R31[1]
I
1h
Selects Function VP_CLKOUT3
O
4h
5h-7h
8h
9h-Fh
PINMUX19_19_16
Reserved
X
Selects Function PRU1_R30[0]
O
Reserved
X
Selects Function GP6[1]
I/O
Reserved
X
VP_CLKIN3/MMCSD1_DAT[1]/PRU1_R30[1]/GP6[2]/PRU1_R31[2] Control
0
Selects Function PRU1_R31[2]
1h
Selects Function VP_CLKIN3
2h
Selects Function MMCSD1_DAT[1]
3h
Reserved
X
4h
Selects Function PRU1_R30[1]
O
Reserved
X
5h-7h
8h
9h-Fh
(1)
X
Selects Function GP8[0]
VP_CLKOUT3/PRU1_R30[0]/GP6[1]/PRU1_R31[1] Control
2h-3h
19-16
Reserved
GP6[0]/PRU1_R31[28] Control
0
23-20
Type (1)
Description
I
I
I/O
Selects Function GP6[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX19_15_12
VP_CLKOUT2/MMCSD1_DAT[2]/PRU1_R30[2]/GP6[3]/PRU1_R31[3] Control
0
Selects Function PRU1_R31[3]
I
1h
Selects Function VP_CLKOUT2
O
2h
Selects Function MMCSD1_DAT[2]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[2]
O
5h-7h
8h
9h-Fh
11-8
PINMUX19_11_8
I/O
Reserved
X
Selects Function PRU1_R31[4]
1h
Selects Function VP_CLKIN2
2h
Selects Function MMCSD1_DAT[3]
3h
Reserved
X
4h
Selects Function PRU1_R30[3]
O
9h-Fh
PINMUX19_7_4
I
I
I/O
Reserved
X
Selects Function GP6[4]
I/O
Reserved
X
MMCSD1_DAT[4]/PRU1_R30[4]/GP8[8]/PRU1_R31[5] Control
0
Selects Function PRU1_R31[5]
1h
Selects Function MMCSD1_DAT[4]
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX19_3_0
I
I/O
Reserved
X
Selects Function PRU1_R30[4]
O
Reserved
X
Selects Function GP8[8]
I/O
Reserved
X
MMCSD1_DAT[5]/PRU1_R30[5]/GP8[9]/PRU1_R31[6] Control
0
Selects Function PRU1_R31[6]
1h
Selects Function MMCSD1_DAT[5]
2h-3h
4h
5h-7h
8h
9h-Fh
252
X
Selects Function GP6[3]
0
8h
3-0
Reserved
VP_CLKIN2/MMCSD1_DAT[3]/PRU1_R30[3]/GP6[4]/PRU1_R31[4] Control
5h-7h
7-4
Type (1)
Description
I
I/O
Reserved
X
Selects Function PRU1_R30[5]
O
Reserved
X
Selects Function GP8[9]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.11 Suspend Source Register (SUSPSRC)
The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals
that support emulation suspend. A value of 1 (default) for a SUSPSRC bit corresponding to the peripheral,
indicates that the DSP emulator controls the peripheral's emulation suspend signal. You should maintain
this register with its default values.
The SUSPSRC is shown in Figure 10-38 and described in Table 10-42.
Figure 10-38. Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
Reserved
Reserved
TIMER64P_2SRC
TIMER64P_1SRC
TIMER64P_0SRC
Reserved
Reserved
EPWM1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
23
22
21
20
19
18
17
16
EPWM0SRC
SPI1SRC
SPI0SRC
UART2SRC
UART1SRC
UART0SRC
I2C1SRC
I2C0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
Reserved
VPIFSRC
Reserved
HPISRC
Reserved
Reserved
USB0SRC
MCBSP1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
MCBSP0SRC
PRUSRC
EMACSRC
UPPSRC
TIMER64P_3SRC
ECAP2SRC
ECAP1SRC
ECAP0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions
Bit
31-30
29
28
27
26-25
24
23
22
21
Field
Reserved
Value
1
TIMER64P_2SRC
Reserved. Write the default value to all bits when modifying this register.
Timer2 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64P_1SRC
Timer1 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64P_0SRC
Reserved
Description
Timer0 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
EPWM1SRC
EPWM1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EPWM0SRC
EPWM0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
SPI1SRC
SPI1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
SPI0SRC
SPI0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
Field
20
UART2SRC
19
18
17
16
13
Reserved
12
HPISRC
11-10
Reserved
9
USB0SRC
5
4
3
254
DSP is the source of the emulation suspend.
UART1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
UART0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
I2C1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
I2C0SRC
VPIFSRC
6
No emulation suspend.
1
I2C1SRC
Reserved
7
0
UART0SRC
14
Description
UART2 Emulation Suspend Source.
UART1SRC
15
8
Value
I2C0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
VPIF Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
HPI Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
USB0 (USB 2.0) Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
MCBSP1SRC
McBSP1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
MCBSP0SRC
McBSP0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
PRUSRC
PRU Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EMACSRC
EMAC Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
UPPSRC
uPP Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64P_3SRC
Timer3 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
2
1
0
Field
Value
ECAP2SRC
Description
ECAP2 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP1SRC
ECAP1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP0SRC
ECAP0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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10.5.12 Chip Signal Register (CHIPSIG)
The interrupts to the DSP can be generated by setting one of the two CHIPSIG[3-2] bits or an NMI
interrupt by setting the CHIPSIG[4] bit in the chip signal register (CHIPSIG). Writing a 1 to these bits sets
the interrupts, writing a 0 has no effect. Reads return the value of these bits and can also be used as
status bits. The CHIPSIG is shown in Figure 10-39 and described in Table 10-43.
Figure 10-39. Chip Signal Register (CHIPSIG)
31
16
Reserved
R-0
15
4
3
2
Reserved
5
CHIPSIG4
CHIPSIG3
CHIPSIG2
Reserved
1
0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-43. Chip Signal Register (CHIPSIG) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1-0
256
Value
0
Reserved
Asserts DSP NMI interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG3
Asserts SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG2
Reserved
Description
Asserts SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Asserts interrupt
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.13 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 10-40 and described in Table 10-44.
For more information on DSP interrupts, see the DSP Subsystem chapter.
Figure 10-40. Chip Signal Clear Register (CHIPSIG_CLR)
31
16
Reserved
R-0
15
4
3
2
Reserved
5
CHIPSIG4
CHIPSIG3
CHIPSIG2
Reserved
1
0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1-0
Value
0
Reserved
Clears DSP NMI interrupt.
0
No effect
1
Clears interrupt
CHIPSIG3
Clears SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG2
Reserved
Description
Clears SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Clears interrupt
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.14 Chip Configuration 0 Register (CFGCHIP0)
The chip configuration 0 register (CFGCHIP0) controls the following functions:
• PLL Controller 0 memory-mapped register lock: Used to lock out writes to the PLLC0 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC0 register space.
• EDMA3_0 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP0
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_0 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
The CFGCHIP0 is shown in Figure 10-41 and described in Table 10-45.
Figure 10-41. Chip Configuration 0 Register (CFGCHIP0)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PLL_MASTER_LOCK
EDMA30TC1DBS
EDMA30TC0DBS
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
Bit
31-5
4
3-2
1-0
258
Field
Reserved
Value
0
PLL_MASTER_LOCK
Description
Reserved.
PLLC0 MMRs lock.
0
PLLC0 MMRs are freely accessible.
1
All PLLC0 MMRs are locked.
EDMA30TC1DBS
EDMA3_0_TC1 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
EDMA30TC0DBS
EDMA3_0_TC0 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
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10.5.15 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• eCAP0/1/2 event input source: Allows using McASP0 TX/RX events or various EMAC TX/RX
threshold, pulse, or miscellaneous interrupt events as eCAP event input sources.
• EDMA3_1 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP1
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_1 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
• McASP0 AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP0 AMUTEIN signal.
The CFGCHIP1 is shown in Figure 10-42 and described in Table 10-46.
Figure 10-42. Chip Configuration 1 Register (CFGCHIP1)
31
27
15
26
22
21
17
16
CAP2SRC
CAP1SRC
CAP0SRC
HPIBYTEAD
R/W-0
R/W-0
R/W-0
R/W-0
14
13
12
11
8
HPIENA
EDMA31TC0DBS
TBCLKSYNC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
7
4
3
0
Reserved
AMUTESEL0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
Bit
31-27
Field
Value
CAP2SRC
Selects the eCAP2 module event input.
0
eCAP2 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
CAP1SRC
Reserved
Selects the eCAP1 module event input.
0
eCAP1 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
Reserved
7h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
260
Reserved
7h
13h-1Fh
26-22
Description
Reserved
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Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued)
Bit
21-17
Field
Value
CAP0SRC
Selects the eCAP0 module event input.
0
eCAP0 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
15
14-13
12
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
HPIBYTEAD
HPI Byte/Word Address Mode select.
Host address is a word address.
1
Host address is a byte address.
HPI Enable Bit.
0
HPI is disabled.
1
HPI is enabled.
EDMA31TC0DBS
EDMA3_1_TC0 Default Burst Size.
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
TBCLKSYNC
Reserved
3-0
AMUTESEL0
Reserved
0
HPIENA
11-4
Reserved
7h
13h-1Fh
16
Description
eHRPWM Module Time Base Clock Synchronization. Allows you to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
0
Time base clock (TBCLK) within each enabled eHRPWM module is stopped.
1
All enabled eHRPWM module clocks are started with the first rising edge of TBCLK aligned. For
perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each eHRPWM
module must be set identically.
0
Reserved. Write the default value to all bits when modifying this register.
Selects the source of McASP0 AMUTEIN signal.
0
Drive McASP0 AMUTEIN signal low.
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
Reserved
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10.5.16 Chip Configuration 2 Register (CFGCHIP2)
The chip configuration 2 register (CFGCHIP2) controls the following functions:
• USB2.0 OTG PHY
The CFGCHIP2 is shown in Figure 10-43 and described in Table 10-47.
Figure 10-43. Chip Configuration 2 Register (CFGCHIP2)
31
24
Reserved
R-0
23
18
15
14
17
16
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
R-0
R-0
R-0
12
11
10
9
8
RESET
USB0OTGMODE
13
Reserved
USB0PHYCLKMUX
USB0PHYPWDN
USB0OTGPWRDN
USB0DATPOL
R/W-1
R/W-3h
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
3
7
6
5
4
Reserved
USB0PHY_PLLON
USB0SESNDEN
USB0VBDTCTEN
USB0REF_FREQ
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
Bit
31-18
17
16
15
14-13
Field
Reserved
262
Clock is not present, power is not good, and PLL has not locked.
1
Clock is present, power is good, and PLL has locked.
Status of USB2.0 PHY VBUS sense.
0
PHY is not sensing voltage presence on the VBUS pin.
1
PHY is sensing voltage presence on the VBUS pin.
USB2.0 PHY reset.
0
Not in reset.
1
USB2.0 PHY in reset.
USB0OTGMODE
USB0PHYCLKMUX
Reserved
0
RESET
Reserved
Description
Status of USB2.0 PHY.
USB0VBUSSENSE
11
9
0
USB0PHYCLKGD
12
10
Value
USB2.0 OTG subsystem mode.
0
No override. PHY drive signals to controller based on its comparators for VBUS and ID pins.
1h
Override phy values to force USB host operation.
2h
Override phy values to force USB device operation.
3h
Override phy values to force USB host operation with VBUS low.
0
Reserved. Write the default value when modifying this register.
USB2.0 PHY reference clock input mux.
0
USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
1
USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL.
USB0PHYPWDN
USB2.0 PHY operation state control.
0
USB2.0 PHY is enabled and is in operating state (normal operation).
1
USB2.0 PHY is disabled and powered down.
USB0OTGPWRDN
USB2.0 OTG subsystem (SS) operation state control.
0
OTG SS is enabled and is in operating state (normal operation).
1
OTG SS is disabled and is powered down.
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Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions (continued)
Bit
8
Field
7
Reserved
6
USB0PHY_PLLON
5
4
3-0
Value
USB0DATPOL
Description
USB2.0 differential data lines polarity selector.
0
Differential data polarities are inverted (USB_DP is connected to D- and USB_DM is
connected to D+).
1
Differential data polarity are not altered (USB_DP is connected to D+ and USB_DM is
connected to D-).
0
Reserved. Write the default value when modifying this register.
Drives USB2.0 PHY, allowing or preventing it from stopping the 48 MHz clock during
USB SUSPEND.
0
USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND.
1
USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND
USB0SESNDEN
USB2.0 Session End comparator enable.
0
Session End comparator is disabled.
1
Session End comparator is enabled.
USB0VBDTCTEN
USB2.0 VBUS line comparators enable.
0
All VBUS line comparators are disabled.
1
All VBUS line comparators are enabled.
USB0REF_FREQ
USB2.0 PHY reference clock input frequencies.
0
Reserved
1h
12 MHz
2h
24 MHz
3h
48 MHz
4h
19.2 MHz
5h
38.4 MHz
6h
13 MHz
7h
26 MHz
8h
20 MHz
9h
40 MHz
Ah-Fh
Reserved
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10.5.17 Chip Configuration 3 Register (CFGCHIP3)
The chip configuration 3 register (CFGCHIP3) controls the following peripheral/module functions:
• EMAC MII/RMII Mode Select.
• uPP Clock Source Control: Allows control for the source of the uPP 2x transmit clock.
• PLL Controller 1 memory-mapped register lock: Used to lock out writes to the PLLC1 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC1 register space.
• ASYNC3 Clock Source Control: Allows control for the source of the ASYNC3 clock.
• PRU Event Input Select.
• DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.5) hardware clock divider is provided to generate
133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this
clock divider.
• EMIFA Module Clock Source Control: Allows control for the source of the EMIFA module clock.
The CFGCHIP3 is shown in Figure 10-44 and described in Table 10-48.
Figure 10-44. Chip Configuration 3 Register (CFGCHIP3)
31
16
Reserved
R-0
15
9
8
Reserved
RMII_SEL
R/W-7Fh
R/W-1
7
6
5
4
3
2
1
0
Reserved
UPP_TX_CLKSRC
PLL1_MASTER_LOCK
ASYNC3_CLKSRC
PRUEVTSEL
DIV45PENA
EMA_CLKSRC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-9
Reserved
7Fh
8
RMII_SEL
7
Reserved
6
UPP_TX_CLKSRC
5
4
3
264
Description
Reserved
Reserved. Write the default value to all bits when modifying this register.
EMAC MII/RMII mode select.
0
MII mode
1
RMII mode
0
Reserved. Write the default value when modifying this register.
Clock source for uPP 2x transmit clock.
0
Clock driven by ASYNC3.
1
Clock driven by external signal, 2xTXCLK.
PLL1_MASTER_LOCK
PLLC1 MMRs lock.
0
PLLC1 MMRs are freely accessible.
1
All PLLC1 MMRs are locked.
ASYNC3_CLKSRC
Clock source for ASYNC3.
0
Clock driven by PLL0_SYSCLK2.
1
Clock driven by PLL1_SYSCLK2.
PRUEVTSEL
PRU event input select.
0
Normal mode
1
Alternate mode
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Table 10-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions (continued)
Bit
2
1
0
Field
Value
DIV45PENA
Description
Controls the fixed DIV4.5 divider in the PLL controller.
0
Divide by 4.5 is disabled.
1
Divide by 4.5 is enabled.
EMA_CLKSRC
Clock source for EMIFA clock domain.
Reserved
0
Clock driven by PLL0_SYSCLK3
1
Clock driven by DIV4.5 PLL output
0
Reserved. Write the default value when modifying this register.
10.5.18 Chip Configuration 4 Register (CFGCHIP4)
The chip configuration 4 register (CFGCHIP4) is used for clearing the AMUNTEIN signal for McASP0.
Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0, if it was
previously set; reads always return a value of 0. The CFGCHIP4 is shown in Figure 10-45 and described
in Table 10-49.
Figure 10-45. Chip Configuration 4 Register (CFGCHIP4)
31
16
Reserved
R-0
15
8
7
1
0
Reserved
Reserved
AMUTECLR0
R/W-FFh
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
Reserved
FFh
Reserved. Write the default value to all bits when modifying this register.
7-1
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
0
AMUTECLR0
Reserved
Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1.
0
No effect
1
Clears interrupt
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10.5.19 VTP I/O Control Register (VTPIO_CTL)
The VTP I/O control register (VTPIO_CTL) is used to control the calibration of the DDR2/mDDR memory
controller I/Os with respect to voltage, temperature, and process (VTP). The voltage, temperature, and
process information is used to control the IO's output impedance. The VTPIO_CTL is shown in Figure 1046 and described in Table 10-50.
Figure 10-46. VTP I/O Control Register (VTPIO_CTL)
31
24
Reserved
R-0
23
19
18
17
16
Reserved
VREFEN
VREFTAP
R-0
R/W-0
R/W-0
15
14
13
12
9
READY
IOPWRDN
CLKRZ
Reserved
PWRSAVE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
5
7
6
LOCK
POWERDN
D
3
F
R/W-0
R/W-1
R/W-6h
R/W-7h
8
2
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions
Bit
Field
31-19
Reserved
18
VREFEN
17-16
Value
0
Internal DDR I/O Vref enable.
Connected to pad, external reference.
1
Reserved
VREFTAP
Selection for internal reference voltage level.
1h-3h
14
13
12-9
8
7
6
266
Reserved
0
0
15
Description
READY
Vref = 50.0% of VDDS
Reserved
VTP Ready status.
0
VTP is not ready.
1
VTP is ready.
IOPWRDN
Power down enable for DDR input buffer.
0
Disable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
1
Enable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
CLKRZ
0
VTP clear. Write 0 to clear VTP flops.
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
PWRSAVE
VTP power save mode. Turn off power to the external resistor when it is not needed. The
PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0.
0
Disable power save mode.
1
Enable power save mode.
LOCK
VTP impedance lock. Lock impedance value so that the VTP controller can be powered down.
0
Unlock impedance.
1
Lock impedance.
POWERDN
VTP power down. Power down the VTP controller. The PWRSAVE bit setting is only valid when
the POWERDN bit is cleared to 0.
0
Disable power down.
1
Enable power down.
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Table 10-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions (continued)
Bit
Field
5-3
D
Value
Drive strength control bit.
0-5h
2-0
Description
Reserved
6h
100% drive strength
7h
Reserved
F
Digital filter control bit.
0-6h
7h
Reserved
Digital filter is enabled.
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10.5.20 DDR Slew Register (DDR_SLEW)
The DDR slew register (DDR_SLEW) reflects the DDR I/O timing as programmed in the device eFuse.
The CMOSEN field configures the DDR I/O cells into an LVCMOS buffer (this makes it mDDR
compatible). The DDR_SLEW is shown in Figure 10-47 and described in Table 10-51.
Figure 10-47. DDR Slew Register (DDR_SLEW)
31
16
Reserved
R-0
15
12
7
11
10
9
8
Reserved
ODT_TERMON
ODT_TERMOFF
R-0
R/W-0
R/W-0
5
4
Reserved
6
DDR_PDENA
CMOSEN
3
DDR_DATASLEW
2
1
DDR_CMDSLEW
0
R-0
R/W-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-51. DDR Slew Register (DDR_SLEW) Field Descriptions
Bit
Field
31-12
Reserved
11-10
ODT_TERMON
Value
0
0
ODT_TERMOFF
5
4
3-2
Reserved
No termination
Reserved
0
Reserved
DDR_PDENA
Enables pull downs for mDDR mode (should be disabled for DDR2).
0
Pull downs are disabled. Disable pull downs when using DDR2.
1
Pull downs are enabled. Enable pull downs when using mDDR.
CMOSEN
Selects mDDR LVCMOS RX / SSTL18 differential RX.
0
SSTL Receiver. Select SSTL when using DDR2.
1
LVCMOS Receiver. Select LVCMOS when using mDDR.
DDR_DATASLEW
Slew rate mode control status for data macro. Slew rate control is not supported on this
device.
0
DDR_CMDSLEW
Slew rate control is off.
Reserved
Slew rate mode control status for command macro. Slew rate control is not supported on
this device.
0
1h-3h
268
Reserved
1h-3h
1h-3h
1-0
No termination
Controls Thevenin termination mode while I/O is not in read or write mode. Termination is
not supported on this device.
0
7-6
Reserved
Controls Thevenin termination mode while I/O is in read or write mode. Termination is not
supported on this device.
1h-3h
9-8
Description
Slew rate control is off.
Reserved
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10.5.21 Deep Sleep Register (DEEPSLEEP)
The deep sleep register (DEEPSLEEP) control the Deep Sleep logic. See your device-specific data
manual and the Boot Considerations chapter for details on boot and configuration settings. The
DEEPSLEEP is shown in Figure 10-48 and described in Table 10-52.
Figure 10-48. Deep Sleep Register (DEEPSLEEP)
31
30
SLEEPENABLE
SLEEPCOMPLETE
29
Reserved
16
R/W-0
R-0
R-0
15
0
SLEEPCOUNT
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-52. Deep Sleep Register (DEEPSLEEP) Field Descriptions
Bit
Field
31
SLEEPENABLE
30
Value
Deep sleep enable. The software must clear this bit to 0 when the device is awakened from
deep sleep.
0
Device is in normal operating mode; DEEPSLEEP pin has no effect.
1
Deep sleep mode is enabled; setting DEEPSLEEP pin low initiates oscillator shut down.
SLEEPCOMPLETE
29-16
Reserved
15-0
SLEEPCOUNT
Description
Deep sleep complete. Once the deep sleep process starts, the software must poll the
SLEEPCOMPLETE bit; when the SLEEPCOMPLETE bit is read as 1, the software should
clear the SLEEPENABLE bit and continue operation.
0
SLEEPCOUNT delay is not complete.
1
SLEEPCOUNT delay is complete.
0
Reserved
0-FFFFh
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16
bits are tied directly to the counter in the Deep Sleep logic.
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10.5.22 Pullup/Pulldown Enable Register (PUPD_ENA)
The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin
group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 10-49 and
described in Table 10-53.
Figure 10-49. Pullup/Pulldown Enable Register (PUPD_ENA)
31
0
PUPDENA[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-53. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions
Bit
31-0
Field
Value
PUPDENA[n]
Description
Enables internal pull-up or pull-down functionality for pin group CP[n]. See your devicespecific data manual for pin group information. The internal pull-up or pull-down functionality
selection for bit position n in PUPD_ENA is set in the same bit position n of the pullup/pulldown
select register (PUPD_SEL).
0
Internal pull-up or pull-down functionality for pin group n is disabled.
1
Internal pull-up or pull-down functionality for pin group n is enabled.
10.5.23 Pullup/Pulldown Select Register (PUPD_SEL)
The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for
the pin group n defined in your device-specific data manual. The PUPD_SEL is shown in Figure 10-50 and
described in Table 10-54 and Table 10-55.
NOTE: The PUPD_SEL settings are not active until the device is out of reset. During reset, all of the
CP[n] pins are pulled down. If the application requires a pull-up during reset, an external pullup should be used.
Figure 10-50. Pullup/Pulldown Select Register (PUPD_SEL)
31
0
PUPDSEL[n]
R/W-C3FF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-54. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions
Bit
31-0
270
Field
Value
PUPDSEL[n]
Description
Selects between the internal pull-up or pull-down functionality for pin group CP[n]. See your
device-specific data manual for pin group information. The selection for bit position n in PUPD_SEL
is only valid when the same bit position n is set in the pullup/pulldown enable register
(PUPD_ENA).
0
Internal pull-down functionality for pin group n is disabled.
1
Internal pull-up functionality for pin group n is enabled.
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Table 10-55. Pullup/Pulldown Select Register (PUPD_SEL) Default Values
Default
Value
Bit
Field
31
PUPDSEL[31]
1
Description
Pin Group CP[31] is configured for pull-up by default.
30
PUPDSEL[30]
1
Pin Group CP[30] is configured for pull-up by default.
29
PUPDSEL[29]
0
Pin Group CP[29] is configured for pull-down by default.
28
PUPDSEL[28]
0
Pin Group CP[28] is configured for pull-down by default.
27
PUPDSEL[27]
0
Pin Group CP[27] is configured for pull-down by default.
26
PUPDSEL[26]
0
Pin Group CP[26] is configured for pull-down by default.
25
PUPDSEL[25]
1
Pin Group CP[25] is configured for pull-up by default.
24
PUPDSEL[24]
1
Pin Group CP[24] is configured for pull-up by default.
23
PUPDSEL[23]
1
Pin Group CP[23] is configured for pull-up by default.
22
PUPDSEL[22]
1
Pin Group CP[22] is configured for pull-up by default.
21
PUPDSEL[21]
1
Pin Group CP[21] is configured for pull-up by default.
20
PUPDSEL[20]
1
Pin Group CP[20] is configured for pull-up by default.
19
PUPDSEL[19]
1
Pin Group CP[19] is configured for pull-up by default.
18
PUPDSEL[18]
1
Pin Group CP[18] is configured for pull-up by default.
17
PUPDSEL[17]
1
Pin Group CP[17] is configured for pull-up by default.
16
PUPDSEL[16]
1
Pin Group CP[16] is configured for pull-up by default.
15
PUPDSEL[15]
1
Pin Group CP[15] is configured for pull-up by default.
14
PUPDSEL[14]
1
Pin Group CP[14] is configured for pull-up by default.
13
PUPDSEL[13]
1
Pin Group CP[13] is configured for pull-up by default.
12
PUPDSEL[12]
1
Pin Group CP[12] is configured for pull-up by default.
11
PUPDSEL[11]
1
Pin Group CP[11] is configured for pull-up by default.
10
PUPDSEL[10]
1
Pin Group CP[10] is configured for pull-up by default.
9
PUPDSEL[9]
1
Pin Group CP[9] is configured for pull-up by default.
8
PUPDSEL[8]
1
Pin Group CP[8] is configured for pull-up by default.
7
PUPDSEL[7]
1
Pin Group CP[7] is configured for pull-up by default.
6
PUPDSEL[6]
1
Pin Group CP[6] is configured for pull-up by default.
5
PUPDSEL[5]
1
Pin Group CP[5] is configured for pull-up by default.
4
PUPDSEL[4]
1
Pin Group CP[4] is configured for pull-up by default.
3
PUPDSEL[3]
1
Pin Group CP[3] is configured for pull-up by default.
2
PUPDSEL[2]
1
Pin Group CP[2] is configured for pull-up by default.
1
PUPDSEL[1]
1
Pin Group CP[1] is configured for pull-up by default.
0
PUPDSEL[0]
1
Pin Group CP[0] is configured for pull-up by default.
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10.5.24 RXACTIVE Control Register (RXACTIVE)
The RXACTIVE control register (RXACTIVE) enables or disables the LVCMOS receivers for the pin group
n defined in your device-specific data manual. The RXACTIVE is shown in Figure 10-51 and described in
Table 10-56.
Figure 10-51. RXACTIVE Control Register (RXACTIVE)
31
0
RXACTIVE[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-56. RXACTIVE Control Register (RXACTIVE) Field Descriptions
Bit
31-0
272
Field
Value
RXACTIVE[n]
Description
Enables the LVCMOS receivers on pin group n. See your device-specific data manual for pin group
information. Receivers should only be disabled if the associated pin group is not being used.
0
LVCMOS receivers for pin group n are disabled.
1
LVCMOS receivers for pin group n are enabled.
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Chapter 11
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Boot Considerations
Topic
11.1
...........................................................................................................................
Page
Introduction ..................................................................................................... 274
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11.1 Introduction
This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• HPI boot
• I2C0/I2C1 boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI0/SPI1 boot
– Serial Flash (Master Mode)
– Serial EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0/1/2 boot
– External Host
• MMC/SD0 boot
See Using the TMS320C6748/C6746/C6742 Bootloader Application Report (SPRAAT2) for more details
on the ROM Boot Loader, a list of boot pins used, and the complete list of supported boot modes.
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Chapter 12
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Programmable Real-Time Unit Subsystem (PRUSS)
Topic
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
...........................................................................................................................
Overview .........................................................................................................
Description ......................................................................................................
Constants Table ...............................................................................................
PRU Module Interface .......................................................................................
Instruction Set..................................................................................................
Instruction Formats ..........................................................................................
PRU Interrupt Controller ....................................................................................
Registers .........................................................................................................
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276
278
279
280
281
284
302
309
275
Overview
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The Programmable Real-Time Unit Subsystem (PRUSS) consists of:
• Two programmable real-time units (PRU0 and PRU1) and their associated memories.
• An interrupt controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The two PRUs
can also work in coordination with the device level host CPU. This is determined by the nature of the
program that is loaded into the two PRUs instruction memory. Several different signaling mechanisms are
available between the two PRUs and the device level host CPU.
The two PRUs are optimized for performing embedded tasks that require manipulation of packed memorymapped data structures, handling of system events that have tight real-time constraints and interfacing
with systems external to the device.
12.1 Overview
The PRU is a optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the DSP/SoC. The PRU is both very small and very efficient at handling such tasks.
The major attributes of the PRU are as follows:
Attribute
Value
IO Architecture
Load / Store
Data Flow Architecture
Register to Register
Core Level Bus Architecture
Type
4-Bus Harvard (1 Instruction, 3 Data)
Instruction I/F
32-Bit
Memory I/F 0
32-Bit
Memory I/F 1
32-Bit
Issue Type
Scalar
Pipelining
None
Ordering
In-order
ALU Type
Unsigned Integer
Execution Model
Registers
276
General Purpose (GP)
30 (R1 – R30)
External Status
1 (R31)
GP / Indexing
1 (R0)
Addressability
Bit, Byte (8-bit), Halfword (16-bit), Word (32-bit), Pointer
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Attribute
Value
Addressing Modes
Load Immediate
16-bit Immediate
Register Base + Register Offset
Register Base + 8-bit Immediate Offset
Register Base with auto increment / decrement
Load / Store – Memory
Constant Table Base + Register Offset
Constant Table Base + 8-bit Immediate Offset
Constant Table Base with auto increment / decrement
Data Path Width
32-Bits
Instruction Width
32-Bits
Accessibility to Internal PRU
Structures
Provides 32-bit Slave with 3 regions:
• Instruction RAM
• Control / Status registers
• Debug access to internal registers (R0-R31) and constant table
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12.2 Description
The processor is based on a four bus architecture which allows instructions to be fetched and executed
concurrently with data transfers. Additionally, an input is provided in order to allow external status
information to be reflected in the internal processor status register. The figure below shows a block
diagram of the processing element and the associated instruction RAM/ROM that contains the code that is
to be executed.
Figure 12-1. PRU Block Diagram
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12.3 Constants Table
The PRU Constants Table is a structure connected to a dedicated interface on the PRU core within the
PRU that is used to provide the base address for the Load Burst Constant + Offset (LBCO) and Store
Burst Constant + Offset (SBCO) instructions. The PRU Constants Table is provided in order to maximize
the usage of the PRU register file for embedded processing applications by moving many of the commonly
used constant or deterministically calculated base addresses from the internal register file to an external
table. Since this table is accessed using a dedicated interface, no performance difference is realized
between the LBCO and LBBO or SBCO and SBBO instructions. The constants in the table are provided in
Table 2.
Table 12-1. Constants Table (1)
Entry #
(1)
Region Pointed To
Value [31:0]
0
PRU0/1 Local INTC
0x00004000
1
Timer64P0
0x01C20000
2
I2C0
0x01C22000
3
PRU0/1 Local Data
0x00000000
4
PRU1/0 Local Data
0x00002000
5
MMC/SD
0x01C40000
6
SPI0
0x01C41000
7
UART0
0x01C42000
8
McASP0 DMA
0x01D02000
9
Reserved
0x01D06000
10
Reserved
0x01D0A000
11
UART1
0x01D0C000
12
UART2
0x01D0D000
13
USB0
0x01E00000
14
USB1
0x01E25000
15
UHPI Config
0x01E10000
16
Reserved
0x01E12000
17
I2C1
0x01E28000
18
EPWM0
0x01F00000
19
EPWM1
0x01F02000
20
Reserved
0x01F04000
21
ECAP0
0x01F06000
22
ECAP1
0x01F07000
23
ECAP2
0x01F08000
24
PRU0/1 Local Data
0x00000n00, n = c24_blk_index[3:0]
25
McASP0 Control
0x01D00n00, n = c25_blk_index[3:0]
26
Reserved
0x01D04000
27
Reserved
0x01D08000
28
DSP Megamodule RAM/ROM
0x11nnnn00, nnnn = c28_pointer[15:0]
29
EMIFA SDRAM
0x40nnnn00, nnnn = c29_pointer[15:0]
30
Shared RAM
0x80nnnn00, nnnn = c30_pointer[15:0]
31
mDDR/DDR2 Data
0xC0nnnn00, nnnn = c31_pointer[15:0]
These constants cannot be used due to memory map restrictions.
1. Constants not in this table can be created ’on the fly’ by two consecutive LDI
#16 instructions. These constants are just ones that are expected to be
commonly used, enough so to be hard-coded into the PRU constants table.
2. Constants table entries 24 through 31 are not fully hard-coded, but contain a
programmable bitfield (ex. c24_blk_index[3:0]) that is programmable through
the PRU control register space (0x01C3_7000 - 0x01C3_73FF for PRU0 and
0x01C3_7800 - 0x01C3_7BFF for PRU1).
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12.4 PRU Module Interface
12.4.1 Event Out Mapping (R31): PRU System Events
PRU Event Interface directly feeds pulsed event information out of the PRU’s internal ALU. This provides
the interface logic between the PRU R31 event_out[5:0] and the system interrupts for the PRUSS Interrupt
controller(INTC).
Bits
31-6
5
4-0
Name
Description
Reserved
pruX_vec_valid
Valid strobe for vector output
pruX_vec[4:0]
Vector output
Writing a ’1’ to pruX_vec_valid (R31 bit 5) simultaneously with a channel number from 0 to 31 written to
pruX_vec[4:0] (R31 bits 4:0) creates a pulse on the output of the appropriate de-multiplexer output. For
example, writing ’100000’ will generate a pulse on demux channel 0, writing ’100001’ will generate a pulse
on demux channel 1, ... writing ’111111’ will generate a pulse on demux channel 31, and writing ’0xxxxx’
will not generate any pulse on the demux output. The demultiplexed values from both of the PRUs are
logically ORed together. The composite demultiplexed output channels 0 through 31 are connected to
system interrupts 32 through 63 respectively.
This allows the PRU to assert one of the systems interrupts 32-63 by writing to its own R31 register. The
system interrupt is used to either post a completion event to one of the host CPUs (ARM, DSP) or to
signal the other PRU. The host to be signaled is determined by the system interrupt to interrupt channel
mapping (programmable). Refer to Section 12.7 for more details.
12.4.2 Status Mapping (R31): Interrupt Events Input
The PRU Real Time Status Interface directly feeds information into register 31(R31) of the PRU’s internal
register file. The firmware on the PRU uses the status information to make decisions during execution.
The status interface is comprised of signals from different modules inside of the PRUSS which require
some level of interaction with the PRU. More details on the Host interrupts imported into bit 30 and 31 of
register R31 of both the PRUs is provided in the chapter 3, PRUSS Interrupt Controller (INTC).
Bits
Name
Description
31
pru_intr_in[1]
PRU Interrupt 1 from INTC
30
pru_intr_in[0]
PRU Interrupt 0 from INTC
pruX_r31_status[29:0]
Status inputs from primary input
29-0
12.4.3 General Purpose Inputs (R31)
The pruX_r31_status[29:0] are mapped out of the PRUSS and are brought out as general purpose input
pins. The values input to the pins "pruX_R31[29:0]" are reflected in the R31 register on bits [29:0] to be
used by the program running on the PRU. Each PRU of the PRUSS has a separate mapping to pins, so
that there are 60 total general purpose inputs to the PRUSS.
12.4.4 General Purpose Outputs (R30)
The pruX_r30[31:0] bits are exported out of the PRUSS and are brought out as general purpose output
pins. The values written to register R30 will be reflected on the general purpose output pins
"pruX_R30[31:0]" to be used by the program running on the PRU. Each PRU of the PRUSS has a
separate mapping to pins, so that there are 64 total general purpose outputs from the PRUSS.
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12.5 Instruction Set
The instruction set is divided into four major categories:
1. Instructions which move data in or out of the processors internal registers
2. Instructions which perform an arithmetic operation
3. Instructions which perform a logical operation
4. Instructions which control program flow
The following sections give a complete list and short description of all of the supported instructions. In
these descriptions, the following abbreviations are used:
Table 12-2. Abbreviations for Instruction Descriptions
Abbreviation
Description
Rs1
Source register 1 from the instruction
Op2
Operand 2 from the instruction – can be either a register (Rs2) or an 8-bit immediate
value
Rd
Destination register from the instruction
BrOff
WdCnt
CPI
Branch offset from the instruction – a 10-bit 2’s complement relative offset
Word count – the # of 32-bit data phases that occur in the burst on an external
memory interface
Clock Cycles Per Instruction
Table 12-3. Load/Store Instructions
Mnemonic
LDI
Instruction
Description
Load Immediate
Load 16-bit immediate value into internal register
CPI
1
LBBO
Load Burst, Base + Offset
Load variable length burst of bytes through one of the memory
interfaces into internal register(s) using a register as the base
address and a register or an 8-bit immediate as the offset
1 + WdCnt
(VBUS)
2 + WdCnt
(VBUSP)
SBBO
Store variable length burst of bytes through one of the memory
Store Burst, Base + Offset interfaces from internal register(s) using a register as the base
address and a register or 8-bit immediate as the offset
1 + WdCnt
LBCO
Load Burst, Constant +
Offset
Load variable length burst of bytes through one of the memory
interfaces into internal register(s) using an indexed constant as
the base address and a register or an 8-bit immediate as the
offset
1 + WdCnt
(VBUS)
2 + WdCnt
(VBUSP)
SBCO
Store Burst, Constant +
Offset
Store variable length burst of bytes through one of the memory
interfaces from internal register(s) using an indexed constant as
the base address and a register or 8-bit immediate as the offset
1 + WdCnt
Table 12-4. Arithmetic Instructions
Mnemonic
ADD
Instruction
Description
CPI
Integer Add
Adds Rs1 and Op2, writes result to Rd, and saves carry.
1
ADC
Integer Add With Carry
Adds Rs1, Op2 and the saved carry, writes result to Rd, and
saves carry.
1
SUB
Integer Subtract
Subtracts Op2 from Rs1 and writes result to Rd and saves carry
(borrow).
1
SUC
Integer Subtract With
Carry
Subtracts Op2 from Rs1 then subtracts the saved carry (borrow)
and writes result to Rd and saves carry (borrow).
1
RSB
Integer Reverse Subtract
Subtracts Rs1 from Op2 and writes result to Rd and saves carry
(borrow).
1
RSC
Interger Reverse Subtract
With Carry
Subtracts Rs1 from Op2 then subtracts the saved carry (borrow)
and writes result to Rd and saves carry (borrow).
1
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Table 12-5. Logical Instructions
Mnemonic
Description
CPI
Bitwise And
Bitwise ANDs Rs1 with Op2 and stores to Rd.
1
OR
Bitwise Or
Bitwise ORs Rs1 with Op2 and stores to Rd.
1
XOR
Bitwise Exclusive Or
Bitwise exclusive ORs Rs1 with Op2 and stores to Rd.
1
NOT
Bitwise Invert
Bitwise inverts Rs1 and stores to Rd.
1
LSR
Logical Shift Right
Shifts Rs1 right (with zero fill) by the value given in the 5 LSBs of
Op2 and stores to Rd.
1
LSL
Logical Shift Left
Shifts Rs1 left (with zero fill) by the value given in the 5 LSBs of
Op2 and stores to Rd.
1
MIN
Minimum
Compares Rs1 and Op2 and the smaller value is copied to Rd.
1
MAX
Maximum
Compares Rs1 and Op2 and the larger value is copied to Rd.
1
CLR
Clear Bit
Copies Rs1 to Rd but with a bit specied by the 5 LSBs of Op2
cleared during the copy.
1
SET
Set Bit
Copies Rs1 to Rd but with a bit specied by the 5 LSBs of Op2
set during the copy.
1
LMBD
Left-most Bit Detect
Scans Rs1 from the leftmost bit for a bit equal to bit 0 of Rs2.
When found, the bit number (0 to 31) is written to Rd. If not
found, the value 32 is written to Rd.
1
Scan Register File
Scans the register file for a byte pattern of a programmable
length (up to 4 bytes) with a programmable field count and field
stride.
The Op1 register contains 4 fields: Rn.b0 = offset in the register
file from R0.b0 to start scanning Rn.b1 = fc (field count), the
number of fields to scan Rn.b2 = fw (field width), the size in bytes
of the field to scan for (1, 2, or 4 bytes) Rn.b3 = fs (field stride),
the number of bytes to advance to the next field in the register
file (1 to 4 bytes)
Op1 is updated after the scan with the offset of the match (or
0xFF if no match) in Rn.b0, and the fields remaining in the scan
(including the matching field) in Rn.b1.
The Op2 is the field to scan for.
SCAN
282
Instruction
AND
Programmable Real-Time Unit Subsystem (PRUSS)
IF fw = fs
2+((fc*fw+3)/4)
ELSE 2+fc
This is a worst
case cycle
count. Matching
scans could take
fewer cycles.
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Table 12-6. Program Flow Control Instructions
Mnemonic
Instruction
Description
CPI
QBBS
Quick Branch – Bit Set
Adds BrOff to the program counter if the bit in Rs1 specified by
the 5 LSBs of Op2 is a 1
QBBC
Quick Branch –
Bit Clear
Adds BrOff to the program counter if the bit in Rs1 specified by
the 5 LSBs of Op2 is a 0
1
QBGT
Quick Branch –
Greater Than
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is greater than Rs1.
1
QBGE
Quick Branch –
Greater Than or Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is greater than or equal to Rs1.
1
QBLT
Quick Branch –
Less Than
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is less than Rs1.
1
QBLE
Quick Branch –
Less Than or Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is less than or equal to Rs1.
1
QBEQ
Quick Branch – Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is equal to Rs1.
1
QBNE
Quick Branch – Not Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is not equal to Rs1.
1
JMP
Unconditional Jump
Sets the program counter equal to either the contents of a
register or to a 16-bit immediate value
1
JAL
Unconditional Jump and
Link
Saves the current program counter into Rd and sets the program
counter equal to either the contents of a register or to a 16-bit
immediate value.
1
Halt Processor
Disables the PRU and does not increment the program counter.
When the PRU is re-enabled, it will continue processing at this
instruction.
1
Sleep
Pauses execution of the current program and disables the clock
for the majority of the core until a specified external event (unmasked status bit) is asserted.
1 to infinity
HALT
SLP
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12.6 Instruction Formats
A total of 7 different instruction formats are supported for the various operations. The following sections
describe the position, size, and function of each of the fields within the various formats.
Figure 12-2. Format 1a: (All Arithmetic and Logical Functions – Register Op2)
31
29
28
OP
15
24
IO
8
ALUOP
13
12
Rs1Sel
Rs1
23
21
20
Rs2Sel
7
16
Rs2
5
RdSel
4
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-7. Format 1a: (All Arithmetic and Logical Functions – Register Op2)
Bit
Field
Description
31-29
OP
0b000 = Specifies Format 1
28-25
ALUOP
0 = ADD
1 = ADC
2 = SUB
3 = SUC
4 = LSL
5 = LSR
6 = RSB
7 = RSC
8 = AND
9 = OR
10 = XOR
11 = NOT
12 = MIN
13 = MAX
14 = CLR
15 = SET
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0 – 31 = This field selects the register number which contains the second source operand
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand
284
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 2
bits 15:8 from the source register 2
bits 23:16 from the source register 2
bits 31:24 from the source register 2
bits 15:0 from the source register 2
bits 23:8 from the source register 2
bits 31:16 from the source register 2
bits 31:0 from the source register 2
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
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Table 12-7. Format 1a: (All Arithmetic and Logical Functions – Register Op2) (continued)
Bit
Field
Description
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-31 = This field selects the destination register number to which the result should be written.
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
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bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
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Instruction Formats
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Figure 12-3. Format 1b: (All Arithmetic and Logical Functions – Immediate Op2)
31
29
28
OP
15
24
IO
8
ALUOP
13
12
Rs1Sel
Rs1
23
16
Imm2
7
5
RdSel
4
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-8. Format 1b: (All Arithmetic and Logical Functions – Immediate Op2)
Bit
Field
Description
31-29
OP
0b000 = Specifies Format 1
28-25
ALUOP
0 = ADD
1 = ADC
2 = SUB
3 = SUC
4 = LSL
5 = LSR
6 = RSB
7 = RSC
8 = AND
9 = OR
10 = XOR
11 = NOT
12 = MIN
13 = MAX
14 = CLR
15 = SET
24
IO
1 = Op2 is an 8-bit immediate
23-16
Imm2
0-255 = This field is the 8-bit immediate value to be used as the source operand 2.
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-31 = This field selects the destination register number to which the result should be written.
286
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
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The following represents the 7 most significant bits of all format 2 instructions:
Figure 12-4. Format 2
31
29 28
OP
25 24
0
SUBOB
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-9. Format 2
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOB
0 = JMP
1 = JAL
2 = LDI
3 = LMBD
4 = SCAN
5 = HALT
6 = currently reserved for MVIx
7-13 = RESERVED
14 = currently reserved for RFI – Return From Interrupt
15 = SLP – Sleep
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Figure 12-5. Format 2a: (JMP,JAL – Register Op2)
31
29
28
OP
25
SUBOP
15
24
IO
8
RESERVED
23
21
20
Rs2Sel
7
16
Rs2
5
4
RdSel
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-10. Format 2a: (JMP,JAL – Register Op2)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOP
0 = JMP
1 = JAL
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0-31 = This field selects the register number which contains the value to be copied to the program
counter.
15-8
RESERVED
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-30 = This field selects the destination register number to which the pre-incremented program
counter should be written. Only written for JAL.
288
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 2
bits 15:8 from the source register 2
bits 23:16 from the source register 2
bits 31:24 from the source register 2
bits 15:0 from the source register 2
bits 23:8 from the source register 2
bits 31:16 from the source register 2
bits 31:0 from the source register 2
bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
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Figure 12-6. Format 2b: (JMP, JAL – Immediate Op2)
31
29
28
25
OP
SUBOP
15
9
24
IO
8
Imm
23
16
Imm
7
5
4
RdSel
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-11. Format 2b: (JMP, JAL – Immediate Op2)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOP
0 = JMP - Jump
1 = JAL – Jump and Link
24
IO
1 = Jump operand is a 16-bit immediate value
23-8
Imm
0h–FFFFh = This field is the 16-bit immediate value to be copied to the program counter.
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-30 = This field selects the destination register number to which the pre-incremented program
counter should be written. Only written for JAL.
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
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bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
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Figure 12-7. Format 2c: (LDI)
31
29
28
25
OP
SUBOP
15
24
IO
8
Imm
23
16
Imm
7
5
RdSel
4
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-12. Format 2c: (LDI)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOP
2 = Specifies LDI
24
RESERVED
23-8
Imm
0
1
2
3
4
5
6
7
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
7-5
RdSel
0
1
2
3
4
5
6
7
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
4-0
Rd
0-31 = This field selects the destination register number to which the result should be written.
290
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Figure 12-8. Format 2d: (LMBD - Leftmost Bit Detect - Register Op2)
31
29
28
OP
15
25
SUBOB
13
12
Rs1Sel
24
IO
8
Rs1
23
21
20
Rs2Sel
7
16
Rs2
5
RdSel
4
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-13. Format 2d: (LMBD - Leftmost Bit Detect - Register Op2)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOB
3 = Specifies LMBD
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0-31 = Rs2 register number 0-31
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = Rs1 register number 0-31
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-31 = Rd register number 0-31
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
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bits 7:0 from Rs2
bits 15:8 from Rs2
bits 23:16 from Rs2
bits 31:24 from Rs2
bits 15:0 from Rs2
bits 23:8 from Rs2
bits 31:16 from Rs2
bits 31:0 from Rs2
bits 7:0 from Rs1
bits 15:8 from Rs1
bits 23:16 from Rs1
bits 31:24 from Rs1
bits 15:0 from Rs1
bits 23:8 from Rs1
bits 31:16 from Rs1
bits 31:0 from Rs1
bits 7:0 from Rd
bits 15:8 from Rd
bits 23:16 from Rd
bits 31:24 from Rd
bits 15:0 from Rd
bits 23:8 from Rd
bits 31:16 from Rd
bits 31:0 from Rd
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Figure 12-9. Format 2e: (LMBD - Immediate Op2)
31
29
28
OP
15
25
SUBOB
13
12
Rs2Sel
24
IO
8
Rs2
23
16
Imm2
7
5
4
RdSel
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-14. Format 2e: (LMBD - Immediate Op2)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOB
3 = Specifies LMBD
24
IO
1 = Op2 is an 8 bit immediate
23-16
Imm2
0-255 = Immediate for src2
15-13
Rs2Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = Rd register number
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-31 = Rd register number 0-31
292
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
S= elect
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from Rs1
bits 15:8 from Rs1
bits 23:16 from Rs1
bits 31:24 from Rs1
bits 15:0 from Rs1
bits 23:8 from Rs1
bits 31:16 from Rs1
bits 31:0 from Rs1
bits 7:0 from Rd
bits 15:8 from Rd
bits 23:16 from Rd
bits 31:24 from Rd
bits 15:0 from Rd
bits 23:8 from Rd
bits 31:16 from Rd
bits 31:0 from Rd
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Figure 12-10. Format 2f: (SCAN - Register Op2)
31
29
28
OP
15
25
SUBOB
13
12
Rs1Sel
24
IO
8
Rs1
23
21
20
Rs2Sel
7
16
Rs2
5
4
RdSel
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-15. Format 2f: (SCAN - Register Op2)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOB
4 = Specifies SCAN
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0-31 = Rs2 register number 0-31
15-13
Rs1Sel
7 = Select bits 31:0 from Rs1
12-8
Rs1
0-31 = Must be identical to Rd
7-5
RdSel
7 = Select bits 31:0 from Rd
4-0
Rd
0-31 = Rd register number 0-31
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
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bits 7:0 from Rs2
bits 15:8 from Rs2
bits 23:16 from Rs2
bits 31:24 from Rs2
bits 15:0 from Rs2
bits 23:8 from Rs2
bits 31:16 from Rs2
bits 31:0 from Rs2
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Figure 12-11. Format 2g: (SCAN - Immediate Op2)
31
29
28
OP
15
25
SUBOB
13
12
Rs1Sel
24
IO
8
23
16
Imm2
7
Rs1
5
4
0
RdSel
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-16. Format 2g: (SCAN - Immediate Op2)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOB
4 = Specifies SCAN
24
IO
1 = Op2 is an 8 bit immediate
23-16
Imm2
0-255 = Immediate for src2
15-13
Rs1Sel
7 = Select bits 31:0 from Rs1
12-8
Rs1
0-31 = Must be identical to Rd
7-5
RdSel
7 = Select bits 31:0 from Rd
4-0
Rd
0-31 = Rd register number 0-31
Figure 12-12. Format 2h: (HALT)
31
29 28
OP
25 24
0
SUBOP
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-17. Format 2h: (HALT)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOB
5 = Specifies HALT
24-0
RESERVED
Figure 12-13. Format 2i: (SLP)
31
29
28
OP
25
SUBOP
24
23
Wake
RESE
OnStat
RVED
us
22
16
RESERVED
15
0
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-18. Format 2i: (SLP)
Bit
Field
Description
31-29
OP
0b001 = Specifies Format 2
28-25
SUBOP
15 = SLP – Sleep
24
RESERVED
23
WakeOnStatus
22-0
RESERVED
294
0 = Do not wake when non-masked status is asserted
1 = Wake when non-masked status is asserted
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Figure 12-14. Format 4a: (Quick Arithmetic Test and Branch – Register Op2)
31
30
OP
15
29
GT
13
28
EQ
12
27
LT
Rs1Sel
26
25
BrOff[9:8]
24
IO
8
23
21
20
Rs2Sel
16
Rs2
7
0
Rs1
BrOff[7:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-19. Format 4a: (Quick Arithmetic Test and Branch – Register Op2)
Bit
Field
Description
31-30
OP
0b01 = Specifies Format 4
29
GT
0-1 = Greater Than: If set specifies that branch should be taken if Op2 > Rs1 (1)
28
EQ
0-1 = Equal: If set specifies that branch should be taken if Op2 == Rs1 (1)
27
LT
0-1 = Less Than: If set specifies that branch should be taken if Op2 < Rs1 (1)
26-25
BrOff[9:8]
0-3 = This field contains the 2-MSBs of the 2s complement signed offset for the branch
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0-31 = This field selects the register number which contains the second source operand that is to
be compared
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand that is to be
compared.
7-0
BrOff[7:0]
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch
(1)
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 2
bits 15:8 from the source register 2
bits 23:16 from the source register 2
bits 31:24 from the source register 2
bits 15:0 from the source register 2
bits 23:8 from the source register 2
bits 31:16 from the source register 2
bits 31:0 from the source register 2
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
Branch is taken if any of the 3 conditions are satisfied: GT, EQ or LT.
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Figure 12-15. Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2)
31
30
OP
15
29
GT
13
28
EQ
12
27
LT
Rs1Sel
26
25
BrOff[9:8]
24
IO
8
23
16
Imm
7
0
Rs1
BrOff[7:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-20. Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2)
Bit
Field
Description
31-30
OP
0b01 = Specifies Format 4
29
GT
0-1 = Greater Than: If set specifies that branch should be taken if Op2 > Rs1 (1)
28
EQ
0-1 = Equal: If set specifies that branch should be taken if Op2 == Rs1 (1)
27
LT
0-1 = Less Than: If set specifies that branch should be taken if Op2 < Rs1 (1)
26-25
BrOff[9:8]
0-3 = This field contains the 2-MSBs of the 2s complement signed offset for the branch
24
IO
1 = Op2 is an 8-bit immediate value
23-16
Imm
0-255 = 8-bit immediate value to be used as second operand to be compared.
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand that is to be
compared.
7-0
BrOff[7:0]
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch
(1)
296
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
Branch is taken if any of the 3 conditions are satisfied: GT, EQ or LT.
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Figure 12-16. Format 5a: (Quick Bit Test and Branch – Register Op2)
31
29
28
BS
12
OP
15
13
27
BC
Rs1Sel
26
25
BrOff[[9:8]
24
IO
8
23
21
20
Rs2Sel
16
Rs2
7
0
Rs1
BrOff[7:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-21. Format 5a: (Quick Bit Test and Branch – Register Op2)
Bit
Field
Description
31-29
OP
0b110 = Specifies Format 5
28
BS
0-1 = Bit Set: If set specifies that branch should be taken if Rs1[Op2[4:0]] == 1 (1)
27
BC
0-1 = Bit Clear: If set specifies that branch should be taken if Rs1[Op2[4:0]] == 0 (1)
26-25
BrOff[9:8]
0-3 = This field contains the 2-MSBs of the 2s complement signed offset for the branch
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0-31 = This field selects the register number which contains the bit number of the first operand
which is to be compared.
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand that is to be
compared.
7-0
BrOff[7:0]
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch
(1)
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 2
bits 15:8 from the source register 2
bits 23:16 from the source register 2
bits 31:24 from the source register 2
bits 15:0 from the source register 2
bits 23:8 from the source register 2
bits 31:16 from the source register 2
bits 31:0 from the source register 2
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
Branch is taken if any of the 2 conditions are satisfied: BS or BC.
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Figure 12-17. Format 5b: (Quick Bit Test and Branch – Immediate Op2)
31
29
28
BS
12
OP
15
13
27
BC
Rs1Sel
26
25
BrOff[[9:8]
24
IO
8
23
21
20
RESERVED
16
Imm
7
0
Rs1
BrOff[7:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-22. Format 5b: (Quick Bit Test and Branch – Immediate Op2)
Bit
Field
Description
31-29
OP
0b110 = Specifies Format 5
28
BS
0-1 = Bit Set: If set specifies that branch should be taken if Rs1[Op2[4:0]] == 1 (1)
27
BC
0-1 = Bit Clear: If set specifies that branch should be taken if Rs1[Op2[4:0]] == 0 (1)
26-25
BrOff[9:8]
0-3 = This field contains the 2-MSBs of the 2s complement signed offset for the branch
24
IO
1 = Op2 is a 5-bit immediate value
23-21
RESERVED
20-16
Imm
0-31 = This field selects the bit number of the first operand which is to be compared.
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand that is to be
compared
7-0
BrOff[7:0]
0-255 = This field contains the 8-LSBs of the 2-s complement signed offset for the branch
(1)
298
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
Branch is taken if any of the 2 conditions are satisfied: BS or BC.
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Figure 12-18. Format 6a: (LBBO/SBBO - Register Offset)
31
29
OP
15
13
28
LoadSt
ore
12
27
25
BurstLen[6:4]
24
IO
8
BurstLen[3:1]
23
Rb
21
20
RoSel
7
BurstL
en[0]
6
16
Ro
5
4
RxByteAddr
0
Rx
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-23. Format 6a: (LBBO/SBBO - Register Offset)
Bit
Field
Description
31-29
OP
0b111 = Specifies Format 6a / 6b
28
LoadStore
0 = SBBO
1 = LBBO
27-25
BurstLen[6:4]
The following 3 fields specify the burst length (in bytes) for the transfer
24
IO
0 = The offset is to be taken from a register
23-21
RoSel
0
1
2
3
4
5
6
7
20-16
Ro
0-31 = This field selects the register number which contains the beginning offset for the transfer.
15-13
BurstLen[3:1]
12-8
Rb
0-31 = This field selects the register number which contains the base address for the transfer
7
BurstLen[0]
0-123 = byte count = BurstLen + 1 (1 – 124 Bytes)
124 = byte count = R0 bits 7:0
125 = byte count = R0 bits 15:8
126 = byte count = R0 bits 23:16
127 = byte count = R0 bits 31:24
6-5
RxByteAddr
0-3 = This field selects the beginning byte number in the source / destination register for the data
transfer
4-0
Rx
0-30 = This field selects the beginning source / destination register number for the data transfer.
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
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bits 7:0 from the offset register
bits 15:8 from the offset register
bits 23:16 from the offset register
bits 31:24 from the offset register
bits 15:0 from the offset register
bits 23:8 from the offset register
bits 31:16 from the offset register
bits 31:0 from the offset register
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Figure 12-19. Format 6b: (LBBO/SBBO - Immediate Offset)
31
29
OP
15
13
28
LoadSt
ore
12
BurstLen[3:1]
27
25
BurstLen[6:4]
24
23
16
IO
9
8
Rb
Imm
7
BurstL
en[0]
6
5
4
RxByteAddr
0
Rx
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-24. Format 6b: (LBBO/SBBO - Immediate Offset)
Bit
Field
Description
31-29
OP
0b111 = Specifies Format 6a / 6b
28
LoadStore
0 = SBBO
1 = LBBO
27-25
BurstLen[6:4]
The following 3 fields specify the burst length (in bytes) for the transfer.
24
IO
1 = The offset is an immediate 8-bit value
23-16
Imm
0-255 = Immediate 8-bit offset value
15-13
BurstLen[3:1]
12-8
Rb
0-31 = This field selects the register number which contains the base address for the transfer
7
BurstLen[0]
0-123 = byte count = BurstLen +1 (1 – 124 Bytes)
124 = byte count = R0 bits 7:0
125 = byte count = R0 bits 15:8
126 = byte count = R0 bits 23:16
127 = byte count = R0 bits 31:24
6-5
RxByteAddr
0-3 = This field selects the beginning byte number in the source / destination register for the data
transfer
4-0
Rx
0-30 = This field selects the beginning source / destination register number for the data transfer.
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Figure 12-20. Format 6c: (LBCO/SBCO - Register Offset)
31
29
OP
15
13
28
LoadSt
ore
12
27
25
BurstLen[6:4]
24
IO
8
BurstLen[3:1]
23
Cb
21
20
RoSel
7
BurstL
en[0]
6
16
Ro
5
4
RxByteAddr
0
Rx
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-25. Format 6c: (LBCO/SBCO - Register Offset)
Bit
Field
Description
31-29
OP
0b100 = Specifies Format 6c / 6d
28
LoadStore
0 = SBCO
1 = LBCO
27-25
BurstLen[6:4]
The following 3 fields specify the burst length (in bytes) for the transfer.
24
IO
0 = The offset is to be taken from a register
23-21
RoSel
0
1
2
3
4
5
6
7
20-16
Ro
0-31 = This field selects the register number which contains the beginning offset for the transfer.
15-13
BurstLen[3:1]
12-8
Cb
0-31 = This field selects the constant table entry number which contains the base address for the
transfer
7
BurstLen[0]
0-123 = byte count = BurstLen + 1 (1 – 124 Bytes)
124 = byte count = R0 bits 7:0
125 = byte count = R0 bits 15:8
126 = byte count = R0 bits 23:16
127 = byte count = R0 bits 31:24
6-5
RxByteAddr
0-3 = This field selects the beginning byte number in the source / destination register for the data
transfer.
4-0
Rx
0-30 = This field selects the beginning source / destination register number for the data transfer.
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
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bits 7:0 from the offset register
bits 15:8 from the offset register
bits 23:16 from the offset register
bits 31:24 from the offset register
bits 15:0 from the offset register
bits 23:8 from the offset register
bits 31:16 from the offset register
bits 31:0 from the offset register
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Figure 12-21. Format 6d: (LBCO/SBCO - Immediate Offset)
31
29
OP
15
13
28
LoadSt
ore
12
27
25
BurstLen[6:4]
24
16
IO
8
BurstLen[3:1]
23
Cb
Imm
7
BurstL
en[0]
6
5
4
RxByteAddr
0
Rx
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-26. Format 6d: (LBCO/SBCO - Immediate Offset)
Bit
Field
Description
31-29
OP
0b100 = Specifies Format 6c / 6d
28
LoadStore
0 = SBCO
1 = LBCO
27-25
BurstLen[6:4]
The following 3 fields specify the burst length (in bytes) for the transfer.
24
IO
1 = The offset is an immediate 8-bit value
23-16
Imm
0-255 = Immediate 8-bit offset value
15-13
BurstLen[3:1]
12-8
Cb
0 – 31 This field selects the constant table entry number which contains the base address for the
transfer
7
BurstLen[0]
0-123 = byte count = BurstLen + 1 (1 – 124 Bytes)
124 = byte count = R0 bits 7:0
125 = byte count = R0 bits 15:8
126 = byte count = R0 bits 23:16
127 = byte count = R0 bits 31:24
6-5
RxByteAddr
0=3 = This field selects the beginning byte number in the source / destination register for the data
transfer
4-0
Rx
0-30 = This field selects the beginning source / destination register number for the data transfer.
12.7 PRU Interrupt Controller
12.7.1 Introduction
The PRUSS interrupt controller (INTC) is an hardware interface between interrupts coming from different
parts of the system (these are referred to as system events), and the PRUs interrupt inputs.
The PRUSS INTC has the following features:
• Capturing up to 32 System Events external to the PRUSS
• 32 additional System events generated by the PRUs
• Supports up to 10 interrupt channels
• Generation of 10 Host Interrupts
– 2 Host Interrupts for the PRUs
– 8 Host Interrupts exported from the PRUSS for signaling the host (ARM/DSP) interrupt controllers
• Each system event can be enabled and disabled
• Each host event can be enabled and disabled.
• Hardware prioritization of events
12.7.2 Interrupt Mapping
The PRUSS INTC supports up to 64 system interrupts from different peripherals and PRUs to be mapped
to 10 channels inside the INTC (see Figure 1). Interrupts from these 10 channels are further mapped to 10
Host Interrupts.
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•
•
•
•
•
•
•
•
•
Any of the 64 system interrupts can be mapped to any of the 10 channels.
Multiple interrupts can be mapped to a single channel.
An interrupt should not be mapped to more than one channel.
Any of the 10 channels can be mapped to any of the 10 host interrupts. It is recommended to map
channel "x" to host interrupt "x", where x is from 0 to 9
A channel should not be mapped to more than one host interrupt.
For channels mapping to the same host interrupt, lower number channels have higher priority.
For interrupts on same channel, priority is determined by the hardware interrupt number. The lower the
interrupt number, the higher the priority.
Host Interrupt 0 is connected to bit 30 in register 31 of PRU0 and PRU1.
Host Interrupt 1 is connected to bit 31 in register 31 for PRU0 and PRU1. Host Interrupts 2 through 9
exported from PRUSS for signaling ARM and DSP interrupt controllers generating system Events
PRUSS_EVTOUT0 to PRUSS_EVTOUT7 respectively.
Figure 12-22.
12.7.3 PRUSS System Events
System events 0 through 31 are external to the PRUSS subsystem and generated from different
peripherals. The source of the first 32 events from the device is listed in the Table 12-27.
System events 32 to 63 are generated by a PRU writing to its own R31 register. The system interrupt is
used to either post a completion event to one of the host CPUs (ARM/DSP) or to signal the other PRU
core of the PRUSS. For more information on the steps to generate the system events 32 to 63 refer to
Section 12.4.1.
The device includes a mux that with a single select signal selects the PRUSS EVT inputs as shown in the
table below. The control signal, PRUSSEVTSEL, can be modified by software in system register
CFGCHIP3[3]. PRUSSEVTSEL defaults to 0 after reset. Note that not all system events are defined for all
devices. Refer to the device datasheet or System Reference Guide for more information.
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Table 12-27. PRUSS System Events [0:31] Assignments
PRUSSEVTSEL = 0
Description
Event
304
PRUSSEVTSEL = 1
Description
0
Emulation Suspend Signal
(Software Use Only)
Emulation Suspend Signal
(Software Use Only)
1
ECAP0 Interrupt
Timer64P2_T12CMPEVT0
2
ECAP1 Interrupt
Timer64P2_T12CMPEVT1
3
Timer64P0 Event Out 12
Timer64P2_T12CMPEVT2
4
ECAP2 Interrupt
Timer64P2_T12CMPEVT3
5
McASP0 TX DMA Request
Timer64P2_T12CMPEVT4
6
McASP0 RX DMA Request
Timer64P2_T12CMPEVT5
7
McBSP0 TX DMA Request
Timer64P2_T12CMPEVT6
8
McBSP0 RX DMA Request
Timer64P2_T12CMPEVT7
9
McBSP1 TX DMA Request
Timer64P3_T12CMPEVT0
10
McBSP1 RX DMA Request
Timer64P3_T12CMPEVT1
11
SPI0 Interrupt 0
Timer64P3_T12CMPEVT2
12
SPI1 Interrupt 0
Timer64P3_T12CMPEVT3
13
UART0 Interrupt
Timer64P3_T12CMPEVT4
14
UART1 Interrupt
Timer64P3_T12CMPEVT5
15
I2C0 Interrupt
Timer64P3_T12CMPEVT6
16
I2C1 Interrupt
Timer64P3_T12CMPEVT7
17
UART2 Interrupt
Timer64P0_T12CMPEVT0
Timer64P0_T12CMPEVT1
Timer64P0_T12CMPEVT2
Timer64P0_T12CMPEVT3
Timer64P0_T12CMPEVT4
Timer64P0_T12CMPEVT5
Timer64P0_T12CMPEVT6
Timer64P0_T12CMPEVT7
18
MMCSD0 Interrupt 0
Timer64P2 Event Out 12
19
MMCSD0 Interrupt 1
Timer64P3 Event Out 12
20
USB0 (USB2.0 HS OTG) Subsystem
Interrupt Request (aggregated from
subsystem’s INTD)
Timer64P1 Event Out 12
21
USB1 (USB1.1 FS OHCI) Subsystem IRQ
Interrupt
UART1 Interrupt
22
Timer64P0 Event Out 34
UART2 Interrupt
23
ECAP0 input (output from mux)
SPI0 Interrupt 0
24
EPWM0 Interrupt
EPWM0 Interrupt
25
EPWM1 Interrupt
EPWM1 Interrupt
26
SATA Interrupt
SPI1 Interrupt 0
27
EDMA3_0_CC0_INT2 (region 2)
GPIO Bank 0 Interrupt
28
EDMA3_0_CC0_INT3 (region 3)
GPIO Bank 1 Interrupt
29
UHPI CPU_INT
McBSP0 TX DMA Request
30
EPWM0TZ Interrupt or EPWM1TZ Interrupt
McBSP0 RX DMA Request
31
McASP0 TX Interrupt or McASP0 RX
Interrupt
McASP0 TX Interrupt or McASP0 RX
Interrupt
Programmable Real-Time Unit Subsystem (PRUSS)
or
or
or
or
or
or
or
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12.7.4 ARM and DSP Interrupt Controller Mapping
Events PRUSS_EVTOUT0 to PRUSS_EVTOUT7 are mapped to the ARM and DSP interrupt controllers.
The following tables show the interrupt mapping.
Table 12-28. ARM Interrupt Controller Mapping
Event Number
Source
3
EVTOUT0
4
EVTOUT1
5
EVTOUT2
6
EVTOUT3
7
EVTOUT4
8
EVTOUT5
9
EVTOUT6
10
EVTOUT7
Table 12-29. DSP Interrupt Controller Mapping
Event Number
Source
6
EVTOUT0
17
EVTOUT1
22
EVTOUT2
35
EVTOUT3
66
EVTOUT4
39
EVTOUT5
44
EVTOUT6
50
EVTOUT7
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12.7.5 INTC Methodology
The INTC module controls the system event mapping to the host interrupt interface. System events are
generated by the device peripherals or PRUs. The INTC receives the system interrupts and maps them to
internal channels. The channels are used to group interrupts together and to prioritize them. These
channels are then mapped onto the host interrupts. Interrupts from system side are active high in polarity.
Also, they are pulse type of interrupts.
The INTC encompasses many functions to process the system interrupts and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, and host interfacing. Figure 12-23 illustrates the flow of system interrupts through the
functions to the host. The following subsections describe each part of the flow.
Figure 12-23.
12.7.5.1 Interrupt Processing
This block does following tasks:
• Synchronization of slower and asynchronous interrupts
• Conversion of polarity to active high
• Conversion of interrupt type to pulse interrupts
After the "processing block", all interrupts will be active high pulses.
12.7.5.2 Interrupt Enabling
The next stage of INTC is to enable system interrupts based on programmed settings. The following
sequence is to be followed to enable interrupts:
1. Enable all host interrupts: By setting the ENABLE bit in the global enable register (GER) to 1, all host
interrupts will be enabled. Individual host interrupts are still enabled or disabled from their individual
enables and are not overridden by the global enable
2. Enable required host interrupts: By writing to the INDEX field in the host interrupt enable indexed set
register (HIEISR), enable the required host interrupts. The host interrupt to enable is the index value
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written. This enables the host interrupt output or triggers the output again if that host interrupt is
already enabled.
3. Enable required system interrupts: System interrupts that are required to get propagated to host are to
be enabled individually by writing to INDEX field in the system interrupt enable indexed set register
(EISR). The interrupt to enable is the index value written. This sets the Enable Register bit of the given
index.
System interrupts can also be enabled by setting the bits of the system interrupt enable set registers
(ESR1-ESR3). Only enabled system interrupts will generate an interrupt to the host.
12.7.5.3 Interrupt Status Checking
The next stage is to capture which system interrupts are pending. There are two kinds of pending status:
raw status and enabled status. Raw status is the pending status of the system interrupt without regards to
the enable bit for the system interrupt. The raw status of system interrupts is captured in system interrupt
status raw/set registers (SRSR1-SRSR2). Enabled status is the pending status of the system interrupts
with the enable bits set. When the enable bit is not set, the enabled status will always be inactive. The
enabled status of system interrupts is captured in system interrupt status enabled/clear registers (SECR1SECR2).
Status of system interrupt ’N’ is indicated by the Nth bit of SECR1-SECR2. Since there are 64 system
interrupts, two 32-bit registers are used to capture the enabled status of interrupts. The pending status
reflects whether the system interrupt occurred since the last time the status register bit was cleared. Each
bit in the status register can be individually cleared.
12.7.5.4 Interrupt Channel Mapping
The INTC has 10 internal channels to which enabled system interrupts can be mapped. Channel 0 has
highest priority and channel 9 has the lowest priority. Channels are used to group the system interrupts
into a smaller number of priorities that can be given to a host interface with a very small number of
interrupt inputs.
When multiple system interrupts are mapped to the same channel their interrupts are ORed together so
that when either is active the output is active. The channel map registers (CMR1-CMR16) define the
channel for each system interrupt. There is one register per 4 system interrupts; therefore, there are 16
channel map registers for a system of 64 interrupts. Channels for each system interrupt can be set using
these registers.
12.7.5.5 Host Interrupt Mapping
The INTC generates 10 host interrupts which can be . The hosts can be the two PRUs, the ARM CPU,
and DSP CPU. The 10 channels from the INTC can be mapped to any of the 10 host interrupts. The host
map registers (HMR1-HMR3) define the host interrupt for each channel. There is one register per 4
channels; therefore, there are 3 host map registers for 10 channels. Multiple channels can be mapped to
the same host interrupt. When multiple channels are mapped to the same host interrupt prioritization is
done to select which interrupt is in the highest-priority channel and which should be sent first to the host.
12.7.5.6 Interrupt Prioritization
The next stage of the INTC is prioritization. Since multiple interrupts can feed into a single channel and
multiple channels can feed into a single host interrupt, it is necessary to read the status of all system
interrupts to determine the highest priority interrupt that is pending. The INTC provides hardware to
perform this prioritization with a given scheme so that software does not have to do this. There are two
levels of prioritization:
• The first level of prioritization is between the active channels for a host interrupt. Channel 0 has the
highest priority and channel 9 has the lowest. So the first level of prioritization picks the lowest
numbered active channel.
• The second level of prioritization is between the active system interrupts for the prioritized channel.
The system interrupt in position 0 has the highest priority and system interrupt 63 has the lowest
priority. So the second level of prioritization picks the lowest position active system interrupt.
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The highest priority interrupt pending across all host interrupts is stored in the global prioritized index
register (GPIR). The highest priority pending interrupt with respect to each host interrupt can be obtained
using the host interrupt prioritized index registers (HIPIRn).
12.7.5.7 Interrupt Nesting
The INTC can also perform a nesting function in its prioritization. Nesting is a method of disabling certain
interrupts (usually lower-priority interrupts) when an interrupt is taken so that only those desired interrupts
can trigger to the host while it is servicing the current interrupt. The typical usage is to nest on the current
interrupt and disable all interrupts of the same or lower priority (or channel). Then the host will only be
interrupted from a higher priority interrupt.
The nesting is done in 1 of 3 methods:
• Nesting for all host interrupts, based on channel priority: When an interrupt is taken, the nesting level is
set to its channel priority. From then, that channel priority and all lower priority channels will be
disabled from generating host interrupts and only higher priority channels are allowed. When the
interrupt is completely serviced, the nesting level is returned to its original value. When there is no
interrupt being serviced, there are no channels disabled due to nesting. The global nesting level
register (GNLR) allows the checking and setting of the global nesting level across all host interrupts.
The nesting level is the channel (and all of lower priority channels) that are nested out because of a
current interrupt.
• Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority
for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting
level is set to its channel priority for just that host interrupt, and other host interrupts do not have their
nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host
but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting
level for the host interrupt is returned to its original value. The host interrupt nesting level registers
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level
controls which channel and lower priority channels are nested. There is one register per host interrupt.
• Software manually performs the nesting of interrupts. When an interrupt is taken, the software will
disable all the host interrupts, manually update the enables for any or all the system interrupts, and
then re-enables all the host interrupts. This now allows only the system interrupts that are still enabled
to trigger to the host. When the interrupt is completely serviced the software must reverse the changes
to re-enable the nested out system interrupts. This method requires the most software interaction but
gives the most flexibility if simple channel based nesting mechanisms are not adequate.
12.7.5.8 Interrupt Status Clearing
After servicing the interrupt (after execution of the ISR), interrupt status is to be cleared. If a system
interrupt status is not cleared, then another host interrupt may not be triggered or another host interrupt
may be triggered incorrectly.It is also essential to clear all system interrupts before the PRU is halted as
the PRU does not power down unless all the interrupt status are cleared. For clearing the status of an
interrupt, whose interrupt number is N, write a 1 to the Nth bit position in the system interrupt status
enabled/clear registers (SECR1-SECR2). System interrupt N can also be cleared by writing the value N
into the system interrupt status indexed clear register (SICR).
12.7.5.9 Interrupt Disabling
At any time, if any interrupt is not to be propagated to the host, then that interrupt should be disabled. For
disabling an interrupt whose interrupt number is N, write a 1 to the Nth bit in the system interrupt enable
clear registers (ECR1-ECR2). System interrupt N can also be disabled by writing the value N in the
system interrupt enable indexed clear register (EICR).
12.7.5.10 Configuring the Interrupt Controller
Follow these steps to configure the interrupt controller.
1. Set polarity and type of system event through the System Interrupt Polarity Registers (SIPR1 and
SPIR2) and the System Interrupt Type Registers (SITR1 and SITR2). Polarity of all system interrupts is
always high. Type of all system interrupts is always pulse.
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2. Map system event to INTC channel through CHANMAP registers.
3. Map channel to host interrupt through HOSTMAP registers. Recommend channel “x” be mapped to
host interrupt “x”.
4. Clear system interrupt by writing 1s to SECR registers.
5. Enable host interrupt by writing index value to HOSTINTENIDX register.
6. Enable interrupt nesting if desired.
7. Globally enable all interrupts through GLBLEN register.
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12.8.1 PRUSS Memory Map
12.8.1.1 Local Memory Map
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 12-30 (Instruction Space) and in Table 12-31 (Data Space). Note that these two
memory maps are implemented inside the PRUSS and are local to the components of the PRUSS.
Table 12-30. Local Instruction Space Memory Map
Start Address
0x00000000
End Address
0x00000FFF
PRU0
PRU1
PRU0 Instruction RAM
PRU1 Instruction RAM
Table 12-31. Local Data Space Memory Map
Start Address
End Address
PRU0
PRU1
0x00000000
0x000001FF
Data RAM 0 (1)
Data RAM 1 (1)
0x00000200
0x00001FFF
Reserved
Reserved
0x00002000
0x000021FF
Data RAM 1 (1)
Data RAM 0 (1)
0x00002200
0x00003FFF
Reserved
Reserved
0x00004000
0x00006FFF
INTC Registers
INTC Registers
0x00007000
0x000077FF
PRU0 Registers
PRU0 Registers
0x00007800
0x00007FFF
PRU1 Registers
PRU1 Registers
0x00008000
0x0000FFFF
Reserved
Reserved
0x00010000
0xFFFFFFFF
Reserved
Reserved
(1)
Note that PRU0 accesses Data RAM0 at address 0x00000000, also PRU1 accesses Data RAM1 at address 0x00000000. Data
RAM0 is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for
PRU1. However for passing information between PRUs, each PRU can access the data ram of the other PRU at address
0x00002000.
12.8.1.2 Global Memory Map
The global view of the PRUSS internal memories and control ports is documented in Table 12-32. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C30000-0x01C3FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
Table 12-32. Subsystem Global Memory Map
Start Address
End Address
Region
0x01C30000
0x01C301FF
Data RAM 0
0x01C30200
0x01C31FFF
Reserved
0x01C32000
0x01C321FF
Data RAM 1
0x01C32200
0x01C33FFF
Reserved
0x01C34000
0x01C36FFF
INTC Registers
0x01C37000
0x01C377FF
PRU0 Registers
0x01C37800
0x01C37FFF
PRU1 Registers
0x01C38000
0x01C38FFF
PRU0 Instruction RAM
0x01C39000
0x01C3BFFF
Reserved
0x01C3C000
0x01C3CFFF
PRU1 Instruction RAM
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Table 12-32. Subsystem Global Memory Map (continued)
Start Address
End Address
0x01C3D000
Region
0x01C3FFFF
Reserved
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses. Please refer to the device's System
Reference Guide or datasheet for device specific memory mapping.
12.8.1.3 PRU Memory Map Overview
The PRU control and status registers region contains control and status registers for the PRU. The control
/ status registers region memory map is shown in Table 12-33.
Table 12-33. PRU Control/Status Register Memory Map
Address Offset
Register Name
Register Description
0h
CONTROL
PRU Control Register
4h
STATUS
PRU Status Register
8h
WAKEUP
PRU Wakeup Enable Register
Ch
CYCLECNT
PRU Cycle Count
10h
STALLCNT
PRU Stall Count
20h
CONTABBLKIDX0
PRU Constant Table Block Index Register 0
28h
CONTABPROPTR0
PRU Constant Table Programmable Pointer Register 0
2Ch
CONTABPROPTR1
PRU Constant Table Programmable Pointer Register 1
400h to 47Ch
INTGPR0 to INTGPR31
PRU Internal General Purpose Registers (for Debug)
480h to 4FCh
INTCTER0 to INTCTER31
PRU Internal Constants Table Entry Registers (for Debug)
12.8.1.3.1 CONTROL Register (Offset = 0h)
Figure 12-24. CONTROL Register
31
16
PCRESETVAL
R/W-0
15
14
9
RUNS
TATE
RESERVED
R/W-0
R-0
8
SINGL
ESTE
P
R/W-0
7
4
RESERVED
R-0
3
COUN
TENA
BLE
R/W-0
2
1
SLEE
PING
ENAB
LE
R/W-0
R/W-0
0
SOFT
RESE
T
R-0 →
1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-34. CONTROL Register Field Descriptions
Bit
31-16
15
Field
Type
Reset
Description
PCRESETVA R/W
L
0
Program Counter Reset Value: This field controls the address where the
PRU will start executing code from after it is taken out of reset*
RUNSTATE
0
Run State: This bit indicates whether the PRU is currently executing an
instruction or is halted.
0 = PRU is halted and host has access to the instruction RAM and debug
registers regions.
1 = PRU is currently running and the host is locked out of the instruction
RAM and debug registers regions This bit is used by an external debug agent
to know when the PRU has actually halted when waiting for a HALT
instruction to execute, a single step to finish, or any other time when the
pru_enable has been cleared.
R
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Table 12-34. CONTROL Register Field Descriptions (continued)
Bit
312
Field
Type
Reset
Description
14-9
RESERVED
R
0
8
SINGLESTE
P
R/W
0
7-4
RESERVED
R
0
3
COUNTENA
BLE
R/W
0
PRU Cycle Counter Enable: Enables PRU cycle counters
0 = Counters not enabled
1 = Counters enabled
2
SLEEPING
R/W
0
PRU Sleep Indicator: This bit indicates whether or not the PRU is currently
asleep.
0 = PRU is not asleep
1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power
up from sleep mode.
1
ENABLE
R/W
0
Processor Enable: This bit controls whether or not the PRU is allowed to
fetch new instructions.
0 = PRU is disabled
1 = PRU is enabled If this bit is de-asserted while the PRU is currently
running and has completed the initial cycle of a multi-cycle instruction
(LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete
before the PRU pauses execution. Otherwise, the PRU will halt immediately.
Because of the unpredictability/timing sensitivity of the instruction execution
loop, this bit is not a reliable indication of whether or not the PRU is currently
running. The pru_state bit should be consulted for an absolute indication of
the run state of the core. When the PRU is halted, it’s internal state remains
coherent therefore this bit can be reasserted without issuing a software reset
and the PRU will resume processing exactly where it left off in the instruction
stream.
0
SOFTRESET R
0→1
Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set
back to 1 on the next cycle after it has been cleared.
Programmable Real-Time Unit Subsystem (PRUSS)
Single Step Enable: This bit controls whether or not the PRU will only
execute a single instruction when enabled.
0 = PRU will free run when enabled
1 = PRU will execute a single instruction and then the pru_enable bit will be
cleared. Note that this bit does not actually enable the PRU, it only sets the
policy for how much code will be run after the PRU is enabled. The
pru_enable bit must be explicitly asserted. It is legal to initialize both the
single_step and pru_enable bits simultaneously. (Two independent writes are
not required to cause the stated functionality)
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12.8.1.3.2 STATUS Register (Offset = 4h)
Figure 12-25. STATUS Register
31
16 15
0
RESERVED
R-0
PCOUNTER
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-35. STATUS Register Field Descriptions
Bit
(1)
Field
Type
Reset
31-16
RESERVED
R
0
15-0
PCOUNTER
R
0
Description
Program Counter: This field is a registered (1 cycle delayed) reflection of the
PRU program counter (1)
Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte
address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20).
12.8.1.3.3 WAKEUP Register (Offset = 8h)
31
0
BITWISEENABLES
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 12-26. WAKEUP Register
31
0
BITWISEENABLES
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-36. WAKEUP Register Field Descriptions
Bit
31-0
Field
Type
BITWISEENA R/W
BLES
Reset
0
Description
Wakeup Enables: This field is ANDed with the incoming R31 status inputs
(whose bit positions were specified in the stmap parameter) to produce a
vector which is unary ORed to produce the status_wakeup source for the
core. Setting any bit in this vector will allow the corresponding status input to
wake up the core when it is asserted high. The PRU should set this enable
vector prior to executing a SLP (sleep) instruction to ensure that the desired
sources can wake up the core.
12.8.1.3.4 CYCLECNT Register (Offset = Ch)
This register counts the number of cycles for which the PRU has been enabled.
Figure 12-27. CYCLECNT Register
31
0
CYCLECOUNT
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 12-37. CYCLECNT Register Field Descriptions
Bit
31-0
Field
CYCLECOU
NT
Type
R/WC
Reset
0
Description
This value is incremented by 1 for every cycle during which the PRU is
enabled and the counter is enabled (both bits "ENABLE" and
"COUNTENABLE" set in the PRU control register).
Counting halts while the PRU is disabled or counter is disabled, and resumes
when re-eneabled. Counter clears the "COUNTENABLE" bit in the PRU
control register when the count reaches 0xFFFFFFFF. (Count does does not
wrap). The register can be read at any time. The register can be cleared
when the counter or PRU is disabled. Clearing this register also clears the
PRU Stall Count Register.
12.8.1.3.5 STALLCNT Register (Offset = 10h)
This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new
instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles
measured over the same cycles as counted by the cycle count register. Thus the value of this register is
always less than or equal to cycle count.
Figure 12-28. STALLCNT Register
31
0
STALLCOUNT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-38. STALLCNT Register Field Descriptions
Bit
31-0
Field
STALLCOUN R
T
Type
Reset
0
Description
This value is incremented by 1 for every cycle during which the PRU is
enabled and the counter is enabled (both bits "ENABLE" and
"COUNTENABLE" set in the PRU control register), and the PRU was unable
to fetch a new instruction for any reason.
Counting halts while the PRU is disabled or the counter is disabled, and
resumes when re-enabled. The register can be read at any time. The register
is cleared when PRU Cycle Count Register is cleared.
12.8.1.3.6 CONTABBLKIDX0 Register (Offset = 20h)
This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU
Constant Table. This register can be written by the PRU whenever it needs to change to a new base
pointer for a block in the State / Scratchpad RAM. This function is useful since the PRU is often
processing multiple processing threads which require it to change contexts. The PRU can use this register
to avoid requiring excessive amounts of code for repetitive context switching. The format of this register is
as follows:
Figure 12-29. CONTABBLKIDX0 Register
31
20
19
RESERVED
R-0
16
C25
R/W-0
15
4
RESERVED
R-0
3
0
C24
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 12-39. CONTABBLKIDX0 Register Field Descriptions
Bit
Field
Type
Reset
31-20
RESERVED
R
0
19-16
C25
R/W
0
15-4
RESERVED
R
0
3-0
C24
R/W
0
Description
PRU Constant Entry 25 Block Index: This field sets the value that will appear
in bits 11:8 of entry 25 in the PRU Constant Table
PRU Constant Entry 24 Block Index: This field sets the value that will appear
in bits 11:8 of entry 24 in the PRU Constant Table
12.8.1.3.7 CONTABPROPTR0 Register (Offset = 28h)
This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant
Table which serve as general purpose pointers which can be configured to point to any locations inside
the session router address map. This register is useful when the PRU needs to frequently access certain
structures inside the session router address space whose locations are not hard coded such as tables in
scratchpad memory. This register is formatted as follows:
Figure 12-30. CONTABPROPTR0 Register
31
16 15
0
C29
R/W-0
C28
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-40. CONTABPROPTR0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
C29
R/W
0
PRU Constant Entry 29 Pointer: This field sets the value that will appear in
bits 23:8 of entry 29 in the PRU Constant Table
15-0
C28
R/W
0
PRU Constant Entry 28 Pointer: This field sets the value that will appear in
bits 23:8 of entry 28 in the PRU Constant Table
12.8.1.3.8 CONTABPROPTR1 Register (Offset = 2Ch)
This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows
the PRU to control entries 30 and 31 in the PRU Constant Table. This register is formatted as follows:
Figure 12-31. CONTABPROPTR1 Register
31
16 15
0
C31
R/W-0
C30
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-41. CONTABPROPTR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
C31
R/W
0
PRU Constant Entry 31 Pointer: This field sets the value that will appear in
bits 23:8 of entry 31 in the PRU Constant Table
15-0
C30
R/W
0
PRU Constant Entry 30 Pointer: This field sets the value that will appear in
bits 23:8 of entry 30 in the PRU Constant Table
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12.8.1.3.9 INTGPR0 to INTGPR31 Register (Offset = 400h + 4*n)
This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these
registers will have the same effect as a read or write to these registers from an internal instruction in the
PRU. For R30, this includes generation of the pulse outputs whenever the register is written. This register
is formatted as follows:
31
0
INTGPRn
R/W-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 12-32. INTGPR0 to INTGPR31 Register
31
0
INTGPRn
R/W-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-42. INTGPR0 to INTGPR31 Register Field Descriptions
Bit
31-0
Field
INTGPRn
Type
R/W
Reset
X
Description
PRU Internal GP Register n: Reading / writing this field directly
inspects/modifies the corresponding internal register in the PRU internal
regfile.
12.8.1.3.10 INTCTER0 to INTCTER31 Register (Offset = 480h + 4*n)
This register allows an external agent to debug the PRU while it is disabled. Since some of the constants
table entries may actually depend on system inputs / and or the internal state of the PRU, these registers
are provided to allow an external agent to easily determine the state of the constants table. This register is
formatted as follows:
Figure 12-33. INTCTER0 to INTCTER31 Register
31
0
INTCTERn
R/W-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-43. INTCTER0 to INTCTER31 Register Field Descriptions
Bit
31-0
316
Field
INTCTERn
Type
R
Reset
X
Programmable Real-Time Unit Subsystem (PRUSS)
Description
PRU Internal Constants Table Entry n: Reading this field directly inspects the
corresponding entry in the PRU internal constants table.
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12.8.1.4 PRU Instruction RAM Region
The instruction RAM region contains storage for instructions. The instruction RAM region memory map is
as follows:
Table 12-44. Instruction RAM Memory Region
Address Offset
Register
0x0000
PRU Instruction RAM
12.8.1.4.1 PRU Instruction RAM (0h)
A total of 1K 32-bit words of instruction storage are provided for the PRU. This memory is to be initialized
by an external (to the PRUSS) host processor. This region is only accessible to external masters when the
PRU is not-running.
Note that the instruction RAM is accessed using byte addresses on the bus. The PC is an instruction
address where each instruction is a 32 bit word and is not a byte address. To compute the byte address
just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20), or to
compute the PC just divide the word aligned byte address by 4 (byte address of 0x8 = PC of 2, byte
address of 0x20 = PC of 8).
12.8.2 INTC Registers
Table 12-45 lists the memory-mapped registers for the INTC. See Section 12.8.1 for the memory address
of these registers.
Table 12-45. PRUSS Interrupt Controller (INTC) Registers
Address Offset
Register Name
Description
0h
REVID
Revision ID Register
4h
CONTROL
Control Register
10h
GLBLEN
Global Enable Register
1Ch
GLBLNSTLVL
Global Nesting Level Register
20h
STATIDXSET
System Interrupt Status Indexed Set Register
24h
STATIDXCLR
System Interrupt Status Indexed Clear Register
28h
ENIDXSET
System Interrupt Enable Indexed Set Register
2Ch
ENIDXCLR
System Interrupt Enable Indexed Clear Register
34h
HSTINTENIDXSET
Host Interrupt Enable Indexed Set Register
38h
HSTINTENIDXCLR
Host Interrupt Enable Indexed Clear Register
80h
GLBLPRIIDX
Global Prioritized Index Register
200h
STATSETINT0
System Interrupt Status Raw/Set Register 0
204h
STATSETINT1
System Interrupt Status Raw/Set Register 1
280h
STATCLRINT0
System Interrupt Status Enabled/Clear Register 0
284h
STATCLRINT1
System Interrupt Status Enabled/Clear Register 1
300h
ENABLESET0
System Interrupt Enable Set Register 0
304h
ENABLESET1
System Interrupt Enable Set Register 1
380h
ENABLECLR0
System Interrupt Enable Clear Register 0
384h
ENABLECLR1
System Interrupt Enable Clear Register 1
400h to 440h
CHANMAP0 to CHANMAP15
Channel Map Registers 0-15
800h to 808h
HOSTMAP0 to HOSTMAP2
Host Map Register 0-2
900h to 928h
HOSTINTPRIIDX0 to HOSTINTPRIIDX9
Host Interrupt Prioritized Index Registers 0-9
D00h
POLARITY0
System Interrupt Polarity Register 0
D04h
POLARITY1
System Interrupt Polarity Register 1
D80h
TYPE0
System Interrupt Type Register 0
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Table 12-45. PRUSS Interrupt Controller (INTC) Registers (continued)
Address Offset
Register Name
Description
D84h
TYPE1
System Interrupt Type Register 1
1100h to 1128h
HOSTINTNSTLVL0 to HOSTINTNSTLVL9
Host Interrupt Nesting Level Registers 0-9
1500h
HOSTINTEN
Host Interrupt Enable Register
12.8.2.1 REVID Register (Offset = 0h)
The Revision Register contains the ID and revision information.
Table 12-46. REVID Register
31
0
REV
R/O-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-47. REVID Register Field Descriptions
Bit
31-0
Field
REV
Type
R/O
Reset
Description
1
Revision ID
12.8.2.2 CONTROL Register (Offset = 4h)
The Control Register holds global control parameters and can forces a soft reset on the module.
Table 12-48. CONTROL Register
31
4
RESERVED
R-0
3 2
NEST
MODE
R/W-0
1 0
RESE
RVED
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-49. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
31-4
RESERVED
R
0
3-2
NESTMODE
R/W
0
1-0
RESERVED
R
0
Description
The nesting mode.
0 = no nesting
1 = automatic individual nesting (per host interrupt)
2 = automatic global nesting (over all host interrupts)
3 = manual nesting
12.8.2.3 GLBLEN Register (Offset = 10h)
The Global Enable Register enables all the host interrupts. Individual host interrupts are still enabled or
disabled from their individual enables and are not overridden by the global enable.
Table 12-50. GLBLEN Register
31
1
RESERVED
R-0
0
ENABLE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 12-51. GLBLEN Register Field Descriptions
Bit
31-1
0
Field
Type
Reset
RESERVED
R
0
ENABLE
R/W
0
Description
The current global enable value when read. Writes set the global enable
12.8.2.4 GLBLNSTLVL Register (Offset = 1Ch)
The Global Nesting Level Register allows the checking and setting of the global nesting level across all
host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of
lower priority) that are nested out because of a current interrupt. This register is only available when
nesting is configured.
Table 12-52. GLBLNSTLVL Register
31
OVERRID
E
W/O-X
30
9
8
0
RESERVED
NESTLEVEL
R-0
R/W-A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-53. GLBLNSTLVL Register Field Descriptions
Bit
Field
Type
Reset
31
OVERRIDE
W/O
X
30-9
RESERVED
R
0
8-0
NESTLEVEL
R/W
Ah
Description
Always read as 0. Writes of 1 override the automatic nesting and set the
nesting_level to the written data.
The current global nesting level (highest channel that is nested). Writes set
the nesting level. In auto nesting mode this value is updated internally unless
the auto_override bit is set.
12.8.2.5 STATIDXSET Register (Offset = 20h)
The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to
set is the index value written. This sets the Raw Status Register bit of the given index.
Table 12-54. STATIDXSET Register
31
10
9
RESERVED
R-0
0
INDEX
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-55. STATIDXSET Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
INDEX
W/S
0
Description
Writes set the status of the interrupt given in the index value. Reads return 0.
12.8.2.6 STATIDXCLR Register (Offset = 24h)
The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The
interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index.
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Table 12-56. STATIDXCLR Register
31
10
9
RESERVED
R-0
0
INDEX
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-57. STATIDXCLR Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
INDEX
W/C
0
Description
Writes clear the status of the interrupt given in the index value. Reads return
0.
12.8.2.7 ENIDXSET Register (Offset = 28h)
The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is
the index value written. This sets the Enable Register bit of the given index.
Table 12-58. ENIDXSET Register
31
10
9
RESERVED
R-0
0
INDEX
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-59. ENIDXSET Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
INDEX
W/S
0
Description
Writes set the enable of the interrupt given in the index value. Reads return
0.
12.8.2.8 ENIDXCLR Register (Offset = 2Ch)
The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable
is the index value written. This clears the Enable Register bit of the given index.
Table 12-60. ENIDXCLR Register
31
10
9
RESERVED
R-0
0
INDEX
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-61. ENIDXCLR Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
INDEX
W/C
0
Description
Writes clear the enable of the interrupt given in the index value. Reads return
0.
12.8.2.9 HSTINTENIDXSET Register (Offset = 34h)
The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt
to enable is the index value written. This enables the host interrupt output or triggers the output again if
already enabled.
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Table 12-62. HSTINTENIDXSET Register
31
10
9
0
RESERVED
R-0
INDEX
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-63. HSTINTENIDXSET Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
INDEX
W/S
0
Description
Writes set the enable of the host interrupt given in the index value. Reads
return 0.
12.8.2.10 HSTINTENIDXCLR Register (Offset = 38h)
The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host
interrupt to disable is the index value written. This disables the host interrupt output.
Table 12-64. HSTINTENIDXCLR Register
31
10
9
0
RESERVED
R-0
INDEX
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-65. HSTINTENIDXCLR Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
INDEX
W/C
0
Description
Writes clear the enable of the host interrupt given in the index value. Reads
return 0.
12.8.2.11 GLBLPRIIDX Register (Offset = 80h)
The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending
across all the host interrupts.
Table 12-66. GLBLPRIIDX Register
31
NONE
R/O-0
30
10
9
RESERVED
R-0
0
PRI_INDEX
R/O-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-67. GLBLPRIIDX Register Field Descriptions
Bit
31
Field
Type
Reset
NONE
R/O
1
30-10
RESERVED
R
0
9-0
PRI_INDEX
R/O
0
Description
No Interrupt is pending. Can be used by host to test for a negative value to
see if no interrupts are pending.
The currently highest priority interrupt index pending across all the host
interrupts.
12.8.2.12 STATESETINT0 Register (Offset = 200h)
The System Interrupt Status Raw/Set Registers show the pending enabled status of the system interrupts.
Software can write to the Status Set Registers to manually set a system interrupt. There is one bit per
system interrupt.
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Table 12-68. STATESETINT0 Register
31
0
RAW_STATUS
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-69. STATESETINT0 Register Field Descriptions
Bit
31-0
Field
Type
RAW_STATU W/S
S
Reset
0
Description
System interrupt raw status and setting of the system interrupts 0 to 31.
Reads return the raw status. Write a 1 in a bit position to set the status of the
system interrupt. Writing a 0 has no effect.
12.8.2.13 STATESETINT1 Register (Offset = 204h)
The System Interrupt Status Raw/Set Registers show the pending enabled status of the system interrupts.
Software can write to the Status Set Registers to manually set a system interrupt. There is one bit per
system interrupt.
Table 12-70. STATESETINT1 Register
31
0
RAW_STATUS
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-71. STATESETINT1 Register Field Descriptions
Bit
31-0
Field
Type
RAW_STATU W/S
S
Reset
0
Description
System interrupt raw status and setting of the system interrupts 32 to 63.
Reads return the raw status. Write a 1 in a bit position to set the status of the
system interrupt. Writing a 0 has no effect.
12.8.2.14 STATCLRINT0 Register (Offset = 280h)
The System Interrupt Status Enabled/Clear Registers show the pending enabled status of the system
interrupts. Software can write to the Status Clear Registers to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt.
Table 12-72. STATCLRINT0 Register
31
0
ENABLE_STATUS
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-73. STATCLRINT0 Register Field Descriptions
322
Bit
Field
31-0
ENABLED_S
TATUS
Type
W/C
Reset
0
Programmable Real-Time Unit Subsystem (PRUSS)
Description
System interrupt enabled status and clearing of the system interrupts 0 to 31.
Reads return the enabled status (before enabling with the Enable Registers).
Write a 1 in a bit position to clear the status of the system interrupt. Writing a
0 has no effect.
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12.8.2.15 STATCLRINT1 Register (Offset = 284h)
The System Interrupt Status Enabled/Clear Registers show the pending enabled status of the system
interrupts. Software can write to the Status Clear Registers to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt.
Table 12-74. STATCLRINT1 Register
31
0
ENABLE_STATUS
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-75. STATCLRINT1 Register Field Descriptions
Bit
Field
31-0
ENABLED_S
TATUS
Type
W/C
Reset
0
Description
System interrupt enabled status and clearing of the system interrupts 32to
63.
Reads return the enabled status (before enabling with the Enable Registers).
Write a 1 in a bit position to clear the status of the system interrupt. Writing a
0 has no effect.
12.8.2.16 ENABLESET0 Register (Offset = 300h)
The System Interrupt Enable Set Register enables system interrupts to trigger outputs. System interrupts
that are not enabled do not interrupt the host. There is a bit per system interrupt.
Table 12-76. ENABLESET0 Register
31
0
ENABLE
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-77. ENABLESET0 Register Field Descriptions
Bit
31-0
Field
ENABLE
Type
W/S
Reset
0
Description
System interrupt enables system interrupts 0 to 31.
Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit
position to set that enable. Writing a 0 has no effect.
12.8.2.17 ENABLESET1 Register (Offset = 304h)
The System Interrupt Enable Set Register enables system interrupts to trigger outputs. System interrupts
that are not enabled do not interrupt the host. There is a bit per system interrupt.
Table 12-78. ENABLESET1 Register
31
0
ENABLE
W/S-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-79. ENABLESET1 Register Field Descriptions
Bit
31-0
Field
ENABLE
Type
W/S
Reset
0
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Description
System interrupt enables system interrupts 32 to 63.
Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit
position to set that enable. Writing a 0 has no effect.
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12.8.2.18 ENABLECLR0 Register (Offset = 380h)
The System Interrupt Enable Clear Register disables system interrupts to map to channels. System
interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt.
Table 12-80. ENABLECLR0 Register
31
0
ENABLE
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-81. ENABLECLR0 Register Field Descriptions
Bit
31-0
Field
ENABLE
Type
W/C
Reset
0
Description
System interrupt enables system interrupts 0 to 31.
Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit
position to clear that enable. Writing a 0 has no effect.
12.8.2.19 ENABLECLR1 Register (Offset = 384h)
The System Interrupt Enable Clear Register disables system interrupts to map to channels. System
interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt.
Table 12-82. ENABLECLR1 Register
31
0
ENABLE
W/C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-83. ENABLECLR1 Register Field Descriptions
Bit
31-0
Field
ENABLE
Type
W/C
Reset
0
Description
System interrupt enables system interrupts 32 to 63.
Read returns the enable value (0 = disabled, 1 = enabled) Write a 1 in a bit
position to clear that enable. Writing a 0 has no effect.
12.8.2.20 CHANMAP0 to CHANMAP15 Register (Offset = 400h to 440h)
The Channel Map Registers specify the channel for each system interrupt. There is one register per 4
system interrupts.
Table 12-84. CHANMAP0 to CHANMAP15 Register
31
24 23
SYSN3_MAP
R/W-0
16 15
SYSN2_MAP
R/W-0
8
7
SYSN1_MAP
R/W-0
0
SYSN_MAP
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-85. CHANMAP0 to CHANMAP15 Register Field Descriptions
Bit
324
Field
Type
Reset
Description
31-24
SYSN3_MAP R/W
0
Sets the channel for the system interrupt N + 3.
23-16
SYSN2_MAP R/W
0
Sets the channel for the system interrupt N + 2.
15-8
SYSN1_MAP R/W
0
Sets the channel for the system interrupt N + 1.
7-0
SYSN_MAP
0
Sets the channel for the system interrupt N.
R/W
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12.8.2.21 HOSTMAP0 to HOSTMAP2 Register (Offset = 800h to 808h)
The Host Interrupt Map Registers define the host interrupt for each channel. There is one register per 4
channels. Channels with forced host interrupt mappings will have their fields read-only.
Table 12-86. HOSTMAP0 to HOSTMAP2 Register
31
24 23
CHANN3_MAP
R/W-0
16 15
CHANN2_MAP
R/W-0
8
7
0
CHANN1_MAP
R/W-0
CHANN_MAP
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-87. HOSTMAP0 to HOSTMAP2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
CHANN3_MA R/W
P
0
Sets the host interrupt for channel N + 3
23-16
CHANN2_MA R/W
P
0
Sets the host interrupt for channel N + 2
15-8
CHANN1_MA R/W
P
0
Sets the host interrupt for channel N + 1
7-0
CHANN_MA
P
0
Sets the host interrupt for channel N
R/W
12.8.2.22 HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register (Offset = 900h to 928h)
The Host Interrupt Prioritized Index Registers show the highest priority current pending interrupt for the
host interrupt. There is one register per host interrupt.
Table 12-88. HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register
31
NONE
R/O-1
30
10
9
RESERVED
R-0
0
PRI_INDEX
R/O-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-89. HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register Field Descriptions
Bit
31
Field
Type
Reset
NONE
R/O
1
30-10
RESERVED
R
0
9-0
PRI_INDEX
R/O
0
Description
No pending interrupt.
Interrupt number of the highest priority pending interrupt for this host
interrupt.
12.8.2.23 POLARITY0 Register (Offset = D00h)
The System Interrupt Polarity Registers define the polarity of the system interrupts. The polarity of all
system interrupts is active high; always write 1 to the bits of this register.
Table 12-90. POLARITY0 Register
31
0
POLARITY
R/W-Default_polarity[N]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 12-91. POLARITY0 Register Field Descriptions
Bit
31-0
12.8.2.24
Field
POLARITY
Type
R/W
Reset
Description
Default_polari Interrupt polarity of the system interrupts 0 to 31.
ty[N]
0 = active low
1 = active high
POLARITY1 Register (Offset = D04h)
The System Interrupt Polarity Registers define the polarity of the system interrupts. The polarity of all
system interrupts is active high; always write 1 to the bits of this register.
Table 12-92. POLARITY1 Register
31
0
POLARITY
R/W-Default_polarity[N]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-93. POLARITY1 Register Field Descriptions
Bit
31-0
12.8.2.25
Field
POLARITY
Type
R/W
Reset
Description
Default_polari Interrupt polarity of the system interrupts 32 to 63.
ty[N]
0 = active low
1 = active high
TYPE0 Register (Offset = D80h)
The Interrupt Type Registers define the type of the system interrupts. The type of all system interrupts is
pulse; always write 0 to the bits of this register.
Table 12-94. TYPE0 Register
31
0
TYPE
R/W-Default_type[N]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-95. TYPE0 Register Field Descriptions
Bit
31-0
12.8.2.26
Field
TYPE
Type
R/W
Reset
Description
Default_type[
N]
Interrupt type of the system interrupts 0 to 31.
0 = level or pulse interrupt
1 = edge interrupt (required edge detect)
TYPE1 Register (Offset = D84h)
The Interrupt Type Registers define the type of the system interrupts. The type of all system interrupts is
pulse; always write 0 to the bits of this register.
Table 12-96. TYPE1 Register
31
0
TYPE
R/W-Default_type[N]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 12-97. TYPE1 Register Field Descriptions
Bit
31-0
Field
TYPE
Type
R/W
Reset
Default_type[
N]
Description
Interrupt type of the system interrupts 32 to 63.
0 = level or pulse interrupt
1 = edge interrupt (required edge detect)
12.8.2.27 HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register (Offset = 1100h to 1128h)
The Host Interrupt Nesting Level Registers display and control the nesting level for each host interrupt.
The nesting level controls which channel and lower priority channels are nested. There is one register per
host interrupt.
Table 12-98. HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register
31
30
AUTO_OV
ERRIDE
W/O-0
9
8
0
RESERVED
NESTING_LEVEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-99. HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register Field Descriptions
Bit
31
Field
Type
Reset
AUTO_OVER W/O
RIDE
0
30-9
RESERVED
R
0
8-0
NESTING_L
EVEL
R/W
0
Description
Reads return 0. Writes of a 1 override the auto updating of the nesting_level
and use the write data.
Reads return the current nesting level for the host interrupt.
Writes set the nesting level for the host interrupt. In auto mode the value is
updated internally unless the auto_override is set and then the write data is
used.
12.8.2.28 HOSTINTEN Register (Offset = 1500h)
The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately
from the global enables. There is one bit per host interrupt. These bits are updated when writing to the
Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers.
Table 12-100. HOSTINTEN Register
31
10
9
RESERVED
R-0
0
ENABLES
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-101. HOSTINTEN Register Field Descriptions
Bit
31-10
9-0
Field
Type
Reset
RESERVED
R
0
ENABLES
R/W
0
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Description
The enable of the host interrupts (one per bit).
0 = disabled
1 = enabled
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Chapter 13
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DDR2/mDDR Memory Controller
This chapter describes the DDR2/mobile DDR (mDDR) memory controller.
Topic
13.1
13.2
13.3
13.4
328
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Supported Use Cases .......................................................................................
Registers .........................................................................................................
DDR2/mDDR Memory Controller
Page
329
331
359
364
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13.1 Introduction
13.1.1 Purpose of the Peripheral
The DDR2/mDDR memory controller is used to interface with JESD79D-2 standard compliant DDR2
SDRAM devices and JESD209 standard mobile DDR (mDDR) SDRAM devices. Memories types such as
DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The
DDR2/mDDR memory is the major memory location for program and data storage.
13.1.2 Features
The DDR2/mDDR memory controller supports the following features:
• JESD79D-2 standard compliant DDR2 SDRAM
• JESD209 standard compliant mobile DDR (mDDR)
• Data bus width of 16 bits
• CAS latencies:
– DDR2: 2, 3, 4, and 5
– mDDR: 2 and 3
• Internal banks:
– DDR2: 1, 2, 4, and 8
– mDDR: 1, 2, and 4
• Burst length: 8
• Burst type: sequential
• 1 CS signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM auto-initialization
• Self-refresh mode
• Partial array self-refresh (for mDDR)
• Power-down mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little-endian mode
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13.1.3 Functional Block Diagram
The DDR2/mDDR memory controller is the main interface to external DDR2/mDDR memory. Figure 13-1
displays the general data paths to on-chip peripherals and external DDR2/mDDR SDRAM.
Master peripherals, EDMA, and the CPU can access the DDR2/mDDR memory controller through the
switched central resource (SCR).
Figure 13-1. Data Paths to DDR2/mDDR Memory Controller
CPU
Master
peripherals
SCR
BUS
DDR2/mDDR
memory
controller
BUS
External
DDR2/mDDR SDRAM
EDMA
13.1.4 Supported Use Case Statement
The DDR2/mDDR memory controller supports JESD79D-2 DDR2 SDRAM memories and the JESD209
mobile DDR (mDDR) SDRAM memories utilizing 16 bits of the DDR2/mDDR memory controller data bus.
See Section 13.3 for more details.
13.1.5 Industry Standard(s) Compliance Statement
The DDR2/mDDR memory controller is compliant with the JESD79D-2 DDR2 SDRAM standard and the
JESD209 mobile DDR (mDDR) standard with the following exception:
• On-Die Termination (ODT). The DDR2/mDDR memory controller does not include any on-die
terminating resistors. Furthermore, the on-die terminating resistors of the DDR2/mDDR SDRAM device
must be disabled by tying the ODT input pin of the DDR2/mDDR SDRAM to ground.
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13.2 Architecture
This section describes the architecture of the DDR2/mDDR memory controller as well as how it is
structured and how it works within the context of the system-on-a-chip. The DDR2/mDDR memory
controller can gluelessly interface to most standard DDR2/mDDR SDRAM devices and supports such
features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through
programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections include details on how to interface and properly configure the DDR2/mDDR
memory controller to perform read and write operations to externally-connected DDR2/mDDR SDRAM
devices. Also, Section 13.3 provides a detailed example of interfacing the DDR2/mDDR memory controller
to a common DDR2/mDDR SDRAM device.
13.2.1 Clock Control
The DDR2/mDDR memory controller receives two input clocks from internal clock sources, VCLK and
2X_CLK (Figure 13-2). VCLK is a divided-down version of the PLL0 clock. 2X_CLK is the PLL1 clock.
2X_CLK should be configured to clock at the frequency of the desired data rate, or stated similarly, it
should operate at twice the frequency of the desired DDR2/mDDR memory clock. DDR_CLK and
DDR_CLK are the two output clocks of the DDR2/mDDR memory controller providing the interface clock
to the DDR2/mDDR SDRAM memory. These two clocks operate at a frequency of 2X_CLK/2.
13.2.1.1 Clock Source
VCLK and 2X_CLK are sourced from two independent PLLs (Figure 13-2). VCLK is sourced from PLL
controller 0 (PLLC0) and 2X_CLK is sourced from PLL controller 1 (PLLC1).
VCLK is clocked at a fixed divider ratio of PLL0. This divider is fixed at 2, meaning VCLK is clocked at a
frequency of PLL0/2.
The clock from PLLC1 is not divided before reaching 2X_CLK. PLLC1 should be configured to supply
2X_CLK at the desired frequency. For example, if a 138-MHz DDR2/mDDR interface clock (DDR_CLK) is
desired, then PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK.
Figure 13-2. DDR2/mDDR Memory Controller Clock Block Diagram
DDR_CLK
DDR_CLK
DDR2
memory
controller
VCLK
2X_CLK
/1
PLLC1
/2
PLLC0
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13.2.1.2 Clock Configuration
The frequency of 2X_CLK is configured by selecting the appropriate PLL multiplier. The PLL multiplier is
selected by programming registers within PLLC1. The PLLC1 divider ration is fixed at 1. For information
on programming the PLL controllers, see the Phase-Locked Loop Controller (PLLC) chapter. For
information on supported clock frequencies, see the Device Clocking chapter and your device-specific
data manual.
NOTE: PLLC1 should be configured and a stable clock present on 2X_CLK before releasing the
DDR2/mDDR memory controller from reset.
13.2.1.3 DDR2/mDDR Memory Controller Internal Clock Domains
There are two clock domains within the DDR2/mDDR memory controller. The two clock domains are
driven by VCLK and a divided-down by 2 version of 2X_CLK called MCLK. The command FIFO, write
FIFO, and read FIFO described in Section 13.2.6 are all on the VCLK domain. From this, VCLK drives the
interface to the peripheral bus.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
To conserve power within the DDR2/mDDR memory controller, VCLK, MCLK, and 2X_CLK may be
stopped. See Section 13.2.16 for proper clock stop procedures.
13.2.2 Signal Descriptions
The DDR2/mDDR memory controller signals are shown in Figure 13-3 and described in DDR2/mDDR
Memory Controller Signal Descriptions. The following features are included:
•
•
•
•
•
The maximum data bus is 16-bits wide.
The address bus is 14-bits wide with an additional three bank address pins.
Two differential output clocks driven by internal clock sources.
Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.
One chip select signal and one clock enable signal.
Figure 13-3. DDR2/mDDR Memory Controller Signals
DDR_CLK
DDR_CLK
DDR_CKE
DDR2
memory
controller
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_BA[2:0]
DDR_A[13:0]
DDR_D[15:0]
DDR_DQGATE0
DDR_DQGATE1
DDR_VREF
50 Ω
DDR_ZP
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DDR2/mDDR Memory Controller Signal Descriptions
(1)
Pin
Type
DDR_CLK,
DDR_CLK
O/Z
Clock: Differential clock outputs.
DDR_CKE
O/Z
Clock enable: Active high.
DDR_CS
O/Z
Chip select: Active low.
DDR_WE
O/Z
Write enable strobe: Active low, command output.
DDR_RAS
O/Z
Row address strobe: Active low, command output.
DDR_CAS
O/Z
Column address strobe: Active low, command output.
DDR_DQM[1:0]
O/Z
Data mask: Active high, output mask signal for write data.
DDR_DQS[1:0]
I/O/Z
Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
DDR_BA[2:0]
O/Z
Bank select: Output, defining which bank a given command is applied.
DDR_A[13:0]
O/Z
Address: Address bus.
DDR_D[15:0]
I/O/Z
Data: Bi-directional data bus. Input for read data, output for write data.
DDR_DQGATE0
O/Z
Strobe Enable: Active high.
DDR_DQGATE1
I/O/Z
Strobe Enable Delay: Loopback signal for timing adjustment (DQS gating). Route from
DDR_DQGATE0 to DDR device and back to DDR_DQGATE1 with same constraints as used for
DDR clock and data.
DDR_ZP
I/O/Z
Output drive strength reference: Reference output for drive strength calibration of N and P
channel outputs. Tie to ground via 50 ohm .5% tolerance 1/16th watt resistor (49.9 ohm .5%
tolerance is acceptable).
DDR_VREF
pwr
Voltage reference input: Voltage reference input for the SSTL_18 I/O buffers. Note even in the
case of mDDR an external resistor divider connected to this pin is necessary.
(1)
Description
Legend: I = input, O = Output, Z = high impedance, pwr = power
13.2.3 Protocol Description(s)
The DDR2/mDDR memory controller supports the DDR2/mDDR SDRAM commands listed in Table 13-1.
Table 13-2 shows the signal truth table for the DDR2/mDDR SDRAM commands.
Table 13-1. DDR2/mDDR SDRAM Commands
Command
Function
ACTV
Activates the selected bank and row.
DCAB
Precharge all command. Deactivates (precharges) all banks.
DEAC
Precharge single command. Deactivates (precharges) a single bank.
DESEL
Device Deselect.
EMRS
Extended Mode Register set. Allows altering the contents of the mode register.
MRS
Mode register set. Allows altering the contents of the mode register.
NOP
No operation.
Power Down
Power-down mode.
READ
Inputs the starting column address and begins the read operation.
READ with
autoprecharge
Inputs the starting column address and begins the read operation. The read operation is followed by a
precharge.
REFR
Autorefresh cycle.
SLFREFR
Self-refresh mode.
WRT
Inputs the starting column address and begins the write operation.
WRT with
autoprecharge
Inputs the starting column address and begins the write operation. The write operation is followed by a
precharge.
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Table 13-2. Truth Table for DDR2/mDDR SDRAM Commands
DDR2/mDDR
SDRAM:
DDR2/mDDR
memory
controller:
334
CKE
CS
RAS
CAS
WE
BA[2:0]
A[13:11, 9:0]
A10
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_CKE
Previous
Cycles
Current
Cycle
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA[2:0]
ACTV
H
H
L
L
H
H
Bank
DCAB
H
H
L
L
H
L
X
X
DEAC
H
H
L
L
H
L
Bank
X
MRS
H
H
L
L
L
L
BA
EMRS
H
H
L
L
L
L
BA
READ
H
H
L
H
L
H
BA
Column Address
L
READ with
precharge
H
H
L
H
L
H
BA
Column Address
H
WRT
H
H
L
H
L
L
BA
Column Address
L
WRT with
precharge
H
H
L
H
L
L
BA
Column Address
H
REFR
H
H
L
L
L
H
X
X
X
SLFREFR
entry
H
L
L
L
L
H
X
X
X
SLFREFR
exit
L
H
H
X
X
X
X
X
X
L
H
H
H
X
X
X
NOP
H
X
L
H
H
H
X
X
X
DESEL
H
X
H
X
X
X
X
X
X
Power Down
entry
H
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
Power Down
exit
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
H
DDR2/mDDR Memory Controller
Row Address
H
L
OP Code
OP Code
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13.2.3.1 Refresh Mode
The DDR2/mDDR memory controller issues refresh commands to the DDR2/mDDR SDRAM memory
(Figure 13-4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE
spaces and banks selected. Following the DCAB command, the DDR2/mDDR memory controller begins
performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register
(SDRCR). Page information is always invalid before and after a REFR command; thus, a refresh cycle
always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands
may not be disabled within the DDR2/mDDR memory controller. See Section 13.2.7 for more details on
REFR command scheduling.
Figure 13-4. Refresh Command
RFR
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
DDR_BA[2:0]
DDR_DQM[1:0]
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13.2.3.2 Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2/mDDR memory
controller or following the initialization sequence. DDR2/mDDR SDRAMs also require this cycle prior to a
refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command,
DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 13-5 shows the timing diagram for
a DCAB command.
Figure 13-5. DCAB Command
DCAB
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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The DEAC command closes a single bank of memory specified by the bank select signals. Figure 13-6
shows the timings diagram for a DEAC command.
Figure 13-6. DEAC Command
DEAC
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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13.2.3.3 Activation (ACTV)
The DDR2/mDDR memory controller automatically issues the activate (ACTV) command before a read or
write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses
(reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of
DDR_A[13:0] selects the row. When the DDR2/mDDR memory controller issues an ACTV command, a
delay of tRCD is incurred before a read or write command is issued. Figure 13-7 shows an example of an
ACTV command. Reads or writes to the currently active row and bank of memory can achieve much
higher throughput than reads or writes to random areas because every time a new row is accessed, the
ACTV command must be issued and a delay of tRCD incurred.
Figure 13-7. ACTV Command
DDR_CLK
DDR_CLK
ACTV
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
ROW
DDR_BA[2:0]
BANK
DDR_DQM[1:0]
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13.2.3.4 READ Command
Figure 13-8 shows the DDR2/mDDR memory controller performing a read burst from DDR2/mDDR
SDRAM. The READ command initiates a burst read operation to an active row. During the READ
command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on
DDR_A[13:0], and the bank address is driven on DDR_BA[2:0].
The DDR2/mDDR memory controller uses a burst length of 8, and has a programmable CAS latency of 2,
3, 4, or 5. The CAS latency is three cycles in Figure 13-8. Read latency is equal to CAS latency plus
additive latency. The DDR2/mDDR memory controller always configures the memory to have an additive
latency of 0, so read latency equals CAS latency. Since the default burst size is 8, the DDR2/mDDR
memory controller returns 8 pieces of data for every read command. If additional accesses are not
pending to the DDR2/mDDR memory controller, the read burst completes and the unneeded data is
disregarded. If additional accesses are pending, depending on the scheduling result, the DDR2/mDDR
memory controller can terminate the read burst and start a new read burst. Furthermore, the DDR2/mDDR
memory controller does not issue a DAB/DEAC command until page information becomes invalid.
Figure 13-8. DDR2/mDDR READ Command
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
CAS Latency
D0
DDR_D[15:0]
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
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13.2.3.5 Write (WRT) Command
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the
WRT command, a write latency is incurred. For DDR2, write latency is equal to CAS latency minus 1
cycles. For mDDR, write latency is equal to 1 cycle, always. All writes have a burst length of 8. The use of
the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 13-9 shows the timing for a
DDR2 write on the DDR2/mDDR memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pending
commands, the DDR2/mDDR memory controller can:
• Mask out the additional data using DDR_DQM outputs
• Terminate the write burst and start a new write burst
The DDR2/mDDR memory controller does not perform the DEAC command until page information
becomes invalid.
Figure 13-9. DDR2/mDDR WRT Command
DDR_CLK
DDR_CLK
Sample
Write Latency
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
DDR_D[15:0]
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
D0
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
NOTE: This diagrams shows write latency for DDR2. For mDDR, write latency is always equal to 1 cycle.
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13.2.3.6 Mode Register Set (MRS and EMRS)
DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on DDR2/mDDR device), single-ended strobe, differential strobe etc.
The DDR2/mDDR memory controller programs the mode and extended mode registers of the
DDR2/mDDR memory by issuing MRS and EMRS commands. When the MRS or EMRS command is
executed, the value on DDR_BA[2:0] selects the mode register to be written and the data on DDR_A[13:0]
is loaded into the register. Figure 13-10 shows the timing for an MRS and EMRS command.
The DDR2/mDDR memory controller only issues MRS and EMRS commands during the DDR2/mDDR
memory controller initialization sequence. See Section 13.2.13 for more information.
Figure 13-10. DDR2/mDDR MRS and EMRS Command
MRS/EMRS
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
13.2.4 Memory Width and Byte Alignment
The DDR2/mDDR memory controller supports memory widths of 16 bits. Table 13-3 summarizes the
addressable memory ranges on the DDR2/mDDR memory controller. Only little-endian format is
supported. Figure 13-11 shows the byte lanes used on the DDR2/mDDR memory controller. The external
memory is always right aligned on the data bus.
Table 13-3. Addressable Memory Ranges
Memory Width
Maximum addressable bytes per CS space
Description
×16
256 Mbytes
Halfword address
Figure 13-11. Byte Alignment
DDR2 memory controller data bus
DDR_D[15:8]
DDR_D[7:0]
16-bit memory device
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13.2.5 Address Mapping
The memory controller views the DDR2/mDDR SDRAM device as one continuous block of memory. The
memory controller receives memory access requests with a 32-bit logical address, and it uses the logical
address to generate a row, column, and bank address for accessing the DDR2/mDDR SDRAM device.
The memory controller supports two address mapping schemes: normal address mapping and special
address mapping. Special address mapping is typically used only with mDDR devices using partial array
self-refresh.
When the internal bank position (IBANKPOS) bit in the SDRAM configuration register (SDCR) is cleared,
the memory controller operates with normal address mapping. In this case, the number of column and
bank address bits is determined by the IBANK and PAGESIZE fields in SDCR. The number of row
address bits is determined by the number of valid address pins for the device and does not need to be set
in a register.
When IBANKPOS is set to 1, the memory controller operates with special address mapping. In this case,
the number of column, row, and bank address bits is determined by the PAGESIZE, ROWSIZE, and
IBANK fields. The ROWSIZE field is in the SDRAM configuration register 2 (SDCR2). See Table 13-4 for a
descriptions of these bit fields.
Table 13-4. Configuration Register Fields for Address Mapping
Bit Field
Bit Value
IBANK
Defines the number of internal banks in the external DDR2/mDDR memory.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
PAGESIZE
Defines the page size of each page in the external DDR2/mDDR memory.
0
256 words (requires 8 column address bits)
1h
512 words (requires 9 column address bits)
2h
1024 words (requires 10 column address bits)
3h
2048 words (requires 11 column address bits)
ROWSIZE
342
Bit Description
Defines the row size of each row in the external DDR2/mDDR memory
0
512 (requires 9 row address bits)
1h
1024 (requires 10 row address bits)
2h
2048 (requires 11 row address bits)
3h
4096 (requires 12 row address bits)
4h
8192 (requires 13 row address bits)
5h
16384 (requires 14 row address bits)
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13.2.5.1 Normal Address Mapping (IBANKPOS = 0)
As stated in Table 13-4, the IBANK and PAGESIZE fields of SDCR control the mapping of the logical,
source address of the DDR2/mDDR memory controller to the DDR2/mDDR SDRAM row, column, and
bank address bits. The DDR2/mDDR memory controller logical address always contains up to 14 row
address bits, whereas the number of column and bank bits are determined by the IBANK and PAGESIZE
fields. Table 13-5 show how the logical address bits map to the DDR2/mDDR SDRAM row, column, and
bank bits for combinations of IBANK and PAGESIZE values. The same DDR2/mDDR memory controller
pins provide the row and column address to the DDR2/mDDR SDRAM, thus the DDR2/mDDR memory
controller appropriately shifts the address during row and column address selection.
Logical Address-to-DDR2/mDDR SDRAM Address Map shows how this address-mapping scheme
organizes the DDR2/mDDR SDRAM rows, columns, and banks into the device memory-map. Note that
during a linear access, the DDR2/mDDR memory controller increments the column address as the logical
address increments. When the DDR2/mDDR memory controller reaches a page/row boundary, it moves
onto the same page/row in the next bank. This movement continues until the same page has been
accessed in all banks. To the DDR2/mDDR SDRAM, this process looks as shown in Figure 13-12.
By traversing across banks while remaining on the same row/page, the DDR2/mDDR memory controller
maximizes the number of activated banks for a linear access. This results in the maximum number of
open pages when performing a linear access being equal to the number of banks. Note that the
DDR2/mDDR memory controller never opens more than one page per bank.
Ending the current access is not a condition that forces the active DDR2/mDDR SDRAM row to be closed.
The DDR2/mDDR memory controller leaves the active row open until it becomes necessary to close it.
This decreases the deactivate-reactivate overhead.
Table 13-5. Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM
SDCR Bit
Logical Address
IBANK
PAGESIZE
31
0
0
-
1
0
-
2h
0
-
3h
0
-
0
1
-
1
1
-
2h
1
-
3h
1
-
0
2h
-
1
2h
-
2h
2h
-
3h
2h
-
0
3h
-
1
3h
-
2h
3h
-
3h
3h
-
30
29
28
27
26
25
24
23
22
21:15
14
13
12
11
10
9
nrb=14
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
0
ncb=8
ncb=8
nbb=3
ncb=8
nrb=14
ncb=9
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=9
ncb=9
nbb=3
ncb=9
nrb=14
ncb=10
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=10
ncb=10
nbb=3
ncb=10
nrb=14
ncb=11
nrb=14
nbb=1
nrb=14
nrb=14
8:1
ncb=8
nbb=2
nbb=3
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ncb=11
ncb=11
ncb=11
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Logical Address-to-DDR2/mDDR SDRAM Address Map
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 0
Row 1, bank 1
Row 1, bank 2
Row 1, bank P
Row N, bank 0
Row N, bank 1
Row N, bank 2
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
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Logical Address-to-DDR2/mDDR SDRAM Address Map (continued)
Figure 13-12. DDR2/mDDR SDRAM Column, Row, and Bank Access
Bank 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Bank 1
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Bank 2
Row 2
Row 0
Row 1
Bank P
Row 2
Row 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Row 2
Row N
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
13.2.5.2 Special Address Mapping (IBANKPOS = 1)
When the internal bank position (IBANKPOS) bit is set to 1, the PAGESIZE, ROWSIZE, and IBANK fields
control the mapping of the logical source address of the memory controller to the column, row, and bank
address bits of the SDRAM device. Table 13-6 shows which source address bits map to the SDRAM
column, row, and bank address bits for all combinations of PAGESIZE, ROWSIZE, and IBANK.
When IBANKPOS is set to 1, the effect of the address-mapping scheme is that as the source address
increments across an SDRAM page boundary, the memory controller proceeds to the next page in the
same bank. This movement along the same bank continues until all the pages have been accessed in the
same bank. The memory controller then proceeds to the next bank in the device. This sequence is shown
in Figure 13-13 and Figure 13-14.
Since, in this address mapping scheme, the memory controller can keep only one bank open, this scheme
is lower in performance than the case when IBANKPOS is cleared to 0. Therefore, this case is only
recommended to be used with Partial Array Self-refresh for mDDR SDRAM where performance may be
traded-off for power savings.
Table 13-6. Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1)
31
Source Address
Bank Address
Row Address
Number of bank bits is defined by
IBANK nbb = 1, 2, or 3
Number of row bits is defined by
ROWSIZE: nrb = 9, 10, 11, 12, 13, or 14
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Column Address
Number of column bits is defined by
PAGESIZE: ncb = 8, 9, 10, or 11
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Figure 13-13. Address Mapping Diagram (IBANKPOS = 1)
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 1, bank 0
Row 2, bank 0
Row 3, bank 0
Row N, bank 0
Row 1, bank 1
Row 2, bank 1
Row 3, bank 1
Row N, bank 1
Row 1, bank P
Row 2, bank P
Row 3, bank P
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
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Figure 13-14. SDRAM Column, Row, Bank Access (IBANKPOS = 1)
Bank 0
C C C
o o o
l l l
0 1 2 3
Row 0
Row 1
Row 2
C
o
l
M
Bank 1
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Row 1
Row 2
Bank 2
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Bank P
Row 0
Row 1
Row N
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 2
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
13.2.6 DDR2/mDDR Memory Controller Interface
To move data efficiently from on-chip resources to external DDR2/mDDR SDRAM memory, the
DDR2/mDDR memory controller makes use of a command FIFO, a write FIFO, a read FIFO, and
command and data schedulers. Table 13-7 describes the purpose of each FIFO.
Figure 13-15 shows the block diagram of the DDR2/mDDR memory controller FIFOs. Commands, write
data, and read data arrive at the DDR2/mDDR memory controller parallel to each other. The same
peripheral bus is used to write and read data from external memory as well as internal memory-mapped
registers.
Table 13-7. DDR2/mDDR Memory Controller FIFO Description
FIFO
Description
Depth (64-bit doublewords)
Command
Stores all commands coming from on-chip requestors
7
Write
Stores write data coming from on-chip requestors to memory
11
Read
Stores read data coming from memory to on-chip requestors
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Figure 13-15. DDR2/mDDR Memory Controller FIFO Block Diagram
Command FIFO
Command/Data
Scheduler
Command
to Memory
Write FIFO
Write Data
to Memory
Read FIFO
Read Data
from
Memory
Registers
Command
Data
13.2.6.1 Command Ordering and Scheduling, Advanced Concept
The DDR2/mDDR memory controller performs command re-ordering and scheduling in an attempt to
achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data,
address, and command buses while hiding the overhead of opening and closing DDR2/mDDR SDRAM
rows. Command re-ordering takes place within the command FIFO.
Typically, a given master issues commands on a single priority. EDMA transfer controller read and write
ports are different masters. The DDR2/mDDR memory controller first reorders commands from each
master based on the following rules:
• Selects the oldest command (first command in the queue)
• Selects a read before a write if:
– The read is to a different block address (2048 bytes) than the write
– The read has greater or equal priority
The second bullet above may be viewed as an exception to the first bullet. This means that for an
individual master, all of its commands will complete from oldest to newest, with the exception that a read
may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master
may have one command ready for execution.
Next, the DDR2/mDDR memory controller examines each of the commands selected by the individual
masters and performs the following reordering:
• Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes
to rows already open.
• Selects the highest priority command from pending reads and writes to open rows. If multiple
commands have the highest priority, then the DDR2/mDDR memory controller selects the oldest
command.
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The DDR2/mDDR memory controller may now have a final read and write command. If the Read FIFO is
not full, then the read command will be performed before the write command, otherwise the write
command will be performed first.
Besides commands received from on-chip resources, the DDR2/mDDR memory controller also issues
refresh commands. The DDR2/mDDR memory controller attempts to delay refresh commands as long as
possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2/mDDR
memory controller issues read, write, and refresh commands to DDR2/mDDR SDRAM memory, it adheres
to the following rules:
1. Refresh request resulting from the Refresh Must level of urgency being reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency being reached
6. Request to enter self-refresh mode
The following results from the above scheduling algorithm:
• All writes from a single master will complete in order
• All reads from a single master will complete in order
• From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
13.2.6.2 Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2/mDDR memory controller. Command
starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2/mDDR SDRAM commands to a row in an open bank can block
commands to the closed row in the same bank.
To avoid these conditions, the DDR2/mDDR memory controller can momentarily raises the priority of the
oldest command in the command FIFO after a set number of transfers have been made. The
PR_OLD_COUNT bit in the peripheral bus burst priority register (PBBPR) sets the number of the transfers
that must be made before the DDR2/mDDR memory controller will raise the priority of the oldest
command.
13.2.6.3 Possible Race Condition
A race condition may exist when certain masters write data to the DDR2/mDDR memory controller. For
example, if master A passes a software message via a buffer in DDR2/mDDR memory and does not wait
for indication that the write completes, when master B attempts to read the software message it may read
stale data and therefore receive an incorrect message. In order to confirm that a write from master A has
landed before a read from master B is performed, master A must wait for the write completion status from
the DDR2/mDDR memory controller before indicating to master B that the data is ready to be read. If
master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2/mDDR memory controller SDRAM status register.
3. Perform a dummy read to the DDR2/mDDR memory controller SDRAM status register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The EDMA peripheral does not need to implement the above workaround. The above workaround is
required for all other peripherals. See your device-specific data manual for more information.
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13.2.7 Refresh Scheduling
The DDR2/mDDR memory controller issues autorefresh (REFR) commands to DDR2/mDDR SDRAM
devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR).
A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until
it reaches zero. Once the interval counter reaches zero, it reloads with the value of the RR bit. Each time
the interval counter expires, a refresh backlog counter increments by 1. Conversely, each time the
DDR2/mDDR memory controller performs a REFR command, the backlog counter decrements by 1. This
means the refresh backlog counter records the number of REFR commands the DDR2/mDDR memory
controller currently has outstanding.
The DDR2/mDDR memory controller issues REFR commands based on the level of urgency. The level of
urgency is defined in Table 13-8. Whenever the refresh must level of urgency is reached, the
DDR2/mDDR memory controller issues a REFR command before servicing any new memory access
requests. Following a REFR command, the DDR2/mDDR memory controller waits T_RFC cycles, defined
in the SDRAM timing register 1 (SDTIMR1), before rechecking the refresh urgency level.
In addition to the refresh counter previously mentioned, a separate backlog counter ensures the interval
between two REFR commands does not exceed 8× the refresh rate. This backlog counter increments by 1
each time the interval counter expires and resets to zero when the DDR2/mDDR memory controller issues
a REFR command. When this backlog counter is greater than 7, the DDR2/mDDR memory controller
issues four REFR commands before servicing any new memory requests.
The refresh counters do not operate when the DDR2/mDDR memory is in self-refresh mode.
Table 13-8. Refresh Urgency Levels
Urgency Level
Description
Refresh May
Backlog count is greater than 0. Indicates there is a backlog of REFR commands, when the DDR2/mDDR
memory controller is not busy it will issue the REFR command.
Refresh Release
Backlog count is greater than 3. Indicates the level at which enough REFR commands have been performed
and the DDR2/mDDR memory controller may service new memory access requests.
Refresh Need
Backlog count is greater than 7. Indicates the DDR2/mDDR memory controller should raise the priority level
of a REFR command above servicing a new memory access.
Refresh Must
Backlog count is greater than 11. Indicates the level at which the DDR2/mDDR memory controller should
perform a REFR command before servicing new memory access requests.
13.2.8 Self-Refresh Mode
Clearing the self refresh/low power (SR_PD) bit to 0 and then setting the low power mode enable
(LPMODEN) bit to 1 in the SDRAM refresh control register (SDRCR) , forces the DDR2/mDDR memory
controller to place the external DDR2/mDDR SDRAM in a low-power mode (self refresh), in which the
DDR2/mDDR SDRAM maintains valid data while consuming a minimal amount of power. When the
LPMODEN bit is set to 1, the DDR2/mDDR memory controller continues normal operation until all
outstanding memory access requests have been serviced and the refresh backlog has been cleared. At
this point, all open pages of DDR2/mDDR SDRAM are closed and a self-refresh (SLFRFR) command (an
autorefresh command with self refresh/low power) is issued.
The memory controller exits the self-refresh state when a memory access is received, when the
LPMODEN bit in SDRCR is cleared to 0, or when the SR_PD bit in SDRCR changed to 1. While in the
self-refresh state, if a request for a memory access is received, the DDR2/mDDR memory controller
services the memory access request, returning to the self-refresh state upon completion. The
DDR2/mDDR memory controller will not wake up from the self-refresh state (whether from a memory
access request, from clearing the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles
have expired since the self-refresh command was issued. The value of T_CKE is defined in the SDRAM
timing register 2 (SDTIMR2).
In the case of DDR2, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR + 1 clock cycles before issuing non-read/write
commands and T_SXRD + 1 clock cycles before issuing read or write commands. The SDRAM timing
register 2 (SDTIMR2) programs the values of T_SXNR and T_SXRD.
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In the case of mDDR, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR+1 clock cycles and then execute auto-refresh
command before issuing any other commands. The SDRAM timing register 2 (SDTIMR2) programs the
value of T_SXNR.
Once in self-refresh mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK) may be
gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See
Section 13.2.16 for more information describing the proper procedure to follow when shutting down
DDR2/mDDR memory controller input clocks.
See Section 13.2.16.1 for a description of the self-refresh programming sequence.
13.2.9 Partial Array Self Refresh for Mobile DDR
For additional power savings during self-refresh, the partial array self-refresh (PASR) feature of the mDDR
allows you to select the amount of memory that will be refreshed during self-refresh. Use the partial array
self-refresh (PASR) bit field in the SDRAM configuration register 2 (SDCR2) to select the amount of
memory to refresh during self-refresh. As shown in Table 13-9 you may select either 4, 2, 1, 1/2, or 1/4
bank(s). The PASR bits are loaded into the extended mode register of the mDDR device, during
autoinitialization (see Section 13.2.13).
The mDDR performs bank interleaving when the internal bank position (IBANKPOS) bit in SDRAM
configuration register (SDCR) is cleared to 0. Since the SDRAM banks are only partially refreshed during
partial array self-refresh, it is recommended that you set IBANKPOS to 1 to avoid bank interleaving. When
IBANKPOS is cleared to 0, it is the responsibility of software to move critical data into the banks that are
to be refreshed during partial array self-refresh. Refer to Section 13.2.5.2 for more information on
IBANKPOS and addressing mapping in general.
Table 13-9. Configuration Bit Field for Partial Array Self-refresh
Bit Field
Bit Value
PASR
Bit Description
Partial array self refresh.
0
Refresh banks 0, 1, 2, and 3
1h
Refresh banks 0 and 1
2h
Refresh bank 0
5h
Refresh 1/2 of bank 0
6h
Refresh 1/4 of bank 0
13.2.10 Power-Down Mode
Setting the self-refresh/low power (SR_PD) bit and the low-power mode enable (LPMODEN) bit in the
SDRAM refresh control register (SDRCR) to 1, forces the DDR2/mDDR memory controller to place the
external DDR2 SDRAM in the power-down mode. When the LPMODEN bit is asserted, the DDR2/mDDR
memory controller continues normal operation until all outstanding memory access requests have been
serviced and the refresh backlog has been cleared. At this point, all open pages of DDR2 SDRAM are
closed and a Power Down command (same as NOP command but driving DDR_CKE low on the same
cycle) is issued.
The DDR2/mDDR memory controller exits the power-down state when a memory access is received,
when a Refresh Must level is reached, when the LPMODEN bit in SDRCR is cleared to 0, or when the
SR_PD bit in SDRCR changed to 0. While in the power-down state, if a request for a memory access is
received, the DDR2/mDDR memory controller services the memory access request, returning to the
power-down state upon completion. The DDR2/mDDR memory controller will not wake-up from the powerdown state (whether from a memory access request, from reaching a Refresh Must level, from clearing
the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the powerdown command was issued. The value of T_CKE is defined in the SDRAM timing register 2 (SDTIMR2).
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After exiting from the power-down state, the DDR2/mDDR memory controller will drive DDR_CKE high
and then not immediately start executing commands. Instead, it will wait T_XP + 1 clock cycles before
issuing commands. The SDRAM timing register 2 (SDTIMR2) programs the values of T_XP.
See Section 13.2.16.1 for a description of the power-down mode programming sequence.
NOTE: Power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
13.2.11 Reset Considerations
The DDR2/mDDR memory controller has two reset signals, chip_rst_n and mod_g_rst_n. The chip_rst_n
is a module-level reset that resets both the state machine as well as the DDR2/mDDR memory controller
memory-mapped registers. The mod_g_rst_n resets the state machine only; it does not reset the
controller's registers, which allows soft reset (from PSC or WDT) to reset the module without resetting the
configuration registers and reduces the programming overhead for setting up access to the DDR2/mDDR
device. If the DDR2/mDDR memory controller is reset independently of other peripherals, the user's
software should not perform memory, as well as register accesses, while chip_rst_n or mod_g_rst_n are
asserted. If memory or register accesses are performed while the DDR2/mDDR memory controller is in
the reset state, other masters may hang. Following the rising edge of chip_rst_n or mod_g_rst_n, the
DDR2/mDDR memory controller immediately begins its initialization sequence. Command and data stored
in the DDR2/mDDR memory controller FIFOs are lost. Table 13-10 describes the different methods for
asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master controller for power
management for all of the peripherals on the device. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. Figure 13-16 shows the
DDR2/mDDR memory controller reset diagram.
Table 13-10. Reset Sources
Reset Signal
Reset Source
chip_rst_n
Hardware/device reset
mod_g_rst_n
Power and sleep controller
Figure 13-16. DDR2/mDDR Memory Controller Reset Block Diagram
Hard
Reset from
PLLC0
DDR
PSC
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DDR2/mDDR Memory Controller
chip_rst_n
mod_g_rst_n
DDR2/mDDR
memory
controller
registers
State
machine
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13.2.12 VTP IO Buffer Calibration
The DDR2/mDDR memory controller is able to control the impedance of the output IO. This feature allows
the DDR2/mDDR memory controller to tune the output impedance of the IO to match that of the PCB
board. Control of the output impedance of the IO is an important feature because impedance matching
reduces reflections, creating a cleaner board design. Calibrating the output impedance of the IO will also
reduce the power consumption of the DDR2/mDDR memory controller. The calibration is performed with
respect to voltage, temperature, and process (VTP). The VTP information obtained from the calibration is
used to control the output impedance of the IO.
The impedance of the output IO is selected by the value of a reference resistor connected to pin DDR_ZP.
The DDR2/mDDR reference design requires the reference resistor to be a 50 ohm, 5.0% tolerance, 1/16th
watt resistor (49.9 ohm, 0.5% tolerance is acceptable).
The VTP IO control register (VTPIO_CTL) is written to begin the calibration process. The VTP calibration
process is described in the DDR2/mDDR initialization sequence in Section 13.2.13.1.
NOTE: VTP IO calibration must be performed following device power up and device reset. If the
DDR2/mDDR memory controller is reset via the Power and Sleep Controller (PSC) and the
VTP input clock is disabled, accesses to the DDR2/mDDR memory controller will not
complete. To re-enable accesses to the DDR2/mDDR memory controller, enable the VTP
input clock and then perform the VTP calibration sequence again.
13.2.13 Auto-Initialization Sequence
The DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on the DDR2/mDDR device), single-ended strobe, differential strobe, etc. The DDR2/mDDR memory
controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS
and EMRS commands during the initialization sequence. The SDRAMEN, MSDRAMEN, DDREN, and
DDR2EN bits in the SDRAM configuration register (SDCR) determine if the DDR2/mDDR memory
controller will perform a DDR2 or mobile DDR initialization sequence. Set these bits as follows for DDR2:
SDRAMEN = 1, MSDRAMEN = 0, DDREN = 1, DDR2EN = 1. Set these bits as follow for mDDR:
SDRAMEN = 1, MSDRAMEN = 1, DDREN = 1, DDR2EN = 0. The DDR2 initialization sequence
performed by the DDR2/mDDR memory controller is compliant with the JESD79D-2 specification and the
mDDR initialization sequence is compliant with the JESD209 specification. The DDR2/mDDR memory
controller performs an initialization sequence under the following conditions:
• Following reset (rising edge of chip_rst_n or mod_g_rst_n)
• Following a write to the DDRDRIVE, CL, IBANK, or PAGESIZE bit fields in the SDRAM configuration
register (SDCR)
During the initialization sequence, the memory controller issues MRS and EMRS commands that
configure the DDR2/mobile DDR SDRAM mode register and extended mode register 1. The register
values for DDR2 are described in Table 13-11 and Table 13-12, and the register values for mDDR are
described in Table 13-13 and Table 13-14. The extended mode registers 2 and 3 are configured with a
value of 0h. At the end of the initialization sequence, the memory controller performs an autorefresh cycle,
leaving the memory controller in an idle state with all banks deactivated.
When a reset occurs, the DDR2/mDDR memory controller immediately begins the initialization sequence.
Under this condition, commands and data stored in the DDR2/mDDR memory controller FIFOs will be lost.
However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDCR,
data and commands stored in the DDR2/mDDR memory controller FIFOs will not be lost and the
DDR2/mDDR memory controller will ensure read and write commands are completed before starting the
initialization sequence.
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Table 13-11. DDR2 SDRAM Configuration by MRS Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Power Down Exit
Fast exit
DDR_A[11:9]
t_WR
11:9
Write Recovery
Write recovery from autoprecharge. Value of 2,
3, 4, 5, or 6 is programmed based on value of
the T_WR bit in the SDRAM timing register 1
(SDTIMR1 ).
DDR_A[8]
0
8
DLL Reset
Out of reset
DDR_A[7]
0
7
Mode: Test or Normal
Normal mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2, 3, 4, or 5 is programmed based on
value of the CL bit in the SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
Table 13-12. DDR2 SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Output Buffer Enable
Output buffer enable
DDR_A[11]
0
11
RDQS Enable
RDQS disable
DDR_A[10]
1
10
DQS enable
Disables differential DQS signaling.
DDR_A[9:7]
0
9:7
OCD Calibration Program
Exit OCD calibration
DDR_A[6]
0
6
ODT Value (Rtt)
Cleared to 0 to select 75 ohms. This feature
is not supported because the DDR_ODT
signal is not pinned out.
DDR_A[5:3]
0
5:3
Additive Latency
0 cycles of additive latency
DDR_A[2]
1
2
ODT Value (Rtt)
Set to 1 to select 75 ohms. This feature is not
supported because the DDR_ODT signal is
not pinned out.
DDR_A[1]
DDRDRIVE[0]
1
Output Driver Impedance
Value of 0 or 1 is programmed based on
value of DDRDRIVE0 bit in SDRAM
configuration register (SDCR).
DDR_A[0]
0
0
DLL enable
DLL enable
Table 13-13. Mobile DDR SDRAM Configuration by MRS Command
354
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating mode
Normal operating mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2 or 3 is programmed based on
value of CL bit in SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
DDR2/mDDR Memory Controller
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Table 13-14. Mobile DDR SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating Mode
Normal operating mode
DDR_A[6:5]
DDRDRIVE[1:0]
6:5
Output Driver Impedance
Value of 0, 1, 2, or 3 is programmed based
on value of DDRDRIVE[1:0] bits in SDRAM
configuration register (SDCR).
DDR_A[4:3]
0
4:3
Temperature Compensated
Self Refresh
Value of 0
DDR_A[2:0]
PASR bits
2:0
Partial Array Self Refresh
Value of 0, 1, 2, 5, or 6 is programmed based
on value of PASR bits in SDRAM
configuration register 2 (SDCR2).
13.2.13.1 Initializing Following Device Power Up or Reset
Following device power up or reset, the DDR2/mDDR memory controller is held in reset with the internal
clocks to the module gated off. Before releasing the DDR2/mDDR memory controller from reset, the
clocks to the module must be turned on. Perform the following steps when turning the clocks on and
initializing the module:
1. Program PLLC1 registers to start the PLL1_SYSCLK1 (that drives 2X_CLK). For information on
programming PLLC1, see the Phase-Locked Loop Controller (PLLC) chapter.
2. Program Power and Sleep Controller (PSC) to enable the DDR2/mDDR memory controller clock.
3. Perform VTP IO calibration:
(a) Clear POWERDN bit in the VTP IO control register (VTPIO_CTL).
(b) Clear LOCK bit in VTPIO_CTL.
(c) Pulse CLKRZ bit in VTPIO_CTL:
(i) Set CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(ii) Clear CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(iii) Set CLKRZ bit.
(d) Poll READY bit in VTPIO_CTL until it changes to 1.
(e) Set LOCK bit in VTPIO_CTL. VTP is locked and dynamic calibration is disabled.
(f) Set POWERDN bit in VTPIO_CTL to save power.
4. Set IOPWRDN bit in VTPIO_CTL to allow the input receivers to save power when the PWRDNEN bit in
the DDR PHY control register 1 (DRPYC1R) is set.
5. Configure DRPYC1R. All of the following steps may be done with a single register write to DRPYC1R:
(a) Set EXT_STRBEN bit to select external DQS strobe gating.
(b) Set PWRDNEN bit to allow the input receivers to power down when they are idle.
(c) Program RL bit value to meet the memory data sheet specification.
6. Configure the DDR slew register (DDR_SLEW):
(a) For DDR2, clear DDR_PDENA and CMOSEN bits.
(b) For mDDR, set the DDR_PDENA and CMOSEN bits.
7. Set the BOOTUNLOCK bit (unlocked) in the SDRAM configuration register (SDCR).
8. Program SDCR to the desired value with BOOTUNLOCK bit cleared to 0 and TIMUNLOCK bit set to 1
(unlocked).
9. For mDDR only, program the SDRAM configuration register 2 (SDCR2) to the desired value.
10. Program the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) to the
desired values to meet the memory data sheet specification.
11. Clear TIMUNLOCK bit (locked) in SDCR.
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12. Program the SDRAM refresh control register (SDRCR). All of the following steps may be done with a
single register write to SDRCR:
(a) Set LPMODEN bit to enable self-refresh. This is necessary for the next two steps.
(b) Set MCLKSTOPEN bit to enable MCLK stopping. This is necessary for the next two steps.
(c) Clear SR_PD bit to select self-refresh. This is necessary for the next two steps.
(d) Program RR refresh rate value to meet the memory data sheet specification.
13. Program the Power and Sleep Controller (PSC) to reset (SyncReset) the DDR2/mDDR memory
controller.
14. Program the Power and Sleep Controller (PSC) to re-enable the DDR2/mDDR memory controller.
15. Clear LPMODEN and MCLKSTOPEN bits in SDRCR to disable self-refresh.
16. Configure the peripheral bus burst priority register (PBBPR) to a value lower than the default value of
FFh. A lower value reduces the likelihood of prolonged command starvation for accesses made from
different master/peripherals to mDDR/DDR2 memory. The optimal value should be determined based
on system considerations; however, a value of 20h or 30h is sufficient for typical applications.
NOTE: Some memory data sheet timing values such as those programmed into the SDRAM timing
register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) may need to be relaxed in
order to compensate for signal delays introduced by board layout.
13.2.14 Interrupt Support
The DDR2/mDDR memory controller supports two addressing modes, linear incrementing and cache line
wrap. Upon receipt of an access request for an unsupported addressing mode, the DDR2/mDDR memory
controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). The DDR2/mDDR
memory controller will then treat the request as a linear incrementing request.
This interrupt is called the line trap interrupt and is the only interrupt the DDR2/mDDR memory controller
supports. It is an active-high interrupt and is enabled by the LTMSET bit in the interrupt mask set register
(IMSR). This interrupt is mapped to the CPU and is multiplexed with RTCINT.
13.2.15 DMA Event Support
The DDR2/mDDR memory controller is a DMA slave peripheral and therefore does not generate DMA
events. Data read and write requests may be made directly by masters and by the DMA.
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13.2.16 Power Management
Power dissipation from the DDR2/mDDR memory controller may be managed by the following methods:
• Self-refresh mode (see Section 13.2.8)
• Power-down mode (see Section 13.2.10)
• Disabling the DDR PHY to reduce power
The DDR2/mDDR memory controller supports low-power modes where the DLL internal to the PHY
and the receivers at the I/O pins can be disabled. These functions are controlled through the
DDR2/mDDR memory controller. Even if the PHY is active, the receivers can be configured to disable
whenever writes are in progress and the receivers are not needed.
• Gating input clocks to the module off
Gating input clocks off to the DDR2/mDDR memory controller achieves higher power savings when
compared to the power savings of self-refresh mode and power-down mode. The input clocks are
turned off outside of the DDR2/mDDR memory controller through the use of the Power and Sleep
Controller (PSC) and the PLL controller 1 (PLLC1). Figure 13-17 shows the connections between the
DDR2/mDDR memory controller, PSC, and PLLC1. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter.
Before gating clocks off, the DDR2/mDDR memory controller must place the DDR2/mDDR SDRAM
memory in self-refresh mode. If the external memory requires a continuous clock, the DDR2/mDDR
memory controller clock provided by PLLC1 must not be turned off because this may result in data
corruption. See the following subsections for the proper procedures to follow when stopping the
DDR2/mDDR memory controller clocks. Once the clocks are stopped, to re-enable the clocks follow
the clock stop procedure in each respective subsection in reverse order.
Figure 13-17. DDR2/mDDR Memory Controller Power Sleep Controller Diagram
PLL0_SYSCLK2/2
CLKSTOP_REQ
VCLKSTOP_REQ
CLKSTOP_ACK
VCLKSTOP_ACK
DDR
PST
MODCLK
MODRST
LRST
DDR2/mDDR
memory
VCLK
controller
chip_rst_n
mod_g_rst_n
2X_CLK
PLLC1
/1
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13.2.16.1 DDR2/mDDR Memory Controller Clock Stop Procedure
NOTE: If a data access occurs to the DDR2/mDDR memory after completing steps 1-4, the DLL will
wake up and lock, then the MCLK will turn on and the access will be performed. Following
steps 5 and 6, in which the clocks are disabled , all DDR2/mDDR memory accesses are not
possible until the clocks are reenabled.
In power-down mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK)
may not be gated off. This is a limitation of the DDR2/mDDR controller. For this reason,
power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
To achieve maximum power savings VCLK, MCLK, 2X_CLK, DDR_CLK, and DDR_CLK should be gated
off. The procedure for clock gating is described in the following steps.
1. Allow software to complete the desired DDR transfers.
2. Change the SR_PD bit to 0 and set the LPMODEN bit to 1 in the DDR2 SDRAM refresh control
register (SDRCR) to enable self-refresh mode. The DDR2/mDDR memory controller will complete any
outstanding accesses and backlogged refresh cycles and then place the external DDR2/mDDR
memory in self-refresh mode.
3. Set the MCLKSTOPEN bit in SDRCR to 1. This enables the DDR2/mDDR memory controller to shut
off the MCLK.
4. Wait 150 CPU clock cycles to allow the MCLK to stop.
5. Program the PSC to disable the DDR2/mDDR memory controller VCLK. You must not disable VCLK in
power-down mode; use only for self-refresh mode (see notes in this section).
6. For maximum power savings, the PLL/PLLC1 should be placed in bypass and powered-down mode to
disable 2X_CLK. You must not disable 2X_CLK in power-down mode; use only for self-refresh mode
(see notes in this section). For information on programming PLLC1, see the Phase-Locked Loop
Controller (PLLC) chapter.
To
1.
2.
3.
turn clocks back on:
Place the PLL/PLLC1 in PLL mode to start 2X_CLK to the DDR2/mDDR memory controller.
Once 2X_CLK is stable, program the PSC to enable VCLK.
Set the RESET_PHY bit in the DDR PHY reset control register (DRPYRCR) to 1. This resets the
DDR2/mDDR memory controller PHY. This bit will self-clear to 0 when reset is complete.
4. Clear the MCLKSTOPEN bit in SDRCR to 0.
5. Clear the LPMODEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.
13.2.17 Emulation Considerations
The DDR2/mDDR memory controller will remain fully functional during emulation halts to allow emulation
access to external memory.
NOTE: VTP IO calibration must be performed before emulation tools attempt to access the register
or data space of the DDR2/mDDR memory controller. A bus lock-up condition will occur if the
emulation tool attempts to access the register or data space of the DDR2/mDDR memory
controller before completing VTP IO calibration. See Section 13.2.12 for information on VTP
IO calibration.
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13.3 Supported Use Cases
The DDR2/mDDR memory controller allows a high degree of programmability for shaping DDR2/mDDR
accesses. The programmability inherent to the DDR2/mDDR memory controller provides the DDR2/mDDR
memory controller with the flexibility to interface with a variety of DDR2/mDDR devices. By programming
the SDRAM configuration register (SDCR), SDRAM refresh control register (SDRCR), SDRAM timing
register 1 (SDTIMR1), and SDRAM timing register 2 (SDTIMR2), the DDR2/mDDR memory controller can
be configured to meet the data sheet specification for DDR2 SDRAM as well as mDDR memory devices.
This section presents an example describing how to interface the DDR2 memory controller to a
DDR2/mDDR-400 device. The DDR2/mDDR memory controller is assumed to be operating at 150 MHz. A
similar procedure can be followed when interfacing to a mDDR memory device.
Connecting the DDR2/mDDR Memory Controller to DDR2/mDDR Memory
Figure 13-18 shows how to connect the DDR2/mDDR memory controller to a DDR2 device. Figure 13-18
displays a 16-bit interface; you can see that all signals are point-to-point connection.
Figure 13-18. Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR2/mDDR
DDR_WE
memory
DDR_RAS
controller
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[15:0]
CK
CK
CKE
DDR2
CS
memory
WE
x16−bit
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR_ZP
50 Ω
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Configuring Memory-Mapped Registers to Meet DDR2 Specification
As previously stated, four memory-mapped registers must be programmed to configure the DDR2/mDDR
memory controller to meet the data sheet specification of the attached DDR2/mDDR device. The registers
are:
• SDRAM configuration register (SDCR)
• SDRAM refresh control register (SDRCR)
• SDRAM timing register 1 (SDTIMR1)
• SDRAM timing register 2 (SDTIMR2)
In addition to these registers, the DDR PHY control register (DRPYC1R) must also be programmed. The
configuration of DRPYC1R is not dependent on the DDR2 device specification but rather on the board
layout.
The following sections describe how to configure each of these registers. See Section 13.4 for more
information on the DDR2/mDDR memory controller registers.
NOTE: When interfacing the DDR2/mDDR memory controller to a mDDR device, the SDRAM
configuration register 2 (SDCR2) must be programmed in addition to the registers mentioned
above.
Configuring SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains register fields that configure the DDR2/mDDR
memory controller to match the data bus width, CAS latency, number of banks, and page size of the
attached memory. In this example, we assume the following DDR2 configuration:
• Data bus width = 16 bits
• CAS latency = 3
• Number of banks = 8
• Page size = 1024 words
Table 13-15 shows the resulting SDCR configuration. Note that the value of the TIMING_UNLOCK field is
dependent on whether or not it is desirable to unlock SDTIMR1 and SDTIMR2. The TIMING_UNLOCK bit
should only be set to 1 when the SDTIMR1 and SDTIMR2 needs to be updated.
Table 13-15. SDCR Configuration
360
Field
Value
Function Selection
TIMING_UNLOCK
x
Set to 1 to unlock the SDRAM timing register 1 and SDRAM timing register 2.
Cleared to 0 to lock the SDRAM timing register 1 and SDRAM timing register 2.
NM
1h
To configure the DDR2/mDDR memory controller for a 16-bit data bus width.
CL
3h
To select a CAS latency of 3.
IBANK
3h
To select 8 internal DDR2 banks.
PAGESIZE
2h
To select 1024-word page size.
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Configuring SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) configures the DDR2/mDDR memory controller to meet the
refresh requirements of the attached memory device. SDRCR also allows the DDR2/mDDR memory
controller to enter and exit self refresh and enable and disable the MCLK stopping. In this example, we
assume that the DDR2/mDDR memory controller is not is in self-refresh mode or power-down mode and
that MCLK stopping is disabled.
The RR field in SDRCR is defined as the rate at which the attached memory device is refreshed in
DDR2/mDDR cycles. The value of this field may be calculated using the following equation:
RR = DDR2/mDDR clock frequency × DDR2/mDDR memory refresh period
Table 13-16 displays the DDR2-400 refresh rate specification.
Table 13-16. DDR2 Memory Refresh Specification
Symbol
Description
Value
tREF
Average Periodic Refresh Interval
7.8 μs
Therefore, the following results assuming 150 MHz DDR2/mDDR clock frequency.
RR = 150 MHz × 7.8 μs = 1170
Therefore, RR = 1170 = 492h.
Table 13-17 shows the resulting SDRCR configuration.
Table 13-17. SDRCR Configuration
Field
Value
Function Selection
LPMODEN
0
DDR2/mDDR memory controller is not in power-down mode.
MCLKSTOP_EN
0
MCLK stopping is disabled.
SR_PD
0
Leave a default value.
RR
492h
Set to 492h DDR2 clock cycles to meet the DDR2/mDDR memory refresh rate requirement.
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Configuring SDRAM Timing Registers (SDTIMR1 and SDTIMR2)
The SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) configure the
DDR2/mDDR memory controller to meet the data sheet timing parameters of the attached memory device.
Each field in SDTIMR1 and SDTIMR2 corresponds to a timing parameter in the DDR2/mDDR data sheet
specification. Table 13-18 and Table 13-19 display the register field name and corresponding DDR2 data
sheet parameter name along with the data sheet value. These tables also provide a formula to calculate
the register field value and displays the resulting calculation. Each of the equations include a minus 1
because the register fields are defined in terms of DDR2/mDDR clock cycles minus 1. See Section 13.4.4
and Section 13.4.5 for more information.
Table 13-18. SDTIMR1 Configuration
Register
Field Name
DDR2 Data
Manual
Parameter
Name
Description
Data Manual
Value (nS)
Formula
(Register field must be ≥)
Register
Value
T_RFC
tRFC
Refresh cycle time
127.5
(tRFC × fDDR2/mDDR_CLK) - 1
19
T_RP
tRP
Precharge command to
refresh or activate
command
15
(tRP × fDDR2/mDDR_CLK) - 1
2
T_RCD
tRCD
Activate command to
read/write command
15
(tRCD × fDDR2/mDDR_CLK) - 1
2
T_WR
tWR
Write recovery time
15
(tWR × fDDR2/mDDR_CLK) - 1
2
T_RAS
tRAS
Active to precharge
command
40
(tRAC × fDDR2/mDDR_CLK) - 1
5
T_RC
tRC
Activate to Activate
command in the same
bank
55
(tRC × fDDR2/mDDR_CLK) - 1
8
T_RRD (1)
tRRD
Activate to Activate
command in a different
bank
10
((4 × tRRD) + (2 × tCK))/(4 × tCK) - 1
1
T_WTR
tWTR
Write to read command
delay
10
(tWTR × fDDR2/mDDR_CLK) - 1
1
(1)
The formula for the T_RRD field applies only for 8 bank DDR2/mDDR memories; when interfacing to DDR2/mDDR memories
with less than 8 banks, the T_RRD field should be calculated using the following formula: (tRRD × fDDR2/mDDR_CLK) - 1.
Table 13-19. SDTIMR2 Configuration
362
Register
Field Name
DDR2 Data
Manual
Parameter
Name
T_RASMAX
tRAS(MAX)
T_XP
Data Manual
Value
Formula
(Register field must be ≥)
Register
Value
Active to precharge
command
70 μs
tRAS(MAX)/DDR refresh rate- 1
8
tXP
Exit power down to a nonread command
2(tCK cycles)
If tXP > tCKE,
then T_XP = tXP- 1,
else T_XP = tCKE- 1
2
T_XSNR
tXSNR
Exit self refresh to a nonread command
137.5 nS
(tXSNR × fDDR2/mDDR_CLK) - 1
18
T_XSRD
tXSRD
Exit self refresh to a read
command
200 (tCK cycles)
tXSRD - 1
199
T_RTP
tRTP
Read to precharge
command delay
15 nS
(tRTP × fDDR2/mDDR_CLK) - 1
1
T_CKE
tCKE
CKE minimum pulse width
3 (tCK cycles)
tCKE - 1
2
Description
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Configuring DDR PHY Control Register (DRPYC1R)
The DDR PHY control register (DRPYC1R) contains a read latency (RL) field that helps the DDR2/mDDR
memory controller determine when to sample read data. The RL field should be programmed to a value
equal to the CAS latency plus the round trip board delay minus 1. The minimum RL value is CAS latency
plus 1 and the maximum RL value is CAS latency plus 2 (again, the RL field would be programmed to
these values minus 1). Table 13-20 shows the resulting DRPYC1R configuration.
When calculating round trip board delay the signals of primary concern are the differential clock signals
(DDR_CLK and DDR_CLK) and data strobe signals (DDR_DQS). For these signals, calculate the round
trip board delay from the DDR memory controller to the memory and then choose the maximum delay to
determine the RL value. In this example, we will assume the round trip board delay is one DDR_CLK
cycle; therefore, RL can be calculated as:
RL = CAS latency + round trip board delay – 1 = 4 + 1 – 1 = 4
Table 13-20. DRPYC1R Configuration
Field
Value
Function Selection
EXT_STRBEN
1h
Programs to select external strobe gating
RL
4h
Read latency is equal to CAS latency plus round trip board delay for data minus 1
PWRDNEN
0
Programmed to power up the DDR2/mDDR memory controller receivers
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13.4 Registers
Table 13-21 lists the memory-mapped registers for the DDR2/mDDR memory controller. Note that the
VTP IO control register (VTPIO_CTL) resides in the System Configuration Module.
Table 13-21. DDR2/mDDR Memory Controller Registers
Address Offset
(1)
Acronym
Register Description
Section
0h
REVID
Revision ID Register
4h
SDRSTAT
SDRAM Status Register
Section 13.4.1
8h
SDCR
SDRAM Configuration Register
Section 13.4.2
Revision ID Register
(REVID)
Ch
SDRCR
SDRAM Refresh Control Register
Section 13.4.3
10h
SDTIMR1
SDRAM Timing Register 1
Section 13.4.4
14h
SDTIMR2
SDRAM Timing Register 2
Section 13.4.5
1Ch
SDCR2
SDRAM Configuration Register 2
Section 13.4.6
20h
PBBPR
Peripheral Bus Burst Priority Register
Section 13.4.7
40h
PC1
Performance Counter 1 Register
Section 13.4.8
44h
PC2
Performance Counter 2 Register
Section 13.4.9
48h
PCC
Performance Counter Configuration Register
Section 13.4.10
4Ch
PCMRS
Performance Counter Master Region Select Register
Section 13.4.11
50h
PCT
Performance Counter Time Register
Performance
Counter Time
Register (PCT)
60h
DRPYRCR
DDR PHY Reset Control Register
Section 13.4.12
C0h
IRR
Interrupt Raw Register
Section 13.4.13
C4h
IMR
Interrupt Masked Register
Section 13.4.14
C8h
IMSR
Interrupt Mask Set Register
Section 13.4.15
CCh
IMCR
Interrupt Mask Clear Register
Section 13.4.16
E4h
DRPYC1R
DDR PHY Control Register 1
Section 13.4.17
01E2 C000h (1)
VTPIO_CTL
VTP IO Control Register
Section 10.5.19
01E2 C004h (1)
DDR_SLEW
DDR Slew Register
Section 10.5.20
This register resides in the register space of the System Configuration (SYSCFG) Module. It is listed in the register space of the
DDR2/mDDR controller because it is applicable to the DDR2/mDDR controller.
Revision ID Register (REVID)
The revision ID register (REVID) contains the current revision ID for the DDR2/mDDR memory controller.
The REVID is shown in Figure 13-19 and described in Table 13-22.
Figure 13-19. Revision ID Register (REVID)
31
0
REV
R-4031 1B1Fh
LEGEND: R = Read only; -n = value after reset
Table 13-22. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4031 1B1Fh
364
Description
Revision ID value of the DDR2/mDDR memory controller.
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13.4.1 SDRAM Status Register (SDRSTAT)
The SDRAM status register (SDRSTAT) is shown in Figure 13-20 and described in Table 13-23.
Figure 13-20. SDRAM Status Register (SDRSTAT)
31
30
29
Rsvd
DUALCLK
Reserved
16
R-0
R-1
R-0
15
3
2
1
0
Reserved
PHYRDY
Reserved
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-23. SDRAM Status Register (SDRSTAT) Field Descriptions
Bit
Field
31
Reserved
30
DUALCLK
29-3
Reserved
2
PHYRDY
1-0
Reserved
Value
0
Description
Reserved
Dual clock. Specifies whether the VCLK and MCLK inputs are asynchronous. This bit should always be
read as 1.
0
VCLK and MCLK are not asynchronous.
1
VCLK and MCLK are asynchronous.
0
Reserved
DDR2/mDDR memory controller DLL ready. Specifies whether the DDR2/mDDR memory controller DLL
is powered up and locked.
0
DLL is not ready, either powered down, in reset, or not locked.
1
DLL is powered up, locked, and ready for operation.
0
Reserved
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13.4.2 SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains fields that program the DDR2/mDDR memory
controller to meet the specification of the attached DDR2/mDDR memory. These fields configure the
DDR2/mDDR memory controller to match the data bus width, CAS latency, number of internal banks, and
page size of the attached DDR2/mDDR memory. Writing to the DDRDRIVE[1:0], CL, IBANK, and
PAGESIZE bit fields causes the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM
initialization sequence. The SDCR is shown in Figure 13-21 and described in Table 13-24.
Figure 13-21. SDRAM Configuration Register (SDCR)
31
27
26
25
24
Reserved
28
DDR2TERM1
IBANK_POS
MSDRAMEN
DDRDRIVE1
R-0
R/W-1
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
BOOTUNLOCK
DDR2DDQS
DDR2TERM0
DDR2EN
DDRDLL_DIS
DDRDRIVE0
DDREN
SDRAMEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
13
12
11
15
14
TIMUNLOCK
NM
Reserved
CL
Reserved
R/W-0
R/W-1
R-0
R/W-5h
R-0
7
6
4
9
3
2
8
0
Reserved
IBANK
Reserved
PAGESIZE
R-0
R/W-2h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-24. SDRAM Configuration Register (SDCR) Field Descriptions
Bit
31-28
Field
Reserved
27
DDR2TERM1
26
IBANK_POS
25
Value
0
0-3h
Description
Reserved
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM0 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDR2TERM0
bit. Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00
to disable the termination because the ODT feature is not supported.
Internal Bank position.
0
Normal addressing
1
Special addressing. Typically used with mobile DDR partial array self-refresh.
MSDRAMEN
Mobile SDRAM enable. Use this bit in conjunction with DDR2EN, DDREN, and SDRAMEN to
enable/disable mobile SDRAM. To change this bit value, use the following sequence:
1.
2.
24
DDRDRIVE1
23
BOOTUNLOCK
0
Disable mobile SDRAM
1
Enable mobile SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE0 bit to make a 2-bit field.
This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDRDRIVE0 bit.
Boot Unlock. Controls the write permission settings for the DDR2TERM[1:0], MSDRAMEN,
DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and SDRAMEN bit fields. To
change these bits, use the following sequence:
1.
2.
366
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the MSDRAMEN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0],
MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and
SDRAMEN bits.
0
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may not be changed.
1
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may be changed.
DDR2/mDDR Memory Controller
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Table 13-24. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
22
DDR2DDQS
Value
Description
DDR2 SDRAM differential DQS enable. This bit is writeable only when the BOOTUNLOCK bit is
unlocked. To change this bit value, use the following sequence:
1.
2.
21
DDR2TERM0
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2DDQS bit.
0
Single-ended DQS
1
Reserved
0-3h
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM1 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0] bits.
Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00 to
disable the termination because the ODT feature is not supported.
0
1h-3h
20
DDR2EN
Disable termination
Reserved
DDR2 enable. This bit is used in conjunction with the DDREN and SDRAMEN bits to enable/disable
DDR2. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
1.
2.
19
0
Disable DDR2
1
Enable DDR2
DDRDLL_DIS
DLL disable for DDR SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked.
To change this bit value, use the following sequence:
1.
2.
18
DDRDRIVE0
Enable DLL
1
Disable DLL inside DDR SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE1 bit to make a 2-bit field.
The DDRDRIVE[1:0] bits configure the output driver impedance control value of the SDRAM
memory. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDRIVE[1:0] bits.
0
For DDR2, normal drive strength. For mobile DDR, full drive strength.
1h
For DDR2, weak drive strength. For mobile DDR, 1/2 drive strength.
2h
For DDR2, reserved. For mobile DDR, 1/4 drive strength.
3h
For DDR2, reserved. For mobile DDR, 1/8 drive strength.
DDREN
DDR enable. This bit is used in conjunction with the DDR2EN and SDRAMEN bits to enable/disable
DDR. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
1.
2.
16
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDLL_DIS bit.
0
1.
2.
17
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2EN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDREN bit.
0
Disable DDR
1
Enable DDR
SDRAMEN
SDRAM enable. This bit is used in conjunction with the DDR2EN and DDREN bits to enable/disable
SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the SDRAMEN bit.
0
Disable SDRAM
1
Enable SDRAM
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Table 13-24. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
15
TIMUNLOCK
Value
Description
Timing unlock. Controls the write permission settings for the CL bit field, and the SDRAM timing
register 1 (SDTIMR1) and the SDRAM timing register 2 (SDTIMR2) bit fields. To change these bits,
use the following sequence:
1.
2.
14
0
CL bit, and SDTIMR1 and SDTIMR2 bit fields may not be changed.
1
CL bit, and SDTIMR1 and SDTIMR2 bit fields may be changed.
NM
13-12
Reserved
11-9
CL
SDRAM data bus width.
0
Reserved
1
16-bit bus width.
0
Reserved
0-7h
SDRAM CAS latency. This bit is writeable only when the TIMUNLOCK bit is unlocked. To change
this bit value, use the following sequence: