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Texas Instruments TMS320C6742 DSP (Rev. C) User guides
TMS320C6742 DSP
Technical Reference Manual
Literature Number: SPRUH81C
April 2013 – Revised September 2016
Contents
Preface....................................................................................................................................... 50
1
Overview ........................................................................................................................... 51
1.1
1.2
2
DSP Subsystem ................................................................................................................. 53
2.1
2.2
2.3
2.4
3
Introduction .................................................................................................................. 61
System Interconnect Block Diagram ..................................................................................... 62
Introduction .................................................................................................................. 64
DSP Memories.............................................................................................................. 64
Peripherals .................................................................................................................. 64
Memory Protection Unit (MPU) ............................................................................................. 65
5.1
5.2
5.3
2
54
55
55
55
59
59
59
59
System Memory ................................................................................................................. 63
4.1
4.2
4.3
5
Introduction ..................................................................................................................
TMS320C674x Megamodule .............................................................................................
2.2.1 Internal Memory Controllers .....................................................................................
2.2.2 Internal Peripherals ...............................................................................................
Memory Map ................................................................................................................
2.3.1 DSP Internal Memory .............................................................................................
2.3.2 External Memory ..................................................................................................
Advanced Event Triggering (AET) .......................................................................................
System Interconnect ........................................................................................................... 60
3.1
3.2
4
Introduction .................................................................................................................. 52
DSP Subsystem ............................................................................................................ 52
Introduction ..................................................................................................................
5.1.1 Purpose of the MPU ..............................................................................................
5.1.2 Features ............................................................................................................
5.1.3 Block Diagram .....................................................................................................
5.1.4 MPU Default Configuration.......................................................................................
Architecture .................................................................................................................
5.2.1 Privilege Levels ....................................................................................................
5.2.2 Memory Protection Ranges ......................................................................................
5.2.3 Permission Structures ............................................................................................
5.2.4 Protection Check ..................................................................................................
5.2.5 DSP L1/L2 Cache Controller Accesses ........................................................................
5.2.6 MPU Register Protection .........................................................................................
5.2.7 Invalid Accesses and Exceptions ...............................................................................
5.2.8 Reset Considerations .............................................................................................
5.2.9 Interrupt Support ..................................................................................................
5.2.10 Emulation Considerations .......................................................................................
MPU Registers..............................................................................................................
5.3.1 Revision Identification Register (REVID) .......................................................................
5.3.2 Configuration Register (CONFIG) ...............................................................................
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ..............................................................
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ...........................................................
5.3.5 Interrupt Enable Set Register (IENSET) .......................................................................
5.3.6 Interrupt Enable Clear Register (IENCLR) .....................................................................
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5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
6
77
77
78
79
80
81
82
83
84
Device Clocking ................................................................................................................. 85
6.1
6.2
6.3
7
Fixed Range Start Address Register (FXD_MPSAR) ........................................................
Fixed Range End Address Register (FXD_MPEAR) .........................................................
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .................................
Programmable Range n Start Address Registers (PROGn_MPSAR) ....................................
Programmable Range n End Address Registers (PROGn_MPEAR) .....................................
Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) ..............
Fault Address Register (FLTADDRR) .........................................................................
Fault Status Register (FLTSTAT) ..............................................................................
Fault Clear Register (FLTCLR) .................................................................................
Overview.....................................................................................................................
Frequency Flexibility .......................................................................................................
Peripheral Clocking ........................................................................................................
6.3.1 DDR2/mDDR Memory Controller Clocking ....................................................................
6.3.2 EMIFA Clocking ...................................................................................................
6.3.3 McASP Clocking ...................................................................................................
6.3.4 I/O Domains ........................................................................................................
86
88
89
89
91
92
93
Phase-Locked Loop Controller (PLLC) .................................................................................. 94
7.1
7.2
7.3
Introduction .................................................................................................................. 95
PLL Controllers ............................................................................................................. 95
7.2.1 Device Clock Generation ......................................................................................... 97
7.2.2 Steps for Programming the PLLs ............................................................................... 98
PLLC Registers ........................................................................................................... 100
7.3.1 PLLC0 Revision Identification Register (REVID) ............................................................ 101
7.3.2 PLLC1 Revision Identification Register (REVID) ............................................................ 102
7.3.3 Reset Type Status Register (RSTYPE) ....................................................................... 102
7.3.4 PLLC0 Reset Control Register (RSCTRL) ................................................................... 103
7.3.5 PLLC0 Control Register (PLLCTL) ............................................................................ 104
7.3.6 PLLC1 Control Register (PLLCTL) ............................................................................ 105
7.3.7 PLLC0 OBSCLK Select Register (OCSEL) .................................................................. 106
7.3.8 PLLC1 OBSCLK Select Register (OCSEL) .................................................................. 107
7.3.9 PLL Multiplier Control Register (PLLM) ....................................................................... 108
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV) ............................................................. 108
7.3.11 PLLC0 Divider 1 Register (PLLDIV1) ........................................................................ 109
7.3.12 PLLC1 Divider 1 Register (PLLDIV1) ........................................................................ 109
7.3.13 PLLC0 Divider 2 Register (PLLDIV2) ........................................................................ 110
7.3.14 PLLC1 Divider 2 Register (PLLDIV2) ........................................................................ 110
7.3.15 PLLC0 Divider 3 Register (PLLDIV3) ........................................................................ 111
7.3.16 PLLC1 Divider 3 Register (PLLDIV3) ........................................................................ 111
7.3.17 PLLC0 Divider 4 Register (PLLDIV4) ........................................................................ 112
7.3.18 PLLC0 Divider 5 Register (PLLDIV5) ........................................................................ 112
7.3.19 PLLC0 Divider 6 Register (PLLDIV6) ........................................................................ 113
7.3.20 PLLC0 Divider 7 Register (PLLDIV7) ........................................................................ 113
7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)............................................................. 114
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)............................................................. 114
7.3.23 PLL Post-Divider Control Register (POSTDIV) ............................................................. 115
7.3.24 PLL Controller Command Register (PLLCMD) ............................................................. 115
7.3.25 PLL Controller Status Register (PLLSTAT) ................................................................. 116
7.3.26 PLLC0 Clock Align Control Register (ALNCTL) ............................................................ 117
7.3.27 PLLC1 Clock Align Control Register (ALNCTL) ............................................................ 118
7.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ............................................. 119
7.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ............................................. 120
7.3.30 PLLC0 Clock Enable Control Register (CKEN) ............................................................. 121
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7.3.31
7.3.32
7.3.33
7.3.34
7.3.35
7.3.36
7.3.37
8
8.3
8.4
8.5
8.6
Introduction ................................................................................................................
Power Domain and Module Topology ..................................................................................
8.2.1 Power Domain States ...........................................................................................
8.2.2 Module States ....................................................................................................
Executing State Transitions .............................................................................................
8.3.1 Power Domain State Transitions ..............................................................................
8.3.2 Module State Transitions .......................................................................................
IcePick Emulation Support in the PSC .................................................................................
PSC Interrupts.............................................................................................................
8.5.1 Interrupt Events ..................................................................................................
8.5.2 Interrupt Registers ...............................................................................................
8.5.3 Interrupt Handling ................................................................................................
PSC Registers.............................................................................................................
8.6.1 Revision Identification Register (REVID) .....................................................................
8.6.2 Interrupt Evaluation Register (INTEVAL) .....................................................................
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ...................................
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ...................................
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ......................................
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ......................................
8.6.7 Power Error Pending Register (PERRPR) ...................................................................
8.6.8 Power Error Clear Register (PERRCR) .......................................................................
8.6.9 Power Domain Transition Command Register (PTCMD)...................................................
8.6.10 Power Domain Transition Status Register (PTSTAT)......................................................
8.6.11 Power Domain 0 Status Register (PDSTAT0) ..............................................................
8.6.12 Power Domain 1 Status Register (PDSTAT1) ..............................................................
8.6.13 Power Domain 0 Control Register (PDCTL0) ...............................................................
8.6.14 Power Domain 1 Control Register (PDCTL1) ...............................................................
8.6.15 Power Domain 0 Configuration Register (PDCFG0) .......................................................
8.6.16 Power Domain 1 Configuration Register (PDCFG1) .......................................................
8.6.17 Module Status n Register (MDSTATn).......................................................................
8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................
8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................
128
128
130
130
132
132
132
133
133
133
134
135
136
137
137
138
138
139
139
140
140
141
142
143
144
145
146
147
148
149
150
151
Power Management........................................................................................................... 152
9.1
9.2
9.3
9.4
9.5
9.6
9.7
4
121
122
123
124
125
126
126
Power and Sleep Controller (PSC) ...................................................................................... 127
8.1
8.2
9
PLLC1 Clock Enable Control Register (CKEN) .............................................................
PLLC0 Clock Status Register (CKSTAT) ....................................................................
PLLC1 Clock Status Register (CKSTAT) ....................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ................................................................
Emulation Performance Counter 0 Register (EMUCNT0) .................................................
Emulation Performance Counter 1 Register (EMUCNT1) .................................................
Introduction ................................................................................................................
Power Consumption Overview ..........................................................................................
PSC and PLLC Overview ................................................................................................
Features ....................................................................................................................
Clock Management .......................................................................................................
9.5.1 Module Clock ON/OFF ..........................................................................................
9.5.2 Module Clock Frequency Scaling ..............................................................................
9.5.3 PLL Bypass and Power Down .................................................................................
DSP Sleep Mode Management .........................................................................................
9.6.1 C674x DSP CPU Sleep Mode .................................................................................
9.6.2 C674x Megamodule Sleep Mode ..............................................................................
RTC-Only Mode ...........................................................................................................
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9.8
9.9
9.10
10
10.3
10.4
10.5
Introduction ................................................................................................................
Protection ..................................................................................................................
10.2.1 Privilege Mode Protection .....................................................................................
10.2.2 Kicker Mechanism Protection .................................................................................
Master Priority Control ...................................................................................................
Interrupt Support ..........................................................................................................
10.4.1 Interrupt Events and Requests................................................................................
10.4.2 Interrupt Multiplexing ...........................................................................................
10.4.3 Host-DSP Communication Interrupts ........................................................................
SYSCFG Registers .......................................................................................................
10.5.1 Revision Identification Register (REVID) ....................................................................
10.5.2 Device Identification Register 0 (DEVIDR0).................................................................
10.5.3 Boot Configuration Register (BOOTCFG) ...................................................................
10.5.4 Chip Revision Identification Register (CHIPREVIDR) .....................................................
10.5.5 Kick Registers (KICK0R-KICK1R) ............................................................................
10.5.6 Host 1 Configuration Register (HOST1CFG) ...............................................................
10.5.7 Interrupt Registers ..............................................................................................
10.5.8 Fault Registers ..................................................................................................
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2) ............................................................
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) .............................................
10.5.11 Suspend Source Register (SUSPSRC) ....................................................................
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) ..............................................................
10.5.14 Chip Configuration 0 Register (CFGCHIP0) ...............................................................
10.5.15 Chip Configuration 1 Register (CFGCHIP1) ...............................................................
10.5.16 Chip Configuration 3 Register (CFGCHIP3) ...............................................................
10.5.17 Chip Configuration 4 Register (CFGCHIP4) ...............................................................
10.5.18 VTP I/O Control Register (VTPIO_CTL) ...................................................................
10.5.19 DDR Slew Register (DDR_SLEW) ..........................................................................
10.5.20 Deep Sleep Register (DEEPSLEEP) .......................................................................
10.5.21 Pullup/Pulldown Enable Register (PUPD_ENA) ..........................................................
10.5.22 Pullup/Pulldown Select Register (PUPD_SEL) ............................................................
10.5.23 RXACTIVE Control Register (RXACTIVE) .................................................................
164
164
164
165
165
166
166
167
167
167
168
169
169
169
171
172
173
176
178
181
221
223
224
225
226
228
229
229
231
232
233
233
235
Boot Considerations ......................................................................................................... 236
11.1
12
156
157
158
158
158
159
160
161
161
161
162
162
System Configuration (SYSCFG) Module ............................................................................. 163
10.1
10.2
11
Dynamic Voltage and Frequency Scaling (DVFS) ...................................................................
9.8.1 Frequency Scaling Considerations ............................................................................
9.8.2 Voltage Scaling Considerations ................................................................................
Deep Sleep Mode.........................................................................................................
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ..............................
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up .....................................
9.9.3 Deep Sleep Sequence ..........................................................................................
9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ........................................
Additional Peripheral Power Management Considerations..........................................................
9.10.1 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode ................................
9.10.2 LVCMOS I/O Buffer Receiver Disable .......................................................................
9.10.3 Pull-Up/Pull-Down Disable.....................................................................................
Introduction ................................................................................................................ 237
DDR2/mDDR Memory Controller ......................................................................................... 238
12.1
Introduction ................................................................................................................
12.1.1 Purpose of the Peripheral .....................................................................................
12.1.2 Features..........................................................................................................
12.1.3 Functional Block Diagram .....................................................................................
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12.2
12.3
12.4
13
240
240
241
241
242
243
251
252
257
260
260
261
261
262
263
263
266
266
267
268
269
274
275
276
279
280
281
282
283
284
284
285
287
288
289
289
290
291
292
Enhanced Capture (eCAP) Module ...................................................................................... 293
13.1
13.2
13.3
13.4
6
12.1.4 Supported Use Case Statement ..............................................................................
12.1.5 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
12.2.1 Clock Control ....................................................................................................
12.2.2 Signal Descriptions .............................................................................................
12.2.3 Protocol Description(s) .........................................................................................
12.2.4 Memory Width and Byte Alignment ..........................................................................
12.2.5 Address Mapping ...............................................................................................
12.2.6 DDR2/mDDR Memory Controller Interface ..................................................................
12.2.7 Refresh Scheduling .............................................................................................
12.2.8 Self-Refresh Mode ..............................................................................................
12.2.9 Partial Array Self Refresh for Mobile DDR ..................................................................
12.2.10 Power-Down Mode ............................................................................................
12.2.11 Reset Considerations .........................................................................................
12.2.12 VTP IO Buffer Calibration ....................................................................................
12.2.13 Auto-Initialization Sequence .................................................................................
12.2.14 Interrupt Support ..............................................................................................
12.2.15 DMA Event Support ...........................................................................................
12.2.16 Power Management ..........................................................................................
12.2.17 Emulation Considerations ....................................................................................
Supported Use Cases ....................................................................................................
Registers ...................................................................................................................
12.4.1 SDRAM Status Register (SDRSTAT) ........................................................................
12.4.2 SDRAM Configuration Register (SDCR) ....................................................................
12.4.3 SDRAM Refresh Control Register (SDRCR) ................................................................
12.4.4 SDRAM Timing Register 1 (SDTIMR1) ......................................................................
12.4.5 SDRAM Timing Register 2 (SDTIMR2) ......................................................................
12.4.6 SDRAM Configuration Register 2 (SDCR2) .................................................................
12.4.7 Peripheral Bus Burst Priority Register (PBBPR)............................................................
12.4.8 Performance Counter 1 Register (PC1) .....................................................................
12.4.9 Performance Counter 2 Register (PC2) .....................................................................
12.4.10 Performance Counter Configuration Register (PCC) .....................................................
12.4.11 Performance Counter Master Region Select Register (PCMRS) .......................................
12.4.12 DDR PHY Reset Control Register (DRPYRCR) ..........................................................
12.4.13 Interrupt Raw Register (IRR) ................................................................................
12.4.14 Interrupt Masked Register (IMR) ............................................................................
12.4.15 Interrupt Mask Set Register (IMSR) ........................................................................
12.4.16 Interrupt Mask Clear Register (IMCR) ......................................................................
12.4.17 DDR PHY Control Register (DRPYC1R) ...................................................................
Introduction ................................................................................................................
13.1.1 Purpose of the Peripheral .....................................................................................
13.1.2 Features..........................................................................................................
Architecture ................................................................................................................
13.2.1 Capture and APWM Operating Mode ........................................................................
13.2.2 Capture Mode Description .....................................................................................
Applications ...............................................................................................................
13.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example .........................................
13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ...........................
13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example .......................................
13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example .........................
13.3.5 Application of the APWM Mode ..............................................................................
Registers ...................................................................................................................
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294
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296
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304
305
307
309
311
313
320
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13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
13.4.8
13.4.9
13.4.10
13.4.11
13.4.12
13.4.13
14
320
321
321
322
322
323
323
325
326
328
329
330
331
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 332
14.1
14.2
14.3
14.4
15
Time-Stamp Counter Register (TSCTR) .....................................................................
Counter Phase Control Register (CTRPHS) ................................................................
Capture 1 Register (CAP1) ....................................................................................
Capture 2 Register (CAP2) ....................................................................................
Capture 3 Register (CAP3) ....................................................................................
Capture 4 Register (CAP4) ....................................................................................
ECAP Control Register 1 (ECCTL1) .........................................................................
ECAP Control Register 2 (ECCTL2) .........................................................................
ECAP Interrupt Enable Register (ECEINT) .................................................................
ECAP Interrupt Flag Register (ECFLG) ....................................................................
ECAP Interrupt Clear Register (ECCLR) ...................................................................
ECAP Interrupt Forcing Register (ECFRC) ................................................................
Revision ID Register (REVID) ...............................................................................
Introduction ................................................................................................................
14.1.1 Introduction ......................................................................................................
14.1.2 Submodule Overview ..........................................................................................
14.1.3 Register Mapping ...............................................................................................
Architecture ................................................................................................................
14.2.1 Overview .........................................................................................................
14.2.2 Proper Interrupt Initialization Procedure .....................................................................
14.2.3 Time-Base (TB) Submodule ...................................................................................
14.2.4 Counter-Compare (CC) Submodule ..........................................................................
14.2.5 Action-Qualifier (AQ) Submodule .............................................................................
14.2.6 Dead-Band Generator (DB) Submodule .....................................................................
14.2.7 PWM-Chopper (PC) Submodule..............................................................................
14.2.8 Trip-Zone (TZ) Submodule ....................................................................................
14.2.9 Event-Trigger (ET) Submodule ...............................................................................
14.2.10 High-Resolution PWM (HRPWM) Submodule.............................................................
Applications to Power Topologies ......................................................................................
14.3.1 Overview of Multiple Modules ................................................................................
14.3.2 Key Configuration Capabilities ................................................................................
14.3.3 Controlling Multiple Buck Converters With Independent Frequencies ...................................
14.3.4 Controlling Multiple Buck Converters With Same Frequencies ...........................................
14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ......................................................
14.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................
14.3.7 Practical Applications Using Phase Control Between PWM Modules ...................................
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ......................................................
14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter......................................
Registers ...................................................................................................................
14.4.1 Time-Base Submodule Registers ............................................................................
14.4.2 Counter-Compare Submodule Registers ....................................................................
14.4.3 Action-Qualifier Submodule Registers .......................................................................
14.4.4 Dead-Band Generator Submodule Registers ...............................................................
14.4.5 PWM-Chopper Submodule Register .........................................................................
14.4.6 Trip-Zone Submodule Registers ..............................................................................
14.4.7 Event-Trigger Submodule Registers .........................................................................
14.4.8 High-Resolution PWM Submodule Registers ...............................................................
333
333
333
337
338
338
341
342
351
356
374
378
382
386
390
397
397
398
399
402
405
408
412
413
418
421
421
425
428
432
435
436
440
443
Enhanced Direct Memory Access (EDMA3) Controller ........................................................... 446
15.1
Introduction ................................................................................................................
15.1.1 Overview .........................................................................................................
15.1.2 Features..........................................................................................................
15.1.3 Functional Block Diagram .....................................................................................
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15.2
15.3
15.4
15.5
15.6
16
450
452
452
455
458
468
471
472
475
477
478
485
487
490
491
493
494
494
494
495
495
495
497
498
500
512
512
519
558
579
579
580
581
External Memory Interface A (EMIFA) .................................................................................. 582
16.1
16.2
8
15.1.4 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
15.2.1 Functional Overview ............................................................................................
15.2.2 Types of EDMA3 Transfers ...................................................................................
15.2.3 Parameter RAM (PaRAM) .....................................................................................
15.2.4 Initiating a DMA Transfer ......................................................................................
15.2.5 Completion of a DMA Transfer................................................................................
15.2.6 Event, Channel, and PaRAM Mapping ......................................................................
15.2.7 EDMA3 Channel Controller Regions .........................................................................
15.2.8 Chaining EDMA3 Channels ...................................................................................
15.2.9 EDMA3 Interrupts ...............................................................................................
15.2.10 Event Queue(s) ................................................................................................
15.2.11 EDMA3 Transfer Controller (EDMA3TC)...................................................................
15.2.12 Event Dataflow ................................................................................................
15.2.13 EDMA3 Prioritization ..........................................................................................
15.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................
15.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................
15.2.16 Reset Considerations .........................................................................................
15.2.17 Power Management ..........................................................................................
15.2.18 Emulation Considerations ....................................................................................
Transfer Examples........................................................................................................
15.3.1 Block Move Example ...........................................................................................
15.3.2 Subframe Extraction Example ................................................................................
15.3.3 Data Sorting Example ..........................................................................................
15.3.4 Peripheral Servicing Example .................................................................................
Registers ...................................................................................................................
15.4.1 Parameter RAM (PaRAM) Entries ............................................................................
15.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................
15.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ........................................................
Tips .........................................................................................................................
15.5.1 Debug Checklist ................................................................................................
15.5.2 Miscellaneous Programming/Debug Tips ...................................................................
Setting Up a Transfer ....................................................................................................
Introduction ................................................................................................................
16.1.1 Purpose of the Peripheral .....................................................................................
16.1.2 Features..........................................................................................................
16.1.3 Functional Block Diagram .....................................................................................
Architecture ................................................................................................................
16.2.1 Clock Control ....................................................................................................
16.2.2 EMIFA Requests ................................................................................................
16.2.3 Pin Descriptions .................................................................................................
16.2.4 SDRAM Controller and Interface .............................................................................
16.2.5 Asynchronous Controller and Interface ......................................................................
16.2.6 Data Bus Parking ...............................................................................................
16.2.7 Reset and Initialization Considerations ......................................................................
16.2.8 Interrupt Support ................................................................................................
16.2.9 EDMA Event Support ..........................................................................................
16.2.10 Pin Multiplexing ................................................................................................
16.2.11 Memory Map ...................................................................................................
16.2.12 Priority and Arbitration ........................................................................................
16.2.13 System Considerations .......................................................................................
16.2.14 Power Management ..........................................................................................
Contents
583
583
583
583
583
584
584
584
586
598
617
617
618
619
619
619
620
621
622
SPRUH81C – April 2013 – Revised September 2016
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16.3
16.4
17
16.2.15 Emulation Considerations ....................................................................................
Example Configuration ...................................................................................................
16.3.1 Hardware Interface .............................................................................................
16.3.2 Software Configuration .........................................................................................
Registers ...................................................................................................................
16.4.1 Module ID Register (MIDR) ...................................................................................
16.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) ...............................................
16.4.3 SDRAM Configuration Register (SDCR) ....................................................................
16.4.4 SDRAM Refresh Control Register (SDRCR) ................................................................
16.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
16.4.6 SDRAM Timing Register (SDTIMR) ..........................................................................
16.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ..................................................
16.4.8 EMIFA Interrupt Raw Register (INTRAW) ...................................................................
16.4.9 EMIFA Interrupt Masked Register (INTMSK) ...............................................................
16.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET).......................................................
16.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ....................................................
16.4.12 NAND Flash Control Register (NANDFCR) ...............................................................
16.4.13 NAND Flash Status Register (NANDFSR) .................................................................
16.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ..........................................
16.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) .......................................
16.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..................................................
16.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..................................................
16.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..................................................
16.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..................................................
16.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) .................................
16.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) .................................
16.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1).....................................
16.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2).....................................
623
624
624
624
646
647
647
649
651
652
654
655
656
657
658
659
660
662
663
664
665
665
666
666
667
667
668
668
General-Purpose Input/Output (GPIO) ................................................................................. 669
17.1
17.2
17.3
Introduction ................................................................................................................
17.1.1 Purpose of the Peripheral .....................................................................................
17.1.2 Features..........................................................................................................
17.1.3 Functional Block Diagram .....................................................................................
17.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
17.2.1 Clock Control ....................................................................................................
17.2.2 Signal Descriptions .............................................................................................
17.2.3 Pin Multiplexing .................................................................................................
17.2.4 Endianness Considerations ...................................................................................
17.2.5 GPIO Register Structure .......................................................................................
17.2.6 Using a GPIO Signal as an Output ...........................................................................
17.2.7 Using a GPIO Signal as an Input .............................................................................
17.2.8 Reset Considerations ..........................................................................................
17.2.9 Initialization ......................................................................................................
17.2.10 Interrupt Support ..............................................................................................
17.2.11 EDMA Event Support .........................................................................................
17.2.12 Power Management ..........................................................................................
17.2.13 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
17.3.1 Revision ID Register (REVID) .................................................................................
17.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ......................................................
17.3.3 GPIO Direction Registers (DIRn) .............................................................................
17.3.4 GPIO Output Data Registers (OUT_DATAn) ...............................................................
SPRUH81C – April 2013 – Revised September 2016
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Contents
670
670
670
670
670
671
671
671
671
671
672
675
676
676
677
677
678
678
678
679
680
681
682
684
9
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17.3.5
17.3.6
17.3.7
17.3.8
17.3.9
17.3.10
17.3.11
17.3.12
18
18.2
18.3
Introduction ................................................................................................................
18.1.1 Purpose of the Peripheral .....................................................................................
18.1.2 Features..........................................................................................................
18.1.3 Functional Block Diagram .....................................................................................
18.1.4 Industry Standard(s) Compliance Statement................................................................
18.1.5 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
18.2.1 Clock Control ....................................................................................................
18.2.2 Memory Map ....................................................................................................
18.2.3 Signal Descriptions .............................................................................................
18.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks ................................................
18.2.5 Protocol Description ............................................................................................
18.2.6 Operation ........................................................................................................
18.2.7 Reset Considerations ..........................................................................................
18.2.8 Initialization ......................................................................................................
18.2.9 Interrupt Support ................................................................................................
18.2.10 EDMA Event Support .........................................................................................
18.2.11 Power Management ..........................................................................................
18.2.12 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
18.3.1 Revision Identification Register (REVID) ....................................................................
18.3.2 Power and Emulation Management Register (PWREMU_MGMT) ......................................
18.3.3 GPIO Enable Register (GPIO_EN) ..........................................................................
18.3.4 GPIO Direction 1 Register (GPIO_DIR1) ....................................................................
18.3.5 GPIO Data 1 Register (GPIO_DAT1) ........................................................................
18.3.6 GPIO Direction 2 Register (GPIO_DIR2) ....................................................................
18.3.7 GPIO Data 2 Register (GPIO_DAT2) ........................................................................
18.3.8 Host Port Interface Control Register (HPIC) ................................................................
18.3.9 Host Port Interface Write Address Register (HPIAW) .....................................................
18.3.10 Host Port Interface Read Address Register (HPIAR) ....................................................
Inter-Integrated Circuit (I2C) Module
19.1
19.2
10
686
688
690
692
694
696
698
700
Host Port Interface (HPI) .................................................................................................... 702
18.1
19
GPIO Set Data Registers (SET_DATAn) ....................................................................
GPIO Clear Data Registers (CLR_DATAn) .................................................................
GPIO Input Data Registers (IN_DATAn) ....................................................................
GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) ...........................................
GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ........................................
GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................
GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) .....................................
GPIO Interrupt Status Registers (INTSTATn) .............................................................
................................................................................... 735
Introduction ................................................................................................................
19.1.1 Purpose of the Peripheral .....................................................................................
19.1.2 Features..........................................................................................................
19.1.3 Functional Block Diagram .....................................................................................
19.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
19.2.1 Bus Structure ....................................................................................................
19.2.2 Clock Generation ...............................................................................................
19.2.3 Clock Synchronization .........................................................................................
19.2.4 Signal Descriptions .............................................................................................
19.2.5 START and STOP Conditions ................................................................................
19.2.6 Serial Data Formats ............................................................................................
19.2.7 Operating Modes ...............................................................................................
Contents
703
703
703
704
705
705
706
706
706
706
707
708
708
723
723
724
725
725
726
726
727
727
728
729
729
730
731
732
734
734
736
736
736
737
737
738
738
739
740
740
741
742
744
SPRUH81C – April 2013 – Revised September 2016
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19.3
20
19.2.8 NACK Bit Generation...........................................................................................
19.2.9 Arbitration ........................................................................................................
19.2.10 Reset Considerations .........................................................................................
19.2.11 Initialization .....................................................................................................
19.2.12 Interrupt Support ..............................................................................................
19.2.13 DMA Events Generated by the I2C Peripheral ............................................................
19.2.14 Power Management ..........................................................................................
19.2.15 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
19.3.1 I2C Own Address Register (ICOAR) .........................................................................
19.3.2 I2C Interrupt Mask Register (ICIMR) .........................................................................
19.3.3 I2C Interrupt Status Register (ICSTR) ......................................................................
19.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) .......................................................
19.3.5 I2C Data Count Register (ICCNT) ............................................................................
19.3.6 I2C Data Receive Register (ICDRR) .........................................................................
19.3.7 I2C Slave Address Register (ICSAR) ........................................................................
19.3.8 I2C Data Transmit Register (ICDXR) ........................................................................
19.3.9 I2C Mode Register (ICMDR) ..................................................................................
19.3.10 I2C Interrupt Vector Register (ICIVR) ......................................................................
19.3.11 I2C Extended Mode Register (ICEMDR) ...................................................................
19.3.12 I2C Prescaler Register (ICPSC).............................................................................
19.3.13 I2C Revision Identification Register (REVID1) ............................................................
19.3.14 I2C Revision Identification Register (REVID2) ...........................................................
19.3.15 I2C DMA Control Register (ICDMAC) ......................................................................
19.3.16 I2C Pin Function Register (ICPFUNC) ....................................................................
19.3.17 I2C Pin Direction Register (ICPDIR) .......................................................................
19.3.18 I2C Pin Data In Register (ICPDIN) .........................................................................
19.3.19 I2C Pin Data Out Register (ICPDOUT) ....................................................................
19.3.20 I2C Pin Data Set Register (ICPDSET) ....................................................................
19.3.21 I2C Pin Data Clear Register (ICPDCLR) ..................................................................
745
746
747
747
748
749
749
749
750
751
752
753
756
757
758
759
760
761
765
766
767
768
768
769
770
771
772
773
774
775
Multichannel Audio Serial Port (McASP) .............................................................................. 776
20.1
20.0.22 Features .......................................................................................................
20.0.23 Protocols Supported .........................................................................................
20.0.24 Functional Block Diagram ....................................................................................
20.0.25 Definition of Terms ...........................................................................................
20.0.26 Overview .......................................................................................................
20.0.27 Clock and Frame Sync Generators ........................................................................
20.0.28 Reset Considerations .........................................................................................
20.0.29 EDMA Event Support .........................................................................................
20.0.30 Power Management ..........................................................................................
Registers ...................................................................................................................
20.1.1 Register Bit Restrictions .......................................................................................
20.1.2 Revision Identification Register (REV) .......................................................................
20.1.3 Pin Function Register (PFUNC) ..............................................................................
20.1.4 Pin Direction Register (PDIR) ................................................................................
20.1.5 Pin Data Output Register (PDOUT) ..........................................................................
20.1.6 Pin Data Input Register (PDIN) ...............................................................................
20.1.7 Pin Data Set Register (PDSET) ..............................................................................
20.1.8 Pin Data Clear Register (PDCLR) ............................................................................
20.1.9 Global Control Register (GBLCTL) ...........................................................................
20.1.10 Audio Mute Control Register (AMUTE).....................................................................
20.1.11 Digital Loopback Control Register (DLBCTL) .............................................................
20.1.12 Digital Mode Control Register (DITCTL) ...................................................................
SPRUH81C – April 2013 – Revised September 2016
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Contents
777
778
779
787
790
790
831
831
831
832
835
836
837
839
841
843
845
847
849
851
853
854
11
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20.1.13
20.1.14
20.1.15
20.1.16
20.1.17
20.1.18
20.1.19
20.1.20
20.1.21
20.1.22
20.1.23
20.1.24
20.1.25
20.1.26
20.1.27
20.1.28
20.1.29
20.1.30
20.1.31
20.1.32
20.1.33
20.1.34
20.1.35
20.1.36
20.1.37
20.1.38
20.1.39
20.1.40
20.1.41
20.1.42
20.1.43
20.1.44
20.1.45
20.1.46
20.1.47
20.1.48
21
855
856
857
859
860
861
862
863
864
865
866
867
868
869
870
872
873
874
875
876
877
878
879
880
881
882
882
883
883
884
884
885
886
887
888
889
Multichannel Buffered Serial Port (McBSP) .......................................................................... 890
21.1
21.2
12
Receiver Global Control Register (RGBLCTL) ............................................................
Receive Format Unit Bit Mask Register (RMASK) ........................................................
Receive Bit Stream Format Register (RFMT) .............................................................
Receive Frame Sync Control Register (AFSRCTL) ......................................................
Receive Clock Control Register (ACLKRCTL) ............................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ......................................
Receive TDM Time Slot Register (RTDM) .................................................................
Receiver Interrupt Control Register (RINTCTL) ...........................................................
Receiver Status Register (RSTAT) .........................................................................
Current Receive TDM Time Slot Registers (RSLOT) ....................................................
Receive Clock Check Control Register (RCLKCHK) .....................................................
Receiver DMA Event Control Register (REVTCTL) ......................................................
Transmitter Global Control Register (XGBLCTL) .........................................................
Transmit Format Unit Bit Mask Register (XMASK) .......................................................
Transmit Bit Stream Format Register (XFMT).............................................................
Transmit Frame Sync Control Register (AFSXCTL) ......................................................
Transmit Clock Control Register (ACLKXCTL) ............................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ......................................
Transmit TDM Time Slot Register (XTDM) ................................................................
Transmitter Interrupt Control Register (XINTCTL) ........................................................
Transmitter Status Register (XSTAT) ......................................................................
Current Transmit TDM Time Slot Register (XSLOT) .....................................................
Transmit Clock Check Control Register (XCLKCHK) ....................................................
Transmitter DMA Event Control Register (XEVTCTL) ...................................................
Serializer Control Registers (SRCTLn) .....................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ...........................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)..........................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ......................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) .....................................
Transmit Buffer Registers (XBUFn) .........................................................................
Receive Buffer Registers (RBUFn) .........................................................................
AFIFO Revision Identification Register (AFIFOREV) .....................................................
Write FIFO Control Register (WFIFOCTL) .................................................................
Write FIFO Status Register (WFIFOSTS)..................................................................
Read FIFO Control Register (RFIFOCTL) .................................................................
Read FIFO Status Register (RFIFOSTS) ..................................................................
Introduction ................................................................................................................
21.1.1 Purpose of the Peripheral .....................................................................................
21.1.2 Features..........................................................................................................
21.1.3 Functional Block Diagram .....................................................................................
21.1.4 Industry Standard Compliance Statement ...................................................................
Architecture ...............................................................................................................
21.2.1 Clock Control ....................................................................................................
21.2.2 Signal Descriptions .............................................................................................
21.2.3 Pin Multiplexing .................................................................................................
21.2.4 Endianness Considerations ...................................................................................
21.2.5 Clock, Frames, and Data ......................................................................................
21.2.6 McBSP Buffer FIFO (BFIFO) ..................................................................................
21.2.7 McBSP Standard Operation ...................................................................................
21.2.8 μ-Law/A-Law Companding Hardware Operation ...........................................................
21.2.9 Multichannel Selection Modes ................................................................................
21.2.10 SPI Operation Using the Clock Stop Mode ................................................................
Contents
891
891
891
892
892
893
893
893
893
893
894
908
908
922
924
932
SPRUH81C – April 2013 – Revised September 2016
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21.3
22
21.2.11 Resetting the Serial Port: RRST, XRST, GRST, and RESET ...........................................
21.2.12 McBSP Initialization Procedure..............................................................................
21.2.13 Interrupt Support ..............................................................................................
21.2.14 EDMA Event Support .........................................................................................
21.2.15 Power Management ..........................................................................................
21.2.16 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
21.3.1 Data Receive Register (DRR) .................................................................................
21.3.2 Data Transmit Register (DXR) ................................................................................
21.3.3 Serial Port Control Register (SPCR) .........................................................................
21.3.4 Receive Control Register (RCR) ..............................................................................
21.3.5 Transmit Control Register (XCR) .............................................................................
21.3.6 Sample Rate Generator Register (SRGR) ..................................................................
21.3.7 Multichannel Control Register (MCR) ........................................................................
21.3.8 Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) ....................................
21.3.9 Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) ...................................
21.3.10 Pin Control Register (PCR) ..................................................................................
21.3.11 BFIFO Revision Identification Register (BFIFOREV) .....................................................
21.3.12 Write FIFO Control Register (WFIFOCTL) .................................................................
21.3.13 Write FIFO Status Register (WFIFOSTS)..................................................................
21.3.14 Read FIFO Control Register (RFIFOCTL) .................................................................
21.3.15 Read FIFO Status Register (RFIFOSTS) ..................................................................
932
933
937
938
939
939
940
941
941
942
944
946
948
949
953
955
957
959
960
961
962
963
Real-Time Clock (RTC) ...................................................................................................... 964
22.1
22.2
22.3
Introduction ................................................................................................................
22.1.1 Purpose of the Peripheral .....................................................................................
22.1.2 Features..........................................................................................................
22.1.3 Block Diagram ...................................................................................................
Architecture ................................................................................................................
22.2.1 Clock Source ....................................................................................................
22.2.2 Signal Descriptions .............................................................................................
22.2.3 Isolated Power Supply .........................................................................................
22.2.4 Operation ........................................................................................................
22.2.5 Interrupt Requests ..............................................................................................
22.2.6 Register Protection Against Spurious Writes ...............................................................
22.2.7 General-Purpose Scratch Registers .........................................................................
22.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) ................................
22.2.9 Emulation Modes of the Real-Time Clock ...................................................................
22.2.10 Reset Considerations .........................................................................................
Registers ...................................................................................................................
22.3.1 Second Register (SECOND) ..................................................................................
22.3.2 Minute Register (MINUTE) ....................................................................................
22.3.3 Hour Register (HOUR) .........................................................................................
22.3.4 Day of the Month Register (DAY) ............................................................................
22.3.5 Month Register (MONTH) .....................................................................................
22.3.6 Year Register (YEAR) ..........................................................................................
22.3.7 Day of the Week Register (DOTW) ..........................................................................
22.3.8 Alarm Second Register (ALARMSECOND) .................................................................
22.3.9 Alarm Minute Register (ALARMMINUTE) ...................................................................
22.3.10 Alarm Hour Register (ALARMHOUR) ......................................................................
22.3.11 Alarm Day of the Month Register (ALARMDAY) ..........................................................
22.3.12 Alarm Month Register (ALARMMONTH) ...................................................................
22.3.13 Alarm Year Register (ALARMYEAR) .......................................................................
22.3.14 Control Register (CTRL) .....................................................................................
SPRUH81C – April 2013 – Revised September 2016
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Contents
965
965
965
965
966
966
966
966
967
969
970
971
971
971
971
972
973
973
974
975
975
976
976
977
977
978
979
980
980
981
13
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22.3.15
22.3.16
22.3.17
22.3.18
22.3.19
22.3.20
22.3.21
23
982
983
984
985
986
987
987
Serial Peripheral Interface (SPI) .......................................................................................... 988
23.1
23.2
23.3
14
Status Register (STATUS) ...................................................................................
Interrupt Register (INTERRUPT) ............................................................................
Compensation (LSB) Register (COMPLSB) ...............................................................
Compensation (MSB) Register (COMPMSB) .............................................................
Oscillator Register (OSC) ....................................................................................
Scratch Registers (SCRATCH0-SCRATCH2) .............................................................
Kick Registers (KICK0R, KICK1R) ..........................................................................
Introduction ................................................................................................................ 989
23.1.1 Purpose of the Peripheral ..................................................................................... 989
23.1.2 Features.......................................................................................................... 989
23.1.3 Functional Block Diagram ..................................................................................... 990
23.1.4 Industry Standard(s) Compliance Statement................................................................ 990
Architecture ................................................................................................................ 991
23.2.1 Clock ............................................................................................................. 991
23.2.2 Signal Descriptions ............................................................................................. 991
23.2.3 Operation Modes ............................................................................................... 991
23.2.4 Programmable Registers ...................................................................................... 992
23.2.5 Master Mode Settings .......................................................................................... 993
23.2.6 Slave Mode Settings ........................................................................................... 995
23.2.7 SPI Operation: 3-Pin Mode .................................................................................... 996
23.2.8 SPI Operation: 4-Pin with Chip Select Mode ............................................................... 997
23.2.9 SPI Operation: 4-Pin with Enable Mode ..................................................................... 999
23.2.10 SPI Operation: 5-Pin Mode ................................................................................. 1001
23.2.11 Data Formats ................................................................................................. 1003
23.2.12 Interrupt Support ............................................................................................. 1006
23.2.13 DMA Events Support ........................................................................................ 1007
23.2.14 Robustness Features ....................................................................................... 1007
23.2.15 Reset Considerations ....................................................................................... 1009
23.2.16 Power Management ......................................................................................... 1009
23.2.17 General-Purpose I/O Pin.................................................................................... 1010
23.2.18 Emulation Considerations .................................................................................. 1010
23.2.19 Initialization ................................................................................................... 1010
23.2.20 Timing Diagrams ............................................................................................. 1011
Registers ................................................................................................................. 1017
23.3.1 SPI Global Control Register 0 (SPIGCR0) ................................................................. 1017
23.3.2 SPI Global Control Register 1 (SPIGCR1) ................................................................. 1018
23.3.3 SPI Interrupt Register (SPIINT0) ............................................................................ 1020
23.3.4 SPI Interrupt Level Register (SPILVL) ...................................................................... 1022
23.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1023
23.3.6 SPI Pin Control Register 0 (SPIPC0) ...................................................................... 1025
23.3.7 SPI Pin Control Register 1 (SPIPC1) ....................................................................... 1026
23.3.8 SPI Pin Control Register 2 (SPIPC2) ....................................................................... 1027
23.3.9 SPI Pin Control Register 3 (SPIPC3) ....................................................................... 1028
23.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1029
23.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1030
23.3.12 SPI Transmit Data Register 0 (SPIDAT0) ................................................................ 1031
23.3.13 SPI Transmit Data Register 1 (SPIDAT1) ................................................................ 1032
23.3.14 SPI Receive Buffer Register (SPIBUF) ................................................................... 1033
23.3.15 SPI Emulation Register (SPIEMU) ........................................................................ 1035
23.3.16 SPI Delay Register (SPIDELAY) .......................................................................... 1036
23.3.17 SPI Default Chip Select Register (SPIDEF) .............................................................. 1039
23.3.18 SPI Data Format Registers (SPIFMTn) ................................................................... 1040
Contents
SPRUH81C – April 2013 – Revised September 2016
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23.3.19 SPI Interrupt Vector Register 1 (INTVEC1) .............................................................. 1042
24
64-Bit Timer Plus
24.1
24.2
25
............................................................................................................ 1043
Introduction ...............................................................................................................
24.1.1 Purpose of the Peripheral ....................................................................................
24.1.2 Features ........................................................................................................
24.1.3 Block Diagram .................................................................................................
24.1.4 Industry Standard Compatibility Statement ................................................................
24.1.5 Architecture – General-Purpose Timer Mode .............................................................
24.1.6 Architecture – Watchdog Timer Mode ......................................................................
24.1.7 Reset Considerations .........................................................................................
24.1.8 Interrupt Support ..............................................................................................
24.1.9 DMA Event Support ...........................................................................................
24.1.10 TM64P_OUT Event Support ...............................................................................
24.1.11 Interrupt/DMA Event Generation Control and Status ...................................................
24.1.12 Power Management .........................................................................................
24.1.13 Emulation Considerations ..................................................................................
Registers .................................................................................................................
24.2.1 Revision ID Register (REVID) ...............................................................................
24.2.2 Emulation Management Register (EMUMGT) .............................................................
24.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ............................................
24.2.4 GPIO Data and Direction Register (GPDATGPDIR) .....................................................
24.2.5 Timer Counter Registers (TIM12 and TIM34) .............................................................
24.2.6 Timer Period Registers (PRD12 and PRD34) .............................................................
24.2.7 Timer Control Register (TCR) ...............................................................................
24.2.8 Timer Global Control Register (TGCR).....................................................................
24.2.9 Watchdog Timer Control Register (WDTCR) ..............................................................
24.2.10 Timer Reload Register 12 (REL12) .......................................................................
24.2.11 Timer Reload Register 34 (REL34) .......................................................................
24.2.12 Timer Capture Register 12 (CAP12) ......................................................................
24.2.13 Timer Capture Register 34 (CAP34) ......................................................................
24.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) ..........................................
Universal Asynchronous Receiver/Transmitter (UART)
25.1
25.2
25.3
1044
1044
1044
1045
1045
1045
1057
1059
1059
1059
1060
1061
1061
1061
1062
1064
1064
1065
1066
1067
1068
1069
1071
1072
1073
1073
1074
1074
1075
....................................................... 1077
Introduction ...............................................................................................................
25.1.1 Purpose of the Peripheral ....................................................................................
25.1.2 Features ........................................................................................................
25.1.3 Functional Block Diagram ....................................................................................
25.1.4 Industry Standard(s) Compliance Statement ..............................................................
Peripheral Architecture .................................................................................................
25.2.1 Clock Generation and Control ...............................................................................
25.2.2 Signal Descriptions............................................................................................
25.2.3 Pin Multiplexing ................................................................................................
25.2.4 Protocol Description ..........................................................................................
25.2.5 Operation .......................................................................................................
25.2.6 Reset Considerations .........................................................................................
25.2.7 Initialization .....................................................................................................
25.2.8 Interrupt Support ..............................................................................................
25.2.9 DMA Event Support ...........................................................................................
25.2.10 Power Management .........................................................................................
25.2.11 Emulation Considerations ..................................................................................
25.2.12 Exception Processing .......................................................................................
Registers .................................................................................................................
25.3.1 Receiver Buffer Register (RBR) .............................................................................
25.3.2 Transmitter Holding Register (THR) ........................................................................
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Contents
1078
1078
1078
1078
1078
1080
1080
1082
1082
1082
1084
1088
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1090
1090
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1090
1091
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1093
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25.3.3
25.3.4
25.3.5
25.3.6
25.3.7
25.3.8
25.3.9
25.3.10
25.3.11
25.3.12
25.3.13
25.3.14
Interrupt Enable Register (IER) .............................................................................
Interrupt Identification Register (IIR) ........................................................................
FIFO Control Register (FCR) ................................................................................
Line Control Register (LCR) .................................................................................
Modem Control Register (MCR) .............................................................................
Line Status Register (LSR) ..................................................................................
Modem Status Register (MSR) ..............................................................................
Scratch Pad Register (SCR) ...............................................................................
Divisor Latches (DLL and DLH) ............................................................................
Revision Identification Registers (REVID1 and REVID2) ..............................................
Power and Emulation Management Register (PWREMU_MGMT) ...................................
Mode Definition Register (MDR) ...........................................................................
1094
1095
1096
1098
1100
1101
1104
1105
1105
1107
1108
1109
Revision History ...................................................................................................................... 1110
16
Contents
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List of Figures
1-1.
TMS320C6742 DSP Block Diagram ..................................................................................... 52
2-1.
TMS320C674x Megamodule Block Diagram ........................................................................... 54
3-1.
System Interconnect Block Diagram ..................................................................................... 62
5-1.
MPU Block Diagram
5-2.
Permission Fields
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
6-1.
6-2.
6-3.
6-4.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
....................................................................................................... 66
.......................................................................................................... 68
Revision ID Register (REVID) ............................................................................................ 72
Configuration Register (CONFIG) ........................................................................................ 73
Interrupt Raw Status/Set Register (IRAWSTAT) ....................................................................... 74
Interrupt Enable Status/Clear Register (IENSTAT) .................................................................... 75
Interrupt Enable Set Register (IENSET) ................................................................................ 76
Interrupt Enable Clear Register (IENCLR) .............................................................................. 76
Fixed Range Start Address Register (FXD_MPSAR) ................................................................. 77
Fixed Range End Address Register (FXD_MPEAR) .................................................................. 77
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .......................................... 78
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) ....................................... 79
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ........................................ 80
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) .......................... 81
Fault Address Register (FLTADDRR) ................................................................................... 82
Fault Status Register (FLTSTAT) ........................................................................................ 83
Fault Clear Register (FLTCLR) ........................................................................................... 84
Overall Clocking Diagram ................................................................................................. 87
DDR2/mDDR Memory Controller Clocking Diagram .................................................................. 90
EMIFA Clocking Diagram ................................................................................................. 91
McASP Clocking Diagram ................................................................................................. 92
PLLC Structure ............................................................................................................. 96
PLLC0 Revision Identification Register (REVID) ..................................................................... 101
PLLC1 Revision Identification Register (REVID) ..................................................................... 102
Reset Type Status Register (RSTYPE) ................................................................................ 102
Reset Control Register (RSCTRL) ..................................................................................... 103
PLLC0 Control Register (PLLCTL) ..................................................................................... 104
PLLC1 Control Register (PLLCTL) ..................................................................................... 105
PLLC0 OBSCLK Select Register (OCSEL) ........................................................................... 106
PLLC1 OBSCLK Select Register (OCSEL) ........................................................................... 107
PLL Multiplier Control Register (PLLM) ................................................................................ 108
PLLC0 Pre-Divider Control Register (PREDIV) ....................................................................... 108
PLLC0 Divider 1 Register (PLLDIV1) .................................................................................. 109
PLLC1 Divider 1 Register (PLLDIV1) .................................................................................. 109
PLLC0 Divider 2 Register (PLLDIV2) ................................................................................. 110
PLLC1 Divider 2 Register (PLLDIV2) ................................................................................. 110
PLLC0 Divider 3 Register (PLLDIV3) ................................................................................. 111
PLLC1 Divider 3 Register (PLLDIV3) ................................................................................. 111
PLLC0 Divider 4 Register (PLLDIV4) .................................................................................. 112
PLLC0 Divider 5 Register (PLLDIV5) .................................................................................. 112
PLLC0 Divider 6 Register (PLLDIV6) .................................................................................. 113
PLLC0 Divider 7 Register (PLLDIV7) .................................................................................. 113
PLLC0 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 114
PLLC1 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 114
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List of Figures
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7-24.
PLL Post-Divider Control Register (POSTDIV) ....................................................................... 115
7-25.
PLL Controller Command Register (PLLCMD)
115
7-26.
PLL Controller Status Register (PLLSTAT)
116
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
9-1.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
18
.......................................................................
...........................................................................
PLLC0 Clock Align Control Register (ALNCTL) ......................................................................
PLLC1 Clock Align Control Register (ALNCTL) ......................................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC0 Clock Enable Control Register (CKEN) .......................................................................
PLLC1 Clock Enable Control Register (CKEN) .......................................................................
PLLC0 Clock Status Register (CKSTAT) ..............................................................................
PLLC1 Clock Status Register (CKSTAT) ..............................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ..........................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ..........................................................................
Emulation Performance Counter 0 Register (EMUCNT0) ...........................................................
Emulation Performance Counter 1 Register (EMUCNT1) ...........................................................
Revision Identification Register (REVID) ..............................................................................
Interrupt Evaluation Register (INTEVAL) ..............................................................................
PSC0 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC1 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC0 Module Error Clear Register 0 (MERRCR0) ..................................................................
PSC1 Module Error Clear Register 0 (MERRCR0) ..................................................................
Power Error Pending Register (PERRPR) ............................................................................
Power Error Clear Register (PERRCR) ................................................................................
Power Domain Transition Command Register (PTCMD)............................................................
Power Domain Transition Status Register (PTSTAT) ................................................................
Power Domain 0 Status Register (PDSTAT0) ........................................................................
Power Domain 1 Status Register (PDSTAT1) ........................................................................
Power Domain 0 Control Register (PDCTL0) .........................................................................
Power Domain 1 Control Register (PDCTL1) .........................................................................
Power Domain 0 Configuration Register (PDCFG0) .................................................................
Power Domain 1 Configuration Register (PDCFG1) .................................................................
Module Status n Register (MDSTATn) .................................................................................
PSC0 Module Control n Register (MDCTLn) .........................................................................
PSC1 Module Control n Register (MDCTLn) .........................................................................
Deep Sleep Mode Sequence ............................................................................................
Revision Identification Register (REVID) ..............................................................................
Device Identification Register 0 (DEVIDR0) ...........................................................................
Boot Configuration Register (BOOTCFG) .............................................................................
Chip Revision Identification Register (CHIPREVIDR)................................................................
Kick 0 Register (KICK0R) ................................................................................................
Kick 1 Register (KICK1R) ................................................................................................
Host 1 Configuration Register (HOST1CFG) .........................................................................
Interrupt Raw Status/Set Register (IRAWSTAT) .....................................................................
Interrupt Enable Status/Clear Register (IENSTAT)...................................................................
Interrupt Enable Register (IENSET) ....................................................................................
Interrupt Enable Clear Register (IENCLR) ............................................................................
End of Interrupt Register (EOI) .........................................................................................
Fault Address Register (FLTADDRR) ..................................................................................
Fault Status Register (FLTSTAT) .......................................................................................
List of Figures
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.................................................................................
Master Priority 1 Register (MSTPRI1) .................................................................................
Master Priority 2 Register (MSTPRI2) .................................................................................
Pin Multiplexing Control 0 Register (PINMUX0) ......................................................................
Pin Multiplexing Control 1 Register (PINMUX1) ......................................................................
Pin Multiplexing Control 2 Register (PINMUX2) ......................................................................
Pin Multiplexing Control 3 Register (PINMUX3) ......................................................................
Pin Multiplexing Control 4 Register (PINMUX4) ......................................................................
Pin Multiplexing Control 5 Register (PINMUX5) ......................................................................
Pin Multiplexing Control 6 Register (PINMUX6) ......................................................................
Pin Multiplexing Control 7 Register (PINMUX7) ......................................................................
Pin Multiplexing Control 8 Register (PINMUX8) ......................................................................
Pin Multiplexing Control 9 Register (PINMUX9) ......................................................................
Pin Multiplexing Control 10 Register (PINMUX10) ...................................................................
Pin Multiplexing Control 11 Register (PINMUX11) ...................................................................
Pin Multiplexing Control 12 Register (PINMUX12) ...................................................................
Pin Multiplexing Control 13 Register (PINMUX13) ...................................................................
Pin Multiplexing Control 14 Register (PINMUX14) ...................................................................
Pin Multiplexing Control 15 Register (PINMUX15) ...................................................................
Pin Multiplexing Control 16 Register (PINMUX16) ...................................................................
Pin Multiplexing Control 17 Register (PINMUX17) ...................................................................
Pin Multiplexing Control 18 Register (PINMUX18) ...................................................................
Pin Multiplexing Control 19 Register (PINMUX19) ...................................................................
Suspend Source Register (SUSPSRC) ................................................................................
Chip Signal Register (CHIPSIG) ........................................................................................
Chip Signal Clear Register (CHIPSIG_CLR) ..........................................................................
Chip Configuration 0 Register (CFGCHIP0) ..........................................................................
Chip Configuration 1 Register (CFGCHIP1) ..........................................................................
Chip Configuration 3 Register (CFGCHIP3) ..........................................................................
Chip Configuration 4 Register (CFGCHIP4) ..........................................................................
VTP I/O Control Register (VTPIO_CTL) ...............................................................................
DDR Slew Register (DDR_SLEW) .....................................................................................
Deep Sleep Register (DEEPSLEEP) ...................................................................................
Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................................
Pullup/Pulldown Select Register (PUPD_SEL) .......................................................................
RXACTIVE Control Register (RXACTIVE) ............................................................................
Data Paths to DDR2/mDDR Memory Controller ......................................................................
DDR2/mDDR Memory Controller Clock Block Diagram .............................................................
DDR2/mDDR Memory Controller Signals .............................................................................
Refresh Command........................................................................................................
DCAB Command..........................................................................................................
DEAC Command..........................................................................................................
ACTV Command ..........................................................................................................
DDR2/mDDR READ Command.........................................................................................
DDR2/mDDR WRT Command ..........................................................................................
DDR2/mDDR MRS and EMRS Command ............................................................................
Byte Alignment ............................................................................................................
DDR2/mDDR SDRAM Column, Row, and Bank Access ............................................................
Address Mapping Diagram (IBANKPOS = 1) .........................................................................
10-15. Master Priority 0 Register (MSTPRI0)
178
10-16.
179
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
SPRUH81C – April 2013 – Revised September 2016
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List of Figures
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181
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12-14. SDRAM Column, Row, Bank Access (IBANKPOS = 1) ............................................................. 257
12-15. DDR2/mDDR Memory Controller FIFO Block Diagram .............................................................. 258
12-16. DDR2/mDDR Memory Controller Reset Block Diagram ............................................................. 262
267
12-18.
269
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
20
...............................................
Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory .........................................
Revision ID Register (REVID) ...........................................................................................
SDRAM Status Register (SDRSTAT) .................................................................................
SDRAM Configuration Register (SDCR) ..............................................................................
SDRAM Refresh Control Register (SDRCR) .........................................................................
SDRAM Timing Register 1 (SDTIMR1) ................................................................................
SDRAM Timing Register 2 (SDTIMR2) ................................................................................
SDRAM Configuration Register 2 (SDCR2) ..........................................................................
Peripheral Bus Burst Priority Register (PBBPR) ......................................................................
Performance Counter 1 Register (PC1) ...............................................................................
Performance Counter 2 Register (PC2) ...............................................................................
Performance Counter Configuration Register (PCC) ................................................................
Performance Counter Master Region Select Register (PCMRS) ..................................................
Performance Counter Time Register (PCT) ...........................................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) ............................................................................................
Interrupt Masked Register (IMR)........................................................................................
Interrupt Mask Set Register (IMSR) ....................................................................................
Interrupt Mask Clear Register (IMCR) .................................................................................
DDR PHY Control Register 1 (DRPYC1R) ............................................................................
Multiple eCAP Modules ..................................................................................................
Capture and APWM Modes of Operation..............................................................................
Capture Function Diagram...............................................................................................
Event Prescale Control...................................................................................................
Prescale Function Waveforms ..........................................................................................
Continuous/One-shot Block Diagram ..................................................................................
Counter and Synchronization Block Diagram .........................................................................
Interrupts in eCAP Module ..............................................................................................
PWM Waveform Details Of APWM Mode Operation ................................................................
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ................................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ..................................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect .............................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ...............................
PWM Waveform Details of APWM Mode Operation .................................................................
Multichannel PWM Example Using 4 eCAP Modules................................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules .......................................
Time-Stamp Counter Register (TSCTR) ...............................................................................
Counter Phase Control Register (CTRPHS) .........................................................................
Capture 1 Register (CAP1) .............................................................................................
Capture 2 Register (CAP2) ..............................................................................................
Capture 3 Register (CAP3) ..............................................................................................
Capture 4 Register (CAP4) ..............................................................................................
ECAP Control Register 1 (ECCTL1) ...................................................................................
ECAP Control Register 2 (ECCTL2) ...................................................................................
ECAP Interrupt Enable Register (ECEINT)............................................................................
12-17. DDR2/mDDR Memory Controller Power Sleep Controller Diagram
List of Figures
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13-26. ECAP Interrupt Flag Register (ECFLG)................................................................................ 328
13-27. ECAP Interrupt Clear Register (ECCLR) .............................................................................. 329
13-28. ECAP Interrupt Forcing Register (ECFRC)............................................................................ 330
13-29. Revision ID Register (REVID) ........................................................................................... 331
14-1.
Multiple ePWM Modules ................................................................................................. 334
14-2.
Submodules and Signal Connections for an ePWM Module........................................................ 335
14-3.
ePWM Submodules and Critical Internal Signal Interconnects ..................................................... 336
14-4.
Time-Base Submodule Block Diagram
14-5.
Time-Base Submodule Signals and Registers ........................................................................ 343
14-6.
Time-Base Frequency and Period ...................................................................................... 345
14-7.
Time-Base Counter Synchronization Scheme 1 ...................................................................... 346
14-8.
Time-Base Up-Count Mode Waveforms ............................................................................... 348
14-9.
Time-Base Down-Count Mode Waveforms
................................................................................
...........................................................................
342
349
14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event ..... 349
14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event
........
350
14-12. Counter-Compare Submodule .......................................................................................... 351
14-13. Counter-Compare Submodule Signals and Registers ............................................................... 351
14-14. Counter-Compare Event Waveforms in Up-Count Mode ............................................................ 354
14-15. Counter-Compare Events in Down-Count Mode
.....................................................................
354
14-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................... 355
14-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ....................................................................................................................... 355
14-18. Action-Qualifier Submodule
.............................................................................................
356
14-19. Action-Qualifier Submodule Inputs and Outputs ...................................................................... 357
14-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ........................................... 358
14-21. Up-Down-Count Mode Symmetrical Waveform ....................................................................... 361
14-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................. 362
14-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................... 364
14-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............. 366
14-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................. 368
14-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ........................................................................................... 370
14-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ......................................................................................................................... 372
14-28. Dead-Band Generator Submodule ..................................................................................... 374
14-29. Configuration Options for the Dead-Band Generator Submodule .................................................. 375
14-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................... 377
14-31. PWM-Chopper Submodule .............................................................................................. 378
14-32. PWM-Chopper Submodule Signals and Registers ................................................................... 379
14-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................ 380
14-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
.......
380
14-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ...................................................................................................................... 381
14-36. Trip-Zone Submodule .................................................................................................... 382
14-37. Trip-Zone Submodule Mode Control Logic ............................................................................ 385
14-38. Trip-Zone Submodule Interrupt Logic .................................................................................. 385
14-39. Event-Trigger Submodule
...............................................................................................
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386
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14-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller ............................................... 387
14-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ........................................ 387
14-42. Event-Trigger Interrupt Generator ...................................................................................... 389
14-43. HRPWM System Interface ............................................................................................... 390
14-44. Resolution Calculations for Conventionally Generated PWM ....................................................... 391
14-45. Operating Logic Using MEP ............................................................................................. 392
14-46. Required PWM Waveform for a Requested Duty = 40.5%
.........................................................
394
14-47. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ................................ 396
14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ................................ 396
14-49. Simplified ePWM Module ................................................................................................ 397
398
14-51.
399
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
14-81.
14-82.
14-83.
14-84.
14-85.
14-86.
14-87.
14-88.
22
......................................
Control of Four Buck Stages. (Note: FPWM1≠ FPWM2≠ FPWM3≠ FPWM4) ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .........................................................
Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) .............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1).............................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) ...........................................................
Half-H Bridge Waveforms for (Note: FPWM2 = FPWM1) ..................................................................
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ...............................
3-Phase Inverter Waveforms for (Only One Inverter Shown) .......................................................
Configuring Two PWM Modules for Phase Control ..................................................................
Timing Waveforms Associated With Phase Control Between 2 Modules .........................................
Control of a 3-Phase Interleaved DC/DC Converter .................................................................
3-Phase Interleaved DC/DC Converter Waveforms for .............................................................
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1 ) ....................................................................
ZVS Full-H Bridge Waveforms ..........................................................................................
Time-Base Control Register (TBCTL) ..................................................................................
Time-Base Status Register (TBSTS) ...................................................................................
Time-Base Phase Register (TBPHS) ..................................................................................
Time-Base Counter Register (TBCNT) ................................................................................
Time-Base Period Register (TBPRD) ..................................................................................
Counter-Compare Control Register (CMPCTL) .......................................................................
Counter-Compare A Register (CMPA) ................................................................................
Counter-Compare B Register (CMPB) .................................................................................
Action-Qualifier Output A Control Register (AQCTLA)...............................................................
Action-Qualifier Output B Control Register (AQCTLB)...............................................................
Action-Qualifier Software Force Register (AQSFRC) ................................................................
Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................
Dead-Band Generator Control Register (DBCTL) ....................................................................
Dead-Band Generator Rising Edge Delay Register (DBRED) ......................................................
Dead-Band Generator Falling Edge Delay Register (DBFED) .....................................................
PWM-Chopper Control Register (PCCTL) .............................................................................
Trip-Zone Select Register (TZSEL) ....................................................................................
Trip-Zone Control Register (TZCTL) ...................................................................................
Trip-Zone Enable Interrupt Register (TZEINT) ........................................................................
Trip-Zone Flag Register (TZFLG).......................................................................................
Trip-Zone Clear Register (TZCLR) .....................................................................................
Trip-Zone Force Register (TZFRC).....................................................................................
Event-Trigger Selection Register (ETSEL) ............................................................................
Event-Trigger Prescale Register (ETPS) ..............................................................................
14-50. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
List of Figures
400
402
403
405
406
408
409
412
413
414
415
418
419
421
423
424
424
425
426
427
428
429
430
431
432
433
434
434
435
436
437
437
438
439
439
440
441
SPRUH81C – April 2013 – Revised September 2016
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14-89. Event-Trigger Flag Register (ETFLG) .................................................................................. 442
14-90. Event-Trigger Clear Register (ETCLR)
................................................................................
442
14-91. Event-Trigger Force Register (ETFRC) ................................................................................ 443
..........................................................
Counter-Compare A High-Resolution Register (CMPAHR) .........................................................
HRPWM Configuration Register (HRCNFG) ..........................................................................
EDMA3 Controller Block Diagram ......................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram ...........................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................
Definition of ACNT, BCNT, and CCNT ................................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................
PaRAM Set ................................................................................................................
Linked Transfer Example ................................................................................................
Link-to-Self Transfer Example ..........................................................................................
QDMA Channel to PaRAM Mapping ...................................................................................
Shadow Region Registers ...............................................................................................
Interrupt Diagram .........................................................................................................
Error Interrupt Operation .................................................................................................
EDMA3 Prioritization .....................................................................................................
Block Move Example .....................................................................................................
Block Move Example PaRAM Configuration ..........................................................................
Subframe Extraction Example ..........................................................................................
Subframe Extraction Example PaRAM Configuration................................................................
Data Sorting Example ....................................................................................................
Data Sorting Example PaRAM Configuration .........................................................................
Servicing Incoming McBSP Data Example ............................................................................
Servicing Incoming McBSP Data Example PaRAM ..................................................................
Servicing Peripheral Burst Example ....................................................................................
Servicing Peripheral Burst Example PaRAM..........................................................................
Servicing Continuous McBSP Data Example .........................................................................
Servicing Continuous McBSP Data Example PaRAM ...............................................................
Servicing Continuous McBSP Data Example Reload PaRAM ......................................................
Ping-Pong Buffering for McBSP Data Example ......................................................................
Ping-Pong Buffering for McBSP Example PaRAM ...................................................................
Ping-Pong Buffering for McBSP Example Pong PaRAM ............................................................
Ping-Pong Buffering for McBSP Example Ping PaRAM .............................................................
Intermediate Transfer Completion Chaining Example ...............................................................
Single Large Block Transfer Example .................................................................................
Smaller Packet Data Transfers Example ..............................................................................
Channel Options Parameter (OPT).....................................................................................
Channel Source Address Parameter (SRC) ..........................................................................
A Count/B Count Parameter (A_B_CNT) ..............................................................................
Channel Destination Address Parameter (DST) ......................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ...............................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) ......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ...............................................
C Count Parameter (CCNT) .............................................................................................
Revision ID Register (REVID) ...........................................................................................
14-92. Time-Base Phase High-Resolution Register (TBPHSHR)
444
14-93.
444
14-94.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
SPRUH81C – April 2013 – Revised September 2016
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List of Figures
445
450
453
454
455
456
457
458
466
467
474
476
481
484
491
495
496
497
497
498
499
500
501
502
502
503
504
504
507
508
508
509
511
511
512
513
515
515
516
516
517
518
518
522
23
www.ti.com
15-44. EDMA3CC Configuration Register (CCCFG) ......................................................................... 522
15-45. QDMA Channel n Mapping Register (QCHMAPn) ................................................................... 524
15-46. DMA Channel Queue Number Register n (DMAQNUMn) ........................................................... 525
15-47. QDMA Channel Queue Number Register (QDMAQNUM) .......................................................... 526
15-48. Event Missed Register (EMR)........................................................................................... 527
528
15-50.
529
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
15-72.
15-73.
15-74.
15-75.
15-76.
15-77.
15-78.
15-79.
15-80.
15-81.
15-82.
15-83.
15-84.
15-85.
15-86.
15-87.
15-88.
15-89.
15-90.
15-91.
15-92.
24
.................................................................................
QDMA Event Missed Register (QEMR)................................................................................
QDMA Event Missed Clear Register (QEMCR) ......................................................................
EDMA3CC Error Register (CCERR) ...................................................................................
EDMA3CC Error Clear Register (CCERRCLR).......................................................................
Error Evaluate Register (EEVAL) .......................................................................................
DMA Region Access Enable Register for Region m (DRAEm) .....................................................
QDMA Region Access Enable for Region m (QRAEm) .............................................................
Event Queue Entry Registers (QxEy) ..................................................................................
Queue n Status Register (QSTATn) ...................................................................................
Queue Watermark Threshold A Register (QWMTHRA) .............................................................
EDMA3CC Status Register (CCSTAT) ................................................................................
Event Register (ER) ......................................................................................................
Event Clear Register (ECR) .............................................................................................
Event Set Register (ESR)................................................................................................
Chained Event Register (CER) .........................................................................................
Event Enable Register (EER) ...........................................................................................
Event Enable Clear Register (EECR) ..................................................................................
Event Enable Set Register (EESR) ....................................................................................
Secondary Event Register (SER) .......................................................................................
Secondary Event Clear Register (SECR) .............................................................................
Interrupt Enable Register (IER) .........................................................................................
Interrupt Enable Clear Register (IECR) ................................................................................
Interrupt Enable Set Register (IESR) ..................................................................................
Interrupt Pending Register (IPR)........................................................................................
Interrupt Clear Register (ICR) ...........................................................................................
Interrupt Evaluate Register (IEVAL) ....................................................................................
QDMA Event Register (QER) ...........................................................................................
QDMA Event Enable Register (QEER) ................................................................................
QDMA Event Enable Clear Register (QEECR) .......................................................................
QDMA Event Enable Set Register (QEESR) .........................................................................
QDMA Secondary Event Register (QSER) ............................................................................
QDMA Secondary Event Clear Register (QSECR) ..................................................................
Revision ID Register (REVID) ...........................................................................................
EDMA3TC Configuration Register (TCCFG) ..........................................................................
EDMA3TC Channel Status Register (TCSTAT) ......................................................................
Error Status Register (ERRSTAT) ......................................................................................
Error Enable Register (ERREN) ........................................................................................
Error Clear Register (ERRCLR) ........................................................................................
Error Details Register (ERRDET) .......................................................................................
Error Interrupt Command Register (ERRCMD) .......................................................................
Read Command Rate Register (RDRATE)............................................................................
Source Active Options Register (SAOPT) .............................................................................
Source Active Source Address Register (SASRC) ...................................................................
15-49. Event Missed Clear Register (EMCR)
List of Figures
530
531
532
533
534
535
536
537
538
539
541
542
543
544
545
546
546
547
547
548
549
549
550
551
552
553
554
555
555
556
557
559
560
561
562
563
564
565
566
567
568
569
SPRUH81C – April 2013 – Revised September 2016
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www.ti.com
15-93. Source Active Count Register (SACNT) ............................................................................... 569
15-94. Source Active Destination Address Register (SADST) .............................................................. 570
15-95. Source Active B-Index Register (SABIDX) ............................................................................ 570
15-96. Source Active Memory Protection Proxy Register (SAMPPRXY) .................................................. 571
15-97. Source Active Count Reload Register (SACNTRLD) ................................................................ 572
15-98. Source Active Source Address B-Reference Register (SASRCBREF) ............................................ 572
15-99. Source Active Destination Address B-Reference Register (SADSTBREF) ....................................... 573
15-100. Destination FIFO Set Count Reload Register (DFCNTRLD) ...................................................... 573
15-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) .................................. 574
15-102. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) ............................. 574
15-103. Destination FIFO Options Register n (DFOPTn) .................................................................... 575
15-104. Destination FIFO Source Address Register n (DFSRCn) .......................................................... 576
15-105. Destination FIFO Count Register n (DFCNTn) ...................................................................... 576
15-106. Destination FIFO Destination Address Register n (DFDSTn) ..................................................... 577
15-107. Destination FIFO B-Index Register n (DFBIDXn) ................................................................... 577
15-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) ......................................... 578
......................................................................................
16-1.
EMIFA Functional Block Diagram
16-2.
Timing Waveform of SDRAM PRE Command ........................................................................ 587
16-3.
EMIFA to 2M × 16 × 4 bank SDRAM Interface ....................................................................... 588
16-4.
EMIFA to 512K × 16 × 2 bank SDRAM Interface
16-5.
Timing Waveform for Basic SDRAM Read Operation ............................................................... 595
16-6.
Timing Waveform for Basic SDRAM Write Operation
16-7.
EMIFA Asynchronous Interface ......................................................................................... 598
16-8.
EMIFA to 8-bit/16-bit Memory Interface................................................................................ 599
16-9.
Common Asynchronous Interface ...................................................................................... 599
....................................................................
...............................................................
583
588
596
16-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 604
16-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode .............................................. 606
16-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...................................... 608
16-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 610
16-14. EMIFA to NAND Flash Interface ........................................................................................ 612
16-15. ECC Value for 8-Bit NAND Flash ....................................................................................... 614
16-16. EMIFA Reset Block Diagram ............................................................................................ 617
16-17. EMIFA PSC Block Diagram ............................................................................................. 622
16-18. Example Configuration Interface ........................................................................................ 625
16-19. SDRAM Timing Register (SDTIMR) .................................................................................... 626
16-20. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 627
16-21. SDRAM Refresh Control Register (SDRCR) .......................................................................... 627
16-22. SDRAM Configuration Register (SDCR)............................................................................... 628
................................................................................
Timing Waveform of an ASRAM Write ................................................................................
Timing Waveform of an ASRAM Read with PCB Delays............................................................
Timing Waveform of an ASRAM Write with PCB Delays ............................................................
Timing Waveform of a NAND Flash Read ............................................................................
Timing Waveform of a NAND Flash Command Write ...............................................................
Timing Waveform of a NAND Flash Address Write .................................................................
Timing Waveform of a NAND Flash Data Write .....................................................................
Module ID Register (MIDR)..............................................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) .......................................................
SDRAM Configuration Register (SDCR)...............................................................................
16-23. Timing Waveform of an ASRAM Read
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
SPRUH81C – April 2013 – Revised September 2016
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List of Figures
630
631
633
634
639
641
641
642
647
647
649
25
www.ti.com
16-34. SDRAM Refresh Control Register (SDRCR) .......................................................................... 651
16-35. Asynchronous n Configuration Register (CEnCFG) .................................................................. 652
16-36. SDRAM Timing Register (SDTIMR) .................................................................................... 654
16-37. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 655
16-38. EMIFA Interrupt Raw Register (INTRAW) ............................................................................. 656
16-39. EMIFA Interrupt Mask Register (INTMSK) ............................................................................ 657
16-40. EMIFA Interrupt Mask Set Register (INTMSKSET) .................................................................. 658
16-41. EMIFA Interrupt Mask Clear Register (INTMSKCLR) ................................................................ 659
16-42. NAND Flash Control Register (NANDFCR) ........................................................................... 660
16-43. NAND Flash Status Register (NANDFSR) ............................................................................ 662
663
16-45.
664
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
26
........................................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ..................................................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..............................................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..............................................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..............................................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..............................................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1).............................................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2).............................................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ................................................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ................................................
GPIO Block Diagram .....................................................................................................
Revision ID Register (REVID) ...........................................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) ................................................................
GPIO Banks 0 and 1 Direction Register (DIR01) .....................................................................
GPIO Banks 2 and 3 Direction Register (DIR23) .....................................................................
GPIO Banks 4 and 5 Direction Register (DIR45) .....................................................................
GPIO Banks 6 and 7 Direction Register (DIR67) .....................................................................
GPIO Bank 8 Direction Register (DIR8) ...............................................................................
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) .......................................................
GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) .......................................................
GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) .......................................................
GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) .......................................................
GPIO Bank 8 Output Data Register (OUT_DATA8) .................................................................
GPIO Banks 0 and 1 Set Data Register (SET_DATA01)............................................................
GPIO Banks 2 and 3 Set Data Register (SET_DATA23)............................................................
GPIO Banks 4 and 5 Set Data Register (SET_DATA45)............................................................
GPIO Banks 6 and 7 Set Data Register (SET_DATA67)............................................................
GPIO Bank 8 Set Data Register (SET_DATA8) ......................................................................
GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) .........................................................
GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .........................................................
GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) .........................................................
GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) .........................................................
GPIO Bank 8 Clear Data Register (CLR_DATA8) ...................................................................
GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ............................................................
GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ............................................................
GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ............................................................
GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ............................................................
GPIO Bank 8 Input Data Register (IN_DATA8).......................................................................
GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01) .............................................
16-44. NAND Flash n ECC Register (NANDFnECC)
List of Figures
665
665
666
666
667
667
668
668
671
680
681
682
682
682
682
683
684
684
684
684
685
686
686
686
686
687
688
688
688
688
689
690
690
690
690
691
692
SPRUH81C – April 2013 – Revised September 2016
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17-30. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) ............................................. 692
17-31. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) ............................................. 692
17-32. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) ............................................. 692
17-33. GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) ........................................................ 693
17-34. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ........................................... 694
17-35. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) ........................................... 694
17-36. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ........................................... 694
17-37. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ........................................... 694
17-38. GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) ..................................................... 695
17-39. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) ............................................. 696
17-40. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) ............................................. 696
17-41. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) ............................................. 696
17-42. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) ............................................. 696
17-43. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8) ....................................................... 697
17-44. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) .......................................... 698
17-45. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) .......................................... 698
17-46. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) .......................................... 698
17-47. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) .......................................... 698
17-48. GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) ..................................................... 699
17-49. GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ...................................................... 700
17-50. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ...................................................... 700
17-51. GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) ...................................................... 700
17-52. GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) ...................................................... 700
17-53. GPIO Bank 8 Interrupt Status Register (INTSTAT8) ................................................................. 701
.......................................................................................................
18-1.
HPI Block Diagram
18-2.
Example of Host-Processor Signal Connections ..................................................................... 709
704
18-3.
HPI Strobe and Select Logic ............................................................................................ 711
18-4.
Multiplexed-Mode Host Read Cycle .................................................................................... 713
18-5.
Multiplexed-Mode Host Write Cycle .................................................................................... 714
18-6.
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) ................................................... 715
18-7.
UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode ......................... 716
18-8.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle) .......................................................... 716
18-9.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles) .............................................................. 716
18-10. UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode ................................... 717
18-11. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1:
No Autoincrementing) .................................................................................................... 717
18-12. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2:
Autoincrementing Selected, FIFO Empty Before Write) ............................................................. 717
18-13. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 3:
Autoincrementing Selected, FIFO Not Empty Before Write) ........................................................ 718
18-14. FIFOs in the HPI .......................................................................................................... 719
18-15. Host-to-CPU Interrupt State Diagram .................................................................................. 724
18-16. CPU-to-Host Interrupt State Diagram .................................................................................. 725
18-17. Revision Identification Register (REVID) .............................................................................. 727
................................................
GPIO Enable Register (GPIO_EN) .....................................................................................
GPIO Direction 1 Register (GPIO_DIR1) ..............................................................................
GPIO Data 1 Register (GPIO_DAT1) ..................................................................................
18-18. Power and Emulation Management Register (PWREMU_MGMT)
727
18-19.
728
18-20.
18-21.
SPRUH81C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
729
729
27
www.ti.com
18-22. GPIO Direction 2 Register (GPIO_DIR2) .............................................................................. 730
18-23. GPIO Data 2 Register (GPIO_DAT2) .................................................................................. 731
18-24. Host Port Interface Control Register (HPIC)–Host Access Permissions .......................................... 732
18-25. Host Port Interface Control Register (HPIC)–CPU Access Permissions .......................................... 732
18-26. Host Port Interface Write Address Register (HPIAW)................................................................ 734
18-27. Host Port Interface Read Address Register (HPIAR) ................................................................ 734
19-1.
I2C Peripheral Block Diagram........................................................................................... 737
19-2.
Multiple I2C Modules Connected ....................................................................................... 738
19-3.
Clocking Diagram for the I2C Peripheral .............................................................................. 739
19-4.
Synchronization of Two I2C Clock Generators During Arbitration
740
19-5.
Bit Transfer on the I2C-Bus
741
19-6.
19-7.
19-8.
19-9.
.................................................
.............................................................................................
I2C Peripheral START and STOP Conditions ........................................................................
I2C Peripheral Data Transfer ............................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) ............................................
741
742
742
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR)......................................................................................................... 743
19-10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR) .............................................................. 743
...
Arbitration Procedure Between Two Master-Transmitters...........................................................
I2C Own Address Register (ICOAR) ...................................................................................
I2C Interrupt Mask Register (ICIMR) ...................................................................................
I2C Interrupt Status Register (ICSTR) .................................................................................
I2C Clock Low-Time Divider Register (ICCLKL) ......................................................................
I2C Clock High-Time Divider Register (ICCLKH) .....................................................................
I2C Data Count Register (ICCNT) ......................................................................................
I2C Data Receive Register (ICDRR) ...................................................................................
I2C Slave Address Register (ICSAR) ..................................................................................
I2C Data Transmit Register (ICDXR) ..................................................................................
I2C Mode Register (ICMDR) ............................................................................................
Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ....................................
I2C Interrupt Vector Register (ICIVR) ..................................................................................
I2C Extended Mode Register (ICEMDR) ..............................................................................
I2C Prescaler Register (ICPSC) ........................................................................................
I2C Revision Identification Register 1 (REVID1) .....................................................................
I2C Revision Identification Register 2 (REVID2) .....................................................................
I2C DMA Control Register (ICDMAC) ..................................................................................
I2C Pin Function Register (ICPFUNC) .................................................................................
I2C Pin Direction Register (ICPDIR) ...................................................................................
I2C Pin Data In Register (ICPDIN) .....................................................................................
I2C Pin Data Out Register (ICPDOUT) ................................................................................
I2C Pin Data Set Register (ICPDSET) .................................................................................
I2C Pin Data Clear Register (ICPDCLR) ..............................................................................
McASP Block Diagram ...................................................................................................
McASP to Parallel 2-Channel DACs ..................................................................................
McASP to 6-Channel DAC and 2-Channel DAC .....................................................................
McASP to Digital Amplifier ...............................................................................................
McASP as Digital Audio Encoder ......................................................................................
TDM Format–6 Channel TDM Example ...............................................................................
TDM Format Bit Delays from Frame Sync ............................................................................
19-11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR)
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
28
List of Figures
743
746
751
752
753
756
756
757
758
759
760
761
764
765
766
767
768
768
769
770
771
772
773
774
775
779
780
780
781
781
782
783
SPRUH81C – April 2013 – Revised September 2016
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20-8.
Inter-IC Sound (I2S) Format ............................................................................................. 783
20-9.
Biphase-Mark Code (BMC) .............................................................................................. 784
20-10. S/PDIF Subframe Format ................................................................................................ 785
20-11. S/PDIF Frame Format .................................................................................................... 786
20-12. Definition of Bit, Word, and Slot
........................................................................................
787
20-13. Bit Order and Word Alignment Within a Slot Examples ............................................................. 788
20-14. Definition of Frame and Frame Sync Width ........................................................................... 789
20-15. Transmit Clock Generator Block Diagram ............................................................................. 791
20-16. Receive Clock Generator Block Diagram .............................................................................. 792
20-17. Frame Sync Generator Block Diagram
...............................................................................
793
20-18. Individual Serializer and Connections Within McASP ................................................................ 794
20-19. Receive Format Unit...................................................................................................... 795
20-20. Transmit Format Unit ..................................................................................................... 796
20-21. McASP I/O Pin Control Block Diagram ................................................................................ 798
20-22. McASP I/O Pin to Control Register Mapping.......................................................................... 799
20-23. Burst Frame Sync Mode ................................................................................................. 804
20-24. Transmit DMA Event (AXEVT) Generation in TDM Time Slots
....................................................
807
20-25. DSP Service Time Upon Transmit DMA Event (AXEVT)............................................................ 812
20-26. DSP Service Time Upon Receive DMA Event (AREVT) ............................................................ 814
20-27. DMA Events in an Audio Example–Two Events ...................................................................... 816
20-28. McASP Audio FIFO (AFIFO) Block Diagram .......................................................................... 817
20-29. Data Flow Through Transmit Format Unit ............................................................................. 820
20-30. Data Flow Through Receive Format Unit .............................................................................. 822
20-31. Audio Mute (AMUTE) Block Diagram .................................................................................. 824
20-32. Transmit Clock Failure Detection Circuit Block Diagram ............................................................ 828
20-33. Receive Clock Failure Detection Circuit Block Diagram ............................................................. 829
20-34. Serializers in Loopback Mode ........................................................................................... 830
20-35. Revision Identification Register (REV) ................................................................................. 836
........................................................................................
Pin Direction Register (PDIR) ...........................................................................................
Pin Data Output Register (PDOUT) ....................................................................................
Pin Data Input Register (PDIN) .........................................................................................
Pin Data Set Register (PDSET).........................................................................................
Pin Data Clear Register (PDCLR) ......................................................................................
Global Control Register (GBLCTL) .....................................................................................
Audio Mute Control Register (AMUTE) ................................................................................
Digital Loopback Control Register (DLBCTL) .........................................................................
Digital Mode Control Register (DITCTL) ...............................................................................
Receiver Global Control Register (RGBLCTL) ........................................................................
Receive Format Unit Bit Mask Register (RMASK) ...................................................................
Receive Bit Stream Format Register (RFMT) .........................................................................
Receive Frame Sync Control Register (AFSRCTL) ..................................................................
Receive Clock Control Register (ACLKRCTL) ........................................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ..................................................
Receive TDM Time Slot Register (RTDM) ............................................................................
Receiver Interrupt Control Register (RINTCTL) ......................................................................
Receiver Status Register (RSTAT) .....................................................................................
Current Receive TDM Time Slot Registers (RSLOT) ................................................................
Receive Clock Check Control Register (RCLKCHK) .................................................................
20-36. Pin Function Register (PFUNC)
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
SPRUH81C – April 2013 – Revised September 2016
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List of Figures
837
839
841
843
845
847
849
851
853
854
855
856
857
859
860
861
862
863
864
865
866
29
www.ti.com
20-57. Receiver DMA Event Control Register (REVTCTL) .................................................................. 867
20-58. Transmitter Global Control Register (XGBLCTL) ..................................................................... 868
20-59. Transmit Format Unit Bit Mask Register (XMASK) ................................................................... 869
20-60. Transmit Bit Stream Format Register (XFMT) ........................................................................ 870
20-61. Transmit Frame Sync Control Register (AFSXCTL) ................................................................. 872
20-62. Transmit Clock Control Register (ACLKXCTL) ....................................................................... 873
20-63. Transmit High-Frequency Clock Control Register (AHCLKXCTL)
.................................................
874
20-64. Transmit TDM Time Slot Register (XTDM) ............................................................................ 875
20-65. Transmitter Interrupt Control Register (XINTCTL).................................................................... 876
20-66. Transmitter Status Register (XSTAT) .................................................................................. 877
20-67. Current Transmit TDM Time Slot Register (XSLOT) ................................................................. 878
20-68. Transmit Clock Check Control Register (XCLKCHK) ................................................................ 879
20-69. Transmitter DMA Event Control Register (XEVTCTL) ............................................................... 880
881
20-71.
882
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
30
................................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .......................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) .....................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ..................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ................................................
Transmit Buffer Registers (XBUFn) ....................................................................................
Receive Buffer Registers (RBUFn) .....................................................................................
AFIFO Revision Identification Register (AFIFOREV) ................................................................
Write FIFO Control Register (WFIFOCTL) ............................................................................
Write FIFO Status Register (WFIFOSTS) .............................................................................
Read FIFO Control Register (RFIFOCTL) .............................................................................
Read FIFO Status Register (RFIFOSTS) ..............................................................................
McBSP Block Diagram ...................................................................................................
Clock and Frame Generation ...........................................................................................
Transmit Data Clocking ..................................................................................................
Receive Data Clocking ...................................................................................................
Sample Rate Generator Block Diagram ...............................................................................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ............................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ............................
Digital Loopback Mode ...................................................................................................
Programmable Frame Period and Width ..............................................................................
Dual-Phase Frame Example ............................................................................................
Single-Phase Frame of Four 8-Bit Elements ..........................................................................
Single-Phase Frame of One 32-Bit Element ..........................................................................
Data Delay .................................................................................................................
2-Bit Data Delay Used to Discard Framing Bit ........................................................................
McBSP Standard Operation .............................................................................................
Receive Operation ........................................................................................................
Transmit Operation .......................................................................................................
Maximum Frame Frequency for Transmit and Receive .............................................................
Unexpected Frame Synchronization With (R/X)FIG = 0 .............................................................
Unexpected Frame Synchronization With (R/X)FIG = 1 .............................................................
Maximum Frame Frequency Operation With 8-Bit Data .............................................................
Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ..................................................
Serial Port Receive Overrun.............................................................................................
Serial Port Receive Overrun Avoided ..................................................................................
20-70. Serializer Control Registers (SRCTLn)
List of Figures
882
883
883
884
884
885
886
887
888
889
892
894
895
895
896
899
899
900
902
904
905
906
906
907
908
909
909
910
911
912
912
913
914
914
SPRUH81C – April 2013 – Revised September 2016
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21-25. Decision Tree Response to Receive Frame Synchronization Pulse ............................................... 915
21-26. Unexpected Receive Frame Synchronization Pulse ................................................................. 916
21-27. Transmit With Data Overwrite ........................................................................................... 916
...........................................................................................................
Transmit Empty Avoided .................................................................................................
Decision Tree Response to Transmit Frame Synchronization Pulse ..............................................
Unexpected Transmit Frame Synchronization Pulse ................................................................
McBSP Buffer FIFO (BFIFO) Block Diagram .........................................................................
Companding Flow ........................................................................................................
Companding Data Formats ..............................................................................................
Transmit Data Companding Format in DXR ..........................................................................
Companding of Internal Data ............................................................................................
DX Timing for Multichannel Operation .................................................................................
Alternating Between the Channels of Partition A and the Channels of Partition B ..............................
Reassigning Channel Blocks Throughout a McBSP Data Transfer ................................................
McBSP Data Transfer in the 8-Partition Mode ........................................................................
Activity on McBSP Pins for the Possible Values of XMCM .........................................................
Data Receive Register (DRR) ...........................................................................................
Data Transmit Register (DXR) ..........................................................................................
Serial Port Control Register (SPCR) ...................................................................................
Receive Control Register (RCR) ........................................................................................
Transmit Control Register (XCR) .......................................................................................
Sample Rate Generator Register (SRGR) ............................................................................
Multichannel Control Registers (MCR) .................................................................................
Enhanced Receive Channel Enable Register n (RCEREn) .........................................................
Enhanced Transmit Channel Enable Register n (XCEREn) ........................................................
Pin Control Register (PCR) ..............................................................................................
BFIFO Revision Identification Register (BFIFOREV) ................................................................
Write FIFO Control Register (WFIFOCTL) ............................................................................
Write FIFO Status Register (WFIFOSTS) .............................................................................
Read FIFO Control Register (RFIFOCTL) .............................................................................
Read FIFO Status Register (RFIFOSTS) ..............................................................................
Real-Time Clock Block Diagram ........................................................................................
32-kHz Oscillator Counter Compensation .............................................................................
Kick State Machine .......................................................................................................
Second Register (SECOND) ............................................................................................
Minute Register (MINUTE) ..............................................................................................
Hour Register (HOUR) ...................................................................................................
Days Register (DAY) .....................................................................................................
Month Register (MONTH) ...............................................................................................
Year Register (YEAR) ....................................................................................................
Day of the Week Register (DOTW) ....................................................................................
Alarm Second Register (ALARMSECOND) ...........................................................................
Alarm Minute Register (ALARMMINUTE) .............................................................................
Alarm Hour Register (ALARMHOUR) ..................................................................................
Alarm Day Register (ALARMDAY) .....................................................................................
Alarm Month Register (ALARMMONTH) ..............................................................................
Alarm Year Register (ALARMYEAR) ...................................................................................
Control Register (CTRL) .................................................................................................
21-28. Transmit Empty
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
SPRUH81C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
917
917
919
919
920
922
922
922
923
925
927
927
928
931
941
941
942
944
946
948
949
953
955
957
959
960
961
962
963
965
969
970
973
973
974
975
975
976
976
977
977
978
979
980
980
981
31
www.ti.com
22-18. Status Register (STATUS)............................................................................................... 982
22-19. Interrupt Register (INTERRUPT)
.......................................................................................
983
22-20. Compensation (LSB) Register (COMPLSB)........................................................................... 984
22-21. Compensation (MSB) Register (COMPMSB) ......................................................................... 985
22-22. Oscillator Register (OSC) ................................................................................................ 986
22-23. Scratch Registers (SCRATCHn) ........................................................................................ 987
22-24. Kick Registers (KICKnR) ................................................................................................. 987
23-1.
SPI Block Diagram........................................................................................................ 990
23-2.
SPI 3-Pin Option .......................................................................................................... 996
23-3.
SPI 4-Pin Option with SPIx_SCS[n]
23-4.
SPI 4-Pin Option with SPIx_ENA
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
24-1.
24-2.
32
................................................................................... 998
..................................................................................... 1000
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ............................................................... 1002
Format for Transmitting 12-Bit Word.................................................................................. 1003
Format for 10-Bit Received Word ..................................................................................... 1003
Clock Mode with POLARITY = 0 and PHASE = 0 .................................................................. 1004
Clock Mode with POLARITY = 0 and PHASE = 1 .................................................................. 1005
Clock Mode with POLARITY = 1 and PHASE = 0 .................................................................. 1005
Clock Mode with POLARITY = 1 and PHASE = 1 .................................................................. 1005
Five Bits per Character (5-Pin Option) ............................................................................... 1006
SPI 3-Pin Master Mode with WDELAY ............................................................................... 1011
SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY ............................. 1012
SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY .................................... 1013
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY ....................................... 1015
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY .................................................... 1016
SPI Global Control Register 0 (SPIGCR0) ........................................................................... 1017
SPI Global Control Register 1 (SPIGCR1) ........................................................................... 1018
SPI Interrupt Register (SPIINT0) ...................................................................................... 1020
SPI Interrupt Level Register (SPILVL) ................................................................................ 1022
SPI Flag Register (SPIFLG) ........................................................................................... 1023
SPI Pin Control Register 0 (SPIPC0) ................................................................................. 1025
SPI Pin Control Register 1 (SPIPC1) ................................................................................. 1026
SPI Pin Control Register 2 (SPIPC2) ................................................................................. 1027
SPI Pin Control Register 3 (SPIPC3) ................................................................................. 1028
SPI Pin Control Register 4 (SPIPC4) ................................................................................. 1029
SPI Pin Control Register 5 (SPIPC5) ................................................................................. 1030
SPI Data Register 0 (SPIDAT0) ....................................................................................... 1031
SPI Data Register 1 (SPIDAT1) ....................................................................................... 1032
SPI Buffer Register (SPIBUF) ......................................................................................... 1033
SPI Emulation Register (SPIEMU) .................................................................................... 1035
SPI Delay Register (SPIDELAY) ...................................................................................... 1036
Example: tC2TDELAY = 8 SPI Module Clock Cycles .................................................................... 1037
Example: tT2CDELAY = 4 SPI Module Clock Cycles .................................................................... 1038
Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout ........................................................... 1038
Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout........................................................... 1038
SPI Default Chip Select Register (SPIDEF) ......................................................................... 1039
SPI Data Format Register (SPIFMTn) ................................................................................ 1040
SPI Interrupt Vector Register 1 (INTVEC1) .......................................................................... 1042
Timer Block Diagram ................................................................................................... 1045
Timer Clock Source Block Diagram................................................................................... 1046
List of Figures
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24-3.
64-Bit Timer Mode Block Diagram .................................................................................... 1047
24-4.
Dual 32-Bit Timers Chained Mode Block Diagram
24-5.
Dual 32-Bit Timers Chained Mode Example ......................................................................... 1050
24-6.
Dual 32-Bit Timers Unchained Mode Block Diagram ............................................................... 1052
24-7.
Dual 32-Bit Timers Unchained Mode Example ...................................................................... 1053
24-8.
32-Bit Timer Counter Overflow Example ............................................................................. 1056
24-9.
Watchdog Timer Mode Block Diagram ............................................................................... 1058
.................................................................
1050
24-10. Watchdog Timer Operation State Diagram .......................................................................... 1058
24-11. Timer Operation in Pulse Mode (CPn = 0) ........................................................................... 1060
24-12. Timer Operation in Clock Mode (CPn = 1) ........................................................................... 1060
24-13. Revision ID Register (REVID) ......................................................................................... 1064
24-14. Emulation Management Register (EMUMGT) ....................................................................... 1064
24-15. GPIO Interrupt Control and Enable Register (GPINTGPEN) ...................................................... 1065
...............................................................
Timer Counter Register 12 (TIM12)...................................................................................
Timer Counter Register 34 (TIM34)...................................................................................
Timer Period Register 12 (PRD12) ...................................................................................
Timer Period Register 34 (PRD34) ...................................................................................
Timer Control Register (TCR) .........................................................................................
Timer Global Control Register (TGCR) ...............................................................................
Watchdog Timer Control Register (WDTCR) ........................................................................
Timer Reload Register 12 (REL12) ...................................................................................
Timer Reload Register 34 (REL34) ...................................................................................
Timer Capture Register 12 (CAP12) ..................................................................................
Timer Capture Register 34 (CAP34) ..................................................................................
Timer Interrupt Control and Status Register (INTCTLSTAT) ......................................................
Timer Compare Register (CMPn) .....................................................................................
UART Block Diagram ...................................................................................................
UART Clock Generation Diagram .....................................................................................
Relationships Between Data Bit, BCLK, and UART Input Clock ..................................................
UART Protocol Formats ................................................................................................
UART Interface Using Autoflow Diagram ............................................................................
Autoflow Functional Timing Waveforms for UARTn_RTS ........................................................
Autoflow Functional Timing Waveforms for UARTn_CTS ........................................................
UART Interrupt Request Enable Paths ...............................................................................
Receiver Buffer Register (RBR) .......................................................................................
Transmitter Holding Register (THR) ..................................................................................
Interrupt Enable Register (IER)........................................................................................
Interrupt Identification Register (IIR) ..................................................................................
FIFO Control Register (FCR) ..........................................................................................
Line Control Register (LCR) ...........................................................................................
Modem Control Register (MCR) .......................................................................................
Line Status Register (LSR).............................................................................................
Modem Status Register (MSR) ........................................................................................
Scratch Pad Register (SCR) ...........................................................................................
Divisor LSB Latch (DLL) ................................................................................................
Divisor MSB Latch (DLH) ..............................................................................................
Revision Identification Register 1 (REVID1) .........................................................................
Revision Identification Register 2 (REVID2) .........................................................................
24-16. GPIO Data and Direction Register (GPDATGPDIR)
1066
24-17.
1067
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
SPRUH81C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1067
1068
1068
1069
1071
1072
1073
1073
1074
1074
1075
1076
1079
1080
1081
1083
1086
1087
1087
1089
1092
1093
1094
1095
1097
1098
1100
1101
1104
1105
1106
1106
1107
1107
33
www.ti.com
25-23. Power and Emulation Management Register (PWREMU_MGMT) ............................................... 1108
25-24. Mode Definition Register (MDR)
34
List of Figures
......................................................................................
1109
SPRUH81C – April 2013 – Revised September 2016
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List of Tables
2-1.
DSP Interrupt Map ......................................................................................................... 55
3-1.
TMS320C6742 DSP System Interconnect Matrix ...................................................................... 61
5-1.
MPU Memory Regions..................................................................................................... 67
5-2.
MPU2 Default Configuration .............................................................................................. 67
5-3.
Device Master Settings .................................................................................................... 67
5-4.
Request Type Access Controls........................................................................................... 69
5-5.
MPU_BOOTCFG_ERR Interrupt Sources .............................................................................. 71
5-6.
Memory Protection Unit 2 (MPU2) Registers ........................................................................... 71
5-7.
Revision ID Register (REVID) Field Descriptions ...................................................................... 72
5-8.
Configuration Register (CONFIG) Field Descriptions
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
................................................................. 73
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions................................................. 74
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions .............................................. 75
Interrupt Enable Set Register (IENSET) Field Descriptions .......................................................... 76
Interrupt Enable Clear Register (IENCLR) Field Descriptions ........................................................ 76
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions ................... 78
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................. 79
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions .................. 80
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions .... 81
Fault Address Register (FLTADDRR) Field Descriptions ............................................................. 82
Fault Status Register (FLTSTAT) Field Descriptions .................................................................. 83
Fault Clear Register (FLTCLR) Field Descriptions..................................................................... 84
Device Clock Inputs ........................................................................................................ 86
System Clock Domains .................................................................................................... 86
Example PLL Frequencies ............................................................................................... 89
DDR2/mDDR Memory Controller MCLK Frequencies................................................................. 90
EMIFA Frequencies ........................................................................................................ 91
Peripherals .................................................................................................................. 93
System PLLC Output Clocks ............................................................................................. 97
PLL Controller 0 (PLLC0) Registers .................................................................................... 100
PLL Controller 1 (PLLC1) Registers .................................................................................... 101
PLLC0 Revision Identification Register (REVID) Field Descriptions ............................................... 101
PLLC1 Revision Identification Register (REVID) Field Descriptions ............................................... 102
Reset Type Status Register (RSTYPE) Field Descriptions ......................................................... 102
Reset Control Register (RSCTRL) Field Descriptions ............................................................... 103
PLLC0 Control Register (PLLCTL) Field Descriptions ............................................................... 104
PLLC1 Control Register (PLLCTL) Field Descriptions ............................................................... 105
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions ..................................................... 106
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions ..................................................... 107
PLL Multiplier Control Register (PLLM) Field Descriptions.......................................................... 108
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................................................ 108
PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................ 109
PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................ 109
PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................ 110
PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................ 110
PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................ 111
PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................ 111
PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions ............................................................ 112
SPRUH81C – April 2013 – Revised September 2016
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List of Tables
35
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7-21.
PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ............................................................ 112
7-22.
PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ............................................................ 113
7-23.
PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ............................................................ 113
7-24.
PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
9-1.
10-1.
10-2.
10-3.
10-4.
36
................................................
PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions ................................................
PLL Post-Divider Control Register (POSTDIV) Field Descriptions .................................................
PLL Controller Command Register (PLLCMD) Field Descriptions .................................................
PLL Controller Status Register (PLLSTAT) Field Descriptions .....................................................
PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC0 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC0 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC1 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions ....................................
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions ....................................
PSC0 Default Module Configuration ...................................................................................
PSC1 Default Module Configuration ...................................................................................
Module States .............................................................................................................
IcePick Emulation Commands ..........................................................................................
PSC Interrupt Events .....................................................................................................
Power and Sleep Controller 0 (PSC0) Registers .....................................................................
Power and Sleep Controller 1 (PSC1) Registers .....................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions ........................................................
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions .........................................
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ............................................
Power Error Pending Register (PERRPR) Field Descriptions ......................................................
Power Error Clear Register (PERRCR) Field Descriptions .........................................................
Power Domain Transition Command Register (PTCMD) Field Descriptions .....................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions .........................................
Power Domain 0 Status Register (PDSTAT0) Field Descriptions ..................................................
Power Domain 1 Status Register (PDSTAT1) Field Descriptions ..................................................
Power Domain 0 Control Register (PDCTL0) Field Descriptions ...................................................
Power Domain 1 Control Register (PDCTL1) Field Descriptions ...................................................
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ...........................................
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ...........................................
Module Status n Register (MDSTATn) Field Descriptions ..........................................................
PSC0 Module Control n Register (MDCTLn) Field Descriptions ...................................................
PSC1 Module Control n Register (MDCTLn) Field Descriptions ...................................................
Power Management Features ...........................................................................................
Master IDs .................................................................................................................
Default Master Priority ...................................................................................................
System Configuration Module 0 (SYSCFG0) Registers .............................................................
System Configuration Module 1 (SYSCFG1) Registers .............................................................
List of Tables
114
114
115
115
116
117
118
119
120
121
121
122
123
124
125
126
126
129
129
131
133
133
136
136
137
137
138
139
140
140
141
142
143
144
145
146
147
148
149
150
151
154
166
166
167
168
SPRUH81C – April 2013 – Revised September 2016
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10-5.
Revision Identification Register (REVID) Field Descriptions ........................................................ 168
10-6.
Device Identification Register 0 (DEVIDR0) Field Descriptions .................................................... 169
10-7.
Boot Configuration Register (BOOTCFG) Field Descriptions ....................................................... 169
10-8.
Chip Revision Identification Register (CHIPREVIDR) Field Descriptions ......................................... 170
10-9.
Kick 0 Register (KICK0R) Field Descriptions
171
10-10. Kick 1 Register (KICK1R) Field Descriptions
171
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
10-52.
10-53.
.........................................................................
.........................................................................
Host 1 Configuration Register (HOST1CFG) Field Descriptions ...................................................
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ...............................................
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................
Interrupt Enable Register (IENSET) Field Descriptions..............................................................
Interrupt Enable Clear Register (IENCLR) Field Descriptions ......................................................
End of Interrupt Register (EOI) Field Descriptions ...................................................................
Fault Address Register (FLTADDRR) Field Descriptions ...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Master Priority 0 Register (MSTPRI0) Field Descriptions ...........................................................
Master Priority 1 Register (MSTPRI1) Field Descriptions ...........................................................
Master Priority 2 Register (MSTPRI2) Field Descriptions ...........................................................
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ................................................
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ................................................
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ................................................
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ................................................
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ................................................
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ................................................
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ................................................
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ................................................
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ................................................
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ................................................
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions .............................................
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions .............................................
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions .............................................
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions .............................................
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions .............................................
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions .............................................
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions .............................................
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions .............................................
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions .............................................
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions .............................................
Suspend Source Register (SUSPSRC) Field Descriptions .........................................................
Chip Signal Register (CHIPSIG) Field Descriptions..................................................................
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ...................................................
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ....................................................
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ....................................................
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ....................................................
Chip Configuration 4 Register (CFGCHIP4) Field Descriptions ....................................................
VTP I/O Control Register (VTPIO_CTL) Field Descriptions .........................................................
DDR Slew Register (DDR_SLEW) Field Descriptions ...............................................................
Deep Sleep Register (DEEPSLEEP) Field Descriptions ............................................................
Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions................................................
Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions .................................................
SPRUH81C – April 2013 – Revised September 2016
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List of Tables
172
173
174
175
175
176
176
177
178
179
180
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
224
225
226
228
229
230
231
232
233
233
37
www.ti.com
10-54. Pullup/Pulldown Select Register (PUPD_SEL) Default Values ..................................................... 234
10-55. RXACTIVE Control Register (RXACTIVE) Field Descriptions ...................................................... 235
12-1.
DDR2/mDDR SDRAM Commands ..................................................................................... 243
12-2.
Truth Table for DDR2/mDDR SDRAM Commands
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
38
.................................................................
Addressable Memory Ranges ...........................................................................................
Configuration Register Fields for Address Mapping..................................................................
Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM .....................................
Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) ...................................................
DDR2/mDDR Memory Controller FIFO Description ..................................................................
Refresh Urgency Levels .................................................................................................
Configuration Bit Field for Partial Array Self-refresh .................................................................
Reset Sources.............................................................................................................
DDR2 SDRAM Configuration by MRS Command ....................................................................
DDR2 SDRAM Configuration by EMRS(1) Command ...............................................................
Mobile DDR SDRAM Configuration by MRS Command.............................................................
Mobile DDR SDRAM Configuration by EMRS(1) Command .......................................................
SDCR Configuration ......................................................................................................
DDR2 Memory Refresh Specification .................................................................................
SDRCR Configuration ....................................................................................................
SDTIMR1 Configuration..................................................................................................
SDTIMR2 Configuration..................................................................................................
DRPYC1R Configuration.................................................................................................
DDR2/mDDR Memory Controller Registers ...........................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................
SDRAM Configuration Register (SDCR) Field Descriptions ........................................................
SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
SDRAM Timing Register 1 (SDTIMR1) Field Descriptions ..........................................................
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ..........................................................
SDRAM Configuration Register 2 (SDCR2) Field Descriptions ....................................................
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ...............................................
Performance Counter 1 Register (PC1) Field Descriptions .........................................................
Performance Counter 2 Register (PC2) Field Descriptions .........................................................
Performance Counter Configuration Register (PCC) Field Descriptions ..........................................
Performance Counter Filter Configuration .............................................................................
Performance Counter Master Region Select Register (PCMRS) Field Descriptions ............................
Performance Counter Time Register (PCT) Field Description ......................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) Field Descriptions ......................................................................
Interrupt Masked Register (IMR) Field Descriptions .................................................................
Interrupt Mask Set Register (IMSR) Field Descriptions ..............................................................
Interrupt Mask Clear Register (IMCR) Field Descriptions ...........................................................
DDR PHY Control Register 1 (DRPYC1R) Field Descriptions ......................................................
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger...........................................
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ............................
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ...............................................
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers ...............................
ECAP Initialization for APWM Mode ...................................................................................
ECAP1 Initialization for Multichannel PWM Generation with Synchronization ...................................
List of Tables
244
251
252
253
255
257
260
261
262
264
264
264
265
270
271
271
272
272
273
274
274
275
276
279
280
281
282
283
284
284
285
286
287
288
288
289
289
290
291
292
306
308
310
312
314
316
SPRUH81C – April 2013 – Revised September 2016
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www.ti.com
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
...................................
ECAP3 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP4 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP1 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP2 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP3 Initialization for Multichannel PWM Generation with Phase Control .....................................
Control and Status Register Set ........................................................................................
Time-Stamp Counter Register (TSCTR) Field Descriptions ........................................................
Counter Phase Control Register (CTRPHS) Field Descriptions ....................................................
Capture 1 Register (CAP1) Field Descriptions........................................................................
Capture 2 Register (CAP2) Field Descriptions........................................................................
Capture 3 Register (CAP3) Field Descriptions........................................................................
Capture 4 Register (CAP4) Field Descriptions........................................................................
ECAP Control Register 1 (ECCTL1) Field Descriptions .............................................................
ECAP Control Register 2 (ECCTL2) Field Descriptions .............................................................
ECAP Interrupt Enable Register (ECEINT) Field Descriptions .....................................................
ECAP Interrupt Flag Register (ECFLG) Field Descriptions .........................................................
ECAP Interrupt Clear Register (ECCLR) Field Descriptions .......................................................
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions .....................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
ePWM Module Control and Status Registers Grouped by Submodule ............................................
Submodule Configuration Parameters .................................................................................
Time-Base Submodule Registers.......................................................................................
Key Time-Base Signals ..................................................................................................
Counter-Compare Submodule Registers .............................................................................
Counter-Compare Submodule Key Signals ...........................................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Submodule Possible Input Events ..................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode ...........................................................
Action-Qualifier Event Priority for Up-Count Mode ...................................................................
Action-Qualifier Event Priority for Down-Count Mode ................................................................
Behavior if CMPA/CMPB is Greater than the Period ................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
Dead-Band Generator Submodule Registers .........................................................................
Classical Dead-Band Operating Modes ...............................................................................
PWM-Chopper Submodule Registers ..................................................................................
Trip-Zone Submodule Registers ........................................................................................
Possible Actions On a Trip Event.......................................................................................
ECAP2 Initialization for Multichannel PWM Generation with Synchronization
SPRUH81C – April 2013 – Revised September 2016
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List of Tables
316
316
316
319
319
319
320
320
321
321
322
322
323
323
325
327
328
329
330
331
337
338
343
344
352
352
356
357
359
359
359
360
363
363
365
365
367
367
369
369
371
371
373
373
374
376
378
383
384
39
www.ti.com
386
14-31.
391
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
40
..................................................................................
Resolution for PWM and HRPWM......................................................................................
HRPWM Submodule Registers .........................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution .............................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ........................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
Submodule Registers ....................................................................................................
Time-Base Submodule Registers.......................................................................................
Time-Base Control Register (TBCTL) Field Descriptions ...........................................................
Time-Base Status Register (TBSTS) Field Descriptions ............................................................
Time-Base Phase Register (TBPHS) Field Descriptions ............................................................
Time-Base Counter Register (TBCNT) Field Descriptions ..........................................................
Time-Base Period Register (TBPRD) Field Descriptions ............................................................
Counter-Compare Submodule Registers ..............................................................................
Counter-Compare Control Register (CMPCTL) Field Descriptions ................................................
Counter-Compare A Register (CMPA) Field Descriptions...........................................................
Counter-Compare B Register (CMPB) Field Descriptions...........................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .......................................
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .......................................
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions ..........................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions .........................
Dead-Band Generator Submodule Registers .........................................................................
Dead-Band Generator Control Register (DBCTL) Field Descriptions..............................................
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions ...............................
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ...............................
PWM-Chopper Control Register (PCCTL) Bit Descriptions .........................................................
Trip-Zone Submodule Registers ........................................................................................
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ...............................................
Trip-Zone Control Register (TZCTL) Field Descriptions .............................................................
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions .................................................
Trip-Zone Flag Register (TZFLG) Field Descriptions ................................................................
Trip-Zone Clear Register (TZCLR) Field Descriptions ..............................................................
Trip-Zone Force Register (TZFRC) Field Descriptions ..............................................................
Event-Trigger Submodule Registers ...................................................................................
14-30. Event-Trigger Submodule Registers
List of Tables
392
393
394
401
401
401
404
404
407
407
410
410
411
416
416
417
420
420
421
421
422
423
424
424
425
425
426
427
428
428
429
430
431
432
432
433
434
434
435
436
436
437
437
438
439
439
440
SPRUH81C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
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.....................................................
Event-Trigger Prescale Register (ETPS) Field Descriptions .......................................................
Event-Trigger Flag Register (ETFLG) Field Descriptions ...........................................................
Event-Trigger Clear Register (ETCLR) Field Descriptions ..........................................................
Event-Trigger Force Register (ETFRC) Field Descriptions .........................................................
High-Resolution PWM Submodule Registers .........................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions ....................................
Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions ...................................
HRPWM Configuration Register (HRCNFG) Field Descriptions ....................................................
EDMA3 Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ....................................................................................
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .....................................
Expected Number of Transfers for Non-Null Transfer ...............................................................
EDMA3 DMA Channel to PaRAM Mapping ...........................................................................
Shadow Region Registers ...............................................................................................
Chain Event Triggers .....................................................................................................
EDMA3 Transfer Completion Interrupts ...............................................................................
EDMA3 Error Interrupts ..................................................................................................
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping .................................................
Number of Interrupts .....................................................................................................
EDMA3 Transfer Controller Configurations ...........................................................................
Read/Write Command Optimization Rules ............................................................................
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries.....................................
Channel Options Parameters (OPT) Field Descriptions .............................................................
Channel Source Address Parameter (SRC) Field Descriptions ....................................................
A Count/B Count Parameter (A_B_CNT) Field Descriptions .......................................................
Channel Destination Address Parameter (DST) Field Descriptions ...............................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .........................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ........................
C Count Parameter (CCNT) Field Descriptions.......................................................................
EDMA3 Channel Controller (EDMA3CC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3CC Configuration Register (CCCFG) Field Descriptions ...................................................
QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions .............................................
DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ....................................
Bits in DMAQNUMn ......................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ....................................
Event Missed Register (EMR) Field Descriptions ....................................................................
Event Missed Clear Register (EMCR) Field Descriptions ...........................................................
QDMA Event Missed Register (QEMR) Field Descriptions .........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................
EDMA3CC Error Register (CCERR) Field Descriptions .............................................................
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................
Error Evaluate Register (EEVAL) Field Descriptions.................................................................
DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions ..............................
QDMA Region Access Enable for Region m (QRAEm) Field Descriptions .......................................
Event Queue Entry Registers (QxEy) Field Descriptions ............................................................
Queue n Status Register (QSTATn) Field Descriptions .............................................................
14-79. Event-Trigger Selection Register (ETSEL) Field Descriptions
440
14-80.
441
14-81.
14-82.
14-83.
14-84.
14-85.
14-86.
14-87.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
SPRUH81C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
442
442
443
443
444
444
445
459
462
463
471
473
475
478
478
478
479
480
487
493
512
513
515
515
516
516
517
518
518
519
522
523
524
525
525
526
527
528
529
530
531
532
533
534
535
536
537
41
www.ti.com
15-41. Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................... 538
15-42. EDMA3CC Status Register (CCSTAT) Field Descriptions .......................................................... 539
15-43. Event Register (ER) Field Descriptions ................................................................................ 541
15-44. Event Clear Register (ECR) Field Descriptions ....................................................................... 542
15-45. Event Set Register (ESR) Field Descriptions ......................................................................... 543
15-46. Chained Event Register (CER) Field Descriptions ................................................................... 544
15-47. Event Enable Register (EER) Field Descriptions ..................................................................... 545
15-48. Event Enable Clear Register (EECR) Field Descriptions ............................................................ 546
.............................................................
Secondary Event Register (SER) Field Descriptions ................................................................
Secondary Event Clear Register (SECR) Field Descriptions .......................................................
Interrupt Enable Register (IER) Field Descriptions ...................................................................
Interrupt Enable Clear Register (IECR) Field Descriptions..........................................................
Interrupt Enable Set Register (IESR) Field Descriptions ............................................................
Interrupt Pending Register (IPR) Field Descriptions .................................................................
Interrupt Clear Register (ICR) Field Descriptions.....................................................................
Interrupt Evaluate Register (IEVAL) Field Descriptions .............................................................
QDMA Event Register (QER) Field Descriptions .....................................................................
QDMA Event Enable Register (QEER) Field Descriptions ..........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions .................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ...................................................
QDMA Secondary Event Register (QSER) Field Descriptions .....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................
EDMA3 Transfer Controller (EDMA3TC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................
Error Status Register (ERRSTAT) Field Descriptions ...............................................................
Error Enable Register (ERREN) Field Descriptions ..................................................................
Error Clear Register (ERRCLR) Field Descriptions ..................................................................
Error Details Register (ERRDET) Field Descriptions ................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions.................................................
Read Command Rate Register (RDRATE) Field Descriptions .....................................................
Source Active Options Register (SAOPT) Field Descriptions.......................................................
Source Active Source Address Register (SASRC) Field Descriptions ............................................
Source Active Count Register (SACNT) Field Descriptions .........................................................
Source Active Destination Address Register (SADST) Field Descriptions ........................................
Source Active B-Index Register (SABIDX) Field Descriptions ......................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................
Source Active Count Reload Register (SACNTRLD) Field Descriptions ..........................................
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions .....................
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions .................
Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions .................................
Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions .............
Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions ........
Destination FIFO Options Register n (DFOPTn) Field Descriptions ...............................................
Destination FIFO Source Address Register n (DFSRCn) Field Descriptions .....................................
Destination FIFO Count Register n (DFCNTn) Field Descriptions .................................................
Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions ................................
15-49. Event Enable Set Register (EESR) Field Descriptions
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
15-72.
15-73.
15-74.
15-75.
15-76.
15-77.
15-78.
15-79.
15-80.
15-81.
15-82.
15-83.
15-84.
15-85.
15-86.
15-87.
15-88.
15-89.
42
List of Tables
546
547
547
548
549
549
550
551
552
553
554
555
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
569
570
570
571
572
572
573
573
574
574
575
576
576
577
SPRUH81C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
15-90. Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions .............................................. 577
15-91. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions .................... 578
15-92. Debug List ................................................................................................................. 579
16-1.
EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories........................................ 584
16-2.
EMIFA Pins Specific to SDRAM ........................................................................................ 585
16-3.
EMIFA Pins Specific to Asynchronous Memory ...................................................................... 585
16-4.
EMIFA SDRAM Commands ............................................................................................. 586
16-5.
Truth Table for SDRAM Commands ................................................................................... 586
16-6.
16-bit EMIFA Address Pin Connections ............................................................................... 588
16-7.
Description of the SDRAM Configuration Register (SDCR) ......................................................... 589
16-8.
Description of the SDRAM Refresh Control Register (SDRCR) .................................................... 589
16-9.
Description of the SDRAM Timing Register (SDTIMR) .............................................................. 590
16-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ...................................... 590
16-11. SDRAM LOAD MODE REGISTER Command ........................................................................ 591
.................................................................................................
.................................................
Normal Mode vs. Select Strobe Mode .................................................................................
Description of the Asynchronous m Configuration Register (CEnCFG) ...........................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..................................
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ............................................
Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) ..........................................
Asynchronous Read Operation in Normal Mode .....................................................................
Asynchronous Write Operation in Normal Mode .....................................................................
Asynchronous Read Operation in Select Strobe Mode ..............................................................
Asynchronous Write Operation in Select Strobe Mode ..............................................................
Description of the NAND Flash Control Register (NANDFCR) .....................................................
Reset Sources.............................................................................................................
Interrupt Monitor and Control Bit Fields ................................................................................
SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface ................................................
SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface ..................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface ..........................................
EMIFA Input Timing Requirements .....................................................................................
ASRAM Output Timing Characteristics ................................................................................
ASRAM Input Timing Requirement for a Read .......................................................................
ASRAM Input Timing Requirements for a Write .....................................................................
ASRAM Timing Requirements With PCB Delays.....................................................................
EMIFA Timing Requirements for TC5516100FT-12 Example .....................................................
ASRAM Timing Requirements for TC5516100FT-12 Example .....................................................
Measured PCB Delays for TC5516100FT-12 Example .............................................................
Configuring CE3CFG for TC5516100FT-12 Example ...............................................................
Recommended Margins..................................................................................................
EMIFA Read Timing Requirements ....................................................................................
NAND Flash Read Timing Requirements .............................................................................
NAND Flash Write Timing Requirements .............................................................................
EMIFA Timing Requirements for HY27UA081G1M Example .......................................................
NAND Flash Timing Requirements for HY27UA081G1M Example ................................................
Configuring CE2CFG for HY27UA081G1M Example ................................................................
16-12. Refresh Urgency Levels
592
16-13. Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM
597
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
SPRUH81C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
598
600
601
603
603
603
605
607
609
611
617
619
624
626
627
627
628
629
629
629
630
632
635
635
635
637
637
638
638
640
643
643
645
43
www.ti.com
16-47. Configuring NANDFCR for HY27UA081G1M Example.............................................................. 645
16-48. External Memory Interface (EMIFA) Registers
.......................................................................
646
16-49. Module ID Register (MIDR) Field Descriptions ....................................................................... 647
16-50. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ................................. 648
16-51. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................ 649
651
16-53.
652
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
16-70.
16-71.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
44
...................................................
Asynchronous n Configuration Register (CEnCFG) Field Descriptions ...........................................
SDRAM Timing Register (SDTIMR) Field Descriptions..............................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ......................................
EMIFA Interrupt Raw Register (INTRAW) Field Descriptions.......................................................
EMIFA Interrupt Mask Register (INTMSK) Field Descriptions ......................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ............................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions .........................................
NAND Flash Control Register (NANDFCR) Field Descriptions .....................................................
NAND Flash Status Register (NANDFSR) Field Descriptions ......................................................
NAND Flash n ECC Register (NANDFnECC) Field Descriptions ..................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ............................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions ........................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ......................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ......................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions ..........................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions ..........................
GPIO Register Bits and Banks Associated With GPIO Signals ....................................................
GPIO Registers ...........................................................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ..........................................
GPIO Direction Register (DIRn) Field Descriptions ..................................................................
GPIO Output Data Register (OUT_DATAn) Field Descriptions ....................................................
GPIO Set Data Register (SET_DATAn) Field Descriptions .........................................................
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ......................................................
GPIO Input Data Register (IN_DATAn) Field Descriptions..........................................................
GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions ......................
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions .............................
GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions .....................
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions ............................
GPIO Interrupt Status Register (INTSTATn) Field Descriptions ....................................................
HPI Pins ....................................................................................................................
Value on Optional Pins when Configured as General-Purpose I/O ................................................
Options for Connecting Host and HPI Data Strobe Pins ............................................................
Access Types Selectable With the UHPI_HCNTL Signals ..........................................................
Cycle Types Selectable With the UHPI_HCNTL and UHPI_HR/W Signals.......................................
HPI Registers..............................................................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ..........................
GPIO Enable Register (GPIO_EN) Field Descriptions...............................................................
GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions ........................................................
16-52. SDRAM Refresh Control Register (SDRCR) Field Descriptions
List of Tables
654
655
656
657
658
659
660
662
663
664
665
665
666
666
667
667
668
668
672
679
680
681
683
685
687
689
691
693
695
697
699
701
706
707
711
712
712
726
727
727
728
729
SPRUH81C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
18-11. GPIO Data 1 Register (GPIO_DAT1) Field Descriptions ............................................................ 729
18-12. GPIO Direction 2 Register (GPIO_DIR2) Field Descriptions ........................................................ 730
18-13. GPIO Data 2 Register (GPIO_DAT2) Field Descriptions ............................................................ 731
18-14. Host Port Interface Control Register (HPIC) Field Descriptions .................................................... 733
18-15. Host Port Interface Write Address Register (HPIAW) Field Descriptions ......................................... 734
18-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions .......................................... 734
19-1.
Operating Modes of the I2C Peripheral ................................................................................ 744
19-2.
Ways to Generate a NACK Bit .......................................................................................... 745
19-3.
Descriptions of the I2C Interrupt Events ............................................................................... 749
19-4.
Inter-Integrated Circuit (I2C) Registers
19-5.
I2C Own Address Register (ICOAR) Field Descriptions ............................................................. 751
19-6.
I2C Interrupt Mask Register (ICIMR) Field Descriptions............................................................. 752
19-7.
I2C Interrupt Status Register (ICSTR) Field Descriptions ........................................................... 753
19-8.
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
................................................................................
...............................................
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ..............................................
I2C Data Count Register (ICCNT) Field Descriptions................................................................
I2C Data Receive Register (ICDRR) Field Descriptions .............................................................
I2C Slave Address Register (ICSAR) Field Descriptions ............................................................
I2C Data Transmit Register (ICDXR) Field Descriptions ............................................................
I2C Mode Register (ICMDR) Field Descriptions ......................................................................
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ..................................
How the MST and FDF Bits Affect the Role of TRX Bit .............................................................
I2C Interrupt Vector Register (ICIVR) Field Descriptions ............................................................
I2C Extended Mode Register (ICEMDR) Field Descriptions ........................................................
I2C Prescaler Register (ICPSC) Field Descriptions ..................................................................
I2C Revision Identification Register 1 (REVID1) Field Descriptions ...............................................
I2C Revision Identification Register 2 (REVID2) Field Descriptions ...............................................
I2C DMA Control Register (ICDMAC) Field Descriptions ...........................................................
I2C Pin Function Register (ICPFUNC) Field Descriptions ..........................................................
I2C Pin Direction Register (ICPDIR) Field Descriptions .............................................................
I2C Pin Data In Register (ICPDIN) Field Descriptions ...............................................................
I2C Pin Data Out Register (ICPDOUT) Field Descriptions ..........................................................
I2C Pin Data Set Register (ICPDSET) Field Descriptions...........................................................
I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ........................................................
Biphase-Mark Encoder ...................................................................................................
Preamble Codes ..........................................................................................................
Channel Status and User Data for Each DIT Block .................................................................
Transmit Bitstream Data Alignment ....................................................................................
Receive Bitstream Data Alignment .....................................................................................
EDMA Events - McASP ..................................................................................................
McASP Registers Accessed by CPU/EDMA Through Peripheral Configuration Port ...........................
McASP Registers Accessed by CPU/EDMA Through DMA Port ..................................................
McASP AFIFO Registers Accessed Through Peripheral Configuration Port .....................................
Revision Identification Register (REV) Field Descriptions ...........................................................
Pin Function Register (PFUNC) Field Descriptions ..................................................................
Pin Direction Register (PDIR) Field Descriptions .....................................................................
Pin Data Output Register (PDOUT) Field Descriptions ..............................................................
Pin Data Input Register (PDIN) Field Descriptions ...................................................................
Pin Data Set Register (PDSET) Field Descriptions ..................................................................
SPRUH81C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
750
756
756
757
758
759
760
761
763
763
765
766
767
768
768
769
770
771
772
773
774
775
784
785
811
819
821
831
832
835
835
836
838
840
842
844
846
45
www.ti.com
20-16. Pin Data Clear Register (PDCLR) Field Descriptions ................................................................ 848
20-17. Global Control Register (GBLCTL) Field Descriptions ............................................................... 849
20-18. Audio Mute Control Register (AMUTE) Field Descriptions .......................................................... 851
20-19. Digital Loopback Control Register (DLBCTL) Field Descriptions ................................................... 853
20-20. Digital Mode Control Register (DITCTL) Field Descriptions......................................................... 854
20-21. Receiver Global Control Register (RGBLCTL) Field Descriptions ................................................. 855
20-22. Receive Format Unit Bit Mask Register (RMASK) Field Descriptions ............................................. 856
20-23. Receive Bit Stream Format Register (RFMT) Field Descriptions
..................................................
857
20-24. Receive Frame Sync Control Register (AFSRCTL) Field Descriptions............................................ 859
20-25. Receive Clock Control Register (ACLKRCTL) Field Descriptions .................................................. 860
20-26. Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ............................ 861
20-27. Receive TDM Time Slot Register (RTDM) Field Descriptions ...................................................... 862
20-28. Receiver Interrupt Control Register (RINTCTL) Field Descriptions ................................................ 863
20-29. Receiver Status Register (RSTAT) Field Descriptions............................................................... 864
20-30. Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions .......................................... 865
866
20-32.
867
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
46
..........................................
Receiver DMA Event Control Register (REVTCTL) Field Descriptions............................................
Transmitter Global Control Register (XGBLCTL) Field Descriptions ..............................................
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ............................................
Transmit Bit Stream Format Register (XFMT) Field Descriptions ..................................................
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions ...........................................
Transmit Clock Control Register (ACLKXCTL) Field Descriptions .................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions ...........................
Transmit TDM Time Slot Register (XTDM) Field Descriptions .....................................................
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions .............................................
Transmitter Status Register (XSTAT) Field Descriptions ............................................................
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions ..........................................
Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ..........................................
Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions .........................................
Serializer Control Registers (SRCTLn) Field Descriptions ..........................................................
AFIFO Revision Identification Register (AFIFOREV) Field Descriptions ..........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ......................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .......................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions ......................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions .......................................................
McBSP Interface Signals ................................................................................................
Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits ...............
Receive Clock Selection .................................................................................................
Transmit Clock Selection ................................................................................................
Receive Frame Synchronization Selection ............................................................................
Transmit Frame Synchronization Selection ...........................................................................
RCR/XCR Fields Controlling Elements per Frame and Bits per Element .........................................
Receive/Transmit Frame Length Configuration .......................................................................
Receive/Transmit Element Length Configuration .....................................................................
Effect of RJUST Bit Values With 12-Bit Example Data ABCh ......................................................
Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh ..................................................
Justification of Expanded Data in DRR ................................................................................
Receive Channel Assignment and Control When Two Receive Partitions are Used ............................
Transmit Channel Assignment and Control When Two Transmit Partitions are Used ..........................
20-31. Receive Clock Check Control Register (RCLKCHK) Field Descriptions
List of Tables
868
869
870
872
873
874
875
876
877
878
879
880
881
885
886
887
888
889
893
897
900
901
902
903
904
904
905
907
907
923
926
926
SPRUH81C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
21-15. Receive Channel Assignment and Control When Eight Receive Partitions are Used ........................... 928
21-16. Transmit Channel Assignment and Control When Eight Transmit Partitions are Used ......................... 928
21-17. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits ......................................... 929
21-18. Reset State of McBSP Pins ............................................................................................. 932
21-19. Receiver Clock and Frame Configurations ............................................................................ 933
21-20. Transmitter Clock and Frame Configurations ......................................................................... 933
21-21. McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR
.................................
939
21-22. McBSP Registers ......................................................................................................... 940
....................................................................
Data Transmit Register (DXR) Field Descriptions ....................................................................
Serial Port Control Register (SPCR) Field Descriptions .............................................................
Receive Control Register (RCR) Field Descriptions .................................................................
Transmit Control Register (XCR) Field Descriptions ................................................................
Sample Rate Generator Register (SRGR) Field Descriptions ......................................................
Multichannel Control Register (MCR) Field Descriptions ............................................................
Enhanced Receive Channel Enable Register n (RCEREn) Field Descriptions ..................................
Use of the Receive Channel Enable Registers .......................................................................
Enhanced Transmit Channel Enable Register n (XCEREn) Field Descriptions ..................................
Use of the Transmit Channel Enable Registers ......................................................................
Pin Control Register (PCR) Field Descriptions .......................................................................
BFIFO Revision Identification Register (BFIFOREV) Field Descriptions ..........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ......................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .......................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions ......................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions .......................................................
Real-Time Clock Signals .................................................................................................
Real-Time Clock (RTC) Registers ......................................................................................
Second Register (SECOND) Field Descriptions ......................................................................
Minute Register (MINUTE) Field Descriptions ........................................................................
Hour Register (HOUR) Field Descriptions .............................................................................
Day Register (DAY) Field Descriptions ................................................................................
Month Register (MONTH) Field Descriptions .........................................................................
Year Register (YEAR) Field Descriptions .............................................................................
Day of the Week Register (DOTW) Field Descriptions ..............................................................
Alarm Second Register (ALARMSECOND) Field Descriptions .....................................................
Alarm Minute Register (ALARMMINUTE) Field Descriptions .......................................................
Alarm Hour Register (ALARMHOUR) Field Descriptions............................................................
Alarm Day Register (ALARMDAY) Field Descriptions ...............................................................
Alarm Month Register (ALARMMONTH) Field Descriptions ........................................................
Alarm Years Register (ALARMYEARS) Field Descriptions .........................................................
Control Register (CTRL) Field Descriptions ...........................................................................
Status Register (STATUS) Field Descriptions ........................................................................
Interrupt Register (INTERRUPT) Field Descriptions .................................................................
Compensations Register (COMPLSB) Field Descriptions...........................................................
Compensations Register (COMPMSB) Field Descriptions ..........................................................
Oscillator Register (OSC) Field Descriptions .........................................................................
Scratch Registers (SCRATCHn) Field Descriptions .................................................................
Kick Registers (KICKnR) Field Descriptions ..........................................................................
SPI Pins ....................................................................................................................
21-23. Data Receive Register (DRR) Field Descriptions
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
23-1.
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List of Tables
941
941
942
944
946
948
949
953
954
955
956
957
959
960
961
962
963
966
972
973
973
974
975
975
976
976
977
977
978
979
980
980
981
982
983
984
985
986
987
987
991
47
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23-2.
SPI Registers .............................................................................................................. 992
23-3.
SPI Register Settings Defining Master Modes ........................................................................ 993
23-4.
Allowed SPI Register Settings in Master Modes
23-5.
SPI Register Settings Defining Slave Modes
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
48
..................................................................... 993
......................................................................... 995
Allowed SPI Register Settings in Slave Modes ....................................................................... 995
Clocking Modes.......................................................................................................... 1004
SPI Registers ............................................................................................................ 1017
SPI Global Control Register 0 (SPIGCR0) Field Descriptions .................................................... 1017
SPI Global Control Register 1 (SPIGCR1) Field Descriptions .................................................... 1018
SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................ 1020
SPI Interrupt Level Register (SPILVL) Field Descriptions ......................................................... 1022
SPI Flag Register (SPIFLG) Field Descriptions ..................................................................... 1023
SPI Pin Control Register 0 (SPIPC0) Field Descriptions........................................................... 1025
SPI Pin Control Register 1 (SPIPC1) Field Descriptions........................................................... 1026
SPI Pin Control Register 2 (SPIPC2) Field Descriptions........................................................... 1027
SPI Pin Control Register 3 (SPIPC3) Field Descriptions........................................................... 1028
SPI Pin Control Register 4 (SPIPC4) Field Descriptions........................................................... 1029
SPI Pin Control Register 5 (SPIPC5) Field Descriptions........................................................... 1030
SPI Data Register 0 (SPIDAT0) Field Descriptions................................................................. 1031
SPI Data Register 1 (SPIDAT1) Field Descriptions................................................................. 1032
SPI Buffer Register (SPIBUF) Field Descriptions ................................................................... 1033
SPI Emulation Register (SPIEMU) Field Descriptions.............................................................. 1035
SPI Delay Register (SPIDELAY) Field Descriptions ................................................................ 1036
SPI Default Chip Select Register (SPIDEF) Field Descriptions ................................................... 1039
SPI Data Format Register (SPIFMTn) Field Descriptions ......................................................... 1040
SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions ................................................... 1042
Timer Clock Source Selection ......................................................................................... 1046
64-Bit Timer Configurations ............................................................................................ 1048
32-Bit Timer Chained Mode Configurations ......................................................................... 1051
32-Bit Timer Unchained Mode Configurations....................................................................... 1054
Counter and Period Registers Used in GP Timer Modes .......................................................... 1056
TSTAT Parameters in Pulse and Clock Modes ..................................................................... 1060
Timer Emulation Modes Selection .................................................................................... 1062
Timer Registers .......................................................................................................... 1062
Revision ID Register (REVID) Field Descriptions ................................................................... 1064
Emulation Management Register (EMUMGT) Field Descriptions ................................................ 1064
GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions ............................... 1065
GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions ......................................... 1066
Timer Counter Register 12 (TIM12) Field Descriptions ............................................................ 1067
Timer Counter Register 34 (TIM34) Field Descriptions ............................................................ 1067
Timer Period Register (PRD12) Field Descriptions ................................................................. 1068
Timer Period Register (PRD34) Field Descriptions ................................................................. 1068
Timer Control Register (TCR) Field Descriptions ................................................................... 1069
Timer Global Control Register (TGCR) Field Descriptions ........................................................ 1071
Watchdog Timer Control Register (WDTCR) Field Descriptions .................................................. 1072
Timer Reload Register 12 (REL12) Field Descriptions ............................................................. 1073
Timer Reload Register 34 (REL34) Field Descriptions ............................................................. 1073
Timer Capture Register 12 (CAP12) Field Descriptions ........................................................... 1074
Timer Capture Register 34 (CAP34) Field Descriptions ........................................................... 1074
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24-24. Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ................................ 1075
24-25. Timer Compare Register (CMPn) Field Descriptions ............................................................... 1076
25-1.
Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode ........................ 1081
25-2.
Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode ........................ 1081
25-3.
UART Signal Descriptions
1082
25-4.
Character Time for Word Lengths
1085
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
.............................................................................................
....................................................................................
UART Interrupt Requests Descriptions ...............................................................................
UART Registers .........................................................................................................
Receiver Buffer Register (RBR) Field Descriptions .................................................................
Transmitter Holding Register (THR) Field Descriptions ............................................................
Interrupt Enable Register (IER) Field Descriptions .................................................................
Interrupt Identification Register (IIR) Field Descriptions............................................................
Interrupt Identification and Interrupt Clearing Information .........................................................
FIFO Control Register (FCR) Field Descriptions ....................................................................
Line Control Register (LCR) Field Descriptions .....................................................................
Relationship Between ST, EPS, and PEN Bits in LCR.............................................................
Number of STOP Bits Generated .....................................................................................
Modem Control Register (MCR) Field Descriptions ................................................................
Line Status Register (LSR) Field Descriptions ......................................................................
Modem Status Register (MSR) Field Descriptions..................................................................
Scratch Pad Register (MSR) Field Descriptions ....................................................................
Divisor LSB Latch (DLL) Field Descriptions .........................................................................
Divisor MSB Latch (DLH) Field Descriptions ........................................................................
Revision Identification Register 1 (REVID1) Field Descriptions ...................................................
Revision Identification Register 2 (REVID2) Field Descriptions ...................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions .........................
Mode Definition Register (MDR) Field Descriptions ................................................................
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List of Tables
1089
1091
1092
1093
1094
1095
1096
1097
1098
1099
1099
1100
1101
1104
1105
1106
1106
1107
1107
1108
1109
49
Preface
SPRUH81C – April 2013 – Revised September 2016
Read This First
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components
• DSP subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box provided at www.ti.com.
The current documentation that describes related peripherals and other technical collateral, is available in
the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
Code Composer Studio is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc..
50
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Chapter 1
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Overview
Topic
1.1
1.2
...........................................................................................................................
Page
Introduction ....................................................................................................... 52
DSP Subsystem ................................................................................................. 52
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Overview
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Introduction
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Introduction
The C6742 DSP efficiently handles communication and audio processing tasks. The C6742 DSP consists
of the following primary components:
• A set of I/O peripherals
• A powerful DMA subsystem and SDRAM EMIF interface
Block Diagram
A block diagram for the 6742 DSP is shown in Figure 1-1.
1.2
DSP Subsystem
The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks of
internal memory (L1P, L1D, and L2). The DSP Subsystem chapter describes the DSPSS components.
Figure 1-1. TMS320C6742 DSP Block Diagram
JTAG Interface
DSP Subsystem
System Control
Input
Clock(s)
C674x™
DSP CPU
PLL/Clock
Generator
w/OSC
Memory Protection
GeneralPurpose
Timer (x2)
Power/Sleep
Controller
AET
32KB
L1 Pgm
32KB
L1 RAM
64K L2 RAM
RTC/
32-kHz
OSC
Pin
Multiplexing
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
EDMA3
(x2)
McASP
w/FIFO
Control Timers
eHRPWM
(x2)
eCAP
(x3)
Serial Interfaces
McBSP
Connectivity
HPI
I2C
SPI
UART
External Memory Interfaces
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/mDDR
Memory
Controller
Note: Not all peripherals are available at the same time due to multiplexing.
DMA Subsystem
The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more
information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter.
52
Overview
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Chapter 2
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DSP Subsystem
Topic
2.1
2.2
2.3
2.4
...........................................................................................................................
Introduction .......................................................................................................
TMS320C674x Megamodule .................................................................................
Memory Map ......................................................................................................
Advanced Event Triggering (AET) ........................................................................
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Page
54
55
59
59
53
Introduction
2.1
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Introduction
The DSP subsystem (Figure 2-1) includes TI’s standard TMS320C674x megamodule and several blocks
of internal memory (L1P, L1D, and L2). This chapter provides an overview of the DSP subsystem and the
following considerations associated with it:
• Memory mapping
• Interrupts
• Power management
For more information on the TMS320C674x megamodule, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5), the TMS320C674x DSP CPU and Instruction Set Reference Guide
(SPRUFE8), and the TMS320C674x DSP Cache User’s Guide (SPRUG82).
Figure 2-1. TMS320C674x Megamodule Block Diagram
32K bytes
L1P RAM/
cache
1M bytes
L2 ROM
64K bytes
L2 RAM
256
128
256
256
Cache control
Memory protect
Bandwidth Mgmt
Cache control
Memory protect
Bandwidth Mgmt
L1P
256
256
256
256
Instruction fetch
Power down
Interrupt
Controller
C674x
Fixed/floating point CPU
Register
file A
Register
file B
64
64
Bandwidth Mgmt
Memory protect
Cache control
8x32
54
DSP Subsystem
IDMA
256
Port
EMC
L1D
MDMA Port
64
32K bytes
L1D RAM/
cache
L2
64
32
Configuration
peripherals
bus
SDMA Port
64
64
High performance
switch fabric
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2.2
TMS320C674x Megamodule
The C674x megamodule (Figure 2-1) consists of the following components:
• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)
For more information about each of these controllers, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5).
2.2.1 Internal Memory Controllers
The C674x megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory (L1) is split into separate program memory (L1P memory) and data
memory (L1D memory). L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also
be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory
locations. The internal direct memory access controller (IDMA) manages DMA among the L1P, L1D, and
L2 memories.
2.2.2 Internal Peripherals
The C674x megamodule includes the following internal peripherals:
• DSP interrupt controller (INTC)
• DSP power-down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA) controller
This section briefly describes the INTC, PDC, BWM, and IDMA controller. For more information on these
internal peripherals, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
2.2.2.1
Interrupt Controller (INTC)
The C674x megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps DSP device events to 12 CPU interrupts. All DSP device events are listed in Table 2-1. The INTC is
fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
Table 2-1. DSP Interrupt Map
Event
Interrupt Name
Source
0
EVT0
C674x Interrupt Control 0
1
EVT1
C674x Interrupt Control 1
2
EVT2
C674x Interrupt Control 2
3
EVT3
C674x Interrupt Control 3
4
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
5
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
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Table 2-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
6
—
Reserved
7
EHRPWM0
HiResTimer/PWM0 Interrupt
8
EDMA3_0_CC0_INT1
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
9
EMU-DTDMA
C674x-ECM
10
EHRPWM0TZ
HiResTimer/PWM0 Trip Zone Interrupt
11
EMU-RTDXRX
C674x-RTDX
12
EMU-RTDXTX
C674x-RTDX
13
IDMAINT0
C674x-EMC
14
IDMAINT1
C674x-EMC
—
Reserved
EHRPWM1
HiResTimer/PWM1 Interrupt
—
Reserved
EHRPWM1TZ
HiResTimer/PWM1 Trip Zone Interrupt
—
Reserved
34
UHPI_DSPINT
HPI DSP Interrupt
35
—
Reserved
36
IIC0_INT
I2C0 Interrupt
37
—
Reserved
38
UART0_INT
UART0 Interrupt
39
—
Reserved
40
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
41
GPIO_B1INT
GPIO Bank 1 Interrupt
42
—
Reserved
43
SPI1_INT
SPI1 Interrupt
44
—
Reserved
45
ECAP0
ECAP0 Interrupt
46
—
Reserved
47
ECAP1
ECAP1 Interrupt
48
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
49
GPIO_B2INT
GPIO Bank 2 Interrupt
50
—
Reserved
51
ECAP2
ECAP2 Interrupt
52
GPIO_B3INT
GPIO Bank 3 Interrupt
53
—
Reserved
54
GPIO_B4INT
GPIO Bank 4 Interrupt
55
EMIFA_INT
EMIFA Interrupt
56
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrrupt
57
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrrupt
58
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrrupt
59
GPIO_B5INT
GPIO Bank 5 Interrupt
60
DDR2_MEMERR
DDR2 Memory Error Interrupt
61
MCASP0_INT
McASP0 Combined RX/TX Interrupt
62
GPIO_B6INT
GPIO Bank 6 Interrupt
63
RTC_IRQS
RTC Combined Interrupt
64
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
65
GPIO_B0INT
GPIO Bank 0 Interrupt
66
—
Reserved
15-17
18
19-22
23
24-33
56
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Table 2-1. DSP Interrupt Map (continued)
Event
67
68-69
Interrupt Name
Source
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
—
Reserved
70
PSC0_ALLINT
PSC0
71
PSC1_ALLINT
PSC1
72
GPIO_B7INT
GPIO Bank 7 Interrupt
73
—
Reserved
74
PROTERR
SYSCFG Protection Shared Interrupt
75
GPIO_B8INT
GPIO Bank 8 Interrupt
76-88
—
Reserved
89
MCBSP1_RINT
McBSP1 Receive Interrupt
90
MCBSP1_XINT
McBSP1 Transmit Interrupt
91
EDMA3_1_CC0_INT1
EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
92
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrrupt
93
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrrupt
94-95
—
Reserved
96
INTERR
C674x-Interrupt Control
97
EMC_IDMAERR
C674x-EMC
—
Reserved
PMC_ED
C674x-PMC
—
Reserved
116
UMC_ED1
C674x-UMC
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
C674x-SYS
120
PMC_CMPA
C674x-PMC
121
PMC_CMPA
C674x-PMC
122
DMC_CMPA
C674x-DMC
123
DMC_CMPA
C674x-DMC
124
UMC_CMPA
C674x-UMC
125
UMC_CMPA
C674x-UMC
126
EMC_CMPA
C674x-EMC
127
EMC_BUSERR
C674x-EMC
98-112
113
114-115
2.2.2.1.1 Interrupt Controller Registers
For more information on the DSP interrupt controller (INTC) registers, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.1.2 NMI Interrupt
In addition to the interrupts listed in Table 2-1, the DSP also supports a special interrupt that behaves
more like an exception, non-maskable interrupt (NMI). The NMI interrupt is controlled by two registers in
the System Configuration Module, the chip signal register (CHIPSIG) and the chip signal clear register
(CHIPSIG_CLR).
The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. The NMI interrupt is cleared
by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. For more information on CHIPSIG and
CHIPSIG_CLR, see the System Configuration (SYSCFG) Module chapter.
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TMS320C674x Megamodule
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Power-Down Controller (PDC)
The C674x megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C674x megamodule and internal memories of the DSP subsystem:
• C674x CPU
• Level 1 program memory controller (PMC)
• Level 1 data memory controller (DMC)
• Level 2 unified memory controller (UMC)
• Extended memory controller (EMC)
• Internal direct memory access (IDMA) controller
• L1P memory
• L1D memory
• L2 memory
This device supports the static power-down feature from the C674x megamodule. The TMS320C674x
DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail.
• Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and
all internal memories immediately upon command from software.
Static power-down (clock gating) affects all components of the C674x megamodule and all internal
memories. Software can initiate static power-down by way of a register bit in the power-down controller
command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.3
Bandwidth Manager (BWM)
The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA3-initiated DMA transfers (and resulting coherency operations)
• DSP subsystem IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of the C674x megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA3, DSP subsystem IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The
programmable priority level has a single meaning throughout the system. There are a total of nine priority
levels, where priority zero is the highest priority and priority eight is the lowest priority. When requests for
a single resource contend, access is granted to the highest-priority requestor. When the contention occurs
for multiple successive cycles, a contention counter assures that the lower-priority requestor gets access
to the resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1
represents a transfer whose priority has been increased due to expiration of the contention counter or a
transfer that is fixed as the highest-priority transfer to a given resource.
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2.2.2.4
Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) port. The IDMA cannot
transfer data to or from the internal DSP memory-mapped register space. The IDMA is fully described in
the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
2.3
Memory Map
Refer to your device-specific data manual for the addresses of the memory-map registers.
2.3.1 DSP Internal Memory
See the System Memory chapter for a description of the DSP internal memory.
2.3.2 External Memory
See the System Interconnect chapter and the System Memory chapter for a description of the additional
memory and peripherals that the DSP has access to.
2.4
Advanced Event Triggering (AET)
The C674x megamodule supports advanced event triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides
the following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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System Interconnect
Topic
3.1
3.2
60
...........................................................................................................................
Page
Introduction ....................................................................................................... 61
System Interconnect Block Diagram ..................................................................... 62
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3.1
Introduction
The DSP, the EDMA3 transfer controllers, and the device peripherals are interconnected through a switch
fabric architecture (see Section 3.2). The switch fabric is composed of multiple switched central resources
(SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals
and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Through the SCRs, the DSP can send data to the EMIF without affecting a
data transfer between a device peripheral and internal shared memory. Bridges are mainly used to
perform bus-width conversion as well as bus operating frequency conversion.
The DSP, the EDMA3 transfer controllers, and the various device peripherals can be classified into two
categories: master peripherals and slave peripherals. Master peripherals are typically capable of initiating
read and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to
and from them. The system master peripherals include the DSP, the EDMA3 transfer controllers, and HPI.
Not all master peripherals may connect to all slave peripherals. The supported connections are designated
by an X in Table 3-1.
Table 3-1. TMS320C6742 DSP System Interconnect Matrix
Masters
Master
Slaves
Default
Priority
DSP
SDMA
EMIFA
DDR2/
mDDR
EDMA3_0_TC0/
TC1
EDMA3_1_TC0
Peripheral
Group (1)
EDMA3_0_CC0
0
EDMA3_1_CC0
0
EDMA3_0_TC0
0
X
X
X
X
X
X
EDMA3_0_TC1
0
X
X
X
X
X
X
DSP CFG
2
X
X
X
DSP MDMA
2
X
X
EDMA3_1_TC0
4
X
X
X
X
X
X
HPI
6
X
X
X
(1)
(2)
X
X
X (2)
Peripheral group: SYSCFG, eCAP0, eCAP1, eCAP2, eHRPWM0, eHRPWM1, GPIO, I2C0, McASP0, McBSP1, PLLC0, PLLC1,
PSC0, PSC1, RTC, SPI1, TIMER64P0, TIMER64P1, EDMA3_0_CC0, EDMA3_1_CC0, UART0, HPI .
The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level.
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System Interconnect Block Diagram
Figure 3-1 shows a system interconnect block diagram.
Figure 3-1. System Interconnect Block Diagram
SCR F0
HPI
BR F0
DSP SDMA (L1D/L2)
SCR F3
MPU2
DDR2/mDDR
DSP MDMA
EDMA3_0_TC0
EDMA3_0_TC1
EDMA3_1_TC0
rd
EDMA3_1_CC0
wr
SCR1
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
rd
wr
EDMA3_1_CC0
rd
SCR F5
PSC0
SCR5
wr
EDMA3_1_TC0
PLLC0
HPI
SYSCFG0
BR5
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 2 Clock Domain
BR3
Timer64P0
BR4
Timer64P1
SCR6
DSP CFG
SYSCFG1
I2C0
SCR F6
RTC
BR6
PSC1
PLLC1
Async 1 Clock Domain
BR7
GPIO
BR F3
EMIFA
Async 3 [PLL1] Clock Domain
SCR4
BR F4
UART0
SCR F7
McBSP1
McASP0
SCR2
Legend:
32-bit BUS
64-bit BUS
EDMA3_0_TC0
eHRPWM0
EDMA3_0_TC1
IP Module
Synchronous Bridge
Asynchronous Bridge
SCR
eHRPWM1
eCAP0
BR F5
SCR F8
eCAP1
eCAP2
Paths with dashed lines cross the subchip boundary
SPI1
EDMA3_0_CC0
62
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System Memory
Topic
4.1
4.2
4.3
...........................................................................................................................
Page
Introduction ....................................................................................................... 64
DSP Memories ................................................................................................... 64
Peripherals ........................................................................................................ 64
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Introduction
This device has multiple on-chip/off-chip memories and several external device interfaces associated with
the DSP and various subsystems. To help simplify software development, a unified memory-map is used
wherever possible to maintain a consistent view of device resources across all masters.
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
4.2
DSP Memories
The DSP internal memories are accessible by the and other master peripherals (as dictated by the
connectivity matrix) via the system interconnect through the DSP SDMA port.
The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
• L1P memory includes 32 KB of RAM. The DSP program memory controller (PMC) allows you to
configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache
sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB
cache.
• L1D memory includes 32 KB of RAM. The DSP data memory controller (DMC) allows you to configure
part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB,
8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB cache.
• L2 memory includes 64 KB of RAM. The DSP unified memory controller (UMC) allows you to configure
part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8
KB, 16 KB, 32 KB, or 64 KB of the 64 KB of RAM. The default configuration is 64 KB normal RAM.
• L2 memory also includes 1024 KB of ROM.
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIF:
– 8/16-bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM,
NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space
• DDR2/mDDR memory controller:
– 16-bit DDR2 with up to 256-MB memory address space
– 16-bit mDDR with up to 256-MB memory address space
Internal Peripherals
The following peripherals are internal to the DSP subsystem and are only accessible to the DSP:
• DSP interrupt controller (INTC)
• DSP power down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA)
For more information on the internal peripherals, see the TMS320C674x DSP Megamodule Reference
Guide (SPRUFK5).
4.3
Peripherals
The DSP has access to all peripherals. See the device-specific data manual for the complete list of
peripherals supported on your device.
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Memory Protection Unit (MPU)
Topic
5.1
5.2
5.3
...........................................................................................................................
Page
Introduction ....................................................................................................... 66
Architecture....................................................................................................... 67
MPU Registers ................................................................................................... 71
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Introduction
This device supports one memory protection unit (MPU2). MPU2 supports the DDR2/mDDR SDRAM.
5.1.1 Purpose of the MPU
The memory protection unit (MPU) is provided to manage access to memory. The MPU allows you to
define multiple ranges and limit access to system masters based on their privilege ID. The MPU can
record a detected fault, or invalid access, and notify the system through an interrupt.
5.1.2 Features
The MPU supports the following features:
• Supports multiple programmable address ranges
• Supports 0 or 1 fixed range
• Supports read, write, and execute access privileges
• Supports privilege ID associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• Supports L1/L2 cache accesses
• Supports protection of its own registers
5.1.3 Block Diagram
Figure 5-1 shows a block diagram of the MPU. An access to a protected memory must pass through the
MPU. During an access, the MPU checks the memory address on the input data bus against fixed and
programmable ranges. If allowed, the transfer is passed unmodified to the output data bus. If the transfer
fails the protection check then the MPU does not pass the transfer to the output bus but rather services
the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor
as well as generating an interrupt about the fault. The MPU generates two interrupts: an address error
interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).
Figure 5-1. MPU Block Diagram
MPU
Input
Data
Bus
Protection
Checks
Output
Data
Bus
MPU_ADDR_ERR_INT
MMRs
MPU_PROT_ERR_INT
MPU Register Bus
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5.1.4 MPU Default Configuration
Table 5-1 shows the memory region protected by the MPU2. Table 5-2 shows the configuration of the
MPU2.
Table 5-1. MPU Memory Regions
Memory Region
Unit
Memory Protection
Start Address
End Address
MPU2
DDR2/mDDR SDRAM
C000 0000h
DFFF FFFFh
Table 5-2. MPU2 Default Configuration
Setting
MPU2
Default permission
Assume allowed
Number of allowed IDs supported
12
Number of fixed ranges supported
0
Number of programmable ranges supported
12
Compare width
5.2
64 KB granularity
Architecture
5.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
DSP CPU instruction and data accesses have a privilege level associated with them. The privilege level is
inherited from the code running on the CPU. See the TMS320C674x DSP CPU and Instruction Set
Reference Guide (SPRUFE8) for more details on privilege levels of the DSP CPU.
Although master peripherals like the HPI do not execute code, they still have a privilege level associated
with them. Unlike the DSP CPU, the privilege level of this peripheral is fixed.
Table 5-3 shows the privilege ID of the CPU and every mastering peripheral. Table 5-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.
Table 5-3. Device Master Settings
Master
Privilege Level
Access Type
EDMA3_0_CC0
Privilege ID
Inherited
Inherited
DMA
EDMA3_0_TC0 and EDMA3_0_TC1
Inherited
Inherited
DMA
EDMA3_1_CC0
Inherited
Inherited
DMA
EDMA3_1_TC0
Inherited
Inherited
DMA
DSP
1
Software dependant
Software dependant
HPI
3
User
DMA
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5.2.2 Memory Protection Ranges
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory. One of the programmable
address ranges could be used to detect accesses to this unpopulated memory.
The MPU divides its assigned memory into address ranges. Each MPU can support one fixed address
range and multiple programmable address ranges. The fixed address range is configured to an exact
address. The programmable address range allows software to program the start and end addresses.
Each address range has the following set of registers:
• Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending
address of the address range.
• Memory protection page attribute register (MPPA): Use to program the permission settings of the
address range.
It is allowed to configure ranges such that they overlap each other. In this case, all the overlapped ranges
must allow the access, otherwise the access is not allowed. The final permissions given to the access are
the lowest of each type of permission from any hit range.
Addresses not covered by a range are either allowed or disallowed based on the configuration of the
MPU. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the
ASSUME_ALLOWED bit in the configuration register (CONFIG).
5.2.3 Permission Structures
The MPU defines a per-range permission structure with three permission fields in a 32-bit permission
entry. Figure 5-2 shows the structure of a permission entry.
Figure 5-2. Permission Fields
31
22
21
20
19
AID11
AID10
AID9
5
4
3
Reserved
15
14
13
12
11
10
AID4
5.2.3.1
AID3
AID2
9
8
6
Reserved
AID1
AID0
17
16
AID8
AID7
AID6
2
1
0
UW
UX
Allowed IDs
Allowed IDs
AID5
18
AIX
Access Types
SR
SW
SX
UR
Requestor-ID Based Access Controls
Each master on the device has an N-bit code associated with it that identifies it for privilege purposes.
This privilege ID accompanies all memory accesses made on behalf of that master. That is, when a
master triggers a memory access command, the privilege ID will be carried alongside the command.
Each memory protection range has an allowed ID (AID) field associated with it that indicates which
requestors may access the given address range. The MPU maps the privilege IDs of all the possible
requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA).
• AID0 through AID11 are used to specify the allowed privilege IDs.
• An additional allowed ID bit, AIDX, captures access made by all privilege IDs not covered by AID0
through AID11.
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies
access to the corresponding requestor.
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5.2.3.2
Request-Type Based Permissions
The memory protection model defines three fundamental functional access types: read, write, and
execute. Read and write refer to data accesses -- accesses originating via the load/store units on the CPU
or via a master peripheral. Execute refers to accesses associated with an instruction fetch.
The memory protection model allows controlling read, write, and execute permissions independently for
both user and supervisor mode. This results in six permission bits, listed in Table 5-4. For each bit, a 1
permits the access type and a 0 denies access. For example, UX = 1 means that User Mode may execute
from the given page. The memory protection unit allows you to specify all six of these bits separately; 64
different encodings are permitted altogether, although programs might not use all of them.
Table 5-4. Request Type Access Controls
Bit
Field
Description
5
SR
Supervisor may read
4
SW
Supervisor may write
3
SX
Supervisor may execute
2
UR
User may read
1
UW
User may write
0
UX
User may execute
5.2.4 Protection Check
During a memory access, the MPU checks if the address range of the input transfer overlaps one of the
address ranges. When the input transfer address is within a range the transfer parameters are checked
against the address range permissions.
The MPU first checks the transfers privilege ID against the AID settings. If the AID bit is 0, then the range
will not be checked; if the AID bit is 1, then the transfer parameters are checked against the memory
protection page attribute register (MPPA) values to detect an allowed access.
For non-debug accesses, the read, write, and execute permissions are also checked. There is a set of
permissions for supervisor mode and a set for user mode. For supervisor mode accesses, the SR, SW,
and SX bits are checked. For user mode accesses, the UR, UW, and UX bits are checked.
If the transfer address range does not match any address range then the transfer is either allowed or
disallowed based on the configuration of the MPU. The MPU can be configured for assumed allowed or
assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register
(CONFIG).
In the case that a transfer spans multiple address ranges, all the overlapped ranges must allow the
access, otherwise the access is not allowed. The final permissions given to the access are the lowest of
each type of permission from any hit range. Therefore, if a transfer matches 2 ranges, one that is RW and
one that is RX, then the final permission is just R.
The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses, see
Section 5.2.5 for more details.
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5.2.5 DSP L1/L2 Cache Controller Accesses
A memory read access that originates from the DSP L1/L2 cache is treated differently to allow memory
protection to be enforced by the DSP level. This is because a subsequent memory access that hits in the
cache does not pass through the MPU. Instead the memory access is serviced directly by the L1/L2
memory controllers.
During a cache memory read, the permission settings stored in the memory protection page attribute
registers (MPPA) are passed to the L1/L2 memory controllers along with the read data. The permissions
settings returned by the MPU are taken from MPPA that covers the address range of the original
request—only the SR, SW, SX, UR, UW, and UX bits are passed. If the request address is covered by
multiple address ranges, then the returned value is the logical-AND of all MPPA permissions. If the
transfer address range is not covered by an address range then the transfer is either allowed or
disallowed based on the configuration of the MPU.
5.2.6 MPU Register Protection
Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page
attribute registers (MPPA) is also protected. All non-debug writes must be by a supervisor entity. A
protection fault can occur from a register write with invalid permissions and this triggers an interrupt just
like a memory access.
Faults are not recorded (nor interrupts generated) for debug accesses.
5.2.7 Invalid Accesses and Exceptions
When a transfer fails the protection check, the MPU does not pass the transfer to the output bus. The
MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.
The behavior of the MPU depends on whether the access was a read or a write:
• For a read: The MPU returns 0s, a permission value is 0 (no access allowed), a protection error status.
• For a write: The MPU receives all the write data and returns a protection error status.
The MPU captures system faults due to addressing or protection violations in its registers. The MPU can
store the fault information for only one fault, so the first detected fault is recorded into the fault registers
and an interrupt is generated. Software must use the fault clear register (FLTCLR) to clear the fault status
so that another fault can be recorded. The MPU will not record another fault nor generate another interrupt
until the existing fault has been cleared. Also, additional faults will be ignored. Faults are not recorded (no
interrupts generated) for debug accesses.
5.2.8 Reset Considerations
After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection
features.
5.2.9 Interrupt Support
5.2.9.1
Interrupt Events and Requests
The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection
interrupt (MPU_PROT_ERR_INT). The MPU_ADDR_ERR_INT is generated when there is an addressing
violation due to an access to a non-existent location in the MPU register space. The
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined
ranges or to the MPU registers.
The transfer parameters that caused the violation are saved in the MPU registers.
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5.2.9.2
Interrupt Multiplexing
The interrupts from both MPUs are combined with the boot configuration module into a single interrupt
called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt controller. Table 5-5
shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR.
Table 5-5. MPU_BOOTCFG_ERR Interrupt Sources
Interrupt
Source
MPU2_ADDR_ERR_INT
MPU2 address error interrupt
MPU2_PROT_ERR_INT
MPU2 protection interrupt
BOOTCFG_ADDR_ERR
Boot configuration address error
BOOTCFG_PROT_ERR
Boot configuration protection error
5.2.10 Emulation Considerations
Memory and MPU registers are not protected against emulation accesses.
5.3
MPU Registers
Table 5-6 lists the memory-mapped registers for the MPU2.
Table 5-6. Memory Protection Unit 2 (MPU2) Registers
Address
Acronym
Register Description
01E1 5000h
REVID
Revision identification register
Section 5.3.1
01E1 5004h
CONFIG
Configuration register
Section 5.3.2
01E1 5010h
IRAWSTAT
Interrupt raw status/set register
Section 5.3.3
01E1 5014h
IENSTAT
Interrupt enable status/clear register
Section 5.3.4
01E1 5018h
IENSET
Interrupt enable set register
Section 5.3.5
01E1 501Ch
IENCLR
Interrupt enable clear register
Section 5.3.6
01E1 5100h
FXD_MPSAR
Fixed range start address register
Section 5.3.7
01E1 5104h
FXD_MPEAR
Fixed range end address register
Section 5.3.8
01E1 5108h
FXD_MPPA
Fixed range memory protection page attributes register
Section 5.3.9
01E1 5200h
PROG1_MPSAR
Programmable range 1 start address register
Section 5.3.10
01E1 5204h
PROG1_MPEAR
Programmable range 1 end address register
Section 5.3.11
01E1 5208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
Section 5.3.12
01E1 5210h
PROG2_MPSAR
Programmable range 2 start address register
Section 5.3.10
01E1 5214h
PROG2_MPEAR
Programmable range 2 end address register
Section 5.3.11
01E1 5218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
Section 5.3.12
01E1 5220h
PROG3_MPSAR
Programmable range 3 start address register
Section 5.3.10
01E1 5224h
PROG3_MPEAR
Programmable range 3 end address register
Section 5.3.11
01E1 5228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
Section 5.3.12
01E1 5230h
PROG4_MPSAR
Programmable range 4 start address register
Section 5.3.10
01E1 5234h
PROG4_MPEAR
Programmable range 4 end address register
Section 5.3.11
01E1 5238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
Section 5.3.12
01E1 5240h
PROG5_MPSAR
Programmable range 5 start address register
Section 5.3.10
01E1 5244h
PROG5_MPEAR
Programmable range 5 end address register
Section 5.3.11
01E1 5248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
Section 5.3.12
01E1 5250h
PROG6_MPSAR
Programmable range 6 start address register
Section 5.3.10
01E1 5254h
PROG6_MPEAR
Programmable range 6 end address register
Section 5.3.11
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Table 5-6. Memory Protection Unit 2 (MPU2) Registers (continued)
Address
Acronym
Register Description
01E1 5258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
Section 5.3.12
Section
01E1 5260h
PROG7_MPSAR
Programmable range 7 start address register
Section 5.3.10
01E1 5274h
PROG7_MPEAR
Programmable range 7 end address register
Section 5.3.11
01E1 5268h
PROG7_MPPA
Programmable range 7 memory protection page attributes register
Section 5.3.12
01E1 5270h
PROG8_MPSAR
Programmable range 8 start address register
Section 5.3.10
01E1 5274h
PROG8_MPEAR
Programmable range 8 end address register
Section 5.3.11
01E1 5278h
PROG8_MPPA
Programmable range 8 memory protection page attributes register
Section 5.3.12
01E1 5280h
PROG9_MPSAR
Programmable range 9 start address register
Section 5.3.10
01E1 5284h
PROG9_MPEAR
Programmable range 9 end address register
Section 5.3.11
01E1 5288h
PROG9_MPPA
Programmable range 9 memory protection page attributes register
Section 5.3.12
01E1 5290h
PROG10_MPSAR
Programmable range 10 start address register
Section 5.3.10
01E1 5294h
PROG10_MPEAR
Programmable range 10 end address register
Section 5.3.11
01E1 5298h
PROG10_MPPA
Programmable range 10 memory protection page attributes register
Section 5.3.12
01E1 52A0h
PROG11_MPSAR
Programmable range 11 start address register
Section 5.3.10
01E1 52A4h
PROG11_MPEAR
Programmable range 11 end address register
Section 5.3.11
01E1 52A8h
PROG11_MPPA
Programmable range 11 memory protection page attributes register
Section 5.3.12
01E1 52B0h
PROG12_MPSAR
Programmable range 12 start address register
Section 5.3.10
01E1 52B4h
PROG12_MPEAR
Programmable range 12 end address register
Section 5.3.11
01E1 52B8h
PROG12_MPPA
Programmable range 12 memory protection page attributes register
Section 5.3.12
01E1 5300h
FLTADDRR
Fault address register
Section 5.3.13
01E1 5304h
FLTSTAT
Fault status register
Section 5.3.14
01E1 5308h
FLTCLR
Fault clear register
Section 5.3.15
5.3.1 Revision Identification Register (REVID)
The revision ID register (REVID) contains the MPU revision. The REVID is shown in Figure 5-3 and
described in Table 5-7.
Figure 5-3. Revision ID Register (REVID)
31
0
REV
R-4E81 0101h
LEGEND: R = Read only; -n = value after reset
Table 5-7. Revision ID Register (REVID) Field Descriptions
72
Bit
Field
Value
31-0
REV
4E81 0101h
Memory Protection Unit (MPU)
Description
Revision ID of the MPU.
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5.3.2 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown
in Figure 5-4 and described in Table 5-8.
NOTE: Although the NUM_AIDS bit defaults to 12 (Ch), not all AIDs may be supported on your
device. Unsupported AIDs should be cleared to 0 in the memory page protection attributes
registers (MPPA). See for a list of AIDs supported on your device.
Figure 5-4. Configuration Register (CONFIG)
31
24
15
23
20
19
16
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-6h
R-1
R-Ch
12
11
1
0
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-Ch
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 5-8. Configuration Register (CONFIG) Field Descriptions
Field
Value
Description
31-24
Bit
ADDR_WIDTH
0-FFh
Address alignment (2n KByte alignment) for range checking.
23-20
NUM_FIXED
0-Fh
Number of fixed address ranges.
19-16
NUM_PROG
0-Fh
Number of programmable address ranges.
15-12
NUM_AIDS
0-Fh
Number of supported AIDs.
11-1
Reserved
0
0
ASSUME_ALLOWED
Reserved
Assume allowed. When an address is not covered by any MPU protection range, this bit
determines whether the transfer is assumed to be allowed or not allowed.
0
Assume is disallowed.
1
Assume is allowed.
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5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 5-5 and described in Table 5-9.
Figure 5-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-9. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
74
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 5-6 and described in Table 510.
Figure 5-6. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.5 Interrupt Enable Set Register (IENSET)
Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Software can
write to IENSET to enable an interrupt. Writes of 0 have no effect. The IENSET is shown in Figure 5-7 and
described in Table 5-11.
Figure 5-7. Interrupt Enable Set Register (IENSET)
31
16
Reserved
R-0
15
2
1
0
ADDRERR_EN
PROTERR_EN
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Interrupt Enable Set Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved
Address violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
PROTERR_EN
Protection violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
5.3.6 Interrupt Enable Clear Register (IENCLR)
Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Software can
write to IENCLR to clear/disable an interrupt. Writes of 0 have no effect. The IENCLR is shown in
Figure 5-8 and described in Table 5-12.
Figure 5-8. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-12. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
76
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved
Address violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
PROTERR_CLR
Protection violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
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5.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPSAR and the fixed range end
address register (FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in Figure 5-9.
Figure 5-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
5.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPEAR and the fixed range start
address register (FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 5-10.
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 5-11
and described in Table 5-13.
Figure 5-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-13. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
78
Controls access from ID = n.
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR)
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory, especially memory. One of the
programmable address ranges could be used to detect accesses to this unpopulated
memory.
The programmable range n start address register (PROGn_MPSAR) holds the start address for the range
n. The PROGn_MPSAR is writeable by a supervisor entity only.
The start address must be aligned on a page boundary. The page size for MPU2 is 64 KBytes. The size of
the page determines the width of the address field in PROGn_MPSAR and the programmable range n end
address register (PROGn_MPEAR). For example, to protect a 64-KB page starting at byte address
8001 0000h, write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
The PROGn_MPSAR for MPU2 is shown in Figure 5-12 and described in Table 5-14.
Figure 5-12. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
31
16 15
0
START_ADDR
Reserved
R/W-C000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-14. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
Field
31-16
START_ADDR
15-0
Reserved
Value
C000h–DFFFh
0
Description
Start address for range N.
Reserved
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5.3.11 Programmable Range n End Address Registers (PROGn_MPEAR)
The programmable range n end address register (PROGn_MPEAR) holds the end address for the range
n. This register is writeable by a supervisor entity only.
The end address must be aligned on a page boundary. The page size for MPU2 is 64 KBytes. The size of
the page determines the width of the address field in the programmable range n start address register
(PROGn_MPSAR) and PROGn_MPEAR. For example, to protect a 64-KB page starting at byte address
8001 0000h, write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
The PROGn_MPEAR for MPU2 is shown in Figure 5-13 and described in Table 5-15.
Figure 5-13. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
31
16 15
0
END_ADDR
Reserved
R/W-DFFFh
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
Field
31-16
END_ADDR
15-0
Reserved
80
Value
C000h–DFFFh
FFFFh
Memory Protection Unit (MPU)
Description
Start address for range N.
Reserved
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5.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA)
The programmable range n memory protection page attributes register (PROGn_MPPA) holds the
permissions for the region n. This register is writeable only by a supervisor entity. The PROGn_MPPA is
shown in Figure 5-14 and described in Table 5-16.
Figure 5-14. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Controls access from ID = n.
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.13 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) holds the address of the first protection fault transfer. The
FLTADDRR is shown in Figure 5-15 and described in Table 5-17.
Figure 5-15. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
82
Field
FLTADDR
Value
0-FFFF FFFFh
Memory Protection Unit (MPU)
Description
Memory address of fault.
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5.3.14 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in Figure 5-16 and described in Table 5-18.
Figure 5-16. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
Reserved
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-18. Fault Status Register (FLTSTAT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MSTID
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
Value
0
0-FFh
0
0-Fh
0
0-3Fh
Description
Reserved
Master ID of fault transfer.
Reserved
Privilege ID of fault transfer.
Reserved
Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).
0
No fault.
1h
User execute fault.
2h
User write fault.
3h
Reserved
4h
User read fault.
5h-7h
8h
9h-Fh
Reserved
Supervisor execute fault.
Reserved
10h
Supervisor write fault.
11h
Reserved
12h
Relaxed cache write back fault.
13h-1Fh
20h
21h-3Eh
3Fh
Reserved
Supervisor read fault.
Reserved
Relaxed cache line fill fault.
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5.3.15 Fault Clear Register (FLTCLR)
The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured
in the fault status register (FLTSTAT) as well as produce an interrupt. Only the TYPE bit field in FLTSTAT
is cleared when a 1 is written to the CLEAR bit. The FLTCLR is shown in Figure 5-17 and described in
Table 5-19.
Figure 5-17. Fault Clear Register (FLTCLR)
31
16
Reserved
R-0
15
1
0
Reserved
CLEAR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 5-19. Fault Clear Register (FLTCLR) Field Descriptions
Bit
31-1
0
84
Field
Reserved
Value
0
CLEAR
Description
Reserved
Command to clear the current fault. Writing 0 has no effect.
0
No effect.
1
Clear the current fault.
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Chapter 6
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Device Clocking
Topic
6.1
6.2
6.3
...........................................................................................................................
Page
Overview ........................................................................................................... 86
Frequency Flexibility .......................................................................................... 88
Peripheral Clocking ............................................................................................ 89
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Overview
This device requires two primary reference clocks:
• One reference clock is required for the phase-locked loop controllers (PLLCs)
• One reference clock is required for the real-time clock (RTC) module.
These reference clocks may be sourced from either the on-board oscillator via an externally supplied
crystal or by a direct external oscillator input. For detailed specifications on clock frequency and voltage
requirements, see the electrical specifications in your device-specific data manual.
All possible input clocks are described in Table 6-1. The CPU and the majority of the device peripherals
operate at fixed ratios of the primary system/CPU clock frequency, as listed in Table 6-2. However, there
are two system clock domains that do not require a fixed ratio to the CPU, these are PLL0_SYSCLK3 and
PLL0_SYSCLK7. Figure 6-1 shows the clocking architecture.
Table 6-1. Device Clock Inputs
Peripheral
Input Clock Signal Name
Oscillator/PLL
OSCIN
RTC
RTC_XI
JTAG
TCK
I2C0
I2C0_SCL
Timers
TM64Pn_IN12
SPI1
SPI1_CLK
McBSP1
CLKS1, CLKR1, CLKX1
McASP0
ACLKR, AHCLKR, ACLKX, AHCLKX
Table 6-2. System Clock Domains
86
CPU/Device Peripherals
System Clock Domain
Fixed Ratio to
CPU Clock Required?
Default Ratio to
CPU Clock
DSP
PLL0_SYSCLK1
Yes
1:1
DSP ports, UART0, EDMA, DDR2/mDDR (bus ports),
HPI,
PLL0_SYSCLK2
Yes
1:2
EMIFA
PLL0_SYSCLK3
No
1:3
System configuration (SYSCFG), GPIO, PLLCs, PSCs
PLL0_SYSCLK4
Yes
1:4
I2C0, Timer64P0/P1, RTC, McASP0 serial clock
PLL0_AUXCLK
Not Applicable
Not Applicable
DDR2/mDDR PHY
PLL1_SYSCLK1
Not Applicable
Not Applicable
PLL0 input reference clock
(not configured by default)
PLL1_SYSCLK3
Not Applicable
Not Applicable
ECAPs, eHRPWMs, McBSP1, McASP0, SPI1
ASYNC3
Not Applicable
Not Applicable
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Figure 6-1. Overall Clocking Diagram
PLL0 Multiplier Out
Div 4.5
1
EMIFA (B)
0+
SYSCLK3 (/3)
SYSCLK1 (/1)
DSP
CFGCHIP3[EMA_CLKSRC]
System CFG
SYSCLK4 (/4)
EDMA
PSCs
PLL0
Controller
HPI
GPIO
CLKSRC
UART0
DDR2/mDDR (A)
EXTCLKSRC
I2C0
AUXCLK
Timers0/1
McASP0 (C)
RTC
PLL
Ref CLK
McBSP1
SYSCLK2 (/2)
0+
SYSCLK2 (/2)
1
PLL1
Controller
CFGCHIP3[ASYNC3_CLKSRC]
eHRPWMs
eCAPs
SPI1
SYSCLK3 (/3)
+ Default Mux Selection
CLKSRC
A
See Section 6.3.1 for DDR2/mDDR clocking.
B
See Section 6.3.2 for EMIFA clocking.
C
See Section 6.3.3 for McASP clocking.
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Frequency Flexibility
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Frequency Flexibility
There are two PLLs on the device with similar architecture and behavior. Each PLL has two clocking
modes:
• PLL Bypass
• PLL Active
When the PLL is in Bypass mode, the reference clock supplied on OSCIN serves as the clock source from
which all of the system clocks (SYSCLK1 to SYSCLK7) are derived. This means that when the PLL is in
Bypass mode, the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that
creates each of the system clocks. For PLL0 only, the EXTCLKSRC bit in PLLCTL can be configured to
use PLL1_SYSCLK3 as the Bypass mode reference clock.
When the PLL operates in Active mode, the PLL is enabled and the PLL multiplier setting is used to
multiply the input clock frequency supplied on the OSCIN pin up to the desired frequency. It is this
multiplied frequency that all system clocks are derived from in PLL Active mode.
The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the
system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1 to SYSCLK7). Each
SYSCLKn has a PLLDIVn block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter
for more details on the PLL.
The combination of the PLL multiplier, POSTDIV, and PLLDIV blocks provides flexibility in the frequencies
that the system clock domains support. This flexibility does have limitations, as follows:
• OSCIN input frequency is limited to a supported range.
• The output of the PLL Multiplier must be within the range specified in the device-specific data manual.
• The output of each PLLDIV block must be less than or equal to the maximum device frequency
specified in the device-specific data manual.
NOTE: The above limitations are provided here as an example and are used to illustrate the
recommended configuration of the PLL controller. These limitations may vary based on core
voltage and between devices. See the device-specific data manual for more details.
Table 6-3 shows examples of possible PLL multiplier settings, along with the available PLL post-divider
modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL
post-divider control register (POSTDIV). For Div1, Div2, Div3, and Div4 modes, the RATIO field would be
programmed to 0, 1, 2, and 3, respectively. The Div1, Div2, Div3, and Div4 modes are shown here as an
example. Additional post-divider modes are supported and are documented in the Phase-Locked Loop
Controller (PLLC) chapter.
NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases.
To decrease PLL power consumption, the lowest PLL multiplier (PLLM) setting should be
chosen that achieves the desired frequency. For example, if 200 MHz is the desired CPU
operating frequency and the OSCIN frequency is 25 MHz; lower power consumption is
achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2
instead of a PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these
modes would result in a CPU frequency of 200 MHz.
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Table 6-3. Example PLL Frequencies
6.3
OSCIN
Frequency
PLL Multiplier
Multiplier
Frequency
Div1
Div2
Div3
Div4
20
30
600 MHz
600
300
200
150
24
25
600 MHz
600
300
200
150
25
24
600 MHz
600
300
200
150
30
20
600 MHz
600
300
200
150
20
25
500 MHz
500
250
167
125
24
20
480 MHz
480
240
160
120
25
18
450 MHz
450
225
150
112.5
30
14
420 MHz
420
210
140
105
25
16
400 MHz
400
200
133
100
Peripheral Clocking
6.3.1 DDR2/mDDR Memory Controller Clocking
The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see
Figure 6-2):
• VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO, write FIFO, and read FIFO of
the DDR2/mDDR memory controller. From this, VCLK drives the interface to the peripheral bus.
• 2X_CLK is sourced from PLL1_SYSCLK1.
2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
Table 6-4 shows example PLL register settings based on the OSCIN reference clock frequency of
25 MHz. From these example configurations, the following observations are made:
• To achieve the maximum frequency (150 MHz) supported by the DDR2/mDDR memory controller and
the typical CPU frequency of 300 MHz, the output of the PLL multiplier should be set to be 300 MHz
and the DDR_CLK source should be set to PLL1_SYSCLK1.
• The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier
block.
• The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock
frequencies.
• For certain PLL1 multiplier and PLL1 post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK1 as the clock source for 2X_CLK.
If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the
application as a free running clock that could be used by an FPGA or for some other purpose, then
2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. This
allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while
still providing a clock on the DDR_CLK and DDR_CLK.
NOTE: DDR_CLK and DDR_CLK are output clock signals.
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Figure 6-2. DDR2/mDDR Memory Controller Clocking Diagram
On Chip
PLL0_SYSCLK2/2
DDR2/mDDR
Memory
Controller
LPSC #6
DDR_CLK
DDR_CLK
VCLK
PLL1_SYSCLK1
2X_CLK
DDR
PHY
MCLK
Table 6-4. DDR2/mDDR Memory Controller MCLK Frequencies
OSCIN
Frequency
PLL1
Multiplier
Register
Setting
PLL1
Multiplier
Frequency
PLL1 Post
Divider
Mode (1)
PLL1
POSTDIV
Output
Frequency
PLL1
PLLDIV1
Register
Setting
PLL1_SYSCLK1
MCLK
24
18h
600 MHz
Div2
300 MHz
8000h
300 MHz
150 MHz
24
15h
528 MHz
Div2
264 MHz
8000h
264 MHz
132 MHz
24
14h
504 MHz
Div2
252 MHz
8000h
252 MHz
126 MHz
(1)
90
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.2 EMIFA Clocking
EMIFA requires a single input clock source. The EMIFA clock can be sourced from either PLL0_SYSCLK3
or DIV4P5 (see Figure 6-3). The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the
System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock
source for EMIFA.
Selecting the appropriate clock source for EMIFA is determined by the desired clock rate. Table 6-5 shows
example PLL register settings and the resulting DIV4P5 and PLL0_SYSCLK3 frequencies based on the
OSCIN reference clock frequency of 25 MHz. From these example configurations, the following
observations can be made:
• To achieve a typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300
MHz, the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be
set to PLL0_SYSCLK3 with the PLLDIV3 register set to 3.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV3 block that sets the divider ratio for PLL0_SYSCLK3 can be changed to achieve various
clock frequencies.
Figure 6-3. EMIFA Clocking Diagram
LPSC
PLL Controller
SYSCLK3
0
DIV4P5 CLK
1
EMIFA
CFGCHIP3[EMA_CLKSRC]
Table 6-5. EMIFA Frequencies
OSCIN
Frequency
PLL Multiplier
Register
Multiplier
Setting
Frequency
Post Divider
Mode (1)
POSTDIV
Output
Frequency
25
24
Div2
300 MHz
Div3
200 MHz
25
25
(1)
18
16
600 MHz
450 MHz
400 MHz
DIV4P5
PLLDIV3
Register
Setting
PLL0_SYSCLK3
133 MHz
2
100 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
Div2
225 MHz
100 MHz
3
56.3 MHz
2
75 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
Div2
200 MHz
89 MHz
2
66.6 MHz
1
100 MHz
Div3
133 MHz
89 MHz
1
66.5 MHz
Div4
100 MHz
89 MHz
0
100 MHz
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.3 McASP Clocking
As shown in Figure 6-4, the McASP peripheral requires multiple clock sources. Internally, the module
clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC
bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module.
The transmit and receive clocks are sourced internally or externally by configuring the McASP clock
control registers ACLKRCTL, AHCLKRCTL, ACLKXCTL, and AHCLKXCTL. If an external clock is driven
into a high-frequency master clock (AHCLKX or AHCLKR), the McASP module allows for a mixed clock
mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the highfrequency master clock through a programmable divider.
When the internal clock source option is selected, the transmit and receive clocks are derived from the
PLL0_AUXCLK clock through programmable dividers.
Figure 6-4. McASP Clocking Diagram
On Chip
CFGCHIP3[ASYNC3_CLKSRC]
PLL0_SYSCLK2
0
PLL1_SYSCLK2
1
LPSC
Module
Clock
McASP0
PLL0_AUXCLK
TX/RX
Reference
Clock
Clock
Generator
Frame Sync
Generator
ACLKX
AHCLKX
AFSX
AFSR
ACLKR
AHCLKR
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6.3.4 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
The peripherals can be divided into the following groups, depending upon their clock requirements, as
shown in Table 6-6.
Table 6-6. Peripherals
Peripherals
Contained
within Group
Source of Peripheral Clock
RTC
—
Peripheral Group
Peripheral Group Definition
RTC
Operates off of a dedicated 32 kHz
crystal oscillator.
Fixed-Frequency Peripherals
As the name suggests, fixedTimer64P0/P1
frequency peripherals have a fixedI2C0
frequency. They are fed the
AUXCLK directly from the oscillator
input.
—
Synchronous peripherals have their HPI
frequencies derived from the CPU
UART0
clock frequency. The peripheral
GPIO
system clock frequency changes
accordingly, if the PLL0 frequency
changes. Most synchronous
peripherals have internal dividers
so they can generate their required
clock frequencies.
PLL0_SYSCLK2
Asynchronous peripherals are not
required to operate at a fixed ratio
of the CPU clock.
eCAPs
ASYNC3
eHRPWMs
ASYNC3
EMIFA
DIV_4P5 or PLL0_SYSCLK3
DDR2/mDDR
PLL1_SYSCLK1 or
PLL1 Direct Output
McASP0
ASYNC3 or
Peripheral Serial Clock
McBSP1
ASYNC3 or
Peripheral Serial Clock
SPI1
ASYNC3 or
Peripheral Serial Clock
Synchronous Peripherals
Asynchronous Peripherals
Synchronous/Asynchronous
Peripherals
Synchronous/asynchronous
peripherals can be run with either
internally generated synchronous
clocks, or externally generated
asynchronous clocks.
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PLL0_SYSCLK2
PLL0_SYSCLK4
Device Clocking
93
Chapter 7
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Phase-Locked Loop Controller (PLLC)
Topic
7.1
7.2
7.3
94
...........................................................................................................................
Page
Introduction ....................................................................................................... 95
PLL Controllers .................................................................................................. 95
PLLC Registers ................................................................................................ 100
Phase-Locked Loop Controller (PLLC)
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7.1
Introduction
This device has two phase-locked loop (PLL) controllers, PLLC0 and PLLC1. These PLL controllers
provide clock signals to most of the components of the device through various clock dividers.
Both PLL0 and PLL1 provide the following:
• Glitch-free transitions when clock settings are changed
• Domain clock alignment
• Clock gating
• PLL power-down
The clock outputs generated by the PLL controllers are:
• Domain clocks: PLL0_SYSCLK[1-7] and PLL1_SYSCLK[1-3]
• Auxiliary clock (PLL0_AUXCLK) from the PLLC0 reference clock source
Dividers that can be used for the PLL controllers are:
• Pre-PLL divider: PREDIV
• Post-PLL divider: POSTDIV
• SYSCLK divider: D1, …, Dn
Various other control signals supported are:
• PLL multiplier: PLLM
• Software-programmable PLL bypass: PLLEN
7.2
PLL Controllers
PLL0 and PLL1 share the same internal architecture so they also share the same approach for mode
configuration.
PLL0 provides the primary system clock to the device. PLL0 operations are software programmable
through the PLL controller 0 (PLLC0) registers.
PLL1 provides the reference clocks to various peripherals (including DDR2/mDDR) and may generate
clocks that are asynchronous to the PLL0 clocks. PLL1 operations are software programmable through the
PLL controller 1 (PLLC1) registers.
Figure 7-1 shows the PLLC0 and PLLC1 architecture.
The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register (PLLM).
The PLLM defaults to a multiplier value of 13h at power-up, which results in a PLL multiplier of 20×. The
PLL0 and PLL1 output clocks may be divided-down for slower device operation using the PLL post-divider
control register (POSTDIV). The POSTDIV has a default value of /2, but may be modified through
software (using the RATIO field in POSTDIV) to achieve lower device operation frequencies. The default
PLLM and POSTDIV settings produce a 300-MHz PLL output clock when given a 30-MHz clock source.
At power-up, PLL0 and PLL1 are powered-down/disabled and must be powered-up by software through
the PLLPWRDN bit in their respective PLL control register (PLLCTL). Before each PLL completes the
power-up and frequency-lock sequence, the system operates in bypass mode by default and the system
clock (OSCIN) is provided directly from an input reference clock (square wave or internal oscillator)
selected by the CLKMODE bit in PLLCTL. After the power-up and frequency-lock sequences are
complete, software can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
The PLL controller registers are listed in Section 7.3.
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Figure 7-1. PLLC Structure
PLL Controller 0
PLLCTL[EXTCLKSRC]
PLL1_SYSCLK3
PLLCTL[CLKMODE]
1
PLLCTL[PLLEN]
0
OSCIN
0
Square
Wave
1
Crystal
0
PREDIV
POSTDIV
PLL
1
PLLM
DEEPSLEEP
Enable
PLLDIV1 (/1)
SYSCLK1
PLLDIV2 (/2)
SYSCLK2
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
PLLDIV3 (/3)
SYSCLK3
EMIFA
Internal
Clock
Source
0
1
DIV4.5
CFGCHIP3[EMA_CLKSRC]
AUXCLK
PLLC0 OBSCLK
(CLKOUT Pin)
DIV4.5
OSCDIV
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
PLLC1 OBSCLK
OCSEL[OCSRC]
PLLCTL[PLLEN]
0
POSTDIV
PLL
1
PLLM
SYSCLK1
SYSCLK2
SYSCLK3
PLL Controller 1
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV1 (/1)
SYSCLK1
DDR2/mDDR
Internal
Clock
Source
14h
17h
18h
19h
OSCDIV
PLLC1 OBSCLK
OCSEL[OCSRC]
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7.2.1 Device Clock Generation
The PLL controllers (PLLC0 and PLLC1) manage the clock ratios, alignment, and gating for the device
system clocks. Various PLL mode attributes such as pre-division, multiplier, and post-division are software
programmable through the PLL controller registers. Additionally, the reset controller in PLLC0 manages
reset propagation through the device, clock alignment, and test points.
The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the
SYSCLK dividers can handle. The POSTDIV stage should be programmed to keep the input to the
SYSCLK dividers within operating limits. See the device datasheet for the maximum operating
frequencies.
PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. These
reference clocks are summarized in Table 7-1. Some output clock dividers require fixed values so that
clock ratios between various device components are maintained regardless of PLL or bypass frequency.
Table 7-1. System PLLC Output Clocks
Output Clock
Used by
Default Ratio
(relative to PLLn_SYSCLK1)
Fixed Clock
Ratio
PLLC0 (1)
PLL0_SYSCLK1
DSP
/1
Yes
PLL0_SYSCLK2
DSP ports, UART0, EDMA, DDR2/mDDR
(bus ports), HPI,
/2
Yes
PLL0_SYSCLK3 (2)
EMIFA
/3
No
PLL0_SYSCLK4
System configuration (SYSCFG), GPIO,
PLLCs, PSCs
/4
Yes
PLL0_SYSCLK5
Not used
/3
No
PLL0_SYSCLK6
Not used
/1
Yes
PLL0_AUXCLK
I2C0, Timer64P0/P1, RTC, McASP0 serial
clock
PLL bypass clock
No
PLL0_OBSCLK
Observation clock (OBSCLK) source
Pin configurable
No
PLLC1
PLL1_SYSCLK1
DDR2/mDDR PHY
/1 or disabled
No
PLL1_SYSCLK2 (3)
ECAPs, eHRPWMs, McBSP1, McASP0,
SPI1 (all these modules use PLL0_SYSCLK2
by default)
/2 or disabled
No
PLL1_SYSCLK3 (4)
PLL0 input reference clock
(not configured by default)
/3 or disabled
No
(1)
(2)
(3)
(4)
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
PLLC0 supports an additional post-divider value of /4.5 that can be used for EMIFA clock generation. When this /4.5 value is
used, the resulting clock will not have a 50% duty cycle. Instead, the duty cycle will be 44.4%. The EMIFA uses PLL0_SYSCLK3
by default, but can be configured to use a /4.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the
EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG)
module.
The ASYNC3 modules use PLL0_SYSCLK2 by default, but all these modules can be configured as a group to use
PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system
configuration (SYSCFG) module.
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit
in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN.
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7.2.2 Steps for Programming the PLLs
Note that there is a lock mechanism implemented to protect the PLL controller registers. See
Section 7.2.2.1 for information on unlocking the PLL controller registers.
Refer to the appropriate subsection on how to program the PLL clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 7.2.2.2.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 7.2.2.3 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and only the SYSCLK dividers will be updated,
follow the sequence in Section 7.2.2.4.
Note that the PLLs are powered down after a Power-on Reset (POR). The PLLs are not powered down
after a Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the
PLLDIVx registers are reset to default values.
7.2.2.1
Locking/Unlocking PLL Register Access
A lock mechanism is implemented on the device to prevent inadvertent writes to the PLL controller
registers. This provides protection from stopping modules when the module clocks are disabled. For
example, the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally
disabled.
The PLL lock bits are located within the system configuration (SYSCFG) module:
• When set, the PLL_MASTER_LOCK bit in the chip configuration 0 register (CFGCHIP0) locks PLLC0.
• When set, the PLL1_MASTER_LOCK bit in the chip configuration 3 register (CFGCHIP3) locks PLLC1.
Because the SYSCFG module has its own lock mechanism, the SYSCFG module must be unlocked first
by writing to the KICK0R and KICK1R registers before the PLL lock bits can be cleared. Like the KICK
registers, the PLL lock bits can only be modified while in a privileged mode. See the System Configuration
(SYSCFG) Module chapter for information on privilege type and the KICK0R and KICK1R registers.
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 and the PLL1_MASTER_LOCK bit in
CFGCHIP3 default to unlocked after reset, so the following procedure is only required if the
PLLs have been locked (set to 1).
To modify the PLL controller registers, use the following sequence:
1. Write the correct key values to KICK0R and KICK1R registers.
2. Clear the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
3. Configure the desired PLL controller register values.
4. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
5. Write an incorrect key value to the KICK0R and KICK1R registers.
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7.2.2.2
Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Program the CLKMODE bit in PLLC0 PLLCTL.
2. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
3. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 (brings PLL out of power-down mode).
5. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
6. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
8. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
7.2.2.3
Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), perform the following
procedure to change the PLL multiplier:
1. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
2. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
3. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
4. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
5. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
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Changing SYSCLK Dividers
If the PLL is already operating at the desired multiplier mode, perform the following procedure to change
the SYSCLK divider values:
1. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress).
2. Program the RATIO field in PLLDIVn.
3. Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7.3
PLLC Registers
Table 7-2 lists the memory-mapped registers for the PLLC0 and Table 7-3 lists the memory-mapped
registers for the PLLC1.
Table 7-2. PLL Controller 0 (PLLC0) Registers
Address
Acronym
Register Description
01C1 1000h
REVID
PLLC0 Revision Identification Register
Section 7.3.1
01C1 10E4h
RSTYPE
PLLC0 Reset Type Status Register
Section 7.3.3
01C1 10E8h
RSCTRL
PLLC0 Reset Control Register
Section 7.3.4
01C1 1100h
PLLCTL
PLLC0 Control Register
Section 7.3.5
01C1 1104h
OCSEL
PLLC0 OBSCLK Select Register
Section 7.3.7
01C1 1110h
PLLM
PLLC0 PLL Multiplier Control Register
Section 7.3.9
01C1 1114h
PREDIV
PLLC0 Pre-Divider Control Register
Section 7.3.10
01C1 1118h
PLLDIV1
PLLC0 Divider 1 Register
Section 7.3.11
01C1 111Ch
PLLDIV2
PLLC0 Divider 2 Register
Section 7.3.13
01C1 1120h
PLLDIV3
PLLC0 Divider 3 Register
Section 7.3.15
01C1 1124h
OSCDIV
PLLC0 Oscillator Divider 1 Register
Section 7.3.21
01C1 1128h
POSTDIV
PLLC0 PLL Post-Divider Control Register
Section 7.3.23
01C1 1138h
PLLCMD
PLLC0 PLL Controller Command Register
Section 7.3.24
01C1 113Ch
PLLSTAT
PLLC0 PLL Controller Status Register
Section 7.3.25
01C1 1140h
ALNCTL
PLLC0 Clock Align Control Register
Section 7.3.26
01C1 1144h
DCHANGE
PLLC0 PLLDIV Ratio Change Status Register
Section 7.3.28
01C1 1148h
CKEN
PLLC0 Clock Enable Control Register
Section 7.3.30
01C1 114Ch
CKSTAT
PLLC0 Clock Status Register
Section 7.3.32
01C1 1150h
SYSTAT
PLLC0 SYSCLK Status Register
Section 7.3.34
01C1 1160h
PLLDIV4
PLLC0 Divider 4 Register
Section 7.3.17
01C1 1164h
PLLDIV5
PLLC0 Divider 5 Register
Section 7.3.18
01C1 1168h
PLLDIV6
PLLC0 Divider 6 Register
Section 7.3.19
01C1 116Ch
PLLDIV7
PLLC0 Divider 7 Register
Section 7.3.20
01C1 11F0h
EMUCNT0
PLLC0 Emulation Performance Counter 0 Register
Section 7.3.36
01C1 11F4h
EMUCNT1
PLLC0 Emulation Performance Counter 1 Register
Section 7.3.37
100 Phase-Locked Loop Controller (PLLC)
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Table 7-3. PLL Controller 1 (PLLC1) Registers
Address
Acronym
Register Description
01E1 A000h
REVID
PLLC1 Revision Identification Register
Section 7.3.2
Section
01E1 A100h
PLLCTL
PLLC1 Control Register
Section 7.3.6
01E1 A104h
OCSEL
PLLC1 OBSCLK Select Register
Section 7.3.8
01E1 A110h
PLLM
PLLC1 PLL Multiplier Control Register
Section 7.3.9
01E1 A118h
PLLDIV1
PLLC1 Divider 1 Register
Section 7.3.12
01E1 A11Ch
PLLDIV2
PLLC1 Divider 2 Register
Section 7.3.14
01E1 A120h
PLLDIV3
PLLC1 Divider 3 Register
Section 7.3.16
01E1 A124h
OSCDIV
PLLC1 Oscillator Divider 1 Register
Section 7.3.22
01E1 A128h
POSTDIV
PLLC1 PLL Post-Divider Control Register
Section 7.3.23
01E1 A138h
PLLCMD
PLLC1 PLL Controller Command Register
Section 7.3.24
01E1 A13Ch
PLLSTAT
PLLC1 PLL Controller Status Register
Section 7.3.25
01E1 A140h
ALNCTL
PLLC1 Clock Align Control Register
Section 7.3.27
01E1 A144h
DCHANGE
PLLC1 PLLDIV Ratio Change Status Register
Section 7.3.29
01E1 A148h
CKEN
PLLC1 Clock Enable Control Register
Section 7.3.31
01E1 A14Ch
CKSTAT
PLLC1 Clock Status Register
Section 7.3.33
01E1 A150h
SYSTAT
PLLC1 SYSCLK Status Register
Section 7.3.35
01E1 A1F0h
EMUCNT0
PLLC1 Emulation Performance Counter 0 Register
Section 7.3.36
01E1 A1F4h
EMUCNT1
PLLC1 Emulation Performance Counter 1 Register
Section 7.3.37
7.3.1 PLLC0 Revision Identification Register (REVID)
The PLLC0 revision identification register (REVID) is shown in Figure 7-2 and described in Table 7-4.
Figure 7-2. PLLC0 Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -n = value after reset
Table 7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 3C00h
Description
Peripheral revision ID for PLLC0.
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7.3.2 PLLC1 Revision Identification Register (REVID)
The PLLC1 revision identification register (REVID) is shown in Figure 7-3 and described in Table 7-5.
Figure 7-3. PLLC1 Revision Identification Register (REVID)
31
0
REV
R-4481 4400h
LEGEND: R = Read only; -n = value after reset
Table 7-5. PLLC1 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 4400h
Description
Peripheral revision ID for PLLC1.
7.3.3 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) latches the cause of the last reset. If multiple reset sources are
asserted simultaneously, RSTYPE records the reset source that deasserts last. If multiple reset sources
are asserted and deasserted simultaneously, RSTYPE latches the highest priority reset source. RSTYPE
is shown in Figure 7-4 and described in Table 7-6.
Figure 7-4. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
PLLSWRST
XWRST
POR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-3
2
1
0
102
Field
Reserved
Value
0
PLLSWRST
Description
Reserved
PLL software reset.
0
PLL soft reset was not the last reset to occur.
1
PLL soft was the last reset to occur.
XWRST
External warm reset.
0
External warm reset was not the last reset to occur.
1
External warm reset was the last reset to occur.
POR
Power on reset.
0
Power On Reset (POR) was not the last reset to occur.
1
Power On Reset (POR) was the last reset to occur.
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7.3.4 PLLC0 Reset Control Register (RSCTRL)
The reset control register (RSCTRL) allows the device to perform a software-initiated reset. Before writing
to the SWRST bit, the register must be unlocked by writing the key value of 5A69h to the KEY bit field.
The KEY bit field reads back as Ch when the register is unlocked; any other key value is invalid and
indicates that the register is locked. Any write to the register following a successful unlock relocks the
register. RSCTRL is shown in Figure 7-5 and described in Table 7-7.
Figure 7-5. Reset Control Register (RSCTRL)
31
17
16
Reserved
SWRST
R-0
R/W-1
15
0
KEY
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7. Reset Control Register (RSCTRL) Field Descriptions
Bit
31-17
16
15-0
Field
Reserved
Value
0
SWRST
KEY
Description
Reserved
PLL software reset. Register must be unlocked before writing to this bit. Writes are possible only
when qualified with a valid key.
0
In software reset
1
Not in software reset
0-FFFFh
RSCTRL unlock key. Key used to enable writes to RSCTRL.
3h
Register is locked when read value is 3h.
Ch
Register is unlocked when read value is Ch.
5A69h
RSCTRL unlock key
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7.3.5 PLLC0 Control Register (PLLCTL)
The PLLC0 control register (PLLCTL) is shown in Figure 7-6 and described in Table 7-8.
Figure 7-6. PLLC0 Control Register (PLLCTL)
31
16
Reserved
R-0
15
10
7
6
9
8
Reserved
EXTCLKSRC
CLKMODE
R-0
R/W-0
R/W-0
5
4
3
2
1
0
Reserved
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-8. PLLC0 Control Register (PLLCTL) Field Descriptions
Bit
31-10
9
8
Reserved
Value
0
EXTCLKSRC
Description
Reserved
External clock source selection.
0
Use OSCIN for the PLL bypass clock.
1
Use PLL1_SYSCLK3 for the PLL bypass clock.
CLKMODE
Reference clock selection.
0
Internal oscillator (crystal)
1
Square wave
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
7-6
2
Reserved
1
PLLPWRDN
0
104
Field
PLL0 reset.
0
PLL0 reset is asserted.
1
PLL0 reset is not asserted.
0
Reserved
PLL0 power-down.
0
PLL0 is operating.
1
PLL0 is powered-down.
PLLEN
PLL0 mode enables.
0
PLL0 is in bypass mode.
1
PLL0 mode is enabled, not bypassed.
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7.3.6 PLLC1 Control Register (PLLCTL)
The PLLC1 control register (PLLCTL) is shown in Figure 7-7 and described in Table 7-9.
Figure 7-7. PLLC1 Control Register (PLLCTL)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
6
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-9. PLLC1 Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
2
Reserved
1
PLLPWRDN
0
PLL1 reset.
0
PLL1 reset is asserted.
1
PLL1 reset is not asserted.
0
Reserved
PLL1 power-down.
0
PLL1 is operating.
1
PLL1 is powered-down.
PLLEN
PLL1 mode enables.
0
PLL1 is in bypass mode.
1
PLL1 mode is enabled, not bypassed.
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7.3.7 PLLC0 OBSCLK Select Register (OCSEL)
The PLLC0 OBSCLK select register (OCSEL) controls which clock is output on the CLKOUT pin so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 7-8 and described in Table 7-10.
Figure 7-8. PLLC0 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-10. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC0 OBSCLK source. Output on CLKOUT pin.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
106
17h
PLL0_SYSCLK1
18h
PLL0_SYSCLK2
19h
PLL0_SYSCLK3
1Ah
PLL0_SYSCLK4
1Bh
PLL0_SYSCLK5
1Ch
PLL0_SYSCLK6
1Dh
PLL0_SYSCLK7
1Eh
PLLC1 OBSCLK
1Fh
Disabled
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7.3.8 PLLC1 OBSCLK Select Register (OCSEL)
The PLLC1 OBSCLK select register (OCSEL) controls which clock is output on PLLC1 OBSCLK so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 7-9 and described in Table 7-11.
Figure 7-9. PLLC1 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC1 OBSCLK source.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL1_SYSCLK1
18h
PLL1_SYSCLK2
19h
PLL1_SYSCLK3
1A-1Fh Reserved
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7.3.9 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 7-10 and described in Table 7-12.
Figure 7-10. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PLLM
Value
0
0-1Fh
Description
Reserved
PLL multiplier select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV)
The PLLC0 pre-divider control register (PREDIV) is shown in Figure 7-11 and described in Table 7-13.
Figure 7-11. PLLC0 Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-14
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
108
Value
0
Description
Reserved
PLLC0 pre-divider enable.
0
PLLC0 pre-divider is disabled. Clock output from the PREDIV stage is disabled.
1
PLLC0 pre-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
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7.3.11 PLLC0 Divider 1 Register (PLLDIV1)
The PLLC0 divider 1 register (PLLDIV1) controls the divider for PLL0_SYSCLK1. PLLDIV1 is shown in
Figure 7-12 and described in Table 7-14.
Figure 7-12. PLLC0 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-14. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.3.12 PLLC1 Divider 1 Register (PLLDIV1)
The PLLC1 divider 1 register (PLLDIV1) controls the divider for PLL1_SYSCLK1. PLLDIV1 is shown in
Figure 7-13 and described in Table 7-15.
Figure 7-13. PLLC1 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
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7.3.13 PLLC0 Divider 2 Register (PLLDIV2)
The PLLC0 divider 2 register (PLLDIV2) controls the divider for PLL0_SYSCLK2. PLLDIV2 is shown in
Figure 7-14 and described in Table 7-16.
Figure 7-14. PLLC0 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
7.3.14 PLLC1 Divider 2 Register (PLLDIV2)
The PLLC1 divider 2 register (PLLDIV2) controls the divider for PLL1_SYSCLK2. PLLDIV2 is shown in
Figure 7-15 and described in Table 7-17.
Figure 7-15. PLLC1 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-17. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D2EN
14-5
Reserved
4-0
RATIO
110
Value
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
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7.3.15 PLLC0 Divider 3 Register (PLLDIV3)
The PLLC0 divider 3 register (PLLDIV3) controls the divider for PLL0_SYSCLK3. PLLDIV3 is shown in
Figure 7-16 and described in Table 7-18.
Figure 7-16. PLLC0 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-18. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
7.3.16 PLLC1 Divider 3 Register (PLLDIV3)
The PLLC1 divider 3 register (PLLDIV3) controls the divider for PLL1_SYSCLK3. PLLDIV3 is shown in
Figure 7-17 and described in Table 7-19.
Figure 7-17. PLLC1 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-0
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-19. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
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7.3.17 PLLC0 Divider 4 Register (PLLDIV4)
The PLLC0 divider 4 register (PLLDIV4) controls the divider for PLL0_SYSCLK4. PLLDIV4 is shown
inFigure 7-18 and described in Table 7-20.
Figure 7-18. PLLC0 Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-20. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D4EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 4 enable.
0
Divider 4 is disabled.
1
Divider 4 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4).
7.3.18 PLLC0 Divider 5 Register (PLLDIV5)
The PLLC0 divider 5 register (PLLDIV5) controls the divider for PLL0_SYSCLK5. PLLDIV5 is shown in
Figure 7-19 and described in Table 7-21.
Figure 7-19. PLLC0 Divider 5 Register (PLLDIV5)
31
16
Reserved
R-0
15
14
5
4
0
D5EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-21. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D5EN
14-5
Reserved
4-0
RATIO
112
Value
Description
Reserved
Divider 5 enable.
0
Divider 5 is disabled.
1
Divider 5 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
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7.3.19 PLLC0 Divider 6 Register (PLLDIV6)
The PLLC0 divider 6 register (PLLDIV6) controls the divider for PLL0_SYSCLK6. PLLDIV6 is shown in
Figure 7-20 and described in Table 7-22.
Figure 7-20. PLLC0 Divider 6 Register (PLLDIV6)
31
16
Reserved
R-0
15
14
5
4
0
D6EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-22. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D6EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 6 enable.
0
Divider 6 is disabled.
1
Divider 6 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.3.20 PLLC0 Divider 7 Register (PLLDIV7)
The PLLC0 divider 7 register (PLLDIV7) controls the divider for PLL0_SYSCLK7. PLLDIV7 is shown in
Figure 7-21 and described in Table 7-23.
Figure 7-21. PLLC0 Divider 7 Register (PLLDIV7)
31
16
Reserved
R-0
15
14
5
4
0
D7EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-23. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D7EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 7 enable.
0
Divider 7 is disabled.
1
Divider 7 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).
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7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)
The PLLC0 oscillator divider 1 register (OSCDIV) controls the divider for PLLC0 OBSCLK, dividing down
the clock selected as the PLLC0 OBSCLK source. The PLLC0 OBSCLK is connected to the CLKOUT pin.
The OSCDIV is shown in Figure 7-22 and described in Table 7-24.
Figure 7-22. PLLC0 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-24. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC0 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC0 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)
The PLLC1 oscillator divider 1 register (OSCDIV) controls the divider for PLLC1 OBSCLK, dividing down
the clock selected as the PLLC1 OBSCLK source. The PLLC1 OBSCLK signal may be selected as the
output on the CLKOUT pin. The OSCDIV is shown in Figure 7-23 and described in Table 7-25.
Figure 7-23. PLLC1 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-25. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
31-16
15
Field
Reserved
0
OD1EN
14-5
Reserved
4-0
RATIO
114
Value
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC1 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC1 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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7.3.23 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 7-24 and described in Table 7-26.
Figure 7-24. PLL Post-Divider Control Register (POSTDIV)
31
16
Reserved
R-0
15
14
5
4
0
POSTDEN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
POSTDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Post-divider enable.
0
Post-divider is disabled.
1
Post-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
7.3.24 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) contains the command bit for phase alignment. A write of
1 initiates the command; a write of 0 clears the bit, but has no effect. PLLCMD is shown in Figure 7-25
and described in Table 7-27.
Figure 7-25. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 7-27. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for phase alignment.
0
Clear bit (no effect)
1
Phase alignment
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7.3.25 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 7-26 and described in Table 7-28.
Figure 7-26. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
STABLE
Reserved
GOSTAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-28. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
116
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation. If 1, indicates GO operation is in progress.
0
GO operation is not in progress.
1
GO operation is in progress.
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7.3.26 PLLC0 Clock Align Control Register (ALNCTL)
The PLLC0 clock align control register (ALNCTL) indicates which PLL0_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 7-27 and described in Table 7-29.
Figure 7-27. PLLC0 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-3h
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-29. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
3h
ALN7
Description
Reserved
PLL0_SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN6
PLL0_SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN5
PLL0_SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN4
PLL0_SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN3
PLL0_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL0_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL0_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.3.27 PLLC1 Clock Align Control Register (ALNCTL)
The PLLC1 clock align control register (ALNCTL) indicates which PLL1_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 7-28 and described in Table 7-30.
Figure 7-28. PLLC1 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-30. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-3
2
1
0
118
Field
Reserved
Value
0
ALN3
Description
Reserved
PLL1_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL1_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL1_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC0 PLLDIV ratio change status register (DCHANGE) indicates if the PLL0_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 7-29 and described in Table 7-31.
Figure 7-29. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-31. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
0
SYS7
Description
Reserved
PLL0_SYSCLK7 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS6
PLL0_SYSCLK6 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS5
PLL0_SYSCLK5 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS4
PLL0_SYSCLK4 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS3
PLL0_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL0_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL0_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC1 PLLDIV ratio change status register (DCHANGE) indicates if the PLL1_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 7-30 and described in Table 7-32.
Figure 7-30. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-32. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-3
2
1
0
120
Field
Reserved
Value
0
SYS3
Description
Reserved
PLL1_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL1_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL1_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.3.30 PLLC0 Clock Enable Control Register (CKEN)
The PLLC0 clock enable control register (CKEN) controls the PLLC0 OBSCLK and AUXCLK clock. CKEN
is shown in Figure 7-31 and described in Table 7-33.
Figure 7-31. PLLC0 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-33. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK enable. Actual PLLC0 OBSCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 OBSCLK is disabled.
1
PLLC0 OBSCLK is enabled. For PLLC0 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC0 oscillator divider 1 register (OSCDIV) must be set to 1.
AUXEN
AUXCLK enable. Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 AUXCLK is disabled.
1
PLLC0 AUXCLK is enabled.
7.3.31 PLLC1 Clock Enable Control Register (CKEN)
The PLLC1 clock enable control register (CKEN) controls the PLLC1 OBSCLK clock. CKEN is shown in
Figure 7-32 and described in Table 7-34.
Figure 7-32. PLLC1 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-34. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK enable. Actual PLLC1 OBSCLK status is shown in the PLLC1 clock status register (CKSTAT).
0
PLLC1 OBSCLK is disabled.
1
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1.
0
Reserved
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7.3.32 PLLC0 Clock Status Register (CKSTAT)
The PLLC0 clock status register (CKSTAT) indicates the PLLC0 OBSCLK and AUXCLK on/off status. The
PLL0_SYSCLK status is shown in the PLLC0 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 7-33 and described in Table 7-35.
Figure 7-33. PLLC0 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R-1
R-1
LEGEND: R = Read only; -n = value after reset
Table 7-35. PLLC0 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
122
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK on status. PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC0 clock enable control register (CKEN).
0
PLLC0 OBSCLK is off.
1
PLLC0 OBSCLK is on.
AUXEN
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control
register (CKEN).
0
PLLC0 AUXCLK is off.
1
PLLC0 AUXCLK is on.
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7.3.33 PLLC1 Clock Status Register (CKSTAT)
The PLLC1 clock status register (CKSTAT) indicates the PLLC1 OBSCLK on/off status. The
PLL1_SYSCLK status is shown in the PLLC1 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 7-34 and described in Table 7-36.
Figure 7-34. PLLC1 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-2h
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-36. PLLC1 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK on status. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC1 clock enable control register (CKEN).
0
PLLC1 OBSCLK is off.
1
PLLC1 OBSCLK is on.
0
Reserved
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7.3.34 PLLC0 SYSCLK Status Register (SYSTAT)
The PLLC0 SYSCLK status register (SYSTAT) indicates the PLL0_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC0 PLLDIVn.
SYSTAT is shown in Figure 7-35 and described in Table 7-37.
Figure 7-35. PLLC0 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-1
7
6
5
4
3
2
1
0
Reserved
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-37. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-7
Reserved
6
SYS7ON
5
4
3
2
1
0
124
Value
3h
Description
Reserved
PLL0_SYSCLK7 on status.
0
Off
1
On
SYS6ON
PLL0_SYSCLK6 on status.
0
Off
1
On
SYS5ON
PLL0_SYSCLK5 on status.
0
Off
1
On
SYS4ON
PLL0_SYSCLK4 on status.
0
Off
1
On
SYS3ON
PLL0_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL0_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL0_SYSCLK1 on status.
0
Off
1
On
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7.3.35 PLLC1 SYSCLK Status Register (SYSTAT)
The PLLC1 SYSCLK status register (SYSTAT) indicates the PLL1_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC1 PLLDIVn.
SYSTAT is shown in Figure 7-36 and described in Table 7-38.
Figure 7-36. PLLC1 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-0
7
2
1
0
Reserved
3
SYS3ON
SYS2ON
SYS1ON
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
SYS3ON
1
0
Value
0
Description
Reserved
PLL1_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL1_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL1_SYSCLK1 on status.
0
Off
1
On
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7.3.36 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 7-37 and described in
Table 7-39. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 7-37. Emulation Performance Counter 0 Register (EMUCNT0)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-39. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit
31-0
Field
Value
COUNT
0-FFFF FFFFh
Description
Counter value for lower 64-bits.
7.3.37 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 7-38 and described in
Table 7-40. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 7-38. Emulation Performance Counter 1 Register (EMUCNT1)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit
31-0
126
Field
COUNT
Value
0-FFFF FFFFh
Description
Counter value for upper 64-bits.
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Chapter 8
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Power and Sleep Controller (PSC)
Topic
...........................................................................................................................
8.1
8.2
8.3
8.4
8.5
8.6
Introduction .....................................................................................................
Power Domain and Module Topology ..................................................................
Executing State Transitions ...............................................................................
IcePick Emulation Support in the PSC ................................................................
PSC Interrupts..................................................................................................
PSC Registers ..................................................................................................
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128
132
133
133
136
127
Introduction
8.1
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Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupts, a state machine for each
peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and
provides clock and reset control. Many of the operations of the PSC are transparent to user (software),
such as power on and reset control. However, the PSC module(s) also provide you with interface to
control several important power, clock and reset operations. The module level power, clock and reset
operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for DSP memories)
• Supports IcePick emulation features: power, clock and reset
8.2
Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of:
• an Always On power domain
• an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in
the DSP subsystem
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 8-1 and Table 8-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 8.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have an LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
NOTE: There are no LPSCs for peripherals in the Async2 clock domain (this includes RTC,
Timer64P0/P1, and I2C0); from a power savings stand point, clock-gating these peripherals
does not result in significant power savings.
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Table 8-1. PSC0 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_0 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3_0 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3_0 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4-8
Not Used
—
—
—
9
UART0
AlwaysON (PD0)
SwRstDisable
—
10
Not Used
—
—
—
11
SCR1 (BR4)
AlwaysON (PD0)
Enable
Yes
12
SCR2 (BR3, BR5, BR6)
AlwaysON (PD0)
Enable
Yes
13-14
Not Used
—
—
—
15
DSP
PD_DSP (PD1)
Enable
—
Table 8-2. PSC1 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_1 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1-2
Not Used
—
—
—
1-2
Not Used
—
—
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
HPI
AlwaysON (PD0)
SwRstDisable
—
5
Not Used
—
—
—
6
DDR2/mDDR
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 (+ McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8-9
Not Used
—
—
—
10
SPI1
AlwaysON (PD0)
SwRstDisable
—
11-14
Not Used
—
—
—
15
McBSP1 (+ McBSP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
16
Not Used
—
—
—
17
eHRPWM0/1
AlwaysON (PD0)
SwRstDisable
—
18-19
Not Used
—
—
—
20
eCAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
EDMA3_1 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR F0
AlwaysON (PD0)
Enable
Yes
25-26
Not Used
—
—
—
27
SCR F6
AlwaysON (PD0)
Enable
Yes
28
SCR F7
AlwaysON (PD0)
Enable
Yes
29
SCR F8
AlwaysON (PD0)
Enable
Yes
30-31
Not Used
—
—
—
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8.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In this device, for both PSC0 and PSC1, the Always ON domain (or PD0 power domain), is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state (See details on
PDCTL register).
Additionally, for both PSC0 and PSC1, the PD1 power domains, the internal/pseudo power domain can
either be in the ON state or OFF state. Furthermore, for these power domains the transition from ON to
OFF state is further qualified by the PSC0/1.PDCTL1.PDMODE settings. The PDCTL1.PDMODE settings
determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
NOTE: Currently programming the PD1 power domain state to OFF is not supported. You should
leave both the PDCTL1.NEXT and PDCTL1.PDMODE values at default/power on reset
values.
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of
the device. There is no capability to individually remove voltage/power from the DSP power
domains .
8.2.2 Module States
The PSC defines several possible states for a module. This various states are essentially a combination of
the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The various
module states are defined in Table 8-3.
The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in
Auto Sleep mode, it will transition back to the clock disabled state (automatically sleep) after servicing the
internal read/write access request where as in Auto Wake mode, on receiving the first internal read/write
access request, the module will permanently transition from the clock disabled to clock enabled state
(automatically wake).
When the module state is programmed to Disable, SwRstDisable, Auto Sleep or Auto Wake modes,
where in the module clocks are off/disabled, an external event or I/O request cannot enable the clocks.
For the module to appropriately respond to such external request, it would need to be reconfigured to the
Enable state.
8.2.2.1
Auto Sleep/Wake Only Configurations and Limitation
NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes. If the
module clocks need to gated/disabled for power savings, you should program the module
state to Disable. For Auto Sleep/Auto Wake Only modules, disabling the clock is not
supported and they should be kept in their default “Enable” state.
Table 8-1 and Table 8-2 each have a column to indicate whether or not the LPSC configuration for a
module is Auto Sleep/Wake Only. Modules that have a “Yes” marked for the Auto Sleep/Wake Only
column can be programmed in software to be in Enable, Auto Sleep and Auto Wake states only; that is, if
the software tries to program these modules to Disable, SyncReset, or SwRstDisable state the power
sleep controller ignores these transition requests and transitions the module state to Enable.
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8.2.2.2
Local Reset
In addition to module reset, the following module can be reset using a special local reset that is also a part
of the PSC module control for resets.
• DSP: When the DSP local reset is asserted the DSP internal memories (L1P, L1D and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of DSP subsystem, as the DSP
module reset would. Local Reset is useful in cases where the DSP is in enable or disable state; since
when module is in SyncReset or SwRstDisable state the module reset is asserted, and the module
reset takes precedence over the local reset.
The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the
module that supports local reset):
1. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset.
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset.
If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted.
Table 8-3. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has
its clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has
its module clock off. This state is typically used for disabling a module
clock to save power. This device is designed in full static CMOS, so when
you stop a module clock, it retains the module’s state. When the clock is
restarted, the module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it
has its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it
has its clock disabled. After initial power-on, several modules come up in
the SwRstDisable state. Generally, software is not expected to initiate this
state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it
can “automatically” transition to “Enable” state whenever there is an
internal read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re deasserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data. See Section 8.2.2.1 for
additional considerations, constraints, limitations around this mode.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from
then on (with module reset re de-asserted and module clock on), without
any software intervention. The transition from sleep to enabled state has
some cycle latency associated with it. It is not envisioned to use this mode
when peripherals are fully operational and moving data. See
Section 8.2.2.1 for additional considerations, constraints, limitations around
this mode.
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Executing State Transitions
This section describes how to execute the state transitions modules.
8.3.1 Power Domain State Transitions
This device consists of two types of domain (in each PSC controller):
• Always On domain(s)
• pseudo/RAM power domain(s)
The Always On power domains are always in the ON state when the chip is powered on. You are not
allowed to change the power domain state to OFF.
The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with
these domains (L1/L2 for PD_DSP in PSC0) so that these RAMs can run in lower power sleep modes via
the power sleep controller.
NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported;
therefore, these domains and the RAM should be left in their default power on state.
As mentioned in Section 8.2, the pseudo/RAM power domains are powered down internally,
and in this context powering down does not imply removing the core voltage from pins
externally.
8.3.2 Module State Transitions
This section describes the procedure for transitioning the module state (clock and reset control). Note that
some peripherals have special programming requirements and additional recommended steps you must
take before you can invoke the PSC module state transition. See the individual peripheral user guides for
more details. For example, the external memory controller requires that you first place the SDRAM
memory in self-refresh mode before you invoke the PSC module state transitions, if you want to maintain
the memory contents.
The following procedure is directly applicable for all modules that are controlled via the PSC (shown in
Table 8-1 and Table 8-2), except for the core(s). To transition the DSP module state, there are additional
system considerations and constraints that you should be aware of. These system considerations and the
procedure for transitioning the DSP module state are described in details in the Power Management
chapter.
NOTE: In the following procedure, x is 0 for modules in PD0 (Power Domain 0 or Always On
domain) and x is 1 for modules in PD1 (Power Domain 1). See Table 8-1 and Table 8-2 for
power domain associations.
The procedure for module state transitions is:
1. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), Enable (3h), Auto
Sleep (4h) or Auto Wake (5h).
NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[x] bit in PTCMD in a later step.
3. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
after the GOSTAT[x] bit in PTSTAT is cleared to 0.
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8.4
IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the
state of power domains and modules. This IcePick support only applies to the following module:
• DSP [MDCTL15]
In particular, Table 8-4 shows IcePick emulation commands recognized by the PSC.
Table 8-4. IcePick Emulation Commands
Power On and
Enable Features
Power On and Enable Descriptions
Reset Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the
module’s local reset.
Force Power
Allows emulation to force the power domain into
an on state. Not applicable as AlwaysOn power
domain is always on.
Wait Reset
Allows emulation to keep local
reset asserted for an extended
period of time after software
initiates local reset de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block
software initiated local and
module resets.
NOTE: When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in
MDCTLn, as set by software.
8.5
PSC Interrupts
The PSC has an interrupt that is tied to the core interrupt controller. This interrupt is named PSCINT in the
interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.
8.5.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Power Domain Emulation Event (applies to pseudo/RAM power domain only)
• Module State Emulation event
• Module Local Reset Emulation event
These interrupt events are summarized in Table 8-5 and described in more detail in this section.
Table 8-5. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Enable Bit
Interrupt Condition
PDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the power domain state
MDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the module state
MDCTLn
EMURSTIE
Interrupt occurs when the emulation tries to alter the module’s local reset
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the userprogrammed state in the NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the
modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed.
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Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTATn. In particular, a power
domain emulation event occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
• When force power is asserted by emulation and power domain is not already in the on state
• When force active is asserted by emulation and power domain is not already in the on state
NOTE:
8.5.1.2
Putting the pseudo/RAM power domain associated with the DSP (PD_DSP) to the off state
currently is not supported.
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTATn). In particular, a module state emulation event
occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
• When force active is asserted by emulation and module is not already in the enable state
8.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTATn). In particular, a module local reset emulation
event occurs under the following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset
• When wait reset is asserted by emulation
• When block reset is asserted by emulation and software attempts to change the state of local reset
8.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support, as specified in
Section 8.4).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled in the DSP interrupt controller. For details on the DSP
interrupt controller, see the DSP Subsystem chapter.
The PSC interrupt status bits are:
• For DSP:
– The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).
– The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain
associated with DSP memories.
The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.
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The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register. When set, this bit forces the
PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set)
when the ALLEV bit in the INTEVAL is set to 1, the PSC interrupt is re-asserted to the interrupt controller.
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do
not miss any PSC interrupts.
See Section 8.6 for a description of the PSC registers.
8.5.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt:
1. Set the EMUIHBIE bit in PDCTLn, the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the
interrupt events that you want.
NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event
becomes active.
2. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. To
interrupt the CPU, PSCn_ALLINT must be enabled in the device interrupt controller. See the DSP
Subsystem chapter for more information on interrupts.
The CPU enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the P[n] bit in PERRPR, and/or the M[n] bit in MERRPR0, the M[n] bit in MERRPR1, to
determine the source of the interrupt(s).
2. For each active event that you want to service:
(a) Read the event status bits in PDSTATn and MDSTATn, depending on the status bits read in the
previous step to determine the event that caused the interrupt.
(b) Service the interrupt as required by your application.
(c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status.
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt
controller, if there are still any active interrupt events.
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PSC Registers
Table 8-6 lists the memory-mapped registers for the PSC0 and Table 8-7 lists the memory-mapped
registers for the PSC1.
Table 8-6. Power and Sleep Controller 0 (PSC0) Registers
Address
Acronym
Register Description
01C1 0000h
REVID
Revision Identification Register
Section 8.6.1
Section
01C1 0018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01C1 0040h
MERRPR0
Module Error Pending Register 0 (module 0-15)
Section 8.6.3
01C1 0050h
MERRCR0
Module Error Clear Register 0 (module 0-15)
Section 8.6.5
01C1 0060h
PERRPR
Power Error Pending Register
Section 8.6.7
01C1 0068h
PERRCR
Power Error Clear Register
Section 8.6.8
01C1 0120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01C1 0128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01C1 0200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01C1 0204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01C1 0300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01C1 0304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01C1 0400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01C1 0404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01C1 0800h01C1 083Ch
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15)
Section 8.6.17
01C1 0A00h01C1 0A3Ch
MDCTL0MDCTL15
Module Control n Register (modules 0-15)
Section 8.6.18
Table 8-7. Power and Sleep Controller 1 (PSC1) Registers
136
Address
Acronym
Register Description
01E2 7000h
REVID
Revision Identification Register
Section 8.6.1
01E2 7018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01E2 7040h
MERRPR0
Module Error Pending Register 0 (module 0-31)
Section 8.6.4
01E2 7050h
MERRCR0
Module Error Clear Register 0 (module 0-31)
Section 8.6.6
01E2 7060h
PERRPR
Power Error Pending Register
Section 8.6.7
01E2 7068h
PERRCR
Power Error Clear Register
Section 8.6.8
01E2 7120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01E2 7128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01E2 7200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01E2 7204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01E2 7300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01E2 7304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01E2 7400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01E2 7404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01E2 7800h01E2 787Ch
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31)
Section 8.6.17
01E2 7A00h01E2 7A7Ch
MDCTL0MDCTL31
Module Control n Register (modules 0-31)
Section 8.6.19
Power and Sleep Controller (PSC)
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8.6.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 8-1 and described in Table 8-8.
Figure 8-1. Revision Identification Register (REVID)
31
0
REV
R-4482 5A00h
LEGEND: R = Read only; -n = value after reset
Table 8-8. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4482 5A00h
Description
Peripheral revision ID.
8.6.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 8-2 and described in Table 8-9.
Figure 8-2. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 8-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt (PSCn_ALLINT).
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 8-3 and described in Table 810.
Figure 8-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31
16
Reserved
R-0
15
14
0
M[15]
Reserved
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit
31-16
15
14-0
Field
Reserved
Value
0
M[15]
Reserved
Description
Reserved
Module interrupt status bit for module 15 (DSP).
0
Module 15 does not have an error condition.
1
Module 15 has an error condition. See the module status 15 register (MDSTAT15) for the error
condition.
0
Reserved
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 8-4.
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
138
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8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 8-5 and described in Table 8-11.
Figure 8-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31
16
Reserved
R-0
15
14
0
M[15]
Reserved
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit
31-16
15
14-0
Field
Reserved
Value
0
M[15]
Reserved
Description
Reserved
Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 15 register (MDSTAT15).
0
A write of 0 has no effect.
1
A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15.
0
Reserved
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 8-6.
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 8-7 and described in Table 8-12.
Figure 8-7. Power Error Pending Register (PERRPR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
RAM/Pseudo (PD1) power domain interrupt status.
0
RAM/Pseudo power domain does not have an error condition.
1
RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0
Reserved
8.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 8-8 and described in Table 8-13.
Figure 8-8. Power Error Clear Register (PERRCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit
31-2
1
0
140
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0
A write of 0 has no effect.
1
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0
Reserved
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8.6.9 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 8-9 and described in Table 814.
Figure 8-9. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-14. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GO[1]
Description
Reserved
RAM/Pseudo (PD1) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
PDCTL.NEXT for this domain, and MDCTL.NEXT for all the modules residing on this domain). If any of
the NEXT fields are not matching the corresponding current state (PDSTAT.STATE, MDSTAT.STATE),
the PSC will transition those respective domain/modules to the new NEXT state.
GO[0]
Always ON (PD0) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching
the corresponding current state (MDSTAT.STATE), the PSC will transition those respective
domain/modules to the new NEXT state.
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8.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 8-10 and described in Table 815 .
Figure 8-10. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
142
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
RAM/Pseudo (PD1) power domain transition status.
0
No transition in progress.
1
RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
GOSTAT[0]
Always ON (PD0) power domain transition status.
0
No transition in progress.
1
Modules in Always ON power domain are transitioning. Always On power domain is transitioning.
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8.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 8-11 and described in Table 8-16.
Figure 8-11. Power Domain 0 Status Register (PDSTAT0)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Reserved
Emulation alters domain state.
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.12 Power Domain 1 Status Register (PDSTAT1)
The power domain 1 status register (PDSTAT1) is shown in Figure 8-12 and described in Table 8-17.
Figure 8-12. Power Domain 1 Status Register (PDSTAT1)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Emulation alters domain state.
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
144
Reserved
0
POR
7-5
Description
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.13 Power Domain 0 Control Register (PDCTL0)
The power domain 0 control register (PDCTL0) is shown in Figure 8-13 and described in Table 8-18.
Figure 8-13. Power Domain 0 Control Register (PDCTL0)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
Reserved
9
EMUIHBIE
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
0-Fh
Power down mode.
0-Eh
Reserved
Fh
11-10
Description
0
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
NEXT
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect
since internally this power domain always remains in the on state.
0
Power domain off.
1
Power domain on.
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8.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 8-14 and described in Table 8-19.
Figure 8-14. Power Domain 1 Control Register (PDCTL1)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
0-Fh
Core off, RAM array retention, RAM periphery off (deep sleep).
Reserved
4h
Core retention, RAM array off, RAM periphery off.
5h
Core retention, RAM array retention, RAM periphery off (deep sleep).
Reserved
8h
Core on, RAM array off, RAM periphery off.
9h
Core on, RAM array retention, RAM periphery off (deep sleep).
Ah
Core on, RAM array retention, RAM periphery off (light sleep).
Bh
Core on, RAM array retention, RAM periphery on.
Fh
EMUIHBIE
Power down mode.
Core off, RAM array off, RAM periphery off.
Ch-Eh
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
1h
6h-7h
9
Reserved
0
2h-3h
11-10
Description
0
Reserved
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
146
NEXT
User-desired power domain next state.
0
Power domain off.
1
Power domain on.
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8.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 8-15 and described in Table 820.
Figure 8-15. Power Domain 0 Configuration Register (PDCFG0)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.16 Power Domain 1 Configuration Register (PDCFG1)
The power domain 1 configuration register (PDCFG1) is shown in Figure 8-16 and described in Table 821.
Figure 8-16. Power Domain 1 Configuration Register (PDCFG1)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
148
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.17 Module Status n Register (MDSTATn)
The module status n register (MDSTATn) is shown in Figure 8-17 and described in Table 8-22.
Figure 8-17. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
Reserved
MCKOUT
Rsvd
MRST
LRSTDONE
LRST
Reserved
7
6
5
STATE
0
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-22. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in the module control
15 register (MDCTL15).
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL15. If you desire to
generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL15.
Emulation alters module reset. This bit applies to DSP module (module 15). This field is 0 for all
other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state. If you desire to generate a PSCINT upon this
event, you must set the EMURSTIE bit in the module control 15 register (MDCTL15).
0
Reserved
Module clock output status. Shows status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to DSP module (module 15). This field is 1 for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Reserved
0
LRSTDONE
7-6
Description
Emulation alters module state. This bit applies to DSP module (module 15). This field is 0 for all
other modules.
EMURST
15-13
9
Value
Module local reset status. This bit applies to DSP module (module 15).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
Module state status: indicates current module status.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
Indicates transition
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8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)
The PSC0 module control n register (MDCTLn) is shown in Figure 8-18 and described in Table 8-23.
Figure 8-18. PSC0 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
10
9
8
Reserved
11
EMUIHBIE
EMURSTIE
LRST
7
Reserved
3
2
NEXT
0
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 15
register (MDCTL15), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-11
Reserved
10
EMUIHBIE
9
8
Force is disabled.
1
Force is enabled.
0
Reserved
Interrupt enable for emulation alters module state. This bit applies to DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
EMURSTIE
Interrupt enable for emulation alters reset. This bit applies to DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
LRST
7-3
Reserved
2-0
NEXT
150
0
Module local reset control. This bit applies to DSP module (module 15).
0
Assert local reset
1
De-assert local reset
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
Power and Sleep Controller (PSC)
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8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn)
The PSC1 module control n register (MDCTLn) is shown in Figure 8-19 and described in Table 8-24.
Figure 8-19. PSC1 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
3
2
0
Reserved
NEXT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 15
register (MDCTL15), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-3
Reserved
2-0
NEXT
0
Force is disabled.
1
Force is enabled.
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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Power Management
Topic
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
152
...........................................................................................................................
Introduction .....................................................................................................
Power Consumption Overview ...........................................................................
PSC and PLLC Overview ...................................................................................
Features ..........................................................................................................
Clock Management ...........................................................................................
DSP Sleep Mode Management............................................................................
RTC-Only Mode ................................................................................................
Dynamic Voltage and Frequency Scaling (DVFS)..................................................
Deep Sleep Mode ..............................................................................................
Additional Peripheral Power Management Considerations.....................................
Power Management
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153
153
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156
156
158
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9.1
Introduction
Power management is an important aspect for most embedded applications. For several applications and
target markets, there may be a specific power budget and requirements to minimize power consumption
for both power supply sizing and battery life considerations. Additionally, lower power consumption results
in more optimal and efficient designs from cost, design, and energy perspectives. This device has several
means of managing the power consumption. This chapter discusses the various power management
features.
9.2
Power Consumption Overview
Power consumed by semiconductor devices has two components: dynamic and static. This can be shown
as:
Ptotal = Pdynamic + Pstatic
The dynamic power is the power consumed to perform work when the device is in active modes (clocks
applied, busses, and I/O switching), that is, analog circuits changing states. The dynamic power is defined
by:
Pdynamic = Capacitance × Voltage2 × Frequency
From the above formula, the dynamic power scales with the clock frequency (device/module frequency for
core operations and switching frequency for I/O). Dynamic power can be reduced by controlling the clocks
in such a way as to either operate at a clock setting just high enough to complete the required operation in
the required timeline or to run at a clock setting until the work is complete and then drastically reduce the
clock frequency or cut off the clocks until additional work must be performed.
In the formula, the dynamic power varies with the voltage squared, so the voltage of operations has
significant impact on overall power consumption and, thus, on the battery life. Dynamic power can be
reduced by scaling the operating voltage, when the performance requirements are not that high and the
device can be operated at a corresponding lower frequency.
The capacitance is the capacitance of the switching nodes, or the load capacitances on the switching I/O
pins.
The static power, as the name suggests, is independent of the switching frequency of the logic. It can be
shown as:
Pstatic = f(leakage current)
It is essentially a function of the “leakage”, or the power consumed by the logic when it is not switching or
is not performing any work. Leakage current is dependent mostly on the manufacturing process used, the
size of the die, etc. Leakage current is unavoidable while power is applied and scales roughly with the
operating junction temperatures. Leakage power can only be avoided by removing power completely from
a device or subsystem. The static power consumption plays a significant role in the Standby Modes (when
the application is not running and in a dormant state) and plays an important role in the battery life for
portable applications, etc.
9.3
PSC and PLLC Overview
The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling
of the clocks to the core and various peripheral modules. The PSC provides a granular support to turn
on/off clocks on a module by module basis. Similarly, the two PLL controllers (PLLC0 and PLLC1) play an
important role in device and module clock generation, and manage the frequency scaling operations for
the device. Together these modules play a significant role in managing the clocks from a power
management feature standpoint. For detailed information on the PSC, see the Power and Sleep Controller
(PSC) chapter. For detailed information on the PLLC0 and PLLC1, see the Device Clocking chapter and
the Phase-Locked Loop Controller (PLLC) chapter.
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Features
9.4
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Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 9-1 describes the power management features.
Table 9-1. Power Management Features
Power Management
Description
Features
PLL bypass and powerdown
Both PLLs can be powered-down and run in
bypass mode when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON
Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic power consumption of the
core and I/O (if any free running I/O clocks).
DSP subsystem
sleep mode
The DSP CPU can be put in sleep (IDLE) mode.
RTC-only mode
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Dynamic Voltage and
Frequency Scaling
(DVFS)
The operating voltage and frequency of the device
can be dynamically scaled to meet the
requirements of the application.
Clock Management
Core Sleep Management
Reduces the dynamic power consumption.
Voltage Management
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Dynamic Voltage and Frequency Scaling
Reduces the dynamic power consumption of the
core and I/O as well as standby power
System/Device Sleep Management
Deep Sleep Mode
All internal clocks of the device can be turned
on/off at the OSCIN level. The deep sleep function
can be controlled externally through the
DEESLEEP pin or internally through the
RTC_ALARM pin.
Reduces the dynamic power consumption of the
core and I/O.
DDR2/mDDR selfrefresh mode
Allows memory to retain its contents while the rest
of the system is powered down.
mDDR and DDR2 can be clock gated to reduce the
dynamic power consumption or the entire device
can be powered down to reduce the static power
consumption.
LVCMOS I/O buffer
receiver disable
LVCMOS I/O buffer receivers are disabled.
Minimizes the I/O power consumption.
Internal pull-up and pulldown resistor control
The internal pull-ups and pull-downs are
enabled/disabled by groups.
Reduces the I/O leakage power.
Peripheral I/O Power Management
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9.5
Clock Management
9.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
NOTE: To preserve the state of the module, the module state in the PSC must be set to Disable. In
this state, the module reset is not asserted and only the module clock is turned off.
Furthermore, special consideration must be given to DSP clock on/off. The procedure to turn the core
clock on/off is further described in .
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module, when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
9.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
9.5.3 PLL Bypass and Power Down
You can bypass each PLL in this device. Bypassing the PLL sends a bypass clock instead of the PLL
VCO output (PLLOUT) to the system clocks of the PLLC. For PLLC0, the bypass clock is selected from
either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. For PLLC1, the bypass clock is always
OSCIN. The OSCIN frequency is typically, at most, up to 50 MHz.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. This can lower the
overall dynamic power consumption, which is linearly proportional to the frequency.
When the PLL controller is placed in bypass mode, the PLL retains its frequency lock. This allows you to
switch between bypass mode and PLL mode without having to wait for the PLL to relock. However,
keeping the PLL locked consumes power. You can also power-down the PLL when bypassing it to
minimize the overall power consumed by the PLL module. The advantage of bypassing the PLL without
powering it down is that you do not have to incur the PLL lock time when switching back to a normal
operating level.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
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DSP Sleep Mode Management
9.6.1 C674x DSP CPU Sleep Mode
The DSP CPU can be put in a low-power state by executing the IDLE instruction. For information on the
IDLE instruction, see the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8).
9.6.2 C674x Megamodule Sleep Mode
The IDLE instruction is used as part of the procedure for shutting down the entire C674x megamodule, by
the power-down controller (PDC) module. In shutting down the entire C674x megamodule, the PDC can
internally clock gate off the following components of the megamodule and internal memories of the DSP
subsystem:
• C674x CPU
• Level 1 Program Memory Controller (PMC)
• Level 1 Data Memory Controller (DMC)
• Level 2 Unified Memory Controller (UMC)
• Extended Memory Controller (EMC)
• L1P Memory
• L1D Memory
• L2 Memory
Putting the entire C674x megamodule into the low-power sleep mode is typically more useful and saves a
lot more power, as compared to just executing the IDLE instruction to put only the CPU in idle mode.
For information on putting the C674x megamodule in the low-power mode using the PDC, see the
TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
9.7
RTC-Only Mode
In real-time clock (RTC)-only mode, the RTC is powered on and the rest of the device is completely
powered off (all supplies except the RTC supply are removed). In this mode, the RTC is fully functional
and keeps track of date, hours, minutes, and seconds. In this mode, the overall power consumption would
be significantly lower, as voltage from the rest of the core and I/O logic can be completely removed,
eliminating most of the active and static power of the device, except for what is consumed by the RTC
module, running at 32 kHz.
NOTE: To put the device in RTC-only mode, there is no software control sequence. You can put the
device in the RTC-only mode by removing the power supply from all core and I/O logic,
except for the RTC core logic supply (RTC_CVDD). During wake up, all power sequencing
requirements described in the device-specific data manual must be followed.
Some limitations apply in the RTC-only mode. First, the RTC_ALARM pin is not available as an option for
use as a control to signal an external power supply to reapply power to the rest of the device. This is
because the RTC_ALARM pin is powered by the I/O supply that is powered down in RTC-only mode.
Second, in RTC-only mode, only the RTC register contents are preserved, all other internal memory and
register contents are lost. Mobile DDR and DDR2 contents can be preserved through the use of selfrefresh (see Section 9.9.2). However, software must be in place to restore the context of the device, for
example, reinitialize internal registers, setup cache memory configurations, interrupt vectors, etc.
9.8
Dynamic Voltage and Frequency Scaling (DVFS)
Dynamic voltage and frequency scaling (DVFS) consists of minimizing the idle time of the system. The
DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a task to be
performed in the required amount of time. This reduces the total power consumption of the device while
still meeting task requirements. DVFS requires control over the clock frequency and the operating voltage
of the device elements. By intelligently switching these elements to their optimal operating points, it is
possible to minimize the power consumption of the device for a given task.
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For reasons related to the device (clock architecture, process, etc.), DVFS is used only for a few discrete
steps, not over a continuum of voltage and frequency values. Each step, or operating performance point
(OPP), is composed of a voltage and frequency pair. For an OPP, the frequency corresponds to the
maximum frequency allowed at a voltage, or reciprocally; the voltage corresponds to the minimum voltage
allowed for a frequency. See your device data manual for a list of the OPPs supported by the device.
When applying DVFS, a processor or system always runs at the lowest OPP that meets the performance
requirement at a given time. You determine the optimal OPP for a given task and then switch to that OPP
to save power.
9.8.1 Frequency Scaling Considerations
The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1).
Through a series of multipliers and dividers you can change the frequencies of various clocks throughout
the device. See the Device Clocking chapter for information on the clock architecture of the device and
see the Phase-Locked Loop Controller (PLLC) chapter for information on the PLL controllers. A few things
must be noted when changing the various internal frequencies of the device:
• Changing the SYSCLK frequency
The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier. A series of dividers
divide PLLOUT to generate the various device SYSCLKs.
To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK
divider ratio. When changing the PLL multiplier, you must put the PLL controller in bypass mode while
the PLL multiplier value is modified and a lock on the new frequency is reached. The lock time is given
in the device data manual. When changing the divider ratios it is not required to put the PLL controller
in bypass mode.
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the
PLL. However, the SYSCLK frequency will depend solely on the divider ratios used.
• SYSCLK domain fixed ratios
Certain SYSCLK domains need to operate at a fixed ratio with respect to the CPU clock. Care should
be taken to ensure that these fixed ratios are maintained. For additional details, see the Device
Clocking chapter.
• PLLC0 bypass clock
When switching the PLL multiplier, the PLL controller must be placed in bypass mode. Bypassing the
PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of
the PLL controller.
For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or
PLL1_SYSCLK3. For PLLC1, the bypass clock is always OSCIN. The OSCIN frequency is typically, at
most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity.
It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved
bandwidth during frequency scaling transitions. For this reason, the PLLC0 bypass clock can be set to
PLL1_SYSCLK3. This selection is made through the EXTCLKSRC bit in the PLLCTL register of
PLLC0.
• Peripheral immunity from CPU clock frequency changes
Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency.
The PLL0_AUXCLK is derived from OSCIN.
Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2.
Furthermore, PLL0_SYSCLK2 must always be /2 of the CPU clock frequency. To keep these
peripherals immune from changes in PLL0 frequency (such as when the CPU frequency is modified),
you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. PLL1 is mainly used to
clock the DDR2/mDDR memory controller.
When peripherals are immune to changes in the CPU clock frequency, their internal clock dividers do
not have to be adjusted for changes in their input clock frequencies.
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9.8.2 Voltage Scaling Considerations
The operating voltage of the device must be totally controlled through mechanisms outside the device. I2C
ports on the device can be used to communicate with external power management chips. A few things
must be noted when changing the operating voltage of the device:
• Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating
performance point (OPP) transitions. See the device data manual for ramp rate specifications.
• Switching to a lower voltage: When switching to a lower voltage, the maximum operating frequency
changes. Care must be taken such that the maximum operating frequency supported at the new
voltage is not violated. For this reason, it is recommended to change the operating frequency before
switching the operating voltage.
9.9
Deep Sleep Mode
This device supports a Deep Sleep mode where all device clocks are stopped and the on-chip oscillator is
shut down to save power. Registers and memory contents are preserved, thus, upon recovery, the
program may continue from where it left off with minimal overhead involved.
The Deep Sleep mode is initiated when the DEEPSLEEP pin is driven low. The device wakes up from
Deep Sleep mode when the DEEPSLEEP pin is driven high. The DEEPSLEEP pin can be driven by an
external controller or it can be driven internally by the real-time clock (RTC). The RTC method allows for
automatic wake-up at a programmed time.
NOTE: Due to pin multiplexing, the DEEPSLEEP pin can only be driven by an external controller or
its internal real-time clock (RTC). The DEEPSLEEP pin cannot be driven by both an external
controller and its internal real-time clock at the same time.
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
9.9.1.1
Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep mode if an external signal is used to wake-up the
device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
3. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
4. Configure the DEEPSLEEP pin as input-only using the PINMUX0_31_28 bits in the PINMUX0 register
in the System Configuration (SYSCFG) Module chapter.
5. The external controller should drive the DEEPSLEEP pin high (not in Deep Sleep).
6. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
7. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
8. Begin polling the SLEEPCOMPLETE bit until it is set to 1. This bit is set once the device is woken up
from Deep Sleep mode.
9. The external controller drives the DEEPSLEEP pin low to initiate Deep Sleep mode.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
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9.9.1.2
Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if an external signal is used to wake-up the
device:
1. The external controller drives the DEEPSLEEP pin high.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 7.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
9.9.2.1
Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep state if the RTC is used to wake-up the device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
3. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
4. Configure the desired wake-up time as an alarm in the RTC.
5. Configure the DEEPSLEEP/RTC_ALARM pin to output RTC_ALARM using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. The pin is driven low
since the alarm has not yet occurred.
6. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
7. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
Also, the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.2.2
Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if the RTC is used to wake-up the device:
1. The RTC alarm occurs and the RTC_ALARM pin is driven high (which is internally connected to the
DEEPSLEEP pin). This causes the Deep Sleep logic to exit the Deep Sleep mode.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
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4. Initialize the PLL controllers as described in Section 7.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.3 Deep Sleep Sequence
Figure 9-1 illustrates the Deep Sleep sequence:
1. Software sets the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System
Configuration (SYSCFG) Module chapter.
2. The DEEPSLEEP pin is driven low by either an external device or the RTC_ALARM pin. The Deep
Sleep mode begins.
3. The PLL controller reference clock is gated.
4. The on-chip oscillator is disabled. If the device is being clocked by an external source, this clock may
stay enabled; the power savings from turning off this clock is minimal.
5. The DEEPSLEEP pin is driven high and the on-chip oscillator is enabled.
6. The Deep Sleep counter beings counting valid clock cycles.
7. The count has reached the number specified in the SLEEPCOUNT bit field and the
SLEEPCOMPLETE bit is set. The PLL reference clock is enabled and the Deep Sleep mode ends.
8. Software clears the SLEEPENABLE bit. The SLEEPCOMPLETE bit is automatically cleared.
Figure 9-1. Deep Sleep Mode Sequence
See Note:
1
2
3
4
5
6
7
8
SLEEPENABLE
(internal)
DEEPSLEEP
CLKGATE
(internal)
PLLC Ref Clk
(internal)
OSC_GZ
(internal)
OSCIN
SLEEPCOMPLETE
(internal)
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9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking
Entering the Deep Sleep mode stops all of the clocks to the device so it is the responsibility of the
software to ensure that all peripheral accesses have been completed and peripheral interfaces
appropriately configured for clocks to stop. Therefore, before an external controller drives the
DEESPLEEP pin, a handshaking mechanism must be in place to give software time to prepare the device
for Deep Sleep mode. The implementation of the handshake mechanism is up to the system designer.
9.9.4.1
Entering Deep Sleep Mode
The following example sequence can be used to activate the Deep Sleep mode using a handshaking
mechanism between your device and an external device:
1. Clear the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter to 0. The DEEPSLEEP pin has no effect until software running on the
device sets this bit.
2. Configure the GP0[8]/DEEPSLEEP/RTC_ALARM pin to output GP0[8] using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. When the pin is
configured for GPIO functionality, the internal DEEPSLEEP signal is still driven by the value on the pin.
3. Configure the GP0[8] pin to generate interrupts on the falling edge of the GPIO signal.
4. An external device drives the GP0[8] pin low.
5. Software prepares the device for Deep Sleep mode.
6. Set the SLEEPENABLE bit in DEEPSLEEP to 1. The Deep Sleep mode is immediately started and all
device clocks are stopped. Also, the SLEEPCOMPLETE bit is automatically cleared.
9.9.4.2
Exiting Deep Sleep Mode
To exit the Deep Sleep mode, follow this sequence:
1. An external device drives the GP0[8] pin high.
2. The device exits the Deep Sleep mode. When the SLEEPCOUNT delay is complete, the Deep Sleep
logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register
(DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.
9.10 Additional Peripheral Power Management Considerations
This section lists additional power management features and considerations that might be part of other
chip-level or peripheral logic, apart from the features supported by the core, PLL controller (PLLC), and
power and sleep controller (PSC).
9.10.1 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode
The DDR2/mDDR memory controller supports different methods for reducing its power consumption
including self-refresh mode, power-down mode, and clock gating. Additionally, the DDR2/mDDR memory
controller DLL, PHY, and the receivers at the I/O pins can be disabled. Even if the PHY is active, the
receivers can be configured to disable whenever writes are in progress and the receivers are not needed.
Self-refresh mode can be used to preserve the contents of DDR2/mDDR memory when the DDR2/mDDR
memory controller is clock gated or when the device is placed in RTC-only mode. However, in the RTConly mode, care must be taken to correctly take the DDR2/mDDR out of self-refresh mode.
NOTE: To preserve the contents of the external memory while the DDR2/mDDR memory controller
is clock gated, its self-refresh mode must be enabled before the DDR2/mDDR memory
controller clock is turned off.
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In RTC-only mode, all portions of the device except for the RTC are powered down, including the
DDR2/mDDR memory controller. During power-up, the DDR2/mDDR memory controller defaults to its
reset state. When the DDR2/mDDR memory controller is taken out of reset, it automatically runs its
memory initialization routine; the self-refresh state of the memory is ignored. This hardware sequence
cannot be stopped by software running on the device.
To correctly take the memory out of self-refresh after coming back from RTC-only mode, follow these
steps:
1. Before going into RTC-only mode, disconnect the DDR2/mDDR memory controller CKE output pin
from the memory; ensure the memory’s CKE input pin continues to be driven low.
2. After coming back from RTC-only mode, configure the device to the desired operating state.
3. Program the DDR2/mDDR memory controller following the normal sequence.
4. Enable the self-refresh mode of the DDR2/mDDR memory controller.
5. Connect the DDR2/mDDR memory controller CKE output pin to the memory.
6. Disable the self-refresh mode of the DDR2/mDDR memory controller.
After this sequence, the DDR2/mDDR memory controller is ready for use. Note that hardware logic is
needed to disconnect the CKE output pin from the memory and to drive the memory’s CKE input pin low.
For more details on the power management features of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.10.2 LVCMOS I/O Buffer Receiver Disable
This device supports two types of LVCMOS I/Os: 1.8V I/Os and low-static current dual-voltage I/Os that
operate at either 1.8V or 3.3V. The receivers on the LCVMOS I/Os are enabled and disabled by software
(see the RXACTIVE Control Register (RXACTIVE) in the System Configuration (SYSCFG) Module
chapter). In the event that certain receivers are not used (such as in a low-power state), they can be
disabled to conserve power.
9.10.3 Pull-Up/Pull-Down Disable
In general, you must ensure that all input pins are always pulled to a logic-high or a logic-low voltage level.
A floating input pin can consume a small amount of I/O leakage current. The I/O leakage current can be
greatly multiplied in the case of several floating inputs pins.
This device includes internal pull-up and pull-down resistors that prevent floating input pins. These internal
resistors are generally very weak and their use is intended for pins that are not connected on the board
design. For pins that are connected, external pull-up and pull-down resistors are recommended.
When an input pin is externally driven to a valid logic level, through an external pull-up resistor or by an
external device for example, it is recommended to disable the internal resistor. Opposing an internal pullup or pull-down resistor can consume a small amount of current. Internal resistors are disabled through
the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module chapter.
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Chapter 10
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System Configuration (SYSCFG) Module
Topic
10.1
10.2
10.3
10.4
10.5
...........................................................................................................................
Introduction .....................................................................................................
Protection ........................................................................................................
Master Priority Control ......................................................................................
Interrupt Support ..............................................................................................
SYSCFG Registers ............................................................................................
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10.1 Introduction
The system configuration (SYSCFG) module is a system-level module containing status and top level
control logic required by the device. The system configuration module consists of a set of memorymapped status and control registers, accessible by the CPU, supporting all of the following system
features, and miscellaneous functions and operations.
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device Boot Configuration Status
• Master Priority Control
– Controls the system priority for all master peripherals (including EDMA3TC)
• Emulation Control
– Emulation suspend control for peripherals that support the feature
• Special Peripheral Status and Control
– Locking of PLL control settings
– Default burst size configuration for EDMA3 transfer controllers
– Event source selection for the eCAP peripheral input capture
– McASP0 AMUTEIN selection and clearing of AMUTE
– Clock source selection for EMIFA and DDR2/mDDR
– HPI Control
The system configuration module controls several global operations of the device; therefore, the module
supports protection against erroneous and illegal accesses to the registers in its memory-map. The
protection mechanisms that are present in the module are:
• A special key sequence that needs to be written into a set of registers in the system configuration
module, to allow write ability to the rest of registers in the system configuration module.
• Several registers in the module are only accessible when the CPU requesting read/write access is in
privileged mode.
10.2 Protection
The SYSCFG module controls several global operations of the device; therefore, it has a protection
mechanism that prevents spurious and illegal accesses to the registers in its memory map. The protection
mechanism enables accesses to these registers only if certain conditions are met.
10.2.1 Privilege Mode Protection
The CPU supports two privilege levels: Supervisor and User. Several registers in the SYSCFG memorymap can only be accessed when the accessing host (CPU or master peripheral) is operating in privileged
mode, that is, in Supervisor mode. The registers that can only be accessed in privileged mode are listed in
Section 10.5. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for
details on privilege levels.
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10.2.2 Kicker Mechanism Protection
NOTE: The Kick registers are disabled in silicon revision 2 and later. The SYSCFG registers are
always unlocked and writes to the Kick registers have no functional effect.
The Kick registers (KICK0R and KICK1R) can only be accessed in privileged mode (the host
needs to be in Supervisor mode). Any number of accesses may be performed to the
SYSCFG module, while the module is unlocked.
The SYSCFG module remains unlocked after the unlock sequence, until locked again.
Locking the module is accomplished by writing any value other then the key values to either
KICK0R or KICK1R.
To access any registers in the SYSCFG module, it is required to follow a special sequence of writes to the
Kick registers (KICK0R and KICK1R) with correct key values. Writing the correct key value to the kick
registers unlocks the registers in the SYSCFG memory-map. In order to access the SYSCFG registers,
the following unlock sequence needs to be executed in software:
1. Write the key value of 83E7 0B13h to KICK0R.
2. Write the key value of 95A4 F1E0h to KICK1R.
After steps 1 and 2, the SYSCFG module registers are accessible and can be configured as per the
application requirements.
10.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the DSP, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or EDMA3 for
initiating the data transfer to/from them. In order to determine allowed connection between masters and
slave, each master request source must have a unique master ID (mstid) associated with it. The master ID
is shown in Table 10-1. See the device-specific data manual to determine the masters present on your
device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 10-2. Application software is expected to modify these values
to obtain the desired performance.
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Table 10-1. Master IDs
Master ID
Peripheral
0-1
Reserved
2
DSP MDMA
3
DSP CFG
4-9
Reserved
10
EDMA3_0_CC0
11
EDMA3_1_CC0
12-15
Reserved
16
EDMA3_0_TC0 - read
17
EDMA3_0_TC0 - write
18
EDMA3_0_TC1 - read
19
EDMA3_0_TC1 - write
20
EDMA3_1_TC0 – read
21
EDMA3_1_TC0 – write
22-36
Reserved
37
HPI
38-255
Reserved
Table 10-2. Default Master Priority
Master
Default Priority (1)
Master Priority Register
EDMA3_0_TC0 (2)
0
MSTPRI1
(2)
EDMA3_0_TC1
0
MSTPRI1
DSP MDMA (3)
2
MSTPRI0
DSP CFG (3)
2
MSTPRI0
4
MSTPRI1
6
MSTPRI2
EDMA3_1_TC0
(2)
HPI
(1)
(2)
(3)
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
The priority for EDMA3_0_TC0, EDMA3_0_TC1, and EDMA3_1_TC0 is configurable through fields in the master priority 1
register (MSTPRI1), not the EDMA3CC QUEPRI register.
The priority for DSP MDMA and DSP CFG is controlled by fields in the master priority 0 register (MSTPRI0) and not
DSP.MDMAARBE.PRI (DSP Bandwidth manager module).
10.4 Interrupt Support
10.4.1 Interrupt Events and Requests
The SYSCFG module generates two interrupts: an address error interrupt (BOOTCFG_ADDR_ERR) and
a protection interrupt (BOOTCFG_PROT_ERR). The BOOTCFG_ADDR_ERR is generated when there is
an addressing violation due to an access to a non-existent location in the SYSCFG register space. The
BOOTCFG_PROT_ERR interrupt is generated when there is a protection violation of either in the defined
ranges or to the SYSCFG registers. It is required to write a value of 0 to the end of interrupt register (EOI)
after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of completion
of the SYSCFG interrupt so that the module can reliably generate subsequent interrupts.
The transfer parameters that caused the violation are saved in the fault address register (FLTADDRR) and
the fault status register (FLTSTAT).
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10.4.2 Interrupt Multiplexing
The interrupts from the SYSCFG module are combined with the interrupts from the MPU module into a
single interrupt called MPU_BOOTCFG_ERR. The combined interrupt is routed to the DSP interrupt
controller.
10.4.3 Host-DSP Communication Interrupts
The SYSCFG module also has a set of registers, the chip signal register (CHIPSIG) and the chip signal
clear register (CHIPSIG_CLR), to facilitate host-to-processor communication. This is generally used to
allow an external host and the DSP to coordinate.
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other
processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller.
10.5 SYSCFG Registers
Table 10-3 lists the memory-mapped registers for the system configuration module 0 (SYSCFG0) and
Table 10-4 lists the memory-mapped registers for the system configuration module 1 (SYSCFG1). These
tables also indicate whether a particular register can be accessed only when the CPU is in privileged
mode.
Table 10-3. System Configuration Module 0 (SYSCFG0) Registers
Address
Acronym
Register Description
Access
01C1 4000h
REVID
Revision Identification Register
—
Section 10.5.1
01C1 4008h
DIEIDR0 (1)
Die Identification Register 0
—
—
01C1 400Ch
DIEIDR1
(1)
Die Identification Register 1
—
—
01C1 4010h
DIEIDR2 (1)
Die Identification Register 2
—
—
01C1 4014h
DIEIDR3 (1)
Die Identification Register 3
—
—
01C1 4018h
DEVIDR0
Device Identification Register 0
Privileged mode
Section 10.5.2
01C1 4020h
BOOTCFG
Boot Configuration Register
Privileged mode
Section 10.5.3
01C1 4024h
CHIPREVIDR
Chip Revision Identification Register
Privileged mode
Section 10.5.4
01C1 4038h
KICK0R
Kick 0 Register
Privileged mode
Section 10.5.5.1
01C1 403Ch
KICK1R
Kick 1 Register
Privileged mode
Section 10.5.5.2
01C1 4044h
HOST1CFG
Host 1 Configuration Register
—
01C1 40E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
Section 10.5.7.1
01C1 40E4h
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
Section 10.5.7.2
01C1 40E8h
IENSET
Interrupt Enable Register
Privileged mode
Section 10.5.7.3
01C1 40ECh
IENCLR
Interrupt Enable Clear Register
Privileged mode
Section 10.5.7.4
01C1 40F0h
EOI
End of Interrupt Register
Privileged mode
Section 10.5.7.5
01C1 40F4h
FLTADDRR
Fault Address Register
Privileged mode
Section 10.5.8.1
01C1 40F8h
FLTSTAT
Fault Status Register
—
Section 10.5.8.2
01C1 4110h
MSTPRI0
Master Priority 0 Register
Privileged mode
Section 10.5.9.1
01C1 4114h
MSTPRI1
Master Priority 1 Register
Privileged mode
Section 10.5.9.2
01C1 4118h
MSTPRI2
Master Priority 2 Register
Privileged mode
Section 10.5.9.3
01C1 4120h
PINMUX0
Pin Multiplexing Control 0 Register
Privileged mode
Section 10.5.10.1
01C1 4124h
PINMUX1
Pin Multiplexing Control 1 Register
Privileged mode
Section 10.5.10.2
01C1 4128h
PINMUX2
Pin Multiplexing Control 2 Register
Privileged mode
Section 10.5.10.3
01C1 412Ch
PINMUX3
Pin Multiplexing Control 3 Register
Privileged mode
Section 10.5.10.4
01C1 4130h
PINMUX4
Pin Multiplexing Control 4 Register
Privileged mode
Section 10.5.10.5
01C1 4134h
PINMUX5
Pin Multiplexing Control 5 Register
Privileged mode
Section 10.5.10.6
01C1 4138h
PINMUX6
Pin Multiplexing Control 6 Register
Privileged mode
Section 10.5.10.7
(1)
Section
Section 10.5.6
This register is for internal-use only.
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Table 10-3. System Configuration Module 0 (SYSCFG0) Registers (continued)
Address
Acronym
Register Description
Access
01C1 413Ch
PINMUX7
Pin Multiplexing Control 7 Register
Privileged mode
Section
01C1 4140h
PINMUX8
Pin Multiplexing Control 8 Register
Privileged mode
Section 10.5.10.9
01C1 4144h
PINMUX9
Pin Multiplexing Control 9 Register
Privileged mode
Section 10.5.10.10
01C1 4148h
PINMUX10
Pin Multiplexing Control 10 Register
Privileged mode
Section 10.5.10.11
01C1 414Ch
PINMUX11
Pin Multiplexing Control 11 Register
Privileged mode
Section 10.5.10.12
01C1 4150h
PINMUX12
Pin Multiplexing Control 12 Register
Privileged mode
Section 10.5.10.13
01C1 4154h
PINMUX13
Pin Multiplexing Control 13 Register
Privileged mode
Section 10.5.10.14
01C1 4158h
PINMUX14
Pin Multiplexing Control 14 Register
Privileged mode
Section 10.5.10.15
01C1 415Ch
PINMUX15
Pin Multiplexing Control 15 Register
Privileged mode
Section 10.5.10.16
01C1 4160h
PINMUX16
Pin Multiplexing Control 16 Register
Privileged mode
Section 10.5.10.17
01C1 4164h
PINMUX17
Pin Multiplexing Control 17 Register
Privileged mode
Section 10.5.10.18
01C1 4168h
PINMUX18
Pin Multiplexing Control 18 Register
Privileged mode
Section 10.5.10.19
01C1 416Ch
PINMUX19
Pin Multiplexing Control 19 Register
Privileged mode
Section 10.5.10.20
01C1 4170h
SUSPSRC
Suspend Source Register
Privileged mode
Section 10.5.11
01C1 4174h
CHIPSIG
Chip Signal Register
—
Section 10.5.12
01C1 4178h
CHIPSIG_CLR
Chip Signal Clear Register
—
Section 10.5.13
01C1 417Ch
CFGCHIP0
Chip Configuration 0 Register
Privileged mode
Section 10.5.14
01C1 4180h
CFGCHIP1
Chip Configuration 1 Register
Privileged mode
Section 10.5.15
01C1 4188h
CFGCHIP3
Chip Configuration 3 Register
Privileged mode
Section 10.5.16
01C1 418Ch
CFGCHIP4
Chip Configuration 4 Register
Privileged mode
Section 10.5.17
Section 10.5.10.8
Table 10-4. System Configuration Module 1 (SYSCFG1) Registers
Address
Acronym
Register Description
Access
01E2 C000h
VTPIO_CTL
VTP I/O Control Register
Privileged mode
Section 10.5.18
Section
01E2 C004h
DDR_SLEW
DDR Slew Register
Privileged mode
Section 10.5.19
01E2 C008h
DEEPSLEEP
Deep Sleep Register
Privileged mode
Section 10.5.20
01E2 C00Ch
PUPD_ENA
Pullup/Pulldown Enable Register
Privileged mode
Section 10.5.21
01E2 C010h
PUPD_SEL
Pullup/Pulldown Selection Register
Privileged mode
Section 10.5.22
01E2 C014h
RXACTIVE
RXACTIVE Control Register
Privileged mode
Section 10.5.23
10.5.1 Revision Identification Register (REVID)
The revision identification register (REVID) provides the revision information for the SYSCFG module. The
REVID is shown in Figure 10-1 and described in Table 10-5.
Figure 10-1. Revision Identification Register (REVID)
31
0
REV
R-4E84 0102h
LEGEND: R = Read only; -n = value after reset
Table 10-5. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E84 0102h
168
Description
Revision ID. Revision information for the SYSCFG module.
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10.5.2 Device Identification Register 0 (DEVIDR0)
The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID
device. Software can use this register to determine the version of the device on which it is executing. The
DEVIDR0 is shown in Figure 10-2 and described in Table 10-6.
Figure 10-2. Device Identification Register 0 (DEVIDR0)
31
0
DEVID0
R-1B7D 102Fh
LEGEND: R = Read only; -n = value after reset
Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions
Bit
31-0
Field
DEVID0
Value
Description
1B7D 102Fh
Device identification.
10.5.3 Boot Configuration Register (BOOTCFG)
The device boot and configuration settings are latched at device reset, and captured in the boot
configuration register (BOOTCFG). See your device-specific data manual and the Boot Considerations
chapter for details on boot and configuration settings. The BOOTCFG is shown in Figure 10-3 and
described in Table 10-7.
Figure 10-3. Boot Configuration Register (BOOTCFG)
31
16
Reserved
R-0
15
0
BOOTMODE
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-7. Boot Configuration Register (BOOTCFG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BOOTMODE
Value
0
Description
Reserved
0-FFFFh
Boot Mode. This reflects the state of the boot mode pins.
10.5.4 Chip Revision Identification Register (CHIPREVIDR)
The chip revision identification register (CHIPREVIDR) provides the software-readable silicon revision
information for the device. The CHIPREVID is shown in Figure 10-4 and described in Table 10-8.
Figure 10-4. Chip Revision Identification Register (CHIPREVIDR)
31
16
Reserved
R-x
15
6
5
0
Reserved
CHIPREVID
R-x
R-4h
LEGEND: R = Read only; -n = value after reset; x = value is indeterminate after reset
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Table 10-8. Chip Revision Identification Register (CHIPREVIDR) Field Descriptions
Bit
Field
31-6
Reserved
5-0
CHIPREVID
Value
0
Reserved
Identifies silicon revision of device.
0-3h
4h
170
Description
Older silicon revision
Silicon revision 2.2
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10.5.5 Kick Registers (KICK0R-KICK1R)
NOTE: The kick registers are disabled in silicon revision 2 and later. The SYSCFG registers are
always unlocked and writes to the kick registers have no functional effect.
The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of
the modules memory-mapped registers. At power-on reset, none of the SYSCFG module registers are
writeable (they are readable). To allow writing to the registers in the module, it is required to “unlock” the
registers by writing to two memory-mapped registers in the SYSCFG module, Kick0 and Kick1, with exact
data values. Once these values are written, then all the registers in the SYSCFG module that are
writeable can be written to. See Section 10.2.2 for the exact key values and sequence of steps. Writing
any other data value to either of these kick registers will cause the memory mapped registers to be
“locked” again and block out any write accesses to registers in the SYSCFG module.
10.5.5.1 Kick 0 Register (KICK0R)
The KICK0R is shown in Figure 10-5 and described in Table 10-9.
Figure 10-5. Kick 0 Register (KICK0R)
31
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-9. Kick 0 Register (KICK0R) Field Descriptions
Bit
Field
Value
31-0
KICK0
0-FFFF FFFFh
Description
KICK0R allows writing to unlock the kick0 data. The written data must be 83E7 0B13h to unlock
this register. It must be written before writing to the kick1 register. Writing any other value will lock
the other MMRs.
10.5.5.2 Kick 1 Register (KICK1R)
The KICK1R is shown in Figure 10-6 and described in Table 10-10.
Figure 10-6. Kick 1 Register (KICK1R)
31
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-10. Kick 1 Register (KICK1R) Field Descriptions
Bit
Field
Value
31-0
KICK1
0-FFFF FFFFh
Description
KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written
before writing to the kick1 register. Writing any other value will lock the other MMRs.
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10.5.6 Host 1 Configuration Register (HOST1CFG)
The host 1 configuration register (HOST1CFG) provides information on the DSP boot address value at
power-on reset. The boot address defaults to 0070 0000h (DSP ROM) on power-up. The address field is
read/writeable after reset and can be modified to allow execution from an alternate location after a module
level or local reset on the DSP. The HOST1CFG is shown in Figure 10-7 and described in Table 10-11.
Figure 10-7. Host 1 Configuration Register (HOST1CFG)
31
16
DSP_ISTP_RST_VAL
R/W-0070h
15
10
9
0
DSP_ISTP_RST_VAL
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions
Bit
Field
31-10 DSP_ISTP_RST_VAL
9-0
172
Reserved
Value
0-3F FFFFh
0
Description
DSP boot address vector.
Reserved
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10.5.7 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
10.5.7.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 10-8 and described in
Table 10-12.
Figure 10-8. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
PROTERR
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
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10.5.7.2 Interrupt Enable Status/Clear Register (IENSTAT)
The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows
clearing of the interrupt status. The IENSTAT is shown in Figure 10-9 and described in Table 10-13.
Figure 10-9. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
174
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
PROTERR
Protection violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
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10.5.7.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 10-10 and described in Table 10-14.
Figure 10-10. Interrupt Enable Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-14. Interrupt Enable Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
PROTERR_EN
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
10.5.7.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 10-11 and described in Table 10-15.
Figure 10-11. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
PROTERR_CLR
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
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10.5.7.5 End of Interrupt Register (EOI)
The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of
the SYSCFG interrupt (for address/protection violation). It is required to write a value of 0 to the EOI
register after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of
completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts.
The EOI is shown in Figure 10-12 and described in Table 10-16.
Figure 10-12. End of Interrupt Register (EOI)
31
16
Reserved
R-0
15
8
7
0
Reserved
EOIVECT
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 10-16. End of Interrupt Register (EOI) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
EOIVECT
0-FFh
Description
Reserved. Always read 0.
EOI vector value. Write the interrupt distribution value of the chip.
10.5.8 Fault Registers
The fault registers are a group of registers responsible for capturing the details on the faulty
(address/protection violation errors) accesses, such as address and type of error.
10.5.8.1 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) captures the address of the first transfer that causes the address
or memory violation error. The FLTADDRR is shown in Figure 10-13 and described in Table 10-17.
Figure 10-13. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
176
Field
FLTADDR
Value
0-FFFF FFFFh
Description
Fault address for the first fault transfer.
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10.5.8.2 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous
transaction. This includes things like the master id for the master that caused the address/memory
violation error, details on whether it is a user or supervisor level read/write or execute fault. The FLTSTAT
is shown in Figure 10-14 and described in Table 10-18.
Figure 10-14. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
ID
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-18. Fault Status Register (FLTSTAT) Field Descriptions
Field
Value
Description
31-24
Bit
ID
0-FFh
Transfer ID of the first fault transfer.
23-16
MSTID
0-FFh
Master ID of the first fault transfer.
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
0
0-Fh
0
Reserved. Always read 0
Privilege ID of the first fault transfer.
Reserved. Always read 0
Fault type of first fault transfer.
0
No transfer fault
1h
User execute fault
2h
User write fault
3h
Reserved
4h
User read fault
5h-7h
8h
9h-Fh
10h
11h-1Fh
20h
21h-3Fh
Reserved
Supervisor execute fault
Reserved
Supervisor write fault
Reserved
Supervisor read fault
Reserved
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10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)
10.5.9.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 10-15 and described in Table 10-19.
Figure 10-15. Master Priority 0 Register (MSTPRI0)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
DSP_CFG
Rsvd
DSP_MDMA
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-19. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
4h
Reserved. Write the default value when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
DSP_CFG
0-7h
11
Reserved
0
10-8
DSP_MDMA
0-7h
DSP CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
DSP DMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Always read as 0.
6-4
Reserved
2h
Reserved. Write the default value when modifying this register.
3
Reserved
0
Reserved. Always read as 0.
2-0
Reserved
2h
Reserved. Write the default value when modifying this register.
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10.5.9.2 Master Priority 1 Register (MSTPRI1)
The master priority 1 register (MSTPRI1) is shown in Figure 10-16 and described in Table 10-20.
Figure 10-16. Master Priority 1 Register (MSTPRI1)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
EDMA31TC0
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
EDMA30TC1
Rsvd
EDMA30TC0
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-20. Master Priority 1 Register (MSTPRI1) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
15
14-12
11
10-8
EDMA31TC0
Reserved
EDMA30TC1
Reserved
EDMA30TC0
0-7h
0
0-7h
0
0-7h
EDMA3_1_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
EDMA3_0_TC1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
EDMA3_0_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Always read as 0.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Always read as 0.
2-0
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.9.3 Master Priority 2 Register (MSTPRI2)
The master priority 2 register (MSTPRI2) is shown in Figure 10-17 and described in Table 10-21.
Figure 10-17. Master Priority 2 Register (MSTPRI2)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
UHPI
Rsvd
Reserved
R/W-0
R/W-5h
R/W-0
R/W-4h
R/W-0
R/W-6h
R/W-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-0
R/W-0
R/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-21. Master Priority 2 Register (MSTPRI2) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
5h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
UHPI
0-7h
HPI port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
Reserved
4h
Reserved. Write the default value when modifying this register.
11
Reserved
0
Reserved. Write the default value when modifying this register.
10-8
Reserved
4h
Reserved. Write the default value when modifying this register.
7
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Write the default value when modifying this register.
2-0
Reserved
4h
Reserved. Write the default value when modifying this register.
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10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the
smallest possible package. On the device, pin multiplexing can be controlled on a pin by pin basis. This is
done by the pin multiplexing registers (PINMUX0-PINMUX19). Each pin that is multiplexed with several
different functions has a corresponding 4-bit field in PINMUXn. Pin multiplexing selects which of several
peripheral pin functions control the pins I/O buffer output data and output enable values only. Note that the
input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers
have no effect on input from a pin. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used. Detailed information about the pin
multiplexing and control is covered in the device-specific data manual. Access to the pin multiplexing utility
is available in OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility Application Report
(SPRAB63).
10.5.10.1 Pin Multiplexing Control 0 Register (PINMUX0)
Figure 10-18. Pin Multiplexing Control 0 Register (PINMUX0)
31
28
27
24
23
20
19
16
PINMUX0_31_28
PINMUX0_27_24
PINMUX0_23_20
PINMUX0_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX0_15_12
PINMUX0_11_8
PINMUX0_7_4
PINMUX0_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
Bit
31-28
Field
Value
PINMUX0_31_28
RTC_ALARM/GP0[8]/DEEPSLEEP Control
0
Selects Function DEEPSLEEP
I
1h
Reserved
X
2h
Selects Function RTC_ALARM
O
3h-7h
8h
9h-Fh
27-24
PINMUX0_27_24
X
Selects Function GP0[8]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function AMUTE
8h
9h-Fh
PINMUX0_23_20
X
Z
I/O
Reserved
X
Selects Function GP0[9]
I/O
Reserved
X
AHCLKX/GP0[10] Control
0
Pin is 3-stated.
1h
Selects Function AHCLKX
2h-7h
8h
9h-Fh
(1)
Reserved
AMUTE/GP0[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP0[10]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX0_19_16
AHCLKR/GP0[11] Control
0
Pin is 3-stated.
1h
Selects Function AHCLKR
2h-7h
8h
9h-Fh
15-12
PINMUX0_15_12
I/O
Reserved
1h
Selects Function AFSX
PINMUX0_11_8
X
Z
I/O
Reserved
X
Selects Function GP0[12]
I/O
Reserved
X
AFSR/GP0[13] Control
0
Pin is 3-stated.
1h
Selects Function AFSR
2h-7h
8h
9h-Fh
PINMUX0_7_4
Z
I/O
Reserved
X
Selects Function GP0[13]
I/O
Reserved
X
ACLKX/GP0[14] Control
0
Pin is 3-stated.
1h
Selects Function ACLKX
2h-7h
8h
9h-Fh
PINMUX0_3_0
Z
I/O
Reserved
X
Selects Function GP0[14]
I/O
Reserved
X
ACLKR/GP0[15] Control
0
Pin is 3-stated.
1h
Selects Function ACLKR
2h-7h
8h
9h-Fh
182
X
Selects Function GP0[11]
Pin is 3-stated.
9h-Fh
3-0
Reserved
0
8h
7-4
Z
I/O
AFSX/GP0[12] Control
2h-7h
11-8
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP0[15]
I/O
Reserved
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10.5.10.2 Pin Multiplexing Control 1 Register (PINMUX1)
Figure 10-19. Pin Multiplexing Control 1 Register (PINMUX1)
31
28
27
24
23
20
19
16
PINMUX1_31_28
PINMUX1_27_24
PINMUX1_23_20
PINMUX1_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX1_15_12
PINMUX1_11_8
PINMUX1_7_4
PINMUX1_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
Bit
31-28
Field
Value
PINMUX1_31_28
AXR8/CLKS1/ECAP1_APWM1/GP0[0] Control
0
Pin is 3-stated.
1h
Selects Function AXR8
2h
Selects Function CLKS1
I
3h
Reserved
X
4h
Selects Function ECAP1_APWM1
5h-7h
8h
9h-Fh
27-24
PINMUX1_27_24
X
Selects Function GP0[0]
I/O
Reserved
X
0
Pin is 3-stated.
Selects Function AXR9
I/O
2h
Selects Function DX1
O
9h-Fh
PINMUX1_23_20
Z
Reserved
X
Selects Function GP0[1]
I/O
Reserved
X
AXR10/DR1/GP0[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR10
2h
Selects Function DR1
3h-7h
8h
9h-Fh
PINMUX1_19_16
Z
I/O
I
Reserved
X
Selects Function GP0[2]
I/O
Reserved
X
AXR11/FSX1/GP0[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR11
I/O
2h
Selects Function FSX1
I/O
3h-7h
8h
9h-Fh
(1)
I/O
Reserved
1h
8h
19-16
Z
I/O
AXR9/DX1/GP0[1] Control
3h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP0[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX1_15_12
AXR12/FSR1/GP0[4] Control
0
Pin is 3-stated.
1h
Selects Function AXR12
I/O
2h
Selects Function FSR1
I/O
3h-7h
8h
9h-Fh
11-8
PINMUX1_11_8
X
Selects Function GP0[4]
I/O
Reserved
X
0
Pin is 3-stated.
Selects Function AXR13
I/O
2h
Selects Function CLKX1
I/O
9h-Fh
PINMUX1_7_4
Z
Reserved
X
Selects Function GP0[5]
I/O
Reserved
X
AXR14/CLKR1/GP0[6] Control
0
Pin is 3-stated.
1h
Selects Function AXR14
I/O
2h
Selects Function CLKR1
I/O
3h-7h
8h
9h-Fh
PINMUX1_3_0
Z
Reserved
X
Selects Function GP0[6]
I/O
Reserved
X
AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR15
2h
Selects Function EPWM0TZ[0]
3h
Reserved
4h
Selects Function ECAP2_APWM2
5h-7h
8h
9h-Fh
184
Reserved
1h
8h
3-0
Z
AXR13/CLKX1/GP0[5] Control
3h-7h
7-4
Type (1)
Description
Z
I/O
I
X
I/O
Reserved
X
Selects Function GP0[7]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.3 Pin Multiplexing Control 2 Register (PINMUX2)
Figure 10-20. Pin Multiplexing Control 2 Register (PINMUX2)
31
28
27
24
23
20
19
16
PINMUX2_31_28
PINMUX2_27_24
PINMUX2_23_20
PINMUX2_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX2_15_12
PINMUX2_11_8
PINMUX2_7_4
PINMUX2_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
Bit
31-28
Field
Value
PINMUX2_31_28
AXR0/ECAP0_APWM0/GP8[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR0
I/O
2h
Selects Function ECAP0_APWM0
I/O
3h
Reserved
4h
Selects Function GP8[7]
5h-Fh
27-24
PINMUX2_27_24
0
Pin is 3-stated.
Selects Function AXR1
5h-Fh
PINMUX2_23_20
X
Z
I/O
Reserved
X
Selects Function GP1[9]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function AXR2
4h
5h-Fh
PINMUX2_19_16
X
Z
I/O
Reserved
X
Selects Function GP1[10]
I/O
Reserved
X
AXR3/GP1[11] Control
0
Pin is 3-stated.
1h
Selects Function AXR3
2h-3h
4h
5h-Fh
PINMUX2_15_12
Z
I/O
Reserved
X
Selects Function GP1[11]
I/O
Reserved
X
AXR4/GP1[12] Control
0
Pin is 3-stated.
1h
Selects Function AXR4
2h-3h
4h
5h-Fh
(1)
I/O
AXR2/GP1[10] Control
2h-3h
15-12
X
Reserved
1h
4h
19-16
Z
AXR1/GP1[9] Control
2h-3h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP1[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX2_11_8
AXR5/GP1[13] Control
0
Pin is 3-stated.
1h
Selects Function AXR5
2h-3h
4h
5h-Fh
7-4
PINMUX2_7_4
Reserved
X
Selects Function GP1[13]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function AXR6
4h
5h-Fh
PINMUX2_3_0
X
Z
I/O
Reserved
X
Selects Function GP1[14]
I/O
Reserved
X
AXR7/EPWM1TZ[0]/GP1[15] Control
0
Pin is 3-stated.
1h
Selects Function AXR7
2h
Selects Function EPWM1TZ[0]
I
Reserved
X
3h-7h
8h
9h-Fh
186
Z
I/O
AXR6/GP1[14] Control
2h-3h
3-0
Type (1)
Description
Z
I/O
Selects Function GP1[15]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.4 Pin Multiplexing Control 3 Register (PINMUX3)
Figure 10-21. Pin Multiplexing Control 3 Register (PINMUX3)
31
28
27
24
23
20
19
16
PINMUX3_31_28
PINMUX3_27_24
PINMUX3_23_20
PINMUX3_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX3_15_12
PINMUX3_11_8
PINMUX3_7_4
PINMUX3_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
Bit
31-28
Field
Value
PINMUX3_31_28
UART0_RTS/GP8[1] Control
0
Pin is 3-stated.
1h
Reserved
X
2h
Selects Function UART0_RTS
O
3h
Reserved
X
4h
Selects Function GP8[1]
5h-Fh
27-24
PINMUX3_27_24
Pin is 3-stated.
Z
Reserved
X
2h
Selects Function UART0_CTS
I
3h
Reserved
X
4h
Selects Function GP8[2]
PINMUX3_23_20
I/O
Reserved
X
UART0_TXD/GP8[3] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UART0_TXD
O
3h
Reserved
4h
Selects Function GP8[3]
PINMUX3_19_16
X
I/O
Reserved
X
UART0_RXD/GP8[4] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UART0_RXD
I
3h
Reserved
4h
Selects Function GP8[4]
PINMUX3_15_12
X
I/O
Reserved
X
EPWMSYNCO/GP8[5] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function EPWMSYNCO
O
3h
Reserved
4h
Selects Function GP8[5]
5h-Fh
(1)
X
0
5h-Fh
15-12
I/O
Reserved
1h
5h-Fh
19-16
Z
UART0_CTS/GP8[2] Control
5h-Fh
23-20
Type (1)
Description
X
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX3_11_8
EPWMSYNCI/GP8[6] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function EPWMSYNCI
I
3h
Reserved
X
4h
Selects Function GP8[6]
5h-Fh
7-4
PINMUX3_7_4
X
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function EPWM0B
PINMUX3_3_0
I/O
Reserved
X
EPWM0A/GP1[8] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function EPWM0A
3h
Reserved
4h
Selects Function GP1[8]
5h-Fh
188
I/O
Reserved
EPWM0B Control
3h-Fh
3-0
Type (1)
Description
I/O
X
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.5 Pin Multiplexing Control 4 Register (PINMUX4)
Figure 10-22. Pin Multiplexing Control 4 Register (PINMUX4)
31
28
27
24
23
20
19
16
PINMUX4_31_28
PINMUX4_27_24
PINMUX4_23_20
PINMUX4_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX4_15_12
PINMUX4_11_8
PINMUX4_7_4
PINMUX4_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
Bit
31-28
Field
Value
PINMUX4_31_28
SP1_SCS[2]/GP1[0] Control
0
Pin is 3-stated.
1h
Selects Function SP1_SCS[2]
2h-7h
8h
9h-Fh
27-24
PINMUX4_27_24
I/O
Reserved
1h
Selects Function SPI1_SCS[3]
PINMUX4_23_20
X
Z
I/O
Reserved
X
Selects Function GP1[1]
I/O
Reserved
X
SPI1_SCS[4]/GP1[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[4]
2h-7h
8h
9h-Fh
PINMUX4_19_16
Z
I/O
Reserved
X
Selects Function GP1[2]
I/O
Reserved
X
SPI1_SCS[5]/GP1[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[5]
2h-7h
8h
9h-Fh
PINMUX4_15_12
Z
I/O
Reserved
X
Selects Function GP1[3]
I/O
Reserved
X
SPI1_SCS[6]/I2C0_SDA/GP1[4] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[6]
I/O
2h
Selects Function I2C0_SDA
I/O
3h-7h
8h
9h-Fh
(1)
X
Selects Function GP1[0]
Pin is 3-stated.
9h-Fh
15-12
I/O
Reserved
0
8h
19-16
Z
SPI1_SCS[3]/GP1[1] Control
2h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP1[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX4_11_8
SPI1_SCS[7]/I2C0_SCL/GP1[5] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[7]
I/O
2h
Selects Function I2C0_SCL
I/O
3h-7h
8h
9h-Fh
7-4
PINMUX4_7_4
Reserved
X
Selects Function GP1[5]
I/O
Reserved
X
0
Selects Function TM64P1_IN12
I
1h
Reserved
X
2h
Selects Function TM64P1_OUT12
O
3h
Reserved
4h
Selects Function GP1[6]
PINMUX4_3_0
X
I/O
Reserved
X
TM64P0_OUT12/GP1[7]/TM64P0_IN12 Control
0
Selects Function TM64P0_IN12
I
1h
Reserved
X
2h
Selects Function TM64P0_OUT12
O
3h
Reserved
4h
Selects Function GP1[7]
5h-Fh
190
Z
TM64P1_OUT12/GP1[6]/TM64P1_IN12 Control
5h-Fh
3-0
Type (1)
Description
X
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.6 Pin Multiplexing Control 5 Register (PINMUX5)
Figure 10-23. Pin Multiplexing Control 5 Register (PINMUX5)
31
28
27
24
23
20
19
16
PINMUX5_31_28
PINMUX5_27_24
PINMUX5_23_20
PINMUX5_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX5_15_12
PINMUX5_11_8
PINMUX5_7_4
PINMUX5_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
Bit
31-28
Field
Value
PINMUX5_31_28
EMA_BA[0]/GP2[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_BA[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX5_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_BA[1]
O
Reserved
X
PINMUX5_23_20
Selects Function GP2[9]
I/O
Reserved
X
SPI1_SIMO/GP2[10] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SIMO
2h-7h
8h
9h-Fh
PINMUX5_19_16
Z
I/O
Reserved
X
Selects Function GP2[10]
I/O
Reserved
X
SPI1_SOMI/GP2[11] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SOMI
2h-7h
8h
9h-Fh
PINMUX5_15_12
Z
I/O
Reserved
X
Selects Function GP2[11]
I/O
Reserved
X
SPI1_ENA/GP2[12] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_ENA
2h-7h
8h
9h-Fh
(1)
I/O
0
8h
15-12
X
Selects Function GP2[8]
1h
9h-Fh
19-16
Reserved
EMA_BA[1]/GP2[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP2[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX5_11_8
SPI1_CLK/GP2[13] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_CLK
2h-7h
8h
9h-Fh
7-4
PINMUX5_7_4
Reserved
X
Selects Function GP2[13]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[0]
I/O
2h
Selects Function EPWM1B
I/O
8h
9h-Fh
PINMUX5_3_0
Z
Reserved
X
Selects Function GP2[14]
I/O
Reserved
X
SPI1_SCS[1]/EPWM1A/GP2[15] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[1]
I/O
2h
Selects Function EPWM1A
I/O
3h-7h
8h
9h-Fh
192
Z
I/O
SPI1_SCS[0]/EPWM1B/GP2[14] Control
3h-7h
3-0
Type (1)
Description
Z
Reserved
X
Selects Function GP2[15]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.7 Pin Multiplexing Control 6 Register (PINMUX6)
Figure 10-24. Pin Multiplexing Control 6 Register (PINMUX6)
31
28
27
24
23
20
19
16
PINMUX6_31_28
PINMUX6_27_24
PINMUX6_23_20
PINMUX6_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX6_15_12
PINMUX6_11_8
PINMUX6_7_4
PINMUX6_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
Bit
31-28
Field
Value
PINMUX6_31_28
EMA_CS[0]/GP2[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX6_27_24
Reserved
X
Pin is 3-stated.
Selects Function EMA_WAIT[1]
I
Reserved
X
PINMUX6_23_20
Z
Selects Function GP2[1]
I/O
Reserved
X
EMA_WE_DQM[1]/GP2[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[1]
O
2h-7h
8h
9h-Fh
PINMUX6_19_16
Reserved
X
Selects Function GP2[2]
I/O
Reserved
X
EMA_WE_DQM[0]/GP2[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[0]
O
2h-7h
8h
9h-Fh
PINMUX6_15_12
Reserved
X
Selects Function GP2[3]
I/O
Reserved
X
EMA_CAS/GP2[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CAS
O
2h-7h
8h
9h-Fh
(1)
I/O
0
8h
15-12
X
Selects Function GP2[0]
1h
9h-Fh
19-16
Reserved
EMA_WAIT[1]/GP2[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP2[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX6_11_8
EMA_RAS/GP2[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_RAS
O
2h-7h
8h
9h-Fh
7-4
PINMUX6_7_4
X
Selects Function GP2[5]
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_SDCKE
O
8h
9h-Fh
PINMUX6_3_0
Reserved
X
Selects Function GP2[6]
I/O
Reserved
X
EMA_CLK/GP2[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CLK
O
2h-7h
8h
9h-Fh
194
Reserved
EMA_SDCKE/GP2[6] Control
2h-7h
3-0
Type (1)
Description
Reserved
X
Selects Function GP2[7]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 10-25. Pin Multiplexing Control 7 Register (PINMUX7)
31
28
27
24
23
20
19
16
PINMUX7_31_28
PINMUX7_27_24
PINMUX7_23_20
PINMUX7_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX7_15_12
PINMUX7_11_8
PINMUX7_7_4
PINMUX7_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit
31-28
Field
Value
PINMUX7_31_28
EMA_WAIT[0]/GP3[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WAIT[0]
I
2h-7h
8h
9h-Fh
27-24
PINMUX7_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_A_RW
O
Reserved
X
PINMUX7_23_20
Selects Function GP3[9]
I/O
Reserved
X
EMA_OE/GP3[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_OE
O
2h-7h
8h
9h-Fh
PINMUX7_19_16
Reserved
X
Selects Function GP3[10]
I/O
Reserved
X
EMA_WE/GP3[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE
O
2h-7h
8h
9h-Fh
PINMUX7_15_12
Reserved
X
Selects Function GP3[11]
I/O
Reserved
X
EMA_CS[5]/GP3[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[5]
O
2h-7h
8h
9h-Fh
(1)
I/O
0
8h
15-12
X
Selects Function GP3[8]
1h
9h-Fh
19-16
Reserved
EMA_A_RW/GP3[9] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP3[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX7_11_8
EMA_CS[4]/GP3[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[4]
O
2h-7h
8h
9h-Fh
7-4
PINMUX7_7_4
X
Selects Function GP3[13]
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[3]
O
8h
9h-Fh
PINMUX7_3_0
Reserved
X
Selects Function GP3[14]
I/O
Reserved
X
EMA_CS[2]/GP3[15] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[2]
O
2h-7h
8h
9h-Fh
196
Reserved
EMA_CS[3]/GP3[14] Control
2h-7h
3-0
Type (1)
Description
Reserved
X
Selects Function GP3[15]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 10-26. Pin Multiplexing Control 8 Register (PINMUX8)
31
28
27
24
23
20
19
16
PINMUX8_31_28
PINMUX8_27_24
PINMUX8_23_20
PINMUX8_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX8_15_12
PINMUX8_11_8
PINMUX8_7_4
PINMUX8_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit
31-28
Field
Value
PINMUX8_31_28
EMA_D[8]/GP3[0] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[8]
2h-7h
8h
9h-Fh
27-24
PINMUX8_27_24
I/O
Reserved
Pin is 3-stated.
Selects Function EMA_D[9]
PINMUX8_23_20
X
Z
I/O
Reserved
X
Selects Function GP3[1]
I/O
Reserved
X
EMA_D[10]/GP3[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[10]
2h-7h
8h
9h-Fh
PINMUX8_19_16
Z
I/O
Reserved
X
Selects Function GP3[2]
I/O
Reserved
X
EMA_D[11]/GP3[3] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[11]
2h-7h
8h
9h-Fh
PINMUX8_15_12
Z
I/O
Reserved
X
Selects Function GP3[3]
I/O
Reserved
X
EMA_D[12]/GP3[4] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[12]
2h-7h
8h
9h-Fh
(1)
X
Selects Function GP3[0]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[9]/GP3[1] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP3[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX8_11_8
EMA_D[13]/GP3[5] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[13]
2h-7h
8h
9h-Fh
7-4
PINMUX8_7_4
Reserved
X
Selects Function GP3[5]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_D[14]
8h
9h-Fh
PINMUX8_3_0
X
Z
I/O
Reserved
X
Selects Function GP3[6]
I/O
Reserved
X
EMA_D[15]/GP3[7] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[15]
2h-7h
8h
9h-Fh
198
Z
I/O
EMA_D[14]/GP3[6] Control
2h-7h
3-0
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP3[7]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.10 Pin Multiplexing Control 9 Register (PINMUX9)
Figure 10-27. Pin Multiplexing Control 9 Register (PINMUX9)
31
28
27
24
23
20
19
16
PINMUX9_31_28
PINMUX9_27_24
PINMUX9_23_20
PINMUX9_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX9_15_12
PINMUX9_11_8
PINMUX9_7_4
PINMUX9_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
Bit
31-28
Field
Value
PINMUX9_31_28
EMA_D[0]/GP4[8] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[0]
2h-7h
8h
9h-Fh
27-24
PINMUX9_27_24
I/O
Reserved
Pin is 3-stated.
Selects Function EMA_D[1]
PINMUX9_23_20
X
Z
I/O
Reserved
X
Selects Function GP4[9]
I/O
Reserved
X
EMA_D[2]/GP4[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[2]
2h-7h
8h
9h-Fh
PINMUX9_19_16
Z
I/O
Reserved
X
Selects Function GP4[10]
I/O
Reserved
X
EMA_D[3]/GP4[11] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[3]
2h-7h
8h
9h-Fh
PINMUX9_15_12
Z
I/O
Reserved
X
Selects Function GP4[11]
I/O
Reserved
X
EMA_D[4]/GP4[12] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[4]
2h-7h
8h
9h-Fh
(1)
X
Selects Function GP4[8]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[1]/GP4[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP4[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX9_11_8
EMA_D[5]/GP4[13] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[5]
2h-7h
8h
9h-Fh
7-4
PINMUX9_7_4
Reserved
X
Selects Function GP4[13]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_D[6]
8h
9h-Fh
PINMUX9_3_0
X
Z
I/O
Reserved
X
Selects Function GP4[14]
I/O
Reserved
X
EMA_D[7]/GP4[15] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[7]
2h-7h
8h
9h-Fh
200
Z
I/O
EMA_D[6]/GP4[14] Control
2h-7h
3-0
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP4[15]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.11 Pin Multiplexing Control 10 Register (PINMUX10)
Figure 10-28. Pin Multiplexing Control 10 Register (PINMUX10)
31
28
27
24
23
20
19
16
PINMUX10_31_28
PINMUX10_27_24
PINMUX10_23_20
PINMUX10_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX10_15_12
PINMUX10_11_8
PINMUX10_7_4
PINMUX10_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
Bit
31-28
Field
Value
PINMUX10_31_28
EMA_A[16]/GP4[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[16]
O
2h-7h
8h
9h-Fh
27-24
PINMUX10_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_A[17]
O
Reserved
X
PINMUX10_23_20
Selects Function GP4[1]
I/O
Reserved
X
EMA_A[18]/GP4[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[18]
O
2h-7h
8h
9h-Fh
PINMUX10_19_16
Reserved
X
Selects Function GP4[2]
I/O
Reserved
X
EMA_A[19]/GP4[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[19]
O
2h-7h
8h
9h-Fh
PINMUX10_15_12
Reserved
X
Selects Function GP4[3]
I/O
Reserved
X
EMA_A[20]/GP4[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[20]
O
2h-7h
8h
9h-Fh
(1)
I/O
0
8h
15-12
X
Selects Function GP4[0]
1h
9h-Fh
19-16
Reserved
EMA_A[17]/GP4[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP4[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX10_11_8
EMA_A[21]/GP4[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[21]
O
2h-7h
8h
9h-Fh
7-4
PINMUX10_7_4
X
Selects Function GP4[5]
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[22]
O
8h
9h-Fh
PINMUX10_3_0
Reserved
X
Selects Function GP4[6]
I/O
Reserved
X
GP4[7] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h-7h
Reserved
8h
9h-Fh
202
Reserved
EMA_A[22]/GP4[6] Control
2h-7h
3-0
Type (1)
Description
X
Selects Function GP4[7]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.12 Pin Multiplexing Control 11 Register (PINMUX11)
Figure 10-29. Pin Multiplexing Control 11 Register (PINMUX11)
31
28
27
24
23
20
19
16
PINMUX11_31_28
PINMUX11_27_24
PINMUX11_23_20
PINMUX11_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX11_15_12
PINMUX11_11_8
PINMUX11_7_4
PINMUX11_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
Bit
31-28
Field
Value
PINMUX11_31_28
EMA_A[8]/GP5[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[8]
O
2h-7h
8h
9h-Fh
27-24
PINMUX11_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_A[9]
O
Reserved
X
PINMUX11_23_20
Selects Function GP5[9]
I/O
Reserved
X
EMA_A[10]/GP5[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[10]
O
2h-7h
8h
9h-Fh
PINMUX11_19_16
Reserved
X
Selects Function GP5[10]
I/O
Reserved
X
EMA_A[11]/GP5[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[11]
O
2h-7h
8h
9h-Fh
PINMUX11_15_12
Reserved
X
Selects Function GP5[11]
I/O
Reserved
X
EMA_A[12]/GP5[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[12]
O
2h-7h
8h
9h-Fh
(1)
I/O
0
8h
15-12
X
Selects Function GP5[8]
1h
9h-Fh
19-16
Reserved
EMA_A[9]/GP5[9] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP5[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX11_11_8
EMA_A[13]/GP5[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[13]
O
2h-7h
8h
9h-Fh
7-4
PINMUX11_7_4
X
Selects Function GP5[13]
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[14]
O
8h
9h-Fh
PINMUX11_3_0
Reserved
X
Selects Function GP5[14]
I/O
Reserved
X
EMA_A[15]/GP5[15] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[15]
O
2h-7h
8h
9h-Fh
204
Reserved
EMA_A[14]/GP5[14] Control
2h-7h
3-0
Type (1)
Description
Reserved
X
Selects Function GP5[15]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.13 Pin Multiplexing Control 12 Register (PINMUX12)
Figure 10-30. Pin Multiplexing Control 12 Register (PINMUX12)
31
28
27
24
23
20
19
16
PINMUX12_31_28
PINMUX12_27_24
PINMUX12_23_20
PINMUX12_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX12_15_12
PINMUX12_11_8
PINMUX12_7_4
PINMUX12_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
Bit
31-28
Field
Value
PINMUX12_31_28
EMA_A[0]/GP5[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX12_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_A[1]
O
Reserved
X
PINMUX12_23_20
Selects Function GP5[1]
I/O
Reserved
X
EMA_A[2]/GP5[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[2]
O
2h-7h
8h
9h-Fh
PINMUX12_19_16
Reserved
X
Selects Function GP5[2]
I/O
Reserved
X
EMA_A[3]/GP5[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[3]
O
2h-7h
8h
9h-Fh
PINMUX12_15_12
Reserved
X
Selects Function GP5[3]
I/O
Reserved
X
EMA_A[4]/GP5[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[4]
O
2h-7h
8h
9h-Fh
(1)
I/O
0
8h
15-12
X
Selects Function GP5[0]
1h
9h-Fh
19-16
Reserved
EMA_A[1]/GP5[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP5[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX12_11_8
EMA_A[5]/GP5[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[5]
O
2h-7h
8h
9h-Fh
7-4
PINMUX12_7_4
X
Selects Function GP5[5]
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[6]
O
8h
9h-Fh
PINMUX12_3_0
Reserved
X
Selects Function GP5[6]
I/O
Reserved
X
EMA_A[7]/GP5[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[7]
O
2h-7h
8h
9h-Fh
206
Reserved
EMA_A[6]/GP5[6] Control
2h-7h
3-0
Type (1)
Description
Reserved
X
Selects Function GP5[7]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.14 Pin Multiplexing Control 13 Register (PINMUX13)
Figure 10-31. Pin Multiplexing Control 13 Register (PINMUX13)
31
28
27
24
23
20
19
16
PINMUX13_31_28
PINMUX13_27_24
PINMUX13_23_20
PINMUX13_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX13_15_12
PINMUX13_11_8
PINMUX13_7_4
PINMUX13_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
Bit
31-28
Field
Value
PINMUX13_31_28
UHPI_HRW/GP6[8] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HRW
I
Reserved
X
3h-7h
8h
9h-Fh
27-24
PINMUX13_27_24
Pin is 3-stated.
Z
Reserved
X
2h
Selects Function UHPI_HHWIL
I
Reserved
X
PINMUX13_23_20
Selects Function GP6[9]
I/O
Reserved
X
UHPI_HCNTL1/GP6[10] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HCNTL1
I
Reserved
X
3h-7h
8h
9h-Fh
PINMUX13_19_16
Selects Function GP6[10]
I/O
Reserved
X
UHPI_HCNTL0/GP6[11] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HCNTL0
I
Reserved
X
3h-7h
8h
9h-Fh
PINMUX13_15_12
Selects Function GP6[11]
I/O
Reserved
X
UHPI_HINT/GP6[12] Control
0
Pin is 3-stated.
1h
Reserved
X
2h
Selects Function UHPI_HINT
O
Reserved
X
3h-7h
8h
9h-Fh
(1)
X
1h
9h-Fh
15-12
I/O
Reserved
UHPI_HHWIL/GP6[9] Control
8h
19-16
Selects Function GP6[8]
0
3h-7h
23-20
Type (1)
Description
Z
Selects Function GP6[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX13_11_8
UHPI_HRDY/GP6[13] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HRDY
O
Reserved
X
3h-7h
8h
9h-Fh
7-4
PINMUX13_7_4
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function CLKOUT
O
2h
Selects Function UHPI_HDS2
I
8h
9h-Fh
PINMUX13_3_0
Reserved
X
Selects Function GP6[14]
I/O
Reserved
X
RESETOUT/UHPI_HAS/GP6[15] Control
0
Selects Function RESETOUT
O
1h
Selects Function RESETOUT
O
2h
Selects Function UHPI_HAS
I
3h-7h
8h
9h-Fh
208
Selects Function GP6[13]
CLKOUT/UHPI_HDS2/GP6[14] Control
3h-7h
3-0
Type (1)
Description
Reserved
X
Selects Function GP6[15]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.15 Pin Multiplexing Control 14 Register (PINMUX14)
Figure 10-32. Pin Multiplexing Control 14 Register (PINMUX14)
31
28
27
24
23
20
19
16
PINMUX14_31_28
PINMUX14_27_24
PINMUX14_23_20
PINMUX14_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX14_15_12
PINMUX14_11_8
PINMUX14_7_4
PINMUX14_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
Bit
31-28
Field
Value
PINMUX14_31_28
UHPI_HD[10] Control
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[10]
3h-Fh
27-24
PINMUX14_27_24
Z
Reserved
X
2h
Selects Function UHPI_HD[11]
PINMUX14_23_20
I/O
Reserved
X
UHPI_HD[12] Control
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[12]
PINMUX14_19_16
Z
X
I/O
Reserved
X
UHPI_HD[13] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[13]
PINMUX14_15_12
I/O
Reserved
X
UHPI_HD[14] Control
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[14]
PINMUX14_11_8
Z
X
I/O
Reserved
X
UHPI_HD[15] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[15]
3h-Fh
(1)
X
Pin is 3-stated.
3h-Fh
11-8
Reserved
1h
3h-Fh
15-12
X
I/O
UHPI_HD[11] Control
3h-Fh
19-16
Z
0
3h-Fh
23-20
Type (1)
Description
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued)
Bit
Field
7-4
PINMUX14_7_4
Value
UHPI_HDS1/GP6[6] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HDS1
I
Reserved
X
3h-7h
8h
9h-Fh
3-0
PINMUX14_3_0
Selects Function GP6[6]
I/O
Reserved
X
UHPI_HCS/GP6[7] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HCS
I
3h-7h
8h
9h-Fh
210
Type (1)
Description
Reserved
X
Selects Function GP6[7]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.16 Pin Multiplexing Control 15 Register (PINMUX15)
Figure 10-33. Pin Multiplexing Control 15 Register (PINMUX15)
31
28
27
24
23
20
19
16
PINMUX15_31_28
PINMUX15_27_24
PINMUX15_23_20
PINMUX15_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX15_15_12
PINMUX15_11_8
PINMUX15_7_4
PINMUX15_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
Bit
31-28
Field
Value
PINMUX15_31_28
UHPI_HD[2] Control
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[2]
3h-Fh
27-24
PINMUX15_27_24
Z
Reserved
X
2h
Selects Function UHPI_HD[3]
PINMUX15_23_20
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[4]
PINMUX15_19_16
X
Z
X
I/O
Reserved
X
UHPI_HD[5] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[5]
PINMUX15_15_12
I/O
Reserved
X
UHPI_HD[6] Control
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[6]
PINMUX15_11_8
Z
X
I/O
Reserved
X
UHPI_HD[7] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[7]
PINMUX15_7_4
I/O
Reserved
X
UHPI_HD[8] Control
0
Pin is 3-stated.
1h
Reserved
2h
Selects Function UHPI_HD[8]
3h-Fh
(1)
I/O
Reserved
UHPI_HD[4] Control
3h-Fh
7-4
X
Pin is 3-stated.
3h-Fh
11-8
Reserved
1h
3h-Fh
15-12
X
I/O
UHPI_HD[3] Control
3h-Fh
19-16
Z
0
3h-Fh
23-20
Type (1)
Description
Z
X
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
Field
3-0
PINMUX15_3_0
Value
UHPI_HD[9] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[9]
3h-Fh
212
Type (1)
Description
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.17 Pin Multiplexing Control 16 Register (PINMUX16)
Figure 10-34. Pin Multiplexing Control 16 Register (PINMUX16)
31
28
27
24
23
20
19
16
PINMUX16_31_28
PINMUX16_27_24
PINMUX16_23_20
PINMUX16_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX16_15_12
PINMUX16_11_8
PINMUX16_7_4
PINMUX16_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
Bit
31-28
Field
Value
PINMUX16_31_28
GP7[10] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX16_27_24
1h-7h
8h
9h-Fh
PINMUX16_23_20
1h-7h
8h
9h-Fh
PINMUX16_19_16
1h-7h
8h
9h-Fh
PINMUX16_15_12
1h-7h
8h
9h-Fh
PINMUX16_11_8
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[11]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[12]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[13]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[14]
I/O
Reserved
X
GP7[15] Control
0
1h-7h
8h
9h-Fh
(1)
X
Selects Function GP7[10]
GP7[14] Control
0
11-8
Reserved
GP7[13] Control
0
15-12
Z
GP7[12] Control
0
19-16
Pin is 3-stated.
GP7[11] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[15]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued)
Bit
Field
7-4
PINMUX16_7_4
Value
UHPI_HD[0]/GP6[5] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[0]
3h-7h
8h
9h-Fh
3-0
PINMUX16_3_0
I/O
Reserved
X
Selects Function GP6[5]
I/O
Reserved
X
UHPI_HD[1] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function UHPI_HD[1]
3h-Fh
214
Type (1)
Description
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.18 Pin Multiplexing Control 17 Register (PINMUX17)
Figure 10-35. Pin Multiplexing Control 17 Register (PINMUX17)
31
28
27
24
23
20
19
16
PINMUX17_31_28
PINMUX17_27_24
PINMUX17_23_20
PINMUX17_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX17_15_12
PINMUX17_11_8
PINMUX17_7_4
PINMUX17_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
Bit
31-28
Field
Value
PINMUX17_31_28
GP7[2]/BOOT[2] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX17_27_24
1h-7h
8h
9h-Fh
PINMUX17_23_20
1h-7h
8h
9h-Fh
PINMUX17_19_16
1h-7h
8h
9h-Fh
PINMUX17_15_12
1h-7h
8h
9h-Fh
PINMUX17_11_8
1h-7h
8h
9h-Fh
PINMUX17_7_4
Reserved
X
Selects Function BOOT[3]
I
Reserved
X
Selects Function GP7[3]
I/O
Reserved
X
Selects Function BOOT[4]
I
Reserved
X
Selects Function GP7[4]
I/O
Reserved
X
Selects Function BOOT[5]
I
Reserved
X
Selects Function GP7[5]
I/O
Reserved
X
Selects Function BOOT[6]
I
Reserved
X
Selects Function GP7[6]
I/O
Reserved
X
Selects Function BOOT[7]
I
Reserved
X
Selects Function GP7[7]
I/O
Reserved
X
GP7[8] Control
0
1h-7h
8h
9h-Fh
(1)
I/O
GP7[7]/BOOT[7] Control
0
7-4
X
Selects Function GP7[2]
GP7[6]/BOOT[6] Control
0
11-8
Reserved
GP7[5]/BOOT[5] Control
0
15-12
I
GP7[4]/BOOT[4] Control
0
19-16
Selects Function BOOT[2]
GP7[3]/BOOT[3] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[8]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued)
Bit
Field
3-0
PINMUX17_3_0
Value
GP7[9] Control
0
1h-7h
8h
9h-Fh
216
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[9]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.19 Pin Multiplexing Control 18 Register (PINMUX18)
Figure 10-36. Pin Multiplexing Control 18 Register (PINMUX18)
31
28
27
24
23
20
19
16
PINMUX18_31_28
PINMUX18_27_24
PINMUX18_23_20
PINMUX18_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX18_15_12
PINMUX18_11_8
PINMUX18_7_4
PINMUX18_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
Bit
31-28
Field
Value
PINMUX18_31_28
GP8[10] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX18_27_24
1h-7h
8h
9h-Fh
PINMUX18_23_20
1h-7h
8h
9h-Fh
PINMUX18_19_16
1h-7h
8h
9h-Fh
PINMUX18_15_12
1h-7h
8h
9h-Fh
PINMUX18_11_8
1h-7h
8h
9h-Fh
PINMUX18_7_4
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[11]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[12]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[13]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[14]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[15]
I/O
Reserved
X
GP7[0]/BOOT[0] Control
0
1h-7h
8h
9h-Fh
(1)
I/O
GP8[15] Control
0
7-4
X
Selects Function GP8[10]
GP8[14] Control
0
11-8
Reserved
GP8[13] Control
0
15-12
Z
GP8[12] Control
0
19-16
Pin is 3-stated.
GP8[11] Control
0
23-20
Type (1)
Description
Selects Function BOOT[0]
I
Reserved
X
Selects Function GP7[0]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued)
Bit
Field
3-0
PINMUX18_3_0
Value
GP7[1]/BOOT[1] Control
0
1h-7h
8h
9h-Fh
218
Type (1)
Description
Selects Function BOOT[1]
I
Reserved
X
Selects Function GP7[1]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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10.5.10.20 Pin Multiplexing Control 19 Register (PINMUX19)
Figure 10-37. Pin Multiplexing Control 19 Register (PINMUX19)
31
28
27
24
23
20
19
16
PINMUX19_31_28
PINMUX19_27_24
PINMUX19_23_20
PINMUX19_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX19_15_12
PINMUX19_11_8
PINMUX19_7_4
PINMUX19_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
Bit
31-28
Field
Value
PINMUX19_31_28
GP8[0] Control. GP8[0] is initially configured as a reserved function after reset and
will not be in a predictable state. This signal will only be stable after the GPIO
configuration for this pin has been completed. You should carefully consider the
system implications of this pin being in an unknown state after reset.
0-7h
8h
9h-Fh
27-24
PINMUX19_27_24
1h-7h
8h
9h-Fh
PINMUX19_23_20
1h-7h
8h
9h-Fh
PINMUX19_19_16
1h-7h
8h
9h-Fh
PINMUX19_15_12
1h-7h
8h
9h-Fh
PINMUX19_11_8
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[0]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[1]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[2]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[3]
I/O
Reserved
X
GP6[4] Control
0
1h-7h
8h
9h-Fh
(1)
Reserved
GP6[3] Control
0
11-8
I/O
GP6[2] Control
0
15-12
X
Selects Function GP8[0]
GP6[1] Control
0
19-16
Reserved
GP6[0] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions (continued)
Bit
Field
7-4
PINMUX19_7_4
Value
GP8[8] Control
0
1h-7h
8h
9h-Fh
3-0
PINMUX19_3_0
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[8]
I/O
Reserved
X
GP8[9] Control
0
1h-7h
8h
9h-Fh
220
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[9]
I/O
Reserved
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X
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10.5.11 Suspend Source Register (SUSPSRC)
The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals
that support emulation suspend. A value of 1 (default) for a SUSPSRC bit corresponding to the peripheral,
indicates that the DSP emulator controls the peripheral's emulation suspend signal. You should maintain
this register with its default values.
The SUSPSRC is shown in Figure 10-38 and described in Table 10-42.
Figure 10-38. Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
Reserved
Reserved
Reserved
TIMER64P_1SRC
TIMER64P_0SRC
Reserved
Reserved
EPWM1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
23
22
21
20
19
18
17
16
EPWM0SRC
SPI1SRC
Reserved
Reserved
Reserved
UART0SRC
Reserved
I2C0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
HPISRC
Reserved
Reserved
Reserved
MCBSP1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
ECAP2SRC
ECAP1SRC
ECAP0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions
Bit
31-29
28
27
26-25
24
23
22
21-19
18
Field
Reserved
Value
1
TIMER64P_1SRC
Timer1 64 Emulation Suspend Source.
No emulation suspend.
1
DSP is the source of the emulation suspend.
Timer0 64 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
EPWM1SRC
EPWM1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
EPWM0SRC
EPWM0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
SPI1SRC
Reserved
SPI1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
UART0SRC
17
Reserved
16
I2C0SRC
Reserved. Write the default value to all bits when modifying this register.
0
TIMER64P_0SRC
Reserved
Description
UART0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
I2C0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
Field
15-13
Reserved
12
HPISRC
11-9
8
7-3
2
1
0
222
Reserved
Value
1
Reserved. Write the default value to all bits when modifying this register.
HPI Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
MCBSP1SRC
Reserved
Description
McBSP1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
ECAP2SRC
ECAP2 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP1SRC
ECAP1 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP0SRC
ECAP0 Emulation Suspend Source.
0
No emulation suspend.
1
DSP is the source of the emulation suspend.
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10.5.12 Chip Signal Register (CHIPSIG)
The interrupts to the DSP can be generated by setting one of the two CHIPSIG[3-2] bits or an NMI
interrupt by setting the CHIPSIG[4] bit in the chip signal register (CHIPSIG). Writing a 1 to these bits sets
the interrupts, writing a 0 has no effect. Reads return the value of these bits and can also be used as
status bits. The CHIPSIG is shown in Figure 10-39 and described in Table 10-43.
Figure 10-39. Chip Signal Register (CHIPSIG)
31
16
Reserved
R-0
15
4
3
2
Reserved
5
CHIPSIG4
CHIPSIG3
CHIPSIG2
Reserved
1
0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-43. Chip Signal Register (CHIPSIG) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1-0
Value
0
Reserved
Asserts DSP NMI interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG3
Asserts SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG2
Reserved
Description
Asserts SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Asserts interrupt
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.13 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 10-40 and described in Table 10-44.
For more information on DSP interrupts, see the DSP Subsystem chapter.
Figure 10-40. Chip Signal Clear Register (CHIPSIG_CLR)
31
16
Reserved
R-0
15
4
3
2
Reserved
5
CHIPSIG4
CHIPSIG3
CHIPSIG2
Reserved
1
0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1-0
224
Value
0
Reserved
Clears DSP NMI interrupt.
0
No effect
1
Clears interrupt
CHIPSIG3
Clears SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG2
Reserved
Description
Clears SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Clears interrupt
0
Reserved. Write the default value to all bits when modifying this register.
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10.5.14 Chip Configuration 0 Register (CFGCHIP0)
The chip configuration 0 register (CFGCHIP0) controls the following functions:
• PLL Controller 0 memory-mapped register lock: Used to lock out writes to the PLLC0 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC0 register space.
• EDMA3_0 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP0
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_0 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
The CFGCHIP0 is shown in Figure 10-41 and described in Table 10-45.
Figure 10-41. Chip Configuration 0 Register (CFGCHIP0)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PLL_MASTER_LOCK
EDMA30TC1DBS
EDMA30TC0DBS
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
Bit
31-5
4
3-2
1-0
Field
Reserved
Value
0
PLL_MASTER_LOCK
Description
Reserved.
PLLC0 MMRs lock.
0
PLLC0 MMRs are freely accessible.
1
All PLLC0 MMRs are locked.
EDMA30TC1DBS
EDMA3_0_TC1 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
EDMA30TC0DBS
EDMA3_0_TC0 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
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10.5.15 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• eCAP0/1/2 event input source: Allows using McASP0 TX/RX events as eCAP event input sources.
• EDMA3_1 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP1
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_1 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
• McASP0 AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP0 AMUTEIN signal.
The CFGCHIP1 is shown in Figure 10-42 and described in Table 10-46.
Figure 10-42. Chip Configuration 1 Register (CFGCHIP1)
31
27
26
22
21
17
16
CAP2SRC
CAP1SRC
CAP0SRC
HPIBYTEAD
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
8
HPIENA
EDMA31TC0DBS
TBCLKSYNC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
7
4
3
0
Reserved
AMUTESEL0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
Bit
31-27
Field
Value
CAP2SRC
Selects the eCAP2 module event input.
0
eCAP2 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-1Fh
26-22
CAP1SRC
0
eCAP1 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
CAP0SRC
Reserved
Selects the eCAP0 module event input.
0
eCAP0 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-1Fh
226
Reserved
Selects the eCAP1 module event input.
3h-1Fh
21-17
Description
Reserved
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Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued)
Bit
Field
16
HPIBYTEAD
15
14-13
12
Value
HPI Byte/Word Address Mode select.
0
Host address is a word address.
1
Host address is a byte address.
HPIENA
HPI Enable Bit.
0
HPI is disabled.
1
HPI is enabled.
EDMA31TC0DBS
EDMA3_1_TC0 Default Burst Size.
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
TBCLKSYNC
11-4
Reserved
3-0
AMUTESEL0
Description
eHRPWM Module Time Base Clock Synchronization. Allows you to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
0
Time base clock (TBCLK) within each enabled eHRPWM module is stopped.
1
All enabled eHRPWM module clocks are started with the first rising edge of TBCLK aligned. For
perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each eHRPWM
module must be set identically.
0
Reserved. Write the default value to all bits when modifying this register.
Selects the source of McASP0 AMUTEIN signal.
0
Drive McASP0 AMUTEIN signal low.
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
Reserved
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10.5.16 Chip Configuration 3 Register (CFGCHIP3)
The chip configuration 3 register (CFGCHIP3) controls the following peripheral/module functions:
• PLL Controller 1 memory-mapped register lock: Used to lock out writes to the PLLC1 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC1 register space.
• ASYNC3 Clock Source Control: Allows control for the source of the ASYNC3 clock.
• DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.5) hardware clock divider is provided to generate
133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this
clock divider.
• EMIFA Module Clock Source Control: Allows control for the source of the EMIFA module clock.
The CFGCHIP3 is shown in Figure 10-43 and described in Table 10-47.
Figure 10-43. Chip Configuration 3 Register (CFGCHIP3)
31
16
15
8
Reserved
Reserved
R-0
R/W-FFh
7
6
5
4
3
2
1
0
Reserved
Reserved
PLL1_MASTER_LOCK
ASYNC3_CLKSRC
Reserved
DIV45PENA
EMA_CLKSRC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-47. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
Reserved
FFh
Reserved. Write the default value to all bits when modifying this register.
7-6
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
5
4
Reserved
2
DIV45PENA
0
PLLC1 MMRs lock.
0
PLLC1 MMRs are freely accessible.
1
All PLLC1 MMRs are locked.
ASYNC3_CLKSRC
3
1
228
PLL1_MASTER_LOCK
Clock source for ASYNC3.
0
Clock driven by PLL0_SYSCLK2.
1
Clock driven by PLL1_SYSCLK2.
0
Reserved. Write the default value when modifying this register.
Controls the fixed DIV4.5 divider in the PLL controller.
0
Divide by 4.5 is disabled.
1
Divide by 4.5 is enabled.
EMA_CLKSRC
Reserved
Reserved
Clock source for EMIFA clock domain.
0
Clock driven by PLL0_SYSCLK3
1
Clock driven by DIV4.5 PLL output
0
Reserved. Write the default value when modifying this register.
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10.5.17 Chip Configuration 4 Register (CFGCHIP4)
The chip configuration 4 register (CFGCHIP4) is used for clearing the AMUNTEIN signal for McASP0.
Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0, if it was
previously set; reads always return a value of 0. The CFGCHIP4 is shown in Figure 10-44 and described
in Table 10-48.
Figure 10-44. Chip Configuration 4 Register (CFGCHIP4)
31
16
Reserved
R-0
15
8
7
1
0
Reserved
Reserved
AMUTECLR0
R/W-FFh
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-48. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
Reserved
FFh
Reserved. Write the default value to all bits when modifying this register.
7-1
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
0
AMUTECLR0
Reserved
Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1.
0
No effect
1
Clears interrupt
10.5.18 VTP I/O Control Register (VTPIO_CTL)
The VTP I/O control register (VTPIO_CTL) is used to control the calibration of the DDR2/mDDR memory
controller I/Os with respect to voltage, temperature, and process (VTP). The voltage, temperature, and
process information is used to control the IO's output impedance. The VTPIO_CTL is shown in Figure 1045 and described in Table 10-49.
Figure 10-45. VTP I/O Control Register (VTPIO_CTL)
31
24
Reserved
R-0
23
19
18
17
16
Reserved
VREFEN
VREFTAP
R-0
R/W-0
R/W-0
15
14
13
READY
IOPWRDN
CLKRZ
12
Reserved
9
PWRSAVE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
5
7
6
LOCK
POWERDN
D
3
2
F
R/W-0
R/W-1
R/W-6h
R/W-7h
8
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 10-49. VTP I/O Control Register (VTPIO_CTL) Field Descriptions
Bit
Field
31-19
Reserved
18
VREFEN
17-16
Value
0
0
Connected to pad, external reference.
1
Reserved
VREFTAP
Selection for internal reference voltage level.
0
14
13
12-9
8
7
6
5-3
READY
Reserved
0
VTP is not ready.
1
VTP is ready.
IOPWRDN
Power down enable for DDR input buffer.
0
Disable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
1
Enable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
CLKRZ
0
VTP clear. Write 0 to clear VTP flops.
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
PWRSAVE
VTP power save mode. Turn off power to the external resistor when it is not needed. The
PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0.
0
Disable power save mode.
1
Enable power save mode.
LOCK
VTP impedance lock. Lock impedance value so that the VTP controller can be powered down.
0
Unlock impedance.
1
Lock impedance.
POWERDN
VTP power down. Power down the VTP controller. The PWRSAVE bit setting is only valid when
the POWERDN bit is cleared to 0.
0
Disable power down.
1
Enable power down.
D
Drive strength control bit.
Reserved
6h
100% drive strength
7h
Reserved
F
Digital filter control bit.
0-6h
7h
230
Vref = 50.0% of VDDS
VTP Ready status.
0-5h
2-0
Reserved
Internal DDR I/O Vref enable.
1h-3h
15
Description
Reserved
Digital filter is enabled.
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10.5.19 DDR Slew Register (DDR_SLEW)
The DDR slew register (DDR_SLEW) reflects the DDR I/O timing as programmed in the device eFuse.
The CMOSEN field configures the DDR I/O cells into an LVCMOS buffer (this makes it mDDR
compatible). The DDR_SLEW is shown in Figure 10-46 and described in Table 10-50.
Figure 10-46. DDR Slew Register (DDR_SLEW)
31
16
Reserved
R-0
15
12
7
11
10
9
8
Reserved
ODT_TERMON
ODT_TERMOFF
R-0
R/W-0
R/W-0
5
4
Reserved
6
DDR_PDENA
CMOSEN
3
DDR_DATASLEW
2
1
DDR_CMDSLEW
0
R-0
R/W-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-50. DDR Slew Register (DDR_SLEW) Field Descriptions
Bit
Field
31-12
Reserved
11-10
ODT_TERMON
Value
0
0
ODT_TERMOFF
5
4
3-2
Reserved
Reserved
No termination
1h-3h
Reserved
0
Reserved
DDR_PDENA
Enables pull downs for mDDR mode (should be disabled for DDR2).
0
Pull downs are disabled. Disable pull downs when using DDR2.
1
Pull downs are enabled. Enable pull downs when using mDDR.
CMOSEN
Selects mDDR LVCMOS RX / SSTL18 differential RX.
0
SSTL Receiver. Select SSTL when using DDR2.
1
LVCMOS Receiver. Select LVCMOS when using mDDR.
DDR_DATASLEW
Slew rate mode control status for data macro. Slew rate control is not supported on this
device.
0
1h-3h
1-0
No termination
Controls Thevenin termination mode while I/O is not in read or write mode. Termination is
not supported on this device.
0
7-6
Reserved
Controls Thevenin termination mode while I/O is in read or write mode. Termination is not
supported on this device.
1h-3h
9-8
Description
DDR_CMDSLEW
Slew rate control is off.
Reserved
Slew rate mode control status for command macro. Slew rate control is not supported on
this device.
0
1h-3h
Slew rate control is off.
Reserved
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10.5.20 Deep Sleep Register (DEEPSLEEP)
The deep sleep register (DEEPSLEEP) control the Deep Sleep logic. See your device-specific data
manual and the Boot Considerations chapter for details on boot and configuration settings. The
DEEPSLEEP is shown in Figure 10-47 and described in Table 10-51.
Figure 10-47. Deep Sleep Register (DEEPSLEEP)
31
30
SLEEPENABLE
SLEEPCOMPLETE
29
Reserved
16
R/W-0
R-0
R-0
15
0
SLEEPCOUNT
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-51. Deep Sleep Register (DEEPSLEEP) Field Descriptions
Bit
Field
31
SLEEPENABLE
30
Reserved
15-0
SLEEPCOUNT
Description
Deep sleep enable. The software must clear this bit to 0 when the device is awakened from
deep sleep.
0
Device is in normal operating mode; DEEPSLEEP pin has no effect.
1
Deep sleep mode is enabled; setting DEEPSLEEP pin low initiates oscillator shut down.
SLEEPCOMPLETE
29-16
232
Value
Deep sleep complete. Once the deep sleep process starts, the software must poll the
SLEEPCOMPLETE bit; when the SLEEPCOMPLETE bit is read as 1, the software should
clear the SLEEPENABLE bit and continue operation.
0
SLEEPCOUNT delay is not complete.
1
SLEEPCOUNT delay is complete.
0
Reserved
0-FFFFh
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16
bits are tied directly to the counter in the Deep Sleep logic.
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10.5.21 Pullup/Pulldown Enable Register (PUPD_ENA)
The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin
group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 10-48 and
described in Table 10-52.
Figure 10-48. Pullup/Pulldown Enable Register (PUPD_ENA)
31
0
PUPDENA[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-52. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions
Bit
31-0
Field
Value
PUPDENA[n]
Description
Enables internal pull-up or pull-down functionality for pin group CP[n]. See your devicespecific data manual for pin group information. The internal pull-up or pull-down functionality
selection for bit position n in PUPD_ENA is set in the same bit position n of the pullup/pulldown
select register (PUPD_SEL).
0
Internal pull-up or pull-down functionality for pin group n is disabled.
1
Internal pull-up or pull-down functionality for pin group n is enabled.
10.5.22 Pullup/Pulldown Select Register (PUPD_SEL)
The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for
the pin group n defined in your device-specific data manual. The PUPD_SEL is shown in Figure 10-49 and
described in Table 10-53 and Table 10-54.
NOTE: The PUPD_SEL settings are not active until the device is out of reset. During reset, all of the
CP[n] pins are pulled down. If the application requires a pull-up during reset, an external pullup should be used.
Figure 10-49. Pullup/Pulldown Select Register (PUPD_SEL)
31
0
PUPDSEL[n]
R/W-C3FF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-53. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions
Bit
31-0
Field
Value
PUPDSEL[n]
Description
Selects between the internal pull-up or pull-down functionality for pin group CP[n]. See your
device-specific data manual for pin group information. The selection for bit position n in PUPD_SEL
is only valid when the same bit position n is set in the pullup/pulldown enable register
(PUPD_ENA).
0
Internal pull-down functionality for pin group n is disabled.
1
Internal pull-up functionality for pin group n is enabled.
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Table 10-54. Pullup/Pulldown Select Register (PUPD_SEL) Default Values
234
Default
Value
Bit
Field
31
PUPDSEL[31]
1
Pin Group CP[31] is configured for pull-up by default.
30
PUPDSEL[30]
1
Pin Group CP[30] is configured for pull-up by default.
29
PUPDSEL[29]
0
Pin Group CP[29] is configured for pull-down by default.
28
PUPDSEL[28]
0
Pin Group CP[28] is configured for pull-down by default.
27
PUPDSEL[27]
0
Pin Group CP[27] is configured for pull-down by default.
26
PUPDSEL[26]
0
Pin Group CP[26] is configured for pull-down by default.
25
PUPDSEL[25]
1
Pin Group CP[25] is configured for pull-up by default.
24
PUPDSEL[24]
1
Pin Group CP[24] is configured for pull-up by default.
23
PUPDSEL[23]
1
Pin Group CP[23] is configured for pull-up by default.
22
PUPDSEL[22]
1
Pin Group CP[22] is configured for pull-up by default.
21
PUPDSEL[21]
1
Pin Group CP[21] is configured for pull-up by default.
20
PUPDSEL[20]
1
Pin Group CP[20] is configured for pull-up by default.
19
PUPDSEL[19]
1
Pin Group CP[19] is configured for pull-up by default.
18
PUPDSEL[18]
1
Pin Group CP[18] is configured for pull-up by default.
17
PUPDSEL[17]
1
Pin Group CP[17] is configured for pull-up by default.
16
PUPDSEL[16]
1
Pin Group CP[16] is configured for pull-up by default.
15
PUPDSEL[15]
1
Pin Group CP[15] is configured for pull-up by default.
14
PUPDSEL[14]
1
Pin Group CP[14] is configured for pull-up by default.
13
PUPDSEL[13]
1
Pin Group CP[13] is configured for pull-up by default.
12
PUPDSEL[12]
1
Pin Group CP[12] is configured for pull-up by default.
11
PUPDSEL[11]
1
Pin Group CP[11] is configured for pull-up by default.
10
PUPDSEL[10]
1
Pin Group CP[10] is configured for pull-up by default.
9
PUPDSEL[9]
1
Pin Group CP[9] is configured for pull-up by default.
8
PUPDSEL[8]
1
Pin Group CP[8] is configured for pull-up by default.
7
PUPDSEL[7]
1
Pin Group CP[7] is configured for pull-up by default.
6
PUPDSEL[6]
1
Pin Group CP[6] is configured for pull-up by default.
5
PUPDSEL[5]
1
Pin Group CP[5] is configured for pull-up by default.
4
PUPDSEL[4]
1
Pin Group CP[4] is configured for pull-up by default.
3
PUPDSEL[3]
1
Pin Group CP[3] is configured for pull-up by default.
2
PUPDSEL[2]
1
Pin Group CP[2] is configured for pull-up by default.
1
PUPDSEL[1]
1
Pin Group CP[1] is configured for pull-up by default.
0
PUPDSEL[0]
1
Pin Group CP[0] is configured for pull-up by default.
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10.5.23 RXACTIVE Control Register (RXACTIVE)
The RXACTIVE control register (RXACTIVE) enables or disables the LVCMOS receivers for the pin group
n defined in your device-specific data manual. The RXACTIVE is shown in Figure 10-50 and described in
Table 10-55.
Figure 10-50. RXACTIVE Control Register (RXACTIVE)
31
0
RXACTIVE[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-55. RXACTIVE Control Register (RXACTIVE) Field Descriptions
Bit
31-0
Field
Value
RXACTIVE[n]
Description
Enables the LVCMOS receivers on pin group n. See your device-specific data manual for pin group
information. Receivers should only be disabled if the associated pin group is not being used.
0
LVCMOS receivers for pin group n are disabled.
1
LVCMOS receivers for pin group n are enabled.
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Boot Considerations
Topic
11.1
236
...........................................................................................................................
Page
Introduction ..................................................................................................... 237
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11.1 Introduction
This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• HPI boot
• I2C0 boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI1 boot
– Serial Flash (Master Mode)
– Serial EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0 boot
– External Host
See Using the TMS320C6748/C6746/C6742 Bootloader Application Report (SPRAAT2) for more details
on the ROM Boot Loader, a list of boot pins used, and the complete list of supported boot modes.
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Chapter 12
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DDR2/mDDR Memory Controller
This chapter describes the DDR2/mobile DDR (mDDR) memory controller.
Topic
12.1
12.2
12.3
12.4
238
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Supported Use Cases .......................................................................................
Registers .........................................................................................................
DDR2/mDDR Memory Controller
Page
239
241
269
274
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12.1 Introduction
12.1.1 Purpose of the Peripheral
The DDR2/mDDR memory controller is used to interface with JESD79D-2 standard compliant DDR2
SDRAM devices and JESD209 standard mobile DDR (mDDR) SDRAM devices. Memories types such as
DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The
DDR2/mDDR memory is the major memory location for program and data storage.
12.1.2 Features
The DDR2/mDDR memory controller supports the following features:
• JESD79D-2 standard compliant DDR2 SDRAM
• JESD209 standard compliant mobile DDR (mDDR)
• Data bus width of 16 bits
• CAS latencies:
– DDR2: 2, 3, 4, and 5
– mDDR: 2 and 3
• Internal banks:
– DDR2: 1, 2, 4, and 8
– mDDR: 1, 2, and 4
• Burst length: 8
• Burst type: sequential
• 1 CS signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM auto-initialization
• Self-refresh mode
• Partial array self-refresh (for mDDR)
• Power-down mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little-endian mode
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12.1.3 Functional Block Diagram
The DDR2/mDDR memory controller is the main interface to external DDR2/mDDR memory. Figure 12-1
displays the general data paths to on-chip peripherals and external DDR2/mDDR SDRAM.
Master peripherals, EDMA, and the CPU can access the DDR2/mDDR memory controller through the
switched central resource (SCR).
Figure 12-1. Data Paths to DDR2/mDDR Memory Controller
CPU
Master
peripherals
SCR
BUS
DDR2/mDDR
memory
controller
BUS
External
DDR2/mDDR SDRAM
EDMA
12.1.4 Supported Use Case Statement
The DDR2/mDDR memory controller supports JESD79D-2 DDR2 SDRAM memories and the JESD209
mobile DDR (mDDR) SDRAM memories utilizing 16 bits of the DDR2/mDDR memory controller data bus.
See Section 12.3 for more details.
12.1.5 Industry Standard(s) Compliance Statement
The DDR2/mDDR memory controller is compliant with the JESD79D-2 DDR2 SDRAM standard and the
JESD209 mobile DDR (mDDR) standard with the following exception:
• On-Die Termination (ODT). The DDR2/mDDR memory controller does not include any on-die
terminating resistors. Furthermore, the on-die terminating resistors of the DDR2/mDDR SDRAM device
must be disabled by tying the ODT input pin of the DDR2/mDDR SDRAM to ground.
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12.2 Architecture
This section describes the architecture of the DDR2/mDDR memory controller as well as how it is
structured and how it works within the context of the system-on-a-chip. The DDR2/mDDR memory
controller can gluelessly interface to most standard DDR2/mDDR SDRAM devices and supports such
features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through
programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections include details on how to interface and properly configure the DDR2/mDDR
memory controller to perform read and write operations to externally-connected DDR2/mDDR SDRAM
devices. Also, Section 12.3 provides a detailed example of interfacing the DDR2/mDDR memory controller
to a common DDR2/mDDR SDRAM device.
12.2.1 Clock Control
The DDR2/mDDR memory controller receives two input clocks from internal clock sources, VCLK and
2X_CLK (Figure 12-2). VCLK is a divided-down version of the PLL0 clock. 2X_CLK is the PLL1 clock.
2X_CLK should be configured to clock at the frequency of the desired data rate, or stated similarly, it
should operate at twice the frequency of the desired DDR2/mDDR memory clock. DDR_CLK and
DDR_CLK are the two output clocks of the DDR2/mDDR memory controller providing the interface clock
to the DDR2/mDDR SDRAM memory. These two clocks operate at a frequency of 2X_CLK/2.
12.2.1.1 Clock Source
VCLK and 2X_CLK are sourced from two independent PLLs (Figure 12-2). VCLK is sourced from PLL
controller 0 (PLLC0) and 2X_CLK is sourced from PLL controller 1 (PLLC1).
VCLK is clocked at a fixed divider ratio of PLL0. This divider is fixed at 2, meaning VCLK is clocked at a
frequency of PLL0/2.
The clock from PLLC1 is not divided before reaching 2X_CLK. PLLC1 should be configured to supply
2X_CLK at the desired frequency. For example, if a 138-MHz DDR2/mDDR interface clock (DDR_CLK) is
desired, then PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK.
Figure 12-2. DDR2/mDDR Memory Controller Clock Block Diagram
DDR_CLK
DDR_CLK
DDR2
memory
controller
VCLK
2X_CLK
/1
PLLC1
/2
PLLC0
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12.2.1.2 Clock Configuration
The frequency of 2X_CLK is configured by selecting the appropriate PLL multiplier. The PLL multiplier is
selected by programming registers within PLLC1. The PLLC1 divider ration is fixed at 1. For information
on programming the PLL controllers, see the Phase-Locked Loop Controller (PLLC) chapter. For
information on supported clock frequencies, see the Device Clocking chapter and your device-specific
data manual.
NOTE: PLLC1 should be configured and a stable clock present on 2X_CLK before releasing the
DDR2/mDDR memory controller from reset.
12.2.1.3 DDR2/mDDR Memory Controller Internal Clock Domains
There are two clock domains within the DDR2/mDDR memory controller. The two clock domains are
driven by VCLK and a divided-down by 2 version of 2X_CLK called MCLK. The command FIFO, write
FIFO, and read FIFO described in Section 12.2.6 are all on the VCLK domain. From this, VCLK drives the
interface to the peripheral bus.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
To conserve power within the DDR2/mDDR memory controller, VCLK, MCLK, and 2X_CLK may be
stopped. See Section 12.2.16 for proper clock stop procedures.
12.2.2 Signal Descriptions
The DDR2/mDDR memory controller signals are shown in Figure 12-3 and described in DDR2/mDDR
Memory Controller Signal Descriptions. The following features are included:
•
•
•
•
•
The maximum data bus is 16-bits wide.
The address bus is 14-bits wide with an additional three bank address pins.
Two differential output clocks driven by internal clock sources.
Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.
One chip select signal and one clock enable signal.
Figure 12-3. DDR2/mDDR Memory Controller Signals
DDR_CLK
DDR_CLK
DDR_CKE
DDR2
memory
controller
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_BA[2:0]
DDR_A[13:0]
DDR_D[15:0]
DDR_DQGATE0
DDR_DQGATE1
DDR_VREF
50 Ω
DDR_ZP
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DDR2/mDDR Memory Controller Signal Descriptions
(1)
Pin
Type
DDR_CLK,
DDR_CLK
O/Z
Clock: Differential clock outputs.
DDR_CKE
O/Z
Clock enable: Active high.
DDR_CS
O/Z
Chip select: Active low.
DDR_WE
O/Z
Write enable strobe: Active low, command output.
DDR_RAS
O/Z
Row address strobe: Active low, command output.
DDR_CAS
O/Z
Column address strobe: Active low, command output.
DDR_DQM[1:0]
O/Z
Data mask: Active high, output mask signal for write data.
DDR_DQS[1:0]
I/O/Z
Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
DDR_BA[2:0]
O/Z
Bank select: Output, defining which bank a given command is applied.
DDR_A[13:0]
O/Z
Address: Address bus.
DDR_D[15:0]
I/O/Z
Data: Bi-directional data bus. Input for read data, output for write data.
DDR_DQGATE0
O/Z
Strobe Enable: Active high.
DDR_DQGATE1
I/O/Z
Strobe Enable Delay: Loopback signal for timing adjustment (DQS gating). Route from
DDR_DQGATE0 to DDR device and back to DDR_DQGATE1 with same constraints as used for
DDR clock and data.
DDR_ZP
I/O/Z
Output drive strength reference: Reference output for drive strength calibration of N and P
channel outputs. Tie to ground via 50 ohm .5% tolerance 1/16th watt resistor (49.9 ohm .5%
tolerance is acceptable).
DDR_VREF
pwr
Voltage reference input: Voltage reference input for the SSTL_18 I/O buffers. Note even in the
case of mDDR an external resistor divider connected to this pin is necessary.
(1)
Description
Legend: I = input, O = Output, Z = high impedance, pwr = power
12.2.3 Protocol Description(s)
The DDR2/mDDR memory controller supports the DDR2/mDDR SDRAM commands listed in Table 12-1.
Table 12-2 shows the signal truth table for the DDR2/mDDR SDRAM commands.
Table 12-1. DDR2/mDDR SDRAM Commands
Command
Function
ACTV
Activates the selected bank and row.
DCAB
Precharge all command. Deactivates (precharges) all banks.
DEAC
Precharge single command. Deactivates (precharges) a single bank.
DESEL
Device Deselect.
EMRS
Extended Mode Register set. Allows altering the contents of the mode register.
MRS
Mode register set. Allows altering the contents of the mode register.
NOP
No operation.
Power Down
Power-down mode.
READ
Inputs the starting column address and begins the read operation.
READ with
autoprecharge
Inputs the starting column address and begins the read operation. The read operation is followed by a
precharge.
REFR
Autorefresh cycle.
SLFREFR
Self-refresh mode.
WRT
Inputs the starting column address and begins the write operation.
WRT with
autoprecharge
Inputs the starting column address and begins the write operation. The write operation is followed by a
precharge.
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Table 12-2. Truth Table for DDR2/mDDR SDRAM Commands
DDR2/mDDR
SDRAM:
DDR2/mDDR
memory
controller:
244
CKE
CS
RAS
CAS
WE
BA[2:0]
A[13:11, 9:0]
A10
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_CKE
Previous
Cycles
Current
Cycle
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA[2:0]
ACTV
H
H
L
L
H
H
Bank
DCAB
H
H
L
L
H
L
X
X
DEAC
H
H
L
L
H
L
Bank
X
MRS
H
H
L
L
L
L
BA
EMRS
H
H
L
L
L
L
BA
READ
H
H
L
H
L
H
BA
Column Address
L
READ with
precharge
H
H
L
H
L
H
BA
Column Address
H
WRT
H
H
L
H
L
L
BA
Column Address
L
WRT with
precharge
H
H
L
H
L
L
BA
Column Address
H
REFR
H
H
L
L
L
H
X
X
X
SLFREFR
entry
H
L
L
L
L
H
X
X
X
SLFREFR
exit
L
H
H
X
X
X
X
X
X
L
H
H
H
X
X
X
NOP
H
X
L
H
H
H
X
X
X
DESEL
H
X
H
X
X
X
X
X
X
Power Down
entry
H
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
Power Down
exit
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
H
DDR2/mDDR Memory Controller
Row Address
H
L
OP Code
OP Code
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12.2.3.1 Refresh Mode
The DDR2/mDDR memory controller issues refresh commands to the DDR2/mDDR SDRAM memory
(Figure 12-4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE
spaces and banks selected. Following the DCAB command, the DDR2/mDDR memory controller begins
performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register
(SDRCR). Page information is always invalid before and after a REFR command; thus, a refresh cycle
always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands
may not be disabled within the DDR2/mDDR memory controller. See Section 12.2.7 for more details on
REFR command scheduling.
Figure 12-4. Refresh Command
RFR
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
DDR_BA[2:0]
DDR_DQM[1:0]
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12.2.3.2 Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2/mDDR memory
controller or following the initialization sequence. DDR2/mDDR SDRAMs also require this cycle prior to a
refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command,
DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 12-5 shows the timing diagram for
a DCAB command.
Figure 12-5. DCAB Command
DCAB
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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The DEAC command closes a single bank of memory specified by the bank select signals. Figure 12-6
shows the timings diagram for a DEAC command.
Figure 12-6. DEAC Command
DEAC
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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12.2.3.3 Activation (ACTV)
The DDR2/mDDR memory controller automatically issues the activate (ACTV) command before a read or
write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses
(reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of
DDR_A[13:0] selects the row. When the DDR2/mDDR memory controller issues an ACTV command, a
delay of tRCD is incurred before a read or write command is issued. Figure 12-7 shows an example of an
ACTV command. Reads or writes to the currently active row and bank of memory can achieve much
higher throughput than reads or writes to random areas because every time a new row is accessed, the
ACTV command must be issued and a delay of tRCD incurred.
Figure 12-7. ACTV Command
DDR_CLK
DDR_CLK
ACTV
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
ROW
DDR_BA[2:0]
BANK
DDR_DQM[1:0]
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12.2.3.4 READ Command
Figure 12-8 shows the DDR2/mDDR memory controller performing a read burst from DDR2/mDDR
SDRAM. The READ command initiates a burst read operation to an active row. During the READ
command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on
DDR_A[13:0], and the bank address is driven on DDR_BA[2:0].
The DDR2/mDDR memory controller uses a burst length of 8, and has a programmable CAS latency of 2,
3, 4, or 5. The CAS latency is three cycles in Figure 12-8. Read latency is equal to CAS latency plus
additive latency. The DDR2/mDDR memory controller always configures the memory to have an additive
latency of 0, so read latency equals CAS latency. Since the default burst size is 8, the DDR2/mDDR
memory controller returns 8 pieces of data for every read command. If additional accesses are not
pending to the DDR2/mDDR memory controller, the read burst completes and the unneeded data is
disregarded. If additional accesses are pending, depending on the scheduling result, the DDR2/mDDR
memory controller can terminate the read burst and start a new read burst. Furthermore, the DDR2/mDDR
memory controller does not issue a DAB/DEAC command until page information becomes invalid.
Figure 12-8. DDR2/mDDR READ Command
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
CAS Latency
D0
DDR_D[15:0]
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
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12.2.3.5 Write (WRT) Command
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the
WRT command, a write latency is incurred. For DDR2, write latency is equal to CAS latency minus 1
cycles. For mDDR, write latency is equal to 1 cycle, always. All writes have a burst length of 8. The use of
the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 12-9 shows the timing for a
DDR2 write on the DDR2/mDDR memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pending
commands, the DDR2/mDDR memory controller can:
• Mask out the additional data using DDR_DQM outputs
• Terminate the write burst and start a new write burst
The DDR2/mDDR memory controller does not perform the DEAC command until page information
becomes invalid.
Figure 12-9. DDR2/mDDR WRT Command
DDR_CLK
DDR_CLK
Sample
Write Latency
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
DDR_D[15:0]
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
D0
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
NOTE: This diagrams shows write latency for DDR2. For mDDR, write latency is always equal to 1 cycle.
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12.2.3.6 Mode Register Set (MRS and EMRS)
DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on DDR2/mDDR device), single-ended strobe, differential strobe etc.
The DDR2/mDDR memory controller programs the mode and extended mode registers of the
DDR2/mDDR memory by issuing MRS and EMRS commands. When the MRS or EMRS command is
executed, the value on DDR_BA[2:0] selects the mode register to be written and the data on DDR_A[13:0]
is loaded into the register. Figure 12-10 shows the timing for an MRS and EMRS command.
The DDR2/mDDR memory controller only issues MRS and EMRS commands during the DDR2/mDDR
memory controller initialization sequence. See Section 12.2.13 for more information.
Figure 12-10. DDR2/mDDR MRS and EMRS Command
MRS/EMRS
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
12.2.4 Memory Width and Byte Alignment
The DDR2/mDDR memory controller supports memory widths of 16 bits. Table 12-3 summarizes the
addressable memory ranges on the DDR2/mDDR memory controller. Only little-endian format is
supported. Figure 12-11 shows the byte lanes used on the DDR2/mDDR memory controller. The external
memory is always right aligned on the data bus.
Table 12-3. Addressable Memory Ranges
Memory Width
Maximum addressable bytes per CS space
Description
×16
256 Mbytes
Halfword address
Figure 12-11. Byte Alignment
DDR2 memory controller data bus
DDR_D[15:8]
DDR_D[7:0]
16-bit memory device
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12.2.5 Address Mapping
The memory controller views the DDR2/mDDR SDRAM device as one continuous block of memory. The
memory controller receives memory access requests with a 32-bit logical address, and it uses the logical
address to generate a row, column, and bank address for accessing the DDR2/mDDR SDRAM device.
The memory controller supports two address mapping schemes: normal address mapping and special
address mapping. Special address mapping is typically used only with mDDR devices using partial array
self-refresh.
When the internal bank position (IBANKPOS) bit in the SDRAM configuration register (SDCR) is cleared,
the memory controller operates with normal address mapping. In this case, the number of column and
bank address bits is determined by the IBANK and PAGESIZE fields in SDCR. The number of row
address bits is determined by the number of valid address pins for the device and does not need to be set
in a register.
When IBANKPOS is set to 1, the memory controller operates with special address mapping. In this case,
the number of column, row, and bank address bits is determined by the PAGESIZE, ROWSIZE, and
IBANK fields. The ROWSIZE field is in the SDRAM configuration register 2 (SDCR2). See Table 12-4 for a
descriptions of these bit fields.
Table 12-4. Configuration Register Fields for Address Mapping
Bit Field
Bit Value
IBANK
Defines the number of internal banks in the external DDR2/mDDR memory.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
PAGESIZE
Defines the page size of each page in the external DDR2/mDDR memory.
0
256 words (requires 8 column address bits)
1h
512 words (requires 9 column address bits)
2h
1024 words (requires 10 column address bits)
3h
2048 words (requires 11 column address bits)
ROWSIZE
252
Bit Description
Defines the row size of each row in the external DDR2/mDDR memory
0
512 (requires 9 row address bits)
1h
1024 (requires 10 row address bits)
2h
2048 (requires 11 row address bits)
3h
4096 (requires 12 row address bits)
4h
8192 (requires 13 row address bits)
5h
16384 (requires 14 row address bits)
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12.2.5.1 Normal Address Mapping (IBANKPOS = 0)
As stated in Table 12-4, the IBANK and PAGESIZE fields of SDCR control the mapping of the logical,
source address of the DDR2/mDDR memory controller to the DDR2/mDDR SDRAM row, column, and
bank address bits. The DDR2/mDDR memory controller logical address always contains up to 14 row
address bits, whereas the number of column and bank bits are determined by the IBANK and PAGESIZE
fields. Table 12-5 show how the logical address bits map to the DDR2/mDDR SDRAM row, column, and
bank bits for combinations of IBANK and PAGESIZE values. The same DDR2/mDDR memory controller
pins provide the row and column address to the DDR2/mDDR SDRAM, thus the DDR2/mDDR memory
controller appropriately shifts the address during row and column address selection.
Logical Address-to-DDR2/mDDR SDRAM Address Map shows how this address-mapping scheme
organizes the DDR2/mDDR SDRAM rows, columns, and banks into the device memory-map. Note that
during a linear access, the DDR2/mDDR memory controller increments the column address as the logical
address increments. When the DDR2/mDDR memory controller reaches a page/row boundary, it moves
onto the same page/row in the next bank. This movement continues until the same page has been
accessed in all banks. To the DDR2/mDDR SDRAM, this process looks as shown in Figure 12-12.
By traversing across banks while remaining on the same row/page, the DDR2/mDDR memory controller
maximizes the number of activated banks for a linear access. This results in the maximum number of
open pages when performing a linear access being equal to the number of banks. Note that the
DDR2/mDDR memory controller never opens more than one page per bank.
Ending the current access is not a condition that forces the active DDR2/mDDR SDRAM row to be closed.
The DDR2/mDDR memory controller leaves the active row open until it becomes necessary to close it.
This decreases the deactivate-reactivate overhead.
Table 12-5. Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM
SDCR Bit
Logical Address
IBANK
PAGESIZE
31
0
0
-
1
0
-
2h
0
-
3h
0
-
0
1
-
1
1
-
2h
1
-
3h
1
-
0
2h
-
1
2h
-
2h
2h
-
3h
2h
-
0
3h
-
1
3h
-
2h
3h
-
3h
3h
-
30
29
28
27
26
25
24
23
22
21:15
14
13
12
11
10
9
nrb=14
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
0
ncb=8
ncb=8
nbb=3
ncb=8
nrb=14
ncb=9
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=9
ncb=9
nbb=3
ncb=9
nrb=14
ncb=10
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=10
ncb=10
nbb=3
ncb=10
nrb=14
ncb=11
nrb=14
nbb=1
nrb=14
nrb=14
8:1
ncb=8
nbb=2
nbb=3
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ncb=11
ncb=11
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Logical Address-to-DDR2/mDDR SDRAM Address Map
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 0
Row 1, bank 1
Row 1, bank 2
Row 1, bank P
Row N, bank 0
Row N, bank 1
Row N, bank 2
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
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Logical Address-to-DDR2/mDDR SDRAM Address Map (continued)
Figure 12-12. DDR2/mDDR SDRAM Column, Row, and Bank Access
Bank 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Bank 1
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Bank 2
Row 2
Row 0
Row 1
Bank P
Row 2
Row 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Row 2
Row N
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
12.2.5.2 Special Address Mapping (IBANKPOS = 1)
When the internal bank position (IBANKPOS) bit is set to 1, the PAGESIZE, ROWSIZE, and IBANK fields
control the mapping of the logical source address of the memory controller to the column, row, and bank
address bits of the SDRAM device. Table 12-6 shows which source address bits map to the SDRAM
column, row, and bank address bits for all combinations of PAGESIZE, ROWSIZE, and IBANK.
When IBANKPOS is set to 1, the effect of the address-mapping scheme is that as the source address
increments across an SDRAM page boundary, the memory controller proceeds to the next page in the
same bank. This movement along the same bank continues until all the pages have been accessed in the
same bank. The memory controller then proceeds to the next bank in the device. This sequence is shown
in Figure 12-13 and Figure 12-14.
Since, in this address mapping scheme, the memory controller can keep only one bank open, this scheme
is lower in performance than the case when IBANKPOS is cleared to 0. Therefore, this case is only
recommended to be used with Partial Array Self-refresh for mDDR SDRAM where performance may be
traded-off for power savings.
Table 12-6. Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1)
31
Source Address
Bank Address
Row Address
Number of bank bits is defined by
IBANK nbb = 1, 2, or 3
Number of row bits is defined by
ROWSIZE: nrb = 9, 10, 11, 12, 13, or 14
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Column Address
Number of column bits is defined by
PAGESIZE: ncb = 8, 9, 10, or 11
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Figure 12-13. Address Mapping Diagram (IBANKPOS = 1)
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 1, bank 0
Row 2, bank 0
Row 3, bank 0
Row N, bank 0
Row 1, bank 1
Row 2, bank 1
Row 3, bank 1
Row N, bank 1
Row 1, bank P
Row 2, bank P
Row 3, bank P
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
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Figure 12-14. SDRAM Column, Row, Bank Access (IBANKPOS = 1)
Bank 0
C C C
o o o
l l l
0 1 2 3
Row 0
Row 1
Row 2
C
o
l
M
Bank 1
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Row 1
Row 2
Bank 2
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Bank P
Row 0
Row 1
Row N
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 2
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
12.2.6 DDR2/mDDR Memory Controller Interface
To move data efficiently from on-chip resources to external DDR2/mDDR SDRAM memory, the
DDR2/mDDR memory controller makes use of a command FIFO, a write FIFO, a read FIFO, and
command and data schedulers. Table 12-7 describes the purpose of each FIFO.
Figure 12-15 shows the block diagram of the DDR2/mDDR memory controller FIFOs. Commands, write
data, and read data arrive at the DDR2/mDDR memory controller parallel to each other. The same
peripheral bus is used to write and read data from external memory as well as internal memory-mapped
registers.
Table 12-7. DDR2/mDDR Memory Controller FIFO Description
FIFO
Description
Depth (64-bit doublewords)
Command
Stores all commands coming from on-chip requestors
7
Write
Stores write data coming from on-chip requestors to memory
11
Read
Stores read data coming from memory to on-chip requestors
17
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Figure 12-15. DDR2/mDDR Memory Controller FIFO Block Diagram
Command FIFO
Command/Data
Scheduler
Command
to Memory
Write FIFO
Write Data
to Memory
Read FIFO
Read Data
from
Memory
Registers
Command
Data
12.2.6.1 Command Ordering and Scheduling, Advanced Concept
The DDR2/mDDR memory controller performs command re-ordering and scheduling in an attempt to
achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data,
address, and command buses while hiding the overhead of opening and closing DDR2/mDDR SDRAM
rows. Command re-ordering takes place within the command FIFO.
Typically, a given master issues commands on a single priority. EDMA transfer controller read and write
ports are different masters. The DDR2/mDDR memory controller first reorders commands from each
master based on the following rules:
• Selects the oldest command (first command in the queue)
• Selects a read before a write if:
– The read is to a different block address (2048 bytes) than the write
– The read has greater or equal priority
The second bullet above may be viewed as an exception to the first bullet. This means that for an
individual master, all of its commands will complete from oldest to newest, with the exception that a read
may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master
may have one command ready for execution.
Next, the DDR2/mDDR memory controller examines each of the commands selected by the individual
masters and performs the following reordering:
• Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes
to rows already open.
• Selects the highest priority command from pending reads and writes to open rows. If multiple
commands have the highest priority, then the DDR2/mDDR memory controller selects the oldest
command.
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The DDR2/mDDR memory controller may now have a final read and write command. If the Read FIFO is
not full, then the read command will be performed before the write command, otherwise the write
command will be performed first.
Besides commands received from on-chip resources, the DDR2/mDDR memory controller also issues
refresh commands. The DDR2/mDDR memory controller attempts to delay refresh commands as long as
possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2/mDDR
memory controller issues read, write, and refresh commands to DDR2/mDDR SDRAM memory, it adheres
to the following rules:
1. Refresh request resulting from the Refresh Must level of urgency being reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency being reached
6. Request to enter self-refresh mode
The following results from the above scheduling algorithm:
• All writes from a single master will complete in order
• All reads from a single master will complete in order
• From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
12.2.6.2 Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2/mDDR memory controller. Command
starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2/mDDR SDRAM commands to a row in an open bank can block
commands to the closed row in the same bank.
To avoid these conditions, the DDR2/mDDR memory controller can momentarily raises the priority of the
oldest command in the command FIFO after a set number of transfers have been made. The
PR_OLD_COUNT bit in the peripheral bus burst priority register (PBBPR) sets the number of the transfers
that must be made before the DDR2/mDDR memory controller will raise the priority of the oldest
command.
12.2.6.3 Possible Race Condition
A race condition may exist when certain masters write data to the DDR2/mDDR memory controller. For
example, if master A passes a software message via a buffer in DDR2/mDDR memory and does not wait
for indication that the write completes, when master B attempts to read the software message it may read
stale data and therefore receive an incorrect message. In order to confirm that a write from master A has
landed before a read from master B is performed, master A must wait for the write completion status from
the DDR2/mDDR memory controller before indicating to master B that the data is ready to be read. If
master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2/mDDR memory controller SDRAM status register.
3. Perform a dummy read to the DDR2/mDDR memory controller SDRAM status register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The EDMA peripheral does not need to implement the above workaround. The above workaround is
required for all other peripherals. See your device-specific data manual for more information.
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12.2.7 Refresh Scheduling
The DDR2/mDDR memory controller issues autorefresh (REFR) commands to DDR2/mDDR SDRAM
devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR).
A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until
it reaches zero. Once the interval counter reaches zero, it reloads with the value of the RR bit. Each time
the interval counter expires, a refresh backlog counter increments by 1. Conversely, each time the
DDR2/mDDR memory controller performs a REFR command, the backlog counter decrements by 1. This
means the refresh backlog counter records the number of REFR commands the DDR2/mDDR memory
controller currently has outstanding.
The DDR2/mDDR memory controller issues REFR commands based on the level of urgency. The level of
urgency is defined in Table 12-8. Whenever the refresh must level of urgency is reached, the
DDR2/mDDR memory controller issues a REFR command before servicing any new memory access
requests. Following a REFR command, the DDR2/mDDR memory controller waits T_RFC cycles, defined
in the SDRAM timing register 1 (SDTIMR1), before rechecking the refresh urgency level.
In addition to the refresh counter previously mentioned, a separate backlog counter ensures the interval
between two REFR commands does not exceed 8× the refresh rate. This backlog counter increments by 1
each time the interval counter expires and resets to zero when the DDR2/mDDR memory controller issues
a REFR command. When this backlog counter is greater than 7, the DDR2/mDDR memory controller
issues four REFR commands before servicing any new memory requests.
The refresh counters do not operate when the DDR2/mDDR memory is in self-refresh mode.
Table 12-8. Refresh Urgency Levels
Urgency Level
Description
Refresh May
Backlog count is greater than 0. Indicates there is a backlog of REFR commands, when the DDR2/mDDR
memory controller is not busy it will issue the REFR command.
Refresh Release
Backlog count is greater than 3. Indicates the level at which enough REFR commands have been performed
and the DDR2/mDDR memory controller may service new memory access requests.
Refresh Need
Backlog count is greater than 7. Indicates the DDR2/mDDR memory controller should raise the priority level
of a REFR command above servicing a new memory access.
Refresh Must
Backlog count is greater than 11. Indicates the level at which the DDR2/mDDR memory controller should
perform a REFR command before servicing new memory access requests.
12.2.8 Self-Refresh Mode
Clearing the self refresh/low power (SR_PD) bit to 0 and then setting the low power mode enable
(LPMODEN) bit to 1 in the SDRAM refresh control register (SDRCR) , forces the DDR2/mDDR memory
controller to place the external DDR2/mDDR SDRAM in a low-power mode (self refresh), in which the
DDR2/mDDR SDRAM maintains valid data while consuming a minimal amount of power. When the
LPMODEN bit is set to 1, the DDR2/mDDR memory controller continues normal operation until all
outstanding memory access requests have been serviced and the refresh backlog has been cleared. At
this point, all open pages of DDR2/mDDR SDRAM are closed and a self-refresh (SLFRFR) command (an
autorefresh command with self refresh/low power) is issued.
The memory controller exits the self-refresh state when a memory access is received, when the
LPMODEN bit in SDRCR is cleared to 0, or when the SR_PD bit in SDRCR changed to 1. While in the
self-refresh state, if a request for a memory access is received, the DDR2/mDDR memory controller
services the memory access request, returning to the self-refresh state upon completion. The
DDR2/mDDR memory controller will not wake up from the self-refresh state (whether from a memory
access request, from clearing the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles
have expired since the self-refresh command was issued. The value of T_CKE is defined in the SDRAM
timing register 2 (SDTIMR2).
In the case of DDR2, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR + 1 clock cycles before issuing non-read/write
commands and T_SXRD + 1 clock cycles before issuing read or write commands. The SDRAM timing
register 2 (SDTIMR2) programs the values of T_SXNR and T_SXRD.
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In the case of mDDR, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR+1 clock cycles and then execute auto-refresh
command before issuing any other commands. The SDRAM timing register 2 (SDTIMR2) programs the
value of T_SXNR.
Once in self-refresh mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK) may be
gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See
Section 12.2.16 for more information describing the proper procedure to follow when shutting down
DDR2/mDDR memory controller input clocks.
See Section 12.2.16.1 for a description of the self-refresh programming sequence.
12.2.9 Partial Array Self Refresh for Mobile DDR
For additional power savings during self-refresh, the partial array self-refresh (PASR) feature of the mDDR
allows you to select the amount of memory that will be refreshed during self-refresh. Use the partial array
self-refresh (PASR) bit field in the SDRAM configuration register 2 (SDCR2) to select the amount of
memory to refresh during self-refresh. As shown in Table 12-9 you may select either 4, 2, 1, 1/2, or 1/4
bank(s). The PASR bits are loaded into the extended mode register of the mDDR device, during
autoinitialization (see Section 12.2.13).
The mDDR performs bank interleaving when the internal bank position (IBANKPOS) bit in SDRAM
configuration register (SDCR) is cleared to 0. Since the SDRAM banks are only partially refreshed during
partial array self-refresh, it is recommended that you set IBANKPOS to 1 to avoid bank interleaving. When
IBANKPOS is cleared to 0, it is the responsibility of software to move critical data into the banks that are
to be refreshed during partial array self-refresh. Refer to Section 12.2.5.2 for more information on
IBANKPOS and addressing mapping in general.
Table 12-9. Configuration Bit Field for Partial Array Self-refresh
Bit Field
Bit Value
PASR
Bit Description
Partial array self refresh.
0
Refresh banks 0, 1, 2, and 3
1h
Refresh banks 0 and 1
2h
Refresh bank 0
5h
Refresh 1/2 of bank 0
6h
Refresh 1/4 of bank 0
12.2.10 Power-Down Mode
Setting the self-refresh/low power (SR_PD) bit and the low-power mode enable (LPMODEN) bit in the
SDRAM refresh control register (SDRCR) to 1, forces the DDR2/mDDR memory controller to place the
external DDR2 SDRAM in the power-down mode. When the LPMODEN bit is asserted, the DDR2/mDDR
memory controller continues normal operation until all outstanding memory access requests have been
serviced and the refresh backlog has been cleared. At this point, all open pages of DDR2 SDRAM are
closed and a Power Down command (same as NOP command but driving DDR_CKE low on the same
cycle) is issued.
The DDR2/mDDR memory controller exits the power-down state when a memory access is received,
when a Refresh Must level is reached, when the LPMODEN bit in SDRCR is cleared to 0, or when the
SR_PD bit in SDRCR changed to 0. While in the power-down state, if a request for a memory access is
received, the DDR2/mDDR memory controller services the memory access request, returning to the
power-down state upon completion. The DDR2/mDDR memory controller will not wake-up from the powerdown state (whether from a memory access request, from reaching a Refresh Must level, from clearing
the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the powerdown command was issued. The value of T_CKE is defined in the SDRAM timing register 2 (SDTIMR2).
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After exiting from the power-down state, the DDR2/mDDR memory controller will drive DDR_CKE high
and then not immediately start executing commands. Instead, it will wait T_XP + 1 clock cycles before
issuing commands. The SDRAM timing register 2 (SDTIMR2) programs the values of T_XP.
See Section 12.2.16.1 for a description of the power-down mode programming sequence.
NOTE: Power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
12.2.11 Reset Considerations
The DDR2/mDDR memory controller has two reset signals, chip_rst_n and mod_g_rst_n. The chip_rst_n
is a module-level reset that resets both the state machine as well as the DDR2/mDDR memory controller
memory-mapped registers. The mod_g_rst_n resets the state machine only; it does not reset the
controller's registers, which allows soft reset (from PSC or WDT) to reset the module without resetting the
configuration registers and reduces the programming overhead for setting up access to the DDR2/mDDR
device. If the DDR2/mDDR memory controller is reset independently of other peripherals, the user's
software should not perform memory, as well as register accesses, while chip_rst_n or mod_g_rst_n are
asserted. If memory or register accesses are performed while the DDR2/mDDR memory controller is in
the reset state, other masters may hang. Following the rising edge of chip_rst_n or mod_g_rst_n, the
DDR2/mDDR memory controller immediately begins its initialization sequence. Command and data stored
in the DDR2/mDDR memory controller FIFOs are lost. Table 12-10 describes the different methods for
asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master controller for power
management for all of the peripherals on the device. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. Figure 12-16 shows the
DDR2/mDDR memory controller reset diagram.
Table 12-10. Reset Sources
Reset Signal
Reset Source
chip_rst_n
Hardware/device reset
mod_g_rst_n
Power and sleep controller
Figure 12-16. DDR2/mDDR Memory Controller Reset Block Diagram
Hard
Reset from
PLLC0
DDR
PSC
262
DDR2/mDDR Memory Controller
chip_rst_n
mod_g_rst_n
DDR2/mDDR
memory
controller
registers
State
machine
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12.2.12 VTP IO Buffer Calibration
The DDR2/mDDR memory controller is able to control the impedance of the output IO. This feature allows
the DDR2/mDDR memory controller to tune the output impedance of the IO to match that of the PCB
board. Control of the output impedance of the IO is an important feature because impedance matching
reduces reflections, creating a cleaner board design. Calibrating the output impedance of the IO will also
reduce the power consumption of the DDR2/mDDR memory controller. The calibration is performed with
respect to voltage, temperature, and process (VTP). The VTP information obtained from the calibration is
used to control the output impedance of the IO.
The impedance of the output IO is selected by the value of a reference resistor connected to pin DDR_ZP.
The DDR2/mDDR reference design requires the reference resistor to be a 50 ohm, 5.0% tolerance, 1/16th
watt resistor (49.9 ohm, 0.5% tolerance is acceptable).
The VTP IO control register (VTPIO_CTL) is written to begin the calibration process. The VTP calibration
process is described in the DDR2/mDDR initialization sequence in Section 12.2.13.1.
NOTE: VTP IO calibration must be performed following device power up and device reset. If the
DDR2/mDDR memory controller is reset via the Power and Sleep Controller (PSC) and the
VTP input clock is disabled, accesses to the DDR2/mDDR memory controller will not
complete. To re-enable accesses to the DDR2/mDDR memory controller, enable the VTP
input clock and then perform the VTP calibration sequence again.
12.2.13 Auto-Initialization Sequence
The DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on the DDR2/mDDR device), single-ended strobe, differential strobe, etc. The DDR2/mDDR memory
controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS
and EMRS commands during the initialization sequence. The SDRAMEN, MSDRAMEN, DDREN, and
DDR2EN bits in the SDRAM configuration register (SDCR) determine if the DDR2/mDDR memory
controller will perform a DDR2 or mobile DDR initialization sequence. Set these bits as follows for DDR2:
SDRAMEN = 1, MSDRAMEN = 0, DDREN = 1, DDR2EN = 1. Set these bits as follow for mDDR:
SDRAMEN = 1, MSDRAMEN = 1, DDREN = 1, DDR2EN = 0. The DDR2 initialization sequence
performed by the DDR2/mDDR memory controller is compliant with the JESD79D-2 specification and the
mDDR initialization sequence is compliant with the JESD209 specification. The DDR2/mDDR memory
controller performs an initialization sequence under the following conditions:
• Following reset (rising edge of chip_rst_n or mod_g_rst_n)
• Following a write to the DDRDRIVE, CL, IBANK, or PAGESIZE bit fields in the SDRAM configuration
register (SDCR)
During the initialization sequence, the memory controller issues MRS and EMRS commands that
configure the DDR2/mobile DDR SDRAM mode register and extended mode register 1. The register
values for DDR2 are described in Table 12-11 and Table 12-12, and the register values for mDDR are
described in Table 12-13 and Table 12-14. The extended mode registers 2 and 3 are configured with a
value of 0h. At the end of the initialization sequence, the memory controller performs an autorefresh cycle,
leaving the memory controller in an idle state with all banks deactivated.
When a reset occurs, the DDR2/mDDR memory controller immediately begins the initialization sequence.
Under this condition, commands and data stored in the DDR2/mDDR memory controller FIFOs will be lost.
However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDCR,
data and commands stored in the DDR2/mDDR memory controller FIFOs will not be lost and the
DDR2/mDDR memory controller will ensure read and write commands are completed before starting the
initialization sequence.
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Table 12-11. DDR2 SDRAM Configuration by MRS Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Power Down Exit
Fast exit
DDR_A[11:9]
t_WR
11:9
Write Recovery
Write recovery from autoprecharge. Value of 2,
3, 4, 5, or 6 is programmed based on value of
the T_WR bit in the SDRAM timing register 1
(SDTIMR1 ).
DDR_A[8]
0
8
DLL Reset
Out of reset
DDR_A[7]
0
7
Mode: Test or Normal
Normal mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2, 3, 4, or 5 is programmed based on
value of the CL bit in the SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
Table 12-12. DDR2 SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Output Buffer Enable
Output buffer enable
DDR_A[11]
0
11
RDQS Enable
RDQS disable
DDR_A[10]
1
10
DQS enable
Disables differential DQS signaling.
DDR_A[9:7]
0
9:7
OCD Calibration Program
Exit OCD calibration
DDR_A[6]
0
6
ODT Value (Rtt)
Cleared to 0 to select 75 ohms. This feature
is not supported because the DDR_ODT
signal is not pinned out.
DDR_A[5:3]
0
5:3
Additive Latency
0 cycles of additive latency
DDR_A[2]
1
2
ODT Value (Rtt)
Set to 1 to select 75 ohms. This feature is not
supported because the DDR_ODT signal is
not pinned out.
DDR_A[1]
DDRDRIVE[0]
1
Output Driver Impedance
Value of 0 or 1 is programmed based on
value of DDRDRIVE0 bit in SDRAM
configuration register (SDCR).
DDR_A[0]
0
0
DLL enable
DLL enable
Table 12-13. Mobile DDR SDRAM Configuration by MRS Command
264
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating mode
Normal operating mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2 or 3 is programmed based on
value of CL bit in SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
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Table 12-14. Mobile DDR SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating Mode
Normal operating mode
DDR_A[6:5]
DDRDRIVE[1:0]
6:5
Output Driver Impedance
Value of 0, 1, 2, or 3 is programmed based
on value of DDRDRIVE[1:0] bits in SDRAM
configuration register (SDCR).
DDR_A[4:3]
0
4:3
Temperature Compensated
Self Refresh
Value of 0
DDR_A[2:0]
PASR bits
2:0
Partial Array Self Refresh
Value of 0, 1, 2, 5, or 6 is programmed based
on value of PASR bits in SDRAM
configuration register 2 (SDCR2).
12.2.13.1 Initializing Following Device Power Up or Reset
Following device power up or reset, the DDR2/mDDR memory controller is held in reset with the internal
clocks to the module gated off. Before releasing the DDR2/mDDR memory controller from reset, the
clocks to the module must be turned on. Perform the following steps when turning the clocks on and
initializing the module:
1. Program PLLC1 registers to start the PLL1_SYSCLK1 (that drives 2X_CLK). For information on
programming PLLC1, see the Phase-Locked Loop Controller (PLLC) chapter.
2. Program Power and Sleep Controller (PSC) to enable the DDR2/mDDR memory controller clock.
3. Perform VTP IO calibration:
(a) Clear POWERDN bit in the VTP IO control register (VTPIO_CTL).
(b) Clear LOCK bit in VTPIO_CTL.
(c) Pulse CLKRZ bit in VTPIO_CTL:
(i) Set CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(ii) Clear CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(iii) Set CLKRZ bit.
(d) Poll READY bit in VTPIO_CTL until it changes to 1.
(e) Set LOCK bit in VTPIO_CTL. VTP is locked and dynamic calibration is disabled.
(f) Set POWERDN bit in VTPIO_CTL to save power.
4. Set IOPWRDN bit in VTPIO_CTL to allow the input receivers to save power when the PWRDNEN bit in
the DDR PHY control register 1 (DRPYC1R) is set.
5. Configure DRPYC1R. All of the following steps may be done with a single register write to DRPYC1R:
(a) Set EXT_STRBEN bit to select external DQS strobe gating.
(b) Set PWRDNEN bit to allow the input receivers to power down when they are idle.
(c) Program RL bit value to meet the memory data sheet specification.
6. Configure the DDR slew register (DDR_SLEW):
(a) For DDR2, clear DDR_PDENA and CMOSEN bits.
(b) For mDDR, set the DDR_PDENA and CMOSEN bits.
7. Set the BOOTUNLOCK bit (unlocked) in the SDRAM configuration register (SDCR).
8. Program SDCR to the desired value with BOOTUNLOCK bit cleared to 0 and TIMUNLOCK bit set to 1
(unlocked).
9. For mDDR only, program the SDRAM configuration register 2 (SDCR2) to the desired value.
10. Program the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) to the
desired values to meet the memory data sheet specification.
11. Clear TIMUNLOCK bit (locked) in SDCR.
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12. Program the SDRAM refresh control register (SDRCR). All of the following steps may be done with a
single register write to SDRCR:
(a) Set LPMODEN bit to enable self-refresh. This is necessary for the next two steps.
(b) Set MCLKSTOPEN bit to enable MCLK stopping. This is necessary for the next two steps.
(c) Clear SR_PD bit to select self-refresh. This is necessary for the next two steps.
(d) Program RR refresh rate value to meet the memory data sheet specification.
13. Program the Power and Sleep Controller (PSC) to reset (SyncReset) the DDR2/mDDR memory
controller.
14. Program the Power and Sleep Controller (PSC) to re-enable the DDR2/mDDR memory controller.
15. Clear LPMODEN and MCLKSTOPEN bits in SDRCR to disable self-refresh.
16. Configure the peripheral bus burst priority register (PBBPR) to a value lower than the default value of
FFh. A lower value reduces the likelihood of prolonged command starvation for accesses made from
different master/peripherals to mDDR/DDR2 memory. The optimal value should be determined based
on system considerations; however, a value of 20h or 30h is sufficient for typical applications.
NOTE: Some memory data sheet timing values such as those programmed into the SDRAM timing
register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) may need to be relaxed in
order to compensate for signal delays introduced by board layout.
12.2.14 Interrupt Support
The DDR2/mDDR memory controller supports two addressing modes, linear incrementing and cache line
wrap. Upon receipt of an access request for an unsupported addressing mode, the DDR2/mDDR memory
controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). The DDR2/mDDR
memory controller will then treat the request as a linear incrementing request.
This interrupt is called the line trap interrupt and is the only interrupt the DDR2/mDDR memory controller
supports. It is an active-high interrupt and is enabled by the LTMSET bit in the interrupt mask set register
(IMSR). This interrupt is mapped to the CPU and is multiplexed with RTCINT.
12.2.15 DMA Event Support
The DDR2/mDDR memory controller is a DMA slave peripheral and therefore does not generate DMA
events. Data read and write requests may be made directly by masters and by the DMA.
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12.2.16 Power Management
Power dissipation from the DDR2/mDDR memory controller may be managed by the following methods:
• Self-refresh mode (see Section 12.2.8)
• Power-down mode (see Section 12.2.10)
• Disabling the DDR PHY to reduce power
The DDR2/mDDR memory controller supports low-power modes where the DLL internal to the PHY
and the receivers at the I/O pins can be disabled. These functions are controlled through the
DDR2/mDDR memory controller. Even if the PHY is active, the receivers can be configured to disable
whenever writes are in progress and the receivers are not needed.
• Gating input clocks to the module off
Gating input clocks off to the DDR2/mDDR memory controller achieves higher power savings when
compared to the power savings of self-refresh mode and power-down mode. The input clocks are
turned off outside of the DDR2/mDDR memory controller through the use of the Power and Sleep
Controller (PSC) and the PLL controller 1 (PLLC1). Figure 12-17 shows the connections between the
DDR2/mDDR memory controller, PSC, and PLLC1. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter.
Before gating clocks off, the DDR2/mDDR memory controller must place the DDR2/mDDR SDRAM
memory in self-refresh mode. If the external memory requires a continuous clock, the DDR2/mDDR
memory controller clock provided by PLLC1 must not be turned off because this may result in data
corruption. See the following subsections for the proper procedures to follow when stopping the
DDR2/mDDR memory controller clocks. Once the clocks are stopped, to re-enable the clocks follow
the clock stop procedure in each respective subsection in reverse order.
Figure 12-17. DDR2/mDDR Memory Controller Power Sleep Controller Diagram
PLL0_SYSCLK2/2
CLKSTOP_REQ
VCLKSTOP_REQ
CLKSTOP_ACK
VCLKSTOP_ACK
DDR
PST
MODCLK
MODRST
LRST
DDR2/mDDR
memory
VCLK
controller
chip_rst_n
mod_g_rst_n
2X_CLK
PLLC1
/1
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12.2.16.1 DDR2/mDDR Memory Controller Clock Stop Procedure
NOTE: If a data access occurs to the DDR2/mDDR memory after completing steps 1-4, the DLL will
wake up and lock, then the MCLK will turn on and the access will be performed. Following
steps 5 and 6, in which the clocks are disabled , all DDR2/mDDR memory accesses are not
possible until the clocks are reenabled.
In power-down mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK)
may not be gated off. This is a limitation of the DDR2/mDDR controller. For this reason,
power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
To achieve maximum power savings VCLK, MCLK, 2X_CLK, DDR_CLK, and DDR_CLK should be gated
off. The procedure for clock gating is described in the following steps.
1. Allow software to complete the desired DDR transfers.
2. Change the SR_PD bit to 0 and set the LPMODEN bit to 1 in the DDR2 SDRAM refresh control
register (SDRCR) to enable self-refresh mode. The DDR2/mDDR memory controller will complete any
outstanding accesses and backlogged refresh cycles and then place the external DDR2/mDDR
memory in self-refresh mode.
3. Set the MCLKSTOPEN bit in SDRCR to 1. This enables the DDR2/mDDR memory controller to shut
off the MCLK.
4. Wait 150 CPU clock cycles to allow the MCLK to stop.
5. Program the PSC to disable the DDR2/mDDR memory controller VCLK. You must not disable VCLK in
power-down mode; use only for self-refresh mode (see notes in this section).
6. For maximum power savings, the PLL/PLLC1 should be placed in bypass and powered-down mode to
disable 2X_CLK. You must not disable 2X_CLK in power-down mode; use only for self-refresh mode
(see notes in this section). For information on programming PLLC1, see the Phase-Locked Loop
Controller (PLLC) chapter.
To
1.
2.
3.
turn clocks back on:
Place the PLL/PLLC1 in PLL mode to start 2X_CLK to the DDR2/mDDR memory controller.
Once 2X_CLK is stable, program the PSC to enable VCLK.
Set the RESET_PHY bit in the DDR PHY reset control register (DRPYRCR) to 1. This resets the
DDR2/mDDR memory controller PHY. This bit will self-clear to 0 when reset is complete.
4. Clear the MCLKSTOPEN bit in SDRCR to 0.
5. Clear the LPMODEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.
12.2.17 Emulation Considerations
The DDR2/mDDR memory controller will remain fully functional during emulation halts to allow emulation
access to external memory.
NOTE: VTP IO calibration must be performed before emulation tools attempt to access the register
or data space of the DDR2/mDDR memory controller. A bus lock-up condition will occur if the
emulation tool attempts to access the register or data space of the DDR2/mDDR memory
controller before completing VTP IO calibration. See Section 12.2.12 for information on VTP
IO calibration.
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12.3 Supported Use Cases
The DDR2/mDDR memory controller allows a high degree of programmability for shaping DDR2/mDDR
accesses. The programmability inherent to the DDR2/mDDR memory controller provides the DDR2/mDDR
memory controller with the flexibility to interface with a variety of DDR2/mDDR devices. By programming
the SDRAM configuration register (SDCR), SDRAM refresh control register (SDRCR), SDRAM timing
register 1 (SDTIMR1), and SDRAM timing register 2 (SDTIMR2), the DDR2/mDDR memory controller can
be configured to meet the data sheet specification for DDR2 SDRAM as well as mDDR memory devices.
This section presents an example describing how to interface the DDR2 memory controller to a
DDR2/mDDR-400 device. The DDR2/mDDR memory controller is assumed to be operating at 150 MHz. A
similar procedure can be followed when interfacing to a mDDR memory device.
Connecting the DDR2/mDDR Memory Controller to DDR2/mDDR Memory
Figure 12-18 shows how to connect the DDR2/mDDR memory controller to a DDR2 device. Figure 12-18
displays a 16-bit interface; you can see that all signals are point-to-point connection.
Figure 12-18. Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR2/mDDR
DDR_WE
memory
DDR_RAS
controller
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[15:0]
CK
CK
CKE
DDR2
CS
memory
WE
x16−bit
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR_ZP
50 Ω
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Configuring Memory-Mapped Registers to Meet DDR2 Specification
As previously stated, four memory-mapped registers must be programmed to configure the DDR2/mDDR
memory controller to meet the data sheet specification of the attached DDR2/mDDR device. The registers
are:
• SDRAM configuration register (SDCR)
• SDRAM refresh control register (SDRCR)
• SDRAM timing register 1 (SDTIMR1)
• SDRAM timing register 2 (SDTIMR2)
In addition to these registers, the DDR PHY control register (DRPYC1R) must also be programmed. The
configuration of DRPYC1R is not dependent on the DDR2 device specification but rather on the board
layout.
The following sections describe how to configure each of these registers. See Section 12.4 for more
information on the DDR2/mDDR memory controller registers.
NOTE: When interfacing the DDR2/mDDR memory controller to a mDDR device, the SDRAM
configuration register 2 (SDCR2) must be programmed in addition to the registers mentioned
above.
Configuring SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains register fields that configure the DDR2/mDDR
memory controller to match the data bus width, CAS latency, number of banks, and page size of the
attached memory. In this example, we assume the following DDR2 configuration:
• Data bus width = 16 bits
• CAS latency = 3
• Number of banks = 8
• Page size = 1024 words
Table 12-15 shows the resulting SDCR configuration. Note that the value of the TIMING_UNLOCK field is
dependent on whether or not it is desirable to unlock SDTIMR1 and SDTIMR2. The TIMING_UNLOCK bit
should only be set to 1 when the SDTIMR1 and SDTIMR2 needs to be updated.
Table 12-15. SDCR Configuration
270
Field
Value
Function Selection
TIMING_UNLOCK
x
Set to 1 to unlock the SDRAM timing register 1 and SDRAM timing register 2.
Cleared to 0 to lock the SDRAM timing register 1 and SDRAM timing register 2.
NM
1h
To configure the DDR2/mDDR memory controller for a 16-bit data bus width.
CL
3h
To select a CAS latency of 3.
IBANK
3h
To select 8 internal DDR2 banks.
PAGESIZE
2h
To select 1024-word page size.
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Configuring SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) configures the DDR2/mDDR memory controller to meet the
refresh requirements of the attached memory device. SDRCR also allows the DDR2/mDDR memory
controller to enter and exit self refresh and enable and disable the MCLK stopping. In this example, we
assume that the DDR2/mDDR memory controller is not is in self-refresh mode or power-down mode and
that MCLK stopping is disabled.
The RR field in SDRCR is defined as the rate at which the attached memory device is refreshed in
DDR2/mDDR cycles. The value of this field may be calculated using the following equation:
RR = DDR2/mDDR clock frequency × DDR2/mDDR memory refresh period
Table 12-16 displays the DDR2-400 refresh rate specification.
Table 12-16. DDR2 Memory Refresh Specification
Symbol
Description
Value
tREF
Average Periodic Refresh Interval
7.8 μs
Therefore, the following results assuming 150 MHz DDR2/mDDR clock frequency.
RR = 150 MHz × 7.8 μs = 1170
Therefore, RR = 1170 = 492h.
Table 12-17 shows the resulting SDRCR configuration.
Table 12-17. SDRCR Configuration
Field
Value
Function Selection
LPMODEN
0
DDR2/mDDR memory controller is not in power-down mode.
MCLKSTOP_EN
0
MCLK stopping is disabled.
SR_PD
0
Leave a default value.
RR
492h
Set to 492h DDR2 clock cycles to meet the DDR2/mDDR memory refresh rate requirement.
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Configuring SDRAM Timing Registers (SDTIMR1 and SDTIMR2)
The SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) configure the
DDR2/mDDR memory controller to meet the data sheet timing parameters of the attached memory device.
Each field in SDTIMR1 and SDTIMR2 corresponds to a timing parameter in the DDR2/mDDR data sheet
specification. Table 12-18 and Table 12-19 display the register field name and corresponding DDR2 data
sheet parameter name along with the data sheet value. These tables also provide a formula to calculate
the register field value and displays the resulting calculation. Each of the equations include a minus 1
because the register fields are defined in terms of DDR2/mDDR clock cycles minus 1. See Section 12.4.4
and Section 12.4.5 for more information.
Table 12-18. SDTIMR1 Configuration
Register
Field Name
DDR2 Data
Manual
Parameter
Name
Description
Data Manual
Value (nS)
Formula
(Register field must be ≥)
Register
Value
T_RFC
tRFC
Refresh cycle time
127.5
(tRFC × fDDR2/mDDR_CLK) - 1
19
T_RP
tRP
Precharge command to
refresh or activate
command
15
(tRP × fDDR2/mDDR_CLK) - 1
2
T_RCD
tRCD
Activate command to
read/write command
15
(tRCD × fDDR2/mDDR_CLK) - 1
2
T_WR
tWR
Write recovery time
15
(tWR × fDDR2/mDDR_CLK) - 1
2
T_RAS
tRAS
Active to precharge
command
40
(tRAC × fDDR2/mDDR_CLK) - 1
5
T_RC
tRC
Activate to Activate
command in the same
bank
55
(tRC × fDDR2/mDDR_CLK) - 1
8
T_RRD (1)
tRRD
Activate to Activate
command in a different
bank
10
((4 × tRRD) + (2 × tCK))/(4 × tCK) - 1
1
T_WTR
tWTR
Write to read command
delay
10
(tWTR × fDDR2/mDDR_CLK) - 1
1
(1)
The formula for the T_RRD field applies only for 8 bank DDR2/mDDR memories; when interfacing to DDR2/mDDR memories
with less than 8 banks, the T_RRD field should be calculated using the following formula: (tRRD × fDDR2/mDDR_CLK) - 1.
Table 12-19. SDTIMR2 Configuration
272
Register
Field Name
DDR2 Data
Manual
Parameter
Name
T_RASMAX
tRAS(MAX)
T_XP
Data Manual
Value
Formula
(Register field must be ≥)
Register
Value
Active to precharge
command
70 μs
tRAS(MAX)/DDR refresh rate- 1
8
tXP
Exit power down to a nonread command
2(tCK cycles)
If tXP > tCKE,
then T_XP = tXP- 1,
else T_XP = tCKE- 1
2
T_XSNR
tXSNR
Exit self refresh to a nonread command
137.5 nS
(tXSNR × fDDR2/mDDR_CLK) - 1
18
T_XSRD
tXSRD
Exit self refresh to a read
command
200 (tCK cycles)
tXSRD - 1
199
T_RTP
tRTP
Read to precharge
command delay
15 nS
(tRTP × fDDR2/mDDR_CLK) - 1
1
T_CKE
tCKE
CKE minimum pulse width
3 (tCK cycles)
tCKE - 1
2
Description
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Configuring DDR PHY Control Register (DRPYC1R)
The DDR PHY control register (DRPYC1R) contains a read latency (RL) field that helps the DDR2/mDDR
memory controller determine when to sample read data. The RL field should be programmed to a value
equal to the CAS latency plus the round trip board delay minus 1. The minimum RL value is CAS latency
plus 1 and the maximum RL value is CAS latency plus 2 (again, the RL field would be programmed to
these values minus 1). Table 12-20 shows the resulting DRPYC1R configuration.
When calculating round trip board delay the signals of primary concern are the differential clock signals
(DDR_CLK and DDR_CLK) and data strobe signals (DDR_DQS). For these signals, calculate the round
trip board delay from the DDR memory controller to the memory and then choose the maximum delay to
determine the RL value. In this example, we will assume the round trip board delay is one DDR_CLK
cycle; therefore, RL can be calculated as:
RL = CAS latency + round trip board delay – 1 = 4 + 1 – 1 = 4
Table 12-20. DRPYC1R Configuration
Field
Value
Function Selection
EXT_STRBEN
1h
Programs to select external strobe gating
RL
4h
Read latency is equal to CAS latency plus round trip board delay for data minus 1
PWRDNEN
0
Programmed to power up the DDR2/mDDR memory controller receivers
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12.4 Registers
Table 12-21 lists the memory-mapped registers for the DDR2/mDDR memory controller. Note that the
VTP IO control register (VTPIO_CTL) resides in the System Configuration Module.
Table 12-21. DDR2/mDDR Memory Controller Registers
Address Offset
(1)
Acronym
Register Description
Section
0h
REVID
Revision ID Register
4h
SDRSTAT
SDRAM Status Register
Section 12.4.1
8h
SDCR
SDRAM Configuration Register
Section 12.4.2
Revision ID Register
(REVID)
Ch
SDRCR
SDRAM Refresh Control Register
Section 12.4.3
10h
SDTIMR1
SDRAM Timing Register 1
Section 12.4.4
14h
SDTIMR2
SDRAM Timing Register 2
Section 12.4.5
1Ch
SDCR2
SDRAM Configuration Register 2
Section 12.4.6
20h
PBBPR
Peripheral Bus Burst Priority Register
Section 12.4.7
40h
PC1
Performance Counter 1 Register
Section 12.4.8
44h
PC2
Performance Counter 2 Register
Section 12.4.9
48h
PCC
Performance Counter Configuration Register
Section 12.4.10
4Ch
PCMRS
Performance Counter Master Region Select Register
Section 12.4.11
50h
PCT
Performance Counter Time Register
Performance
Counter Time
Register (PCT)
60h
DRPYRCR
DDR PHY Reset Control Register
Section 12.4.12
C0h
IRR
Interrupt Raw Register
Section 12.4.13
C4h
IMR
Interrupt Masked Register
Section 12.4.14
C8h
IMSR
Interrupt Mask Set Register
Section 12.4.15
CCh
IMCR
Interrupt Mask Clear Register
Section 12.4.16
E4h
DRPYC1R
DDR PHY Control Register 1
Section 12.4.17
01E2 C000h (1)
VTPIO_CTL
VTP IO Control Register
Section 10.5.18
01E2 C004h (1)
DDR_SLEW
DDR Slew Register
Section 10.5.19
This register resides in the register space of the System Configuration (SYSCFG) Module. It is listed in the register space of the
DDR2/mDDR controller because it is applicable to the DDR2/mDDR controller.
Revision ID Register (REVID)
The revision ID register (REVID) contains the current revision ID for the DDR2/mDDR memory controller.
The REVID is shown in Figure 12-19 and described in Table 12-22.
Figure 12-19. Revision ID Register (REVID)
31
0
REV
R-4031 1B1Fh
LEGEND: R = Read only; -n = value after reset
Table 12-22. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4031 1B1Fh
274
Description
Revision ID value of the DDR2/mDDR memory controller.
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12.4.1 SDRAM Status Register (SDRSTAT)
The SDRAM status register (SDRSTAT) is shown in Figure 12-20 and described in Table 12-23.
Figure 12-20. SDRAM Status Register (SDRSTAT)
31
30
29
Rsvd
DUALCLK
Reserved
16
R-0
R-1
R-0
15
3
2
1
0
Reserved
PHYRDY
Reserved
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-23. SDRAM Status Register (SDRSTAT) Field Descriptions
Bit
Field
31
Reserved
30
DUALCLK
29-3
Reserved
2
PHYRDY
1-0
Reserved
Value
0
Description
Reserved
Dual clock. Specifies whether the VCLK and MCLK inputs are asynchronous. This bit should always be
read as 1.
0
VCLK and MCLK are not asynchronous.
1
VCLK and MCLK are asynchronous.
0
Reserved
DDR2/mDDR memory controller DLL ready. Specifies whether the DDR2/mDDR memory controller DLL
is powered up and locked.
0
DLL is not ready, either powered down, in reset, or not locked.
1
DLL is powered up, locked, and ready for operation.
0
Reserved
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12.4.2 SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains fields that program the DDR2/mDDR memory
controller to meet the specification of the attached DDR2/mDDR memory. These fields configure the
DDR2/mDDR memory controller to match the data bus width, CAS latency, number of internal banks, and
page size of the attached DDR2/mDDR memory. Writing to the DDRDRIVE[1:0], CL, IBANK, and
PAGESIZE bit fields causes the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM
initialization sequence. The SDCR is shown in Figure 12-21 and described in Table 12-24.
Figure 12-21. SDRAM Configuration Register (SDCR)
31
27
26
25
24
Reserved
28
DDR2TERM1
IBANK_POS
MSDRAMEN
DDRDRIVE1
R-0
R/W-1
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
BOOTUNLOCK
DDR2DDQS
DDR2TERM0
DDR2EN
DDRDLL_DIS
DDRDRIVE0
DDREN
SDRAMEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
13
12
11
15
14
TIMUNLOCK
NM
Reserved
CL
Reserved
R/W-0
R/W-1
R-0
R/W-5h
R-0
7
6
4
9
3
2
8
0
Reserved
IBANK
Reserved
PAGESIZE
R-0
R/W-2h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-24. SDRAM Configuration Register (SDCR) Field Descriptions
Bit
31-28
Field
Reserved
27
DDR2TERM1
26
IBANK_POS
25
Value
0
0-3h
Description
Reserved
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM0 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDR2TERM0
bit. Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00
to disable the termination because the ODT feature is not supported.
Internal Bank position.
0
Normal addressing
1
Special addressing. Typically used with mobile DDR partial array self-refresh.
MSDRAMEN
Mobile SDRAM enable. Use this bit in conjunction with DDR2EN, DDREN, and SDRAMEN to
enable/disable mobile SDRAM. To change this bit value, use the following sequence:
1.
2.
24
DDRDRIVE1
23
BOOTUNLOCK
0
Disable mobile SDRAM
1
Enable mobile SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE0 bit to make a 2-bit field.
This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDRDRIVE0 bit.
Boot Unlock. Controls the write permission settings for the DDR2TERM[1:0], MSDRAMEN,
DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and SDRAMEN bit fields. To
change these bits, use the following sequence:
1.
2.
276
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the MSDRAMEN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0],
MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and
SDRAMEN bits.
0
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may not be changed.
1
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may be changed.
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Table 12-24. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
22
DDR2DDQS
Value
Description
DDR2 SDRAM differential DQS enable. This bit is writeable only when the BOOTUNLOCK bit is
unlocked. To change this bit value, use the following sequence:
1.
2.
21
DDR2TERM0
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2DDQS bit.
0
Single-ended DQS
1
Reserved
0-3h
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM1 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0] bits.
Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00 to
disable the termination because the ODT feature is not supported.
0
1h-3h
20
DDR2EN
Disable termination
Reserved
DDR2 enable. This bit is used in conjunction with the DDREN and SDRAMEN bits to enable/disable
DDR2. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
1.
2.
19
0
Disable DDR2
1
Enable DDR2
DDRDLL_DIS
DLL disable for DDR SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked.
To change this bit value, use the following sequence:
1.
2.
18
DDRDRIVE0
Enable DLL
1
Disable DLL inside DDR SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE1 bit to make a 2-bit field.
The DDRDRIVE[1:0] bits configure the output driver impedance control value of the SDRAM
memory. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDRIVE[1:0] bits.
0
For DDR2, normal drive strength. For mobile DDR, full drive strength.
1h
For DDR2, weak drive strength. For mobile DDR, 1/2 drive strength.
2h
For DDR2, reserved. For mobile DDR, 1/4 drive strength.
3h
For DDR2, reserved. For mobile DDR, 1/8 drive strength.
DDREN
DDR enable. This bit is used in conjunction with the DDR2EN and SDRAMEN bits to enable/disable
DDR. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
1.
2.
16
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDLL_DIS bit.
0
1.
2.
17
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2EN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDREN bit.
0
Disable DDR
1
Enable DDR
SDRAMEN
SDRAM enable. This bit is used in conjunction with the DDR2EN and DDREN bits to enable/disable
SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the SDRAMEN bit.
0
Disable SDRAM
1
Enable SDRAM
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Table 12-24. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
15
TIMUNLOCK
Value
Description
Timing unlock. Controls the write permission settings for the CL bit field, and the SDRAM timing
register 1 (SDTIMR1) and the SDRAM timing register 2 (SDTIMR2) bit fields. To change these bits,
use the following sequence:
1.
2.
14
0
CL bit, and SDTIMR1 and SDTIMR2 bit fields may not be changed.
1
CL bit, and SDTIMR1 and SDTIMR2 bit fields may be changed.
NM
13-12
Reserved
11-9
CL
SDRAM data bus width.
0
Reserved
1
16-bit bus width.
0
Reserved
0-7h
SDRAM CAS latency. This bit is writeable only when the TIMUNLOCK bit is unlocked. To change
this bit value, use the following sequence:
1.
2.
0-1h
8-7
Reserved
6-4
IBANK
3
2-0
Reserved
PAGESIZE
Write a 1 to the TIMUNLOCK bit.
Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit.
Reserved
2h
CAS Latency = 2
3h
CAS Latency = 3
4h
CAS Latency = 4
5h
CAS Latency = 5
6h-7h
Reserved
0
Reserved
0-7h
Internal SDRAM bank setup. Defines the number of internal banks on the external SDRAM device.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
4h-7h
Reserved
0
Reserved
0-7h
Page Size. Defines the page size of the SDRAM device.
0
256-word page requiring 8 column address bits.
1h
512-word page requiring 9 column address bits.
2h
1024-word page requiring 10 column address bits.
3h
2048-word page requiring 11 column address bits.
4h-7h
278
Write a 1 to the TIMUNLOCK bit.
Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit and SDTIMR1 and
SDTIMR2 bit fields.
Reserved
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12.4.3 SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) is used to configure the DDR2/mDDR memory controller to:
• Enter and Exit the self-refresh and power-down states.
• Enable and disable MCLK, stopping when in the self-refresh state.
• Meet the refresh requirement of the attached DDR2/mDDR device by programming the rate at which
the DDR2/mDDR memory controller issues autorefresh commands.
The SDRCR is shown in Table 12-25 and described in Figure 12-22.
Figure 12-22. SDRAM Refresh Control Register (SDRCR)
31
30
LPMODEN
MCLKSTOPEN
29
Reserved
24
SR_PD
23
22
Reserved
16
R/W-0
R/W-0
R-0
R/W-0
R-0
15
0
RR
R/W-884h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-25. SDRAM Refresh Control Register (SDRCR) Field Descriptions
Bit
Field
31
LPMODEN
30
29-24
23
Value
Low-power mode enable.
0
Disable low-power mode.
1
Enable low-power mode. The state of bit SR_PD selects either self-refresh or power-down
mode.
MCLKSTOPEN
Reserved
MCLK stop enable.
0
Disables MCLK stopping, MCLK may not be stopped.
1
Enables MCLK stopping, MCLK may be stopped. The LPMODEN bit must be set to 1 before
setting the MCLKSTOPEN bit to 1.
0
Reserved
SR_PD
22-16
Reserved
15-0
RR
Description
Self-refresh or Power-down select. This bit is only in effect when the LPMODEN bit is set to 1;
this bit is ignored when the LPMODEN bit is cleared to 0.
0
Self-refresh mode.
1
Power-down mode.
0
Reserved
0-FFFFh
Refresh rate. Defines the rate at which the attached SDRAM devices will be refreshed. The
value of this field may be calculated with the following equation:
RR = SDRAM frequency/SDRAM refresh rate
where SDRAM refresh rate is derived from the SDRAM data sheet.
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12.4.4 SDRAM Timing Register 1 (SDTIMR1)
The SDRAM timing register 1 (SDTIMR1) configures the DDR2/mDDR memory controller to meet many of
the AC timing specification of the DDR2/mDDR memory. The SDTIMR1 is programmable only when the
TIMUNLOCK bit is set to 1 in the SDRAM configuration register (SDCR). Note that DDR_CLK is equal to
the period of the DDR_CLK signal. See the DDR2/mDDR memory data sheet for information on the
appropriate values to program each field. The SDTIMR1 is shown in Figure 12-23 and described in
Table 12-26.
Figure 12-23. SDRAM Timing Register 1 (SDTIMR1)
31
25
24
22
21
19
18
16
T_RFC
T_RP
T_RCD
T_WR
R/W-Fh
R/W-2h
R/W-2h
R/W-2h
15
11
10
6
5
3
2
1
0
T_RAS
T_RC
T_RRD
Rsvd
T_WTR
R/W-6h
R/W-9h
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-26. SDRAM Timing Register 1 (SDTIMR1) Field Descriptions
Bit
31-25
Field
Value
Description
T_RFC
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh
or activate command, minus 1. Corresponds to the trfc AC timing parameter in the DDR2/mDDR data
sheet. Calculate by:
T_RFC = (trfc/DDR_CLK) - 1
24-22
T_RP
0-7h
21-19
T_RCD
0-7h
18-16
T_WR
0-7h
Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate
command, minus 1. Corresponds to the trp AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RP = (trp/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write
command, minus 1. Corresponds to the trcd AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RCD = (trcd/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge
command, minus 1. Corresponds to the twr AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_WR = (twr/DDR_CLK) - 1
When the value of this field is changed from its previous value, the initialization sequence will begin.
15-11
T_RAS
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge
command, minus 1. Corresponds to the tras AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RAS = (tras/DDR_CLK) - 1
T_RAS must be greater than or equal to T_RCD.
10-6
T_RC
5-3
T_RRD
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate
command, minus 1. Corresponds to the trc AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RC = (trc/DDR_CLK) - 1
0-7h
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command
in a different bank, minus 1. Corresponds to the trrd AC timing parameter in the DDR2/mDDR data
sheet. Calculate by:
T_RRD = (trrd/DDR_CLK) - 1
For an 8 bank DDR2/mDDR device, this field must be equal to ((4 × tRRD) + (2 × tCK)) / (4 × tCK) - 1.
2
1-0
Reserved
T_WTR
0
0-3h
Reserved
Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.
Corresponds to the twtr AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_WTR = (twtr/DDR_CLK) - 1
280
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12.4.5 SDRAM Timing Register 2 (SDTIMR2)
Like the SDRAM timing register 1 (SDTIMR1), the SDRAM timing register 2 (SDTIMR2) also configures
the DDR2/mDDR memory controller to meet the AC timing specification of the DDR2/mDDR memory. The
SDTIMR2 is programmable only when the TIMUNLOCK bit is set to 1 in the SDRAM configuration register
(SDCR). Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2/mDDR data
sheet for information on the appropriate values to program each field. SDTIMR2 is shown in Figure 12-24
and described in Table 12-27.
Figure 12-24. SDRAM Timing Register 2 (SDTIMR2)
31
30
27
26
25
24
23
22
16
Rsvd
T_RASMAX
T_XP
T_ODT
T_XSNR
R-0
R/W-8h
R/W-2h
R/W-2h
R/W-32h
15
8
7
5
4
0
T_XSRD
T_RTP
T_CKE
R/W-A7h
R/W-1
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-27. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
Bit
Field
31
Reserved
30-27
T_RASMAX
Value
0
0-Fh
Description
Any writes to these bit(s) must always have a value of 0.
Specifies the maximum number of refresh rate intervals from Activate to Precharge command.
Corresponds to the tras AC timing parameter and the refresh rate in the DDR2/mDDR data sheet.
Calculate by:
T_RASMAX = (trasmax/refresh_rate) - 1
Round down to the nearest cycle.
26-25
T_XP
0-3h
Specifies the minimum number of DDR_CLK cycles from Power Down exit to any other command
except a read command, minus 1. Corresponds to the txp or tcke AC timing parameter in the
DDR2/mDDR data sheet. This field must satisfy the greater of tXP or tCKE.
If txp > tcke, then calculate by T_XP = txp - 1
If txp < tcke, then calculate by T_XP = tcke - 1
24-23
T_ODT
0-3h
Specifies the minimum number of DDR_CLK cycles from ODT enable to write data driven for DDR2
SDRAM. T_ODT must be equal to (CAS latency - tAOND -1). T_ODT must be less than CAS latency
minus 1. This feature is not supported because the DDR_ODT signal is not pinned out.
22-16
T_XSNR
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a self_refresh exit to any other command
except a read command, minus 1. Corresponds to the txsnr AC timing parameter in the DDR2/mDDR
data sheet. Calculate by:
15-8
T_XSRD
0-FFh
7-5
T_RTP
0-7h
4-0
T_CKE
0-1Fh
T_XSNR = (txsnr/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from a self_refresh exit to a read command, minus
1. Corresponds to the txsrd AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_XSRD = txsrd - 1
Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
command, minus 1. Corresponds to the trtp AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RTP = (trtp/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
Corresponds to the tcke AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_CKE = tcke - 1
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12.4.6 SDRAM Configuration Register 2 (SDCR2)
The SDRAM configuration register 2 (SDCR2) contains fields to configure partial array self-refresh and
rowsize of the mDDR. This register is applicable only when the IBANK_POS bit in the SDRAM
configuration register (SDCR) is set to 1 for special addressing. Writing to the PASR and ROWSIZE bit
fields will cause the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM initialization
sequence. SDCR2 is shown in Figure 12-25 and described in Table 12-28.
Figure 12-25. SDRAM Configuration Register 2 (SDCR2)
31
19
18
16
Reserved
PASR
R-0
R/W-0
15
3
2
0
Reserved
ROWSIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-28. SDRAM Configuration Register 2 (SDCR2) Field Descriptions
Bit
Field
31-19
Reserved
18-16
PASR
Value
0
Reserved
0-7h
Partial array self-refresh.
0
4 banks will be refreshed.
1h
2 banks will be refreshed.
2h
1 bank will be refreshed.
3h-4h
Reserved
5h
1/2 bank will be refreshed.
6h
1/4 bank will be refreshed.
7h
Reserved
Reserved
15-3
Reserved
0
2-0
ROWSIZE
0-7h
282
Description
Row size. Defines the number of row address bit for DDR device.
0
9 row address bits
1h
10 row address bits
2h
11 row address bits
3h
12 row address bits
4h
13 row address bits
5h
14 row address bits
6h
15 row address bits
7h
16 row address bits
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12.4.7 Peripheral Bus Burst Priority Register (PBBPR)
The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the
DDR2/mDDR memory controller. To avoid command starvation, the DDR2/mDDR memory controller
momentarily raises the priority of the oldest command in the command FIFO after a set number of
transfers have been made. The PR_OLD_COUNT bit sets the number of transfers that must be made
before the DDR2/mDDR memory controller raises the priority of the oldest command. See
Section 12.2.6.2 for more details on command starvation.
Proper configuration of the PBBPR is critical to correct system operation. The DDR2/mDDR memory
controller always prioritizes accesses to open rows as highest, if there is any bank conflict regardless of
master priority. This is done to allow most efficient utilization of the DDR2/mDDR. However, it could lead
to excessive blocking of high priority masters. If the PR_OLD_COUNT bits are cleared to 00h, then the
DDR2/mDDR memory controller always honors the master priority, regardless of open row/bank status.
For most systems, the PBBPR should be set to a moderately low value to provide an acceptable balance
of DDR2/mDDR efficiency and latency for high priority masters (for example, 10h or 20h).
The PBBPR is shown in Figure 12-26 and described in Table 12-29.
Figure 12-26. Peripheral Bus Burst Priority Register (PBBPR)
31
16
Reserved
R-0
15
8
7
0
Reserved
PR_OLD_COUNT
R-0
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-29. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
PR_OLD_COUNT
Value
0
0-FFh
Description
Any writes to these bit(s) must always have a value of 0.
Priority raise old counter. Specifies the number of memory transfers after which the
DDR2/mDDR memory controller will elevate the priority of the oldest command in the command
FIFO. Clearing to 00h will ensure master priority is strictly honored (at the cost of decreased
DDR2/mDDR memory controller efficiency, as open row will always be closed immediately if
any bank conflict occurs). Recommended setting for typical system operation is between 10h
and 20h.
0
1 memory transfer
1h
2 memory transfers
2h
3 memory transfers
3h-FFh 4 to 256 memory transfers
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12.4.8 Performance Counter 1 Register (PC1)
For debug or gathering performance statistics, the PC1 and PC2 counters and associated configuration
registers are provided. These are intended for debug and analysis only. By configuring the performance
counter configuration register (PCC) to define the type of statistics to gather and configuring the
performance counter master region select register (PCMRS) to filter accesses only to specific chip select
regions, performing system applications and then reading these counters, different statistics can be
gathered. To reset the counters, you must reset (mod_g_rst_n) the DDR2/mDDR memory controller
through the PSC. For details on the PSC, see the Power and Sleep Controller (PSC) chapter.
The performance counter 1 register (PC1) is shown in Figure 12-27 and described in Table 12-30.
Figure 12-27. Performance Counter 1 Register (PC1)
31
0
Counter1
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-30. Performance Counter 1 Register (PC1) Field Descriptions
Bit
31-0
Field
Counter1
Value
Description
0-FFFF FFFFh
32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register (PCMRS).
12.4.9 Performance Counter 2 Register (PC2)
The performance counter 2 register (PC2) is shown in Figure 12-28 and described in Table 12-31.
Figure 12-28. Performance Counter 2 Register (PC2)
31
0
Counter2
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-31. Performance Counter 2 Register (PC2) Field Descriptions
Bit
31-0
284
Field
Counter2
Value
0-FFFF FFFFh
DDR2/mDDR Memory Controller
Description
32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register (PCMRS).
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12.4.10 Performance Counter Configuration Register (PCC)
The performance counter configuration register (PCC) is shown in Figure 12-29 and described in
Table 12-32.
Table 12-33 shows the possible filter configurations for the two performance counters. These filter
configurations can be used in conjunction with a Master ID and/or an external chip select to obtain
performance statistics for a particular master and/or an external chip select.
Figure 12-29. Performance Counter Configuration Register (PCC)
31
30
CNTR2_MSTID_EN
CNTR2_REGION_EN
29
Reserved
20
CNTR2_CFG
R/W-0
R/W-0
R-0
R/W-1
13
4
19
16
15
14
CNTR1_MSTID_EN
CNTR1_REGION_EN
Reserved
3
CNTR1_CFG
0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-32. Performance Counter Configuration Register (PCC) Field Descriptions
Bit
Field
31
CNTR2_MSTID_EN
30
Value
Description
Master ID filter enable for performance counter 2 register (PC2). Refer to Table 12-33 for
details.
0
Master ID filter is disabled. PC2 counts accesses from all masters to DDR2/mDDR SDRAM.
1
Master ID filter is enabled. PC2 counts accesses from the master, corresponding to the
Master ID value in the MST_ID2 bit field of the performance counter master region select
register (PCMRS).
CNTR2_REGION_EN
Chip select filter enable for performance counter 2 register (PC2). Refer to Table 12-33 for
details.
0
Chip select filter is disabled. PC2 counts total number of accesses (DDR2/mDDR SDRAM +
DDR2/mDDR memory controller memory-mapped register accesses). The REGION_SEL2
bit field value in the performance counter master region select register (PCMRS) is a don’t
care.
1
Chip select filter is enabled. If the REGION_SEL2 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL2 = 0: PC2 counts accesses to DDR2/mDDR SDRAM memory.
REGION_SEL2 = 7h: PC2 counts accesses to DDR2/mDDR memory controller memorymapped registers.
29-20
Reserved
19-16
CNTR2_CFG
15
14
0
0-Fh
CNTR1_MSTID_EN
Any writes to these bit(s) must always have a value of 0.
Filter configuration for performance counter 2 register (PC2). Refer to Table 12-33 for
details.
Master ID filter enable for performance counter 1 register (PC1). Refer to Table 12-33 for
details.
0
Master ID filter is disabled. PC1 counts accesses from all masters to DDR2/mDDR SDRAM.
1
Master ID filter is enabled. PC1 counts accesses from the master, corresponding to the
Master ID value in the MST_ID1 bit field of the performance counter master region select
register (PCMRS).
CNTR1_REGION_EN
Chip select filter enable for performance counter 1 register (PC1). Refer to Table 12-33 for
details.
0
Chip select filter is disabled. PC1 counts total number of accesses (DDR2/mDDR SDRAM +
DDR2/mDDR memory controller memory-mapped register accesses). The REGION_SEL1
bit field value in the performance counter master region select register (PCMRS) is a don’t
care.
1
Chip select filter is enabled. If the REGION_SEL1 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL1 = 0: PC1 counts accesses to DDR2/mDDR SDRAM memory.
REGION_SEL1 = 7h: PC1 counts accesses to DDR2/mDDR memory controller memorymapped registers.
13-4
Reserved
0
Any writes to these bit(s) must always have a value of 0.
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Table 12-32. Performance Counter Configuration Register (PCC) Field Descriptions (continued)
Bit
Field
3-0
CNTR1_CFG
Value
0-Fh
Description
Filter configuration for performance counter 1 register (PC1). Refer to Table 12-33 for
details.
Table 12-33. Performance Counter Filter Configuration
Performance Counter Configuration Register (PCC) Bit
CNTRn_CFG
CNTRn_REGION_EN
0
0
CNTRn_MSTID_EN Description
0 or 1
Counts the total number of READ/WRITE commands the
external memory controller receives.
The size of counter increments are determines by the size of the
transfer and the default burst size (DBS). The counter breaks up
transfers into sizes according to DBS. Therefore, counter
increments for transfers aligned to DBS are equal to the transfer
size divided by the DBS.
1h
0
0
Counts the total number of ACTIVATE commands the
external memory controller issues to DDR2/mDDR memory.
The counter increments by a value of 1 for every request to
read/write data to a closed bank in DDR2/mDDR memory by the
external memory controller.
2h
0 or 1
0 or 1
Counts the total number of READ commands (read accesses)
the DDR2/mDDR memory controller receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size divided by the DBS.
3h
0 or 1
0 or 1
Counts the total number of WRITE commands the
DDR2/mDDR memory controller receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size of data written to the
DDR2/mDDR memory controller divided by the DBS.
4h
0
0
Counts the number of external memory controller cycles
(DDR_CLK cycles) that the command FIFO is full.
Use the following to calculate the counter value as a percentage:
% = counter value / total DDR_CLK cycles in a sample period
As the value of this counter approaches 100%, the DDR2/mDDR
memory controller is approaching a congestion point where the
command FIFO is full 100% of the time and a command will have
to wait at the SCR to be accepted in the command FIFO.
5h-7h
0
0
8h
0 or 1
0 or 1
Reserved
Counts the number of commands (requests) in the command
FIFO that require a priority elevation.
To avoid command starvation, the DDR2/mDDR memory
controller can momentarily raise the priority of the oldest
command in the command FIFO after a set number of transfers
have been made. The PR_OLD_COUNT bit field in the peripheral
bus burst priority register (PBBPR) sets the number of the
transfers that must be made before the DDR2/mDDR memory
controller will raise the priority of the oldest command.
9h
0
0
Counts the number of DDR2/mDDR memory controller cycles
(DDR_CLK cycles) that a command is pending in the
command FIFO. This counter increments every cycle the
command FIFO is not empty.
Use the following to calculate the counter value as a percentage:
% = counter value / total DDR_CLK cycles in sample period
As the value of this counter approaches 100%, the number of
cycles the DDR2/mDDR memory controller has a command in the
command FIFO to service approaches 100%.
Ah-Fh
286
0
DDR2/mDDR Memory Controller
0
Reserved
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12.4.11 Performance Counter Master Region Select Register (PCMRS)
The performance counter master region select register (PCMRS) is shown in Figure 12-30 and described
in Table 12-34.
Figure 12-30. Performance Counter Master Region Select Register (PCMRS)
31
24
23
20
19
16
MST_ID2
Reserved
REGION_SEL2
R/W-0
R-0
R/W-0
15
8
7
4
3
0
MST_ID1
Reserved
REGION_SEL1
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-34. Performance Counter Master Region Select Register (PCMRS) Field Descriptions
Bit
Field
Value
Description
31-24
MST_ID2
0-FFh
Master ID for performance counter 2 register (PC2). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
23-20
Reserved
0
Any writes to these bit(s) must always have a value of 0.
19-16
REGION_SEL2
0-Fh
Region select for performance counter 2 register (PC2).
0
1h-6h
7h
15-8
MST_ID1
7-4
Reserved
3-0
REGION_SEL1
PC2 counts total DDR2/mDDR accesses.
Reserved
PC2 counts total DDR2/mDDR memory controller memory-mapped register accesses.
8h-Fh
Reserved
0-FFh
Master ID for performance counter 1 register (PC1). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
0
Any writes to these bit(s) must always have a value of 0.
0-Fh
Region select for performance counter 1 register (PC1).
0
1h-6h
7h
8h-Fh
PC1 counts total DDR2/mDDR accesses.
Reserved
PC1 counts total DDR2/mDDR memory controller memory-mapped register accesses.
Reserved
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Performance Counter Time Register (PCT)
The performance counter time register (PCT) is shown in Figure 12-31 and described in Table 12-35.
Figure 12-31. Performance Counter Time Register (PCT)
31
0
TOTAL_TIME
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-35. Performance Counter Time Register (PCT) Field Description
Bit
31-0
Field
Value
TOTAL_TIME
Description
0-FFFF FFFFh
32-bit counter that continuously counts number for DDR_CLK cycles elapsed after the
DDR2/mDDR memory controller is brought out of reset.
12.4.12 DDR PHY Reset Control Register (DRPYRCR)
The DDR PHY reset control register (DRPYRCR) is used to reset the DDR PHY. The DRPYRCR is shown
in Figure 12-32 and described in Table 12-36.
Figure 12-32. DDR PHY Reset Control Register (DRPYRCR)
31
16
Reserved
R-0
15
11
10
9
0
Reserved
RESET_PHY
Reserved
R-04h
R/W-0
R-091h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-36. DDR PHY Reset Control Register (DRPYRCR)
Bit
31-11
10
9-0
288
Field
Reserved
Value
0000 04h
RESET_PHY
Reserved
Description
Always write the default value to these bits.
Reset DDR PHY.
0
No effect.
1
Resets DDR PHY.
091h
DDR2/mDDR Memory Controller
Always write the default value to these bits.
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12.4.13 Interrupt Raw Register (IRR)
The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs,
the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is
shown in Figure 12-33 and described in Table 12-37.
Figure 12-33. Interrupt Raw Register (IRR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LT
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 12-37. Interrupt Raw Register (IRR) Field Descriptions
Bit
31-3
2
1-0
Field
Reserved
Value
0
Reserved
LT
Reserved
Description
Line trap. Write a 1 to clear LT and the LTM bit in the interrupt masked register (IMR); a write of 0 has
no effect.
0
A line trap condition has not occurred.
1
Illegal memory access type. See Section 12.2.14 for more details.
0
Reserved
12.4.14 Interrupt Masked Register (IMR)
The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt
condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR
bit is set. The IMR bit is not set if the interrupt is not enabled in IMSR. The IMR is shown in Figure 12-34
and described in Table 12-38.
Figure 12-34. Interrupt Masked Register (IMR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTM
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 12-38. Interrupt Masked Register (IMR) Field Descriptions
Bit
31-3
2
1-0
Field
Reserved
Value
0
LTM
Reserved
Description
Reserved
Line trap masked. Write a 1 to clear LTM and the LT bit in the interrupt raw register (IRR); a write of 0
has no effect.
0
A line trap condition has not occurred.
1
Illegal memory access type (only set if the LTMSET bit in IMSR is set). See Section 12.2.14 for more
details.
0
Reserved
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12.4.15 Interrupt Mask Set Register (IMSR)
The interrupt mask set register (IMSR) enables the DDR2/mDDR memory controller interrupt. The IMSR is
shown in Figure 12-35 and described in Table 12-39.
NOTE: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask
clear register (IMCR), the interrupt is not enabled and neither bit is set to 1.
Figure 12-35. Interrupt Mask Set Register (IMSR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMSET
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-39. Interrupt Mask Set Register (IMSR) Field Descriptions
Bit
Field
31-3
Reserved
2
LTMSET
1-0
290
Reserved
Value
0
Description
Reserved
Line trap interrupt set. Write a 1 to set LTMSET and the LTMCLR bit in the interrupt mask clear register
(IMCR); a write of 0 has no effect.
0
Line trap interrupt is not enabled; a write of 1 to the LTMCLR bit in IMCR occurred.
1
Line trap interrupt is enabled.
0
Reserved
DDR2/mDDR Memory Controller
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12.4.16 Interrupt Mask Clear Register (IMCR)
The interrupt mask clear register (IMCR) disables the DDR2/mDDR memory controller interrupt. Once an
interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 12-36
and described in Table 12-40.
NOTE: If the LTMCLR bit in IMCR is set concurrently with the LTMSET bit in the interrupt mask set
register (IMSR), the interrupt is not enabled and neither bit is set to 1.
Figure 12-36. Interrupt Mask Clear Register (IMCR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMCLR
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 12-40. Interrupt Mask Clear Register (IMCR) Field Descriptions
Bit
Field
31-3
Reserved
2
LTMCLR
1-0
Reserved
Value
0
Description
Reserved
Line trap interrupt clear. Write a 1 to clear LTMCLR and the LTMSET bit in the interrupt mask set
register (IMSR); a write of 0 has no effect.
0
Line trap interrupt is not enabled.
1
Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred.
0
Reserved
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12.4.17 DDR PHY Control Register (DRPYC1R)
The DDR PHY control register 1 (DRPYC1R) configures the DDR2/mDDR memory controller read latency.
The DRPYC1R is shown in Figure 12-37 and described in Table 12-41.
Figure 12-37. DDR PHY Control Register 1 (DRPYC1R)
31
16
Reserved
R-0
7
6
Rsvd
15
CONFIG_DLL_MODE
14
12
11
Reserved
8
EXT_STRBEN
PWRDNEN
5
Reserved
3
2
RL
0
R-0
R/W-0
R-0
R/W-0
R/W-1
R-0
R/W-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-41. DDR PHY Control Register 1 (DRPYC1R) Field Descriptions
Bit
Field
31-15
Reserved
14-12
CONFIG_DLL_MODE
11-8
7
6
0
DLL REFCLK is enabled.
2h
DLL REFCLK is disabled.
3h-7h
Reserved
0
Reserved
Internal/External strobe gating.
0
Internal strobe gating mode.
1
External strobe gating mode.
PWRDNEN
2-0
RL
Reserved
DLL configuration. Controls the value assigned to the config_dll_mode input.
EXT_STRBEN
Reserved
Description
0-1h
Reserved
5-3
292
Value
Power down receivers.
0
Receivers powered up when idle.
1
Receivers powered down when idle.
0
Reserved
0-7h
DDR2/mDDR Memory Controller
Read latency. Read latency is equal to CAS latency plus round trip board delay for data
minus 1. The maximum value of read latency that is supported is CAS latency plus 2. The
minimum read latency value that is supported is CAS latency plus 1. The read latency value
is defined in number of MCLK/DDR_CLK cycles.
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Chapter 13
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Enhanced Capture (eCAP) Module
The enhanced capture (eCAP) module is essential in systems where accurate timing of external events is
important. This chapter describes the eCAP module.
Topic
13.1
13.2
13.3
13.4
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Applications ....................................................................................................
Registers .........................................................................................................
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320
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13.1 Introduction
13.1.1 Purpose of the Peripheral
Uses for eCAP include:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
13.1.2 Features
The eCAP module includes the following features:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event time-stamps
• Continuous mode capture of time-stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All above resources dedicated to a single input pin
• When not used in capture mode, the ECAP module can be configured as a single channel PWM output
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13.2 Architecture
The eCAP module represents one complete capture channel that can be instantiated multiple times
depending on the target device. In the context of this guide, one eCAP channel has the following
independent key resources:
• Dedicated input capture pin
• 32-bit time base counter
• 4 × 32-bit time-stamp capture registers (CAP1-CAP4)
• 4-stage sequencer (Modulo4 counter) that is synchronized to external events, ECAP pin rising/falling
edges.
• Independent edge polarity (rising/falling edge) selection for all 4 events
• Input capture signal prescaling (from 2-62)
• One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events
• Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme
• Interrupt capabilities on any of the 4 capture events
Multiple identical eCAP modules can be contained in a system as shown in Figure 13-1. The number of
modules is device-dependent and is based on target application needs. In this chapter, the letter x within a
signal or module name is used to indicate a generic eCAP instance on a device.
Figure 13-1. Multiple eCAP Modules
VBus32
From EPWM
SyncIn
ECAP1
module
ECAP1
ECAP1INT
SyncOut
SyncIn
Interrupt
Controller
ECAP2/
APWM2
module
ECAP2
GPIO
MUX
ECAP2INT
SyncOut
SyncIn
ECAPx/
APWMx
module
ECAPx
ECAPxINT
SyncOut
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13.2.1 Capture and APWM Operating Mode
You can use the eCAP module resources to implement a single-channel PWM generator (with 32 bit
capabilities) when it is not being used for input captures. The counter operates in count-up mode,
providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The CAP1 and CAP2
registers become the active period and compare registers, respectively, while CAP3 and CAP4 registers
become the period and capture shadow registers, respectively. Figure 13-2 is a high-level view of both the
capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 13-2. Capture and APWM Modes of Operation
SyncIn
Counter (”timer”)
Capture
mode
32
Note:
Same pin
depends on
operating
mode
CAP1 reg
CAP2 reg
CAP3 reg
Sequencing
Edge detection
Edge polarity
Prescale
ECAPx
pin
CAP4 reg
ECAPxINT
Interrupt I/F
Or
SyncIn
Counter (”timer”)
APWM
mode
32
Syncout
Period reg
(active) (”CAP1”)
Compare reg
(active) (”CAP2”)
Period reg
(shadow) (”CAP3”)
PWM
Compare logic
APWMx
pin
Compare reg
(shadow) (”CAP4”)
ECAPxINT
296
Interrupt I/F
(1)
A single pin is shared between CAP and APWM functions. In capture mode, it is an input; in APWM mode, it
is an output.
(2)
In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 invokes the shadow mode.
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13.2.2 Capture Mode Description
Figure 13-3 shows the various components that implement the capture function.
Figure 13-3. Capture Function Diagram
ECCTL2[SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
SYNC
CTRPHS
(phase register-32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
TSCTR
(counter-32 bit)
SYNCOut
PRD [0-31]
Delta-mode
RST
CTR [0-31]
PWM
compare
logic
CMP [0-31]
32
CTR=PRD
CTR [0-31]
CTR=CMP
32
PRD [0-31]
ECCTL1 [ CAPLDEN, CTRRSTx]
CAP1
(APRD active)
APRD
shadow
32
32
Polarity
select
LD2
Polarity
select
32
CMP [0-31]
32
CAP2
(ACMP active)
LD
32
32
LD1
LD
MODE SELECT
ECAPx
32
Event
qualifier
ACMP
shadow
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Event
Prescale
Polarity
select
LD3
LD4
ECCTL1[EVTPS]
Polarity
select
4
Capture events
Edge Polarity Select
ECCTL1[CAPxPOL]
4
CEVT[1:4]
to Interrupt
Controller
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
ECCTL2 [ RE-ARM, CONT/ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
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13.2.2.1 Event Prescaler
An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the
prescaler. This is useful when very high frequency signals are used as inputs. Figure 13-4 shows a
functional diagram and Figure 13-5 shows the operation of the prescale function.
Figure 13-4. Event Prescale Control
Event prescaler
0
PSout
1
By−pass
ECAPx pin
(from GPIO)
/n
5
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)
(1)
When a prescale value of 1 is chosen (ECCTL1[13:9] = 0000) the input capture signal by-passes the
prescale logic completely.
Figure 13-5. Prescale Function Waveforms
ECAPx
PSout
div 2
PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10
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13.2.2.2 Edge Polarity Select and Qualifier
• Four independent edge polarity (rising edge/falling edge) selection multiplexers are used, one for each
capture event.
• Each edge (up to 4) is event qualified by the Modulo4 sequencer.
• The edge event is gated to its respective CAPn register by the Mod4 counter. The CAPn register is
loaded on the falling edge.
13.2.2.3
•
•
•
Continuous/One-Shot Control
The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.
The continuous/one-shot block (Figure 13-6) controls the start/stop and reset (zero) functions of the Mod4
counter via a mono-shot type of action that can be triggered by the stop-value comparator and re-armed
via software control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both
the Mod4 counter and contents of CAP1-4 registers (time-stamps).
Re-arming prepares the eCAP module for another capture sequence. Also re-arming clears (to zero) the
Mod4 counter and permits loading of CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored,
and capture values continue to be written to CAP1-4 in a circular buffer sequence.
Figure 13-6. Continuous/One-shot Block Diagram
0 1 2 3
2:4 MUX
2
CEVT1
CEVT2
CEVT3
CEVT4
CLK
Modulo 4
counter Stop
RST
Mod_eq
One−shot
control logic
Stop value (2b)
ECCTL2[STOP_WRAP]
ECCTL2[RE−ARM]
ECCTL2[CONT/ONESHT]
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13.2.2.4 32-Bit Counter and Phase Control
This counter (Figure 13-7) provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.
Figure 13-7. Counter and Synchronization Block Diagram
SYNC
ECCTL2[SWSYNC]
ECCTL2[SYNCOSEL]
SYNCI
CTR=PRD
Disable
Disable
ECCTL2[SYNCI_EN]
SYNCO
Sync out
select
CTRPHS
LD_CTRPHS
Delta−mode
RST
TSCTR
(counter 32b)
SYSCLK
CLK
CTR−OVF
OVF
CTR[31−0]
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13.2.2.5 CAP1-CAP4 Registers
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a timestamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this
bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.
CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and
CAP2 during APWM operation.
13.2.2.6 Interrupt Control
An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events
(CTR = PRD, CTR = CMP). See Figure 13-8.
A counter overflow event (FFFF FFFFh->0000 0000h) is also provided as an interrupt source (CTROVF).
The capture events are edge and sequencer qualified (that is, ordered in time) by the polarity select and
Mod4 gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPn module) going to the
interrupt controller.
Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR = PRD, CTR = CMP) can be
generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated to the interrupt controller only if any of the
interrupt events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must
clear the global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR) before any
other interrupt pulses are generated. You can force an interrupt event via the interrupt force register
(ECFRC). This is useful for test purposes.
13.2.2.7 Shadow Load and Lockout Control
In capture mode, this logic inhibits (locks out) any shadow loading of CAP1 or CAP2 from APRD and
ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
• Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value.
• On period equal, CTR[31:0] = PRD[31:0]
NOTE: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode
(ECCTL2[CAP/APWM == 0]). The CTR = PRD, CTR = CMP flags are only valid in APWM
mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes.
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Figure 13-8. Interrupts in eCAP Module
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT1
ECFLG
Clear
ECCLR
ECFRC
Latch
ECFLG
ECEINT
ECCLR
Set
ECFLG
Clear
Clear
Latch
ECEINT
Generate
interrupt
pulse when
input=1
ECCLR
ECFRC
Latch
Set
ECAPxINT
CEVT2
1
Set
CEVT3
ECFLG
0
Clear
0
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT4
ECFLG
Clear
ECCLR
ECFRC
Latch
CTROVF
Set
ECEINT
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
PRDEQ
Set
ECFLG
Clear
Latch
ECEINT
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Set
ECCLR
ECFRC
CMPEQ
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13.2.2.8 APWM Mode Operation
Main operating highlights of the APWM section:
• The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
• When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
• Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers either immediately upon a write, or on a CTR = PRD
trigger.
• In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
• During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates,
during run-time, you only need to use the shadow registers.
Figure 13-9. PWM Waveform Details Of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
The behavior of APWM active-high mode (APWMPOL == 0) is:
CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle (<100% duty)
CMP = PERIOD+1, output high for complete period (100% duty)
CMP > PERIOD+1, output high for complete period
The behavior of APWM active-low mode (APWMPOL == 1) is:
CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle (<100% duty)
CMP = PERIOD+1, output low for complete period (100% duty)
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CMP > PERIOD+1, output low for complete period
13.3 Applications
The following sections will provide Applications examples and code snippets to show how to configure and
operate the eCAP module. For clarity and ease of use, below are useful #defines which will help in the
understanding of the examples.
304
// ECCTL1 ( ECAP Control Reg 1)
//==========================
// CAPxPOL bits
#define
EC_RISING
#define
EC_FALLING
0x0
0x1
// CTRRSTx bits
#define
EC_ABS_MODE
#define
EC_DELTA_MODE
0x0
0x1
// PRESCALE bits
#define
EC_BYPASS
#define
EC_DIV1
#define
EC_DIV2
#define
EC_DIV4
#define
EC_DIV6
#define
EC_DIV8
#define
EC_DIV10
0x0
0x0
0x1
0x2
0x3
0x4
0x5
// ECCTL2 ( ECAP Control Reg 2)
//==========================
// CONT/ONESHOT bit
#define
EC_CONTINUOUS
#define
EC_ONESHOT
0x0
0x1
// STOPVALUE bit
#define
EC_EVENT1
#define
EC_EVENT2
#define
EC_EVENT3
#define
EC_EVENT4
0x0
0x1
0x2
0x3
// RE-ARM bit
#define
EC_ARM
0x1
// TSCTRSTOP bit
#define
EC_FREEZE
#define
EC_RUN
0x0
0x1
// SYNCO_SEL bit
#define
EC_SYNCIN
#define
EC_CTR_PRD
#define
EC_SYNCO_DIS
0x0
0x1
0x2
// CAP/APWM mode bit
#define
EC_CAP_MODE
#define
EC_APWM_MODE
0x0
0x1
// APWMPOL bit
#define
EC_ACTV_HI
#define
EC_ACTV_LO
0x0
0x1
// Generic
#define
EC_DISABLE
#define
EC_ENABLE
#define
EC_FORCE
0x0
0x1
0x1
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13.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
Figure 13-10 shows an example of continuous capture operation (Mod4 counter wraps around). In this
figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this
gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the
next state. When the TSCTR reaches FFFF FFFFh (maximum value), it wraps around to 0000 0000h (not
shown in Figure 13-10), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
time-stamps are valid at the point indicated by the diagram, after the 4th event, hence event CEVT4 can
conveniently be used to trigger an interrupt and the CPU can read data from the CAPn registers.
Figure 13-10. Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
CEVT1
CEVT2
CEVT3
CEVT4
CEVT1
CAPx pin
t5
t4
FFFFFFFF
t3
t2
t1
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
0
1
2
XX
3
0
1
t5
t1
XX
t2
XX
CAP3
t3
XX
CAP4
t4
t
Polarity selection
Capture registers [1−4]
All capture values valid
(can be read) at this time
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Table 13-1. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_RISING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_RISING
ECCTL1
CTRRST1
EC_ABS_MODE
ECCTL1
CTRRST2
EC_ABS_MODE
ECCTL1
CTRRST3
EC_ABS_MODE
ECCTL1
CTRRST4
EC_ABS_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-1. Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising edge trigger
// Run Time ( e.g. CEVT4 triggered ISR call)
//==========================================
TSt1 = ECAPxRegs.CAP1;
// Fetch Time-Stamp
TSt2 = ECAPxRegs.CAP2;
// Fetch Time-Stamp
TSt3 = ECAPxRegs.CAP3;
// Fetch Time-Stamp
TSt4 = ECAPxRegs.CAP4;
// Fetch Time-Stamp
Period1 = TSt2-TSt1;
Period2 = TSt3-TSt2;
Period3 = TSt4-TSt3;
306
Enhanced Capture (eCAP) Module
captured
captured
captured
captured
at
at
at
at
t1
t2
t3
t4
// Calculate 1st period
// Calculate 2nd period
// Calculate 3rd period
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13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
In Figure 13-11 the eCAP operating mode is almost the same as in the previous section except capture
events are qualified as either rising or falling edge, this now gives both period and duty cycle information:
Period1 = t3 – t1, Period2 = t5 – t3, …etc. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x 100%, etc. Duty
Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, etc.
Figure 13-11. Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
CEVT2
CEVT4
CEVT1
CEVT2
CEVT3
CEVT1
CEVT4
CEVT1
CEVT3
CAPx pin
FFFFFFFF
t6
t5
CTR[0−31]
t3
t9
t8
t7
t4
t2
t1
00000000
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
0
1
2
XX
3
0
1
t1
XX
0
t6
t3
XX
3
t5
t2
XX
2
t7
t4
t8
tt
Polarity selection
Capture registers [1−4]
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Table 13-2. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_FALLING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_FALLING
ECCTL1
CTRRST1
EC_ABS_MODE
ECCTL1
CTRRST2
EC_ABS_MODE
ECCTL1
CTRRST3
EC_ABS_MODE
ECCTL1
CTRRST4
EC_ABS_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-2. Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising & Falling edge triggers
// Run Time ( e.g. CEVT4 triggered ISR call)
//==========================================
TSt1 = ECAPxRegs.CAP1;
// Fetch Time-Stamp
TSt2 = ECAPxRegs.CAP2;
// Fetch Time-Stamp
TSt3 = ECAPxRegs.CAP3;
// Fetch Time-Stamp
TSt4 = ECAPxRegs.CAP4;
// Fetch Time-Stamp
Period1 = TSt3-TSt1;
DutyOnTime1 = TSt2-TSt1;
DutyOffTime1 = TSt3-TSt2;
308
Enhanced Capture (eCAP) Module
captured
captured
captured
captured
at
at
at
at
t1
t2
t3
t4
// Calculate 1st period
// Calculate On time
// Calculate Off time
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13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
Figure 13-12 shows how the eCAP module can be used to collect Delta timing data from pulse train
waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4 counter
wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event. Here
Capture events are qualified as Rising edge only. On an event, TSCTR contents (time-stamp) is captured
first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If TSCTR
reaches FFFF FFFFh (maximum value), before the next event, it wraps around to 0000 0000h and
continues, a CNTOVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage
of Delta-time Mode is that the CAPn contents directly give timing data without the need for CPU
calculations: Period1 = T1, Period2 = T2,…etc. As shown in Figure 13-12, the CEVT1 event is a good
trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Figure 13-12. Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
CEVT1
CEVT3
CEVT2
CEVT4
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T2
T4
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
0
1
2
XX
3
0
1
CTR value at CEVT1
t4
XX
t1
XX
CAP3
t2
XX
CAP4
t3
t
Polarity selection
Capture registers [1−4]
All capture values valid
(can be read) at this time
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Table 13-3. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_RISING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_RISING
ECCTL1
CTRRST1
EC_DELTA_MODE
ECCTL1
CTRRST2
EC_DELTA_MODE
ECCTL1
CTRRST3
EC_DELTA_MODE
ECCTL1
CTRRST4
EC_DELTA_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-3. Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
// Code snippet for CAP mode Delta Time, Rising edge trigger
// Run Time ( e.g. CEVT1 triggered ISR call)
//==========================================
// Note: here Time-stamp directly represents the Period value.
Period4 = ECAPxRegs.CAP1;
// Fetch Time-Stamp captured at
Period1 = ECAPxRegs.CAP2;
// Fetch Time-Stamp captured at
Period2 = ECAPxRegs.CAP3;
// Fetch Time-Stamp captured at
Period3 = ECAPxRegs.CAP4;
// Fetch Time-Stamp captured at
310
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T1
T2
T3
T4
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13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
In Figure 13-13 the eCAP operating mode is almost the same as in previous section except Capture
events are qualified as either Rising or Falling edge, this now gives both Period and Duty cycle
information: Period1 = T1 + T2, Period2 = T3 + T4, …etc Duty Cycle1 (on-time %) = T1 / Period1 × 100%,
etc Duty Cycle1 (off-time %) = T2 / Period1 × 100%, etc
During initialization, you must write to the active registers for both period and compare. This will then
automatically copy the init values into the shadow values. For subsequent compare updates, that is,
during run-time, only the shadow registers must be used.
Figure 13-13. Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
CEVT2
CEVT4
CEVT1
CEVT2
CEVT3
CEVT4
CEVT5
CEVT3
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T5
T8
T2
T6
T4
T7
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
0
1
XX
2
3
0
1
2
t5
t1
XX
t2
XX
0
t4
CTR value at CEVT1
XX
3
t6
t3
t7
t
Polarity selection
Capture registers [1−4]
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Table 13-4. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_FALLING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_FALLING
ECCTL1
CTRRST1
EC_DELTA_MODE
ECCTL1
CTRRST2
EC_DELTA_MODE
ECCTL1
CTRRST3
EC_DELTA_MODE
ECCTL1
CTRRST4
EC_DELTA_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-4. Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
// Code snippet for CAP mode Delta Time, Rising and Falling edge triggers
// Run Time ( e.g. CEVT1 triggered ISR call)
//==========================================
// Note: here Time-stamp directly represents the Duty cycle values.
DutyOnTime1 = ECAPxRegs.CAP2;
// Fetch Time-Stamp captured at
DutyOffTime1 = ECAPxRegs.CAP3;
// Fetch Time-Stamp captured at
DutyOnTime2 = ECAPxRegs.CAP4;
// Fetch Time-Stamp captured at
DutyOffTime2 = ECAPxRegs.CAP1;
// Fetch Time-Stamp captured at
T2
T3
T4
T1
Period1 = DutyOnTime1 + DutyOffTime1;
Period2 = DutyOnTime2 + DutyOffTime2;
312
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13.3.5
13.3.5.1
Application of the APWM Mode
Simple PWM Generation (Independent Channel/s) Example
In this example, the eCAP module is configured to operate as a PWM generator. Here a very simple
single channel PWM waveform is generated from output pin APWMn. The PWM polarity is active high,
which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high
level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value
represents the off-time.
Figure 13-14. PWM Waveform Details of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
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Table 13-5. ECAP Initialization for APWM Mode
Register
Bit
Value
CAP1
CAP1
0x1000
CTRPHS
CTRPHS
0x0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-5. Code Snippet for APWM Mode
// Code snippet for APWM mode Example 1
// Run Time (Instant 1, e.g. ISR call)
//======================
ECAPxRegs.CAP2 = 0x300;
// Set Duty cycle i.e. compare value
// Run Time (Instant 2, e.g. another ISR call)
//======================
ECAPxRegs.CAP2 = 0x500;
// Set Duty cycle i.e. compare value
13.3.5.2
Multichannel PWM Generation with Synchronization Example
Figure 13-15 takes advantage of the synchronization feature between eCAP modules. Here 4 independent
PWM channels are required with different frequencies, but at integer multiples of each other to avoid
"beat" frequencies. Hence one eCAP module is configured as the Master and the remaining 3 are Slaves
all receiving their synch pulse (CTR = PRD) from the master. Note the Master is chosen to have the lower
frequency (F1 = 1/20,000) requirement. Here Slave2 Freq = 2 × F1, Slave3 Freq = 4 × F1 and Slave4
Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is
shown.
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Figure 13-15. Multichannel PWM Example Using 4 eCAP Modules
DC bus
Motor
dc
brush
APWM1
Motor
dc
brush
APWM2
Motor
dc
brush
APWM3
Motor
dc
brush
APWM4
TSCTR
FFFF FFFFh
Master APWM(1) module
20,000
APRD(1)
ACMP(1)
0000 0000
7,000
APWM1
(o/p pin)
CTR=PRD
(SyncOut)
Time
Phase = 0°
Slave APWM(2−4) module/s
10,000
APRD(2)
0
5,000
APRD(3)
0
4,000
APRD(4)
Time
0
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Table 13-6. ECAP1 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
20000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_CTR_PRD
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-7. ECAP2 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
10000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-8. ECAP3 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
5000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-9. ECAP4 Initialization for Multichannel PWM Generation with Synchronization
316
Register
Bit
Value
CAP1
CAP1
4000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
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Example 13-6. Code Snippet for Multichannel PWM Generation with Synchronization
// Code snippet for APWM mode Example 2
// Run Time (Note: Example execution of one run-time instant)
//============================================================
ECAP1Regs.CAP2 = 7000;
// Set Duty cycle i.e., compare value
ECAP2Regs.CAP2 = 2000;
// Set Duty cycle i.e., compare value
ECAP3Regs.CAP2 = 550;
// Set Duty cycle i.e., compare value
ECAP4Regs.CAP2 = 6500;
// Set Duty cycle i.e., compare value
13.3.5.3
=
=
=
=
7000
2000
550
6500
Multichannel PWM Generation with Phase Control Example
In Figure 13-16, the Phase control feature of the APWM mode is used to control a 3 phase Interleaved
DC/DC converter topology. This topology requires each phase to be off-set by 120° from each other.
Hence if “Leg” 1 (controlled by APWM1) is the reference Leg (or phase), that is, 0°, then Leg 2 need 120°
off-set and Leg 3 needs 240° off-set. The waveforms in Figure 13-16 show the timing relationship between
each of the phases (Legs). Note eCAP1 module is the Master and issues a sync out pulse to the slaves
(modules 2, 3) whenever TSCTR = Period value.
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Figure 13-16. Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules
Comple−
mentary
and
deadband
logic
Comple−
mentary
and
deadband
logic
Comple−
mentary
and
deadband
logic
APWM1
APWM2
APWM3
Vout
TSCTR
APRD(1)
APRD(1)
1200
700
SYNCO pulse
(CTR=PRD)
APWM1
Φ2=120°
CTRPHS(2)=800
APWM2
Φ3=240°
CTRPHS(3)=400
APWM3
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Table 13-10. ECAP1 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_CTR_PRD
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-11. ECAP2 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
800
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 13-12. ECAP3 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
400
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
Example 13-7. Code Snippet for Multichannel PWM Generation with Phase Control
// Code snippet for APWM mode Example 3
// Run Time (Note: Example execution of one run-time instant)
//============================================================
// All phases are set to the same duty cycle
ECAP1Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
ECAP2Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
ECAP3Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
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13.4 Registers
Table 13-13 shows the eCAP module control and status register set. All 32-bit registers are aligned on
even address boundaries and are organized in little-endian mode. The 16 least-significant bits of a 32-bit
register are located on lowest address (even address).
NOTE:
In APWM mode, writing to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the
shadow registers CAP3/CAP4 invokes the shadow mode.
Table 13-13. Control and Status Register Set
Offset
Acronym
0h
TSCTR
4h
CTRPHS
Description
Size (×16)
Section
Time-Stamp Counter Register
2
Section 13.4.1
Counter Phase Offset Value Register
2
Section 13.4.2
8h
CAP1
Capture 1 Register
2
Section 13.4.3
Ch
CAP2
Capture 2 Register
2
Section 13.4.4
10h
CAP3
Capture 3 Register
2
Section 13.4.5
14h
CAP4
Capture 4 Register
2
Section 13.4.6
28h
ECCTL1
Capture Control Register 1
1
Section 13.4.7
2Ah
ECCTL2
Capture Control Register 2
1
Section 13.4.8
2Ch
ECEINT
Capture Interrupt Enable Register
1
Section 13.4.9
2Eh
ECFLG
Capture Interrupt Flag Register
1
Section 13.4.10
30h
ECCLR
Capture Interrupt Clear Register
1
Section 13.4.11
32h
ECFRC
Capture Interrupt Force Register
1
Section 13.4.12
5Ch
REVID
Revision ID Register
2
Section 13.4.13
13.4.1 Time-Stamp Counter Register (TSCTR)
The time-stamp counter register (TSCTR) is shown in Figure 13-17 and described in Table 13-14.
Figure 13-17. Time-Stamp Counter Register (TSCTR)
31
0
TSCTR
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-14. Time-Stamp Counter Register (TSCTR) Field Descriptions
Bit
31-0
320
Field
TSCTR
Value
0-FFFF FFFFh
Enhanced Capture (eCAP) Module
Description
Active 32-bit counter register that is used as the capture time-base
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13.4.2 Counter Phase Control Register (CTRPHS)
The counter phase control register (CTRPHS) is shown in Figure 13-18 and described in Table 13-15.
Figure 13-18. Counter Phase Control Register (CTRPHS)
31
0
CTRPHS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-15. Counter Phase Control Register (CTRPHS) Field Descriptions
Bit
31-0
Field
CTRPHS
Value
0-FFFF FFFFh
Description
Counter phase value register that can be programmed for phase lag/lead. This register
shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a
control bit. Used to achieve phase control synchronization with respect to other eCAP and
EPWM time-bases.
13.4.3 Capture 1 Register (CAP1)
The capture 1 register (CAP1) is shown in Figure 13-19 and described in Table 13-16.
Figure 13-19. Capture 1 Register (CAP1)
31
0
CAP1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-16. Capture 1 Register (CAP1) Field Descriptions
Bit
Field
Value
31-0
CAP1
0-FFFF FFFFh
Description
This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• APRD active register when used in APWM mode
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13.4.4 Capture 2 Register (CAP2)
The capture 2 register (CAP2) is shown in Figure 13-20 and described in Table 13-17.
Figure 13-20. Capture 2 Register (CAP2)
31
0
CAP2
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-17. Capture 2 Register (CAP2) Field Descriptions
Bit
Field
Value
31-0
CAP2
0-FFFF FFFFh
Description
This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• ACMP active register when used in APWM mode
13.4.5 Capture 3 Register (CAP3)
The capture 3 register (CAP3) is shown in Figure 13-21 and described in Table 13-18.
Figure 13-21. Capture 3 Register (CAP3)
31
0
CAP3
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-18. Capture 3 Register (CAP3) Field Descriptions
Bit
Field
Value
31-0
CAP3
0-FFFF FFFFh
322
Enhanced Capture (eCAP) Module
Description
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow
(APRD) register. You update the PWM period value through this register. In this mode, CAP3
shadows CAP1.
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13.4.6 Capture 4 Register (CAP4)
The capture 4 register (CAP4) is shown in Figure 13-22 and described in Table 13-19.
Figure 13-22. Capture 4 Register (CAP4)
31
0
CAP4
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-19. Capture 4 Register (CAP4) Field Descriptions
Bit
Field
Value
31-0
CAP4
0-FFFF FFFFh
Description
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare
shadow (ACMP) register. You update the PWM compare value through this register. In this
mode, CAP4 shadows CAP2.
13.4.7 ECAP Control Register 1 (ECCTL1)
The ECAP control register 1 (ECCTL1) is shown in Figure 13-23 and described in Table 13-20.
Figure 13-23. ECAP Control Register 1 (ECCTL1)
15
14
13
9
8
FREE/SOFT
PRESCALE
CAPLDEN
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CTRRST4
CAP4POL
CTRRST3
CAP3POL
CTRRST2
CAP2POL
CTRRST1
CAP1POL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-20. ECAP Control Register 1 (ECCTL1) Field Descriptions
Bit
15-14
13-9
Field
FREE/SOFT
PRESCALE
Value
0-3h
Description
Emulation Control
0
TSCTR counter stops immediately on emulation suspend
1h
TSCTR counter runs until = 0
2h-3h
TSCTR counter is unaffected by emulation suspend (Run Free)
0-1Fh
Event Filter prescale select
0
Divide by 1 (i.e,. no prescale, by-pass the prescaler)
1
Divide by 2
2h
Divide by 4
3h
Divide by 6
4h
Divide by 8
5h
Divide by 10
...
8
1Eh
Divide by 60
1Fh
Divide by 62
CAPLDEN
Enable Loading of CAP1-4 registers on a capture event
0
Disable CAP1-4 register loads at capture event time.
1
Enable CAP1-4 register loads at capture event time.
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Table 13-20. ECAP Control Register 1 (ECCTL1) Field Descriptions (continued)
Bit
7
6
5
4
3
2
1
0
324
Field
Value
CTRRST4
Description
Counter Reset on Capture Event 4
0
Do not reset counter on Capture Event 4 (absolute time stamp operation)
1
Reset counter after Capture Event 4 time-stamp has been captured
(used in difference mode operation)
CAP4POL
Capture Event 4 Polarity select
0
Capture Event 4 triggered on a rising edge (RE)
1
Capture Event 4 triggered on a falling edge (FE)
CTRRST3
Counter Reset on Capture Event 3
0
Do not reset counter on Capture Event 3 (absolute time stamp)
1
Reset counter after Event 3 time-stamp has been captured
(used in difference mode operation)
CAP3POL
Capture Event 3 Polarity select
0
Capture Event 3 triggered on a rising edge (RE)
1
Capture Event 3 triggered on a falling edge (FE)
CTRRST2
Counter Reset on Capture Event 2
0
Do not reset counter on Capture Event 2 (absolute time stamp)
1
Reset counter after Event 2 time-stamp has been captured
(used in difference mode operation)
CAP2POL
Capture Event 2 Polarity select
0
Capture Event 2 triggered on a rising edge (RE)
1
Capture Event 2 triggered on a falling edge (FE)
CTRRST1
Counter Reset on Capture Event 1
0
Do not reset counter on Capture Event 1 (absolute time stamp)
1
Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)
CAP1POL
Capture Event 1 Polarity select
0
Capture Event 1 triggered on a rising edge (RE)
1
Capture Event 1 triggered on a falling edge (FE)
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13.4.8 ECAP Control Register 2 (ECCTL2)
The ECAP control register 2 (ECCTL2) is shown in Figure 13-24 and described in Table 13-21.
Figure 13-24. ECAP Control Register 2 (ECCTL2)
15
11
7
10
9
8
Reserved
APWMPOL
CAP/APWM
SWSYNC
R-0
R/W-0
R/W-0
R/W-0
2
1
5
4
3
SYNCO_SEL
6
SYNCI_EN
TSCTRSTOP
RE-ARM
STOP_WRAP
CONT/ONESHT
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-21. ECAP Control Register 2 (ECCTL2) Field Descriptions
Bit
15-11
10
9
Field
Reserved
Value
0
APWMPOL
Description
Reserved
APWM output polarity select. This is applicable only in APWM operating mode
0
Output is active high (Compare value defines high time)
1
Output is active low (Compare value defines low time)
CAP/APWM
CAP/APWM operating mode select
0
ECAP module operates in capture mode. This mode forces the following configuration:
•
•
•
•
1
ECAP module operates in APWM mode. This mode forces the following configuration:
•
•
•
•
8
SWSYNC
Inhibits TSCTR resets via CTR = PRD event
Inhibits shadow loads on CAP1 and 2 registers
Permits user to enable CAP1-4 register load
ECAPn/APWMn pin operates as a capture input
Resets TSCTR on CTR = PRD event (period boundary
Permits shadow loading on CAP1 and 2 registers
Disables loading of time-stamps into CAP1-4 registers
ECAPn/APWMn pin operates as a APWM output
Software-forced Counter (TSCTR) Synchronizing. This provides a convenient software method to
synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via
the CTR = PRD event.
0
Writing a zero has no effect. Reading always returns a zero
1
Writing a one forces a TSCTR shadow load of current ECAP module and any ECAP modules
down-stream providing the SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a zero.
Note: Selection CTR = PRD is meaningful only in APWM mode; however, you can choose it in CAP
mode if you find doing so useful.
7-6
5
4
SYNCO_SEL
0-3h
Sync-Out Select
0
Select sync-in event to be the sync-out signal (pass through)
1h
Select CTR = PRD event to be the sync-out signal
2h
Disable sync out signal
3h
Disable sync out signal
SYNCI_EN
Counter (TSCTR) Sync-In select mode
0
Disable sync-in option
1
Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W
force event.
TSCTRSTOP
Time Stamp (TSCTR) Counter Stop (freeze) Control
0
TSCTR stopped
1
TSCTR free-running
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Table 13-21. ECAP Control Register 2 (ECCTL2) Field Descriptions (continued)
Bit
3
2-1
Field
Value
RE-ARM
STOP_WRAP
Description
One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one
shot or continuous mode.
0
Has no effect (reading always returns a 0)
1
Arms the one-shot sequence as follows:
1) Resets the Mod4 counter to zero
2) Unfreezes the Mod4 counter
3) Enables capture register loads
0-3h
Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur
before the CAP(1-4) registers are frozen, that is, capture sequence is stopped.
Wrap value for continuous mode. This is the number (between 1-4) of the capture register in which
the circular buffer wraps around and starts again.
0
Stop after Capture Event 1 in one-shot mode.
Wrap after Capture Event 1 in continuous mode.
1h
Stop after Capture Event 2 in one-shot mode.
Wrap after Capture Event 2 in continuous mode.
2h
Stop after Capture Event 3 in one-shot mode.
Wrap after Capture Event 3 in continuous mode.
3h
Stop after Capture Event 4 in one-shot mode.
Wrap after Capture Event 4 in continuous mode.
Notes: STOP_WRAP is compared to Mod4 counter and, when equal, 2 actions occur:
• Mod4 counter is stopped (frozen)
• Capture register loads are inhibited
In one-shot mode, further interrupt events are blocked until re-armed.
0
CONT/ONESHT
Continuous or one-shot mode control (applicable only in capture mode)
0
Operate in continuous mode
1
Operate in one-shot mode
13.4.9 ECAP Interrupt Enable Register (ECEINT)
The ECAP interrupt enable register (ECEINT) is shown in Figure 13-25 and described in Table 13-22.
The interrupt enable bits (CEVTn) block any of the selected events from generating an interrupt. Events
will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR
registers.
The proper procedure for configuring peripheral modes and interrupts is:
1. Disable global interrupts
2. Stop eCAP counter
3. Disable eCAP interrupts
4. Configure peripheral registers
5. Clear spurious eCAP interrupt flags
6. Enable eCAP interrupts
7. Start eCAP counter
8. Enable global interrupts
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Figure 13-25. ECAP Interrupt Enable Register (ECEINT)
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CEVT3
CEVT2
CETV1
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-22. ECAP Interrupt Enable Register (ECEINT) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
Value
0
Reserved
Counter Equal Compare Interrupt Enable
0
Disable Compare Equal as an Interrupt source
1
Enable Compare Equal as an Interrupt source
CTR=PRD
Counter Equal Period Interrupt Enable
0
Disable Period Equal as an Interrupt source
1
Enable Period Equal as an Interrupt source
CTROVF
Counter Overflow Interrupt Enable
0
Disable counter Overflow as an Interrupt source
1
Enable counter Overflow as an Interrupt source
CEVT4
Capture Event 4 Interrupt Enable
0
Disable Capture Event 4 as an Interrupt source
1
Enable Capture Event 4 as an Interrupt source
CEVT3
Capture Event 3 Interrupt Enable
0
Disable Capture Event 3 as an Interrupt source
1
Enable Capture Event 3 as an Interrupt source
CEVT2
Capture Event 2 Interrupt Enable
0
Disable Capture Event 2 as an Interrupt source
1
Enable Capture Event 2 as an Interrupt source
CEVT1
Reserved
Description
Capture Event 1 Interrupt Enable
0
Disable Capture Event 1 as an Interrupt source
1
Enable Capture Event 1 as an Interrupt source
0
Reserved
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13.4.10 ECAP Interrupt Flag Register (ECFLG)
The ECAP interrupt flag register (ECFLG) is shown in Figure 13-26 and described in Table 13-23.
Figure 13-26. ECAP Interrupt Flag Register (ECFLG)
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CETV3
CEVT2
CETV1
INT
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-23. ECAP Interrupt Flag Register (ECFLG) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
328
Value
0
Description
Reserved
Compare Equal Compare Status Flag. This flag is only active in APWM mode.
0
Indicates no event occurred
1
Indicates the counter (TSCTR) reached the compare register value (ACMP)
CTR=PRD
Counter Equal Period Status Flag. This flag is only active in APWM mode.
0
Indicates no event occurred
1
Indicates the counter (TSCTR) reached the period register value (APRD) and was reset.
CTROVF
Counter Overflow Status Flag. This flag is active in CAP and APWM mode.
0
Indicates no event occurred.
1
Indicates the counter (TSCTR) has made the transition from 0xFFFFFFFF to 0x00000000
CEVT4
Capture Event 4 Status Flag This flag is only active in CAP mode.
0
Indicates no event occurred
1
Indicates the fourth event occurred at ECAPn pin
CEVT3
Capture Event 3 Status Flag. This flag is active only in CAP mode.
0
Indicates no event occurred.
1
Indicates the third event occurred at ECAPn pin.
CEVT2
Capture Event 2 Status Flag. This flag is only active in CAP mode.
0
Indicates no event occurred.
1
Indicates the second event occurred at ECAPn pin.
CEVT1
Capture Event 1 Status Flag. This flag is only active in CAP mode.
0
Indicates no event occurred.
1
Indicates the first event occurred at ECAPn pin.
INT
Global Interrupt Status Flag
0
Indicates no interrupt generated.
1
Indicates that an interrupt was generated.
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13.4.11 ECAP Interrupt Clear Register (ECCLR)
The ECAP interrupt clear register (ECCLR) is shown in Figure 13-27 and described in Table 13-24.
Figure 13-27. ECAP Interrupt Clear Register (ECCLR)
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CETV3
CETV2
CETV1
INT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-24. ECAP Interrupt Clear Register (ECCLR) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
Value
0
Description
Reserved
Counter Equal Compare Status Flag
0
Writing a 0 has no effect. Always reads back a 0
1
Writing a 1 clears the CTR=CMP flag condition
CTR=PRD
Counter Equal Period Status Flag
0
Writing a 0 has no effect. Always reads back a 0
1
Writing a 1 clears the CTR=PRD flag condition
CTROVF
Counter Overflow Status Flag
0
Writing a 0 has no effect. Always reads back a 0
1
Writing a 1 clears the CTROVF flag condition
CEVT4
Capture Event 4 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the CEVT3 flag condition.
CEVT3
Capture Event 3 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the CEVT3 flag condition.
CEVT2
Capture Event 2 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
0
Writing a 1 clears the CEVT2 flag condition.
CEVT1
Capture Event 1 Status Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the CEVT1 flag condition.
INT
Global Interrupt Clear Flag
0
Writing a 0 has no effect. Always reads back a 0.
1
Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are
set to 1.
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13.4.12 ECAP Interrupt Forcing Register (ECFRC)
The ECAP interrupt forcing register (ECFRC) is shown in Figure 13-28 and described in Table 13-25.
Figure 13-28. ECAP Interrupt Forcing Register (ECFRC)
15
14
13
12
11
10
9
8
Reserved
R-0
7
6
5
4
3
2
1
0
CTR=CMP
CTR=PRD
CTROVF
CEVT4
CETV3
CETV2
CETV1
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-25. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
Bit
Field
15-8
Reserved
7
CTR=CMP
6
5
4
3
2
1
0
330
Value
0
Reserved
Force Counter Equal Compare Interrupt
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CTR=CMP flag bit.
CTR=PRD
Force Counter Equal Period Interrupt
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CTR=PRD flag bit.
CTROVF
Force Counter Overflow
0
No effect. Always reads back a 0.
1
Writing a 1 to this bit sets the CTROVF flag bit.
CEVT4
Force Capture Event 4
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT4 flag bit
CEVT3
Force Capture Event 3
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT3 flag bit
CEVT2
Force Capture Event 2
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT2 flag bit.
CEVT1
Reserved
Description
Force Capture Event 1
0
No effect. Always reads back a 0.
1
Writing a 1 sets the CEVT1 flag bit.
0
Reserved
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13.4.13 Revision ID Register (REVID)
The revision ID register (REVID) is shown in Figure 13-29 and described in Table 13-26.
Figure 13-29. Revision ID Register (REVID)
31
0
REV
R-44D2 2100h
LEGEND: R = Read only; -n = value after reset
Table 13-26. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
Description
31-0
REV
44D2 2100h
Revision ID.
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Chapter 14
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Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM)
This chapter describes the enhanced high-resolution pulse-width modulator (eHRPWM).
Topic
14.1
14.2
14.3
14.4
332
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Applications to Power Topologies ......................................................................
Registers .........................................................................................................
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
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333
338
397
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14.1 Introduction
14.1.1 Introduction
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
In this chapter, the letter x within a signal or module name is used to indicate a generic ePWM instance on
a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the ePWMx
instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and, likewise, EPWM4A and EPWM4B belong
to ePWM4.
14.1.2 Submodule Overview
The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA
and EPWMxB. Multiple ePWM modules are instanced within a device as shown in Figure 14-1. Each
ePWM instance is identical with one exception. Some instances include a hardware extension that allows
more precise control of the PWM outputs. This extension is the high-resolution pulse width modulator
(HRPWM) and is described in Section 14.2.10. See your device-specific data manual to determine which
ePWM instances include this feature. Each ePWM module is indicated by a numerical value starting with
1. For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx
indicates any instance.
The ePWM modules are chained together via a clock synchronization scheme that allows them to operate
as a single system when required. Additionally, this synchronization scheme can be extended to the
capture peripheral modules (eCAP). The number of modules is device-dependent and based on target
application needs. Modules can also operate stand-alone.
Each ePWM module supports the following features:
• Dedicated 16-bit time-base counter with period and frequency control
• Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations::
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
• Asynchronous override control of PWM signals through software.
• Programmable phase-control support for lag or lead operation relative to other ePWM modules.
• Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
• Dead-band generation with independent rising and falling edge delay control.
• Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
• A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
• Programmable event prescaling minimizes CPU overhead on interrupts.
• PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
Each ePWM module is connected to the input/output signals shown in Figure 14-1. The signals are
described in detail in subsequent sections.
The order in which the ePWM modules are connected may differ from what is shown in Figure 14-1. See
Section 14.2.3.3.2 for the synchronization scheme for a particular device. Each ePWM module consists of
seven submodules and is connected within a system via the signals shown in Figure 14-2.
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Figure 14-1. Multiple ePWM Modules
xSYNCI
SYNCI
EPWM1INT
EPWM1A
ePWM1 module
EPWM1B
TZ1 to TZn
SYNCO
xSYNCO
To eCAP1
SYNCI
EPWM2INT
Interrupt
Controller
EPWM2A
ePWM2 module
EPWM2B
GPIO
MUX
TZ1 to TZn
SYNCO
SYNCI
EPWMxINT
EPWMxA
ePWMx module
EPWMxB
TZ1 to TZn
SYNCO
Peripheral
Frame 1
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Figure 14-2. Submodules and Signal Connections for an ePWM Module
ePWM module
EPWMxSYNCI
EPWMxSYNCO
Time-base (TB) module
Counter-compare (CC) module
Interrupt
controller
EPWMxTZINT
EPWMxINT
Action-qualifier (AQ) module
Dead-band (DB) module
PWM-chopper (PC) module
TZ1 to TZn
EPWMxA
EPWMxB
GPIO
MUX
Event-trigger (ET) module
Trip-zone (TZ) module
Peripheral bus
Figure 14-3 shows more internal details of a single ePWM module. The main signals used by the ePWM
module are:
• PWM output signals (EPWMxA and EPWMxB). The PWM output signals are made available
external to the device through the GPIO peripheral described in the system control and interrupts guide
for your device.
• Trip-zone signals (TZ1 to TZn). These input signals alert the ePWM module of an external fault
condition. Each module on a device can be configured to either use or ignore any of the trip-zone
signals. The trip-zone signal can be configured as an asynchronous input through the GPIO peripheral.
See your device-specific data manual to determine how many trip-zone pins are available in the
device.
• Time-base synchronization input (EPWMxSYNCI) and output (EPWMxSYNCO) signals. The
synchronization signals daisy chain the ePWM modules together. Each module can be configured to
either use or ignore its synchronization input. The clock synchronization input and output signal are
brought out to pins only for ePWM1 (ePWM module #1). The synchronization output for ePWM1
(EPWM1SYNCO) is also connected to the SYNCI of the first enhanced capture module (eCAP1).
• Peripheral Bus. The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the
ePWM register file.
Figure 14-3 also shows the key internal submodule interconnect signals. Each submodule is described in
detail in Section 14.2.
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Figure 14-3. ePWM Submodules and Critical Internal Signal Interconnects
Time−base (TB)
Sync
in/out
select
Mux
CTR = 0
CTR = CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR = PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR = 0
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
CTR = PRD
CTR = 0
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
control
Counter compare (CC)
CTR = CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxA
CMPA shadow (24)
Dead
band
(DB)
CTR = CMPB
16
PWM
chopper
(PC)
EPWMB
EPWMxB
CMPB active (16)
EPWMxTZINT
CMPB shadow (16)
336
Trip
zone
(TZ)
CTR = 0
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14.1.3 Register Mapping
Table 14-1 shows the complete ePWM module control and status register set grouped by submodule.
Each register set is duplicated for each instance of the ePWM module. The start address for each ePWM
register file instance on a device is specified in the appropriate data manual.
Table 14-1. ePWM Module Control and Status Registers Grouped by Submodule
Acronym
Offset (1)
Size
(×16)
Shadow Register Description
Time-Base Submodule Registers
TBCTL
0h
1
No
Time-Base Control Register
TBSTS
2h
1
No
Time-Base Status Register
TBPHSHR
4h
1
No
Extension for HRPWM Phase Register
TBPHS
6h
1
No
Time-Base Phase Register
TBCNT
8h
1
No
Time-Base Counter Register
TBPRD
Ah
1
Yes
Time-Base Period Register
(2)
Counter-Compare Submodule Registers
CMPCTL
Eh
1
No
Counter-Compare Control Register
CMPAHR
10h
1
No
Extension for HRPWM Counter-Compare A Register
CMPA
12h
1
Yes
Counter-Compare A Register
CMPB
14h
1
Yes
Counter-Compare B Register
(2)
Action-Qualifier Submodule Registers
AQCTLA
16h
1
No
Action-Qualifier Control Register for Output A (EPWMxA)
AQCTLB
18h
1
No
Action-Qualifier Control Register for Output B (EPWMxB)
AQSFRC
1Ah
1
No
Action-Qualifier Software Force Register
AQCSFRC
1Ch
1
Yes
Action-Qualifier Continuous S/W Force Register Set
Dead-Band Generator Submodule Registers
DBCTL
1Eh
1
No
Dead-Band Generator Control Register
DBRED
20h
1
No
Dead-Band Generator Rising Edge Delay Count Register
DBFED
22h
1
No
Dead-Band Generator Falling Edge Delay Count Register
No
PWM-Chopper Control Register
PWM-Chopper Submodule Registers
PCCTL
3Ch
1
Trip-Zone Submodule Registers
TZSEL
24h
1
No
Trip-Zone Select Register
TZCTL
28h
1
No
Trip-Zone Control Register
TZEINT
2Ah
1
No
Trip-Zone Enable Interrupt Register
TZFLG
2Ch
1
No
Trip-Zone Flag Register
TZCLR
2Eh
1
No
Trip-Zone Clear Register
TZFRC
30h
1
No
Trip-Zone Force Register
Event-Trigger Submodule Registers
ETSEL
32h
1
No
Event-Trigger Selection Register
ETPS
34h
1
No
Event-Trigger Pre-Scale Register
ETFLG
36h
1
No
Event-Trigger Flag Register
ETCLR
38h
1
No
Event-Trigger Clear Register
ETFRC
3Ah
1
No
Event-Trigger Force Register
High-Resolution PWM (HRPWM) Submodule Registers
HRCNFG
(1)
(2)
1040h
1
No
HRPWM Configuration Register
(2)
Locations not shown are reserved.
These registers are only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise,
these locations are reserved. See your device-specific data manual to determine which instances include the HRPWM.
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14.2 Architecture
Seven submodules are included in every ePWM peripheral. There are some instances that include a highresolution submodule that allows more precise control of the PWM outputs. Each of these submodules
performs specific tasks that can be configured by software.
14.2.1 Overview
Table 14-2 lists the eight key submodules together with a list of their main configuration parameters. For
example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the
counter-compare submodule in Section 14.2.4 for relevant details.
Table 14-2. Submodule Configuration Parameters
Submodule
Time-base (TB)
Configuration Parameter or Option
Reference
• Scale the time-base clock (TBCLK) relative to the system clock
(SYSCLKOUT).
• Configure the PWM time-base counter (TBCNT) frequency or period.
• Set the mode for the time-base counter:
•
•
•
•
•
–
count-up mode: used for asymmetric PWM
–
count-down mode: used for asymmetric PWM
Section 14.2.3
– count-up-and-down mode: used for symmetric PWM
Configure the time-base phase relative to another ePWM module.
Synchronize the time-base counter between modules through hardware
or software.
Configure the direction (up or down) of the time-base counter after a
synchronization event.
Configure how the time-base counter will behave when the device is
halted by an emulator.
Specify the source for the synchronization output of the ePWM module:
–
Synchronization input signal
–
Time-base counter equal to zero
–
Time-base counter equal to counter-compare B (CMPB)
–
No output synchronization signal generated.
Counter-compare (CC)
• Specify the PWM duty cycle for output EPWMxA and/or output EPWMxB
• Specify the time at which switching events occur on the EPWMxA or
EPWMxB output
Section 14.2.4
Action-qualifier (AQ)
• Specify the type of action taken when a time-base or counter-compare
submodule event occurs:
Section 14.2.5
–
No action taken
–
Output EPWMxA and/or EPWMxB switched high
–
Output EPWMxA and/or EPWMxB switched low
– Output EPWMxA and/or EPWMxB toggled
• Force the PWM output state through software control
• Configure and control the PWM dead-band through software
Dead-band (DB)
• Control of traditional complementary dead-band relationship between
upper and lower switches
• Specify the output rising-edge-delay value
• Specify the output falling-edge delay value
• Bypass the dead-band module entirely. In this case the PWM waveform
is passed through without modification.
Section 14.2.6
PWM-chopper (PC)
•
•
•
•
Section 14.2.7
Create a chopping (carrier) frequency.
Pulse width of the first pulse in the chopped pulse train.
Duty cycle of the second and subsequent pulses.
Bypass the PWM-chopper module entirely. In this case the PWM
waveform is passed through without modification.
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Table 14-2. Submodule Configuration Parameters (continued)
Submodule
Trip-zone (TZ)
Configuration Parameter or Option
• Configure the ePWM module to react to one, all, or none of the trip-zone
pins.
• Specify the tripping action taken when a fault occurs:
–
Force EPWMxA and/or EPWMxB high
–
Force EPWMxA and/or EPWMxB low
–
Force EPWMxA and/or EPWMxB to a high-impedance state
Reference
Section 14.2.8
– Configure EPWMxA and/or EPWMxB to ignore any trip condition.
• Configure how often the ePWM will react to each trip-zone pin:
–
One-shot
– Cycle-by-cycle
• Enable the trip-zone to initiate an interrupt.
• Bypass the trip-zone module entirely.
Event-trigger (ET)
• Enable the ePWM events that will trigger an interrupt.
• Specify the rate at which events cause triggers (every occurrence or
every second or third occurrence)
• Poll, set, or clear event flags
Section 14.2.9
High-Resolution PWM
(HRPWM)
• Enable extended time resolution capabilities
• Configure finer time granularity control or edge positioning
Section 14.2.10
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Code examples are provided in the remainder of this chapter that show how to implement various ePWM
module configurations. These examples use the constant definitions shown in Example 14-1.
Example 14-1. Constant Definitions Used in the Code Examples
// TBCTL (Time-Base Control)
// = = = = = = = = = = = = = = = = = =
// TBCNT MODE bit
#define
TB_COUNT_UP
0x0
#define
TB_COUNT_DOWN
0x1
#define
TB_COUNT_UPDOWN
0x2
#define
TB_FREEZE
0x3
// PHSEN bit
#define
TB_DISABLE
0x0
#define
TB_ENABLE
0x1
// PRDLD bit
#define
TB_SHADOW
0x0
#define
TB_IMMEDIATE
0x1
// SYNCOSEL bit
#define
TB_SYNC_IN
0x0
#define
TB_CTR_ZERO
0x1
#define
TB_CTR_CMPB
0x2
#define
TB_SYNC_DISABLE
0x3
// HSPCLKDIV and CLKDIV bits
#define
TB_DIV1
0x0
#define
TB_DIV2
0x1
#define
TB_DIV4
0x2
// PHSDIR bit
#define
TB_DOWN
0x0
#define
TB_UP
0x1
// CMPCTL (Compare Control)
// = = = = = = = = = = = = = = = = = =
// LOADAMODE and LOADBMODE bits
#define
CC_CTR_ZERO
0x0
#define
CC_CTR_PRD
0x1
#define
CC_CTR_ZERO_PRD
0x2
#define
CC_LD_DISABLE
0x3
// SHDWAMODE and SHDWBMODE bits
#define
CC_SHADOW
0x0
#define
CC_IMMEDIATE
0x1
// AQCTLA and AQCTLB (Action-qualifier
// = = = = = = = = = = = = = = = = = =
// ZRO, PRD, CAU, CAD, CBU, CBD bits
#define
AQ_NO_ACTION
0x0
#define
AQ_CLEAR
0x1
#define
AQ_SET
0x2
#define
AQ_TOGGLE
0x3
// DBCTL (Dead-Band Control)
// = = = = = = = = = = = = = = = = = =
// MODE bit
#define
DB_DISABLE
0x0
#define
DBA_ENABLE
0x1
#define
DBB_ENABLE
0x2
#define
DB_FULL_ENABLE
0x3
// POLSEL bit
#define
DB_ACTV_HI
0x0
#define
DB_ACTV_LOC
0x1
#define
DB_ACTV_HIC
0x2
#define
DB_ACTV_LO
0x3
// PCCTL (chopper control)
// = = = = = = = = = = = = = = = = = =
// CHPEN bit
#define
CHP_DISABLE
0x0
#define
CHP_ENABLE
0x1
340
= = = = = = = =
= = = = = = = =
Control)
= = = = = = = =
= = = = = = = =
= = = = = = = =
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Example 14-1. Constant Definitions Used in the Code Examples (continued)
// CHPFREQ bit
#define
CHP_DIV1
#define
CHP_DIV2
#define
CHP_DIV3
#define
CHP_DIV4
#define
CHP_DIV5
#define
CHP_DIV6
#define
CHP_DIV7
#define
CHP_DIV8
// CHPDUTY bit
#define
CHP1_8TH
#define
CHP2_8TH
#define
CHP3_8TH
#define
CHP4_8TH
#define
CHP5_8TH
#define
CHP6_8TH
#define
CHP7_8TH
// TZSEL (Trip-zone Select)
// = = = = = = = = = = = = = = =
// CBCn and OSHTn bits
#define
TZ_DISABLE
#define
TZ_ENABLE
// TZCTL (Trip-zone Control)
// = = = = = = = = = = = = = = =
// TZA and TZB bits
#define
TZ_HIZ
#define
TZ_FORCE_HI
#define
TZ_FORCE_LO
#define
TZ_NONE
// ETSEL (Event-trigger Select)
// = = = = = = = = = = = = = = =
// INTSEL bit
#define
ET_CTR_ZERO
#define
ET_CTR_PRD
#define
ET_CTRU_CMPA
#define
ET_CTRD_CMPA
#define
ET_CTRU_CMPB
#define
ET_CTRD_CMPB
// ETPS (Event-trigger Prescale)
// = = = = = = = = = = = = = = =
// INTPRD bit
#define
ET_DISABLE
#define
ET_1ST
#define
ET_2ND
#define
ET_3RD
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
= = = = = = = = = = =
0x0
0x1
= = = = = = = = = = =
0x0
0x1
0x2
0x3
= = = = = = = = = = =
0x1
0x2
0x4
0x5
0x6
0x7
= = = = = = = = = = =
0x0
0x1
0x2
0x3
14.2.2 Proper Interrupt Initialization Procedure
When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to
spurious events due to the ePWM registers not being properly initialized. The proper procedure for
initializing the ePWM peripheral is:
1. Disable global interrupts (CPU INTM flag)
2. Disable ePWM interrupts
3. Initialize peripheral registers
4. Clear any spurious ePWM flags
5. Enable ePWM interrupts
6. Enable global interrupts
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14.2.3 Time-Base (TB) Submodule
Each ePWM module has its own time-base submodule that determines all of the event timing for the
ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work
together as a single system. Figure 14-4 illustrates the time-base module's place within the ePWM.
Figure 14-4. Time-Base Submodule Block Diagram
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.3.1 Purpose of the Time-Base Submodule
You can configure the time-base submodule for the following:
• Specify the ePWM time-base counter (TBCNT) frequency or period to control how often events occur.
• Manage time-base synchronization with other ePWM modules.
• Maintain a phase relationship with other ePWM modules.
• Set the time-base counter to count-up, count-down, or count-up-and-down mode.
• Generate the following events:
– CTR = PRD: Time-base counter equal to the specified period (TBCNT = TBPRD) .
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h).
• Configure the rate of the time-base clock; a prescaled version of the CPU system clock
(SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate.
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14.2.3.2 Controlling and Monitoring the Time-Base Submodule
Table 14-3 lists the registers used to control and monitor the time-base submodule.
Table 14-3. Time-Base Submodule Registers
Acronym
Register Description
Address Offset
Shadowed
TBCTL
Time-Base Control Register
0h
No
TBSTS
Time-Base Status Register
2h
No
(1)
TBPHSHR
HRPWM extension Phase Register
4h
No
TBPHS
Time-Base Phase Register
6h
No
TBCNT
Time-Base Counter Register
8h
No
TBPRD
Time-Base Period Register
Ah
Yes
(1)
This register is available only on ePWM instances that include the high-resolution extension (HRPWM). On ePWM modules that
do not include the HRPWM, this location is reserved. See your device-specific data manual to determine which ePWM instances
include this feature.
Figure 14-5 shows the critical signals and registers of the time-base submodule. Table 14-4 provides
descriptions of the key signals associated with the time-base submodule.
Figure 14-5. Time-Base Submodule Signals and Registers
TBPRD
Period Shadow
TBCTL[PRDLD]
TBPRD
Period Active
TBCTL[SWFSYNC]
16
CTR = PRD
TBCNT
EPWMxSYNCI
16
CTR = 0
CTR_dir
CTR_max
TBCLK
Reset
Zero Counter
Mode
Dir UP/DOWN
Load
Max
clk
TBCNT
Counter Active Reg
TBCTL[CTRMODE]
CTR = 0
TBCTL[PHSEN] CTR = CMPB
Disable
X
Sync
Out
Select
EPWMxSYNCO
16
TBPHS
Phase Active Reg
SYSCLKOUT
Clock
Prescale
TBCTL[SYNCOSEL]
TBCLK
TBCTL[HSPCLKDIV]
TBCTL[CLKDIV]
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Table 14-4. Key Time-Base Signals
Signal
Description
EPWMxSYNCI
Time-base synchronization input.
Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the
synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM
module (EPWM1) this signal comes from a device pin. For subsequent ePWM modules this signal is passed
from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral,
EPWM3SYNCI is generated by ePWM2 and so forth. See Section 14.2.3.3.2 for information on the
synchronization order of a particular device.
EPWMxSYNCO
Time-base synchronization output.
This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain.
The ePWM module generates this signal from one of three event sources:
1.
2.
3.
CTR = PRD
EPWMxSYNCI (Synchronization input pulse)
CTR = 0: The time-base counter equal to zero (TBCNT = 0000h).
CTR = CMPB: The time-base counter equal to the counter-compare B (TBCNT = CMPB) register.
Time-base counter equal to the specified period.
This signal is generated whenever the counter value is equal to the active period register value. That is when
TBCNT = TBPRD.
CTR = 0
Time-base counter equal to zero.
This signal is generated whenever the counter value is zero. That is when TBCNT equals 0000h.
CTR = CMPB
Time-base counter equal to active counter-compare B register (TBCNT = CMPB).
This event is generated by the counter-compare submodule and used by the synchronization out logic.
CTR_dir
Time-base counter direction.
Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is
increasing and low when it is decreasing.
CTR_max
Time-base counter equal max value. (TBCNT = FFFFh)
Generated event when the TBCNT value reaches its maximum value. This signal is only used only as a status
bit.
TBCLK
Time-base clock.
This is a prescaled version of the system clock (SYSCLKOUT) and is used by all submodules within the
ePWM. This clock determines the rate at which time-base counter increments or decrements.
14.2.3.3 Calculating PWM Period and Frequency
The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the
time-base counter. Figure 14-6 shows the period (Tpwm) and frequency (Fpwm) relationships for the upcount, down-count, and up-down-count time-base counter modes when when the period is set to 4
(TBPRD = 4). The time increment for each step is defined by the time-base clock (TBCLK) which is a
prescaled version of the system clock (SYSCLKOUT).
The time-base counter has three modes of operation selected by the time-base control register (TBCTL):
• Up-Down-Count Mode: In up-down-count mode, the time-base counter starts from zero and
increments until the period (TBPRD) value is reached. When the period value is reached, the timebase counter then decrements until it reaches zero. At this point the counter repeats the pattern and
begins to increment.
• Up-Count Mode: In this mode, the time-base counter starts from zero and increments until it reaches
the value in the period register (TBPRD). When the period value is reached, the time-base counter
resets to zero and begins to increment once again.
• Down-Count Mode: In down-count mode, the time-base counter starts from the period (TBPRD) value
and decrements until it reaches zero. When it reaches zero, the time-base counter is reset to the
period value and it begins to decrement once again.
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Figure 14-6. Time-Base Frequency and Period
TPWM
4
PRD
4
4
3
3
2
3
2
1
2
1
0
Z 1
0
0
For Up Count and Down Count
TPWM
4
4
3
TPWM = (TBPRD + 1) x TTBCLK
FPWM = 1/ (TPWM)
PRD
4
3
2
3
2
1
2
1
0
1 Z
0
0
TPWM
TPWM
4
3
3
3
2
2
1
14.2.3.3.1
3
2
2
1
0
CTR_dir
1
1
0
Up
For Up and Down Count
TPWM = 2 x TBPRD x TTBCLK
FPWM = 1 / (TPWM)
4
Down
0
Up
Down
Time-Base Period Shadow Register
The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to
be synchronized with the hardware. The following definitions are used to describe all shadow registers in
the ePWM module:
• Active Register: The active register controls the hardware and is responsible for actions that the
hardware causes or invokes.
• Shadow Register: The shadow register buffers or provides a temporary holding location for the active
register. It has no direct effect on any control hardware. At a strategic point in time the shadow
register's content is transferred to the active register. This prevents corruption or spurious operation
due to the register being asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is
written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD
shadow register as follows:
•
•
Time-Base Period Shadow Mode: The TBPRD shadow register is enabled when TBCTL[PRDLD] =
0. Reads from and writes to the TBPRD memory address go to the shadow register. The shadow
register contents are transferred to the active register (TBPRD (Active) ← TBPRD (shadow)) when the
time-base counter equals zero (TBCNT = 0000h). By default the TBPRD shadow register is enabled.
Time-Base Period Immediate Load Mode: If immediate load mode is selected (TBCTL[PRDLD] = 1),
then a read from or a write to the TBPRD memory address goes directly to the active register.
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Time-Base Counter Synchronization
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM
module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The
input synchronization for the first instance (ePWM1) comes from an external pin. The possible
synchronization connections for the remaining ePWM modules is shown in Figure 14-7.
Figure 14-7. Time-Base Counter Synchronization Scheme 1
GPIO MUX
EPWM1SYNCI
ePWM1
EPWM1SYNCO
EPWM2SYNCI
ePWM2
EPWM2SYNCO
EPWM3SYNCI
ePWM3
EPWM3SYNCO
EPWMxSYNCI
ePWMx
EPWMxSYNCO
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Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN]
bit is set, then the time-base counter (TBCNT) of the ePWM module will be automatically loaded with the
phase register (TBPHS) contents when one of the following conditions occur:
• EPWMxSYNCI: Synchronization Input Pulse: The value of the phase register is loaded into the
counter register when an input synchronization pulse is detected (TBPHS → TBCNT). This operation
occurs on the next valid time-base clock (TBCLK) edge.
• Software Forced Synchronization Pulse: Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a
software forced synchronization. This pulse is ORed with the synchronization input signal, and
therefore has the same effect as a pulse on EPWMxSYNCI.
This feature enables the ePWM module to be automatically synchronized to the time base of another
ePWM module. Lead or lag phase control can be added to the waveforms generated by different ePWM
modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the direction of
the time-base counter immediately after a synchronization event. The new direction is independent of the
direction prior to the synchronization event. The TBPHS bit is ignored in count-up or count-down modes.
See Figure 14-8 through Figure 14-11 for examples.
Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse. The
synchronization pulse can still be allowed to flow-through to the EPWMxSYNCO and be used to
synchronize other ePWM modules. In this way, you can set up a master time-base (for example, ePWM1)
and downstream modules (ePWM2 - ePWMx) may elect to run in synchronization with the master.
14.2.3.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit in the chip configuration register 1 (CFGCHIP1) in the System Module can be used
to globally synchronize the time-base clocks of all enabled ePWM modules on a device. The TBCLKSYNC
bit is part of the chip configuration registers and is described in the device-specific data manual. When
TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped (default). When TBCLKSYNC = 1,
all ePWM time-base clocks are started with the rising edge of TBCLK aligned. For perfectly synchronized
TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The
proper procedure for enabling the ePWM clocks is as follows:
1. Enable the ePWM module clocks.
2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Set TBCLKSYNC = 1.
14.2.3.5 Time-Base Counter Modes and Timing Waveforms
The time-base counter operates in one of four modes:
• Up-count mode which is asymmetrical.
• Down-count mode which is asymmetrical.
• Up-down-count which is symmetrical.
• Frozen where the time-base counter is held constant at the current value.
To illustrate the operation of the first three modes, Figure 14-8 to Figure 14-11 show when events are
generated and how the time-base responds to an EPWMxSYNCI signal.
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Figure 14-8. Time-Base Up-Count Mode Waveforms
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR_dir
CTR = 0
CTR = PRD
CNT_max
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Figure 14-9. Time-Base Down-Count Mode Waveforms
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR_dir
CTR = 0
CTR = PRD
CNT_max
Figure 14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
UP
UP
UP
UP
CTR_dir
DOWN
DOWN
DOWN
CTR = 0
CTR = PRD
CNT_max
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Figure 14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
UP
UP
UP
CTR_dir
DOWN
DOWN
DOWN
CTR = 0
CTR = PRD
CNT_max
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14.2.4 Counter-Compare (CC) Submodule
Figure 14-12 illustrates the counter-compare submodule within the ePWM. Figure 14-13 shows the basic
structure of the counter-compare submodule.
Figure 14-12. Counter-Compare Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
MUX
EPWMxB
CTR = 0
TZ1 to TZn
EPWMxTZINT
Interrupt
controller
Figure 14-13. Counter-Compare Submodule Signals and Registers
Time
Base
(TB)
Module
TBCNT
CTR = CMPA
CMPA
CTR = PRD
CTR =0
16
Shadow
load
16
CMPA
Compare A Active Reg.
CMPA
Compare A Shadow Reg.
CMPCTL[LOADAMODE]
TBCNT
Digital
comparator A
CMPCTL
[SHDWAFULL]
CMPCTL
[SHDWAMODE]
Action
Qualifier
(AQ)
Module
16
CTR = CMPB
CMPB
CTR = PRD
CTR = 0
Shadow
load
16
Digital
comparator B
CMPB
Compare B Active Reg.
CMPB
Compare B Shadow Reg.
CMPCTL[SHDWBFULL]
CMPCTL[SHDWBMODE]
CMPCTL[LOADBMODE]
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14.2.4.1 Purpose of the Counter-Compare Submodule
The counter-compare submodule takes as input the time-base counter value. This value is continuously
compared to the counter-compare A (CMPA) and counter-compare B (CMPB) registers. When the timebase counter is equal to one of the compare registers, the counter-compare unit generates an appropriate
event.
The counter-compare submodule:
• Generates events based on programmable time stamps using the CMPA and CMPB registers
– CTR = CMPA: Time-base counter equals counter-compare A register (TBCNT = CMPA).
– CTR = CMPB: Time-base counter equals counter-compare B register (TBCNT = CMPB)
• Controls the PWM duty cycle if the action-qualifier submodule is configured appropriately
• Shadows new compare values to prevent corruption or glitches during the active PWM cycle
14.2.4.2 Controlling and Monitoring the Counter-Compare Submodule
Table 14-5 lists the registers used to control and monitor the counter-compare submodule. Table 14-6 lists
the key signals associated with the counter-compare submodule.
Table 14-5. Counter-Compare Submodule Registers
Acronym
Register Description
CMPCTL
Counter-Compare Control Register.
(1)
Address Offset
Shadowed
Eh
No
CMPAHR
HRPWM Counter-Compare A Extension Register
10h
Yes
CMPA
Counter-Compare A Register
12h
Yes
CMPB
Counter-Compare B Register
14h
Yes
(1)
This register is available only on ePWM modules with the high-resolution extension (HRPWM). On ePWM modules that do not
include the HRPWM, this location is reserved. Refer to the device-specific data manual to determine which ePWM instances
include this feature.
Table 14-6. Counter-Compare Submodule Key Signals
352
Signal
Description of Event
Registers Compared
CTR = CMPA
Time-base counter equal to the active counter-compare A value
TBCNT = CMPA
CTR = CMPB
Time-base counter equal to the active counter-compare B value
TBCNT = CMPB
CTR = PRD
Time-base counter equal to the active period.
TBCNT = TBPRD
Used to load active counter-compare A and B registers from the shadow register
CTR = 0
Time-base counter equal to zero.
TBCNT = 0000h
Used to load active counter-compare A and B registers from the shadow register
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14.2.4.3 Operational Highlights for the Counter-Compare Submodule
The counter-compare submodule is responsible for generating two independent compare events based on
two compare registers:
1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCNT = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCNT = CMPB).
For up-count or down-count mode, each event occurs only once per cycle. For up-down-count mode each
event occurs twice per cycle, if the compare value is between 0000h and TBPRD; and occurs once per
cycle, if the compare value is equal to 0000h or equal to TBPRD. These events are fed into the actionqualifier submodule where they are qualified by the counter direction and converted into actions if
enabled. Refer to Section 14.2.5.1 for more details.
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occurs at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. Which register is written to or read from is determined
by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the
CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:
•
•
Shadow Mode: The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE]
bit and the shadow register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow
mode is enabled by default for both CMPA and CMPB.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events:
– CTR = PRD: Time-base counter equal to the period (TBCNT = TBPRD).
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
– Both CTR = PRD and CTR = 0
Which of these three events is specified by the CMPCTL[LOADAMODE] and CMPCTL[LOADBMODE]
register bits. Only the active register contents are used by the counter-compare submodule to generate
events to be sent to the action-qualifier.
Immediate Load Mode: If immediate load mode is selected (TBCTL[SHADWAMODE] = 1 or
TBCTL[SHADWBMODE] = 1), then a read from or a write to the register will go directly to the active
register.
14.2.4.4 Count Mode Timing Waveforms
The counter-compare module can generate compare events in all three count modes:
• Up-count mode: used to generate an asymmetrical PWM waveform.
• Down-count mode: used to generate an asymmetrical PWM waveform.
• Up-down-count mode: used to generate a symmetrical PWM waveform.
To best illustrate the operation of the first three modes, the timing diagrams in Figure 14-14 to Figure 1417 show when events are generated and how the EPWMxSYNCI signal interacts.
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Figure 14-14. Counter-Compare Event Waveforms in Up-Count Mode
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
NOTE: An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCNT count
sequence. This can lead to a compare event being skipped. This skipping is considered normal operation and
must be taken into account.
Figure 14-15. Counter-Compare Events in Down-Count Mode
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
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Figure 14-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPB
CTR = CMPA
Figure 14-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on
Synchronization Event
TBCNT
FFFFh
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0000h
EPWMxSYNCI
CTR = CMPB
CTR = CMPA
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14.2.5 Action-Qualifier (AQ) Submodule
Figure 14-18 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. The
action-qualifier submodule has the most important role in waveform construction and PWM generation. It
decides which events are converted into various action types, thereby producing the required switched
waveforms at the EPWMxA and EPWMxB outputs.
Figure 14-18. Action-Qualifier Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.5.1 Purpose of the Action-Qualifier Submodule
The action-qualifier submodule is responsible for the following:
• Qualifying and generating actions (set, clear, toggle) based on the following events:
– CTR = PRD: Time-base counter equal to the period (TBCNT = TBPRD)
– CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
– CTR = CMPA: Time-base counter equal to the counter-compare A register (TBCNT = CMPA)
– CTR = CMPB: Time-base counter equal to the counter-compare B register (TBCNT = CMPB)
• Managing priority when these events occur concurrently
• Providing independent control of events when the time-base counter is increasing and when it is
decreasing.
14.2.5.2 Controlling and Monitoring the Action-Qualifier Submodule
Table 14-7 lists the registers used to control and monitor the action-qualifier submodule.
Table 14-7. Action-Qualifier Submodule Registers
356
Acronym
Register Description
AQCTLA
Action-Qualifier Control Register For Output A (EPWMxA)
Address Offset
Shadowed
16h
No
AQCTLB
AQSFRC
Action-Qualifier Control Register For Output B (EPWMxB)
18h
No
Action-Qualifier Software Force Register
1Ah
AQCSFRC
No
Action-Qualifier Continuous Software Force
1Ch
Yes
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The action-qualifier submodule is based on event-driven logic. It can be thought of as a programmable
cross switch with events at the input and actions at the output, all of which are software controlled via the
set of registers shown in Figure 14-19. The possible input events are summarized again in Table 14-8.
Figure 14-19. Action-Qualifier Submodule Inputs and Outputs
Action-qualifier (AQ) Module
TBCLK
AQCTLA[15:0]
Action-qualifier control A
EPWMA
CTR = PRD
AQCTLB[15:0]
Action-qualifier control B
CTR = 0
CTR = CMPA
AQSFRC[15:0]
Action-qualifier S/W force
CTR = CMPB
EPWMB
AQCSFRC[3:0] (shadow)
continuous S/W force
CTR_dir
AQCSFRC[3:0] (active)
continuous S/W force
Table 14-8. Action-Qualifier Submodule Possible Input Events
Signal
Description
Registers Compared
CTR = PRD
Time-base counter equal to the period value
TBCNT = TBPRD
CTR = 0
Time-base counter equal to zero
TBCNT = 0000h
CTR = CMPA
Time-base counter equal to the counter-compare A
TBCNT = CMPA
CTR = CMPB
Time-base counter equal to the counter-compare B
TBCNT = CMPB
Software forced event
Asynchronous event initiated by software
The software forced action is a useful asynchronous event. This control is handled by registers AQSFRC
and AQCSFRC.
The action-qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a
particular event occurs. The event inputs to the action-qualifier submodule are further qualified by the
counter direction (up or down). This allows for independent action on outputs on both the count-up and
count-down phases.
The possible actions imposed on outputs EPWMxA and EPWMxB are:
• Set High: Set output EPWMxA or EPWMxB to a high level.
• Clear Low: Set output EPWMxA or EPWMxB to a low level.
• Toggle: If EPWMxA or EPWMxB is currently pulled high, then pull the output low. If EPWMxA or
EPWMxB is currently pulled low, then pull the output high.
• Do Nothing: Keep outputs EPWMxA and EPWMxB at same level as currently set. Although the "Do
Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this
event can still trigger interrupts. See the event-trigger submodule description in Section 14.2.9 for
details.
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Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be
configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can
operate on output EPWMxA. All qualifier actions are configured via the control registers found at the end
of this section.
For clarity, the drawings in this chapter use a set of symbolic actions. These symbols are summarized in
Figure 14-20. Each symbol represents an action as a marker in time. Some actions are fixed in time (zero
and period) while the CMPA and CMPB actions are moveable and their time positions are programmed
via the counter-compare A and B registers, respectively. To turn off or disable an action, use the "Do
Nothing option"; it is the default at reset.
Figure 14-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
TB Counter equals:
Actions
S/W
force
Zero
Comp
A
Comp
B
Period
SW
Z
CA
CB
P
SW
Z
CA
CB
P
SW
Z
CA
CB
P
Do Nothing
Clear Low
Set High
SW
T
358
Z
T
CA
T
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T
P
T
Toggle
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14.2.5.3 Action-Qualifier Event Priority
It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case
events are assigned a priority by the hardware. The general rule is events occurring later in time have a
higher priority and software forced events always have the highest priority. The event priority levels for updown-count mode are shown in Table 14-9. A priority level of 1 is the highest priority and level 7 is the
lowest. The priority changes slightly depending on the direction of TBCNT.
Table 14-9. Action-Qualifier Event Priority for Up-Down-Count Mode
Event if TBCNT is Incrementing
TBCNT = 0 up to TBCNT = TBPRD
Event if TBCNT is Decrementing
TBCNT = TBPRD down to TBCNT = 1
Software forced event
Software forced event
2
Counter equals CMPB on up-count (CBU)
Counter equals CMPB on down-count (CBD)
3
Counter equals CMPA on up-count (CAU)
Counter equals CMPA on down-count (CAD)
4
Counter equals zero
Priority Level
1 (Highest)
5
6 (Lowest)
(1)
Counter equals period (TBPRD)
Counter equals CMPB on down-count (CBD)
(1)
Counter equals CMPB on up-count (CBU)
(1)
Counter equals CMPA on down-count (CAD)
(1)
Counter equals CMPA on up-count (CBU)
(1)
To maintain symmetry for up-down-count mode, both up-events (CAU/CBU) and down-events (CAD/CBD) can be generated for
TBPRD. Otherwise, up-events can occur only when the counter is incrementing and down-events can occur only when the
counter is decrementing.
Table 14-10 shows the action-qualifier priority for up-count mode. In this case, the counter direction is
always defined as up and thus down-count events will never be taken.
Table 14-10. Action-Qualifier Event Priority for Up-Count Mode
Priority Level
Event
1 (Highest)
Software forced event
2
Counter equal to period (TBPRD)
3
Counter equal to CMPB on up-count (CBU)
4
Counter equal to CMPA on up-count (CAU)
5 (Lowest)
Counter equal to Zero
Table 14-11 shows the action-qualifier priority for down-count mode. In this case, the counter direction is
always defined as down and thus up-count events will never be taken.
Table 14-11. Action-Qualifier Event Priority for Down-Count Mode
Priority Level
Event
1 (Highest)
Software forced event
2
Counter equal to Zero
3
Counter equal to CMPB on down-count (CBD)
4
Counter equal to CMPA on down-count (CAD)
5 (Lowest)
Counter equal to period (TBPRD)
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It is possible to set the compare value greater than the period. In this case the action will take place as
shown in Table 14-12.
Table 14-12. Behavior if CMPA/CMPB is Greater than the Period
Counter Mode
Compare on Up-Count Event CAU/CBU
Compare on Down-Count Event CAU/CBU
Up-Count Mode
If CMPA/CMPB ≤ TBPRD period, then the event
occurs on a compare match (TBCNT = CMPA or
CMPB).
Never occurs.
If CMPA/CMPB > TBPRD, then the event will not
occur.
Down-Count Mode
Never occurs.
If CMPA/CMPB < TBPRD, the event will occur on a
compare match (TBCNT = CMPA or CMPB).
If CMPA/CMPB ≥ TBPRD, the event will occur on a
period match (TBCNT = TBPRD).
Up-Down-Count
Mode
If CMPA/CMPB < TBPRD and the counter is
incrementing, the event occurs on a compare match
(TBCNT = CMPA or CMPB).
If CMPA/CMPB < TBPRD and the counter is
decrementing, the event occurs on a compare match
(TBCNT = CMPA or CMPB).
If CMPA/CMPB is ≥ TBPRD, the event will occur on a If CMPA/CMPB ≥ TBPRD, the event occurs on a
period match (TBCNT = TBPRD).
period match (TBCNT = TBPRD).
14.2.5.4 Waveforms for Common Configurations
NOTE:
The waveforms in this chapter show the ePWMs behavior for a static compare register
value. In a running system, the active compare registers (CMPA and CMPB) are typically
updated from their respective shadow registers once every period. The user specifies when
the update will take place; either when the time-base counter reaches zero or when the timebase counter reaches period. There are some cases when the action based on the new
value can be delayed by one period or the action based on the old value can take effect for
an extra period. Some PWM configurations avoid this situation. These include, but are not
limited to, the following:
Use up-down-count mode to generate a symmetric PWM:
•
•
If you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or
equal to 1.
If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD - 1.
This means there will always be a pulse of at least one TBCLK cycle in a PWM
period which, when very short, tend to be ignored by the system.
Use up-down-count mode to generate an asymmetric PWM:
•
To achieve 50%-0% asymmetric PWM use the following configuration: Load
CMPA/CMPB on period and use the period action to clear the PWM and a
compare-up action to set the PWM. Modulate the compare value from 0 to
TBPRD to achieve 50%-0% PWM duty.
When using up-count mode to generate an asymmetric PWM:
•
360
To achieve 0-100% asymmetric PWM use the following configuration: Load
CMPA/CMPB on TBPRD. Use the Zero action to set the PWM and a compareup action to clear the PWM. Modulate the compare value from 0 to TBPRD+1 to
achieve 0-100% PWM duty.
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Figure 14-21 shows how a symmetric PWM waveform can be generated using the up-down-count mode
of the TBCNT. In this mode 0%-100% DC modulation is achieved by using equal compare matches on the
up count and down count portions of the waveform. In the example shown, CMPA is used to make the
comparison. When the counter is incrementing the CMPA match will pull the PWM output high. Likewise,
when the counter is decrementing the compare match will pull the PWM signal low. When CMPA = 0, the
PWM signal is low for the entire period giving the 0% duty waveform. When CMPA = TBPRD, the PWM
signal is high achieving 100% duty.
When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values
greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period
which, when very short, tend to be ignored by the system.
Figure 14-21. Up-Down-Count Mode Symmetrical Waveform
4
4
Mode: Up-Down Count
TBPRD = 4
CAU = SET, CAD = CLEAR
0% - 100% Duty
3
3
3
2
1
1
1
1
TBCNT
2
2
2
3
0
0
0
TBCTR Direction
DOWN
UP
UP
DOWN
Case 1:
CMPA = 4, 0% Duty
EPWMxA/EPWMxB
Case 2:
CMPA = 3, 25% Duty
EPWMxA/EPWMxB
Case 3:
CMPA = 2, 50% Duty
EPWMxA/EPWMxB
Case 3:
CMPA = 1, 75% Duty
EPWMxA/EPWMxB
Case 4:
CMPA = 0, 100% Duty
EPWMxA/EPWMxB
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The PWM waveforms in Figure 14-22 through Figure 14-27 show some common action-qualifier
configurations. Some conventions used in the figures are as follows:
• TBPRD, CMPA, and CMPB refer to the value written in their respective registers. The active register,
not the shadow register, is used by the hardware.
• CMPx, refers to either CMPA or CMPB.
• EPWMxA and EPWMxB refer to the output signals from ePWMx
• Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count
mode
• Sym = Symmetric, Asym = Asymmetric
Table 14-13 and Table 14-14 contains initialization and runtime register configurations for the waveforms
in Figure 14-22.
Figure 14-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High
TBCNT
TBPRD
(value)
Z
P
CB
CA
Z
P
CB
CA
Z
P
Z
P
CB
CA
Z
P
CB
CA
Z
P
EPWMxA
EPWMxB
(1)
PWM period = (TBPRD + 1 ) × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to
CMPA).
(3)
Duty modulation for EPWMxB is set by CMPB and is active high (that is, high time duty proportional to
CMPB).
(4)
The "Do Nothing" actions ( X ) are shown for completeness, but will not be shown on subsequent diagrams.
(5)
Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK
period. TBCNT wraps from period to 0000h.
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Table 14-13. EPWMx Initialization for Figure 14-22
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
350 (15Eh)
Compare A = 350 TBCLK counts
CMPB
CMPB
200 (C8h)
Compare B = 200 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
CAU
AQ_CLEAR
ZRO
AQ_SET
CBU
AQ_CLEAR
AQCTLA
AQCTLB
Table 14-14. EPWMx Run Time Changes for Figure 14-22
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-15 and Table 14-16 contains initialization and runtime register configurations for the waveforms
in Figure 14-23.
Figure 14-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low
TBCNT
TBPRD
(value)
P
CA
P
CA
P
EPWMxA
P
CB
CB
P
P
EPWMxB
(1)
PWM period = (TBPRD + 1 ) × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to
CMPA).
(3)
Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to
CMPB).
(4)
The Do Nothing actions ( X ) are shown for completeness here, but will not be shown on subsequent
diagrams.
(5)
Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK
period. TBCNT wraps from period to 0000h.
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Table 14-15. EPWMx Initialization for Figure 14-23
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
350 (15Eh)
Compare A = 350 TBCLK counts
CMPB
CMPB
200 (C8h)
Compare B = 200 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
PRD
AQ_CLEAR
CBU
AQ_SET
AQCTLA
AQCTLB
Table 14-16. EPWMx Run Time Changes for Figure 14-23
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-17 and Table 14-18 contains initialization and runtime register configurations for the waveforms
Figure 14-24. Use the code in Example 14-1 to define the headers.
Figure 14-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on
EPWMxA
TBCNT
TBPRD
(value)
CA
CB
CA
CB
EPWMxA
Z
T
Z
T
Z
T
EPWMxB
(1)
PWM frequency = 1/( (TBPRD + 1 ) × TTBCLK )
(2)
Pulse can be placed anywhere within the PWM cycle (0000h - TBPRD)
(3)
High time duty proportional to (CMPB - CMPA)
(4)
EPWMxB can be used to generate a 50% duty square wave with frequency = 1/2 × ((TBPRD + 1) × TBCLK)
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Table 14-17. EPWMx Initialization for Figure 14-24
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
200 (C8h)
Compare A = 200 TBCLK counts
CMPB
CMPB
400 (190h)
Compare B = 400 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CBU
AQ_CLEAR
ZRO
AQ_TOGGLE
AQCTLA
AQCTLB
Table 14-18. EPWMx Run Time Changes for Figure 14-24
Register
Bit
Value
Comments
CMPA
CMPA
EdgePosA
Adjust duty for output EPWM1A
CMPB
CMPB
EdgePosB
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Table 14-19 and Table 14-20 contains initialization and runtime register configurations for the waveforms
in Figure 14-25. Use the code in Example 14-1 to define the headers.
Figure 14-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Active Low
TBCNT
TBPRD
(value)
CA
CA
CA
CA
EPWMxA
CB
CB
CB
CB
EPWMxB
(1)
PWM period = 2 x TBPRD × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to
CMPA).
(3)
Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to
CMPB).
(4)
Outputs EPWMxA and EPWMxB can drive independent power switches
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Table 14-19. EPWMx Initialization for Figure 14-25
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
400 (190h)
Compare A = 400 TBCLK counts
CMPB
CMPB
500 (1F4h)
Compare B = 500 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CAD
AQ_CLEAR
CBU
AQ_SET
CBD
AQ_CLEAR
AQCTLA
AQCTLB
Table 14-20. EPWMx Run Time Changes for Figure 14-25
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-21 and Table 14-22 contains initialization and runtime register configurations for the waveforms
in Figure 14-26. Use the code in Example 14-1 to define the headers.
Figure 14-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Complementary
TBCNT
TBPRD
(value)
CA
CA
CA
CA
EPWMxA
CB
CB
CB
CB
EPWMxB
(1)
PWM period = 2 × TBPRD × TTBCLK
(2)
Duty modulation for EPWMxA is set by CMPA, and is active low, i.e., low time duty proportional to CMPA
(3)
Duty modulation for EPWMxB is set by CMPB and is active high, i.e., high time duty proportional to CMPB
(4)
Outputs EPWMx can drive upper/lower (complementary) power switches
(5)
Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module
is also available if the more classical edge delay method is required.
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Table 14-21. EPWMx Initialization for Figure 14-26
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
350 (15Eh)
Compare A = 350 TBCLK counts
CMPB
CMPB
400 (190h)
Compare B = 400 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CAD
AQ_CLEAR
CBU
AQ_CLEAR
CBD
AQ_SET
AQCTLA
AQCTLB
Table 14-22. EPWMx Run Time Changes for Figure 14-26
Register
Bit
Value
Comments
CMPA
CMPA
Duty1A
Adjust duty for output EPWM1A
CMPB
CMPB
Duty1B
Adjust duty for output EPWM1B
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Table 14-23 and Table 14-24 contains initialization and runtime register configurations for the waveforms
in Figure 14-27. Use the code in Example 14-1 to define the headers.
Figure 14-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on
EPWMxA—Active Low
TBCNT
CA
CA
CB
CB
EPWMxA
Z
P
Z
P
EPWMxB
(1)
PWM period = 2 × TBPRD × TBCLK
(2)
Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse
placement techniques.
(3)
Duty modulation for EPWMxA is set by CMPA and CMPB.
(4)
Low time duty for EPWMxA is proportional to (CMPA + CMPB).
(5)
To change this example to active high, CMPA and CMPB actions need to be inverted (i.e., Set ! Clear and
Clear Set).
(6)
Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB)
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Table 14-23. EPWMx Initialization for Figure 14-27
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 601 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCNT
TBCNT
0
Clear TB counter
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
HSPCLKDIV
TB_DIV1
Phase loading disabled
TBCLK = SYSCLK
CLKDIV
TB_DIV1
CMPA
CMPA
250 (FAh)
Compare A = 250 TBCLK counts
CMPB
CMPB
450 (1C2h)
Compare B = 450 TBCLK counts
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
CBD
AQ_CLEAR
ZRO
AQ_CLEAR
PRD
AQ_SET
AQCTLA
AQCTLB
Table 14-24. EPWMx Run Time Changes for Figure 14-27
Register
Bit
Value
Comments
CMPA
CMPA
EdgePosA
Adjust duty for output EPWM1A
CMPB
CMPB
EdgePosB
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14.2.6 Dead-Band Generator (DB) Submodule
Figure 14-28 illustrates the dead-band generator submodule within the ePWM module.
Figure 14-28. Dead-Band Generator Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
Action
Qualifier
(AQ)
CTR = PRD
Time-Base
(TB)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.6.1 Purpose of the Dead-Band Submodule
The "Action-qualifier (AQ) Module" section discussed how it is possible to generate the required deadband by having full control over edge placement using both the CMPA and CMPB resources of the ePWM
module. However, if the more classical edge delay-based dead-band with polarity control is required, then
the dead-band generator submodule should be used.
The key functions of the dead-band generator submodule are:
• Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a
single EPWMxA input
• Programming signal pairs for:
– Active high (AH)
– Active low (AL)
– Active high complementary (AHC)
– Active low complementary (ALC)
• Adding programmable delay to rising edges (RED)
• Adding programmable delay to falling edges (FED)
• Can be totally bypassed from the signal path (note dotted lines in diagram)
14.2.6.2 Controlling and Monitoring the Dead-Band Submodule
The dead-band generator submodule operation is controlled and monitored via the following registers:
Table 14-25. Dead-Band Generator Submodule Registers
374
Acronym
Register Description
Address Offset
Shadowed
DBCTL
Dead-Band Control Register
1Eh
No
DBRED
Dead-Band Rising Edge Delay Count Register
20h
No
DBFED
Dead-Band Falling Edge Delay Count Register
22h
No
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14.2.6.3 Operational Highlights for the Dead-Band Generator Submodule
The following sections provide the operational highlights.
The dead-band submodule has two groups of independent selection options as shown in Figure 14-29.
• Input Source Selection: The input signals to the dead-band module are the EPWMxA and EPWMxB
output signals from the action-qualifier. In this section they will be referred to as EPWMxA In and
EPWMxB In. Using the DBCTL[IN_MODE) control bits, the signal source for each delay, falling-edge or
rising-edge, can be selected:
– EPWMxA In is the source for both falling-edge and rising-edge delay. This is the default mode.
– EPWMxA In is the source for falling-edge delay, EPWMxB In is the source for rising-edge delay.
– EPWMxA In is the source for rising edge delay, EPWMxB In is the source for falling-edge delay.
– EPWMxB In is the source for both falling-edge and rising-edge delay.
• Output Mode Control: The output mode is configured by way of the DBCTL[OUT_MODE] bits. These
bits determine if the falling-edge delay, rising-edge delay, neither, or both are applied to the input
signals.
• Polarity Control: The polarity control (DBCTL[POLSEL]) allows you to specify whether the rising-edge
delayed signal and/or the falling-edge delayed signal is to be inverted before being sent out of the
dead-band submodule.
Figure 14-29. Configuration Options for the Dead-Band Generator Submodule
EPWMxA in
Rising edge
delay
0 S4
In
0 S2
0 S1
Out
1
1
1
EPWMxA
RED
(10-bit
counter)
Falling edge
delay
0 S5
In
0 S3
(10-bit
counter)
DBCTL[IN_MODE]
1 S0
EPWMxB
Out
1
1
FED
DBCTL[POLSEL]
0
DBCTL[OUT_MODE]
EPWMxB in
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Although all combinations are supported, not all are typical usage modes. Table 14-26 lists some classical
dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such that
EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional modes
can be achieved by changing the input signal source. The modes shown in Table 14-26 fall into the
following categories:
• Mode 1: Bypass both falling-edge delay (FED) and rising-edge delay (RED) Allows you to fully
disable the dead-band submodule from the PWM signal path.
• Mode 2-5: Classical Dead-Band Polarity Settings These represent typical polarity configurations that
should address all the active high/low modes required by available industry power switch gate drivers.
The waveforms for these typical cases are shown in Figure 14-30. Note that to generate equivalent
waveforms to Figure 14-30, configure the action-qualifier submodule to generate the signal as shown
for EPWMxA.
• Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay Finally the last two
entries in Table 14-26 show combinations where either the falling-edge-delay (FED) or rising-edgedelay (RED) blocks are bypassed.
Table 14-26. Classical Dead-Band Operating Modes
DBCTL[POLSEL]
Mode
Mode Description
(1)
S3
DBCTL[OUT_MODE]
S2
S1
S0
1
EPWMxA and EPWMxB Passed Through (No Delay)
x
x
0
0
2
Active High Complementary (AHC)
1
0
1
1
3
Active Low Complementary (ALC)
0
1
1
1
4
Active High (AH)
0
0
1
1
5
Active Low (AL)
1
1
1
1
6
EPWMxA Out = EPWMxA In (No Delay)
0 or 1
0 or 1
0 or 1
0 or 1
EPWMxB Out = EPWMxA In with Falling Edge Delay
7
EPWMxA Out = EPWMxA In with Rising Edge Delay
0
1
1
0
EPWMxB Out = EPWMxB In with No Delay
(1)
376
These are classical dead-band modes and assume that DBCTL[IN_MODE] = 0,0. That is, EPWMxA in is the source for both the
falling-edge and rising-edge delays. Enhanced, non-traditional modes can be achieved by changing the IN_MODE configuration.
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Figure 14-30 shows waveforms for typical cases where 0% < duty < 100%.
Figure 14-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
Period
Original
(outA)
RED
Rising Edge
Delayed (RED)
FED
Falling Edge
Delayed (FED)
Active High
Complementary
(AHC)
Active Low
Complementary
(ALC)
Active High
(AH)
Active Low
(AL)
The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is
delayed by. For example, the formula to calculate falling-edge-delay and rising-edge-delay are:
FED = DBFED × TTBCLK
RED = DBRED × TTBCLK
Where TTBCLK is the period of TBCLK, the prescaled version of SYSCLKOUT.
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14.2.7 PWM-Chopper (PC) Submodule
Figure 14-31 illustrates the PWM-chopper (PC) submodule within the ePWM module. The PWM-chopper
submodule allows a high-frequency carrier signal to modulate the PWM waveform generated by the
action-qualifier and dead-band submodules. This capability is important if you need pulse transformerbased gate drivers to control the power switching elements.
Figure 14-31. PWM-Chopper Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
EPWMxA
EPWMxB
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxA
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.7.1 Purpose of the PWM-Chopper Submodule
The key functions of the PWM-chopper submodule are:
• Programmable chopping (carrier) frequency
• Programmable pulse width of first pulse
• Programmable duty cycle of second and subsequent pulses
• Can be fully bypassed if not required
14.2.7.2 Controlling the PWM-Chopper Submodule
The PWM-chopper submodule operation is controlled via the register in Table 14-27.
Table 14-27. PWM-Chopper Submodule Registers
378
Acronym
Register Description
PCCTL
PWM-chopper Control Register
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Address Offset
Shadowed
3Ch
No
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14.2.7.3 Operational Highlights for the PWM-Chopper Submodule
Figure 14-32 shows the operational details of the PWM-chopper submodule. The carrier clock is derived
from SYSCLKOUT. Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in
the PCCTL register. The one-shot block is a feature that provides a high energy first pulse to ensure hard
and fast power switch turn on, while the subsequent pulses sustain pulses, ensuring the power switch
remains on. The one-shot width is programmed via the OSHTWTH bits. The PWM-chopper submodule
can be fully disabled (bypassed) via the CHPEN bit.
Figure 14-32. PWM-Chopper Submodule Signals and Registers
Bypass
0
EPWMxA
EPWMxA
Start
One
shot
OSHT
PWMA_ch
1
Clk
Pulse-width
SYSCLKOUT
/8
PCCTL
[OSHTWTH]
PCCTL
[OSHTWTH]
Pulse-width
Divider and
duty control
PCCTL
[CHPEN]
PSCLK
PCCTL[CHPFREQ]
PCCTL[CHPDUTY]
Clk
One
shot
EPWMxB
PWMB_ch
1
OSHT
EPWMxA
Start
Bypass
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14.2.7.4 Waveforms
Figure 14-33 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are
not shown. Details of the one-shot and duty-cycle control are discussed in the following sections.
Figure 14-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
EPWMxA
EPWMxB
PSCLK
EPWMxA
EPWMxB
14.2.7.4.1
One-Shot Pulse
The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or
period of the first pulse is given by:
T1stpulse = TSYSCLKOUT × 8 × OSHTWTH
Where TSYSCLKOUT is the period of the system clock (SYSCLKOUT) and OSHTWTH is the four control bits
(value from 1 to 16)
Figure 14-34 shows the first and subsequent sustaining pulses.
Figure 14-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and
Subsequent Sustaining Pulses
Start OSHT pulse
EPWMxA in
PSCLK
Prog. pulse width
(OSHTWTH)
OSHT
EPWMxA out
Sustaining pulses
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14.2.7.4.2
Duty Cycle Control
Pulse transformer-based gate drive designs need to comprehend the magnetic properties or
characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist
the gate drive designer, the duty cycles of the second and subsequent pulses have been made
programmable. These sustaining pulses ensure the correct drive strength and polarity is maintained on the
power switch gate during the on period, and hence a programmable duty cycle allows a design to be
tuned or optimized via software control.
Figure 14-35 shows the duty cycle control that is possible by programming the CHPDUTY bits. One of
seven possible duty ratios can be selected ranging from 12.5% to 87.5%.
Figure 14-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of
Sustaining Pulses
PSCLK
PSCLK
period
75%
50%
25%
62.5% 37.5%
87.5%
12.5%
PSCLK Period
Duty
1/8
Duty
2/8
Duty
3/8
Duty
4/8
Duty
5/8
Duty
6/8
Duty
7/8
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14.2.8 Trip-Zone (TZ) Submodule
Figure 14-36 shows how the trip-zone (TZ) submodule fits within the ePWM module. Each ePWM module
is connected to every TZ signal that are sourced from the GPIO MUX. These signals indicates external
fault or trip conditions, and the ePWM outputs can be programmed to respond accordingly when faults
occur. See your device-specific data manual to determine the number of trip-zone pins available for the
device.
Figure 14-36. Trip-Zone Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
EPWMxA
EPWMxA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
Interrupt
controller
(ET)
CTR_Dir
CTR = 0
EPWMxINT
PWMchopper
(PC)
Trip
Zone
(TZ)
GPIO
EPWMxB
CTR = CMPB
EPWMxB
CTR = 0
Interrupt
controller
MUX
TZ1 to TZn
EPWMxTZINT
14.2.8.1 Purpose of the Trip-Zone Submodule
The key functions of the trip-zone submodule are:
• Trip inputs TZ1 to TZn can be flexibly mapped to any ePWM module.
• Upon a fault condition, outputs EPWMxA and EPWMxB can be forced to one of the following:
– High
– Low
– High-impedance
– No action taken
• Support for one-shot trip (OSHT) for major short circuits or over-current conditions.
• Support for cycle-by-cycle tripping (CBC) for current limiting operation.
• Each trip-zone input pin can be allocated to either one-shot or cycle-by-cycle operation.
• Interrupt generation is possible on any trip-zone pin.
• Software-forced tripping is also supported.
• The trip-zone submodule can be fully bypassed if it is not required.
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14.2.8.2 Controlling and Monitoring the Trip-Zone Submodule
The trip-zone submodule operation is controlled and monitored through the following registers:
Table 14-28. Trip-Zone Submodule Registers
Acronym
Register Description
Address Offset
Shadowed
TZSEL
Trip-Zone Select Register
24h
No
TZCTL
Trip-Zone Control Register
28h
No
TZEINT
Trip-Zone Enable Interrupt Register
2Ah
No
TZFLG
Trip-Zone Flag Register
2Ch
No
TZCLR
Trip-Zone Clear Register
2Eh
No
TZFRC
Trip-Zone Force Register
30h
No
14.2.8.3 Operational Highlights for the Trip-Zone Submodule
The following sections describe the operational highlights and configuration options for the trip-zone
submodule.
The trip-zone signals at pin TZ1 to TZn is an active-low input signal. When the pin goes low, it indicates
that a trip event has occurred. Each ePWM module can be individually configured to ignore or use each of
the trip-zone pins. Which trip-zone pins are used by a particular ePWM module is determined by the
TZSEL register for that specific ePWM module. The trip-zone signal may or may not be synchronized to
the system clock (SYSCLKOUT). A minimum of 1 SYSCLKOUT low pulse on the TZ n inputs is sufficient
to trigger a fault condition in the ePWM module. The asynchronous trip makes sure that if clocks are
missing for any reason, the outputs can still be tripped by a valid event present on the TZn inputs.
The TZ n input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for a
ePWM module. The configuration is determined by the TZSEL[CBCn] and TZSEL[OSHTn] bits (where n
corresponds to the trip pin) respectively.
•
•
Cycle-by-Cycle (CBC): When a cycle-by-cycle trip event occurs, the action specified in the TZCTL
register is carried out immediately on the EPWMxA and/or EPWMxB output. Table 14-29 lists the
possible actions. In addition, the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a
EPWMxTZINT interrupt is generated if it is enabled in the TZEINT register.
The specified condition on the pins is automatically cleared when the ePWM time-base counter
reaches zero (TBCNT = 0000h) if the trip event is no longer present. Therefore, in this mode, the trip
event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually
cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the
TZFLG[CBC] bit is cleared, then it will again be immediately set.
One-Shot (OSHT): When a one-shot trip event occurs, the action specified in the TZCTL register is
carried out immediately on the EPWMxA and/or EPWMxB output. Table 14-29 lists the possible
actions. In addition, the one-shot trip event flag (TZFLG[OST]) is set and a EPWMxTZINT interrupt is
generated if it is enabled in the TZEINT register. The one-shot trip condition must be cleared manually
by writing to the TZCLR[OST] bit.
The action taken when a trip event occurs can be configured individually for each of the ePWM output
pins by way of the TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in
Table 14-29, can be taken on a trip event.
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Table 14-29. Possible Actions On a Trip Event
TZCTL[TZA]
and/or
TZCTL[TZB]
EPWMxA
and/or
EPWMxB
Comment
0
High-Impedance
Tripped
1h
Force to High State
Tripped
2h
Force to Low State
Tripped
3h
No Change
Do Nothing. No change is made to the output.
Example 14-2. Trip-Zone Configurations
Scenario A:
A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B
high.
• Configure the ePWM1 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ as a one-shot event source for ePWM2
– TZCTL[TZA] = 1: EPWM2A will be forced high on a trip event.
– TZCTL[TZB] = 1: EPWM2B will be forced high on a trip event.
Scenario B:
A cycle-by-cycle event on TZ5 pulls both EPWM1A, EPWM1B low.
A one-shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state.
• Configure the ePWM1 registers as follows:
– TZSEL[CBC5] = 1: enables TZ5 as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM2
– TZSEL[OSHT6] = 1: enables TZ6 as a one-shot event source for ePWM1
– TZCTL[TZA] = 0: EPWM1A will be put into a high-impedance state on a trip event.
– TZCTL[TZB] = 3: EPWM1B will ignore the trip event.
14.2.8.4 Generating Trip Event Interrupts
Figure 14-37 and Figure 14-38 illustrate the trip-zone submodule control and interrupt logic, respectively.
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Figure 14-37. Trip-Zone Submodule Mode Control Logic
TZCTL[TZB]
TZCTL[TZA]
EPWMxA
EPWMxB
Trip
logic
CTR = 0
Clear
Latch
cyc−by-cyc
mode
(CBC)
TZFRC[CBC]
Trip
EPWMxA
EPWMxB
CBC
trip event
Set
TZ1
Set
Sync
TZFLG[CBC]
TZn
TZCLR[CBC]
Clear
TZSEL[CBC1 to CBCn]
TZCLR[OST]
Clear
Latch
one-shot
mode
(OSHT)
Set
TZFRC[OSHT]
Trip
OSHT
trip event
TZ1
Sync
Async Trip
TZn
TZSEL[OSHT1 to OSHTn]
Set
TZFLG[OST]
Clear
Figure 14-38. Trip-Zone Submodule Interrupt Logic
TZFLG[INT]
TZCLR[INT]
TZFLG[CBC]
Clear
Clear
Latch
TZCLR[CBC]
Latch
Set
Set
TZEINT[CBC]
CBC
trip event
TZFLG[OST]
EPWMxTZINT
(Interrupt controller)
Generate
interrupt
pulse when
input=1
Clear
TZEINT[OST]
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TZCLR[OST]
Latch
Set
OSHT
trip event
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14.2.9 Event-Trigger (ET) Submodule
Figure 14-39 shows the event-trigger (ET) submodule in the ePWM system. The event-trigger submodule
manages the events generated by the time-base submodule and the counter-compare submodule to
generate an interrupt to the CPU.
Figure 14-39. Event-Trigger Submodule
CTR = PRD
CTR = CMPA
Event
Trigger
and
CTR = CMPB
Interrupt
CTR = 0
EPWMxSYNCI
EPWMxSYNCO
CTR = PRD
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR_Dir
CTR = 0
EPWMxINT
(ET)
CTR_Dir
EPWMxA
EPWMA
Dead
Band
(DB)
CTR = CMPA
Counter
Compare
(CC)
CTR = CMPB
PWMchopper
(PC)
Trip
Zone
(TZ)
EPWMxB
EPWMB
CTR = 0
TZ1 to TZn
EPWMxTZINT
14.2.9.1 Purpose of the Event-Trigger Submodule
The key functions of the event-trigger submodule are:
• Receives event inputs generated by the time-base and counter-compare submodules
• Uses the time-base direction information for up/down event qualification
• Uses prescaling logic to issue interrupt requests at:
– Every event
– Every second event
– Every third event
• Provides full visibility of event generation via event counters and flags
14.2.9.2 Controlling and Monitoring the Event-Trigger Submodule
The key registers used to configure the event-trigger submodule are shown in Table 14-30:
Table 14-30. Event-Trigger Submodule Registers
386
Acronym
Register Description
Address Offset
Shadowed
ETSEL
Event-Trigger Selection Register
32h
No
ETPS
Event-Trigger Prescale Register
34h
No
ETFLG
Event-Trigger Flag Register
36h
No
ETCLR
Event-Trigger Clear Register
38h
No
ETFRC
Event-Trigger Force Register
3Ah
No
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14.2.9.3 Operational Overview of the Event-Trigger Submodule
The following sections describe the event-trigger submodule's operational highlights.
Each ePWM module has one interrupt request line connected to the interrupt controller as shown in
Figure 14-40.
Figure 14-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
EPWM1INT
EPWM1
module
EPWM2INT
EPWM2
module
Interrupt
controller
EPWMxINT
EPWMx
module
The event-trigger submodule monitors various event conditions (the left side inputs to event-trigger
submodule shown in Figure 14-41) and can be configured to prescale these events before issuing an
Interrupt request. The event-trigger prescaling logic can issue Interrupt requests at:
• Every event
• Every second event
• Every third event
Figure 14-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
clear
CTR = 0
Event Trigger
Module Logic
CTR = PRD
EPWMxINT
Interrupt
controller
count
CTRU=CMPA
CTR = CMPA
clear
ETSEL reg
CTRD=CMPA
Direction
qualifier
CTR = CMPB
/n
CTRU=CMPB
CTRD=CMPB
/n
ETPS reg
count
ETFLG reg
clear
ETCLR reg
CTR_dir
/n
ETFRC reg
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•
•
•
•
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ETSEL—This selects which of the possible events will trigger an interrupt.
ETPS—This programs the event prescaling options previously mentioned.
ETFLG—These are flag bits indicating status of the selected and prescaled events.
ETCLR—These bits allow you to clear the flag bits in the ETFLG register via software.
ETFRC—These bits allow software forcing of an event. Useful for debugging or software intervention.
A more detailed look at how the various register bits interact with the Interrupt is shown in Figure 14-42.
Figure 14-42 shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD])
bits specify the number of events required to cause an interrupt pulse to be generated. The choices
available are:
• Do not generate an interrupt
• Generate an interrupt on every event
• Generate an interrupt on every second event
• Generate an interrupt on every third event
An interrupt cannot be generated on every fourth or more events.
Which event can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) bits. The
event can be one of the following:
• Time-base counter equal to zero (TBCNT = 0000h).
• Time-base counter equal to period (TBCNT = TBPRD).
• Time-base counter equal to the compare A register (CMPA) when the timer is incrementing.
• Time-base counter equal to the compare A register (CMPA) when the timer is decrementing.
• Time-base counter equal to the compare B register (CMPB) when the timer is incrementing.
• Time-base counter equal to the compare B register (CMPB) when the timer is decrementing.
The number of events that have occurred can be read from the interrupt event counter (ETPS[INTCNT])
register bits. That is, when the specified event occurs the ETPS[INTCNT] bits are incremented until they
reach the value specified by ETPS[INTPRD]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops
counting and its output is set. The counter is only cleared when an interrupt is sent to the interrupt
controller.
When ETPS[INTCNT] reaches ETPS[INTPRD], one of the following behaviors will occur:
• If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an
interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is
cleared ETPS[INTCNT] = 0. The counter will begin counting events again.
• If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter
stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
• If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high
until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.
Writing to the INTPRD bits will automatically clear the counter INTCNT = 0 and the counter output will be
reset (so no interrupts are generated). Writing a 1 to the ETFRC[INT] bit will increment the event counter
INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the
counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored.
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Figure 14-42. Event-Trigger Interrupt Generator
ETCLR[INT]
Clear
Set
Latch
ETFLG[INT]
ETPS[INTCNT]
EPWMxINT
Generate
interrupt
pulse
when
input = 1
1
ETSEL[INTSEL]
0
Clear CNT
2-bit
Counter
0
ETFRC[INT]
Inc CNT
ETSEL[INT]
ETPS[INTPRD]
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000
001
010
011
100
101
101
111
0
CTR=0
CTR=PRD
0
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
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14.2.10 High-Resolution PWM (HRPWM) Submodule
Figure 14-43 shows the high-resolution PWM (HRPWM) submodule in the ePWM system. Some devices
include the high-resolution PWM submodule, see your device-specific data manual to determine which
ePWM instances include this feature.
Figure 14-43. HRPWM System Interface
Time−base (TB)
Sync
in/out
select
Mux
CTR = 0
CTR = CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR = PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR = 0
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
CTR = PRD
CTR = 0
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
control
Counter compare (CC)
CTR = CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxA
CMPA shadow (24)
Dead
band
(DB)
CTR = CMPB
16
PWM
chopper
(PC)
EPWMB
EPWMxB
CMPB active (16)
EPWMxTZINT
CMPB shadow (16)
390
Trip
zone
(TZ)
CTR = 0
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TZ1 to TZn
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14.2.10.1 Purpose of the High-Resolution PWM Submodule
The enhanced high-resolution pulse-width modulator (eHRPWM) extends the time resolution capabilities
of the conventionally derived digital pulse-width modulator (PWM). HRPWM is typically used when PWM
resolution falls below ~9-10 bits. The key features of HRPWM are:
• Extended time resolution capability
• Used in both duty cycle and phase-shift control methods
• Finer time granularity control or edge positioning using extensions to the Compare A and Phase
registers
• Implemented using the A signal path of PWM, that is, on the EPWMxA output. EPWMxB output has
conventional PWM capabilities
The ePWM peripheral is used to perform a function that is mathematically equivalent to a digital-to-analog
converter (DAC). As shown in Figure 14-44, the effective resolution for conventionally generated PWM is
a function of PWM frequency (or period) and system clock frequency.
Figure 14-44. Resolution Calculations for Conventionally Generated PWM
TPWM
PWM resolution (%) = FPWM/FSYSCLKOUT x 100%
PWM resolution (bits) = Log2 (FPWM/FSYSCLKOUT)
PWM
t
TSYSCLK
If the required PWM operating frequency does not offer sufficient resolution in PWM mode, you may want
to consider HRPWM. As an example of improved performance offered by HRPWM, Table 14-31 shows
resolution in bits for various PWM frequencies. Table 14-31 values assume a MEP step size of 180 ps.
See your device-specific data manual for typical and maximum performance specifications for the MEP.
Table 14-31. Resolution for PWM and HRPWM
Regular Resolution (PWM)
High Resolution (HRPWM)
PWM Frequency (kHz)
Bits
%
Bits
%
20
12.3
0.0
18.1
0.000
50
11.0
0.0
16.8
0.001
100
10.0
0.1
15.8
0.002
150
9.4
0.2
15.2
0.003
200
9.0
0.2
14.8
0.004
250
8.6
0.3
14.4
0.005
500
7.6
0.5
13.8
0.007
1000
6.6
1.0
12.4
0.018
1500
6.1
1.5
11.9
0.027
2000
5.6
2.0
11.4
0.036
Although each application may differ, typical low-frequency PWM operation (below 250 kHz) may not
require HRPWM. HRPWM capability is most useful for high-frequency PWM requirements of power
conversion topologies such as:
• Single-phase buck, boost, and flyback
• Multi-phase buck, boost, and flyback
• Phase-shifted full bridge
• Direct modulation of D-Class power amplifiers
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14.2.10.2 Architecture of the High-Resolution PWM Submodule
The HRPWM is based on micro edge positioner (MEP) technology. MEP logic is capable of positioning an
edge very finely by sub-dividing one coarse system clock of a conventional PWM generator. The time step
accuracy is on the order of 150 ps. The HRPWM also has a self-check software diagnostics mode to
check if the MEP logic is running optimally, under all operating conditions.
Figure 14-45 shows the relationship between one coarse system clock and edge position in terms of MEP
steps, which are controlled via an 8-bit field in the Compare A extension register (CMPAHR).
Figure 14-45. Operating Logic Using MEP
PWM period (N CPU cycles)
PWM duty
(0 to 1.0 in Q15 format)
MEP scale factor
Number of MEP steps
in one coarse step
Coarse step size
MEP step
Number of coarse steps = integer(PWMduty * PWMperiod)
Number of MEP steps
= fraction(PWMduty * PWMperiod) * (MEPScaleFactor)
16−bit CMPA register value
= number of coarse steps
16−bit CMPAHR register value = (number of MEP steps) << 8 + 0x180 (rounding) (A)
A
For MEP range and rounding adjustment.
To generate an HRPWM waveform, configure the TBM, CCM, and AQM registers as you would to
generate a conventional PWM of a given frequency and polarity. The HRPWM works together with the
TBM, CCM, and AQM registers to extend edge resolution, and should be configured accordingly. Although
many programming combinations are possible, only a few are needed and practical.
14.2.10.3 Controlling and Monitoring the High-Resolution PWM Submodule
The MEP of the HRPWM is controlled by two extension registers, each 8-bits wide. These two HRPWM
registers are concatenated with the 16-bit TBPHS and CMPA registers used to control PWM operation.
• TBPHSHR - Time-Base Phase High-Resolution Register
• CMPAHR - Counter-Compare A High-Resolution Register
Table 14-32 lists the registers used to control and monitor the high-resolution PWM submodule.
Table 14-32. HRPWM Submodule Registers
392
Acronym
Register Description
TBPHSHR
Extension Register for HRPWM Phase
CMPAHR
Extension Register for HRPWM Duty
HRCNFG
HRPWM Configuration Register
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Address Offset
Shadowed
4h
No
10h
Yes
1040h
No
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14.2.10.4 Configuring the High-Resolution PWM Submodule
Once the ePWM has been configured to provide conventional PWM of a given frequency and polarity, the
HRPWM is configured by programming the HRCNFG register located at offset address 1040h. This
register provides configuration options for the following key operating modes:
• Edge Mode: The MEP can be programmed to provide precise position control on the rising edge (RE),
falling edge (FE), or both edges (BE) at the same time. FE and RE are used for power topologies
requiring duty cycle control, while BE is used for topologies requiring phase shifting, for example,
phase shifted full bridge.
• Control Mode: The MEP is programmed to be controlled either from the CMPAHR register (duty cycle
control) or the TBPHSHR register (phase control). RE or FE control mode should be used with
CMPAHR register. BE control mode should be used with TBPHSHR register.
• Shadow Mode: This mode provides the same shadowing (double buffering) option as in regular PWM
mode. This option is valid only when operating from the CMPAHR register and should be chosen to be
the same as the regular load option for the CMPA register. If TBPHSHR is used, then this option has
no effect.
14.2.10.5 Operational Highlights for the High-Resolution PWM Submodule
The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps, each of which has
a time resolution on the order of 150 ps. The MEP works with the TBM and CCM registers to be certain
that time steps are optimally applied and that edge placement accuracy is maintained over a wide range of
PWM frequencies, system clock frequencies and other operating conditions. Table 14-33 shows the
typical range of operating frequencies supported by the HRPWM.
Table 14-33. Relationship Between MEP Steps, PWM Frequency and Resolution
System
(MHz)
(1)
(2)
(3)
(4)
(5)
MEP Steps Per
SYSCLKOUT (1) (2)
(3)
PWM Minimum
(Hz) (4)
PWM Maximum
(MHz)
Resolution at
Maximum
(Bits) (5)
50.0
111
763
2.50
11.1
60.0
93
916
3.00
10.9
70.0
79
1068
3.50
10.6
80.0
69
1221
4.00
10.4
90.0
62
1373
4.50
10.3
100.0
56
1526
5.00
10.1
System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT
Table data based on a MEP time resolution of 180 ps (this is an example value)
MEP steps applied = TSYSCLKOUT/180 ps in this example.
PWM minimum frequency is based on a maximum period value, TBPRD = 65 535. PWM mode is asymmetrical up-count.
Resolution in bits is given for the maximum PWM frequency stated.
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14.2.10.5.1 Edge Positioning
In a typical power control loop (switch modes, digital motor control (DMC), uninterruptible power supply
(UPS)), a digital controller (PID, 2pole/2zero, lag/lead, etc.) issues a duty command, usually expressed in
a per unit or percentage terms.
In the following example, assume that for a particular operating point, the demanded duty cycle is 0.405 or
40.5% on-time and the required converter PWM frequency is 1.25 MHz. In conventional PWM generation
with a system clock of 100 MHz, the duty cycle choices are in the vicinity of 40.5%. In Figure 14-46, a
compare value of 32 counts (duty = 40%) is the closest to 40.5% that you can attain. This is equivalent to
an edge position of 320 ns instead of the desired 324 ns. This data is shown in Table 14-34.
By utilizing the MEP, you can achieve an edge position much closer to the desired point of 324 ns.
Table 14-34 shows that in addition to the CMPA value, 22 steps of the MEP (CMPAHR register) will
position the edge at 323.96 ns, resulting in almost zero error. In this example, it is assumed that the MEP
has a step resolution of 180 ns.
Figure 14-46. Required PWM Waveform for a Requested Duty = 40.5%
Tpwm = 800 ns
324 ns
Demanded
duty (40.5%)
10 ns steps
0
30 31 32 33 34
79
EPWM1A
37.5%
40.0%
38.8%
42.5%
41.3%
Table 14-34. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)
CMPA
(count) (1) (2)
DUTY
(%)
High Time
(ns)
CMPA
(count)
CMPAHR
(count)
Duty
(%)
High Time
(ns)
28
35.0
280
32
18
40.405
323.24
29
36.3
290
32
19
40.428
323.42
30
37.5
300
32
20
40.450
323.60
31
38.8
310
32
21
40.473
323.78
32
40.0
320
32
22
40.495
323.96
33
41.3
330
32
23
40.518
324.14
34
42.5
340
32
24
40.540
324.32
32
25
40.563
324.50
32
26
40.585
324.68
32
27
40.608
324.86
(3)
Required
32.40
(1)
(2)
(3)
394
40.5
324
System clock, SYSCLKOUT and TBCLK = 100 MHz, 10 ns
For a PWM Period register value of 80 counts, PWM Period = 80 × 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz
Assumed MEP step size for the above example = 180 ps
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14.2.10.5.2 Scaling Considerations
The mechanics of how to position an edge precisely in time has been demonstrated using the resources
of the standard (CMPA) and MEP (CMPAHR) registers. In a practical application, however, it is necessary
to seamlessly provide the CPU a mapping function from a per-unit (fractional) duty cycle to a final integer
(non-fractional) representation that is written to the [CMPA:CMPAHR] register combination.
To do this, first examine the scaling or mapping steps involved. It is common in control software to
express duty cycle in a per-unit or percentage basis. This has the advantage of performing all needed
math calculations without concern for the final absolute duty cycle, expressed in clock counts or high time
in ns. Furthermore, it makes the code more transportable across multiple converter types running different
PWM frequencies.
To implement the mapping scheme, a two-step scaling procedure is required.
Assumptions for this example:
System clock, SYSCLKOUT
PWM frequency
Required PWM duty cycle, PWMDuty
PWM period in terms of coarse steps,
PWMperiod (800 ns/10 ns)
Number of MEP steps per coarse step at
180 ps (10 ns/180 ps), MEP_SF
Value to keep CMPAHR within the range
of 1-255 and fractional rounding constant
(default value)
=
=
=
=
10 ns (100 MHz)
1.25 MHz (1/800 ns)
0.405 (40.5%)
80
= 55
= 180h
Step 1: Percentage Integer Duty value conversion for CMPA register
CMPA register value
=
=
=
=
CMPA register value
int(PWMDuty × PWMperiod); int means integer part
int(0.405 × 80)
int(32.4)
32 (20h)
Step 2: Fractional value conversion for CMPAHR register
CMPAHR register value
= (frac(PWMDuty × PWMperiod) × MEP_SF) << 8) +
180h; frac means fractional part
= (frac(32.4) × 55 <<8) + 180h; Shift is to move the
value as CMPAHR high byte
= ((0.4 × 55) <<8) + 180h
= (22 <<8) + 180h
= 22 × 256 + 180h ; Shifting left by 8 is the same
multiplying by 256.
= 5632 + 180h
= 1600h + 180h
= 1780h; CMPAHR value = 1700h, lower 8 bits will be
ignored by hardware.
CMPAHR value
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14.2.10.5.3 Duty Cycle Range Limitation
In high resolution mode, the MEP is not active for 100% of the PWM period. It becomes operational
3 SYSCLK cycles after the period starts.
Duty cycle range limitations are illustrated in Figure 14-47. This limitation imposes a lower duty cycle limit
on the MEP. For example, precision edge control is not available all the way down to 0% duty cycle.
Although for the first 3 or 6 cycles, the HRPWM capabilities are not available, regular PWM duty control is
still fully operational down to 0% duty. In most applications this should not be an issue as the controller
regulation point is usually not designed to be close to 0% duty cycle.
Figure 14-47. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
TPWM
0
3
6
100
EPWM1A
If the application demands HRPWM operation in the low percent duty cycle region, then the HRPWM can
be configured to operate in count-down mode with the rising edge position (REP) controlled by the MEP.
This is illustrated in Figure 14-48. In this case low percent duty limitation is no longer an issue.
Figure 14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
Tpwm
0
3
100
6
EPWM1A
396
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14.3 Applications to Power Topologies
An ePWM module has all the local resources necessary to operate completely as a standalone module or
to operate in synchronization with other identical ePWM modules.
14.3.1 Overview of Multiple Modules
Previously in this user's guide, all discussions have described the operation of a single module. To
facilitate the understanding of multiple modules working together in a system, the ePWM module
described in reference is represented by the more simplified block diagram shown in Figure 14-49. This
simplified ePWM block shows only the key resources needed to explain how a multiswitch power topology
is controlled with multiple ePWM modules working together.
Figure 14-49. Simplified ePWM Module
SyncIn
Phase reg
EN
EPWMxA
Φ=0°
EPWMxB
CTR = 0
CTR=CMPB
X
SyncOut
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14.3.2 Key Configuration Capabilities
The key configuration choices available to each module are as follows:
• Options for SyncIn
– Load own counter with phase register on an incoming sync strobe—enable (EN) switch closed
– Do nothing or ignore incoming sync strobe—enable switch open
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to
CTR = CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
• Options for SyncOut
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to
CTR = CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
For each choice of SyncOut, a module may also choose to load its own counter with a new phase value
on a SyncIn strobe input or choose to ignore it, i.e., via the enable switch. Although various combinations
are possible, the two most common—master module and slave module modes—are shown in Figure 1450.
Figure 14-50. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
Ext SyncIn
(optional)
Master
Slave
Phase reg
SyncIn
Phase reg EN
Φ=0°
EN
398
EPWM2A
Φ=0°
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
SyncIn
2
SyncOut
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
EPWM2B
CTR=0
CTR=CMPB
X
SyncOut
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14.3.3 Controlling Multiple Buck Converters With Independent Frequencies
One of the simplest power converter topologies is the buck. A single ePWM module configured as a
master can control two buck stages with the same PWM frequency. If independent frequency control is
required for each buck converter, then one ePWM module must be allocated for each converter stage.
Figure 14-51 shows four buck stages, each running at independent frequencies. In this case, all four
ePWM modules are configured as Masters and no synchronization is used. Figure 14-52 shows the
waveforms generated by the setup shown in Figure 14-51; note that only three waveforms are shown,
although there are four stages.
Figure 14-51. Control of Four Buck Stages. (Note: FPWM1≠ FPWM2≠ FPWM3≠ FPWM4)
Ext SyncIn
(optional)
Master1
Phase reg
SyncIn
En
Vin1
Φ=X
Vout1
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
Buck #1
EPWM1A
SyncOut
Master2
Phase reg
SyncIn
Vin2
Vout2
En
EPWM2A
Φ=X
2
Buck #2
EPWM2B
CTR=0
CTR=CMPB
X
EPWM2A
SyncOut
Master3
Phase reg
SyncIn
Vin3
En
Vout3
EPWM3A
Φ=X
3
Buck #3
EPWM3B
CTR=0
CTR=CMPB
X
EPWM3A
SyncOut
Master4
Phase reg
Vin4
SyncIn
Vout4
En
EPWM4A
Φ=X
EPWM4B
CTR=0
CTR=CMPB
X
3
Buck #4
EPWM4A
SyncOut
NOTE: Θ = X indicates value in phase register is a "don't care"
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Figure 14-52. Buck Waveforms for Figure 14-51 (Note: Only three bucks shown here)
P
I
P
I
700
P
P
I
1200
CA
P
CA
P
EPWM1A
700
P
1400
CA
P
CA
EPWM2A
500
CA
P
CA
800
P
CA
P
EPWM3A
P
I
Indicates this event triggers an interrupt
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Table 14-35. EPWM1 Initialization for Figure 14-52
Register
Bit
Value
Comments
TBPRD
TBPRD
1200 (4B0h)
Period = 1201 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
CMPCTL
AQCTLA
Phase loading disabled
Table 14-36. EPWM2 Initialization for Figure 14-52
Register
Bit
Value
Comments
TBPRD
TBPRD
1400 (578h)
Period = 1401 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
CMPCTL
AQCTLA
Phase loading disabled
Table 14-37. EPWM3 Initialization for Figure 14-52
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 801 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_DISABLE
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
PRD
AQ_CLEAR
CAU
AQ_SET
CMPCTL
AQCTLA
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Example 14-3. Configuration for Example in Figure 14-52
// Run Time (Note: Example execution of one run-time instance)
//=========================================================
EPwm1Regs.CMPA.half.CMPA = 700;
// adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 700;
// adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 500;
// adjust duty for output EPWM3A
14.3.4 Controlling Multiple Buck Converters With Same Frequencies
If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at
integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules
remain locked. Figure 14-53 shows such a configuration; Figure 14-54 shows the waveforms generated by
the configuration.
Figure 14-53. Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1)
Vin1
Buck #1
Ext SyncIn
(optional)
Master
Phase reg
Vout1
EPWM1A
SyncIn
En
EPWM1A
Φ=0°
Vin2
Vout2
EPWM1B
CTR=0
CTR=CMPB
Buck #2
EPWM1B
X
SyncOut
Vin3
Vout3
Buck #3
Slave
Phase reg
EPWM2A
SyncIn
En
EPWM2A
Φ=X
EPWM2B
CTR=0
CTR=CMPB
X
Vout4
Buck #4
SyncOut
402
Vin4
EPWM2B
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Figure 14-54. Buck Waveforms for Figure 14-53 (Note: FPWM2 = FPWM1)
600
Z
I
400
Z
I
Z
I
400
200
200
CA
P
A
CA
CA
P
A
CA
EPWM1A
CB
CB
CB
CB
EPWM1B
500
500
300
300
CA
CA
CA
CA
EPWM2A
CB
CB
CB
CB
EPWM2B
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Table 14-38. EPWM1 Initialization for Figure 14-53
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM1A
CAD
AQ_CLEAR
CBU
AQ_SET
CBD
AQ_CLEAR
CMPCTL
AQCTLA
AQCTLB
Phase loading disabled
Sync down-stream module
Set actions for EPWM1B
Table 14-39. EPWM2 Initialization for Figure 14-53
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM2A
CAD
AQ_CLEAR
CBU
AQ_SET
CBD
AQ_CLEAR
CMPCTL
AQCTLA
AQCTLB
Phase loading enabled
Sync flow-through
Set actions for EPWM2B
Example 14-4. Code Snippet for Configuration in Figure 14-53
// Run Time (Note: Example execution of one run-time instance)
//===========================================================
EPwm1Regs.CMPA.half.CMPA = 400;
// adjust duty for output
EPwm1Regs.CMPB = 200;
// adjust duty for output
EPwm2Regs.CMPA.half.CMPA = 500;
// adjust duty for output
EPwm2Regs.CMPB = 300;
// adjust duty for output
404
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EPWM1A
EPWM1B
EPWM2A
EPWM2B
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14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
Topologies that require control of multiple switching elements can also be addressed with these same
ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control
can be extended to multiple stages. Figure 14-55 shows control of two synchronized Half-H bridge stages
where stage 2 can operate at integer multiple (N) frequencies of stage 1. Figure 14-56 shows the
waveforms generated by the configuration shown in Figure 14-55.
Module 2 (slave) is configured for Sync flow-through; if required, this configuration allows for a third Half-H
bridge to be controlled by PWM module 3 and also, most importantly, to remain in synchronization with
master module 1.
Figure 14-55. Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1)
VDC_bus
Ext SyncIn
(optional)
Master
Phase reg
En
Φ=0°
SyncIn
EPWM1A
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
EPWM1B
SyncOut
Slave
Phase reg
En
Φ=0°
Vout1
SyncIn
VDC_bus
EPWM2A
Vout2
EPWM2B
CTR=0
CTR=CMPB
X
EPWM2A
SyncOut
EPWM2B
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Figure 14-56. Half-H Bridge Waveforms for Figure 14-55 (Note: FPWM2 = FPWM1)
Z
I
Z
I
600
400
400
200
200
Z
CB
A
Z
I
Z
CA
CB
A
CA
EPWM1A
CA
CB
A
Z
CA
CB
A
Z
CA
CB
A
Z
EPWM1B
Pulse Center
500
500
250
Z
CB
A
250
CA
Z
CB
A
CA
EPWM2A
CA
CB
A
Z
EPWM2B
Pulse Center
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Table 14-40. EPWM1 Initialization for Figure 14-55
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM1A
CAU
AQ_CLEAR
ZRO
AQ_CLEAR
CAD
AQ_SET
CMPCTL
AQCTLA
AQCTLB
Phase loading disabled
Sync down-stream module
Set actions for EPWM1B
Table 14-41. EPWM2 Initialization for Figure 14-55
Register
Bit
Value
Comments
TBPRD
TBPRD
600 (258h)
Period = 1200 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM2A
CAU
AQ_CLEAR
ZRO
AQ_CLEAR
CAD
AQ_SET
CMPCTL
AQCTLA
AQCTLB
Phase loading enabled
Sync flow-through
Set actions for EPWM2B
Example 14-5. Code Snippet for Configuration in Figure 14-55
// Run Time (Note: Example execution of one run-time instance)
//===========================================================
EPwm1Regs.CMPA.half.CMPA = 400; // adjust duty for output
EPwm1Regs.CMPB = 200;
// adjust duty for output
EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output
EPwm2Regs.CMPB = 250;
// adjust duty for output
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EPWM1B
EPWM2A
EPWM2B
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14.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
The idea of multiple modules controlling a single power stage can be extended to the 3-phase Inverter
case. In such a case, six switching elements can be controlled using three PWM modules, one for each
leg of the inverter. Each leg must switch at the same frequency and all legs must be synchronized. A
master + two slaves configuration can easily address this requirement. Figure 14-57 shows how six PWM
modules can control two independent 3-phase Inverters; each running a motor.
As in the cases shown in the previous sections, we have a choice of running each inverter at a different
frequency (module 1 and module 4 are masters as in Figure 14-57), or both inverters can be synchronized
by using one master (module 1) and five slaves. In this case, the frequency of modules 4, 5, and 6 (all
equal) can be integer multiples of the frequency for modules 1, 2, 3 (also all equal).
Figure 14-57. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
Ext SyncIn
(optional)
Master
Phase reg
En
SyncIn
EPWM1A
Φ=0°
CTR=0
CTR=CMPB
X
1
SyncOut
Slave
Phase reg
En
EPWM1B
EPWM1A
SyncIn
EPWM2A
Φ=0°
CTR=0
CTR=CMPB
X
2
SyncOut
Slave
Phase reg
En
EPWM2A
EPWM3A
VAB
VCD
EPWM2B
VEF
EPWM1B
EPWM2B
EPWM3B
3 phase motor
SyncIn
Φ=0°
EPWM3A
CTR=0
CTR=CMPB
X
3
SyncOut
3 phase inverter #1
EPWM3B
Slave
Phase reg
SyncIn
En
Φ=0°
EPWM4A
CTR=0
CTR=CMPB
X
4
SyncOut
Slave
Phase reg
En
EPWM4B
EPWM4A
SyncIn
Φ=0°
VEF
EPWM4B
X
EPWM5B
EPWM6B
SyncOut
3 phase motor
SyncIn
Φ=0°
CTR=0
CTR=CMPB
X
6
SyncOut
408
VCD
EPWM5B
CTR=0
Slave
Phase reg
En
EPWM6A
VAB
EPWM5A
CTR=CMPB
5
EPWM5A
EPWM6A
3 phase inverter #2
EPWM6B
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Figure 14-58. 3-Phase Inverter Waveforms for Figure 14-57 (Only One Inverter Shown)
Z
I
Z
I
800
500
500
CA
CA
P
A
EPWM1A
CA
CA
P
A
RED
RED
EPWM1B
FED
FED
Φ2=0
600
600
CA
CA
CA
CA
EPWM2A
RED
EPWM2B
FED
700
700
Φ3=0
CA
EPWM3A
CA
CA
CA
RED
EPWM3B
FED
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Table 14-42. EPWM1 Initialization for Figure 14-57
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 1600 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM1A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
50
RED = 50 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Phase loading disabled
Sync down-stream module
Table 14-43. EPWM2 Initialization for Figure 14-57
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 1600 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM2A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
50
RED = 50 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
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Sync flow-through
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Table 14-44. EPWM3 Initialization for Figure 14-57
Register
Bit
Value
Comments
TBPRD
TBPRD
800 (320h)
Period = 1600 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM3A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
50
RED = 50 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Slave module
Sync flow-through
Example 14-6. Code Snippet for Configuration in Figure 14-57
// Run Time (Note: Example execution of one run-time instance)
//=========================================================
EPwm1Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A
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14.3.7 Practical Applications Using Phase Control Between PWM Modules
So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero
or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple
PWM modules can address another class of power topologies that rely on phase relationship between
legs (or stages) for correct operation. As described in the TB module section, a PWM module can be
configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCNT register. To
illustrate this concept, Figure 14-59 shows a master and slave module with a phase relationship of 120°,
that is, the slave leads the master.
Figure 14-59. Configuring Two PWM Modules for Phase Control
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
En
EPWM1A
Φ=0°
EPWM1B
CTR=0
CTR=CMPB
X
1
SyncOut
Slave
Phase reg
SyncIn
En
EPWM2A
Φ=120°
EPWM2B
CTR=0
CTR=CMPB
X
2
SyncOut
Figure 14-60 shows the associated timing waveforms for this configuration. Here, TBPRD = 600 for both
master and slave. For the slave, TBPHS = 200 (200/600 × 360° = 120°). Whenever the master generates
a SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCNT register so the
slave time-base is always leading the master's time-base by 120°.
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Figure 14-60. Timing Waveforms Associated With Phase Control Between 2 Modules
FFFFh
TBCNT
Master Module
600
600
TBPRD
0000h
CTR = PRD
(SycnOut)
FFFFh
time
TBCNT
Phase = 120°
Φ2
Slave Module
TBPRD
600
600
200
200
TBPHS
0000h
SyncIn
time
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter
A popular power topology that makes use of phase-offset between modules is shown in Figure 14-61. This
system uses three PWM modules, with module 1 configured as the master. To work, the phase
relationship between adjacent modules must be F = 120°. This is achieved by setting the slave TBPHS
registers 2 and 3 with values of 1/3 and 2/3 of the period value, respectively. For example, if the period
register is loaded with a value of 600 counts, then TBPHS (slave 2) = 200 and TBPHS (slave 3) = 400.
Both slave modules are synchronized to the master 1 module.
This concept can be extended to four or more phases, by setting the TBPHS values appropriately. The
following formula gives the TBPHS values for N phases:
TBPHS(N,M) = (TBPRD/N) × (M - 1)
Where:
N = number of phases
M = PWM module number
For example, for the 3-phase case (N = 3), TBPRD = 600,
TBPHS(3,2) = (600/3) × (2 - 1) = 200 × 1 = 200 (Phase value for Slave module 2)
TBPHS(3,3) = (600/3) × (3 - 1) = 200 × 2 = 400 (Phase value for Slave module 3)
Figure 14-62 shows the waveforms for the configuration in Figure 14-61.
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Figure 14-61. Control of a 3-Phase Interleaved DC/DC Converter
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
VIN
En
Φ=0°
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
EPWM1A
EPWM2A
EPWM3A
EPWM1B
EPWM2B
EPWM3B
SyncOut
Slave
Phase reg
SyncIn
VOUT
En
EPWM2A
Φ=120°
EPWM2B
CTR=0
CTR=CMPB
X
2
SyncOut
Slave
Phase reg
SyncIn
En
EPWM3A
Φ=240°
EPWM3B
CTR=0
CTR=CMPB
X
3
414
SyncOut
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Figure 14-62. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 14-61
Z
I
285
CA
EPWM1A
285
P
A
CA
CA
RED
P
A
FED
Z
I
CA
CA
RED
EPWM1B
300
Z
I
Z
I
450
P
A
CA
RED
FED
FED
Φ2=120°
TBPHS
(=300)
EPWM2A
EPWM2B
300
Φ2=120°
TBPHS
(=300)
EPWM3A
EPWM3B
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Table 14-45. EPWM1 Initialization for Figure 14-61
Register
Bit
Value
Comments
TBPRD
TBPRD
450 (1C2h)
Period = 900 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_CTR_ZERO
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM1A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
20
FED = 20 TBCLKs
DBRED
20
RED = 20 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Phase loading disabled
Sync down-stream module
Table 14-46. EPWM2 Initialization for Figure 14-61
Register
Bit
Value
Comments
TBPRD
TBPRD
450 (1C2h)
Period = 900 TBCLK counts
TBPHS
TBPHS
300
Phase = (300/900) × 360 = 120°
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
Sync flow-through
PHSDIR
TB_DOWN
Count DOWN on sync
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM2A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
20
FED = 20 TBCLKs
DBRED
20
RED = 20 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
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Table 14-47. EPWM3 Initialization for Figure 14-61
Register
Bit
Value
Comments
TBPRD
TBPRD
450 (1C2h)
Period = 900 TBCLK counts
TBPHS
TBPHS
300
Phase = (300/900) × 360 = 120°
TBCTL
CTRMODE
TB_UPDOWN
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
Sync flow-through
PHSDIR
TB_UP
Count UP on sync
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
CAU
AQ_SET
Set actions for EPWM3A
CAD
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
20
FED = 20 TBCLKs
DBRED
20
RED = 20 TBCLKs
CMPCTL
AQCTLA
DBCTL
DBFED
Slave module
Example 14-7. Code Snippet for Configuration in Figure 14-61
// Run Time (Note: Example execution of one run-time instance)
//===========================================================
EPwm1Regs.CMPA.half.CMPA = 285;
// adjust duty for output EPWM1A
EPwm2Regs.CMPA.half.CMPA = 285;
// adjust duty for output EPWM2A
EPwm3Regs.CMPA.half.CMPA = 285;
// adjust duty for output EPWM3A
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14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
The example given in Figure 14-63 assumes a static or constant phase relationship between legs
(modules). In such a case, control is achieved by modulating the duty cycle. It is also possible to
dynamically change the phase value on a cycle-by-cycle basis. This feature lends itself to controlling a
class of power topologies known as phase-shifted full bridge, or zero voltage switched full bridge. Here the
controlled parameter is not duty cycle (this is kept constant at approximately 50 percent); instead it is the
phase relationship between legs. Such a system can be implemented by allocating the resources of two
PWM modules to control a single power stage, which in turn requires control of four switching elements.
Figure 14-64 shows a master/slave module combination synchronized together to control a full H-bridge.
In this case, both master and slave modules are required to switch at the same PWM frequency. The
phase is controlled by using the slave's phase register (TBPHS). The master's phase register is not used
and therefore can be initialized to zero.
Figure 14-63. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1 )
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
En
Φ=0°
EPWM1A
CTR=0
CTR=CMPB
X
EPWM1B
Slave
Phase reg
SyncOut
Vout
VDC_bus
EPWM1A
EPWM2A
EPWM1B
EPWM2B
SyncIn
En
EPWM2A
Φ=Var°
CTR=0
CTR=CMPB
X
EPWM2B
SyncOut
Var = Variable
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Figure 14-64. ZVS Full-H Bridge Waveforms
Z
I
Z
I
Z
I
1200
600
200
Z
CB
A
CA
Z
CB
A
CA
Z
RED
ZVS transition
EPWM1A
Power phase
FED
ZVS transition
EPWM1B
300
TBPHS
=(1200−Φ2)
Φ2=variable
CB
A
Z
CA
CB
A
Z
Z
CA
RED
EPWM2A
EPWM2B
FED
Power phase
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Table 14-48. EPWM1 Initialization for Figure 14-63
Register
Bit
Value
Comments
TBPRD
TBPRD
1200 (4B0h)
Period = 1201 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_DISABLE
PRDLD
TB_SHADOW
Phase loading disabled
SYNCOSEL
TB_CTR_ZERO
Sync down-stream module
CMPA
CMPA
600 (258h)
Set 50% duty for EPWM1A
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM1A
CAU
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
50
FED = 50 TBCLKs
DBRED
70
RED = 70 TBCLKs
AQCTLA
DBCTL
DBFED
Table 14-49. EPWM2 Initialization for Figure 14-63
Register
Bit
Value
Comments
TBPRD
TBPRD
1200 (4B0h)
Period = 1201 TBCLK counts
TBPHS
TBPHS
0
Clear Phase Register to 0
TBCTL
CTRMODE
TB_UP
PHSEN
TB_ENABLE
PRDLD
TB_SHADOW
SYNCOSEL
TB_SYNC_IN
Sync flow-through
CMPA
CMPA
600 (258h)
Set 50% duty for EPWM2A
CMPCTL
SHDWAMODE
CC_SHADOW
SHDWBMODE
CC_SHADOW
LOADAMODE
CC_CTR_ZERO
Load on CTR = 0
LOADBMODE
CC_CTR_ZERO
Load on CTR = 0
ZRO
AQ_SET
Set actions for EPWM2A
CAU
AQ_CLEAR
MODE
DB_FULL_ENABLE
Enable Dead-band module
POLSEL
DB_ACTV_HIC
Active Hi complementary
DBFED
30
FED = 30 TBCLKs
DBRED
40
RED = 40 TBCLKs
AQCTLA
DBCTL
DBFED
Slave module
Example 14-8. Code Snippet for Configuration in Figure 14-63
// Run Time (Note: Example execution of one run-time instance)
//============================================================
EPwm2Regs.TBPHS = 1200-300;
// Set Phase reg to 300/1200 * 360 = 90 deg
EPwm1Regs.DBFED = FED1_NewValue;
// Update ZVS transition interval
EPwm1Regs.DBRED = RED1_NewValue;
// Update ZVS transition interval
EPwm2Regs.DBFED = FED2_NewValue;
// Update ZVS transition interval
EPwm2Regs.DBRED = RED2_NewValue;
// Update ZVS transition interval
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14.4 Registers
This section includes the registers for the submodules.
Table 14-50. Submodule Registers
Submodule
Section
Time-Base Submodule Registers
Section 14.4.1
Counter-Compare Submodule Registers
Section 14.4.2
Action-Qualifier Submodule Registers
Section 14.4.3
Dead-Band Generator Submodule Registers
Section 14.4.4
PWM-Chopper Submodule Registers
Section 14.4.5
Trip-Zone Submodule Registers
Section 14.4.6
Event-Trigger Submodule Registers
Section 14.4.7
High-Resolution PWM Registers
Section 14.4.8
14.4.1 Time-Base Submodule Registers
Table 14-51 lists the memory-mapped registers for the time-base submodule. See your device-specific
data manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-51 should be considered as reserved locations and the register contents should not be modified.
Table 14-51. Time-Base Submodule Registers
Offset
(1)
Acronym
Register Description
Section
0h
TBCTL
Time-Base Control Register
Section 14.4.1.1
2h
TBSTS
Time-Base Status Register
Section 14.4.1.2
4h
TBPHSHR
Time-Base Phase High-Resolution Register (1)
Section 14.4.8.1
6h
TBPHS
Time-Base Phase Register
Section 14.4.1.3
8h
TBCNT
Time-Base Counter Register
Section 14.4.1.4
Ah
TBPRD
Time-Base Period Register
Section 14.4.1.5
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved. See your device-specific data manual to determine which instances include the HRPWM.
14.4.1.1 Time-Base Control Register (TBCTL)
The time-base control register (TBCTL) is shown in Figure 14-65 and described in Table 14-52.
Figure 14-65. Time-Base Control Register (TBCTL)
15
14
13
12
10
9
8
FREE, SOFT
PHSDIR
CLKDIV
HSPCLKDIV
R/W-0
R/W-0
R/W-0
R/W-0
7
6
HSPCLKDIV
SWFSYNC
R/W-1
R/W-0
5
4
3
2
1
0
SYNCOSEL
PRDLD
PHSEN
CTRMODE
R/W-0
R/W-0
R/W-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 14-52. Time-Base Control Register (TBCTL) Field Descriptions
Bit
15-14
Field
FREE, SOFT
Value
0-3h
Description
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
0
Stop after the next time-base counter increment or decrement
1h
Stop when counter completes a whole cycle:
• Up-count mode: stop when the time-base counter = period (TBCNT = TBPRD)
• Down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
• Up-down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
2h-3h
13
PHSDIR
Free run
Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-downcount mode. The PHSDIR bit indicates the direction the time-base counter (TBCNT) will count after
a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register.
This is irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
12:10
9-7
CLKDIV
HSPCLKDIV
0
Count down after the synchronization event.
1
Count up after the synchronization event.
0-7h
Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value.
TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
0
/1 (default on reset)
1h
/2
2h
/4
3h
/8
4h
/16
5h
/32
6h
/64
7h
/128
0-7h
High-Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock
prescale value.
TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager
(EV) peripheral.
6
0
/1
1h
/2 (default on reset)
2h
/4
3h
/6
4h
/8
5h
/10
6h
/12
7h
/14
SWFSYNC
Software Forced Synchronization Pulse
0
Writing a 0 has no effect and reads always return a 0.
1
Writing a 1 forces a one-time synchronization pulse to be generated.
This event is ORed with the EPWMxSYNCI input of the ePWM module.
SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.
5-4
422
SYNCOSEL
0-3h
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
0
EPWMxSYNC:
1h
CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
2h
CTR = CMPB : Time-base counter equal to counter-compare B (TBCNT = CMPB)
3h
Disable EPWMxSYNCO signal
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Table 14-52. Time-Base Control Register (TBCTL) Field Descriptions (continued)
Bit
3
Field
Value
PRDLD
Description
Active Period Register Load From Shadow Register Select
0
The period register (TBPRD) is loaded from its shadow register when the time-base counter,
TBCNT, is equal to zero.
A write or read to the TBPRD register accesses the shadow register.
1
Load the TBPRD register immediately without using a shadow register.
A write or read to the TBPRD register directly accesses the active register.
2
1-0
PHSEN
Counter Register Load From Phase Register Enable
CTRMODE
0
Do not load the time-base counter (TBCNT) from the time-base phase register (TBPHS)
1
Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or
when a software synchronization is forced by the SWFSYNC bit.
0-3h
Counter Mode. The time-base counter mode is normally configured once and not changed during
normal operation. If you change the mode of the counter, the change will take effect at the next
TBCLK edge and the current counter value shall increment or decrement from the value before the
mode change.
These bits set the time-base counter mode of operation as follows:
0
Up-count mode
1h
Down-count mode
2h
Up-down-count mode
3h
Stop-freeze counter operation (default on reset)
14.4.1.2 Time-Base Status Register (TBSTS)
The time-base status register (TBSTS) is shown in Figure 14-66 and described in Table 14-53.
Figure 14-66. Time-Base Status Register (TBSTS)
15
2
1
0
Reserved
3
CTRMAX
SYNCI
CTRDIR
R-0
R/W1C-0
R/W1C-0
R-1
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to clear; -n = value after reset
Table 14-53. Time-Base Status Register (TBSTS) Field Descriptions
Bit
Field
15-3
Reserved
2
CTRMAX
1
0
Value
0
Description
Reserved
Time-Base Counter Max Latched Status Bit
0
Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no
effect.
1
Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing a 1
to this bit will clear the latched event.
SYNCI
Input Synchronization Latched Status Bit
0
Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred.
1
Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI).
Writing a 1 to this bit will clear the latched event.
CTRDIR
Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no
meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL[CTRMODE].
0
Time-Base Counter is currently counting down.
1
Time-Base Counter is currently counting up.
14.4.1.3 Time-Base Phase Register (TBPHS)
The time-base phase register (TBPHS) is shown in Figure 14-67 and described in Table 14-54.
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Figure 14-67. Time-Base Phase Register (TBPHS)
15
0
TBPHS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-54. Time-Base Phase Register (TBPHS) Field Descriptions
Bits
Name
15-0
TBPHS
Value
0-FFFFh
Description
These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying
the synchronization input signal.
• If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is not
loaded with the phase.
• If TBCTL[PHSEN] = 1, then the time-base counter (TBCNT) will be loaded with the phase (TBPHS)
when a synchronization event occurs. The synchronization event can be initiated by the input
synchronization signal (EPWMxSYNCI) or by a software forced synchronization.
14.4.1.4 Time-Base Counter Register (TBCNT)
The time-base counter register (TBCNT) is shown in Figure 14-68 and described in Table 14-55.
Figure 14-68. Time-Base Counter Register (TBCNT)
15
0
TBCNT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-55. Time-Base Counter Register (TBCNT) Field Descriptions
Bits
Name
15-0
TBCNT
Value
0-FFFFh
Description
Reading these bits gives the current time-base counter value.
Writing to these bits sets the current time-base counter value. The update happens as soon as the write
occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not
shadowed.
424
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14.4.1.5 Time-Base Period Register (TBPRD)
The time-base period register (TBPRD) is shown in Figure 14-69 and described in Table 14-56.
Figure 14-69. Time-Base Period Register (TBPRD)
15
0
TBPRD
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-56. Time-Base Period Register (TBPRD) Field Descriptions
Bits
Name
15-0
TBPRD
Value
0-FFFFh
Description
These bits determine the period of the time-base counter. This sets the PWM frequency.
Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is
shadowed.
• If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the
shadow register. In this case, the active register will be loaded from the shadow register when the
time-base counter equals zero.
• If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active
register, that is the register actively controlling the hardware.
• The active and shadow registers share the same memory map address.
14.4.2 Counter-Compare Submodule Registers
Table 14-57 lists the memory-mapped registers for the counter-compare submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-57 should be considered as reserved locations and the register contents should not be
modified.
Table 14-57. Counter-Compare Submodule Registers
Offset
(1)
Acronym
Register Description
Section
Eh
CMPCTL
Counter-Compare Control Register
Section 14.4.2.1
10h
CMPAHR
Counter-Compare A High-Resolution Register (1)
Section 14.4.8.2
12h
CMPA
Counter-Compare A Register
Section 14.4.2.2
14h
CMPB
Counter-Compare B Register
Section 14.4.2.3
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved. See your device-specific data manual to determine which instances include the HRPWM.
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14.4.2.1 Counter-Compare Control Register (CMPCTL)
The counter-compare control register (CMPCTL) is shown in Figure 14-70 and described in Table 14-58.
Figure 14-70. Counter-Compare Control Register (CMPCTL)
15
10
9
8
Reserved
SHDWBFULL
SHDWAFULL
R-0
R-0
R-0
1
0
7
6
5
4
3
2
Reserved
SHDWBMODE
Reserved
SHDWAMODE
LOADBMODE
LOADAMODE
R-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-58. Counter-Compare Control Register (CMPCTL) Field Descriptions
Bits
Name
15-10 Reserved
9
8
6
SHDWBMODE
5
Reserved
4
SHDWAMODE
426
LOADBMODE
LOADAMODE
Reserved
Counter-compare B (CMPB) Shadow Register Full Status Flag. This bit self clears once a load-strobe
occurs.
0
CMPB shadow FIFO not full yet
1
Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value.
SHDWAFULL
Reserved
1-0
0
SHDWBFULL
7
3-2
Value Description
Counter-compare A (CMPA) Shadow Register Full Status Flag. The flag bit is set when a 32-bit write to
CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register
will not affect the flag. This bit self clears once a load-strobe occurs.
0
CMPA shadow FIFO not full yet
1
Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value.
0
Reserved
Counter-compare B (CMPB) Register Operating Mode
0
Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1
Immediate mode. Only the active compare B register is used. All writes and reads directly access the
active register for immediate compare action.
Reserved
Counter-compare A (CMPA) Register Operating Mode
0
Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1
Immediate mode. Only the active compare register is used. All writes and reads directly access the
active register for immediate compare action
0-3h
Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWBMODE] = 1).
0
Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h
Load on either CTR = 0 or CTR = PRD
3h
Freeze (no loads possible)
0-3h
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWAMODE] = 1).
0
Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h
Load on either CTR = 0 or CTR = PRD
3h
Freeze (no loads possible)
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14.4.2.2 Counter-Compare A Register (CMPA)
The counter-compare A register (CMPA) is shown in Figure 14-71 and described in Table 14-59.
Figure 14-71. Counter-Compare A Register (CMPA)
15
0
CMPA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-59. Counter-Compare A Register (CMPA) Field Descriptions
Bits
Name
Value
15-0
CMPA
0-FFFFh
Description
The value in the active CMPA register is continuously compared to the time-base counter (TBCNT).
When the values are equal, the counter-compare module generates a "time-base counter equal to
counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it
into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output
depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined
in the AQCTLA and AQCTLB registers include:
•
•
•
•
Do nothing; the event is ignored.
Clear: Pull the EPWMxA and/or EPWMxB signal low
Set: Pull the EPWMxA and/or EPWMxB signal high
Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this
register is shadowed.
• If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically
go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event
will load the active register from the shadow register.
• Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is
currently full.
• If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go
directly to the active register, that is the register actively controlling the hardware.
• In either mode, the active and shadow registers share the same memory map address.
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14.4.2.3 Counter-Compare B Register (CMPB)
The counter-compare B register (CMPB) is shown in Figure 14-72 and described in Table 14-60.
Figure 14-72. Counter-Compare B Register (CMPB)
15
0
CMPB
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-60. Counter-Compare B Register (CMPB) Field Descriptions
Bits
Name
Value
15-0
CMPB
0-FFFFh
Description
The value in the active CMPB register is continuously compared to the time-base counter (TBCNT).
When the values are equal, the counter-compare module generates a "time-base counter equal to
counter compare B" event. This event is sent to the action-qualifier where it is qualified and converted it
into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output
depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined
in the AQCTLA and AQCTLB registers include:
•
•
•
•
Do nothing. event is ignored.
Clear: Pull the EPWMxA and/or EPWMxB signal low
Set: Pull the EPWMxA and/or EPWMxB signal high
Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit. By default this
register is shadowed.
• If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically
go to the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event
will load the active register from the shadow register:
• Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is
currently full.
• If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go
directly to the active register, that is the register actively controlling the hardware.
• In either mode, the active and shadow registers share the same memory map address.
14.4.3 Action-Qualifier Submodule Registers
Table 14-61 lists the memory-mapped registers for the action-qualifier submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-61 should be considered as reserved locations and the register contents should not be
modified.
Table 14-61. Action-Qualifier Submodule Registers
428
Offset
Acronym
Register Description
16h
AQCTLA
Action-Qualifier Output A Control Register
Section 14.4.3.1
Section
18h
AQCTLB
Action-Qualifier Output B Control Register
Section 14.4.3.2
1Ah
AQSFRC
Action-Qualifier Software Force Register
Section 14.4.3.3
1Ch
AQCSFRC
Action-Qualifier Continuous Software Force Register
Section 14.4.3.4
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14.4.3.1 Action-Qualifier Output A Control Register (AQCTLA)
The action-qualifier output A control register (AQCTLA) is shown in Figure 14-73 and described in
Table 14-62.
Figure 14-73. Action-Qualifier Output A Control Register (AQCTLA)
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CBD
CBU
CAD
CAU
PRD
ZRO
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-62. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions
Bits
Name
15-12
Reserved
11-10
CBD
9-8
7-6
5-4
3-2
CBU
CAD
CAU
PRD
Value
0
0-3h
Description
Reserved
Action when the time-base counter equals the active CMPB register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPB register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the period.
Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0
or counting down.
1-0
ZRO
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when counter equals zero.
Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or
counting up.
0
Do nothing (action disabled)
1h
Clear: force EPWMxA output low.
2h
Set: force EPWMxA output high.
3h
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
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14.4.3.2 Action-Qualifier Output B Control Register (AQCTLB)
The action-qualifier output B control register (AQCTLB) is shown in Figure 14-74 and described in
Table 14-63.
Figure 14-74. Action-Qualifier Output B Control Register (AQCTLB)
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CBD
CBU
CAD
CAU
PRD
ZRO
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-63. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
Bits
Name
15-12
Reserved
11-10
CBD
9-8
7-6
5-4
3-2
CBU
CAD
CAU
PRD
Value
0
0-3h
Description
Reserved
Action when the counter equals the active CMPB register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPB register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is decrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the active CMPA register and the counter is incrementing.
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when the counter equals the period.
Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0
or counting down.
1-0
ZRO
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
0-3h
Action when counter equals zero.
Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or
counting up.
430
0
Do nothing (action disabled)
1h
Clear: force EPWMxB output low.
2h
Set: force EPWMxB output high.
3h
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
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14.4.3.3 Action-Qualifier Software Force Register (AQSFRC)
The action-qualifier software force register (AQSFRC) is shown in Figure 14-75 and described in
Table 14-64.
Figure 14-75. Action-Qualifier Software Force Register (AQSFRC)
15
8
7
6
5
4
3
2
1
0
Reserved
RLDCSF
OTSFB
ACTSFB
OTSFA
ACTSFA
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-64. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
Bit
Field
Value
15-8
Reserved
0
7-6
RLDCSF
0-3h
5
Description
Reserved
AQCSFRC Active Register Reload From Shadow Options
0
Load on event counter equals zero
1h
Load on event counter equals period
2h
Load on event counter equals zero or counter equals period
3h
Load immediately (the active register is directly accessed by the CPU and is not loaded from the
shadow register).
OTSFB
One-Time Software Forced Event on Output B
0
Writing a 0 (zero) has no effect. Always reads back a 0
This bit is auto cleared once a write to this register is complete, that is, a forced event is initiated.)
This is a one-shot forced event. It can be overridden by another subsequent event on output B.
1
4-3
ACTSFB
0-3h
Initiates a single s/w forced event
Action when One-Time Software Force B Is invoked
0
Does nothing (action disabled)
1h
Clear (low)
2h
Set (high)
3h
Toggle (Low -> High, High -> Low)
Note: This action is not qualified by counter direction (CNT_dir)
2
OTSFA
One-Time Software Forced Event on Output A
0
Writing a 0 (zero) has no effect. Always reads back a 0.
This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated).
1
1-0
ACTSFA
0-3h
Initiates a single software forced event
Action When One-Time Software Force A Is Invoked
0
Does nothing (action disabled)
1h
Clear (low)
2h
Set (high)
3h
Toggle (Low → High, High → Low)
Note: This action is not qualified by counter direction (CNT_dir)
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14.4.3.4 Action-Qualifier Continuous Software Force Register (AQCSFRC)
The action-qualifier continuous software force register (AQCSFRC) is shown in Figure 14-76 and
described in Table 14-65.
Figure 14-76. Action-Qualifier Continuous Software Force Register (AQCSFRC)
15
4
3
2
1
0
Reserved
CSFB
CSFA
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-65. Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
Bits
Name
15-4
Reserved
3-2
CSFB
Value
0
0-3h
Description
Reserved
Continuous Software Force on Output B
In immediate mode, a continuous force takes effect on the next TBCLK edge.
In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the
active register. To configure shadow mode, use AQSFRC[RLDCSF].
1-0
CSFA
0
Forcing disabled, that is, has no effect
1h
Forces a continuous low on output B
2h
Forces a continuous high on output B
3h
Software forcing is disabled and has no effect
0-3h
Continuous Software Force on Output A
In immediate mode, a continuous force takes effect on the next TBCLK edge.
In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the
active register.
0
Forcing disabled, that is, has no effect
1h
Forces a continuous low on output A
2h
Forces a continuous high on output A
3h
Software forcing is disabled and has no effect
14.4.4 Dead-Band Generator Submodule Registers
Table 14-66 lists the memory-mapped registers for the dead-band generator submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-66 should be considered as reserved locations and the register contents should not be
modified.
Table 14-66. Dead-Band Generator Submodule Registers
432
Offset
Acronym
1Eh
DBCTL
Register Description
Dead-Band Generator Control Register
Section 14.4.4.1
20h
DBRED
Dead-Band Generator Rising Edge Delay Register
Section 14.4.4.2
22h
DBFED
Dead-Band Generator Falling Edge Delay Register
Section 14.4.4.3
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14.4.4.1 Dead-Band Generator Control Register (DBCTL)
The dead-band generator control register (DBCTL) is shown in Figure 14-77 and described in
Table 14-67.
Figure 14-77. Dead-Band Generator Control Register (DBCTL)
15
6
5
4
3
2
1
0
Reserved
IN_MODE
POLSEL
OUT_MODE
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-67. Dead-Band Generator Control Register (DBCTL) Field Descriptions
Bits
Name
15-6
Reserved
Value
0
5-4
IN_MODE
0-3h
Description
Reserved
Dead Band Input Mode Control. Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in
Figure 14-29. This allows you to select the input source to the falling-edge and rising-edge delay.
To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and
rising-edge delays.
0
EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
1h
EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
2h
EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
3-2
POLSEL
3h
EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed
signal.
0-3h
Polarity Select Control. Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 1429. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band
submodule.
The following descriptions correspond to classical upper/lower switch control as found in one leg of a
digital motor control inverter.
These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other enhanced modes
are also possible, but not regarded as typical usage modes.
1-0
OUT_MODE
0
Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
1h
Active low complementary (ALC) mode. EPWMxA is inverted.
2h
Active high complementary (AHC). EPWMxB is inverted.
3h
Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.
0-3h
Dead-band Output Mode Control. Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in
Figure 14-29. This allows you to selectively enable or bypass the dead-band generation for the fallingedge and rising-edge delay.
0
Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and
EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule.
In this mode, the POLSEL and IN_MODE bits have no effect.
1h
Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to
the EPWMxA input of the PWM-chopper submodule.
The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined
by DBCTL[IN_MODE].
2h
Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to
the EPWMxB input of the PWM-chopper submodule.
The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined
by DBCTL[IN_MODE].
3h
Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on
output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE].
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14.4.4.2 Dead-Band Generator Rising Edge Delay Register (DBRED)
The dead-band generator rising edge delay register (DBRED) is shown in Figure 14-78 and described in
Table 14-68.
Figure 14-78. Dead-Band Generator Rising Edge Delay Register (DBRED)
15
10
9
0
Reserved
DEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-68. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
Bits
15-10
9-0
Name
Value
Reserved
0
DEL
0-3FFh
Description
Reserved
Rising Edge Delay Count. 10-bit counter.
14.4.4.3 Dead-Band Generator Falling Edge Delay Register (DBFED)
The dead-band generator falling edge delay register (DBFED) is shown in Figure 14-79 and described in
Table 14-69.
Figure 14-79. Dead-Band Generator Falling Edge Delay Register (DBFED)
15
10
9
0
Reserved
DEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-69. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
Bits
15-10
9-0
434
Name
Reserved
DEL
Value
0
0-3FFh
Description
Reserved
Falling Edge Delay Count. 10-bit counter
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14.4.5 PWM-Chopper Submodule Register
The PWM-chopper control register (PCCTL) is shown in Figure 14-80 and described in Table 14-70.
Figure 14-80. PWM-Chopper Control Register (PCCTL)
15
11
10
8
7
5
4
1
0
Reserved
CHPDUTY
CHPFREQ
OSHTWTH
CHPEN
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-70. PWM-Chopper Control Register (PCCTL) Bit Descriptions
Bits
Name
Value
15-11
Reserved
0
10-8
CHPDUTY
0-7h
7-5
4-1
CHPFREQ
OSHTWTH
Reserved
Chopping Clock Duty Cycle
0
Duty = 1/8 (12.5%)
1h
Duty = 2/8 (25.0%)
2h
Duty = 3/8 (37.5%)
3h
Duty = 4/8 (50.0%)
4h
Duty = 5/8 (62.5%)
5h
Duty = 6/8 (75.0%)
6h
Duty = 7/8 (87.5%)
7h
Reserved
0-7h
Chopping Clock Frequency
0
Divide by 1 (no prescale)
1h
Divide by 2
2h
Divide by 3
3h-7h
Divide by 4 to divide by 8
0-Fh
One-Shot Pulse Width
0
1 × SYSCLKOUT/8 wide
1h
2 × SYSCLKOUT/8 wide
2h
3 × SYSCLKOUT/8 wide
3h-Fh
0
Description
CHPEN
4 × SYSCLKOUT/8 wide to 16 × SYSCLKOUT/8 wide
PWM-chopping Enable
0
Disable (bypass) PWM chopping function
1
Enable chopping function
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14.4.6 Trip-Zone Submodule Registers
Table 14-71 lists the memory-mapped registers for the trip-zone submodule. See your device-specific data
manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-71 should be considered as reserved locations and the register contents should not be modified.
Table 14-71. Trip-Zone Submodule Registers
Offset
Acronym
24h
TZSEL
Register Description
Trip-Zone Select Register
Section 14.4.6.1
Section
28h
TZCTL
Trip-Zone Control Register
Section 14.4.6.2
2Ah
TZEINT
Trip-Zone Enable Interrupt Register
Section 14.4.6.3
2Ch
TZFLG
Trip-Zone Flag Register
Section 14.4.6.4
2Eh
TZCLR
Trip-Zone Clear Register
Section 14.4.6.5
30h
TZFRC
Trip-Zone Force Register
Section 14.4.6.6
14.4.6.1 Trip-Zone Select Register (TZSEL)
The trip-zone select register (TZSEL) is shown in Figure 14-81 and described in Table 14-72.
Figure 14-81. Trip-Zone Select Register (TZSEL)
15
9
Reserved/OSHTn
(1)
8
OSHT1
R/W-0
7
1
Reserved/CBCn
R/W-0
(1)
R/W-0
0
CBC1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
(1)
Number of register bits depends on how many trip-zone pins are available in the device. See your device-specific data manual.
Table 14-72. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
Bits
Name
15-8
OSHTn
7-0
436
Value
Description
Trip-zone n (TZn) select. One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go
low, a one-shot trip event occurs for this ePWM module. When the event occurs, the action defined in
the TZCTL register (Section 14.4.6.2) is taken on the EPWMxA and EPWMxB outputs. The one-shot
trip condition remains latched until you clear the condition via the TZCLR register (Section 14.4.6.5).
0
Disable TZn as a one-shot trip source for this ePWM module.
1
Enable TZn as a one-shot trip source for this ePWM module.
CBCn
Trip-zone n (TZn) select. Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins
go low, a cycle-by-cycle trip event occurs for this ePWM module. When the event occurs, the action
defined in the TZCTL register (Section 14.4.6.2) is taken on the EPWMxA and EPWMxB outputs. A
cycle-by-cycle trip condition is automatically cleared when the time-base counter reaches zero.
0
Disable TZn as a CBC trip source for this ePWM module.
1
Enable TZn as a CBC trip source for this ePWM module.
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14.4.6.2 Trip-Zone Control Register (TZCTL)
The trip-zone control register (TZCTL) is shown in Figure 14-82 and described in Table 14-73.
Figure 14-82. Trip-Zone Control Register (TZCTL)
15
4
3
2
1
0
Reserved
TZB
TZA
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-73. Trip-Zone Control Register (TZCTL) Field Descriptions
Bits
Name
15–4
Reserved
3–2
TZB
1–0
TZA
Value
0
0-3h
Description
Reserved
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can
cause an event is defined in the TZSEL register (Section 14.4.6.1).
0
High impedance (EPWMxB = High-impedance state)
1h
Force EPWMxB to a high state
2h
Force EPWMxB to a low state
3h
Do nothing, no action is taken on EPWMxB.
0-3h
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can
cause an event is defined in the TZSEL register (Section 14.4.6.1).
0
High impedance (EPWMxA = High-impedance state)
1h
Force EPWMxA to a high state
2h
Force EPWMxA to a low state
3h
Do nothing, no action is taken on EPWMxA.
14.4.6.3 Trip-Zone Enable Interrupt Register (TZEINT)
The trip-zone enable interrupt register (TZEINT) is shown in Figure 14-83 and described in Table 14-74.
Figure 14-83. Trip-Zone Enable Interrupt Register (TZEINT)
15
2
1
0
Reserved
3
OST
CBC
Rsvd
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-74. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
Bits
Name
15-3
Reserved
2
1
0
Value
0
OST
Reserved
Trip-zone One-Shot Interrupt Enable
0
Disable one-shot interrupt generation
1
Enable Interrupt generation; a one-shot trip event will cause a EPWMxTZINT interrupt.
CBC
Reserved
Description
Trip-zone Cycle-by-Cycle Interrupt Enable
0
Disable cycle-by-cycle interrupt generation.
1
Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt.
0
Reserved
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14.4.6.4 Trip-Zone Flag Register (TZFLG)
The trip-zone flag register (TZFLG) is shown in Figure 14-84 and described in Table 14-75.
Figure 14-84. Trip-Zone Flag Register (TZFLG)
15
3
2
1
0
Reserved
OST
CBC
INT
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-75. Trip-Zone Flag Register (TZFLG) Field Descriptions
Bits
Name
15-3
Reserved
2
Value
0
OST
Description
Reserved
Latched Status Flag for A One-Shot Trip Event.
0
No one-shot trip event has occurred.
1
Indicates a trip event has occurred on a pin selected as a one-shot trip source.
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5).
1
CBC
Latched Status Flag for Cycle-By-Cycle Trip Event
0
No cycle-by-cycle trip event has occurred.
1
Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The TZFLG[CBC]
bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present
when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the
pins is automatically cleared when the ePWM time-base counter reaches zero (TBCNT = 0000h) if the
trip condition is no longer present. The condition on the pins is only cleared when the TBCNT = 0000h
no matter where in the cycle the CBC flag is cleared.
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5).
0
INT
Latched Trip Interrupt Status Flag
0
Indicates no interrupt has been generated.
1
Indicates an EPWMxTZINT interrupt was generated because of a trip condition.
No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the interrupt flag is
cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag
bits will prevent further interrupts.
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5).
438
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14.4.6.5 Trip-Zone Clear Register (TZCLR)
The trip-zone clear register (TZCLR) is shown in Figure 14-85 and described in Table 14-76.
Figure 14-85. Trip-Zone Clear Register (TZCLR)
15
3
2
1
0
Reserved
OST
CBC
INT
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-76. Trip-Zone Clear Register (TZCLR) Field Descriptions
Bits
Name
15-3
Reserved
2
1
0
Value
0
OST
Description
Reserved
Clear Flag for One-Shot Trip (OST) Latch
0
Has no effect. Always reads back a 0.
1
Clears this Trip (set) condition.
CBC
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0
Has no effect. Always reads back a 0.
1
Clears this Trip (set) condition.
INT
Global Interrupt Clear Flag
0
Has no effect. Always reads back a 0.
1
Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the TZFLG[INT]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated.
Clearing all flag bits will prevent further interrupts.
14.4.6.6 Trip-Zone Force Register (TZFRC)
The trip-zone force register (TZFRC) is shown in Figure 14-86 and described in Table 14-77.
Figure 14-86. Trip-Zone Force Register (TZFRC)
15
2
1
0
Reserved
3
OST
CBC
Rsvd
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-77. Trip-Zone Force Register (TZFRC) Field Descriptions
Bits
Name
15-3
Reserved
2
1
0
Value
0
OST
Reserved
Force a One-Shot Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a one-shot trip event and sets the TZFLG[OST] bit.
CBC
Reserved
Description
Force a Cycle-by-Cycle Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
0
Reserved
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14.4.7 Event-Trigger Submodule Registers
Table 14-78 lists the memory-mapped registers for the event-trigger submodule. See your device-specific
data manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-78 should be considered as reserved locations and the register contents should not be modified.
Table 14-78. Event-Trigger Submodule Registers
Offset
Acronym
32h
ETSEL
Register Description
Event-Trigger Selection Register
Section 14.4.7.1
Section
34h
ETPS
Event-Trigger Prescale Register
Section 14.4.7.2
36h
ETFLG
Event-Trigger Flag Register
Section 14.4.7.3
38h
ETCLR
Event-Trigger Clear Register
Section 14.4.7.4
3Ah
ETFRC
Event-Trigger Force Register
Section 14.4.7.5
14.4.7.1 Event-Trigger Selection Register (ETSEL)
The event-trigger selection register (ETSEL) is shown in Figure 14-87 and described in Table 14-79.
Figure 14-87. Event-Trigger Selection Register (ETSEL)
15
4
3
2
0
Reserved
INTEN
INTSEL
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-79. Event-Trigger Selection Register (ETSEL) Field Descriptions
Bits
Name
15-4
Reserved
3
2-0
440
Value
0
INTEN
INTSEL
Description
Reserved
Enable ePWM Interrupt (EPWMx_INT) Generation
0
Disable EPWMx_INT generation
1
Enable EPWMx_INT generation
0-7h
ePWM Interrupt (EPWMx_INT) Selection Options
0
Reserved
1h
Enable event time-base counter equal to zero. (TBCNT = 0000h)
2h
Enable event time-base counter equal to period (TBCNT = TBPRD)
3h
Reserved
4h
Enable event time-base counter equal to CMPA when the timer is incrementing.
5h
Enable event time-base counter equal to CMPA when the timer is decrementing.
6h
Enable event: time-base counter equal to CMPB when the timer is incrementing.
7h
Enable event: time-base counter equal to CMPB when the timer is decrementing.
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14.4.7.2 Event-Trigger Prescale Register (ETPS)
The event-trigger prescale register (ETPS) is shown in Figure 14-88 and described in Table 14-80.
Figure 14-88. Event-Trigger Prescale Register (ETPS)
15
4
3
2
1
0
Reserved
INTCNT
INTPRD
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-80. Event-Trigger Prescale Register (ETPS) Field Descriptions
Bits
Name
15-4
Reserved
3-2
INTCNT
1-0
INTPRD
Value
0
0-3h
Description
Reserved
ePWM Interrupt Event (EPWMx_INT) Counter Register. These bits indicate how many selected
ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is
generated. If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the
counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
0
No events have occurred.
1h
1 event has occurred.
2h
2 events have occurred.
3h
3 events have occurred.
0-3h
ePWM Interrupt (EPWMx_INT) Period Select. These bits determine how many selected
ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated, the interrupt
must be enabled (ETSEL[INT] = 1). If the interrupt status flag is set from a previous interrupt
(ETFLG[INT] = 1) then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit.
This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is
generated, the ETPS[INTCNT] bits will automatically be cleared.
Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is
enabled and the status flag is clear.
Writing a INTPRD value that is less than the current counter value will result in an undefined state.
If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the
counter is incremented.
0
Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
1h
Generate an interrupt on the first event INTCNT = 01 (first event)
2h
Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
3h
Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
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14.4.7.3 Event-Trigger Flag Register (ETFLG)
The event-trigger flag register (ETFLG) is shown in Figure 14-89 and described in Table 14-81.
Figure 14-89. Event-Trigger Flag Register (ETFLG)
15
1
0
Reserved
INT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-81. Event-Trigger Flag Register (ETFLG) Field Descriptions
Bits
Name
15-1
Reserved
0
Value
0
INT
Description
Reserved
Latched ePWM Interrupt (EPWMx_INT) Status Flag
0
Indicates no event occurred
1
Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated
until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit is still set. If an
interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared. Refer to Figure 1442.
14.4.7.4 Event-Trigger Clear Register (ETCLR)
The event-trigger clear register (ETCLR) is shown in Figure 14-90 and described in Table 14-82.
Figure 14-90. Event-Trigger Clear Register (ETCLR)
15
1
0
Reserved
INT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-82. Event-Trigger Clear Register (ETCLR) Field Descriptions
Bits
Name
15-1
Reserved
0
442
Value
0
INT
Description
Reserved
ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0
Writing a 0 has no effect. Always reads back a 0.
1
Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated.
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14.4.7.5 Event-Trigger Force Register (ETFRC)
The event-trigger force register (ETFRC) is shown in Figure 14-91 and described in Table 14-83.
Figure 14-91. Event-Trigger Force Register (ETFRC)
15
1
0
Reserved
INT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-83. Event-Trigger Force Register (ETFRC) Field Descriptions
Bits
Name
15-1
Reserved
0
Value
0
INT
Description
Reserved
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The
INT flag bit will be set regardless.
0
Writing 0 to this bit will be ignored. Always reads back a 0.
1
Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.
14.4.8 High-Resolution PWM Submodule Registers
Table 14-84 lists the memory-mapped registers for the high-resolution PWM submodule. See your devicespecific data manual for the memory address of these registers. All other register offset addresses not
listed in Table 14-84 should be considered as reserved locations and the register contents should not be
modified.
Table 14-84. High-Resolution PWM Submodule Registers
Offset
Acronym
Register Description
Section
4h
TBPHSHR
Time-Base Phase High-Resolution Register
Section 14.4.8.1
10h
CMPAHR
Counter-Compare A High-Resolution Register
Section 14.4.8.2
1040h
HRCNFG
HRPWM Configuration Register
Section 14.4.8.3
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14.4.8.1 Time-Base Phase High-Resolution Register (TBPHSHR)
The time-base phase high-resolution register (TBPHSHR) is shown in Figure 14-92 and described in
Table 14-85.
Figure 14-92. Time-Base Phase High-Resolution Register (TBPHSHR)
15
8
7
0
TBPHSH
Reserved
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-85. Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions
Bit
Field
Value
Description
15-8
TBPHSH
0-FFh
Time-base phase high-resolution bits
7-0
Reserved
0
Reserved
14.4.8.2 Counter-Compare A High-Resolution Register (CMPAHR)
The counter-compare A high-resolution register (CMPAHR) is shown in Figure 14-93 and described in
Table 14-86.
Figure 14-93. Counter-Compare A High-Resolution Register (CMPAHR)
15
8
7
0
CMPAHR
Reserved
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-86. Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions
Field
Value
Description
15-8
Bit
CMPAHR
1-FFh
Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to
enable HRPWM capabilities. Valid MEP range of operation 1-255h.
7-0
Reserved
0
444
Reserved
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14.4.8.3 HRPWM Configuration Register (HRCNFG)
The HRPWM configuration register (HRCNFG) is shown in Figure 14-94 and described in Table 14-87.
Figure 14-94. HRPWM Configuration Register (HRCNFG)
15
4
3
2
1
0
Reserved
HRLOAD
CTLMODE
EDGMODE
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-87. HRPWM Configuration Register (HRCNFG) Field Descriptions
Bit
Field
15-4
Reserved
3
HRLOAD
Value
0
Description
ReserveD
Shadow mode bit: Selects the time event that loads the CMPAHR shadow value into the active register:
0
CTR = 0 (counter equals zero)
1
CTR = PRD (counter equal period)
Note: Load mode selection is valid only if CTLMODE = 0 has been selected. You should select this event
to match the selection of the CMPA load mode (CMPCTL[LOADMODE] bits) in the EPWM module as
follows:
2
1-0
CTLMODE
EDGMODE
0
Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h
Load on either CTR = 0 or CTR = PRD (should not be used with HRPWM)
3h
Freeze (no loads possible – should not be used with HRPWM)
Control Mode Bits: Selects the register (CMP or TBPHS) that controls the MEP:
0
CMPAHR(8) Register controls the edge position (this is duty control mode). (default on reset)
1
TBPHSHR(8) Register controls the edge position (this is phase control mode).
0-3h
Edge Mode Bits: Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic:
0
HRPWM capability is disabled (default on reset)
1h
MEP control of rising edge
2h
MEP control of falling edge
3h
MEP control of both edges
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Chapter 15
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Enhanced Direct Memory Access (EDMA3) Controller
The enhanced direct memory access (EDMA3) controller is a high-performance, multichannel,
multithreaded DMA controller that allows you to program a wide variety of transfer geometries and transfer
sequences. This chapter describes the features and operations of the EDMA3 controller.
Section 15.1 provides a brief overview, features, and terminology. Section 15.2 provides the architecture
details and common operations of the EDMA3 channel controllers (EDMA3_m_CC0) and the EDMA3
transfer controllers (EDMA3_m_TCn). Section 15.3 contains examples and common usage scenarios.
Section 15.4 describes the memory-mapped registers associated with the EDMA3 controller.
Topic
15.1
15.2
15.3
15.4
15.5
15.6
446
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Transfer Examples ............................................................................................
Registers .........................................................................................................
Tips ................................................................................................................
Setting Up a Transfer ........................................................................................
Enhanced Direct Memory Access (EDMA3) Controller
Page
447
452
495
512
579
581
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