Texas Instruments | AM1802 ARM Microprocessor (Rev. C) | User Guides | Texas Instruments AM1802 ARM Microprocessor (Rev. C) User guides

Texas Instruments AM1802 ARM Microprocessor (Rev. C) User guides
AM1802
Sitara ARM Microprocessor
Technical Reference Manual
Literature Number: SPRUH84C
April 2013 – Revised September 2016
Contents
Preface....................................................................................................................................... 55
1
Overview ........................................................................................................................... 56
1.1
1.2
2
ARM Subsystem ................................................................................................................. 58
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
Introduction .................................................................................................................. 66
System Interconnect Block Diagram ..................................................................................... 67
Introduction .................................................................................................................. 69
ARM Memories ............................................................................................................. 69
Peripherals .................................................................................................................. 69
Memory Protection Unit (MPU) ............................................................................................. 70
5.1
5.2
5.3
2
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64
System Memory ................................................................................................................. 68
4.1
4.2
4.3
5
Introduction ..................................................................................................................
Operating States/Modes ...................................................................................................
Processor Status Registers ...............................................................................................
Exceptions and Exception Vectors .......................................................................................
The 16-BIS/32-BIS Concept ..............................................................................................
16-BIS/32-BIS Advantages ...............................................................................................
Co-Processor 15 (CP15) ..................................................................................................
2.7.1 Addresses in an ARM926EJ-S System ........................................................................
2.7.2 Memory Management Unit (MMU) ..............................................................................
2.7.3 Caches and Write Buffer ........................................................................................
System Interconnect ........................................................................................................... 65
3.1
3.2
4
Introduction .................................................................................................................. 57
ARM Subsystem ............................................................................................................ 57
Introduction ..................................................................................................................
5.1.1 Purpose of the MPU ..............................................................................................
5.1.2 Features ............................................................................................................
5.1.3 Block Diagram .....................................................................................................
5.1.4 MPU Default Configuration.......................................................................................
Architecture .................................................................................................................
5.2.1 Privilege Levels ....................................................................................................
5.2.2 Memory Protection Ranges ......................................................................................
5.2.3 Permission Structures ............................................................................................
5.2.4 Protection Check ..................................................................................................
5.2.5 MPU Register Protection .........................................................................................
5.2.6 Invalid Accesses and Exceptions ...............................................................................
5.2.7 Reset Considerations .............................................................................................
5.2.8 Interrupt Support ..................................................................................................
5.2.9 Emulation Considerations ........................................................................................
MPU Registers..............................................................................................................
5.3.1 Revision Identification Register (REVID) .......................................................................
5.3.2 Configuration Register (CONFIG) ...............................................................................
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ..............................................................
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ...........................................................
5.3.5 Interrupt Enable Set Register (IENSET) .......................................................................
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5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
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Device Clocking ................................................................................................................. 91
6.1
6.2
6.3
7
Interrupt Enable Clear Register (IENCLR) .....................................................................
Fixed Range Start Address Register (FXD_MPSAR) ........................................................
Fixed Range End Address Register (FXD_MPEAR) .........................................................
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .................................
Programmable Range n Start Address Registers (PROGn_MPSAR) ....................................
Programmable Range n End Address Registers (PROGn_MPEAR) .....................................
Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) ..............
Fault Address Register (FLTADDRR) .........................................................................
Fault Status Register (FLTSTAT) ..............................................................................
Fault Clear Register (FLTCLR) .................................................................................
Overview..................................................................................................................... 92
Frequency Flexibility ....................................................................................................... 94
Peripheral Clocking ........................................................................................................ 95
6.3.1 USB Clocking ...................................................................................................... 95
6.3.2 DDR2/mDDR Memory Controller Clocking .................................................................... 96
6.3.3 EMIFA Clocking ................................................................................................... 98
6.3.4 EMAC Clocking .................................................................................................... 99
6.3.5 McASP Clocking ................................................................................................. 100
6.3.6 I/O Domains ...................................................................................................... 101
Phase-Locked Loop Controller (PLLC) ................................................................................ 102
7.1
7.2
7.3
Introduction ................................................................................................................
PLL Controllers ............................................................................................................
7.2.1 Device Clock Generation .......................................................................................
7.2.2 Steps for Programming the PLLs ..............................................................................
PLLC Registers ...........................................................................................................
7.3.1 PLLC0 Revision Identification Register (REVID) ............................................................
7.3.2 PLLC1 Revision Identification Register (REVID) ............................................................
7.3.3 Reset Type Status Register (RSTYPE) .......................................................................
7.3.4 PLLC0 Reset Control Register (RSCTRL) ...................................................................
7.3.5 PLLC0 Control Register (PLLCTL) ............................................................................
7.3.6 PLLC1 Control Register (PLLCTL) ............................................................................
7.3.7 PLLC0 OBSCLK Select Register (OCSEL) ..................................................................
7.3.8 PLLC1 OBSCLK Select Register (OCSEL) ..................................................................
7.3.9 PLL Multiplier Control Register (PLLM) .......................................................................
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV) .............................................................
7.3.11 PLLC0 Divider 1 Register (PLLDIV1) ........................................................................
7.3.12 PLLC1 Divider 1 Register (PLLDIV1) ........................................................................
7.3.13 PLLC0 Divider 2 Register (PLLDIV2) ........................................................................
7.3.14 PLLC1 Divider 2 Register (PLLDIV2) ........................................................................
7.3.15 PLLC0 Divider 3 Register (PLLDIV3) ........................................................................
7.3.16 PLLC1 Divider 3 Register (PLLDIV3) ........................................................................
7.3.17 PLLC0 Divider 4 Register (PLLDIV4) ........................................................................
7.3.18 PLLC0 Divider 5 Register (PLLDIV5) ........................................................................
7.3.19 PLLC0 Divider 6 Register (PLLDIV6) ........................................................................
7.3.20 PLLC0 Divider 7 Register (PLLDIV7) ........................................................................
7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV).............................................................
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV).............................................................
7.3.23 PLL Post-Divider Control Register (POSTDIV) .............................................................
7.3.24 PLL Controller Command Register (PLLCMD) .............................................................
7.3.25 PLL Controller Status Register (PLLSTAT) .................................................................
7.3.26 PLLC0 Clock Align Control Register (ALNCTL) ............................................................
7.3.27 PLLC1 Clock Align Control Register (ALNCTL) ............................................................
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7.3.28
7.3.29
7.3.30
7.3.31
7.3.32
7.3.33
7.3.34
7.3.35
7.3.36
7.3.37
8
8.3
8.4
8.5
8.6
Introduction ................................................................................................................
Power Domain and Module Topology ..................................................................................
8.2.1 Power Domain States ...........................................................................................
8.2.2 Module States ....................................................................................................
Executing State Transitions .............................................................................................
8.3.1 Power Domain State Transitions ..............................................................................
8.3.2 Module State Transitions .......................................................................................
IcePick Emulation Support in the PSC .................................................................................
PSC Interrupts.............................................................................................................
8.5.1 Interrupt Events ..................................................................................................
8.5.2 Interrupt Registers ...............................................................................................
8.5.3 Interrupt Handling ................................................................................................
PSC Registers.............................................................................................................
8.6.1 Revision Identification Register (REVID) .....................................................................
8.6.2 Interrupt Evaluation Register (INTEVAL) .....................................................................
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ...................................
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ...................................
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ......................................
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ......................................
8.6.7 Power Error Pending Register (PERRPR) ...................................................................
8.6.8 Power Error Clear Register (PERRCR) .......................................................................
8.6.9 Power Domain Transition Command Register (PTCMD)...................................................
8.6.10 Power Domain Transition Status Register (PTSTAT)......................................................
8.6.11 Power Domain 0 Status Register (PDSTAT0) ..............................................................
8.6.12 Power Domain 1 Status Register (PDSTAT1) ..............................................................
8.6.13 Power Domain 0 Control Register (PDCTL0) ...............................................................
8.6.14 Power Domain 1 Control Register (PDCTL1) ...............................................................
8.6.15 Power Domain 0 Configuration Register (PDCFG0) .......................................................
8.6.16 Power Domain 1 Configuration Register (PDCFG1) .......................................................
8.6.17 Module Status n Register (MDSTATn).......................................................................
8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................
8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................
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Power Management........................................................................................................... 160
9.1
9.2
9.3
9.4
9.5
9.6
4
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134
134
Power and Sleep Controller (PSC) ...................................................................................... 135
8.1
8.2
9
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .............................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .............................................
PLLC0 Clock Enable Control Register (CKEN) .............................................................
PLLC1 Clock Enable Control Register (CKEN) .............................................................
PLLC0 Clock Status Register (CKSTAT) ....................................................................
PLLC1 Clock Status Register (CKSTAT) ....................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ................................................................
Emulation Performance Counter 0 Register (EMUCNT0) .................................................
Emulation Performance Counter 1 Register (EMUCNT1) .................................................
Introduction ................................................................................................................
Power Consumption Overview ..........................................................................................
PSC and PLLC Overview ................................................................................................
Features ....................................................................................................................
Clock Management .......................................................................................................
9.5.1 Module Clock ON/OFF ..........................................................................................
9.5.2 Module Clock Frequency Scaling ..............................................................................
9.5.3 PLL Bypass and Power Down .................................................................................
ARM Sleep Mode Management ........................................................................................
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9.7
9.8
9.9
9.10
10
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System Configuration (SYSCFG) Module ............................................................................. 173
10.1
10.2
10.3
10.4
10.5
11
9.6.1 ARM Wait-For-Interrupt Sleep Mode ..........................................................................
9.6.2 ARM Clock OFF..................................................................................................
9.6.3 ARM Subsystem Clock ON .....................................................................................
RTC-Only Mode ...........................................................................................................
Dynamic Voltage and Frequency Scaling (DVFS) ...................................................................
9.8.1 Frequency Scaling Considerations ............................................................................
9.8.2 Voltage Scaling Considerations ................................................................................
Deep Sleep Mode.........................................................................................................
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ..............................
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up .....................................
9.9.3 Deep Sleep Sequence ..........................................................................................
9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ........................................
Additional Peripheral Power Management Considerations..........................................................
9.10.1 USB PHY Power Down Control ..............................................................................
9.10.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode ................................
9.10.3 LVCMOS I/O Buffer Receiver Disable .......................................................................
9.10.4 Pull-Up/Pull-Down Disable.....................................................................................
Introduction ................................................................................................................
Protection ..................................................................................................................
10.2.1 Privilege Mode Protection .....................................................................................
10.2.2 Kicker Mechanism Protection .................................................................................
Master Priority Control ...................................................................................................
Interrupt Support ..........................................................................................................
10.4.1 Interrupt Events and Requests................................................................................
10.4.2 Interrupt Multiplexing ...........................................................................................
SYSCFG Registers .......................................................................................................
10.5.1 Revision Identification Register (REVID) ....................................................................
10.5.2 Device Identification Register 0 (DEVIDR0).................................................................
10.5.3 Boot Configuration Register (BOOTCFG) ...................................................................
10.5.4 Chip Revision Identification Register (CHIPREVIDR) .....................................................
10.5.5 Kick Registers (KICK0R-KICK1R) ............................................................................
10.5.6 Host 0 Configuration Register (HOST0CFG) ...............................................................
10.5.7 Interrupt Registers ..............................................................................................
10.5.8 Fault Registers ..................................................................................................
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2) ............................................................
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) .............................................
10.5.11 Suspend Source Register (SUSPSRC) ....................................................................
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) ..............................................................
10.5.14 Chip Configuration 0 Register (CFGCHIP0) ...............................................................
10.5.15 Chip Configuration 1 Register (CFGCHIP1) ...............................................................
10.5.16 Chip Configuration 2 Register (CFGCHIP2) ...............................................................
10.5.17 Chip Configuration 3 Register (CFGCHIP3) ...............................................................
10.5.18 Chip Configuration 4 Register (CFGCHIP4) ...............................................................
10.5.19 VTP I/O Control Register (VTPIO_CTL) ...................................................................
10.5.20 DDR Slew Register (DDR_SLEW) ..........................................................................
10.5.21 Deep Sleep Register (DEEPSLEEP) .......................................................................
10.5.22 Pullup/Pulldown Enable Register (PUPD_ENA) ..........................................................
10.5.23 Pullup/Pulldown Select Register (PUPD_SEL) ............................................................
10.5.24 RXACTIVE Control Register (RXACTIVE) .................................................................
ARM Interrupt Controller (AINTC)
11.1
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....................................................................................... 245
Introduction ................................................................................................................ 246
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11.2
11.3
11.4
Interrupt Mapping .........................................................................................................
AINTC Methodology ......................................................................................................
11.3.1 Interrupt Processing ............................................................................................
11.3.2 Interrupt Enabling ...............................................................................................
11.3.3 Interrupt Status Checking ......................................................................................
11.3.4 Interrupt Channel Mapping ....................................................................................
11.3.5 Host Interrupt Mapping Interrupts ............................................................................
11.3.6 Interrupt Prioritization ..........................................................................................
11.3.7 Interrupt Nesting ................................................................................................
11.3.8 Interrupt Vectorization .........................................................................................
11.3.9 Interrupt Status Clearing .......................................................................................
11.3.10 Interrupt Disabling .............................................................................................
AINTC Registers ..........................................................................................................
11.4.1 Revision Identification Register (REVID) ....................................................................
11.4.2 Control Register (CR) ..........................................................................................
11.4.3 Global Enable Register (GER) ................................................................................
11.4.4 Global Nesting Level Register (GNLR) ......................................................................
11.4.5 System Interrupt Status Indexed Set Register (SISR) .....................................................
11.4.6 System Interrupt Status Indexed Clear Register (SICR) ..................................................
11.4.7 System Interrupt Enable Indexed Set Register (EISR) ....................................................
11.4.8 System Interrupt Enable Indexed Clear Register (EICR)..................................................
11.4.9 Host Interrupt Enable Indexed Set Register (HIEISR) .....................................................
11.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR) .................................................
11.4.11 Vector Base Register (VBR) .................................................................................
11.4.12 Vector Size Register (VSR) ..................................................................................
11.4.13 Vector Null Register (VNR) ..................................................................................
11.4.14 Global Prioritized Index Register (GPIR) ...................................................................
11.4.15 Global Prioritized Vector Register (GPVR) ................................................................
11.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1) ...................................................
11.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2) ...................................................
11.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3) ...................................................
11.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4) ...................................................
11.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1) ............................................
11.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2) ............................................
11.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3) ............................................
11.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4) ............................................
11.4.24 System Interrupt Enable Set Register 1 (ESR1) ..........................................................
11.4.25 System Interrupt Enable Set Register 2 (ESR2) ..........................................................
11.4.26 System Interrupt Enable Set Register 3 (ESR3) ..........................................................
11.4.27 System Interrupt Enable Set Register 4 (ESR4) ..........................................................
11.4.28 System Interrupt Enable Clear Register 1 (ECR1) .......................................................
11.4.29 System Interrupt Enable Clear Register 2 (ECR2) .......................................................
11.4.30 System Interrupt Enable Clear Register 3 (ECR3) .......................................................
11.4.31 System Interrupt Enable Clear Register 4 (ECR4) .......................................................
11.4.32 Channel Map Registers (CMR0-CMR25) ..................................................................
11.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1) ......................................................
11.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2) ......................................................
11.4.35 Host Interrupt Nesting Level Register 1 (HINLR1) ........................................................
11.4.36 Host Interrupt Nesting Level Register 2 (HINLR2) ........................................................
11.4.37 Host Interrupt Enable Register (HIER) .....................................................................
11.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1) ...................................................
11.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2) ...................................................
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Boot Considerations ......................................................................................................... 275
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12.1
13
DDR2/mDDR Memory Controller ......................................................................................... 277
13.1
13.2
13.3
13.4
14
Introduction ................................................................................................................ 276
Introduction ................................................................................................................
13.1.1 Purpose of the Peripheral .....................................................................................
13.1.2 Features..........................................................................................................
13.1.3 Functional Block Diagram .....................................................................................
13.1.4 Supported Use Case Statement ..............................................................................
13.1.5 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
13.2.1 Clock Control ....................................................................................................
13.2.2 Signal Descriptions .............................................................................................
13.2.3 Protocol Description(s) .........................................................................................
13.2.4 Memory Width and Byte Alignment ..........................................................................
13.2.5 Address Mapping ...............................................................................................
13.2.6 DDR2/mDDR Memory Controller Interface ..................................................................
13.2.7 Refresh Scheduling .............................................................................................
13.2.8 Self-Refresh Mode ..............................................................................................
13.2.9 Partial Array Self Refresh for Mobile DDR ..................................................................
13.2.10 Power-Down Mode ............................................................................................
13.2.11 Reset Considerations .........................................................................................
13.2.12 VTP IO Buffer Calibration ....................................................................................
13.2.13 Auto-Initialization Sequence .................................................................................
13.2.14 Interrupt Support ..............................................................................................
13.2.15 DMA Event Support ...........................................................................................
13.2.16 Power Management ..........................................................................................
13.2.17 Emulation Considerations ....................................................................................
Supported Use Cases ....................................................................................................
Registers ...................................................................................................................
13.4.1 SDRAM Status Register (SDRSTAT) ........................................................................
13.4.2 SDRAM Configuration Register (SDCR) ....................................................................
13.4.3 SDRAM Refresh Control Register (SDRCR) ................................................................
13.4.4 SDRAM Timing Register 1 (SDTIMR1) ......................................................................
13.4.5 SDRAM Timing Register 2 (SDTIMR2) ......................................................................
13.4.6 SDRAM Configuration Register 2 (SDCR2) .................................................................
13.4.7 Peripheral Bus Burst Priority Register (PBBPR)............................................................
13.4.8 Performance Counter 1 Register (PC1) .....................................................................
13.4.9 Performance Counter 2 Register (PC2) .....................................................................
13.4.10 Performance Counter Configuration Register (PCC) .....................................................
13.4.11 Performance Counter Master Region Select Register (PCMRS) .......................................
13.4.12 DDR PHY Reset Control Register (DRPYRCR) ..........................................................
13.4.13 Interrupt Raw Register (IRR) ................................................................................
13.4.14 Interrupt Masked Register (IMR) ............................................................................
13.4.15 Interrupt Mask Set Register (IMSR) ........................................................................
13.4.16 Interrupt Mask Clear Register (IMCR) ......................................................................
13.4.17 DDR PHY Control Register (DRPYC1R) ...................................................................
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Enhanced Direct Memory Access (EDMA3) Controller ........................................................... 332
14.1
14.2
Introduction ................................................................................................................
14.1.1 Overview .........................................................................................................
14.1.2 Features..........................................................................................................
14.1.3 Functional Block Diagram .....................................................................................
14.1.4 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
14.2.1 Functional Overview ............................................................................................
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14.3
14.4
14.5
14.6
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EMAC/MDIO Module .......................................................................................................... 467
15.1
15.2
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14.2.2 Types of EDMA3 Transfers ...................................................................................
14.2.3 Parameter RAM (PaRAM) .....................................................................................
14.2.4 Initiating a DMA Transfer ......................................................................................
14.2.5 Completion of a DMA Transfer................................................................................
14.2.6 Event, Channel, and PaRAM Mapping ......................................................................
14.2.7 EDMA3 Channel Controller Regions .........................................................................
14.2.8 Chaining EDMA3 Channels ...................................................................................
14.2.9 EDMA3 Interrupts ...............................................................................................
14.2.10 Event Queue(s) ................................................................................................
14.2.11 EDMA3 Transfer Controller (EDMA3TC)...................................................................
14.2.12 Event Dataflow ................................................................................................
14.2.13 EDMA3 Prioritization ..........................................................................................
14.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................
14.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................
14.2.16 Reset Considerations .........................................................................................
14.2.17 Power Management ..........................................................................................
14.2.18 Emulation Considerations ....................................................................................
Transfer Examples........................................................................................................
14.3.1 Block Move Example ...........................................................................................
14.3.2 Subframe Extraction Example ................................................................................
14.3.3 Data Sorting Example ..........................................................................................
14.3.4 Peripheral Servicing Example .................................................................................
Registers ...................................................................................................................
14.4.1 Parameter RAM (PaRAM) Entries ............................................................................
14.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................
14.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ........................................................
Tips .........................................................................................................................
14.5.1 Debug Checklist ................................................................................................
14.5.2 Miscellaneous Programming/Debug Tips ...................................................................
Setting Up a Transfer ....................................................................................................
Introduction ................................................................................................................
15.1.1 Purpose of the Peripheral .....................................................................................
15.1.2 Features..........................................................................................................
15.1.3 Functional Block Diagram .....................................................................................
15.1.4 Industry Standard(s) Compliance Statement................................................................
15.1.5 Terminology .....................................................................................................
Architecture ................................................................................................................
15.2.1 Clock Control ....................................................................................................
15.2.2 Memory Map ....................................................................................................
15.2.3 Signal Descriptions .............................................................................................
15.2.4 Ethernet Protocol Overview ...................................................................................
15.2.5 Programming Interface .........................................................................................
15.2.6 EMAC Control Module .........................................................................................
15.2.7 MDIO Module ...................................................................................................
15.2.8 EMAC Module ...................................................................................................
15.2.9 MAC Interface ...................................................................................................
15.2.10 Packet Receive Operation ...................................................................................
15.2.11 Packet Transmit Operation ..................................................................................
15.2.12 Receive and Transmit Latency ..............................................................................
15.2.13 Transfer Node Priority ........................................................................................
15.2.14 Reset Considerations .........................................................................................
15.2.15 Initialization .....................................................................................................
Contents
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15.3
16
15.2.16 Interrupt Support ..............................................................................................
15.2.17 Power Management ..........................................................................................
15.2.18 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
15.3.1 EMAC Control Module Registers .............................................................................
15.3.2 MDIO Registers .................................................................................................
15.3.3 EMAC Module Registers.......................................................................................
509
513
513
514
514
528
541
External Memory Interface A (EMIFA) .................................................................................. 591
16.1
16.2
16.3
16.4
Introduction ................................................................................................................
16.1.1 Purpose of the Peripheral .....................................................................................
16.1.2 Features..........................................................................................................
16.1.3 Functional Block Diagram .....................................................................................
Architecture ................................................................................................................
16.2.1 Clock Control ....................................................................................................
16.2.2 EMIFA Requests ................................................................................................
16.2.3 Pin Descriptions .................................................................................................
16.2.4 SDRAM Controller and Interface .............................................................................
16.2.5 Asynchronous Controller and Interface ......................................................................
16.2.6 Data Bus Parking ...............................................................................................
16.2.7 Reset and Initialization Considerations ......................................................................
16.2.8 Interrupt Support ................................................................................................
16.2.9 EDMA Event Support ..........................................................................................
16.2.10 Pin Multiplexing ................................................................................................
16.2.11 Memory Map ...................................................................................................
16.2.12 Priority and Arbitration ........................................................................................
16.2.13 System Considerations .......................................................................................
16.2.14 Power Management ..........................................................................................
16.2.15 Emulation Considerations ....................................................................................
Example Configuration ...................................................................................................
16.3.1 Hardware Interface .............................................................................................
16.3.2 Software Configuration .........................................................................................
Registers ...................................................................................................................
16.4.1 Module ID Register (MIDR) ...................................................................................
16.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) ...............................................
16.4.3 SDRAM Configuration Register (SDCR) ....................................................................
16.4.4 SDRAM Refresh Control Register (SDRCR) ................................................................
16.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
16.4.6 SDRAM Timing Register (SDTIMR) ..........................................................................
16.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ..................................................
16.4.8 EMIFA Interrupt Raw Register (INTRAW) ...................................................................
16.4.9 EMIFA Interrupt Masked Register (INTMSK) ...............................................................
16.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET).......................................................
16.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ....................................................
16.4.12 NAND Flash Control Register (NANDFCR) ...............................................................
16.4.13 NAND Flash Status Register (NANDFSR) .................................................................
16.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ..........................................
16.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) .......................................
16.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..................................................
16.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..................................................
16.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..................................................
16.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..................................................
16.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) .................................
16.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) .................................
SPRUH84C – April 2013 – Revised September 2016
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Contents
592
592
592
592
592
593
593
593
595
607
626
626
627
628
628
628
629
630
631
632
633
633
633
655
656
656
658
660
661
663
664
665
666
667
668
669
671
672
673
674
674
675
675
676
676
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16.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)..................................... 677
16.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)..................................... 677
17
General-Purpose Input/Output (GPIO) ................................................................................. 678
17.1
17.2
17.3
18
679
679
679
679
679
680
680
680
680
680
681
684
685
685
686
686
687
687
687
688
689
690
691
693
695
697
699
701
703
705
707
709
................................................................................... 711
Introduction ................................................................................................................ 712
18.1.1 Purpose of the Peripheral ..................................................................................... 712
18.1.2 Features.......................................................................................................... 712
18.1.3 Functional Block Diagram ..................................................................................... 713
18.1.4 Industry Standard(s) Compliance Statement................................................................ 713
Architecture ................................................................................................................ 714
18.2.1 Bus Structure .................................................................................................... 714
18.2.2 Clock Generation ............................................................................................... 715
18.2.3 Clock Synchronization ......................................................................................... 716
18.2.4 Signal Descriptions ............................................................................................. 716
18.2.5 START and STOP Conditions ................................................................................ 717
18.2.6 Serial Data Formats ............................................................................................ 718
18.2.7 Operating Modes ............................................................................................... 720
18.2.8 NACK Bit Generation........................................................................................... 721
18.2.9 Arbitration ........................................................................................................ 722
18.2.10 Reset Considerations ......................................................................................... 723
18.2.11 Initialization ..................................................................................................... 723
Inter-Integrated Circuit (I2C) Module
18.1
18.2
10
Introduction ................................................................................................................
17.1.1 Purpose of the Peripheral .....................................................................................
17.1.2 Features..........................................................................................................
17.1.3 Functional Block Diagram .....................................................................................
17.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
17.2.1 Clock Control ....................................................................................................
17.2.2 Signal Descriptions .............................................................................................
17.2.3 Pin Multiplexing .................................................................................................
17.2.4 Endianness Considerations ...................................................................................
17.2.5 GPIO Register Structure .......................................................................................
17.2.6 Using a GPIO Signal as an Output ...........................................................................
17.2.7 Using a GPIO Signal as an Input .............................................................................
17.2.8 Reset Considerations ..........................................................................................
17.2.9 Initialization ......................................................................................................
17.2.10 Interrupt Support ..............................................................................................
17.2.11 EDMA Event Support .........................................................................................
17.2.12 Power Management ..........................................................................................
17.2.13 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
17.3.1 Revision ID Register (REVID) .................................................................................
17.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ......................................................
17.3.3 GPIO Direction Registers (DIRn) .............................................................................
17.3.4 GPIO Output Data Registers (OUT_DATAn) ...............................................................
17.3.5 GPIO Set Data Registers (SET_DATAn) ....................................................................
17.3.6 GPIO Clear Data Registers (CLR_DATAn) .................................................................
17.3.7 GPIO Input Data Registers (IN_DATAn) ....................................................................
17.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) ...........................................
17.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ........................................
17.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................
17.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) .....................................
17.3.12 GPIO Interrupt Status Registers (INTSTATn) .............................................................
Contents
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18.3
19
18.2.12 Interrupt Support ..............................................................................................
18.2.13 DMA Events Generated by the I2C Peripheral ............................................................
18.2.14 Power Management ..........................................................................................
18.2.15 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
18.3.1 I2C Own Address Register (ICOAR) .........................................................................
18.3.2 I2C Interrupt Mask Register (ICIMR) .........................................................................
18.3.3 I2C Interrupt Status Register (ICSTR) ......................................................................
18.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) .......................................................
18.3.5 I2C Data Count Register (ICCNT) ............................................................................
18.3.6 I2C Data Receive Register (ICDRR) .........................................................................
18.3.7 I2C Slave Address Register (ICSAR) ........................................................................
18.3.8 I2C Data Transmit Register (ICDXR) ........................................................................
18.3.9 I2C Mode Register (ICMDR) ..................................................................................
18.3.10 I2C Interrupt Vector Register (ICIVR) ......................................................................
18.3.11 I2C Extended Mode Register (ICEMDR) ...................................................................
18.3.12 I2C Prescaler Register (ICPSC).............................................................................
18.3.13 I2C Revision Identification Register (REVID1) ............................................................
18.3.14 I2C Revision Identification Register (REVID2) ...........................................................
18.3.15 I2C DMA Control Register (ICDMAC) ......................................................................
18.3.16 I2C Pin Function Register (ICPFUNC) ....................................................................
18.3.17 I2C Pin Direction Register (ICPDIR) .......................................................................
18.3.18 I2C Pin Data In Register (ICPDIN) .........................................................................
18.3.19 I2C Pin Data Out Register (ICPDOUT) ....................................................................
18.3.20 I2C Pin Data Set Register (ICPDSET) ....................................................................
18.3.21 I2C Pin Data Clear Register (ICPDCLR) ..................................................................
724
725
725
725
726
727
728
729
732
733
734
735
736
737
741
742
743
744
744
745
746
747
748
749
750
751
Multichannel Audio Serial Port (McASP) .............................................................................. 752
19.1
19.0.22 Features .......................................................................................................
19.0.23 Protocols Supported .........................................................................................
19.0.24 Functional Block Diagram ....................................................................................
19.0.25 Definition of Terms ...........................................................................................
19.0.26 Overview .......................................................................................................
19.0.27 Clock and Frame Sync Generators ........................................................................
19.0.28 Reset Considerations .........................................................................................
19.0.29 EDMA Event Support .........................................................................................
19.0.30 Power Management ..........................................................................................
Registers ...................................................................................................................
19.1.1 Register Bit Restrictions .......................................................................................
19.1.2 Revision Identification Register (REV) .......................................................................
19.1.3 Pin Function Register (PFUNC) ..............................................................................
19.1.4 Pin Direction Register (PDIR) ................................................................................
19.1.5 Pin Data Output Register (PDOUT) ..........................................................................
19.1.6 Pin Data Input Register (PDIN) ...............................................................................
19.1.7 Pin Data Set Register (PDSET) ..............................................................................
19.1.8 Pin Data Clear Register (PDCLR) ............................................................................
19.1.9 Global Control Register (GBLCTL) ...........................................................................
19.1.10 Audio Mute Control Register (AMUTE).....................................................................
19.1.11 Digital Loopback Control Register (DLBCTL) .............................................................
19.1.12 Digital Mode Control Register (DITCTL) ...................................................................
19.1.13 Receiver Global Control Register (RGBLCTL) ............................................................
19.1.14 Receive Format Unit Bit Mask Register (RMASK) ........................................................
19.1.15 Receive Bit Stream Format Register (RFMT) .............................................................
19.1.16 Receive Frame Sync Control Register (AFSRCTL) ......................................................
SPRUH84C – April 2013 – Revised September 2016
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Contents
753
754
755
763
766
766
807
807
807
808
811
812
813
815
817
819
821
823
825
827
829
830
831
832
833
835
11
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19.1.17
19.1.18
19.1.19
19.1.20
19.1.21
19.1.22
19.1.23
19.1.24
19.1.25
19.1.26
19.1.27
19.1.28
19.1.29
19.1.30
19.1.31
19.1.32
19.1.33
19.1.34
19.1.35
19.1.36
19.1.37
19.1.38
19.1.39
19.1.40
19.1.41
19.1.42
19.1.43
19.1.44
19.1.45
19.1.46
19.1.47
19.1.48
20
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
20.1
20.2
12
Receive Clock Control Register (ACLKRCTL) ............................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ......................................
Receive TDM Time Slot Register (RTDM) .................................................................
Receiver Interrupt Control Register (RINTCTL) ...........................................................
Receiver Status Register (RSTAT) .........................................................................
Current Receive TDM Time Slot Registers (RSLOT) ....................................................
Receive Clock Check Control Register (RCLKCHK) .....................................................
Receiver DMA Event Control Register (REVTCTL) ......................................................
Transmitter Global Control Register (XGBLCTL) .........................................................
Transmit Format Unit Bit Mask Register (XMASK) .......................................................
Transmit Bit Stream Format Register (XFMT).............................................................
Transmit Frame Sync Control Register (AFSXCTL) ......................................................
Transmit Clock Control Register (ACLKXCTL) ............................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ......................................
Transmit TDM Time Slot Register (XTDM) ................................................................
Transmitter Interrupt Control Register (XINTCTL) ........................................................
Transmitter Status Register (XSTAT) ......................................................................
Current Transmit TDM Time Slot Register (XSLOT) .....................................................
Transmit Clock Check Control Register (XCLKCHK) ....................................................
Transmitter DMA Event Control Register (XEVTCTL) ...................................................
Serializer Control Registers (SRCTLn) .....................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ...........................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)..........................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ......................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) .....................................
Transmit Buffer Registers (XBUFn) .........................................................................
Receive Buffer Registers (RBUFn) .........................................................................
AFIFO Revision Identification Register (AFIFOREV) .....................................................
Write FIFO Control Register (WFIFOCTL) .................................................................
Write FIFO Status Register (WFIFOSTS)..................................................................
Read FIFO Control Register (RFIFOCTL) .................................................................
Read FIFO Status Register (RFIFOSTS) ..................................................................
.................................................. 866
Introduction ................................................................................................................
20.1.1 Purpose of the Peripheral .....................................................................................
20.1.2 Features..........................................................................................................
20.1.3 Functional Block Diagram .....................................................................................
20.1.4 Supported Use Case Statement ..............................................................................
20.1.5 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
20.2.1 Clock Control ....................................................................................................
20.2.2 Signal Descriptions .............................................................................................
20.2.3 Protocol Descriptions ...........................................................................................
20.2.4 Data Flow in the Input/Output FIFO ..........................................................................
20.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) .............................................
20.2.6 FIFO Operation During Card Read Operation ..............................................................
20.2.7 FIFO Operation During Card Write Operation ..............................................................
20.2.8 Reset Considerations ..........................................................................................
20.2.9 Initialization ......................................................................................................
20.2.10 Interrupt Support ..............................................................................................
20.2.11 DMA Event Support ...........................................................................................
20.2.12 Power Management ..........................................................................................
20.2.13 Emulation Considerations ....................................................................................
Contents
836
837
838
839
840
841
842
843
844
845
846
848
849
850
851
852
853
854
855
856
857
858
858
859
859
860
860
861
862
863
864
865
867
867
867
867
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868
868
869
870
871
872
874
875
877
877
879
882
883
883
883
SPRUH84C – April 2013 – Revised September 2016
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20.3
20.4
21
Procedures for Common Operations ...................................................................................
20.3.1 Card Identification Operation ..................................................................................
20.3.2 MMC/SD Mode Single-Block Write Operation Using CPU ................................................
20.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA .........................................
20.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ...........................................
20.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ..............................................
20.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU ..............................................
20.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA ............................................
20.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ..............................................
20.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA ............................................
20.3.10 SDIO Card Function ..........................................................................................
Registers ...................................................................................................................
20.4.1 MMC Control Register (MMCCTL) ...........................................................................
20.4.2 MMC Memory Clock Control Register (MMCCLK) .........................................................
20.4.3 MMC Status Register 0 (MMCST0) ..........................................................................
20.4.4 MMC Status Register 1 (MMCST1) ..........................................................................
20.4.5 MMC Interrupt Mask Register (MMCIM) .....................................................................
20.4.6 MMC Response Time-Out Register (MMCTOR) ...........................................................
20.4.7 MMC Data Read Time-Out Register (MMCTOD) ..........................................................
20.4.8 MMC Block Length Register (MMCBLEN) ..................................................................
20.4.9 MMC Number of Blocks Register (MMCNBLK).............................................................
20.4.10 MMC Number of Blocks Counter Register (MMCNBLC).................................................
20.4.11 MMC Data Receive Register (MMCDRR) .................................................................
20.4.12 MMC Data Transmit Register (MMCDXR) .................................................................
20.4.13 MMC Command Register (MMCCMD) .....................................................................
20.4.14 MMC Argument Register (MMCARGHL)...................................................................
20.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) .....................................................
20.4.16 MMC Data Response Register (MMCDRSP) .............................................................
20.4.17 MMC Command Index Register (MMCCIDX) .............................................................
20.4.18 SDIO Control Register (SDIOCTL) .........................................................................
20.4.19 SDIO Status Register 0 (SDIOST0) ........................................................................
20.4.20 SDIO Interrupt Enable Register (SDIOIEN) ...............................................................
20.4.21 SDIO Interrupt Status Register (SDIOIST).................................................................
20.4.22 MMC FIFO Control Register (MMCFIFOCTL) .............................................................
884
884
887
889
889
891
891
893
893
895
895
896
897
898
899
901
902
904
905
906
907
907
908
908
909
911
912
914
914
915
916
917
917
918
Real-Time Clock (RTC) ...................................................................................................... 919
21.1
21.2
21.3
Introduction ................................................................................................................
21.1.1 Purpose of the Peripheral .....................................................................................
21.1.2 Features..........................................................................................................
21.1.3 Block Diagram ...................................................................................................
Architecture ................................................................................................................
21.2.1 Clock Source ....................................................................................................
21.2.2 Signal Descriptions .............................................................................................
21.2.3 Isolated Power Supply .........................................................................................
21.2.4 Operation ........................................................................................................
21.2.5 Interrupt Requests ..............................................................................................
21.2.6 Register Protection Against Spurious Writes ...............................................................
21.2.7 General-Purpose Scratch Registers .........................................................................
21.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) ................................
21.2.9 Emulation Modes of the Real-Time Clock ...................................................................
21.2.10 Reset Considerations .........................................................................................
Registers ...................................................................................................................
21.3.1 Second Register (SECOND) ..................................................................................
21.3.2 Minute Register (MINUTE) ....................................................................................
SPRUH84C – April 2013 – Revised September 2016
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Contents
920
920
920
920
921
921
921
921
922
924
925
926
926
926
926
927
928
928
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21.3.3
21.3.4
21.3.5
21.3.6
21.3.7
21.3.8
21.3.9
21.3.10
21.3.11
21.3.12
21.3.13
21.3.14
21.3.15
21.3.16
21.3.17
21.3.18
21.3.19
21.3.20
21.3.21
22
929
930
930
931
931
932
932
933
934
935
935
936
937
938
939
940
941
942
942
Serial Peripheral Interface (SPI) .......................................................................................... 943
22.1
22.2
22.3
14
Hour Register (HOUR) .........................................................................................
Day of the Month Register (DAY) ............................................................................
Month Register (MONTH) .....................................................................................
Year Register (YEAR) ..........................................................................................
Day of the Week Register (DOTW) ..........................................................................
Alarm Second Register (ALARMSECOND) .................................................................
Alarm Minute Register (ALARMMINUTE) ...................................................................
Alarm Hour Register (ALARMHOUR) ......................................................................
Alarm Day of the Month Register (ALARMDAY) ..........................................................
Alarm Month Register (ALARMMONTH) ...................................................................
Alarm Year Register (ALARMYEAR) .......................................................................
Control Register (CTRL) .....................................................................................
Status Register (STATUS) ...................................................................................
Interrupt Register (INTERRUPT) ............................................................................
Compensation (LSB) Register (COMPLSB) ...............................................................
Compensation (MSB) Register (COMPMSB) .............................................................
Oscillator Register (OSC) ....................................................................................
Scratch Registers (SCRATCH0-SCRATCH2) .............................................................
Kick Registers (KICK0R, KICK1R) ..........................................................................
Introduction ................................................................................................................
22.1.1 Purpose of the Peripheral .....................................................................................
22.1.2 Features..........................................................................................................
22.1.3 Functional Block Diagram .....................................................................................
22.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
22.2.1 Clock .............................................................................................................
22.2.2 Signal Descriptions .............................................................................................
22.2.3 Operation Modes ...............................................................................................
22.2.4 Programmable Registers ......................................................................................
22.2.5 Master Mode Settings ..........................................................................................
22.2.6 Slave Mode Settings ...........................................................................................
22.2.7 SPI Operation: 3-Pin Mode ....................................................................................
22.2.8 SPI Operation: 4-Pin with Chip Select Mode ...............................................................
22.2.9 SPI Operation: 4-Pin with Enable Mode .....................................................................
22.2.10 SPI Operation: 5-Pin Mode ..................................................................................
22.2.11 Data Formats ..................................................................................................
22.2.12 Interrupt Support ..............................................................................................
22.2.13 DMA Events Support .........................................................................................
22.2.14 Robustness Features .........................................................................................
22.2.15 Reset Considerations .........................................................................................
22.2.16 Power Management ..........................................................................................
22.2.17 General-Purpose I/O Pin .....................................................................................
22.2.18 Emulation Considerations ....................................................................................
22.2.19 Initialization .....................................................................................................
22.2.20 Timing Diagrams ..............................................................................................
Registers ...................................................................................................................
22.3.1 SPI Global Control Register 0 (SPIGCR0) ..................................................................
22.3.2 SPI Global Control Register 1 (SPIGCR1) ..................................................................
22.3.3 SPI Interrupt Register (SPIINT0) .............................................................................
22.3.4 SPI Interrupt Level Register (SPILVL) .......................................................................
22.3.5 SPI Flag Register (SPIFLG) ...................................................................................
22.3.6 SPI Pin Control Register 0 (SPIPC0) .......................................................................
Contents
944
944
944
945
945
946
946
946
946
947
948
950
951
952
954
956
958
961
962
962
964
964
965
965
965
966
972
972
973
975
977
978
980
SPRUH84C – April 2013 – Revised September 2016
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22.3.7
22.3.8
22.3.9
22.3.10
22.3.11
22.3.12
22.3.13
22.3.14
22.3.15
22.3.16
22.3.17
22.3.18
22.3.19
23
981
982
983
984
985
986
987
988
990
991
994
995
997
64-Bit Timer Plus .............................................................................................................. 998
23.1
23.2
24
SPI Pin Control Register 1 (SPIPC1) ........................................................................
SPI Pin Control Register 2 (SPIPC2) ........................................................................
SPI Pin Control Register 3 (SPIPC3) ........................................................................
SPI Pin Control Register 4 (SPIPC4) .......................................................................
SPI Pin Control Register 5 (SPIPC5) .......................................................................
SPI Transmit Data Register 0 (SPIDAT0)..................................................................
SPI Transmit Data Register 1 (SPIDAT1)..................................................................
SPI Receive Buffer Register (SPIBUF).....................................................................
SPI Emulation Register (SPIEMU) ..........................................................................
SPI Delay Register (SPIDELAY) ............................................................................
SPI Default Chip Select Register (SPIDEF) ...............................................................
SPI Data Format Registers (SPIFMTn) ....................................................................
SPI Interrupt Vector Register 1 (INTVEC1) ................................................................
Introduction ................................................................................................................ 999
23.1.1 Purpose of the Peripheral ..................................................................................... 999
23.1.2 Features.......................................................................................................... 999
23.1.3 Block Diagram ................................................................................................. 1000
23.1.4 Industry Standard Compatibility Statement ................................................................ 1000
23.1.5 Architecture – General-Purpose Timer Mode ............................................................. 1000
23.1.6 Architecture – Watchdog Timer Mode ...................................................................... 1012
23.1.7 Reset Considerations ......................................................................................... 1014
23.1.8 Interrupt Support .............................................................................................. 1014
23.1.9 DMA Event Support ........................................................................................... 1014
23.1.10 TM64P_OUT Event Support ............................................................................... 1015
23.1.11 Interrupt/DMA Event Generation Control and Status ................................................... 1016
23.1.12 Power Management ......................................................................................... 1016
23.1.13 Emulation Considerations .................................................................................. 1016
Registers ................................................................................................................. 1017
23.2.1 Revision ID Register (REVID) ............................................................................... 1019
23.2.2 Emulation Management Register (EMUMGT) ............................................................. 1019
23.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ............................................ 1020
23.2.4 GPIO Data and Direction Register (GPDATGPDIR) ..................................................... 1021
23.2.5 Timer Counter Registers (TIM12 and TIM34) ............................................................. 1022
23.2.6 Timer Period Registers (PRD12 and PRD34) ............................................................. 1023
23.2.7 Timer Control Register (TCR) ............................................................................... 1024
23.2.8 Timer Global Control Register (TGCR)..................................................................... 1026
23.2.9 Watchdog Timer Control Register (WDTCR) .............................................................. 1027
23.2.10 Timer Reload Register 12 (REL12) ....................................................................... 1028
23.2.11 Timer Reload Register 34 (REL34) ....................................................................... 1028
23.2.12 Timer Capture Register 12 (CAP12) ...................................................................... 1029
23.2.13 Timer Capture Register 34 (CAP34) ...................................................................... 1029
23.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) .......................................... 1030
Universal Asynchronous Receiver/Transmitter (UART)
24.1
24.2
....................................................... 1032
Introduction ...............................................................................................................
24.1.1 Purpose of the Peripheral ....................................................................................
24.1.2 Features ........................................................................................................
24.1.3 Functional Block Diagram ....................................................................................
24.1.4 Industry Standard(s) Compliance Statement ..............................................................
Peripheral Architecture .................................................................................................
24.2.1 Clock Generation and Control ...............................................................................
24.2.2 Signal Descriptions............................................................................................
24.2.3 Pin Multiplexing ................................................................................................
SPRUH84C – April 2013 – Revised September 2016
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Contents
1033
1033
1033
1033
1033
1035
1035
1037
1037
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24.3
25
1037
1039
1043
1043
1043
1045
1045
1045
1045
1046
1047
1048
1049
1050
1051
1053
1055
1056
1059
1060
1060
1062
1063
1064
.......................................................................... 1065
Introduction ............................................................................................................... 1066
25.1.1 Purpose of the Peripheral .................................................................................... 1066
25.1.2 Features ........................................................................................................ 1066
25.1.3 Functional Block Diagram .................................................................................... 1066
25.1.4 Industry Standard(s) Compliance Statement .............................................................. 1067
Architecture .............................................................................................................. 1067
25.2.1 Clock Control .................................................................................................. 1067
25.2.2 Signal Descriptions............................................................................................ 1068
25.2.3 Indexed and Non-Indexed Registers ....................................................................... 1068
25.2.4 USB PHY Initialization ........................................................................................ 1069
25.2.5 VBUS Voltage Sourcing Control ............................................................................ 1069
25.2.6 Dynamic FIFO Sizing ......................................................................................... 1069
25.2.7 USB Controller Host and Peripheral Modes Operation .................................................. 1070
25.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ............................ 1106
25.2.9 Test Modes..................................................................................................... 1130
25.2.10 Reset Considerations ....................................................................................... 1132
25.2.11 Interrupt Support ............................................................................................. 1132
25.2.12 DMA Event Support ......................................................................................... 1132
25.2.13 Power Management ......................................................................................... 1132
Use Cases................................................................................................................ 1133
25.3.1 User Case 1: Example of How to Initialize the USB Controller ......................................... 1133
25.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode ................. 1137
25.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode........................ 1138
25.3.4 User Case 4: Example of How to Program the USB DMA Controller .................................. 1140
Registers ................................................................................................................. 1145
25.4.1 Revision Identification Register (REVID) ................................................................... 1152
25.4.2 Control Register (CTRLR).................................................................................... 1152
25.4.3 Status Register (STATR) ..................................................................................... 1153
Universal Serial Bus 2.0 (USB) Controller
25.1
25.2
25.3
25.4
16
24.2.4 Protocol Description ..........................................................................................
24.2.5 Operation .......................................................................................................
24.2.6 Reset Considerations .........................................................................................
24.2.7 Initialization .....................................................................................................
24.2.8 Interrupt Support ..............................................................................................
24.2.9 DMA Event Support ...........................................................................................
24.2.10 Power Management .........................................................................................
24.2.11 Emulation Considerations ..................................................................................
24.2.12 Exception Processing .......................................................................................
Registers .................................................................................................................
24.3.1 Receiver Buffer Register (RBR) .............................................................................
24.3.2 Transmitter Holding Register (THR) ........................................................................
24.3.3 Interrupt Enable Register (IER) .............................................................................
24.3.4 Interrupt Identification Register (IIR) ........................................................................
24.3.5 FIFO Control Register (FCR) ................................................................................
24.3.6 Line Control Register (LCR) .................................................................................
24.3.7 Modem Control Register (MCR) .............................................................................
24.3.8 Line Status Register (LSR) ..................................................................................
24.3.9 Modem Status Register (MSR) ..............................................................................
24.3.10 Scratch Pad Register (SCR) ...............................................................................
24.3.11 Divisor Latches (DLL and DLH) ............................................................................
24.3.12 Revision Identification Registers (REVID1 and REVID2) ..............................................
24.3.13 Power and Emulation Management Register (PWREMU_MGMT) ...................................
24.3.14 Mode Definition Register (MDR) ...........................................................................
Contents
SPRUH84C – April 2013 – Revised September 2016
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25.4.4
25.4.5
25.4.6
25.4.7
25.4.8
25.4.9
25.4.10
25.4.11
25.4.12
25.4.13
25.4.14
25.4.15
25.4.16
25.4.17
25.4.18
25.4.19
25.4.20
25.4.21
25.4.22
25.4.23
25.4.24
25.4.25
25.4.26
25.4.27
25.4.28
25.4.29
25.4.30
25.4.31
25.4.32
25.4.33
25.4.34
25.4.35
25.4.36
25.4.37
25.4.38
25.4.39
25.4.40
25.4.41
25.4.42
25.4.43
25.4.44
25.4.45
25.4.46
25.4.47
25.4.48
25.4.49
25.4.50
25.4.51
25.4.52
25.4.53
25.4.54
25.4.55
25.4.56
Emulation Register (EMUR) .................................................................................
Mode Register (MODE) ......................................................................................
Auto Request Register (AUTOREQ) .......................................................................
SRP Fix Time Register (SRPFIXTIME) ....................................................................
Teardown Register (TEARDOWN)..........................................................................
USB Interrupt Source Register (INTSRCR) ...............................................................
USB Interrupt Source Set Register (INTSETR)..........................................................
USB Interrupt Source Clear Register (INTCLRR) .......................................................
USB Interrupt Mask Register (INTMSKR) ................................................................
USB Interrupt Mask Set Register (INTMSKSETR) ......................................................
USB Interrupt Mask Clear Register (INTMSKCLRR) ...................................................
USB Interrupt Source Masked Register (INTMASKEDR) ..............................................
USB End of Interrupt Register (EOIR) ....................................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) .................................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) .................................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) .................................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) .................................................
Function Address Register (FADDR) .....................................................................
Power Management Register (POWER) .................................................................
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .............................................
Interrupt Enable Register for INTRTX (INTRTXE) ......................................................
Interrupt Enable Register for INTRRX (INTRRXE) ......................................................
Interrupt Register for Common USB Interrupts (INTRUSB)............................................
Interrupt Enable Register for INTRUSB (INTRUSBE) ..................................................
Frame Number Register (FRAME) ........................................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)..................
Register to Enable the USB 2.0 Test Modes (TESTMODE) ...........................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)...........................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..........................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...............................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ..........................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...............................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ...........................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..........................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...............................
Count 0 Register (COUNT0) ...............................................................................
Receive Count Register (RXCOUNT) .....................................................................
Type Register (Host mode only) (HOST_TYPE0) ......................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) .........................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ..........................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .........................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................
Configuration Data Register (CONFIGDATA) ...........................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .........................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .........................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .........................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .........................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .........................................
Device Control Register (DEVCTL) .......................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ)...............................................................
Receive Endpoint FIFO Size (RXFIFOSZ) ...............................................................
SPRUH84C – April 2013 – Revised September 2016
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Contents
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1154
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1157
1158
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1191
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25.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR) ......................................................
25.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) ......................................................
25.4.59 Hardware Version Register (HWVERS) ..................................................................
25.4.60 Transmit Function Address (TXFUNCADDR) ............................................................
25.4.61 Transmit Hub Address (TXHUBADDR) ...................................................................
25.4.62 Transmit Hub Port (TXHUBPORT) ........................................................................
25.4.63 Receive Function Address (RXFUNCADDR) ............................................................
25.4.64 Receive Hub Address (RXHUBADDR) ...................................................................
25.4.65 Receive Hub Port (RXHUBPORT) ........................................................................
25.4.66 CDMA Revision Identification Register (DMAREVID) ..................................................
25.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ................................
25.4.68 CDMA Emulation Control Register (DMAEMU) .........................................................
25.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3]) ...............
25.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3]) ...............
25.4.71 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]RXHPCRA[3]) ...................................................................................................
25.4.72 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]RXHPCRB[3]) ...................................................................................................
25.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL) ............................................
25.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63]) ...................................
25.4.75 Queue Manager Revision Identification Register (QMGRREVID) ....................................
25.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................
25.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ...................
25.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ...................
25.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ...................
25.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ...................
25.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ..................
25.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ..............................
25.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ..................
25.4.84 Queue Manager Queue Pending Register 0 (PEND0) .................................................
25.4.85 Queue Manager Queue Pending Register 1 (PEND1) .................................................
25.4.86 Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]QMEMRBASE[15]) .............................................................................................
25.4.87 Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ...
25.4.88 Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]) ..............................
25.4.89 Queue Manager Queue N Status Register A (QSTATA[0]-QSTATA[63]) ...........................
25.4.90 Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) ...........................
25.4.91 Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) ...........................
1193
1193
1194
1195
1195
1195
1196
1196
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1197
1198
1198
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1200
1201
1202
1202
1204
1204
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1208
1209
1209
1210
1210
1211
1212
1213
1214
1214
1215
Revision History ...................................................................................................................... 1216
18
Contents
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
1-1.
AM1802 ARM Microprocessor Block Diagram ......................................................................... 57
3-1.
System Interconnect Block Diagram ..................................................................................... 67
5-1.
MPU Block Diagram
5-2.
Permission Fields
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
....................................................................................................... 71
.......................................................................................................... 73
Revision ID Register (REVID) ............................................................................................ 79
Configuration Register (CONFIG) ........................................................................................ 79
Interrupt Raw Status/Set Register (IRAWSTAT) ....................................................................... 80
Interrupt Enable Status/Clear Register (IENSTAT) .................................................................... 81
Interrupt Enable Set Register (IENSET) ................................................................................ 82
Interrupt Enable Clear Register (IENCLR) .............................................................................. 82
Fixed Range Start Address Register (FXD_MPSAR) ................................................................. 83
Fixed Range End Address Register (FXD_MPEAR) .................................................................. 83
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .......................................... 84
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) ....................................... 85
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) ....................................... 85
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) ........................................ 86
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ........................................ 86
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) .......................... 87
Fault Address Register (FLTADDRR) ................................................................................... 88
Fault Status Register (FLTSTAT) ........................................................................................ 89
Fault Clear Register (FLTCLR) ........................................................................................... 90
Overall Clocking Diagram ................................................................................................. 93
USB Clocking Diagram .................................................................................................... 95
DDR2/mDDR Memory Controller Clocking Diagram .................................................................. 97
EMIFA Clocking Diagram ................................................................................................. 98
EMAC Clocking Diagram .................................................................................................. 99
McASP Clocking Diagram ............................................................................................... 100
PLLC Structure ............................................................................................................ 104
PLLC0 Revision Identification Register (REVID) ..................................................................... 109
PLLC1 Revision Identification Register (REVID) ..................................................................... 110
Reset Type Status Register (RSTYPE) ................................................................................ 110
Reset Control Register (RSCTRL) ..................................................................................... 111
PLLC0 Control Register (PLLCTL) ..................................................................................... 112
PLLC1 Control Register (PLLCTL) ..................................................................................... 113
PLLC0 OBSCLK Select Register (OCSEL) ........................................................................... 114
PLLC1 OBSCLK Select Register (OCSEL) ........................................................................... 115
PLL Multiplier Control Register (PLLM) ................................................................................ 116
PLLC0 Pre-Divider Control Register (PREDIV) ....................................................................... 116
PLLC0 Divider 1 Register (PLLDIV1) .................................................................................. 117
PLLC1 Divider 1 Register (PLLDIV1) .................................................................................. 117
PLLC0 Divider 2 Register (PLLDIV2) ................................................................................. 118
PLLC1 Divider 2 Register (PLLDIV2) ................................................................................. 118
PLLC0 Divider 3 Register (PLLDIV3) ................................................................................. 119
PLLC1 Divider 3 Register (PLLDIV3) ................................................................................. 119
PLLC0 Divider 4 Register (PLLDIV4) .................................................................................. 120
PLLC0 Divider 5 Register (PLLDIV5) .................................................................................. 120
PLLC0 Divider 6 Register (PLLDIV6) .................................................................................. 121
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
19
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7-21.
PLLC0 Divider 7 Register (PLLDIV7) .................................................................................. 121
7-22.
PLLC0 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 122
7-23.
PLLC1 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 122
7-24.
PLL Post-Divider Control Register (POSTDIV) ....................................................................... 123
7-25.
PLL Controller Command Register (PLLCMD)
123
7-26.
PLL Controller Status Register (PLLSTAT)
124
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
9-1.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
20
.......................................................................
...........................................................................
PLLC0 Clock Align Control Register (ALNCTL) ......................................................................
PLLC1 Clock Align Control Register (ALNCTL) ......................................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC0 Clock Enable Control Register (CKEN) .......................................................................
PLLC1 Clock Enable Control Register (CKEN) .......................................................................
PLLC0 Clock Status Register (CKSTAT) ..............................................................................
PLLC1 Clock Status Register (CKSTAT) ..............................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ..........................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ..........................................................................
Emulation Performance Counter 0 Register (EMUCNT0) ...........................................................
Emulation Performance Counter 1 Register (EMUCNT1) ...........................................................
Revision Identification Register (REVID) ..............................................................................
Interrupt Evaluation Register (INTEVAL) ..............................................................................
PSC0 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC1 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC0 Module Error Clear Register 0 (MERRCR0) ..................................................................
PSC1 Module Error Clear Register 0 (MERRCR0) ..................................................................
Power Error Pending Register (PERRPR) ............................................................................
Power Error Clear Register (PERRCR) ................................................................................
Power Domain Transition Command Register (PTCMD)............................................................
Power Domain Transition Status Register (PTSTAT) ................................................................
Power Domain 0 Status Register (PDSTAT0) ........................................................................
Power Domain 1 Status Register (PDSTAT1) ........................................................................
Power Domain 0 Control Register (PDCTL0) .........................................................................
Power Domain 1 Control Register (PDCTL1) .........................................................................
Power Domain 0 Configuration Register (PDCFG0) .................................................................
Power Domain 1 Configuration Register (PDCFG1) .................................................................
Module Status n Register (MDSTATn) .................................................................................
PSC0 Module Control n Register (MDCTLn) .........................................................................
PSC1 Module Control n Register (MDCTLn) .........................................................................
Deep Sleep Mode Sequence ............................................................................................
Revision Identification Register (REVID) ..............................................................................
Device Identification Register 0 (DEVIDR0) ...........................................................................
Boot Configuration Register (BOOTCFG) .............................................................................
Chip Revision Identification Register (CHIPREVIDR)................................................................
Kick 0 Register (KICK0R) ................................................................................................
Kick 1 Register (KICK1R) ................................................................................................
Host 0 Configuration Register (HOST0CFG) .........................................................................
Interrupt Raw Status/Set Register (IRAWSTAT) .....................................................................
Interrupt Enable Status/Clear Register (IENSTAT)...................................................................
Interrupt Enable Register (IENSET) ....................................................................................
Interrupt Enable Clear Register (IENCLR) ............................................................................
List of Figures
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126
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128
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129
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SPRUH84C – April 2013 – Revised September 2016
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.........................................................................................
Fault Address Register (FLTADDRR) ..................................................................................
Fault Status Register (FLTSTAT) .......................................................................................
Master Priority 0 Register (MSTPRI0) .................................................................................
Master Priority 1 Register (MSTPRI1) .................................................................................
Master Priority 2 Register (MSTPRI2) .................................................................................
Pin Multiplexing Control 0 Register (PINMUX0) ......................................................................
Pin Multiplexing Control 1 Register (PINMUX1) ......................................................................
Pin Multiplexing Control 2 Register (PINMUX2) ......................................................................
Pin Multiplexing Control 3 Register (PINMUX3) ......................................................................
Pin Multiplexing Control 4 Register (PINMUX4) ......................................................................
Pin Multiplexing Control 5 Register (PINMUX5) ......................................................................
Pin Multiplexing Control 6 Register (PINMUX6) ......................................................................
Pin Multiplexing Control 7 Register (PINMUX7) ......................................................................
Pin Multiplexing Control 8 Register (PINMUX8) ......................................................................
Pin Multiplexing Control 9 Register (PINMUX9) ......................................................................
Pin Multiplexing Control 10 Register (PINMUX10) ...................................................................
Pin Multiplexing Control 11 Register (PINMUX11) ...................................................................
Pin Multiplexing Control 12 Register (PINMUX12) ...................................................................
Pin Multiplexing Control 13 Register (PINMUX13) ...................................................................
Pin Multiplexing Control 14 Register (PINMUX14) ...................................................................
Pin Multiplexing Control 15 Register (PINMUX15) ...................................................................
Pin Multiplexing Control 16 Register (PINMUX16) ...................................................................
Pin Multiplexing Control 17 Register (PINMUX17) ...................................................................
Pin Multiplexing Control 18 Register (PINMUX18) ...................................................................
Pin Multiplexing Control 19 Register (PINMUX19) ...................................................................
Suspend Source Register (SUSPSRC) ................................................................................
Chip Signal Register (CHIPSIG) ........................................................................................
Chip Signal Clear Register (CHIPSIG_CLR) ..........................................................................
Chip Configuration 0 Register (CFGCHIP0) ..........................................................................
Chip Configuration 1 Register (CFGCHIP1) ..........................................................................
Chip Configuration 2 Register (CFGCHIP2) ..........................................................................
Chip Configuration 3 Register (CFGCHIP3) ..........................................................................
Chip Configuration 4 Register (CFGCHIP4) ..........................................................................
VTP I/O Control Register (VTPIO_CTL) ...............................................................................
DDR Slew Register (DDR_SLEW) .....................................................................................
Deep Sleep Register (DEEPSLEEP) ...................................................................................
Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................................
Pullup/Pulldown Select Register (PUPD_SEL) .......................................................................
RXACTIVE Control Register (RXACTIVE) ............................................................................
AINTC Interrupt Mapping ................................................................................................
Flow of System Interrupts to Host ......................................................................................
Revision Identification Register (REVID) ..............................................................................
Control Register (CR) ....................................................................................................
Global Enable Register (GER) ..........................................................................................
Global Nesting Level Register (GNLR) ................................................................................
System Interrupt Status Indexed Set Register (SISR) ...............................................................
System Interrupt Status Indexed Clear Register (SICR) ............................................................
System Interrupt Enable Indexed Set Register (EISR) ..............................................................
10-12. End of Interrupt Register (EOI)
185
10-13.
185
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
186
187
188
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11-10. System Interrupt Enable Indexed Clear Register (EICR) ............................................................ 258
11-11. Host Interrupt Enable Indexed Set Register (HEISR) ................................................................ 259
11-12. Host Interrupt Enable Indexed Clear Register (HIEICR)
............................................................
259
11-13. Vector Base Register (VBR)............................................................................................. 260
11-14. Vector Size Register (VSR)
.............................................................................................
260
11-15. Vector Null Register (VNR) .............................................................................................. 261
11-16. Global Prioritized Index Register (GPIR) .............................................................................. 261
11-17. Global Prioritized Vector Register (GPVR) ............................................................................ 262
11-18. System Interrupt Status Raw/Set Register 1 (SRSR1) .............................................................. 262
11-19. System Interrupt Status Raw/Set Register 2 (SRSR2) .............................................................. 263
11-20. System Interrupt Status Raw/Set Register 3 (SRSR3) .............................................................. 263
11-21. System Interrupt Status Raw/Set Register 4 (SRSR4) .............................................................. 264
11-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) ....................................................... 264
11-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) ....................................................... 265
11-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) ....................................................... 265
11-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) ....................................................... 266
11-26. System Interrupt Enable Set Register 1 (ESR1)...................................................................... 266
11-27. System Interrupt Enable Set Register 2 (ESR2)...................................................................... 267
11-28. System Interrupt Enable Set Register 3 (ESR3)...................................................................... 267
11-29. System Interrupt Enable Set Register 4 (ESR4)...................................................................... 268
11-30. System Interrupt Enable Clear Register 1 (ECR1) ................................................................... 268
11-31. System Interrupt Enable Clear Register 2 (ECR2) ................................................................... 269
11-32. System Interrupt Enable Clear Register 3 (ECR3) ................................................................... 269
11-33. System Interrupt Enable Clear Register 4 (ECR4) ................................................................... 270
11-34. Channel Map Registers (CMRn) ........................................................................................ 270
11-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) ................................................................. 271
11-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) ................................................................. 271
11-37. Host Interrupt Nesting Level Register 1 (HINLR1) ................................................................... 272
11-38. Host Interrupt Nesting Level Register 2 (HINLR2) ................................................................... 272
11-39. Host Interrupt Enable Register (HIER) ................................................................................. 273
11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) ............................................................... 274
11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) ............................................................... 274
13-1.
Data Paths to DDR2/mDDR Memory Controller ...................................................................... 279
13-2.
DDR2/mDDR Memory Controller Clock Block Diagram ............................................................. 280
13-3.
DDR2/mDDR Memory Controller Signals
13-4.
Refresh Command........................................................................................................ 284
13-5.
DCAB Command.......................................................................................................... 285
13-6.
DEAC Command.......................................................................................................... 286
13-7.
ACTV Command .......................................................................................................... 287
13-8.
DDR2/mDDR READ Command......................................................................................... 288
13-9.
DDR2/mDDR WRT Command .......................................................................................... 289
.............................................................................
281
13-10. DDR2/mDDR MRS and EMRS Command ............................................................................ 290
13-11. Byte Alignment ............................................................................................................ 290
13-12. DDR2/mDDR SDRAM Column, Row, and Bank Access ............................................................ 294
13-13. Address Mapping Diagram (IBANKPOS = 1) ......................................................................... 295
13-14. SDRAM Column, Row, Bank Access (IBANKPOS = 1) ............................................................. 296
13-15. DDR2/mDDR Memory Controller FIFO Block Diagram .............................................................. 297
13-16. DDR2/mDDR Memory Controller Reset Block Diagram ............................................................. 301
13-17. DDR2/mDDR Memory Controller Power Sleep Controller Diagram
22
List of Figures
...............................................
306
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13-18. Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory ......................................... 308
13-19. Revision ID Register (REVID) ........................................................................................... 313
.................................................................................
..............................................................................
SDRAM Refresh Control Register (SDRCR) .........................................................................
SDRAM Timing Register 1 (SDTIMR1) ................................................................................
SDRAM Timing Register 2 (SDTIMR2) ................................................................................
SDRAM Configuration Register 2 (SDCR2) ..........................................................................
Peripheral Bus Burst Priority Register (PBBPR) ......................................................................
Performance Counter 1 Register (PC1) ...............................................................................
Performance Counter 2 Register (PC2) ...............................................................................
Performance Counter Configuration Register (PCC) ................................................................
Performance Counter Master Region Select Register (PCMRS) ..................................................
Performance Counter Time Register (PCT) ...........................................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) ............................................................................................
Interrupt Masked Register (IMR)........................................................................................
Interrupt Mask Set Register (IMSR) ....................................................................................
Interrupt Mask Clear Register (IMCR) .................................................................................
DDR PHY Control Register 1 (DRPYC1R) ............................................................................
EDMA3 Controller Block Diagram ......................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram ...........................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................
Definition of ACNT, BCNT, and CCNT ................................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................
PaRAM Set ................................................................................................................
Linked Transfer Example ................................................................................................
Link-to-Self Transfer Example ..........................................................................................
QDMA Channel to PaRAM Mapping ...................................................................................
Shadow Region Registers ...............................................................................................
Interrupt Diagram .........................................................................................................
Error Interrupt Operation .................................................................................................
EDMA3 Prioritization .....................................................................................................
Block Move Example .....................................................................................................
Block Move Example PaRAM Configuration ..........................................................................
Subframe Extraction Example ..........................................................................................
Subframe Extraction Example PaRAM Configuration................................................................
Data Sorting Example ....................................................................................................
Data Sorting Example PaRAM Configuration .........................................................................
Servicing Incoming McBSP Data Example ............................................................................
Servicing Incoming McBSP Data Example PaRAM ..................................................................
Servicing Peripheral Burst Example ....................................................................................
Servicing Peripheral Burst Example PaRAM..........................................................................
Servicing Continuous McBSP Data Example .........................................................................
Servicing Continuous McBSP Data Example PaRAM ...............................................................
Servicing Continuous McBSP Data Example Reload PaRAM ......................................................
Ping-Pong Buffering for McBSP Data Example ......................................................................
Ping-Pong Buffering for McBSP Example PaRAM ...................................................................
13-20. SDRAM Status Register (SDRSTAT)
314
13-21. SDRAM Configuration Register (SDCR)
315
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
318
319
320
321
322
323
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14-30. Ping-Pong Buffering for McBSP Example Pong PaRAM ............................................................ 393
14-31. Ping-Pong Buffering for McBSP Example Ping PaRAM ............................................................. 394
14-32. Intermediate Transfer Completion Chaining Example ............................................................... 396
.................................................................................
Smaller Packet Data Transfers Example ..............................................................................
Channel Options Parameter (OPT).....................................................................................
Channel Source Address Parameter (SRC) ..........................................................................
A Count/B Count Parameter (A_B_CNT) ..............................................................................
Channel Destination Address Parameter (DST) ......................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ...............................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) ......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ...............................................
C Count Parameter (CCNT) .............................................................................................
Revision ID Register (REVID) ...........................................................................................
EDMA3CC Configuration Register (CCCFG) .........................................................................
QDMA Channel n Mapping Register (QCHMAPn) ...................................................................
DMA Channel Queue Number Register n (DMAQNUMn) ...........................................................
QDMA Channel Queue Number Register (QDMAQNUM) ..........................................................
Event Missed Register (EMR)...........................................................................................
Event Missed Clear Register (EMCR) .................................................................................
QDMA Event Missed Register (QEMR)................................................................................
QDMA Event Missed Clear Register (QEMCR) ......................................................................
EDMA3CC Error Register (CCERR) ...................................................................................
EDMA3CC Error Clear Register (CCERRCLR).......................................................................
Error Evaluate Register (EEVAL) .......................................................................................
DMA Region Access Enable Register for Region m (DRAEm) .....................................................
QDMA Region Access Enable for Region m (QRAEm) .............................................................
Event Queue Entry Registers (QxEy) ..................................................................................
Queue n Status Register (QSTATn) ...................................................................................
Queue Watermark Threshold A Register (QWMTHRA) .............................................................
EDMA3CC Status Register (CCSTAT) ................................................................................
Event Register (ER) ......................................................................................................
Event Clear Register (ECR) .............................................................................................
Event Set Register (ESR)................................................................................................
Chained Event Register (CER) .........................................................................................
Event Enable Register (EER) ...........................................................................................
Event Enable Clear Register (EECR) ..................................................................................
Event Enable Set Register (EESR) ....................................................................................
Secondary Event Register (SER) .......................................................................................
Secondary Event Clear Register (SECR) .............................................................................
Interrupt Enable Register (IER) .........................................................................................
Interrupt Enable Clear Register (IECR) ................................................................................
Interrupt Enable Set Register (IESR) ..................................................................................
Interrupt Pending Register (IPR)........................................................................................
Interrupt Clear Register (ICR) ...........................................................................................
Interrupt Evaluate Register (IEVAL) ....................................................................................
QDMA Event Register (QER) ...........................................................................................
QDMA Event Enable Register (QEER) ................................................................................
QDMA Event Enable Clear Register (QEECR) .......................................................................
14-33. Single Large Block Transfer Example
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
24
List of Figures
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440
SPRUH84C – April 2013 – Revised September 2016
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.........................................................................
14-80. QDMA Secondary Event Register (QSER) ............................................................................
14-81. QDMA Secondary Event Clear Register (QSECR) ..................................................................
14-82. Revision ID Register (REVID) ...........................................................................................
14-83. EDMA3TC Configuration Register (TCCFG) ..........................................................................
14-84. EDMA3TC Channel Status Register (TCSTAT) ......................................................................
14-85. Error Status Register (ERRSTAT) ......................................................................................
14-86. Error Enable Register (ERREN) ........................................................................................
14-87. Error Clear Register (ERRCLR) ........................................................................................
14-88. Error Details Register (ERRDET) .......................................................................................
14-89. Error Interrupt Command Register (ERRCMD) .......................................................................
14-90. Read Command Rate Register (RDRATE)............................................................................
14-91. Source Active Options Register (SAOPT) .............................................................................
14-92. Source Active Source Address Register (SASRC) ...................................................................
14-93. Source Active Count Register (SACNT) ...............................................................................
14-94. Source Active Destination Address Register (SADST) ..............................................................
14-95. Source Active B-Index Register (SABIDX) ............................................................................
14-96. Source Active Memory Protection Proxy Register (SAMPPRXY) ..................................................
14-97. Source Active Count Reload Register (SACNTRLD) ................................................................
14-98. Source Active Source Address B-Reference Register (SASRCBREF) ............................................
14-99. Source Active Destination Address B-Reference Register (SADSTBREF) .......................................
14-100. Destination FIFO Set Count Reload Register (DFCNTRLD) ......................................................
14-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) ..................................
14-102. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) .............................
14-103. Destination FIFO Options Register n (DFOPTn) ....................................................................
14-104. Destination FIFO Source Address Register n (DFSRCn) ..........................................................
14-105. Destination FIFO Count Register n (DFCNTn) ......................................................................
14-106. Destination FIFO Destination Address Register n (DFDSTn) .....................................................
14-107. Destination FIFO B-Index Register n (DFBIDXn) ...................................................................
14-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) .........................................
15-1. EMAC and MDIO Block Diagram .......................................................................................
15-2. Ethernet Configuration—MII Connections .............................................................................
15-3. Ethernet Configuration—RMII Connections ...........................................................................
15-4. Ethernet Frame Format ..................................................................................................
15-5. Basic Descriptor Format .................................................................................................
15-6. Typical Descriptor Linked List ...........................................................................................
15-7. Transmit Buffer Descriptor Format .....................................................................................
15-8. Receive Buffer Descriptor Format ......................................................................................
15-9. EMAC Control Module Block Diagram .................................................................................
15-10. MDIO Module Block Diagram ...........................................................................................
15-11. EMAC Module Block Diagram ..........................................................................................
15-12. EMAC Control Module Revision ID Register (REVID) ...............................................................
15-13. EMAC Control Module Software Reset Register (SOFTRESET) ..................................................
15-14. EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................
14-79. QDMA Event Enable Set Register (QEESR)
440
441
442
444
445
446
447
448
449
450
451
452
453
454
454
455
455
456
457
457
458
458
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461
461
462
462
463
469
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476
477
480
483
487
489
493
515
516
517
15-15. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 518
15-16. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 519
15-17. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 520
15-18. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 521
SPRUH84C – April 2013 – Revised September 2016
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25
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15-19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 522
15-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 523
15-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 524
15-22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
.........
525
15-23. EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........ 526
15-24. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX)
.......
527
15-25. MDIO Revision ID Register (REVID) ................................................................................... 528
15-26. MDIO Control Register (CONTROL) ................................................................................... 529
15-27. PHY Acknowledge Status Register (ALIVE) .......................................................................... 530
15-28. PHY Link Status Register (LINK) ....................................................................................... 530
15-29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ...................................... 531
15-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ..................................... 532
15-31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................. 533
15-32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)............................ 534
15-33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) .......................... 535
15-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .................... 536
537
15-36.
538
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
26
...................................................................
MDIO User PHY Select Register 0 (USERPHYSEL0) ...............................................................
MDIO User Access Register 1 (USERACCESS1) ...................................................................
MDIO User PHY Select Register 1 (USERPHYSEL1) ...............................................................
Transmit Revision ID Register (TXREVID) ............................................................................
Transmit Control Register (TXCONTROL) ............................................................................
Transmit Teardown Register (TXTEARDOWN) ......................................................................
Receive Revision ID Register (RXREVID) ............................................................................
Receive Control Register (RXCONTROL) .............................................................................
Receive Teardown Register (RXTEARDOWN) .......................................................................
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)...............................................
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .............................................
Transmit Interrupt Mask Set Register (TXINTMASKSET) ...........................................................
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR).....................................................
MAC Input Vector Register (MACINVECTOR) .......................................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ...............................................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) .............................................
Receive Interrupt Mask Set Register (RXINTMASKSET) ...........................................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .....................................................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ...............................................
MAC Interrupt Mask Set Register (MACINTMASKSET) .............................................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................................
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......................
Receive Unicast Enable Set Register (RXUNICASTSET) ..........................................................
Receive Unicast Clear Register (RXUNICASTCLEAR) .............................................................
Receive Maximum Length Register (RXMAXLEN) ...................................................................
Receive Buffer Offset Register (RXBUFFEROFFSET) ..............................................................
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ..............................
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) .....................................
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ............................................
15-35. MDIO User Access Register 0 (USERACCESS0)
List of Figures
539
540
544
544
545
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555
556
557
558
558
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566
566
567
SPRUH84C – April 2013 – Revised September 2016
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15-67. MAC Control Register (MACCONTROL) .............................................................................. 568
15-68. MAC Status Register (MACSTATUS) .................................................................................. 570
15-69. Emulation Control Register (EMCONTROL) .......................................................................... 572
15-70. FIFO Control Register (FIFOCONTROL) .............................................................................. 572
15-71. MAC Configuration Register (MACCONFIG)
.........................................................................
573
15-72. Soft Reset Register (SOFTRESET) .................................................................................... 573
15-73. MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 574
15-74. MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 574
15-75. MAC Hash Address Register 1 (MACHASH1) ........................................................................ 575
15-76. MAC Hash Address Register 2 (MACHASH2) ........................................................................ 575
15-77. Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 576
15-78. Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 576
15-79. Receive Pause Timer Register (RXPAUSE) .......................................................................... 577
15-80. Transmit Pause Timer Register (TXPAUSE).......................................................................... 577
15-81. MAC Address Low Bytes Register (MACADDRLO).................................................................. 578
15-82. MAC Address High Bytes Register (MACADDRHI) .................................................................. 579
15-83. MAC Index Register (MACINDEX) ..................................................................................... 579
15-84. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) .......................................... 580
..........................................
Transmit Channel n Completion Pointer Register (TXnCP) .........................................................
Receive Channel n Completion Pointer Register (RXnCP) .........................................................
Statistics Register .........................................................................................................
EMIFA Functional Block Diagram ......................................................................................
Timing Waveform of SDRAM PRE Command ........................................................................
EMIFA to 2M × 16 × 4 bank SDRAM Interface .......................................................................
EMIFA to 512K × 16 × 2 bank SDRAM Interface ....................................................................
Timing Waveform for Basic SDRAM Read Operation ...............................................................
Timing Waveform for Basic SDRAM Write Operation ...............................................................
EMIFA Asynchronous Interface .........................................................................................
EMIFA to 8-bit/16-bit Memory Interface................................................................................
Common Asynchronous Interface ......................................................................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode..............................................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode ..............................................
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ......................................
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ......................................
EMIFA to NAND Flash Interface ........................................................................................
ECC Value for 8-Bit NAND Flash .......................................................................................
EMIFA Reset Block Diagram ............................................................................................
EMIFA PSC Block Diagram .............................................................................................
Example Configuration Interface ........................................................................................
SDRAM Timing Register (SDTIMR) ....................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................
SDRAM Refresh Control Register (SDRCR) ..........................................................................
SDRAM Configuration Register (SDCR)...............................................................................
Timing Waveform of an ASRAM Read ................................................................................
Timing Waveform of an ASRAM Write ................................................................................
Timing Waveform of an ASRAM Read with PCB Delays............................................................
Timing Waveform of an ASRAM Write with PCB Delays ............................................................
Timing Waveform of a NAND Flash Read ............................................................................
15-85. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
580
15-86.
581
15-87.
15-88.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
SPRUH84C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
581
582
592
596
597
597
604
605
607
608
608
613
615
617
619
621
623
626
631
634
635
636
636
637
639
640
642
643
648
27
www.ti.com
...............................................................
Timing Waveform of a NAND Flash Address Write .................................................................
Timing Waveform of a NAND Flash Data Write .....................................................................
Module ID Register (MIDR)..............................................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) .......................................................
SDRAM Configuration Register (SDCR)...............................................................................
SDRAM Refresh Control Register (SDRCR) ..........................................................................
Asynchronous n Configuration Register (CEnCFG) ..................................................................
SDRAM Timing Register (SDTIMR) ....................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................
EMIFA Interrupt Raw Register (INTRAW) .............................................................................
EMIFA Interrupt Mask Register (INTMSK) ............................................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) ..................................................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) ................................................................
NAND Flash Control Register (NANDFCR) ...........................................................................
NAND Flash Status Register (NANDFSR) ............................................................................
NAND Flash n ECC Register (NANDFnECC) ........................................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ..................................................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..............................................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..............................................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..............................................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..............................................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1).............................................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2).............................................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ................................................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ................................................
GPIO Block Diagram .....................................................................................................
Revision ID Register (REVID) ...........................................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) ................................................................
GPIO Banks 0 and 1 Direction Register (DIR01) .....................................................................
GPIO Banks 2 and 3 Direction Register (DIR23) .....................................................................
GPIO Banks 4 and 5 Direction Register (DIR45) .....................................................................
GPIO Banks 6 and 7 Direction Register (DIR67) .....................................................................
GPIO Bank 8 Direction Register (DIR8) ...............................................................................
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) .......................................................
GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) .......................................................
GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) .......................................................
GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) .......................................................
GPIO Bank 8 Output Data Register (OUT_DATA8) .................................................................
GPIO Banks 0 and 1 Set Data Register (SET_DATA01)............................................................
GPIO Banks 2 and 3 Set Data Register (SET_DATA23)............................................................
GPIO Banks 4 and 5 Set Data Register (SET_DATA45)............................................................
GPIO Banks 6 and 7 Set Data Register (SET_DATA67)............................................................
GPIO Bank 8 Set Data Register (SET_DATA8) ......................................................................
GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) .........................................................
GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .........................................................
GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) .........................................................
GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) .........................................................
GPIO Bank 8 Clear Data Register (CLR_DATA8) ...................................................................
16-28. Timing Waveform of a NAND Flash Command Write
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
28
List of Figures
650
650
651
656
656
658
660
661
663
664
665
666
667
668
669
671
672
673
674
674
675
675
676
676
677
677
680
689
690
691
691
691
691
692
693
693
693
693
694
695
695
695
695
696
697
697
697
697
698
SPRUH84C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
17-24. GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ............................................................ 699
17-25. GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ............................................................ 699
17-26. GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ............................................................ 699
17-27. GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ............................................................ 699
17-28. GPIO Bank 8 Input Data Register (IN_DATA8)....................................................................... 700
17-29. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01) ............................................. 701
17-30. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) ............................................. 701
17-31. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) ............................................. 701
17-32. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) ............................................. 701
17-33. GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) ........................................................ 702
17-34. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ........................................... 703
17-35. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) ........................................... 703
17-36. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ........................................... 703
17-37. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ........................................... 703
17-38. GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) ..................................................... 704
17-39. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) ............................................. 705
17-40. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) ............................................. 705
17-41. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) ............................................. 705
17-42. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) ............................................. 705
17-43. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8) ....................................................... 706
17-44. GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) .......................................... 707
17-45. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) .......................................... 707
17-46. GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) .......................................... 707
17-47. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) .......................................... 707
17-48. GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) ..................................................... 708
17-49. GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ...................................................... 709
17-50. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ...................................................... 709
17-51. GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) ...................................................... 709
17-52. GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) ...................................................... 709
17-53. GPIO Bank 8 Interrupt Status Register (INTSTAT8) ................................................................. 710
18-1.
I2C Peripheral Block Diagram........................................................................................... 713
18-2.
Multiple I2C Modules Connected ....................................................................................... 714
18-3.
Clocking Diagram for the I2C Peripheral .............................................................................. 715
18-4.
Synchronization of Two I2C Clock Generators During Arbitration
18-5.
18-6.
18-7.
18-8.
18-9.
.................................................
Bit Transfer on the I2C-Bus .............................................................................................
I2C Peripheral START and STOP Conditions ........................................................................
I2C Peripheral Data Transfer ............................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) ............................................
716
717
717
718
718
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR)......................................................................................................... 719
18-10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR) .............................................................. 719
18-11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR)
...
719
18-12. Arbitration Procedure Between Two Master-Transmitters........................................................... 722
18-13. I2C Own Address Register (ICOAR) ................................................................................... 727
18-14. I2C Interrupt Mask Register (ICIMR) ................................................................................... 728
18-15. I2C Interrupt Status Register (ICSTR) ................................................................................. 729
18-16. I2C Clock Low-Time Divider Register (ICCLKL) ...................................................................... 732
18-17. I2C Clock High-Time Divider Register (ICCLKH) ..................................................................... 732
18-18. I2C Data Count Register (ICCNT) ...................................................................................... 733
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
29
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18-19. I2C Data Receive Register (ICDRR) ................................................................................... 734
18-20. I2C Slave Address Register (ICSAR) .................................................................................. 735
18-21. I2C Data Transmit Register (ICDXR)
..................................................................................
736
18-22. I2C Mode Register (ICMDR) ............................................................................................ 737
18-23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit .................................... 740
18-24. I2C Interrupt Vector Register (ICIVR) .................................................................................. 741
18-25. I2C Extended Mode Register (ICEMDR) .............................................................................. 742
18-26. I2C Prescaler Register (ICPSC) ........................................................................................ 743
744
18-28.
744
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
30
.....................................................................
I2C Revision Identification Register 2 (REVID2) .....................................................................
I2C DMA Control Register (ICDMAC) ..................................................................................
I2C Pin Function Register (ICPFUNC) .................................................................................
I2C Pin Direction Register (ICPDIR) ...................................................................................
I2C Pin Data In Register (ICPDIN) .....................................................................................
I2C Pin Data Out Register (ICPDOUT) ................................................................................
I2C Pin Data Set Register (ICPDSET) .................................................................................
I2C Pin Data Clear Register (ICPDCLR) ..............................................................................
McASP Block Diagram ...................................................................................................
McASP to Parallel 2-Channel DACs ..................................................................................
McASP to 6-Channel DAC and 2-Channel DAC .....................................................................
McASP to Digital Amplifier ...............................................................................................
McASP as Digital Audio Encoder ......................................................................................
TDM Format–6 Channel TDM Example ...............................................................................
TDM Format Bit Delays from Frame Sync ............................................................................
Inter-IC Sound (I2S) Format .............................................................................................
Biphase-Mark Code (BMC) ..............................................................................................
S/PDIF Subframe Format ................................................................................................
S/PDIF Frame Format ....................................................................................................
Definition of Bit, Word, and Slot ........................................................................................
Bit Order and Word Alignment Within a Slot Examples .............................................................
Definition of Frame and Frame Sync Width ...........................................................................
Transmit Clock Generator Block Diagram .............................................................................
Receive Clock Generator Block Diagram ..............................................................................
Frame Sync Generator Block Diagram ...............................................................................
Individual Serializer and Connections Within McASP ................................................................
Receive Format Unit......................................................................................................
Transmit Format Unit .....................................................................................................
McASP I/O Pin Control Block Diagram ................................................................................
McASP I/O Pin to Control Register Mapping..........................................................................
Burst Frame Sync Mode .................................................................................................
Transmit DMA Event (AXEVT) Generation in TDM Time Slots ....................................................
DSP Service Time Upon Transmit DMA Event (AXEVT)............................................................
DSP Service Time Upon Receive DMA Event (AREVT) ............................................................
DMA Events in an Audio Example–Two Events ......................................................................
McASP Audio FIFO (AFIFO) Block Diagram ..........................................................................
Data Flow Through Transmit Format Unit .............................................................................
Data Flow Through Receive Format Unit ..............................................................................
Audio Mute (AMUTE) Block Diagram ..................................................................................
Transmit Clock Failure Detection Circuit Block Diagram ............................................................
18-27. I2C Revision Identification Register 1 (REVID1)
List of Figures
745
746
747
748
749
750
751
755
756
756
757
757
758
759
759
760
761
762
763
764
765
767
768
769
770
771
772
774
775
780
783
788
790
792
793
796
798
800
804
SPRUH84C – April 2013 – Revised September 2016
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19-33. Receive Clock Failure Detection Circuit Block Diagram ............................................................. 805
19-34. Serializers in Loopback Mode ........................................................................................... 806
19-35. Revision Identification Register (REV) ................................................................................. 812
........................................................................................
Pin Direction Register (PDIR) ...........................................................................................
Pin Data Output Register (PDOUT) ....................................................................................
Pin Data Input Register (PDIN) .........................................................................................
Pin Data Set Register (PDSET).........................................................................................
Pin Data Clear Register (PDCLR) ......................................................................................
Global Control Register (GBLCTL) .....................................................................................
Audio Mute Control Register (AMUTE) ................................................................................
Digital Loopback Control Register (DLBCTL) .........................................................................
Digital Mode Control Register (DITCTL) ...............................................................................
Receiver Global Control Register (RGBLCTL) ........................................................................
Receive Format Unit Bit Mask Register (RMASK) ...................................................................
Receive Bit Stream Format Register (RFMT) .........................................................................
Receive Frame Sync Control Register (AFSRCTL) ..................................................................
Receive Clock Control Register (ACLKRCTL) ........................................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ..................................................
Receive TDM Time Slot Register (RTDM) ............................................................................
Receiver Interrupt Control Register (RINTCTL) ......................................................................
Receiver Status Register (RSTAT) .....................................................................................
Current Receive TDM Time Slot Registers (RSLOT) ................................................................
Receive Clock Check Control Register (RCLKCHK) .................................................................
Receiver DMA Event Control Register (REVTCTL) ..................................................................
Transmitter Global Control Register (XGBLCTL) .....................................................................
Transmit Format Unit Bit Mask Register (XMASK) ...................................................................
Transmit Bit Stream Format Register (XFMT) ........................................................................
Transmit Frame Sync Control Register (AFSXCTL) .................................................................
Transmit Clock Control Register (ACLKXCTL) .......................................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) .................................................
Transmit TDM Time Slot Register (XTDM) ............................................................................
Transmitter Interrupt Control Register (XINTCTL)....................................................................
Transmitter Status Register (XSTAT) ..................................................................................
Current Transmit TDM Time Slot Register (XSLOT) .................................................................
Transmit Clock Check Control Register (XCLKCHK) ................................................................
Transmitter DMA Event Control Register (XEVTCTL) ...............................................................
Serializer Control Registers (SRCTLn) ................................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .......................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) .....................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ..................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ................................................
Transmit Buffer Registers (XBUFn) ....................................................................................
Receive Buffer Registers (RBUFn) .....................................................................................
AFIFO Revision Identification Register (AFIFOREV) ................................................................
Write FIFO Control Register (WFIFOCTL) ............................................................................
Write FIFO Status Register (WFIFOSTS) .............................................................................
Read FIFO Control Register (RFIFOCTL) .............................................................................
Read FIFO Status Register (RFIFOSTS) ..............................................................................
19-36. Pin Function Register (PFUNC)
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
19-73.
19-74.
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
813
815
817
819
821
823
825
827
829
830
831
832
833
835
836
837
838
839
840
841
842
843
844
845
846
848
849
850
851
852
853
854
855
856
857
858
858
859
859
860
860
861
862
863
864
865
31
www.ti.com
20-1.
MMC/SD Card Controller Block Diagram .............................................................................. 867
20-2.
MMC/SD Controller Interface Diagram................................................................................. 868
20-3.
MMC Configuration and SD Configuration Diagram ................................................................. 869
20-4.
MMC/SD Controller Clocking Diagram ................................................................................. 870
20-5.
MMC/SD Mode Write Sequence Timing Diagram .................................................................... 871
20-6.
MMC/SD Mode Read Sequence Timing Diagram .................................................................... 872
20-7.
FIFO Operation Diagram
20-8.
Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA ....................................... 874
20-9.
FIFO Operation During Card Read Diagram .......................................................................... 876
................................................................................................
873
20-10. FIFO Operation During Card Write Diagram .......................................................................... 878
20-11. MMC Card Identification Procedure .................................................................................... 885
20-12. SD Card Identification Procedure ....................................................................................... 886
20-13. MMC/SD Mode Single-Block Write Operation ........................................................................ 888
20-14. MMC/SD Mode Single-Block Read Operation ........................................................................ 890
20-15. MMC/SD Multiple-Block Write Operation .............................................................................. 892
20-16. MMC/SD Mode Multiple-Block Read Operation ...................................................................... 894
20-17. MMC Control Register (MMCCTL)
.....................................................................................
897
20-18. MMC Memory Clock Control Register (MMCCLK) ................................................................... 898
20-19. MMC Status Register 0 (MMCST0) .................................................................................... 899
20-20. MMC Status Register 1 (MMCST1) .................................................................................... 901
20-21. MMC Interrupt Mask Register (MMCIM) ............................................................................... 902
20-22. MMC Response Time-Out Register (MMCTOR) ..................................................................... 904
905
20-24. MMC Block Length Register (MMCBLEN)
906
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
32
....................................................................
............................................................................
MMC Number of Blocks Register (MMCNBLK) .......................................................................
MMC Number of Blocks Counter Register (MMCNBLC) ............................................................
MMC Data Receive Register (MMCDRR) .............................................................................
MMC Data Transmit Register (MMCDXR) ............................................................................
MMC Command Register (MMCCMD).................................................................................
Command Format ........................................................................................................
MMC Argument Register (MMCARGHL) ..............................................................................
MMC Response Register 0 and 1 (MMCRSP01) ....................................................................
MMC Response Register 2 and 3 (MMCRSP23) ....................................................................
MMC Response Register 4 and 5 (MMCRSP45) ....................................................................
MMC Response Register 6 and 7 (MMCRSP67) ....................................................................
MMC Data Response Register (MMCDRSP) .........................................................................
MMC Command Index Register (MMCCIDX) .........................................................................
SDIO Control Register (SDIOCTL) .....................................................................................
SDIO Status Register 0 (SDIOST0) ....................................................................................
SDIO Interrupt Enable Register (SDIOIEN) ...........................................................................
SDIO Interrupt Status Register (SDIOIST) ............................................................................
MMC FIFO Control Register (MMCFIFOCTL) ........................................................................
Real-Time Clock Block Diagram ........................................................................................
32-kHz Oscillator Counter Compensation .............................................................................
Kick State Machine .......................................................................................................
Second Register (SECOND) ............................................................................................
Minute Register (MINUTE) ..............................................................................................
Hour Register (HOUR) ...................................................................................................
Days Register (DAY) .....................................................................................................
20-23. MMC Data Read Time-Out Register (MMCTOD)
List of Figures
907
907
908
908
909
910
911
912
912
912
912
914
914
915
916
917
917
918
920
924
925
928
928
929
930
SPRUH84C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
...............................................................................................
Year Register (YEAR) ....................................................................................................
Day of the Week Register (DOTW) ....................................................................................
Alarm Second Register (ALARMSECOND) ...........................................................................
Alarm Minute Register (ALARMMINUTE) .............................................................................
Alarm Hour Register (ALARMHOUR) ..................................................................................
Alarm Day Register (ALARMDAY) .....................................................................................
Alarm Month Register (ALARMMONTH) ..............................................................................
Alarm Year Register (ALARMYEAR) ...................................................................................
Control Register (CTRL) .................................................................................................
Status Register (STATUS)...............................................................................................
Interrupt Register (INTERRUPT) .......................................................................................
Compensation (LSB) Register (COMPLSB)...........................................................................
Compensation (MSB) Register (COMPMSB) .........................................................................
Oscillator Register (OSC) ................................................................................................
Scratch Registers (SCRATCHn) ........................................................................................
Kick Registers (KICKnR) .................................................................................................
SPI Block Diagram........................................................................................................
SPI 3-Pin Option ..........................................................................................................
SPI 4-Pin Option with SPIx_SCS[n] ...................................................................................
SPI 4-Pin Option with SPIx_ENA ......................................................................................
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ................................................................
Format for Transmitting 12-Bit Word ...................................................................................
Format for 10-Bit Received Word .......................................................................................
Clock Mode with POLARITY = 0 and PHASE = 0....................................................................
Clock Mode with POLARITY = 0 and PHASE = 1....................................................................
Clock Mode with POLARITY = 1 and PHASE = 0....................................................................
Clock Mode with POLARITY = 1 and PHASE = 1....................................................................
Five Bits per Character (5-Pin Option) .................................................................................
SPI 3-Pin Master Mode with WDELAY ................................................................................
SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY ...............................
SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY ......................................
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY.........................................
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY ......................................................
SPI Global Control Register 0 (SPIGCR0) ............................................................................
SPI Global Control Register 1 (SPIGCR1) ............................................................................
SPI Interrupt Register (SPIINT0) .......................................................................................
SPI Interrupt Level Register (SPILVL) .................................................................................
SPI Flag Register (SPIFLG) .............................................................................................
SPI Pin Control Register 0 (SPIPC0) ..................................................................................
SPI Pin Control Register 1 (SPIPC1) ..................................................................................
SPI Pin Control Register 2 (SPIPC2) ..................................................................................
SPI Pin Control Register 3 (SPIPC3) ..................................................................................
SPI Pin Control Register 4 (SPIPC4) ..................................................................................
SPI Pin Control Register 5 (SPIPC5) ..................................................................................
SPI Data Register 0 (SPIDAT0) ........................................................................................
SPI Data Register 1 (SPIDAT1) ........................................................................................
SPI Buffer Register (SPIBUF) ...........................................................................................
SPI Emulation Register (SPIEMU) .....................................................................................
Month Register (MONTH)
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
930
931
931
932
932
933
934
935
935
936
937
938
939
940
941
942
942
945
951
953
955
957
958
958
959
960
960
960
961
966
967
968
970
971
972
973
975
977
978
980
981
982
983
984
985
986
987
988
990
33
www.ti.com
22-33. SPI Delay Register (SPIDELAY)........................................................................................ 991
22-34. Example: tC2TDELAY = 8 SPI Module Clock Cycles ...................................................................... 992
22-35. Example: tT2CDELAY = 4 SPI Module Clock Cycles ...................................................................... 993
............................................................ 993
Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout ............................................................ 993
SPI Default Chip Select Register (SPIDEF) ........................................................................... 994
SPI Data Format Register (SPIFMTn) ................................................................................. 995
SPI Interrupt Vector Register 1 (INTVEC1) ........................................................................... 997
Timer Block Diagram ................................................................................................... 1000
Timer Clock Source Block Diagram................................................................................... 1001
64-Bit Timer Mode Block Diagram .................................................................................... 1002
Dual 32-Bit Timers Chained Mode Block Diagram ................................................................. 1005
Dual 32-Bit Timers Chained Mode Example ......................................................................... 1005
Dual 32-Bit Timers Unchained Mode Block Diagram ............................................................... 1007
Dual 32-Bit Timers Unchained Mode Example ...................................................................... 1008
32-Bit Timer Counter Overflow Example ............................................................................. 1011
Watchdog Timer Mode Block Diagram ............................................................................... 1013
Watchdog Timer Operation State Diagram .......................................................................... 1013
Timer Operation in Pulse Mode (CPn = 0) ........................................................................... 1015
Timer Operation in Clock Mode (CPn = 1) ........................................................................... 1015
Revision ID Register (REVID) ......................................................................................... 1019
Emulation Management Register (EMUMGT) ....................................................................... 1019
GPIO Interrupt Control and Enable Register (GPINTGPEN) ...................................................... 1020
GPIO Data and Direction Register (GPDATGPDIR) ............................................................... 1021
Timer Counter Register 12 (TIM12)................................................................................... 1022
Timer Counter Register 34 (TIM34)................................................................................... 1022
Timer Period Register 12 (PRD12) ................................................................................... 1023
Timer Period Register 34 (PRD34) ................................................................................... 1023
Timer Control Register (TCR) ......................................................................................... 1024
Timer Global Control Register (TGCR) ............................................................................... 1026
Watchdog Timer Control Register (WDTCR) ........................................................................ 1027
Timer Reload Register 12 (REL12) ................................................................................... 1028
Timer Reload Register 34 (REL34) ................................................................................... 1028
Timer Capture Register 12 (CAP12) .................................................................................. 1029
Timer Capture Register 34 (CAP34) .................................................................................. 1029
Timer Interrupt Control and Status Register (INTCTLSTAT) ...................................................... 1030
Timer Compare Register (CMPn) ..................................................................................... 1031
UART Block Diagram ................................................................................................... 1034
UART Clock Generation Diagram ..................................................................................... 1035
Relationships Between Data Bit, BCLK, and UART Input Clock .................................................. 1036
UART Protocol Formats ................................................................................................ 1038
UART Interface Using Autoflow Diagram ............................................................................ 1041
Autoflow Functional Timing Waveforms for UARTn_RTS ........................................................ 1042
Autoflow Functional Timing Waveforms for UARTn_CTS ........................................................ 1042
UART Interrupt Request Enable Paths ............................................................................... 1044
Receiver Buffer Register (RBR) ....................................................................................... 1047
Transmitter Holding Register (THR) .................................................................................. 1048
Interrupt Enable Register (IER)........................................................................................ 1049
Interrupt Identification Register (IIR) .................................................................................. 1050
22-36. Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout
22-37.
22-38.
22-39.
22-40.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
34
List of Figures
SPRUH84C – April 2013 – Revised September 2016
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24-13. FIFO Control Register (FCR) .......................................................................................... 1052
24-14. Line Control Register (LCR) ........................................................................................... 1053
24-15. Modem Control Register (MCR) ....................................................................................... 1055
24-16. Line Status Register (LSR)............................................................................................. 1056
24-17. Modem Status Register (MSR) ........................................................................................ 1059
24-18. Scratch Pad Register (SCR) ........................................................................................... 1060
24-19. Divisor LSB Latch (DLL) ................................................................................................ 1061
24-20. Divisor MSB Latch (DLH)
..............................................................................................
1061
24-21. Revision Identification Register 1 (REVID1) ......................................................................... 1062
24-22. Revision Identification Register 2 (REVID2) ......................................................................... 1062
24-23. Power and Emulation Management Register (PWREMU_MGMT) ............................................... 1063
24-24. Mode Definition Register (MDR)
......................................................................................
1064
25-1.
Functional Block Diagram .............................................................................................. 1066
25-2.
USB Clocking Diagram ................................................................................................. 1067
25-3.
Interrupt Service Routine Flow Chart ................................................................................. 1071
25-4.
CPU Actions at Transfer Phases ...................................................................................... 1076
25-5.
Sequence of Transfer ................................................................................................... 1076
25-6.
Service Endpoint 0 Flow Chart ........................................................................................ 1078
25-7.
IDLE Mode Flow Chart ................................................................................................. 1079
25-8.
TX Mode Flow Chart .................................................................................................... 1080
25-9.
RX Mode Flow Chart.................................................................................................... 1081
25-10. Setup Phase of a Control Transaction Flow Chart.................................................................. 1091
25-11. IN Data Phase Flow Chart ............................................................................................. 1093
25-12. OUT Data Phase Flow Chart .......................................................................................... 1095
25-13. Completion of SETUP or OUT Data Phase Flow Chart ............................................................ 1097
25-14. Completion of IN Data Phase Flow Chart ............................................................................ 1099
25-15. USB Controller Block Diagram ........................................................................................ 1106
25-16. Host Packet Descriptor Layout ........................................................................................ 1109
25-17. Host Buffer Descriptor Layout ......................................................................................... 1112
25-18. Teardown Descriptor Layout ........................................................................................... 1114
25-19. Relationship Between Memory Regions and Linking RAM ........................................................ 1117
25-20. High-Level Transmit and Receive Data Transfer Example ........................................................ 1123
25-21. Transmit Descriptors and Queue Status Configuration ............................................................ 1124
25-22. Transmit USB Data Flow Example (Initialization) ................................................................... 1125
25-23. Transmit USB Data Flow Example (Completion)
...................................................................
1126
25-24. Receive Descriptors and Queue Status Configuration ............................................................. 1127
25-25. Receive USB Data Flow Example (Initialization) .................................................................... 1127
25-26. Receive USB Data Flow Example (Completion) .................................................................... 1128
25-27. Revision Identification Register (REVID) ............................................................................. 1152
25-28. Control Register (CTRLR) .............................................................................................. 1152
25-29. Status Register (STATR) ............................................................................................... 1153
...........................................................................................
................................................................................................
Auto Request Register (AUTOREQ)..................................................................................
SRP Fix Time Register (SRPFIXTIME) ..............................................................................
Teardown Register (TEARDOWN)....................................................................................
USB Interrupt Source Register (INTSRCR)..........................................................................
USB Interrupt Source Set Register (INTSETR) .....................................................................
USB Interrupt Source Clear Register (INTCLRR) ...................................................................
25-30. Emulation Register (EMUR)
1153
25-31. Mode Register (MODE)
1154
25-32.
1156
25-33.
25-34.
25-35.
25-36.
25-37.
SPRUH84C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1157
1157
1158
1159
1160
35
www.ti.com
25-38. USB Interrupt Mask Register (INTMSKR)............................................................................ 1161
25-39. USB Interrupt Mask Set Register (INTMSKSETR)
.................................................................
1162
25-40. USB Interrupt Mask Clear Register (INTMSKCLRR) ............................................................... 1163
25-41. USB Interrupt Source Masked Register (INTMASKEDR) .......................................................... 1164
25-42. USB End of Interrupt Register (EOIR) ................................................................................ 1165
25-43. Generic RNDIS EP1 Size Register (GENRNDISSZ1).............................................................. 1165
25-44. Generic RNDIS EP2 Size Register (GENRNDISSZ2).............................................................. 1166
25-45. Generic RNDIS EP3 Size Register (GENRNDISSZ3).............................................................. 1166
25-46. Generic RNDIS EP4 Size Register (GENRNDISSZ4).............................................................. 1167
25-47. Function Address Register (FADDR) ................................................................................. 1167
25-48. Power Management Register (POWER) ............................................................................. 1168
25-49. Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)
...........................................
1169
25-50. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ........................................................ 1170
25-51. Interrupt Enable Register for INTRTX (INTRTXE) .................................................................. 1171
25-52. Interrupt Enable Register for INTRRX (INTRRXE)
.................................................................
1171
25-53. Interrupt Register for Common USB Interrupts (INTRUSB) ....................................................... 1172
25-54. Interrupt Enable Register for INTRUSB (INTRUSBE) .............................................................. 1173
25-55. Frame Number Register (FRAME) .................................................................................... 1173
25-56. Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................. 1174
25-57. Register to Enable the USB 2.0 Test Modes (TESTMODE)
......................................................
1174
25-58. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ...................................... 1175
25-59. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ...................................... 1176
1177
25-61. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
1178
25-62.
1179
25-63.
25-64.
25-65.
25-66.
25-67.
25-68.
25-69.
25-70.
25-71.
25-72.
25-73.
25-74.
25-75.
25-76.
25-77.
25-78.
25-79.
25-80.
25-81.
25-82.
25-83.
25-84.
25-85.
25-86.
36
...........................................
.....................................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...........................................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP).......................................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ......................................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...........................................
Count 0 Register (COUNT0) ...........................................................................................
Receive Count Register (RXCOUNT) ................................................................................
Type Register (Host mode only) (HOST_TYPE0) ..................................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) .....................................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ......................................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ............................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .....................................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL).............................................
Configuration Data Register (CONFIGDATA) .......................................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .....................................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .....................................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .....................................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .....................................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .....................................................
Device Control Register (DEVCTL) ...................................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ) ..........................................................................
Receive Endpoint FIFO Size (RXFIFOSZ) ...........................................................................
Transmit Endpoint FIFO Address (TXFIFOADDR) .................................................................
Receive Endpoint FIFO Address (RXFIFOADDR) ..................................................................
Hardware Version Register (HWVERS) ..............................................................................
Transmit Function Address (TXFUNCADDR) .......................................................................
25-60. Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
List of Figures
1180
1181
1182
1183
1183
1184
1184
1185
1185
1186
1187
1188
1189
1189
1190
1190
1191
1191
1192
1192
1193
1193
1194
1195
SPRUH84C – April 2013 – Revised September 2016
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www.ti.com
..............................................................................
25-88. Transmit Hub Port (TXHUBPORT)....................................................................................
25-89. Receive Function Address (RXFUNCADDR) ........................................................................
25-90. Receive Hub Address (RXHUBADDR) ...............................................................................
25-91. Receive Hub Port (RXHUBPORT) ....................................................................................
25-92. CDMA Revision Identification Register (DMAREVID) ..............................................................
25-93. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ...........................................
25-94. CDMA Emulation Control Register (DMAEMU) .....................................................................
25-95. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) ........................................
25-96. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) ........................................
25-97. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) ....................................
25-98. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) ....................................
25-99. CDMA Scheduler Control Register (DMA_SCHED_CTRL) .......................................................
25-100. CDMA Scheduler Table Word n Registers (WORD[n]) ...........................................................
25-101. Queue Manager Revision Identification Register (QMGRREVID) ...............................................
25-102. Queue Manager Queue Diversion Register (DIVERSION).......................................................
25-103. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) .............................
25-104. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) .............................
25-105. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) .............................
25-106. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) .............................
25-107. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) .............................
25-108. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .........................................
25-109. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) .............................
25-110. Queue Manager Queue Pending Register 0 (PEND0) ...........................................................
25-111. Queue Manager Queue Pending Register 1 (PEND1) ...........................................................
25-112. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) ............................
25-113. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) ....................................
25-114. Queue Manager Queue N Control Register D (CTRLD[N]) ......................................................
25-115. Queue Manager Queue N Status Register A (QSTATA[N]) .....................................................
25-116. Queue Manager Queue N Status Register B (QSTATB[N]) .....................................................
25-117. Queue Manager Queue N Status Register C (QSTATC[N]) .....................................................
25-87. Transmit Hub Address (TXHUBADDR)
SPRUH84C – April 2013 – Revised September 2016
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List of Figures
1195
1195
1196
1196
1196
1197
1197
1198
1198
1199
1200
1201
1202
1202
1204
1204
1205
1206
1207
1208
1208
1209
1209
1210
1210
1211
1212
1213
1214
1214
1215
37
www.ti.com
List of Tables
2-1.
Exception Vector Table for ARM ......................................................................................... 61
2-2.
Different Address Types in ARM System ............................................................................... 63
3-1.
AM1802 ARM Microprocessor System Interconnect Matrix .......................................................... 66
5-1.
MPU Memory Regions..................................................................................................... 72
5-2.
MPU Default Configuration................................................................................................ 72
5-3.
Device Master Settings .................................................................................................... 73
5-4.
Request Type Access Controls........................................................................................... 74
5-5.
MPU_BOOTCFG_ERR Interrupt Sources .............................................................................. 76
5-6.
Memory Protection Unit 1 (MPU1) Registers ........................................................................... 77
5-7.
Memory Protection Unit 2 (MPU2) Registers ........................................................................... 77
5-8.
Revision ID Register (REVID) Field Descriptions ...................................................................... 79
5-9.
Configuration Register (CONFIG) Field Descriptions
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
38
................................................................. 79
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions................................................. 80
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions .............................................. 81
Interrupt Enable Set Register (IENSET) Field Descriptions .......................................................... 82
Interrupt Enable Clear Register (IENCLR) Field Descriptions ........................................................ 82
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions ................... 84
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................. 85
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................. 85
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions .................. 86
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions .................. 86
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions .... 87
Fault Address Register (FLTADDRR) Field Descriptions ............................................................. 88
Fault Status Register (FLTSTAT) Field Descriptions .................................................................. 89
Fault Clear Register (FLTCLR) Field Descriptions..................................................................... 90
Device Clock Inputs ........................................................................................................ 92
System Clock Domains .................................................................................................... 92
Example PLL Frequencies ............................................................................................... 95
USB Clock Multiplexing Options.......................................................................................... 95
DDR2/mDDR Memory Controller MCLK Frequencies................................................................. 97
EMIFA Frequencies ........................................................................................................ 98
EMAC Reference Clock Frequencies .................................................................................. 100
Peripherals ................................................................................................................. 101
System PLLC Output Clocks ............................................................................................ 105
PLL Controller 0 (PLLC0) Registers .................................................................................... 108
PLL Controller 1 (PLLC1) Registers .................................................................................... 109
PLLC0 Revision Identification Register (REVID) Field Descriptions ............................................... 109
PLLC1 Revision Identification Register (REVID) Field Descriptions ............................................... 110
Reset Type Status Register (RSTYPE) Field Descriptions ......................................................... 110
Reset Control Register (RSCTRL) Field Descriptions ............................................................... 111
PLLC0 Control Register (PLLCTL) Field Descriptions ............................................................... 112
PLLC1 Control Register (PLLCTL) Field Descriptions ............................................................... 113
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions ..................................................... 114
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions ..................................................... 115
PLL Multiplier Control Register (PLLM) Field Descriptions.......................................................... 116
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................................................ 116
PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................ 117
List of Tables
SPRUH84C – April 2013 – Revised September 2016
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7-15.
PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................ 117
7-16.
PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................ 118
7-17.
PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................ 118
7-18.
PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................ 119
7-19.
PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................ 119
7-20.
PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions ............................................................ 120
7-21.
PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ............................................................ 120
7-22.
PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ............................................................ 121
7-23.
PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ............................................................ 121
7-24.
PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
122
7-25.
PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
122
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
................................................
................................................
PLL Post-Divider Control Register (POSTDIV) Field Descriptions .................................................
PLL Controller Command Register (PLLCMD) Field Descriptions .................................................
PLL Controller Status Register (PLLSTAT) Field Descriptions .....................................................
PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC0 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC0 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC1 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions ....................................
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions ....................................
PSC0 Default Module Configuration ...................................................................................
PSC1 Default Module Configuration ...................................................................................
Module States .............................................................................................................
IcePick Emulation Commands ..........................................................................................
PSC Interrupt Events .....................................................................................................
Power and Sleep Controller 0 (PSC0) Registers .....................................................................
Power and Sleep Controller 1 (PSC1) Registers .....................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions ........................................................
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions .........................................
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ............................................
Power Error Pending Register (PERRPR) Field Descriptions ......................................................
Power Error Clear Register (PERRCR) Field Descriptions .........................................................
Power Domain Transition Command Register (PTCMD) Field Descriptions .....................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions .........................................
Power Domain 0 Status Register (PDSTAT0) Field Descriptions ..................................................
Power Domain 1 Status Register (PDSTAT1) Field Descriptions ..................................................
Power Domain 0 Control Register (PDCTL0) Field Descriptions ...................................................
Power Domain 1 Control Register (PDCTL1) Field Descriptions ...................................................
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ...........................................
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ...........................................
Module Status n Register (MDSTATn) Field Descriptions ..........................................................
PSC0 Module Control n Register (MDCTLn) Field Descriptions ...................................................
SPRUH84C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
123
123
124
125
126
127
128
129
129
130
131
132
133
134
134
136
137
139
141
141
144
144
145
145
146
147
148
148
149
150
151
152
153
154
155
156
157
158
39
www.ti.com
8-24.
PSC1 Module Control n Register (MDCTLn) Field Descriptions ................................................... 159
9-1.
Power Management Features ........................................................................................... 162
10-1.
Master IDs ................................................................................................................. 175
10-2.
Default Master Priority
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
40
...................................................................................................
System Configuration Module 0 (SYSCFG0) Registers .............................................................
System Configuration Module 1 (SYSCFG1) Registers .............................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Device Identification Register 0 (DEVIDR0) Field Descriptions ....................................................
Boot Configuration Register (BOOTCFG) Field Descriptions .......................................................
Chip Revision Identification Register (CHIPREVIDR) Field Descriptions .........................................
Kick 0 Register (KICK0R) Field Descriptions .........................................................................
Kick 1 Register (KICK1R) Field Descriptions .........................................................................
Host 0 Configuration Register (HOST0CFG) Field Descriptions ...................................................
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ...............................................
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................
Interrupt Enable Register (IENSET) Field Descriptions..............................................................
Interrupt Enable Clear Register (IENCLR) Field Descriptions ......................................................
End of Interrupt Register (EOI) Field Descriptions ...................................................................
Fault Address Register (FLTADDRR) Field Descriptions ...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Master Priority 0 Register (MSTPRI0) Field Descriptions ...........................................................
Master Priority 1 Register (MSTPRI1) Field Descriptions ...........................................................
Master Priority 2 Register (MSTPRI2) Field Descriptions ...........................................................
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ................................................
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ................................................
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ................................................
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ................................................
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ................................................
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ................................................
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ................................................
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ................................................
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ................................................
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ................................................
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions .............................................
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions .............................................
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions .............................................
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions .............................................
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions .............................................
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions .............................................
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions .............................................
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions .............................................
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions .............................................
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions .............................................
Suspend Source Register (SUSPSRC) Field Descriptions .........................................................
Chip Signal Register (CHIPSIG) Field Descriptions..................................................................
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ...................................................
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ....................................................
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ....................................................
Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ....................................................
List of Tables
176
176
178
178
178
179
179
180
180
181
182
183
184
184
185
185
186
187
188
189
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
221
223
225
227
229
231
232
233
234
235
SPRUH84C – April 2013 – Revised September 2016
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10-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions .................................................... 237
10-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions .................................................... 238
10-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions ......................................................... 239
10-51. DDR Slew Register (DDR_SLEW) Field Descriptions ............................................................... 240
10-52. Deep Sleep Register (DEEPSLEEP) Field Descriptions ............................................................ 241
10-53. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions................................................ 242
10-54. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions ................................................. 242
10-55. Pullup/Pulldown Select Register (PUPD_SEL) Default Values ..................................................... 243
10-56. RXACTIVE Control Register (RXACTIVE) Field Descriptions ...................................................... 244
11-1.
AINTC System Interrupt Assignments ................................................................................. 247
11-2.
ARM Interrupt Controller (AINTC) Registers .......................................................................... 253
11-3.
Revision Identification Register (REVID) Field Descriptions ........................................................ 254
11-4.
Control Register (CR) Field Descriptions .............................................................................. 255
11-5.
Global Enable Register (GER) Field Descriptions .................................................................... 256
11-6.
Global Nesting Level Register (GNLR) Field Descriptions .......................................................... 256
11-7.
System Interrupt Status Indexed Set Register (SISR) Field Descriptions ......................................... 257
11-8.
System Interrupt Status Indexed Clear Register (SICR) Field Descriptions ...................................... 257
11-9.
System Interrupt Enable Indexed Set Register (EISR) Field Descriptions ........................................ 258
11-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions ..................................... 258
11-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions
.........................................
259
11-12. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions ...................................... 259
11-13. Vector Base Register (VBR) Field Descriptions ...................................................................... 260
11-14. Vector Size Register (VSR) Field Descriptions ....................................................................... 260
11-15. Vector Null Register (VNR) Field Descriptions........................................................................ 261
11-16. Global Prioritized Index Register (GPIR) Field Descriptions ........................................................ 261
11-17. Global Prioritized Vector Register (GPVR) Field Descriptions ...................................................... 262
11-18. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions ........................................ 262
11-19. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions ........................................ 263
11-20. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions ........................................ 263
11-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions ........................................ 264
11-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions ................................. 264
11-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions ................................. 265
11-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions ................................. 265
11-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions ................................. 266
11-26. System Interrupt Enable Set Register 1 (ESR1) Field Descriptions ............................................... 266
11-27. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions ............................................... 267
11-28. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions ............................................... 267
11-29. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions ............................................... 268
11-30. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions ............................................. 268
11-31. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions ............................................. 269
11-32. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions ............................................. 269
11-33. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions ............................................. 270
11-34. Channel Map Registers (CMRn) Field Descriptions
.................................................................
270
11-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions ........................................... 271
11-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions ........................................... 271
11-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions ............................................. 272
11-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions ............................................. 272
11-39. Host Interrupt Enable Register (HIER) Field Descriptions
..........................................................
273
11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions ......................................... 274
SPRUH84C – April 2013 – Revised September 2016
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List of Tables
41
www.ti.com
11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions ......................................... 274
13-1.
DDR2/mDDR SDRAM Commands ..................................................................................... 282
13-2.
Truth Table for DDR2/mDDR SDRAM Commands
13-3.
Addressable Memory Ranges ........................................................................................... 290
13-4.
Configuration Register Fields for Address Mapping.................................................................. 291
13-5.
Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
42
.................................................................
.....................................
Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) ...................................................
DDR2/mDDR Memory Controller FIFO Description ..................................................................
Refresh Urgency Levels .................................................................................................
Configuration Bit Field for Partial Array Self-refresh .................................................................
Reset Sources.............................................................................................................
DDR2 SDRAM Configuration by MRS Command ....................................................................
DDR2 SDRAM Configuration by EMRS(1) Command ...............................................................
Mobile DDR SDRAM Configuration by MRS Command.............................................................
Mobile DDR SDRAM Configuration by EMRS(1) Command .......................................................
SDCR Configuration ......................................................................................................
DDR2 Memory Refresh Specification .................................................................................
SDRCR Configuration ....................................................................................................
SDTIMR1 Configuration..................................................................................................
SDTIMR2 Configuration..................................................................................................
DRPYC1R Configuration.................................................................................................
DDR2/mDDR Memory Controller Registers ...........................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................
SDRAM Configuration Register (SDCR) Field Descriptions ........................................................
SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
SDRAM Timing Register 1 (SDTIMR1) Field Descriptions ..........................................................
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ..........................................................
SDRAM Configuration Register 2 (SDCR2) Field Descriptions ....................................................
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ...............................................
Performance Counter 1 Register (PC1) Field Descriptions .........................................................
Performance Counter 2 Register (PC2) Field Descriptions .........................................................
Performance Counter Configuration Register (PCC) Field Descriptions ..........................................
Performance Counter Filter Configuration .............................................................................
Performance Counter Master Region Select Register (PCMRS) Field Descriptions ............................
Performance Counter Time Register (PCT) Field Description ......................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) Field Descriptions ......................................................................
Interrupt Masked Register (IMR) Field Descriptions .................................................................
Interrupt Mask Set Register (IMSR) Field Descriptions ..............................................................
Interrupt Mask Clear Register (IMCR) Field Descriptions ...........................................................
DDR PHY Control Register 1 (DRPYC1R) Field Descriptions ......................................................
EDMA3 Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ....................................................................................
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .....................................
Expected Number of Transfers for Non-Null Transfer ...............................................................
EDMA3 DMA Channel to PaRAM Mapping ...........................................................................
Shadow Region Registers ...............................................................................................
Chain Event Triggers .....................................................................................................
List of Tables
283
292
294
296
299
300
301
303
303
303
304
309
310
310
311
311
312
313
313
314
315
318
319
320
321
322
323
323
324
325
326
327
327
328
328
329
330
331
345
348
349
357
359
361
363
SPRUH84C – April 2013 – Revised September 2016
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www.ti.com
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
...............................................................................
EDMA3 Error Interrupts ..................................................................................................
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping .................................................
Number of Interrupts .....................................................................................................
EDMA3 Transfer Controller Configurations ...........................................................................
Read/Write Command Optimization Rules ............................................................................
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries.....................................
Channel Options Parameters (OPT) Field Descriptions .............................................................
Channel Source Address Parameter (SRC) Field Descriptions ....................................................
A Count/B Count Parameter (A_B_CNT) Field Descriptions .......................................................
Channel Destination Address Parameter (DST) Field Descriptions ...............................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .........................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ........................
C Count Parameter (CCNT) Field Descriptions.......................................................................
EDMA3 Channel Controller (EDMA3CC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3CC Configuration Register (CCCFG) Field Descriptions ...................................................
QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions .............................................
DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ....................................
Bits in DMAQNUMn ......................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ....................................
Event Missed Register (EMR) Field Descriptions ....................................................................
Event Missed Clear Register (EMCR) Field Descriptions ...........................................................
QDMA Event Missed Register (QEMR) Field Descriptions .........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................
EDMA3CC Error Register (CCERR) Field Descriptions .............................................................
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................
Error Evaluate Register (EEVAL) Field Descriptions.................................................................
DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions ..............................
QDMA Region Access Enable for Region m (QRAEm) Field Descriptions .......................................
Event Queue Entry Registers (QxEy) Field Descriptions ............................................................
Queue n Status Register (QSTATn) Field Descriptions .............................................................
Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions .......................................
EDMA3CC Status Register (CCSTAT) Field Descriptions ..........................................................
Event Register (ER) Field Descriptions ................................................................................
Event Clear Register (ECR) Field Descriptions .......................................................................
Event Set Register (ESR) Field Descriptions .........................................................................
Chained Event Register (CER) Field Descriptions ...................................................................
Event Enable Register (EER) Field Descriptions .....................................................................
Event Enable Clear Register (EECR) Field Descriptions ............................................................
Event Enable Set Register (EESR) Field Descriptions .............................................................
Secondary Event Register (SER) Field Descriptions ................................................................
Secondary Event Clear Register (SECR) Field Descriptions .......................................................
Interrupt Enable Register (IER) Field Descriptions ...................................................................
Interrupt Enable Clear Register (IECR) Field Descriptions..........................................................
Interrupt Enable Set Register (IESR) Field Descriptions ............................................................
Interrupt Pending Register (IPR) Field Descriptions .................................................................
Interrupt Clear Register (ICR) Field Descriptions.....................................................................
EDMA3 Transfer Completion Interrupts
SPRUH84C – April 2013 – Revised September 2016
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List of Tables
364
364
365
365
372
378
397
398
400
400
401
401
402
403
403
404
407
408
409
410
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
426
427
428
429
430
431
431
432
432
433
434
434
435
436
43
www.ti.com
.............................................................
QDMA Event Register (QER) Field Descriptions .....................................................................
QDMA Event Enable Register (QEER) Field Descriptions ..........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions .................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ...................................................
QDMA Secondary Event Register (QSER) Field Descriptions .....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................
EDMA3 Transfer Controller (EDMA3TC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................
Error Status Register (ERRSTAT) Field Descriptions ...............................................................
Error Enable Register (ERREN) Field Descriptions ..................................................................
Error Clear Register (ERRCLR) Field Descriptions ..................................................................
Error Details Register (ERRDET) Field Descriptions ................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions.................................................
Read Command Rate Register (RDRATE) Field Descriptions .....................................................
Source Active Options Register (SAOPT) Field Descriptions.......................................................
Source Active Source Address Register (SASRC) Field Descriptions ............................................
Source Active Count Register (SACNT) Field Descriptions .........................................................
Source Active Destination Address Register (SADST) Field Descriptions ........................................
Source Active B-Index Register (SABIDX) Field Descriptions ......................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................
Source Active Count Reload Register (SACNTRLD) Field Descriptions ..........................................
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions .....................
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions .................
Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions .................................
Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions .............
Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions ........
Destination FIFO Options Register n (DFOPTn) Field Descriptions ...............................................
Destination FIFO Source Address Register n (DFSRCn) Field Descriptions .....................................
Destination FIFO Count Register n (DFCNTn) Field Descriptions .................................................
Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions ................................
Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions ..............................................
Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions ....................
Debug List .................................................................................................................
EMAC and MDIO Signals for MII Interface ............................................................................
EMAC and MDIO Signals for RMII Interface ..........................................................................
Ethernet Frame Description .............................................................................................
Basic Descriptor Description ............................................................................................
Receive Frame Treatment Summary ..................................................................................
Middle of Frame Overrun Treatment ...................................................................................
Emulation Control .........................................................................................................
EMAC Control Module Registers .......................................................................................
EMAC Control Module Revision ID Register (REVID) Field Descriptions .........................................
EMAC Control Module Software Reset Register (SOFTRESET) ..................................................
EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................
14-57. Interrupt Evaluate Register (IEVAL) Field Descriptions
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
14-81.
14-82.
14-83.
14-84.
14-85.
14-86.
14-87.
14-88.
14-89.
14-90.
14-91.
14-92.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
437
438
439
440
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
454
455
455
456
457
457
458
458
459
459
460
461
461
462
462
463
464
473
474
475
477
502
503
513
514
515
516
517
15-12. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 518
44
List of Tables
SPRUH84C – April 2013 – Revised September 2016
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15-13. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 519
15-14. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 520
15-15. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 521
15-16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 522
15-17. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 523
15-18. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 524
.........
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .......
Management Data Input/Output (MDIO) Registers...................................................................
MDIO Revision ID Register (REVID) Field Descriptions.............................................................
MDIO Control Register (CONTROL) Field Descriptions .............................................................
PHY Acknowledge Status Register (ALIVE) Field Descriptions ....................................................
PHY Link Status Register (LINK) Field Descriptions .................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ..............
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions .......
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions .....
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ....
15-19. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
525
526
527
528
528
529
530
530
531
532
533
534
535
15-32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ............................................................................................................... 536
15-33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................. 537
15-34. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ........................................ 538
15-35. MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................. 539
15-36. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ........................................ 540
15-37. Ethernet Media Access Controller (EMAC) Registers ............................................................... 541
15-38. Transmit Revision ID Register (TXREVID) Field Descriptions ...................................................... 544
15-39. Transmit Control Register (TXCONTROL) Field Descriptions ...................................................... 544
15-40. Transmit Teardown Register (TXTEARDOWN) Field Descriptions ................................................ 545
15-41. Receive Revision ID Register (RXREVID) Field Descriptions ...................................................... 546
15-42. Receive Control Register (RXCONTROL) Field Descriptions ...................................................... 546
................................................
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ........................
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions.......................
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ....................................
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ..............................
MAC Input Vector Register (MACINVECTOR) Field Descriptions .................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ..................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .........................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions .......................
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions .....................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ...............................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ..........................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions.........................
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ......................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................
15-43. Receive Teardown Register (RXTEARDOWN) Field Descriptions
547
15-44.
548
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
549
550
551
552
553
554
555
556
557
558
558
559
559
15-58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 560
15-59. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 563
SPRUH84C – April 2013 – Revised September 2016
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List of Tables
45
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15-60. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 564
15-61. Receive Maximum Length Register (RXMAXLEN) Field Descriptions
............................................
565
15-62. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions........................................ 565
15-63. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 566
15-64. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............... 566
15-65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ...................... 567
15-66. MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 568
15-67. MAC Status Register (MACSTATUS) Field Descriptions
...........................................................
570
15-68. Emulation Control Register (EMCONTROL) Field Descriptions .................................................... 572
15-69. FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................ 572
15-70. MAC Configuration Register (MACCONFIG) Field Descriptions ................................................... 573
15-71. Soft Reset Register (SOFTRESET) Field Descriptions .............................................................. 573
15-72. MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................ 574
15-73. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................. 574
575
15-75. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
575
15-76.
576
15-77.
15-78.
15-79.
15-80.
15-81.
15-82.
15-83.
15-84.
15-85.
15-86.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
46
.................................................
.................................................
Back Off Test Register (BOFFTEST) Field Descriptions ............................................................
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions .....................................
Receive Pause Timer Register (RXPAUSE) Field Descriptions ....................................................
Transmit Pause Timer Register (TXPAUSE) Field Descriptions ...................................................
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ...........................................
MAC Address High Bytes Register (MACADDRHI) Field Descriptions............................................
MAC Index Register (MACINDEX) Field Descriptions ...............................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ....................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ....................
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions ..................................
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ...................................
EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories........................................
EMIFA Pins Specific to SDRAM ........................................................................................
EMIFA Pins Specific to Asynchronous Memory ......................................................................
EMIFA SDRAM Commands .............................................................................................
Truth Table for SDRAM Commands ...................................................................................
16-bit EMIFA Address Pin Connections ...............................................................................
Description of the SDRAM Configuration Register (SDCR) .........................................................
Description of the SDRAM Refresh Control Register (SDRCR) ....................................................
Description of the SDRAM Timing Register (SDTIMR) ..............................................................
Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ......................................
SDRAM LOAD MODE REGISTER Command ........................................................................
Refresh Urgency Levels .................................................................................................
Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM .................................................
Normal Mode vs. Select Strobe Mode .................................................................................
Description of the Asynchronous m Configuration Register (CEnCFG) ...........................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..................................
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ............................................
Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) ..........................................
Asynchronous Read Operation in Normal Mode .....................................................................
Asynchronous Write Operation in Normal Mode .....................................................................
Asynchronous Read Operation in Select Strobe Mode ..............................................................
Asynchronous Write Operation in Select Strobe Mode ..............................................................
15-74. MAC Hash Address Register 1 (MACHASH1) Field Descriptions
List of Tables
576
577
577
578
579
579
580
580
581
581
593
594
594
595
595
597
598
598
599
599
600
601
606
607
609
610
612
612
612
614
616
618
SPRUH84C – April 2013 – Revised September 2016
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www.ti.com
16-23. Description of the NAND Flash Control Register (NANDFCR) ..................................................... 620
16-24. Reset Sources............................................................................................................. 626
16-25. Interrupt Monitor and Control Bit Fields ................................................................................ 628
16-26. SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface ................................................ 633
16-27. SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface .................................. 635
16-28. RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface ................................................. 636
16-29. RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface ................................................. 636
16-30. SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface
..........................................
637
16-31. EMIFA Input Timing Requirements ..................................................................................... 638
16-32. ASRAM Output Timing Characteristics ................................................................................ 638
16-33. ASRAM Input Timing Requirement for a Read ....................................................................... 638
16-34. ASRAM Input Timing Requirements for a Write
.....................................................................
639
16-35. ASRAM Timing Requirements With PCB Delays..................................................................... 641
.....................................................
ASRAM Timing Requirements for TC5516100FT-12 Example .....................................................
Measured PCB Delays for TC5516100FT-12 Example .............................................................
Configuring CE3CFG for TC5516100FT-12 Example ...............................................................
Recommended Margins..................................................................................................
EMIFA Read Timing Requirements ....................................................................................
NAND Flash Read Timing Requirements .............................................................................
NAND Flash Write Timing Requirements .............................................................................
EMIFA Timing Requirements for HY27UA081G1M Example .......................................................
NAND Flash Timing Requirements for HY27UA081G1M Example ................................................
Configuring CE2CFG for HY27UA081G1M Example ................................................................
Configuring NANDFCR for HY27UA081G1M Example..............................................................
External Memory Interface (EMIFA) Registers .......................................................................
Module ID Register (MIDR) Field Descriptions .......................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions .................................
SDRAM Configuration Register (SDCR) Field Descriptions ........................................................
SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
Asynchronous n Configuration Register (CEnCFG) Field Descriptions ...........................................
SDRAM Timing Register (SDTIMR) Field Descriptions..............................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ......................................
EMIFA Interrupt Raw Register (INTRAW) Field Descriptions.......................................................
EMIFA Interrupt Mask Register (INTMSK) Field Descriptions ......................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ............................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions .........................................
NAND Flash Control Register (NANDFCR) Field Descriptions .....................................................
NAND Flash Status Register (NANDFSR) Field Descriptions ......................................................
NAND Flash n ECC Register (NANDFnECC) Field Descriptions ..................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ............................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions ........................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions ........................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ......................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ......................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions ..........................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions ..........................
16-36. EMIFA Timing Requirements for TC5516100FT-12 Example
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
16-70.
16-71.
SPRUH84C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
644
644
644
646
646
647
647
649
652
652
654
654
655
656
657
658
660
661
663
664
665
666
667
668
669
671
672
673
674
674
675
675
676
676
677
677
47
www.ti.com
17-1.
GPIO Register Bits and Banks Associated With GPIO Signals .................................................... 681
17-2.
GPIO Registers
17-3.
Revision ID Register (REVID) Field Descriptions
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
48
...........................................................................................................
....................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ..........................................
GPIO Direction Register (DIRn) Field Descriptions ..................................................................
GPIO Output Data Register (OUT_DATAn) Field Descriptions ....................................................
GPIO Set Data Register (SET_DATAn) Field Descriptions .........................................................
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ......................................................
GPIO Input Data Register (IN_DATAn) Field Descriptions..........................................................
GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions ......................
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions .............................
GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions .....................
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions ............................
GPIO Interrupt Status Register (INTSTATn) Field Descriptions ....................................................
Operating Modes of the I2C Peripheral ................................................................................
Ways to Generate a NACK Bit ..........................................................................................
Descriptions of the I2C Interrupt Events ...............................................................................
Inter-Integrated Circuit (I2C) Registers ................................................................................
I2C Own Address Register (ICOAR) Field Descriptions .............................................................
I2C Interrupt Mask Register (ICIMR) Field Descriptions.............................................................
I2C Interrupt Status Register (ICSTR) Field Descriptions ...........................................................
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions ...............................................
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ..............................................
I2C Data Count Register (ICCNT) Field Descriptions................................................................
I2C Data Receive Register (ICDRR) Field Descriptions .............................................................
I2C Slave Address Register (ICSAR) Field Descriptions ............................................................
I2C Data Transmit Register (ICDXR) Field Descriptions ............................................................
I2C Mode Register (ICMDR) Field Descriptions ......................................................................
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ..................................
How the MST and FDF Bits Affect the Role of TRX Bit .............................................................
I2C Interrupt Vector Register (ICIVR) Field Descriptions ............................................................
I2C Extended Mode Register (ICEMDR) Field Descriptions ........................................................
I2C Prescaler Register (ICPSC) Field Descriptions ..................................................................
I2C Revision Identification Register 1 (REVID1) Field Descriptions ...............................................
I2C Revision Identification Register 2 (REVID2) Field Descriptions ...............................................
I2C DMA Control Register (ICDMAC) Field Descriptions ...........................................................
I2C Pin Function Register (ICPFUNC) Field Descriptions ..........................................................
I2C Pin Direction Register (ICPDIR) Field Descriptions .............................................................
I2C Pin Data In Register (ICPDIN) Field Descriptions ...............................................................
I2C Pin Data Out Register (ICPDOUT) Field Descriptions ..........................................................
I2C Pin Data Set Register (ICPDSET) Field Descriptions...........................................................
I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ........................................................
Biphase-Mark Encoder ...................................................................................................
Preamble Codes ..........................................................................................................
Channel Status and User Data for Each DIT Block .................................................................
Transmit Bitstream Data Alignment ....................................................................................
Receive Bitstream Data Alignment .....................................................................................
EDMA Events - McASP ..................................................................................................
McASP Registers Accessed by CPU/EDMA Through Peripheral Configuration Port ...........................
List of Tables
688
689
690
692
694
696
698
700
702
704
706
708
710
720
721
725
726
727
728
729
732
732
733
734
735
736
737
739
739
741
742
743
744
744
745
746
747
748
749
750
751
760
761
787
795
797
807
808
SPRUH84C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
..................................................
McASP AFIFO Registers Accessed Through Peripheral Configuration Port .....................................
Revision Identification Register (REV) Field Descriptions ...........................................................
Pin Function Register (PFUNC) Field Descriptions ..................................................................
Pin Direction Register (PDIR) Field Descriptions .....................................................................
Pin Data Output Register (PDOUT) Field Descriptions ..............................................................
Pin Data Input Register (PDIN) Field Descriptions ...................................................................
Pin Data Set Register (PDSET) Field Descriptions ..................................................................
Pin Data Clear Register (PDCLR) Field Descriptions ................................................................
Global Control Register (GBLCTL) Field Descriptions ...............................................................
Audio Mute Control Register (AMUTE) Field Descriptions ..........................................................
Digital Loopback Control Register (DLBCTL) Field Descriptions ...................................................
Digital Mode Control Register (DITCTL) Field Descriptions.........................................................
Receiver Global Control Register (RGBLCTL) Field Descriptions .................................................
Receive Format Unit Bit Mask Register (RMASK) Field Descriptions .............................................
Receive Bit Stream Format Register (RFMT) Field Descriptions ..................................................
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions............................................
Receive Clock Control Register (ACLKRCTL) Field Descriptions ..................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ............................
Receive TDM Time Slot Register (RTDM) Field Descriptions ......................................................
Receiver Interrupt Control Register (RINTCTL) Field Descriptions ................................................
Receiver Status Register (RSTAT) Field Descriptions...............................................................
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions ..........................................
Receive Clock Check Control Register (RCLKCHK) Field Descriptions ..........................................
Receiver DMA Event Control Register (REVTCTL) Field Descriptions............................................
Transmitter Global Control Register (XGBLCTL) Field Descriptions ..............................................
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ............................................
Transmit Bit Stream Format Register (XFMT) Field Descriptions ..................................................
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions ...........................................
Transmit Clock Control Register (ACLKXCTL) Field Descriptions .................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions ...........................
Transmit TDM Time Slot Register (XTDM) Field Descriptions .....................................................
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions .............................................
Transmitter Status Register (XSTAT) Field Descriptions ............................................................
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions ..........................................
Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ..........................................
Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions .........................................
Serializer Control Registers (SRCTLn) Field Descriptions ..........................................................
AFIFO Revision Identification Register (AFIFOREV) Field Descriptions ..........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ......................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .......................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions ......................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions .......................................................
MMC/SD Controller Pins Used in Each Mode ........................................................................
MMC/SD Mode Write Sequence ........................................................................................
MMC/SD Mode Read Sequence........................................................................................
Description of MMC/SD Interrupt Requests ...........................................................................
Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers ............................................
MMC Control Register (MMCCTL) Field Descriptions ...............................................................
McASP Registers Accessed by CPU/EDMA Through DMA Port
SPRUH84C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
811
811
812
814
816
818
820
822
824
825
827
829
830
831
832
833
835
836
837
838
839
840
841
842
843
844
845
846
848
849
850
851
852
853
854
855
856
857
861
862
863
864
865
870
871
872
882
896
897
49
www.ti.com
20-7.
MMC Memory Clock Control Register (MMCCLK) Field Descriptions ............................................. 898
20-8.
MMC Status Register 0 (MMCST0) Field Descriptions .............................................................. 899
20-9.
MMC Status Register 1 (MMCST1) Field Descriptions .............................................................. 901
20-10. MMC Interrupt Mask Register (MMCIM) Field Descriptions......................................................... 902
20-11. MMC Response Time-Out Register (MMCTOR) Field Descriptions ............................................... 904
20-12. MMC Data Read Time-Out Register (MMCTOD) Field Descriptions .............................................. 905
20-13. MMC Block Length Register (MMCBLEN) Field Descriptions ...................................................... 906
20-14. MMC Number of Blocks Register (MMCNBLK) Field Descriptions
................................................
907
20-15. MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions ...................................... 907
20-16. MMC Data Receive Register (MMCDRR) Field Descriptions ....................................................... 908
20-17. MMC Data Transmit Register (MMCDXR) Field Descriptions ...................................................... 908
20-18. MMC Command Register (MMCCMD) Field Descriptions .......................................................... 909
20-19. Command Format
........................................................................................................
910
20-20. MMC Argument Register (MMCARGHL) Field Descriptions ........................................................ 911
20-21. R1, R3, R4, R5, or R6 Response (48 Bits) ............................................................................ 913
913
20-23.
914
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
22-1.
22-2.
22-3.
50
.................................................................................................
MMC Data Response Register (MMCDRSP) Field Descriptions ...................................................
MMC Command Index Register (MMCCIDX) Field Descriptions...................................................
SDIO Control Register (SDIOCTL) Field Descriptions ...............................................................
SDIO Status Register 0 (SDIOST0) Field Descriptions ..............................................................
SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions .....................................................
SDIO Interrupt Status Register (SDIOIST) Field Descriptions ......................................................
MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions ..................................................
Real-Time Clock Signals .................................................................................................
Real-Time Clock (RTC) Registers ......................................................................................
Second Register (SECOND) Field Descriptions ......................................................................
Minute Register (MINUTE) Field Descriptions ........................................................................
Hour Register (HOUR) Field Descriptions .............................................................................
Day Register (DAY) Field Descriptions ................................................................................
Month Register (MONTH) Field Descriptions .........................................................................
Year Register (YEAR) Field Descriptions .............................................................................
Day of the Week Register (DOTW) Field Descriptions ..............................................................
Alarm Second Register (ALARMSECOND) Field Descriptions .....................................................
Alarm Minute Register (ALARMMINUTE) Field Descriptions .......................................................
Alarm Hour Register (ALARMHOUR) Field Descriptions............................................................
Alarm Day Register (ALARMDAY) Field Descriptions ...............................................................
Alarm Month Register (ALARMMONTH) Field Descriptions ........................................................
Alarm Years Register (ALARMYEARS) Field Descriptions .........................................................
Control Register (CTRL) Field Descriptions ...........................................................................
Status Register (STATUS) Field Descriptions ........................................................................
Interrupt Register (INTERRUPT) Field Descriptions .................................................................
Compensations Register (COMPLSB) Field Descriptions...........................................................
Compensations Register (COMPMSB) Field Descriptions ..........................................................
Oscillator Register (OSC) Field Descriptions .........................................................................
Scratch Registers (SCRATCHn) Field Descriptions .................................................................
Kick Registers (KICKnR) Field Descriptions ..........................................................................
SPI Pins ....................................................................................................................
SPI Registers ..............................................................................................................
SPI Register Settings Defining Master Modes ........................................................................
20-22. R2 Response (136 Bits)
List of Tables
914
915
916
917
917
918
921
927
928
928
929
930
930
931
931
932
932
933
934
935
935
936
937
938
939
940
941
942
942
946
947
948
SPRUH84C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
..................................................................... 948
SPI Register Settings Defining Slave Modes ......................................................................... 950
Allowed SPI Register Settings in Slave Modes ....................................................................... 950
Clocking Modes ........................................................................................................... 959
SPI Registers .............................................................................................................. 972
SPI Global Control Register 0 (SPIGCR0) Field Descriptions ...................................................... 972
SPI Global Control Register 1 (SPIGCR1) Field Descriptions ...................................................... 973
SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................. 975
SPI Interrupt Level Register (SPILVL) Field Descriptions ........................................................... 977
SPI Flag Register (SPIFLG) Field Descriptions ...................................................................... 978
SPI Pin Control Register 0 (SPIPC0) Field Descriptions ............................................................ 980
SPI Pin Control Register 1 (SPIPC1) Field Descriptions ............................................................ 981
SPI Pin Control Register 2 (SPIPC2) Field Descriptions ............................................................ 982
SPI Pin Control Register 3 (SPIPC3) Field Descriptions ............................................................ 983
SPI Pin Control Register 4 (SPIPC4) Field Descriptions ............................................................ 984
SPI Pin Control Register 5 (SPIPC5) Field Descriptions ............................................................ 985
SPI Data Register 0 (SPIDAT0) Field Descriptions .................................................................. 986
SPI Data Register 1 (SPIDAT1) Field Descriptions .................................................................. 987
SPI Buffer Register (SPIBUF) Field Descriptions .................................................................... 988
SPI Emulation Register (SPIEMU) Field Descriptions ............................................................... 990
SPI Delay Register (SPIDELAY) Field Descriptions ................................................................. 991
SPI Default Chip Select Register (SPIDEF) Field Descriptions .................................................... 994
SPI Data Format Register (SPIFMTn) Field Descriptions ........................................................... 995
SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions ..................................................... 997
Timer Clock Source Selection ......................................................................................... 1001
64-Bit Timer Configurations ............................................................................................ 1003
32-Bit Timer Chained Mode Configurations ......................................................................... 1006
32-Bit Timer Unchained Mode Configurations....................................................................... 1009
Counter and Period Registers Used in GP Timer Modes .......................................................... 1011
TSTAT Parameters in Pulse and Clock Modes ..................................................................... 1015
Timer Emulation Modes Selection .................................................................................... 1017
Timer Registers .......................................................................................................... 1017
Revision ID Register (REVID) Field Descriptions ................................................................... 1019
Emulation Management Register (EMUMGT) Field Descriptions ................................................ 1019
GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions ............................... 1020
GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions ......................................... 1021
Timer Counter Register 12 (TIM12) Field Descriptions ............................................................ 1022
Timer Counter Register 34 (TIM34) Field Descriptions ............................................................ 1022
Timer Period Register (PRD12) Field Descriptions ................................................................. 1023
Timer Period Register (PRD34) Field Descriptions ................................................................. 1023
Timer Control Register (TCR) Field Descriptions ................................................................... 1024
Timer Global Control Register (TGCR) Field Descriptions ........................................................ 1026
Watchdog Timer Control Register (WDTCR) Field Descriptions .................................................. 1027
Timer Reload Register 12 (REL12) Field Descriptions ............................................................. 1028
Timer Reload Register 34 (REL34) Field Descriptions ............................................................. 1028
Timer Capture Register 12 (CAP12) Field Descriptions ........................................................... 1029
Timer Capture Register 34 (CAP34) Field Descriptions ........................................................... 1029
Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ................................ 1030
Timer Compare Register (CMPn) Field Descriptions ............................................................... 1031
Allowed SPI Register Settings in Master Modes
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51
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24-1.
Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode ........................ 1036
24-2.
Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode ........................ 1036
24-3.
UART Signal Descriptions
1037
24-4.
Character Time for Word Lengths
1040
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
52
.............................................................................................
....................................................................................
UART Interrupt Requests Descriptions ...............................................................................
UART Registers .........................................................................................................
Receiver Buffer Register (RBR) Field Descriptions .................................................................
Transmitter Holding Register (THR) Field Descriptions ............................................................
Interrupt Enable Register (IER) Field Descriptions .................................................................
Interrupt Identification Register (IIR) Field Descriptions............................................................
Interrupt Identification and Interrupt Clearing Information .........................................................
FIFO Control Register (FCR) Field Descriptions ....................................................................
Line Control Register (LCR) Field Descriptions .....................................................................
Relationship Between ST, EPS, and PEN Bits in LCR.............................................................
Number of STOP Bits Generated .....................................................................................
Modem Control Register (MCR) Field Descriptions ................................................................
Line Status Register (LSR) Field Descriptions ......................................................................
Modem Status Register (MSR) Field Descriptions..................................................................
Scratch Pad Register (MSR) Field Descriptions ....................................................................
Divisor LSB Latch (DLL) Field Descriptions .........................................................................
Divisor MSB Latch (DLH) Field Descriptions ........................................................................
Revision Identification Register 1 (REVID1) Field Descriptions ...................................................
Revision Identification Register 2 (REVID2) Field Descriptions ...................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions .........................
Mode Definition Register (MDR) Field Descriptions ................................................................
USB Clock Multiplexing Options.......................................................................................
PHY PLL Clock Frequencies Supported .............................................................................
USB Terminal Functions ...............................................................................................
PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ..............................................
PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ...........................................
PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions .....................................
PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ..................................
Host Packet Descriptor Word 0 (HPD Word 0) ......................................................................
Host Packet Descriptor Word 1 (HPD Word 1) ......................................................................
Host Packet Descriptor Word 2 (HPD Word 2) ......................................................................
Host Packet Descriptor Word 3 (HPD Word 3) ......................................................................
Host Packet Descriptor Word 4 (HPD Word 4) ......................................................................
Host Packet Descriptor Word 5 (HPD Word 5) ......................................................................
Host Packet Descriptor Word 6 (HPD Word 6) ......................................................................
Host Packet Descriptor Word 7 (HPD Word 7) ......................................................................
Host Buffer Descriptor Word 0 (HBD Word 0) .......................................................................
Host Buffer Descriptor Word 1 (HBD Word 1) .......................................................................
Host Buffer Descriptor Word 2 (HBD Word 2) .......................................................................
Host Buffer Descriptor Word 3 (HBD Word 3) .......................................................................
Host Buffer Descriptor Word 4 (HBD Word 4) .......................................................................
Host Buffer Descriptor Word 5 (HBD Word 5) .......................................................................
Host Buffer Descriptor Word 6 (HBD Word 6) .......................................................................
Host Buffer Descriptor Word 7 (HBD Word 7) .......................................................................
Teardown Descriptor Word 0 ..........................................................................................
List of Tables
1044
1046
1047
1048
1049
1050
1051
1052
1053
1054
1054
1055
1056
1059
1060
1061
1061
1062
1062
1063
1064
1067
1068
1068
1083
1084
1086
1088
1109
1109
1110
1110
1110
1110
1111
1111
1112
1112
1112
1112
1113
1113
1113
1113
1114
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......................................................................................
Allocation of Queues ....................................................................................................
Interrupts Generated by the USB Controller .........................................................................
USB Interrupt Conditions ...............................................................................................
USB Interrupts ...........................................................................................................
Universal Serial Bus OTG (USB0) Registers ........................................................................
Revision Identification Register (REVID) Field Descriptions ......................................................
Control Register (CTRLR) Field Descriptions .......................................................................
Status Register (STATR) Field Descriptions.........................................................................
Emulation Register (EMUR) Field Descriptions .....................................................................
Mode Register (MODE) Field Descriptions ..........................................................................
Auto Request Register (AUTOREQ) Field Descriptions ...........................................................
SRP Fix Time Register (SRPFIXTIME) Field Descriptions ........................................................
Teardown Register (TEARDOWN) Field Descriptions .............................................................
USB Interrupt Source Register (INTSRCR) Field Descriptions ...................................................
USB Interrupt Source Set Register (INTSETR) Field Descriptions ...............................................
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................
USB Interrupt Mask Register (INTMSKR) Field Descriptions .....................................................
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions ...........................................
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions.........................................
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ...................................
USB End of Interrupt Register (EOIR) Field Descriptions .........................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions .......................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions .......................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions .......................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions .......................................
Function Address Register (FADDR) Field Descriptions ...........................................................
Power Management Register (POWER) Field Descriptions .......................................................
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)Field Descriptions ..............
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ..................................
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ...........................................
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions .......................................
Frame Number Register (FRAME) Field Descriptions .............................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)Field Descriptions ........
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions ................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions .....................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ...............
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions .....................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions ................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions .....................
Count 0 Register (COUNT0) Field Descriptions ....................................................................
Receive Count Register (RXCOUNT) Field Descriptions ..........................................................
Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ...............................
25-25. Teardown Descriptor Words 1-7
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.
25-45.
25-46.
25-47.
25-48.
25-49.
25-50.
25-51.
25-52.
25-53.
25-54.
25-55.
25-56.
25-57.
25-58.
25-59.
25-60.
25-61.
25-62.
25-63.
25-64.
25-65.
25-66.
25-67.
25-68.
25-69.
25-70.
25-71.
25-72.
25-73.
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List of Tables
1114
1115
1129
1129
1132
1145
1152
1152
1153
1153
1154
1156
1157
1157
1158
1159
1160
1161
1162
1163
1164
1165
1165
1166
1166
1167
1167
1168
1169
1170
1171
1171
1172
1173
1173
1174
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1183
1184
1184
53
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25-74. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................ 1185
25-75. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ...................... 1185
25-76. Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions ............................... 1186
25-77. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions ...................... 1187
25-78. Configuration Data Register (CONFIGDATA) Field Descriptions ................................................. 1188
25-79. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions .............................. 1189
25-80. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions .............................. 1189
25-81. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions .............................. 1190
25-82. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions .............................. 1190
25-83. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions .............................. 1191
25-84. Device Control Register (DEVCTL) Field Descriptions ............................................................. 1191
25-85. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions .................................................... 1192
25-86. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions .................................................... 1192
25-87. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions ........................................... 1193
25-88. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions
...........................................
1193
25-89. Hardware Version Register (HWVERS) Field Descriptions........................................................ 1194
25-90. Transmit Function Address (TXFUNCADDR) Field Descriptions ................................................. 1195
25-91. Transmit Hub Address (TXHUBADDR) Field Descriptions ........................................................ 1195
25-92. Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................. 1195
25-93. Receive Function Address (RXFUNCADDR) Field Descriptions
.................................................
1196
25-94. Receive Hub Address (RXHUBADDR) Field Descriptions......................................................... 1196
25-95. Receive Hub Port (RXHUBPORT) Field Descriptions .............................................................. 1196
25-96. CDMA Revision Identification Register (DMAREVID) Field Descriptions ........................................ 1197
25-97. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ..................... 1197
25-98. CDMA Emulation Control Register (DMAEMU) Field Descriptions ............................................... 1198
.................
CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions ................
Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ............
Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ............
CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions ................................
CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions .....................................
Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions ........................
Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions .......
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions ......
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ...................
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions ......
Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions .....................................
Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions .....................................
Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions .....
Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions ..............
Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions ................................
Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions ...............................
Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions ...............................
Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions ...............................
25-99. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions
25-100.
25-101.
25-102.
25-103.
25-104.
25-105.
25-106.
25-107.
25-108.
25-109.
25-110.
25-111.
25-112.
25-113.
25-114.
25-115.
25-116.
25-117.
25-118.
25-119.
25-120.
25-121.
54
List of Tables
1198
1199
1200
1201
1202
1202
1204
1204
1205
1206
1207
1208
1208
1209
1209
1210
1210
1211
1212
1213
1214
1214
1215
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Preface
SPRUH84C – April 2013 – Revised September 2016
Read This First
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components
• ARM subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Code Composer Studio is a trademark of Texas Instruments.
ARM926EJ-S, Jazelle are trademarks of ARM Limited.
SD is a trademark of SanDisk Corporation.
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55
Chapter 1
SPRUH84C – April 2013 – Revised September 2016
Overview
Topic
...........................................................................................................................
1.1
1.2
56
Overview
Page
Introduction ....................................................................................................... 57
ARM Subsystem................................................................................................. 57
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Introduction
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1.1
Introduction
The AM1802 ARM microprocessor contains an ARM RISC CPU for general-purpose processing and
systems control. The AM1802 ARM microprocessor consists of the following primary components:
• ARM subsystem and associated memories
• A set of I/O peripherals
• A powerful DMA subsystem and SDRAM EMIF interface
Block Diagram
A block diagram for the AM1802 ARM Microprocessor is shown in Figure 1-1.
1.2
ARM Subsystem
The ARM926EJ-S™ 32-bit RISC CPU in the ARM subsystem (ARMSS) acts as the overall system
controller. The ARM CPU performs general system control tasks, such as system initialization,
configuration, power management, user interface, and user command implementation. The ARM
Subsystem chapter describes the ARMSS components and system control functions that the ARM core
performs.
Figure 1-1. AM1802 ARM Microprocessor Block Diagram
ARM Subsystem
JTAG Interface
System Control
PLL/Clock
Generator
w/OSC
Input
Clock(s)
GeneralPurpose
Timer (x4)
RTC/
32-kHz
OSC
ARM926EJ-S CPU
With MMU
Memory Protection
4KB ETB
16KB
16KB
I-Cache D-Cache
Power/Sleep
Controller
8KB RAM
(Vector Table)
Pin
Multiplexing
64KB ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
EDMA3
(x2)
McASP
w/FIFO
I2C
Connectivity
USB2.0
OTG Ctlr
PHY
EMAC
10/100
MDIO
(MII/RMII)
Shared
Memory
Serial Interfaces
SPI
(x2)
UART
(x3)
128KB
RAM
External Memory Interfaces
MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/mDDR
Memory
Controller
Note: Not all peripherals are available at the same time due to multiplexing.
DMA Subsystem
The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more
information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter.
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57
Chapter 2
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ARM Subsystem
Topic
2.1
2.2
2.3
2.4
2.5
2.6
2.7
58
...........................................................................................................................
Introduction .......................................................................................................
Operating States/Modes ......................................................................................
Processor Status Registers .................................................................................
Exceptions and Exception Vectors .......................................................................
The 16-BIS/32-BIS Concept ..................................................................................
16-BIS/32-BIS Advantages ...................................................................................
Co-Processor 15 (CP15) ......................................................................................
ARM Subsystem
Page
59
60
60
61
62
62
63
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2.1
Introduction
This chapter describes the ARM subsystem and its associated memories. The ARM subsystem consists of
the following components:
• ARM926EJ-S™ 32-bit RISC CPU
• 16-KB Instruction cache
• 16-KB Data cache
• Memory Management Unit (MMU)
• Co-Processor 15 (CP15) to control MMU, cache, etc.
• Jazelle™ Java Accelerator
• ARM Internal Memory
– 8 KB RAM
– 64 KB built-in ROM
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer
– Support for 32-bit ARM/16-bit THUMB instruction sets
– Fixed little-endian memory format
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The
ARM926EJ-S processor targets multi-tasking applications where full memory management, high
performance, low die size, and low power are all important.
The ARM926EJ-S processor supports the 32-bit ARM and the 16-bit THUMB instruction sets, enabling
you to trade off between high performance and high code density. This includes features for efficient
execution of Java byte codes and providing Java performance similar to Just in Time (JIT) Java interpreter
without associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard architecture and provides
a complete high performance subsystem, including the following:
• An ARM926EJ-S integer core
• A Memory Management Unit (MMU)
• Separate instruction and data Advanced Microcontroller Bus Architecture (AHBA) Advanced High
Performance Bus (AHB) bus interfaces
NOTE: There is no TCM memory and interface on this device.
The ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM core also has 8 KB RAM (typically used for vector table) and 64 KB ROM (for boot images)
associated with it. The RAM/ROM locations are not accessible by any other master peripherals.
Furthermore, the ARM has DMA and CFG bus master ports via the AHB interface.
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59
Operating States/Modes
2.2
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Operating States/Modes
The ARM can operate in two states: ARM (32-bit) mode and THUMB (16-bit) mode. You can switch the
ARM926EJ-S processor between ARM mode and THUMB mode using the BX instruction.
The ARM can operate in the following modes:
• User mode (USR): Non-privileged mode, usually for the execution of most application programs.
• Fast interrupt mode (FIQ): Fast interrupt processing
• Interrupt mode (IRQ): Normal interrupt processing
• Supervisor mode (SVC): Protected mode of execution for operating systems
• Abort mode (ABT): Mode of execution after a data abort or a pre-fetch abort
• System mode (SYS): Privileged mode of execution for operating systems
• Undefined mode (UND): Executing an undefined instruction causes the ARM to enter undefined mode.
You can only enter privileged modes (system or supervisor) from other privileged modes.
To enter supervisor mode from user mode, generate a software interrupt (SWI). An IRQ interrupt causes
the processor to enter the IRQ mode. An FIQ interrupt causes the processor to enter the FIQ mode.
Different stacks must be set up for different modes. The stack pointer (SP) automatically changes to the
SP of the mode that was entered.
2.3
Processor Status Registers
The processor status register (PSR) controls the enabling and disabling of interrupts and setting the mode
of operation of the processor. The 8 least-significant bits PSR[7:0] are the control bits of the processor.
PSR[27:8] are reserved bits and PSR[31:28] are status registers. The details of the control bits are:
• Bit 7 - I bit: Disable IRQ (I =1) or enable IRQ (I = 0)
• Bit 6 - F bit: Disable FIQ (F = 1) or enable FIQ (F = 0)
• Bit 5 - T bit: Controls whether the processor is in thumb mode (T = 1) or ARM mode (T = 0)
• Bits 4:0 Mode: Controls the mode of operation of the processor
– PSR [4:0] = 10000 : User mode
– PSR [4:0] = 10001 : FIQ mode
– PSR [4:0] = 10010 : IRQ mode
– PSR [4:0] = 10011 : Supervisor mode
– PSR [4:0] = 10111 : Abort mode
– PSR [4:0] = 11011 : Undefined mode
– PSR [4:0] = 11111 : System mode
Status bits show the result of the most recent ALU operation. The details of status bits are:
• Bit 31 - N bit: Negative or less than
• Bit 30 - Z bit: Zero
• Bit 29 - C bit: Carry or borrow
• Bit 28 - V bit: Overflow or underflow
NOTE: See the Programmer’s Model of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
60
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Exceptions and Exception Vectors
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2.4
Exceptions and Exception Vectors
Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that
occur in an ARM system are given below:
• Reset exception: processor reset
• FIQ interrupt: fast interrupt
• IRQ interrupt: normal interrupt
• Abort exception: abort indicates that the current memory access could not be completed. The abort
could be a pre-fetch abort or a data abort.
• SWI interrupt: use software interrupt to enter supervisor mode.
• Undefined exception: occurs when the processor executes an undefined instruction
The exceptions in the order of highest priority to lowest priority are: reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction, and SWI. SWI and undefined instruction have the same priority. The ARM is
configured with the VINITHI signal set high (VINITHI = 1), such that the vector table is located at address
FFFF 0000h. This address maps to the beginning of the ARM local RAM (8 KB).
NOTE: The VINITHI signal is configurable by way of the register setting in CP15. However, it is not
recommended to set VINITHI = 0, as the device has no physical memory in the 0000 0000h
address region.
The default vector table is shown in Table 2-1.
Table 2-1. Exception Vector Table for ARM
Vector Offset Address
Exception
Mode on entry
I Bit State on Entry
F Bit State on Entry
0h
Reset
Supervisor
Set
Set
4h
Undefined instruction
Undefined
Set
Unchanged
8h
Software interrupt
Supervisor
Set
Unchanged
Ch
Pre-fetch abort
Abort
Set
Unchanged
10h
Data abort
Abort
Set
Unchanged
14h
Reserved
—
—
—
18h
IRQ
IRQ
Set
Unchanged
1Ch
FIQ
FIQ
Set
Set
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The 16-BIS/32-BIS Concept
2.5
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The 16-BIS/32-BIS Concept
The key idea behind 16-BIS is that of a super-reduced instruction set. Essentially, the ARM926EJ
processor has two instruction sets:
• ARM mode or 32-BIS: the standard 32-bit instruction set
• THUMB mode or 16-BIS: a 16-bit instruction set
The 16-bit instruction length (16-BIS) allows the 16-BIS to approach twice the density of standard 32-BIS
code while retaining most of the 32-BIS’s performance advantage over a traditional 16-bit processor using
16-bit registers. This is possible because 16-BIS code operates on the same 32-bit register set as 32-BIS
code. 16-bit code can provide up to 65% of the code size of the 32-bit code and 160% of the performance
of an equivalent 32-BIS processor connected to a 16-bit memory system.
2.6
16-BIS/32-BIS Advantages
16-bit instructions operate with the standard 32-bit register configuration, allowing excellent interoperability between 32-BIS and 16-BIS states. Each 16-bit instruction has a corresponding 32-bit
instruction with the same effect on the processor model. The major advantage of a 32-bit architecture over
a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a
large address space efficiently. When processing 32-bit data, a 16-bit architecture takes at least two
instructions to perform the same task as a single 32-bit instruction. However, not all of the code in a
program processes 32-bit data (for example, code that performs character string handling), and some
instructions (like branches) do not process any data at all. If a 16-bit architecture only has 16-bit
instructions, and a 32-bit architecture only has 32-bit instructions, then the 16-bit architecture has better
code density overall, and has better than one half of the performance of the 32-bit architecture. Clearly,
32-bit performance comes at the cost of code density. The 16-bit instruction breaks this constraint by
implementing a 16-bit instruction length on a 32-bit architecture, making the processing of 32-bit data
efficient with compact instruction coding. This provides far better performance than a 16-bit architecture,
with better code density than a 32-bit architecture. The 16-BIS also has a major advantage over other 32bit architectures with 16-bit instructions. The advantage is the ability to switch back to full 32-bit code and
execute at full speed. Thus, critical loops for applications such as fast interrupts can be coded using the
full 32-BIS and linked with 16-BIS code. The overhead of switching from 16-bit code to 32-bit code is
folded into sub-routine entry time. Various portions of a system can be optimized for speed or for code
density by switching between 16-BIS and 32-BIS execution, as appropriate.
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2.7
Co-Processor 15 (CP15)
The system control coprocessor (CP15) is used to configure and control instruction and data caches,
Tightly-Coupled Memories (TCMs), Memory Management Units (MMUs), and many system functions. The
CP15 registers are only accessible with MRC and MCR instructions by the ARM in a privileged mode like
supervisor mode or system mode.
2.7.1 Addresses in an ARM926EJ-S System
Three different types of addresses exist in an ARM926EJ-S system. They are listed in Table 2-2.
Table 2-2. Different Address Types in ARM System
Domain
ARM9EJ-S
Caches and MMU
TCM and AMBA Bus
Address type
Virtual Address (VA)
Modified Virtual Address (MVA)
Physical Address (PA)
An example of the address manipulation that occurs when the ARM9EJ-S core requests an instruction is
shown in Example 2-1
Example 2-1. Address Manipulation
The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated to the MVA. The Instruction Cache (Icache) and Memory Management Unit (MMU) detect
the MVA.
If the protection check carried out by the MMU on the MVA does not abort and the MVA tag is in the Icache,
the instruction data is returned to the ARM9EJ-S core.
If the protection check carried out by the MMU on the MVA does not abort, and the MVA tag is not in the
cache, then the MMU translates the MVA to produce the PA.
NOTE: See the Programmers Model of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
2.7.2 Memory Management Unit (MMU)
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as
SymbianOS, WindowsCE, and Linux. A single set of two level page tables stored in main memory controls
the address translation, permission checks, and memory region attributes for both data and instruction
accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information
held in the page tables.
The MMU features are as follows:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access protection scheme.
• Mapping sizes are 1 MB (sections), 64 KB (large pages), 4 KB (small pages) and 1 KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10
NOTE: See the Memory Management Unit of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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2.7.3 Caches and Write Buffer
The ARM926EJ-S processor includes:
• An Instruction cache (Icache)
• A Data cache (Dcache)
• A write buffer
The size of the data cache is 16 KB, instruction cache is 16 KB, and write buffer is 17 bytes.
The caches have the following features:
• Virtual index, virtual tag, addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32 bytes per line), and two
dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
• Perform critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown and controlling cache pollution.
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the
TAGRAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
• Cache maintenance operations to provide efficient invalidation of the following:
– The entire Dcache or Icache
– Regions of the Dcache or Icache
– The entire Dcache
– Regions of virtual memory
• They also provide operations for efficient cleaning and invalidation of the following:
– The entire Dcache
– Regions of the Dcache
– Regions of virtual memory
The write buffer is used for all writes to a non-cachable bufferable region, write-through region, and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines.
The main write buffer has a 16-word data buffer and a four-address buffer.
The Dcache write-back has eight data word entries and a single address entry.
The MCR drain write buffer enables both write buffers to be drained under software control.
The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be
put into a low power state until an interrupt occurs.
NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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Chapter 3
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System Interconnect
Topic
3.1
3.2
...........................................................................................................................
Page
Introduction ....................................................................................................... 66
System Interconnect Block Diagram ..................................................................... 67
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Introduction
3.1
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Introduction
The ARM, the EDMA3 transfer controllers, and the device peripherals are interconnected through a switch
fabric architecture (see Section 3.2). The switch fabric is composed of multiple switched central resources
(SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals
and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Bridges are mainly used to perform bus-width conversion as well as bus
operating frequency conversion.
The ARM, the EDMA3 transfer controllers, and the various device peripherals can be classified into two
categories: master peripherals and slave peripherals. Master peripherals are typically capable of initiating
read and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to
and from them. The system master peripherals include the ARM, the EDMA3 transfer controllers, EMAC,
and USB2.0. Not all master peripherals may connect to all slave peripherals. The supported connections
are designated by an X in Table 3-1.
Table 3-1. AM1802 ARM Microprocessor System Interconnect Matrix
Masters
Master
Default
Priority
ARM
RAM
EMIFA
DDR2/
mDDR
128K
RAM
EDMA3_0_
TC0/TC1
EDMA3_1_
TC0
Peripheral
Group (1)
EDMA3_0_CC0
0
EDMA3_1_CC0
0
EDMA3_0_TC0
0
X
X
X
X
X
X
EDMA3_0_TC1
0
X
X
X
X
X
X
ARM I
2
X
X
X
X
X
ARM D
2
X
X
X
X
X
X
X
X
EDMA3_1_TC0
4
X
X
X
X
X
X
EMAC
4
X
X
X
USB2.0
4
X
X
X
(1)
66
Slaves
ARM
ROM,
AINTC
X
X
Peripheral group: SYSCFG, EMAC, GPIO, I2C0, McASP0, MDIO, MMC/SD0, PLLC0, PLLC1, PSC0, PSC1, RTC, SPI0, SPI1,
TIMER64P0, TIMER64P1, TIMER64P2, TIMER64P3, EDMA3_0_CC0, EDMA3_1_CC0, UART0, UART1, UART2, USB0
(USB2.0).
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3.2
System Interconnect Block Diagram
Figure 3-1 shows a system interconnect block diagram.
Figure 3-1. System Interconnect Block Diagram
USB0 VBUSP
USB0 CDMA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
SCR F1
EMAC
SCR F0
BR F0
BR F6
SCR F4
128 KB
On-chip RAM
MPU1
BR F1
SCR F3
EDMA3_0_TC0
EDMA3_0_TC1
rd
MPU2
DDR2/mDDR
EDMA3_1_CC0
wr
SCR1
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
rd
wr
EDMA3_1_CC0
EDMA3_1_TC0
PSC0
rd
SCR5
wr
SCR F5
EDMA3_1_TC0
PLLC0
USB0 Cfg
SYSCFG0
BR5
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 2 Clock Domain
Clock Domain: SYSCLK6 [CPU/1 Synchronous]
ARM-I
BR3
BR1
SCR0
ARM-D
Timer64P0
BR4
SCR6
BR2
SYSCFG1
Timer64P1
EMAC
I2C0
SCR F6
RTC
BR0
BR6
EMAC MDIO
GPIO
PSC1
PLLC1
BR8
Async 1 Clock Domain
AINTC
BR7
BR F3
EMIFA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 3 [PLL1] Clock Domain
ARM ROM
UART1
ARM RAM
BR F4
SCR F7
UART2
McASP0
SCR2
MMC/SD0
SCR4
SPI0
UART0
Legend:
32-bit BUS
64-bit BUS
EDMA3_0_TC0
IP Module
Synchronous Bridge
Asynchronous Bridge
SCR
EDMA3_0_TC1
Timer64P2
BR F5
SCR F8
Timer64P3
SPI1
Paths with dashed lines cross the subchip boundary
EDMA3_0_CC0
EDMA3_0_CC0
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System Memory
Topic
4.1
4.2
4.3
68
...........................................................................................................................
Page
Introduction ....................................................................................................... 69
ARM Memories................................................................................................... 69
Peripherals ........................................................................................................ 69
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4.1
Introduction
This device has multiple on-chip/off-chip memories and several external device interfaces associated with
and various subsystems. To help simplify software development, a unified memory-map is used wherever
possible to maintain a consistent view of device resources across all masters.
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
4.2
ARM Memories
The configuration for the ARM internal memory is:
• 8 KB ARM local RAM
• 64 KB ARM local ROM
• 16 KB Instruction Cache and 16 KB Data cache
The ARM RAM/ROM are only accessible by ARM and PRU0.
On-Chip RAM Memory
This device also offers an on-chip 128-KB single-port RAM, apart from the ARM internal memories. This
on-chip RAM is accessible by the ARM, and is also accessible by several master peripherals. Writes to
this RAM by all masters is atomic.
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIF:
– 8/16-bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM,
NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space
• DDR2/mDDR memory controller:
– 16-bit DDR2 with up to 256-MB memory address space
– 16-bit mDDR with up to 256-MB memory address space
Internal Peripherals
The peripheral only accessible by the ARM is the ARM interrupt controller (AINTC). For more information
on the AINTC, see the ARM Interrupt Controller (AINTC) chapter.
4.3
Peripherals
The ARM has access to all peripherals. This also includes system modules like the PLL controller (PLLC),
the power and sleep controller (PSC), and the system configuration module (SYSCFG). See the devicespecific data manual for the complete list of peripherals supported on your device.
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Memory Protection Unit (MPU)
Topic
5.1
5.2
5.3
70
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Introduction ....................................................................................................... 71
Architecture....................................................................................................... 72
MPU Registers ................................................................................................... 77
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5.1
Introduction
This device supports two memory protection units (MPU1 and MPU2). MPU1 supports the 128KB on-chip
RAM and MPU2 supports the DDR2/mDDR SDRAM.
5.1.1 Purpose of the MPU
The memory protection unit (MPU) is provided to manage access to memory. The MPU allows you to
define multiple ranges and limit access to system masters based on their privilege ID. The MPU can
record a detected fault, or invalid access, and notify the system through an interrupt.
5.1.2 Features
The MPU supports the following features:
• Supports multiple programmable address ranges
• Supports 0 or 1 fixed range
• Supports read, write, and execute access privileges
• Supports privilege ID associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• Supports protection of its own registers
5.1.3 Block Diagram
Figure 5-1 shows a block diagram of the MPU. An access to a protected memory must pass through the
MPU. During an access, the MPU checks the memory address on the input data bus against fixed and
programmable ranges. If allowed, the transfer is passed unmodified to the output data bus. If the transfer
fails the protection check then the MPU does not pass the transfer to the output bus but rather services
the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor
as well as generating an interrupt about the fault. The MPU generates two interrupts: an address error
interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).
Figure 5-1. MPU Block Diagram
MPU
Input
Data
Bus
Protection
Checks
Output
Data
Bus
MPU_ADDR_ERR_INT
MMRs
MPU_PROT_ERR_INT
MPU Register Bus
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5.1.4 MPU Default Configuration
Two MPUs are supported on the device, one for the 128KB on-chip RAM and one for the DDR2/mDDR
SDRAM. Table 5-1 shows the memory regions protected by each MPU. Table 5-2 shows the configuration
of each MPU.
Table 5-1. MPU Memory Regions
Memory Region
Unit
Memory Protection
Start Address
End Address
MPU1
128KB On-chip RAM
8000 0000h
8001 FFFFh
MPU2
DDR2/mDDR SDRAM
C000 0000h
DFFF FFFFh
Table 5-2. MPU Default Configuration
Setting
MPU1
MPU2
Assume allowed
Assume allowed
Number of allowed IDs supported
12
12
Number of fixed ranges supported
1
0
Default permission
Number of programmable ranges supported
Compare width
5.2
6
12
1 KB granularity
64 KB granularity
Architecture
5.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
ARM CPU instruction and data accesses have a privilege level associated with them. See the ARM926EJS Technical Reference Manual (TRM), downloadable from http://infocenter.arm.com/help/index.jsp for
more details on privilege levels of the ARM CPU.
Table 5-3 shows the privilege ID of the CPU and every mastering peripheral. Table 5-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.
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Table 5-3. Device Master Settings
Master
Privilege Level
Access Type
EDMA3_0_CC0
Privilege ID
Inherited
Inherited
DMA
EDMA3_0_TC0 and EDMA3_0_TC1
Inherited
Inherited
DMA
EDMA3_1_CC0
Inherited
Inherited
DMA
EDMA3_1_TC0
Inherited
Inherited
DMA
ARM (instruction access)
0
Software dependant
Instruction
ARM (data access)
0
Software dependant
Data
EMAC
4
Supervisor
Data/DMA
USB2.0
6
Supervisor
DMA
5.2.2 Memory Protection Ranges
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory. One of the programmable
address ranges could be used to detect accesses to this unpopulated memory.
The MPU divides its assigned memory into address ranges. Each MPU can support one fixed address
range and multiple programmable address ranges. The fixed address range is configured to an exact
address. The programmable address range allows software to program the start and end addresses.
Each address range has the following set of registers:
• Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending
address of the address range.
• Memory protection page attribute register (MPPA): Use to program the permission settings of the
address range.
It is allowed to configure ranges such that they overlap each other. In this case, all the overlapped ranges
must allow the access, otherwise the access is not allowed. The final permissions given to the access are
the lowest of each type of permission from any hit range.
Addresses not covered by a range are either allowed or disallowed based on the configuration of the
MPU. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the
ASSUME_ALLOWED bit in the configuration register (CONFIG).
5.2.3 Permission Structures
The MPU defines a per-range permission structure with three permission fields in a 32-bit permission
entry. Figure 5-2 shows the structure of a permission entry.
Figure 5-2. Permission Fields
31
22
21
20
Reserved
15
14
13
12
11
10
9
Allowed IDs
AID5
AID4
AID3
AID2
8
6
AID11
AID10
5
4
Reserved
AID1
AID0
19
18
17
16
Allowed IDs
AIX
AID9
AID8
AID7
AID6
3
2
1
0
UW
UX
Access Types
SR
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SX
UR
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Requestor-ID Based Access Controls
Each master on the device has an N-bit code associated with it that identifies it for privilege purposes.
This privilege ID accompanies all memory accesses made on behalf of that master. That is, when a
master triggers a memory access command, the privilege ID will be carried alongside the command.
Each memory protection range has an allowed ID (AID) field associated with it that indicates which
requestors may access the given address range. The MPU maps the privilege IDs of all the possible
requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA).
• AID0 through AID11 are used to specify the allowed privilege IDs.
• An additional allowed ID bit, AIDX, captures access made by all privilege IDs not covered by AID0
through AID11.
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies
access to the corresponding requestor.
5.2.3.2
Request-Type Based Permissions
The memory protection model defines three fundamental functional access types: read, write, and
execute. Read and write refer to data accesses -- accesses originating via the load/store units on the CPU
or via a master peripheral. Execute refers to accesses associated with an instruction fetch.
The memory protection model allows controlling read, write, and execute permissions independently for
both user and supervisor mode. This results in six permission bits, listed in Table 5-4. For each bit, a 1
permits the access type and a 0 denies access. For example, UX = 1 means that User Mode may execute
from the given page. The memory protection unit allows you to specify all six of these bits separately; 64
different encodings are permitted altogether, although programs might not use all of them.
Table 5-4. Request Type Access Controls
74
Bit
Field
Description
5
SR
Supervisor may read
4
SW
Supervisor may write
3
SX
Supervisor may execute
2
UR
User may read
1
UW
User may write
0
UX
User may execute
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5.2.4 Protection Check
During a memory access, the MPU checks if the address range of the input transfer overlaps one of the
address ranges. When the input transfer address is within a range the transfer parameters are checked
against the address range permissions.
The MPU first checks the transfers privilege ID against the AID settings. If the AID bit is 0, then the range
will not be checked; if the AID bit is 1, then the transfer parameters are checked against the memory
protection page attribute register (MPPA) values to detect an allowed access.
For non-debug accesses, the read, write, and execute permissions are also checked. There is a set of
permissions for supervisor mode and a set for user mode. For supervisor mode accesses, the SR, SW,
and SX bits are checked. For user mode accesses, the UR, UW, and UX bits are checked.
If the transfer address range does not match any address range then the transfer is either allowed or
disallowed based on the configuration of the MPU. The MPU can be configured for assumed allowed or
assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register
(CONFIG).
In the case that a transfer spans multiple address ranges, all the overlapped ranges must allow the
access, otherwise the access is not allowed. The final permissions given to the access are the lowest of
each type of permission from any hit range. Therefore, if a transfer matches 2 ranges, one that is RW and
one that is RX, then the final permission is just R.
5.2.5 MPU Register Protection
Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page
attribute registers (MPPA) is also protected. All non-debug writes must be by a supervisor entity. A
protection fault can occur from a register write with invalid permissions and this triggers an interrupt just
like a memory access.
Faults are not recorded (nor interrupts generated) for debug accesses.
5.2.6 Invalid Accesses and Exceptions
When a transfer fails the protection check, the MPU does not pass the transfer to the output bus. The
MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.
The behavior of the MPU depends on whether the access was a read or a write:
• For a read: The MPU returns 0s, a permission value is 0 (no access allowed), a protection error status.
• For a write: The MPU receives all the write data and returns a protection error status.
The MPU captures system faults due to addressing or protection violations in its registers. The MPU can
store the fault information for only one fault, so the first detected fault is recorded into the fault registers
and an interrupt is generated. Software must use the fault clear register (FLTCLR) to clear the fault status
so that another fault can be recorded. The MPU will not record another fault nor generate another interrupt
until the existing fault has been cleared. Also, additional faults will be ignored. Faults are not recorded (no
interrupts generated) for debug accesses.
5.2.7 Reset Considerations
After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection
features.
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5.2.8 Interrupt Support
5.2.8.1
Interrupt Events and Requests
The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection
interrupt (MPU_PROT_ERR_INT). The MPU_ADDR_ERR_INT is generated when there is an addressing
violation due to an access to a non-existent location in the MPU register space. The
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined
ranges or to the MPU registers.
The transfer parameters that caused the violation are saved in the MPU registers.
5.2.8.2
Interrupt Multiplexing
The interrupts from both MPUs are combined with the boot configuration module into a single interrupt
called MPU_BOOTCFG_ERR. The combined interrupt is routed to the ARM interrupt controller. Table 5-5
shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR.
Table 5-5. MPU_BOOTCFG_ERR Interrupt Sources
Interrupt
Source
MPU1_ADDR_ERR_INT
MPU1 address error interrupt
MPU1_PROT_ERR_INT
MPU1 protection interrupt
MPU2_ADDR_ERR_INT
MPU2 address error interrupt
MPU2_PROT_ERR_INT
MPU2 protection interrupt
BOOTCFG_ADDR_ERR
Boot configuration address error
BOOTCFG_PROT_ERR
Boot configuration protection error
5.2.9 Emulation Considerations
Memory and MPU registers are not protected against emulation accesses.
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5.3
MPU Registers
There are two MPUs on the device. Each MPU contains a set of memory-mapped registers.
Table 5-6 lists the memory-mapped registers for the MPU1. Table 5-7 lists the memory-mapped registers
for the MPU2.
Table 5-6. Memory Protection Unit 1 (MPU1) Registers
Address
Acronym
Register Description
01E1 4000h
REVID
Revision identification register
Section 5.3.1
Section
01E1 4004h
CONFIG
Configuration register
Section 5.3.2
01E1 4010h
IRAWSTAT
Interrupt raw status/set register
Section 5.3.3
01E1 4014h
IENSTAT
Interrupt enable status/clear register
Section 5.3.4
01E1 4018h
IENSET
Interrupt enable set register
Section 5.3.5
01E1 401Ch
IENCLR
Interrupt enable clear register
01E1 4200h
PROG1_MPSAR
Programmable range 1 start address register
Section 5.3.10.1
01E1 4204h
PROG1_MPEAR
Programmable range 1 end address register
Section 5.3.11.1
01E1 4208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 4210h
PROG2_MPSAR
Programmable range 2 start address register
Section 5.3.10.1
01E1 4214h
PROG2_MPEAR
Programmable range 2 end address register
Section 5.3.11.1
01E1 4218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 4220h
PROG3_MPSAR
Programmable range 3 start address register
Section 5.3.10.1
01E1 4224h
PROG3_MPEAR
Programmable range 3 end address register
Section 5.3.11.1
01E1 4228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 4230h
PROG4_MPSAR
Programmable range 4 start address register
Section 5.3.10.1
01E1 4234h
PROG4_MPEAR
Programmable range 4 end address register
Section 5.3.11.1
01E1 4238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 4240h
PROG5_MPSAR
Programmable range 5 start address register
Section 5.3.10.1
01E1 4244h
PROG5_MPEAR
Programmable range 5 end address register
Section 5.3.11.1
01E1 4248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 4250h
PROG6_MPSAR
Programmable range 6 start address register
Section 5.3.10.1
01E1 4254h
PROG6_MPEAR
Programmable range 6 end address register
Section 5.3.11.1
01E1 4258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
Section 5.3.12
01E1 4300h
FLTADDRR
Fault address register
Section 5.3.13
01E1 4304h
FLTSTAT
Fault status register
Section 5.3.14
01E1 4308h
FLTCLR
Fault clear register
Section 5.3.15
Section 5.3.6
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Table 5-7. Memory Protection Unit 2 (MPU2) Registers
Address
Acronym
Register Description
01E1 5000h
REVID
Revision identification register
Section 5.3.1
01E1 5004h
CONFIG
Configuration register
Section 5.3.2
01E1 5010h
IRAWSTAT
Interrupt raw status/set register
Section 5.3.3
01E1 5014h
IENSTAT
Interrupt enable status/clear register
Section 5.3.4
01E1 5018h
IENSET
Interrupt enable set register
Section 5.3.5
01E1 501Ch
IENCLR
Interrupt enable clear register
Section 5.3.6
01E1 5100h
FXD_MPSAR
Fixed range start address register
Section 5.3.7
01E1 5104h
FXD_MPEAR
Fixed range end address register
Section 5.3.8
01E1 5108h
FXD_MPPA
Fixed range memory protection page attributes register
Section 5.3.9
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Table 5-7. Memory Protection Unit 2 (MPU2) Registers (continued)
78
Address
Acronym
Register Description
01E1 5200h
PROG1_MPSAR
Programmable range 1 start address register
Section 5.3.10.2
01E1 5204h
PROG1_MPEAR
Programmable range 1 end address register
Section 5.3.11.2
01E1 5208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 5210h
PROG2_MPSAR
Programmable range 2 start address register
Section 5.3.10.2
01E1 5214h
PROG2_MPEAR
Programmable range 2 end address register
Section 5.3.11.2
01E1 5218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 5220h
PROG3_MPSAR
Programmable range 3 start address register
Section 5.3.10.2
01E1 5224h
PROG3_MPEAR
Programmable range 3 end address register
Section 5.3.11.2
01E1 5228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 5230h
PROG4_MPSAR
Programmable range 4 start address register
Section 5.3.10.2
01E1 5234h
PROG4_MPEAR
Programmable range 4 end address register
Section 5.3.11.2
01E1 5238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 5240h
PROG5_MPSAR
Programmable range 5 start address register
Section 5.3.10.2
01E1 5244h
PROG5_MPEAR
Programmable range 5 end address register
Section 5.3.11.2
01E1 5248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 5250h
PROG6_MPSAR
Programmable range 6 start address register
Section 5.3.10.2
01E1 5254h
PROG6_MPEAR
Programmable range 6 end address register
Section 5.3.11.2
01E1 5258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
01E1 5260h
PROG7_MPSAR
Programmable range 7 start address register
Section 5.3.10.2
01E1 5274h
PROG7_MPEAR
Programmable range 7 end address register
Section 5.3.11.2
01E1 5268h
PROG7_MPPA
Programmable range 7 memory protection page attributes register
01E1 5270h
PROG8_MPSAR
Programmable range 8 start address register
Section 5.3.10.2
01E1 5274h
PROG8_MPEAR
Programmable range 8 end address register
Section 5.3.11.2
01E1 5278h
PROG8_MPPA
Programmable range 8 memory protection page attributes register
01E1 5280h
PROG9_MPSAR
Programmable range 9 start address register
Section 5.3.10.2
01E1 5284h
PROG9_MPEAR
Programmable range 9 end address register
Section 5.3.11.2
01E1 5288h
PROG9_MPPA
Programmable range 9 memory protection page attributes register
01E1 5290h
PROG10_MPSAR
Programmable range 10 start address register
Section 5.3.10.2
01E1 5294h
PROG10_MPEAR
Programmable range 10 end address register
Section 5.3.11.2
01E1 5298h
PROG10_MPPA
Programmable range 10 memory protection page attributes register
01E1 52A0h
PROG11_MPSAR
Programmable range 11 start address register
Section 5.3.10.2
01E1 52A4h
PROG11_MPEAR
Programmable range 11 end address register
Section 5.3.11.2
01E1 52A8h
PROG11_MPPA
Programmable range 11 memory protection page attributes register
01E1 52B0h
PROG12_MPSAR
Programmable range 12 start address register
Section 5.3.10.2
01E1 52B4h
PROG12_MPEAR
Programmable range 12 end address register
Section 5.3.11.2
01E1 52B8h
PROG12_MPPA
Programmable range 12 memory protection page attributes register
Section 5.3.12
01E1 5300h
FLTADDRR
Fault address register
Section 5.3.13
01E1 5304h
FLTSTAT
Fault status register
Section 5.3.14
01E1 5308h
FLTCLR
Fault clear register
Section 5.3.15
Memory Protection Unit (MPU)
Section
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
Section 5.3.12
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5.3.1 Revision Identification Register (REVID)
The revision ID register (REVID) contains the MPU revision. The REVID is shown in Figure 5-3 and
described in Table 5-8.
Figure 5-3. Revision ID Register (REVID)
31
0
REV
R-4E81 0101h
LEGEND: R = Read only; -n = value after reset
Table 5-8. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E81 0101h
Description
Revision ID of the MPU.
5.3.2 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown
in Figure 5-4 and described in Table 5-9.
NOTE: Although the NUM_AIDS bit defaults to 12 (Ch), not all AIDs may be supported on your
device. Unsupported AIDs should be cleared to 0 in the memory page protection attributes
registers (MPPA). See for a list of AIDs supported on your device.
Figure 5-4. Configuration Register (CONFIG)
31
24
15
23
20
19
16
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-0 (1) or 6h (2)
R-0 (1) or 1 (2)
R-6h (1) or Ch (2)
12
11
1
0
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-Ch
R-0
R-1
LEGEND: R = Read only; -n = value after reset
(1)
(2)
For MPU1.
For MPU2.
Table 5-9. Configuration Register (CONFIG) Field Descriptions
Field
Value
Description
31-24
Bit
ADDR_WIDTH
0-FFh
Address alignment (2n KByte alignment) for range checking.
23-20
NUM_FIXED
0-Fh
Number of fixed address ranges.
19-16
NUM_PROG
0-Fh
Number of programmable address ranges.
15-12
NUM_AIDS
0-Fh
Number of supported AIDs.
11-1
Reserved
0
0
ASSUME_ALLOWED
Reserved
Assume allowed. When an address is not covered by any MPU protection range, this bit
determines whether the transfer is assumed to be allowed or not allowed.
0
Assume is disallowed.
1
Assume is allowed.
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5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 5-5 and described in Table 5-10.
Figure 5-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
80
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 5-6 and described in Table 511.
Figure 5-6. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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5.3.5 Interrupt Enable Set Register (IENSET)
Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Software can
write to IENSET to enable an interrupt. Writes of 0 have no effect. The IENSET is shown in Figure 5-7 and
described in Table 5-12.
Figure 5-7. Interrupt Enable Set Register (IENSET)
31
16
Reserved
R-0
15
2
1
0
ADDRERR_EN
PROTERR_EN
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-12. Interrupt Enable Set Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved
Address violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
PROTERR_EN
Protection violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
5.3.6 Interrupt Enable Clear Register (IENCLR)
Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Software can
write to IENCLR to clear/disable an interrupt. Writes of 0 have no effect. The IENCLR is shown in
Figure 5-8 and described in Table 5-13.
Figure 5-8. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-13. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
82
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved
Address violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
PROTERR_CLR
Protection violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
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5.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPSAR and the fixed range end
address register (FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in Figure 5-9.
Figure 5-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
5.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPEAR and the fixed range start
address register (FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 5-10.
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 5-11
and described in Table 5-14.
Figure 5-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-14. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
84
Controls access from ID = n.
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR)
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory, especially memory. One of the
programmable address ranges could be used to detect accesses to this unpopulated
memory.
The programmable range n start address register (PROGn_MPSAR) holds the start address for the range
n. The PROGn_MPSAR is writeable by a supervisor entity only.
The start address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 KBbyte; the page size for MPU2 is 64 KBytes. The size of the page determines
the width of the address field in PROGn_MPSAR and the programmable range n end address register
(PROGn_MPEAR). For example, to protect a 64-KB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
5.3.10.1 MPU1 Programmable Range n Start Address Register (PROG1_MPSAR-PROG6_MPSAR)
The PROGn_MPSAR for MPU1 is shown in Figure 5-12 and described in Table 5-15.
Figure 5-12. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
Reserved
R/W-20 0000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-15. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
START_ADDR
Reserved
20 0000h–
20 007Fh
0
Description
Start address for range N .
Reserved
5.3.10.2 MPU2 Programmable Range n Start Address Register (PROG1_MPSAR-PROG12_MPSAR)
The PROGn_MPSAR for MPU2 is shown in Figure 5-13 and described in Table 5-16.
Figure 5-13. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
31
16 15
0
START_ADDR
Reserved
R/W-C000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
Field
31-16
START_ADDR
15-0
Reserved
Value
C000h–DFFFh
0
Description
Start address for range N.
Reserved
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5.3.11 Programmable Range n End Address Registers (PROGn_MPEAR)
The programmable range n end address register (PROGn_MPEAR) holds the end address for the range
n. This register is writeable by a supervisor entity only.
The end address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 KByte; the page size for MPU2 is 64 KBytes. The size of the page determines the
width of the address field in the programmable range n start address register (PROGn_MPSAR) and
PROGn_MPEAR. For example, to protect a 64-KB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
5.3.11.1 MPU1 Programmable Range n End Address Register (PROG1_MPEAR-PROG6_MPEAR)
The PROGn_MPEAR for MPU1 is shown in Figure 5-14 and described in Table 5-17.
Figure 5-14. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
Reserved
R/W-20 007Fh
R-3FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-17. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
END_ADDR
Reserved
20 0000h–
20 007Fh
3FFh
Description
End address for range N.
Reserved
5.3.11.2 MPU2 Programmable Range n End Address Register (PROG1_MPEAR-PROG12_MPEAR)
The PROGn_MPEAR for MPU2 is shown in Figure 5-15 and described in Table 5-18.
Figure 5-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
31
16 15
0
END_ADDR
Reserved
R/W-DFFFh
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
Field
31-16
END_ADDR
15-0
Reserved
86
Value
C000h–DFFFh
FFFFh
Memory Protection Unit (MPU)
Description
Start address for range N.
Reserved
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5.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA)
The programmable range n memory protection page attributes register (PROGn_MPPA) holds the
permissions for the region n. This register is writeable only by a supervisor entity. The PROGn_MPPA is
shown in Figure 5-16 and described in Table 5-19.
Figure 5-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-19. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Controls access from ID = n.
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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5.3.13 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) holds the address of the first protection fault transfer. The
FLTADDRR is shown in Figure 5-17 and described in Table 5-20.
Figure 5-17. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-20. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
88
Field
FLTADDR
Value
0-FFFF FFFFh
Memory Protection Unit (MPU)
Description
Memory address of fault.
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5.3.14 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in Figure 5-18 and described in Table 5-21.
Figure 5-18. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
Reserved
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-21. Fault Status Register (FLTSTAT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MSTID
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
Value
0
0-FFh
0
0-Fh
0
0-3Fh
Description
Reserved
Master ID of fault transfer.
Reserved
Privilege ID of fault transfer.
Reserved
Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).
0
No fault.
1h
User execute fault.
2h
User write fault.
3h
Reserved
4h
User read fault.
5h-7h
8h
9h-Fh
Reserved
Supervisor execute fault.
Reserved
10h
Supervisor write fault.
11h
Reserved
12h
Relaxed cache write back fault.
13h-1Fh
20h
21h-3Eh
3Fh
Reserved
Supervisor read fault.
Reserved
Relaxed cache line fill fault.
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5.3.15 Fault Clear Register (FLTCLR)
The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured
in the fault status register (FLTSTAT) as well as produce an interrupt. Only the TYPE bit field in FLTSTAT
is cleared when a 1 is written to the CLEAR bit. The FLTCLR is shown in Figure 5-19 and described in
Table 5-22.
Figure 5-19. Fault Clear Register (FLTCLR)
31
16
Reserved
R-0
15
1
0
Reserved
CLEAR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 5-22. Fault Clear Register (FLTCLR) Field Descriptions
Bit
31-1
0
90
Field
Reserved
Value
0
CLEAR
Description
Reserved
Command to clear the current fault. Writing 0 has no effect.
0
No effect.
1
Clear the current fault.
Memory Protection Unit (MPU)
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Chapter 6
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Device Clocking
Topic
6.1
6.2
6.3
...........................................................................................................................
Page
Overview ........................................................................................................... 92
Frequency Flexibility .......................................................................................... 94
Peripheral Clocking ............................................................................................ 95
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Overview
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Overview
This device requires two primary reference clocks:
• One reference clock is required for the phase-locked loop controllers (PLLCs)
• One reference clock is required for the real-time clock (RTC) module.
These reference clocks may be sourced from either the on-board oscillator via an externally supplied
crystal or by a direct external oscillator input. For detailed specifications on clock frequency and voltage
requirements, see the electrical specifications in your device-specific data manual.
In addition to the reference clocks required for the PLLCs and RTC module, some peripherals, such as the
USB, may also require an input reference clock to be supplied. All possible input clocks are described in
Table 6-1. The CPU and the majority of the device peripherals operate at fixed ratios of the primary
system/ARM clock frequency, as listed in Table 6-2. However, there are two system clock domains that do
not require a fixed ratio to the ARM, these are PLL0_SYSCLK3 and PLL0_SYSCLK7. Figure 6-1 shows
the clocking architecture.
Table 6-1. Device Clock Inputs
Peripheral
Input Clock Signal Name
Oscillator/PLL
OSCIN
RTC
RTC_XI
JTAG
TCK, RTCK
EMAC RMII
RMII_MHZ_50_CLK
EMAC MII
MII_TXCLK, MII_RXCLK
USB2.0
USB_REFCLKIN
I2C0
I2C0_SCL
Timers
TM64Pn_IN12
SPIs
SPIn_CLK
McASP0
ACLKR, AHCLKR, ACLKX, AHCLKX
Table 6-2. System Clock Domains
92
CPU/Device Peripherals
System Clock Domain
Fixed Ratio to
ARM Clock Required?
Default Ratio to
ARM Clock
ARM RAM/ROM, On-chip RAM, UART0, EDMA, SPI0,
MMC/SDs, DDR2/mDDR (bus ports), USB2.0,
PLL0_SYSCLK2
Yes
1:2
EMIFA
PLL0_SYSCLK3
No
1:3
System configuration (SYSCFG), GPIO, PLLCs, PSCs, PLL0_SYSCLK4
EMAC/MDIO, ARM INTC
Yes
1:4
ARM
PLL0_SYSCLK6
Yes
1:1
EMAC RMII clock
PLL0_SYSCLK7
No
1:6
I2C0, Timer64P0/P1, RTC, USB2.0 PHY, McASP0
serial clock
PLL0_AUXCLK
Not Applicable
Not Applicable
DDR2/mDDR PHY
PLL1_SYSCLK1
Not Applicable
Not Applicable
PLL0 input reference clock
(not configured by default)
PLL1_SYSCLK3
Not Applicable
Not Applicable
UART1/2, Timer64P2/3, McASP0, SPI1
ASYNC3
Not Applicable
Not Applicable
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Figure 6-1. Overall Clocking Diagram
PLL0 Multiplier Out
Div 4.5
EMIFA (C)
0+
SYSCLK3 (/3)
SYSCLK6 (/1)
1
CFGCHIP3[EMA_CLKSRC]
ARM
On-chip RAM
ARM INTC
SYSCLK4 (/4)
ARM RAM/ROM
System CFG
PLL0
Controller
EDMA
PSCs
SPI0
EMAC/MDIO (D)
CLKSRC
MMC/SD0
GPIO
USB2.0 (A)
EXTCLKSRC
UART0
DDR2/mDDR (B)
I2C0
AUXCLK
Timers0/1
RTC
PLL
Ref CLK
Timers2/3
SYSCLK2 (/2)
0+
1
SYSCLK2 (/2)
PLL1
Controller
CFGCHIP3[ASYNC3_CLKSRC]
UART1/2
McASP0 (E)
SPI1
SYSCLK3 (/3)
+ Default Mux Selection
CLKSRC
A
See Section 6.3.1 for USB clocking.
B
See Section 6.3.2 for DDR2/mDDR clocking.
C
See Section 6.3.3 for EMIFA clocking.
D
See Section 6.3.4 for EMAC clocking.
E
See Section 6.3.5 for McASP clocking.
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Frequency Flexibility
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Frequency Flexibility
There are two PLLs on the device with similar architecture and behavior. Each PLL has two clocking
modes:
• PLL Bypass
• PLL Active
When the PLL is in Bypass mode, the reference clock supplied on OSCIN serves as the clock source from
which all of the system clocks (SYSCLK1 to SYSCLK7) are derived. This means that when the PLL is in
Bypass mode, the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that
creates each of the system clocks. For PLL0 only, the EXTCLKSRC bit in PLLCTL can be configured to
use PLL1_SYSCLK3 as the Bypass mode reference clock.
When the PLL operates in Active mode, the PLL is enabled and the PLL multiplier setting is used to
multiply the input clock frequency supplied on the OSCIN pin up to the desired frequency. It is this
multiplied frequency that all system clocks are derived from in PLL Active mode.
The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the
system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1 to SYSCLK7). Each
SYSCLKn has a PLLDIVn block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter
for more details on the PLL.
The combination of the PLL multiplier, POSTDIV, and PLLDIV blocks provides flexibility in the frequencies
that the system clock domains support. This flexibility does have limitations, as follows:
• OSCIN input frequency is limited to a supported range.
• The output of the PLL Multiplier must be within the range specified in the device-specific data manual.
• The output of each PLLDIV block must be less than or equal to the maximum device frequency
specified in the device-specific data manual.
NOTE: The above limitations are provided here as an example and are used to illustrate the
recommended configuration of the PLL controller. These limitations may vary based on core
voltage and between devices. See the device-specific data manual for more details.
Table 6-3 shows examples of possible PLL multiplier settings, along with the available PLL post-divider
modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL
post-divider control register (POSTDIV). For Div1, Div2, Div3, and Div4 modes, the RATIO field would be
programmed to 0, 1, 2, and 3, respectively. The Div1, Div2, Div3, and Div4 modes are shown here as an
example. Additional post-divider modes are supported and are documented in the Phase-Locked Loop
Controller (PLLC) chapter.
NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases.
To decrease PLL power consumption, the lowest PLL multiplier (PLLM) setting should be
chosen that achieves the desired frequency. For example, if 200 MHz is the desired CPU
operating frequency and the OSCIN frequency is 25 MHz; lower power consumption is
achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2
instead of a PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these
modes would result in a CPU frequency of 200 MHz.
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Table 6-3. Example PLL Frequencies
6.3
OSCIN
Frequency
PLL Multiplier
Multiplier
Frequency
Div1
Div2
Div3
Div4
20
30
600 MHz
600
300
200
150
24
25
600 MHz
600
300
200
150
25
24
600 MHz
600
300
200
150
30
20
600 MHz
600
300
200
150
20
25
500 MHz
500
250
167
125
24
20
480 MHz
480
240
160
120
25
18
450 MHz
450
225
150
112.5
30
14
420 MHz
420
210
140
105
25
16
400 MHz
400
200
133
100
Peripheral Clocking
6.3.1 USB Clocking
Figure 6-2 shows the clock connections for the USB2.0 module. Note that there is no built-in oscillator.
The USB2.0 subsystem requires a reference clock for its internal PLL. This reference clock can be
sourced from either the USB_REFCLKIN pin or from the AUXCLK of the system PLL. The reference clock
input to the USB2.0 subsystem is selected by programming the USB0PHYCLKMUX bit in the chip
configuration 2 register (CFGCHIP2) of the System Configuration Module. The USB_REFCLKIN source
should be selected when it is not possible (such as when specific audio rates are required) to operate the
device at one of the allowed input frequencies to the USB2.0 subsystem. The USB2.0 subsystem
peripheral bus clock is sourced from PLL0_SYSCLK2. Table 6-4 determines the source origination as well
as the source input frequency to the USB 2.0 PHY. Once the clock source origination (internal/external)
and its frequency is determined, the firmware should program the PHY PLL with the correct input
frequency via CFGCHIP2.USB0REF_FREQ.
Figure 6-2. USB Clocking Diagram
USB_
AUXCLK REFCLKIN
CFGCHIP2[USB0PHYCLKMUX]
1
0
USB 2.0
Subsystem
(USB0)
Table 6-4. USB Clock Multiplexing Options
CFGCHIP2.
USB0PHYCLKMUX
bit
USB2.0
Clock
Source
0
USB_REFCLKIN
USB_REFCLKIN must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be configured to accept any of these input
clock frequencies.
1
PLL0_AUXCLK
PLL0_AUXCLK must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be configured to accept any of these input
clock frequencies.
Additional Conditions
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6.3.2 DDR2/mDDR Memory Controller Clocking
The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see
Figure 6-3):
• VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO, write FIFO, and read FIFO of
the DDR2/mDDR memory controller. From this, VCLK drives the interface to the peripheral bus.
• 2X_CLK is sourced from PLL1_SYSCLK1.
2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
Table 6-5 shows example PLL register settings based on the OSCIN reference clock frequency of
25 MHz. From these example configurations, the following observations are made:
• To achieve the maximum frequency (150 MHz) supported by the DDR2/mDDR memory controller and
the typical CPU frequency of 300 MHz, the output of the PLL multiplier should be set to be 300 MHz
and the DDR_CLK source should be set to PLL1_SYSCLK1.
• The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier
block.
• The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock
frequencies.
• For certain PLL1 multiplier and PLL1 post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK1 as the clock source for 2X_CLK.
If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the
application as a free running clock that could be used by an FPGA or for some other purpose, then
2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. This
allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while
still providing a clock on the DDR_CLK and DDR_CLK.
NOTE: DDR_CLK and DDR_CLK are output clock signals.
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Figure 6-3. DDR2/mDDR Memory Controller Clocking Diagram
On Chip
PLL0_SYSCLK2/2
DDR2/mDDR
Memory
Controller
LPSC #6
DDR_CLK
DDR_CLK
VCLK
PLL1_SYSCLK1
2X_CLK
DDR
PHY
MCLK
Table 6-5. DDR2/mDDR Memory Controller MCLK Frequencies
OSCIN
Frequency
PLL1
Multiplier
Register
Setting
PLL1
Multiplier
Frequency
PLL1 Post
Divider
Mode (1)
PLL1
POSTDIV
Output
Frequency
PLL1
PLLDIV1
Register
Setting
PLL1_SYSCLK1
MCLK
24
18h
600 MHz
Div2
300 MHz
8000h
300 MHz
150 MHz
24
15h
528 MHz
Div2
264 MHz
8000h
264 MHz
132 MHz
24
14h
504 MHz
Div2
252 MHz
8000h
252 MHz
126 MHz
(1)
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.3 EMIFA Clocking
EMIFA requires a single input clock source. The EMIFA clock can be sourced from either PLL0_SYSCLK3
or DIV4P5 (see Figure 6-4). The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the
System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock
source for EMIFA.
Selecting the appropriate clock source for EMIFA is determined by the desired clock rate. Table 6-6 shows
example PLL register settings and the resulting DIV4P5 and PLL0_SYSCLK3 frequencies based on the
OSCIN reference clock frequency of 25 MHz. From these example configurations, the following
observations can be made:
• To achieve a typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300
MHz, the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be
set to PLL0_SYSCLK3 with the PLLDIV3 register set to 3.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV3 block that sets the divider ratio for PLL0_SYSCLK3 can be changed to achieve various
clock frequencies.
Figure 6-4. EMIFA Clocking Diagram
LPSC
PLL Controller
SYSCLK3
0
DIV4P5 CLK
1
EMIFA
CFGCHIP3[EMA_CLKSRC]
Table 6-6. EMIFA Frequencies
OSCIN
Frequency
PLL Multiplier
Register
Multiplier
Setting
Frequency
Post Divider
Mode (1)
POSTDIV
Output
Frequency
25
24
Div2
300 MHz
Div3
200 MHz
25
18
25
(1)
98
16
600 MHz
450 MHz
400 MHz
DIV4P5
PLLDIV3
Register
Setting
PLL0_SYSCLK3
133 MHz
2
100 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
Div2
225 MHz
100 MHz
3
56.3 MHz
2
75 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
Div2
200 MHz
89 MHz
2
66.6 MHz
1
100 MHz
Div3
133 MHz
89 MHz
1
66.5 MHz
Div4
100 MHz
89 MHz
0
100 MHz
See Section 6.2 for explanation of POSTDIV divider modes.
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6.3.4 EMAC Clocking
The EMAC module sources its peripheral bus interface reference clock from PLL0_SYSCLK4 that is at a
fixed ratio of the CPU clock. The external clock requirement for EMAC varies with the interface used.
When the MII interface is active, the MII_TXCLK and MII_RXCLK signals must be provided from an
external source. When the RMII interface is active, the RMII 50 MHz reference clock is sourced either
from an external clock on the RMII_MHZ_50_CLK pin or from PLL0_SYSCLK7 (as shown in Figure 6-5).
The PINMUX15_3_0 bits in the pin multiplexing control 15 register (PINMUX15) of the System
Configuration Module control this clock selection:
• PINMUX15_3_0 = 0: enables sourcing of the 50 MHz reference clock from an external source on the
RMII_MHZ_50_CLK pin.
• PINMUX15_3_0 = 8h: enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7. Also,
PLL0_SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin.
Table 6-7 shows example PLL register settings and the resulting PLL0_SYSCLK7 frequencies based on
the OSCIN reference clock frequency of 25 MHz.
Figure 6-5. EMAC Clocking Diagram
On Chip
PLL Controller 0
LPSC
EMAC
SYSCLK4
SYSCLK7
50 MHz Reference Clock
PINMUX15[3:0]
1000 0000
3-State
0000 1000
RMII_MHZ_50_CLK
Signal
NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of
50 MHz +/-50 ppm.
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Table 6-7. EMAC Reference Clock Frequencies
OSCIN
Frequency
PLL Multiplier
Register Setting
Multiplier
Frequency
Post Divider
Mode (1)
POSTDIV Output
Frequency
PLLDIV7
Register
Setting
PLL0_SYSCLK7
25
24
600 MHz
Div2
300 MHz
5
50 MHz
Div3
200 MHz
3
50 MHz
Div4
150 MHz
2
50 MHz
Div2
225 MHz
Div3
150 MHz
Div4
112.5 MHz
25
(1)
(2)
18
450 MHz
Not Applicable (2)
2
50 MHz
Not Applicable (2)
See Section 6.2 for explanation of POSTDIV divider modes.
Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7.
6.3.5 McASP Clocking
As shown in Figure 6-6, the McASP peripheral requires multiple clock sources. Internally, the module
clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC
bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module.
The transmit and receive clocks are sourced internally or externally by configuring the McASP clock
control registers ACLKRCTL, AHCLKRCTL, ACLKXCTL, and AHCLKXCTL. If an external clock is driven
into a high-frequency master clock (AHCLKX or AHCLKR), the McASP module allows for a mixed clock
mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the highfrequency master clock through a programmable divider.
When the internal clock source option is selected, the transmit and receive clocks are derived from the
PLL0_AUXCLK clock through programmable dividers.
Figure 6-6. McASP Clocking Diagram
On Chip
CFGCHIP3[ASYNC3_CLKSRC]
PLL0_SYSCLK2
0
LPSC
PLL1_SYSCLK2
Module
Clock
McASP0
1
PLL0_AUXCLK
TX/RX
Reference
Clock
Clock
Generator
Frame Sync
Generator
ACLKX
AHCLKX
AFSX
AFSR
ACLKR
AHCLKR
100
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6.3.6 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
The peripherals can be divided into the following groups, depending upon their clock requirements, as
shown in Table 6-8.
Table 6-8. Peripherals
Peripherals
Contained
within Group
Source of Peripheral Clock
RTC
—
Peripheral Group
Peripheral Group Definition
RTC
Operates off of a dedicated 32 kHz
crystal oscillator.
Fixed-Frequency Peripherals
As the name suggests, fixedTimer64P0/P1
frequency peripherals have a fixedI2C0
frequency. They are fed the
AUXCLK directly from the oscillator
input.
—
Synchronous peripherals have their MMC/SD0
frequencies derived from the ARM
UART0
clock frequency. The peripheral
GPIO
system clock frequency changes
accordingly, if the PLL0 frequency
changes. Most synchronous
peripherals have internal dividers
so they can generate their required
clock frequencies.
PLL0_SYSCLK2
Asynchronous peripherals are not
required to operate at a fixed ratio
of the ARM clock.
UART1/2
ASYNC3
Timer64P2/P3
ASYNC3
EMIFA
DIV_4P5 or PLL0_SYSCLK3
DDR2/mDDR
PLL1_SYSCLK1 or
PLL1 Direct Output
McASP0
ASYNC3 or
Peripheral Serial Clock
SPI0
PLL0_SYSCLK2 or
Peripheral Serial Clock
SPI1
ASYNC3 or
Peripheral Serial Clock
EMAC
PLL0_SYSCLK4 or
RMII_MHZ_50_CLK
USB2.0
USB_REFCLKIN or AUXCLK
Synchronous Peripherals
Asynchronous Peripherals
Synchronous/Asynchronous
Peripherals
Synchronous/asynchronous
peripherals can be run with either
internally generated synchronous
clocks, or externally generated
asynchronous clocks.
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PLL0_SYSCLK2
PLL0_SYSCLK4
Device Clocking
101
Chapter 7
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Phase-Locked Loop Controller (PLLC)
Topic
7.1
7.2
7.3
102
...........................................................................................................................
Page
Introduction ..................................................................................................... 103
PLL Controllers ................................................................................................ 103
PLLC Registers ................................................................................................ 108
Phase-Locked Loop Controller (PLLC)
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7.1
Introduction
This device has two phase-locked loop (PLL) controllers, PLLC0 and PLLC1. These PLL controllers
provide clock signals to most of the components of the device through various clock dividers.
Both PLL0 and PLL1 provide the following:
• Glitch-free transitions when clock settings are changed
• Domain clock alignment
• Clock gating
• PLL power-down
The clock outputs generated by the PLL controllers are:
• Domain clocks: PLL0_SYSCLK[1-7] and PLL1_SYSCLK[1-3]
• Auxiliary clock (PLL0_AUXCLK) from the PLLC0 reference clock source
Dividers that can be used for the PLL controllers are:
• Pre-PLL divider: PREDIV
• Post-PLL divider: POSTDIV
• SYSCLK divider: D1, …, Dn
Various other control signals supported are:
• PLL multiplier: PLLM
• Software-programmable PLL bypass: PLLEN
7.2
PLL Controllers
PLL0 and PLL1 share the same internal architecture so they also share the same approach for mode
configuration.
PLL0 provides the primary system clock to the device. PLL0 operations are software programmable
through the PLL controller 0 (PLLC0) registers.
PLL1 provides the reference clocks to various peripherals (including DDR2/mDDR) and may generate
clocks that are asynchronous to the PLL0 clocks. PLL1 operations are software programmable through the
PLL controller 1 (PLLC1) registers.
Figure 7-1 shows the PLLC0 and PLLC1 architecture.
The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register (PLLM).
The PLLM defaults to a multiplier value of 13h at power-up, which results in a PLL multiplier of 20×. The
PLL0 and PLL1 output clocks may be divided-down for slower device operation using the PLL post-divider
control register (POSTDIV). The POSTDIV has a default value of /2, but may be modified through
software (using the RATIO field in POSTDIV) to achieve lower device operation frequencies. The default
PLLM and POSTDIV settings produce a 300-MHz PLL output clock when given a 30-MHz clock source.
At power-up, PLL0 and PLL1 are powered-down/disabled and must be powered-up by software through
the PLLPWRDN bit in their respective PLL control register (PLLCTL). Before each PLL completes the
power-up and frequency-lock sequence, the system operates in bypass mode by default and the system
clock (OSCIN) is provided directly from an input reference clock (square wave or internal oscillator)
selected by the CLKMODE bit in PLLCTL. After the power-up and frequency-lock sequences are
complete, software can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
The PLL controller registers are listed in Section 7.3.
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Figure 7-1. PLLC Structure
PLL Controller 0
PLLCTL[EXTCLKSRC]
PLL1_SYSCLK3
PLLCTL[CLKMODE]
1
PLLCTL[PLLEN]
0
OSCIN
0
Square
Wave
1
Crystal
0
PREDIV
POSTDIV
PLL
1
PLLM
DEEPSLEEP
Enable
PLLDIV1 (/1)
SYSCLK1
PLLDIV2 (/2)
SYSCLK2
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
PLLDIV3 (/3)
SYSCLK3
EMIFA
Internal
Clock
Source
0
1
DIV4.5
CFGCHIP3[EMA_CLKSRC]
AUXCLK
PLLC0 OBSCLK
(CLKOUT Pin)
DIV4.5
OSCDIV
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
PLLC1 OBSCLK
OCSEL[OCSRC]
PLLCTL[PLLEN]
0
POSTDIV
PLL
1
PLLM
SYSCLK1
SYSCLK2
SYSCLK3
PLL Controller 1
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV1 (/1)
SYSCLK1
DDR2/mDDR
Internal
Clock
Source
14h
17h
18h
19h
OSCDIV
PLLC1 OBSCLK
OCSEL[OCSRC]
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7.2.1 Device Clock Generation
The PLL controllers (PLLC0 and PLLC1) manage the clock ratios, alignment, and gating for the device
system clocks. Various PLL mode attributes such as pre-division, multiplier, and post-division are software
programmable through the PLL controller registers. Additionally, the reset controller in PLLC0 manages
reset propagation through the device, clock alignment, and test points.
The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the
SYSCLK dividers can handle. The POSTDIV stage should be programmed to keep the input to the
SYSCLK dividers within operating limits. See the device datasheet for the maximum operating
frequencies.
PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. These
reference clocks are summarized in Table 7-1. Some output clock dividers require fixed values so that
clock ratios between various device components are maintained regardless of PLL or bypass frequency.
Table 7-1. System PLLC Output Clocks
Output Clock
Used by
Default Ratio
(relative to PLLn_SYSCLK1)
Fixed Clock
Ratio
PLLC0 (1)
PLL0_SYSCLK1
Not used
/1
Yes
PLL0_SYSCLK2
ARM RAM/ROM, On-chip RAM, UART0,
EDMA, SPI0, MMC/SD0, DDR2/mDDR (bus
ports), USB2.0
/2
Yes
PLL0_SYSCLK3 (2)
EMIFA
/3
No
PLL0_SYSCLK4
System configuration (SYSCFG), GPIO,
PLLCs, PSCs, EMAC/MDIO, ARM INTC
/4
Yes
PLL0_SYSCLK5
Not used
/3
No
PLL0_SYSCLK6
ARM
/1
Yes
PLL0_SYSCLK7
EMAC RMII clock
PLL0_AUXCLK
I2C0, Timer64P0/P1, RTC, USB2.0 PHY,
McASP0 serial clock
PLL0_OBSCLK
Observation clock (OBSCLK) source
/6
No
PLL bypass clock
No
Pin configurable
No
PLLC1
PLL1_SYSCLK1
DDR2/mDDR PHY
/1 or disabled
No
PLL1_SYSCLK2 (3)
UART1/2, Timer64P2/3, McASP0, SPI1 (all
these modules use PLL0_SYSCLK2 by
default)
/2 or disabled
No
PLL1_SYSCLK3 (4)
PLL0 input reference clock
(not configured by default)
/3 or disabled
No
(1)
(2)
(3)
(4)
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
PLLC0 supports an additional post-divider value of /4.5 that can be used for EMIFA clock generation. When this /4.5 value is
used, the resulting clock will not have a 50% duty cycle. Instead, the duty cycle will be 44.4%. The EMIFA uses PLL0_SYSCLK3
by default, but can be configured to use a /4.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the
EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG)
module.
The ASYNC3 modules use PLL0_SYSCLK2 by default, but all these modules can be configured as a group to use
PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system
configuration (SYSCFG) module.
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit
in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN.
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7.2.2 Steps for Programming the PLLs
Note that there is a lock mechanism implemented to protect the PLL controller registers. See
Section 7.2.2.1 for information on unlocking the PLL controller registers.
Refer to the appropriate subsection on how to program the PLL clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 7.2.2.2.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 7.2.2.3 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and only the SYSCLK dividers will be updated,
follow the sequence in Section 7.2.2.4.
Note that the PLLs are powered down after a Power-on Reset (POR). The PLLs are not powered down
after a Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the
PLLDIVx registers are reset to default values.
7.2.2.1
Locking/Unlocking PLL Register Access
A lock mechanism is implemented on the device to prevent inadvertent writes to the PLL controller
registers. This provides protection from stopping modules when the module clocks are disabled. For
example, the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally
disabled.
The PLL lock bits are located within the system configuration (SYSCFG) module:
• When set, the PLL_MASTER_LOCK bit in the chip configuration 0 register (CFGCHIP0) locks PLLC0.
• When set, the PLL1_MASTER_LOCK bit in the chip configuration 3 register (CFGCHIP3) locks PLLC1.
Because the SYSCFG module has its own lock mechanism, the SYSCFG module must be unlocked first
by writing to the KICK0R and KICK1R registers before the PLL lock bits can be cleared. Like the KICK
registers, the PLL lock bits can only be modified while in a privileged mode. See the System Configuration
(SYSCFG) Module chapter for information on privilege type and the KICK0R and KICK1R registers.
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 and the PLL1_MASTER_LOCK bit in
CFGCHIP3 default to unlocked after reset, so the following procedure is only required if the
PLLs have been locked (set to 1).
To modify the PLL controller registers, use the following sequence:
1. Write the correct key values to KICK0R and KICK1R registers.
2. Clear the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
3. Configure the desired PLL controller register values.
4. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
5. Write an incorrect key value to the KICK0R and KICK1R registers.
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7.2.2.2
Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Program the CLKMODE bit in PLLC0 PLLCTL.
2. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
3. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 (brings PLL out of power-down mode).
5. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
6. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
8. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
7.2.2.3
Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), perform the following
procedure to change the PLL multiplier:
1. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
2. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
3. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
4. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
5. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
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Changing SYSCLK Dividers
If the PLL is already operating at the desired multiplier mode, perform the following procedure to change
the SYSCLK divider values:
1. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress).
2. Program the RATIO field in PLLDIVn.
3. Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7.3
PLLC Registers
Table 7-2 lists the memory-mapped registers for the PLLC0 and Table 7-3 lists the memory-mapped
registers for the PLLC1.
Table 7-2. PLL Controller 0 (PLLC0) Registers
Address
Acronym
Register Description
01C1 1000h
REVID
PLLC0 Revision Identification Register
Section 7.3.1
01C1 10E4h
RSTYPE
PLLC0 Reset Type Status Register
Section 7.3.3
01C1 10E8h
RSCTRL
PLLC0 Reset Control Register
Section 7.3.4
01C1 1100h
PLLCTL
PLLC0 Control Register
Section 7.3.5
01C1 1104h
OCSEL
PLLC0 OBSCLK Select Register
Section 7.3.7
01C1 1110h
PLLM
PLLC0 PLL Multiplier Control Register
Section 7.3.9
01C1 1114h
PREDIV
PLLC0 Pre-Divider Control Register
Section 7.3.10
01C1 1118h
PLLDIV1
PLLC0 Divider 1 Register
Section 7.3.11
01C1 111Ch
PLLDIV2
PLLC0 Divider 2 Register
Section 7.3.13
01C1 1120h
PLLDIV3
PLLC0 Divider 3 Register
Section 7.3.15
01C1 1124h
OSCDIV
PLLC0 Oscillator Divider 1 Register
Section 7.3.21
01C1 1128h
POSTDIV
PLLC0 PLL Post-Divider Control Register
Section 7.3.23
01C1 1138h
PLLCMD
PLLC0 PLL Controller Command Register
Section 7.3.24
01C1 113Ch
PLLSTAT
PLLC0 PLL Controller Status Register
Section 7.3.25
01C1 1140h
ALNCTL
PLLC0 Clock Align Control Register
Section 7.3.26
01C1 1144h
DCHANGE
PLLC0 PLLDIV Ratio Change Status Register
Section 7.3.28
01C1 1148h
CKEN
PLLC0 Clock Enable Control Register
Section 7.3.30
01C1 114Ch
CKSTAT
PLLC0 Clock Status Register
Section 7.3.32
01C1 1150h
SYSTAT
PLLC0 SYSCLK Status Register
Section 7.3.34
01C1 1160h
PLLDIV4
PLLC0 Divider 4 Register
Section 7.3.17
01C1 1164h
PLLDIV5
PLLC0 Divider 5 Register
Section 7.3.18
01C1 1168h
PLLDIV6
PLLC0 Divider 6 Register
Section 7.3.19
01C1 116Ch
PLLDIV7
PLLC0 Divider 7 Register
Section 7.3.20
01C1 11F0h
EMUCNT0
PLLC0 Emulation Performance Counter 0 Register
Section 7.3.36
01C1 11F4h
EMUCNT1
PLLC0 Emulation Performance Counter 1 Register
Section 7.3.37
108 Phase-Locked Loop Controller (PLLC)
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Table 7-3. PLL Controller 1 (PLLC1) Registers
Address
Acronym
Register Description
01E1 A000h
REVID
PLLC1 Revision Identification Register
Section 7.3.2
Section
01E1 A100h
PLLCTL
PLLC1 Control Register
Section 7.3.6
01E1 A104h
OCSEL
PLLC1 OBSCLK Select Register
Section 7.3.8
01E1 A110h
PLLM
PLLC1 PLL Multiplier Control Register
Section 7.3.9
01E1 A118h
PLLDIV1
PLLC1 Divider 1 Register
Section 7.3.12
01E1 A11Ch
PLLDIV2
PLLC1 Divider 2 Register
Section 7.3.14
01E1 A120h
PLLDIV3
PLLC1 Divider 3 Register
Section 7.3.16
01E1 A124h
OSCDIV
PLLC1 Oscillator Divider 1 Register
Section 7.3.22
01E1 A128h
POSTDIV
PLLC1 PLL Post-Divider Control Register
Section 7.3.23
01E1 A138h
PLLCMD
PLLC1 PLL Controller Command Register
Section 7.3.24
01E1 A13Ch
PLLSTAT
PLLC1 PLL Controller Status Register
Section 7.3.25
01E1 A140h
ALNCTL
PLLC1 Clock Align Control Register
Section 7.3.27
01E1 A144h
DCHANGE
PLLC1 PLLDIV Ratio Change Status Register
Section 7.3.29
01E1 A148h
CKEN
PLLC1 Clock Enable Control Register
Section 7.3.31
01E1 A14Ch
CKSTAT
PLLC1 Clock Status Register
Section 7.3.33
01E1 A150h
SYSTAT
PLLC1 SYSCLK Status Register
Section 7.3.35
01E1 A1F0h
EMUCNT0
PLLC1 Emulation Performance Counter 0 Register
Section 7.3.36
01E1 A1F4h
EMUCNT1
PLLC1 Emulation Performance Counter 1 Register
Section 7.3.37
7.3.1 PLLC0 Revision Identification Register (REVID)
The PLLC0 revision identification register (REVID) is shown in Figure 7-2 and described in Table 7-4.
Figure 7-2. PLLC0 Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -n = value after reset
Table 7-4. PLLC0 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 3C00h
Description
Peripheral revision ID for PLLC0.
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7.3.2 PLLC1 Revision Identification Register (REVID)
The PLLC1 revision identification register (REVID) is shown in Figure 7-3 and described in Table 7-5.
Figure 7-3. PLLC1 Revision Identification Register (REVID)
31
0
REV
R-4481 4400h
LEGEND: R = Read only; -n = value after reset
Table 7-5. PLLC1 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 4400h
Description
Peripheral revision ID for PLLC1.
7.3.3 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) latches the cause of the last reset. If multiple reset sources are
asserted simultaneously, RSTYPE records the reset source that deasserts last. If multiple reset sources
are asserted and deasserted simultaneously, RSTYPE latches the highest priority reset source. RSTYPE
is shown in Figure 7-4 and described in Table 7-6.
Figure 7-4. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
PLLSWRST
XWRST
POR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-3
2
1
0
110
Field
Reserved
Value
0
PLLSWRST
Description
Reserved
PLL software reset.
0
PLL soft reset was not the last reset to occur.
1
PLL soft was the last reset to occur.
XWRST
External warm reset.
0
External warm reset was not the last reset to occur.
1
External warm reset was the last reset to occur.
POR
Power on reset.
0
Power On Reset (POR) was not the last reset to occur.
1
Power On Reset (POR) was the last reset to occur.
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7.3.4 PLLC0 Reset Control Register (RSCTRL)
The reset control register (RSCTRL) allows the device to perform a software-initiated reset. Before writing
to the SWRST bit, the register must be unlocked by writing the key value of 5A69h to the KEY bit field.
The KEY bit field reads back as Ch when the register is unlocked; any other key value is invalid and
indicates that the register is locked. Any write to the register following a successful unlock relocks the
register. RSCTRL is shown in Figure 7-5 and described in Table 7-7.
Figure 7-5. Reset Control Register (RSCTRL)
31
17
16
Reserved
SWRST
R-0
R/W-1
15
0
KEY
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7. Reset Control Register (RSCTRL) Field Descriptions
Bit
31-17
16
15-0
Field
Reserved
Value
0
SWRST
KEY
Description
Reserved
PLL software reset. Register must be unlocked before writing to this bit. Writes are possible only
when qualified with a valid key.
0
In software reset
1
Not in software reset
0-FFFFh
RSCTRL unlock key. Key used to enable writes to RSCTRL.
3h
Register is locked when read value is 3h.
Ch
Register is unlocked when read value is Ch.
5A69h
RSCTRL unlock key
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7.3.5 PLLC0 Control Register (PLLCTL)
The PLLC0 control register (PLLCTL) is shown in Figure 7-6 and described in Table 7-8.
Figure 7-6. PLLC0 Control Register (PLLCTL)
31
16
Reserved
R-0
15
10
7
6
9
8
Reserved
EXTCLKSRC
CLKMODE
R-0
R/W-0
R/W-0
5
4
3
2
1
0
Reserved
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-8. PLLC0 Control Register (PLLCTL) Field Descriptions
Bit
31-10
9
8
Reserved
Value
0
EXTCLKSRC
Description
Reserved
External clock source selection.
0
Use OSCIN for the PLL bypass clock.
1
Use PLL1_SYSCLK3 for the PLL bypass clock.
CLKMODE
Reference clock selection.
0
Internal oscillator (crystal)
1
Square wave
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
7-6
2
Reserved
1
PLLPWRDN
0
112
Field
PLL0 reset.
0
PLL0 reset is asserted.
1
PLL0 reset is not asserted.
0
Reserved
PLL0 power-down.
0
PLL0 is operating.
1
PLL0 is powered-down.
PLLEN
PLL0 mode enables.
0
PLL0 is in bypass mode.
1
PLL0 mode is enabled, not bypassed.
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7.3.6 PLLC1 Control Register (PLLCTL)
The PLLC1 control register (PLLCTL) is shown in Figure 7-7 and described in Table 7-9.
Figure 7-7. PLLC1 Control Register (PLLCTL)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
6
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-9. PLLC1 Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
2
Reserved
1
PLLPWRDN
0
PLL1 reset.
0
PLL1 reset is asserted.
1
PLL1 reset is not asserted.
0
Reserved
PLL1 power-down.
0
PLL1 is operating.
1
PLL1 is powered-down.
PLLEN
PLL1 mode enables.
0
PLL1 is in bypass mode.
1
PLL1 mode is enabled, not bypassed.
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7.3.7 PLLC0 OBSCLK Select Register (OCSEL)
The PLLC0 OBSCLK select register (OCSEL) controls which clock is output on the CLKOUT pin so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 7-8 and described in Table 7-10.
Figure 7-8. PLLC0 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-10. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC0 OBSCLK source. Output on CLKOUT pin.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
114
17h
PLL0_SYSCLK1
18h
PLL0_SYSCLK2
19h
PLL0_SYSCLK3
1Ah
PLL0_SYSCLK4
1Bh
PLL0_SYSCLK5
1Ch
PLL0_SYSCLK6
1Dh
PLL0_SYSCLK7
1Eh
PLLC1 OBSCLK
1Fh
Disabled
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7.3.8 PLLC1 OBSCLK Select Register (OCSEL)
The PLLC1 OBSCLK select register (OCSEL) controls which clock is output on PLLC1 OBSCLK so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 7-9 and described in Table 7-11.
Figure 7-9. PLLC1 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC1 OBSCLK source.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL1_SYSCLK1
18h
PLL1_SYSCLK2
19h
PLL1_SYSCLK3
1A-1Fh Reserved
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7.3.9 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 7-10 and described in Table 7-12.
Figure 7-10. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PLLM
Value
0
0-1Fh
Description
Reserved
PLL multiplier select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV)
The PLLC0 pre-divider control register (PREDIV) is shown in Figure 7-11 and described in Table 7-13.
Figure 7-11. PLLC0 Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-14
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
116
Value
0
Description
Reserved
PLLC0 pre-divider enable.
0
PLLC0 pre-divider is disabled. Clock output from the PREDIV stage is disabled.
1
PLLC0 pre-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
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7.3.11 PLLC0 Divider 1 Register (PLLDIV1)
The PLLC0 divider 1 register (PLLDIV1) controls the divider for PLL0_SYSCLK1. PLLDIV1 is shown in
Figure 7-12 and described in Table 7-14.
Figure 7-12. PLLC0 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-14. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.3.12 PLLC1 Divider 1 Register (PLLDIV1)
The PLLC1 divider 1 register (PLLDIV1) controls the divider for PLL1_SYSCLK1. PLLDIV1 is shown in
Figure 7-13 and described in Table 7-15.
Figure 7-13. PLLC1 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
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7.3.13 PLLC0 Divider 2 Register (PLLDIV2)
The PLLC0 divider 2 register (PLLDIV2) controls the divider for PLL0_SYSCLK2. PLLDIV2 is shown in
Figure 7-14 and described in Table 7-16.
Figure 7-14. PLLC0 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
7.3.14 PLLC1 Divider 2 Register (PLLDIV2)
The PLLC1 divider 2 register (PLLDIV2) controls the divider for PLL1_SYSCLK2. PLLDIV2 is shown in
Figure 7-15 and described in Table 7-17.
Figure 7-15. PLLC1 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-17. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D2EN
14-5
Reserved
4-0
RATIO
118
Value
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
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7.3.15 PLLC0 Divider 3 Register (PLLDIV3)
The PLLC0 divider 3 register (PLLDIV3) controls the divider for PLL0_SYSCLK3. PLLDIV3 is shown in
Figure 7-16 and described in Table 7-18.
Figure 7-16. PLLC0 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-18. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
7.3.16 PLLC1 Divider 3 Register (PLLDIV3)
The PLLC1 divider 3 register (PLLDIV3) controls the divider for PLL1_SYSCLK3. PLLDIV3 is shown in
Figure 7-17 and described in Table 7-19.
Figure 7-17. PLLC1 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-0
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-19. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
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7.3.17 PLLC0 Divider 4 Register (PLLDIV4)
The PLLC0 divider 4 register (PLLDIV4) controls the divider for PLL0_SYSCLK4. PLLDIV4 is shown
inFigure 7-18 and described in Table 7-20.
Figure 7-18. PLLC0 Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-20. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D4EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 4 enable.
0
Divider 4 is disabled.
1
Divider 4 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4).
7.3.18 PLLC0 Divider 5 Register (PLLDIV5)
The PLLC0 divider 5 register (PLLDIV5) controls the divider for PLL0_SYSCLK5. PLLDIV5 is shown in
Figure 7-19 and described in Table 7-21.
Figure 7-19. PLLC0 Divider 5 Register (PLLDIV5)
31
16
Reserved
R-0
15
14
5
4
0
D5EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-21. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D5EN
14-5
Reserved
4-0
RATIO
120
Value
Description
Reserved
Divider 5 enable.
0
Divider 5 is disabled.
1
Divider 5 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
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7.3.19 PLLC0 Divider 6 Register (PLLDIV6)
The PLLC0 divider 6 register (PLLDIV6) controls the divider for PLL0_SYSCLK6. PLLDIV6 is shown in
Figure 7-20 and described in Table 7-22.
Figure 7-20. PLLC0 Divider 6 Register (PLLDIV6)
31
16
Reserved
R-0
15
14
5
4
0
D6EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-22. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D6EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 6 enable.
0
Divider 6 is disabled.
1
Divider 6 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
7.3.20 PLLC0 Divider 7 Register (PLLDIV7)
The PLLC0 divider 7 register (PLLDIV7) controls the divider for PLL0_SYSCLK7. PLLDIV7 is shown in
Figure 7-21 and described in Table 7-23.
Figure 7-21. PLLC0 Divider 7 Register (PLLDIV7)
31
16
Reserved
R-0
15
14
5
4
0
D7EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-23. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D7EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 7 enable.
0
Divider 7 is disabled.
1
Divider 7 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).
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7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)
The PLLC0 oscillator divider 1 register (OSCDIV) controls the divider for PLLC0 OBSCLK, dividing down
the clock selected as the PLLC0 OBSCLK source. The PLLC0 OBSCLK is connected to the CLKOUT pin.
The OSCDIV is shown in Figure 7-22 and described in Table 7-24.
Figure 7-22. PLLC0 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-24. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC0 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC0 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)
The PLLC1 oscillator divider 1 register (OSCDIV) controls the divider for PLLC1 OBSCLK, dividing down
the clock selected as the PLLC1 OBSCLK source. The PLLC1 OBSCLK signal may be selected as the
output on the CLKOUT pin. The OSCDIV is shown in Figure 7-23 and described in Table 7-25.
Figure 7-23. PLLC1 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-25. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
31-16
15
Field
Reserved
0
OD1EN
14-5
Reserved
4-0
RATIO
122
Value
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC1 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC1 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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7.3.23 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 7-24 and described in Table 7-26.
Figure 7-24. PLL Post-Divider Control Register (POSTDIV)
31
16
Reserved
R-0
15
14
5
4
0
POSTDEN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
POSTDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Post-divider enable.
0
Post-divider is disabled.
1
Post-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
7.3.24 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) contains the command bit for phase alignment. A write of
1 initiates the command; a write of 0 clears the bit, but has no effect. PLLCMD is shown in Figure 7-25
and described in Table 7-27.
Figure 7-25. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 7-27. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for phase alignment.
0
Clear bit (no effect)
1
Phase alignment
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7.3.25 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 7-26 and described in Table 7-28.
Figure 7-26. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
STABLE
Reserved
GOSTAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-28. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
124
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation. If 1, indicates GO operation is in progress.
0
GO operation is not in progress.
1
GO operation is in progress.
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7.3.26 PLLC0 Clock Align Control Register (ALNCTL)
The PLLC0 clock align control register (ALNCTL) indicates which PLL0_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 7-27 and described in Table 7-29.
Figure 7-27. PLLC0 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-3h
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-29. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
3h
ALN7
Description
Reserved
PLL0_SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN6
PLL0_SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN5
PLL0_SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN4
PLL0_SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN3
PLL0_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL0_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL0_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.3.27 PLLC1 Clock Align Control Register (ALNCTL)
The PLLC1 clock align control register (ALNCTL) indicates which PLL1_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 7-28 and described in Table 7-30.
Figure 7-28. PLLC1 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-30. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-3
2
1
0
126
Field
Reserved
Value
0
ALN3
Description
Reserved
PLL1_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL1_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL1_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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7.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC0 PLLDIV ratio change status register (DCHANGE) indicates if the PLL0_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 7-29 and described in Table 7-31.
Figure 7-29. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-31. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
0
SYS7
Description
Reserved
PLL0_SYSCLK7 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS6
PLL0_SYSCLK6 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS5
PLL0_SYSCLK5 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS4
PLL0_SYSCLK4 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS3
PLL0_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL0_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL0_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC1 PLLDIV ratio change status register (DCHANGE) indicates if the PLL1_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 7-30 and described in Table 7-32.
Figure 7-30. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-32. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-3
2
1
0
128
Field
Reserved
Value
0
SYS3
Description
Reserved
PLL1_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL1_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL1_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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7.3.30 PLLC0 Clock Enable Control Register (CKEN)
The PLLC0 clock enable control register (CKEN) controls the PLLC0 OBSCLK and AUXCLK clock. CKEN
is shown in Figure 7-31 and described in Table 7-33.
Figure 7-31. PLLC0 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-33. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK enable. Actual PLLC0 OBSCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 OBSCLK is disabled.
1
PLLC0 OBSCLK is enabled. For PLLC0 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC0 oscillator divider 1 register (OSCDIV) must be set to 1.
AUXEN
AUXCLK enable. Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 AUXCLK is disabled.
1
PLLC0 AUXCLK is enabled.
7.3.31 PLLC1 Clock Enable Control Register (CKEN)
The PLLC1 clock enable control register (CKEN) controls the PLLC1 OBSCLK clock. CKEN is shown in
Figure 7-32 and described in Table 7-34.
Figure 7-32. PLLC1 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-34. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK enable. Actual PLLC1 OBSCLK status is shown in the PLLC1 clock status register (CKSTAT).
0
PLLC1 OBSCLK is disabled.
1
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1.
0
Reserved
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7.3.32 PLLC0 Clock Status Register (CKSTAT)
The PLLC0 clock status register (CKSTAT) indicates the PLLC0 OBSCLK and AUXCLK on/off status. The
PLL0_SYSCLK status is shown in the PLLC0 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 7-33 and described in Table 7-35.
Figure 7-33. PLLC0 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R-1
R-1
LEGEND: R = Read only; -n = value after reset
Table 7-35. PLLC0 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
130
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK on status. PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC0 clock enable control register (CKEN).
0
PLLC0 OBSCLK is off.
1
PLLC0 OBSCLK is on.
AUXEN
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control
register (CKEN).
0
PLLC0 AUXCLK is off.
1
PLLC0 AUXCLK is on.
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7.3.33 PLLC1 Clock Status Register (CKSTAT)
The PLLC1 clock status register (CKSTAT) indicates the PLLC1 OBSCLK on/off status. The
PLL1_SYSCLK status is shown in the PLLC1 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 7-34 and described in Table 7-36.
Figure 7-34. PLLC1 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-2h
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-36. PLLC1 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK on status. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC1 clock enable control register (CKEN).
0
PLLC1 OBSCLK is off.
1
PLLC1 OBSCLK is on.
0
Reserved
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7.3.34 PLLC0 SYSCLK Status Register (SYSTAT)
The PLLC0 SYSCLK status register (SYSTAT) indicates the PLL0_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC0 PLLDIVn.
SYSTAT is shown in Figure 7-35 and described in Table 7-37.
Figure 7-35. PLLC0 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-1
7
6
5
4
3
2
1
0
Reserved
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-37. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-7
Reserved
6
SYS7ON
5
4
3
2
1
0
132
Value
3h
Description
Reserved
PLL0_SYSCLK7 on status.
0
Off
1
On
SYS6ON
PLL0_SYSCLK6 on status.
0
Off
1
On
SYS5ON
PLL0_SYSCLK5 on status.
0
Off
1
On
SYS4ON
PLL0_SYSCLK4 on status.
0
Off
1
On
SYS3ON
PLL0_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL0_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL0_SYSCLK1 on status.
0
Off
1
On
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7.3.35 PLLC1 SYSCLK Status Register (SYSTAT)
The PLLC1 SYSCLK status register (SYSTAT) indicates the PLL1_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC1 PLLDIVn.
SYSTAT is shown in Figure 7-36 and described in Table 7-38.
Figure 7-36. PLLC1 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-0
7
2
1
0
Reserved
3
SYS3ON
SYS2ON
SYS1ON
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
SYS3ON
1
0
Value
0
Description
Reserved
PLL1_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL1_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL1_SYSCLK1 on status.
0
Off
1
On
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7.3.36 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 7-37 and described in
Table 7-39. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 7-37. Emulation Performance Counter 0 Register (EMUCNT0)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-39. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit
31-0
Field
Value
COUNT
0-FFFF FFFFh
Description
Counter value for lower 64-bits.
7.3.37 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 7-38 and described in
Table 7-40. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 7-38. Emulation Performance Counter 1 Register (EMUCNT1)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit
31-0
134
Field
COUNT
Value
0-FFFF FFFFh
Description
Counter value for upper 64-bits.
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Chapter 8
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Power and Sleep Controller (PSC)
Topic
...........................................................................................................................
8.1
8.2
8.3
8.4
8.5
8.6
Introduction .....................................................................................................
Power Domain and Module Topology ..................................................................
Executing State Transitions ...............................................................................
IcePick Emulation Support in the PSC ................................................................
PSC Interrupts..................................................................................................
PSC Registers ..................................................................................................
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136
136
140
141
141
144
135
Introduction
8.1
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Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupts, a state machine for each
peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and
provides clock and reset control. Many of the operations of the PSC are transparent to user (software),
such as power on and reset control. However, the PSC module(s) also provide you with interface to
control several important power, clock and reset operations. The module level power, clock and reset
operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for L3 RAM)
• Supports IcePick emulation features: power, clock and reset
8.2
Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of:
• an Always On power domain
• an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in
the L3 RAM
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 8-1 and Table 8-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 8.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have an LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
NOTE: There are no LPSCs for peripherals in the Async2 clock domain (this includes RTC,
Timer64P0/P1, and I2C0); from a power savings stand point, clock-gating these peripherals
does not result in significant power savings.
Table 8-1. PSC0 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_0 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3_0 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3_0 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
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Table 8-1. PSC0 Default Module Configuration (continued)
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4
SPI0
AlwaysON (PD0)
SwRstDisable
—
5
MMC/SD0
AlwaysON (PD0)
SwRstDisable
—
6
ARM Interrupt Controller
AlwaysON (PD0)
Enable
—
7
ARM RAM/ROM
AlwaysON (PD0)
Enable
Yes
8
Not Used
—
—
—
9
UART0
AlwaysON (PD0)
SwRstDisable
—
10
SCR0 (BR0, BR1, BR2, BR8)
AlwaysON (PD0)
Enable
Yes
11
SCR1 (BR4)
AlwaysON (PD0)
Enable
Yes
12
SCR2 (BR3, BR5, BR6)
AlwaysON (PD0)
Enable
Yes
13
Not Used
—
—
—
14
ARM
AlwaysON (PD0)
SwRstDisable
—
15
Not Used
—
—
—
Table 8-2. PSC1 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_1 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
Not Used
—
—
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
Not Used
—
—
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
DDR2/mDDR
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 (+ McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8-9
Not Used
—
—
—
10
SPI1
AlwaysON (PD0)
SwRstDisable
—
11
Not Used
—
—
—
12
UART1
AlwaysON (PD0)
SwRstDisable
—
13
UART2
AlwaysON (PD0)
SwRstDisable
—
14-20
Not Used
—
—
—
21
EDMA3_1 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR F0
AlwaysON (PD0)
Enable
Yes
25
SCR F1
AlwaysON (PD0)
Enable
Yes
26
Not Used
—
—
—
27
SCR F6
AlwaysON (PD0)
Enable
Yes
28
SCR F7
AlwaysON (PD0)
Enable
Yes
29
SCR F8
AlwaysON (PD0)
Enable
Yes
30
Not Used
—
—
—
31
On-chip RAM
PD_SHRAM
Enable
—
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8.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In this device, for both PSC0 and PSC1, the Always ON domain (or PD0 power domain), is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state (See details on
PDCTL register).
Additionally, for both PSC0 and PSC1, the PD1 power domains, the internal/pseudo power domain can
either be in the ON state or OFF state. Furthermore, for these power domains the transition from ON to
OFF state is further qualified by the PSC0/1.PDCTL1.PDMODE settings. The PDCTL1.PDMODE settings
determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.
• On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128KB On-chip RAM
NOTE: Currently programming the PD1 power domain state to OFF is not supported. You should
leave both the PDCTL1.NEXT and PDCTL1.PDMODE values at default/power on reset
values.
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of
the device. There is no capability to individually remove voltage/power from the on-chip RAM
power domains.
8.2.2 Module States
The PSC defines several possible states for a module. This various states are essentially a combination of
the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The various
module states are defined in Table 8-3.
The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in
Auto Sleep mode, it will transition back to the clock disabled state (automatically sleep) after servicing the
internal read/write access request where as in Auto Wake mode, on receiving the first internal read/write
access request, the module will permanently transition from the clock disabled to clock enabled state
(automatically wake).
When the module state is programmed to Disable, SwRstDisable, Auto Sleep or Auto Wake modes,
where in the module clocks are off/disabled, an external event or I/O request cannot enable the clocks.
For the module to appropriately respond to such external request, it would need to be reconfigured to the
Enable state.
8.2.2.1
Auto Sleep/Wake Only Configurations and Limitation
NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes. If the
module clocks need to gated/disabled for power savings, you should program the module
state to Disable. For Auto Sleep/Auto Wake Only modules, disabling the clock is not
supported and they should be kept in their default “Enable” state.
Table 8-1 and Table 8-2 each have a column to indicate whether or not the LPSC configuration for a
module is Auto Sleep/Wake Only. Modules that have a “Yes” marked for the Auto Sleep/Wake Only
column can be programmed in software to be in Enable, Auto Sleep and Auto Wake states only; that is, if
the software tries to program these modules to Disable, SyncReset, or SwRstDisable state the power
sleep controller ignores these transition requests and transitions the module state to Enable.
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8.2.2.2
Local Reset
In addition to module reset, the following module can be reset using a special local reset that is also a part
of the PSC module control for resets.
• ARM: When the ARM local reset is asserted the entire ARM processor is reset , including cache etc.
This does not include the ARM RAM/ROM or ARM interrupt controller module as these exist outside
the ARM core. The local reset for ARM additionally ensures that any outstanding requests are
completed before ARM is reset, therefore for scenarios where it is needed to just reset the ARM locally
but not change the state of clocks, user can use ARM local reset feature.
The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the
module that supports local reset):
1. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset.
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset.
If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted.
Table 8-3. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has
its clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has
its module clock off. This state is typically used for disabling a module
clock to save power. This device is designed in full static CMOS, so when
you stop a module clock, it retains the module’s state. When the clock is
restarted, the module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it
has its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it
has its clock disabled. After initial power-on, several modules come up in
the SwRstDisable state. Generally, software is not expected to initiate this
state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it
can “automatically” transition to “Enable” state whenever there is an
internal read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re deasserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data. See Section 8.2.2.1 for
additional considerations, constraints, limitations around this mode.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from
then on (with module reset re de-asserted and module clock on), without
any software intervention. The transition from sleep to enabled state has
some cycle latency associated with it. It is not envisioned to use this mode
when peripherals are fully operational and moving data. See
Section 8.2.2.1 for additional considerations, constraints, limitations around
this mode.
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Executing State Transitions
This section describes how to execute the state transitions modules.
8.3.1 Power Domain State Transitions
This device consists of two types of domain (in each PSC controller):
• Always On domain(s)
• pseudo/RAM power domain(s)
The Always On power domains are always in the ON state when the chip is powered on. You are not
allowed to change the power domain state to OFF.
The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with
these domains (On-chip RAM for PD_SHRAM in PSC1) so that these RAMs can run in lower power sleep
modes via the power sleep controller.
NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported;
therefore, these domains and the RAM should be left in their default power on state.
As mentioned in Section 8.2, the pseudo/RAM power domains are powered down internally,
and in this context powering down does not imply removing the core voltage from pins
externally.
8.3.2 Module State Transitions
This section describes the procedure for transitioning the module state (clock and reset control). Note that
some peripherals have special programming requirements and additional recommended steps you must
take before you can invoke the PSC module state transition. See the individual peripheral user guides for
more details. For example, the external memory controller requires that you first place the SDRAM
memory in self-refresh mode before you invoke the PSC module state transitions, if you want to maintain
the memory contents.
The following procedure is directly applicable for all modules that are controlled via the PSC (shown in
Table 8-1 and Table 8-2), except for the core(s). To transition module state, there are additional system
considerations and constraints that you should be aware of. These system considerations and the
procedure for transitioning module state are described in details in the Power Management chapter.
NOTE: In the following procedure, x is 0 for modules in PD0 (Power Domain 0 or Always On
domain) and x is 1 for modules in PD1 (Power Domain 1). See Table 8-1 and Table 8-2 for
power domain associations.
The procedure for module state transitions is:
1. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), Enable (3h), Auto
Sleep (4h) or Auto Wake (5h).
NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[x] bit in PTCMD in a later step.
3. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
after the GOSTAT[x] bit in PTSTAT is cleared to 0.
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8.4
IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the
state of power domains and modules. This IcePick support only applies to the following module:
• ARM [MDCTL14]
In particular, Table 8-4 shows IcePick emulation commands recognized by the PSC.
Table 8-4. IcePick Emulation Commands
Power On and
Enable Features
Power On and Enable Descriptions
Reset Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the
module’s local reset.
Force Power
Allows emulation to force the power domain into
an on state. Not applicable as AlwaysOn power
domain is always on.
Wait Reset
Allows emulation to keep local
reset asserted for an extended
period of time after software
initiates local reset de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block
software initiated local and
module resets.
NOTE: When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in
MDCTLn, as set by software.
8.5
PSC Interrupts
The PSC has an interrupt that is tied to the core interrupt controller. This interrupt is named PSCINT in the
interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.
8.5.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Power Domain Emulation Event (applies to pseudo/RAM power domain only)
• Module State Emulation event
• Module Local Reset Emulation event
These interrupt events are summarized in Table 8-5 and described in more detail in this section.
Table 8-5. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Enable Bit
Interrupt Condition
PDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the power domain state
MDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the module state
MDCTLn
EMURSTIE
Interrupt occurs when the emulation tries to alter the module’s local reset
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the userprogrammed state in the NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the
modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed.
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Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTATn. In particular, a power
domain emulation event occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
• When force power is asserted by emulation and power domain is not already in the on state
• When force active is asserted by emulation and power domain is not already in the on state
8.5.1.2
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTATn). In particular, a module state emulation event
occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
• When force active is asserted by emulation and module is not already in the enable state
8.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTATn). In particular, a module local reset emulation
event occurs under the following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset
• When wait reset is asserted by emulation
• When block reset is asserted by emulation and software attempts to change the state of local reset
8.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support, as specified in
Section 8.4).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled appropriately in the ARM interrupt controller. For
details on the ARM interrupt controller, see the ARM Interrupt Controller (AINTC) chapter.
The PSC interrupt status bits are:
• For ARM:
– The M[14] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for ARM (MDSTAT14).
The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.
The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register. When set, this bit forces the
PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set)
when the ALLEV bit in the INTEVAL is set to 1, the PSC interrupt is re-asserted to the interrupt controller.
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do
not miss any PSC interrupts.
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See Section 8.6 for a description of the PSC registers.
8.5.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt:
1. Set the EMUIHBIE bit in PDCTLn, the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the
interrupt events that you want.
NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event
becomes active.
2. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. To
interrupt the CPU, PSCn_ALLINT must be enabled in the device interrupt controller. See the for more
information on interrupts.
The CPU enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the P[n] bit in PERRPR, and/or the M[n] bit in MERRPR0, the M[n] bit in MERRPR1, to
determine the source of the interrupt(s).
2. For each active event that you want to service:
(a) Read the event status bits in PDSTATn and MDSTATn, depending on the status bits read in the
previous step to determine the event that caused the interrupt.
(b) Service the interrupt as required by your application.
(c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status.
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt
controller, if there are still any active interrupt events.
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PSC Registers
Table 8-6 lists the memory-mapped registers for the PSC0 and Table 8-7 lists the memory-mapped
registers for the PSC1.
Table 8-6. Power and Sleep Controller 0 (PSC0) Registers
Address
Acronym
Register Description
01C1 0000h
REVID
Revision Identification Register
Section 8.6.1
Section
01C1 0018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01C1 0040h
MERRPR0
Module Error Pending Register 0 (module 0-15)
Section 8.6.3
01C1 0050h
MERRCR0
Module Error Clear Register 0 (module 0-15)
Section 8.6.5
01C1 0060h
PERRPR
Power Error Pending Register
Section 8.6.7
01C1 0068h
PERRCR
Power Error Clear Register
Section 8.6.8
01C1 0120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01C1 0128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01C1 0200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01C1 0204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01C1 0300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01C1 0304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01C1 0400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01C1 0404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01C1 0800h01C1 083Ch
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15)
Section 8.6.17
01C1 0A00h01C1 0A3Ch
MDCTL0MDCTL15
Module Control n Register (modules 0-15)
Section 8.6.18
Table 8-7. Power and Sleep Controller 1 (PSC1) Registers
144
Address
Acronym
Register Description
01E2 7000h
REVID
Revision Identification Register
Section 8.6.1
01E2 7018h
INTEVAL
Interrupt Evaluation Register
Section 8.6.2
01E2 7040h
MERRPR0
Module Error Pending Register 0 (module 0-31)
Section 8.6.4
01E2 7050h
MERRCR0
Module Error Clear Register 0 (module 0-31)
Section 8.6.6
01E2 7060h
PERRPR
Power Error Pending Register
Section 8.6.7
01E2 7068h
PERRCR
Power Error Clear Register
Section 8.6.8
01E2 7120h
PTCMD
Power Domain Transition Command Register
Section 8.6.9
01E2 7128h
PTSTAT
Power Domain Transition Status Register
Section 8.6.10
01E2 7200h
PDSTAT0
Power Domain 0 Status Register
Section 8.6.11
01E2 7204h
PDSTAT1
Power Domain 1 Status Register
Section 8.6.12
01E2 7300h
PDCTL0
Power Domain 0 Control Register
Section 8.6.13
01E2 7304h
PDCTL1
Power Domain 1 Control Register
Section 8.6.14
01E2 7400h
PDCFG0
Power Domain 0 Configuration Register
Section 8.6.15
01E2 7404h
PDCFG1
Power Domain 1 Configuration Register
Section 8.6.16
01E2 7800h01E2 787Ch
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31)
Section 8.6.17
01E2 7A00h01E2 7A7Ch
MDCTL0MDCTL31
Module Control n Register (modules 0-31)
Section 8.6.19
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8.6.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 8-1 and described in Table 8-8.
Figure 8-1. Revision Identification Register (REVID)
31
0
REV
R-4482 5A00h
LEGEND: R = Read only; -n = value after reset
Table 8-8. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4482 5A00h
Description
Peripheral revision ID.
8.6.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 8-2 and described in Table 8-9.
Figure 8-2. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 8-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt (PSCn_ALLINT).
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 8-3 and described in Table 810.
Figure 8-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31
16
Reserved
R-0
15
14
Rsvd
M[14]
13
Reserved
0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit
31-15
14
13-0
Field
Reserved
Value
0
M[14]
Reserved
Description
Reserved
Module interrupt status bit for module 14 (ARM).
0
Module 14 does not have an error condition.
1
Module 14 has an error condition. See the module status 14 register (MDSTAT14) for the error
condition.
0
Reserved
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 8-4.
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 8-5 and described in Table 8-11.
Figure 8-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31
16
Reserved
R-0
15
14
Rsvd
M[14]
13
Reserved
0
W-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
Reserved
0
Reserved. Write the default value when modifying this register.
14
M[14]
13-0
Reserved
Clears the interrupt status bit (M[14]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 14 register (MDSTAT14).
0
A write of 0 has no effect.
1
A write of 1 clears the M[14] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT14.
0
Reserved
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 8-6.
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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8.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 8-7 and described in Table 8-12.
Figure 8-7. Power Error Pending Register (PERRPR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
RAM/Pseudo (PD1) power domain interrupt status.
0
RAM/Pseudo power domain does not have an error condition.
1
RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0
Reserved
8.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 8-8 and described in Table 8-13.
Figure 8-8. Power Error Clear Register (PERRCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit
31-2
1
0
148
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0
A write of 0 has no effect.
1
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0
Reserved
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8.6.9 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 8-9 and described in Table 814.
Figure 8-9. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-14. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GO[1]
Description
Reserved
RAM/Pseudo (PD1) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
PDCTL.NEXT for this domain, and MDCTL.NEXT for all the modules residing on this domain). If any of
the NEXT fields are not matching the corresponding current state (PDSTAT.STATE, MDSTAT.STATE),
the PSC will transition those respective domain/modules to the new NEXT state.
GO[0]
Always ON (PD0) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching
the corresponding current state (MDSTAT.STATE), the PSC will transition those respective
domain/modules to the new NEXT state.
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8.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 8-10 and described in Table 815 .
Figure 8-10. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
150
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
RAM/Pseudo (PD1) power domain transition status.
0
No transition in progress.
1
RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
GOSTAT[0]
Always ON (PD0) power domain transition status.
0
No transition in progress.
1
Modules in Always ON power domain are transitioning. Always On power domain is transitioning.
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8.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 8-11 and described in Table 8-16.
Figure 8-11. Power Domain 0 Status Register (PDSTAT0)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Reserved
Emulation alters domain state.
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.12 Power Domain 1 Status Register (PDSTAT1)
The power domain 1 status register (PDSTAT1) is shown in Figure 8-12 and described in Table 8-17.
Figure 8-12. Power Domain 1 Status Register (PDSTAT1)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Emulation alters domain state.
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
152
Reserved
0
POR
7-5
Description
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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8.6.13 Power Domain 0 Control Register (PDCTL0)
The power domain 0 control register (PDCTL0) is shown in Figure 8-13 and described in Table 8-18.
Figure 8-13. Power Domain 0 Control Register (PDCTL0)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
Reserved
9
EMUIHBIE
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
0-Fh
Power down mode.
0-Eh
Reserved
Fh
11-10
Description
0
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
NEXT
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect
since internally this power domain always remains in the on state.
0
Power domain off.
1
Power domain on.
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8.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 8-14 and described in Table 8-19.
Figure 8-14. Power Domain 1 Control Register (PDCTL1)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
0-Fh
Core off, RAM array retention, RAM periphery off (deep sleep).
Reserved
4h
Core retention, RAM array off, RAM periphery off.
5h
Core retention, RAM array retention, RAM periphery off (deep sleep).
Reserved
8h
Core on, RAM array off, RAM periphery off.
9h
Core on, RAM array retention, RAM periphery off (deep sleep).
Ah
Core on, RAM array retention, RAM periphery off (light sleep).
Bh
Core on, RAM array retention, RAM periphery on.
Fh
EMUIHBIE
Power down mode.
Core off, RAM array off, RAM periphery off.
Ch-Eh
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
1h
6h-7h
9
Reserved
0
2h-3h
11-10
Description
0
Reserved
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
154
NEXT
User-desired power domain next state.
0
Power domain off.
1
Power domain on.
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8.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 8-15 and described in Table 820.
Figure 8-15. Power Domain 0 Configuration Register (PDCFG0)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.16 Power Domain 1 Configuration Register (PDCFG1)
The power domain 1 configuration register (PDCFG1) is shown in Figure 8-16 and described in Table 821.
Figure 8-16. Power Domain 1 Configuration Register (PDCFG1)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
156
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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8.6.17 Module Status n Register (MDSTATn)
The module status n register (MDSTATn) is shown in Figure 8-17 and described in Table 8-22.
Figure 8-17. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
Reserved
MCKOUT
Rsvd
MRST
LRSTDONE
LRST
Reserved
7
6
5
STATE
0
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-22. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in the module control
14 register (MDCTL14).
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL14. If you desire to
generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL14.
Emulation alters module reset. This bit applies to ARM module (module 14). This field is 0 for all
other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state. If you desire to generate a PSCINT upon this
event, you must set the EMURSTIE bit in the module control 14 register (MDCTL14).
0
Reserved
Module clock output status. Shows status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to ARM module (module 14). This field is 1 for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Reserved
0
LRSTDONE
7-6
Description
Emulation alters module state. This bit applies to ARM module (module 14). This field is 0 for all
other modules.
EMURST
15-13
9
Value
Module local reset status. This bit applies to ARM module (module 14).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
Module state status: indicates current module status.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
Indicates transition
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8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)
The PSC0 module control n register (MDCTLn) is shown in Figure 8-18 and described in Table 8-23.
Figure 8-18. PSC0 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
10
9
8
Reserved
11
EMUIHBIE
EMURSTIE
LRST
7
Reserved
3
2
NEXT
0
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-11
Reserved
10
EMUIHBIE
9
8
Force is disabled.
1
Force is enabled.
0
Reserved
Interrupt enable for emulation alters module state. This bit applies to ARM module (module 14).
0
Disable interrupt.
1
Enable interrupt.
EMURSTIE
Interrupt enable for emulation alters reset. This bit applies to ARM module (module 14).
0
Disable interrupt.
1
Enable interrupt.
LRST
7-3
Reserved
2-0
NEXT
158
0
Module local reset control. This bit applies to ARM module (module 14).
0
Assert local reset
1
De-assert local reset
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn)
The PSC1 module control n register (MDCTLn) is shown in Figure 8-19 and described in Table 8-24.
Figure 8-19. PSC1 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
3
2
0
Reserved
NEXT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-3
Reserved
2-0
NEXT
0
Force is disabled.
1
Force is enabled.
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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Chapter 9
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Power Management
Topic
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
160
...........................................................................................................................
Introduction .....................................................................................................
Power Consumption Overview ...........................................................................
PSC and PLLC Overview ...................................................................................
Features ..........................................................................................................
Clock Management ...........................................................................................
ARM Sleep Mode Management ...........................................................................
RTC-Only Mode ................................................................................................
Dynamic Voltage and Frequency Scaling (DVFS)..................................................
Deep Sleep Mode ..............................................................................................
Additional Peripheral Power Management Considerations.....................................
Power Management
Page
161
161
161
162
163
164
166
166
167
171
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9.1
Introduction
Power management is an important aspect for most embedded applications. For several applications and
target markets, there may be a specific power budget and requirements to minimize power consumption
for both power supply sizing and battery life considerations. Additionally, lower power consumption results
in more optimal and efficient designs from cost, design, and energy perspectives. This device has several
means of managing the power consumption. This chapter discusses the various power management
features.
9.2
Power Consumption Overview
Power consumed by semiconductor devices has two components: dynamic and static. This can be shown
as:
Ptotal = Pdynamic + Pstatic
The dynamic power is the power consumed to perform work when the device is in active modes (clocks
applied, busses, and I/O switching), that is, analog circuits changing states. The dynamic power is defined
by:
Pdynamic = Capacitance × Voltage2 × Frequency
From the above formula, the dynamic power scales with the clock frequency (device/module frequency for
core operations and switching frequency for I/O). Dynamic power can be reduced by controlling the clocks
in such a way as to either operate at a clock setting just high enough to complete the required operation in
the required timeline or to run at a clock setting until the work is complete and then drastically reduce the
clock frequency or cut off the clocks until additional work must be performed.
In the formula, the dynamic power varies with the voltage squared, so the voltage of operations has
significant impact on overall power consumption and, thus, on the battery life. Dynamic power can be
reduced by scaling the operating voltage, when the performance requirements are not that high and the
device can be operated at a corresponding lower frequency.
The capacitance is the capacitance of the switching nodes, or the load capacitances on the switching I/O
pins.
The static power, as the name suggests, is independent of the switching frequency of the logic. It can be
shown as:
Pstatic = f(leakage current)
It is essentially a function of the “leakage”, or the power consumed by the logic when it is not switching or
is not performing any work. Leakage current is dependent mostly on the manufacturing process used, the
size of the die, etc. Leakage current is unavoidable while power is applied and scales roughly with the
operating junction temperatures. Leakage power can only be avoided by removing power completely from
a device or subsystem. The static power consumption plays a significant role in the Standby Modes (when
the application is not running and in a dormant state) and plays an important role in the battery life for
portable applications, etc.
9.3
PSC and PLLC Overview
The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling
of the clocks to the core and various peripheral modules. The PSC provides a granular support to turn
on/off clocks on a module by module basis. Similarly, the two PLL controllers (PLLC0 and PLLC1) play an
important role in device and module clock generation, and manage the frequency scaling operations for
the device. Together these modules play a significant role in managing the clocks from a power
management feature standpoint. For detailed information on the PSC, see the Power and Sleep Controller
(PSC) chapter. For detailed information on the PLLC0 and PLLC1, see the Device Clocking chapter and
the Phase-Locked Loop Controller (PLLC) chapter.
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Features
9.4
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Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 9-1 describes the power management features.
Table 9-1. Power Management Features
Power Management
Description
Features
PLL bypass and powerdown
Both PLLs can be powered-down and run in
bypass mode when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON
Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic power consumption of the
core and I/O (if any free running I/O clocks).
ARM subsystem
sleep modes
The ARM CPU can be put in sleep mode.
Additionally, the ARM subsystem clock can be
completely gated when not in use.
Clock Management
Core Sleep Management
Reduces the dynamic power consumption.
Voltage Management
RTC-only mode
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Dynamic Voltage and Frequency Scaling
Dynamic Voltage and
Frequency Scaling
(DVFS)
The operating voltage and frequency of the device
can be dynamically scaled to meet the
requirements of the application.
Reduces the dynamic power consumption of the
core and I/O as well as standby power
System/Device Sleep Management
Deep Sleep Mode
All internal clocks of the device can be turned
on/off at the OSCIN level. The deep sleep function
can be controlled externally through the
DEESLEEP pin or internally through the
RTC_ALARM pin.
Reduces the dynamic power consumption of the
core and I/O.
USB PHY power-down
The USB2.0 PHY can be powered-down.
Minimizes the USB2.0 I/O power consumption
when not in use.
DDR2/mDDR selfrefresh mode
Allows memory to retain its contents while the rest
of the system is powered down.
mDDR and DDR2 can be clock gated to reduce the
dynamic power consumption or the entire device
can be powered down to reduce the static power
consumption.
LVCMOS I/O buffer
receiver disable
LVCMOS I/O buffer receivers are disabled.
Minimizes the I/O power consumption.
Internal pull-up and pulldown resistor control
The internal pull-ups and pull-downs are
enabled/disabled by groups.
Reduces the I/O leakage power.
Peripheral I/O Power Management
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9.5
Clock Management
9.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
NOTE: To preserve the state of the module, the module state in the PSC must be set to Disable. In
this state, the module reset is not asserted and only the module clock is turned off.
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module, when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
9.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
9.5.3 PLL Bypass and Power Down
You can bypass each PLL in this device. Bypassing the PLL sends a bypass clock instead of the PLL
VCO output (PLLOUT) to the system clocks of the PLLC. For PLLC0, the bypass clock is selected from
either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. For PLLC1, the bypass clock is always
OSCIN. The OSCIN frequency is typically, at most, up to 50 MHz.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. This can lower the
overall dynamic power consumption, which is linearly proportional to the frequency.
When the PLL controller is placed in bypass mode, the PLL retains its frequency lock. This allows you to
switch between bypass mode and PLL mode without having to wait for the PLL to relock. However,
keeping the PLL locked consumes power. You can also power-down the PLL when bypassing it to
minimize the overall power consumed by the PLL module. The advantage of bypassing the PLL without
powering it down is that you do not have to incur the PLL lock time when switching back to a normal
operating level.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
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9.6
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ARM Sleep Mode Management
9.6.1 ARM Wait-For-Interrupt Sleep Mode
The ARM module can be put into a low-power state using a special sleep mode called wait-for-interrupt
(WFI). When the wait-for-interrupt mode is enabled, all internal clocks within the ARM9 module are shut
off, the core is completely inactive and only resumes operation after receiving an interrupt. This is a
feature for dynamic power management of the ARM processor itself, it does not impact the static power.
NOTE: To enable the WFI mode, the ARM needs to be in supervisor mode.
You can enable the WFI mode via the CP15 register #7 using the following instruction:
• MCR p15, #0, <Rd>, c7, c0, #4
Once the ARM module transitions into the WFI mode, it will remain in this state until an interrupt request
(IRQ/FIQ) occurs.
The following sequence exemplifies how to enter the WFI mode:
• Enable any interrupt (for example, an external interrupt) that you plan to use as the wake-up interrupt
to exit from the WFI mode.
• Enable the WFI mode using the following CP15 instruction:
– MCR p15, #0, r3, c7, c0, #4
The following sequence describes the procedure to wake-up from the WFI mode:
• To wake-up from the WFI mode, trigger any enabled interrupt (for example, an external interrupt).
• The ARM’s PC jumps to the IRQ/FIQ vector and you must handle the interrupt in an interrupt service
routine (ISR).
Exit the ISR and continue normal program execution starting from the instruction immediately following the
instruction that enabled the WFI mode.
NOTE: The ARM interrupt controller (AINTC) and the module sourcing the wake-up interrupt (for
example, GPIO or watchdog timer) must not be disabled, or the device will never wake up.
For more information on this sleep mode, see the ARM926EJ-S Technical Reference Manual
(TRM), downloadable from http://infocenter.arm.com/help/index.jsp.
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9.6.2 ARM Clock OFF
The software must be structured such that no peripheral is allowed to access the ARM resources before
disabling the clocks to the ARM subsystem. The ARM must check for the completion of all its master
peripheral initiated requests (that is, CFG and DMA port operations, etc.).
ARM module clock off sequence:
1. The ARM must have the ARM Clock Stop Request interrupt (ARMCLKSTOPREQ, ARM interrupt # 90)
enabled and the associated interrupt service routine (ISR) set up before the following ARM clock
shutdown procedure.
(a) Initiate the ARM clock off sequence by issuing the ARM clock stop command (PSC DISABLE
Command) to the ARM subsystem by writing a 2h to the NEXT bit field in the ARM local power
sleep controller (LPSC) module control register (PSC0.MDCTL14).
(b) Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power
domain transition command register (PSC0.PTCMD) to start the state transition sequence for the
ARM module. This generates the ARMCLKSTOPREQ interrupt to the ARM.
(c) Check (poll for 0) the GOSTAT[0] bit in the power domain transition status register (PSC0.PTSTAT)
for power transition sequence completion. The GOSTAT[0] bit transitions to 0 when the ARM
executes the wait-for-interrupt instruction from inside its interrupt service routine (ISR).
(d) Check (poll for 2h) the STATE bit field in the ARM LPSC module status register
(PSC0.MDSTAT14) indicating the ARM clock stop sequence completion (STATE: Disable).
The following sequence should be executed by the ARM within the ARM Clock Stop Request interrupt
ISR:
1. Check for completion of all ARM master requests (the ARM polls transfer completion statuses of all
Master peripherals).
2. Enable the interrupt to be used as the “wake-up” interrupt (for example, one of the CHIPSIG interrupts
controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module
chapter—CHIPSIG[0], CHIPSIG[1], etc.) that will be used to wake-up the ARM during the ARM clockon sequence.
3. Execute the wait-for-interrupt (WFI) ARM instruction.
9.6.3 ARM Subsystem Clock ON
The ARM module defaults to the SwRstDisable state; therefore, the software is responsible for enabling
the clock and releasing the reset to the ARM at power-on reset.
1. Wait for the GOSTAT[0] bit in the power domain transition status register (PSC0.PTSTAT) to clear to
0. You must wait for the power domain to finish any previously initiated transitions before initiating a
new transition.
2. Write a 3h to the NEXT bit in the ARM local power sleep controller (LPSC) module control register
(PSC0.MDCTL14) to prepare the ARM module for an enable transition.
3. Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power
domain transition command register (PSC0.PTCMD) to start the state transition sequence for the ARM
module.
4. Check (poll for 0) the GOSTAT[0] bit in PSC0.PTSTAT for power transition sequence completion. The
domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0.
5. Wait for the STATE bit field in the ARM LPSC module status register (PSC0.MDSTAT14) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
NOTE: This only applies if you are transitioning from the Disable state. If previously in the Disable
state, a wake-up interrupt must be triggered in order to wake the ARM (to exit the wait-forinterrupt mode). This example assumes that the ARM enabled this interrupt before entering
its wait-for-interrupt sleep mode state.
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RTC-Only Mode
In real-time clock (RTC)-only mode, the RTC is powered on and the rest of the device is completely
powered off (all supplies except the RTC supply are removed). In this mode, the RTC is fully functional
and keeps track of date, hours, minutes, and seconds. In this mode, the overall power consumption would
be significantly lower, as voltage from the rest of the core and I/O logic can be completely removed,
eliminating most of the active and static power of the device, except for what is consumed by the RTC
module, running at 32 kHz.
NOTE: To put the device in RTC-only mode, there is no software control sequence. You can put the
device in the RTC-only mode by removing the power supply from all core and I/O logic,
except for the RTC core logic supply (RTC_CVDD). During wake up, all power sequencing
requirements described in the device-specific data manual must be followed.
Some limitations apply in the RTC-only mode. First, the RTC_ALARM pin is not available as an option for
use as a control to signal an external power supply to reapply power to the rest of the device. This is
because the RTC_ALARM pin is powered by the I/O supply that is powered down in RTC-only mode.
Second, in RTC-only mode, only the RTC register contents are preserved, all other internal memory and
register contents are lost. Mobile DDR and DDR2 contents can be preserved through the use of selfrefresh (see Section 9.9.2). However, software must be in place to restore the context of the device, for
example, reinitialize internal registers, setup cache memory configurations, interrupt vectors, etc.
9.8
Dynamic Voltage and Frequency Scaling (DVFS)
Dynamic voltage and frequency scaling (DVFS) consists of minimizing the idle time of the system. The
DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a task to be
performed in the required amount of time. This reduces the total power consumption of the device while
still meeting task requirements. DVFS requires control over the clock frequency and the operating voltage
of the device elements. By intelligently switching these elements to their optimal operating points, it is
possible to minimize the power consumption of the device for a given task.
For reasons related to the device (clock architecture, process, etc.), DVFS is used only for a few discrete
steps, not over a continuum of voltage and frequency values. Each step, or operating performance point
(OPP), is composed of a voltage and frequency pair. For an OPP, the frequency corresponds to the
maximum frequency allowed at a voltage, or reciprocally; the voltage corresponds to the minimum voltage
allowed for a frequency. See your device data manual for a list of the OPPs supported by the device.
When applying DVFS, a processor or system always runs at the lowest OPP that meets the performance
requirement at a given time. You determine the optimal OPP for a given task and then switch to that OPP
to save power.
9.8.1 Frequency Scaling Considerations
The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1).
Through a series of multipliers and dividers you can change the frequencies of various clocks throughout
the device. See the Device Clocking chapter for information on the clock architecture of the device and
see the Phase-Locked Loop Controller (PLLC) chapter for information on the PLL controllers. A few things
must be noted when changing the various internal frequencies of the device:
• Changing the SYSCLK frequency
The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier. A series of dividers
divide PLLOUT to generate the various device SYSCLKs.
To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK
divider ratio. When changing the PLL multiplier, you must put the PLL controller in bypass mode while
the PLL multiplier value is modified and a lock on the new frequency is reached. The lock time is given
in the device data manual. When changing the divider ratios it is not required to put the PLL controller
in bypass mode.
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the
PLL. However, the SYSCLK frequency will depend solely on the divider ratios used.
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•
•
•
SYSCLK domain fixed ratios
Certain SYSCLK domains need to operate at a fixed ratio with respect to the ARM clock. Care should
be taken to ensure that these fixed ratios are maintained. For additional details, see the Device
Clocking chapter.
PLLC0 bypass clock
When switching the PLL multiplier, the PLL controller must be placed in bypass mode. Bypassing the
PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of
the PLL controller.
For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or
PLL1_SYSCLK3. For PLLC1, the bypass clock is always OSCIN. The OSCIN frequency is typically, at
most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity.
It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved
bandwidth during frequency scaling transitions. For this reason, the PLLC0 bypass clock can be set to
PLL1_SYSCLK3. This selection is made through the EXTCLKSRC bit in the PLLCTL register of
PLLC0.
Peripheral immunity from ARM clock frequency changes
Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency.
The PLL0_AUXCLK is derived from OSCIN.
Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2.
Furthermore, PLL0_SYSCLK2 must always be /2 of the ARM clock frequency. To keep these
peripherals immune from changes in PLL0 frequency (such as when the ARM frequency is modified),
you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. PLL1 is mainly used to
clock the DDR2/mDDR memory controller.
When peripherals are immune to changes in the ARM clock frequency, their internal clock dividers do
not have to be adjusted for changes in their input clock frequencies.
9.8.2 Voltage Scaling Considerations
The operating voltage of the device must be totally controlled through mechanisms outside the device. I2C
ports on the device can be used to communicate with external power management chips. A few things
must be noted when changing the operating voltage of the device:
• Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating
performance point (OPP) transitions. See the device data manual for ramp rate specifications.
• Switching to a lower voltage: When switching to a lower voltage, the maximum operating frequency
changes. Care must be taken such that the maximum operating frequency supported at the new
voltage is not violated. For this reason, it is recommended to change the operating frequency before
switching the operating voltage.
9.9
Deep Sleep Mode
This device supports a Deep Sleep mode where all device clocks are stopped and the on-chip oscillator is
shut down to save power. Registers and memory contents are preserved, thus, upon recovery, the
program may continue from where it left off with minimal overhead involved.
The Deep Sleep mode is initiated when the DEEPSLEEP pin is driven low. The device wakes up from
Deep Sleep mode when the DEEPSLEEP pin is driven high. The DEEPSLEEP pin can be driven by an
external controller or it can be driven internally by the real-time clock (RTC). The RTC method allows for
automatic wake-up at a programmed time.
NOTE: Due to pin multiplexing, the DEEPSLEEP pin can only be driven by an external controller or
its internal real-time clock (RTC). The DEEPSLEEP pin cannot be driven by both an external
controller and its internal real-time clock at the same time.
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9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
9.9.1.1
Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep mode if an external signal is used to wake-up the
device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 9.10.1).
3. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
4. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
5. Configure the DEEPSLEEP pin as input-only using the PINMUX0_31_28 bits in the PINMUX0 register
in the System Configuration (SYSCFG) Module chapter.
6. The external controller should drive the DEEPSLEEP pin high (not in Deep Sleep).
7. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
9. Begin polling the SLEEPCOMPLETE bit until it is set to 1. This bit is set once the device is woken up
from Deep Sleep mode.
10. The external controller drives the DEEPSLEEP pin low to initiate Deep Sleep mode.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.1.2
Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if an external signal is used to wake-up the
device:
1. The external controller drives the DEEPSLEEP pin high.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 7.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
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9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
9.9.2.1
Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep state if the RTC is used to wake-up the device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 9.10.1).
3. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
4. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
5. Configure the desired wake-up time as an alarm in the RTC.
6. Configure the DEEPSLEEP/RTC_ALARM pin to output RTC_ALARM using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. The pin is driven low
since the alarm has not yet occurred.
7. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
Also, the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.9.2.2
Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if the RTC is used to wake-up the device:
1. The RTC alarm occurs and the RTC_ALARM pin is driven high (which is internally connected to the
DEEPSLEEP pin). This causes the Deep Sleep logic to exit the Deep Sleep mode.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 7.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
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9.9.3 Deep Sleep Sequence
Figure 9-1 illustrates the Deep Sleep sequence:
1. Software sets the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System
Configuration (SYSCFG) Module chapter.
2. The DEEPSLEEP pin is driven low by either an external device or the RTC_ALARM pin. The Deep
Sleep mode begins.
3. The PLL controller reference clock is gated.
4. The on-chip oscillator is disabled. If the device is being clocked by an external source, this clock may
stay enabled; the power savings from turning off this clock is minimal.
5. The DEEPSLEEP pin is driven high and the on-chip oscillator is enabled.
6. The Deep Sleep counter beings counting valid clock cycles.
7. The count has reached the number specified in the SLEEPCOUNT bit field and the
SLEEPCOMPLETE bit is set. The PLL reference clock is enabled and the Deep Sleep mode ends.
8. Software clears the SLEEPENABLE bit. The SLEEPCOMPLETE bit is automatically cleared.
Figure 9-1. Deep Sleep Mode Sequence
See Note:
1
2
3
4
5
6
7
8
SLEEPENABLE
(internal)
DEEPSLEEP
CLKGATE
(internal)
PLLC Ref Clk
(internal)
OSC_GZ
(internal)
OSCIN
SLEEPCOMPLETE
(internal)
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9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking
Entering the Deep Sleep mode stops all of the clocks to the device so it is the responsibility of the
software to ensure that all peripheral accesses have been completed and peripheral interfaces
appropriately configured for clocks to stop. Therefore, before an external controller drives the
DEESPLEEP pin, a handshaking mechanism must be in place to give software time to prepare the device
for Deep Sleep mode. The implementation of the handshake mechanism is up to the system designer.
9.9.4.1
Entering Deep Sleep Mode
The following example sequence can be used to activate the Deep Sleep mode using a handshaking
mechanism between your device and an external device:
1. Clear the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter to 0. The DEEPSLEEP pin has no effect until software running on the
device sets this bit.
2. Configure the GP0[8]/DEEPSLEEP/RTC_ALARM pin to output GP0[8] using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. When the pin is
configured for GPIO functionality, the internal DEEPSLEEP signal is still driven by the value on the pin.
3. Configure the GP0[8] pin to generate interrupts on the falling edge of the GPIO signal.
4. An external device drives the GP0[8] pin low.
5. Software prepares the device for Deep Sleep mode.
6. Set the SLEEPENABLE bit in DEEPSLEEP to 1. The Deep Sleep mode is immediately started and all
device clocks are stopped. Also, the SLEEPCOMPLETE bit is automatically cleared.
9.9.4.2
Exiting Deep Sleep Mode
To exit the Deep Sleep mode, follow this sequence:
1. An external device drives the GP0[8] pin high.
2. The device exits the Deep Sleep mode. When the SLEEPCOUNT delay is complete, the Deep Sleep
logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register
(DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.
9.10 Additional Peripheral Power Management Considerations
This section lists additional power management features and considerations that might be part of other
chip-level or peripheral logic, apart from the features supported by the core, PLL controller (PLLC), and
power and sleep controller (PSC).
9.10.1 USB PHY Power Down Control
The USB modules can be clock gated using the PSC; however, this does not power down/clock gate the
PHY logic. You can put the USB2.0 PHY and OTG module in the lowest power state, when not in use, by
writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the Chip Configuration 2 Register
(CFGCHIP2) in the System Configuration (SYSCFG) Module chapter.
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9.10.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode
The DDR2/mDDR memory controller supports different methods for reducing its power consumption
including self-refresh mode, power-down mode, and clock gating. Additionally, the DDR2/mDDR memory
controller DLL, PHY, and the receivers at the I/O pins can be disabled. Even if the PHY is active, the
receivers can be configured to disable whenever writes are in progress and the receivers are not needed.
Self-refresh mode can be used to preserve the contents of DDR2/mDDR memory when the DDR2/mDDR
memory controller is clock gated or when the device is placed in RTC-only mode. However, in the RTConly mode, care must be taken to correctly take the DDR2/mDDR out of self-refresh mode.
NOTE: To preserve the contents of the external memory while the DDR2/mDDR memory controller
is clock gated, its self-refresh mode must be enabled before the DDR2/mDDR memory
controller clock is turned off.
In RTC-only mode, all portions of the device except for the RTC are powered down, including the
DDR2/mDDR memory controller. During power-up, the DDR2/mDDR memory controller defaults to its
reset state. When the DDR2/mDDR memory controller is taken out of reset, it automatically runs its
memory initialization routine; the self-refresh state of the memory is ignored. This hardware sequence
cannot be stopped by software running on the device.
To correctly take the memory out of self-refresh after coming back from RTC-only mode, follow these
steps:
1. Before going into RTC-only mode, disconnect the DDR2/mDDR memory controller CKE output pin
from the memory; ensure the memory’s CKE input pin continues to be driven low.
2. After coming back from RTC-only mode, configure the device to the desired operating state.
3. Program the DDR2/mDDR memory controller following the normal sequence.
4. Enable the self-refresh mode of the DDR2/mDDR memory controller.
5. Connect the DDR2/mDDR memory controller CKE output pin to the memory.
6. Disable the self-refresh mode of the DDR2/mDDR memory controller.
After this sequence, the DDR2/mDDR memory controller is ready for use. Note that hardware logic is
needed to disconnect the CKE output pin from the memory and to drive the memory’s CKE input pin low.
For more details on the power management features of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
9.10.3 LVCMOS I/O Buffer Receiver Disable
This device supports two types of LVCMOS I/Os: 1.8V I/Os and low-static current dual-voltage I/Os that
operate at either 1.8V or 3.3V. The receivers on the LCVMOS I/Os are enabled and disabled by software
(see the RXACTIVE Control Register (RXACTIVE) in the System Configuration (SYSCFG) Module
chapter). In the event that certain receivers are not used (such as in a low-power state), they can be
disabled to conserve power.
9.10.4 Pull-Up/Pull-Down Disable
In general, you must ensure that all input pins are always pulled to a logic-high or a logic-low voltage level.
A floating input pin can consume a small amount of I/O leakage current. The I/O leakage current can be
greatly multiplied in the case of several floating inputs pins.
This device includes internal pull-up and pull-down resistors that prevent floating input pins. These internal
resistors are generally very weak and their use is intended for pins that are not connected on the board
design. For pins that are connected, external pull-up and pull-down resistors are recommended.
When an input pin is externally driven to a valid logic level, through an external pull-up resistor or by an
external device for example, it is recommended to disable the internal resistor. Opposing an internal pullup or pull-down resistor can consume a small amount of current. Internal resistors are disabled through
the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module chapter.
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System Configuration (SYSCFG) Module
Topic
10.1
10.2
10.3
10.4
10.5
...........................................................................................................................
Introduction .....................................................................................................
Protection ........................................................................................................
Master Priority Control ......................................................................................
Interrupt Support ..............................................................................................
SYSCFG Registers ............................................................................................
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10.1 Introduction
The system configuration (SYSCFG) module is a system-level module containing status and top level
control logic required by the device. The system configuration module consists of a set of memorymapped status and control registers, accessible by the CPU, supporting all of the following system
features, and miscellaneous functions and operations.
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device Boot Configuration Status
• Master Priority Control
– Controls the system priority for all master peripherals (including EDMA3TC)
• Emulation Control
– Emulation suspend control for peripherals that support the feature
• Special Peripheral Status and Control
– Locking of PLL control settings
– Default burst size configuration for EDMA3 transfer controllers
– McASP0 AMUTEIN selection and clearing of AMUTE
– USB PHY Control
– Clock source selection for EMIFA and DDR2/mDDR
The system configuration module controls several global operations of the device; therefore, the module
supports protection against erroneous and illegal accesses to the registers in its memory-map. The
protection mechanisms that are present in the module are:
• A special key sequence that needs to be written into a set of registers in the system configuration
module, to allow write ability to the rest of registers in the system configuration module.
• Several registers in the module are only accessible when the CPU requesting read/write access is in
privileged mode.
10.2 Protection
The SYSCFG module controls several global operations of the device; therefore, it has a protection
mechanism that prevents spurious and illegal accesses to the registers in its memory map. The protection
mechanism enables accesses to these registers only if certain conditions are met.
10.2.1 Privilege Mode Protection
The CPU supports two privilege levels: Supervisor and User. Several registers in the SYSCFG memorymap can only be accessed when the accessing host (CPU or master peripheral) is operating in privileged
mode, that is, in Supervisor mode. The registers that can only be accessed in privileged mode are listed in
Section 10.5. See the ARM926EJ-S Technical Reference Manual (TRM), downloadable from
http://infocenter.arm.com/help/index.jsp for details on privilege levels.
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10.2.2 Kicker Mechanism Protection
NOTE: The kick registers are disabled in this device. The SYSCFG registers are always unlocked
and writes to the kick registers have no functional effect.
To access any registers in the SYSCFG module, it is required to follow a special sequence of writes to the
Kick registers (KICK0R and KICK1R) with correct key values. Writing the correct key value to the kick
registers unlocks the registers in the SYSCFG memory-map. In order to access the SYSCFG registers,
the following unlock sequence needs to be executed in software:
1. Write the key value of 83E7 0B13h to KICK0R.
2. Write the key value of 95A4 F1E0h to KICK1R.
After steps 1 and 2, the SYSCFG module registers are accessible and can be configured as per the
application requirements.
10.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the ARM, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or EDMA3 for
initiating the data transfer to/from them. In order to determine allowed connection between masters and
slave, each master request source must have a unique master ID (mstid) associated with it. The master ID
is shown in Table 10-1. See the device-specific data manual to determine the masters present on your
device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 10-2. Application software is expected to modify these values
to obtain the desired performance.
Table 10-1. Master IDs
Master ID
Peripheral
0
ARM - Instruction
1
ARM - Data
2-9
Reserved
10
EDMA3_0_CC0
11
EDMA3_1_CC0
12-15
Reserved
16
EDMA3_0_TC0 - read
17
EDMA3_0_TC0 - write
18
EDMA3_0_TC1 - read
19
EDMA3_0_TC1 - write
20
EDMA3_1_TC0 – read
21
EDMA3_1_TC0 – write
22-33
Reserved
34
USB2.0 CFG
35
USB2.0 DMA
36
Reserved
36-37
Reserved
38
39-255
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Table 10-2. Default Master Priority
Default Priority (1)
Master Priority Register
(2)
0
MSTPRI1
EDMA3_0_TC1 (2)
0
MSTPRI1
ARM - Instruction
2
MSTPRI0
ARM - Data
2
MSTPRI0
EDMA3_1_TC0 (2)
4
MSTPRI1
Master
EDMA3_0_TC0
(1)
(2)
EMAC
4
MSTPRI2
USB2.0 CFG
4
MSTPRI2
USB2.0 DMA
4
MSTPRI2
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
The priority for EDMA3_0_TC0, EDMA3_0_TC1, and EDMA3_1_TC0 is configurable through fields in the master priority 1
register (MSTPRI1), not the EDMA3CC QUEPRI register.
10.4 Interrupt Support
10.4.1 Interrupt Events and Requests
The SYSCFG module generates two interrupts: an address error interrupt (BOOTCFG_ADDR_ERR) and
a protection interrupt (BOOTCFG_PROT_ERR). The BOOTCFG_ADDR_ERR is generated when there is
an addressing violation due to an access to a non-existent location in the SYSCFG register space. The
BOOTCFG_PROT_ERR interrupt is generated when there is a protection violation of either in the defined
ranges or to the SYSCFG registers. It is required to write a value of 0 to the end of interrupt register (EOI)
after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of completion
of the SYSCFG interrupt so that the module can reliably generate subsequent interrupts.
The transfer parameters that caused the violation are saved in the fault address register (FLTADDRR) and
the fault status register (FLTSTAT).
10.4.2 Interrupt Multiplexing
The interrupts from the SYSCFG module are combined with the interrupts from the MPU module into a
single interrupt called MPU_BOOTCFG_ERR. The combined interrupt is routed to the ARM interrupt
controller.
10.5 SYSCFG Registers
Table 10-3 lists the memory-mapped registers for the system configuration module 0 (SYSCFG0) and
Table 10-4 lists the memory-mapped registers for the system configuration module 1 (SYSCFG1). These
tables also indicate whether a particular register can be accessed only when the CPU is in privileged
mode.
Table 10-3. System Configuration Module 0 (SYSCFG0) Registers
Address
Acronym
Register Description
Access
01C1 4000h
REVID
Revision Identification Register
—
Section 10.5.1
01C1 4008h
DIEIDR0 (1)
Die Identification Register 0
—
—
01C1 400Ch
DIEIDR1 (1)
Die Identification Register 1
—
—
01C1 4010h
DIEIDR2 (1)
Die Identification Register 2
—
—
01C1 4014h
DIEIDR3
(1)
Die Identification Register 3
—
01C1 4018h
DEVIDR0
Device Identification Register 0
Privileged mode
(1)
Section
—
Section 10.5.2
This register is for internal-use only.
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Table 10-3. System Configuration Module 0 (SYSCFG0) Registers (continued)
Address
Acronym
Register Description
Access
01C1 4020h
BOOTCFG
Boot Configuration Register
Privileged mode
01C1 4024h
CHIPREVIDR
Chip Revision Identification Register
Privileged mode
Section 10.5.4
01C1 4038h
KICK0R
Kick 0 Register
Privileged mode
Section 10.5.5.1
01C1 403Ch
KICK1R
Kick 1 Register
Privileged mode
Section 10.5.5.2
01C1 4040h
HOST0CFG
Host 0 Configuration Register
—
01C1 40E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
Section 10.5.7.1
01C1 40E4h
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
Section 10.5.7.2
01C1 40E8h
IENSET
Interrupt Enable Register
Privileged mode
Section 10.5.7.3
01C1 40ECh
IENCLR
Interrupt Enable Clear Register
Privileged mode
Section 10.5.7.4
01C1 40F0h
EOI
End of Interrupt Register
Privileged mode
Section 10.5.7.5
01C1 40F4h
FLTADDRR
Fault Address Register
Privileged mode
Section 10.5.8.1
01C1 40F8h
FLTSTAT
Fault Status Register
—
Section 10.5.8.2
01C1 4110h
MSTPRI0
Master Priority 0 Register
Privileged mode
Section 10.5.9.1
01C1 4114h
MSTPRI1
Master Priority 1 Register
Privileged mode
Section 10.5.9.2
01C1 4118h
MSTPRI2
Master Priority 2 Register
Privileged mode
Section 10.5.9.3
01C1 4120h
PINMUX0
Pin Multiplexing Control 0 Register
Privileged mode
Section 10.5.10.1
01C1 4124h
PINMUX1
Pin Multiplexing Control 1 Register
Privileged mode
Section 10.5.10.2
01C1 4128h
PINMUX2
Pin Multiplexing Control 2 Register
Privileged mode
Section 10.5.10.3
01C1 412Ch
PINMUX3
Pin Multiplexing Control 3 Register
Privileged mode
Section 10.5.10.4
01C1 4130h
PINMUX4
Pin Multiplexing Control 4 Register
Privileged mode
Section 10.5.10.5
01C1 4134h
PINMUX5
Pin Multiplexing Control 5 Register
Privileged mode
Section 10.5.10.6
01C1 4138h
PINMUX6
Pin Multiplexing Control 6 Register
Privileged mode
Section 10.5.10.7
01C1 413Ch
PINMUX7
Pin Multiplexing Control 7 Register
Privileged mode
Section 10.5.10.8
01C1 4140h
PINMUX8
Pin Multiplexing Control 8 Register
Privileged mode
Section 10.5.10.9
01C1 4144h
PINMUX9
Pin Multiplexing Control 9 Register
Privileged mode
Section 10.5.10.10
01C1 4148h
PINMUX10
Pin Multiplexing Control 10 Register
Privileged mode
Section 10.5.10.11
01C1 414Ch
PINMUX11
Pin Multiplexing Control 11 Register
Privileged mode
Section 10.5.10.12
01C1 4150h
PINMUX12
Pin Multiplexing Control 12 Register
Privileged mode
Section 10.5.10.13
01C1 4154h
PINMUX13
Pin Multiplexing Control 13 Register
Privileged mode
Section 10.5.10.14
01C1 4158h
PINMUX14
Pin Multiplexing Control 14 Register
Privileged mode
Section 10.5.10.15
01C1 415Ch
PINMUX15
Pin Multiplexing Control 15 Register
Privileged mode
Section 10.5.10.16
01C1 4160h
PINMUX16
Pin Multiplexing Control 16 Register
Privileged mode
Section 10.5.10.17
01C1 4164h
PINMUX17
Pin Multiplexing Control 17 Register
Privileged mode
Section 10.5.10.18
01C1 4168h
PINMUX18
Pin Multiplexing Control 18 Register
Privileged mode
Section 10.5.10.19
01C1 416Ch
PINMUX19
Pin Multiplexing Control 19 Register
Privileged mode
Section 10.5.10.20
01C1 4170h
SUSPSRC
Suspend Source Register
Privileged mode
Section 10.5.11
01C1 4174h
CHIPSIG
Chip Signal Register
—
Section 10.5.12
01C1 4178h
CHIPSIG_CLR
Chip Signal Clear Register
—
Section 10.5.13
01C1 417Ch
CFGCHIP0
Chip Configuration 0 Register
Privileged mode
Section 10.5.14
01C1 4180h
CFGCHIP1
Chip Configuration 1 Register
Privileged mode
Section 10.5.15
01C1 4184h
CFGCHIP2
Chip Configuration 2 Register
Privileged mode
Section 10.5.16
01C1 4188h
CFGCHIP3
Chip Configuration 3 Register
Privileged mode
Section 10.5.17
01C1 418Ch
CFGCHIP4
Chip Configuration 4 Register
Privileged mode
Section 10.5.18
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Section 10.5.6
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Table 10-4. System Configuration Module 1 (SYSCFG1) Registers
Address
Acronym
Register Description
Access
01E2 C000h
VTPIO_CTL
VTP I/O Control Register
Privileged mode
Section 10.5.19
Section
01E2 C004h
DDR_SLEW
DDR Slew Register
Privileged mode
Section 10.5.20
01E2 C008h
DEEPSLEEP
Deep Sleep Register
Privileged mode
Section 10.5.21
01E2 C00Ch
PUPD_ENA
Pullup/Pulldown Enable Register
Privileged mode
Section 10.5.22
01E2 C010h
PUPD_SEL
Pullup/Pulldown Selection Register
Privileged mode
Section 10.5.23
01E2 C014h
RXACTIVE
RXACTIVE Control Register
Privileged mode
Section 10.5.24
10.5.1 Revision Identification Register (REVID)
The revision identification register (REVID) provides the revision information for the SYSCFG module. The
REVID is shown in Figure 10-1 and described in Table 10-5.
Figure 10-1. Revision Identification Register (REVID)
31
0
REV
R-4E84 0102h
LEGEND: R = Read only; -n = value after reset
Table 10-5. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E84 0102h
Description
Revision ID. Revision information for the SYSCFG module.
10.5.2 Device Identification Register 0 (DEVIDR0)
The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID
device. Software can use this register to determine the version of the device on which it is executing. The
DEVIDR0 is shown in Figure 10-2 and described in Table 10-6.
Figure 10-2. Device Identification Register 0 (DEVIDR0)
31
0
DEVID0
R-1B7D 102Fh
LEGEND: R = Read only; -n = value after reset
Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions
Bit
31-0
178
Field
DEVID0
Value
1B7D 102Fh
Description
Device identification.
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10.5.3 Boot Configuration Register (BOOTCFG)
The device boot and configuration settings are latched at device reset, and captured in the boot
configuration register (BOOTCFG). See your device-specific data manual and the Boot Considerations
chapter for details on boot and configuration settings. The BOOTCFG is shown in Figure 10-3 and
described in Table 10-7.
Figure 10-3. Boot Configuration Register (BOOTCFG)
31
16
Reserved
R-0
15
0
BOOTMODE
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-7. Boot Configuration Register (BOOTCFG) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
BOOTMODE
0
Description
Reserved
0-FFFFh
Boot Mode. This reflects the state of the boot mode pins.
10.5.4 Chip Revision Identification Register (CHIPREVIDR)
The chip revision identification register (CHIPREVIDR) provides the software-readable silicon revision
information for the device. The CHIPREVID is shown in Figure 10-4 and described in Table 10-8.
Figure 10-4. Chip Revision Identification Register (CHIPREVIDR)
31
16
Reserved
R-x
15
6
5
0
Reserved
CHIPREVID
R-x
R-4h
LEGEND: R = Read only; -n = value after reset; x = value is indeterminate after reset
Table 10-8. Chip Revision Identification Register (CHIPREVIDR) Field Descriptions
Bit
Field
31-6
Reserved
5-0
CHIPREVID
Value
0
Description
Reserved
Identifies silicon revision of device.
0-3h
4h
Older silicon revision
Silicon revision 2.2
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10.5.5 Kick Registers (KICK0R-KICK1R)
NOTE: The kick registers are disabled in this device. The SYSCFG registers are always unlocked
and writes to the kick registers have no functional effect.
The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of
the modules memory-mapped registers. At power-on reset, none of the SYSCFG module registers are
writeable (they are readable). To allow writing to the registers in the module, it is required to “unlock” the
registers by writing to two memory-mapped registers in the SYSCFG module, Kick0 and Kick1, with exact
data values. Once these values are written, then all the registers in the SYSCFG module that are
writeable can be written to. See Section 10.2.2 for the exact key values and sequence of steps. Writing
any other data value to either of these kick registers will cause the memory mapped registers to be
“locked” again and block out any write accesses to registers in the SYSCFG module.
10.5.5.1 Kick 0 Register (KICK0R)
The KICK0R is shown in Figure 10-5 and described in Table 10-9.
Figure 10-5. Kick 0 Register (KICK0R)
31
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-9. Kick 0 Register (KICK0R) Field Descriptions
Bit
Field
Value
31-0
KICK0
0-FFFF FFFFh
Description
KICK0R allows writing to unlock the kick0 data. The written data must be 83E7 0B13h to unlock
this register. It must be written before writing to the kick1 register. Writing any other value will lock
the other MMRs.
10.5.5.2 Kick 1 Register (KICK1R)
The KICK1R is shown in Figure 10-6 and described in Table 10-10.
Figure 10-6. Kick 1 Register (KICK1R)
31
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-10. Kick 1 Register (KICK1R) Field Descriptions
Bit
Field
Value
31-0
KICK1
0-FFFF FFFFh
180
Description
KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written
before writing to the kick1 register. Writing any other value will lock the other MMRs.
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10.5.6 Host 0 Configuration Register (HOST0CFG)
The ARM subsystem is held in reset when 0 is written to the BOOTRDY bit in the host 0 configuration
register (HOST0CFG). In a typical application, the BOOTRDY bit should not be cleared.
The HOST0CFG is shown in Figure 10-7 and described in Table 10-11.
Figure 10-7. Host 0 Configuration Register (HOST0CFG)
31
16
Reserved
R-0
15
1
0
Reserved
BOOTRDY
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-11. Host 0 Configuration Register (HOST0CFG) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
BOOTRDY
Description
Reserved
ARM boot ready bit allowing ARM to boot.
0
ARM held in reset mode.
1
ARM released from wait in reset mode.
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10.5.7 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
10.5.7.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 10-8 and described in
Table 10-12.
Figure 10-8. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
182
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
PROTERR
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
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10.5.7.2 Interrupt Enable Status/Clear Register (IENSTAT)
The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows
clearing of the interrupt status. The IENSTAT is shown in Figure 10-9 and described in Table 10-13.
Figure 10-9. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
PROTERR
Protection violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
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10.5.7.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 10-10 and described in Table 10-14.
Figure 10-10. Interrupt Enable Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-14. Interrupt Enable Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
PROTERR_EN
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
10.5.7.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 10-11 and described in Table 10-15.
Figure 10-11. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
184
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
PROTERR_CLR
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
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10.5.7.5 End of Interrupt Register (EOI)
The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of
the SYSCFG interrupt (for address/protection violation). It is required to write a value of 0 to the EOI
register after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of
completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts.
The EOI is shown in Figure 10-12 and described in Table 10-16.
Figure 10-12. End of Interrupt Register (EOI)
31
16
Reserved
R-0
15
8
7
0
Reserved
EOIVECT
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 10-16. End of Interrupt Register (EOI) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
EOIVECT
0-FFh
Description
Reserved. Always read 0.
EOI vector value. Write the interrupt distribution value of the chip.
10.5.8 Fault Registers
The fault registers are a group of registers responsible for capturing the details on the faulty
(address/protection violation errors) accesses, such as address and type of error.
10.5.8.1 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) captures the address of the first transfer that causes the address
or memory violation error. The FLTADDRR is shown in Figure 10-13 and described in Table 10-17.
Figure 10-13. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
Field
FLTADDR
Value
0-FFFF FFFFh
Description
Fault address for the first fault transfer.
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10.5.8.2 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous
transaction. This includes things like the master id for the master that caused the address/memory
violation error, details on whether it is a user or supervisor level read/write or execute fault. The FLTSTAT
is shown in Figure 10-14 and described in Table 10-18.
Figure 10-14. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
ID
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-18. Fault Status Register (FLTSTAT) Field Descriptions
Field
Value
Description
31-24
Bit
ID
0-FFh
Transfer ID of the first fault transfer.
23-16
MSTID
0-FFh
Master ID of the first fault transfer.
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
0
0-Fh
0
Privilege ID of the first fault transfer.
Reserved. Always read 0
Fault type of first fault transfer.
0
No transfer fault
1h
User execute fault
2h
User write fault
3h
Reserved
4h
User read fault
5h-7h
8h
9h-Fh
10h
11h-1Fh
20h
21h-3Fh
186
Reserved. Always read 0
Reserved
Supervisor execute fault
Reserved
Supervisor write fault
Reserved
Supervisor read fault
Reserved
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10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)
10.5.9.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 10-15 and described in Table 10-19.
Figure 10-15. Master Priority 0 Register (MSTPRI0)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
Reserved
Rsvd
Reserved
Rsvd
ARM_D
Rsvd
ARM_I
R/W-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-19. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
4h
Reserved. Write the default value when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
Reserved
2h
Reserved. Write the default value when modifying this register.
11
Reserved
0
Reserved. Always read as 0.
10-8
Reserved
2h
Reserved. Write the default value when modifying this register.
7
Reserved
0
Reserved. Always read as 0.
6-4
3
2-0
ARM_D
Reserved
ARM_I
0-7h
0
0-7h
ARM_D port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
ARM_I port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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10.5.9.2 Master Priority 1 Register (MSTPRI1)
The master priority 1 register (MSTPRI1) is shown in Figure 10-16 and described in Table 10-20.
Figure 10-16. Master Priority 1 Register (MSTPRI1)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
EDMA31TC0
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
EDMA30TC1
Rsvd
EDMA30TC0
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-20. Master Priority 1 Register (MSTPRI1) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
15
14-12
11
10-8
EDMA31TC0
Reserved
EDMA30TC1
Reserved
EDMA30TC0
0-7h
0
0-7h
0
0-7h
EDMA3_1_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
EDMA3_0_TC1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
EDMA3_0_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Always read as 0.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Always read as 0.
2-0
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
188
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10.5.9.3 Master Priority 2 Register (MSTPRI2)
The master priority 2 register (MSTPRI2) is shown in Figure 10-17 and described in Table 10-21.
Figure 10-17. Master Priority 2 Register (MSTPRI2)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-5h
R/W-0
R/W-4h
R/W-0
R/W-6h
R/W-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
USB0CDMA
Rsvd
USB0CFG
Rsvd
Reserved
Rsvd
EMAC
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-0
R/W-0
R/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-21. Master Priority 2 Register (MSTPRI2) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
5h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
6h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
USB0CDMA
0-7h
11
Reserved
0
10-8
USB0CFG
0-7h
USB0 (USB2.0) CDMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
USB0 (USB2.0) CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Write the default value when modifying this register.
2-0
EMAC
0-7h
EMAC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the
smallest possible package. On the device, pin multiplexing can be controlled on a pin by pin basis. This is
done by the pin multiplexing registers (PINMUX0-PINMUX19). Each pin that is multiplexed with several
different functions has a corresponding 4-bit field in PINMUXn. Pin multiplexing selects which of several
peripheral pin functions control the pins I/O buffer output data and output enable values only. Note that the
input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers
have no effect on input from a pin. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used. Detailed information about the pin
multiplexing and control is covered in the device-specific data manual. Access to the pin multiplexing utility
is available in AM18xx Pin Multiplexing Utility Application Report (SPRABA2).
10.5.10.1 Pin Multiplexing Control 0 Register (PINMUX0)
Figure 10-18. Pin Multiplexing Control 0 Register (PINMUX0)
31
28
27
24
23
20
19
16
PINMUX0_31_28
PINMUX0_27_24
PINMUX0_23_20
PINMUX0_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX0_15_12
PINMUX0_11_8
PINMUX0_7_4
PINMUX0_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
Bit
Field
31-28
Value
PINMUX0_31_28
RTC_ALARM/UART2_CTS/GP0[8]/DEEPSLEEP Control
0
Selects Function DEEPSLEEP
1h
Reserved
X
2h
Selects Function RTC_ALARM
O
3h
Reserved
X
4h
Selects Function UART2_CTS
I
Reserved
X
5h-7h
8h
9h-Fh
27-24
PINMUX0_27_24
Selects Function GP0[8]
I/O
Reserved
0
Pin is 3-stated.
1h
Selects Function AMUTE
4h
5h-7h
8h
9h-Fh
190
I
X
AMUTE/UART2_RTS/GP0[9] Control
2h-3h
(1)
Type (1)
Description
Z
I/O
Reserved
X
Selects Function UART2_RTS
O
Reserved
X
Selects Function GP0[9]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit
23-20
Field
Value
PINMUX0_23_20
AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10] Control
0
Pin is 3-stated.
1h
Selects Function AHCLKX
2h
Selects Function USB_REFCLKIN
I
3h
Reserved
X
4h
Selects Function UART1_CTS
I
Reserved
X
5h-7h
8h
9h-Fh
19-16
PINMUX0_19_16
1h
Selects Function AHCLKR
8h
9h-Fh
PINMUX0_15_12
X
Z
I/O
Reserved
X
Selects Function UART1_RTS
O
Reserved
X
Selects Function GP0[11]
I/O
Reserved
X
AFSX/GP0[12] Control
0
Pin is 3-stated.
1h
Selects Function AFSX
2h-7h
8h
9h-Fh
PINMUX0_11_8
Z
I/O
Reserved
X
Selects Function GP0[12]
I/O
Reserved
X
AFSR/GP0[13] Control
0
Pin is 3-stated.
1h
Selects Function AFSR
2h-7h
8h
9h-Fh
PINMUX0_7_4
Z
I/O
Reserved
X
Selects Function GP0[13]
I/O
Reserved
X
ACLKX/GP0[14] Control
0
Pin is 3-stated.
1h
Selects Function ACLKX
2h-7h
8h
9h-Fh
3-0
I/O
Reserved
Pin is 3-stated.
5h-7h
7-4
Selects Function GP0[10]
0
4h
11-8
Z
I/O
AHCLKR/UART1_RTS/GP0[11] Control
2h-3h
15-12
Type (1)
Description
PINMUX0_3_0
Z
I/O
Reserved
X
Selects Function GP0[14]
I/O
Reserved
X
ACLKR/GP0[15] Control
0
Pin is 3-stated.
1h
Selects Function ACLKR
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP0[15]
I/O
Reserved
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10.5.10.2 Pin Multiplexing Control 1 Register (PINMUX1)
Figure 10-19. Pin Multiplexing Control 1 Register (PINMUX1)
31
28
27
24
23
20
19
16
PINMUX1_31_28
PINMUX1_27_24
PINMUX1_23_20
PINMUX1_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX1_15_12
PINMUX1_11_8
PINMUX1_7_4
PINMUX1_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
Bit
Field
31-28
Value
PINMUX1_31_28
AXR8/GP0[0] Control
0
Pin is 3-stated.
1h
Selects Function AXR8
2h-7h
8h
9h-Fh
27-24
PINMUX1_27_24
Selects Function AXR9
PINMUX1_23_20
X
Z
I/O
Reserved
X
Selects Function GP0[1]
I/O
Reserved
X
AXR10/GP0[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR10
8h
9h-Fh
PINMUX1_19_16
Z
I/O
Reserved
X
Selects Function GP0[2]
I/O
Reserved
X
AXR11/GP0[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR11
2h-7h
8h
9h-Fh
PINMUX1_15_12
Z
I/O
Reserved
X
Selects Function GP0[3]
I/O
Reserved
X
AXR12/GP0[4] Control
0
Pin is 3-stated.
1h
Selects Function AXR12
2h-7h
8h
9h-Fh
192
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP0[0]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
AXR9/GP0[1] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP0[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX1_11_8
AXR13/GP0[5] Control
0
Pin is 3-stated.
1h
Selects Function AXR13
2h-7h
8h
9h-Fh
7-4
PINMUX1_7_4
Z
I/O
Reserved
X
Selects Function GP0[5]
I/O
Reserved
X
AXR14/GP0[6] Control
0
Pin is 3-stated.
1h
Selects Function AXR14
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX1_3_0
Z
I/O
Reserved
X
Selects Function GP0[6]
I/O
Reserved
X
AXR15/GP0[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR15
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP0[7]
I/O
Reserved
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10.5.10.3 Pin Multiplexing Control 2 Register (PINMUX2)
Figure 10-20. Pin Multiplexing Control 2 Register (PINMUX2)
31
28
27
24
23
20
19
16
PINMUX2_31_28
PINMUX2_27_24
PINMUX2_23_20
PINMUX2_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX2_15_12
PINMUX2_11_8
PINMUX2_7_4
PINMUX2_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
Bit
Field
31-28
Value
PINMUX2_31_28
AXR0/GP8[7]/MII_TXD[0] Control
0
Pin is 3-stated.
1h
Selects Function AXR0
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX2_27_24
I/O
Reserved
X
Selects Function MII_TXD[0]
O
Reserved
X
Pin is 3-stated.
Selects Function AXR1
8h
9h-Fh
PINMUX2_23_20
Z
I/O
Reserved
X
Selects Function GP1[9]
I/O
Reserved
X
Selects Function MII_TXD[1]
O
Reserved
X
AXR2/GP1[10]/MII_TXD[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR2
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX2_19_16
Z
I/O
Reserved
X
Selects Function GP1[10]
I/O
Reserved
X
Selects Function MII_TXD[2]
O
Reserved
X
AXR3/GP1[11]/MII_TXD[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR3
2h-3h
4h
5h-7h
8h
9h-Fh
194
X
Selects Function GP8[7]
1h
4h
(1)
I/O
AXR1/GP1[9]/MII_TXD[1] Control
5h-7h
19-16
Z
Reserved
0
2h-3h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP1[11]
I/O
Reserved
X
Selects Function MII_TXD[3]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX2_15_12
AXR4/GP1[12]/MII_COL Control
0
Pin is 3-stated.
1h
Selects Function AXR4
2h-3h
4h
5h-7h
8h
9h-Fh
11-8
PINMUX2_11_8
X
Selects Function GP1[12]
I/O
Reserved
X
Selects Function MII_COL
I
Reserved
X
AXR5/GP1[13]/MII_TXCLK Control
Pin is 3-stated.
1h
Selects Function AXR5
4h
5h-7h
8h
9h-Fh
PINMUX2_7_4
Z
I/O
Reserved
X
Selects Function GP1[13]
I/O
Reserved
X
Selects Function MII_TXCLK
I
Reserved
X
AXR6/GP1[14]/MII_TXEN Control
0
Pin is 3-stated.
1h
Selects Function AXR6
2h-3h
4h
5h-7h
8h
9h-Fh
3-0
Z
I/O
Reserved
0
2h-3h
7-4
Type (1)
Description
PINMUX2_3_0
Z
I/O
Reserved
X
Selects Function GP1[14]
I/O
Reserved
X
Selects Function MII_TXEN
O
Reserved
X
AXR7/GP1[15] Control
0
Pin is 3-stated.
1h
Selects Function AXR7
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP1[15]
I/O
Reserved
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10.5.10.4 Pin Multiplexing Control 3 Register (PINMUX3)
Figure 10-21. Pin Multiplexing Control 3 Register (PINMUX3)
31
28
27
24
23
20
19
16
PINMUX3_31_28
PINMUX3_27_24
PINMUX3_23_20
PINMUX3_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX3_15_12
PINMUX3_11_8
PINMUX3_7_4
PINMUX3_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
Bit
Field
31-28
Value
PINMUX3_31_28
SPI0_SCS[2]/UART0_RTS/GP8[1]/MII_RXD[0] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[2]
I/O
2h
Selects Function UART0_RTS
O
3h
Reserved
4h
Selects Function GP8[1]
5h-7h
8h
9h-Fh
27-24
PINMUX3_27_24
Reserved
X
Selects Function MII_RXD[0]
I
Reserved
X
0
Pin is 3-stated.
Selects Function SPI0_SCS[3]
I/O
2h
Selects Function UART0_CTS
I
3h
Reserved
4h
Selects Function GP8[2]
9h-Fh
PINMUX3_23_20
Z
X
I/O
Reserved
X
Selects Function MII_RXD[1]
I
Reserved
X
SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[4]
I/O
2h
Selects Function UART0_TXD
O
3h
Reserved
X
4h
Selects Function GP8[3]
5h-7h
8h
9h-Fh
196
X
I/O
1h
8h
(1)
Z
SPI0_SCS[3]/UART0_CTS/GP8[2]/MII_RXD[1] Control
5h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function MII_RXD[2]
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX3_19_16
SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[5]
2h
Selects Function UART0_RXD
I
3h
Reserved
X
4h
Selects Function GP8[4]
5h-7h
8h
9h-Fh
15-12
PINMUX3_15_12
X
Selects Function MII_RXD[3]
I
Reserved
X
Pin is 3-stated.
1h
Selects Function SPI0_SIMO
5h-7h
8h
9h-Fh
PINMUX3_11_8
Z
I/O
Reserved
X
Selects Function GP8[5]
I/O
Reserved
X
Selects Function MII_CRS
I
Reserved
X
SPI0_SOMI/GP8[6]/MII_RXER Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SOMI
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX3_7_4
Z
I/O
Reserved
X
Selects Function GP8[6]
I/O
Reserved
X
Selects Function MII_RXER
I
Reserved
X
SPI0_ENA/MII_RXDV Control
0
Pin is 3-stated.
1h
Selects Function SPI0_ENA
2h-7h
8h
9h-Fh
3-0
I/O
Reserved
0
4h
7-4
Z
I/O
SPI0_SIMO/GP8[5]/MII_CRS Control
2h-3h
11-8
Type (1)
Description
PINMUX3_3_0
Z
I/O
Reserved
X
Selects Function MII_RXDV
I
Reserved
X
SPI0_CLK/GP1[8]/MII_RXCLK Control
0
Pin is 3-stated.
1h
Selects Function SPI0_CLK
2h-3h
4h
5h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP1[8]
I/O
Reserved
X
Selects Function MII_RXCLK
I
Reserved
X
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10.5.10.5 Pin Multiplexing Control 4 Register (PINMUX4)
Figure 10-22. Pin Multiplexing Control 4 Register (PINMUX4)
31
28
27
24
23
20
19
16
PINMUX4_31_28
PINMUX4_27_24
PINMUX4_23_20
PINMUX4_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX4_15_12
PINMUX4_11_8
PINMUX4_7_4
PINMUX4_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
Bit
Field
31-28
Value
PINMUX4_31_28
SP1_SCS[2]/UART1_TXD/GP1[0] Control
0
Pin is 3-stated.
1h
Selects Function SP1_SCS[2]
I/O
2h
Selects Function UART1_TXD
O
3h-7h
8h
9h-Fh
27-24
PINMUX4_27_24
I/O
Reserved
X
Pin is 3-stated.
Selects Function SPI1_SCS[3]
2h
Selects Function UART1_RXD
I
Reserved
X
PINMUX4_23_20
Z
I/O
Selects Function GP1[1]
I/O
Reserved
X
SPI1_SCS[4]/UART2_TXD/GP1[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[4]
I/O
2h
Selects Function UART2_TXD
O
3h-7h
8h
9h-Fh
PINMUX4_19_16
Z
Reserved
X
Selects Function GP1[2]
I/O
Reserved
X
SPI1_SCS[5]/UART2_RXD/GP1[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[5]
2h
Selects Function UART2_RXD
I
Reserved
X
3h-7h
8h
9h-Fh
198
X
Selects Function GP1[0]
1h
9h-Fh
(1)
Reserved
SPI1_SCS[3]/UART1_RXD/GP1[1] Control
8h
19-16
Z
0
3h-7h
23-20
Type (1)
Description
Z
I/O
Selects Function GP1[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX4_15_12
SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[6]
I/O
2h
Selects Function I2C0_SDA
I/O
3h
Reserved
X
4h
Selects Function TM64P3_OUT12
O
5h-7h
8h
9h-Fh
11-8
PINMUX4_11_8
Reserved
X
Selects Function GP1[4]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[7]
I/O
2h
Selects Function I2C0_SCL
I/O
3h
Reserved
X
4h
Selects Function TM64P2_OUT12
O
8h
9h-Fh
PINMUX4_7_4
Z
Reserved
X
Selects Function GP1[5]
I/O
Reserved
X
SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 Control
0
Selects Function TM64P1_IN12
I
1h
Selects Function SPI0_SCS[0]
I/O
2h
Selects Function TM64P1_OUT12
O
3h
Reserved
4h
Selects Function GP1[6]
5h-7h
8h
9h-Fh
3-0
Z
SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] Control
5h-7h
7-4
Type (1)
Description
PINMUX4_3_0
X
I/O
Reserved
X
Selects Function MDIO_D
I/O
Reserved
X
SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 Control
0
Selects Function TM64P0_IN12
I
1h
Selects Function SPI0_SCS[1]
I/O
2h
Selects Function TM64P0_OUT12
O
3h
Reserved
4h
Selects Function GP1[7]
5h-7h
8h
9h-Fh
X
I/O
Reserved
X
Selects Function MDIO_CLK
O
Reserved
X
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10.5.10.6 Pin Multiplexing Control 5 Register (PINMUX5)
Figure 10-23. Pin Multiplexing Control 5 Register (PINMUX5)
31
28
27
24
23
20
19
16
PINMUX5_31_28
PINMUX5_27_24
PINMUX5_23_20
PINMUX5_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX5_15_12
PINMUX5_11_8
PINMUX5_7_4
PINMUX5_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
Bit
Field
31-28
Value
PINMUX5_31_28
EMA_BA[0]/GP2[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_BA[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX5_27_24
X
Z
Selects Function EMA_BA[1]
O
Reserved
X
PINMUX5_23_20
Selects Function GP2[9]
I/O
Reserved
X
SPI1_SIMO/GP2[10] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SIMO
8h
9h-Fh
PINMUX5_19_16
Z
I/O
Reserved
X
Selects Function GP2[10]
I/O
Reserved
X
SPI1_SOMI/GP2[11] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SOMI
2h-7h
8h
9h-Fh
PINMUX5_15_12
Z
I/O
Reserved
X
Selects Function GP2[11]
I/O
Reserved
X
SPI1_ENA/GP2[12] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_ENA
2h-7h
8h
9h-Fh
200
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP2[8]
1h
9h-Fh
19-16
Reserved
EMA_BA[1]/GP2[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP2[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX5_11_8
SPI1_CLK/GP2[13] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_CLK
2h-7h
8h
9h-Fh
7-4
PINMUX5_7_4
Z
I/O
Reserved
X
Selects Function GP2[13]
I/O
Reserved
X
SPI1_SCS[0]/GP2[14]/TM64P3_IN12 Control
0
Selects Function TM64P3_IN12
I
1h
Selects Function SPI1_SCS[0]
I/O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX5_3_0
Reserved
X
Selects Function GP2[14]
I/O
Reserved
X
SPI1_SCS[1]/GP2[15]/TM64P2_IN12 Control
0
Selects Function TM64P2_IN12
I
1h
Selects Function SPI1_SCS[1]
I/O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP2[15]
I/O
Reserved
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10.5.10.7 Pin Multiplexing Control 6 Register (PINMUX6)
Figure 10-24. Pin Multiplexing Control 6 Register (PINMUX6)
31
28
27
24
23
20
19
16
PINMUX6_31_28
PINMUX6_27_24
PINMUX6_23_20
PINMUX6_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX6_15_12
PINMUX6_11_8
PINMUX6_7_4
PINMUX6_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
Bit
Field
31-28
Value
PINMUX6_31_28
EMA_CS[0]/GP2[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX6_27_24
X
Selects Function EMA_WAIT[1]
I
Reserved
X
PINMUX6_23_20
Z
Selects Function GP2[1]
I/O
Reserved
X
EMA_WE_DQM[1]/GP2[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[1]
O
8h
9h-Fh
PINMUX6_19_16
Reserved
X
Selects Function GP2[2]
I/O
Reserved
X
EMA_WE_DQM[0]/GP2[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[0]
O
2h-7h
8h
9h-Fh
PINMUX6_15_12
Reserved
X
Selects Function GP2[3]
I/O
Reserved
X
EMA_CAS/GP2[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CAS
O
2h-7h
8h
9h-Fh
202
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP2[0]
1h
9h-Fh
19-16
Reserved
EMA_WAIT[1]/GP2[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP2[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX6_11_8
EMA_RAS/GP2[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_RAS
O
2h-7h
8h
9h-Fh
7-4
PINMUX6_7_4
Reserved
X
Selects Function GP2[5]
I/O
Reserved
X
EMA_SDCKE/GP2[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_SDCKE
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX6_3_0
Reserved
X
Selects Function GP2[6]
I/O
Reserved
X
EMA_CLK/GP2[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CLK
O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP2[7]
I/O
Reserved
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10.5.10.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 10-25. Pin Multiplexing Control 7 Register (PINMUX7)
31
28
27
24
23
20
19
16
PINMUX7_31_28
PINMUX7_27_24
PINMUX7_23_20
PINMUX7_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX7_15_12
PINMUX7_11_8
PINMUX7_7_4
PINMUX7_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit
Field
31-28
Value
PINMUX7_31_28
EMA_WAIT[0]/GP3[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WAIT[0]
I
2h-7h
8h
9h-Fh
27-24
PINMUX7_27_24
X
Z
Selects Function EM_A_RW
O
Reserved
X
PINMUX7_23_20
Selects Function GP3[9]
I/O
Reserved
X
EMA_OE/GP3[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_OE
O
8h
9h-Fh
PINMUX7_19_16
Reserved
X
Selects Function GP3[10]
I/O
Reserved
X
EMA_WE/GP3[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE
O
2h-7h
8h
9h-Fh
PINMUX7_15_12
Reserved
X
Selects Function GP3[11]
I/O
Reserved
X
EMA_CS[5]/GP3[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[5]
O
2h-7h
8h
9h-Fh
204
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP3[8]
1h
9h-Fh
19-16
Reserved
EM_A_RW/GP3[9] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP3[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX7_11_8
EMA_CS[4]/GP3[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[4]
O
2h-7h
8h
9h-Fh
7-4
PINMUX7_7_4
Reserved
X
Selects Function GP3[13]
I/O
Reserved
X
EMA_CS[3]/GP3[14] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[3]
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX7_3_0
Reserved
X
Selects Function GP3[14]
I/O
Reserved
X
EMA_CS[2]/GP3[15] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[2]
O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP3[15]
I/O
Reserved
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10.5.10.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 10-26. Pin Multiplexing Control 8 Register (PINMUX8)
31
28
27
24
23
20
19
16
PINMUX8_31_28
PINMUX8_27_24
PINMUX8_23_20
PINMUX8_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX8_15_12
PINMUX8_11_8
PINMUX8_7_4
PINMUX8_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit
Field
31-28
Value
PINMUX8_31_28
EMA_D[8]/GP3[0] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[8]
2h-7h
8h
9h-Fh
27-24
PINMUX8_27_24
Selects Function EMA_D[9]
PINMUX8_23_20
X
Z
I/O
Reserved
X
Selects Function GP3[1]
I/O
Reserved
X
EMA_D[10]/GP3[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[10]
8h
9h-Fh
PINMUX8_19_16
Z
I/O
Reserved
X
Selects Function GP3[2]
I/O
Reserved
X
EMA_D[11]/GP3[3] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[11]
2h-7h
8h
9h-Fh
PINMUX8_15_12
Z
I/O
Reserved
X
Selects Function GP3[3]
I/O
Reserved
X
EMA_D[12]/GP3[4] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[12]
2h-7h
8h
9h-Fh
206
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP3[0]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[9]/GP3[1] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP3[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX8_11_8
EMA_D[13]/GP3[5] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[13]
2h-7h
8h
9h-Fh
7-4
PINMUX8_7_4
Z
I/O
Reserved
X
Selects Function GP3[5]
I/O
Reserved
X
EMA_D[14]/GP3[6] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[14]
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX8_3_0
Z
I/O
Reserved
X
Selects Function GP3[6]
I/O
Reserved
X
EMA_D[15]/GP3[7] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[15]
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP3[7]
I/O
Reserved
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10.5.10.10 Pin Multiplexing Control 9 Register (PINMUX9)
Figure 10-27. Pin Multiplexing Control 9 Register (PINMUX9)
31
28
27
24
23
20
19
16
PINMUX9_31_28
PINMUX9_27_24
PINMUX9_23_20
PINMUX9_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX9_15_12
PINMUX9_11_8
PINMUX9_7_4
PINMUX9_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
Bit
Field
31-28
Value
PINMUX9_31_28
EMA_D[0]/GP4[8] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[0]
2h-7h
8h
9h-Fh
27-24
PINMUX9_27_24
Selects Function EMA_D[1]
PINMUX9_23_20
X
Z
I/O
Reserved
X
Selects Function GP4[9]
I/O
Reserved
X
EMA_D[2]/GP4[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[2]
8h
9h-Fh
PINMUX9_19_16
Z
I/O
Reserved
X
Selects Function GP4[10]
I/O
Reserved
X
EMA_D[3]/GP4[11] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[3]
2h-7h
8h
9h-Fh
PINMUX9_15_12
Z
I/O
Reserved
X
Selects Function GP4[11]
I/O
Reserved
X
EMA_D[4]/GP4[12] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[4]
2h-7h
8h
9h-Fh
208
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP4[8]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[1]/GP4[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP4[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX9_11_8
EMA_D[5]/GP4[13] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[5]
2h-7h
8h
9h-Fh
7-4
PINMUX9_7_4
Z
I/O
Reserved
X
Selects Function GP4[13]
I/O
Reserved
X
EMA_D[6]/GP4[14] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[6]
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX9_3_0
Z
I/O
Reserved
X
Selects Function GP4[14]
I/O
Reserved
X
EMA_D[7]/GP4[15] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[7]
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP4[15]
I/O
Reserved
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10.5.10.11 Pin Multiplexing Control 10 Register (PINMUX10)
Figure 10-28. Pin Multiplexing Control 10 Register (PINMUX10)
31
28
27
24
23
20
19
16
PINMUX10_31_28
PINMUX10_27_24
PINMUX10_23_20
PINMUX10_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX10_15_12
PINMUX10_11_8
PINMUX10_7_4
PINMUX10_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
Bit
Field
31-28
Value
PINMUX10_31_28
EMA_A[16]/MMCSD0_DAT[5]/GP4[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[16]
O
2h
Selects Function MMCSD0_DAT[5]
I/O
3h-7h
8h
9h-Fh
27-24
PINMUX10_27_24
X
Z
Selects Function EMA_A[17]
O
2h
Selects Function MMCSD0_DAT[4]
I/O
PINMUX10_23_20
Reserved
X
Selects Function GP4[1]
I/O
Reserved
X
EMA_A[18]/MMCSD0_DAT[3]/GP4[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[18]
O
2h
Selects Function MMCSD0_DAT[3]
I/O
8h
9h-Fh
PINMUX10_19_16
Reserved
X
Selects Function GP4[2]
I/O
Reserved
X
EMA_A[19]/MMCSD0_DAT[2]/GP4[3] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[19]
O
2h
Selects Function MMCSD0_DAT[2]
I/O
3h-7h
8h
9h-Fh
PINMUX10_15_12
Z
Reserved
X
Selects Function GP4[3]
I/O
Reserved
X
EMA_A[20]/MMCSD0_DAT[1]/GP4[4] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[20]
O
2h
Selects Function MMCSD0_DAT[1]
I/O
3h-7h
8h
9h-Fh
210
Reserved
Pin is 3-stated.
3h-7h
(1)
I/O
1h
9h-Fh
15-12
X
Selects Function GP4[0]
EMA_A[17]/MMCSD0_DAT[4]/GP4[1] Control
8h
19-16
Reserved
0
3h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP4[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX10_11_8
EMA_A[21]/MMCSD0_DAT[0]/GP4[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[21]
O
2h
Selects Function MMCSD0_DAT[0]
I/O
3h-7h
8h
9h-Fh
7-4
PINMUX10_7_4
Reserved
X
Selects Function GP4[5]
I/O
Reserved
X
EMA_A[22]/MMCSD0_CMD/GP4[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[22]
O
2h
Selects Function MMCSD0_CMD
I/O
3h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX10_3_0
Reserved
X
Selects Function GP4[6]
I/O
Reserved
X
MMCSD0_CLK/GP4[7] Control
0
Pin is 3-stated.
Z
1h
Reserved
X
2h
Selects Function MMCSD0_CLK
O
3h-7h
8h
9h-Fh
Reserved
X
Selects Function GP4[7]
I/O
Reserved
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10.5.10.12 Pin Multiplexing Control 11 Register (PINMUX11)
Figure 10-29. Pin Multiplexing Control 11 Register (PINMUX11)
31
28
27
24
23
20
19
16
PINMUX11_31_28
PINMUX11_27_24
PINMUX11_23_20
PINMUX11_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX11_15_12
PINMUX11_11_8
PINMUX11_7_4
PINMUX11_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
Bit
Field
31-28
Value
PINMUX11_31_28
EMA_A[8]/GP5[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[8]
O
2h-7h
8h
9h-Fh
27-24
PINMUX11_27_24
X
Z
Selects Function EMA_A[9]
O
Reserved
X
PINMUX11_23_20
Selects Function GP5[9]
I/O
Reserved
X
EMA_A[10]/GP5[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[10]
O
8h
9h-Fh
PINMUX11_19_16
Reserved
X
Selects Function GP5[10]
I/O
Reserved
X
EMA_A[11]/GP5[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[11]
O
2h-7h
8h
9h-Fh
PINMUX11_15_12
Reserved
X
Selects Function GP5[11]
I/O
Reserved
X
EMA_A[12]/GP5[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[12]
O
2h-7h
8h
9h-Fh
212
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP5[8]
1h
9h-Fh
19-16
Reserved
EMA_A[9]/GP5[9] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP5[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX11_11_8
EMA_A[13]/GP5[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[13]
O
2h-7h
8h
9h-Fh
7-4
PINMUX11_7_4
Reserved
X
Selects Function GP5[13]
I/O
Reserved
X
EMA_A[14]/MMCSD0_DAT[7]/GP5[14] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[14]
O
2h
Selects Function MMCSD0_DAT[7]
I/O
3h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX11_3_0
Z
Reserved
X
Selects Function GP5[14]
I/O
Reserved
X
EMA_A[15]/MMCSD0_DAT[6]/GP5[15] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[15]
O
2h
Selects Function MMCSD0_DAT[6]
I/O
3h-7h
8h
9h-Fh
Z
Reserved
X
Selects Function GP5[15]
I/O
Reserved
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10.5.10.13 Pin Multiplexing Control 12 Register (PINMUX12)
Figure 10-30. Pin Multiplexing Control 12 Register (PINMUX12)
31
28
27
24
23
20
19
16
PINMUX12_31_28
PINMUX12_27_24
PINMUX12_23_20
PINMUX12_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX12_15_12
PINMUX12_11_8
PINMUX12_7_4
PINMUX12_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
Bit
Field
31-28
Value
PINMUX12_31_28
EMA_A[0]/GP5[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX12_27_24
X
Z
Selects Function EMA_A[1]
O
Reserved
X
PINMUX12_23_20
Selects Function GP5[1]
I/O
Reserved
X
EMA_A[2]/GP5[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[2]
O
8h
9h-Fh
PINMUX12_19_16
Reserved
X
Selects Function GP5[2]
I/O
Reserved
X
EMA_A[3]/GP5[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[3]
O
2h-7h
8h
9h-Fh
PINMUX12_15_12
Reserved
X
Selects Function GP5[3]
I/O
Reserved
X
EMA_A[4]/GP5[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[4]
O
2h-7h
8h
9h-Fh
214
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP5[0]
1h
9h-Fh
19-16
Reserved
EMA_A[1]/GP5[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP5[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX12_11_8
EMA_A[5]/GP5[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[5]
O
2h-7h
8h
9h-Fh
7-4
PINMUX12_7_4
Reserved
X
Selects Function GP5[5]
I/O
Reserved
X
EMA_A[6]/GP5[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[6]
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX12_3_0
Reserved
X
Selects Function GP5[6]
I/O
Reserved
X
EMA_A[7]/GP5[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[7]
O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP5[7]
I/O
Reserved
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10.5.10.14 Pin Multiplexing Control 13 Register (PINMUX13)
Figure 10-31. Pin Multiplexing Control 13 Register (PINMUX13)
31
28
27
24
23
20
19
16
PINMUX13_31_28
PINMUX13_27_24
PINMUX13_23_20
PINMUX13_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX13_15_12
PINMUX13_11_8
PINMUX13_7_4
PINMUX13_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
Bit
Field
31-28
Value
PINMUX13_31_28
GP6[8] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX13_27_24
1h-7h
8h
9h-Fh
PINMUX13_23_20
1h-7h
8h
9h-Fh
PINMUX13_19_16
1h-7h
8h
9h-Fh
PINMUX13_15_12
1h-7h
8h
9h-Fh
PINMUX13_11_8
1h-7h
8h
9h-Fh
216
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[9]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[10]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[11]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[12]
I/O
Reserved
X
GP6[13] Control
0
(1)
Selects Function GP6[8]
GP6[12] Control
0
11-8
X
GP6[11] Control
0
15-12
Z
Reserved
GP6[10] Control
0
19-16
Pin is 3-stated.
GP6[9] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[13]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued)
Bit
Field
7-4
PINMUX13_7_4
Value
CLKOUT/GP6[14] Control
0
Pin is 3-stated.
Z
1h
Selects Function CLKOUT
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX13_3_0
Reserved
X
Selects Function GP6[14]
I/O
Reserved
X
RESETOUT/GP6[15] Control
0
Selects Function RESETOUT
O
1h
Selects Function RESETOUT
O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP6[15]
I/O
Reserved
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10.5.10.15 Pin Multiplexing Control 14 Register (PINMUX14)
Figure 10-32. Pin Multiplexing Control 14 Register (PINMUX14)
31
28
27
24
23
20
19
16
PINMUX14_31_28
PINMUX14_27_24
PINMUX14_23_20
PINMUX14_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX14_15_12
PINMUX14_11_8
PINMUX14_7_4
PINMUX14_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
Bit
Field
31-28
Value
PINMUX14_31_28
RMII_RXER Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX14_27_24
1h-7h
8h
9h-Fh
PINMUX14_23_20
1h-7h
8h
9h-Fh
PINMUX14_19_16
1h-7h
8h
9h-Fh
PINMUX14_15_12
1h-7h
8h
9h-Fh
PINMUX14_11_8
1h-7h
8h
9h-Fh
PINMUX14_7_4
1h-7h
8h
9h-Fh
218
X
Pin is 3-stated.
Z
Reserved
X
Selects Function RMII_RXD[0]
I
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function RMII_RXD[1]
I
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function RMII_TXEN
O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function RMII_TXD[0]
O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function RMII_TXD[1]
O
Reserved
X
GP6[6] Control
0
(1)
I
Reserved
RMII_TXD[1] Control
0
7-4
Selects Function RMII_RXER
RMII_TXD[0] Control
0
11-8
X
RMII_TXEN Control
0
15-12
Z
Reserved
RMII_RXD[1] Control
0
19-16
Pin is 3-stated.
RMII_RXD[0] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[6]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued)
Bit
Field
3-0
PINMUX14_3_0
Value
Type (1)
Description
GP6[7] Control
0
1h-7h
8h
9h-Fh
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[7]
I/O
Reserved
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10.5.10.16 Pin Multiplexing Control 15 Register (PINMUX15)
Figure 10-33. Pin Multiplexing Control 15 Register (PINMUX15)
31
28
27
24
23
20
19
16
PINMUX15_31_28
PINMUX15_27_24
PINMUX15_23_20
PINMUX15_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX15_15_12
PINMUX15_11_8
PINMUX15_7_4
PINMUX15_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
Bit
Field
31-28
Value
PINMUX15_31_28
PINMUX15_31_28 Control
0
1h-Fh
27-24
PINMUX15_27_24
1h-Fh
PINMUX15_23_20
0
PINMUX15_19_16
0
PINMUX15_15_12
0
PINMUX15_11_8
1h-Fh
PINMUX15_7_4
1h-7h
8h
9h-Fh
PINMUX15_3_0
1h-7h
8h
9h-Fh
220
Pin is 3-stated.
Z
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function RMII_CRS_DV
I
Reserved
X
RMII_MHZ_50_CLK Control
0
(1)
X
RMII_CRS_DV Control
0
3-0
Z
Reserved
PINMUX15_11_8 Control
0
7-4
Pin is 3-stated.
PINMUX15_15_12 Control
1h-Fh
11-8
X
PINMUX15_19_16 Control
1h-Fh
15-12
Z
Reserved
PINMUX15_23_20 Control
1h-Fh
19-16
Pin is 3-stated.
PINMUX15_27_24 Control
0
23-20
Type (1)
Description
Enables sourcing of the 50 MHz reference clock from an external source on the
RMII_MHZ_50_CLK pin to the EMAC.
I
Reserved
X
Selects Function RMII_MHZ_50_CLK. Enables sourcing of the 50 MHz reference
clock from PLL0_SYSCLK7 to the EMAC. Also, PLL0_SYSCLK7 is driven out on the
RMII_MHZ_50_CLK pin. Note that the SYSCLK7 output clock does not meet the
RMII reference clock specification of 50 MHz +/-50 ppm. See Section 6.3.4 for more
information.
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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10.5.10.17 Pin Multiplexing Control 16 Register (PINMUX16)
Figure 10-34. Pin Multiplexing Control 16 Register (PINMUX16)
31
28
27
24
23
20
19
16
PINMUX16_31_28
PINMUX16_27_24
PINMUX16_23_20
PINMUX16_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX16_15_12
PINMUX16_11_8
PINMUX16_7_4
PINMUX16_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
Bit
31-28
Field
Value
PINMUX16_31_28
GP7[10] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX16_27_24
1h-7h
8h
9h-Fh
PINMUX16_23_20
1h-7h
8h
9h-Fh
PINMUX16_19_16
1h-7h
8h
9h-Fh
PINMUX16_15_12
1h-7h
8h
9h-Fh
PINMUX16_11_8
1h-7h
8h
9h-Fh
PINMUX16_7_4
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[11]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[12]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[13]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[14]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[15]
I/O
Reserved
X
GP6[5] Control
0
3h-7h
8h
9h-Fh
(1)
I/O
Reserved
GP7[15] Control
0
7-4
Selects Function GP7[10]
GP7[14] Control
0
11-8
X
GP7[13] Control
0
15-12
Z
Reserved
GP7[12] Control
0
19-16
Pin is 3-stated.
GP7[11] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[5]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued)
Bit
Field
3-0
PINMUX16_3_0
Value
PINMUX16_3_0 Control
0
1h-Fh
222
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
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10.5.10.18 Pin Multiplexing Control 17 Register (PINMUX17)
Figure 10-35. Pin Multiplexing Control 17 Register (PINMUX17)
31
28
27
24
23
20
19
16
PINMUX17_31_28
PINMUX17_27_24
PINMUX17_23_20
PINMUX17_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX17_15_12
PINMUX17_11_8
PINMUX17_7_4
PINMUX17_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
Bit
31-28
Field
Value
PINMUX17_31_28
GP7[2]/BOOT[2] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX17_27_24
1h-7h
8h
9h-Fh
PINMUX17_23_20
1h-7h
8h
9h-Fh
PINMUX17_19_16
1h-7h
8h
9h-Fh
PINMUX17_15_12
1h-7h
8h
9h-Fh
PINMUX17_11_8
1h-7h
8h
9h-Fh
PINMUX17_7_4
X
Selects Function BOOT[3]
I
Reserved
X
Selects Function GP7[3]
I/O
Reserved
X
Selects Function BOOT[4]
I
Reserved
X
Selects Function GP7[4]
I/O
Reserved
X
Selects Function BOOT[5]
I
Reserved
X
Selects Function GP7[5]
I/O
Reserved
X
Selects Function BOOT[6]
I
Reserved
X
Selects Function GP7[6]
I/O
Reserved
X
Selects Function BOOT[7]
I
Reserved
X
Selects Function GP7[7]
I/O
Reserved
X
GP7[8] Control
0
1h-7h
8h
9h-Fh
(1)
I/O
Reserved
GP7[7]/BOOT[7] Control
0
7-4
Selects Function GP7[2]
GP7[6]/BOOT[6] Control
0
11-8
X
GP7[5]/BOOT[5] Control
0
15-12
I
Reserved
GP7[4]/BOOT[4] Control
0
19-16
Selects Function BOOT[2]
GP7[3]/BOOT[3] Control
0
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[8]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued)
Bit
Field
3-0
PINMUX17_3_0
Value
GP7[9] Control
0
1h-7h
8h
9h-Fh
224
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP7[9]
I/O
Reserved
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X
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10.5.10.19 Pin Multiplexing Control 18 Register (PINMUX18)
Figure 10-36. Pin Multiplexing Control 18 Register (PINMUX18)
31
28
27
24
23
20
19
16
PINMUX18_31_28
PINMUX18_27_24
PINMUX18_23_20
PINMUX18_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX18_15_12
PINMUX18_11_8
PINMUX18_7_4
PINMUX18_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
Bit
31-28
Field
Value
PINMUX18_31_28
GP8[10] Control
0
1h-7h
8h
9h-Fh
27-24
PINMUX18_27_24
1h-7h
8h
9h-Fh
PINMUX18_23_20
1h-7h
8h
9h-Fh
PINMUX18_19_16
1h-7h
8h
9h-Fh
PINMUX18_15_12
1h-7h
8h
9h-Fh
PINMUX18_11_8
1h-7h
8h
9h-Fh
PINMUX18_7_4
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[11]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[12]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[13]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[14]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[15]
I/O
Reserved
X
GP7[0]/BOOT[0] Control
0
1h-7h
8h
9h-Fh
(1)
I/O
Reserved
GP8[15] Control
0
7-4
Selects Function GP8[10]
GP8[14] Control
0
11-8
X
GP8[13] Control
0
15-12
Z
Reserved
GP8[12] Control
0
19-16
Pin is 3-stated.
GP8[11] Control
0
23-20
Type (1)
Description
Selects Function BOOT[0]
I
Reserved
X
Selects Function GP7[0]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued)
Bit
Field
3-0
PINMUX18_3_0
Value
GP7[1]/BOOT[1] Control
0
1h-7h
8h
9h-Fh
226
Type (1)
Description
Selects Function BOOT[1]
I
Reserved
X
Selects Function GP7[1]
I/O
Reserved
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X
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10.5.10.20 Pin Multiplexing Control 19 Register (PINMUX19)
Figure 10-37. Pin Multiplexing Control 19 Register (PINMUX19)
31
28
27
24
23
20
19
16
PINMUX19_31_28
PINMUX19_27_24
PINMUX19_23_20
PINMUX19_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX19_15_12
PINMUX19_11_8
PINMUX19_7_4
PINMUX19_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
Bit
31-28
Field
Value
PINMUX19_31_28
RTCK/GP8[0] Control
0
Selects Function RTCK
O
1h
Selects Function RTCK
O
2h-7h
8h
9h-Fh
27-24
PINMUX19_27_24
0
8h
9h-Fh
PINMUX19_23_20
1h-7h
8h
9h-Fh
PINMUX19_19_16
0
8h
9h-Fh
PINMUX19_15_12
1h-7h
8h
9h-Fh
PINMUX19_11_8
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[0]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[1]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[2]
I/O
Reserved
X
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[3]
I/O
Reserved
X
GP6[4] Control
0
1h-7h
8h
9h-Fh
(1)
Reserved
GP6[3] Control
0
11-8
I/O
GP6[2] Control
1h-7h
15-12
X
Selects Function GP8[0]
GP6[1] Control
0
19-16
Reserved
GP6[0] Control
1h-7h
23-20
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP6[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 10-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions (continued)
Bit
Field
7-4
PINMUX19_7_4
Value
GP8[8] Control
0
1h-7h
8h
9h-Fh
3-0
PINMUX19_3_0
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[8]
I/O
Reserved
X
GP8[9] Control
0
1h-7h
8h
9h-Fh
228
Type (1)
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function GP8[9]
I/O
Reserved
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X
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10.5.11 Suspend Source Register (SUSPSRC)
The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals
that support emulation suspend. A value of 0 for a SUSPSRC bit corresponding to the peripheral,
indicates that the ARM emulator controls the peripheral's emulation suspend signal.
The SUSPSRC is shown in Figure 10-38 and described in Table 10-42.
Figure 10-38. Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
Reserved
Reserved
TIMER64P_2SRC
TIMER64P_1SRC
TIMER64P_0SRC
Reserved
Reserved
Reserved
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
23
22
21
20
19
18
17
16
Reserved
SPI1SRC
SPI0SRC
UART2SRC
UART1SRC
UART0SRC
Reserved
I2C0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USB0SRC
Reserved
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
Reserved
Reserved
EMACSRC
Reserved
TIMER64P_3SRC
Reserved
Reserved
Reserved
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions
Bit
31-30
29
28
27
Field
Reserved
SPI1SRC
19
Reserved. Write the default value to all bits when modifying this register.
Timer2 64 Emulation Suspend Source.
ARM is the source of the emulation suspend.
1
No emulation suspend.
Timer1 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
TIMER64P_0SRC
22
Description
0
TIMER64P_1SRC
Reserved
20
1
TIMER64P_2SRC
26-23
21
Value
Timer0 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
SPI1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
SPI0SRC
SPI0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
UART2SRC
UART2 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
UART1SRC
UART1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
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Table 10-42. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
Field
18
UART0SRC
17
Reserved
16
I2C0SRC
15-10
Reserved
9
USB0SRC
8-6
5
Reserved
3
TIMER64P_3SRC
Reserved
Description
UART0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
I2C0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
USB0 (USB 2.0) Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
EMACSRC
4
2-0
230
Reserved
Value
EMAC Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
Timer3 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
No emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
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10.5.12 Chip Signal Register (CHIPSIG)
Interrupts to the ARM may be generated by setting one of the four CHIPSIG[3-0] bits in the chip signal
register (CHIPSIG). Writing a 1 to these bits sets the interrupts, writing a 0 has no effect. Reads return the
value of these bits and can also be used as status bits. The CHIPSIG is shown in Figure 10-39 and
described in Table 10-43.
Figure 10-39. Chip Signal Register (CHIPSIG)
31
16
Reserved
R-0
15
4
3
2
1
0
Reserved
5
Rsvd
CHIPSIG3
CHIPSIG2
CHIPSIG1
CHIPSIG0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-43. Chip Signal Register (CHIPSIG) Field Descriptions
Bit
Field
Value
Description
31-5
Reserved
0
Reserved
4
Reserved
0
Reserved. Write the default value when modifying this register.
3
CHIPSIG3
2
1
0
Asserts SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG2
Asserts SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG1
Asserts SYSCFG_CHIPINT1 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG0
Asserts SYSCFG_CHIPINT0 interrupt.
0
No effect
1
Asserts interrupt
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10.5.13 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 10-40 and described in Table 10-44.
Figure 10-40. Chip Signal Clear Register (CHIPSIG_CLR)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
Rsvd
CHIPSIG3
CHIPSIG2
CHIPSIG1
CHIPSIG0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit
Field
Value
Description
31-5
Reserved
0
Reserved
4
Reserved
0
Reserved. Write the default value when modifying this register.
3
CHIPSIG3
2
1
0
232
Clears SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG2
Clears SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG1
Clears SYSCFG_CHIPINT1 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG0
Clears SYSCFG_CHIPINT0 interrupt.
0
No effect
1
Clears interrupt
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10.5.14 Chip Configuration 0 Register (CFGCHIP0)
The chip configuration 0 register (CFGCHIP0) controls the following functions:
• PLL Controller 0 memory-mapped register lock: Used to lock out writes to the PLLC0 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC0 register space.
• EDMA3_0 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP0
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_0 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
The CFGCHIP0 is shown in Figure 10-41 and described in Table 10-45.
Figure 10-41. Chip Configuration 0 Register (CFGCHIP0)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PLL_MASTER_LOCK
EDMA30TC1DBS
EDMA30TC0DBS
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
Bit
31-5
4
3-2
1-0
Field
Reserved
Value
0
PLL_MASTER_LOCK
Description
Reserved.
PLLC0 MMRs lock.
0
PLLC0 MMRs are freely accessible.
1
All PLLC0 MMRs are locked.
EDMA30TC1DBS
EDMA3_0_TC1 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
EDMA30TC0DBS
EDMA3_0_TC0 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
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10.5.15 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• EDMA3_1 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP1
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_1 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
• McASP0 AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP0 AMUTEIN signal.
The CFGCHIP1 is shown in Figure 10-42 and described in Table 10-46.
Figure 10-42. Chip Configuration 1 Register (CFGCHIP1)
31
16
Reserved
R/W-0
15
14
13
12
4
3
0
Rsvd
EDMA31TC0DBS
Reserved
AMUTESEL0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
Bit
Field
31-15
Reserved
14-13
EDMA31TC0DBS
12-4
Reserved
3-0
AMUTESEL0
Value
0
Reserved. Write the default value to all bits when modifying this register.
EDMA3_1_TC0 Default Burst Size.
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
Selects the source of McASP0 AMUTEIN signal.
0
Drive McASP0 AMUTEIN signal low.
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
234
Description
Reserved
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10.5.16 Chip Configuration 2 Register (CFGCHIP2)
The chip configuration 2 register (CFGCHIP2) controls the following functions:
• USB2.0 OTG PHY
The CFGCHIP2 is shown in Figure 10-43 and described in Table 10-47.
Figure 10-43. Chip Configuration 2 Register (CFGCHIP2)
31
24
Reserved
R-0
23
18
15
14
17
16
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
R-0
R-0
R-0
12
11
10
9
8
RESET
USB0OTGMODE
13
Reserved
USB0PHYCLKMUX
USB0PHYPWDN
USB0OTGPWRDN
USB0DATPOL
R/W-1
R/W-3h
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
3
7
6
5
4
Reserved
USB0PHY_PLLON
USB0SESNDEN
USB0VBDTCTEN
USB0REF_FREQ
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
Bit
31-18
17
16
15
14-13
Field
Reserved
Clock is not present, power is not good, and PLL has not locked.
1
Clock is present, power is good, and PLL has locked.
Status of USB2.0 PHY VBUS sense.
0
PHY is not sensing voltage presence on the VBUS pin.
1
PHY is sensing voltage presence on the VBUS pin.
USB2.0 PHY reset.
0
Not in reset.
1
USB2.0 PHY in reset.
USB0OTGMODE
USB0PHYCLKMUX
Reserved
0
RESET
Reserved
Description
Status of USB2.0 PHY.
USB0VBUSSENSE
11
9
0
USB0PHYCLKGD
12
10
Value
USB2.0 OTG subsystem mode.
0
No override. PHY drive signals to controller based on its comparators for VBUS and ID pins.
1h
Override phy values to force USB host operation.
2h
Override phy values to force USB device operation.
3h
Override phy values to force USB host operation with VBUS low.
0
Reserved. Write the default value when modifying this register.
USB2.0 PHY reference clock input mux.
0
USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
1
USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL.
USB0PHYPWDN
USB2.0 PHY operation state control.
0
USB2.0 PHY is enabled and is in operating state (normal operation).
1
USB2.0 PHY is disabled and powered down.
USB0OTGPWRDN
USB2.0 OTG subsystem (SS) operation state control.
0
OTG SS is enabled and is in operating state (normal operation).
1
OTG SS is disabled and is powered down.
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Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions (continued)
Bit
8
Field
7
Reserved
6
USB0PHY_PLLON
5
4
3-0
Value
USB0DATPOL
USB2.0 differential data lines polarity selector.
0
Differential data polarities are inverted (USB_DP is connected to D- and USB_DM is
connected to D+).
1
Differential data polarity are not altered (USB_DP is connected to D+ and USB_DM is
connected to D-).
0
Reserved. Write the default value when modifying this register.
Drives USB2.0 PHY, allowing or preventing it from stopping the 48 MHz clock during
USB SUSPEND.
0
USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND.
1
USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND
USB0SESNDEN
USB2.0 Session End comparator enable.
0
Session End comparator is disabled.
1
Session End comparator is enabled.
USB0VBDTCTEN
USB2.0 VBUS line comparators enable.
0
All VBUS line comparators are disabled.
1
All VBUS line comparators are enabled.
USB0REF_FREQ
USB2.0 PHY reference clock input frequencies.
0
Reserved
1h
12 MHz
2h
24 MHz
3h
48 MHz
4h
19.2 MHz
5h
38.4 MHz
6h
13 MHz
7h
26 MHz
8h
20 MHz
9h
40 MHz
Ah-Fh
236
Description
Reserved
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10.5.17 Chip Configuration 3 Register (CFGCHIP3)
The chip configuration 3 register (CFGCHIP3) controls the following peripheral/module functions:
• EMAC MII/RMII Mode Select.
• PLL Controller 1 memory-mapped register lock: Used to lock out writes to the PLLC1 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC1 register space.
• ASYNC3 Clock Source Control: Allows control for the source of the ASYNC3 clock.
• DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.5) hardware clock divider is provided to generate
133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this
clock divider.
• EMIFA Module Clock Source Control: Allows control for the source of the EMIFA module clock.
The CFGCHIP3 is shown in Figure 10-44 and described in Table 10-48.
Figure 10-44. Chip Configuration 3 Register (CFGCHIP3)
31
16
Reserved
R-0
15
9
8
Reserved
RMII_SEL
R/W-7Fh
R/W-1
7
6
5
4
3
2
1
0
Reserved
Reserved
PLL1_MASTER_LOCK
ASYNC3_CLKSRC
Reserved
DIV45PENA
EMA_CLKSRC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-9
Reserved
7Fh
8
RMII_SEL
7-6
5
4
Reserved
Reserved
DIV45PENA
1
0
MII mode
1
RMII mode
0
Reserved. Write the default value when modifying this register.
PLLC1 MMRs lock.
0
PLLC1 MMRs are freely accessible.
1
All PLLC1 MMRs are locked.
Clock source for ASYNC3.
0
Clock driven by PLL0_SYSCLK2.
1
Clock driven by PLL1_SYSCLK2.
0
Reserved. Write the default value when modifying this register.
Controls the fixed DIV4.5 divider in the PLL controller.
0
Divide by 4.5 is disabled.
1
Divide by 4.5 is enabled.
EMA_CLKSRC
Reserved
Reserved. Write the default value to all bits when modifying this register.
EMAC MII/RMII mode select.
ASYNC3_CLKSRC
2
Reserved
0
PLL1_MASTER_LOCK
3
Description
Clock source for EMIFA clock domain.
0
Clock driven by PLL0_SYSCLK3
1
Clock driven by DIV4.5 PLL output
0
Reserved. Write the default value when modifying this register.
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10.5.18 Chip Configuration 4 Register (CFGCHIP4)
The chip configuration 4 register (CFGCHIP4) is used for clearing the AMUNTEIN signal for McASP0.
Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0, if it was
previously set; reads always return a value of 0. The CFGCHIP4 is shown in Figure 10-45 and described
in Table 10-49.
Figure 10-45. Chip Configuration 4 Register (CFGCHIP4)
31
16
Reserved
R-0
15
8
7
1
0
Reserved
Reserved
AMUTECLR0
R/W-FFh
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
Reserved
FFh
Reserved. Write the default value to all bits when modifying this register.
7-1
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
0
AMUTECLR0
Reserved
Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1.
0
No effect
1
Clears interrupt
10.5.19 VTP I/O Control Register (VTPIO_CTL)
The VTP I/O control register (VTPIO_CTL) is used to control the calibration of the DDR2/mDDR memory
controller I/Os with respect to voltage, temperature, and process (VTP). The voltage, temperature, and
process information is used to control the IO's output impedance. The VTPIO_CTL is shown in Figure 1046 and described in Table 10-50.
Figure 10-46. VTP I/O Control Register (VTPIO_CTL)
31
24
Reserved
R-0
23
19
18
17
16
Reserved
VREFEN
VREFTAP
R-0
R/W-0
R/W-0
15
14
13
READY
IOPWRDN
CLKRZ
12
Reserved
9
PWRSAVE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
5
7
6
LOCK
POWERDN
D
3
2
F
R/W-0
R/W-1
R/W-6h
R/W-7h
8
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 10-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions
Bit
Field
31-19
Reserved
18
VREFEN
17-16
Value
0
0
Connected to pad, external reference.
1
Reserved
VREFTAP
Selection for internal reference voltage level.
0
14
13
12-9
8
7
6
5-3
READY
Vref = 50.0% of VDDS
Reserved
VTP Ready status.
0
VTP is not ready.
1
VTP is ready.
IOPWRDN
Power down enable for DDR input buffer.
0
Disable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
1
Enable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
CLKRZ
0
VTP clear. Write 0 to clear VTP flops.
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
PWRSAVE
VTP power save mode. Turn off power to the external resistor when it is not needed. The
PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0.
0
Disable power save mode.
1
Enable power save mode.
LOCK
VTP impedance lock. Lock impedance value so that the VTP controller can be powered down.
0
Unlock impedance.
1
Lock impedance.
POWERDN
VTP power down. Power down the VTP controller. The PWRSAVE bit setting is only valid when
the POWERDN bit is cleared to 0.
0
Disable power down.
1
Enable power down.
D
Drive strength control bit.
0-5h
2-0
Reserved
Internal DDR I/O Vref enable.
1h-3h
15
Description
Reserved
6h
100% drive strength
7h
Reserved
F
Digital filter control bit.
0-6h
7h
Reserved
Digital filter is enabled.
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10.5.20 DDR Slew Register (DDR_SLEW)
The DDR slew register (DDR_SLEW) reflects the DDR I/O timing as programmed in the device eFuse.
The CMOSEN field configures the DDR I/O cells into an LVCMOS buffer (this makes it mDDR
compatible). The DDR_SLEW is shown in Figure 10-47 and described in Table 10-51.
Figure 10-47. DDR Slew Register (DDR_SLEW)
31
16
Reserved
R-0
15
12
7
11
10
9
8
Reserved
ODT_TERMON
ODT_TERMOFF
R-0
R/W-0
R/W-0
5
4
Reserved
6
DDR_PDENA
CMOSEN
3
DDR_DATASLEW
2
1
DDR_CMDSLEW
0
R-0
R/W-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-51. DDR Slew Register (DDR_SLEW) Field Descriptions
Bit
Field
31-12
Reserved
11-10
ODT_TERMON
Value
0
0
ODT_TERMOFF
5
4
3-2
Reserved
No termination
Reserved
0
Reserved
DDR_PDENA
Enables pull downs for mDDR mode (should be disabled for DDR2).
0
Pull downs are disabled. Disable pull downs when using DDR2.
1
Pull downs are enabled. Enable pull downs when using mDDR.
CMOSEN
Selects mDDR LVCMOS RX / SSTL18 differential RX.
0
SSTL Receiver. Select SSTL when using DDR2.
1
LVCMOS Receiver. Select LVCMOS when using mDDR.
DDR_DATASLEW
Slew rate mode control status for data macro. Slew rate control is not supported on this
device.
0
DDR_CMDSLEW
Slew rate control is off.
Reserved
Slew rate mode control status for command macro. Slew rate control is not supported on
this device.
0
1h-3h
240
Reserved
1h-3h
1h-3h
1-0
No termination
Controls Thevenin termination mode while I/O is not in read or write mode. Termination is
not supported on this device.
0
7-6
Reserved
Controls Thevenin termination mode while I/O is in read or write mode. Termination is not
supported on this device.
1h-3h
9-8
Description
Slew rate control is off.
Reserved
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10.5.21 Deep Sleep Register (DEEPSLEEP)
The deep sleep register (DEEPSLEEP) control the Deep Sleep logic. See your device-specific data
manual and the Boot Considerations chapter for details on boot and configuration settings. The
DEEPSLEEP is shown in Figure 10-48 and described in Table 10-52.
Figure 10-48. Deep Sleep Register (DEEPSLEEP)
31
30
SLEEPENABLE
SLEEPCOMPLETE
29
Reserved
16
R/W-0
R-0
R-0
15
0
SLEEPCOUNT
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-52. Deep Sleep Register (DEEPSLEEP) Field Descriptions
Bit
Field
31
SLEEPENABLE
30
Value
Deep sleep enable. The software must clear this bit to 0 when the device is awakened from
deep sleep.
0
Device is in normal operating mode; DEEPSLEEP pin has no effect.
1
Deep sleep mode is enabled; setting DEEPSLEEP pin low initiates oscillator shut down.
SLEEPCOMPLETE
29-16
Reserved
15-0
SLEEPCOUNT
Description
Deep sleep complete. Once the deep sleep process starts, the software must poll the
SLEEPCOMPLETE bit; when the SLEEPCOMPLETE bit is read as 1, the software should
clear the SLEEPENABLE bit and continue operation.
0
SLEEPCOUNT delay is not complete.
1
SLEEPCOUNT delay is complete.
0
Reserved
0-FFFFh
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16
bits are tied directly to the counter in the Deep Sleep logic.
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10.5.22 Pullup/Pulldown Enable Register (PUPD_ENA)
The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin
group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 10-49 and
described in Table 10-53.
Figure 10-49. Pullup/Pulldown Enable Register (PUPD_ENA)
31
0
PUPDENA[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-53. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions
Bit
31-0
Field
Value
PUPDENA[n]
Description
Enables internal pull-up or pull-down functionality for pin group CP[n]. See your devicespecific data manual for pin group information. The internal pull-up or pull-down functionality
selection for bit position n in PUPD_ENA is set in the same bit position n of the pullup/pulldown
select register (PUPD_SEL).
0
Internal pull-up or pull-down functionality for pin group n is disabled.
1
Internal pull-up or pull-down functionality for pin group n is enabled.
10.5.23 Pullup/Pulldown Select Register (PUPD_SEL)
The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for
the pin group n defined in your device-specific data manual. The PUPD_SEL is shown in Figure 10-50 and
described in Table 10-54 and Table 10-55.
NOTE: The PUPD_SEL settings are not active until the device is out of reset. During reset, all of the
CP[n] pins are pulled down. If the application requires a pull-up during reset, an external pullup should be used.
Figure 10-50. Pullup/Pulldown Select Register (PUPD_SEL)
31
0
PUPDSEL[n]
R/W-C3FF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-54. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions
Bit
31-0
242
Field
Value
PUPDSEL[n]
Description
Selects between the internal pull-up or pull-down functionality for pin group CP[n]. See your
device-specific data manual for pin group information. The selection for bit position n in PUPD_SEL
is only valid when the same bit position n is set in the pullup/pulldown enable register
(PUPD_ENA).
0
Internal pull-down functionality for pin group n is disabled.
1
Internal pull-up functionality for pin group n is enabled.
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Table 10-55. Pullup/Pulldown Select Register (PUPD_SEL) Default Values
Default
Value
Bit
Field
31
PUPDSEL[31]
1
Description
Pin Group CP[31] is configured for pull-up by default.
30
PUPDSEL[30]
1
Pin Group CP[30] is configured for pull-up by default.
29
PUPDSEL[29]
0
Pin Group CP[29] is configured for pull-down by default.
28
PUPDSEL[28]
0
Pin Group CP[28] is configured for pull-down by default.
27
PUPDSEL[27]
0
Pin Group CP[27] is configured for pull-down by default.
26
PUPDSEL[26]
0
Pin Group CP[26] is configured for pull-down by default.
25
PUPDSEL[25]
1
Pin Group CP[25] is configured for pull-up by default.
24
PUPDSEL[24]
1
Pin Group CP[24] is configured for pull-up by default.
23
PUPDSEL[23]
1
Pin Group CP[23] is configured for pull-up by default.
22
PUPDSEL[22]
1
Pin Group CP[22] is configured for pull-up by default.
21
PUPDSEL[21]
1
Pin Group CP[21] is configured for pull-up by default.
20
PUPDSEL[20]
1
Pin Group CP[20] is configured for pull-up by default.
19
PUPDSEL[19]
1
Pin Group CP[19] is configured for pull-up by default.
18
PUPDSEL[18]
1
Pin Group CP[18] is configured for pull-up by default.
17
PUPDSEL[17]
1
Pin Group CP[17] is configured for pull-up by default.
16
PUPDSEL[16]
1
Pin Group CP[16] is configured for pull-up by default.
15
PUPDSEL[15]
1
Pin Group CP[15] is configured for pull-up by default.
14
PUPDSEL[14]
1
Pin Group CP[14] is configured for pull-up by default.
13
PUPDSEL[13]
1
Pin Group CP[13] is configured for pull-up by default.
12
PUPDSEL[12]
1
Pin Group CP[12] is configured for pull-up by default.
11
PUPDSEL[11]
1
Pin Group CP[11] is configured for pull-up by default.
10
PUPDSEL[10]
1
Pin Group CP[10] is configured for pull-up by default.
9
PUPDSEL[9]
1
Pin Group CP[9] is configured for pull-up by default.
8
PUPDSEL[8]
1
Pin Group CP[8] is configured for pull-up by default.
7
PUPDSEL[7]
1
Pin Group CP[7] is configured for pull-up by default.
6
PUPDSEL[6]
1
Pin Group CP[6] is configured for pull-up by default.
5
PUPDSEL[5]
1
Pin Group CP[5] is configured for pull-up by default.
4
PUPDSEL[4]
1
Pin Group CP[4] is configured for pull-up by default.
3
PUPDSEL[3]
1
Pin Group CP[3] is configured for pull-up by default.
2
PUPDSEL[2]
1
Pin Group CP[2] is configured for pull-up by default.
1
PUPDSEL[1]
1
Pin Group CP[1] is configured for pull-up by default.
0
PUPDSEL[0]
1
Pin Group CP[0] is configured for pull-up by default.
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10.5.24 RXACTIVE Control Register (RXACTIVE)
The RXACTIVE control register (RXACTIVE) enables or disables the LVCMOS receivers for the pin group
n defined in your device-specific data manual. The RXACTIVE is shown in Figure 10-51 and described in
Table 10-56.
Figure 10-51. RXACTIVE Control Register (RXACTIVE)
31
0
RXACTIVE[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 10-56. RXACTIVE Control Register (RXACTIVE) Field Descriptions
Bit
31-0
244
Field
Value
RXACTIVE[n]
Description
Enables the LVCMOS receivers on pin group n. See your device-specific data manual for pin group
information. Receivers should only be disabled if the associated pin group is not being used.
0
LVCMOS receivers for pin group n are disabled.
1
LVCMOS receivers for pin group n are enabled.
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Chapter 11
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ARM Interrupt Controller (AINTC)
Topic
11.1
11.2
11.3
11.4
...........................................................................................................................
Introduction .....................................................................................................
Interrupt Mapping .............................................................................................
AINTC Methodology ..........................................................................................
AINTC Registers ...............................................................................................
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246
249
253
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11.1 Introduction
The ARM interrupt controller (AINTC) is an interface between interrupts coming from different parts of the
system (these are referred to as system interrupts in this document), and the ARM9 interrupt interface.
ARM9 supports two types of interrupts: FIQ and IRQ (these are referred to as host interrupts in this
document). The AINTC has the following features:
• Supports up to 101 system interrupts.
• Supports up to 32 interrupt channels.
• Channels 0 and 1 are mapped (hard-wired) to the FIQ ARM interrupt and channels 2-31 are mapped to
IRQ ARM interrupt.
• Each system interrupt can be enabled and disabled.
• Each host interrupt can be enabled and disabled.
• Hardware prioritization of interrupts.
• Combining of interrupts from IPs to a single system interrupt.
• Supports two active low debug interrupts.
See the ARM926EJ Technical Reference Manual for information about the ARM's FIQ and IRQ interrupts.
11.2 Interrupt Mapping
The AINTC supports up to 101 system interrupts from different peripherals to be mapped to 32 channels
inside the AINTC (see Figure 11-1). Interrupts from these 32 channels are further mapped to either an
ARM FIQ interrupt or an ARM IRQ interrupt.
•
•
•
•
•
•
•
Any of the 101 system interrupts can be mapped to any of the 32 channels.
Multiple interrupts can be mapped to a single channel.
An interrupt should not be mapped to more than one channel.
Interrupts from channels 0 and 1 are mapped to FIQ ARM interrupt on host side.
Interrupts from channels 2 to 31 are mapped to IRQ ARM interrupt on host side.
For I < k, interrupts on channel-I have higher priority than interrupts on channel-k.
For interrupts on same channel, priority is determined by the hardware interrupt number. The lower the
interrupt number, the higher the priority.
Table 11-1 shows the system interrupt assignments for the AINTC.
Figure 11-1. AINTC Interrupt Mapping
Host Interrupt Mapping
of Channels
AINTC
ARM
Channel 0
Channel Mapping
of System Interrupts
Intr 0
Peripheral A
Intr 1
FIQ
Channel 1
Channel 2
Intr (n–1)
IRQ
Channel m
Peripheral Z
Intr n
n ≤ 100
m ≤ 31
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Table 11-1. AINTC System Interrupt Assignments
Event
Interrupt Name
Source
0
COMMTX
ARM
1
COMMRX
ARM
2
NINT
ARM
—
Reserved
11
EDMA3_0_CC0_INT0
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
12
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrupt
13
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrupt
14
EMIFA_INT
EMIFA Interrupt
15
IIC0_INT
I2C0 interrupt
16
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
17
MMCSD0_INT1
MMCSD0 SDIO Interrupt
18
PSC0_ALLINT
PSC0 Interrupt
19
RTC_IRQS[1:0]
RTC Interrupt
20
SPI0_INT
SPI0 Interrupt
21
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
22
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
23
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
24
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
25
UART0_INT
UART0 Interrupt
26
—
Reserved
27
PROTERR
SYSCFG Protection Shared Interrupt
28
SYSCFG_CHIPINT0
SYSCFG CHIPSIG Register
29
SYSCFG_CHIPINT1
SYSCFG CHIPSIG Register
30
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
31
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
32
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrupt
33
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
34
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
35
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
36
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
37
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
38
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
39
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
40
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
41
DDR2_MEMERR
DDR2 Controller Interrupt
42
GPIO_B0INT
GPIO Bank 0 Interrupt
43
GPIO_B1INT
GPIO Bank 1 Interrupt
44
GPIO_B2INT
GPIO Bank 2 Interrupt
45
GPIO_B3INT
GPIO Bank 3 Interrupt
46
GPIO_B4INT
GPIO Bank 4 Interrupt
47
GPIO_B5INT
GPIO Bank 5 Interrupt
48
GPIO_B6INT
GPIO Bank 6 Interrupt
49
GPIO_B7INT
GPIO Bank 7 Interrupt
50
GPIO_B8INT
GPIO Bank 8 Interrupt
3-10
51-52
—
Reserved
53
UART_INT1
UART1 Interrupt
54
MCASP_INT
McASP0 Combined RX/TX Interrupt
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Table 11-1. AINTC System Interrupt Assignments (continued)
Event
Interrupt Name
Source
55
PSC1_ALLINT
PSC1 Interrupt
56
SPI1_INT
SPI1 Interrupt
57
—
Reserved
58
USB0_INT
USB0 (USB2.0) Interrupt
—
Reserved
UART2_INT
UART2 Interrupt
—
Reserved
T64P2_ALL
Timer64P2 Combined Interrupt (TINT12 and TINT34)
59-60
61
62-67
68
69-73
—
Reserved
74
T64P2_CMPINT0
Timer64P2 - Compare Interrupt 0
75
T64P2_CMPINT1
Timer64P2 - Compare Interrupt 1
76
T64P2_CMPINT2
Timer64P2 - Compare Interrupt 2
77
T64P2_CMPINT3
Timer64P2 - Compare Interrupt 3
78
T64P2_CMPINT4
Timer64P2 - Compare Interrupt 4
79
T64P2_CMPINT5
Timer64P2 - Compare Interrupt 5
80
T64P2_CMPINT6
Timer64P2 - Compare Interrupt 6
81
T64P2_CMPINT7
Timer64P2 - Compare Interrupt 7
82
T64P3_CMPINT0
Timer64P3 - Compare Interrupt 0
83
T64P3_CMPINT1
Timer64P3 - Compare Interrupt 1
84
T64P3_CMPINT2
Timer64P3 - Compare Interrupt 2
85
T64P3_CMPINT3
Timer64P3 - Compare Interrupt 3
86
T64P3_CMPINT4
Timer64P3 - Compare Interrupt 4
87
T64P3_CMPINT5
Timer64P3 - Compare Interrupt 5
88
T64P3_CMPINT6
Timer64P3 - Compare Interrupt 6
89
T64P3_CMPINT7
Timer64P3 - Compare Interrupt 7
90
ARMCLKSTOPREQ
PSC0 Interrupt
—
Reserved
93
EDMA3_1_CC0_INT0
EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
94
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrupt
95
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrupt
96
T64P3_ALL
Timer64P3 Combined Interrupt (TINT12 and TINT34)
—
Reserved
91-92
97-100
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11.3 AINTC Methodology
The AINTC module controls the system interrupt mapping to the host interrupt interface. System interrupts
are generated by the device peripherals. The AINTC receives the system interrupts and maps them to
internal channels. The channels are used to combine and prioritize system interrupts. These channels are
then mapped onto the host interface that is typically a smaller number of host interrupts or a vector input.
Interrupts from system side are active high in polarity. Also, they are pulse type of interrupts.
The AINTC encompasses many functions to process the system interrupts and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, vectorization, debug, and host interfacing. Figure 11-2 illustrates the flow of system interrupts
through the functions to the host. The following subsections describe each part of the flow.
Figure 11-2. Flow of System Interrupts to Host
Status
Enabling
Processing
System
Interrupts
Prioritization
Channel
Mapping
Vectorization
Host
Interfacing
Host Interrupts
Host Int
Mapping
11.3.1 Interrupt Processing
The interrupt processing block does the following tasks:
• Synchronization of slower and asynchronous interrupts
• Conversion of polarity to active high
• Conversion of interrupt type to pulse interrupts
After the processing block, all interrupts will be active-high pulses.
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11.3.2 Interrupt Enabling
The AINTC interrupt enable system allows individual interrupts to be enabled or disabled. Use the
following sequence to enable interrupts:
1. Enable global host interrupts. All host interrupts are enabled by setting the ENABLE bit in the global
enable register (GER). Individual host interrupts are enabled or disabled from their individual enables
and are not overridden by the global enable.
2. Enable host interrupt lines. Host interrupt lines (FIQ and IRQ) can be enabled through one of two
methods:
(a) Set the desired mapped bit(s) in the host interrupt enable register (HIER), or
(b) Write the host interrupt index (0-1) to the host interrupt enable indexed set register (HIEISR) for
every interrupt line to enable.
3. Enable system interrupts. System interrupts can be individually enabled through one of two methods:
(a) Set the desired mapped bit(s) in the system interrupt enable set registers (ESR1-ESR4), or
(b) Write the system interrupt index (0-100) to the system interrupt enable indexed set register (EISR)
for every system interrupt to enable.
11.3.3 Interrupt Status Checking
The next stage is to capture which system interrupts are pending. There are two kinds of pending status:
raw status and enabled status. Raw status is the pending status of the system interrupt without regards to
the enable bit for the system interrupt. Enabled status is the pending status of the system interrupts with
the enable bits active. When the enable bit is inactive, the enabled status will always be inactive.
The enabled status of system interrupts is captured in system interrupt status enabled/clear registers
(SECR1-SECR4). Status of system interrupt 'N' is indicated by the Nth bit of SECR1-SECR4. Since there
exists 101 system interrupts, four 32-bit registers are used to capture the enabled status of interrupts.
The pending status reflects whether the system interrupt occurred since the last time the status register bit
was cleared. Each bit in the status register is individually clearable.
11.3.4 Interrupt Channel Mapping
The AINTC has 32 internal channels to which enabled system interrupts can be mapped. Higher priority
interrupts should be mapped to channels 0 and 1. Other interrupts can be mapped to any of the channels
from 2 to 31. Channel 0 has highest priority and channel 31 has the lowest priority. Channels 0 and 1 are
connected to FIQ ARM interrupt. Channels 2 to 31 are connected to IRQ ARM interrupt. Channels are
used to group the system interrupts into a smaller number of priorities that can be given to a host interface
with a very small number of interrupt inputs. When multiple system interrupts are mapped to the same
channel their interrupts are ORed together so that when either is active the output is active.
The channel map registers (CMRm) define the channel for each system interrupt. There is one register
per 4 system interrupts; therefore, there are 26 channel map registers (CMR0-CMR25) for a system of
101 interrupts. Channel for each system interrupt can be set using these registers.
11.3.5 Host Interrupt Mapping Interrupts
The Host is ARM9, which has two lines: FIQ and IRQ. The 32 channels from the AINTC are mapped to
these two lines. The AINTC has a fixed host interrupt mapping scheme. Channels 0 and 1 are mapped to
FIQ and channels 2-31 are mapped to IRQ. Thus, system interrupts mapped to channels 0 and 1 are
propagated as FIQ to the host and system interrupts mapped to channels 2-31 are propagated as IRQ to
the host. When multiple channels are mapped to the same host interrupt, then prioritization is done to
select which interrupt is in the highest-priority channel and which should be sent first to the host.
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11.3.6 Interrupt Prioritization
The next stage of the AINTC is prioritization. Since multiple interrupts feed into a single channel and
multiple channels feed into a single host interrupt, it is necessary to prioritize between all the system
interrupts/channels to decide on a single system interrupt to handle. The AINTC provides hardware to
perform this prioritization with a given scheme so that software does not have to do this. There are two
levels of prioritizations:
1. The first level of prioritization is between the active channels for a host interrupt. Channel 0 has the
highest priority and channel 31 has the lowest. So the first level of prioritization picks the lowest
numbered active channel.
2. The second level of prioritization is between the active system interrupts for the prioritized channel.
The system interrupt in vector position 0 has the highest priority and system interrupt 100 has the
lowest priority. So the second level of prioritization picks the lowest vector position active system
interrupt.
The prioritized system interrupt for each host interrupt line (FIQ and IRQ) can be obtained from the host
interrupt prioritized index registers (HIPIR1 and HIPIR2). The host interrupt prioritized index register
values update dynamically as interrupts arrive at AINTC so care should be taken to avoid register race
conditions.
The AINTC features a prioritization hold mode that is intended to prevent race conditions while servicing
interrupts. This mode is enabled by setting the priority hold mode (PRHOLDMODE) bit in the control
register (CR). When enabled, a read of either the host interrupt prioritized index register (HIPIRn) or the
host interrupt prioritized vector register (HIPVRn) will freeze both the HIPIRn and HIPVRn values for the
respective host interrupt n. The values are frozen until one of the following actions is taken to release the
registers:
1. Write to the host interrupt prioritized index register (HIPIRn)
2. Write to the host interrupt prioritized vector register (HIPVRn)
3. Write-set bit n of the host interrupt enable register (HIER)
4. Write-set the active interrupt index to the host interrupt enable index set register (HIEISR)
5. Write-clear the active interrupt index to the host interrupt enable index clear register (HIEICR)
11.3.7 Interrupt Nesting
If interrupt service routines (ISRs) consume a large number of CPU cycles and may delay the servicing of
other interrupts, the AINTC can perform a nesting function in its prioritization. Nesting is a method of
disabling certain interrupts (usually lower-priority interrupts) when an interrupt is taken so that only those
desired interrupts can trigger to the host while it is servicing the current interrupt. The typical usage is to
nest on the current interrupt and disable all interrupts of the same or lower priority (or channel). Then the
host will only be interrupted from a higher priority interrupt.
Nesting is available in 1 of 3 methods selectable by the NESTMODE bit in the control register (CR):
1. Nesting for all host interrupts, based on channel priority: When an interrupt is taken, the nesting level is
set to its channel priority. From then, that channel priority and all lower priority channels will be
disabled from generating host interrupts and only higher priority channels are allowed. When the
interrupt is completely serviced, the nesting level is returned to its original value. When there is no
interrupt being serviced, there are no channels disabled due to nesting. The global nesting level
register (GNLR) allows the checking and setting of the global nesting level across all host interrupts.
The nesting level is the channel (and all of lower priority channels) that are nested out because of a
current interrupt.
2. Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority
for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting
level is set to its channel priority for just that host interrupt, and other host interrupts do not have their
nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host
but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting
level for the host interrupt is returned to its original value. The host interrupt nesting level registers
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level
controls which channel and lower priority channels are nested. There is one register per host interrupt.
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3. Software manually performs the nesting of interrupts. When an interrupt is taken, the software will
disable all the host interrupts, manually update the enables for any or all the system interrupts, and
then re-enable all the host interrupts. This now allows only the system interrupts that are still enabled
to trigger to the host. When the interrupt is completely serviced the software must reverse the changes
to re-enable the nested out system interrupts. This method requires the most software interaction but
gives the most flexibility if simple channel based nesting mechanisms are not adequate.
The recommended approach is the automatic host interrupt nesting method (second method). Because
higher priority interrupts can preempt lower priority interrupts in this method, a software stack is used to
keep track of nest priorities. The base stack value should be initialized to the default nest priority of the
application. Take the following steps within the ARM hardware interrupt service routine to handle interrupts
using host interrupt priority nesting:
1. Disable the ARM hardware interrupt.
2. Clear the OVERRIDE bit in the host interrupt nesting level register n (HINLRn) to expose the priority
level of the active interrupt.
3. Push the active (or desired) interrupt priority value into the nest priority stack.
4. Write the active (or desired) priority level into HINLRn by setting the OVERRIDE bit.
5. Calculate and store the ISR address for the active interrupt. Unfreeze the host interrupt prioritized
index register n (HIPIRn) and the host interrupt prioritized vector register n (HIPVRn), if the
PRHOLDMODE bit in the control register (CR) is set.
6. Clear the system interrupt status by setting the appropriate bit in the system interrupt status
enabled/clear register n (SECRn) or by writing the appropriate index to the system interrupt status
indexed clear register (SICR).
7. Acknowledge and enable the ARM hardware interrupt.
8. Execute the ISR at the address stored from step 5. During this step, interrupts enabled by the new
nest priority level will be able to preempt the ISR.
9. Disable the ARM hardware interrupt.
10. Discard the most recent priority level in the nest priority stack and restore the previous priority level to
HINLRn by setting the OVERRIDE bit.
11. Enable the ARM hardware interrupt.
11.3.8 Interrupt Vectorization
The next stage of the AINTC is vectorization. Vectorization is an advanced feature that allows the host to
receive an interrupt service routine (ISR) address in addition to just the interrupt status. Without
vectorization the host would receive the interrupt and enter a general ISR that gets the prioritized system
interrupt to service from the AINTC, looks up the specific ISR address for that system interrupt, and then
jumps to that address. With vectorization the host can read a register that has the ISR address already
calculated and jump to that address immediately.
Vectorization uses a base and universal size where all the ISR code is placed in a contiguous memory
region with each ISR code a standard size. For this calculation, the vector base register (VBR) is
programmed by software to hold the base address of all the ISR code and the vector size register (VSR)
is programmed for the size in words between ISR code for each system interrupt. The index number of
each system interrupt is used to calculate the final offset. The specific system interrupt ISR address is
then calculated as:
ISR address = base + (index × size)
There is also a special case when there is no interrupt pending and then the ISR address is the ISR Null
address. This is in case the vector address is executed when there is no pending interrupt so that a Null
handler can be in place to just return from the interrupt. The vector null address register (VNR) holds the
address of the ISR null address. When there is a pending interrupt then the ISR address is calculated as
exact base + offset for that interrupt number.
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11.3.9 Interrupt Status Clearing
After servicing the interrupt (after execution of the ISR), interrupt status is to be cleared. If a system
interrupt status is not cleared, then another host interrupt may not be triggered or another host interrupt
may be triggered incorrectly. For clearing the status of an interrupt, whose interrupt number is N, write a 1
to the Nth bit position in the system interrupt status enabled/clear registers (SECR1-SECR4). System
interrupt N can also be cleared by writing the value N into the system interrupt status indexed clear
register (SICR).
11.3.10 Interrupt Disabling
At any time, if any interrupt is not to be propagated to the host, then that interrupt should be disabled. For
disabling an interrupt whose interrupt number is N, write a 1 to the Nth bit in the system interrupt enable
clear registers (ECR1-ECR4). System interrupt N can also be disabled by writing the value N in the
system interrupt enable indexed clear register (EICR).
11.4 AINTC Registers
Table 11-2 lists the memory-mapped registers for the AINTC.
Table 11-2. ARM Interrupt Controller (AINTC) Registers
Address
Acronym
Register Description
FFFE E000h
REVID
Revision Identification Register
Section 11.4.1
FFFE E004h
CR
Control Register
Section 11.4.2
FFFE E010h
GER
Global Enable Register
Section 11.4.3
FFFE E01Ch
GNLR
Global Nesting Level Register
Section 11.4.4
FFFE E020h
SISR
System Interrupt Status Indexed Set Register
Section 11.4.5
FFFE E024h
SICR
System Interrupt Status Indexed Clear Register
Section 11.4.6
FFFE E028h
EISR
System Interrupt Enable Indexed Set Register
Section 11.4.7
FFFE E02Ch
EICR
System Interrupt Enable Indexed Clear Register
Section 11.4.8
FFFE E034h
HIEISR
Host Interrupt Enable Indexed Set Register
Section 11.4.9
FFFE E038h
HIEICR
Host Interrupt Enable Indexed Clear Register
Section 11.4.10
FFFE E050h
VBR
Vector Base Register
Section 11.4.11
FFFE E054h
VSR
Vector Size Register
Section 11.4.12
FFFE E058h
VNR
Vector Null Register
Section 11.4.13
FFFE E080h
GPIR
Global Prioritized Index Register
Section 11.4.14
FFFE E084h
GPVR
Global Prioritized Vector Register
Section 11.4.15
FFFE E200h
SRSR1
System Interrupt Status Raw/Set Register 1
Section 11.4.16
FFFE E204h
SRSR2
System Interrupt Status Raw/Set Register 2
Section 11.4.17
FFFE E208h
SRSR3
System Interrupt Status Raw/Set Register 3
Section 11.4.18
FFFE E20Ch
SRSR4
System Interrupt Status Raw/Set Register 4
Section 11.4.19
FFFE E280h
SECR1
System Interrupt Status Enabled/Clear Register 1
Section 11.4.20
FFFE E284h
SECR2
System Interrupt Status Enabled/Clear Register 2
Section 11.4.21
FFFE E288h
SECR3
System Interrupt Status Enabled/Clear Register 3
Section 11.4.22
FFFE E28Ch
SECR4
System Interrupt Status Enabled/Clear Register 4
Section 11.4.23
FFFE E300h
ESR1
System Interrupt Enable Set Register 1
Section 11.4.24
FFFE E304h
ESR2
System Interrupt Enable Set Register 2
Section 11.4.25
FFFE E308h
ESR3
System Interrupt Enable Set Register 3
Section 11.4.26
FFFE E30Ch
ESR4
System Interrupt Enable Set Register 4
Section 11.4.27
FFFE E380h
ECR1
System Interrupt Enable Clear Register 1
Section 11.4.28
FFFE E384h
ECR2
System Interrupt Enable Clear Register 2
Section 11.4.29
FFFE E388h
ECR3
System Interrupt Enable Clear Register 3
Section 11.4.30
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Table 11-2. ARM Interrupt Controller (AINTC) Registers (continued)
Address
Acronym
Register Description
FFFE E38Ch
ECR4
System Interrupt Enable Clear Register 4
Section 11.4.31
Section
FFFE E400h–
FFFE E464h
CMR0-CMR25
Channel Map Registers 0-25
Section 11.4.32
FFFE E900h
HIPIR1
Host Interrupt Prioritized Index Register 1
Section 11.4.33
FFFE E904h
HIPIR2
Host Interrupt Prioritized Index Register 2
Section 11.4.34
FFFE F100h
HINLR1
Host Interrupt Nesting Level Register 1
Section 11.4.35
FFFE F104h
HINLR2
Host Interrupt Nesting Level Register 2
Section 11.4.36
FFFE F500h
HIER
Host Interrupt Enable Register
Section 11.4.37
FFFE F600h
HIPVR1
Host Interrupt Prioritized Vector Register 1
Section 11.4.38
FFFE F604h
HIPVR2
Host Interrupt Prioritized Vector Register 2
Section 11.4.39
11.4.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 19-35 and described in Table 11-3.
Figure 11-3. Revision Identification Register (REVID)
31
0
REV
R-4E82 A900h
LEGEND: R = Read only; -n = value after reset
Table 11-3. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E82 A900h
254
Description
Revision ID of the AINTC.
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11.4.2 Control Register (CR)
The control register (CR) holds global control parameters. The CR is shown in Figure 11-4 and described
in Table 11-4.
Figure 11-4. Control Register (CR)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PRHOLDMODE
NESTMODE
Reserved
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-4. Control Register (CR) Field Descriptions
Bit
31-5
4
3-2
1-0
Field
Reserved
Value
0
PRHOLDMODE
NESTMODE
Reserved
Description
Reserved
Enables priority holding mode.
0
No priority holding. Prioritized MMRs will continually update.
1
Priority holding enabled. Prioritized Index and Vector Address MMRs will hold their value after the
first is read. See Section 11.3.6 for details.
0-3h
Nesting mode.
0
No nesting
1h
Automatic individual nesting (per host interrupt)
2h
Automatic global nesting (over all host interrupts)
3h
Manual nesting
0
Reserved
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11.4.3 Global Enable Register (GER)
The global enable register (GER) enables all the host interrupts. Individual host interrupts are still enabled
or disabled from their individual enables and are not overridden by the global enable. The GER is shown
in Figure 11-5 and described in Table 11-5.
Figure 11-5. Global Enable Register (GER)
31
16
Reserved
R-0
15
1
0
Reserved
ENABLE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-5. Global Enable Register (GER) Field Descriptions
Bit
Field
Value
31-1
Reserved
0
0
ENABLE
0-1
Description
Reserved
The current global enable value when read. Writes set the global enable.
11.4.4 Global Nesting Level Register (GNLR)
The global nesting level register (GNLR) allows the checking and setting of the global nesting level across
all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of
lower priority) that are nested out because of a current interrupt. The GNLR is shown in Figure 11-6 and
described in Table 11-6.
Figure 11-6. Global Nesting Level Register (GNLR)
31
30
16
OVERRIDE
Reserved
R/W-0
R-0
15
9
8
0
Reserved
NESTLVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-6. Global Nesting Level Register (GNLR) Field Descriptions
Bit
Field
31
OVERRIDE
Value
0-1
30-9
Reserved
0
8-0
NESTLVL
0-1FFh
256
ARM Interrupt Controller (AINTC)
Description
Always read as 0. Writes of 1 override the automatic nesting and set the NESTLVL to the written
data.
Reserved
The current global nesting level (highest channel that is nested). Writes set the nesting level. In
autonesting mode this value is updated internally, unless the auto_override bit is set.
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11.4.5 System Interrupt Status Indexed Set Register (SISR)
The system interrupt status indexed set register (SISR) allows setting the status of an interrupt. The
interrupt to set is the INDEX value written. This sets the Raw Status Register bit of the given INDEX. The
SISR is shown in Figure 11-7 and described in Table 11-7.
Figure 11-7. System Interrupt Status Indexed Set Register (SISR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-7. System Interrupt Status Indexed Set Register (SISR) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
INDEX
Description
0
Reserved
0-7Fh
Writes set the status of the interrupt given in the INDEX value. Reads return 0.
11.4.6 System Interrupt Status Indexed Clear Register (SICR)
The system interrupt status indexed clear register (SICR) allows clearing the status of an interrupt. The
interrupt to clear is the INDEX value written. This clears the Raw Status Register bit of the given INDEX.
The SICR is shown in Figure 11-8 and described in Table 11-8.
Figure 11-8. System Interrupt Status Indexed Clear Register (SICR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-8. System Interrupt Status Indexed Clear Register (SICR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INDEX
Value
0
0-7Fh
Description
Reserved
Writes clear the status of the interrupt given in the INDEX value. Reads return 0.
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11.4.7 System Interrupt Enable Indexed Set Register (EISR)
The system interrupt enable indexed set register (EISR) allows enabling an interrupt. The interrupt to
enable is the INDEX value written. This sets the Enable Register bit of the given INDEX. The EISR is
shown in Figure 11-9 and described in Table 11-9.
Figure 11-9. System Interrupt Enable Indexed Set Register (EISR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-9. System Interrupt Enable Indexed Set Register (EISR) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
INDEX
Description
0
Reserved
0-7Fh
Writes set the enable of the interrupt given in the INDEX value. Reads return 0.
11.4.8 System Interrupt Enable Indexed Clear Register (EICR)
The system interrupt enable indexed clear register (EICR) allows disabling an interrupt. The interrupt to
disable is the INDEX value written. This clears the Enable Register bit of the given INDEX. The EICR is
shown in Figure 11-10 and described in Table 11-10.
Figure 11-10. System Interrupt Enable Indexed Clear Register (EICR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INDEX
258
Value
0
0-7Fh
ARM Interrupt Controller (AINTC)
Description
Reserved
Writes clear the enable of the interrupt given in the INDEX value. Reads return 0.
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11.4.9 Host Interrupt Enable Indexed Set Register (HIEISR)
The host interrupt enable indexed set register (HIEISR) allows enabling a host interrupt output. The host
interrupt to enable is the INDEX value written. This enables the host interrupt output or triggers the output
again if already enabled. The HEISR is shown in Figure 11-11 and described in Table 11-11.
Figure 11-11. Host Interrupt Enable Indexed Set Register (HEISR)
31
16
Reserved
R-0
15
1
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
INDEX
Description
Reserved
Writes set the enable of the host interrupt given in the INDEX value. Reads return 0.
0
Writing a 0 sets FIQ.
1
Writing a 1 sets IRQ.
11.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR)
The host interrupt enable indexed clear register (HIEICR) allows disabling a host interrupt output. The host
interrupt to disable is the INDEX value written. This disables the host interrupt output. The HIEICR is
shown in Figure 11-12 and described in Table 11-12.
Figure 11-12. Host Interrupt Enable Indexed Clear Register (HIEICR)
31
16
Reserved
R-0
15
1
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-12. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
INDEX
Description
Reserved
Writes clear the enable of the host interrupt given in the INDEX value. Reads return 0.
0
Writing a 0 clears FIQ.
1
Writing a 1 clears IRQ.
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11.4.11 Vector Base Register (VBR)
The vector base register (VBR) holds the base address of the ISR vector addresses. The VBR is shown in
Figure 11-13 and described in Table 11-13.
Figure 11-13. Vector Base Register (VBR)
31
0
BASE
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-13. Vector Base Register (VBR) Field Descriptions
Bit
Field
Value
Description
31-0
BASE
0-FFFF FFFFh
ISR Base Address.
11.4.12 Vector Size Register (VSR)
The vector size register (VSR) holds the sizes of the individual ISR routines in the vector table. This is
only the sizes to space the calculated vector addresses for the initial ISR targets (the ISR targets could
branch off to the full ISR routines). The VSR is shown in Figure 11-14 and described in Table 11-14.
NOTE: The VSR must be configured even if the desired value is equal to the default value.
Figure 11-14. Vector Size Register (VSR)
31
16
Reserved
R-0
15
8
7
0
Reserved
SIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-14. Vector Size Register (VSR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
SIZE
Value
0
0-FFh
Description
Reserved
Size of ISR address spaces.
0
4 bytes
1h
8 bytes
2h
16 bytes
3h
32 bytes
4h
64 bytes
5h-FFh ...
260
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11.4.13 Vector Null Register (VNR)
The vector null register (VNR) holds the address of the ISR null address that handles no pending
interrupts (if accidentally branched to when no interrupts are pending). The VNR is shown in Figure 11-15
and described in Table 11-15.
Figure 11-15. Vector Null Register (VNR)
31
0
NULL
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-15. Vector Null Register (VNR) Field Descriptions
Bit
Field
Value
31-0
NULL
0-FFFF FFFFh
Description
ISR Null Address.
11.4.14 Global Prioritized Index Register (GPIR)
The global prioritized index register (GPIR) shows the interrupt number of the highest priority interrupt
pending across all the host interrupts. The GPIR is shown in Figure 11-16 and described in Table 11-16.
Figure 11-16. Global Prioritized Index Register (GPIR)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-16. Global Prioritized Index Register (GPIR) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are
pending.
Reserved
The currently highest priority interrupt index pending across all the host interrupts.
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11.4.15 Global Prioritized Vector Register (GPVR)
The global prioritized vector register (GPVR) shows the interrupt vector address of the highest priority
interrupt pending across all the host interrupts. The GPVR is shown in Figure 11-17 and described in
Table 11-17.
Figure 11-17. Global Prioritized Vector Register (GPVR)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-17. Global Prioritized Vector Register (GPVR) Field Descriptions
Bit
Field
Value
Description
31-0
ADDR
0-FFFF FFFFh
The currently highest priority interrupts vector address across all the host interrupts.
11.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1)
The system interrupt status raw/set register 1 (SRSR1) shows the pending enabled status of the system
interrupts 0 to 31. Software can write to SRSR1 to set a system interrupt without a hardware trigger. There
is one bit per system interrupt. The SRSR1 is shown in Figure 11-18 and described in Table 11-18.
Figure 11-18. System Interrupt Status Raw/Set Register 1 (SRSR1)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-18. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions
Bit
31-0
262
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n.
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11.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2)
The system interrupt status raw/set register 2 (SRSR2) shows the pending enabled status of the system
interrupts 32 to 63. Software can write to SRSR2 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR2 is shown in Figure 11-19 and described in Table 11-19.
Figure 11-19. System Interrupt Status Raw/Set Register 2 (SRSR2)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-19. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions
Bit
31-0
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 32.
11.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3)
The system interrupt status raw/set register 3 (SRSR3) shows the pending enabled status of the system
interrupts 64 to 95. Software can write to SRSR3 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR3 is shown in Figure 11-20 and described in Table 11-20.
Figure 11-20. System Interrupt Status Raw/Set Register 3 (SRSR3)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-20. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions
Bit
31-0
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 64 to 95. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 64.
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11.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4)
The system interrupt status raw/set register 4 (SRSR4) shows the pending enabled status of the system
interrupts 96 to 100. Software can write to SRSR4 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR4 is shown in Figure 11-21 and described in Table 11-21.
Figure 11-21. System Interrupt Status Raw/Set Register 4 (SRSR4)
31
5
4
0
Reserved
RAW_STATUS[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
RAW_STATUS[n]
Description
0
Reserved
System interrupt raw status and setting of the system interrupts 96 to 100. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 96.
11.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1)
The system interrupt status enabled/clear register 1 (SECR1) shows the pending enabled status of the
system interrupts 0 to 31. Software can write to SECR1 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR1 is
shown in Figure 11-22 and described in Table 11-22.
Figure 11-22. System Interrupt Status Enabled/Clear Register 1 (SECR1)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions
Bit
31-0
264
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n.
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11.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2)
The system interrupt status enabled/clear register 2 (SECR2) shows the pending enabled status of the
system interrupts 32 to 63. Software can write to SECR2 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR2 is
shown in Figure 11-23 and described in Table 11-23.
Figure 11-23. System Interrupt Status Enabled/Clear Register 2 (SECR2)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions
Bit
31-0
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 32.
11.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3)
The system interrupt status enabled/clear register 3 (SECR3) shows the pending enabled status of the
system interrupts 64 to 95. Software can write to SECR3 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR3 is
shown in Figure 11-24 and described in Table 11-24.
Figure 11-24. System Interrupt Status Enabled/Clear Register 3 (SECR3)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions
Bit
31-0
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 64 to 95. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 64.
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11.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4)
The system interrupt status enabled/clear register 4 (SECR4) shows the pending enabled status of the
system interrupts 96 to 100. Software can write to SECR4 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR4 is
shown in Figure 11-25 and described in Table 11-25.
Figure 11-25. System Interrupt Status Enabled/Clear Register 4 (SECR4)
31
5
4
0
Reserved
ENBL_STATUS[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
0
4-0
ENBL_STATUS[n]
Description
Reserved
System interrupt enabled status and clearing of the system interrupts 96 to 100. Reads return
the enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 96.
11.4.24 System Interrupt Enable Set Register 1 (ESR1)
The system interrupt enable set register 1 (ESR1) enables system interrupts 0 to 31 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR1 is shown in Figure 11-26 and described in Table 11-26.
Figure 11-26. System Interrupt Enable Set Register 1 (ESR1)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-26. System Interrupt Enable Set Register 1 (ESR1) Field Descriptions
Bit
31-0
266
Field
Value
ENABLE[n]
Description
System interrupt 0 to 31 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n.
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11.4.25 System Interrupt Enable Set Register 2 (ESR2)
The system interrupt enable set register 2 (ESR2) enables system interrupts 32 to 63 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR2 is shown in Figure 11-27 and described in Table 11-27.
Figure 11-27. System Interrupt Enable Set Register 2 (ESR2)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-27. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions
Bit
31-0
Field
Value
ENABLE[n]
Description
System interrupt 32 to 63 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 32.
11.4.26 System Interrupt Enable Set Register 3 (ESR3)
The system interrupt enable set register 3 (ESR3) enables system interrupts 64 to 95 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR3 is shown in Figure 11-28 and described in Table 11-28.
Figure 11-28. System Interrupt Enable Set Register 3 (ESR3)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-28. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions
Bit
31-0
Field
Value
ENABLE[n]
Description
System interrupt 64 to 95 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 64.
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11.4.27 System Interrupt Enable Set Register 4 (ESR4)
The system interrupt enable set register 4 (ESR4) enables system interrupts 96 to 100 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR4 is shown in Figure 11-29 and described in Table 11-29.
Figure 11-29. System Interrupt Enable Set Register 4 (ESR4)
31
5
4
0
Reserved
ENABLE[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-29. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
ENABLE[n]
0
Description
Reserved
System interrupt 96 to 100 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 96.
11.4.28 System Interrupt Enable Clear Register 1 (ECR1)
The system interrupt enable clear register 1 (ECR1) disables system interrupts 0 to 31 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR1 is shown in Figure 11-30 and described in Table 11-30.
Figure 11-30. System Interrupt Enable Clear Register 1 (ECR1)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-30. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions
Bit
31-0
268
Field
Value
DISABLE[n]
Description
System interrupt 0 to 31 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n.
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11.4.29 System Interrupt Enable Clear Register 2 (ECR2)
The system interrupt enable clear register 2 (ECR2) disables system interrupts 32 to 63 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR2 is shown in Figure 11-31 and described in Table 11-31.
Figure 11-31. System Interrupt Enable Clear Register 2 (ECR2)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-31. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions
Bit
31-0
Field
Value
DISABLE[n]
Description
System interrupt 32 to 63 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 32.
11.4.30 System Interrupt Enable Clear Register 3 (ECR3)
The system interrupt enable clear register 3 (ECR3) disables system interrupts 64 to 95 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR3 is shown in Figure 11-32 and described in Table 11-32.
Figure 11-32. System Interrupt Enable Clear Register 3 (ECR3)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 11-32. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions
Bit
27-0
Field
Value
DISABLE[n]
Description
System interrupt 64 to 95 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 64.
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11.4.31 System Interrupt Enable Clear Register 4 (ECR4)
The system interrupt enable clear register 4 (ECR4) disables system interrupts 96 to 100 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR4 is shown in Figure 11-33 and described in Table 11-33.
Figure 11-33. System Interrupt Enable Clear Register 4 (ECR4)
31
5
4
0
Reserved
DISABLE[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-33. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions
Bit
Field
31-5
Reserved
4-0
DISABLE[n]
Value
0
Description
Reserved
System interrupt 96 to 100 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 96.
11.4.32 Channel Map Registers (CMR0-CMR25)
The channel map registers (CMR0-CMR25) define the channel for each system interrupt. There is one
register per 4 system interrupts. The CMRn is shown in Figure 11-34 and described in Table 11-34.
Figure 11-34. Channel Map Registers (CMRn)
31
24
23
16
CHNL_NPLUS3
CHNL_NPLUS2
R/W-0
R/W-0
15
8
7
0
CHNL_NPLUS1
CHNL_N
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-34. Channel Map Registers (CMRn) Field Descriptions
Bit
Field
Value
Description
31-24
CHNL_NPLUS3
0-FFh
Sets the host interrupt for channel N + 3.
23-16
CHNL_NPLUS2
0-FFh
Sets the host interrupt for channel N + 2.
15-8
CHNL_NPLUS1
0-FFh
Sets the host interrupt for channel N + 1.
7-0
CHNL_N
0-FFh
Sets the channel for the system interrupt N. (N ranges from 0 to 100).
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11.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1)
The host interrupt prioritized index register 1 (HIPIR1) shows the highest priority current pending interrupt
for the FIQ interrupt. The HIPIR1 is shown in Figure 11-35 and described in Table 11-35.
Figure 11-35. Host Interrupt Prioritized Index Register 1 (HIPIR1)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending.
Reserved
Interrupt number of the highest priority pending interrupt for FIQ host interrupt.
11.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2)
The host interrupt prioritized index register 2 (HIPIR2) shows the highest priority current pending interrupt
for the IRQ interrupt. The HIPIR2 is shown in Figure 11-36 and described in Table 11-36.
Figure 11-36. Host Interrupt Prioritized Index Register 2 (HIPIR2)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending.
Reserved
Interrupt number of the highest priority pending interrupt for IRQ host interrupt.
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11.4.35 Host Interrupt Nesting Level Register 1 (HINLR1)
The host interrupt nesting level register 1 (HINLR1) displays and controls the nesting level for FIQ host
interrupt. The nesting level controls which channel and lower priority channels are nested. The HINLR1 is
shown in Figure 11-37 and described in Table 11-37.
Figure 11-37. Host Interrupt Nesting Level Register 1 (HINLR1)
31
30
16
OVERRIDE
Reserved
W-0
R-0
15
9
8
0
Reserved
NEST_LVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 11-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions
Bit
Field
31
OVERRIDE
Value
30-9
Reserved
8-0
NEST_LVL
0-1
0
0-1FFh
Description
Reads return 0. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.
Reserved
Reads return the current nesting level for the FIQ host interrupt. Writes set the nesting level for the
FIQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and
then the write data is used.
11.4.36 Host Interrupt Nesting Level Register 2 (HINLR2)
The host interrupt nesting level register 2 (HINLR2) displays and controls the nesting level for IRQ host
interrupt. The nesting level controls which channel and lower priority channels are nested. The HINLR2 is
shown in Figure 11-38 and described in Table 11-38.
Figure 11-38. Host Interrupt Nesting Level Register 2 (HINLR2)
31
30
16
OVERRIDE
Reserved
W-0
R-0
15
9
8
0
Reserved
NEST_LVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 11-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions
Bit
Field
31
OVERRIDE
30-9
Reserved
8-0
NEST_LVL
272
Value
0-1
0
0-1FFh
ARM Interrupt Controller (AINTC)
Description
Reads return 0. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.
Reserved
Reads return the current nesting level for the IRQ host interrupt. Writes set the nesting level for the
IRQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and
then the write data is used.
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11.4.37 Host Interrupt Enable Register (HIER)
The host interrupt enable register (HIER) enables or disables individual host interrupts (FIQ and IRQ).
These work separately from the global enables. There is one bit per host interrupt. These bits are updated
when writing to the host interrupt enable indexed set register (HIEISR) and the host interrupt disable
indexed clear register (HIDISR). The HIER is shown in Figure 11-39 and described in Table 11-39.
Figure 11-39. Host Interrupt Enable Register (HIER)
31
16
Reserved
R-0
15
1
0
Reserved
2
IRQ
FIQ
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-39. Host Interrupt Enable Register (HIER) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
IRQ
Description
Reserved
Enable of IRQ
0
IRQ is disabled.
1
IRQ is enabled.
FIQ
Enable of FIQ
0
FIQ is disabled.
1
FIQ is enabled.
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11.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1)
The host interrupt prioritized vector register 1 (HIPVR1) shows the interrupt vector address of the highest
priority interrupt pending for FIQ host interrupt. The HIPVR1 is shown in Figure 11-40 and described in
Table 11-40.
Figure 11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions
Bit
Field
Value
31-0
ADDR
0-FFFF FFFFh
Description
The currently highest priority interrupt vector address across for the FIQ host interrupt.
11.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2)
The host interrupt prioritized vector register 2 (HIPVR2) shows the interrupt vector address of the highest
priority interrupt pending for IRQ host interrupt. The HIPVR2 is shown in Figure 11-41 and described in
Table 11-41.
Figure 11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions
Bit
Field
Value
31-0
ADDR
0-FFFF FFFFh
274
Description
The currently highest priority interrupt vector address across for the IRQ host interrupt.
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Chapter 12
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Boot Considerations
Topic
12.1
...........................................................................................................................
Page
Introduction ..................................................................................................... 276
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12.1 Introduction
This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ARM ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• I2C0 boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI0/SPI1 boot
– Serial Flash (Master Mode)
– Serial EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0/1/2 boot
– External Host
• MMC/SD0 boot
See Using the AM18xx Bootloader Application Report (SPRABA5) for more details on the ROM Boot
Loader, a list of boot pins used, and the complete list of supported boot modes.
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Chapter 13
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DDR2/mDDR Memory Controller
This chapter describes the DDR2/mobile DDR (mDDR) memory controller.
Topic
13.1
13.2
13.3
13.4
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Supported Use Cases .......................................................................................
Registers .........................................................................................................
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280
308
313
277
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13.1 Introduction
13.1.1 Purpose of the Peripheral
The DDR2/mDDR memory controller is used to interface with JESD79D-2 standard compliant DDR2
SDRAM devices and JESD209 standard mobile DDR (mDDR) SDRAM devices. Memories types such as
DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The
DDR2/mDDR memory is the major memory location for program and data storage.
13.1.2 Features
The DDR2/mDDR memory controller supports the following features:
• JESD79D-2 standard compliant DDR2 SDRAM
• JESD209 standard compliant mobile DDR (mDDR)
• Data bus width of 16 bits
• CAS latencies:
– DDR2: 2, 3, 4, and 5
– mDDR: 2 and 3
• Internal banks:
– DDR2: 1, 2, 4, and 8
– mDDR: 1, 2, and 4
• Burst length: 8
• Burst type: sequential
• 1 CS signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM auto-initialization
• Self-refresh mode
• Partial array self-refresh (for mDDR)
• Power-down mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little-endian mode
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13.1.3 Functional Block Diagram
The DDR2/mDDR memory controller is the main interface to external DDR2/mDDR memory. Figure 13-1
displays the general data paths to on-chip peripherals and external DDR2/mDDR SDRAM.
Master peripherals, EDMA, and the CPU can access the DDR2/mDDR memory controller through the
switched central resource (SCR).
Figure 13-1. Data Paths to DDR2/mDDR Memory Controller
CPU
Master
peripherals
SCR
BUS
DDR2/mDDR
memory
controller
BUS
External
DDR2/mDDR SDRAM
EDMA
13.1.4 Supported Use Case Statement
The DDR2/mDDR memory controller supports JESD79D-2 DDR2 SDRAM memories and the JESD209
mobile DDR (mDDR) SDRAM memories utilizing 16 bits of the DDR2/mDDR memory controller data bus.
See Section 13.3 for more details.
13.1.5 Industry Standard(s) Compliance Statement
The DDR2/mDDR memory controller is compliant with the JESD79D-2 DDR2 SDRAM standard and the
JESD209 mobile DDR (mDDR) standard with the following exception:
• On-Die Termination (ODT). The DDR2/mDDR memory controller does not include any on-die
terminating resistors. Furthermore, the on-die terminating resistors of the DDR2/mDDR SDRAM device
must be disabled by tying the ODT input pin of the DDR2/mDDR SDRAM to ground.
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13.2 Architecture
This section describes the architecture of the DDR2/mDDR memory controller as well as how it is
structured and how it works within the context of the system-on-a-chip. The DDR2/mDDR memory
controller can gluelessly interface to most standard DDR2/mDDR SDRAM devices and supports such
features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through
programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections include details on how to interface and properly configure the DDR2/mDDR
memory controller to perform read and write operations to externally-connected DDR2/mDDR SDRAM
devices. Also, Section 13.3 provides a detailed example of interfacing the DDR2/mDDR memory controller
to a common DDR2/mDDR SDRAM device.
13.2.1 Clock Control
The DDR2/mDDR memory controller receives two input clocks from internal clock sources, VCLK and
2X_CLK (Figure 13-2). VCLK is a divided-down version of the PLL0 clock. 2X_CLK is the PLL1 clock.
2X_CLK should be configured to clock at the frequency of the desired data rate, or stated similarly, it
should operate at twice the frequency of the desired DDR2/mDDR memory clock. DDR_CLK and
DDR_CLK are the two output clocks of the DDR2/mDDR memory controller providing the interface clock
to the DDR2/mDDR SDRAM memory. These two clocks operate at a frequency of 2X_CLK/2.
13.2.1.1 Clock Source
VCLK and 2X_CLK are sourced from two independent PLLs (Figure 13-2). VCLK is sourced from PLL
controller 0 (PLLC0) and 2X_CLK is sourced from PLL controller 1 (PLLC1).
VCLK is clocked at a fixed divider ratio of PLL0. This divider is fixed at 2, meaning VCLK is clocked at a
frequency of PLL0/2.
The clock from PLLC1 is not divided before reaching 2X_CLK. PLLC1 should be configured to supply
2X_CLK at the desired frequency. For example, if a 138-MHz DDR2/mDDR interface clock (DDR_CLK) is
desired, then PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK.
Figure 13-2. DDR2/mDDR Memory Controller Clock Block Diagram
DDR_CLK
DDR_CLK
DDR2
memory
controller
VCLK
2X_CLK
/1
PLLC1
/2
PLLC0
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13.2.1.2 Clock Configuration
The frequency of 2X_CLK is configured by selecting the appropriate PLL multiplier. The PLL multiplier is
selected by programming registers within PLLC1. The PLLC1 divider ration is fixed at 1. For information
on programming the PLL controllers, see the Phase-Locked Loop Controller (PLLC) chapter. For
information on supported clock frequencies, see the Device Clocking chapter and your device-specific
data manual.
NOTE: PLLC1 should be configured and a stable clock present on 2X_CLK before releasing the
DDR2/mDDR memory controller from reset.
13.2.1.3 DDR2/mDDR Memory Controller Internal Clock Domains
There are two clock domains within the DDR2/mDDR memory controller. The two clock domains are
driven by VCLK and a divided-down by 2 version of 2X_CLK called MCLK. The command FIFO, write
FIFO, and read FIFO described in Section 13.2.6 are all on the VCLK domain. From this, VCLK drives the
interface to the peripheral bus.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
To conserve power within the DDR2/mDDR memory controller, VCLK, MCLK, and 2X_CLK may be
stopped. See Section 13.2.16 for proper clock stop procedures.
13.2.2 Signal Descriptions
The DDR2/mDDR memory controller signals are shown in Figure 13-3 and described in DDR2/mDDR
Memory Controller Signal Descriptions. The following features are included:
•
•
•
•
•
The maximum data bus is 16-bits wide.
The address bus is 14-bits wide with an additional three bank address pins.
Two differential output clocks driven by internal clock sources.
Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.
One chip select signal and one clock enable signal.
Figure 13-3. DDR2/mDDR Memory Controller Signals
DDR_CLK
DDR_CLK
DDR_CKE
DDR2
memory
controller
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_BA[2:0]
DDR_A[13:0]
DDR_D[15:0]
DDR_DQGATE0
DDR_DQGATE1
DDR_VREF
50 Ω
DDR_ZP
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DDR2/mDDR Memory Controller Signal Descriptions
(1)
Pin
Type
DDR_CLK,
DDR_CLK
O/Z
Clock: Differential clock outputs.
DDR_CKE
O/Z
Clock enable: Active high.
DDR_CS
O/Z
Chip select: Active low.
DDR_WE
O/Z
Write enable strobe: Active low, command output.
DDR_RAS
O/Z
Row address strobe: Active low, command output.
DDR_CAS
O/Z
Column address strobe: Active low, command output.
DDR_DQM[1:0]
O/Z
Data mask: Active high, output mask signal for write data.
DDR_DQS[1:0]
I/O/Z
Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
DDR_BA[2:0]
O/Z
Bank select: Output, defining which bank a given command is applied.
DDR_A[13:0]
O/Z
Address: Address bus.
DDR_D[15:0]
I/O/Z
Data: Bi-directional data bus. Input for read data, output for write data.
DDR_DQGATE0
O/Z
Strobe Enable: Active high.
DDR_DQGATE1
I/O/Z
Strobe Enable Delay: Loopback signal for timing adjustment (DQS gating). Route from
DDR_DQGATE0 to DDR device and back to DDR_DQGATE1 with same constraints as used for
DDR clock and data.
DDR_ZP
I/O/Z
Output drive strength reference: Reference output for drive strength calibration of N and P
channel outputs. Tie to ground via 50 ohm .5% tolerance 1/16th watt resistor (49.9 ohm .5%
tolerance is acceptable).
DDR_VREF
pwr
Voltage reference input: Voltage reference input for the SSTL_18 I/O buffers. Note even in the
case of mDDR an external resistor divider connected to this pin is necessary.
(1)
Description
Legend: I = input, O = Output, Z = high impedance, pwr = power
13.2.3 Protocol Description(s)
The DDR2/mDDR memory controller supports the DDR2/mDDR SDRAM commands listed in Table 13-1.
Table 13-2 shows the signal truth table for the DDR2/mDDR SDRAM commands.
Table 13-1. DDR2/mDDR SDRAM Commands
282
Command
Function
ACTV
Activates the selected bank and row.
DCAB
Precharge all command. Deactivates (precharges) all banks.
DEAC
Precharge single command. Deactivates (precharges) a single bank.
DESEL
Device Deselect.
EMRS
Extended Mode Register set. Allows altering the contents of the mode register.
MRS
Mode register set. Allows altering the contents of the mode register.
NOP
No operation.
Power Down
Power-down mode.
READ
Inputs the starting column address and begins the read operation.
READ with
autoprecharge
Inputs the starting column address and begins the read operation. The read operation is followed by a
precharge.
REFR
Autorefresh cycle.
SLFREFR
Self-refresh mode.
WRT
Inputs the starting column address and begins the write operation.
WRT with
autoprecharge
Inputs the starting column address and begins the write operation. The write operation is followed by a
precharge.
DDR2/mDDR Memory Controller
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Table 13-2. Truth Table for DDR2/mDDR SDRAM Commands
DDR2/mDDR
SDRAM:
DDR2/mDDR
memory
controller:
CKE
CS
RAS
CAS
WE
BA[2:0]
A[13:11, 9:0]
A10
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_CKE
Previous
Cycles
Current
Cycle
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA[2:0]
ACTV
H
H
L
L
H
H
Bank
DCAB
H
H
L
L
H
L
X
X
DEAC
H
H
L
L
H
L
Bank
X
MRS
H
H
L
L
L
L
BA
EMRS
H
H
L
L
L
L
BA
READ
H
H
L
H
L
H
BA
Column Address
L
READ with
precharge
H
H
L
H
L
H
BA
Column Address
H
WRT
H
H
L
H
L
L
BA
Column Address
L
WRT with
precharge
H
H
L
H
L
L
BA
Column Address
H
REFR
H
H
L
L
L
H
X
X
X
SLFREFR
entry
H
L
L
L
L
H
X
X
X
SLFREFR
exit
L
H
H
X
X
X
X
X
X
L
H
H
H
X
X
X
NOP
H
X
L
H
H
H
X
X
X
DESEL
H
X
H
X
X
X
X
X
X
Power Down
entry
H
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
Power Down
exit
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
H
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Row Address
H
L
OP Code
OP Code
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13.2.3.1 Refresh Mode
The DDR2/mDDR memory controller issues refresh commands to the DDR2/mDDR SDRAM memory
(Figure 13-4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE
spaces and banks selected. Following the DCAB command, the DDR2/mDDR memory controller begins
performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register
(SDRCR). Page information is always invalid before and after a REFR command; thus, a refresh cycle
always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands
may not be disabled within the DDR2/mDDR memory controller. See Section 13.2.7 for more details on
REFR command scheduling.
Figure 13-4. Refresh Command
DDR_CLK
DDR_CLK
RFR
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
DDR_BA[2:0]
DDR_DQM[1:0]
284
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13.2.3.2 Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2/mDDR memory
controller or following the initialization sequence. DDR2/mDDR SDRAMs also require this cycle prior to a
refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command,
DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 13-5 shows the timing diagram for
a DCAB command.
Figure 13-5. DCAB Command
DCAB
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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The DEAC command closes a single bank of memory specified by the bank select signals. Figure 13-6
shows the timings diagram for a DEAC command.
Figure 13-6. DEAC Command
DEAC
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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13.2.3.3 Activation (ACTV)
The DDR2/mDDR memory controller automatically issues the activate (ACTV) command before a read or
write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses
(reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of
DDR_A[13:0] selects the row. When the DDR2/mDDR memory controller issues an ACTV command, a
delay of tRCD is incurred before a read or write command is issued. Figure 13-7 shows an example of an
ACTV command. Reads or writes to the currently active row and bank of memory can achieve much
higher throughput than reads or writes to random areas because every time a new row is accessed, the
ACTV command must be issued and a delay of tRCD incurred.
Figure 13-7. ACTV Command
ACTV
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
ROW
DDR_BA[2:0]
BANK
DDR_DQM[1:0]
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13.2.3.4 READ Command
Figure 13-8 shows the DDR2/mDDR memory controller performing a read burst from DDR2/mDDR
SDRAM. The READ command initiates a burst read operation to an active row. During the READ
command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on
DDR_A[13:0], and the bank address is driven on DDR_BA[2:0].
The DDR2/mDDR memory controller uses a burst length of 8, and has a programmable CAS latency of 2,
3, 4, or 5. The CAS latency is three cycles in Figure 13-8. Read latency is equal to CAS latency plus
additive latency. The DDR2/mDDR memory controller always configures the memory to have an additive
latency of 0, so read latency equals CAS latency. Since the default burst size is 8, the DDR2/mDDR
memory controller returns 8 pieces of data for every read command. If additional accesses are not
pending to the DDR2/mDDR memory controller, the read burst completes and the unneeded data is
disregarded. If additional accesses are pending, depending on the scheduling result, the DDR2/mDDR
memory controller can terminate the read burst and start a new read burst. Furthermore, the DDR2/mDDR
memory controller does not issue a DAB/DEAC command until page information becomes invalid.
Figure 13-8. DDR2/mDDR READ Command
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
CAS Latency
DDR_D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
288
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13.2.3.5 Write (WRT) Command
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the
WRT command, a write latency is incurred. For DDR2, write latency is equal to CAS latency minus 1
cycles. For mDDR, write latency is equal to 1 cycle, always. All writes have a burst length of 8. The use of
the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 13-9 shows the timing for a
DDR2 write on the DDR2/mDDR memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pending
commands, the DDR2/mDDR memory controller can:
• Mask out the additional data using DDR_DQM outputs
• Terminate the write burst and start a new write burst
The DDR2/mDDR memory controller does not perform the DEAC command until page information
becomes invalid.
Figure 13-9. DDR2/mDDR WRT Command
DDR_CLK
DDR_CLK
Sample
Write Latency
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
DDR_D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
NOTE: This diagrams shows write latency for DDR2. For mDDR, write latency is always equal to 1 cycle.
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13.2.3.6 Mode Register Set (MRS and EMRS)
DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on DDR2/mDDR device), single-ended strobe, differential strobe etc.
The DDR2/mDDR memory controller programs the mode and extended mode registers of the
DDR2/mDDR memory by issuing MRS and EMRS commands. When the MRS or EMRS command is
executed, the value on DDR_BA[2:0] selects the mode register to be written and the data on DDR_A[13:0]
is loaded into the register. Figure 13-10 shows the timing for an MRS and EMRS command.
The DDR2/mDDR memory controller only issues MRS and EMRS commands during the DDR2/mDDR
memory controller initialization sequence. See Section 13.2.13 for more information.
Figure 13-10. DDR2/mDDR MRS and EMRS Command
MRS/EMRS
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
13.2.4 Memory Width and Byte Alignment
The DDR2/mDDR memory controller supports memory widths of 16 bits. Table 13-3 summarizes the
addressable memory ranges on the DDR2/mDDR memory controller. Only little-endian format is
supported. Figure 13-11 shows the byte lanes used on the DDR2/mDDR memory controller. The external
memory is always right aligned on the data bus.
Table 13-3. Addressable Memory Ranges
Memory Width
Maximum addressable bytes per CS space
Description
×16
256 Mbytes
Halfword address
Figure 13-11. Byte Alignment
DDR2 memory controller data bus
DDR_D[15:8]
DDR_D[7:0]
16-bit memory device
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13.2.5 Address Mapping
The memory controller views the DDR2/mDDR SDRAM device as one continuous block of memory. The
memory controller receives memory access requests with a 32-bit logical address, and it uses the logical
address to generate a row, column, and bank address for accessing the DDR2/mDDR SDRAM device.
The memory controller supports two address mapping schemes: normal address mapping and special
address mapping. Special address mapping is typically used only with mDDR devices using partial array
self-refresh.
When the internal bank position (IBANKPOS) bit in the SDRAM configuration register (SDCR) is cleared,
the memory controller operates with normal address mapping. In this case, the number of column and
bank address bits is determined by the IBANK and PAGESIZE fields in SDCR. The number of row
address bits is determined by the number of valid address pins for the device and does not need to be set
in a register.
When IBANKPOS is set to 1, the memory controller operates with special address mapping. In this case,
the number of column, row, and bank address bits is determined by the PAGESIZE, ROWSIZE, and
IBANK fields. The ROWSIZE field is in the SDRAM configuration register 2 (SDCR2). See Table 13-4 for a
descriptions of these bit fields.
Table 13-4. Configuration Register Fields for Address Mapping
Bit Field
Bit Value
IBANK
Bit Description
Defines the number of internal banks in the external DDR2/mDDR memory.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
PAGESIZE
Defines the page size of each page in the external DDR2/mDDR memory.
0
256 words (requires 8 column address bits)
1h
512 words (requires 9 column address bits)
2h
1024 words (requires 10 column address bits)
3h
2048 words (requires 11 column address bits)
ROWSIZE
Defines the row size of each row in the external DDR2/mDDR memory
0
512 (requires 9 row address bits)
1h
1024 (requires 10 row address bits)
2h
2048 (requires 11 row address bits)
3h
4096 (requires 12 row address bits)
4h
8192 (requires 13 row address bits)
5h
16384 (requires 14 row address bits)
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13.2.5.1 Normal Address Mapping (IBANKPOS = 0)
As stated in Table 13-4, the IBANK and PAGESIZE fields of SDCR control the mapping of the logical,
source address of the DDR2/mDDR memory controller to the DDR2/mDDR SDRAM row, column, and
bank address bits. The DDR2/mDDR memory controller logical address always contains up to 14 row
address bits, whereas the number of column and bank bits are determined by the IBANK and PAGESIZE
fields. Table 13-5 show how the logical address bits map to the DDR2/mDDR SDRAM row, column, and
bank bits for combinations of IBANK and PAGESIZE values. The same DDR2/mDDR memory controller
pins provide the row and column address to the DDR2/mDDR SDRAM, thus the DDR2/mDDR memory
controller appropriately shifts the address during row and column address selection.
Logical Address-to-DDR2/mDDR SDRAM Address Map shows how this address-mapping scheme
organizes the DDR2/mDDR SDRAM rows, columns, and banks into the device memory-map. Note that
during a linear access, the DDR2/mDDR memory controller increments the column address as the logical
address increments. When the DDR2/mDDR memory controller reaches a page/row boundary, it moves
onto the same page/row in the next bank. This movement continues until the same page has been
accessed in all banks. To the DDR2/mDDR SDRAM, this process looks as shown in Figure 13-12.
By traversing across banks while remaining on the same row/page, the DDR2/mDDR memory controller
maximizes the number of activated banks for a linear access. This results in the maximum number of
open pages when performing a linear access being equal to the number of banks. Note that the
DDR2/mDDR memory controller never opens more than one page per bank.
Ending the current access is not a condition that forces the active DDR2/mDDR SDRAM row to be closed.
The DDR2/mDDR memory controller leaves the active row open until it becomes necessary to close it.
This decreases the deactivate-reactivate overhead.
Table 13-5. Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM
SDCR Bit
292
Logical Address
IBANK
PAGESIZE
31
0
0
-
1
0
-
2h
0
-
3h
0
-
0
1
-
1
1
-
2h
1
-
3h
1
-
0
2h
-
1
2h
-
2h
2h
-
3h
2h
-
0
3h
-
1
3h
-
2h
3h
-
3h
3h
-
30
29
DDR2/mDDR Memory Controller
28
27
26
25
24
23
22
21:15
14
13
12
11
10
9
nrb=14
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
0
ncb=8
ncb=8
nbb=3
ncb=8
nrb=14
ncb=9
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=9
ncb=9
nbb=3
ncb=9
nrb=14
ncb=10
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=10
ncb=10
nbb=3
ncb=10
nrb=14
ncb=11
nrb=14
nbb=1
nrb=14
nrb=14
8:1
ncb=8
nbb=2
nbb=3
ncb=11
ncb=11
ncb=11
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Logical Address-to-DDR2/mDDR SDRAM Address Map
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 0
Row 1, bank 1
Row 1, bank 2
Row 1, bank P
Row N, bank 0
Row N, bank 1
Row N, bank 2
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
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Logical Address-to-DDR2/mDDR SDRAM Address Map (continued)
Figure 13-12. DDR2/mDDR SDRAM Column, Row, and Bank Access
Bank 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Bank 1
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Bank 2
Row 2
Row 0
Row 1
Bank P
Row 2
Row 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Row 2
Row N
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
13.2.5.2 Special Address Mapping (IBANKPOS = 1)
When the internal bank position (IBANKPOS) bit is set to 1, the PAGESIZE, ROWSIZE, and IBANK fields
control the mapping of the logical source address of the memory controller to the column, row, and bank
address bits of the SDRAM device. Table 13-6 shows which source address bits map to the SDRAM
column, row, and bank address bits for all combinations of PAGESIZE, ROWSIZE, and IBANK.
When IBANKPOS is set to 1, the effect of the address-mapping scheme is that as the source address
increments across an SDRAM page boundary, the memory controller proceeds to the next page in the
same bank. This movement along the same bank continues until all the pages have been accessed in the
same bank. The memory controller then proceeds to the next bank in the device. This sequence is shown
in Figure 13-13 and Figure 13-14.
Since, in this address mapping scheme, the memory controller can keep only one bank open, this scheme
is lower in performance than the case when IBANKPOS is cleared to 0. Therefore, this case is only
recommended to be used with Partial Array Self-refresh for mDDR SDRAM where performance may be
traded-off for power savings.
Table 13-6. Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1)
31
Source Address
Bank Address
Number of bank bits is defined by
IBANK nbb = 1, 2, or 3
294
DDR2/mDDR Memory Controller
1
Row Address
Column Address
Number of row bits is defined by
ROWSIZE: nrb = 9, 10, 11, 12, 13, or 14
Number of column bits is defined by
PAGESIZE: ncb = 8, 9, 10, or 11
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Figure 13-13. Address Mapping Diagram (IBANKPOS = 1)
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 1, bank 0
Row 2, bank 0
Row 3, bank 0
Row N, bank 0
Row 1, bank 1
Row 2, bank 1
Row 3, bank 1
Row N, bank 1
Row 1, bank P
Row 2, bank P
Row 3, bank P
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
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Figure 13-14. SDRAM Column, Row, Bank Access (IBANKPOS = 1)
Bank 0
C C C
o o o
l l l
0 1 2 3
Row 0
Row 1
Row 2
C
o
l
M
Bank 1
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Row 1
Row 2
Bank 2
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Bank P
Row 0
Row 1
Row N
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 2
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
13.2.6 DDR2/mDDR Memory Controller Interface
To move data efficiently from on-chip resources to external DDR2/mDDR SDRAM memory, the
DDR2/mDDR memory controller makes use of a command FIFO, a write FIFO, a read FIFO, and
command and data schedulers. Table 13-7 describes the purpose of each FIFO.
Figure 13-15 shows the block diagram of the DDR2/mDDR memory controller FIFOs. Commands, write
data, and read data arrive at the DDR2/mDDR memory controller parallel to each other. The same
peripheral bus is used to write and read data from external memory as well as internal memory-mapped
registers.
Table 13-7. DDR2/mDDR Memory Controller FIFO Description
296
FIFO
Description
Depth (64-bit doublewords)
Command
Stores all commands coming from on-chip requestors
7
Write
Stores write data coming from on-chip requestors to memory
11
Read
Stores read data coming from memory to on-chip requestors
17
DDR2/mDDR Memory Controller
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Figure 13-15. DDR2/mDDR Memory Controller FIFO Block Diagram
Command FIFO
Command/Data
Scheduler
Command
to Memory
Write FIFO
Write Data
to Memory
Read FIFO
Read Data
from
Memory
Registers
Command
Data
13.2.6.1 Command Ordering and Scheduling, Advanced Concept
The DDR2/mDDR memory controller performs command re-ordering and scheduling in an attempt to
achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data,
address, and command buses while hiding the overhead of opening and closing DDR2/mDDR SDRAM
rows. Command re-ordering takes place within the command FIFO.
Typically, a given master issues commands on a single priority. EDMA transfer controller read and write
ports are different masters. The DDR2/mDDR memory controller first reorders commands from each
master based on the following rules:
• Selects the oldest command (first command in the queue)
• Selects a read before a write if:
– The read is to a different block address (2048 bytes) than the write
– The read has greater or equal priority
The second bullet above may be viewed as an exception to the first bullet. This means that for an
individual master, all of its commands will complete from oldest to newest, with the exception that a read
may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master
may have one command ready for execution.
Next, the DDR2/mDDR memory controller examines each of the commands selected by the individual
masters and performs the following reordering:
• Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes
to rows already open.
• Selects the highest priority command from pending reads and writes to open rows. If multiple
commands have the highest priority, then the DDR2/mDDR memory controller selects the oldest
command.
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The DDR2/mDDR memory controller may now have a final read and write command. If the Read FIFO is
not full, then the read command will be performed before the write command, otherwise the write
command will be performed first.
Besides commands received from on-chip resources, the DDR2/mDDR memory controller also issues
refresh commands. The DDR2/mDDR memory controller attempts to delay refresh commands as long as
possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2/mDDR
memory controller issues read, write, and refresh commands to DDR2/mDDR SDRAM memory, it adheres
to the following rules:
1. Refresh request resulting from the Refresh Must level of urgency being reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency being reached
6. Request to enter self-refresh mode
The following results from the above scheduling algorithm:
• All writes from a single master will complete in order
• All reads from a single master will complete in order
• From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
13.2.6.2 Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2/mDDR memory controller. Command
starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2/mDDR SDRAM commands to a row in an open bank can block
commands to the closed row in the same bank.
To avoid these conditions, the DDR2/mDDR memory controller can momentarily raises the priority of the
oldest command in the command FIFO after a set number of transfers have been made. The
PR_OLD_COUNT bit in the peripheral bus burst priority register (PBBPR) sets the number of the transfers
that must be made before the DDR2/mDDR memory controller will raise the priority of the oldest
command.
13.2.6.3 Possible Race Condition
A race condition may exist when certain masters write data to the DDR2/mDDR memory controller. For
example, if master A passes a software message via a buffer in DDR2/mDDR memory and does not wait
for indication that the write completes, when master B attempts to read the software message it may read
stale data and therefore receive an incorrect message. In order to confirm that a write from master A has
landed before a read from master B is performed, master A must wait for the write completion status from
the DDR2/mDDR memory controller before indicating to master B that the data is ready to be read. If
master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2/mDDR memory controller SDRAM status register.
3. Perform a dummy read to the DDR2/mDDR memory controller SDRAM status register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The EDMA peripheral does not need to implement the above workaround. The above workaround is
required for all other peripherals. See your device-specific data manual for more information.
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13.2.7 Refresh Scheduling
The DDR2/mDDR memory controller issues autorefresh (REFR) commands to DDR2/mDDR SDRAM
devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR).
A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until
it reaches zero. Once the interval counter reaches zero, it reloads with the value of the RR bit. Each time
the interval counter expires, a refresh backlog counter increments by 1. Conversely, each time the
DDR2/mDDR memory controller performs a REFR command, the backlog counter decrements by 1. This
means the refresh backlog counter records the number of REFR commands the DDR2/mDDR memory
controller currently has outstanding.
The DDR2/mDDR memory controller issues REFR commands based on the level of urgency. The level of
urgency is defined in Table 13-8. Whenever the refresh must level of urgency is reached, the
DDR2/mDDR memory controller issues a REFR command before servicing any new memory access
requests. Following a REFR command, the DDR2/mDDR memory controller waits T_RFC cycles, defined
in the SDRAM timing register 1 (SDTIMR1), before rechecking the refresh urgency level.
In addition to the refresh counter previously mentioned, a separate backlog counter ensures the interval
between two REFR commands does not exceed 8× the refresh rate. This backlog counter increments by 1
each time the interval counter expires and resets to zero when the DDR2/mDDR memory controller issues
a REFR command. When this backlog counter is greater than 7, the DDR2/mDDR memory controller
issues four REFR commands before servicing any new memory requests.
The refresh counters do not operate when the DDR2/mDDR memory is in self-refresh mode.
Table 13-8. Refresh Urgency Levels
Urgency Level
Description
Refresh May
Backlog count is greater than 0. Indicates there is a backlog of REFR commands, when the DDR2/mDDR
memory controller is not busy it will issue the REFR command.
Refresh Release
Backlog count is greater than 3. Indicates the level at which enough REFR commands have been performed
and the DDR2/mDDR memory controller may service new memory access requests.
Refresh Need
Backlog count is greater than 7. Indicates the DDR2/mDDR memory controller should raise the priority level
of a REFR command above servicing a new memory access.
Refresh Must
Backlog count is greater than 11. Indicates the level at which the DDR2/mDDR memory controller should
perform a REFR command before servicing new memory access requests.
13.2.8 Self-Refresh Mode
Clearing the self refresh/low power (SR_PD) bit to 0 and then setting the low power mode enable
(LPMODEN) bit to 1 in the SDRAM refresh control register (SDRCR) , forces the DDR2/mDDR memory
controller to place the external DDR2/mDDR SDRAM in a low-power mode (self refresh), in which the
DDR2/mDDR SDRAM maintains valid data while consuming a minimal amount of power. When the
LPMODEN bit is set to 1, the DDR2/mDDR memory controller continues normal operation until all
outstanding memory access requests have been serviced and the refresh backlog has been cleared. At
this point, all open pages of DDR2/mDDR SDRAM are closed and a self-refresh (SLFRFR) command (an
autorefresh command with self refresh/low power) is issued.
The memory controller exits the self-refresh state when a memory access is received, when the
LPMODEN bit in SDRCR is cleared to 0, or when the SR_PD bit in SDRCR changed to 1. While in the
self-refresh state, if a request for a memory access is received, the DDR2/mDDR memory controller
services the memory access request, returning to the self-refresh state upon completion. The
DDR2/mDDR memory controller will not wake up from the self-refresh state (whether from a memory
access request, from clearing the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles
have expired since the self-refresh command was issued. The value of T_CKE is defined in the SDRAM
timing register 2 (SDTIMR2).
In the case of DDR2, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR + 1 clock cycles before issuing non-read/write
commands and T_SXRD + 1 clock cycles before issuing read or write commands. The SDRAM timing
register 2 (SDTIMR2) programs the values of T_SXNR and T_SXRD.
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In the case of mDDR, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR+1 clock cycles and then execute auto-refresh
command before issuing any other commands. The SDRAM timing register 2 (SDTIMR2) programs the
value of T_SXNR.
Once in self-refresh mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK) may be
gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See
Section 13.2.16 for more information describing the proper procedure to follow when shutting down
DDR2/mDDR memory controller input clocks.
See Section 13.2.16.1 for a description of the self-refresh programming sequence.
13.2.9 Partial Array Self Refresh for Mobile DDR
For additional power savings during self-refresh, the partial array self-refresh (PASR) feature of the mDDR
allows you to select the amount of memory that will be refreshed during self-refresh. Use the partial array
self-refresh (PASR) bit field in the SDRAM configuration register 2 (SDCR2) to select the amount of
memory to refresh during self-refresh. As shown in Table 13-9 you may select either 4, 2, 1, 1/2, or 1/4
bank(s). The PASR bits are loaded into the extended mode register of the mDDR device, during
autoinitialization (see Section 13.2.13).
The mDDR performs bank interleaving when the internal bank position (IBANKPOS) bit in SDRAM
configuration register (SDCR) is cleared to 0. Since the SDRAM banks are only partially refreshed during
partial array self-refresh, it is recommended that you set IBANKPOS to 1 to avoid bank interleaving. When
IBANKPOS is cleared to 0, it is the responsibility of software to move critical data into the banks that are
to be refreshed during partial array self-refresh. Refer to Section 13.2.5.2 for more information on
IBANKPOS and addressing mapping in general.
Table 13-9. Configuration Bit Field for Partial Array Self-refresh
Bit Field
Bit Value
PASR
Bit Description
Partial array self refresh.
0
Refresh banks 0, 1, 2, and 3
1h
Refresh banks 0 and 1
2h
Refresh bank 0
5h
Refresh 1/2 of bank 0
6h
Refresh 1/4 of bank 0
13.2.10 Power-Down Mode
Setting the self-refresh/low power (SR_PD) bit and the low-power mode enable (LPMODEN) bit in the
SDRAM refresh control register (SDRCR) to 1, forces the DDR2/mDDR memory controller to place the
external DDR2 SDRAM in the power-down mode. When the LPMODEN bit is asserted, the DDR2/mDDR
memory controller continues normal operation until all outstanding memory access requests have been
serviced and the refresh backlog has been cleared. At this point, all open pages of DDR2 SDRAM are
closed and a Power Down command (same as NOP command but driving DDR_CKE low on the same
cycle) is issued.
The DDR2/mDDR memory controller exits the power-down state when a memory access is received,
when a Refresh Must level is reached, when the LPMODEN bit in SDRCR is cleared to 0, or when the
SR_PD bit in SDRCR changed to 0. While in the power-down state, if a request for a memory access is
received, the DDR2/mDDR memory controller services the memory access request, returning to the
power-down state upon completion. The DDR2/mDDR memory controller will not wake-up from the powerdown state (whether from a memory access request, from reaching a Refresh Must level, from clearing
the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the powerdown command was issued. The value of T_CKE is defined in the SDRAM timing register 2 (SDTIMR2).
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After exiting from the power-down state, the DDR2/mDDR memory controller will drive DDR_CKE high
and then not immediately start executing commands. Instead, it will wait T_XP + 1 clock cycles before
issuing commands. The SDRAM timing register 2 (SDTIMR2) programs the values of T_XP.
See Section 13.2.16.1 for a description of the power-down mode programming sequence.
NOTE: Power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
13.2.11 Reset Considerations
The DDR2/mDDR memory controller has two reset signals, chip_rst_n and mod_g_rst_n. The chip_rst_n
is a module-level reset that resets both the state machine as well as the DDR2/mDDR memory controller
memory-mapped registers. The mod_g_rst_n resets the state machine only; it does not reset the
controller's registers, which allows soft reset (from PSC or WDT) to reset the module without resetting the
configuration registers and reduces the programming overhead for setting up access to the DDR2/mDDR
device. If the DDR2/mDDR memory controller is reset independently of other peripherals, the user's
software should not perform memory, as well as register accesses, while chip_rst_n or mod_g_rst_n are
asserted. If memory or register accesses are performed while the DDR2/mDDR memory controller is in
the reset state, other masters may hang. Following the rising edge of chip_rst_n or mod_g_rst_n, the
DDR2/mDDR memory controller immediately begins its initialization sequence. Command and data stored
in the DDR2/mDDR memory controller FIFOs are lost. Table 13-10 describes the different methods for
asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master controller for power
management for all of the peripherals on the device. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. Figure 13-16 shows the
DDR2/mDDR memory controller reset diagram.
Table 13-10. Reset Sources
Reset Signal
Reset Source
chip_rst_n
Hardware/device reset
mod_g_rst_n
Power and sleep controller
Figure 13-16. DDR2/mDDR Memory Controller Reset Block Diagram
Hard
Reset from
PLLC0
DDR
PSC
chip_rst_n
mod_g_rst_n
DDR2/mDDR
memory
controller
registers
State
machine
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13.2.12 VTP IO Buffer Calibration
The DDR2/mDDR memory controller is able to control the impedance of the output IO. This feature allows
the DDR2/mDDR memory controller to tune the output impedance of the IO to match that of the PCB
board. Control of the output impedance of the IO is an important feature because impedance matching
reduces reflections, creating a cleaner board design. Calibrating the output impedance of the IO will also
reduce the power consumption of the DDR2/mDDR memory controller. The calibration is performed with
respect to voltage, temperature, and process (VTP). The VTP information obtained from the calibration is
used to control the output impedance of the IO.
The impedance of the output IO is selected by the value of a reference resistor connected to pin DDR_ZP.
The DDR2/mDDR reference design requires the reference resistor to be a 50 ohm, 5.0% tolerance, 1/16th
watt resistor (49.9 ohm, 0.5% tolerance is acceptable).
The VTP IO control register (VTPIO_CTL) is written to begin the calibration process. The VTP calibration
process is described in the DDR2/mDDR initialization sequence in Section 13.2.13.1.
NOTE: VTP IO calibration must be performed following device power up and device reset. If the
DDR2/mDDR memory controller is reset via the Power and Sleep Controller (PSC) and the
VTP input clock is disabled, accesses to the DDR2/mDDR memory controller will not
complete. To re-enable accesses to the DDR2/mDDR memory controller, enable the VTP
input clock and then perform the VTP calibration sequence again.
13.2.13 Auto-Initialization Sequence
The DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on the DDR2/mDDR device), single-ended strobe, differential strobe, etc. The DDR2/mDDR memory
controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS
and EMRS commands during the initialization sequence. The SDRAMEN, MSDRAMEN, DDREN, and
DDR2EN bits in the SDRAM configuration register (SDCR) determine if the DDR2/mDDR memory
controller will perform a DDR2 or mobile DDR initialization sequence. Set these bits as follows for DDR2:
SDRAMEN = 1, MSDRAMEN = 0, DDREN = 1, DDR2EN = 1. Set these bits as follow for mDDR:
SDRAMEN = 1, MSDRAMEN = 1, DDREN = 1, DDR2EN = 0. The DDR2 initialization sequence
performed by the DDR2/mDDR memory controller is compliant with the JESD79D-2 specification and the
mDDR initialization sequence is compliant with the JESD209 specification. The DDR2/mDDR memory
controller performs an initialization sequence under the following conditions:
• Following reset (rising edge of chip_rst_n or mod_g_rst_n)
• Following a write to the DDRDRIVE, CL, IBANK, or PAGESIZE bit fields in the SDRAM configuration
register (SDCR)
During the initialization sequence, the memory controller issues MRS and EMRS commands that
configure the DDR2/mobile DDR SDRAM mode register and extended mode register 1. The register
values for DDR2 are described in Table 13-11 and Table 13-12, and the register values for mDDR are
described in Table 13-13 and Table 13-14. The extended mode registers 2 and 3 are configured with a
value of 0h. At the end of the initialization sequence, the memory controller performs an autorefresh cycle,
leaving the memory controller in an idle state with all banks deactivated.
When a reset occurs, the DDR2/mDDR memory controller immediately begins the initialization sequence.
Under this condition, commands and data stored in the DDR2/mDDR memory controller FIFOs will be lost.
However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDCR,
data and commands stored in the DDR2/mDDR memory controller FIFOs will not be lost and the
DDR2/mDDR memory controller will ensure read and write commands are completed before starting the
initialization sequence.
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Table 13-11. DDR2 SDRAM Configuration by MRS Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Power Down Exit
Fast exit
DDR_A[11:9]
t_WR
11:9
Write Recovery
Write recovery from autoprecharge. Value of 2,
3, 4, 5, or 6 is programmed based on value of
the T_WR bit in the SDRAM timing register 1
(SDTIMR1 ).
DDR_A[8]
0
8
DLL Reset
Out of reset
DDR_A[7]
0
7
Mode: Test or Normal
Normal mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2, 3, 4, or 5 is programmed based on
value of the CL bit in the SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
Table 13-12. DDR2 SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Output Buffer Enable
Output buffer enable
DDR_A[11]
0
11
RDQS Enable
RDQS disable
DDR_A[10]
1
10
DQS enable
Disables differential DQS signaling.
DDR_A[9:7]
0
9:7
OCD Calibration Program
Exit OCD calibration
DDR_A[6]
0
6
ODT Value (Rtt)
Cleared to 0 to select 75 ohms. This feature
is not supported because the DDR_ODT
signal is not pinned out.
DDR_A[5:3]
0
5:3
Additive Latency
0 cycles of additive latency
DDR_A[2]
1
2
ODT Value (Rtt)
Set to 1 to select 75 ohms. This feature is not
supported because the DDR_ODT signal is
not pinned out.
DDR_A[1]
DDRDRIVE[0]
1
Output Driver Impedance
Value of 0 or 1 is programmed based on
value of DDRDRIVE0 bit in SDRAM
configuration register (SDCR).
DDR_A[0]
0
0
DLL enable
DLL enable
Table 13-13. Mobile DDR SDRAM Configuration by MRS Command
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating mode
Normal operating mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2 or 3 is programmed based on
value of CL bit in SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
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Table 13-14. Mobile DDR SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating Mode
Normal operating mode
DDR_A[6:5]
DDRDRIVE[1:0]
6:5
Output Driver Impedance
Value of 0, 1, 2, or 3 is programmed based
on value of DDRDRIVE[1:0] bits in SDRAM
configuration register (SDCR).
DDR_A[4:3]
0
4:3
Temperature Compensated
Self Refresh
Value of 0
DDR_A[2:0]
PASR bits
2:0
Partial Array Self Refresh
Value of 0, 1, 2, 5, or 6 is programmed based
on value of PASR bits in SDRAM
configuration register 2 (SDCR2).
13.2.13.1 Initializing Following Device Power Up or Reset
Following device power up or reset, the DDR2/mDDR memory controller is held in reset with the internal
clocks to the module gated off. Before releasing the DDR2/mDDR memory controller from reset, the
clocks to the module must be turned on. Perform the following steps when turning the clocks on and
initializing the module:
1. Program PLLC1 registers to start the PLL1_SYSCLK1 (that drives 2X_CLK). For information on
programming PLLC1, see the Phase-Locked Loop Controller (PLLC) chapter.
2. Program Power and Sleep Controller (PSC) to enable the DDR2/mDDR memory controller clock.
3. Perform VTP IO calibration:
(a) Clear POWERDN bit in the VTP IO control register (VTPIO_CTL).
(b) Clear LOCK bit in VTPIO_CTL.
(c) Pulse CLKRZ bit in VTPIO_CTL:
(i) Set CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(ii) Clear CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(iii) Set CLKRZ bit.
(d) Poll READY bit in VTPIO_CTL until it changes to 1.
(e) Set LOCK bit in VTPIO_CTL. VTP is locked and dynamic calibration is disabled.
(f) Set POWERDN bit in VTPIO_CTL to save power.
4. Set IOPWRDN bit in VTPIO_CTL to allow the input receivers to save power when the PWRDNEN bit in
the DDR PHY control register 1 (DRPYC1R) is set.
5. Configure DRPYC1R. All of the following steps may be done with a single register write to DRPYC1R:
(a) Set EXT_STRBEN bit to select external DQS strobe gating.
(b) Set PWRDNEN bit to allow the input receivers to power down when they are idle.
(c) Program RL bit value to meet the memory data sheet specification.
6. Configure the DDR slew register (DDR_SLEW):
(a) For DDR2, clear DDR_PDENA and CMOSEN bits.
(b) For mDDR, set the DDR_PDENA and CMOSEN bits.
7. Set the BOOTUNLOCK bit (unlocked) in the SDRAM configuration register (SDCR).
8. Program SDCR to the desired value with BOOTUNLOCK bit cleared to 0 and TIMUNLOCK bit set to 1
(unlocked).
9. For mDDR only, program the SDRAM configuration register 2 (SDCR2) to the desired value.
10. Program the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) to the
desired values to meet the memory data sheet specification.
11. Clear TIMUNLOCK bit (locked) in SDCR.
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12. Program the SDRAM refresh control register (SDRCR). All of the following steps may be done with a
single register write to SDRCR:
(a) Set LPMODEN bit to enable self-refresh. This is necessary for the next two steps.
(b) Set MCLKSTOPEN bit to enable MCLK stopping. This is necessary for the next two steps.
(c) Clear SR_PD bit to select self-refresh. This is necessary for the next two steps.
(d) Program RR refresh rate value to meet the memory data sheet specification.
13. Program the Power and Sleep Controller (PSC) to reset (SyncReset) the DDR2/mDDR memory
controller.
14. Program the Power and Sleep Controller (PSC) to re-enable the DDR2/mDDR memory controller.
15. Clear LPMODEN and MCLKSTOPEN bits in SDRCR to disable self-refresh.
16. Configure the peripheral bus burst priority register (PBBPR) to a value lower than the default value of
FFh. A lower value reduces the likelihood of prolonged command starvation for accesses made from
different master/peripherals to mDDR/DDR2 memory. The optimal value should be determined based
on system considerations; however, a value of 20h or 30h is sufficient for typical applications.
NOTE: Some memory data sheet timing values such as those programmed into the SDRAM timing
register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) may need to be relaxed in
order to compensate for signal delays introduced by board layout.
13.2.14 Interrupt Support
The DDR2/mDDR memory controller supports two addressing modes, linear incrementing and cache line
wrap. Upon receipt of an access request for an unsupported addressing mode, the DDR2/mDDR memory
controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). The DDR2/mDDR
memory controller will then treat the request as a linear incrementing request.
This interrupt is called the line trap interrupt and is the only interrupt the DDR2/mDDR memory controller
supports. It is an active-high interrupt and is enabled by the LTMSET bit in the interrupt mask set register
(IMSR). This interrupt is mapped to the CPU and is multiplexed with RTCINT.
13.2.15 DMA Event Support
The DDR2/mDDR memory controller is a DMA slave peripheral and therefore does not generate DMA
events. Data read and write requests may be made directly by masters and by the DMA.
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13.2.16 Power Management
Power dissipation from the DDR2/mDDR memory controller may be managed by the following methods:
• Self-refresh mode (see Section 13.2.8)
• Power-down mode (see Section 13.2.10)
• Disabling the DDR PHY to reduce power
The DDR2/mDDR memory controller supports low-power modes where the DLL internal to the PHY
and the receivers at the I/O pins can be disabled. These functions are controlled through the
DDR2/mDDR memory controller. Even if the PHY is active, the receivers can be configured to disable
whenever writes are in progress and the receivers are not needed.
• Gating input clocks to the module off
Gating input clocks off to the DDR2/mDDR memory controller achieves higher power savings when
compared to the power savings of self-refresh mode and power-down mode. The input clocks are
turned off outside of the DDR2/mDDR memory controller through the use of the Power and Sleep
Controller (PSC) and the PLL controller 1 (PLLC1). Figure 13-17 shows the connections between the
DDR2/mDDR memory controller, PSC, and PLLC1. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter.
Before gating clocks off, the DDR2/mDDR memory controller must place the DDR2/mDDR SDRAM
memory in self-refresh mode. If the external memory requires a continuous clock, the DDR2/mDDR
memory controller clock provided by PLLC1 must not be turned off because this may result in data
corruption. See the following subsections for the proper procedures to follow when stopping the
DDR2/mDDR memory controller clocks. Once the clocks are stopped, to re-enable the clocks follow
the clock stop procedure in each respective subsection in reverse order.
Figure 13-17. DDR2/mDDR Memory Controller Power Sleep Controller Diagram
PLL0_SYSCLK2/2
CLKSTOP_REQ
VCLKSTOP_REQ
CLKSTOP_ACK
VCLKSTOP_ACK
DDR
PST
MODCLK
MODRST
LRST
DDR2/mDDR
memory
VCLK
controller
chip_rst_n
mod_g_rst_n
2X_CLK
PLLC1
/1
306
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13.2.16.1 DDR2/mDDR Memory Controller Clock Stop Procedure
NOTE: If a data access occurs to the DDR2/mDDR memory after completing steps 1-4, the DLL will
wake up and lock, then the MCLK will turn on and the access will be performed. Following
steps 5 and 6, in which the clocks are disabled , all DDR2/mDDR memory accesses are not
possible until the clocks are reenabled.
In power-down mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK)
may not be gated off. This is a limitation of the DDR2/mDDR controller. For this reason,
power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
To achieve maximum power savings VCLK, MCLK, 2X_CLK, DDR_CLK, and DDR_CLK should be gated
off. The procedure for clock gating is described in the following steps.
1. Allow software to complete the desired DDR transfers.
2. Change the SR_PD bit to 0 and set the LPMODEN bit to 1 in the DDR2 SDRAM refresh control
register (SDRCR) to enable self-refresh mode. The DDR2/mDDR memory controller will complete any
outstanding accesses and backlogged refresh cycles and then place the external DDR2/mDDR
memory in self-refresh mode.
3. Set the MCLKSTOPEN bit in SDRCR to 1. This enables the DDR2/mDDR memory controller to shut
off the MCLK.
4. Wait 150 CPU clock cycles to allow the MCLK to stop.
5. Program the PSC to disable the DDR2/mDDR memory controller VCLK. You must not disable VCLK in
power-down mode; use only for self-refresh mode (see notes in this section).
6. For maximum power savings, the PLL/PLLC1 should be placed in bypass and powered-down mode to
disable 2X_CLK. You must not disable 2X_CLK in power-down mode; use only for self-refresh mode
(see notes in this section). For information on programming PLLC1, see the Phase-Locked Loop
Controller (PLLC) chapter.
To
1.
2.
3.
turn clocks back on:
Place the PLL/PLLC1 in PLL mode to start 2X_CLK to the DDR2/mDDR memory controller.
Once 2X_CLK is stable, program the PSC to enable VCLK.
Set the RESET_PHY bit in the DDR PHY reset control register (DRPYRCR) to 1. This resets the
DDR2/mDDR memory controller PHY. This bit will self-clear to 0 when reset is complete.
4. Clear the MCLKSTOPEN bit in SDRCR to 0.
5. Clear the LPMODEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.
13.2.17 Emulation Considerations
The DDR2/mDDR memory controller will remain fully functional during emulation halts to allow emulation
access to external memory.
NOTE: VTP IO calibration must be performed before emulation tools attempt to access the register
or data space of the DDR2/mDDR memory controller. A bus lock-up condition will occur if the
emulation tool attempts to access the register or data space of the DDR2/mDDR memory
controller before completing VTP IO calibration. See Section 13.2.12 for information on VTP
IO calibration.
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13.3 Supported Use Cases
The DDR2/mDDR memory controller allows a high degree of programmability for shaping DDR2/mDDR
accesses. The programmability inherent to the DDR2/mDDR memory controller provides the DDR2/mDDR
memory controller with the flexibility to interface with a variety of DDR2/mDDR devices. By programming
the SDRAM configuration register (SDCR), SDRAM refresh control register (SDRCR), SDRAM timing
register 1 (SDTIMR1), and SDRAM timing register 2 (SDTIMR2), the DDR2/mDDR memory controller can
be configured to meet the data sheet specification for DDR2 SDRAM as well as mDDR memory devices.
This section presents an example describing how to interface the DDR2 memory controller to a
DDR2/mDDR-400 device. The DDR2/mDDR memory controller is assumed to be operating at 150 MHz. A
similar procedure can be followed when interfacing to a mDDR memory device.
Connecting the DDR2/mDDR Memory Controller to DDR2/mDDR Memory
Figure 13-18 shows how to connect the DDR2/mDDR memory controller to a DDR2 device. Figure 13-18
displays a 16-bit interface; you can see that all signals are point-to-point connection.
Figure 13-18. Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR2/mDDR
DDR_WE
memory
DDR_RAS
controller
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[15:0]
CK
CK
CKE
DDR2
CS
memory
WE
x16−bit
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR_ZP
50 Ω
308
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Configuring Memory-Mapped Registers to Meet DDR2 Specification
As previously stated, four memory-mapped registers must be programmed to configure the DDR2/mDDR
memory controller to meet the data sheet specification of the attached DDR2/mDDR device. The registers
are:
• SDRAM configuration register (SDCR)
• SDRAM refresh control register (SDRCR)
• SDRAM timing register 1 (SDTIMR1)
• SDRAM timing register 2 (SDTIMR2)
In addition to these registers, the DDR PHY control register (DRPYC1R) must also be programmed. The
configuration of DRPYC1R is not dependent on the DDR2 device specification but rather on the board
layout.
The following sections describe how to configure each of these registers. See Section 13.4 for more
information on the DDR2/mDDR memory controller registers.
NOTE: When interfacing the DDR2/mDDR memory controller to a mDDR device, the SDRAM
configuration register 2 (SDCR2) must be programmed in addition to the registers mentioned
above.
Configuring SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains register fields that configure the DDR2/mDDR
memory controller to match the data bus width, CAS latency, number of banks, and page size of the
attached memory. In this example, we assume the following DDR2 configuration:
• Data bus width = 16 bits
• CAS latency = 3
• Number of banks = 8
• Page size = 1024 words
Table 13-15 shows the resulting SDCR configuration. Note that the value of the TIMING_UNLOCK field is
dependent on whether or not it is desirable to unlock SDTIMR1 and SDTIMR2. The TIMING_UNLOCK bit
should only be set to 1 when the SDTIMR1 and SDTIMR2 needs to be updated.
Table 13-15. SDCR Configuration
Field
Value
Function Selection
TIMING_UNLOCK
x
Set to 1 to unlock the SDRAM timing register 1 and SDRAM timing register 2.
Cleared to 0 to lock the SDRAM timing register 1 and SDRAM timing register 2.
NM
1h
To configure the DDR2/mDDR memory controller for a 16-bit data bus width.
CL
3h
To select a CAS latency of 3.
IBANK
3h
To select 8 internal DDR2 banks.
PAGESIZE
2h
To select 1024-word page size.
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Configuring SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) configures the DDR2/mDDR memory controller to meet the
refresh requirements of the attached memory device. SDRCR also allows the DDR2/mDDR memory
controller to enter and exit self refresh and enable and disable the MCLK stopping. In this example, we
assume that the DDR2/mDDR memory controller is not is in self-refresh mode or power-down mode and
that MCLK stopping is disabled.
The RR field in SDRCR is defined as the rate at which the attached memory device is refreshed in
DDR2/mDDR cycles. The value of this field may be calculated using the following equation:
RR = DDR2/mDDR clock frequency × DDR2/mDDR memory refresh period
Table 13-16 displays the DDR2-400 refresh rate specification.
Table 13-16. DDR2 Memory Refresh Specification
Symbol
Description
Value
tREF
Average Periodic Refresh Interval
7.8 μs
Therefore, the following results assuming 150 MHz DDR2/mDDR clock frequency.
RR = 150 MHz × 7.8 μs = 1170
Therefore, RR = 1170 = 492h.
Table 13-17 shows the resulting SDRCR configuration.
Table 13-17. SDRCR Configuration
310
Field
Value
Function Selection
LPMODEN
0
DDR2/mDDR memory controller is not in power-down mode.
MCLKSTOP_EN
0
MCLK stopping is disabled.
SR_PD
0
Leave a default value.
RR
492h
Set to 492h DDR2 clock cycles to meet the DDR2/mDDR memory refresh rate requirement.
DDR2/mDDR Memory Controller
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Configuring SDRAM Timing Registers (SDTIMR1 and SDTIMR2)
The SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) configure the
DDR2/mDDR memory controller to meet the data sheet timing parameters of the attached memory device.
Each field in SDTIMR1 and SDTIMR2 corresponds to a timing parameter in the DDR2/mDDR data sheet
specification. Table 13-18 and Table 13-19 display the register field name and corresponding DDR2 data
sheet parameter name along with the data sheet value. These tables also provide a formula to calculate
the register field value and displays the resulting calculation. Each of the equations include a minus 1
because the register fields are defined in terms of DDR2/mDDR clock cycles minus 1. See Section 13.4.4
and Section 13.4.5 for more information.
Table 13-18. SDTIMR1 Configuration
Register
Field Name
DDR2 Data
Manual
Parameter
Name
Description
Data Manual
Value (nS)
Formula
(Register field must be ≥)
Register
Value
T_RFC
tRFC
Refresh cycle time
127.5
(tRFC × fDDR2/mDDR_CLK) - 1
19
T_RP
tRP
Precharge command to
refresh or activate
command
15
(tRP × fDDR2/mDDR_CLK) - 1
2
T_RCD
tRCD
Activate command to
read/write command
15
(tRCD × fDDR2/mDDR_CLK) - 1
2
T_WR
tWR
Write recovery time
15
(tWR × fDDR2/mDDR_CLK) - 1
2
T_RAS
tRAS
Active to precharge
command
40
(tRAC × fDDR2/mDDR_CLK) - 1
5
T_RC
tRC
Activate to Activate
command in the same
bank
55
(tRC × fDDR2/mDDR_CLK) - 1
8
T_RRD (1)
tRRD
Activate to Activate
command in a different
bank
10
((4 × tRRD) + (2 × tCK))/(4 × tCK) - 1
1
T_WTR
tWTR
Write to read command
delay
10
(tWTR × fDDR2/mDDR_CLK) - 1
1
(1)
The formula for the T_RRD field applies only for 8 bank DDR2/mDDR memories; when interfacing to DDR2/mDDR memories
with less than 8 banks, the T_RRD field should be calculated using the following formula: (tRRD × fDDR2/mDDR_CLK) - 1.
Table 13-19. SDTIMR2 Configuration
Register
Field Name
DDR2 Data
Manual
Parameter
Name
T_RASMAX
tRAS(MAX)
T_XP
Data Manual
Value
Formula
(Register field must be ≥)
Register
Value
Active to precharge
command
70 μs
tRAS(MAX)/DDR refresh rate- 1
8
tXP
Exit power down to a nonread command
2(tCK cycles)
If tXP > tCKE,
then T_XP = tXP- 1,
else T_XP = tCKE- 1
2
T_XSNR
tXSNR
Exit self refresh to a nonread command
137.5 nS
(tXSNR × fDDR2/mDDR_CLK) - 1
18
T_XSRD
tXSRD
Exit self refresh to a read
command
200 (tCK cycles)
tXSRD - 1
199
T_RTP
tRTP
Read to precharge
command delay
15 nS
(tRTP × fDDR2/mDDR_CLK) - 1
1
T_CKE
tCKE
CKE minimum pulse width
3 (tCK cycles)
tCKE - 1
2
Description
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Configuring DDR PHY Control Register (DRPYC1R)
The DDR PHY control register (DRPYC1R) contains a read latency (RL) field that helps the DDR2/mDDR
memory controller determine when to sample read data. The RL field should be programmed to a value
equal to the CAS latency plus the round trip board delay minus 1. The minimum RL value is CAS latency
plus 1 and the maximum RL value is CAS latency plus 2 (again, the RL field would be programmed to
these values minus 1). Table 13-20 shows the resulting DRPYC1R configuration.
When calculating round trip board delay the signals of primary concern are the differential clock signals
(DDR_CLK and DDR_CLK) and data strobe signals (DDR_DQS). For these signals, calculate the round
trip board delay from the DDR memory controller to the memory and then choose the maximum delay to
determine the RL value. In this example, we will assume the round trip board delay is one DDR_CLK
cycle; therefore, RL can be calculated as:
RL = CAS latency + round trip board delay – 1 = 4 + 1 – 1 = 4
Table 13-20. DRPYC1R Configuration
312
Field
Value
Function Selection
EXT_STRBEN
1h
Programs to select external strobe gating
RL
4h
Read latency is equal to CAS latency plus round trip board delay for data minus 1
PWRDNEN
0
Programmed to power up the DDR2/mDDR memory controller receivers
DDR2/mDDR Memory Controller
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13.4 Registers
Table 13-21 lists the memory-mapped registers for the DDR2/mDDR memory controller. Note that the
VTP IO control register (VTPIO_CTL) resides in the System Configuration Module.
Table 13-21. DDR2/mDDR Memory Controller Registers
Address Offset
(1)
Acronym
Register Description
Section
0h
REVID
Revision ID Register
4h
SDRSTAT
SDRAM Status Register
Section 13.4.1
8h
SDCR
SDRAM Configuration Register
Section 13.4.2
Revision ID Register
(REVID)
Ch
SDRCR
SDRAM Refresh Control Register
Section 13.4.3
10h
SDTIMR1
SDRAM Timing Register 1
Section 13.4.4
14h
SDTIMR2
SDRAM Timing Register 2
Section 13.4.5
1Ch
SDCR2
SDRAM Configuration Register 2
Section 13.4.6
20h
PBBPR
Peripheral Bus Burst Priority Register
Section 13.4.7
40h
PC1
Performance Counter 1 Register
Section 13.4.8
44h
PC2
Performance Counter 2 Register
Section 13.4.9
48h
PCC
Performance Counter Configuration Register
Section 13.4.10
4Ch
PCMRS
Performance Counter Master Region Select Register
Section 13.4.11
50h
PCT
Performance Counter Time Register
Performance
Counter Time
Register (PCT)
60h
DRPYRCR
DDR PHY Reset Control Register
Section 13.4.12
C0h
IRR
Interrupt Raw Register
Section 13.4.13
C4h
IMR
Interrupt Masked Register
Section 13.4.14
C8h
IMSR
Interrupt Mask Set Register
Section 13.4.15
CCh
IMCR
Interrupt Mask Clear Register
Section 13.4.16
E4h
DRPYC1R
DDR PHY Control Register 1
Section 13.4.17
01E2 C000h (1)
VTPIO_CTL
VTP IO Control Register
Section 10.5.19
01E2 C004h (1)
DDR_SLEW
DDR Slew Register
Section 10.5.20
This register resides in the register space of the System Configuration (SYSCFG) Module. It is listed in the register space of the
DDR2/mDDR controller because it is applicable to the DDR2/mDDR controller.
Revision ID Register (REVID)
The revision ID register (REVID) contains the current revision ID for the DDR2/mDDR memory controller.
The REVID is shown in Figure 13-19 and described in Table 13-22.
Figure 13-19. Revision ID Register (REVID)
31
0
REV
R-4031 1B1Fh
LEGEND: R = Read only; -n = value after reset
Table 13-22. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4031 1B1Fh
Description
Revision ID value of the DDR2/mDDR memory controller.
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13.4.1 SDRAM Status Register (SDRSTAT)
The SDRAM status register (SDRSTAT) is shown in Figure 13-20 and described in Table 13-23.
Figure 13-20. SDRAM Status Register (SDRSTAT)
31
30
29
Rsvd
DUALCLK
Reserved
16
R-0
R-1
R-0
15
3
2
1
0
Reserved
PHYRDY
Reserved
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-23. SDRAM Status Register (SDRSTAT) Field Descriptions
Bit
Field
31
Reserved
30
DUALCLK
29-3
Reserved
2
PHYRDY
1-0
314
Reserved
Value
0
Description
Reserved
Dual clock. Specifies whether the VCLK and MCLK inputs are asynchronous. This bit should always be
read as 1.
0
VCLK and MCLK are not asynchronous.
1
VCLK and MCLK are asynchronous.
0
Reserved
DDR2/mDDR memory controller DLL ready. Specifies whether the DDR2/mDDR memory controller DLL
is powered up and locked.
0
DLL is not ready, either powered down, in reset, or not locked.
1
DLL is powered up, locked, and ready for operation.
0
Reserved
DDR2/mDDR Memory Controller
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13.4.2 SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains fields that program the DDR2/mDDR memory
controller to meet the specification of the attached DDR2/mDDR memory. These fields configure the
DDR2/mDDR memory controller to match the data bus width, CAS latency, number of internal banks, and
page size of the attached DDR2/mDDR memory. Writing to the DDRDRIVE[1:0], CL, IBANK, and
PAGESIZE bit fields causes the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM
initialization sequence. The SDCR is shown in Figure 13-21 and described in Table 13-24.
Figure 13-21. SDRAM Configuration Register (SDCR)
31
27
26
25
24
Reserved
28
DDR2TERM1
IBANK_POS
MSDRAMEN
DDRDRIVE1
R-0
R/W-1
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
BOOTUNLOCK
DDR2DDQS
DDR2TERM0
DDR2EN
DDRDLL_DIS
DDRDRIVE0
DDREN
SDRAMEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
13
12
11
15
14
TIMUNLOCK
NM
Reserved
CL
Reserved
R/W-0
R/W-1
R-0
R/W-5h
R-0
7
6
4
9
3
2
8
0
Reserved
IBANK
Reserved
PAGESIZE
R-0
R/W-2h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-24. SDRAM Configuration Register (SDCR) Field Descriptions
Bit
31-28
Field
Reserved
27
DDR2TERM1
26
IBANK_POS
25
Value
0
0-3h
Description
Reserved
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM0 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDR2TERM0
bit. Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00
to disable the termination because the ODT feature is not supported.
Internal Bank position.
0
Normal addressing
1
Special addressing. Typically used with mobile DDR partial array self-refresh.
MSDRAMEN
Mobile SDRAM enable. Use this bit in conjunction with DDR2EN, DDREN, and SDRAMEN to
enable/disable mobile SDRAM. To change this bit value, use the following sequence:
1.
2.
24
DDRDRIVE1
23
BOOTUNLOCK
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the MSDRAMEN bit.
0
Disable mobile SDRAM
1
Enable mobile SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE0 bit to make a 2-bit field.
This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDRDRIVE0 bit.
Boot Unlock. Controls the write permission settings for the DDR2TERM[1:0], MSDRAMEN,
DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and SDRAMEN bit fields. To
change these bits, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0],
MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and
SDRAMEN bits.
0
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may not be changed.
1
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may be changed.
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Table 13-24. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
22
DDR2DDQS
Value
Description
DDR2 SDRAM differential DQS enable. This bit is writeable only when the BOOTUNLOCK bit is
unlocked. To change this bit value, use the following sequence:
1.
2.
21
DDR2TERM0
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2DDQS bit.
0
Single-ended DQS
1
Reserved
0-3h
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM1 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0] bits.
Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00 to
disable the termination because the ODT feature is not supported.
0
1h-3h
20
DDR2EN
Disable termination
Reserved
DDR2 enable. This bit is used in conjunction with the DDREN and SDRAMEN bits to enable/disable
DDR2. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
1.
2.
19
0
Disable DDR2
1
Enable DDR2
DDRDLL_DIS
DLL disable for DDR SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked.
To change this bit value, use the following sequence:
1.
2.
18
DDRDRIVE0
Enable DLL
1
Disable DLL inside DDR SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE1 bit to make a 2-bit field.
The DDRDRIVE[1:0] bits configure the output driver impedance control value of the SDRAM
memory. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
0
For DDR2, normal drive strength. For mobile DDR, full drive strength.
For DDR2, weak drive strength. For mobile DDR, 1/2 drive strength.
2h
For DDR2, reserved. For mobile DDR, 1/4 drive strength.
3h
For DDR2, reserved. For mobile DDR, 1/8 drive strength.
DDREN
DDR enable. This bit is used in conjunction with the DDR2EN and SDRAMEN bits to enable/disable
DDR. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDREN bit.
0
Disable DDR
1
Enable DDR
SDRAMEN
SDRAM enable. This bit is used in conjunction with the DDR2EN and DDREN bits to enable/disable
SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
316
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDRIVE[1:0] bits.
1h
1.
2.
16
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDLL_DIS bit.
0
1.
2.
17
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2EN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the SDRAMEN bit.
0
Disable SDRAM
1
Enable SDRAM
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Table 13-24. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
15
TIMUNLOCK
Value
Description
Timing unlock. Controls the write permission settings for the CL bit field, and the SDRAM timing
register 1 (SDTIMR1) and the SDRAM timing register 2 (SDTIMR2) bit fields. To change these bits,
use the following sequence:
1.
2.
14
0
CL bit, and SDTIMR1 and SDTIMR2 bit fields may not be changed.
1
CL bit, and SDTIMR1 and SDTIMR2 bit fields may be changed.
NM
13-12
Reserved
11-9
CL
SDRAM data bus width.
0
Reserved
1
16-bit bus width.
0
Reserved
0-7h
SDRAM CAS latency. This bit is writeable only when the TIMUNLOCK bit is unlocked. To change
this bit value, use the following sequence:
1.
2.
0-1h
8-7
Reserved
6-4
IBANK
3
2-0
Reserved
PAGESIZE
Write a 1 to the TIMUNLOCK bit.
Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit and SDTIMR1 and
SDTIMR2 bit fields.
Write a 1 to the TIMUNLOCK bit.
Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit.
Reserved
2h
CAS Latency = 2
3h
CAS Latency = 3
4h
CAS Latency = 4
5h
CAS Latency = 5
6h-7h
Reserved
0
Reserved
0-7h
Internal SDRAM bank setup. Defines the number of internal banks on the external SDRAM device.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
4h-7h
Reserved
0
Reserved
0-7h
Page Size. Defines the page size of the SDRAM device.
0
256-word page requiring 8 column address bits.
1h
512-word page requiring 9 column address bits.
2h
1024-word page requiring 10 column address bits.
3h
2048-word page requiring 11 column address bits.
4h-7h
Reserved
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13.4.3 SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) is used to configure the DDR2/mDDR memory controller to:
• Enter and Exit the self-refresh and power-down states.
• Enable and disable MCLK, stopping when in the self-refresh state.
• Meet the refresh requirement of the attached DDR2/mDDR device by programming the rate at which
the DDR2/mDDR memory controller issues autorefresh commands.
The SDRCR is shown in Table 13-25 and described in Figure 13-22.
Figure 13-22. SDRAM Refresh Control Register (SDRCR)
31
30
LPMODEN
MCLKSTOPEN
29
Reserved
24
SR_PD
23
22
Reserved
16
R/W-0
R/W-0
R-0
R/W-0
R-0
15
0
RR
R/W-884h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-25. SDRAM Refresh Control Register (SDRCR) Field Descriptions
Bit
Field
31
LPMODEN
30
29-24
23
Value
Low-power mode enable.
0
Disable low-power mode.
1
Enable low-power mode. The state of bit SR_PD selects either self-refresh or power-down
mode.
MCLKSTOPEN
Reserved
MCLK stop enable.
0
Disables MCLK stopping, MCLK may not be stopped.
1
Enables MCLK stopping, MCLK may be stopped. The LPMODEN bit must be set to 1 before
setting the MCLKSTOPEN bit to 1.
0
Reserved
SR_PD
22-16
Reserved
15-0
RR
Description
Self-refresh or Power-down select. This bit is only in effect when the LPMODEN bit is set to 1;
this bit is ignored when the LPMODEN bit is cleared to 0.
0
Self-refresh mode.
1
Power-down mode.
0
Reserved
0-FFFFh
Refresh rate. Defines the rate at which the attached SDRAM devices will be refreshed. The
value of this field may be calculated with the following equation:
RR = SDRAM frequency/SDRAM refresh rate
where SDRAM refresh rate is derived from the SDRAM data sheet.
318
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13.4.4 SDRAM Timing Register 1 (SDTIMR1)
The SDRAM timing register 1 (SDTIMR1) configures the DDR2/mDDR memory controller to meet many of
the AC timing specification of the DDR2/mDDR memory. The SDTIMR1 is programmable only when the
TIMUNLOCK bit is set to 1 in the SDRAM configuration register (SDCR). Note that DDR_CLK is equal to
the period of the DDR_CLK signal. See the DDR2/mDDR memory data sheet for information on the
appropriate values to program each field. The SDTIMR1 is shown in Figure 13-23 and described in
Table 13-26.
Figure 13-23. SDRAM Timing Register 1 (SDTIMR1)
31
25
24
22
21
19
18
16
T_RFC
T_RP
T_RCD
T_WR
R/W-Fh
R/W-2h
R/W-2h
R/W-2h
15
11
10
6
5
3
2
1
0
T_RAS
T_RC
T_RRD
Rsvd
T_WTR
R/W-6h
R/W-9h
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-26. SDRAM Timing Register 1 (SDTIMR1) Field Descriptions
Bit
31-25
Field
Value
Description
T_RFC
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh
or activate command, minus 1. Corresponds to the trfc AC timing parameter in the DDR2/mDDR data
sheet. Calculate by:
T_RFC = (trfc/DDR_CLK) - 1
24-22
T_RP
0-7h
21-19
T_RCD
0-7h
18-16
T_WR
0-7h
Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate
command, minus 1. Corresponds to the trp AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RP = (trp/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write
command, minus 1. Corresponds to the trcd AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RCD = (trcd/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge
command, minus 1. Corresponds to the twr AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_WR = (twr/DDR_CLK) - 1
When the value of this field is changed from its previous value, the initialization sequence will begin.
15-11
T_RAS
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge
command, minus 1. Corresponds to the tras AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RAS = (tras/DDR_CLK) - 1
T_RAS must be greater than or equal to T_RCD.
10-6
T_RC
5-3
T_RRD
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate
command, minus 1. Corresponds to the trc AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RC = (trc/DDR_CLK) - 1
0-7h
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command
in a different bank, minus 1. Corresponds to the trrd AC timing parameter in the DDR2/mDDR data
sheet. Calculate by:
T_RRD = (trrd/DDR_CLK) - 1
For an 8 bank DDR2/mDDR device, this field must be equal to ((4 × tRRD) + (2 × tCK)) / (4 × tCK) - 1.
2
1-0
Reserved
T_WTR
0
0-3h
Reserved
Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.
Corresponds to the twtr AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_WTR = (twtr/DDR_CLK) - 1
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13.4.5 SDRAM Timing Register 2 (SDTIMR2)
Like the SDRAM timing register 1 (SDTIMR1), the SDRAM timing register 2 (SDTIMR2) also configures
the DDR2/mDDR memory controller to meet the AC timing specification of the DDR2/mDDR memory. The
SDTIMR2 is programmable only when the TIMUNLOCK bit is set to 1 in the SDRAM configuration register
(SDCR). Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2/mDDR data
sheet for information on the appropriate values to program each field. SDTIMR2 is shown in Figure 13-24
and described in Table 13-27.
Figure 13-24. SDRAM Timing Register 2 (SDTIMR2)
31
30
27
26
25
24
23
22
16
Rsvd
T_RASMAX
T_XP
T_ODT
T_XSNR
R-0
R/W-8h
R/W-2h
R/W-2h
R/W-32h
15
8
7
5
4
0
T_XSRD
T_RTP
T_CKE
R/W-A7h
R/W-1
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-27. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
Bit
Field
31
Reserved
30-27
T_RASMAX
Value
0
0-Fh
Description
Any writes to these bit(s) must always have a value of 0.
Specifies the maximum number of refresh rate intervals from Activate to Precharge command.
Corresponds to the tras AC timing parameter and the refresh rate in the DDR2/mDDR data sheet.
Calculate by:
T_RASMAX = (trasmax/refresh_rate) - 1
Round down to the nearest cycle.
26-25
T_XP
0-3h
Specifies the minimum number of DDR_CLK cycles from Power Down exit to any other command
except a read command, minus 1. Corresponds to the txp or tcke AC timing parameter in the
DDR2/mDDR data sheet. This field must satisfy the greater of tXP or tCKE.
If txp > tcke, then calculate by T_XP = txp - 1
If txp < tcke, then calculate by T_XP = tcke - 1
24-23
T_ODT
0-3h
Specifies the minimum number of DDR_CLK cycles from ODT enable to write data driven for DDR2
SDRAM. T_ODT must be equal to (CAS latency - tAOND -1). T_ODT must be less than CAS latency
minus 1. This feature is not supported because the DDR_ODT signal is not pinned out.
22-16
T_XSNR
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a self_refresh exit to any other command
except a read command, minus 1. Corresponds to the txsnr AC timing parameter in the DDR2/mDDR
data sheet. Calculate by:
15-8
T_XSRD
0-FFh
7-5
T_RTP
0-7h
4-0
T_CKE
0-1Fh
T_XSNR = (txsnr/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from a self_refresh exit to a read command, minus
1. Corresponds to the txsrd AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_XSRD = txsrd - 1
Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
command, minus 1. Corresponds to the trtp AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RTP = (trtp/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
Corresponds to the tcke AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_CKE = tcke - 1
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13.4.6 SDRAM Configuration Register 2 (SDCR2)
The SDRAM configuration register 2 (SDCR2) contains fields to configure partial array self-refresh and
rowsize of the mDDR. This register is applicable only when the IBANK_POS bit in the SDRAM
configuration register (SDCR) is set to 1 for special addressing. Writing to the PASR and ROWSIZE bit
fields will cause the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM initialization
sequence. SDCR2 is shown in Figure 13-25 and described in Table 13-28.
Figure 13-25. SDRAM Configuration Register 2 (SDCR2)
31
19
18
16
Reserved
PASR
R-0
R/W-0
15
3
2
0
Reserved
ROWSIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-28. SDRAM Configuration Register 2 (SDCR2) Field Descriptions
Bit
Field
31-19
Reserved
18-16
PASR
Value
0
Description
Reserved
0-7h
Partial array self-refresh.
0
4 banks will be refreshed.
1h
2 banks will be refreshed.
2h
1 bank will be refreshed.
3h-4h
Reserved
5h
1/2 bank will be refreshed.
6h
1/4 bank will be refreshed.
7h
Reserved
Reserved
15-3
Reserved
0
2-0
ROWSIZE
0-7h
Row size. Defines the number of row address bit for DDR device.
0
9 row address bits
1h
10 row address bits
2h
11 row address bits
3h
12 row address bits
4h
13 row address bits
5h
14 row address bits
6h
15 row address bits
7h
16 row address bits
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13.4.7 Peripheral Bus Burst Priority Register (PBBPR)
The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the
DDR2/mDDR memory controller. To avoid command starvation, the DDR2/mDDR memory controller
momentarily raises the priority of the oldest command in the command FIFO after a set number of
transfers have been made. The PR_OLD_COUNT bit sets the number of transfers that must be made
before the DDR2/mDDR memory controller raises the priority of the oldest command. See
Section 13.2.6.2 for more details on command starvation.
Proper configuration of the PBBPR is critical to correct system operation. The DDR2/mDDR memory
controller always prioritizes accesses to open rows as highest, if there is any bank conflict regardless of
master priority. This is done to allow most efficient utilization of the DDR2/mDDR. However, it could lead
to excessive blocking of high priority masters. If the PR_OLD_COUNT bits are cleared to 00h, then the
DDR2/mDDR memory controller always honors the master priority, regardless of open row/bank status.
For most systems, the PBBPR should be set to a moderately low value to provide an acceptable balance
of DDR2/mDDR efficiency and latency for high priority masters (for example, 10h or 20h).
The PBBPR is shown in Figure 13-26 and described in Table 13-29.
Figure 13-26. Peripheral Bus Burst Priority Register (PBBPR)
31
16
Reserved
R-0
15
8
7
0
Reserved
PR_OLD_COUNT
R-0
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-29. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
PR_OLD_COUNT
Value
0
0-FFh
Description
Any writes to these bit(s) must always have a value of 0.
Priority raise old counter. Specifies the number of memory transfers after which the
DDR2/mDDR memory controller will elevate the priority of the oldest command in the command
FIFO. Clearing to 00h will ensure master priority is strictly honored (at the cost of decreased
DDR2/mDDR memory controller efficiency, as open row will always be closed immediately if
any bank conflict occurs). Recommended setting for typical system operation is between 10h
and 20h.
0
1 memory transfer
1h
2 memory transfers
2h
3 memory transfers
3h-FFh 4 to 256 memory transfers
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13.4.8 Performance Counter 1 Register (PC1)
For debug or gathering performance statistics, the PC1 and PC2 counters and associated configuration
registers are provided. These are intended for debug and analysis only. By configuring the performance
counter configuration register (PCC) to define the type of statistics to gather and configuring the
performance counter master region select register (PCMRS) to filter accesses only to specific chip select
regions, performing system applications and then reading these counters, different statistics can be
gathered. To reset the counters, you must reset (mod_g_rst_n) the DDR2/mDDR memory controller
through the PSC. For details on the PSC, see the Power and Sleep Controller (PSC) chapter.
The performance counter 1 register (PC1) is shown in Figure 13-27 and described in Table 13-30.
Figure 13-27. Performance Counter 1 Register (PC1)
31
0
Counter1
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-30. Performance Counter 1 Register (PC1) Field Descriptions
Bit
31-0
Field
Counter1
Value
Description
0-FFFF FFFFh
32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register (PCMRS).
13.4.9 Performance Counter 2 Register (PC2)
The performance counter 2 register (PC2) is shown in Figure 13-28 and described in Table 13-31.
Figure 13-28. Performance Counter 2 Register (PC2)
31
0
Counter2
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-31. Performance Counter 2 Register (PC2) Field Descriptions
Bit
31-0
Field
Counter2
Value
0-FFFF FFFFh
Description
32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register (PCMRS).
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13.4.10 Performance Counter Configuration Register (PCC)
The performance counter configuration register (PCC) is shown in Figure 13-29 and described in
Table 13-32.
Table 13-33 shows the possible filter configurations for the two performance counters. These filter
configurations can be used in conjunction with a Master ID and/or an external chip select to obtain
performance statistics for a particular master and/or an external chip select.
Figure 13-29. Performance Counter Configuration Register (PCC)
31
30
CNTR2_MSTID_EN
CNTR2_REGION_EN
29
Reserved
20
CNTR2_CFG
R/W-0
R/W-0
R-0
R/W-1
13
4
19
16
15
14
CNTR1_MSTID_EN
CNTR1_REGION_EN
Reserved
3
CNTR1_CFG
0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-32. Performance Counter Configuration Register (PCC) Field Descriptions
Bit
Field
31
CNTR2_MSTID_EN
30
Value
Description
Master ID filter enable for performance counter 2 register (PC2). Refer to Table 13-33 for
details.
0
Master ID filter is disabled. PC2 counts accesses from all masters to DDR2/mDDR SDRAM.
1
Master ID filter is enabled. PC2 counts accesses from the master, corresponding to the
Master ID value in the MST_ID2 bit field of the performance counter master region select
register (PCMRS).
CNTR2_REGION_EN
Chip select filter enable for performance counter 2 register (PC2). Refer to Table 13-33 for
details.
0
Chip select filter is disabled. PC2 counts total number of accesses (DDR2/mDDR SDRAM +
DDR2/mDDR memory controller memory-mapped register accesses). The REGION_SEL2
bit field value in the performance counter master region select register (PCMRS) is a don’t
care.
1
Chip select filter is enabled. If the REGION_SEL2 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL2 = 0: PC2 counts accesses to DDR2/mDDR SDRAM memory.
REGION_SEL2 = 7h: PC2 counts accesses to DDR2/mDDR memory controller memorymapped registers.
29-20
Reserved
19-16
CNTR2_CFG
15
14
0
0-Fh
CNTR1_MSTID_EN
Any writes to these bit(s) must always have a value of 0.
Filter configuration for performance counter 2 register (PC2). Refer to Table 13-33 for
details.
Master ID filter enable for performance counter 1 register (PC1). Refer to Table 13-33 for
details.
0
Master ID filter is disabled. PC1 counts accesses from all masters to DDR2/mDDR SDRAM.
1
Master ID filter is enabled. PC1 counts accesses from the master, corresponding to the
Master ID value in the MST_ID1 bit field of the performance counter master region select
register (PCMRS).
CNTR1_REGION_EN
Chip select filter enable for performance counter 1 register (PC1). Refer to Table 13-33 for
details.
0
Chip select filter is disabled. PC1 counts total number of accesses (DDR2/mDDR SDRAM +
DDR2/mDDR memory controller memory-mapped register accesses). The REGION_SEL1
bit field value in the performance counter master region select register (PCMRS) is a don’t
care.
1
Chip select filter is enabled. If the REGION_SEL1 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL1 = 0: PC1 counts accesses to DDR2/mDDR SDRAM memory.
REGION_SEL1 = 7h: PC1 counts accesses to DDR2/mDDR memory controller memorymapped registers.
13-4
324
Reserved
DDR2/mDDR Memory Controller
0
Any writes to these bit(s) must always have a value of 0.
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Table 13-32. Performance Counter Configuration Register (PCC) Field Descriptions (continued)
Bit
Field
3-0
CNTR1_CFG
Value
0-Fh
Description
Filter configuration for performance counter 1 register (PC1). Refer to Table 13-33 for
details.
Table 13-33. Performance Counter Filter Configuration
Performance Counter Configuration Register (PCC) Bit
CNTRn_CFG
CNTRn_REGION_EN
0
0
CNTRn_MSTID_EN Description
0 or 1
Counts the total number of READ/WRITE commands the
external memory controller receives.
The size of counter increments are determines by the size of the
transfer and the default burst size (DBS). The counter breaks up
transfers into sizes according to DBS. Therefore, counter
increments for transfers aligned to DBS are equal to the transfer
size divided by the DBS.
1h
0
0
Counts the total number of ACTIVATE commands the
external memory controller issues to DDR2/mDDR memory.
The counter increments by a value of 1 for every request to
read/write data to a closed bank in DDR2/mDDR memory by the
external memory controller.
2h
0 or 1
0 or 1
Counts the total number of READ commands (read accesses)
the DDR2/mDDR memory controller receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size divided by the DBS.
3h
0 or 1
0 or 1
Counts the total number of WRITE commands the
DDR2/mDDR memory controller receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size of data written to the
DDR2/mDDR memory controller divided by the DBS.
4h
0
0
Counts the number of external memory controller cycles
(DDR_CLK cycles) that the command FIFO is full.
Use the following to calculate the counter value as a percentage:
% = counter value / total DDR_CLK cycles in a sample period
As the value of this counter approaches 100%, the DDR2/mDDR
memory controller is approaching a congestion point where the
command FIFO is full 100% of the time and a command will have
to wait at the SCR to be accepted in the command FIFO.
5h-7h
0
0
8h
0 or 1
0 or 1
Reserved
Counts the number of commands (requests) in the command
FIFO that require a priority elevation.
To avoid command starvation, the DDR2/mDDR memory
controller can momentarily raise the priority of the oldest
command in the command FIFO after a set number of transfers
have been made. The PR_OLD_COUNT bit field in the peripheral
bus burst priority register (PBBPR) sets the number of the
transfers that must be made before the DDR2/mDDR memory
controller will raise the priority of the oldest command.
9h
0
0
Counts the number of DDR2/mDDR memory controller cycles
(DDR_CLK cycles) that a command is pending in the
command FIFO. This counter increments every cycle the
command FIFO is not empty.
Use the following to calculate the counter value as a percentage:
% = counter value / total DDR_CLK cycles in sample period
As the value of this counter approaches 100%, the number of
cycles the DDR2/mDDR memory controller has a command in the
command FIFO to service approaches 100%.
Ah-Fh
0
0
Reserved
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13.4.11 Performance Counter Master Region Select Register (PCMRS)
The performance counter master region select register (PCMRS) is shown in Figure 13-30 and described
in Table 13-34.
Figure 13-30. Performance Counter Master Region Select Register (PCMRS)
31
24
23
20
19
16
MST_ID2
Reserved
REGION_SEL2
R/W-0
R-0
R/W-0
15
8
7
4
3
0
MST_ID1
Reserved
REGION_SEL1
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-34. Performance Counter Master Region Select Register (PCMRS) Field Descriptions
Bit
Field
Value
Description
31-24
MST_ID2
0-FFh
Master ID for performance counter 2 register (PC2). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
23-20
Reserved
0
Any writes to these bit(s) must always have a value of 0.
19-16
REGION_SEL2
0-Fh
Region select for performance counter 2 register (PC2).
0
1h-6h
7h
15-8
MST_ID1
7-4
Reserved
3-0
REGION_SEL1
Reserved
PC2 counts total DDR2/mDDR memory controller memory-mapped register accesses.
8h-Fh
Reserved
0-FFh
Master ID for performance counter 1 register (PC1). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
0
Any writes to these bit(s) must always have a value of 0.
0-Fh
Region select for performance counter 1 register (PC1).
0
1h-6h
7h
8h-Fh
326
PC2 counts total DDR2/mDDR accesses.
PC1 counts total DDR2/mDDR accesses.
Reserved
PC1 counts total DDR2/mDDR memory controller memory-mapped register accesses.
Reserved
DDR2/mDDR Memory Controller
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Performance Counter Time Register (PCT)
The performance counter time register (PCT) is shown in Figure 13-31 and described in Table 13-35.
Figure 13-31. Performance Counter Time Register (PCT)
31
0
TOTAL_TIME
R-0
LEGEND: R = Read only; -n = value after reset
Table 13-35. Performance Counter Time Register (PCT) Field Description
Bit
31-0
Field
Value
TOTAL_TIME
Description
0-FFFF FFFFh
32-bit counter that continuously counts number for DDR_CLK cycles elapsed after the
DDR2/mDDR memory controller is brought out of reset.
13.4.12 DDR PHY Reset Control Register (DRPYRCR)
The DDR PHY reset control register (DRPYRCR) is used to reset the DDR PHY. The DRPYRCR is shown
in Figure 13-32 and described in Table 13-36.
Figure 13-32. DDR PHY Reset Control Register (DRPYRCR)
31
16
Reserved
R-0
15
11
10
9
0
Reserved
RESET_PHY
Reserved
R-04h
R/W-0
R-091h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-36. DDR PHY Reset Control Register (DRPYRCR)
Bit
31-11
10
9-0
Field
Reserved
Value
0000 04h
RESET_PHY
Reserved
Description
Always write the default value to these bits.
Reset DDR PHY.
0
No effect.
1
Resets DDR PHY.
091h
Always write the default value to these bits.
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13.4.13 Interrupt Raw Register (IRR)
The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs,
the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is
shown in Figure 13-33 and described in Table 13-37.
Figure 13-33. Interrupt Raw Register (IRR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LT
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 13-37. Interrupt Raw Register (IRR) Field Descriptions
Bit
31-3
2
1-0
Field
Reserved
Value
0
Reserved
LT
Reserved
Description
Line trap. Write a 1 to clear LT and the LTM bit in the interrupt masked register (IMR); a write of 0 has
no effect.
0
A line trap condition has not occurred.
1
Illegal memory access type. See Section 13.2.14 for more details.
0
Reserved
13.4.14 Interrupt Masked Register (IMR)
The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt
condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR
bit is set. The IMR bit is not set if the interrupt is not enabled in IMSR. The IMR is shown in Figure 13-34
and described in Table 13-38.
Figure 13-34. Interrupt Masked Register (IMR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTM
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 13-38. Interrupt Masked Register (IMR) Field Descriptions
Bit
31-3
2
1-0
328
Field
Reserved
Value
0
LTM
Reserved
Description
Reserved
Line trap masked. Write a 1 to clear LTM and the LT bit in the interrupt raw register (IRR); a write of 0
has no effect.
0
A line trap condition has not occurred.
1
Illegal memory access type (only set if the LTMSET bit in IMSR is set). See Section 13.2.14 for more
details.
0
Reserved
DDR2/mDDR Memory Controller
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13.4.15 Interrupt Mask Set Register (IMSR)
The interrupt mask set register (IMSR) enables the DDR2/mDDR memory controller interrupt. The IMSR is
shown in Figure 13-35 and described in Table 13-39.
NOTE: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask
clear register (IMCR), the interrupt is not enabled and neither bit is set to 1.
Figure 13-35. Interrupt Mask Set Register (IMSR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMSET
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-39. Interrupt Mask Set Register (IMSR) Field Descriptions
Bit
Field
31-3
Reserved
2
LTMSET
1-0
Reserved
Value
0
Description
Reserved
Line trap interrupt set. Write a 1 to set LTMSET and the LTMCLR bit in the interrupt mask clear register
(IMCR); a write of 0 has no effect.
0
Line trap interrupt is not enabled; a write of 1 to the LTMCLR bit in IMCR occurred.
1
Line trap interrupt is enabled.
0
Reserved
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13.4.16 Interrupt Mask Clear Register (IMCR)
The interrupt mask clear register (IMCR) disables the DDR2/mDDR memory controller interrupt. Once an
interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 13-36
and described in Table 13-40.
NOTE: If the LTMCLR bit in IMCR is set concurrently with the LTMSET bit in the interrupt mask set
register (IMSR), the interrupt is not enabled and neither bit is set to 1.
Figure 13-36. Interrupt Mask Clear Register (IMCR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMCLR
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 13-40. Interrupt Mask Clear Register (IMCR) Field Descriptions
Bit
Field
31-3
Reserved
2
LTMCLR
1-0
330
Reserved
Value
0
Description
Reserved
Line trap interrupt clear. Write a 1 to clear LTMCLR and the LTMSET bit in the interrupt mask set
register (IMSR); a write of 0 has no effect.
0
Line trap interrupt is not enabled.
1
Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred.
0
Reserved
DDR2/mDDR Memory Controller
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13.4.17 DDR PHY Control Register (DRPYC1R)
The DDR PHY control register 1 (DRPYC1R) configures the DDR2/mDDR memory controller read latency.
The DRPYC1R is shown in Figure 13-37 and described in Table 13-41.
Figure 13-37. DDR PHY Control Register 1 (DRPYC1R)
31
16
Reserved
R-0
7
6
Rsvd
15
CONFIG_DLL_MODE
14
12
11
Reserved
8
EXT_STRBEN
PWRDNEN
5
Reserved
3
2
RL
0
R-0
R/W-0
R-0
R/W-0
R/W-1
R-0
R/W-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-41. DDR PHY Control Register 1 (DRPYC1R) Field Descriptions
Bit
Field
31-15
Reserved
14-12
CONFIG_DLL_MODE
11-8
7
6
Reserved
Value
0
DLL configuration. Controls the value assigned to the config_dll_mode input.
DLL REFCLK is enabled.
2h
DLL REFCLK is disabled.
3h-7h
Reserved
0
Reserved
Internal/External strobe gating.
0
Internal strobe gating mode.
1
External strobe gating mode.
PWRDNEN
Reserved
2-0
RL
Reserved
0-1h
EXT_STRBEN
5-3
Description
Power down receivers.
0
Receivers powered up when idle.
1
Receivers powered down when idle.
0
Reserved
0-7h
Read latency. Read latency is equal to CAS latency plus round trip board delay for data
minus 1. The maximum value of read latency that is supported is CAS latency plus 2. The
minimum read latency value that is supported is CAS latency plus 1. The read latency value
is defined in number of MCLK/DDR_CLK cycles.
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Chapter 14
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Enhanced Direct Memory Access (EDMA3) Controller
The enhanced direct memory access (EDMA3) controller is a high-performance, multichannel,
multithreaded DMA controller that allows you to program a wide variety of transfer geometries and transfer
sequences. This chapter describes the features and operations of the EDMA3 controller.
Section 14.1 provides a brief overview, features, and terminology. Section 14.2 provides the architecture
details and common operations of the EDMA3 channel controllers (EDMA3_m_CC0) and the EDMA3
transfer controllers (EDMA3_m_TCn). Section 14.3 contains examples and common usage scenarios.
Section 14.4 describes the memory-mapped registers associated with the EDMA3 controller.
Topic
14.1
14.2
14.3
14.4
14.5
14.6
332
...........................................................................................................................
Introduction .....................................................................................................
Architecture .....................................................................................................
Transfer Examples ............................................................................................
Registers .........................................................................................................
Tips ................................................................................................................
Setting Up a Transfer ........................................................................................
Enhanced Direct Memory Access (EDMA3) Controller
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333
338
380
397
464
466
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14.1 Introduction
14.1.1 Overview
The enhanced direct memory access (EDMA3) controller’s primary purpose is to service userprogrammed data transfers between two memory-mapped slave endpoints on the device. Typical usage
includes, but is not limited to:
• Servicing software driven paging transfers (for example, from external memory to internal device
memory
• Servicing event driven peripherals, such as a serial port
• Performing sorting or subframe extraction of various data structures
• Offloading data transfers from the main device CPU(s) (See your device-specific data manual for
specific peripherals that are accessible via EDMA3. See the section on SCR connectivity in your
device-specific data manual for EDMA3 connectivity.)
The EDMA3 controller consists of two principal blocks:
• EDMA3 channel controller: (EDMA3_m_CC0)
• EDMA3 transfer controller: (EDMA3_m_TCn)
The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CC
includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The
EDMA3CC serves to prioritize incoming software requests or events from peripherals, and submits
transfer requests (TR) to the EDMA3 transfer controller.
The EDMA3 transfer controllers are responsible for data movement. The transfer request packets (TRP)
submitted by the EDMA3CC contains the transfer context, based on which the transfer controller issues
read/write commands to the source and destination addresses programmed for a given transfer.
14.1.2 Features
The EDMA3 channel controller (EDMA3CC) has the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions
– A-synchronized transfers: 1 dimension serviced per event
– AB-synchronized transfers: 2 dimensions serviced per event
– Independent indexes on source and destination
– Chaining feature allows 3-D transfer based on single event
• Flexible transfer definition
– Increment or constant addressing modes
– Linking mechanism allows automatic PaRAM set update. Useful for ping-pong type transfers, autoreload transfers.
– Chaining allows multiple transfers to execute with a single event
• Interrupt generation for:
– Transfer completion
– Error conditions (illegal addresses, illegal modes, exceeding queue threshold)
• Debug visibility
– Queue watermarking
– Error and status recording to facilitate debug
– Missed event detection
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•
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EDMA3_0_CC0:
– 32 DMA channels
– 8 QDMA channels
– 128 parameter RAM (PaRAM) entries
– 2 event queues
– 4 shadow regions
– 2 transfer controllers (EDMA3_0_TC0 and EDMA3_0_TC1)
– 5 interrupts:
• EDMA3_0_CC0_INT0
• EDMA3_0_CC0_INT1
• EDMA3_0_CC0_INT2
• EDMA3_0_CC0_INT3
• EDMA3_0_CC0_ERRINT
EDMA3_1_CC0:
– 32 DMA channels
– 8 QDMA channels
– 128 parameter RAM (PaRAM) entries
– 1 event queue
– 4 shadow regions
– 1 transfer controller (EDMA3_1_TC0)
– 5 interrupts:
• EDMA3_1_CC0_INT0
• EDMA3_1_CC0_INT1
• EDMA3_1_CC0_INT2
• EDMA3_1_CC0_INT3
• EDMA3_1_CC0_ERRINT
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The EDMA3 transfer controller (EDMA3TC) has the following features:
• Supports 2-dimensional transfers with independent indexes on source and destination (EDMA3CC
manages the 3rd dimension)
• More then one transfer controller allows concurrent transfers
• Programmable priority level for each transfer controller relative to each other and other masters in the
system.
• Support for increment or constant addressing mode transfers
• Error conditions with interrupt support
• Supports more then one in-flight transfer requests
• Debug/status visibility
• 64-bit wide read and write ports
• Little-endian mode
• EDMA3_0_TC0:
– FIFIOSIZE = 128 bytes
– BUSWIDTH (Read/Write Controllers) = 8 byte (64 bits)
– DSTREGDEPTH = 4
– DBS (default) = 16 bytes. The default burst size (DBS) is programmable, and can be configured for
16-, 32-, or 64-bytes burst size. See the Chip Configuration 0 Register (CFGCHIP0) in the System
Configuration (SYSCFG) Module chapter for details to change the default burst size value.
– Error interrupt: EDMA3_0_TC0_ERRINT
– EDMA3 channel controller used: EDMA3_0_CC0
• EDMA3_0_TC1:
– FIFIOSIZE = 128 bytes
– BUSWIDTH (Read/Write Controllers) = 8 byte (64 bits)
– DSTREGDEPTH = 4
– DBS (default) = 16 bytes. The default burst size (DBS) is programmable, and can be configured for
16-, 32-, or 64-bytes burst size. See the Chip Configuration 0 Register (CFGCHIP0) in the System
Configuration (SYSCFG) Module chapter for details to change the default burst size value.
– Error interrupt: EDMA3_0_TC1_ERRINT
– EDMA3 channel controller used: EDMA3_0_CC0
• EDMA3_1_TC0:
– FIFIOSIZE = 256 bytes
– BUSWIDTH (Read/Write Controllers) = 8 byte (64 bits)
– DSTREGDEPTH = 4
– DBS (default) = 16 bytes. The default burst size (DBS) is programmable, and can be configured for
16-, 32-, or 64-bytes burst size. See the Chip Configuration 1 Register (CFGCHIP1) in the System
Configuration (SYSCFG) Module chapter for details to change the default burst size value.
– Error interrupt: EDMA3_1_TC0_ERRINT
– EDMA3 channel controller used: EDMA3_1_CC0
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14.1.3 Functional Block Diagram
Figure 14-1 shows a block diagram of the EDMA3 controller.
Figure 14-1. EDMA3 Controller Block Diagram
Transfer
controllers
EDMA3_0_CC0
MMR
To/from
EDMA3
programmer
DMA/QDMA
channel
logic
Event
queue(s)
PaRAM
Transfer
request
submission
TC0
Read/write
commands
and data
TC1
Read/write
commands
and data
EDMA3_0_
TC0_ERRINT
EDMA3_0_
CC0_INT[3:0]
EDMA3_0_
CC0_ERRINT
Completion
and error
interrupt
logic
MMR
Completion
detection
EDMA3_0_
TC1_ERRINT
Transfer
controllers
EDMA3_1_CC0
MMR
To/from
EDMA3
programmer
DMA/QDMA
channel
logic
Event
queue
PaRAM
Transfer
request
submission
TC0
Read/write
commands
and data
EDMA3_1_
TC0_ERRINT
EDMA3_1_
CC0_INT[3:0]
EDMA3_1_
CC0_ERRINT
Completion
and error
interrupt
logic
Completion
detection
14.1.4 Terminology Used in This Document
The following are some terms used in this chapter.
Term
A-synchronized
transfer
AB-synchronized
transfer
Chaining
Meaning
A transfer type where 1 dimension is serviced per synchronization event.
A transfer type where 2 dimensions are serviced per synchronization event.
A trigger mechanism in which a transfer can be initiated at the completion of
another transfer or subtransfer.
CPU(s)
The main processing engine or engines on a device.
DMA channel
A channel that can be triggered by external, manual, and chained events. All DMA
channels exist in the EDMA3CC.
Dummy set or
A PaRAM set for which at least one of the count fields is equal to 0 and at least
Dummy PaRAM set one of the count fields is nonzero. A null PaRAM set has all the count set fields
cleared.
Dummy transfer
A dummy set results in the EDMA3CC performing a dummy transfer. This is not an
error condition. A null set results in an error condition.
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Term
EDMA3 channel
controller
(EDMA3CC)
EDMA3
programmer
EDMA3 transfer
controller(s)
(EDMA3TC)
Enhanced direct
memory access
(EDMA3)
controller
Link parameter set
Linking
Memory-mapped
slave
Master
peripherals
Null set or Null
PaRAM set
Null transfer
QDMA channel
Parameter RAM
(PaRAM)
Parameter RAM
(PaRAM) set
Parameter RAM
(PaRAM) set entry
Slave end points
Meaning
The user-programmable portion of the EDMA3. The EDMA3CC contains the
parameter RAM (PaRAM) , event processing logic, DMA/QDMA channels, event
queues, etc. The EDMA3CC services events (external, manual, chained, QDMA)
and is responsible for submitting transfer requests to the transfer controllers
(EDMA3TC), which perform the actual transfer.
Any entity on the chip that has read/write access to the EDMA3 registers and can
program an EDMA3 transfer.
Transfer controllers are the transfer engine for the EDMA3. Performs the
read/writes as dictated by the transfer requests submitted by the EDMA3CC.
Consists of the EDMA3 channel controller (EDMA3CC) and EDMA3 transfer
controller(s) (EDMA3TC). Is referred to as EDMA3 in this document.
A PaRAM set that is used for linking.
The mechanism of reloading a PaRAM set with new transfer characteristics on
completion of the current transfer.
All on-chip memories, off-chip memories, and slave peripherals. These typically rely
on the EDMA3 (or other master peripheral) to perform transfers to and from them.
All peripherals that are capable of initiating read and write transfers to the
peripherals system and may not solely rely on the EDMA3 for their data transfers.
A PaRAM set that has all count fields cleared (except for the link field). A dummy
PaRAM set has at least one of the count fields nonzero.
A trigger event for a null PaRAM set results in the EDMA3CC performing a null
transfer. This is an error condition. A dummy transfer is not an error condition.
One of the 8 channels that can be triggered when writing to the trigger word
(TRWORD) of a PaRAM set. All QDMA channels exist in the EDMA3CC.
Programmable RAM that stores PaRAM sets used by DMA channels, QDMA
channels, and linking.
A 32-byte EDMA3 channel transfer definition. Each parameter set consists of
8 words (4-bytes each), which store the context for a DMA/QDMA/link transfer. A
PaRAM set includes source address, destination address, counts, indexes, options,
etc.
One of the 4-byte components of the parameter set.
All on-chip memories, off-chip memories, and slave peripherals. These rely on the
EDMA3 to perform transfers to and from them.
Transfer request
A command for data movement that is issued from the EDMA3CC to the
(TR)
EDMA3TC. A TR includes source and destination addresses, counts, indexes,
options, etc.
Trigger event
Action that causes the EDMA3CC to service the PaRAM set and submit a transfer
request to the EDMA3TC. Trigger events for DMA channels include manual
triggered (CPU triggered), external event triggered, and chain triggered. Trigger
events for QDMA channels include autotriggered and link triggered.
Trigger word
For QDMA channels, the trigger word specifies the PaRAM set entry that when
written results in a QDMA trigger event. The trigger word is programmed via the
QDMA channel n mapping register (QCHMAPn) and can point to any PaRAM set
entry.
TR synchronization See Trigger event.
(sync) event
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14.2 Architecture
This section discusses the architecture of the EDMA3 controller.
14.2.1 Functional Overview
This section provides an overview of the EDMA3 channel controller (EDMA3CC) and EDMA3 transfer
controller (EDMA3TC).
14.2.1.1 EDMA3 Channel Controller (EDMA3CC)
Figure 14-2 shows a functional block diagram of the EDMA3 channel controller (EDMA3CC).
The main blocks of the EDMA3CC are:
• DMA/QDMA Channel Logic: This block consists of logic that captures external system or peripheral
events that can be used to initiate event triggered transfers, it also includes registers that allow
configuring the DMA/QDMA channels (queue mapping, PaRAM entry mapping). It includes all the
registers for different trigger type (manual, external events, chained and auto triggered) for
enabling/disabling events, and monitor event status.
• Parameter RAM (PaRAM): Maintains parameter set entries for channel and reload parameter sets. The
PaRAM needs to be written with the transfer context for the desired channels and link parameter sets.
• Event queues: These form the interface between the event detection logic and the transfer request
submission logic.
• Transfer Request Submission Logic: This logic processes PaRAM sets based on a trigger event
submitted to the event queue and submits a transfer request (TR) to the transfer controller associated
with the event queue.
• Completion detection: The completion detect block detects completion of transfers by the EDMA3
transfer controller (EDMA3TC) and/or slave peripherals. Completion of transfers can optionally be used
to chain trigger new transfers or to assert interrupts. The logic includes the interrupt processing
registers for enabling/disabling interrupt (to be sent to the CPU), interrupt status/clearing registers.
Additionally there are:
• Region registers: Region registers allow DMA resources (DMA channels and interrupts) to be assigned
to unique regions, which can be owned by unique EDMA programmers (a use model for hetero/multi
core devices) or by unique tasks/threads (a use model for single core devices).
• Debug registers: Debug registers allow debug visibility by providing registers to read the queue status,
channel controller status (what logic within the CC is active), and missed event status.
The EDMA3CC includes two channel types: DMA channels and QDMA channels.
Each channel is associated with a given event queue/transfer controller and with a given PaRAM set. The
main difference between a DMA channel and QDMA channel is how the transfers are triggered by the
system. See Section 14.2.4.
A trigger event is needed to initiate a transfer. For DMA channels, a trigger event may be due to an
external event, manual write to the event set register, or chained event. QDMA channels are autotriggered
when a write is performed to the user-programmed trigger word. All such trigger events are logged into
appropriate registers upon recognition. See DMA channel registers (Section 14.4.2.5) and QDMA channel
registers (Section 14.4.2.7).
Once a trigger event is recognized, the event type/channel is queued in the appropriate EDMA3CC event
queue. The assignment of each DMA/QDMA channel to event queue is programmable. Each queue is
16 deep, so up to 16 events may be queued (on a single queue) in the EDMA3CC at an instant in time.
Additional pending events mapped to a full queue are queued when event queue space becomes
available. See Section 14.2.10.
If events on different channels are detected simultaneously, the events are queued based on fixed priority
arbitration scheme with the DMA channels being higher priority than the QDMA channels. Among the two
groups of channels, the lowest-numbered channel is the highest priority.
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Figure 14-2. EDMA3 Channel Controller (EDMA3CC) Block Diagram
From peripherals/external events
Event
enable
register
(EER)
Event
set
register
(ESR)
32
15
15
0
32
Queue 1
Chained
event
register
(CER)
Event queues
8
PaRAM
Completion
interface
Completion
detection
Error
detection
Error Interrrupt
To
EDMA3TC(s)
Parameter
set 127
Queue bypass
QDMA trigger
EDMA3 channel
controller
Parameter
set 126
8:1 priority encoder
QDMA
event
register
(QER)
Parameter
set 1
Queue 0
32
Chain
trigger
Parameter
set 0
0
Transfer request submission
Manual
trigger
Event
register
(ER)
Channel mapping
Event
trigger
E1 E0
32:1 priority encoder
E31
From
EDMA3TC(s)
Completion
interrupt
Transfer Completion
Interrupts
Each event in the event queue is processed in the order it was queued. On reaching the head of the
queue, the PaRAM associated with that channel is read to determine the transfer details. The TR
submission logic evaluates the validity of the TR and is responsible for submitting a valid transfer request
(TR) to the appropriate EDMA3TC (based on the event queue to EDMA3TC association, Q0 goes to TC0,
and Q1 goes to TC1, etc.). For more details, see Section 14.2.3.
The EDMA3TC receives the request and is responsible for data movement as specified in the transfer
request packet (TRP) and other necessary tasks like buffering, ensuring transfers are carried out in an
optimal fashion wherever possible. For more details on EDMA3TC, see Section 14.2.1.2.
You may have chosen to receive an interrupt or chain to another channel on completion of the current
transfer in which case the EDMA3TC signals completion to the EDMA3CC completion detection logic
when the transfer is done. You can alternately choose to trigger completion when a TR leaves the
EDMA3CC boundary rather than wait for all the data transfers to complete. Based on the setting of the
EDMA3CC interrupt registers, the completion interrupt generation logic is responsible for generating
EDMA3CC completion interrupts to the CPU. For more details, see Section 14.2.5.
Additionally, the EDMA3CC also has an error detection logic, which causes error interrupt generation on
various error conditions (like missed events, exceeding event queue thresholds, etc.). For more details on
error interrupts, see Section 14.2.9.4.
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14.2.1.2 EDMA3 Transfer Controller (EDMA3TC)
Figure 14-3 shows a functional block diagram of the EDMA3 transfer controller (EDMA3TC).
The main blocks of the EDMA3TC are:
• DMA program register set: The DMA program register set stores the transfer requests received from
the EDMA3 channel controller (EDMA3CC).
• DMA source active register set: The DMA source active register set stores the context for the DMA
transfer request currently in progress in the read controller.
• Read controller: The read controller issues read commands to the source address.
• Destination FIFO register set: The destination (Dst) FIFO register set stores the context for the DMA
transfer request(s) currently in progress or pending in the write controller.
• Write controller: The write controller issues write commands/write data to the destination address.
• Data FIFO: The data FIFO holds temporary in-flight data. The source peripheral's read data is stored in
the data FIFO and subsequently written to the destination peripheral/end point by the write controller.
• Completion interface: The completion interface sends completion codes to the EDMA3CC when a
transfer completes, and is used for generating interrupts and chained events (see Section 14.2.5 for
details on transfer completion reporting).
Figure 14-3. EDMA3 Transfer Controller (EDMA3TC) Block Diagram
Transfer request
submission
To completion
detection logic
in EDMA3_m_CC0
EDMA3_m_TCn_ERRINT
Data
FIFO
Write
controller
Program
register set
Source active
register set
Read
controller
EDMA3_m_TCn
Destination FIFO
register set
Read
command
Read data
Write
command
Write data
When the EDMA3TC is idle and receives its first TR, the TR is received in the DMA program register set,
where it transitions to the DMA source active set and the destination FIFO register set immediately. The
source active register set tracks the commands for the source side of the transfers, and the destination
FIFO register set tracks commands for the destination side of the transfer. The second TR (if pending from
EDMA3CC) is loaded into the DMA program set, ensuring it can start as soon as possible when the active
transfer (the transfer in the source active set) is completed. As soon as the current active set is
exhausted, the TR is loaded from the DMA program register set into the DMA source active register set as
well as to the appropriate entry in the destination FIFO register set.
The read controller issues read commands governed by the rules of command fragmentation and
optimization. These are issued only when the data FIFO has space available for the read data. The
number of read commands issued depends on the TR transfer size. The TC write controller starts issuing
write commands as soon as sufficient data is read in the data FIFO for the write controller to issue
optimally sized write commands following the rules for command fragmentation and optimization. For
details on command fragmentation and optimization, see Section 14.2.11.1.2.
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The DSTREGDEPTH parameter (fixed for a given transfer controller) determines the number of entries in
the Dst FIFO register set. The number of entries determines the amount of TR pipelining possible for a
given TC. The write controller can manage the write context for the number of entries in the Dst FIFO
register set. This allows the read controller to go ahead and issue read commands for the subsequent TRs
while the Dst FIFO register set manages the write commands and data for the previous TR. In summary, if
the DSTREGDEPTH is n, the read controller is able to process up to nTRs ahead of the write controller.
However, the overall TR pipelining is also subject to the amount of free space in the data FIFO.
14.2.2 Types of EDMA3 Transfers
An EDMA3 transfer is always defined in terms of three dimensions. Figure 14-4 shows the three
dimensions used by EDMA3 transfers. These three dimensions are defined as:
• 1st Dimension or Array (A): The 1st dimension in a transfer consists of ACNT contiguous bytes.
• 2nd Dimension or Frame (B): The 2nd dimension in a transfer consists of BCNT arrays of ACNT bytes.
Each array transfer in the 2nd dimension is separated from each other by an index programmed using
SRCBIDX or DSTBIDX.
• 3rd Dimension or Block (C): The 3rd dimension in a transfer consists of CCNT frames of BCNT arrays
of ACNT bytes. Each transfer in the 3rd dimension is separated from the previous by an index
programmed using SRCCIDX or DSTCIDX.
Note that the reference point for the index depends on the synchronization type. The amount of data
transferred upon receipt of a trigger/synchronization event is controlled by the synchronization types
(SYNCDIM bit in OPT). Of the three dimensions, only two synchronization types are supported: Asynchronized transfers and AB-synchronized transfers.
Figure 14-4. Definition of ACNT, BCNT, and CCNT
ACNT bytes in
Array/1st dimension
Frame 0
Array 1
Array 2
Array BCNT
Frame 1
Array 1
Array 2
Array BCNT
Frame CCNT
Array 1
Array 2
Array BCNT
CCNT frames in
Block/3rd dimmension
BCNT arrays in Frame/2nd dimmension
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14.2.2.1 A-Synchronized Transfers
In an A-synchronized transfer, each EDMA3 sync event initiates the transfer of the 1st dimension of ACNT
bytes, or one array of ACNT bytes. In other words, each event/TR packet conveys the transfer information
for one array only. Thus, BCNT × CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by SRCBIDX and DSTBIDX, as shown in Figure 14-5, where the start
address of Array N is equal to the start address of Array N – 1 plus source (SRCBIDX) or destination
(DSTBIDX).
Frames are always separated by SRCCIDX and DSTCIDX. For A-synchronized transfers, after the frame
is exhausted, the address is updated by adding SRCCIDX/DSTCIDX to the beginning address of the last
array in the frame. As in Figure 14-5, SRCCIDX/DSTCIDX is the difference between the start of Frame 0
Array 3 to the start of Frame 1 Array 0.
Figure 14-5 shows an A-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes.
In this example, a total of 12 sync events (BCNT × CCNT) exhaust a PaRAM set. See Section 14.2.3.6 for
details on parameter set updates.
Figure 14-5. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
Frame 0
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Array 0
Array 1
Array 2
Each array submit
as one TR
Array 3
(SRC|DST)
CIDX
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Frame 1
Array 0
Array 1
Array 2
Array 3
(SRC|DST)
CIDX
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Frame 2
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Array 3
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14.2.2.2 AB-Synchronized Transfers
In a AB-synchronized transfer, each EDMA3 sync event initiates the transfer of 2 dimensions or one
frame. In other words, each event/TR packet conveys information for one entire frame of BCNT arrays of
ACNT bytes. Thus, CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 14-6. Frames are always
separated by SRCCIDX and DSTCIDX.
Note that for AB-synchronized transfers, after a TR for the frame is submitted, the address update is to
add SRCCIDX/DSTCIDX to the beginning address of the beginning array in the frame. This is different
from A-synchronized transfers where the address is updated by adding SRCCIDX/DSTCIDX to the start
address of the last array in the frame. See Section 14.2.3.6 for details on parameter set updates.
Figure 14-6 shows an AB-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT)
bytes. In this example, a total of 3 sync events (CCNT) exhaust a PaRAM set; that is, a total of 3 transfers
of 4 arrays each completes the transfer.
Figure 14-6. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
Frame 0
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Array 0
Array 1
Array 2
(SRC|DST)
(SRC|DST)
BIDX
BIDX
Each array submit
as one TR
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 1
Array 0
Array 1
Array 2
(SRC|DST)
(SRC|DST)
BIDX
BIDX
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 2
Array 0
Array 1
Array 2
Array 3
NOTE: ABC-synchronized transfers are not directly supported. But can be logically achieved by
chaining between multiple AB-synchronized transfers.
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14.2.3 Parameter RAM (PaRAM)
The EDMA3 controller is a RAM-based architecture. The transfer context (source/destination addresses,
count, indexes, etc.) for DMA or QDMA channels is programmed in a parameter RAM table within the
EDMA3CC, referred to as PaRAM. The PaRAM table is segmented into multiple PaRAM sets. Each
PaRAM set includes eight 4-byte PaRAM set entries (32-bytes total per PaRAM set), which includes
typical DMA transfer parameters such as source address, destination address, transfer counts, indexes,
options, etc. See your device-specific data manual for the addresses of the PaRAM set entries.
The PaRAM structure supports flexible ping-pong, circular buffering, channel chaining, and autoreloading
(linking). The first n PaRAM sets are directly mapped to the DMA channels (where n is the number of
DMA channels supported in the EDMA3CC for a specific device). The remaining PaRAM sets can be used
for link entries or associated with QDMA channels. Additionally if the DMA channels are not used, the
PaRAM sets associated with the unused DMA channels can also be used for link entries or QDMA
channels.
NOTE: By default, QDMA channels are mapped to PaRAM set 0. These should be remapped before
use, see Section 14.2.6.2.
14.2.3.1 PaRAM Set
Each parameter set of PaRAM is organized into eight 32-bit words or 32 bytes, as shown in Figure 14-7
and described in Table 14-1. Each PaRAM set consists of 16-bit and 32-bit parameters.
Figure 14-7. PaRAM Set
Set
#
PaRAM
PaRAM set
0
Parameter set 0
OPT
1
Parameter set 1
2
Parameter set 2
3
Parameter set 3
Parameter set n−2
n−1
Parameter set n−1
n
Parameter set n
+4h
ACNT
+8h
SRCBIDX
+10h
BCNTRLD
LINK
+14h
DSTCIDX
SRCCIDX
+18h
Rsvd
CCNT
+1Ch
DST
DSTBIDX
n−2
+0h
SRC
BCNT
Byte
address
offset
+Ch
Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device.
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Table 14-1. EDMA3 Channel Parameter Description
Offset Address
(bytes)
Acronym
Parameter
Description
0h
OPT
Channel Options
Transfer Configuration Options
4h
SRC
Channel Source Address
The byte address from which data is transferred.
ACNT
Count for 1st Dimension
Unsigned value specifying the number of contiguous bytes
within an array (first dimension of the transfer). Valid values
range from 1 to 65 535.
BCNT
Count for 2nd Dimension
Unsigned value specifying the number of arrays in a frame,
where an array is ACNT bytes. Valid values range from 1 to
65 535.
DST
Channel Destination Address
The byte address to which data is transferred.
SRCBIDX
Source BCNT Index
Signed value specifying the byte address offset between
source arrays within a frame (2nd dimension). Valid values
range from –32 768 and 32 767.
DSTBIDX
Destination BCNT Index
Signed value specifying the byte address offset between
destination arrays within a frame (2nd dimension). Valid
values range from –32 768 and 32 767.
LINK
Link Address
The PaRAM address containing the PaRAM set to be linked
(copied from) when the current PaRAM set is exhausted. A
value of FFFFh specifies a null link.
BCNTRLD
BCNT Reload
The count value used to reload BCNT when BCNT
decrements to 0 (TR submitted for the last array in 2nd
dimension). Only relevant in A-synchronized transfers.
SRCCIDX
Source CCNT Index
Signed value specifying the byte address offset between
frames within a block (3rd dimension). Valid values range
from –32 768 and 32 767.
8h (1)
Ch
10h (1)
14h (1)
18h (1)
A-synchronized transfers: The byte address offset from the
beginning of the last source array in a frame to the
beginning of the first source array in the next frame.
AB-synchronized transfers: The byte address offset from the
beginning of the first source array in a frame to the
beginning of the first source array in the next frame.
DSTCIDX
Destination CCNT index
Signed value specifying the byte address offset between
frames within a block (3rd dimension). Valid values range
from –32 768 and 32 767.
A-synchronized transfers: The byte address offset from the
beginning of the last destination array in a frame to the
beginning of the first destination array in the next frame.
AB-synchronized transfers: The byte address offset from the
beginning of the first destination array in a frame to the
beginning of the first destination array in the next frame.
1Ch
(1)
CCNT
Count for 3rd Dimension
Unsigned value specifying the number of frames in a block,
where a frame is BCNT arrays of ACNT bytes. Valid values
range from 1 to 65 535.
RSVD
Reserved
Reserved
If OPT, SRC, or DST is the trigger word for a QDMA transfer then it is required to do a 32-bit access to that field. Furthermore, it is
recommended to perform only 32-bit accesses on the parameter RAM for best code compatibility. For example, switching the endianness
of the processor swaps addresses of the 16-bit fields, but 32-bit accesses avoid the issue entirely.
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14.2.3.2 EDMA3 Channel Parameter Set Fields
14.2.3.2.1
Channel Options Parameter (OPT)
The 32-bit channel options parameter (OPT) specifies the transfer configuration options. The channel
options parameter (OPT) is described in Section 14.4.1.1.
14.2.3.2.2 Channel Source Address (SRC)
The 32-bit source address parameter specifies the starting byte address of the source. For SAM in
increment mode, there are no alignment restrictions imposed by EDMA3. For SAM in constant addressing
mode, you must program the source address to be aligned to a 256-bit aligned address (5 LSBs of
address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 14.2.11.2 for
additional details.
14.2.3.2.3 Channel Destination Address (DST)
The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM
in increment mode, there are no alignment restrictions imposed by EDMA3. For DAM in constant
addressing mode, you must program the destination address to be aligned to a 256-bit aligned address
(5 LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See
Section 14.2.11.2 for additional details.
14.2.3.2.4 Count for 1st Dimension (ACNT)
ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned
value with valid values between 0 and 65 535. Therefore, the maximum number of bytes in an array is
65 535 bytes (64K – 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to
EDMA3TC. A transfer with ACNT equal to 0 is considered either a null or dummy transfer.
See Section 14.2.3.5 and Section 14.2.5.3 for details on dummy/null completion conditions.
14.2.3.2.5 Count for 2nd Dimension (BCNT)
BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal
operation, valid values for BCNT are between 1 and 65 535. Therefore, the maximum number of arrays in
a frame is 65 535 (64K – 1 arrays). A transfer with BCNT equal to 0 is considered either a null or dummy
transfer.
See Section 14.2.3.5 and Section 14.2.5.3 for details on dummy/null completion conditions.
14.2.3.2.6 Count for 3rd Dimension (CCNT)
CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are
between 1 and 65 535. Therefore, the maximum number of frames in a block is 65 535 (64K – 1 frames).
A transfer with CCNT equal to 0 is considered either a null or dummy transfer.
See Section 14.2.3.5 and Section 14.2.5.3 for details on dummy/null completion conditions.
14.2.3.2.7 BCNT Reload (BCNTRLD)
BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the
2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the
EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT reaches 0, the
EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value.
For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC
decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.
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14.2.3.2.8 Source B Index (SRCBIDX)
SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each
array in the 2nd dimension. Valid values for SRCBIDX are between –32 768 and 32 767. It provides a
byte address offset from the beginning of the source array to the beginning of the next source array. It
applies to both A-synchronized and AB-synchronized transfers. Some examples:
• SRCBIDX = 0000h (0): no address offset from the beginning of an array to the beginning of the next
array. All arrays are fixed to the same beginning address.
• SRCBIDX = 0003h (+3): the address offset from the beginning of an array to the beginning of the next
array in a frame is 3 bytes. For example, if the current array begins at address 1000h, the next array
begins at 1003h.
• SRCBIDX = FFFFh (–1): the address offset from the beginning of an array to the beginning of the next
array in a frame is –1 byte. For example, if the current array begins at address 5054h, the next array
begins at 5053h.
14.2.3.2.9 Destination B Index (DSTBIDX)
DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between
each array in the 2nd dimension. Valid values for DSTBIDX are between –32 768 and 32 767. It provides
a byte address offset from the beginning of the destination array to the beginning of the next destination
array within the current frame. It applies to both A-synchronized and AB-synchronized transfers. See
SRCBIDX (Section 14.2.3.2.8) for examples.
14.2.3.2.10 Source C Index (SRCCIDX)
SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the
3rd dimension. Valid values for SRCCIDX are between –32 768 and 32 767. It provides a byte address
offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first
source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that
when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame
(Figure 14-5), while the current array in an AB-synchronized transfer is the first array in the frame
(Figure 14-6).
14.2.3.2.11 Destination C Index (DSTCIDX)
DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the
3rd dimension. Valid values are between –32 768 and 32 767. It provides a byte address offset from the
beginning of the current array (pointed to by DST address) to the beginning of the first destination array
TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when
DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame
(Figure 14-5), while the current array in a AB-synchronized transfer is the first array in the frame
(Figure 14-6).
14.2.3.2.12 Link Address (LINK)
The EDMA3CC provides a mechanism, called linking, to reload the current PaRAM set upon its natural
termination (that is, after the count fields are decremented to 0) with a new PaRAM set. The 16-bit
parameter LINK specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads
the next PaRAM set during linking.
You must program the link address to point to a valid aligned 32-byte PaRAM set. The 5 LSBs of the LINK
field should be cleared to 0.
The EDMA3CC ignores the upper 2 bits of the LINK entry, allowing the programmer the flexibility of
programming the link address as either an absolute/literal byte address or use the PaRAM-base-relative
offset address. Therefore, if you make use of the literal address with a range from 4000h to 7FFFh, it will
be treated as a PaRAM-base-relative value of 0000h to 3FFFh.
You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM
address that falls in the range of the available PaRAM addresses on the device.
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A LINK value of FFFFh is referred to as a NULL link that should cause the EDMA3CC to perform an
internal write of 0 to all entries of the current PaRAM set, except for the LINK field that is set to FFFFh.
Also, see Section 14.2.5 for details on terminating a transfer.
14.2.3.3 Null PaRAM Set
A null PaRAM set is defined as a PaRAM set where all count fields (ACNT, BCNT, and CCNT) are
cleared to 0. If a PaRAM set associated with a channel is a NULL set, then when serviced by the
EDMA3CC, the bit corresponding to the channel is set in the associated event missed register (EMR or
QEMR). This bit remains set in the associated secondary event register (SER or QSER). This implies that
any future events on the same channel are ignored by the EDMA3CC and you are required to clear the bit
in SER or QSER for the channel. This is considered an error condition, since events are not expected on
a channel that is configured as a null transfer. See Section 14.4.2.5.8 and Section 14.4.2.2.1 for more
information on the SER and EMR registers, respectively.
14.2.3.4 Dummy PaRAM Set
A dummy PaRAM set is defined as a PaRAM set where at least one of the count fields (ACNT, BCNT, or
CCNT) is cleared to 0 and at least one of the count fields is nonzero.
If a PaRAM set associated with a channel is a dummy set, then when serviced by the EDMA3CC, it will
not set the bit corresponding to the channel (DMA/QDMA) in the event missed register (EMR or QEMR)
and the secondary event register (SER or QSER) bit gets cleared similar to a normal transfer. Future
events on that channel are serviced. A dummy transfer is a legal transfer of 0 bytes. See
Section 14.4.2.5.8 and Section 14.4.2.2.1 for more information on the SER and EMR registers,
respectively.
14.2.3.5 Dummy Versus Null Transfer Comparison
There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request.
A null transfer request is an error condition, but a dummy transfer is a legal transfer of 0 bytes. A null
transfer causes an error bit (En) in EMR to get set and the En bit in SER remains set, essentially
preventing any further transfers on that channel without clearing the associated error registers.
Table 14-2 summarizes the conditions and effects of null and dummy transfer requests.
Table 14-2. Dummy and Null Transfer Request
Feature
Null TR
Dummy TR
EMR/QEMR is set
Yes
No
SER/QSER remains set
Yes
No
Link update (STATIC = 0 in OPT)
Yes
Yes
QER is set
Yes
Yes
IPR and CER is set using early completion
Yes
Yes
14.2.3.6 Parameter Set Updates
When a TR is submitted for a given DMA/QDMA channel and its corresponding PaRAM set, the
EDMA3CC is responsible for updating the PaRAM set in anticipation of the next trigger event. For nonfinal
events, this includes address and count updates; for final events, this includes the link update.
The specific PaRAM set entries that are updated depend on the channel’s synchronization type (Asynchronized or B-synchronized) and the current state of the PaRAM set. A B-update refers to the
decrementing of BCNT in the case of A-synchronized transfers after the submission of successive TRs. A
C-update refers to the decrementing of CCNT in the case of A-synchronized transfers after BCNT TRs for
ACNT byte transfers have submitted. For AB-synchronized transfers, a C-update refers to the
decrementing of CCNT after submission of every transfer request.
See Table 14-3 for details and conditions on the parameter updates. A link update occurs when the
PaRAM set is exhausted, as described in Section 14.2.3.7.
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After the TR is read from the PaRAM (and is in process of being submitted to EDMA3TC), the following
fields are updated if needed:
• A-synchronized: BCNT, CCNT, SRC, DST
• AB-synchronized: CCNT, SRC, DST
The following fields are not updated (except for during linking, where all fields are overwritten by the link
PaRAM set):
• A-synchronized: ACNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK
• AB-synchronized: ACNT, BCNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK
Note that PaRAM updates only pertain to the information that is needed to properly submit the next
transfer request to the EDMA3TC. Updates that occur while data is moved within a transfer request are
tracked within the transfer controller, and is detailed in Section 14.2.11. For A-synchronized transfers, the
EDMA3CC always submits a TRP for ACNT bytes (BCNT = 1 and CCNT = 1). For AB-synchronized
transfers, the EDMA3CC always submits a TRP for ACNT bytes of BCNT arrays (CCNT = 1). The
EDMA3TC is responsible for updating source and destination addresses within the array based on ACNT
and FWID (in OPT). For AB-synchronized transfers, the EDMA3TC is also responsible to update source
and destination addresses between arrays based on SRCBIDX and DSTBIDX.
Table 14-3 shows the details of parameter updates that occur within EDMA3CC for A-synchronized and
AB-synchronized transfers.
Table 14-3. Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set)
A-Synchronized Transfer
AB-Synchronized Transfer
B-Update
C-Update
Link Update
BCNT == 1 &&
CCNT == 1
B-Update
C-Update
Link Update
BCNT > 1
BCNT == 1 &&
CCNT > 1
N/A
CCNT > 1
SRC
+= SRCBIDX
+= SRCCIDX
= Link.SRC
in EDMA3TC
+= SRCCIDX
= Link.SRC
DST
+= DSTBIDX
+= DSTCIDX
= Link.DST
in EDMA3TC
+= DSTCIDX
= Link.DST
Condition:
CCNT == 1
ACNT
None
None
= Link.ACNT
None
None
= Link.ACNT
BCNT
–= 1
= BCNTRLD
= Link.BCNT
in EDMA3TC
N/A
= Link.BCNT
CCNT
None
–= 1
= Link.CCNT
in EDMA3TC
–=1
= Link.CCNT
SRCBIDX
None
None
= Link.SRCBIDX
in EDMA3TC
None
= Link.SRCBIDX
DSTBIDX
None
None
= Link.DSTBIDX
None
None
= Link.DSTBIDX
SRCCIDX
None
None
= Link.SRCBIDX
in EDMA3TC
None
= Link.SRCBIDX
DSTCIDX
None
None
= Link.DSTBIDX
None
None
= Link.DSTBIDX
LINK
None
None
= Link.LINK
None
None
= Link.LINK
BCNTRLD
None
None
= Link.BCNTRLD
None
None
= Link.BCNTRLD
OPT (1)
None
None
= LINK.OPT
None
None
= LINK.OPT
(1)
In all cases, no updates occur if OPT.STATIC == 1 for the current PaRAM set.
NOTE: The EDMA3CC includes no special hardware to detect when an indexed address update
calculation overflows/underflows. The address update will wrap across boundaries as
programmed by the user. You should ensure that no transfer is allowed to cross internal port
boundaries between peripherals. A single TR must target a single source/destination slave
endpoint.
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14.2.3.7 Linking Transfers
The EDMA3CC provides a mechanism known as linking, which allows the entire PaRAM set to be
reloaded from a location within the PaRAM memory map (for both DMA and QDMA channels). Linking is
especially useful for maintaining ping-pong buffers, circular buffering, and repetitive/continuous transfers
all with no CPU intervention. Upon completion of a transfer, the current transfer parameters are reloaded
with the parameter set pointed to by the 16-bit link address field (of the current parameter set). Linking
only occurs when the STATIC bit in OPT is cleared to 0.
NOTE: A transfer (DMA or QDMA) should always be linked to another useful transfer. If it is required
to terminate a transfer, the transfer should be linked to a NULL set.
The link update occurs after the current PaRAM set event parameters have been exhausted. An event's
parameters are exhausted when the EDMA3 channel controller has submitted all the transfers associated
with the PaRAM set.
A link update occurs for null and dummy transfers depending on the state of the STATIC bit in OPT and
the LINK field. In both cases (null or dummy), if the value of LINK is FFFFh then a null PaRAM set (with all
0s and LINK set to FFFFh) is written to the current PaRAM set. Similarly, if LINK is set to a value other
than FFFFh then the appropriate PaRAM location pointed to by LINK is copied to the current PaRAM set.
Once the channel completion conditions are met for an event, the transfer parameters located at the link
address are loaded into the current DMA or QDMA channel’s associated parameter set. The EDMA3CC
reads the entire PaRAM set (8 words) from the PaRAM set specified by LINK and writes all 8 words to the
PaRAM set associated with the current channel. Figure 14-8 shows an example of a linked transfer.
Any PaRAM set in the PaRAM can be used as a link/reload parameter set; however, it is recommended
that the PaRAM sets associated with peripheral synchronization events (see Section 14.2.6) should only
be used for linking if the synchronization event isolated with the channel mapped to that PaRAM set is
disabled.
If a PaRAM set location is mapped to a QDMA channel (by QCHMAPn), then copying the link PaRAM set
onto the current QDMA channel PaRAM set is recognized as a trigger event and is latched in QER since a
write to the trigger word was performed. This feature can be used to create a linked list of transfers using
a single QDMA channel and multiple PaRAM sets.
Link-to-self transfers replicate the behavior of autoinitialization, which facilitates the use of circular
buffering and repetitive transfers. After an EDMA3 channel exhausts its current PaRAM set, it reloads all
the parameter set entries from another PaRAM set, which is initialized with values identical to the original
PaRAM set. Figure 14-9 shows an example of a linked-to-self transfer. In Figure 14-9, parameter set 127
has the LINK field address pointing to the address of parameter set 127, that is, linked-to-self.
NOTE: If the STATIC bit in OPT is set for a PaRAM set, then link updates are not performed. The
link updates performed internally by the EDMA3CC are atomic. This implies that when the
EDMA3CC is updating a PaRAM set, accesses to PaRAM by other EDMA3 programmer's
(for example, CPU configuration accesses) are not allowed. Also for QDMA, for example, if
the first word of the PaRAM entry is defined as a trigger word, EDMA3CC logic assures that
all 8 PaRAM words are updated before the new QDMA event can trigger the transfer for that
PaRAM entry.
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14.2.3.7.1 Constant Addressing Mode Transfers/Alignment Issues
If either SAM or DAM is set to 1 (constant addressing mode), then the source or destination address must
be aligned to a 256-bit aligned address, respectively, and the corresponding BIDX should be an even
multiple of 32 bytes (256 bit). The EDMA3CC does not recognize errors here but the EDMA3TC asserts
an error, if this is not true. See Section 14.2.11.2.
NOTE: The constant addressing (CONST) mode has limited applicability. The EDMA3 should be
configured for the constant addressing mode (SAM/DAM = 1) only if the transfer source or
destination (on-chip memory, off-chip memory controllers, slave peripherals) support the
constant addressing mode. See your device-specific data manual to verify if constant
addressing mode is supported. If the constant addressing mode is not supported, the similar
logical transfer can be achieved using the increment (INCR) mode (SAM/DAM = 0) by
appropriately programming the count and indices values.
14.2.3.7.2 Element Size
The EDMA3 controller does not use the concept of element-size and element-indexing. Instead, all
transfers are defined in terms of all three dimensions: ACNT, BCNT, and CCNT. An element-indexed
transfer is logically achieved by programming ACNT to the size of the element and BCNT to the number of
elements that need to be transferred. For example, if you have 16-bit audio data and 256 audio samples
that needed to be transferred to a serial port, this can be done by programming the ACNT = 2 (2 bytes)
and BCNT = 256.
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Figure 14-8. Linked Transfer Example
(a) At initialization
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
BCNTRLD X Link X=4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Parameter set 126
Parameter set 127
(b) After completion of PaRAM set 3
(link update)
OPT Y
SRC Y
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT Y
SRC Y
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Parameter set 126
Parameter set 127
(c) After completion of PaRAM set 127
(link to null set)
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT Y
SRC Y
Link
update
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
PaRAM set 3 (Null PaRAM set)
0h
0h
0h
0h
0h
01C0 4FC0h
1CA0 4FE0h
352
126
127
Parameter set 126
Parameter set 127
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0h
0h
0h
0h
0h
Link=FFFFh
0h
0h
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Figure 14-9. Link-to-Self Transfer Example
(a) At initialization
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
BCNTRLD X
Link=4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Parameter set 126
Parameter set 127
(b) After completion of PaRAM set 3
(link update)
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X Link =4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X Link =4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Parameter set 126
Parameter set 127
(c) After completion of PaRAM set 127
(link to self)
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
Link
update
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X Link =4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 3
OPT X
SRC X
BCNT X
01C0 4FC0h
1CA0 4FE0h
126
127
Parameter set 126
Parameter set 127
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ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link=4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
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14.2.4 Initiating a DMA Transfer
There are multiple ways to initiate a programmed data transfer using the EDMA3 channel controller.
Transfers on DMA channels are initiated by three sources:
• Event-triggered transfer request (this is the more typical usage of EDMA3): Allows for a peripheral,
system, or externally-generated event to trigger a transfer request.
• Manually-triggered transfer request: The CPU manually triggers a transfer by writing a 1 to the
corresponding bit in the event set register (ESR).
• Chain-triggered transfer request: A transfer is triggered on the completion of another transfer or
subtransfer.
Transfers on QDMA channels are initiated by two sources:
• Autotriggered transfer request: A transfer is triggered when the PaRAM set entry programmed
trigger word is written to.
• Link-triggered transfer requests: When linking occurs, the transfer is triggered when the PaRAM set
entry programmed trigger word is written to.
14.2.4.1 DMA Channel
14.2.4.1.1 Event-Triggered Transfer Request
When an event is asserted from a peripheral or device pins, it gets latched in the corresponding bit of the
event register (ER.En = 1). If the corresponding event in the event enable register (EER) is enabled
(EER.En = 1), then the EDMA3CC prioritizes and queues the event in the appropriate event queue. When
the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
If the PaRAM set is valid (not a NULL set), then a transfer request packet (TRP) is submitted to the
EDMA3TC and the En bit in ER is cleared. At this point, a new event can be safely received by the
EDMA3CC.
If the PaRAM set associated with the channel is a NULL set (see Section 14.2.3.3), then no transfer
request (TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the
corresponding channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was
discarded due to a null TR being serviced. Good programming practices should include cleaning the event
missed error before retriggering the DMA channel.
When an event is received, the corresponding event bit in the event register is set (ER.En = 1), regardless
of the state of EER.En. If the event is disabled when an external event is received (ER.En = 1 and
EER.En = 0), the ER.En bit remains set. If the event is subsequently enabled (EER.En = 1), then the
pending event is processed by the EDMA3CC and the TR is processed/submitted, after which the ER.En
bit is cleared.
If an event is being processed (prioritized or is in the event queue) and another sync event is received for
the same channel prior to the original being cleared (ER.En != 0), then the second event is registered as a
missed event in the corresponding bit of the event missed register (EMR.En = 1).
For the synchronization events associated with each of the programmable DMA channels, see your
device-specific data manual to determine the event to channel mapping.
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14.2.4.1.2 Manually-Triggered Transfer Request
A DMA transfer is initiated by a write to the event set register (ESR) by the CPU (or any EDMA
programmer). Writing a 1 to an event bit in the ESR results in the event being prioritized/queued in the
appropriate event queue, regardless of the state of the EER.En bit. When the event reaches the head of
the queue, it is evaluated for submission as a transfer request to the transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If the PaRAM set associated with the channel is a NULL set (see Section 14.2.3.3), then no transfer
request (TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the
corresponding channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was
discarded due to a null TR being serviced. Good programming practices should include clearing the event
missed error before retriggering the DMA channel.
If an event is being processed (prioritized or is in the event queue) and the same channel is manually set
by a write to the corresponding channel bit of the event set register (ESR.En = 1) prior to the original
being cleared (ESR.En = 0), then the second event is registered as a missed event in the corresponding
bit of the event missed register (EMR.En = 1).
14.2.4.1.3 Chain-Triggered Transfer Request
Chaining is a mechanism by which the completion of one transfer automatically sets the event for another
channel. When a chained completion code is detected, the value of which is dictated by the transfer
completion code (TCC[5:0] in OPT of the PaRAM set associated with the channel), it results in the
corresponding bit in the chained event register (CER) to be set (CER.E[TCC] = 1).
Once a bit is set in CER, the EDMA3CC prioritizes and queues the event in the appropriate event queue.
When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If the PaRAM set associated with the channel is a NULL set (see Section 14.2.3.3), then no transfer
request (TR) is submitted and the corresponding En bit in CER is cleared and simultaneously the
corresponding channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was
discarded due to a null TR being serviced. In this case, the error condition must be cleared by you before
the DMA channel can be retriggered. Good programming practices might include clearing the event
missed error before retriggering the DMA channel.
If a chaining event is being processed (prioritized or queued) and another chained event is received for
the same channel prior to the original being cleared (CER.En != 0), then the second chained event is
registered as a missed event in the corresponding channel bit of the event missed register (EMR.En = 1).
NOTE: Chained event registers, event registers, and event set registers operate independently. An
event (En) can be triggered by any of the trigger sources (event-triggered, manuallytriggered, or chain-triggered).
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14.2.4.2 QDMA Channels
14.2.4.2.1 Autotriggered and Link-Triggered Transfer Request
NOTE: If OPT, SRC, or DST is the trigger word for a QDMA transfer then it is required to do a 32-bit
access to that field.
QDMA-based transfer requests are issued when a QDMA event gets latched in the QDMA event register
(QER.En = 1). A bit corresponding to a QDMA channel is set in the QDMA event register (QER) when the
following occurs:
• A CPU (or any EDMA3 programmer) write occurs to a PaRAM address that is defined as a QDMA
channel trigger word (programmed in the QDMA channel n mapping register (QCHMAPn)) for the
particular QDMA channel and the QDMA channel is enabled via the QDMA event enable register
(QEER.En = 1).
• EDMA3CC performs a link update on a PaRAM set address that is configured as a QDMA channel
(matches QCHMAPn settings) and the corresponding channel is enabled via the QDMA event enable
register (QEER.En = 1).
Once a bit is set in QER, the EDMA3CC prioritizes and queues the event in the appropriate event queue.
When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If a bit is already set in QER (QER.En = 1) and a second QDMA event for the same QDMA channel
occurs prior to the original being cleared, the second QDMA event gets captured in the QDMA event miss
register (QEMR.En = 1).
14.2.4.3 Comparison Between DMA and QDMA Channels
The primary difference between DMA and QDMA channels is the event/channel synchronization. QDMA
events are either autotriggered or link triggered. Autotriggering allows QDMA channels to be triggered by
CPU(s) with a minimum number of linear writes to PaRAM. Link triggering allows a linked list of transfers
to be executed, using a single QDMA PaRAM set and multiple link PaRAM sets.
A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the
QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM
set that has been mapped to a QDMA channel (link triggered). Note that for CPU triggered (manually
triggered) DMA channels, in addition to writing to the PaRAM set, it is required to write to the event set
register (ESR) to kick-off the transfer.
QDMA channels are typically for cases where a single event will accomplish a complete transfer since the
CPU (or EDMA3 programmer) must reprogram some portion of the QDMA PaRAM set in order to retrigger
the channel. In other words, QDMA transfers are programmed with BCNT = CCNT = 1 for A-synchronized
transfers, and CCNT = 1 for AB-synchronized transfers.
Additionally, since linking is also supported (if STATIC = 0 in OPT) for QDMA transfers, it allows you to
initiate a linked list of QDMAs, so when EDMA3CC copies over a link PaRAM set (including the write to
the trigger word), the current PaRAM set mapped to the QDMA channel will automatically be recognized
as a valid QDMA event and initiate another set of transfers as specified by the linked set.
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14.2.5 Completion of a DMA Transfer
A parameter set for a given channel is complete when the required number of transfer requests is
submitted (based on receiving the number of synchronization events). The expected number of TRs for a
non-null/non-dummy transfer is shown in Table 14-4 for both synchronization types along with state of the
PaRAM set prior to the final TR being submitted. When the counts (BCNT and/or CCNT) are this value,
the next TR results in a:
• Final chaining or interrupt codes to be sent by the transfer controllers (instead of intermediate).
• Link updates (linking to either null or another valid link set).
Table 14-4. Expected Number of Transfers for Non-Null Transfer
Sync Mode
Counts at time 0
Total # Transfers
Counts prior to final TR
A-synchronized
ACNT
BCNT
CCNT
(BCNT × CCNT ) TRs of ACNT bytes each
BCNT == 1 && CCNT == 1
AB-synchronized
ACNT
BCNT
CCNT
CCNT TRs for ACNT × BCNT bytes each
CCNT == 1
You must program the PaRAM OPT field with a specific transfer completion code (TCC) along with the
other OPT fields (TCCHEN, TCINTEN, ITCCHEN, and ITCINTEN bits) to indicate whether the completion
code is to be used for generating a chained event or/and for generating an interrupt upon completion of a
transfer.
The specific TCC value (6-bit binary value) programmed dictates which of the 64-bits in the chain event
register (CER[TCC]) and/or interrupt pending register (IPR[TCC]) is set.
See Section 14.2.9 for details on interrupts and Section 14.2.8 for details on chaining.
You can also selectively program whether the transfer controller sends back completion codes on
completion of the final transfer request (TR) of a parameter set (TCCHEN or TCINTEN), for all but the
final transfer request (TR) of a parameter set (ITCCHEN or ITCINTEN), or for all TRs of a parameter set
(both). See Section 14.2.8 for details on chaining (intermediate/final chaining) and Section 14.2.9 for
details on intermediate/final interrupt completion.
A completion detection interface exists between the EDMA3 channel controller and transfer controller(s).
This interface sends back information from the transfer controller to the channel controller to indicate that
a specific transfer is completed.
All DMA/QDMA PaRAM sets must also specify a link address value. For repetitive transfers such as pingpong buffers, the link address value should point to another predefined PaRAM set. Alternatively, a
nonrepetitive transfer should set the link address value to the null link value. The null link value is defined
as FFFFh. See Section 14.2.3.7 for more details.
NOTE: Any incoming events that are mapped to a null PaRAM set results in an error condition. The
error condition should be cleared before the corresponding channel is used again. See
Section 14.2.3.5.
There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal
completion, early completion, and dummy/null completion. This applies to both chained events and
completion interrupt generation.
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14.2.5.1 Normal Completion
In normal completion mode (TCCMODE = 0 in OPT), the transfer or sub-transfer is considered to be
complete when the EDMA3 channel controller receives the completion codes from the EDMA3 transfer
controller. In this mode, the completion code to the channel controller is posted by the transfer controller
after it receives a signal from the destination peripheral. Normal completion is typically used to generate
an interrupt to inform the CPU that a set of data is ready for processing.
14.2.5.2 Early Completion
In early completion mode (TCCMODE = 1 in OPT), the transfer is considered to be complete when the
EDMA3 channel controller submits the transfer request (TR) to the EDMA3 transfer controller. In this
mode, the channel controller generates the completion code internally. Early completion is typically useful
for chaining, as it allows subsequent transfers to be chained-triggered while the previous transfer is still in
progress within the transfer controller, maximizing the overall throughput of the set of the transfers.
14.2.5.3 Dummy or Null Completion
This is a variation of early completion. Dummy or null completion is associated with a dummy set
(Section 14.2.3.4) or null set (Section 14.2.3.3). In both cases, the EDMA3 channel controller does not
submit the associated transfer request to the EDMA3 transfer controller(s). However, if the set
(dummy/null) has the OPT field programmed to return completion code (intermediate/final
interrupt/chaining completion), then it will set the appropriate bits in the interrupt pending register (IPR) or
chained event register (CER). The internal early completion path is used by the channel controller to
return the completion codes internally (that is, EDMA3CC generates the completion code).
14.2.6 Event, Channel, and PaRAM Mapping
Most of the DMA channels are tied to a specific hardware peripheral event, thus allowing transfers to be
triggered by events from device peripherals or external hardware. A DMA channel typically requests a
data transfer when it receives its event (apart from manually-triggered, chain-triggered, and other
transfers). The amount of data transferred per synchronization event depends on the channel’s
configuration (ACNT, BCNT, CCNT, etc.) and the synchronization type (A-synchronized or ABsynchronized).
The association of an event to a channel is fixed. Each of the DMA channels has one specific event
associated with it. For the synchronization events associated with each of the programmable DMA
channels, see your device-specific data manual to determine the event to channel mapping.
If in an application, a channel does not make use of the associated synchronization event or does not
have an associated synchronization event (unused), that channel can be used for manually-triggered or
chained-triggered transfers, for linking/reloading, or as a QDMA channel.
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14.2.6.1 DMA Channel to PaRAM Mapping
The mapping between the DMA channel numbers and the PaRAM sets is a fixed, one-to-one mapping
(see Table 14-5). In other words, channel (event) 0 is mapped to PaRAM set 0, channel (event 1) is
mapped to PaRAM set 1, etc. So, for example, in order to program a transfer for event number 3, DMA
channel 3 is associated with PaRAM set number 3 and you need to program this PaRAM set for
configuring transfers associated with event number 3. See your device-specific data manual for the
addresses of the PaRAM set entries.
Table 14-5. EDMA3 DMA Channel to PaRAM Mapping
PaRAM Set Number
Mapping
PaRAM Set 0
DMA Channel 0/Reload/QDMA
PaRAM Set 1
DMA Channel 1/Reload/QDMA
PaRAM Set 2
DMA Channel 2/Reload/QDMA
PaRAM Set 3
DMA Channel 3/Reload/QDMA
PaRAM Set 4
DMA Channel 4/Reload/QDMA
PaRAM Set 5
DMA Channel 5/Reload/QDMA
PaRAM Set 6
DMA Channel 6/Reload/QDMA
PaRAM Set 7
DMA Channel 7/Reload/QDMA
PaRAM Set 8
DMA Channel 8/Reload/QDMA
PaRAM Set 9
DMA Channel 9/Reload/QDMA
PaRAM Set 10
DMA Channel 10/Reload/QDMA
PaRAM Set 11
DMA Channel 11/Reload/QDMA
PaRAM Set 12
DMA Channel 12/Reload/QDMA
PaRAM Set 13
DMA Channel 13/Reload/QDMA
PaRAM Set 14
DMA Channel 14/Reload/QDMA
PaRAM Set 15
DMA Channel 15/Reload/QDMA
PaRAM Set 16
DMA Channel 16/Reload/QDMA
...
...
PaRAM Set 30
DMA Channel 30/Reload/QDMA
PaRAM Set 31
DMA Channel 31/Reload/QDMA
PaRAM Set 32
Reload/QDMA
PaRAM Set 33
Reload/QDMA
...
...
PaRAM Set n - 2
Reload/QDMA
PaRAM Set n - 1
Reload/QDMA
PaRAM Set n
Reload/QDMA
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14.2.6.2 QDMA Channel to PaRAM Mapping
The mapping between the QDMA channels and the PaRAM sets is programmable .The QDMA channel n
mapping register (QCHMAPn) in the EDMA3CC provides programmability for the QDMA channels to be
mapped to any of the PaRAM sets in the PaRAM memory map. Figure 14-10 illustrates the use of
QCHMAP.
Additionally, QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel. A
trigger word is one of the 8 words in the PaRAM set. For a QDMA transfer to occur, a valid TR
synchronization event for EDMA3CC is a write to the trigger word in the PaRAM set pointed to by
QCHMAP for a particular QDMA channel.
NOTE:
By default, QDMA channels are mapped to PaRAM set 0. Care must be taken to
appropriately remap PaRAM set 0 before it is used.
Figure 14-10. QDMA Channel to PaRAM Mapping
31
QCHMAPn
14 13
0000 0000 0000 00
Set
#
5 4
PAENTRY
00 0000 011
2 1 0
TR WORD
1 11
PaRAM
PaRAM set
00
Byte
address
offset
0
Parameter set 0
OPT
+0h
1
Parameter set 1
SRC
+4h
2
Parameter set 2
3
Parameter set 3
n−2
Parameter set n−2
n−1
Parameter set n−1
n
Parameter set n
BCNT
ACNT
DST
+8h
+Ch
DSTBIDX
SRCBIDX
+10h
BCNTRLD
LINK
+14h
DSTCIDX
SRCCIDX
Rsvd
CCNT
+18h
+1Ch
Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device.
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14.2.7 EDMA3 Channel Controller Regions
The EDMA3 channel controller (EDMA3CC) divides its address space into multiple regions. Individual
channel resources can be exclusively assigned to a specific region, where each region is typically
assigned to a specific EDMA programmer. This allows partitioning of EDMA channel (DMA/QDMA)
resources in hetero- or multi-core devices, and devices where certain additional masters (for example,
coprocessors) can also program/initiate EDMA3 transfers. The application software running on these
cores/coprocessors can operate in these exclusive shadow region memory-maps, minimizing possibilities
of resource conflicts.
14.2.7.1 Region Overview
The EDMA3CC memory-mapped registers are divided in three main categories:
1. Global registers
2. Global region channel registers
3. Shadow region channel registers
The global registers are located at a single/fixed location in the EDMA3CC memory map. These registers
control EDMA3 resource mapping and provide debug visibility and error tracking information. See your
device-specific data manual for the EDMA3CC memory map.
The channel registers (including DMA, QDMA, and interrupt registers) are accessible via the global
channel region address range, or in the shadow n channel region address range(s). For example, the
event enable register (EER) is visible in the global region register space at offset 1020h, or region
addresses at offset 2020h for region 0 and at offset 2220h for region 1.
The underlying control register bits that are accessible via the shadow region address space (except for
IEVALn) are controlled by the DMA region access enable registers (DRAEm) and QDMA region access
enable registers (QRAEm). Table 14-6 lists the registers in the shadow region memory-map. (See
EDMA3CC memory-map figure for the complete global and shadow region memory-maps.) Figure 14-11
illustrates the conceptual view of the regions (where n is the number of shadow regions supported in the
EDMA3CC for a specific device).
Table 14-6. Shadow Region Registers
DRAEm
QRAEm
ER
QER
ECR
QEER
ESR
QEECR
CER
QEESR
EER
EECR
EESR
SER
SECR
IER
IECR
IESR
IPR
ICR
Register not affected by DRAE
IEVAL
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Figure 14-11. Shadow Region Registers
Shadow region 0
Access address
01C0 2000h
01C0 2094h
except IEVAL
ER
DRAE0
QSECR
IEVAL
QRAE0
Shadow region 0
registers
Physical register
ER
ECR
ESR
CER
EER
EECR
EESR
SER
SECR
01C0 1000h
IER
IECR
IESR
IPR
ICR
IEVAL
ER
Access address
01C0 2600h
01C0 2694h
DRAE3
QSECR
IEVAL
QRAE3
QER
QEER
QEECR
QEESR
QSER
QSECR
01C0 1094h
Shadow region 3
registers
14.2.7.2 Channel Controller Shadow Regions
For each EDMA3 shadow region (and associated memory-maps) there is a set of registers associated
with the shadow region that allows association of the DMA/QDMA channels and interrupt completion
codes to the region. These registers are user-programmed per region to assign ownership of the
DMA/QDMA channels and TCC values to a region.
• DRAEm: One register exists for each of the shadow regions. The number of bits in each register
matches the number of DMA channels. These registers need to be programmed to assign ownership
of DMA channels to the respective region. Accesses to DMA event registers and interrupt registers via
the shadow region address map are filtered through DRAE. A value of 1 in the corresponding DRAE bit
implies that the corresponding DMA/interrupt channel is accessible; a value of 0 in the corresponding
DRAE bit forces writes to be discarded and returns a value of 0 for reads.
• QRAEm: One register exists for every region. The number of bits in each register matches the number
of QDMA channels. These registers must be programmed to assign ownership of QDMA channels to
the respective region. To enable a channel in a shadow region using shadow region 0 QEER, the
respective bit in QRAE must be set or writing into QEESR will not have the desired effect.
It is typical for an application to have a unique assignment of QDMA/DMA channels (and, therefore, a
given bit position) to a given region.
The use of shadow regions allows for restricted access to EDMA3 resources (DMA channels, QDMA
channels, TCC, interrupts) by tasks/cores/EDMA3 programmers in a system by setting or clearing bits in
the DRAE/QRAE registers. If exclusive access to any given channel/TCC code is required for a region,
then only that region's DRAE/QRAE should have the associated bit set.
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Additionally, with each shadow region, there is an associated shadow region completion interrupt
(EDMA3CC_INTn where n denotes the shadow region number). For multi-core/hetero-core devices, the
various shadow region interrupts might be tied to the interrupt controllers for different cores. For single
core devices, all shadow region interrupts would be routed to the device interrupt controller. See your
device-specific data manual for the shadow region interrupt hookup to the device interrupt controller(s).
The DRAE associated with each shadow region acts as a secondary interrupt enable (along with the
interrupt enable register) for the respective shadow region interrupts. See Section 14.2.9 for more
information on interrupts.
Example 14-1. Resource Pool Division Across Two Regions
This example illustrates a resource pool division across two regions, assuming region 0 must be allocated 16
DMA channels (0-15) and 1 QDMA channel (0), and 16 TCC codes (0-15). Region 1 needs to be allocated 16
DMA channels (16-31) and 7 QDMA channels (1-7), and 16 TCC codes (16-31). DRAE should be equal to the
OR of the bits that are required for the DMA channels and the TCC codes:
Region 0: DRAE = 0x0000FFFF QRAE = 0x00000001 Region 1: DRAE = 0xFFFF0000 QRAE = 0x000000FE
14.2.8 Chaining EDMA3 Channels
The channel chaining capability for the EDMA3 allows the completion of an EDMA3 channel transfer to
trigger another EDMA3 channel transfer. The purpose is to allow you the ability to chain several events
through one event occurrence.
Chaining is different from linking (Section 14.2.3.7). The EDMA3 link feature reloads the current channel
parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any
channel parameter set; it provides a synchronization event to the chained channel (see Section 14.2.4.1.3
for chain-triggered transfer requests).
Chaining is achieved at either final transfer completion or intermediate transfer completion, or both, of the
current channel. Consider a channel m (DMA/QDMA) required to chain to channel n. Channel number n
(0-31) needs to be programmed into the TCC field of channel m channel options parameter (OPT) set.
• If final transfer completion chaining (TCCHEN = 1 and ITCCHEN = 0 in channel m OPT) is enabled,
the chain-triggered event occurs after the last transfer request of channel m is submitted (early
completion) or completed (normal completion).
• If intermediate transfer completion chaining (TCCHEN = 0 and ITCCHEN = 0 in channel m OPT) is
enabled, the chain-triggered event occurs after every intermediate transfer request of channel m is
submitted (early completion) or completed (normal completion).
• If both final and intermediate transfer completion chaining (TCCHEN = 1 and ITCCHEN = 1 in channel
m OPT) are enabled, the chain-trigger event occurs after every transfer request of channel m is
submitted (early completion) or completed (normal completion).
Table 14-7 shows the number of chain event triggers occurring in different synchronized scenarios.
Consider channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 14-7. Chain Event Triggers
(Number of chained event triggers on channel 30)
Options
A-Synchronized
AB-Synchronized
TCCHEN = 1, ITCCHEN = 0
1 (Last TR)
1 (Last TR)
TCCHEN = 0, ITCCHEN = 1
19 (All but the last TR)
4 (All but the last TR)
TCCHEN = 1, ITCCHEN = 1
20 (All TRs)
5 (All TRs)
14.2.9 EDMA3 Interrupts
The EDMA3 interrupts are divided into 2 categories:
• Transfer completion interrupts
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Error interrupts
The transfer completion interrupts are listed in Table 14-8. The error interrupts are listed in Table 14-9.
Table 14-8. EDMA3 Transfer Completion Interrupts
Name
Description
EDMA3_0_CC0_INT0
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt
AINTC
11
EDMA3_0_CC0_INT1
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
—
EDMA3_0_CC0_INT2
EDMA3_0 Channel Controller 0 Shadow Region 2 Transfer Completion Interrupt
—
EDMA3_0_CC0_INT3
EDMA3_0 Channel Controller 0 Shadow Region 3 Transfer Completion Interrupt
—
EDMA3_1_CC0_INT0
EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt
93
EDMA3_1_CC0_INT1
EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
—
EDMA3_1_CC0_INT2
EDMA3_1 Channel Controller 0 Shadow Region 2 Transfer Completion Interrupt
—
EDMA3_1_CC0_INT3
EDMA3_1 Channel Controller 0 Shadow Region 3 Transfer Completion Interrupt
—
Table 14-9. EDMA3 Error Interrupts
Name
Description
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrupt
AINTC
12
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrupt
13
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrupt
32
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrupt
94
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrupt
95
14.2.9.1 Transfer Completion Interrupts
The EDMA3CC is responsible for generating transfer completion interrupts to the CPU. The EDMA3
generates a single completion interrupt per shadow region on behalf of all DMA/QDMA channels. Various
control registers and bit fields facilitate EDMA3 interrupt generation.
The transfer completion code (TCC) value is directly mapped to the bits of the interrupt pending register
(IPR), as shown in Table 14-10. For example, if TCC = 00 0000b, IPR[0] is set after transfer completion,
and results in an interrupt generation to the CPU if in the EDMA3CC and device interrupt controller are
configured to allow a CPU interrupt. See Section 14.2.9.1.1 for details on enabling EDMA3 transfer
completion interrupts.
When a completion code is returned (as a result of early or normal completion), the corresponding bit in
IPR is set. For the completion code to be returned, the PaRAM set associated with the transfer must
enable the transfer completion interrupt (final/intermediate) in the channel options parameter (OPT).
The transfer completion code (TCC) can be programmed to any value for a DMA/QDMA channel. There
does not need to be a direct relation between the channel number and the transfer completion code value.
This allows multiple channels having the same transfer completion code value to cause a CPU to execute
the same interrupt service routine (ISR) for different channels.
NOTE: The TCC field in the channel options parameter (OPT) is a 6-bit field and can be
programmed for any value between 0-64. For devices with 32 DMA channels, the TCC
should have a value between 0 to 31 so that it sets the appropriate bits (0 to 31) in IPR (and
can interrupt the CPU(s) on enabling the IER register bits (0-31)).
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Table 14-10. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
TCC Bits in OPT
(TCINTEN/ITCINTEN = 1)
IPR Bit Set
00 0000b
IPR0
00 0001b
IPR1
00 0010b
IPR2
00 0011b
IPR3
00 0100b
IPR4
…
…
…
…
01 1110b
IPR30
01 1111b
IPR31
You can enable interrupt generation at either final transfer completion or intermediate transfer completion,
or both. Consider channel m as an example.
• If the final transfer interrupt (TCINTEN = 1 and ITCINTEN = 0 in OPT) is enabled, the interrupt occurs
after the last transfer request of channel m is either submitted or completed (depending on early or
normal completion).
• If the intermediate transfer interrupt (TCINTEN = 0 and ITCINTEN = 1 in OPT) is enabled, the interrupt
occurs after every intermediate transfer request of channel m is either submitted or completed
(depending on early or normal completion).
• If both final and intermediate transfer completion interrupts (TCINTEN = 1 and ITCINTEN = 1 in OPT)
are enabled, the interrupt occurs after every transfer request of channel m is submitted or completed
(depending on early or normal completion).
Table 14-11 shows the number of interrupts occurring in different synchronized scenarios. Consider
channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 14-11. Number of Interrupts
Options
A-Synchronized
AB-Synchronized
TCINTEN = 1, ITCINTEN = 0
1 (Last TR)
1 (Last TR)
TCINTEN = 0, ITCINTEN = 1
19 (All but the last TR)
4 (All but the last TR)
TCINTEN = 1, ITCINTEN = 1
20 (All TRs)
5 (All TRs)
14.2.9.1.1 Enabling Transfer Completion Interrupts
For the EDMA3 channel controller to assert a transfer completion to the external world, the interrupts have
to be enabled in the EDMA3CC. This is in addition to setting up the TCINTEN and ITCINTEN bits in OPT
of the associated PaRAM set.
The EDMA3 channel controller has interrupt enable registers (IER) and each bit location in IER serves as
a primary enable for the corresponding interrupt pending register (IPR).
All the interrupt registers (IER, IESR, IECR, and IPR) are either manipulated from the global DMA channel
region or by way of the DMA channel shadow regions. The shadow regions provide a view to the same
set of physical registers that are in the global region.
The EDMA3 channel controller has a hierarchical completion interrupt scheme that makes use of a single
set of interrupt pending register (IPR) and single set of interrupt enable registers (IER). A second level of
interrupt masking is provided by the programmable DMA region access enable registers (DRAE). See
Figure 14-12.
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For the EDMA3CC to generate the transfer completion interrupts that are associated with each shadow
region, the following conditions must be true:
• EDMA3CC_INT0: (IPR.E0 & IER.E0 & DRAE0.E0) | (IPR.E1 & IER.E1 & DRAE0.E1) | …| (IPR.En &
IER.En & DRAE0.En)
• EDMA3CC_INT1: (IPR.E0 & IER.E0 & DRAE1.E0) | (IPR.E1 & IER.E1 & DRAE1.E1) | …| (IPR.En &
IER.En & DRAE1.En)
where n is the number of shadow regions supported in the EDMA3CC for a specific device.
Figure 14-12. Interrupt Diagram
Interrupt pending
register (IPR)
X
1
0
Interrupt
enable
register
(IER)
X
DMA region
access enable 1
(DRAE1)
DMA region
access enable 0
(DRAE0)
1
0
X
1
0
X
1
DMA region
access enable n
(DRAE3)
0
...
X
1
0
...
IEVAL0.EVAL
Eval
pulse
EDMA3_m_CC0_INT0
IEVAL3.EVAL
IEVAL1.EVAL
Eval
pulse
Eval
pulse
EDMA3_m_CC0_INT1
EDMA3_m_CC0_INT3
NOTE: The DRAE for all regions is expected to be set up at system initialization and to remain static
for an extended period of time. The interrupt enable registers should be used for dynamic
enable/disable of individual interrupts.
Because there is no relation between the TCC value and the DMA/QDMA channel, it is
possible, for example, for DMA channel 0 to have the OPT.TCC = 31 in its associated
PaRAM set. This would mean that if a transfer completion interrupt is enabled
(OPT.TCINTEN or OPT.ITCINTEN is set), then based on the TCC value, IPR.E31 is set up
on completion. For proper channel operations and interrupt generation using the shadow
region map, you must program the DRAE that is associated with the shadow region to have
read/write access to both bit 0 (corresponding to channel 0) and bit 31 (corresponding to
IPR.E31 bit that is set upon completion).
14.2.9.1.2 Clearing Transfer Completion Interrupts
Transfer completion interrupts that are latched to the interrupt pending register (IPR) is cleared by writing
a 1 to the corresponding bit in the interrupt pending clear register (ICR). For example, a write of 1 to
ICR.E0 clears a pending interrupt in IPR.E0.
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If an incoming transfer completion code (TCC) gets latched to a bit in IPR, then additional bits that get set
due to a subsequent transfer completion will not result in asserting the EDMA3CC completion interrupt. In
order for the completion interrupt to be pulsed, the required transition is from a state where no enabled
interrupts are set to a state where at least one enabled interrupt is set.
14.2.9.2 EDMA3 Interrupt Servicing
On completion of a transfer (early or normal completion), the EDMA3 channel controller sets the
appropriate bit in the interrupt pending register (IPR) as specified by the transfer completion codes. If the
completion interrupts are appropriately enabled, then the CPU enters the interrupt service routine (ISR)
when the completion interrupt is asserted. Since there is a single completion interrupt for all DMA/QDMA
channels.
After servicing the interrupt, the ISR should clear the corresponding bit in IPR; therefore, enabling
recognition of future interrupts. Only when all IPR bits are cleared, the EDMA3CC will assert additional
completion interrupts.
It is possible that when one interrupt is serviced; many other transfer completions result in additional bits
being set in IPR, thereby resulting in additional interrupts. It is likely that each of these bits in IPR would
need different types of service; therefore, the ISR must check all pending interrupts and continue until all
the posted interrupts are appropriately serviced.
Following are examples (pseudo code) for a CPU interrupt service routine for an EDMA3CC completion
interrupt.
The ISR routine in Example 14-2 is more exhaustive and incurs a higher latency.
Example 14-2. Interrupt Servicing
The pseudo code:
1. Read the interrupt pending register (IPR).
2. Perform the operations needed.
3. Write to the interrupt pending clear register (ICR) to clear the corresponding IPR bit.
4. Read IPR again:
(a) If IPR is not equal to 0, repeat from step 2 (implies occurrence of new event between step 2 to step 4).
(b) If IPR is equal to 0, this should assure you that all enabled interrupts are inactive.
NOTE: It is possible that during step 4, an event occurs while the IPR bits are read to be 0 and the
application is still in the interrupt service routine. If this happens, a new interrupt is recorded in
the device interrupt controller and a new interrupt is generated as soon as the application exits
the interrupt service routine.
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Example 14-3 is less rigorous, with less burden on the software in polling for set interrupt bits, but can
occasionally cause a race condition, as mentioned above.
Example 14-3. Interrupt Servicing
If it is desired to leave any enabled and pending (possibly lower priority) interrupts, it is required to force the
interrupt logic to reassert the interrupt pulse by setting the EVAL bit in the interrupt evaluation register
(IEVAL).
The pseudo code:
1. Enter ISR.
2. Read IPR.
3. For the condition set in IPR that you desire to service:
(a) Service interrupt as required by application.
(b) Clear bit for serviced conditions (others may still be set, and other transfers may have resulted in
returning the TCC to EDMA3CC after step 2).
4. Read IPR prior to exiting ISR:
(a) If IPR is equal to 0, then exit ISR.
(b) If IPR is not equal to 0, then set IEVAL so that upon exit of ISR, a new interrupt is triggered if any
enabled interrupts are still pending.
The EVAL bit must not be set when IPR is read to be 0, to avoid generation of extra interrupt pulses.
NOTE:
Since the DMA region access registers (DRAE) are required to enable the transfer
completion region interrupts, it is assumed that there will be a unique and nonoverlapping (in
most cases) assignment of the channels and interrupts among the different shadow regions.
This allows the interrupt registers (IER, IESR, IECR, IPR, and ICR) in the different shadow
regions to functionally operate in an independent manner and nonoverlapping. The above
examples for the interrupt service routine is based on this assumption.
14.2.9.3 Interrupt Evaluation Operations
The EDMA3CC has interrupt evaluate registers (IEVAL) in each shadow region. These registers are the
only registers in the DMA channel shadow region memory map that are not affected by the settings for the
DMA region access enable registers (DRAE). A write of 1 to the EVAL bit in these registers associated
with a particular shadow region results in pulsing the associated region interrupt, if any enabled interrupt
(via IER) is still pending (IPR). This register can be used in order to assure that the interrupts are not
missed by the CPU (or the EDMA3 master associated with the shadow region) if the software architecture
chooses not to use all interrupts. See Example 14-3 for the use of IEVAL in the EDMA3 interrupt service
routine (ISR).
Similarly an error evaluate register (EEVAL) exists in the global region. A write of 1 to the EVAL bit in
EEVAL causes the pulsing of the error interrupt if any pending errors are in EMR, QEMR, or CCERR. See
Section 14.2.9.4 for additional details on error interrupts.
NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the
IEVAL operated upon is from that particular shadow region memory map.
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14.2.9.4 Error Interrupts
The EDMA3CC error registers provide the capability to differentiate error conditions (event missed,
threshold exceed, etc.). Additionally, if the error bits are set in these registers, it results in asserting the
EDMA3CC error interrupt. If EDMA3CC error interrupt is enabled in the device interrupt controller, then it
allows the CPU to handle the error conditions.
The EDMA3CC has a single error interrupt ( EDMA3_m_CC0_ERRINT) that gets asserted for all
EDMA3CC error conditions. There are four conditions that cause the error interrupt to be pulsed:
• DMA missed events: for all 32 DMA channels. These get latched in the event missed registers (EMR).
• QDMA missed events: for all QDMA channels. These get latched in the QDMA event missed register
(QEMR).
• Threshold exceed: for all event queues. These get latched in EDMA3CC error register (CCERR).
• TCC error: for outstanding transfer requests expected to return completion code (TCCHEN or
TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 31. This also gets latched in the
EDMA3CC error register (CCERR).
Figure 14-13 illustrates the EDMA3CC error interrupt generation operation.
If any of the bits are set in the error registers due to any error condition, the ( EDMA3_m_CC0_ERRINT)
always is asserted, as there are no enables for masking these error events. Similar to the transfer
completion interrupts, the error interrupt also is pulsed only when the error interrupt condition transitions
from a state where no errors are set to a state where at least one error bit is set. If additional error events
are latched prior to the original error bits being cleared, the EDMA3CC does not generate additional
interrupt pulses.
To reduce the burden on the software, similar to the interrupt evaluate register (IEVAL), there is an error
evaluate register (EEVAL) that allows reevaluation of pending set error events/bits. This can be used so
that the CPU(s) does not miss any error events.
NOTE: It is a good practice to have the error interrupt enabled in the device interrupt controller and
associate an interrupt service routine with it to address the various error conditions
appropriately. This puts less burden on software (polling for error status) and additionally
provides a good debug mechanism for unexpected error conditions.
Figure 14-13. Error Interrupt Operation
EMR
31
QEMR
1
0
7
CCERR
1
0
16
n
1
0
EEVAL.EVAL
Eval/
pulse
EDMA3_m_CC0_ERRINT
Note: n is the number of queues supported in the EDMA3CC for a specific device.
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14.2.10 Event Queue(s)
Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the
event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC.
Each queue is 16 entries deep, that is, a maximum of 16 queued events per event queue. If there are
more than 16 events, then the events that cannot find a place in the event queue remain set in the
associated event register.
The number of event queues in the EDMA3CC determines the number of transfer controllers connected to
the EDMA3CC. By default, there is a one-to-one mapping between the queues and transfer controllers.
Therefore, the transfer requests (TRs) associated with events in Q0 get submitted to TC0. Similarly,
transfer requests associated with events in Q1 get submitted to TC1, and so on.
An event that wins prioritization against other DMA and/or QDMA pending events is placed at the end of
the appropriate event queue. Each event queue is serviced in a FIFO (first in–first out) order. Once the
event reaches the head of its queue and the corresponding transfer controller is ready to receive another
TR, the event is dequeued and the PaRAM set corresponding to the dequeued event is processed and
submitted as a transfer request packet (TRP) to the associated EDMA3 transfer controller.
A lower numbered queue has a higher dequeuing priority then a higher numbered queue. For example,
Q0 has higher priority than Q1, if Q0 and Q1 both have at least one event entry and if both TC0 and TC1
can accept transfer requests, then the event in Q0 is dequeued first and its associated PaRAM set is
processed and submitted as a transfer request (TR) to TC0.
All the event entries in all the event queues are software readable (not writeable) by accessing the event
queue entry registers (QxEy). Each event entry register characterizes the queued event in terms of the
type of event (manual, event, chained or autotriggered) and the event number. See Section 14.4.2.4.1 for
a description of the bit fields in the queue event entry registers.
14.2.10.1 DMA/QDMA Channel to Event Queue Mapping
Each DMA channel and QDMA channel is independently programmed to map to a specific queue using
the DMA queue number register n (DMAQNUMn) and the QDMA channel queue number register
(QDMANUM). The mapping of DMA/QDMA channels is critical to achieving the desired performance level
for the EDMA and most importantly in meeting real-time deadlines.
NOTE: If an event is ready to be queued and both the event queue and the EDMA3 transfer
controller associated to the event queue are empty, then the event bypasses the event
queue, and goes to the PaRAM processing logic and eventually to the transfer request
submission logic for submission to the EDMA3TC. In this case, the event is not logged in the
event queue status registers.
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14.2.10.2 Queue RAM Debug Visibility
Each event queue has 16 entries. These 16 entries are managed in a circular FIFO manner. All event
queue entries for all event queues are software readable by the event queue entry register (QxEx).
Additionally, for each queue there is a queue status register (QSTATn).
These registers provide user visibility and may be helpful while debugging real-time issues (typically postmortem), involving multiple events and event sources. The event queue entry register (QxEx) uniquely
identifies the specific event type (event-triggered, manually-triggered, chain-triggered, and QDMA events)
along with the event number (for DMA/QDMA channels) that are in the queue or have been de-queued
(passed through the queue). QSTATn includes fields for the start pointer (STRTPTR) that provides the
offset to the head entry of an event. It also includes a NUMVAL field that provides the total number of
valid entries residing in the event queue at a given instance of time. The STRTPTR field may be used to
index appropriately into the 16 event entries. The NUMVAL number of entries starting from STRTPTR are
indicative of events still queued in the respective queue. The remaining entries may be read to determine
which events have already been de-queued and submitted to the associated transfer controller.
14.2.10.3 Queue Resource Tracking
The EDMA3CC event queue includes watermarking/threshold logic that allows you to keep track of
maximum usage of all event queues. This is useful for debugging real-time deadline violations that may
result from head-of-line blocking on a given EDMA3 event queue.
You can program the maximum number of events that can queue up in an event queue by programming
the threshold value (between 0 to 15) in the queue watermark threshold A register (QWMTHRA). The
maximum queue usage is recorded actively in the watermark (WM) field of the queue status register
(QSTATn) that keeps getting updated based on a comparison of number of valid entries, which is also
visible in the NUMVAL bit in QSTATn and the maximum number of entries (WM bit in QSTATn).
If the queue usage is exceeded, this status is visible in the EDMA3CC registers: the QTHRXCDn bit in the
channel controller error register (CCERR) and the THRXCD bit in QSTATn, where n stands for the event
queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt.
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14.2.11 EDMA3 Transfer Controller (EDMA3TC)
The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller
(EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR)
to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR.
14.2.11.1 Architecture Details
14.2.11.1.1 EDMA3TC Configuration
Each transfer controller on a device is designed differently based on considerations like performance
requirements, system topology (main SCR bus width, external memory bus width), gate count, etc. The
parameters that determine the TC configurations are:
• FIFOSIZE: Determines the size in bytes for the Data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main SCR interface.
• DSTREGDEPTH: This determines the number of Destination FIFO register set. The number of
Destination FIFO register set for a transfer controller, determines the maximum number of outstanding
transfer requests (TR pipelining).
Of the four parameters, the FIFOSIZE, BUSWIDTH, and DSTREGDEPTH values are fixed in design for a
given device. The default burst size (DBS) for EDMA3_0_TC0 and EDMA3_0_TC1 is configurable by the
chip configuration 0 register (CFGCHIP0) in the System Configuration Module and for EDMA3_1_TC0 is
configurable by the chip configuration 1 register (CFGCHIP1) in the System Configuration Module.
Table 14-12 provides the configuration of the individual EDMA3 transfer controllers on the device.
The burst size for each transfer controlled can be programmed to be 16-, 32-, or 64-bytes. The default
values for DBS are typically chosen for optimal performance in most intended-use conditions; therefore, if
you decide to use a value other then the default, you should evaluate the impact on performance.
Depending on the FIFOSIZE and source/destination locations the performance for the transfer can vary
significantly for different burst size values.
NOTE: It is expected that the DBS value for a transfer controller is static and should be based on
the application requirement. It is not recommended that the DBS value be changed on-thefly.
Table 14-12. EDMA3 Transfer Controller Configurations
372
Parameter
EDMA3_0_TC0
EDMA3_0_TC1
EDMA3_1_TC0
FIFOSIZE
128 bytes
128 bytes
256 bytes
BUSWIDTH
8 bytes (64 bits)
8 bytes (64 bits)
8 bytes (64 bits)
DSTREGDEPTH
4 entries
4 entries
4 entries
DBS (default)
16 bytes
16 bytes
16 bytes
Error interrupt
EDMA3_0_TC0_ERRINT
EDMA3_0_TC1_ERRINT
EDMA3_1_TC0_ERRINT
EDMA3 channel controller
used
EDMA3_0_CC0
EDMA3_0_CC0
EDMA3_1_CC0
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14.2.11.1.2 Command Fragmentation
The TC read and write controllers in conjunction with the source and destination register sets are
responsible for issuing optimally-sized reads and writes to the slave endpoints. The transfer controller
read/write transaction as specified by the transfer request packet is internally broken down into smaller
bursts; this determines the default burst size (DBS) for the transfer controller. See Section 14.2.11.1.1 for
the DBS value of each EDMA3TC.
The EDMA3TC attempts to issue the largest possible command size as limited by the DBS value or the
ACNT/BCNT value of the TR. EDMA3TC obeys the following rules:
• The read/write controllers always issue commands less than or equal to the DBS value.
• The first command of a 1D transfer is always issued so that subsequent commands align to the DBS
value.
Example 14-4 shows the command fragmentation for a DBS of 32 bytes. In summary, if the ACNT value is
larger than the DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the
source/destination addresses. Each BCNT number of arrays are then serviced in succession.
Example 14-4. Command Fragmentation (DBS = 32)
The pseudo code:
1. ACNT = 8, BCNT = 8, SRCBIDX = 8, DSTBIDX = 10, SRCADDR = 64, DSTADDR = 191
Read Controller: This is optimized from a 2D-transfer to a 1D-transfer such that the read side is equivalent
to ACNT = 64, BCNT = 1.
Cmd0 = 32 byte, Cmd0 = 32 byte
Write Controller: Since DSTBIDX != ACNT, it is not optimized.
Cmd0 = 8 byte, Cmd1 = 8 byte, Cmd2 = 8 byte, Cmd3 = 8 byte, Cmd4 = 8 byte, Cmd5 = 8 byte, Cmd6 = 8
byte, Cmd7 = 8 byte.
2. ACNT = 64, BCNT = 1, SRCADDR = 31, DSTADDR = 513
Read Controller: Read address is not aligned.
Cmd0 = 1 byte, (now the SRCADDR is aligned to 32 for the next command)
Cmd1 = 32 bytes
Cmd2 = 31 bytes
Write Controller: The write address is also not aligned.
Cmd0 = 31 bytes, (now the DSTADDR is aligned to 32 for the next command)
Cmd1 = 32 bytes
Cmd2 = 1 byte
14.2.11.1.3 TR Pipelining and Data Ordering
The transfer controller(s) can issue back-to-back transfer requests (TR). The number of outstanding TRs
for a TC is limited by the number of destination FIFO register entries that is controlled by the
DSTREGDEPTH parameter (fixed in design for a given transfer controller). TR pipelining refers to the
ability of the TC read controller to issue read commands for a subsequent TR, while the TC write
controller is still performing writes for the previous TR. Consider the case of 2 TRs (TR0 followed by TR1),
because of TR pipelining, the TC read controller can start issuing the read commands for TR1 as soon as
the last read command for TR0 has been issued, meanwhile the write commands and write data for TR0
are tracked by the destination FIFO registers. In summary, the TC read controller is able to process n TRs
ahead of the write controller, where n is the number of destination FIFO register entries (typically 4).
TR pipelining is useful for maintaining throughput on back-to-back small TRs. It eliminates the read
overhead because reads start in the background of a previous TR writes.
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It should be noted that back-to-back TRs are targeted to different end points even though the read return
data for the two TRs might get returned out of order (that is, read data for TR1 might come in before read
data for TR0), the transfer controller issues that the write commands are issued in order (that is, write
commands for TR0 will be issued before write commands for TR1).
14.2.11.2 Error Generation
Similar to the channel controller, the transfer controllers are capable of detecting and reporting several
error conditions. The TC errors are generated, under three main conditions:
• BUSERR: The TC read or write controllers detect an error signaled by the source or destination
address. The additional details on the type of error is also recorded in the ERRDET register, which
indicates whether it is a read error (source address errors) or write error (destination address error).
• MMRAERR: CPU accesses illegal/reserved addresses in the EDMA3CC/TC memory-map.
• TRERR: A transfer request packet is detected to be violating the constant addressing mode transfer
rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes).
You can poll for the errors, as the status of the errors can be read from the ERRSTAT registers,
additionally if the error bits are enabled in the ERREN register, a bit set in the ERRSTAT will cause the
error condition to interrupt the CPU(s). You can decide to enable/disable either or all error types.
14.2.11.3 Debug Features
The DMA program register set, DMA source active register set, and the destination FIFO register set are
used to derive a brief history of TRs serviced through the transfer controller.
Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing
activity within different parts of the transfer controller:
• The SRCACTV bit indicates whether the source active set is active.
• The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given
instance.
• The PROGBUSY bit indicates whether a valid TR is present in the DMA program set.
If the TRs are in progression, caution must be used and you must realize that there is a chance that the
values read from the EDMA3TC status registers will be inconsistent since the EDMA3TC may change the
values of these registers due to ongoing activities.
It is recommended that you ensure no additional submission of TRs to the EDMA3TC in order to facilitate
ease of debug.
14.2.11.3.1 Destination FIFO Register Pointer
The destination FIFO register pointer is implemented as a circular buffer with the start pointer being
DFSTRTPTR and a buffer depth of usually 2 or 4. The EDMA3TC maintains two important status details in
TCSTAT that may be used during advanced debugging, if necessary. The DFSTRTPTR is a start pointer,
that is, the index to the head of the destination FIFO register. The DSTACTV is a counter for the number
of valid (occupied) entries. These registers may be used to get a brief history of transfers.
Examples of some register field values and their interpretation:
• DFSTRTPTR = 0 and DSTACTV = 0 implies that no TRs are stored in the destination FIFO register.
• DFSTRTPTR = 1 and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 1 and the second pending TR is read from the destination
FIFO register entry 2.
• DFSTRTPTR = 3h and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 3 and the second pending TR is read from the destination
FIFO register entry 0.
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14.2.12 Event Dataflow
This section summarizes the data flow of a single event, from the time the event is latched to the channel
controller to the time the transfer completion code is returned. The following steps list the sequence of
EDMA3CC activity:
1. Event is asserted from an external source (peripheral or external interrupt). This also is similar for a
manually-triggered, chained-triggered, or QDMA-triggered event. The event is latched into the ER.En
(or CER.En, ESR.En, QER.En) bit.
2. Once an event is prioritized and queued into the appropriate event queue, the SER.En (or QSER.En)
bit is set to inform the event prioritization/processing logic to disregard this event since it is already in
the queue. Alternatively, if the transfer controller and the event queue are empty, then the event
bypasses the queue.
3. The EDMA3CC processing and the submission logic evaluates the appropriate PaRAM set and
determines whether it is a non-null and non-dummy transfer request (TR).
4. The EDMA3CC clears the ER.En (or CER.En, ESR.En, QER.En) bit and the SER.En bit as soon as it
determines the TR is non-null. In the case of a null set, the SER.En bit remains set. It submits the nonnull/non-dummy TR to the associated transfer controller. If the TR was programmed for early
completion, the EDMA3CC immediately sets the interrupt pending register (IPR.I[TCC]).
5. If the TR was programmed for normal completion, the EDMA3CC sets the interrupt pending register
(IPR.I[TCC]) when the EDMA3TC informs the EDMA3CC about completion of the transfer (returns
transfer completion codes).
6. The EDMA3CC programs the associated EDMA3TCn Program Register Set with the TR.
7. The TR is then passed to the Source Active set and the Dst FIFO Register Set, if both the register sets
are available.
8. The Read Controller processes the TR by issuing read commands to the source slave endpoint. The
Read Data lands in the Data FIFO of the EDMA3TCn.
9. As soon as sufficient data is available, the Write Controller begins processing the TR by issuing write
commands to the destination slave endpoint.
10. This continues until the TR completes and on receiving the acknowledgement signal from the
destination slave end point, the EDMA3TCn then signals completion status to the EDMA3CC.
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14.2.13 EDMA3 Prioritization
The EDMA3 controller has many implementation rules to deal with concurrent events/channels, transfers,
etc. The following subsections detail various arbitration details whenever there might be occurrence of
concurrent activity. Figure 14-14 shows the different places EDMA3 priorities come into play.
14.2.13.1 Channel Priority
The DMA event register (ER) captures all external/peripheral events connected to the EDMA3CC;
likewise, the QDMA event register (QER) captures QDMA events for all QDMA channels; therefore, it is
possible for events to occur simultaneously on the DMA/QDMA event inputs. For events arriving
simultaneously, the event associated with the lowest channel number is prioritized for submission to the
event queues (for DMA events, channel 0 has the highest priority and channel 31 has the lowest priority;
similarly, for QDMA events, channel 0 has the highest priority and channel 7 has the lowest priority). This
mechanism only sorts simultaneous events for submission to the event queues.
If a DMA and QDMA event occurs simultaneously, the DMA event always has prioritization against the
QDMA event for submission to the event queues.
Figure 14-14. EDMA3 Prioritization
Chain
trigger
Event
register
(ER)
Event
enable
register
(EER)
32
Event
queues
15
0
Queue 1
Parameter
set 126
32
To
EDMA3TC(s)
Parameter
set 127
QDMA
event
register
(QER)
8
Queue bypass
PaRAM
Completion
interface
QDMA trigger
376
Parameter
set 1
32
Chained
event
register
(CER)
EDMA3 channel
controller
Parameter
set 0
0
Queue 0
15
Event
set
register
(ESR)
Dequeue priority
Channel mapping
Manual
trigger
Channel priority
32:1 priority encoder
Event
trigger
Trigger source priority
E1 E0
8:1 priority encoder
E31
Transfer request submission
From peripherals/external events
Completion
detection
Error
detection
Completion
interrupt
Error Interrupt
Transfer Completion
Interrupts
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EDMA3TC(s)
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14.2.13.2 Trigger Source Priority
If a DMA channel is associated with more than one trigger source (event trigger, manual trigger, and chain
trigger), and if multiple events are set simultaneously for the same channel (ER.En = 1, ESR.En = 1,
CER.En = 1), then the EDMA3CC always services these events in the following priority order: event
trigger (via ER) is higher priority than chain trigger (via CER) and chain trigger is higher priority than
manual trigger (via ESR).
This implies that if for channel 0, both ER.E0 = 1 and CER.E0 = 1 at the same time, then the ER.E0 event
is always queued before the CER.E0 event.
14.2.13.3 Dequeue Priority
The priority of the associated transfer request (TR) is further mitigated by which event queue is being used
for event submission (dictated by DMAQNUMn and QDMAQNUM). For submission of a TR to the transfer
controller, events need to be dequeued from the event queues. A lower numbered queue has a higher
dequeuing priority then a higher numbered queue. For example, if there are events in Q0 and Q1 and the
respective transfer controllers (TC0 and TC1) are ready to receive the next TR from the EDMA3CC, then
the transfer requests associated with events in Q0 will get submitted to TC0 prior to any transfer requests
associated with events in Q1 getting submitted to TC1.
NOTE: At any given time, if there are outstanding events in multiple queues, when the transfer
controller associated with the lower numbered (higher priority) queue is busy processing
earlier transfer requests and the transfer controller associated with the higher numbered
(lower priority) queue is idle, then the event in the higher numbered (lower priority) queue will
dequeue first.
14.2.13.4
Master (Transfer Controller) Priority
All master peripherals on the device have a programmable priority level. When multiple masters are trying
to access common shared resources (slave memory or peripherals), this priority value allows the system
interconnect to arbitrate requests from different masters based on their priority. This priority assignment is
determined in the Master Priority Registers (MSTPRI0-MSTPRI2) in the System Configuration Module
(see the System Configuration (SYSCFG) Module chapter), where each master has an allocated priority
value (power on reset default value), which can be re programmed based on the applications prioritization
requirements. The priority value can be configured between 0 to 7, with 0 being the highest priority and 7
being the lowest priority.
Each transfer controller on the device is also a master peripheral. The priority of the transfer requests
(read/write commands) issued by the individual EDMA3TC read/write ports in the system can be
programmed via these registers.
The dequeue priority has a relatively secondary effect as compared to this Master priority; therefore, it is
important to program the priority of each transfer controller with respect to each other and also with
respect to other masters in the system.
NOTE: On previous architectures, the EDMA3TC priority was controlled by the QUEPRI register in
the EDMA3CC memory-map. However for this device, the priority control for the transfer
controllers is controlled by the chip-level registers in the System Configuration Module.
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14.2.14 EDMA3CC and EDMA3TC Performance and System Considerations
14.2.14.1 System Priority Considerations
The main switched central resource (SCR) (see your device-specific data manual) arbitrates bus requests
from all the masters (CPU, master peripherals, and the EDMA3 transfer controllers) to the shared slave
resources (peripherals and memories). The priorities of transfer requests (read and write commands) from
the EDMA3 transfer controllers with respect to each other and the other masters within the system is
configured as explained in Section 14.2.13.4.
It is recommended that this priority be altered based on system level considerations. For example,
peripherals servicing audio/video/display threads that typically have real-time deadlines should be
programmed as highest priority requestors in the systems, where as, peripherals responsible for doing
bulk/block/paging transfers with no real-time deadlines, should be programmed as a lower system priority.
The default priority for all transfer controllers is the same, 0 or highest priority relative to other masters;
therefore, it is recommended that a TC servicing audio data requests from serial ports should be
configured at a higher priority as compared to TC service memory to memory (paging/bulk) transfer
requests.
14.2.14.2 TC Transfer Optimization Considerations
The transfer controller can internally optimize the way it issues read commands and write commands for a
given transfer under certain conditions. For 2D transfers (that is, BCNT arrays of ACNT bytes), if the
ACNT value is less than or equal to the DBS value, then the transfer controller will try to optimize the TR
into a 1D transfer in order to maximize efficiency. The optimization only takes place if the EDMA3TC
recognizes that the 2D transfer is organized as a single dimension (SAM/DAM = 0, increment mode),
SRC/DST BIDX = ACNT, the ACNT value is a power of 2, and the BCNT value is less than or equal to
1023. If these conditions are met, then instead of issuing ACNT bytes worth read and/or write commands,
the TC will try to optimize the bus usage by issuing commands as if ACNT' = ACNT × BCNT and
BCNT = 1.
Table 14-13 summarizes the conditions in which the optimizations are performed.
Table 14-13. Read/Write Command Optimization Rules
ACNT ≤ DBS
ACNT is power of 2
BIDX = ACNT
BCNT ≤ 1023
SAM/DAM = 0
(Increment)
Yes
Yes
Yes
Yes
Yes
Optimized
Yes
No
x
x
Yes
Not Optimized
Yes
x
No
x
Yes
Not Optimized
No
x
x
x
Yes
Not Optimized
x
x
x
x
No
Not Optimized
Description
Consider a case in which it is needed to transfer 4096 bytes where the data is arranged linearly in both
the source and destination locations (SAM/DAM = 0, SRC/DST BIDX = ACNT): Scenario A programs the
ACNT = 4, BCNT = 1024 , AB-synchronized transfer; and Scenario B programs the ACNT = 64,
BCNT = 64. Scenario B will yield a much optimized transfer and higher throughput, as the transfer meets
all the optimization rules, which would result in TC internally treating it as a transfer with an ACNT' = 4096
(ACNT × BCNT). The TC will optimally size, default burst size worth read and write commands. In the
case of Scenario B, since one of the optimization rules is not met (BCNT value is greater then 1023), the
TC will end up issuing several ACNT byte (4 byte) size commands to complete the transfers, which will
result in inefficient usage of the read/write buses.
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14.2.14.3 Throttling the Read Command Rate in a Transfer Controller
By default, the transfer controller issues reads as fast as possible. In some cases, the reads issued by the
EDMA3TCC could fill the available command buffering for a slave, delaying other (potentially higher
priority) masters from successfully submitting commands to that slave. The rate at which read commands
are issued by the EDMA3TC is controlled by the read command rate register (RDRATE), and this can be
used to throttle the rate at which the commands are issued from the TC read interface. RDRATE defines
the number of cycles that the EDMA3TC read controller waits before issuing subsequent commands for a
given TR, thus minimizing the chance of the EDMA3TC consuming all available slave resources. The
RDRATE value should be set to a relatively small value (or kept at default, which implies issuing read
requests as fast as possible) if the transfer controller is targeted for high-priority transfers and set to a high
value if the transfer controller is targeted for low-priority transfers. In contrast, the write Interface does not
have any performance turning knobs because writes always have an interval between commands as write
commands are submitted along with the associated write data.
14.2.15 EDMA3 Operating Frequency (Clock Control)
The EDMA3 channel controller and transfer controller are clocked from PLL controller 0 (PLLC0). For
details, see the Phase-Locked Loop Controller (PLLC) chapter.
14.2.16 Reset Considerations
A hardware reset resets the EDMA3 (EDMA3CC and EDMA3TC) and the EDMA3 configuration registers.
The PaRAM memory contents are undefined after device reset and you should not rely on parameters to
be reset to a known state. The PaRAM set must be initialized to a desired value before it is used.
14.2.17 Power Management
The EDMA3 (EDMA3CC and EDMA3TC) can be placed in reduced-power modes to conserve power
during periods of low activity. The power management of the peripheral is controlled by the device Power
and Sleep Controller (PSC). The PSC acts as a master controller for power management for all
peripherals on the device. For detailed information on power management procedures using the PSC, see
the Power and Sleep Controller (PSC) chapter.
The EDMA3 controller can be idled on receiving a clock stop request from the PSC. The requests to
EDMA3CC and EDMA3TC are separate. In general, you should verify that there are no pending activities
in the EDMA3 controller before issuing a clock stop request via PSC.
The EDMA3CC checks for the following conditions:
• No pending DMA/QDMA events
• No outstanding events in the event queues
• Transfer request processing logic is not active
• No completion requests outstanding (early or normal completion)
• No configuration bus requests in progress
The first four conditions are software readable by the channel controller status register (CCSTAT) in the
EDMA3CC.
Similarly, from the EDMA3TC perspective, you should check that there are no outstanding TRs that are
getting processed and essentially the read/write controller is not busy processing a TR. The activity of
EDMA3TC logic is read in TCSTAT for each EDMA3TC.
It is generally recommended to first disable the EDMA3CC and then the EDMA3TC(s) to put the EDMA3
controller in reduced-power modes.
Additionally, when EDMA3 is involved in servicing a peripheral and it is required to power-down both the
peripheral and the EDMA, the recommended sequence is to first disable the peripheral, then disable the
DMA channel associated with the peripheral (clearing the EER bit for the channel), then disable the
EDMA3CC, and finally disable the EDMA3TC(s).
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14.2.18 Emulation Considerations
During debug when using the emulator, the CPU(s) may be halted on an execute packet boundary for
single-stepping, benchmarking, profiling, or other debug purposes. During an emulation halt, the EDMA3
channel controller and transfer controller operations continue. Events continue to be latched and
processed and transfer requests continue to be submitted and serviced.
Since EDMA3 is involved in servicing multiple master and slave peripherals, it is not feasible to have an
independent behavior of the EDMA3 for emulation halts. EDMA3 functionality would be coupled with the
peripherals it is servicing, which might have different behavior during emulation halts. For example, if a
multichannel buffered serial port (McBSP) is halted during an emulation access (FREE = 0 and SOFT = 0
or 1 in the McBSP registers), the McBSP stops generating the McBSP receive or transmit events (REVT
or XEVT) to the EDMA. From the point of view of the McBSP, the EDMA3 is suspended, but other
peripherals (for example, a timer) still assert events and will be serviced by the EDMA.
14.3 Transfer Examples
The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration.
The following sections provides a description and PaRAM configuration for some typical use case
scenarios.
14.3.1 Block Move Example
The most basic transfer performed by the EDMA3 is a block move. During device operation it is often
necessary to transfer a block of data from one location to another, usually between on-chip and off-chip
memory.
In this example, a section of data is to be copied from external memory to internal L2 SRAM. A data block
of 256 bytes residing at address 4000 0000h (external memory ) needs to be transferred to internal
address 1180 0000h (L2), as shown in Figure 14-15. Figure 14-16 shows the parameters for this transfer.
The source address for the transfer is set to the start of the data block in external memory, and the
destination address is set to the start of the data block in L2. If the data block is less than 64K bytes, the
PaRAM configuration in Figure 14-16 holds true with the synchronization type set to A-synchronized and
indexes cleared to 0. If the amount of data is greater than 64K bytes, BCNT and the B-indexes need to be
set appropriately with the synchronization type set to AB-synchronized. The STATIC bit in OPT is set to
prevent linking.
This transfer example may also be set up using QDMA. For successive transfer submissions, of a similar
nature, the number of cycles used to submit the transfer are fewer depending on the number of changing
transfer parameters. You may program the QDMA trigger word to be the highest numbered offset in the
PaRAM set that undergoes change.
Figure 14-15. Block Move Example
4000 0000h
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249 250 251 252 253 254 255 256
380
Enhanced Direct Memory Access (EDMA3) Controller
1180 0000h
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... 244 245 246 247 248
249 250 251 252 253 254 255 256
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Figure 14-16. Block Move Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
Parameter
0010 0008h
Channel Options Parameter (OPT)
4000 0000h
Channel Source Address (SRC)
0001h
0100h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0000h
Destination BCNT Index (DSTBIDX)
0000h
FFFFh
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31