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Texas Instruments DM388 Base Board User guides
DM388 Base Board
User's Guide
Literature Number: SPRUI85
August 2016
Contents
Preface ........................................................................................................................................ 7
1
Introduction to DM388 Base EVM ........................................................................................... 9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
2.2
2.3
2.4
2.5
EVM Interfaces .............................................................................................................
2.1.1 DDR Interface ......................................................................................................
2.1.2 NAND Interface ....................................................................................................
2.1.3 SD/MMC Interface.................................................................................................
2.1.4 Audio Interface.....................................................................................................
2.1.5 EMAC Interface ....................................................................................................
2.1.6 EEPROM Interfaces ..............................................................................................
2.1.7 HDMI ................................................................................................................
2.1.8 Video DAC Interface ..............................................................................................
2.1.9 High-Speed USB Interface .......................................................................................
2.1.10 SPI Flash Interface ...............................................................................................
2.1.11 UART Interface ...................................................................................................
2.1.12 I2C Interface .......................................................................................................
2.1.13 Debug Interface ..................................................................................................
2.1.14 PCI Express Interface ...........................................................................................
2.1.15 MSP430™ Interface .............................................................................................
Clock .........................................................................................................................
Power ........................................................................................................................
2.3.1 DM388 Power From PMIC .......................................................................................
DM388 EVM Muxing Options .............................................................................................
2.4.1 McASP0 Muxing ...................................................................................................
2.4.2 McASP1 Muxing ...................................................................................................
2.4.3 McASP0_AXR [4:5] Lines Muxing ..............................................................................
2.4.4 McASP5 and GPIO Selection for VC Board ...................................................................
2.4.5 MCA1_AHCLKX Muxing .........................................................................................
UART2, I2C2, and VOUT Muxing ........................................................................................
18
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35
Physical Description ........................................................................................................... 37
3.1
3.2
2
10
12
13
13
14
15
16
Interfaces and Power Section of DM388 Base EVM ................................................................. 17
2.1
3
DM388 Processor ..........................................................................................................
Block Diagram ..............................................................................................................
Key Features ................................................................................................................
Functional Overview .......................................................................................................
Memory and I/O Mapping .................................................................................................
GPIO Mapping ..............................................................................................................
I2C Address Mapping ......................................................................................................
DM388 EVM Layout........................................................................................................
Connectors, Switches, Headers, and Jumpers .........................................................................
3.2.1 SD/MMC Card Holder ............................................................................................
3.2.2 JTAG Header ......................................................................................................
3.2.3 Component Video Out ............................................................................................
3.2.4 VGA Connector ....................................................................................................
3.2.5 Composite Video Connector .....................................................................................
3.2.6 USB-OTG Connector .............................................................................................
Contents
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3.3
3.4
3.2.7 HDMI OUT Connector ............................................................................................
3.2.8 Ethernet Connector ...............................................................................................
3.2.9 PCI Express Connector ..........................................................................................
3.2.10 UART Connector .................................................................................................
3.2.11 EEPROM Header ................................................................................................
3.2.12 MSP JTAG Header ..............................................................................................
3.2.13 Audio Connectors ................................................................................................
3.2.14 Power Switches ..................................................................................................
3.2.15 Boot Mode Switches .............................................................................................
3.2.16 Reset Switch SW4 ...............................................................................................
3.2.17 Power-On Reset Switch SW7 ..................................................................................
3.2.18 GPIO Switches and LEDs .......................................................................................
3.2.19 Fuses ..............................................................................................................
Test Points ..................................................................................................................
Expansion Connector ......................................................................................................
47
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64
66
A
Schematics ........................................................................................................................ 73
B
Assembly Drawings .......................................................................................................... 112
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List of Figures
1-1.
DM388 Processor .......................................................................................................... 10
1-2.
DM388 EVM Block Diagram .............................................................................................. 12
2-1.
PCIe Clock AC-Decoupling Capacitors – Host Clocking Enabled ................................................... 24
2-2.
IP_EVM_12V................................................................................................................ 26
2-3.
TPS_EVM_5V0 ............................................................................................................. 26
2-4.
BCK2_3V3
2-5.
EVM_5V0 .................................................................................................................... 27
2-6.
EVM_3V3 .................................................................................................................... 28
2-7.
PMIC Circuitry .............................................................................................................. 30
2-8.
McASP0 Muxing ............................................................................................................ 31
2-9.
McASP1 Muxing ............................................................................................................ 32
2-10.
McASP0 Muxing ............................................................................................................ 33
2-11.
MCA5 and GPIO Selection
2-12.
Required Output Selection ................................................................................................ 35
2-13.
UART2, I2C2, and VOUT Muxing ........................................................................................ 36
3-1.
TMDXEVM388 Base EVM (Top View) .................................................................................. 38
3-2.
..............................................................................
SD/MMC Card Holder .....................................................................................................
JTAG Header ...............................................................................................................
Component Video Connectors............................................................................................
Component Video Cable ..................................................................................................
VGA Connector .............................................................................................................
VGA Male-to-Male Cable ..................................................................................................
Composite Video Out Connector .........................................................................................
Composite Video Cable ...................................................................................................
USB-OTG Connectors .....................................................................................................
HDMI Connector ............................................................................................................
HDMI Cable .................................................................................................................
Ethernet Connectors .......................................................................................................
PCIe Connector.............................................................................................................
PCIe Cable ..................................................................................................................
UART Connector ...........................................................................................................
MSP430 UART Connector ................................................................................................
UART F-F Serial Cable ....................................................................................................
EEPROM Header ..........................................................................................................
MSP JTAG Header.........................................................................................................
Audio Codec Connectors ..................................................................................................
HP-Out, Mic-in, and Line-in Cables ......................................................................................
EVM Switch Arrangement .................................................................................................
Boot Mode Switches .......................................................................................................
Reset Switches .............................................................................................................
GPIO Switch and LEDs....................................................................................................
Major Test Points ...........................................................................................................
Version History .............................................................................................................
DM385 Block Diagram .....................................................................................................
Memory Map ................................................................................................................
McASP Muxing .............................................................................................................
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
A-1.
A-2.
A-3.
A-4.
4
..................................................................................................................
...............................................................................................
TMDXEVM388 Base EVM (Bottom View)
List of Figures
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A-5.
DM385 McASP ............................................................................................................. 78
A-6.
McASP Muxing and Decoders ............................................................................................ 79
A-7.
McASP B-B Connection ................................................................................................... 80
A-8.
AIC3106 ..................................................................................................................... 81
A-9.
GMII0 Interface ............................................................................................................. 82
A-10. Ethernet Controller 0 ....................................................................................................... 83
A-11. Ethernet Controller 1 ....................................................................................................... 84
A-12. NAND Flash ................................................................................................................. 85
A-13. GPMC B-B Connector ..................................................................................................... 86
A-14. DM385 MMC0, MMC1, and MMC2 ...................................................................................... 87
A-15. DM385 DDR0 Terminations............................................................................................... 88
A-16. DDR0-0, DDR0-1, DDR0-2, and DDR0-3 ............................................................................... 89
A-17. DM385 VIN0, VOUT0, and VOUT1 ...................................................................................... 90
A-18. Video B-B Connector ...................................................................................................... 91
A-19. DM385 Serial Interfaces ................................................................................................... 92
A-20. SPI Flash .................................................................................................................... 93
A-21. DM385 HDMI, SATA, USB0, and USB1 ................................................................................ 94
A-22. USB Interface ............................................................................................................... 95
A-23. DM385 PCIe, JTAG, and Video .......................................................................................... 96
A-24. PCIe Connector............................................................................................................. 97
A-25. SerDes Clocks .............................................................................................................. 98
A-26. DM385 Clocks .............................................................................................................. 99
......................................................................................................
...........................................................................................................
DM385 Power .............................................................................................................
DM385 VSS ...............................................................................................................
TPS659113-A .............................................................................................................
TPS659113-B .............................................................................................................
TPS51116..................................................................................................................
TPS65232..................................................................................................................
Power Selection ...........................................................................................................
Power In....................................................................................................................
Changes in Schematics ..................................................................................................
DDR3_TP ..................................................................................................................
Assembly Drawing (Top Side) ..........................................................................................
Assembly Drawing (Bottom Side).......................................................................................
A-27. Power Monitor CPU
100
A-28. Power Monitors
101
A-29.
A-30.
A-31.
A-32.
A-33.
A-34.
A-35.
A-36.
A-37.
A-38.
B-1.
B-2.
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102
103
104
105
106
107
108
109
110
111
113
114
5
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List of Tables
6
0-1.
Document History ............................................................................................................ 7
0-2.
Board History ................................................................................................................. 7
0-3.
Acronyms ..................................................................................................................... 8
1-1.
Memory and I/O Map ...................................................................................................... 14
1-2.
GPIO Mapping .............................................................................................................. 15
1-3.
I2C Address Mapping
2-1.
McASP1 Mapping .......................................................................................................... 19
2-2.
Board Information .......................................................................................................... 21
2-3.
I2C Power-Monitor Addresses
2-4.
McASP0 Mapping .......................................................................................................... 31
2-5.
McASP1 Muxing ............................................................................................................ 33
2-6.
McASP0_AXR Muxing ..................................................................................................... 34
2-7.
Channel Selection .......................................................................................................... 35
2-8.
Channel Selection and Output ............................................................................................ 35
2-9.
I/O Expander GPIOs ....................................................................................................... 36
3-1.
Pinout of SD/MMC Card Holder .......................................................................................... 40
3-2.
Pinout of JTAG Header .................................................................................................... 41
3-3.
Pinout of RGB Connector ................................................................................................. 42
3-4.
Pinout of VGA Connector ................................................................................................. 43
3-5.
CV OUT...................................................................................................................... 45
3-6.
Pinout of USB-OTG Connector ........................................................................................... 46
3-7.
Pinout of HDMI OUT ....................................................................................................... 47
3-8.
Pinout of Ethernet Connectors
3-9.
Pinout of PCIe Connector ................................................................................................. 51
3-10.
Pinout of UART Connectors .............................................................................................. 53
3-11.
Pinout of EEPROM Header ............................................................................................... 55
3-12.
Pinout of MSP JTAG Header ............................................................................................. 56
3-13.
Pinout of Audio LINE OUT ................................................................................................ 57
3-14.
Pinout of Audio LINE IN ................................................................................................... 57
3-15.
Pinout of Audio MIC IN .................................................................................................... 58
3-16.
Boot Mode Combinations
3-17.
Warm Reset Push-Button ................................................................................................. 61
3-18.
Cold-Reset Push-Button ................................................................................................... 62
3-19.
Test Point Signals .......................................................................................................... 65
3-20.
64-Pin Video Expansion Connector (J27) ............................................................................... 66
3-21.
128-Pin Video Expansion Connector (J28) ............................................................................. 67
3-22.
128-Pin GPMC Expansion Connector (J19) ............................................................................ 68
3-23.
128-Pin MCASP Expansion Connector
70
3-24.
64-Pin GPMC Expansion Connector
71
......................................................................................................
............................................................................................
...........................................................................................
.................................................................................................
.................................................................................
....................................................................................
List of Tables
16
25
49
60
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Preface
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About This Manual
Developed with Mistral Solutions, the DM388 base evaluation module (EVM) enables developers to start
immediate evaluation of DM388 processors and begin building on different video applications.
This document describes the board level operations of the DM388 base EVM. The EVM is based on the
Texas Instruments DM388 Applications Processor.
National Conventions
The DM388 base EVM will sometimes be referred to as the DM814x EVM or the base EVM.
Information About Cautions
This Document may contain cautions.
This is an Example of a Caution Statement
A caution statement describes a situation that could potentially damage your software, hardware, or other
equipment. The information in a caution is provided for your protection. Please read each caution
carefully.
Related Documents, Application Notes, and User Guides
Information regarding the DM388 processor can be found at http://www.ti.com.
Table 0-1. Document History
Version Number
Description of Changes
0.1
Draft version
Table 0-2. Board History
PCB Revision
History
Revision A
Created
Revision B
HDDAC and GMPC sections changed
DaVinci, MSP430, Code Composer Studio are trademarks of Texas Instruments.
NEON is a trademark of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited.
Mentor is a registered trademark of Mentor Graphics Corporation.
PCI Express is a registered trademark of PCI-SIG.
Skype is a trademark of Skype.
DesignWare is a registered trademark of Synopsys, Inc..
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Acronyms
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Acronyms
Table 0-3 lists the acronyms used in this document.
Table 0-3. Acronyms
Acronym
Ball grid array
CCS
Code Composer Studio
DDR
Double data rate
EEPROM
Electrically erasable programmable read-only memory
ESD
Electrostatic discharge
EVM
Evaluation module
GPIO
General purpose Input/Output
GPMC
General purpose memory controller
2
IC
Inter-integrated circuit
JTAG
Joint test action group
LCD
Liquid crystal display
LED
Light emitting diode
MAC
Media access controller
McBSP
Multichannel buffered serial port
OTG
On-the-go
PCB
Printed circuit board
PHY
Physical transceiver
SD/MMC
SDRC
SDRAM
Secure digital and multimedia card
SDRAM controller
Synchronous dynamic random access memory
SPI
Serial peripheral interface
SPDT
Single pole double throw
UART
Universal asynchronous receiver transmitter
USB
8
Definition
BGA
Universal serial bus
About This Manual
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Chapter 1
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Introduction to DM388 Base EVM
This chapter provides a functional overview of the DM388 processor, key features, and a high-level block
diagram of the DM388 base EVM design. This chapter also provides information about memory and I/O
mapping, GPIO mapping, and inter-integrated circuit (I2C) mapping of devices on the DM388 base EVM.
Topic
1.1
1.2
1.3
1.4
1.5
1.6
1.7
...........................................................................................................................
DM388 Processor ...............................................................................................
Block Diagram ...................................................................................................
Key Features .....................................................................................................
Functional Overview ...........................................................................................
Memory and I/O Mapping ....................................................................................
GPIO Mapping....................................................................................................
I2C Address Mapping ..........................................................................................
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10
12
13
13
14
15
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9
DM388 Processor
1.1
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DM388 Processor
The DM388 processor mainly consists of ARM® Cortex®-A8 RISC CPU with NEON™ technology
extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors.
Figure 1-1. DM388 Processor
The DM388 processor is a highly integrated, programmable platform that leverages DaVinci™ technology
from TI to meet the processing needs of the following applications:
• IP-netcam
• Digital video server (DVS)
• High-definition webcam
• High-definition embedded video communication modules
• Remote media display (RMD) and interactive digital signage
In
•
•
•
•
•
•
•
•
•
addition to these markets, this user's guide also addresses:
3G gesture control (HDI)
Video doorbell
Telemedicine
Test and Measurement
Analytics
Instrumentation
Inspection and machine vision
Avionics
Skype™ endpoint applications
An ARM Cortex-A8 RISC CPU with a NEON extension, a TI C674x VLIW floating-point DSP core, and
high-definition video and imaging coprocessors provide the programmability.
The ARM Cortex-A8 32-bit RISC microprocessor with NEON floating-point extension includes:
10
Introduction to DM388 Base EVM
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DM388 Processor
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•
•
•
•
•
32KB of instruction cache
32KB of data cache
256KB of L2 cache
176KB of on-chip boot ROM (128KB of secure ROM and 48 KB of public ROM)
64KB of RAM
The DM388 processor is a 609-pin, Pb-Free BGA Package that has a 0.5-mm ball pitch with Via Channel
technology to reduce the printed-circuit board (PCB) cost. The core of the ARM Cortex-A8 CPU operates
at a speed of up to 1 GHz.
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Block Diagram
1.2
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Block Diagram
Figure 1-2 shows the block diagram of the DM388 processor.
Figure 1-2. DM388 EVM Block Diagram
+12V DC
TPS51116
+5V DC
TPS65232
+3.3V DC
TPS76901
+1.8V
TPS659113
+3.3V
Core
Voltages
20.00MHz
+5V
1GB DDR3
EEPROM
SD/MMC card
IR Receiver
+1.5V
BUS FET
Switch
McASP-1
OSC-0
27.00MHz
HDMI_OUT
DDR-0
I2C-0
McASP-1/3/5
HDMI_I2C
ESD Protection
I2C-1
VIN-0
VOUT-0
VOUT-1
CSI2
I2C2/UART2
SD/MMC-1
UART-1
B-B
Connector
McASP-0/2/4
BUS FET
Switch
McASP-0
OSC-1
OSC
USB-OTG
Mini-AB
Audio Line
IN/OUT/HP/Mic
AIC3106
HDMI
Connector
B-B
Connector
32.768
KHz Osc
NAND Flash-256MB
Boot SW
USB-1
DM388 EVM
USB-OTG
Mini-AB
SPI Flash
USB-0
RJ-45
RGMII PHY
AR8031
RGMII0
RJ-45
RGMII PHY
AR8031
RGMII1
GPMC
SPI-0
SPI-1
TIMER
DCAN-0
SD/MMC-0
UART-0/DCAN1
B-B
Connector
MAX3221
DB-9
PCIe Connector
PCI-e
VCO 100MHz
I2C-0
PCF8575
(1 & 2)
I2C-2
PCF8575
(3)
LEDs
Switches
JTAG Connector
JTAG
TV_OUT0-1
HDDAC
Video Amplifier
(THS7360)
Composite
Video
RGB
VGA
Connector
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12
Introduction to DM388 Base EVM
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Key Features
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1.3
Key Features
The DM388 processor includes the following key features:
• High-performance digital media System-on-Chip (SoC)
• Memory
– 32-bit DDR3 SDRAM interface (DDR0)
– 1GB (256MB x4 chip) of memory from Micron is used on the DDR3 interface of the DM388 EVM
– 256MB of NAND flash memory from Micron with socket for placing the NAND is used on the
DM388 base EVM
• Power for the processor is derived from integrated power-management IC TPS659113.
• Analog video-out interface – Composite SD video from the TV OUT interface of the processor is
available on the yellow RCA jack of the board.
• Component video out (RGB) from the HD digital-to-analog converter (DAC) interface of the processor
is available on the board of the VGA connector.
• Digital video-out interface – Supported by an on-chip high-definition multimedia interface (HDMI)
transmitter with a resolution and frame rate of 1080p60.
• USB interface – Dual high- and full-speed USB OTG 2.0 port with integrated PHYs
• Ethernet interface – Two RGMII ports interfaced to the MAC have a speed of 10/100/1000 Mbps.
• Stereo audio interface – Audio Line IN, Mic IN, Speaker OUT and Headset OUT
• Serial Interfaces – SD/MMC connector in 4-bit SD mode Supporting up to 48 MHz
• A 32-MB serial peripheral interface (SPI) flash memory is available on the DM388 EVM for SPI
booting.
• Ultra-low-power MSP430™ microcontroller (MCU) to monitor the current flow of the DM388 device with
INA226
• Dip switch to select different boot mode configurations
• Standard 20-pin JTAG debug interface
• Video, GPMC, and MCASP expansion board-to-board connectors are available to connect different
application boards of the DM814x and AM387x (such as video camera, video conference, video
security, and catalog application).
• PCI Express® 2.0 port with integrated PHY and one lane supports up to 5.0 GT/s
• RoHS compliant
1.4
Functional Overview
The DM388 EVM is based on the DM388 application processor from TI. The Micron memory
MT41J256M8HX-125 is connected to the DM388 processor through the SSTL_15 interface. The DDR
memory on the board consists of four chips (MT41J256M8HX-125) of micron memory that each have a
capacity of 2Gb (256MB), and the memory has an excellent on-chip ODT for better signal quality. NAND
flash memory is connected to the processor through the GPMC interface. The chip enable pin of the
NAND device is connected to GPMC_nCS0 of the DM388 processor.
Analog video outputs of the EVM support composite TV outputs on the main board. The composite video
outputs are available on the respective connector by default.
The DM388 base EVM supports multiple video input options from the application board through VIN0,
VIN1, and the camera port. Any of the following interfaces can be active at a given point of time when the
catalog application board is connected through the expansion board to the board connectors.
• S-video input digitized through video decoder (TVP5147)
• Composite video input digitized through video decoder (TVP5147)
• RGB video input digitized through video decoder (TVP7002)
• VGA input digitized through video decoder (TVP7002)
• Camera input from parallel camera interface
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Memory and I/O Mapping
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The EVM has a SD/MMC slot connected by using an SD/MMC1 4-bit interface on the main board. The
SD/MMC2 interface is routed to the expansion connector for WLAN module on application board. The
EVM has two RGMII Ethernet ports (RGMII0, RGMnII1) using two external AR8031 Gigabit PHY devices
that are interfaced to the processor through the RGMII interface. It has a PCIe2.0 ×4 connector with
integrated PHY on the DM814x processor that can be configured as Root complex or Endpoint.
The EVM supports two UART interfaces (DM388 UART, MSP430 UART) through two serial ports (DB9
connector) on the main board. The board has two USB mini-AB connectors to support a high-speed USB
OTG2.0 interface. One Stereo Line IN, MIC IN, Speaker OUT, and Stereo Headset OUT audio interface is
supported through the audio codec TLV320AIC3106IRGZT on the EVM. The audio codec on the EVM is
controlled by the I2C0 and MCASP1 interface.
The EVM has five DIP switches for various purposes such as selecting different boot modes, GPIO
toggling, video-out enable, NAND and SPI flash selection, and resetting the GPIO. The EVM also includes
three reset push-button switches, one SYS_WAKE push-button switch, and three slide switches for power
flow. The EVM has a standard 20-pin JTAG header (10 × 2 1.27-mm pitch) for debug interface. This JTAG
port can be accessed through Code Composer Studio™ development version 4.0 and higher. The EVM is
powered by a 12-V, 5-A external power supply, and a TPS659113 power-management device provides
the required CPU core voltages and I/O voltages for the DM388 processor.
1.5
Memory and I/O Mapping
Table 1-1 provides the memory and I/O mapping for the DM388 EVM.
Table 1-1. Memory and I/O Map
Device
Start Address
End Address
Size
GPMC
0x0000_0000
0x1FFF_FFFF
512MB
GPMC
On-chip ROM
0x4000_0000
0x4001_FFFF
128KB
Secure ROM
0x4002_0000
0x4002_BFFF
48KB
ROM
0x402F_0000
0x402F_FFFF
64KB
Secure RAM
0x4030_0000
0x4031_FFFF
128KB
OCMC SRAM
PCIe
0x2000_0000
0x2FFF_FFFF
256MB
PCIe
DDR
0x8000_0000
0xFFFF_FFFF
2GB
DDR
I2C0
0x4802_8000
0x4802_8FFF
4KB
I2C0 peripheral registers
I2C1
0x4802_A000
0x4802_AFFF
4KB
I2C1 peripheral registers
On-chip RAM
14
Description
I2C2
0x4819_C000
0x4819_CFFF
4KB
I2C2 peripheral registers
SPI0
0x4803_0000
0x4803_0FFF
4KB
SPI0 peripheral registers
SPI1
0x481A_0000
0x481A_0FFF
4KB
SPI1 peripheral registers
MMC
0x481D_8000
0x481E_7FFF
64KB
MMC/SD/SDIO1 peripheral
registers
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1.6
GPIO Mapping
Table 1-2 lists some of the GPIOs that are used in the DM388 base EVM.
Table 1-2. GPIO Mapping
Number
GPIO Name
Source
1
ENET_WoL_INT
GP0[12]
2
HDMI_CT_HPD
PCF8575 DEVICE-3
Enabling load switch
3
HDMI_LS_OE
PCF8575 DEVICE-3
Enabling level shifter
4
DISABLE_SD
PCF8575 DEVICE-3
5
DISABLE_SF
PCF8575 DEVICE-3
SD and SF channel control of
video amplifier
6
BYPASS_SD
PCF8575 DEVICE-3
7
BYPASS_SF
PCF8575 DEVICE-3
8
FILTER1
PCF8575 DEVICE-3
9
FILTER1
PCF8575 DEVICE-3
10
IO_EXP2_GP1
PCF8575 DEVICE-2
GPIO used in CATALOG board
11
IO_EXP2_GP2
PCF8575 DEVICE-2
GPIO used in CATALOG
12
MCA0_DEC_A
MCA0_DEC_B
PCF8575 DEVICE-2
Purpose
WoL interrupt
To bypass LPF of SD and SF in
VA
Selectable filter for SF channels
MCASP0 decoder select
Lines
13
MCA1_MUX_SEL
PCF8575 DEVICE-2
MCASP1 MUX select lines
14
MCA0/1/3_RSEL_A
MCA0/1/3_RSEL_B
PCF8575 DEVICE-2
MCASP0/1/3_R decoder select
lines
15
PCF8575_INT_IO2
GP0[13]
16
MCA0_AXR9
PCF8575 DEVICE-2
GPIO used in VC board
17
IO_EXP2_GP3
PCF8575 DEVICE-2
GPIO used in VC board
18
MCA5_MUX_OE
PCF8575 DEVICE-2
To select B/T GPIO N
MCA5_AHCLKX
19
VOUT_FLD_SEL1
PCF8575 DEVICE-3
20
VOUT_FLD_SEL2
PCF8575 DEVICE-3
21
GPIO_VC_1
PCF8575 DEVICE-2
22
GPIO_VC_2
PCF8575 DEVICE-2
GPIO used on the application
board
23
MCA1_MUX2_nOE
PCF8575 DEVICE-2
MCASP1 muxing selection
24
ENET_INT
GP1[10]
Interrupt from EMAC PHY ICs
25
PCF8575_INT_IO1
GP1[4]
Interrupt from PCF8575 (U39)
26
EN_BCK2_LS
TPS659113-GPIO 7
Enabling load switch
27
EN_BCK3_TPS65232
TPS659113-GPIO 2
Enabling PCI_3V3
28
EN_TPS51116
TPS659113-GPIO 0
Enabling DDR supply
29
MSP430_INT
PCF8575 DEVICE- 1
Interrupt from MSP430
30
TPS_INT1
TPS659113-INT 1
31
TPS_SLEEP
PCF8575 DEVICE-1
Sleep for TPS659113
32
PCI_SW_RESETn
PCF8575 DEVICE-1
PCIe reset
33
IR_REMOTE_OFF
PCF8575 DEVICE 1
To control IR sensor
34
UART0_OFF
PCF8575 DEVICE-1
UART0 controlling
35
EXP_ETH_RESET
PCF8575 DEVICE-1
Ethernet reset
36
GPMC_ADD_SELn
PCF8575 DEVICE-1
To select either GPMC or HDMI
lines
37
SW_VOUT_EN
TDA04H0SK1 device
Video software enable
38
GPMC_nWP
TDA04H0SK1 device
GPMC write-protect
39
RESET_GPIO
TDA04H0SK1 device
Enabling PCI POR buffer
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Interrupt
To provide the pin muxing
option for the VOUT0_FLD and
VOUT1_FLD pins
Interrupt from PMIC
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I2C Address Mapping
1.7
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I2C Address Mapping
Table 1-3 provides the address mapping for the I2C interface on the DM388 base EVM.
Table 1-3. I2C Address Mapping
16
I2C Used
Device
Address
I2C0
Audio codec
0x18
I2C0
EEPROM
0x50
I2C0
TPS659113
0x2D
I2C0
I/O Expander-PCF8575
0x20
I2C0
PCF8575-2
0x23
I2C2
PCF8575-3
0x20
I2C1
HDMI
I2C0 and I2C2
Application board devices
I2C0
MSP430
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Chapter 2
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Interfaces and Power Section of DM388 Base EVM
This chapter provides information about the interfaces and power section of the DM388 EVM.
Topic
2.1
2.2
2.3
2.4
2.5
...........................................................................................................................
EVM Interfaces ...................................................................................................
Clock ................................................................................................................
Power ...............................................................................................................
DM388 EVM Muxing Options................................................................................
UART2, I2C2, and VOUT Muxing...........................................................................
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18
25
25
30
35
17
EVM Interfaces
2.1
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EVM Interfaces
The main interfaces of the DM388 base EVM are:
• DDR
• NAND flash
• SD/MMC
• Audio
• Ethernet
• EEPROM
• HDMI
• Composite video
• Component video
• VGA
• USB
• SPI flash
• UART
• JTAG
• PCI Express
2.1.1 DDR Interface
The DM388 supports single 32-bit mDDR/DDR2/DDR3 SDRAM interface (DDR0). The DDR3 device on
the DM388 base EVM is the MT41J256M8HX-125 with configuration of 256MB x 8. Four 8-bit, 256-MB
DDR3 devices are interfaced to 32-bit memory mDDR/DDR2/DDR3 SDRAM interface (DDR0). Hence a
total of 1GB of DDR3 memory is interfaced DM814x/AM387x.
The DDR3 supply voltage (1.5 V) and termination voltage (0.75 V) for the DDR3 chips is generated by the
synchronous buck converter (TPS51116). The reference voltage (0.75 V) is generated by a voltage
divider. For the DQ and DQS lines, series termination is 0E; 22E series termination is provided for DM
lines. All of the address and control lines have a resistor (51E) and a 0.1-µF capacitor parallel termination.
DM0 and DQS0 are the references for write and read to the first DDR chip DDRx_0 (in each DDR
interface). DM1 and DQS1 are the references for the second DDR chip (DDRx_1), DM2 and DQS2 are
the references for the third DDR chip (DDRx_2), and DM3 and DQS3 are the references for the fourth
DDR chip (DDRx_3).The address lines A[0:14], bank address lines BA[0:2], and the control signals are
connected to each of the DDR3 chips.
2.1.2 NAND Interface
The MT29F2G16ABAEAWP:E is the NAND flash device used on the DM388 EVM. The memory
configuration is 2Gb with a 16-bit databus. The NAND flash is interfaced to the GPMC port of the DM388.
NAND flash has 16 multiplexed I/O lines for data and address. The address lines are selected by enabling
the GPMC_ADVN_ALE (address latch enable) to high. The chip select of NAND flash is connected to
GPMC_nCS0 of the GPMC controller. A DIP switch (SW5) is provided on the DM388 base EVM to select
between onboard NAND booting or NOR booting on an application board (video security). For onboard
NAND booting, SW5.1 should be on. NAND IC is placed inside the 48-pin socket on the EVM.
The NAND and SPI interface selection table is silkscreened on the board for user convenience.
2.1.3 SD/MMC Interface
The SD/MMC card connector (MHC-W21-601-LF) interfaces to the SD1/MMC1 port of the DM388. The
load switch (MIC94062YC6) controls the power supply to the MMC card (VMMC). VMMC is derived from
the EVM_3V3 supply. The enable pin of the load switch (U70) is connected to GP1[2]. The load switch is
enabled by default (resistor R266 connecting the GP1[2] pin to the EN pin of the load switch is not
mounted in the default configuration).
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The card detect pin of the SD/MMC connector is connected directly to the SD1_SDCD (ball G28) of the
DM388. The write-protect pin of the SD/MMC connector is not connected directly to the E29 pin of the
DM388; a resistor option is available if the write-protect feature is required. Write-protect is multiplexed
(muxed) with {UART0_DSRn/SPI[0]_SCS[2]n/I2C[2]_SDA/SD1_SDWP/GP1[3]}. By default, the SD/MMC
card is not write-protected (resistor R265 connects the pin to E29 as described in this paragraph). The
E29 pin is used for I2C2 data on the application boards as well as on the base board.
2.1.4 Audio Interface
The audio codec used in the DM388 base EVM is a TLV320AIC3106 device. The device is a low-power
stereo audio codec with a stereo headphone amplifier with single-ended or fully-differential configurations.
The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital
filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for
32-kHz, 44.1-kHz, and 48-kHz rates.
The stereo audio analog-to-digital converter (ADC) supports sampling rates from 8 kHz to 96 kHz and is
preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for lowlevel microphone inputs. A highly programmable PLL is included for flexible clock generation and support
for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz. The
audio codec operates at an analog supply of 3.3 V, a digital core supply of 1.8 V, and a digital I/O supply
of 3.3 V. A 24.576-MHZ clock is used as a master clock for the audio codec in the EVM.
The TLV320AIC3106 is controlled by I2C0 and McASP1 interfaces. McASP1 selection involves muxing
logic because only two McASP instances are available on the DM388 device. Mux logic supports all of the
legacy expansion boards of DM814x, which has six instances of McASP.
McASP1 is mapped to the onboard codec, McASP1, McASP3, and McASP5. McASP1 signals
MCA1_ACLKX, MCA1_AFSX, MCA1_AXR[0], and MCA1_AXR[1] are mapped to other interfaces using
two ICs of Quad x [2:1] MUX SN74CB3Q3257PWR (U36 and U49). Two GPIOs from I/O expander
PCF8575PWR (U50) are used to select the required interfaces (onboard codec, McASP1, McASP3, and
McASP5) from McASP1 lines using MUX logic.
GPIO MCA1_MUX2_nOE from I/O expander U50 is used to enable any multiplexer IC. GPIO
MCA1_MUX_SEL is used to select a particular channel (or particular interface) from the MUX that is
enabled.
Table 2-1 lists the McASP1 mapping.
Table 2-1. McASP1 Mapping
MCA1_MUX2_nOE
MCA1_MUX_SEL
MUX Selected
0
0
MUX2 (CH 1)
McASP5
McASP1 is mapped to
0
1
MUX2 (CH 2)
McASP3
1
0
MUX1 (CH 1)
McASP1 on expansion
connector
1
1
MUX1 (CH 2)
Onboard codec
The default state of GPIOs from the I/O expander is high (logic 1). By default, McASP1 is mapped to the
onboard codec.
NOTE: Interfaces that use McASP1, McASP3, and McASP5 cannot be tested simultaneously.
Whenever McASP1 must be routed to expansion connectors to test the interfaces on the
application boards, the onboard codec will be automatically disabled.
2.1.5 EMAC Interface
The EMAC software controls the flow of packet data between the device and two external Ethernet PHYs,
with hardware flow control and quality-of-service (QOS) support. The EMAC software contains a 3-port
gigabit switch, where one port is internally connected and the other two ports are brought out externally.
Each external EMAC port supports 10Base-T (10 Mbps) and 100BaseTX (100 Mbps) in half- or full-duplex
mode, or 1000BaseT (1000 Mbps) in full-duplex mode.
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The EVM has two RGMII Ethernet ports (RGMII0, RGMII1) that use two external PHY AR8031 devices
that are interfaced to the processor through the RGMII interface. A single MDIO interface (MDIO clock and
MDIO data) is connected out to control the PHY configuration and status monitoring of RGMII0 and
RGMII1. Multiple external PHYs can be controlled by the MDIO interface. The EMAC software I/Os
operate at 3.3 V and are compatible with 2.5-V I/O signaling. Therefore, Ethernet PHYs with a 2.5-V I/O
interface can be used.
The AR8031 requires a single, 3.3-V power supply with an I/O level of 2.5 V. On-chip regulators provide
all other required voltages. The AR8031 embeds cable diagnostics test (CDT) technology on chip; this
allows measuring the cable length, detecting the cable status, and identifying remote and local PHY
malfunctions, bad or marginal patch cord segments, or connectors. Some of the problems that can be
detected include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and a
bad transformer. The AR8031 also supports Wake-on-LAN (WoL) to detect magic packet and notify the
sleeping system to wake up. The AR8031 integrates the termination R/C circuitry and the serial resistors
for the line side and no external parallel termination required between PHY and magnetics on the board.
The EVM uses two external 25-MHz crystals (Y2 and Y7) to generate local clock for RGMII0 and RGMII1.
The PHY uses three clock signals (RX_CLK, MDIO_CLK, and GTX_CLK) and four transmit and receive
data lines. Signal RX_CLK comes from PHY to MAC, and signal GTX_CLK comes from MAC to PHY.
2.1.6 EEPROM Interfaces
The EVM uses a 256-Kb I2C CMOS Serial EEPROM CAT24C256WI-GT3 to store the board ID
information. EEPROM is interfaced to the DM388 processor by using I2C0. The CAT24C256 device is a
256-Kb Serial CMOS EEPROM, internally organized as 512 pages of 64 bytes each. The device features
a 64-byte page write buffer and supports the standard (100 kHz) and fast (400 kHz) I2C protocol.
The write-protect pin (WP) of EEPROM has been pulled low internally by default. If the EEPROM memory
must be write-protected, pins 7 and 8 of J19 must be shorted by using a jumper.
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Table 2-2 lists the board ID information that is stored. This information is read-only data and should be
used to get complete details of the board.
Table 2-2. Board Information
Field Name
Size (in Bytes)
Field Contents
Header
4
0xAA 0x55 0x33 0xEE
Board name
8
813X_EVM
Version
4
B001 (Alphabet) = Beta.001 PCB Version
B – Rev B Board
001 : Batch No
BOM version
2
XX (Number)
ECN version
2
XX (Number)
Test package version
2
XX (Number)
Batch code
4
WW YY (2 digits for week and 2 digits for year)
Board serial number
4
XXXX (4-digit number)
Configuration option
18
None
Processor mount option
1
0x01: Socketed
0x02: Soldered
Reserved
32719
None
2.1.7 HDMI
The DM388 processor includes an HDMI transmitter for digital video and audio data to display devices.
The HDMI interface consists of a digital HDMI transmitter (HDMI 1.3a-compliant transmitter) core with a
TMDS encoder, a core wrapper with interface logic and control registers, and a transmit PHY. An HDMI
connector is connected to the processor through ESD protection device (TPD12S016PWR [U4]). The
HDMI is controlled by the I2C1 interface of the DM388. The HDMI has three differential pairs of data lines
and one differential pair of clock lines.
The HDMI has the following features:
• Hot-plug detection
• Supports up to a 165-MHz pixel clock
– 1920 × 1080p at 75 Hz with 8-bit per component color depth
– 1600 × 1200 at 60 Hz with 8-bit per component color depth
• Support for deep-color mode:
– 10-bit per component color depth up to 1080p at 60 Hz (maximum pixel clock = 148.5 MHz)
– 12-bit per component color depth up to 720p and 1080i at 60 Hz (maximum pixel clock = 123.75
MHz)
• The TMDS clock to the HDMI-PHY is up to 185.625 MHz.
NOTE: The GPMC_A22 signal is internally muxed with CE_REMOTE_IN on pin N2, and the
GPMC_A23 signal is muxed with HDMI_HP_IN on R8 of the DM814x processor. GPMC lines
or HDMI lines are selected through switch IC U98 (SN74CB3Q3257PWR) using a GPIO
signal (GPMC_ADD_SELn) from U39 (PCF8575PWR). By default, HDMI lines are selected
and used in the board.
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2.1.8 Video DAC Interface
The DM388 processor supports one SD DAC module (AVDAC1BGTVV4) from the OMAP4430 and a
GS70 3-channel HD DAC. The SD DAC module supports composite video standard with sampling rates
up to 60 MSPS. The composite video signal (TV_OUT0) is connected directly from the processor to RCA
jack J8. An option is available to pass the TV_OUT0 signal through video amplifier THS7360IPW (U5).
The HD DAC consists of three channels of 10-bit current-steering DACs. The output of the DAC can drive
the composite video signal to 37.5-Ω load directly. The HD DAC also contains an internal band gap to
provide a low-noise reference voltage to the video DAC. The HD DAC supports sampling rates up to 150
MSPS.
HD DAC signals HDDAC_A, HDDAC_B, and HDDAC_C from the processor are connected to component
video connectors J7 (Green), J9 (Blue), and J6 (Red) through video amplifier THS7360IPW (U5). HD DAC
signals from U5 are also routed to VGA connector P1. The VGA control signals and the sync signals are
routed to P1 through an ESD protection device TPD7S019-15DBQR (U7).The control signals required for
U5 are taken from I/O expander PCF8575PWR (U14) by using I2C2 lines.
2.1.9 High-Speed USB Interface
The USB controller provides a low-cost connectivity solution for numerous consumer portable devices by
providing a mechanism for data transfer between USB devices with a line and bus speed of up to 480
Mbps. The USB subsystem of the DM388 device has two independent USB 2.0 modules (USB0 and
USB1) built around two OTG controllers; the OTG supplement feature (support for a dynamic role change)
is also supported. Each port can support a dual-role feature allowing for additional versatility that enables
operation capability as a host or a peripheral. Both ports have identical capabilities and operate
independently.
Each USB controller is built around the Mentor® USB OTG controller and the TI GS70 PHY. Each USB
controller has a user-configurable 32KB of endpoint FIFO, and has the support for 15 transmit endpoints
and 15 receive endpoints in addition to endpoint 0. The USB uses the CPPI 4.1 DMA to accelerate data
movement through dedicated DMA hardware. The two USB modules share the CPPI DMA controller and
accompanying queue manager, interrupt pacer, power-management module, and PHY and UTMI clock.
The PHY does not have a built-in charge pump and requires an external power source to source the 5-V
VBUS power. The PHY has a built-in charge detection for device mode and a control capability for host
applications for implementing an external charge detection capability.
For an OTG controller, the procedure of the controller to assume the role of a host or a device is governed
by the state of the ID pin. Also, the procedure is controlled by the USB cable connector type. The DM388
device bonds out these ID pins and allows the control to be handled directly from the connector (for
example, the USB controller assumes the role based on the cable end inserted into the mini A/B
connector [J3 and J4] on the EVM). A jumper option is available on the EVM to ground the USB_ID pin for
USB0 (J12) and USB1 (J13). This jumper option enables the EVM to be used in Host Only mode.
2.1.10 SPI Flash Interface
The SPI flash interface is a high-speed synchronous serial I/O port that allows a serial bit stream (4 to 32
bits) to be shifted in and out of the device at the programmed bit-transfer rate. The DM388 processor
supports four SPIs. The SPI0 signal from DM388 controls SPI flash memory device. A 32-Mb SPI flash
memory (W25X32VSFIG) on the EVM provides SPI booting. For SPI booting, SW5.2 must be on and
SW5.1 must be off.
2.1.11 UART Interface
The UART performs serial-to-parallel conversions on data received from a peripheral device, and performs
parallel-to-serial conversions on data received from the CPU. There are three UART interfaces (UART0,
UART1, and UART2) available for the DM388. One UART interface is available for the MSP430 on the
EVM. UART0 on the base EVM is selected by enabling the UART0_OFF signal to low. UART0 is also
routed to application boards through board-to-board connectors on the EVM. The UART interface
(UART0) can be used on the base EVM or the application boards. UART0 supports a baud rrate of up to
3.6 Mbps. UART1 is connected to the IR receiver on the EVM. The IR receiver is selected by enabling the
IR_REMOTE_OFF signal to LOW.
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2
2.1.12 I C Interface
The device includes three I2C modules that provide an interface to other devices that are compliant with
version 2.1 of the Philips Semiconductors Inter-IC bus (I2C-bus) specification. External components
attached to this 2-wire serial bus can transmit and receive 8-bit data to and from the device through the
I2C module.
The I2C port supports the following features in the DM388:
• Standard and fast modes from 10 to 400 kbps
• Noise filter to remove noise 50 ns or less
• Seven- and 10-bit device addressing modes
• Multimaster transmitter and slave receiver mode
• Multimaster receiver and slave transmitter mode
• Combined master transmit and receive and receive and transmit modes
• Two DMA channels, one interrupt line
• Built-in FIFO (32 byte) for buffered read or write
I2C0 of DM388 is being shared across devices like the audio codec, I/O expanders, MSP430 MCU,
TPS659113, and EEPROM. I2C2 is shared across the I/O expander and VGA connector. Also, I2C0 and
I2C2 are routed to the board-to-board expansion connector to support the interfaces on the application
board. The HDMI interface uses I2C1 signals.
2.1.13 Debug Interface
The EVM supports two JTAG debug interfaces: DM388-JTAG and MSP430-JTAG. Debug connectors are
used to test, debug, execute, trace, and download the program to the target unit. The following two JTAG
connectors are on the board:
• 14-pin MSP430-JTAG header
• 20-pin DM388-JTAG Header
2.1.14 PCI Express Interface
PCIe is a serial-based technology that uses low-voltage differential signaling (LVDS) to reduce the number
of data-signal lines and high-frequency clock signals in a point-to-point interconnect arrangement between
two devices. PCIe also eliminates multiple host presences on the same bus.
The PCIe subsystem contains the DesignWare® core (DWC), PCIe dual-mode (DM) core, and SerDes
PHY. The DM core operates in endpoint (EP) mode or root-complex (RC) port mode. The core supports a
single in-port and a single out-port. The operating mode of the PCIe core is set to EP or RC based on: the
value sampled from the BOOTMODE[4:0] pins, use as a secondary boot loader, or application software by
configuring the PCIE_CFG [PCIE_DEVTYPE] register. The DM core can be switched between modes at
run time by applying a power-on reset.
PCIe supports high-speed data transfer at rates of up to 5.0 Gbps per lane per direction. PCIe on the EVM
uses PCI_3V3 and IP_EVM_12V as the supply voltages. The clock required for clocking data and PHY
functional clocks are generated by the PHY through the supplied external input 100-MHz differential clock
from the device (U56 [CDCM61002RHBR]) on the EVM.
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Use the following instructions to enable the PCIe to be compatible with the spread spectrum clock of a
PC.
1. Remove the PCIe clock AC-decoupling capacitors on C218, C219, C228, and C229 (see Figure 2-1).
2. Place a 0805 size 270-pF or 0.1-µF capacitor across the pads of C218 and C228 for negative
reference clock and across the pads of C219 and C229 for positive reference clock that are in
proximity.
3. Configure the DM388 board as EP and configure the computer as RC.
Figure 2-1. PCIe Clock AC-Decoupling Capacitors – Host Clocking Enabled
2.1.15 MSP430™ Interface
All of the power supplies on the base EVM and application boards are provided with power measurement
capability by using the ultra-low-power MSP430 MCU.
Use the MSP430-based controller in combination with a current and power monitor and the I2C interface
(INA226) for power monitoring. In the DM388 base EVM, 11 INA current monitors are available for
monitoring the currents of the following supplies:
• PLL_1V8
• HDMI_CSI_1V8
• CVDD_ARM
• VDDQ_DM_1V5
• DVDD
• VDDA_1V8
• DVDD_GPMC
• DVDD_C
• CORE_VDD
• CVDD_DSP
• VMMC
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Table 2-3 shows the I2C addresses if the power monitors.
Table 2-3. I2C Power-Monitor Addresses
2.2
Supply Number
Supply Name
Address
1
PLL_1V8
1000000
2
HDMI_CSI_1V8
1000001
3
CVDD_ARM
1000010
4
VDDQ_DM_1V5
1000011
5
DVDD
1000100
6
VDDA_1V8
1000101
7
DVDD_GPMC
1000110
8
DVDD_C
1000111
9
CORE_VDD
1001000
10
CVDD_DSP
1001001
11
VMMC
1001010
Clock
The EVM has the following clocks:
• Y1 – Provides 32.768-kHz real-time clock (RTC) to the power-management IC (TPS659113).
• Y2 – Provides 25-MHz clock for Ethernet PHY (RGMII0).
• Y3 – Provides 20-MHz device (DEV) clock that generates the majority of the internal reference clocks
for the DM388.
• Y4 – Provides 32.768-kHz auxiliary clock to the MSP430 MCU.
• Y5 – Provides 25-MHz clock to generate differential clock for the PCI and SerDes CLK.
• Y6 – Provides 27-MHz auxiliary (AUX) clock that can be used as a source for the audio, video PLLs, or
both.
• Y7 – Provides 25-MHz clock for Ethernet PHY (RGMII1).
• U58 – Provides 32768-Hz clock input that is provided at the CLKIN32 pin to serve as a reference clock
in place of the RTCDIVIDER clock for the following modules:
– RTC
– GPIO0, GPIO1, GPIO2, and GPIO3
– TIMER1, TIMER2, TIMER3, TIMER4, TIMER5, TIMER6, and TIMER7
– SYNCTIMER
2.3
Power
The main power input for the EVM system is provided by using an external 12-V universal adapter. The
other voltages required for the main board are derived by using onboard regulators on the main board.
Four major switching regulators are used to derive power for the DM388 EVM.
• TPS65232 (U16) – Gives TPS_EVM_5V0, BCK2_3V3, PCI_3V3
• TPS659113 (U25) – Gives power to DM388
• TPS51116 (U46) – DDR power supply
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Figure 2-2 shows the 12-V supply circuitry.
Figure 2-2. IP_EVM_12V
IP_EVM_12V
DPDT
Switch
4XPCIe CONN
TPS_EVM_5V
Triple Buck
Regulator
(TPS65232)
BUCK2_3V3
TPS_PCI_3V3
DDR Buck
Regulator
(TPS51116)
optional
DDR3
Memory
VDDQ 1V5
Application
Boards
Expansion
Connectors
PMIC
(TPS659113)
PCI CONN
CORE_VDD
DM388
Copyright © 2016, Texas Instruments Incorporated
Figure 2-3- shows the TPS_EVM_5V0 supply circuitry.
Figure 2-3. TPS_EVM_5V0
EVM_5V0
TPS_EVM_5V0
EXP_EVM_5V0
On-Board
Peripherals
Application
Boards
DDR BUCK
Regulator
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Figure 2-4 shows the BCK2_3V3 supply circuitry.
Figure 2-4. BCK2_3V3
TPS_BCK2_3V3
PMIC
(TPS659113)
BCK2_3V3
Power Switch
(MIC94062YC6)
EVM_3V3
PMIC
(TPS659113)
EXP_EVM_3V
Application
Boards
LS_EVM_3V3
Copyright © 2016, Texas Instruments Incorporated
Figure 2-5 shows the EVM_5V0 supply circuitry.
Figure 2-5. EVM_5V0
EVM_5V0
HDMI
Interface
Power
Distribution
Switch(TPS2065)
USB0/ 1 OTG
VGA ESD Suppressor
(TPD7S019) & VGA Connector
Voltage Supervisory CKT
Power Monitoring CKT
(INA226)
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Power
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Figure 2-6 shows the EVM_3V3 supply circuitry.
Figure 2-6. EVM_3V3
EVM_3V3
MCASP MUXING
Section
ETH0_AVD
D_3V3
Ferrite
Bead
ETH1_AVD
D_3V3
Ferrite
Bead
Ethernet PHY
(AR8031-AL1A)
Ethernet
Connector-
Ethernet PHY
(AR8031-AL1A)
Ethernet
Connector-
NAND Flash
(MT29F2G16AADWP:D)
IR Receiver
(TSOP34840)
EEPROM
(CAT24C256WI-)
PROM_EVM_3V3
RS-232 Line
Driver
(MAX3221CPWR)
UART DB-9
Connector
SPI Flash
(W25X32VSFIG)
IO Expanders(3)
(PCF8575PWR)
HDMI ESD
Suppressor
C-Video O/P
Video Amplifier
(THS7360IPW)
VGA Connector
Component
Video Conn
CLOCKGENERATOR
(CDCM61002RHBR)
32.768KHz
Oscillator
VGA Port ESD
Protection
(TPD7S019)
RGB O/P
3V3_VDDA
Ferrite
Bead
C-Video
Connector
DM813x
(CLKIN32)
Reset Circuitry
Of DM385
Micro-Controller
RS-232 Line
Driver
(MAX3221CPWR)
UART DB-9
Connector
Power Monitor
IC
LDO(TPS71711DCKR)
TPS_VHD_1V1
HD-DAC Section
Of DM385
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2.3.1 DM388 Power From PMIC
The following list provides the power requirements of the DM388 processor that the power-management
IC (TPS659113 [U25]) generates and distributes.
• DM388 I/O supply: TPS_VDDA_1V8-1.8V
• DM388 core supply
– VDD1(CVDD_ARM)-1.2V
– VDD2 (CVDD_DSP)-1.2V
– CORE_VDD-1.2V
• DM388 auxiliary supplies
– DVDD_GPMC-3.3V
– DVDD-3.3V
– DVDD_C-3.3V
– DVDD_SD-3.3V
– VDDA_1V8-1.8V
– HDMI_CSI_1V8-1.8V
– VDDA_USB_1V8-1.8V
– VDDQ_1V5-1.5V
• DM388 VDAC supply
– VDAC_3V3-3.3V
– VDAC_1V8-1.8V
• PLL supply PLL_1V8-1.8V
The input supply to the power manager is from the TPS_EVM_5V0 and TPS_BCK2_3V3 to generate
different voltage rails. The TPS659113 is controlled by the I2C0 interface of the DM388 processor and the
address is 0X2D.
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DM388 EVM Muxing Options
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Figure 2-7 shows the PMIC circuitry.
Figure 2-7. PMIC Circuitry
VDD_CDC
Clock Generator
(CDCM61002)
PMIC IC
TPS659113
TPS_EVM_5V0
Audio Codec
(TLV320AIC3106)
VRTC
TPS_VDD_CDC
VDAC_3V3
VDAC_1V8
Internal LDOs
and
DC-DC CNTRL
VDDA_USB_1V8
PLL_1V8
HDMI_CSI_1V8
HDMI_CSI_1V8
DM388
CORE_VDD
TPS_BCK2_3V3
CVDD_ARM
CVDD_DSP
Internal SMPS
VDDA_1V8
Copyright © 2016, Texas Instruments Incorporated
2.4
DM388 EVM Muxing Options
On the DM388 base Board EVM, McASP muxing has been implemented because of the shortage of
McASP interfaces compared to Centaurus. In Centaurus, six McASP (McASP[0:5]) interfaces are
available, and in the DM388 only two McASP (McASP[0:1]) interfaces are available. Because the DM388
EVM supports four other application boards that use the McASP[0:5], the muxing option is given for the
available McASPs on the DM388 EVM.
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2.4.1 McASP0 Muxing
Figure 2-8 shows the muxing of McASP0.
Figure 2-8. McASP0 Muxing
MCA0_DEC_A
MCA0_nOE_CONN0
NOT USED
MCA0_nOE_CONN4
McASP-0
Decoder
MCA0_DEC_B
nOE
McASP-0
Bus FET
Switch
(1)
MCA0_nOE_CONN2
MCA0_nOE_CONN0
McASP-0
To Expansion
Connector
ACLKX,
AFSX, AXR-0,1,2,3
MCA0_nOE_CONN2
McASP-0
From DM813X
ACLKX, AFSX
ACLKR, AFSR
AXR-0, 1, 2, 3
nOE
(ACLKX,AFSX,
ACLKR,AFSR,
AXR0,1,2,3)
McASP-2
To Expansion
Connector
McASP-0
Bus FET
Switch
(2)
ACLKX, AFSX,
AXR-0,1, 2, 3
MCA0_nOE_CONN4
nOE
McASP-4
To Expansion
Connector
Copyright © 2016, Texas Instruments Incorporated
The McASP0 signals MCA0_ACLKX, MCA0_AFSX, and MCA0_AXR[0:3] are mapped using MUXs, and
MCA0_AFSR and MCA0_CLKR are directly connected to expansion connector.
To map McASP0 exclusively to one of the McASPs (McASP0, McASP2, McASP4), a decoder has been
used with the controlling inputs taken from the I/O expander GPIOs (MCA0_DEC_A and MCA0_DEC_B).
By configuring these two GPIOs , McASP0 mapping is achieved (see Table 2-4).
The default state of GPIOs from the I/O expander is high (logic 1). By default, McASP0 is mapped to
McASP0.
Table 2-4 shows the McASP0 mapping.
Table 2-4. McASP0 Mapping
MCA0_DEC_B
MCA0_DEC_A
Output From Decoder
Mux Selected
McASP0 is Mapped to
0
0
Not used
—
—
0
1
MCA0_nOE_CONN4 is
LOW
BUS FET SWITCH-2
(CH 2)
McASP4
1
0
MCA0_nOE_CONN2 is
LOW
BUS FET SWITCH-2
(CH 1)
McASP2
1
1
MCA0_nOE_CONN0 is
LOW
BUS FET SWITCH-1
McASP0
NOTE: Interfaces on the application boards that use McASP0, McASP2, or McASP4 cannot be
tested at the same time.
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2.4.2 McASP1 Muxing
Figure 2-9 shows the McASP1 muxing.
Figure 2-9. McASP1 Muxing
ACLKX,AFSX,
AXR-0, AXR-1
McASP-1 to
On-board CODEC
McASP-1
4 x 1:2
MUX (1)
nOE
ACLKX,AFSX,
AXR-0, AXR-1
S
McASP-1
From DM813X
McASP-1 to
Expansion Connector
(ACLKX, AFSX,
AXR-0, AXR-1)
ACLKX,AFSX,
AXR-0, AXR-1
McASP-3 to
Expansion Connector
McASP-1
4 x 1:2
MUX (2)
GPIOs from
IO Expander
nOE
MCA1_MUX2_nOE
S
MCA1_MUX_SEL
ACLKX,AFSX,
AXR-0, AXR-1
McASP-5 to
Expansion Connector
Copyright © 2016, Texas Instruments Incorporated
McASP1 is mapped to the onboard codec, McASP1, McASP3, McASP5. McASP1 signals MCA1_ACLKX,
MCA1_AFSX, MCA1_AXR[0], and MCA1_AXR[1] are mapped to other interfaces using two 4 × [2:1]
MUXs. Two GPIOs from the I/O expander are used to select the required interfaces (codec, McASP1,
McASP3, McASP5) from McASP1 lines using a MUX.
GPIO MCA1_MUX2_nOE from the I/O expander is used to enable any multiplexer IC, and GPIO
MCA1_MUX_SEL is used to select a particular channel (or particular interface) from the MUX that is
enabled.
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Table 2-5 provides the McASP1 muxing.
Table 2-5. McASP1 Muxing
MCA1_MUX2_nOE
MCA1_MUX_SEL
MUX Selected
McASP1 is Mapped to
0
0
MUX2 (CH 1)
McASP5
0
1
MUX2 (CH 2)
McASP3
1
0
MUX1 (CH 1)
McASP1 on expansion
connector
1
1
MUX1 (CH 2)
Onboard codec
The default state of GPIOs from the I/O expander is high (logic 1). By default, McASP1 is mapped to the
onboard codec.
NOTE: Interfaces that use McASP1, McASP3, McASP5 cannot be tested at the same time. When
McASP1 must be routed to expansion connectors to test the interfaces on the application
boards, the onboard codec must be disabled.
2.4.3 McASP0_AXR [4:5] Lines Muxing
In Centaurus, McASP0 has five data channels (MCA0_AXR[0:9]), McASP1 has two data channels
(MCA1_AXR[0:3]), and McASP3 also has two data channels (MCA3_AXR[0:3]). In the DM388, McASP0
has three data channels (MCA0_AXR[0:5]) and McASP1 has one data channel (MCA1_AXR[0:1]).
Because McASP3 is muxed with McASP1 signals and MCA0_AXR[4:5], MCA1_AXR[2:3], and
MCA3_AXR[2:3] are used on the application boards, hence the EVM provides one more muxing option to
select between MCA0_AXR[4:5], MCA1_AXR[2:3], and MCA3_AXR[2:3].
Figure 2-10 shows the McASP0 muxing.
Figure 2-10. McASP0 Muxing
MCA0/1/3_RSEL_A
MCA0/1/3_RSEL_B
McASP0/1/3
DECODER
NOT USED
MCA0/1/3_nOE_3
MCA0/1/3_nOE_1
MCA0/1/3_nOE_0
nOE
MCA0/1/3_nOE_0
AXR_4, AXR_5
McASP-0 To
Expansion
Connector
AXR_2, AXR_3
McASP-1 To
Expansion
Connector
AXR_2, AXR_3
McASP-3 To
Expansion
Connector
McASP-0
Bus FET
Switch (3)
MCA0/1/3_nOE_1
nOE
MCA0_AXR [4]
MCA0/1/3_nOE_3
nOE
McASP-0
Bus FET
Switch (4)
Copyright © 2016, Texas Instruments Incorporated
MCA0_AXR[4:5] is used as an input to MUXs, and a decoder is used to select one interface at a time.
Input to the decoder is taken from the I/O expander. The following GPIOs are HIGH by default and map
the inputs to McASP0_AXR[4:5] that are connected to expansion connector.
• MCA0_RSEL_A
• MCA1_RSEL_A
• MCA2_RSEL_A
• MCA0_RSEL_B
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DM388 EVM Muxing Options
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MCA1_RSEL_B
MCA3_RSEL_B
Table 2-6 lists the selections.
Table 2-6. McASP0_AXR Muxing
Output from decoder
MUX selected
MCA0_AXR[4:5] is
Mapped to
MCA0/1/3_ RSEL_B
MCA0/1/3_ RSEL_A
0
0
Not used
—
—
0
1
MCA0/1/3_nOE_3
BUS FET SWITCH-4
MCA3_AXR[2:3]
1
0
MCA0/1/3_nOE_1
BUS FET SWITCH-3
(CH 2)
MCA1_AXR[2:3]
1
1
MCA0/1/3_nOE_0
BUS FET SWITCH-3
(CH 1)
MCA0_AXR[4:5]
NOTE: McASP0 and McASP1 muxing must be considered before selecting the MCA0_AXR[4:5]
lines. Ensure that McASP0 lines are selected by using other muxing schemes before opting
for MCA0_AXR[4:5] lines to McASP0. Similarly, before opting MCA0_AXR[4:5] lines that are
mapped to MCA1_AXR[2:3] and MCA3_AXR[2:3], ensure that McASP1 and McASP3 are
selected using other muxing schemes.
2.4.4 McASP5 and GPIO Selection for VC Board
The McASP5 signals (MCA5_AFSX and MCA5_AXR0) are used as GPIOs on the video conference
board. McASP5 signals are mapped from McASP1 on the DM388 EVM, and McASP1 lines on the DM388
cannot be configured as GPIOs. As a result, DM388 EVM provides a muxing option of McASP5 lines
(MCA5_AFSX and MCA5_AXR0) that are mapped from McASP1 and two GPIOs (GPIO_VC_1 and
GPIO_VC_2) from the I/O expander. The output (MCA5_AFSX_EXP and MCA5_AFSX_EXP) from the
MUX stage is routed to the expansion connector.
When the VCONF board is plugged in, signals on the expansion connectors are used as GPIOs. These
signals can be used as McASP5 lines when other application boards are plugged in.
Figure 2-11 shows the selection of either MCA5 lines or GPIOs from the I/O expander by using a GPIO
(MCA5_MUX_OE) from the same I/O expander.
Figure 2-11. MCA5 and GPIO Selection
MCA5_ASFX
MCA5_AFSX/AXR0
MCA5_AXR0
To Expansion Connector
(either MCA5 lines or GPIOs )
nOE1/2
Bus FET
Switch
GPIO_VC_1
GPIO_VC_2
GPIO_VC_1
GPIO_VC_2
( GPIOs from
IO Expander )
nOE3/4
MCA5_MUX_OE
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Table 2-7 shows the selection.
Table 2-7. Channel Selection
MCA5_MUX_OE
Channel Selected
Signals on Expansion Connector
1
CH 1
MCA5_AFSX and MCA5_AXR0
0
CH 2
GPIO_VC_1 and GPIO_VC_2
By default, MCA5_AFSX and MCA5_AXR0 are available on the expansion connector if McASP5 is
enabled in the McASP1 muxing scheme.
2.4.5 MCA1_AHCLKX Muxing
MCA1_AHCLKX is used in the Centaurus EVM to provide an option to get MCLK for the onboard codec or
it will be routed to the expansion connector. In the DM388, ensure that MCA1_AHCLKX provides the
same option as it does in the Centaurus EVM.
GPIO MCA1_MUX_SEL from the I/O expander is used to select the required output (see Figure 2-12).
Figure 2-12. Required Output Selection
MCA1_AHCLKX_1
B_AIC_MCLK
To On-board Codec
nOE1
Bus FET
Switch
DM_AUD_CLKIN1
MCA1_MUX_SEL
( GPIOs from IO Expander )
To Expansion
Conncector
nOE2
Copyright © 2016, Texas Instruments Incorporated
Table 2-8 lists the channel selection and output.
Table 2-8. Channel Selection and Output
MCA1_SEL_OE
Channel Selected
OUTPUT
1
CH 1
B_AIC_MCLK (codec)
0
CH 2
DM_AUD_CLKIN1 (expansion)
By default, MCA1_AHCLKX is connected to the onboard codec (B_AIC_MCLK) because the GPIO from
the I/O expander is high.
2.5
UART2, I2C2, and VOUT Muxing
In Centaurus, UART3 (TX and RX) and I2C2 (SCL and SDA) are pin multiplexed. These signals are
connected to the expansion connector and are used on the application boards as UART3 or as I2C2
signals. However, the UART3 interface is not available on the DM388. Instead of UART3, UART2 signals
are used on the DM388 device. Because the I2C2 signals are not pin multiplexed with UART2 signals, the
DM388 EVM provides an option to select UART2 (TX and RX) or I2C2 (SCL and SDA) and route the
selected signals to the expansion connector.
The UART3 (RTS and CTS) signals are pin multiplexed with UART0 (RIN and DTRn) in
Centaurus.UART2 is used instead of UART3 on the DM388, and UART2 (RTS and CTS) lines are pin
multiplexed with VOUT0 and VOUT1 lines.
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The UART2_RTS signal is pin muxed with VOUT0_FLD and CAM_PCLK, and the UART2_CTS signal is
pin muxed with VOUT1_FLD. The EVM provides a logic using a MUX, a buffer, and a decoder to get
UART3 or I2C2 and VOUT0 and VOUT1 (see Figure 2-13).
Figure 2-13. UART2, I2C2, and VOUT Muxing
NOT USED
UART2/I2C2_nOE
VOUT_FLD_SEL1
VOUT_FLD_SEL2
DECODER
CAM_PCLK_nOE
VOUT_FLD_nOE
I2C2_SCL
I2C2_SDA
I2C
BUFFER
UART2/I2C2_nOE
To Expansion Connector
I2C2 lines
(I2C2_SCL/UART2_RXD_EXP
I2C2_SDA/UART2_TXD_EXP)
OE
UART2_TX
UART2_RX
UART
BUFFER
UART2 Lines
(TX/RX)
nOE
VOUT0/1_FLD
VOUT0_FLD/UART2_RTS
VOUT1_FLD/UART2_CTS
To Expansion Connector
(VOUT0_FLD & VOUT1_FLD)
Bus FET
Switch
VOUT_FLD_nOE
CAM_PCLK_nOE
UART2/I2C2_nOE
nOE1
UART2(RTS/CTS)
nOE2
To Expansion Connector
(UART2_RTSn_EXP &
UART2_CTSn_EXP)
nOE3
Copyright © 2016, Texas Instruments Incorporated
Table 2-9 lists the I/O expander GPIOs (VOUT_FLD_SEL1 and VOUT_FLD_SEL2) that are used as inputto-decoder.
By default, inputs to the decoder are high, so VOUT_FLD_nOE = LOW is selected and VOUT0_FLD and
VOUT1_FLD signals are routed to the expansion connector. Because all other outputs from the decoder
are high, when UART2 and I2C2_nOE are high, the I2C2 buffer is enabled. So, I2C2, VOUT0_FLD, and
VOUT1_FLD lines will be enabled by default.
When UART2 and I2C2_nOE are LOW, the UART2 signals (TX, RX, RTS, and CTS) are available on the
expansion connectors. I2C2 and VOUT lines are not available whenever UART2 signals are selected.
Table 2-9. I/O Expander GPIOs
36
VOUT_FLD_SEL2
VOUT_FLD_SEL1
Output From Decoder
Device Selected
0
0
Not used
—
OUTPUT
—
0
1
UART2/I2C2_nOE
Bus FET switch (CH 3)
UART2 signals. I2C2
buffer is disabled.
1
0
CAM_PCLK_nOE
I2C buffer and VOUT bus
FET switch (CH 2)
VOUT0_FLD as i/p
(CAM_PCLK). I2C2
buffer is enabled.
1
1
VOUT_FLD_nOE
I2C buffer and VOUT bus
FET switch (CH 1)
VOUT0_FLD and
VOUT1_FLD. I2C2 buffer
is enabled.
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Chapter 3
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Physical Description
This chapter provides information about the physical characteristics of the board.
Topic
3.1
3.2
3.3
3.4
...........................................................................................................................
DM388 EVM Layout ............................................................................................
Connectors, Switches, Headers, and Jumpers .......................................................
Test Points ........................................................................................................
Expansion Connector .........................................................................................
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38
39
64
66
37
DM388 EVM Layout
3.1
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DM388 EVM Layout
The DM388 base EVM has the following dimensions:
• 317.5 mm × 187.96 mm
• 10-layer PCB
• 2-cm height (completed PCB)
Figure 3-1 shows the top view of the DM388.
Figure 3-1. TMDXEVM388 Base EVM (Top View)
38
Physical Description
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Connectors, Switches, Headers, and Jumpers
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Figure 3-2 shows the bottom view of the DM388.
Figure 3-2. TMDXEVM388 Base EVM (Bottom View)
3.2
Connectors, Switches, Headers, and Jumpers
The DM388 base EVM has several connectors, switches, headers, and jumpers that serve various
purposes. These components are detailed in the subsections that follow.
3.2.1 SD/MMC Card Holder
The SD/MMC card holder is a 28-pin connector that is on the top side of the board; the card holder
provides an interface to a SD/MMC card. Figure 3-3 shows the location of SD/MMC connector on the base
EVM.
Figure 3-3. SD/MMC Card Holder
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Connectors, Switches, Headers, and Jumpers
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Table 3-1 provides the pinout details of the SD/MMC card holder (J22).
Table 3-1. Pinout of SD/MMC Card Holder
Pin Number
Signal Name
Pin Number
Signal Name
1
MMC1_DAT3
15
MMC1_SD_CD
2
MMC1_CMD
16
NC
3
GND
17
NC
4
VMMC
18
GND
5
MMC1_CLK
19
NC
6
GND
20
NC
7
MMC1_DAT0
21
GND
8
MMC1_DAT1
22
NC
9
MMC1_DAT2
23
NC
10
NC
24
NC
11
NC
25
NC
12
NC
26
NC
13
NC
27
GND
14
MMC1_SD_WP
28
GND
3.2.2 JTAG Header
A JTAG emulator can be used for advanced debugging by connecting it to the JTAG header on the top
side of the EVM. The JTAG header has 20 pins (10 × 2, 1.27-mm pitch). If the user has a 14-pin JTAG
version, then users must contact their emulator supplier for the appropriate adapter. All JTAG signal levels
are 3.3 V.
Figure 3-4 shows the location of the JTAG header.
Figure 3-4. JTAG Header
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Table 3-2 provides the pinout details of the JTAG header (J18).
Table 3-2. Pinout of JTAG Header
Pin Number
Signal Name
1
TMS
2
TRSTN
3
TDI
4
TDIS
5
TVD
6
KEY
7
TDO
8
GND1
9
TCKRTN
10
GND2
11
TCLK
12
GND3
13
EMU0
14
EMU1
15
SRST
16
GND4
17
EMU2
18
EMU3
19
EMU4
20
GND5
3.2.3 Component Video Out
A T.V. or monitor that supports HD DAC inputs can be connected to the component video connectors
(RGB connectors) of the base EVM board by using a component video cable. HD DAC signals from the
DM388 processor are connected to the RGB connectors through video-amplifier U5. Component video
connectors J7 (green), J9 (blue), and J6 (red) are 4-pin connectors (see Figure 3-5).
Figure 3-5. Component Video Connectors
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Table 3-3 provides the pinout details of the RGB connectors.
Table 3-3. Pinout of RGB Connector
Pin Number
Signal
1
VIDEO OUT
2
GND
3
GND
4
GND
Figure 3-6 shows an example of a component video cable.
Figure 3-6. Component Video Cable
3.2.4 VGA Connector
A VGA cable can be used to connect a T.V. or monitor to the DM388 EVM through the VGA connector
(P1) provided on the board. HD DAC signals from the video-amplifier (U5) are shared with VGA connector
P1. VGA connector P1 is a 15-pin female connector.
Signals from U5 are passed through ESD protection IC TPD7S019-15DBQR and then go to the VGA
connector.
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Figure 3-7 shows a top view and side view of the VGA connector.
Figure 3-7. VGA Connector
Table 3-4 provides the pinout details of the VGA connector.
Table 3-4. Pinout of VGA Connector
Pin Number
Signal Name
1
Red video
2
Green video
3
Blue video
4
NC
5
GND
6
GND
7
GND
8
GND
9
EVM_5V0
10
GND
11
NC
12
I2C2_SDA_BUF
13
VGA_HSYNC
14
VGA_VSYNC
15
I2C2_SCL_BUF
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Figure 3-8 shows an example of a VGA male-to-male cable.
Figure 3-8. VGA Male-to-Male Cable
3.2.5 Composite Video Connector
A composite video (CV) cable is used to connect a T.V. or monitor to the base board through the RCA
jack (J8) provided on the board. Figure 3-9 shows J8 as viewed from the card edge.
Figure 3-9. Composite Video Out Connector
Composite video connector J8 is a 4-pin RCA connector. Do not plug the cable into connector J8 while the
board is powered on.
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Table 3-5 provides the pinout details of the CV OUT on the RCA connector.
Table 3-5. CV OUT
Pin Number
Signal
1
VIDEO OUT
2
GND
3
GND
4
GND
Figure 3-10. Composite Video Cable
3.2.6 USB-OTG Connector
The DM388 EVM is equipped with two USB-OTG connectors (J3 and J4). Both USB interfaces are
capable of dynamic role change; they can act as a host or as a device. TPD2E001DRLR ESD protection
devices U2 and U3 are used for USB0 and USB1, respectively.
While configuring the OTGs in host-only mode, the header must be placed on J10 and J12 for USB0, and
on J11 and J13 for USB1. Type A to mini-AB adapter is used to connect a memory stick, mouse, or other
USB slave devices. The USBBx_DRV_VBUS signal from the processor is given to TPS2065DR (U6 and
U1). This signal is driven high, enabling the TPS2065 IC to provide USBx_VBUS voltage to a connected
slave device.
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Figure 3-11 shows the connectors on the side of the board.
Figure 3-11. USB-OTG Connectors
The USB-OTG connector is a 9-pin, mini-AB connector. Table 3-6 provides the pinout details of the USBOTG connector (J3 and J4).
Table 3-6. Pinout of USB-OTG Connector
46
Pin Number
Pin Name
Pin Number
Pin Name
1
VCC
6
SH1
2
D+
7
SH2
3
D–
8
SH3
4
ID
9
SH4
5
GND
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3.2.7 HDMI OUT Connector
Any T.V. or monitor with an HDMI connection can be connected to the DM388 EVM through the HDMI
connector. This connector is on the top side of the EVM. The HDMI signals from the processor are routed
to the HDMI connector (J2) through an ESD protection device (TPD12S016PWR [U4]). Figure 3-12 shows
the HDMI connector.
Figure 3-12. HDMI Connector
The HDMI connector is a 23-pin, type-A receptacle connector. Table 3-7 provides the pinout details of
HDMI OUT J2.
Table 3-7. Pinout of HDMI OUT
Pin Number
Signal Name
Pin Number
1
HDMI_D2+
2
GND
3
HDMI_D2–
4
HDMI_D1+
5
GND
6
HDMI_D1–
7
HDMI_DO+
8
GND
9
HDMI_DO–
10
HDMI_CLK+
11
GND
12
HDMI_CLK–
13
CE_REMOTE_OUT
14
NC
15
DDC_CLK
16
DDC_DAT
17
GND
18
5V_OUT_HDMI
19
HDMI_HP_OUT
20
GND
21
GND
22
GND
21
GND
—
—
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Figure 3-13 shows an example of an HDMI cable.
Figure 3-13. HDMI Cable
3.2.8 Ethernet Connector
The DM388 EVM has two RJ-45 connectors with magnetics for RGMII0 and RGMII1 interfaces. Both
connectors are connected to the respective Ethernet PHY transceivers (AR8031-AL1A) through parallel
termination. The AR8031-AL1A supports WoL interrupt to detect the magic packet and notify the sleeping
system to wake up. The ENETx_WoL signal from U52 or U66 is given to GP0[12] of the DM388 processor
through an OR gate (U53).
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Figure 3-14 shows the Ethernet connectors.
Figure 3-14. Ethernet Connectors
Table 3-8 provides the pinout details of the Ethernet connectors.
Table 3-8. Pinout of Ethernet Connectors
Pin Number
Signal Name
Pin Number
Signal Name
1
GND
2
PHY_VDD_2V5
3
TRD[3]P
4
TRD[2]N
5
TRD[2]P
6
TRD[2]N
7
TRD[1]P
8
TRD[1[N
9
TRD[0]P
10
TRD[0]N
D1
ENET_LED_LINK
D2
GND
D3
ENET_LED_RX
D4
EVM_3V3
SH1
GND
SH2
GND
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3.2.9 PCI Express Connector
The EVM has four PCIe 2.0 connectors with integrated PHY on the DM388 device. The dual mode (DM)
core operates in endpoint (EP) mode or root complex (RC) port mode. The core supports one in port and
one out port. The operating mode of the device, the role that the PCIe core assumes, is set to EP or RC
based on the value that is sampled from the BOOTMODE[4:0] pins. Figure 3-15 shows the PCIe
connector.
Figure 3-15. PCIe Connector
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Table 3-9 provides the pinout details of the PCIe connector.
Table 3-9. Pinout of PCIe Connector
Pin Number
Pin Description
Pin Number
B1
IP_EVM_12V
A1
PRSNT#
B2
IP_EVM_12V
A2
IP_EVM_12V
B3
IP_EVM_12V
A3
IP_EVM_12V
B4
GND
A4
GND
B5
NC
A5
TCK
B6
NC
A6
TDI
B7
GND
A7
NC
B8
PCI_3V3
A8
TMS
B9
TRSTn
A9
PCI_3V3
B10
NC
A10
PCI_3V3
B11
NC
A11
PCI_CON_PORz
B12
NC
A12
GND
B13
GND
A13
REFCLKp
B14
CON.PCIE_TXP0
A14
REFCLKn
B15
CON.PCIE_TXN0
A15
GND
B16
GND
A16
CON.PCIE_RXP0
B17
PRSNT#
A17
CON.PCIE_RXN0
B18
GND
A18
GND
B19
NC
A19
NC
B20
NC
A20
GND
B21
GND
A21
NC
B22
GND
A22
NC
B23
NC
A23
GND
B24
NC
A24
GND
B25
GND
A25
NC
B26
GND
A26
NC
B27
NC
A27
GND
B28
NC
A28
GND
B29
GND
A29
NC
B30
NC
A30
NC
B31
PRSNT#
A31
GND
B32
GND
A32
NC
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Figure 3-16 shows an example of a PCIe cable.
Figure 3-16. PCIe Cable
3.2.10 UART Connector
The EVM has two UART DB-9 connectors. One UART connector (P3) is connected to the DM388 through
the RS-232 transceiver. The other UART connector (P2) is connected to the MSP430 MCU through the
RS-232 transceiver. Figure 3-17 shows the UART connector of the DM388 device.
Figure 3-17. UART Connector
The voltage- and current-monitoring results calibrated by the MSP430 MCU can be viewed on the console
through MSP430 UART connector.
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Figure 3-18 shows the UART connector of the MSP430.
Figure 3-18. MSP430 UART Connector
Table 3-10 provides the pinout details of the UART connectors.
Table 3-10. Pinout of UART Connectors
Pin Number
Description
Pin Number
Description
1
NC
7
RTS
2
RXD
8
CTS
3
TXD
9
NC
4
NC
10
UART_GND
5
GND
11
UART_GND
6
NC
—
—
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Figure 3-19 shows a UART F-F serial cable.
Figure 3-19. UART F-F Serial Cable
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3.2.11 EEPROM Header
The DM388 EVM has five 2-pin EEPROM headers on the board. A jumper should be put on the header as
shown in Figure 3-20. To get the default connection from the DM388, place the jumper between pins 1
and 2 , 3 and 4, 5 and 6, and 9 and 10. Do not place a jumper between pins 7 and 8. Pins 7 and 8 must
be shorted for the write-protect function of EEPROM.
Figure 3-20. EEPROM Header
Table 3-11 provides the pinout details of the EEPROM header.
Table 3-11. Pinout of EEPROM Header
Pin Number
Description
Pin Number
Description
1
EVM_3V3
2
PROM_EVM_3V3
3
I2C0_SCL
4
PROM_I2C0_SCL
5
I2C0_SDA
6
PROM_I2C0_SDA
7
EVM_3V3
8
PROM_WP
9
GND
10
GND
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3.2.12 MSP JTAG Header
The MSP430 MCU is used to monitor the voltage and current ratings on the chosen power rails that are
connected to INA226 devices. INA226 devices are controlled through I2C0 lines. The MSP430 MCU must
be programmed through the MSP430 emulator that is connected to the MSP JTAG header (JP2). The
calibrated results can be observed on the console through the MSP-DB9 connector. Figure 3-21 shows
the MSP JTAG header.
Figure 3-21. MSP JTAG Header
The DM388 EVM has a 14-pin (2 × 7), 2.54-mm pitch JTAG header to access the MSP430 MCU. Table 312 provides the pinout details of the MSP JTAG header.
Table 3-12. Pinout of MSP JTAG Header
56
Pin Number
Signal Name
Pin Number
Signal Name
1
MSP430_TDO/TDI
8
NC
2
NC
9
NC
3
NC
10
NC
4
EVM_3V3
11
NC
5
NC
12
NC
6
NC
13
NC
7
MSP430_TCK
14
NC
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3.2.13 Audio Connectors
The DM81x and AM38x EVM includes an audio codec (TLV320AIC3106IRGZT) that is controlled through
MCASP1 and I2C0 lines. The EVM has four audio connectors for different functions, such as:
• Headphone OUT (J17)
• Speaker OUT (J16)
• Audio LINE IN (J15)
• Microphone input (J14)
Figure 3-22 shows the audio codec connectors.
Figure 3-22. Audio Codec Connectors
Each connector is a 3.5-mm, 4-pin, female stereo jack that is connected to the audio codec through a
coupling capacitor. Table 3-13 provides the pinout details of the audio LINE OUT connector.
Table 3-13. Pinout of Audio LINE OUT
Pin Number
Signal Name
1
GND
2
LEFT_OUT
3
RIGHT_OUT
4
NC
Table 3-14 provides the pinout details of the audio LINE IN connector.
Table 3-14. Pinout of Audio LINE IN
Pin Number
Signal Name
1
GND
2
LEFT_IN
3
RIGHT_IN
4
GND
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Table 3-15 provides the pinout details of the audio MIC IN connector.
Table 3-15. Pinout of Audio MIC IN
Pin Number
Signal Name
1
GND
2
LEFT_IN
3
Shorted to pin 2
4
GND
Figure 3-23 shows examples of HP-out, mic-in, and line-in cables.
Figure 3-23. HP-Out, Mic-in, and Line-in Cables
3.2.14 Power Switches
The DM388 EVM has one DPDT switch (SW1) for main power (12-V supply) and three SPST, 3-pin slide
switches for various purposes.
• SW3 (TOS65232 SW) – Connected to IP_EVM_12V when the switch position is toward the arrow
mark, and off when it is away from the arrow mark.
• SW6 (EXP_EVM_3V3 SW) – Connected to EXP_EVM_3V3 when the switch position is away from the
arrow mark, providing EVM_3V3 to the application board if required.
• SW8 (EXP_EVM_5V0 SW) – Connected to EXP_EVM_5V0 when the switch position is away from the
arrow mark, providing EVM_5V0 to the application board if required.
3.2.14.1 Default Switch Settings of EVM
Ensure the switches are positioned as follows when the EVM is powered on:
• SW3 – toward the arrow mark (right side)
• SW6 – toward the arrow mark (right side)
• SW8 – toward the arrow mark (left side)
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Figure 3-24 shows the arrangement of the switches.
Figure 3-24. EVM Switch Arrangement
3.2.15 Boot Mode Switches
Switch positions 1 to 5 of S1 determine the order of boot modes. The first boot mode listed for each S1
[5:1] configuration is the primary boot mode. If the primary boot mode fails, the second, third, and fourth
boot modes are executed in that order until a successful boot is completed.
The other positions of S1 [6:12] and SW10 [1:4] are reserved and are to be pulled down (off). The boot
mode order table is silk screened on the EVM board for user convenience.
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Figure 3-25 shows the boot mode switches.
Figure 3-25. Boot Mode Switches
Table 3-16 provides the boot mode combinations.
Table 3-16. Boot Mode Combinations
60
S1.1
S1.2
S1.3
S1.4
S1.5
0
1
0
0
1
NAND- NANDI2C- SPI- UART
Boot Mode Order
1
0
0
0
0
UART-XIP/WAIT(MUX0)(1)-MMC-SPI
1
1
1
0
1
MMC-SPI –UART-EMAC
0
0
1
0
0
EMAC-SPI-NAND-NANDI2C
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3.2.16 Reset Switch SW4
This switch generates a warm reset to the processor to reset all modules in the device except for the test
and emulation logic and the EMAC switch. Table 3-17 provides the two settings and results of the warmreset push-button.
Table 3-17. Warm Reset Push-Button
Setting
Result
Open
Normal operating condition.
Open = logical 1 state
Push button closed
Active low reset signal.
Closed = logical 0 state
The following sequence must be followed during a warm reset:
1. Ensure that the power supplies and input clock sources are stable.
2. Ensure that the RESET pin is asserted (low) for a minimum of 30 DEV clock cycles. The following
things occur within the low period of the RESET pin:
• All pins (except for the test and emulation pins) enter a Hi-Z mode and the associated pulls are
enabled.
• The PRCM asserts reset to all modules within the device, except for the test and emulation logic,
EMAC switch, PLL, and clock configuration.
3. Deassert (drive high) the RESET pin. The following things occur when the RESET pin is deasserted:
• All pins, except test and emulation pins, enter a Hi-Z mode and the associated pulls are enabled.
• Reset to the ARM Cortex-A8 processor and modules without a local processor is deasserted
except for the test and emulation logic, EMAC switch, PLL, and clock configuration.
• If BTMODE[11] was latched as 0, then RSTOUT_WD_OUT is asserted for TBD DEV clock cycles.
• The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
• The ARM Cortex-A8 processor begins executing from the boot ROM.
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Figure 3-26 shows the reset switches.
Figure 3-26. Reset Switches
3.2.17 Power-On Reset Switch SW7
Switch SW7 can be used to reset the entire chip (including the test and emulation logic and the EMAC
switch). PORn is also referred to as a cold reset because it must be asserted when the device goes
through a power-up cycle. Table 3-18 provides the two settings and results of the cold-reset push button.
Table 3-18. Cold-Reset Push-Button
Setting
Result
Open
Normal operating condition.
Open = logical 1 state
Push button closed
Active low power-on reset.
Closed = logical 0 state
The following sequence must be followed during a power-on reset (POR):
1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted
(low).
2. Wait for input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if used by
the system) while keeping the POR pin asserted.
When the power supplies and the input clock sources are stable, go to Step 3.
3. Ensure that the POR pin remains asserted for a minimum of two DEV clock cycles. The following
things occur within the low period of the POR pin:
• All pins (except the emulation pins) enter a Hi-Z mode and the associated pulls are enabled.
• The PRCM asserts reset to all modules within the device.
• The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.
4. Deassert (drive high) the POR pin. The followings things occur when the POR pin is deasserted:
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•
•
•
•
•
The BTMODE[15:0] pins are latched.
Reset to the ARM Cortex-A8 processor and modules without a local processor is deasserted.
If BTMODE[11] was latched as 0, then RSTOUT_WD_OUT is briefly asserted.
The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
The ARM Cortex-A8 processor begins executing from the boot ROM.
3.2.18 GPIO Switches and LEDs
The DM388 EVM includes four LEDs and a GPIO switch (SW9) controlled by an I/O expander
(PCF8575PWR [U39]) through an I2C0 interface. Figure 3-27 shows the GPIO switch and LEDs.
Figure 3-27. GPIO Switch and LEDs
3.2.19 Fuses
The DM388 EVM has a fuse (F1) near switch SW1. One end of F1 is connected to a Schottky barrier
rectifier and transient voltage suppressors. The other end of F1 is connected to switch SW1.The current
rating of F1 is 4 A and the voltage rating is 125 VDC.
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Test Points
3.3
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Test Points
The DM388 EVM has many test points. All test points are available on the top side of the board. Figure 328 shows the position of each major test point.
Figure 3-28. Major Test Points
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Table 3-19 lists each test point signal.
Table 3-19. Test Point Signals
Signal Number
Supply
Reference
1
IP_EVM_12V
TP1
2
EVM_5V0
TP6
3
LS_EVM_3V3
TP61
4
PCI_3V3
TP9
5
VDDQ_1V5
TP72
6
CORE_VDD
TP19
7
CVDD_ARM
TP47
8
CVDD_DSP
TP67
9
VDDA_1V8
TP49
10
PLL_1V8
TP25
11
VDDA_USB_1V8
TP39
12
VDAC_1V8
TP26
13
DVDD
TP55
14
DVDD_GPMC
TP52
15
DVDD_SD
TP89
16
EVM_1V8
TP10
17
VAIC_1V8
TP51
18
RSTOUTn
TP74
19
PORz
TP62
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Expansion Connector
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Expansion Connector
Table 3-20 provides the pinout details of the 64-pin, board-to-board video expansion connector (J27) of
the EVM.
Table 3-20. 64-Pin Video Expansion Connector (J27)
66
Pin Number
Pin Description
Pin Number
1
VIN0_DE0
2
NC
3
GND
4
GND
5
VIN0_HSYNC
6
NC
7
NC
8
NC
9
GND
10
GND
11
VIN0_VSYNC
12
NC
13
NC
14
VIN0_DE1
15
GND
16
GND
17
NC
18
NC
19
NC
20
VIN0_FLD0
21
GND
22
GND
23
NC
24
CS12_DX4
25
NC
26
CS12_DY4
27
GND
28
GND
29
NC
30
CS12_DX3
31
NC
32
CS12_DY3
33
GND
34
GND
35
SPI1_SCLK
36
CS12_DX2
37
SPI1_MISO
38
CS12_DY2
39
GND
40
GND
41
SPI1_MOSI
42
CS12_DY1
43
SPI1_nCS0
44
CS12_DX1
45
GND
46
GND
47
NC
48
CS12_DY0
49
NC
50
CS12_DX0
51
GND
52
GND
53
NC
54
NC
55
NC
56
NC
57
GND
58
GND
59
NC
60
NC
61
GND
62
GND
63
GND
64
GND
Physical Description
Pin Description
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Table 3-21 provides the pinout details of the 128-pin, board-to-board video expansion connector (J28) of
the EVM.
Table 3-21. 128-Pin Video Expansion Connector (J28)
Pin Number
Pin Description
Pin Number
Pin Description
1
VIN0_DE0
2
VIN0_D0
3
GND
4
GND
5
VIN0_FLD0
6
VIN0_D2
7
VIN0_CLK1
8
VIN0_D9
9
GND
10
GND
11
VIN0_D1
12
VOUT0_G_Y_YC2
13
VIN0_D4
14
VOUT0_G_Y_YC6
15
GND
16
GND
17
VIN0_D11
18
VOUT0_R_CR4
19
VIN0_D5
20
VIN0_D6
21
GND
22
GND
23
VIN0_D12
24
VIN0_D8
25
VIN0_D10
26
VIN0_D3
27
GND
28
GND
29
VIN0_D14
30
VIN0_D7
31
VIN0_D13
32
VOUT0_G_Y_YC4
33
GND
34
GND
35
VIN0_D15
36
VOUT0_B_CB_C8
37
VOUT0_CLK
38
VOUT0_G_Y_YC5
39
GND
40
GND
41
VOUT0_G_Y_YC8
42
VOUT0_B_CB_C6
43
VOUT0_G_Y_YC7
44
VOUT0_B_CB_C5
45
GND
46
GND
47
EXP_EVM_3V3
48
IP_EVM_12V
49
EXP_EVM_3V3
50
IP_EVM_12V
51
GND
52
GND
53
EXP_EVM_5V0
54
IP_EVM_12V
55
EXP_EVM_5V0
56
IP_EVM_12V
57
GND
58
GND
59
VOUT0_B_CB_C9
60
VOUT0_B_CB_C3
61
VOUT0_R_CR2
62
VOUT0_B_CB_C7
63
GND
64
GND
65
VOUT0_R_CR6
66
VOUT0_G_Y_YC3
67
VOUT0_R_CR5
68
VOUT0_G_Y_YC9
69
GND
70
GND
71
VOUT0_R_CR9
72
VIN0_CLK0
73
VOUT0_HSYNC
74
VOUT0_B_CB_C4
75
GND
76
GND
77
VIN0_D16
78
VOUT0_B_CB_C2
79
VIN0_D17
80
VOUT0_R_CR3
81
GND
82
GND
83
VIN0_D18
84
VIN0_D19
85
VOUT0_VSYNC
86
VIN0_D20
87
GND
88
GND
89
NC
90
NC
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Table 3-21. 128-Pin Video Expansion Connector (J28) (continued)
Pin Number
Pin Description
Pin Number
Pin Description
91
NC
92
VIN0_D21
93
GND
94
GND
95
VOUT0_AVID
96
VIN0_D22
97
NC
98
VOUT0_R_CR7
99
GND
100
GND
101
VIN0_FLD1
102
VOUT0_R_CR8
103
USB1_CE
104
VIN0_D23
105
GND
106
GND
107
NC
108
NC
109
NC
110
USB0_CE
111
GND
112
GND
113
PM_I2C_SCL
114
NC
115
PM_I2C_SDA
116
NC
117
GND
118
GND
119
NC
120
NC
121
GND
122
GND
123
GND
124
GND
125
GND
126
GND
127
GND
128
GND
Table 3-22 provides the pinout details of the 128-pin board-to-board GPMC expansion connector (J19).
Table 3-22. 128-Pin GPMC Expansion Connector (J19)
68
Pin Number
Pin Description
Pin Number
Pin Description
1
McA5_AXR0_EXO
2
PM_I2C_SCL
3
GND
4
GND
5
GPMC_nCS3
6
PM_I2C_SDA
7
EXP_GPMC_nCS0
8
OSC_WAKE
9
GND
10
GND
11
GPMC_nCS2
12
GPMC_A22
13
GPMC_nCS1
14
GPMC_A23
15
GND
16
GND
17
GPMC_WEN
18
GPMC_nCS4
19
McA5_AXR1
20
VOUT1_R_CR0
21
GND
22
GND
23
GPMC_OEN_REN
24
VOUT1_R_CR1
25
GPMC_nBE1
26
MMC2_DAT1
27
GND
28
GND
29
VOUT1_G_Y_YC1
30
MMC2_DAT2
31
MMC2_DAT0
32
MMC2_DAT3
33
GND
34
GND
35
VOUT1_B_CB_C1
36
VOUT1_B_CB_C2
37
VOUT1_B_CB_C0
38
MMC2_CLK
39
GND
40
GND
41
VOUT1_FLD_EXP
42
GPMC_WAIT0
43
GPMC_D0
44
McA5_AFSX_EXP
45
GND
46
GND
Physical Description
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Table 3-22. 128-Pin GPMC Expansion Connector (J19) (continued)
Pin Number
Pin Description
Pin Number
Pin Description
47
EXP_EVM_3V3
48
IP_EVM_12V
49
EXP_EVM_3V3
50
IP_EVM_12V
51
GND
52
GND
53
EXP_EVM_5V0
54
IP_EVM_12V
55
EXP_EVM_5V0
56
IP_EVM_12V
57
GND
58
GND
59
GPMC_D2
60
VOUT1_G_Y_YC0
61
GPMC_D5
62
GPMC_nBE0_YC0
63
GND
64
GND
65
GPMC_D7
66
GPMC_D4
67
GPMC_D9
68
GPMC_D3
69
GND
70
GND
71
GPMC_D12
72
GPMC_D1
73
GPMC_D11
74
McA5_ACLKX
75
GND
76
GND
77
GPMC_D10
78
GPMC_nADV_ALE
79
GPMC_CLK
80
GPMC_D6
81
GND
82
GND
83
GPMC_D15
84
GPMC_D8
85
NC
86
GPMC_D13
87
GND
88
GND
89
NC
90
NC
91
AUXOSC_MXI
92
NC
93
GND
94
GND
95
NC
96
MMC0_DAT0
97
UART2_CTSn_EXP
98
MMC0_DAT1
99
GND
100
GND
101
SPI0_nCS0
102
GPMC_D14
103
SPI0_SCLK
104
MMC0_DAT2
105
GND
106
GND
107
GPMC_A21
108
SPI0_MOSI
109
SPI0_nCS1
110
SPI0_MISO
111
GND
112
GND
113
MMC0_CLK
114
DCAN0/UART2_RX
115
MMC0_CMD
116
MMC0_DAT3
117
GND
118
GND
119
EXP_UART0_RXD
120
DCAN0/UART2_TX
121
GND
122
GND
123
GND
124
GND
125
GND
126
GND
127
GND
128
GND
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Table 3-23 shows the pinout details of the 128-pin board-to-board MCASP expansion connector (J30).
Table 3-23. 128-Pin MCASP Expansion Connector
70
Pin Number
Pin Description
Pin Number
Pin Description
1
PM_I2C_SCL
2
I2C2_SDA/UART2_TXD_EXP
3
GND
4
GND
5
PM_I2C_SDA
6
I2C2_SCL/UART2_RXD_EXP
7
EXP_MCA2_AXR0
8
I2C0_SDA
9
GND
10
GND
11
MCA1_AXR2
12
I2C0_SCL
13
EXP_MCA2_AXR1
14
I2C1_SDA
15
GND
16
GND
17
MCA1_AXR3
18
I2C1_SCL
19
EXP_MCA2_ACLKX
20
MCA0_AXR3
21
GND
22
GND
23
MCA2_AXR2
24
MCA0_AXR2
25
EXP_MCA2_AFSX
26
NC
27
GND
28
GND
29
AUD_CLKIN2
30
AUD_CLKIN0
31
MCA2_AXR3
32
MCA0_AFSR
33
GND
34
GND
35
MCA1_AXR1
36
MCA0_ACLKX
37
MCA1_AXR0
38
MCA0_AFSX
39
GND
40
GND
41
VOUT1_G_Y_YC8
42
MCA1_AFSX
43
VOUT1_B_CB_C9
44
MCA0_AXR1
45
GND
46
GND
47
EXP_EVM_3V3
48
IP_EVM_12V
49
EXP_EVM_3V3
50
IP_EVM_12V
51
GND
52
GND
53
EXP_EVM_5V0
54
IP_EVM_12V
55
EXP_EVM_5V0
56
IP_EVM_12V
57
GND
58
GND
59
AUD_CLKIN1
60
VOUT1_G_Y_YC4
61
MDIO_MDIO
62
MCA0_AXR5
63
GND
64
GND
65
MDIO_MDCLK
66
MCA0_AXR4
67
MCA1_ACLKX
68
MCA0_AXR0
69
GND
70
GND
71
COUT1_B_CB_C3
72
MCA1_ACLKR
73
VOUT1_B_CB_C4
74
NC
75
GND
76
GND
77
COUT1_B_CB_C6
78
MCA1_AFSR
79
VOUT1_B_CB_C5
80
VOUT1_G_Y_YC7
81
GND
82
GND
83
VOUT1_B_CB_C8
84
VOUT1_R_CR7
85
VOUT1_B_CB_C7
86
VOUT1_VSYNC
87
GND
88
GND
89
VOUT1_G_Y_YC3
90
VOUT1_R_CR8
91
VOUT1_G_Y_YC5
92
NC
Physical Description
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Table 3-23. 128-Pin MCASP Expansion Connector (continued)
Pin Number
Pin Description
Pin Number
Pin Description
93
GND
94
GND
95
VOUT1_G_Y_YC6
96
MCA0_AXR9
97
VOUT_G_Y_YC9
98
VOUT1_HSYNC
99
GND
100
GND
101
VOUT1_R_CR4
102
NC
103
VOUT1_R_CR6
104
MCA0_ACLKR
105
GND
106
GND
107
VOUT1_R_CR5
108
NC
109
VOUT1_CLK
110
NC
111
GND
112
GND
113
VOUT1_R_CR9
114
VOUT1_AVID
115
NC
116
NC
117
GND
118
GND
119
NC
120
NC
121
GND
122
GND
123
GND
124
GND
125
GND
126
GND
127
GND
128
GND
Table 3-24 shows the pinout details of the 64-pin board-to-board GPMC expansion connector (J31).
Table 3-24. 64-Pin GPMC Expansion Connector
Pin Number
Pin Description
Pin Number
Pin Description
1
VOUT1_R_CR3
2
MCA3_ACLKX
3
GND
4
GND
5
EXP_UART0_TXD
6
GPMC_A20
7
MCA3_AXR0
8
GPMC_A18
9
GND
10
GND
11
VOUT1_R_CR2
12
GPMC_A19
13
MCA3_AXR1
14
GPMC_A17
15
GND
16
GND
17
MMC2_DAT7
18
MMC2_DAT5
19
MMC2_DAT6
20
VOUT1_G_Y_YC2
21
GND
22
GND
23
VOUT0_FLD_EXP
24
MCA3_AXR2
25
IO_EXP2_GP3
26
MCA3_AXR3
27
GND
28
GND
29
CLK32OUT
30
MCA3_AFSX
31
MCA4_ACLKX
32
EXP_UART0_CTSn
33
GND
34
GND
35
NC
36
EXP_UART0_RTSn
37
NC
38
GPMC_A16
39
GND
40
GND
41
NC
42
UART2_RTSn_EXP
43
NC
44
RSTOUTn
45
GND
46
GND
47
NC
48
IO_EXP2_GP1
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Table 3-24. 64-Pin GPMC Expansion Connector (continued)
72
Pin Number
Pin Description
Pin Number
Pin Description
49
GPIO_VS_1
50
IO_EXP2_GP2
51
GND
52
GND
53
MCA4_AXR0
54
MCA4_AXR1
55
EXP_WARM_RESET
56
MCA4_AFSX
57
GND
58
GND
59
APP_PORz
60
MMC2_DAT4
61
GND
62
GND
63
GND
64
GND
Physical Description
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Appendix A
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Schematics
Figure A-1 through Figure A-38 show the schematics of the DM385 device.
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Schematics
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Appendix A
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Figure A-1. Version History
5
4
3
2
1
VERSION HISTORY
VER #
0.01
DATE
02/01/2012
D
0.02
14/01/2012
AUTHOR
DESCRIPTION OF CHANGES
SCHEMATICS "MS_TI_DM385EVM_REVA_SCH(VERSION 1.06)" IS TAKEN AS REFERNCE AND
CHANGES ARE MADE FOR REVB AS LISTED BELOW
1)MIC94060YC6 (U27 & U70) ICs ARE REPLACED WITH MIC94062YC6.
2)THE ESD PROTECTION ICs TPD2E007DCKR (U95,U96,U97) IS ADDED NEAR THE LINE-IN,LINE-OUT
& HP-OUT JACK.
3)THE ESD PROTECTION ICs ESDALC6V1P6 (D12 & D13) IS ADDED ALONG
THE MMC CONNECTOR LINES.
4)SWITCH IC SN74CB3Q3257PWR (U98) IS ADDED FOR GPMC ADDRESS PIN MUXING. TP71 REMOVED
5)A DECOUPLING CAPACITOR(C688) IS INCLUDED ON PIN B7(HDDDA_VREF) IN TMS320DM385.
6)NAME OF PIN B7 IN TMS320DM385 IS CORRECTED AS HDDAC_VREF FROM HDDDAC_VREF.
7)R273 IS MADE IN TO DNI.
8)R250 IS CHANGED TO 2.67K.
9)R44,R45,R46 ARE CHANGED TO 165OHM.
10)R481 IS MADE IN TO DNI AND R241 IS MADE IN TO 0 OHM.
11)A PUSH BUTTON SWITCH (SW12) IS INCLUDED FOR OSC_WAKE.
0.03
20/01/2012
1)
2)
3)
4)
5)
6)
7)
8)
9)
1.00
24/01/2012
1.01
07/03/2012
1.02
09/05/2016
REVIEWED BY
MISTRAL DESIGN TEAM
MANJUNATHA BM
APPROVED BY
KRISHNA PRASAD A
D
MISTRAL DESIGN TEAM
R43 VALUE CHANGED TO 46.7K
R579 VALUE CHANGED TO 26.7K
U98 OE SIGNAL AND UNUSED INPUTS PULLED DOWN TO GND
ESDALC6V1P6 DEVICE(D12 & D13) DELETED AND ADDED TPD4E001(U99 & U100) ON MMC LINES
R26 AND R43 MADE AS DNI AND R58 IS MOUNTED
C689, C690 AND C691 ARE ADDED FOR U70
C692 AND C693 ADDED FOR U27
C694 ADDED FOR U98
SWAPPED THE MMC1 SIGNALS ON U99 AND U100 FOR ROUTING CONVENIENCE
MANJUNATHA BM
KRISHNA PRASAD A
MISTRAL DESIGN TEAM
MANJUNATHA BM
KRISHNA PRASAD A
1) Baselined as 1.00
MISTRAL DESIGN TEAM
MANJUNATHA BM
KRISHNA PRASAD A
THE RoHS NON COMPLIANT COMPONENTS ARE REPLACED WITH THE ALTERNATIVES THAT ARE RoHS COMPLIANT:
1) T494A106M016AS (C321,C323) ARE REPLACED BY T494A106M016AT.
2) 9C06031A2212FKHFT (R64,R142,R178) ARE REPLACED BY RC0603FR-0722K1L.
3) 9C04021A10R0JLHF3 (R85,R89,R90,R94) ARE REPLACED BY ERJ-2GEJ100X.
4) TDA04H0SK1 (SW9,SW10,SW11) ARE REPLACED BY GDH04S04.
MISTRAL DESIGN TEAM
MANJUNATHA BM
KRISHNA PRASAD A
MISTRAL DESIGN TEAM
KRISHNA PRASAD A
KRISHNA PRASAD A
C
C
SATA INTERFACE DNI'd
( J23,J24,J25,J26,U86,C310,C350,C343,C323,C351,C344,C318,C349,C334,C321,
C348,C335,C683,R479,R486,R485,R482,LD10,LD11 )
B
B
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
VERSION HISTORY
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Approved by:
Date: Monday, May 31, 2010
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
74
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Monday, August 08, 2016
2
of
39
1
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Appendix A
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Figure A-2. DM385 Block Diagram
5
4
3
2
1
BLOCK DIAGRAM- DM385 EVM BASE BOARD
D
D
C
C
B
B
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
BLOCK DIAGRAM
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
Document Number
Size
Approved by:
MISTRAL DESIGN TEAM
KRISHNA PRASAD A
MS_TI_DM385EVM_REVB_SCH
B
Date
Monday, May 31, 2010
Monday, August 08, 2016
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Design file path:
Date:
Sheet
Tuesday, January 24, 2012
Rev
Drawn by:
Date:
5
4
3
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B
3
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39
1
Schematics
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Appendix A
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Figure A-3. Memory Map
5
4
3
2
MEMORY MAP TO BE UPDATED
1
GPIO ASSIGNMENT (NEWLY ADDED)
GPIO ASSIGNMENT(SAME AS CENTAURUS)
ETHERNET-GPMC
D
NAND-GPMC
GPIO NAME
SOURCE
DDR-0
ENET_INT
GP1[10]
ETHERNET
SPI FLASH
PCF8575_INT_IO1
GP1[4]
I NTERRUPT
TPS_INT1
TPS659113-- INT 1
INTERRUPT FROM PMIC
I2C DEVICES
PURPOSE
0011000
I2C0- EEPROM
1010000
I2C0- PCF8575-1
0100000
EN_BCK3_TPS65232
TPS659113-- GPIO 2
ENABLING PCI_3V3
I2C0- PCF8575-2
0100011
EN_TPS51116
TPS659113-- GPIO 0
ENABLING DDR SUPPLY
MSP430_INT
PCF8575 DEVICE-1
INTERRUPT FOR MSP430
EXP_ETH_RESET
PCF8575 DEVICE-1
ETHERNET RESET
TPS_SLEEP
PCF8575 DEVICE-1
SLEEP FOR TPS659113
PCI_SW_RESETn
PCF8575 DEVICE-1
PCI RESET
IR_REMOTE_OFF
PCF8575 DEVICE-1
IR SENSOR CONTROLLING
TPS659113-- GPIO 7
ENABLING LOAD SWITCH
EN_TPS62350 (REMOVED) TPS659113-- GPIO 6
ENABLING CVDD_HDVICP
I2C1- HDMI
I2C2- PCF8575-3
0100000
PMI2C
I2C POWER MONITORS---MSP430
PM_I2C ADDRESS
PLL_1V8
1000000
HDMI_CSI_1V8
1000001
CVDD_ARM
1000010
VDDQ_DM_1V5
1000011
VDDA_1V8
1000101
DVDD_GPMC
1000110
CVDD_DSP
1001001
CORE_VDD
1001000
DVDD
1000100
DVDD_C
1000111
VMMC
1001010
C
SOURCE
GP0[12]
PURPOSE
HDMI_CT_HPD
PCF8575 DEVICE -3
ENABLING LOAD SWITCH
HDMI_LS_OE
PCF8575 DEVICE -3
ENABLING LEVEL SHIFTER
DISABLE_SD
PCF8575 DEVICE -3
DISABLE_SF
PCF8575 DEVICE -3
BYPASS_SD
PCF8575 DEVICE -3
BYPASS_SF
PCF8575 DEVICE -3
FILTER1
PCF8575 DEVICE -3
FILTER1
PCF8575 DEVICE -3
IO_EXP2_GP1
PCF8575 DEVICE -2
IO_EXP2_GP2
PCF8575 DEVICE -2
GPIO USED IN CATLOG
MCA0_DEC_A
MCA0_DEC_B
PCF8575 DEVICE -2
MCASP0 DECODER SELECT
LINES
MCA1_MUX_SEL
PCF8575 DEVICE -2
MCASP1 MUX SELECT
LINES
MCA0/1/3_RSEL_A
MCA0/1/3_RSEL_B
PCF8575 DEVICE -2
MCASP0/1/3_R DECODER
SELECT LINES
WoL INTERRUPT
D
I2C0- AUDIO CODEC
EN_BCK2_LS
GPIO NAME
ENET_WoL_INT
SD AND SF CHANNEL CONTROL
OF VIDEO AMPLIFIER
TO BYPASS LPF OF
SD AND SF IN VA
SELECTABLE FILTER FOR
SF CHANNELS
GPIO USED IN CATLOG
UART0_OFF
PCF8575 DEVICE-1
UART-0 CONTROLLING
GPMC_ADD_SELn
PCF8575 DEVICE-1
TO SELECT EITHER GPMC OR
HDMI LINES.
SW_VOUT_EN
TDA04H0SK1 DEVICE
VIDEO SW ENABLE
PCF8575_INT_IO2
GPMC_nWP
TDA04H0SK1 DEVICE
GPMC WRITE PROTECT
MCA0_AXR9
PCF8575 DEVICE -2
GPIO USED IN VC BOARD
RESET_GPIO
TDA04H0SK1 DEVICE
ENABLING PCI POR BUFFER
IO_EXP2_GP3
PCF8575 DEVICE -2
GPIO USED IN VC BOARD
MCA5_MUX_OE
PCF8575 DEVICE -2
TO SELECT B/T GPIO N
MCA5_AHCLKX
VOUT_FLD_SEL1
PCF8575 DEVICE -3
TO PROVIDE THE PIN MUXING
OPTION FOR VOUT0/1_FLD PIN
VOUT_FLD_SEL2
PCF8575 DEVICE -3
GPIO_VC_1
PCF8575 DEVICE -2
GPIO_VC_2
PCF8575 DEVICE -2
GP0[13]
MCA1_MUX2_nOE
PCF8575 DEVICE -2
C
INTERRUPT
GPIO USED ON THE APPLICATION
BOARD.
MCASP1 MUXING SELECTION.
B
B
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
MEMORY MAP
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date:
Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
76
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Thursday, March 08, 2012
4
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-4. McASP Muxing
5
4
3
2
1
M c A SP -0 M U X IN G
D
D
M c AS P -0
M CA 0_ nO E_C O NN0
B u s FET
Sw itc h
(1 )
M c ASP -0
Fro m D M3 85
McASP-1 MUXING
nO E
A CLK X, A FS X,
A CLK R, A FS R,
A XR -0, 1, 2, 3
M cA SP-0
To E xp a ns io n C o n ne c tor
McASP-1
M CA0 _n OE_ CO NN2
A CLKX , AF S X,
A XR- 0, 1, 2, 3
nO E
(A C L K X , AC L K R,
A FSX, A FSR
A X R -0 , 1 , 2 , 3 )
M c ASP -2
T o E xpa n sio n Co n n ecto r
M c AS P -0
B u s FET
Sw itc h
(2 )
MC A0_ nO E_C ON N4
nO E
AC LKX , A F SX ,
AX R- 0,1, 2, 3
nOE
M c ASP -4
T o E xpa n sio n Co n n ecto r
ACLKX, AFSX,
AXR-0, AXR-1
McASP-1
ToExpansionConnector
McASP-1
FromDM385
C
McASP-1
(ACLKX, AFSX,
AXR-0, AXR-1)
M c ASP - 0
A X R -4, AXR -5
n OE
McASP-1
ToBaseBoardCODEC
(1)
SEL
C
MC A 0/1 /3 _n OE _ 0
ACLKX, AFSX,
AXR-0, AXR-1
4x1:2
Mux
B u s FE T
Sw itc h
(3)
A X R-2 , A X R -3
4x1:2
Mux
M c ASP -0
T o Ex p an sio n C on n ec to r
ACLKX, AFSX,
AXR-0, AXR-1
McASP-3
ToExpansionConnector
ACLKX, AFSX,
AXR-0, AXR-1
McASP-5
ToExpansionConnector
(2)
M cA SP-1
To Ex p an s ion C o n ne c tor
MCA1_MUX_SEL
SEL
MCA1_MUX2_nOE
nOE
M CA 0 /1/3 _ n OE_ 1
n OE
T o b e re fe rred
w it h M c A SP 1
S ch e m e
M cA SP -0
Fr om DM 38 5
(A XR -4, A X R-5)
MC A 0/1 /3 _ nO E_ 3
B
M c ASP - 0
B u s FE T
Sw itc h
(4)
n OE
A X R -2, AXR -3
M cA SP-3
To Ex p an s ion C o n ne c tor
B
To get McASP0 _AXR [4,5] on EXP Connector
Enable : MCA0/1/3_nOE_0
To get McASP1 _AXR [2,3] on EXP Connector
Enable : MCA0/1/3_nOE_1
To get McASP3 _AXR [2,3] on EXP Connector
Enable : MCA0/1/3_nOE_3
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
MCASP MUXING BLK DIAGRAM
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Design file path:
Date:
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Document Number
MS_TI_DM385EVM_REVB_SCH
Tuesday, January 24, 2012
Rev
B
Sheet
5
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
77
Appendix A
www.ti.com
Figure A-5. DM385 McASP
5
4
3
2
1
U55F
McASP0,1
D
7
7
7
7
MCA0_ACLKX_1
MCA0_ACLKR_1
MCA0_AFSR_1
MCA0_AFSX_1
7
7
7
7
7
7
MCA0_AXR0_1
MCA0_AXR1_1
MCA0_AXR2_1
MCA0_AXR3_1
MCA0_AXR4_1
MCA0_AXR5_1
MCA0_ACLKX_1
MCA0_ACLKR
MCA0_AFSR
MCA0_AFSX_1
23
R543 22E
R534 22E
CPU.MCA0_ACLKX
CPU.MCA0_ACLKR
AD28
AD30
AF30
AE29
MCA0_AXR0_1
MCA0_AXR1_1
MCA0_AXR2_1
MCA0_AXR3_1
MCA0_AXR4_1
MCA0_AXR5_1
AF29
AE31
AE30
AC31
AD26
AD27
R379
USBB1_DRV_VBUS
AF31
AF27
AG30
0E
DM_AUD_CLKIN0
DM_AUD_CLKIN2
MCA[0]_ACLKX
MCA[0]_ACLKR
MCA[0]_AFSR
MCA[0]_AFSX
AC23 CPU.MCA1_ACLKX R538
AD29 CPU.MCA1_ACLKR R339
AC24
AB22
MCA[1]_ACLKX
MCA[1]_ACLKR/MCA[1]_AXR[4]
MCA[1]_AFSR/MCA[1]_AXR[5]
MCA[1]_AFSX
MCA[0]_AXR[0]
MCA[0]_AXR[1]/I2C[3]_SCL
MCA[0]_AXR[2]/I2C[3]_SDA
MCA[0]_AXR[3]
MCA[0]_AXR[4]/MCA[1]_AXR[8]
MCA[0]_AXR[5]/MCA[1]_AXR[9]
MCA[1]_AXR[0]/SD0_DAT[4]
MCA[1]_AXR[1]/SD0_DAT[5]
SD0_DAT[6]/GP0[12]
SD0_DAT[7]/GP0[13]
Y22
Y21
MCA1_AXR0_1
MCA1_AXR1_1
AB31
AC30
R304 22E
R320 22E
22E
22E
MCA1_ACLKX_1
MCA1_ACLKR_1
MCA1_AFSR
MCA1_AFSX_1
MCA1_ACLKX_1
7
MCA1_ACLKR
8
MCA1_AFSR
8
MCA1_AFSX_1
7
MCA1_AXR0_1
MCA1_AXR1_1
ENET_WoL_INT
PCF8575_INT_IO2
7
7
D
12
21
AUD_CLKIN0/MCA[0]_AXR[7]/MCA[0]_AHCLKX/ATL_CLKOUT1/ATL_CLKOUT0/USB1_DRVVBUS
AUD_CLKIN1/MCA[0]_AXR[8]/MCA[1]_AHCLKX/ATL_CLKOUT2/EDMA_EVT3/TIM2_IO/GP0[8]
AUD_CLKIN2/MCA[0]_AXR[9]/sata_act1_led/ATL_CLKOUT3/EDMA_EVT2/TIM3_IO/GP0[9]
TMS320DM385
6
MCA1_AHCLKX_1
R562
0E
22
SATA_ACT1_LED
R374
0E
NOTE :
1) MCA[2]_AHCLKX (AUD_CLKIN2) IS REMOVED IN DM385 AND IT IS PROVIDED FROM MUXING OPTION OF MCA[0].
SO MCA[0]_AHCLKX IS MAPPED TO MCA[2]AHCLKX.
EVM_3V3
C571
0.1uF
C430
PLACE THE RESISTOR R375 WHEN VC BOARD IS USED.
BY DEFAULT OPTION IS USB1_DRV_VBUS
2
MCA1_MUX_SEL
R560
0E
R561
0E
2
4
1
5
SN74LVC1G04DCKR
7
2B
2OE
4
C138
7
7
21
21
5
1
MCA5_AFSX
MCA5_AXR0
GPIO_VC_1
GPIO_VC_2
GPIO_VC_1
GPIO_VC_2
R212
R213
R191
R192
2
0E
0E
0E
0E
5
9
12
2
MCA5_MUX_OE
SN74CB3Q3306ADCUR
4
1
4
10
13
1A
1B
2A
2B
3A
3B
4A
4B
1OE
2OE
3OE
4OE
3
MCA5_AFSX_EXP
14
6
MCA5_AXR0_EXP
14
8
11
3
SN74LVC1G04DCKR
B
0.1uF
14
U32
C146
0.1uF
U33
21
DM_AUD_CLKIN1
EVM_3V3
B_AIC_MCLK
NOTE:
MCA5_AFSX & MCA5_AXR0 ARE USED AS GPIOs ON VC BOARD.
MCA5 IS MUXXED WITH MCA1 IN DM385 EVM.NO GPIOs ARE
AVAILABLE ON MCA1 LINES OF DM385.
BY DEFAULT MCA5 LINES ARE SELECTED.
HENCE WE ARE PROVIDING AN OPTION TO SELECT B/T THE GPIOs
FROM IO EXPANDER AND THE MCASP LINES.
BY DEFAULT MCA5 LINES ARE SELECTED.
6
EVM_3V3
9
VCC
CDCV304PW
AIC_MCLK
FOR AIC3106
B_AIC_MCLK
GND
6
CLKIN
DM_AUD_CLKIN0
DM_AUD_CLKIN1
DM_AUD_CLKIN2
AIC_MCLK
R384 DNI 0E
R383 DNI 0E
R382 DNI 0E
R392
22E
3
SN74CBTLV3125PWR
7
1
3
5
7
8
8
2A
R375 DNI 0E
R376
0E
R377
0E
DNI
22E R398
22E
1Y0
1Y1
1Y2
1Y3
4
R399
OE
AUD_CLKIN2
AUD_CLKIN1
AUD_CLKIN0
2
24.5760MHz
3
2
VDD
0.1uF C258
GND
OUTPUT
10K
8
8
8
DNI
22E R391
OE
R397
U65
GND
1
B
4
U64
VDD
VDAC_3V3
1B
C579 0.1uF
VDAC_3V3
C
1OE
3
VDAC_3V3
1A
GND
21,7
MCA1_AHCLKX_1
VCC
U94
6
2) MCASP0_AXR[6:8] SIGANALS ARE NOT USED IN ANY OF THE APPLICATION BOARDS.
NO MCASP MUXING OPTION IS GIVEN TO THESE SIGNALS ON DM385 BASE BOARD.
VDAC_3V3
0.1uF
U93
5
1
C
NOTE:
B_AIC_MCLK IS SELECTED WHICH IS USED BY ON-BOARD CODEC AS DEFAULT OPTION WHICH IS
PRESENTLY MADE DNI.
OR ELSE DM_CLKIN1 IS SELECTED WHICH IS USED ON APPLICATION BOARDS WHEN MCA1_MUX2_NOE IS HIGH.
EVM_3V3
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
DM385_MCASP
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
Design file path:
Date:
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
78
4
3
Schematics
2
Tuesday, January 24, 2012
Rev
B
Sheet
6
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-6. McASP Muxing and Decoders
5
4
3
2
1
DNI
RA43 8
7
6
5
EVM_3V3
C139
0.1uF
1 0E
2
3
4
MCASP1 MUXING
EVM_3V3
EVM_3V3
C193
16
U36
MCA1_MUX1_nOE
4
4
4
VCC
2
MCA1_MUX2_nOE
1A
1B1
1B2
SN74LVC1G04DCKR
MCA1_ACLKX_1
MCA1_AFSX_1
MCA1_AXR0_1
MCA1_AXR1_1
10E
2
3
4
7
9
12
21,6,7
1
MCA1_MUX_SEL
MCA1_MUX1_nOE
15
2A
2B1
2B2
3A
3B1
3B2
4A
4B1
4B2
5
6
MCA1_AFSX
R199
0E
11
10
MCA1_AXR0
R198
0E
14
13
MCA1_AXR1
R204
0E
MCA1_ACLKX
B_AIC_BCLK
8
9
MCA1_AFSX
B_AIC_WCLK
8
MCA1_AXR0
B_AIC_DIN
8
9
MCA1_AXR1
B_AIC_DOUT
8
6,7
6,7
6,7
6,7
9
1 0E
2
3
4
7
9
12
21,6,7
1
MCA1_MUX_SEL
9
21,7
S
OE
SN74CB3Q3257PWR
RA28 8
7
6
5
MCA1_ACLKX_1
MCA1_AFSX_1
MCA1_AXR0_1
MCA1_AXR1_1
15
MCA1_MUX2_nOE
GND
RA44 8
7
6
5
MCA1_ACLKX
R210
0E
1A
16
1B1
1B2
2A
2B1
2B2
3A
3B1
3B2
4A
4B1
4B2
2
3
MCA5_ACLKX
MCA3_ACLKX
5
6
MCA5_AFSX
MCA3_AFSX
11
10
MCA5_AXR0
MCA3_AXR0
14
13
MCA5_AXR1
MCA3_AXR1
14
14
MCA5_AFSX
MCA3_AFSX
6
14
MCA5_AXR0
MCA3_AXR0
6
14
MCA5_AXR1
MCA3_AXR1
14
14
D
S
OE
SN74CB3Q3257PWR
MCASP0 MUXING
EVM_3V3
C449
MCASP0 DECODER
EVM_3V3
MCA5_ACLKX
MCA3_ACLKX
8
6,7
6,7
6,7
6,7
3
D
2
3
VCC
U49
21,7
0.1uF
0.1uF
GND
C150
8
5
1
U31
0.1uF
EVM_3V3
EVM_3V3
A
Y1
Y2
B
MCA0_nOE_CONN4
5
MCA0_nOE_CONN2
3
MCA0_nOE_CONN0
6,7
6,7
6,7
6,7
6,7
6,7
6
6
MCA0_ACLKX_1
MCA0_AFSX_1
MCA0_AXR0_1
MCA0_AXR1_1
MCA0_AXR2_1
MCA0_AXR3_1
MCA0_ACLKR_1
MCA0_AFSR_1
4
Y3
6
4 0E
RA4
3
2
1
4
3
2
1
RA1
0E
MCA0_nOE_CONN0
2
3
4
5
6
7
8
9
19
SN74LVC1G139
20
A1
A2
A3
A4
A5
A6
A7
A8
OE
SN74CBTLV3245ADBQR
MCA0_ACLKX
MCA0_AFSX
MCA0_AXR0
MCA0_AXR1
MCA0_AXR2
MCA0_AXR3
MCA0_ACLKR
MCA0_AFSR
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
MCA0_ACLKX
MCA0_AFSX
MCA0_AXR0
MCA0_AXR1
MCA0_AXR2
MCA0_AXR3
MCA0_ACLKR
MCA0_AFSR
8
RA22 5
6
7
8
R540
R255
4 0E
3
2
1
0E
0E
2
3
4
5
6
7
9
10
11
12
8
6,7
6,7
6,7
6,7
MCA0_ACLKX_1
MCA0_AFSX_1
MCA0_AXR0_1
MCA0_AXR1_1
RA16 5
6
7
8
40E
3
2
1
13
14
16
18
19
20
21
22
23
24
8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
48
47
1OE
2OE
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
8
17
41
32
MCA0_nOE_CONN2
MCA0_nOE_CONN4
VCC
MCA0_ACLKX_1
MCA0_AFSX_1
MCA0_AXR0_1
MCA0_AXR1_1
MCA0_AXR2_1
MCA0_AXR3_1
8
8
8
8
8
1
NC
6,7
6,7
6,7
6,7
6,7
6,7
46
45
44
43
42
40
39
38
37
36
EXP_MCA2_ACLKX
EXP_MCA2_AFSX
EXP_MCA2_AXR0
EXP_MCA2_AXR1
MCA2_AXR2
MCA2_AXR3
35
34
33
31
30
29
28
27
26
25
MCA4_ACLKX
MCA4_AFSX
MCA4_AXR0
MCA4_AXR1
EXP_MCA2_ACLKX
EXP_MCA2_AFSX
EXP_MCA2_AXR0
EXP_MCA2_AXR1
MCA2_AXR2
8
MCA2_AXR3
8
8
8
8
8
C
MCA4_ACLKX
MCA4_AFSX
MCA4_AXR0
MCA4_AXR1
14
14
14
14
1
NC
GND1
GND2
GND3
GND5
2
5
6
7
8
5
6
7
8
VCC
1
MCA0_DEC_B
7
GND
MCA0_DEC_A
21
Y0
0.1uF
10
8
R499
10K
VCC
R500
10K
21
C166
U43
GND
C
U91
0.1uF
15
U47
C431
SN74CB3T16210DGV
MCASP0/1/3 DECODER
EVM_3V3
EVM_3V3
EVM_3V3
EVM_3V3
Y1
Y2
Y3
6
MCA0/1/3_nOE_3
5
MCA0/1/3_nOE_1
2
5
9
12
3
MCA0/1/3_nOE_0
1
4
10
13
MCA0/1/3_nOE_0
4
MCA0/1/3_nOE_1
SN74LVC1G139
0.1uF
14
1A
1B
2A
2B
3A
3B
4A
4B
1OE
2OE
3OE
4OE
SN74CBTLV3125PWR
MCA0_AXR4
3
6
MCA0_AXR5
8
MCA1_AXR2
11
MCA1_AXR3
MCA0_AXR4
8
MCA0_AXR5
8
MCA1_AXR2
8
MCA1_AXR3
8
U76
6,7
MCA0_AXR4_1
R453
0E
MCA0_AXR5_1
R442
0E
2
1
6,7
MCA0/1/3_nOE_3
5
7
1A
8
Y0
B
1 0E
2
3
4
VCC
A
RA39 8
7
6
5
B
1B
3
MCA3_AXR2
6
MCA3_AXR3
MCA3_AXR2
14
MCA3_AXR3
14
1OE
2A
2B
2OE
GND
2
MCA0_AXR4_1
MCA0_AXR5_1
4
1
6,7
6,7
7
VCC
8
R465
VCC
R464
10K
0.1uF
GND
MCA0/1/3_RSEL_A
MCA0/1/3_RSEL_B
C276
U77
7
21
21
0.1uF
C289
U75
GND
B
10K
C283
SN74CB3Q3306ADCUR
MCASP0 DECODER SELECTION TABLE
MCASP0/1/3 DECODER SELECTION TABLE
MCASP1 MUX SELECTION TABLE
MCASP1 IS MAPPED
CODEC
TO
A
MCASP1
MCASP3
B
A
B
A
LOW
LOW
NOT USED
LOW
LOW
NOT USED
LOW
HIGH
MCASP4
LOW
HIGH
MCASP3_AXR[2:3]
HIGH
LOW
MCASP2
HIGH
LOW
MCASP1_AXR[2:3]
HIGH
HIGH
MCASP0 (default)
HIGH
HIGH
MCASP0_AXR[4:5] (default)
MCASP0 IS MAPPED TO
MCASP0_AXR[4:5] IS MAPPED TO
MCASP5
MCA1_MUX2_nOE
HIGH
HIGH
LOW
LOW
MCA1_MUX_SEL
HIGH
LOW
HIGH
LOW
A
BY DEFAULT, CODEC IS SELECTED BY MCASP1.
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
MCASP_MUXING
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
7
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
79
Appendix A
www.ti.com
Figure A-7. McASP B-B Connection
5
4
3
2
1
J30
I2C1_SCL
MCA0_AXR3
7
MCA0_AXR2
6
7
7
18
C
7
7
7
MCA1_AFSX
MCA0_AXR1
VOUT1_G_Y_YC4
7
MCA0_AXR5
7
7
MCA0_AXR4
MCA0_AXR0
6
MCA1_ACLKR
6
MCA1_AFSR
VOUT1_G_Y_YC7
18
18
18
VOUT1_R_CR7
VOUT1_VSYNC
18
B
AUD_CLKIN0
MCA0_AFSR
MCA0_ACLKX
MCA0_AFSX
VOUT1_R_CR8
21
18
MCA0_AXR9
VOUT1_HSYNC
7
MCA0_ACLKR
18
VOUT1_AVID
MCA0_AXR3
MCA0_AXR2
MCA0_AFSR
MCA0_ACLKX
MCA0_AFSX
MCA1_AFSX
MCA0_AXR1
IP_EVM_12V
VOUT1_G_Y_YC4
MCA0_AXR5
MCA0_AXR4
MCA0_AXR0
MCA1_ACLKR
MCA1_AFSR
VOUT1_G_Y_YC7
VOUT1_R_CR7
VOUT1_VSYNC
VOUT1_R_CR8
VOUT1_HSYNC
MCA0_ACLKR
VOUT1_AVID
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
G2
G4
G6
G8
G1
G3
G5
G7
PM_I2C_SCL
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
MDIO_MDIO
PM_I2C_SDA
EXP_MCA2_AXR0
MCA1_AXR2
EXP_MCA2_AXR1
PM_I2C_SCL
MCA1_AXR2
7
EXP_MCA2_AXR1
7
MCA1_AXR3
MCA1_AXR3
7
EXP_MCA2_ACLKX
EXP_MCA2_ACLKX
MCA2_AXR2
EXP_MCA2_AFSX
MCA2_AXR3
MCA1_AXR1
MCA1_AXR0
VOUT1_G_Y_YC8
VOUT1_B_CB_C9
EXP_EVM_3V3
EXP_EVM_5V0
14,19,28,29
PM_I2C_SDA
14,19,28,29
EXP_MCA2_AXR0
7
7
MCA2_AXR2
7
EXP_MCA2_AFSX
7
AUD_CLKIN2
MCA2_AXR3
6
7
MCA1_AXR1
MCA1_AXR0
7
7
VOUT1_G_Y_YC8
VOUT1_B_CB_C9
18
18
EXP_EVM_3V3
EXP_EVM_5V0
AUD_CLKIN1
MDIO_MDCLK
MCA1_ACLKX
VOUT1_B_CB_C3
VOUT1_B_CB_C4
VOUT1_B_CB_C6
VOUT1_B_CB_C5
VOUT1_B_CB_C8
VOUT1_B_CB_C7
VOUT1_G_Y_YC3
VOUT1_G_Y_YC5
VOUT1_G_Y_YC6
VOUT1_G_Y_YC9
VOUT1_R_CR4
VOUT1_R_CR6
VOUT1_R_CR5
VOUT1_CLK
VOUT1_R_CR9
MDIO_MDIO
D
6
IP_EVM_12V
10uF C443
20
7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
10uF C440
0E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
0.1uF C445
R267
I2C0_SCL
I2C1_SDA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
0.1uF C442
20,21,28,33,9
20
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
100uF C444
0E
0E
100uF C441
0E
R274
R270
10uF C448
R272
I2C2_SCL/UART2_RXD_EXP
20,21,28,33,9
I2C0_SDA
0.1uF C446
I2C2_SDA/UART2_TXD_EXP
18
100uF C447
D
18
C
10,11,12
MDIO_MDCLK
MCA1_ACLKX
10,11,12
7
VOUT1_B_CB_C3
VOUT1_B_CB_C4
18
18
VOUT1_B_CB_C6
VOUT1_B_CB_C5
18
18
VOUT1_B_CB_C8
VOUT1_B_CB_C7
18
18
VOUT1_G_Y_YC3
VOUT1_G_Y_YC5
18
18
VOUT1_G_Y_YC6
VOUT1_G_Y_YC9
18
18
VOUT1_R_CR4
VOUT1_R_CR6
CONNECTOR : J30 ON DM385 Board
App.BOARD
18
18
VOUT1_R_CR5
18
VOUT1_CLK
18
VOUT1_R_CR9
MATING CONNECTOR
VIDEO CAMERA
VIDEO CONFERENCE
18
121
123
125
127
B
J3
J3
VIDEO SECURITY
J14
I/O EXPANDER
J3
CON_PMC_60X2_F
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
McASP B-B CONN
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Design file path:
Date:
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
80
4
3
Schematics
2
Document Number
MS_TI_DM385EVM_REVB_SCH
Tuesday, January 24, 2012
Rev
B
Sheet
8
of
39
1
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-8. AIC3106
5
4
3
2
1
FL4
VDAC_3V3
1
C58
0.1uF
FL5
U13
C28
0.1uF
C29
2.2uF
220E
DVSS
DRVSS.1
DRVSS.2
4
R63
0E
U95
C32
1
LINE IN
IO1
IO2
5
0.1uF
2
6
3
GND
GND_AIC
7
8
TPD2E007DCKR
9
CON_AUDIOJACK4_STX-3500-4N
10
2
4
3
1
GND_AIC
R14
C22
0.1uF
R29
14
0E
11
R31
MIC
12
330E
0.1uF
R32
13
2.2K
0E
C27
20,21,28,33,8
20,21,28,33,8
R94
R89
R90
R85
R50
R51
I2C0_SDA
I2C0_SCL
GND_AIC
33
RSTOUTn
AIC_BCLK
AIC_WCLK
AIC_DIN
AIC_DOUT
10E
10E
10E
10E
38
39
40
41
2
1
0E
0E
43
VDAC_3V3
R79
10K
DNI
R93
20K
220E
D
26
15
GND_AIC
CON_AUDIOJACK4_STX-3500-4N
LINE1R+
GND_AIC
LINE1R-
HPLOUT
HPLCOM
C113
33uF_6.3V
33uF_6.3V
C97
U96
1
LINE2L-
HPROUT
HPRCOM
23
22
LINE2R+
LINE2R-
MONO_LO+
MONO_LO-
2
4
3
1
18
19
LINE2L+
27
28
TP36
TP43
IO1
2
IO2
R149 HP
0E
OUT
LEFT_LO+
MIC3L
LEFT_LOMICDET
RIGHT_LO+
MICBIAS
RESET
GPIO1
GPIO2
BCLK
WCLK
DIN
DOUT
MFP0
MFP1
MFP2
MFP3
CON_AUDIOJACK4_STX-3500-4N
GND_AIC
29
GND_AIC
R105 100E
30
31
R92
100E
C75
0.047uF
C63
0.047uF
32
2
4
3
1
VDAC_3V3
35
34
U97
R34
10K
DNI
R41
10K
DNI
R47
10K
DNI
1
R106
20K
R87
20K
TP41
TP46
45
46
47
48
GND_AIC
VAIC_1V8
SELECT
MCLK
IN
OUT
GND_AIC
R35
10K
DNI
R42
10K
DNI
R48
2K
2.2uF
C
R53
2K
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
I2C0 ADDRESS : 0X18
R148
0E
5
GND_AIC
4
GND
NC/FB
EN
R110
80K
C72
C65
4.7uF 0.1uF
2
C106
3
TPD2E007DCKR
AIC_MCLK_BUF
37
R78
2K
100mA
1
J16
LINE OUT
GND_AIC
TP51
U23
2
IO2
GND_AIC
vout= 1.224(1+80/169)= 1.8V
VDAC_3V3
IO1
R52
10K
DNI
SDA
SCL
R84
20K
J17
TPD2E007DCKR
GND_AIC
MIC3R
TPAD
11,12,14,26,27
AIC_BCLK_BUF
AIC_WCLK_BUF
AIC_DIN_BUF
AIC_DOUT_BUF
C110
0.1uF
25
49
GND_AIC
R25
10K
DNI
C17
0.1uF
DNI
C
AVSS_DAC
AVSS_ADC
LINE1L-
RIGHT_LO-
GND_AIC
C109
2.2uF
GND_AIC
AVDD_DAC
LINE1L+
R118
3
0.1uF
2
0E
C45
C67
0.1uF
IOVDD
D
2
4
3
1
VDAC_3V3
1
20
21
GND
44
CON_AUDIOJACK4_STX-3500-4N
DVDD.1
3
42
GND
36
3
C44
10uF
20K R129
C48
0.1uF
FL6
GND_AIC
20K R146
C40
0.1uF
J14
C52
0.1uF
TLV320AIC3106IRGZT
16
DRVDD.1 17
DRVDD.2 24
DRVDD.3
+
VAIC_1V8
J15
C47
0.1uF
220E
2
1
+
VDAC_3V3
2
TPS76901DBVT
R113
169K_1%
EVM_3V3
VDAC_3V3
EVM_3V3
DNI
C104 0.1uF
C79
DNI
0.1uF
EVM_3V3
R492
0E
AIC_BCLK_BUF
R491
0E
AIC_WCLK_BUF
B_AIC_DIN
R495
0E
AIC_DIN_BUF
B_AIC_WCLK
3
A
DIR
R109
10K
DNI
SN74AVCH1T45DBVR
EVM_3V3
EVM_3V3
C98
AIC_MCLK
R494
0E
AIC_MCLK_BUF
B_AIC_DOUT
R493
0E
AIC_DOUT_BUF
C82
DNI
0.1uF
C96
VDAC_3V3
C84
B_AIC_DOUT
DIR
B_AIC_DOUT
R111
3
5
10K
DNI
A
DIR
SN74AVCH2T45DCTR
6
DNI
0.1uF
DNI
B
4
AIC_DOUT_BUF
GND
7
VCCB
1
AIC_DIN_BUF
AIC_MCLK_BUF
VCCA
8
1
VCCB
B1
B2
7
6
2
R120
10K
DNI
DNI
GND
5
EVM_3V3
A1
A2
4
B_AIC_DIN
AIC_MCLK
VCCA
7
6
B
AIC_WCLK_BUF
4
SN74AVCH1T45DBVR
DNI
0.1uF
U21
2
3
DNI
B
VDAC_3V3
DNI
0.1uF
U22
B_AIC_DIN
AIC_MCLK
6
6
1
B_AIC_WCLK
VCCB
R127
10K
DNI
7
AIC_BCLK_BUF
VCCA
B
4
5
2
R108
10K
DNI
B_AIC_WCLK
DNI
0.1uF
GND
DIR
U20
DNI
2
5
A
VCCA
B_AIC_BCLK
3
GND
B_AIC_BCLK
VCCB
1
U19
B_AIC_BCLK
C80
EVM_3V3
R126
10K
DNI 7
B
VDAC_3V3
DNI
C105 0.1uF
SN74AVCH1T45DBVR
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
AIC3106
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVA_SCH
Rev
B
Sheet
Tuesday, March 06, 2012
9
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
81
Appendix A
www.ti.com
Figure A-9. GMII0 Interface
5
4
3
2
1
D
D
U55C
GMII0 INTERFACE
11
12
12
RGMII0_RXC
RGMII1_RXC
RGMII1_RXD[2]
12
RGMII1_RXD[3]
12
12
12
RGMII1_TXCTL
RGMII1_TXC
RGMII1_RXD[0]
RGMII0_RXC
RGMII1_RXC
RGMII1_RXD[2]
AG4
AL6
AF8
RGMII1_RXD[3]
CRGMII1_TXD[1]
RGMII1_TXCTL
R551
CRGMII1_TXD[0]
CRGMII1_TXD[2]
RGMII1_TXC R548
RGMII1_RXD[0]
CRGMII1_TXD[3]
AK6
AJ7
AK7
AE4
AK8
AJ8
AH8
AG8
22E
22E
AK1
EMAC[0]_MRCLK/VIN[1]B_D[4]/EMAC[0]_RMCsM8ISDV/SPI[3]_SCS[2]n/GP3[27]/RGMII0_TXCAG1
EMAC[0]_MTCLK/VIN[1]B_D[0]/SPI[3]_SCS[3]n/I2C[2]_SDA/GP3[23]/RGMII0_RXC
EMAC_RMREFCLK/TIM2_IO/GP1[10]
EMAC[0]_GMTCLK/GPMC_A[6]/SPI[2]_D[1]/RGMII1_RXC
EMAC[0]_MTXEN/EMAC[1]_RMTXEN/GPMC_A[15]/UART1_RTSn/RGMII1_RXD[2]
AK2
EMAC[0]_MRXD[0]/VIN[1]B_D[5]/EMAC[0]_RMTXD[0]/GP3[28]/RGMII0_TXD[0] AL2
EMAC[0]_MRXD[1]/VIN[1]B_D[6]/EMAC[0]_RMTXD[1]/GP3[29]/RGMII0_RXD[0]
EMAC[0]_MTXD[0]/GPMC_A[7]/SPI[2]_D[0]/RGMII1_RXD[3]
AL3
EMAC[0]_MTXD[1]/GPMC_A[8]/RGMII1_TXD[1]
EMAC[0]_MRXD[2]/VIN[1]B_D[7]/EMAC[0]_RMTXEN/GP3[30]/RGMII0_RXD[1] AK3
EMAC[0]_MTXD[2]/EMAC[1]_RMRXD[0]/GPMC_A[9]/RGMII1_TXCTL
EMAC[0]_MRXD[3]/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/RGMII1_RXCTL AK4
EMAC[0]_MTXD[3]/EMAC[1]_RMRXD[1]/GPMC_A[10]/RGMII1_TXD[0]
EMAC[0]_MRXD[4]/GPMC_A[1]/RGMII0_RXD[3] AJ4
EMAC[0]_MTXD[4]/EMAC[1]_RMRXER/GPMC_A[11]/RGMII1_TXD[2]
EMAC[0]_MRXD[5]/GPMC_A[2]/RGMII0_TXD[3]
EMAC[0]_MTXD[5]/EMAC[1]_RMCRSDV/GPMC_A[12]/UART1_RXD/RGMII1_TXC
AL5
EMAC[0]_MTXD[6]/EMAC[1]_RMTXD[0]/GPMC_A[13]/UART1_TXD/RGMII1_RXD[0]
EMAC[0]_MRXD[6]/GPMC_A[3]/RGMII0_TXD[2] AK5
EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[1]/GPMC_A[14]/UART1_CTSn/RGMII1_TXD[3]
EMAC[0]_MRXD[7]/GPMC_A[4]/SPI[2]_SCS[3]n/RGMII0_TXD[1]
C
11,12,8
11,12,8
MDIO_MDCLK
MDIO_MDIO
R329
R334
22E
22E
AG2
AG3
EMAC[0]_MRXDV/GPMC_A[5]/SPI[2]_SCLK/RGMII1_RXD[1]
EMAC[0]_MRXER/VIN[1]B_D[3]/EMAC[0]_RMRXER/GP3[26]/RGMII0_TXCTL
MDCLK/GP1[11]
MDIO/GP1[12]
EMAC[0]_MCOL/VIN[1]B_D[1]/EMAC[0]_RMRXD[0]/GP3[24]/RGMII0_RXCTL
EMAC[0]_MCRS/VIN[1]B_D[2]/EMAC[0]_RMRXD[1]/GP3[25]/RGMII0_RXD[2]
R541
R544
22E RGMII0_TXC
0E
RGMII0_TXC
ENET_INT
12
CRGMII0_TXD[0]
RGMII0_RXD[0]
RGMII0_RXD[1]
RGMII1_RXCTL
RGMII0_RXD[3]
CRGMII0_TXD[3]
11
RGMII0_RXD[0]
11
RGMII0_RXD[1]
RGMII1_RXCTL
RGMII0_RXD[3]
11
12
11
CRGMII0_TXD[2]
CRGMII0_TXD[1]
RGMII1_RXD[1]
R547
22E RGMII0_TXCTL
AJ6
AJ2
RGMII0_RXCTL
RGMII0_RXD[2]
AH1
AH2
RGMII1_RXD[1]
RGMII0_TXCTL
RGMII0_RXCTL
RGMII0_RXD[2]
12
11
C
11
11
TMS320DM385
12
12
12
12
B
RGMII1_TXD[0]
RGMII1_TXD[1]
RGMII1_TXD[2]
RGMII1_TXD[3]
RGMII1_TXD[0] RA34 5
RGMII1_TXD[1]
6
RGMII1_TXD[2]
7
RGMII1_TXD[3]
8
4 22E CRGMII1_TXD[0]
CRGMII1_TXD[1]
3
CRGMII1_TXD[2]
2
CRGMII1_TXD[3]
1
CRGMII0_TXD[0]
CRGMII0_TXD[1]
CRGMII0_TXD[2]
CRGMII0_TXD[3]
RA37 4
3
2
1
5 22E RGMII0_TXD[0]
RGMII0_TXD[1]
6
RGMII0_TXD[2]
7
RGMII0_TXD[3]
8
RGMII0_TXD[0]
RGMII0_TXD[1]
RGMII0_TXD[2]
RGMII0_TXD[3]
11
11
11
11
B
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
DM385_GMII
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
82
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
Schematics
2
Rev
B
Sheet
10
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-10. Ethernet Controller 0
5
4
3
2
1
EVM_3V3
L14
10E
C481
EVM_3V3
ETH0_AVDD_3V3
VDDIO0_REG
10E
C480
10uF_10V
R363 DNI 10K
+1.1V
VDDIO0_REG
PHYADDRESS0 (IPD)
RGMII0_RXD[0]
PHYADDRESS1 (IPD)
RGMII0_RXD[1]
R364
MODE2[3:0]
(Default assemble: 0000)
1100 BaseT, RMII1;
1101 BaseT, RMII2;
1110 100X, RGMII, 75OHMS;
1111 100X, TRANS, 75OHMS;
0000 BaseT, RGMII;
0001 BaseT, SGMII;
0010 1000X, RGMII, 50OHMS;
0011 1000X, RGMII, 75OHMS;
0100 1000X, TRANS, 50OHMS;
0101 1000X, TRANS, 75OHMS;
0110 100X, RGMII, 50OHMS;
0111 100X, TRANS, 50OHMS;
Others Reserved
10K
VDDH_PHY0
R361 DNI 10K
R533
0E
C530
C489
4.7uH
EVM_3V3VDDH_PHY0
ETH0_AVDD_3V3
VDDIO0_REG
C488
1uF
0.1uF
C519
C216
C482
0.1uF
C217
C501
0.1uF
D
0.1uF
C202
1uF
0.1uF
C500
0.1uF
DVDDL_PHY0
L13
2
0.1uF
1
10uF C203
L15
0.1uF
2
0.1uF
+
1
R362
10K
R352 DNI 10K
MODE2[0]
RGMII0_RXCTL
MODE2[1]
RGMII0_RXD[2]
MODE2[2]
RGMII0_RXC
MODE2[3]
RGMII0_RXD[3]
R365
10K
RGMII0_TXCTL
RGMII0_RXCTL
RGMII0_RXCTL
34
32
R351 22E
RGMII0_RXC
R337 22E
33
RGMII0_TXC
R330 22E
35
TP91
R332 22E
PHY0_SYNE_CLK
25
TP86
R313 22E
PHY0_PPS/GPIO
22
10
RGMII0_RXC
10
RGMII0_TXC
ETH0_RESET
2
7
6
1
22pF C198
9
C
12
ENET0_INT
12
ENET0_WoL
ENET0_INT 5
40
29
3
LX
VDDIO_REG
16
10
47
44
19
13
4
VDD33
AVDD33
TRXP0
TRXN0
TRXP1
TRXN1
TRXP2
TRXN2
TRXP3
TRXN3
TX_EN
RX_DV
SIP
SIN
RX_CLK
GTX_CLK
SOP
SON
CLK_125M
SD
PPS
MDC
MDIO
11
12
TRD0[0]P
TRD0[0]N
14
15
TRD0[1]P
TRD0[1]N
17
18
TRD0[2]P
TRD0[2]N
20
21
TRD0[3]P
TRD0[3]N
R360
10K
R338 DNI 10K
R331
10K
R357 DNI 10K
TP83
TP80
43
42
TP87
TP85
1
48
4.7K
10K
VDDH_PHY0
R335 DNI 10K
46
45
41
R358
R312
SEL_GPIO_INT
PHY0_LED_1000n
ANA_MOD (IPU)
PHY0_LED_ACTn
R336
D
10K
R327 DNI 10K
R318
10K
DVDDL_PHY0
MDIO_MDCLK
10,12,8
MDIO_MDIO
10,12,8
RST
XTLI
XTLO
LED_ACT
LED_LINK1000
RBIAS
LED_LINK10_100
23
PHY0_LED_ACTn
C226
DNI 470pF
24
PHY0_LED_1000n
C231
DNI 470pF
26
PHY0_LED_10/100n C235
DNI 470pF
INT
WOL_INT
49
2
22pF C199
2.37K_1% R285
Y2
25MHz
RXD0
RXD1
RXD2
RXD3
VDDH_REG
1 22E 31
2
30
3
28
4
27
DVDDL
RGMII0_TXCTL
8 RA33
7
6
5
AVDDL
10
RGMII0_RXD[0]
RGMII0_RXD[1]
RGMII0_RXD[2]
RGMII0_RXD[3]
AVDDL
RGMII0_RXD[0]
RGMII0_RXD[1]
RGMII0_RXD[2]
RGMII0_RXD[3]
TXD0
TXD1
TXD2
TXD3
AVDDL
10
10
10
10
36
37
38
39
AVDDL
RGMII0_TXD[0]
RGMII0_TXD[1]
RGMII0_TXD[2]
RGMII0_TXD[3]
EVM_3V3
EP
10
RGMII0_TXD[0]
RGMII0_TXD[1]
RGMII0_TXD[2]
RGMII0_TXD[3]
10
10
10
10
8
R359 DNI 10K
U52
PHY0_LED_1000n
R345
330E
1
C
DNI GREEN
LD7 2
AR8031-AL1A
LTST-C150GKT
2 LD6
1
LTST-C150GKT
EVM_3V3
MDIO_MDCLK
MDIO_MDIO
ENET0_INT
10K R525
1.5K R530
DNI
10K R528
ETHERNET CONNECTOR-1
J20
G
PHY0_LED_ACTn
R277
221E_1%
D1
Y
D2
R390 DNI 10K
1 CH_GND
2 VCC
3 MX3+
TRD0[3]P
RJ-8 TD3-
EVM_3V3
TRD0[3]N
4 MX3-
TRD0[2]P
5 MX2+
TRD0[2]N
6 MX2-
TRD0[1]P
7 MX1+
RJ-7 TD3+
EVM_3V3
C230
EVM_3V3
B
8
U57A
RSTOUTn
7
RJ-5 TD2-
ETH0_RESET
2
SN74LVC2G08DCTR
C551
RJ-4 TD2+
0.1uF
EXP_ETH_RESET
B
R542
100K
1
4
12,21
12,14,26,27,9
RJ-6 TD1-
0.1uF
R326
100K
TRD0[1]N
8 MX1-
TRD0[0]P
9 MX0+
TRD0[0]N
10 MX0-
RJ-3 TD1+
RJ-2 TD0-
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
RJ-1 TD0+
G
D3
Y
Shield
D4
R343
221E_1%
CON_RJ45-14_6605814-6
A
R517
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
RJ-45
Cable
side
SH1
SH2
PHY0_LED_10/100n
A
0E
ETHERNET CONTROLLER-0
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
11
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
83
Appendix A
www.ti.com
Figure A-11. Ethernet Controller 1
5
4
3
2
1
MODE2[3:0]
(Default assemble: 0000)
1100 BaseT, RMII1;
1101 BaseT, RMII2;
1110 100X, RGMII, 75OHMS;
1111 100X, TRANS, 75OHMS;
0000 BaseT, RGMII;
0001 BaseT, SGMII;
0010 1000X, RGMII, 50OHMS;
0011 1000X, RGMII, 75OHMS;
0100 1000X, TRANS, 50OHMS;
0101 1000X, TRANS, 75OHMS;
0110 100X, RGMII, 50OHMS;
0111 100X, TRANS, 50OHMS;
Others Reserved
VDDIO1_REG
L17
10E
ETH1_AVDD_3V3
L18
10E
RGMII1_RXC
RGMII1_TXC
33
R430 22E
RGMII1_TXC
R423 22E
TP106
R425 22E
PHY1_SYNE_CLK
25
TP104
R402 22E
PHY1_PPS/GPIO
22
ETH1_RESET
2
7
6
1
22pF C263
9
ENET1_INT
5
ENET1_WoL
40
C270
C583
C269
0.1uF
10uF C265
29
16
10
SIP
SIN
RX_CLK
GTX_CLK
SOP
SON
CLK_125M
SD
PPS
MDC
MDIO
TRD1[1]P
TRD1[1]N
17
18
TRD1[2]P
TRD1[2]N
20
21
TRD1[3]P
TRD1[3]N
R450
10K
R444
10K
MODE2[1]
RGMII1_RXD[2]
MODE2[2]
RGMII1_RXC
MODE2[3]
RGMII1_RXD[3]
R447
10K
R431 DNI 10K
R424
10K
TP95
TP97
43
42
TP100
TP102
1
48
4.7K
10K
VDDH_PHY1
R428 DNI 10K
46
45
41
R445
R401
SEL_GPIO_INT
PHY1_LED_1000n
ANA_MOD (IPU)
PHY1_LED_ACTn
R429
10K
R414 DNI 10K
R405
10K
DVDDL_PHY1
MDIO_MDCLK
10,11,8
MDIO_MDIO
10,11,8
RST
XTLI
XTLO
LED_ACT
LED_LINK1000
RBIAS
LED_LINK10_100
23
PHY1_LED_ACTn
C274
DNI 470pF
24
PHY1_LED_1000n
C284
DNI 470pF
26
PHY1_LED_10/100n C287
PHY1_LED_1000n
R437
LD9
DNI GREEN
2
1
330E
EVM_3V3
LTST-C150GKT
DNI 470pF
LD8
INT
2
WOL_INT
D
R446 DNI 10K
1
C
LTST-C150GKT
EVM_3V3
AR8031-AL1A
MDIO_MDCLK
MDIO_MDIO
ENET1_INT
EVM_3V3
RGMII1_RXCTL
MODE2[0]
3
LX
VDDIO_REG
4
47
44
RX_DV
TRD1[0]P
TRD1[0]N
14
15
R452 DNI 10K
R448 DNI 10K
DNI
10K R556
2
C572
10uF_10V
TRXP3
TRXN3
TX_EN
49
0.1uF
22pF C264
+
2.37K_1% R385
Y7
25MHz
C573
EVM_3V3
35
TRXP2
TRXN2
11
12
RGMII1_RXD[1]
R440 DNI 10K
C576
1uF
0.1uF
32
RGMII1_RXC
TRXP1
TRXN1
RGMII1_RXD[0]
PHYADDRESS1 (IPD)
R449 DNI 10K
0E
10K R554
RGMII1_RXCTL R439 22E
10
10
19
C582
0.1uF
34
13
C578
0.1uF
RGMII1_TXCTL
RXD0
RXD1
RXD2
RXD3
TRXP0
TRXN0
PHYADDRESS0 (IPD)
VDDH_PHY1
R564
1.5K R559
RGMII1_RXCTL
1 22E 31
2
30
3
28
4
27
VDD33
RGMII1_TXCTL
8 RA38
7
6
5
TXD0
TXD1
TXD2
TXD3
AVDD33
10
RGMII1_RXD[0]
RGMII1_RXD[1]
RGMII1_RXD[2]
RGMII1_RXD[3]
36
37
38
39
VDDH_REG
RGMII1_RXD[0]
RGMII1_RXD[1]
RGMII1_RXD[2]
RGMII1_RXD[3]
VDDIO1_REG
DVDDL
10
10
10
10
4.7uH
VDDIO1_REG
ETH1_AVDD_3V3
AVDDL
RGMII1_TXD[0]
RGMII1_TXD[1]
RGMII1_TXD[2]
RGMII1_TXD[3]
L16
EVM_3V3VDDH_PHY1
EP
10
RGMII1_TXD[0]
RGMII1_TXD[1]
RGMII1_TXD[2]
RGMII1_TXD[3]
10
10
10
10
8
C574
0.1uF
U66
AVDDL
C581
0.1uF
C580
1uF C266
0.1uF
D
0.1uF
2DVDDL_PHY1
1
C
R451 10K
2
AVDDL
1
AVDDL
EVM_3V3
ETHERNET CONNECTOR-2
R389 DNI 10K
J21
G
EVM_3V3
PHY1_LED_ACTn
R381
221E_1%
D1
Y
D2
R546
100K
8
U57B
11,21
EXP_ETH_RESET
11,14,26,27,9
RSTOUTn
1 CH_GND
2 VCC
5
ETH1_RESET
3
3 MX3+
TRD1[3]P
RJ-8 TD3-
4
C554
0.1uF
6
SN74LVC2G08DCTR
TRD1[3]N
4 MX3-
TRD1[2]P
5 MX2+
RJ-7 TD3+
RJ-6 TD1-
EVM_3V3
B
5
ENET_INT
ENET_INT
U60
TRD1[2]N
6 MX2-
TRD1[1]P
7 MX1+
RJ-5 TD2-
RJ-4 TD2+
1
ENET1_INT
2
ENET0_INT
4
SN74LVC1G02DBVR
ENET0_INT
11
3
10
0.1uF
C250
B
TRD1[1]N
8 MX1-
TRD1[0]P
9 MX0+
RJ-3 TD1+
RJ-2 TD0-
RJ-1 TD0+
10 MX0-
TRD1[0]N
EVM_3V3
1
ENET0_WoL
2
ENET1_WoL
SN74LVC1G32DBVR
A
ENET0_WoL
11
DNI
4.7K
R532
DNI
4.7K
R563
4
ENET_WoL_INT
3
6
U53
G
RJ-45
Cable
side
D3
Y
Shield
D4
PHY1_LED_10/100n R433
221E_1%
CON_RJ45-14_6605814-6
A
R550
NATURE OF CHANGE
REV NO.
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
SH1
SH2
5
C204 0.1uF
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
0E
ETHERNET CONTROLLER-1
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
84
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
12
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-12. NAND Flash
5
13,14
13,14
13,14
13,14
4
RA3
GPMC_D14
GPMC_D2
GPMC_D8
GPMC_D15
8
7
6
5
1 22E
2
3
4
5
6
7
8
8
7
6
5
22E
4
3
2
1
1 22E
2
3
4
GP_D6
GP_D12
GP_D13
GP_D0
GP_D15
GP_D8
GP_D2
GP_D14
4 22E
3
2
1
1 RA14
2
3
4
GP_D9
GP_D10
GP_D5
GP_D11
GP_D3
GP_D1
GP_D4
GP_D7
BTMODE9
BTMODE10
BTMODE5
BTMODE11
BTMODE3
BTMODE1
BTMODE4
BTMODE7
14
14
14
14
14
14
2
1
U55D
RA5
BTMODE6
BTMODE12
BTMODE13
BTMODE0
BTMODE15
BTMODE8
BTMODE2
BTMODE14
D
3
RA2
RA17 5
6
7
8
22E 8
7
6
5
GP_A16
GP_A17
GP_A18
GP_A19
GP_A20
GP_A21
GPMC_A16
GPMC_A17
GPMC_A18
GPMC_A19
GPMC_A20
GPMC_A21
GPMC_A22_T
GPMC_A23_T
GP_A22
GP_A23
R527 22E
R302 22E
GP_D0
GP_D1
GP_D2
GP_D3
GP_D4
GP_D5
GP_D6
GP_D7
GP_D8
W6
W4
W3
U2
W9
T5
T3
T2
T1
GP_D9
GP_D10
GP_D11
GP_D12
GP_D13
GP_D14
GP_D15
T8
R6
R4
R3
R2
R1
P2
GP_A16
GP_A17
GP_A18
GP_A19
GP_A20
GP_A21
GP_A22
GP_A23
M1
M2
M3
M5
N9
N1
N2
R8
GPMC INTERFACE
GPMC_D[0]/BTMODE[0]
GPMC_D[1]/BTMODE[1]
GPMC_D[2]/BTMODE[2]
GPMC_D[3]/BTMODE[3]
GPMC_D[4]/BTMODE[4]
GPMC_D[5]/BTMODE[5]
GPMC_D[6]/BTMODE[6]
GPMC_D[7]/BTMODE[7]
GPMC_D[8]/BTMODE[8]
AB9
GPMC_CLK/GPMC_CS[5]n/GPMC_WAIT[1]/CLKOUT1/EDMA_EVT3/TIM4_IO/GP1[27]
GPMC_CLK
Y3
Y11
Y5
GPMC_WEn
R536 22E
Y8
W8
GPMC_OEn_REn
GPMC_WAIT[0]/GPMC_A[26]/EDMA_EVT0/GP1[31]
GPMC_D[9]/BTMODE[9]
GPMC_D[10]/BTMODE[10]
GPMC_D[11]/BTMODE[11]
GPMC_D[12]/BTMODE[12]
GPMC_D[13]/BTMODE[13]
GPMC_D[14]/BTMODE[14]
GPMC_D[15]/BTMODE[15]
R308 22E
AA10
GPMC_ADVn_ALE/GPMC_CS[6]n/TIM5_IO/GP1[28]
GPMC_BE[0]n_CLE/GPMC_A[25]/EDMA_EVT2/TIM6_IO/GP1[29]
GPMC_BE[1]n/GPMC_A[24]/EDMA_EVT1/TIM7_IO/GP1[30]
13,14
GPMC_nBE0_CLE
GPMC_nBE1
14
13,14
GPMC_WEN
13,14
D
R537 22E
GPMC_OEN_REN
13,14
GPMC_WAIT0
13,14
GPMC_nCS0
AC9
AA12
AC3
AF2
AG6
GPMC_CS[0]n/GP1[23]
GPMC_CS[1]n/GPMC_A[25]/GP1[24]
GPMC_CS[2]n/GPMC_A[24]/GP1[25]
GPMC_CS[3]n/VIN[1]B_CLK/SPI[2]_SCS[0]n/GP1[26]
GPMC_CS[4]n/SD2_CMD/GP1[8]
14
GPMC_nADV_ALE
GPMC_nCS1
GPMC_nCS2
GPMC_nCS3
GPMC_nCS4
R319 DNI 22E
GPMC_A[16]/GP2[5]
GPMC_A[17]/GP2[6]
GPMC_A[18]/TIM2_IO/GP1[13]
GPMC_A[19]/TIM3_IO/GP1[14]
GPMC_A[20]/SPI[2]_SCS[1]n/GP1[15]
GPMC_A[21]/SPI[2]_D[0]/GP1[16]
GPMC_A[22]/SPI[2]_D[1]/HDMI_CEC/TIM4_IO/GP1[17]
GPMC_A[23]/SPI[2]_SCLK/HDMI_HPDET/TIM5_IO/GP1[18]
14
14
14
14
PCF8575_INT_IO1
20,21
EVM_3V3
TMS320DM385
S1
RA6
8
7
6
5
RA18 8
7
6
5
1 22E
2
3
4
1 22E
2
3
4
GPMC_D7
GPMC_D4
GPMC_D1
GPMC_D3
RA15 8
7
6
5
1 22E
2
3
4
BTMODE0
BTMODE1
BTMODE2
BTMODE3
BTMODE4
BTMODE10
BTMODE11
BTMODE12
BTMODE13
BTMODE14
BTMODE15
BTMODE5
EVM_3V3
EVM_3V3
C151
0.1uF
EVM_3V3
C148
U37
U38
0.1uF
GPMC_nCS0
5
1
C
2
A
R208
10K
24
23
22
21
20
19
18
17
16
15
14
13
5
13,14
13,14
13,14
13,14
GPMC_D6
GPMC_D12
GPMC_D13
GPMC_D0
GPMC_D9
GPMC_D10
GPMC_D5
GPMC_D11
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
RA35 4
3
2
1
RA32 4
3
2
1
RA30 4
3
2
1
5 1K
6
7
8
5 1K
6
7
8
5 1K
6
7
8
218-12LPST
VCC
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
B
4
EXP_GPMC_nCS0
EXP_GPMC_nCS0
14
C
EVM_3V3
SW10
SPI
XIP (MUX0)
MMC
00011
SPI
NAND
NANDI2C
00100
12
10K
21
1
GPMC_ADD_SELn
3A
3B1
3B2
4A
4B1
4B2
GPMC_A23
HDMI_HP_IN
8 RA26
7
6
5
10K 1
2
3
4
22
14
22
EVM_3V3
11
10
14
13
EVM_3V3
S
15
NAND FLASH
EVM_3V3
C162
0.1uF
UART
2
A
10010
5
U48
VCC
U42
GPMC_nCS0
SPI
B
4
9
SPI
EMAC
10011
EVM_3V3
10100
1
OE
SN74CBTLV1G125DBVR
GPMC_nBE0_CLE
GPMC_nADV_ALE
13,14
R516
10K
3
NAND_BOOTn
UART
13,14
13,14
GND
EVM_3V3
MMC
13,14
GPMC_WEN
GPMC_nBE0_CLE
16
GPMC_ADVN_ALE
17
GPMC_WEN
18
GPMC_OEN_REN
GPMC_OEN_REN
25
GPMC_nWP
GPMC_nWP
NAND/SPI BOOT
NANDI2C
MMC
EMAC
UART
10101
SPI
MMC
MMC
SPI
SPI
MMC
UART
UART
EMAC
EMAC
10110
1
4NAND_BOOTn
2
3
8
19
7
R121
10K
SW5
R122
10K
SPI_BOOTn
EVM_3V3
SPI_BOOTn
10111
1
2
3
4
5
6
10
11
14
15
21
R513
10K
TDA02H0SB1
PCIE_32
RESERVED
MMC
PCIe_64
RESERVED
13,14
WE
RE
WP
R/B
NC-1
NC-2
NC-3
NC-4
NC-5
NC-6
NC-7
NC-8
NC-9
NC-10
GPMC_WAIT0
GPMC_WAIT0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
ALE
NC-11
NC-12
NC-13
NC-14
NC-15
NC-16
DNU
GPMC_D0
GPMC_D1
GPMC_D2
GPMC_D3
GPMC_D4
GPMC_D5
GPMC_D6
GPMC_D7
GPMC_D8
GPMC_D9
GPMC_D10
GPMC_D11
GPMC_D12
GPMC_D13
GPMC_D14
GPMC_D15
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
GPMC_D0
GPMC_D1
GPMC_D2
GPMC_D3
GPMC_D4
GPMC_D5
GPMC_D6
GPMC_D7
GPMC_D8
GPMC_D9
GPMC_D10
GPMC_D11
GPMC_D12
GPMC_D13
GPMC_D14
GPMC_D15
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
13,14
20
21
22
23
24
35
38
A
MT29F2G16ABAEAWP:E
11001
NATURE OF CHANGE
REV NO.
CLE
11000
NOTE: POSITION 1 IN ON CONDITION
SPI
CE
13
25
36
48
A
B
R226
10K
SN74CB3Q3257PWR
10K
10K
10K
8
R581
R580
R577
OE
C469
UART
EMAC
00001
GPMC_A22
14
CE_REMOTE_IN
5
6
C456
00010
SPI
2B1
2B2
C457
NANDI2C
MMC
16
2A
EVM_3V3
2
3
0.1uF
7
C694
0.1uF
1B1
1B2
0.01uF
GPMC_A23_T
1A
C459
NAND
NANDI2C
GDH04S04
0.01uF
SPI
NAND
8
7
6
5
1K
C460
UART
NANDI2C
1
2
3
4
RA27
0.1uF
4
R576
NAND
4
0.01uF
00000
XIP w/WAIT
(MUX0)
NANDI2C
3
12
34
37
39
RESERVED
GPMC_A22_T
VCC
BTMODE[4:0]
UART
NAND
2
VCC1
VCC2
VCC3
VCC4
RESERVED
4th
9
B
8
7
6
5
ON
1
VSS1
VSS2
VSS3
VSS4
RESERVED
U98
3rd
GND
RESERVED
1
2
3
4
EVM_3V3
BOOT MODES
2nd
BTMODE6
BTMODE7
BTMODE8
BTMODE9
5 RA36
6
7
8
5 RA31
6
7
8
5 RA29
6
7
8
BOOT MODE SETTING
1st
OE
SN74LVC1G04DCKR
SN74CBTLV1G125DBVR
10K 4
3
2
1
10K 4
3
2
1
10K4
3
2
1
1
GND
4
3
2
3
NAND_BOOTn
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
NAND FLASH
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Monday, March 05, 2012
13
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
85
Appendix A
www.ti.com
Figure A-13. GPMC B-B Connector
5
4
3
2
1
R558 DNI 0E
R557 DNI 0E
R552 DNI 0E
R553 DNI 0E
EVM_3V3
C262 0.1uF
J29
PM_I2C_SDA
OSC_WAKE
13
13
GPMC_A22
GPMC_A23
13
18
18
15
VOUT1_R_CR1
MMC2_DAT1
15
15
MMC2_DAT2
MMC2_DAT3
18
VOUT1_R_CR1
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
VOUT1_B_CB_C2
MMC2_CLK
VOUT1_B_CB_C2
MMC2_CLK
15
13
GPMC_WAIT0
McA5_AFSX_EXP
6
IP_EVM_12V
18
VOUT1_G_Y_YC0
13
GPMC_nBE0_CLE
C
13
13
GPMC_D4
GPMC_D3
13
GPMC_D1
McA5_ACLKX
7
13
GPMC_nCS4
VOUT1_R_CR0
GPMC_nCS4
VOUT1_R_CR0
VOUT1_G_Y_YC0
GPMC_nBE0_CLE
GPMC_D4
GPMC_D3
GPMC_D1
McA5_ACLKX
GPMC_nADV_ALE
GPMC_D6
GPMC_nADV_ALE
13
GPMC_D6
13
13
15
15
GPMC_D8
GPMC_D13
GPMC_D8
GPMC_D13
MMC0_DAT0
MMC0_DAT1
MMC0_DAT0
MMC0_DAT1
13
15
20,21
20,21
GPMC_WAIT0
McA5_AFSX_EXP
GPMC_D14
GPMC_D14
MMC0_DAT2
SPI0_MOSI
SPI0_MISO
18,20
DCAN0/UART2_RX
15
MMC0_DAT3
18,20
DCAN0/UART2_TX
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
G2
G4
G6
G8
G1
G3
G5
G7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
McA5_AXR0_EXP
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
GPMC_D5
GPMC_nCS3
EXP_GPMC_nCS0
GPMC_nCS2
GPMC_nCS1
GPMC_WEN
McA5_AXR1
GPMC_OEN_REN
GPMC_nBE1
VOUT1_G_Y_YC1
MMC2_DAT0
VOUT1_B_CB_C1
VOUT1_B_CB_C0
VOUT1_FLD_EXP
GPMC_D0
McA5_AXR0_EXP
6
20
GPMC_nCS3
13
EXP_GPMC_nCS0
GPMC_nCS2
GPMC_nCS1
13
13
GPMC_WEN
McA5_AXR1
13
7
13
GPMC_OEN_REN
GPMC_nBE1
13
13
VOUT1_G_Y_YC1
MMC2_DAT0
15
18
UART0_TXD
20
UART0_RXD
20
UART0_RTSn
20
UART0_CTSn
21
UART0_TXD
2
UART0_RXD
5
UART0_RTSn
9
UART0_CTSn
12
1
4
10
13
EXP_UART_EN#
1A
2A
2B
3A
3B
4A
4B
1OE
2OE
3OE
4OE
SN74CBTLV3125PWR
VOUT1_B_CB_C1
VOUT1_B_CB_C0
18
18
VOUT1_FLD_EXP
GPMC_D0
13
18
EXP_EVM_3V3
D
1B
3
EXP_UART0_TXD
6
EXP_UART0_RXD
8
EXP_UART0_RTSn
11
EXP_UART0_CTSn
EXP_EVM_5V0
GPMC_D2
GPMC_D7
GPMC_D9
GPMC_D12
GPMC_D11
GPMC_D10
GPMC_CLK
GPMC_D15
GPMC_D2
13
GPMC_D5
13
GPMC_D7
GPMC_D9
13
13
J31
7
GPMC_D12
GPMC_D11
13
13
13
13
GPMC_A20
GPMC_A18
GPMC_D10
GPMC_CLK
13
13
13
13
GPMC_A19
GPMC_A17
GPMC_D15
13
15
18
AUXOSC_MXI
27
UART2_CTSn_EXP
SPI0_nCS0
SPI0_SCLK
GPMC_A21
SPI0_nCS1
MMC0_CLK
MMC0_CMD
MCA3_ACLKX
SPI0_nCS0
SPI0_SCLK
20,21
20,21
GPMC_A21
SPI0_nCS1
13
20
MMC0_CLK
MMC0_CMD
MMC2_DAT5
VOUT1_G_Y_YC2
7
7
MCA3_AXR2
MCA3_AXR3
7
MCA3_AFSX
18
13
GPMC_A16
18
UART2_RTSn_EXP
11,12,26,27,9
RSTOUTn
21
21
15
15
EXP_UART0_RXD
121
123
125
127
IO_EXP2_GP1
IO_EXP2_GP2
7
7
MCA4_AXR1
MCA4_AFSX
15
MMC2_DAT4
MCA3_ACLKX
GPMC_A20
GPMC_A18
GPMC_A19
GPMC_A17
MMC2_DAT5
VOUT1_G_Y_YC2
MCA3_AXR2
MCA3_AXR3
MCA3_AFSX
EXP_UART0_CTSn
EXP_UART0_RTSn
GPMC_A16
UART2_RTSn_EXP
RSTOUTn
MLB_DAT
MLB_SIG
MCA4_AXR1
MCA4_AFSX
MMC2_DAT4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
VOUT1_R_CR3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
EXP_UART0_TXD
MCA3_AXR0
VOUT1_R_CR2
MCA3_AXR1
MMC2_DAT7
MMC2_DAT6
VOUT0_FLD_EXP
MLB_CLK
R545
0E
MCA4_ACLKX
IP_EVM_12V
EXP_EVM_5V0
C434
C
18
15
15
VOUT0_FLD_EXP
18
IO_EXP2_GP3
21
CLK32OUT
27,33
MCA4_ACLKX
7
21
7
27
27
NOTE:
MLB SIGNALS ARE NOT AVAILABLE
IN DM385.TWO MLB SIGNALS WHICH
ARE USED AS GPIOs ON THE CATLOG BOARD
ARE GIVEN FROM IO EXPANDER-2
10uF C432
0.1uF
100uF C433
C436
10uF C438
0.1uF
100uF C437
C159
10uF C153
0.1uF
100uF C157
7
MMC2_DAT7
MMC2_DAT6
GPIO_VS_1
EXP_EVM_3V3
CONNECTOR : J29 ON DM385 Board
18
7
VOUT1_R_CR2
MCA3_AXR1
MCA4_AXR0
EXP_WARM_RESET
QSH-030-01-L-D-A
App.BOARD
MCA3_AXR0
APP_PORz
CON_PMC_60X2_F
B
VOUT1_R_CR3
MCA4_AXR0
61
62
63
64
122
124
126
128
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
VCC
19,28,29,8
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
PM_I2C_SCL
14
U61
19,28,29,8
7
D
B
CONNECTOR : J31 ON DM385 Board
MATING CONNECTOR
App.BOARD
MATING CONNECTOR
VIDEO CAMERA
J4
VIDEO CAMERA
J5
VIDEO CONFERENCE
J4
VIDEO CONFERENCE
J5
VIDEO SECURITY
J13
VIDEO SECURITY
J15
I/O EXPANDER
J4
I/O EXPANDER
J5
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
GPMC B-B CONN
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
86
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
14
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-14. DM385 MMC0, MMC1, and MMC2
5
4
3
2
1
C277
C278
0.1uF
0.1uF
VMMC
VMMC
VMMC
TP105
O/P CURRENT: 2A
C689
VMMC_3V3
C691
NC
C690
EN
R435
4.7uF
6
MIC94062YC6
1
0.1uF
MMC1_POW
VOUT
GND2
3
VIN
GND1
4
5
0.1uF
20
D
U70
2
R407
51K
D
0.01E_1%
DVDD_SD
R434
R568
R570
R571
R574
R456
R460
R461
R454
R455
10KDNI
10KDNI
10KDNI
10KDNI
10K
10K
10K
10K
10K
TP82
TP78
TP81
TP77
0.01E_1%
C309
10uF
C316
0.1uF
J22
MMC1_DAT3
MMC1_CMD
U55M
14
MMC2_CLK
14
14
14
14
14
14
14
14
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
MMC2_DAT4
MMC2_DAT5
MMC2_DAT6
MMC2_DAT7
MMC2_CLKR314 22E
AC6
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
MMC2_DAT4
MMC2_DAT5
MMC2_DAT6
MMC2_DAT7
AC4
AC5
AC8
AD1
AD2
AE1
AE2
AE3
SD1_CLK
SD1_CMD/GP0[0]
SD0_DAT[0]/SD1_DAT[4]/GP0[3]
SD0_DAT[1]_SDIRQn/SD1_DAT[5]/GP0[4]
SD0_DAT[2]_SDRWn/SD1_DAT[6]/GP0[5]
SD0_DAT[3]/SD1_DAT[7]/GP0[6]
SD1_DAT[0]
SD1_DAT[1]_SDIRQn
SD1_DAT[2]_SDRWn
SD1_DAT[3]
W30
Y29
W31
AA30
U29
Y27
0E MMC1_CLK
R462
MMC1_CMD
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
TP108
TP111
TP110
TP109
SD2_SCLK/GP1[15]
16
17
18
19
20
21
22
23
24
25
26
27
28
EVM_3V3
SD2_DAT[0]/GPMC_A[4]/GP1[14]
SD2_DAT[1]_SDIRQn/GPMC_A[3]/GP1[13]
SD2_DAT[2]_SDRWn/GPMC_A[2]/GP2[6]
SD2_DAT[3]/GPMC_A[1]/GP2[5]
SD2_DAT[4]/GPMC_A[27]/GPMC_A[23]/GPMC_CS[7]n/EDMA_EVT0/TIM7_IO/GP1[22]
SD2_DAT[5]/GPMC_A[26]/GPMC_A[22]/TIM6_IO/GP1[21]
SD2_DAT[6]/GPMC_A[25]/GPMC_A[21]/UART2_TXD/GP1[20]
SD2_DAT[7]/GPMC_A[24]/GPMC_A[20]/UART2_RXD/GP1[19]
TMS320DM385
20
20
R458
C
AA28
AA26
Y31
Y30
R459
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
SD0_CLK/GP0[1]
SD0_CMD/SD1_CMD/GP0[2]
10K
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC1_CLK
MMC0,1,2
AB30
AA29
10K
14
14
14
14
MMC0_CLK R535 22E
MMC0_CMD
R573
R572
R569
R567
MMC0_CLK
MMC0_CMD
100K
100K
100K
100K
14
14
1
2
3
4
5
6
7
8
9
10
11
12
13
MMC1_SD_WP
MMC1_SD_CD
MMC1_SD_WP
MMC1_SD_CD
14
15
#1_MMC+/MMCM/RSMMC/MMC/SD
#2_MMC+/MMCM/RSMMC/MMC/SD
#3_MMC+/MMCM/RSMMC/MMC/SD
#4_MMC+/MMCM/RSMMC/MMC/SD
#5_MMC+/MMCM/RSMMC/MMC/SD
#6_MMC+/MMCM/RSMMC/MMC/SD
#7_MMC+/MMCM/RSMMC/MMC/SD
#8_MMC+/MMCM/SD
#9_MMC+/MMCM/SD
#10_MMC+/MMCM
#11_MMC+/MMCM
#12_MMC+/MMCM
#13_MMC+/MMCM
C
#1_miniSD
#2_miniSD
#3_miniSD
#4_miniSD
#5_miniSD
#6_miniSD
#7_miniSD
#8_miniSD
#9_miniSD
#10_miniSD
#11_miniSD
GND1
GND2
SD_WP
CD
CON_SDCARD_28_MHC-W21-601
SD/MMC
IO1
IO2
Check arrangement to be done
CSI INTERFACE
19
19
CSI2_DX0
CSI2_DY0
AB2
AC2
19
19
CSI2_DX1
CSI2_DY1
AA1
AB1
19
19
CSI2_DX2
CSI2_DY2
AA2
Y2
19
19
CSI2_DX3
CSI2_DY3
W2
W1
19
19
CSI2_DX4
CSI2_DY4
V1
V2
SERDES_CLKP
SERDES_CLKN
CSI2_DX[1]
CSI2_DY[1]
IFORCE
VSENSE
CSI2_DX[3]
CSI2_DY[3]
CSI2_DX[4]
CSI2_DY[4]
IO4
4
MMC1_DAT3
MMC1_DAT2
1
5
MMC1_DAT0
MMC1_DAT1
2
TPD4E001DBVR
IO1
IO2
6
IO3
IO4
4
MMC1_SD_CD
5
MMC1_SD_WP
B
TPD4E001DBVR
R276 DNI 100E
CSI2_DX[0]
CSI2_DY[0]
CSI2_DX[2]
CSI2_DY[2]
6
3
U55B
IO3
VCC
2
3
1
MMC1_CMD
VCC
MMC1_CLK
GND
B
VMMC_3V3
U100
GND
VMMC_3V3
U99
ATESTV
ATESTV1
BTMONITOR_IPADp
BTMONITOR_IPADn
VBBNW_ARM
VBBNW_IVA
C219 270pF SERDES_IN_REFP
SERDES_IN_REFN
C218 270pF
H30
H31
SERDES_IN_REFP
SERDES_IN_REFN
26
26
H25
H29
H27
AD8
AJ24
AH24
J19
W23
C468 1uF
C525 1uF
TMS320DM385
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
DM385_MMC0/1/2_CSI2
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
15
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
87
Appendix A
www.ti.com
Figure A-15. DM385 DDR0 Terminations
5
4
3
2
1
DDR0 TERMINATIONS
U55E
D
VDDQ_1V5
DDR0 INTERFACE
17
17
17
17
17
17
17
17
17
17
17
B
DDR0_D16
DDR0_D17
DDR0_D18
DDR0_D19
DDR0_D20
DDR0_D21
DDR0_D22
DDR0_D23
TDDR0_DM3
DDR0_DQS3
DDR0_DQSN3
DDR0_D24
DDR0_D25
DDR0_D26
DDR0_D27
DDR0_D28
DDR0_D29
DDR0_D30
DDR0_D31
16,17,39
16,17,39
16,17,39
AK12
AL15
AK15
DDR0_D8
DDR0_D9
DDR0_D10
DDR0_D11
DDR0_D12
DDR0_D13
DDR0_D14
DDR0_D15
AJ12
AG12
AD12
AB12
AK13
AC13
AL14
AK14
TDDR0_DM2
R411 22E
DDR0_DQS2
DDR0_DQSN2
AJ15
AL17
AK17
DDR0_D16
DDR0_D17
DDR0_D18
DDR0_D19
DDR0_D20
DDR0_D21
DDR0_D22
DDR0_D23
AH15
AF15
AD15
AK16
AJ16
AG16
AD16
AC16
TDDR0_DM3
R408 22E
DDR0_DQS3
DDR0_DQSN3
AK18
AL20
AK20
DDR0_D24
DDR0_D25
DDR0_D26
DDR0_D27
DDR0_D28
DDR0_D29
DDR0_D30
DDR0_D31
AK19
AJ19
AH19
AF19
AD19
AC19
AJ20
AG20
DDR0_CLK0
DDR0_CLK0N
DDR0_CKE
DDR0_CLK0
DDR0_CLK0N
DDR0_CKE
AL27
AK27
AD20
DDR[0]_A[0]
DDR[0]_A[1]
DDR[0]_A[2]
DDR[0]_A[3]
DDR[0]_A[4]
DDR[0]_A[5]
DDR[0]_A[6]
DDR[0]_A[7]
DDR[0]_A[8]
DDR[0]_A[9]
DDR[0]_A[10]
DDR[0]_A[11]
DDR[0]_A[12]
DDR[0]_A[13]
DDR[0]_A[14]
DDR[0]_A[15]
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DDR[0]_DQS[1]n
DDR[0]_D[8]
DDR[0]_D[9]
DDR[0]_D[10]
DDR[0]_D[11]
DDR[0]_D[12]
DDR[0]_D[13]
DDR[0]_D[14]
DDR[0]_D[15]
DDR[0]_CS[0]n
DDR[0]_DQM[2]
DDR[0]_DQS[2]
DDR[0]_DQS[2]n
DDR[0]_RASn
DDR[0]_CASn
DDR[0]_D[16]
DDR[0]_D[17]
DDR[0]_D[18]
DDR[0]_D[19]
DDR[0]_D[20]
DDR[0]_D[21]
DDR[0]_D[22]
DDR[0]_D[23]
DDR[0]_ODT[0]
DDR[0]_ODT[1]
DDR[0]_WEn
DDR[0]_RST
VREFSSTL_DDR[0]
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]n
DDR[0]_VTP
DDR0_BA0
DDR0_BA1
DDR0_BA2
DDR0_BA0
DDR0_BA1
DDR0_BA2
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
AL24
AC22
AJ23
AJ27
AK28
AH27
AK30
AG23
AL29
AK29
AD23
AK24
AH23
AK23
AL23
AK22
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
0E
R388
16,17,39
16,17,39
16,17,39
16,17,39
DDR0_A14
R441
49.9E_1%
R443
49.9E_1%
DDR0_A7
DDR0_A6
DDR0_A1
DDR0_A9
RA56 51E
8
1
7
2
6
3
5
4
DDR0_BA0
DDR0_A3
DDR0_BA1
DDR0_A12
RA55 51E
8
1
7
2
6
3
5
4
DDR0_A4
DDR0_A0
DDR0_A5
DDR0_A2
RA41 51E
8
1
7
2
6
3
5
4
DDR0_WEN
DDR0_A10
DDR0_CSN0
DDR0_BA2
RA40 51E
8
1
7
2
6
3
5
4
DDR0_A14
DDR0_A13
DDR0_A8
DDR0_A11
RA42 51E
8
1
7
2
6
3
5
4
DDR0_CKE
DDR0_CASN
DDR0_RASN
DDR0_ODT0
RA54 51E
8
1
7
2
6
3
5
4
16,17,39
TP99
DDR[0]_CS[1]n HAS BEEN CHANGED TO DDR[0]_A[15]
AB21
DDR0_CLK0
DDR0_CLK0N
DDR0_CSN0
AJ25
AK25
DDR0_RASN
DDR0_CASN
AL21
AK21
DDR0_ODT0
AL26
DDR0_WEN
AA20
DDR0_RSTn
DDR0_CSN0
16,17,39
DDR0_RASN
DDR0_CASN
16,17,39 VDDQ_1V5
16,17,39
DDR0_ODT0
TP98
DDR0_WEN
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
VREF
R480
10K
16,17,39
TP112
DDR0_RSTn
17
16,17,39
16,17,39
16,17,39
16,17,39
AL18
AL30
CDDR0_VTP
R549
16,17,39
16,17,39
16,17,39
16,17,39
49.9E_1%
C563
10uF
DDR[0]_D[24]
DDR[0]_D[25]
DDR[0]_D[26]
DDR[0]_D[27]
DDR[0]_D[28]
DDR[0]_D[29]
DDR[0]_D[30]
DDR[0]_D[31]
D
C298 0.1uF
C655 0.1uF
C317 0.1uF
C662 0.1uF
C326 0.1uF
C681 0.1uF
C
C353 0.1uF
C312 0.1uF
C641 0.1uF
C677 0.1uF
VREF_VTT
C345 0.1uF
VDDQ_1V5
C682 0.1uF
C360 0.1uF
B
VREF_VTT
VDDQ_1V5
TPS_VREF
DDR[0]_CLK
DDR[0]_CLKn
R219
0E_1%
DDR[0]_CKE
TMS320DM385
0.1uF C575
17
17
17
17
17
17
17
17
TDDR0_DM2
DDR0_DQS2
DDR0_DQSN2
TDDR0_DM1
R412 22E
DDR0_DQS1
DDR0_DQSN1
DDR[0]_D[0]
DDR[0]_D[1]
DDR[0]_D[2]
DDR[0]_D[3]
DDR[0]_D[4]
DDR[0]_D[5]
DDR[0]_D[6]
DDR[0]_D[7]
AK26
AF23
AH25
0.1uF C271
17
17
17
DDR0_D8
DDR0_D9
DDR0_D10
DDR0_D11
DDR0_D12
DDR0_D13
DDR0_D14
DDR0_D15
AL9
AK9
AK10
AJ11
AH11
AD9
AF11
AL12
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
0.1uF C584
17
17
17
17
17
17
17
17
DDR0_D0
DDR0_D1
DDR0_D2
DDR0_D3
DDR0_D4
DDR0_D5
DDR0_D6
DDR0_D7
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DDR[0]_DQS[0]n
0.1uF C620
TDDR0_DM1
DDR0_DQS1
DDR0_DQSN1
AL8
AL11
AK11
0.1uF C299
17
17
17
DDR0_D0
DDR0_D1
DDR0_D2
DDR0_D3
DDR0_D4
DDR0_D5
DDR0_D6
DDR0_D7
R410 22E
0.1uF C665
17
17
17
17
17
17
17
17
C
TDDR0_DM0
DDR0_DQS0
DDR0_DQSN0
TDDR0_DM0
DDR0_DQS0
DDR0_DQSN0
0.1uF C590
17
17
17
Decaps added to provide
avenues for return currents
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
DM385_DDRO N TERMINATIONS
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
88
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
Schematics
2
Rev
B
Sheet
16
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-16. DDR0-0, DDR0-1, DDR0-2, and DDR0-3
2
C651
C624
C680
C656
C640
C675
C636
C630
C601
C610
C650
C647
C625
C631
C611
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C661
0.1uF
0.1uF
C673
0.1uF
C607
C634
0.1uF
0.1uF
C664
0.1uF
C660
C657
0.1uF
0.1uF
C614
0.1uF
C600
C639
0.1uF
0.1uF
C608
0.1uF
0.1uF
C678
0.1uF
B9
C1
E2
E9
C602
C613
0.1uF
C668
0.1uF
C633
C646
0.1uF
0.1uF
C654
0.1uF
0.1uF
C637
0.1uF
C638
C604
0.1uF
C667
C605
0.1uF
0.1uF
C623
0.1uF
0.1uF
C669
0.1uF
C626
C599
0.1uF
0.1uF
C663
0.1uF
C672
C587
0.1uF
0.1uF
C649
0.1uF
C622
C645
0.1uF
0.1uF
C628
C588
A3
F1
F9
H1
H9
J7
+
+
C282
VDDQ_1V5
E1
J8
+
+
VREF
VD_VREF
R256
0E_1%
VREF
VREF
C311
VDDQ_1V5
0.1uF
C314
0.1uF
C315
0.1uF
C313
0.1uF
C365
0.1uF
0.1uF
DDR0-1
C369
C367
MT41J256M8HX-125
MT41J256M8HX-125
DDR0-0
D
16
VREF
C371
BA0
BA1
BA2
TDDR0_DM1
0.1uF
J2
K8
J3
NC1
NC2
NC3
NC4
NC5
NC6
TDDR0_DM1
A7
0.1uF
DDR0_BA0
DDR0_BA1
DDR0_BA2
VREFDQ
VREFCA
B7
0.1uF
A3
F1
F9
H1
H9
J7
DM/TDQS
NF/TDQS#
VDDQ_1V5
0.1uF
NC1
NC2
NC3
NC4
NC5
NC6
E1
J8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
VDDQ_1V5
C280
VREFDQ
VREFCA
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
TDDR0_DQS1
TDDR0_DQSN1
VDDQ_1V5
VDDQ_1V5
33uF_6.3V
VREF
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
C3
D3
VDDQ_1V5
33uF_6.3V
16
DQS
DQS#
MEM01_D8
MEM01_D9
MEM01_D10
MEM01_D11
MEM01_D12
MEM01_D13
MEM01_D14
MEM01_D15
B3
C7
C2
C8
E3
E8
D2
E7
C275
TDDR0_DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
33uF_6.3V
TDDR0_DM0
A7
VDDQ1
VDDQ2
VDDQ3
VDDQ4
B7
1
VDDQ_1V5
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
TDDR0_DQS0
TDDR0_DQSN0
ODT
ZQ
RESET#
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
B2
B8
C9
D1
D9
BA0
BA1
BA2
DM/TDQS
NF/TDQS#
C3
D3
G1
H8
DDR0_RSTn N2
DDR0_CKE G9
DDR0_CLK0 F7
DDR0_CLK0N G7
DDR0_CSN0 H2
DDR0_RASn F3
DDR0_CASn G3
DDR0_WEn H3
240E R468
VDDQ1
VDDQ2
VDDQ3
VDDQ4
J2
K8
J3
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
DDR0_BA0
DDR0_BA1
DDR0_BA2
DQS
DQS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
MEM00_D0
MEM00_D1
MEM00_D2
MEM00_D3
MEM00_D4
MEM00_D5
MEM00_D6
MEM00_D7
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
DDR0_BA0
DDR0_BA1
DDR0_BA2
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
B3
C7
C2
C8
E3
E8
D2
E7
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
16,17,39
16,17,39
16,17,39
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
DDR0_ODT0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
ODT
ZQ
RESET#
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
DDR0_RSTn
DDR0_CKE
DDR0_CLK0
DDR0_CLK0N
DDR0_CE0n
DDR0_RASn
DDR0_CASn
DDR0_WEn
G1
H8
N2
G9
F7
G7
H2
F3
G3
H3
B2
B8
C9
D1
D9
16
DDR0_RSTn
16,17,39
DDR0_CKE
16,17,39
DDR0_CLK0
16,17,39
DDR0_CLK0N
16,17,39
DDR0_CSN0
16,17,39
DDR0_RASn
16,17,39
DDR0_CASn
16,17,39
DDR0_WEn
DDR0_ODT0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
240E R466
D
DDR0_ODT0
B9
C1
E2
E9
A2
A9
D7
K1
K9
M1
M9
G2
G8
U80
U78
16,17,39
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
A2
A9
D7
K1
K9
M1
M9
G2
G8
VDDQ_1V5
0.1uF
3
C281
4
VDDQ_1V5
33uF_6.3V
5
C
C
VDDQ_1V5
B9
C1
E2
E9
A3
F1
F9
H1
H9
J7
C291
C295
C612
C340
C589
C304
C635
C364
C618
C594
C329
C674
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDDQ_1V5
C330
C354
C586
C338
C307
C356
C644
C671
C370
C627
C659
C595
C328
C372
C616
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
B
0.1uF
NC1
NC2
NC3
NC4
NC5
NC6
E1
J8
0.1uF
VREF
VREFDQ
VREFCA
C648
16
0.1uF
MT41J256M8HX-125
VDDQ_1V5
TDDR0_DM3
A7
C670
A2
A9
D7
K1
K9
M1
M9
G2
G8
BA0
BA1
BA2
TDDR0_DM3
0.1uF
J2
K8
J3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
DDR0_BA0
DDR0_BA1
DDR0_BA2
NF/TDQS#
TDDR0_DQS3
TDDR0_DQSN3
C3
D3
B7
0.1uF
DDR0_BA0
DDR0_BA1
DDR0_BA2
DM/TDQS
C642
16,17,39
16,17,39
16,17,39
DQS
DQS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
C337
A3
F1
F9
H1
H9
J7
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
MEM03_D24
MEM03_D25
MEM03_D26
MEM03_D27
MEM03_D28
MEM03_D29
MEM03_D30
MEM03_D31
0.1uF
E1
J8
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
B3
C7
C2
C8
E3
E8
D2
E7
0.1uF
NC1
NC2
NC3
NC4
NC5
NC6
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VREF
VREFDQ
VREFCA
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
C308
16
ODT
ZQ
RESET#
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
0.1uF
240E R467
TDDR0_DM2
A7
DDR0_RSTn
DDR0_CKE
DDR0_CLK0
DDR0_CLK0N
DDR0_CE0n
DDR0_RASn
DDR0_CASn
DDR0_WEn
C585
TDDR0_DM2
DDR0_CKE
DDR0_CLK0
DDR0_CLK0N
DDR0_CSN0
DDR0_RASn
DDR0_CASn
DDR0_WEn
0.1uF
BA0
BA1
BA2
NF/TDQS#
TDDR0_DQS2
TDDR0_DQSN2
C3
D3
B7
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
G1
H8
N2
G9
F7
G7
H2
F3
G3
H3
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
J2
K8
J3
DM/TDQS
DDR0_ODT0
DDR0_ODT0
B2
B8
C9
D1
D9
DDR0_BA0
DDR0_BA1
DDR0_BA2
DQS
DQS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
16,17,39
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
DDR0_BA0
DDR0_BA1
DDR0_BA2
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
MEM02_D16
MEM02_D17
MEM02_D18
MEM02_D19
MEM02_D20
MEM02_D21
MEM02_D22
MEM02_D23
B3
C7
C2
C8
E3
E8
D2
E7
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
16,17,39
16,17,39
16,17,39
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
U79
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
ODT
ZQ
RESET#
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
G1
H8
N2
G9
F7
G7
H2
F3
G3
H3
B2
B8
C9
D1
D9
DDR0_RSTn
DDR0_CKE
DDR0_CKE
DDR0_CLK0
DDR0_CLK0
DDR0_CLK0N
DDR0_CLK0N
DDR0_CE0n
DDR0_CSN0
DDR0_RASn
DDR0_RASn
DDR0_CASn
DDR0_CASn
DDR0_WEn
DDR0_WEn
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
16,17,39
B
DDR0_ODT0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
R469
240E
DDR0_ODT0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
U81
16,17,39
B9
C1
E2
E9
A2
A9
D7
K1
K9
M1
M9
G2
G8
VDDQ_1V5
MT41J256M8HX-125
VDDQ_1V5
DDR0-2
A
16
16
16
16
DDR0_DQSN1
DDR0_DQS1
DDR0_DQSN0
DDR0_DQS0
DDR0_DQSN1
DDR0_DQS1
DDR0_DQSN0
DDR0_DQS0
R420
R419
R416
R415
0E
0E
0E
0E
TDDR0_DQSN1
TDDR0_DQS1
TDDR0_DQSN0
TDDR0_DQS0
NATURE OF CHANGE
REV NO.
DDR0_DQSN3
DDR0_DQS3
DDR0_DQSN2
DDR0_DQS2
R418
R417
R422
R421
0E
0E
0E
0E
TDDR0_DQSN3
TDDR0_DQS3
TDDR0_DQSN2
TDDR0_DQS2
APPROVED BY
DATE
C603
C306
C294
C597
C293
C302
C598
C629
C332
C676
C339
C632
C355
C596
C619
C592
C292
C357
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C593
C621
C679
C301
C609
C615
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
MEM02_D20
MEM02_D22
MEM02_D16
MEM02_D18
0.1uF
RA52 0E
8
1
7
2
6
3
5
4
C658
DDR0_D20
DDR0_D22
DDR0_D16
DDR0_D18
0.1uF
MEM03_D27
MEM03_D25
MEM03_D29
MEM03_D31
C305
DDR0_D20
DDR0_D22
DDR0_D16
DDR0_D18
1
2
3
4
0.1uF
16
16
16
16
8
7
6
5
C606
DDR0_DQSN3
DDR0_DQS3
DDR0_DQSN2
DDR0_DQS2
MEM02_D19
MEM02_D23
MEM02_D17
MEM02_D21
1
2
3
4
VDDQ_1V5
0E
DDR0_D27
DDR0_D25
DDR0_D29
DDR0_D31
0.1uF
16
16
16
16
DDR0_D19
DDR0_D23
DDR0_D17
DDR0_D21
DDR0_D27
DDR0_D25
DDR0_D29
DDR0_D31
C617
DDR0_D19
DDR0_D23
DDR0_D17
DDR0_D21
RA49
16
16
16
16
0.1uF
16
16
16
16
0E
C366
MEM00_D5
MEM00_D3
MEM00_D1
MEM00_D7
RA51
8
7
6
5
MEM03_D28
MEM03_D30
MEM03_D24
MEM03_D26
0.1uF
0E
1
2
3
4
RA50 0E
8
1
7
2
6
3
5
4
C591
RA53
8
7
6
5
DDR0_D28
DDR0_D30
DDR0_D24
DDR0_D26
C368
DDR0_D5
DDR0_D3
DDR0_D1
DDR0_D7
DDR0_D28
DDR0_D30
DDR0_D24
DDR0_D26
0.1uF
DDR0_D5
DDR0_D3
DDR0_D1
DDR0_D7
16
16
16
16
0.1uF
16
16
16
16
MEM01_D11
MEM01_D9
MEM01_D13
MEM01_D15
C303
MEM01_D14
MEM01_D12
MEM01_D8
MEM01_D10
1
2
3
4
0E
1
2
3
4
C331
0E
RA47
8
7
6
5
0.1uF
DDR0_D11
DDR0_D9
DDR0_D13
DDR0_D15
0.1uF
DDR0_D11
DDR0_D9
DDR0_D13
DDR0_D15
C666
16
16
16
16
C643
RA48
8
7
6
5
MEM00_D6
MEM00_D4
MEM00_D2
MEM00_D0
0.1uF
DDR0_D14
DDR0_D12
DDR0_D8
DDR0_D10
RA46 0E
8
1
7
2
6
3
5
4
0.1uF
DDR0_D14
DDR0_D12
DDR0_D8
DDR0_D10
DDR0_D6
DDR0_D4
DDR0_D2
DDR0_D0
C652
16
16
16
16
DDR0_D6
DDR0_D4
DDR0_D2
DDR0_D0
0.1uF
16
16
16
16
DDR0-3
A
Mistral Solutions [P] Ltd.
Title
DDR0
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
17
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
89
Appendix A
www.ti.com
Figure A-17. DM385 VIN0, VOUT0, and VOUT1
5
4
19
19
3
2
1
VIN0_VSYNC_EXP
VIN0_HSYNC_EXP
U55G
19
19
VIN0_CLK0
R511
22E
VIN0_CLK1
R509
22E
VIN0_VSYNC R504 DNI 0E
VIN0_HSYNC R506 DNI 0E
VIN0_CLK0
VIN0_CLK1
CPU_VIN0_CLK0
CPU_VIN0_CLK1
C9
H12
J13
C12
VIN0,VOUT0,VOUT1
VIN[0]A_CLK/GP2[2]
VIN[0]B_CLK/CLKOUT0/GP1[9]
VIN[0]A_FLD/VIN[0]B_VSYNC/I2C[2]_SCL/GP2[1]
VIN[0]A_DE/VIN[0]B_HSYNC/I2C[2]_SDA/GP2[0]
VOUT[1]_CLK/EMAC[1]_MTCLK/VIN[1]A_HSYNC/GP2[28]
VOUT[1]_G_Y_YC[0]/CAM_D[2]/GPMC_A[6]/GP0[23]
VOUT[1]_G_Y_YC[1]/CAM_D[3]/GPMC_A[5]/GP0[22]
VOUT[1]_G_Y_YC[2]/GPMC_A[13]/VIN[1]A_D[
VOUT[1]_G_Y_YC[3]/EMAC[1]_MRXD[6]/VIN[1]A_D[8]/GP3[7]
VOUT[1]_G_Y_YC[4]/EMAC[1]_MRXD[7]/VIN[1]A_D[9]/GP3[8]
VOUT[1]_G_Y_YC[5]/EMAC[1]_MRXDV/VIN[1]A_D[10]/GP3[9]
VOUT[1]_G_Y_YC[6]/EMAC[1]_GMTCLK/VIN[1]A_D[11]/GP3[10]
VOUT[1]_G_Y_YC[7]/EMAC[1]_MTXD[0]/VIN[1]A_D[12]/GP3[11]
VOUT[1]_G_Y_YC[8]/EMAC[1]_MTXD[1]/VIN[1]A_D[13]/GP3[12]
VOUT[1]_G_Y_YC[9]/EMAC[1]_MTXD[2]/VIN[1]A_D[14]/GP3[13]
D
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
24
EMU2
24
19
19
19
19
19
19
19
19
EMU3
SW_VOUT_C2
R254
RA12 8
7
6
5
RA13 8
7
6
5
CVOUT_C2
0E
1 22E CVOUT_YC9
CVOUT_YC8
2
CVOUT_CR3
3
CVOUT_CR4
4
1 22E CVOUT_CR5
CVOUT_CR8
2
CVOUT_CR9
3
CVOUT_CR7
4
R248
8
7
6
5
RA8 8
7
6
5
VOUT_YC4
VOUT_C4
R522
RA11 8
7
6
5
RA10 8
7
6
5
VOUT0_FLD
R510
22E
VOUT0_HSYNC
VOUT0_VSYNC
VOUT0_CLK
R512
R507
R508
22E
22E
22E
VOUT_YC9
VOUT_YC8
VOUT_CR3
VOUT_CR4
VOUT_CR5
VOUT_CR8
VOUT_CR9
VOUT_CR7
SW_VOUT_YC2
19
19
19
VOUT0_AVID
VOUT_C5
VOUT_CR6
VOUT_C7
VOUT_C8
VOUT_C9
VOUT_YC3
VOUT_C3
RA9
CVOUT_C2
CVOUT_C3
CVOUT_C4
CVOUT_C5
CVOUT_C6
CVOUT_C7
CVOUT_C8
CVOUT_C9
F24
D21
J23
H23
J24
E24
D24
C24
CVOUT_YC2
0E
1 22E CVOUT0_AVID
CVOUT_C5
2
CVOUT_CR6
3
CVOUT_C7
4
1 22E CVOUT_C8
CVOUT_C9
2
CVOUT_YC3
3
CVOUT_C3
4
CVOUT_YC2
CVOUT_YC3
CVOUT_YC4
CVOUT_YC5
CVOUT_YC6
CVOUT_YC7
CVOUT_YC8
CVOUT_YC9
C25
C26
E26
B26
A26
B25
B27
A27
CVOUT_CR2
0E
1 22E CVOUT_C6
CVOUT_YC7
2
CVOUT_YC5
3
CVOUT_YC6
4
1 22E
2
CVOUT_YC4
3
CVOUT_C4
4
CVOUT_CR2
CVOUT_CR3
CVOUT_CR4
CVOUT_CR5
CVOUT_CR6
CVOUT_CR7
CVOUT_CR8
CVOUT_CR9
C28
B28
B29
A29
C30
B30
A30
B31
CVOUT0_FLD
CVOUT0_AVID
CVOUT0_FLD
C20
B3
CVOUT0_HSYNC
CVOUT0_VSYNC
CVOUT0_CLK
CVOUT0_HSYNC
CVOUT0_VSYNC
CVOUT0_CLK
F21
E20
K22
VIN[0]A_D[0]/GP1[11]
VIN[0]A_D[1]/GP1[12]
VIN[0]A_D[2]/GP2[7]
VIN[0]A_D[3]/GP2[8]
VIN[0]A_D[4]/GP2[9]
VIN[0]A_D[5]/GP2[10]
VIN[0]A_D[6]/GP2[11]
VIN[0]A_D[7]/GP2[12]
VIN[0]A_D[8]_BD[0]/GP2[13]
VIN[0]A_D[9]_BD[1]/GP2[14]
VIN[0]A_D[10]_BD[2]/GP2[15]
VIN[0]A_D[11]_BD[3]/CAM_WEn/GP2[16]
VIN[0]A_D[12]_BD[4]/CLKOUT1/GP2[17]
VIN[0]A_D[13]_BD[5]/CAM_RESET/GP2[18]
VIN[0]A_D[14]_BD[6]/CAM_STROBE/GP2[19]
VIN[0]A_D[15]_BD[7]/CAM_SHUTTER/GP2[20]
VIN[0]A_D[16]/CAM_D[8]/I2C[2]_SCL/GP0[10]
VIN[0]A_D[17]/CAM_D[9]/EMAC[1]_RMRXER/GP0[11]
VIN[0]A_D[18]/CAM_D[10]/EMAC[1]_RMRXD[1]/I2C[3]_SCL/GP0[12]
VIN[0]A_D[19]/CAM_D[11]/EMAC[1]_RMRXD[0]/I2C[3]_SDA/GP0[13]
VIN[0]A_D[20]/CAM_D[12]/EMAC[1]_RMCRSDV/SPI[3]_SCS[0]n/GP0[14]
VIN[0]A_D[21]/CAM_D[13]/EMAC[1]_RMTXD[0]/SPI[3]_SCLK/GP0[15]
VIN[0]A_D[22]/CAM_D[14]/EMAC[1]_RMTXD[1]/SPI[3]_D[1]/GP0[16]
VIN[0]A_D[23]/CAM_D[15]/EMAC[1]_RMTXEN/SPI[3]_D[0]/GP0[17]
VOUT[1]_R_CR[0]/CAM_D[0]/GPMC_A[8]/GP0[25]
VOUT[1]_R_CR[1]/CAM_D[1]/GPMC_A[7]/GP0[24]
VOUT[1]_R_CR[2]/GPMC_A[15]/VIN[1]A_D[23]/HDMI_HPDET/SPI[2]_D[1]/GP3[22]
VOUT[1]_R_CR[3]/GPMC_A[14]/VIN[1]A_Ds22]/HDMI_SDA/SPI[2]_SCLK/I2C[2]_SDA/GP3[21]
VOUT[1]_R_CR[4]/EMAC[1]_MTXD[3]/VIN[1]A_D[15]/SPI[3]_SCS[1]n/GP3[14]
VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/VIN[1]A_D[16]/SPI[3]_SCLK/GP3[15]
VOUT[1]_R_CR[6]/EMAC[1]_MTXD[5]/VIN[1]A_D[17]/SPI[3]_D[1]/GP3[16]
VOUT[1]_R_CR[7]/EMAC[1]_MTXD[6]/VIN[1]A_D[18]/SPI[3]_D[0]/GP3[17]
VOUT[1]_R_CR[8]/EMAC[1]_MTXD[7]/VIN[1]A_D[19]/GP3[18]
VOUT[1]_R_CR[9]/EMAC[1]_MTXEN/VIN[1]A_D[20]/GP3[19]
VOUT[1]_B_CB_C[0]/CAM_VS/GPMC_A[10]/UART2_TXD/GP0[27]
VOUT[1]_B_CB_C[1]/CAM_HS/GPMC_A[9]/UART2_RXD/GP0[26]
VOUT[1]_B_CB_C[2]/GPMC_A[0]/VIN[1]A_D[7]/HDMI_CEC/SPI[2]_D[0]/GP3[30]
VOUT[1]_B_CB_C[3]/EMAC[1]_MRCLK/VIN[1]A_D[0]/GP3[0]
VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/GP3[1]
VOUT[1]_B_CB_C[5]/EMAC[1]_MRXD[1]/VIN[1]A_D[2]/GP3[2]
VOUT[1]_B_CB_C[6]/EMAC[1]_MRXD[2]/VIN[1]A_D[3]/GP3[3]
VOUT[1]_B_CB_C[7]/EMAC[1]_MRXD[3]/VIN[1]A_D[4]/GP3[4]
VOUT[1]_B_CB_C[8]/EMAC[1]_MRXD[4]/VIN[1]A_D[5]/I2C[3]_SCL/GP3[5]
VOUT[1]_B_CB_C[9]/EMAC[1]_MRXD[5]/VIN[1]A_D[6]/I2C[3]_SDA/GP3[6]
VOUT[0]_B_CB_C[2]/EMU2/GP2[22]
VOUT[0]_B_CB_C[3]/GP2[23]
VOUT[0]_B_CB_C[4]
VOUT[0]_B_CB_C[5]
VOUT[0]_B_CB_C[6]
VOUT[0]_B_CB_C[7]
VOUT[0]_B_CB_C[8]
VOUT[0]_B_CB_C[9]
VOUT[1]_HSYNC/EMAC[1]_MCOL/VIN[1]A_VSYNC/SPI[3]_D[1]/GP2[29]
VOUT[1]_VSYNC/EMAC[1]_MCRS/VIN[1]A_FLD/VIN[1]A_DE/SPI[3]_D[0]/GP2[30]
VOUT[1]_AVID/EMAC[1]_MRXER/VIN[1]A_CLK/TIM6_IO/GP2[31]
VOUT[1]_FLD/CAM_FLD/CAM_WEn/GPMC_A[11]/UART2_CTSn/GP0[28]
VIN[0]A_FLD/CAM_D[5]/GP0[20]
VIN[0]A_VSYNC/GP2[4]
VOUT[0]_G_Y_YC[2]/EMU3/GP2[24]
VOUT[0]_G_Y_YC[3]GP2[25]
VOUT[0]_G_Y_YC[4]
VOUT[0]_G_Y_YC[5]
VOUT[0]_G_Y_YC[6]
VOUT[0]_G_Y_YC[7]
VOUT[0]_G_Y_YC[8]
VOUT[0]_G_Y_YC[9]
VIN[0]A_DE/CAM_D[7]/GP0[18]
VIN[0]B_FLD/CAM_D[4]/GP0[21]
VIN[0]B_DE/CAM_D[6]/GP0[19]
VIN[0]A_HSYNC/GP2[3]
CVOUT1_CLK
CVOUT1_YC0
CVOUT1_YC1
CVOUT1_YC2
CVOUT1_YC3
CVOUT1_YC4
CVOUT1_YC5
CVOUT1_YC6
CVOUT1_YC7
CVOUT1_YC8
CVOUT1_YC9
CVOUT1_YC0
CVOUT1_YC1
CVOUT1_CB1
CVOUT1_CR1
CVOUT1_CR4
CVOUT1_YC2
CVOUT1_CR3
CVOUT1_CB0
CVOUT1_YC8
CVOUT1_YC9
RA7
8
7
6
5
RA21 8
7
6
5
R279
R520
1 22E
2
3
4
1 22E
2
3
4
22E
22E
VOUT1_G_Y_YC0
14
VOUT1_G_Y_YC1
14
VOUT1_B_CB_C1
14
VOUT1_R_CR1
14
VOUT1_R_CR4
8
VOUT1_G_Y_YC2
14
VOUT1_R_CR3
14
VOUT1_B_CB_C0
14
VOUT1_G_Y_YC8
8
VOUT1_G_Y_YC9
8
C2
C1
L6
L4
H2
M11
L12
M10
J2
K2
CVOUT1_CR0
CVOUT1_CR1
CVOUT1_CR2
CVOUT1_CR3
CVOUT1_CR4
CVOUT1_CR5
CVOUT1_CR6
CVOUT1_CR7
CVOUT1_CR8
CVOUT1_CR9
CVOUT1_CB6
CVOUT1_CB7
CVOUT1_CR6
CVOUT1_CB2
CVOUT1_CR0
CVOUT1_CR7
CVOUT1_YC3
CVOUT1_YC4
CVOUT1_CR8
CVOUT1_CR9
RA24 8
7
6
5
RA25 8
7
6
5
R529
R531
1 22E
2
3
4
1 22E
2
3
4
22E
22E
VOUT1_B_CB_C6
8
VOUT1_B_CB_C7
8
VOUT1_R_CR6
8
VOUT1_B_CB_C2
14
VOUT1_R_CR0
14
VOUT1_R_CR7
8
VOUT1_G_Y_YC3
8
VOUT1_G_Y_YC4
8
VOUT1_R_CR8
8
VOUT1_R_CR9
8
H9
D5
M8
F2
F3
G1
G2
H3
G3
H5
CVOUT1_CB0
CVOUT1_CB1
CVOUT1_CB2
CVOUT1_CB3
CVOUT1_CB4
CVOUT1_CB5
CVOUT1_CB6
CVOUT1_CB7
CVOUT1_CB8
CVOUT1_CB9
CVOUT1_CB5
CVOUT1_YC7
CVOUT1_CR5
CVOUT1_CR2
CVOUT1_CB3
CVOUT1_CB4
CVOUT1_YC5
CVOUT1_YC6
CVOUT1_CB8
CVOUT1_CB9
RA20 8
7
6
5
RA19 8
7
6
5
R515
R521
1 22E
2
3
4
1 22E
2
3
4
22E
22E
VOUT1_B_CB_C5
8
VOUT1_G_Y_YC7
8
VOUT1_R_CR5
8
VOUT1_R_CR2
14
VOUT1_B_CB_C3
8
VOUT1_B_CB_C4
8
VOUT1_G_Y_YC5
8
VOUT1_G_Y_YC6
8
VOUT1_B_CB_C8
8
VOUT1_B_CB_C9
8
CVOUT1_HSYNC
CVOUT1_VSYNC
E2
F5
F1
J10
CVOUT1_AVID
CVOUT1_FLD
B4
C13
R503
R505
R287
R524
22E VOUT1_HSYNC
22E VOUT1_VSYNC
R523
R288
22E
22E
VIN0_FLD0
VIN0_VSYNC
8
VOUT1_HSYNC
VOUT1_VSYNC
VOUT1_AVID
VOUT1_FLD
VOUT1_AVID
VOUT1_FLD
D
8
8
8
18
C
19
19
VIN0_DE0
VIN0_FLD1
VIN0_DE1
VIN0_HSYNC
0E
VOUT1_CLK
CVOUT1_AVID
CVOUT1_FLD
VIN0_DE0
VIN0_FLD1
C5
D13
22E
CVOUT1_HSYNC
CVOUT1_VSYNC
VIN0_FLD0
VIN0_VSYNC
0E
B5
A3
R526
19
19
VIN0_DE1
19
VIN0_HSYNC
19
EMU4
19
19
VOUT_YC4
VOUT_C4
VOUT0_FLD
VOUT0_HSYNC
VOUT0_VSYNC
19
VOUT0_CLK
VOUT_C6
VOUT_YC7
VOUT_YC5
VOUT_YC6
R202
R203
R194
VOUT[0]_AVID/VOUT[0]_FLD/SPI[3]_SCLK/TIM7_IO/GP2[21]
VOUT[0]_FLD/CAM_PCLK/GPMC_A[12]/UART2_RTSn/GP2[02]
VOUT[0]_HSYNC
VOUT[0]_VSYNC
VOUT[0]_CLK
U34
TMS320DM385
EVM_3V3
SW_VOUT_C2
2
SW_VOUT_YC2
5
SW_VOUT_CR2
9
EVM_3V3
C170 0.1uF
12
1
4
10
13
R181 DNI 10K
14
U45
2
5
9
12
0E
0E
0E
Y0
A
Y1
Y2
B
Y3
4
VOUT_FLD_nOE
CAM_PCLK_nOE
UART2/I2C2_nOE
7
6
UART2/I2C2_nOE
5
CAM_PCLK_nOE
3
VOUT_FLD_nOE
1
4
10
13
1A
2A
3A
4A
EVM_3V3
1Y
2Y
3Y
4Y
1OE
2OE
3OE
4OE
SN74ALVC125PW
3
6
VOUT0_FLD_EXP
VOUT0_FLD
18
8
11
UART2_RTSn_EXP
14
R176
10K
EVM_3V3
EVM_3V3
14
LOW
LOW
NOT USED
LOW
HIGH
UART2/I2C2_nOE
HIGH
LOW
CAM_PCLK
HIGH
HIGH
VOUT0/1_FLD(default)
VOUT1_FLD R231
0E
VOUT_FLD_nOE
UART2/I2C2_nOE
2
5
9
12
1
4
10
13
1A
2A
3A
4A
1OE
2OE
3OE
4OE
A
SN74ALVC125PW
20,21,24
I2C2_SCL
20,21,24
I2C2_SDA
3B
4A
4B
1OE
2OE
3OE
4OE
EVM_3V3
I2C2_SCL
3
I2C2_SDA
6
UART2/I2C2_nOE
1
VOUT_C2
6
VOUT_YC2
19
8
VOUT_CR2
19
19
11
B
EVM_3V3
3Y
4Y
3
6
R228
0EVOUT1_FLD
VOUT1_FLD_EXP
R159
8
SCLIN
SDAIN
EN
4
1Y
2Y
10K
2
SCLOUT
7
SDAOUT
I2C2_SCL/UART2_RXD_EXP
18,8
I2C2_SDA/UART2_TXD_EXP
18,8
5
READY
TCA4311AD
14
8
11
EVM_3V3
U35
0.1uF
VCC
18,8
2
1
I2C2_SCL/UART2_RXD_EXP
14,20
DCAN0/UART2_TX
NOTE:
BY DEFAULT, VOUT1_FLD,& I2C2 LINES ARE ENABLED AND UART2 LINES ARE DISABLED.
WHENEVER UART2 LINES ARE ENABLED,BOTH I2C2 AND VOUT0/1_FLD LINES ARE NOT AVAILABLE.
NATURE OF CHANGE
3A
3
R196
10K
14
VCC
18
VOUT1_FLD
UART2_CTSn_EXP
GND
VOUT0/1_FLD PIN IS
USED AS
2B
C128 0.1uF
7
A
1B
I2C2_SCL
U30
SN74LVC1G139
DNI
2A
R177
10K
I2C2_SDA
U44
REV NO.
SW_VOUT_EN
1A
SN74CBTLV3125PWR
C225 0.1uF
B
25
14,18
VCC
VOUT_FLD_SEL2
2
R238
R230
R237
GND
VOUT_FLD_SEL1
1
VOUT0_FLD
VOUT0_FLD_EXP
8
R169
VCC
R168
10K
18
14,18
GND
21
0.1uF
GND
21
10K
C119
VCC
EVM_3V3
U26
7
EVM_3V3
B
0E
0E
0E
EVM_3V3
0.1uF C141
DNI
19
19
18
VOUT_C6
VOUT_YC7
VOUT_YC5
VOUT_YC6
14
19
19
19
19
VOUT[0]_R_CR[2]/EMU4/GP2[26]
VOUT[0]_R_CR[3]/GP2[27]
VOUT[0]_R_CR[4]
VOUT[0]_R_CR[5]
VOUT[0]_R_CR[6]
VOUT[0]_R_CR[7]
VOUT[0]_R_CR[8]
VOUT[0]_R_CR[9]
VCC
SW_VOUT_CR2
GND
24
VOUT0_AVID
19
VOUT_C5
VOUT_CR6
VOUT_C7
19
VOUT_C8
19
VOUT_C9
19
VOUT_YC3
19
VOUT_C3
B18
A17
B17
C17
D17
F17
L20
H20
B16
C16
E16
H17
J16
H16
F13
H13
K11
E12
K10
D7
F9
C7
A6
A5
CVOUT1_CLK
B2
A2
L2
H6
J8
J1
H4
J9
L3
K1
7
C
VOUT_YC9
VOUT_YC8
VOUT_CR3
VOUT_CR4
VOUT_CR5
VOUT_CR8
VOUT_CR9
VOUT_CR7
VIN0_D0
VIN0_D1
VIN0_D2
VIN0_D3
VIN0_D4
VIN0_D5
VIN0_D6
VIN0_D7
VIN0_D8
VIN0_D9
VIN0_D10
VIN0_D11
VIN0_D12
VIN0_D13
VIN0_D14
VIN0_D15
VIN0_D16
VIN0_D17
VIN0_D18
VIN0_D19
VIN0_D20
VIN0_D21
VIN0_D22
VIN0_D23
VIN0_D0
VIN0_D1
VIN0_D2
VIN0_D3
VIN0_D4
VIN0_D5
VIN0_D6
VIN0_D7
VIN0_D8
VIN0_D9
VIN0_D10
VIN0_D11
VIN0_D12
VIN0_D13
VIN0_D14
VIN0_D15
VIN0_D16
VIN0_D17
VIN0_D18
VIN0_D19
VIN0_D20
VIN0_D21
VIN0_D22
VIN0_D23
D3
R180 0E
5
7
1A
1OE
1Y
2A
2OE
2Y
6
R179
0E
DCAN0/UART2_RX
14,20
A
GND
UART2/I2C2_nOE
C143
8
3
I2C2_SDA/UART2_TXD_EXP
18,8
4
SN74LVC2G125DCUT
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
DM385_VIDEO
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
90
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
18
of
39
1
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-18. Video B-B Connector
5
4
3
2
1
D
D
J28
VIN0_D0
18
18
VIN0_D2
VIN0_D9
18
18
18
VOUT_CR4
VIN0_D6
18
18
VIN0_D8
VIN0_D3
18
VIN0_D7
VOUT_YC4
18
18
18
VOUT_C8
VOUT_YC5
18
18
IP_EVM_12V
VOUT_C6
VOUT_C5
18
18
18
18
VOUT0_G_Y_YC2
VOUT0_G_Y_YC6
VOUT0_R_CR4
VIN0_D6
VIN0_D8
VIN0_D3
VIN0_D7
VOUT0_G_Y_YC4
VOUT0_B_CB_C8
VOUT0_G_Y_YC5
VOUT0_B_CB_C6
VOUT0_B_CB_C5
VOUT0_B_CB_C3
VOUT_C3
VOUT0_B_CB_C7
VOUT_C7
18
VOUT_C2
VOUT_CR3
18
18
VIN0_D19
VIN0_D20
18
VIN0_D21
18
18
VIN0_D22
VOUT_CR7
18
18
VOUT_CR8
VIN0_D23
22
VIN0_CLK0
VOUT0_B_CB_C4
VIN0_CLK0
VOUT_C4
18
18
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
VOUT0_G_Y_YC3
VOUT0_G_Y_YC9
VOUT_YC3
VOUT_YC9
18
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
VIN0_D2
VIN0_D9
VOUT_YC2
VOUT_YC6
18
C
VIN0_D0
VOUT0_B_CB_C2
VOUT0_R_CR3
VIN0_D19
VIN0_D20
VIN0_D21
VIN0_D22
VOUT0_R_CR7
VOUT0_R_CR8
VIN0_D23
USB0_CE
USB0_CE
122
124
126
128
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
G2
G4
G6
G8
G1
G3
G5
G7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
VIN0_DE0
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
VOUT0_R_CR2
VIN0_DE0
VIN0_FLD0
VIN0_CLK1
18,19
VIN0_FLD0
VIN0_CLK1
VIN0_D1
VIN0_D4
VIN0_D11
VIN0_D5
VIN0_D12
VIN0_D10
VIN0_D14
VIN0_D13
VIN0_D15
VOUT0_CLK
18,19
18
VIN0_D1
VIN0_D4
18
18
VIN0_D11
VIN0_D5
18
18
VIN0_D12
VIN0_D10
18
18
VIN0_D14
VIN0_D13
18
18
VIN0_D15
VOUT0_CLK
18
J27
18
18
VOUT0_G_Y_YC8
VOUT0_G_Y_YC7
VOUT_YC8
VOUT_YC7
VOUT0_B_CB_C9
VOUT_C9
VOUT0_R_CR6
VOUT0_R_CR5
VOUT0_R_CR9
VOUT0_HSYNC
18,19
VOUT_CR2
18
VOUT_CR6
VOUT_CR5
18
18
VIN0_D16
VIN0_D17
VIN0_D18
VOUT0_VSYNC
VIN0_FLD0
VIN0_FLD0
15
15
CSI2_DX4
CSI2_DY4
15
15
CSI2_DX3
CSI2_DY3
15
15
CSI2_DX2
CSI2_DY2
15
15
CSI2_DY1
CSI2_DX1
15
15
CSI2_DY0
CSI2_DX0
CSI2_DX4
CSI2_DY4
CSI2_DX3
CSI2_DY3
18
VOUT_CR9
18
VOUT0_HSYNC
VIN0_D16
VIN0_D17
VIN0_DE1
VIN0_DE1
18 EXP_EVM_3V3
18
EXP_EVM_5V0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CSI2_DX2
CSI2_DY2
CSI2_DY1
CSI2_DX1
CSI2_DY0
CSI2_DX0
18
18
18
VIN0_D18
18
VOUT0_VSYNC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
VIN0_DE0
VIN0_DE0
18,19
VIN0_HSYNC
R143 DNI 0E
VIN0_HSYNC
18
VIN0_HSYNC_EXP
18
VIN0_VSYNC
R144 DNI 0E
VIN0_VSYNC
18
VIN0_VSYNC_EXP
18
SPI1_SCLK
SPI1_MISO
SPI1_MOSI
SPI1_nCS0
SPI1_SCLK
SPI1_MISO
20
20
SPI1_MOSI
SPI1_nCS0
20
20
C
18
61
62
63
64
18
VOUT0_AVID
VOUT0_AVID
VIN0_FLD1
USB1_CE
VIN0_FLD1
USB1_CE
18
QSH-030-01-L-D-A
18
22
PM_I2C_SCL
PM_I2C_SDA
14,28,29,8
14,28,29,8
121
123
125
127
B
B
EXP_EVM_5V0
EXP_EVM_3V3
IP_EVM_12V
C136
10uF C132
0.1uF
100uF C131
C412
10uF C416
0.1uF
100uF C422
C411
10uF C417
0.1uF
100uF C421
CON_PMC_60X2_F
CONNECTOR : J28 ON DM385 Board
CONNECTOR : J27 ON DM385 Board
App.BOARD
MATING CONNECTOR
VIDEO CAMERA
J1
VIDEO CONFERENCE
J1
VIDEO SECURITY
J11
I/O EXPANDER
J1
App.BOARD
VIDEO CAMERA
VIDEO CONFERENCE
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
MATING CONNECTOR
J2
J2
VIDEO SECURITY
J12
I/O EXPANDER
J2
Mistral Solutions [P] Ltd.
A
Title
VIDEO B-B CONN
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
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2
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C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
19
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
91
Appendix A
www.ti.com
Figure A-19. DM385 Serial Interfaces
3
2
SATA_ACT0_LED
14,18
14,18
R265 DNI 0E
R225
22E
R266 DNI 0E
R258
0E
E29
E30
R269
N26
E31
0E
M21
L22
DCAN0/UART2_TX
DCAN0/UART2_RX
SPI[0]_SCS[0]n
SPI[0]_SCS[1]n/SD1_SDCD/SATA_ACT0_LED/EDMA_EVT1/TIM4_IO/GP1[6]
UART0_CTSn/DCAN1_TX/SPI[1]_SCS[3]n/SD0_SDCD
UART0_RTSn/DCAN1_RX/SPI[1]_S
SPI[0]_SCLK
SPI[0]_D[0]
SPI[0]_D[1]
UART0_DSRn/SPI[0]_SCS[2]n/I2C[2]_SDA/SD1_SDWP/GP1[3]
UART0_DTRn/UART1_TXD/GP1[4]
SPI[1]_SCS[0]n/GP1[16]
SPI[1]_SCLK/GP1[17]
SPI[1]_D[0]/GP1[26]
SPI[1]_D[1]/GP1[18]
UART0_DCDn/SPI[0]_SCS[3]n/I2C[2]_SCL/SD1_POW/GP1[2]
UART0_RIN/UART1_RXD/GP1[5]
I2C[0]_SCL
I2C[0]_SDA
DCAN0_TX/UART2_TXD/I2C[3]_SDA/GP1[0]
DCAN0_RX/UART2_RXD/I2C[3]_SCL/GP1[1]
I2C[1]_SCL/HDMI_SCL
I2C[1]_SDA/HDMI_SDA
G29
G28
SPI0_nCS0
R249
0E
N24
J28
J27
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
J29
M29
N23
M27
SPI1_nCS0
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
T27
T24
I2C0_SCL
I2C0_SDA
15
SPI0_nCS0
SPI0_nCS1
14,21
14
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
14,21
14,21
14,21
SPI1_nCS0
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
19
19
19
19
EVM_3V3
EVM_3V3
R261
R253
TMS320DM385
5
4
VCC
GND
EVM_3V3
R395
100E
C327
1uF
U68
2
21
VCC
11
T_IN
TSOP34840
UART0_RXD_RS232
9
20,21
UART0_OFF
UART0_OFF
R_OUT
1
R_IN
EN
2
PROM_EVM_3V3
INVALID
C1+
C2+
C1-
C2-
C213
8
VCC
U51
HDR_5X2
PROM_GND
PROM_I2C0_SDA
5
A0
A1
A2
SDA
FROMCAT24C256WI-GT3
B
TO GET THE DEFAULT CONNECTION
DM385 PLEASE PLACE THE SHORT LINKS
BETWEEN 1-2, 3-4, 5-6 AND 9-10 ONLY.
4
VSS
EEPROM HDR
SCL
WP
6
V+
PROM_I2C0_SCL
R309
0E
DNI
R300
0E
DNI
R291
0E
DNI
R310
0E
R301
0E
R292
0E
R478
0E
6
GND
V-
3
7
C347
1uF
C310
1uF
EVM_3V3
EVM_3V3
EVM_3V3
PROM_WP
EEPROM
C685
1uF
R483
10K
C684
10uF
PROM_GND PROM_GND PROM_GND
VCC
PROM_GND
FORCEOFF
FORCEON
I2C ADDRESS : 0X50
UART0_RTSn
R484
10K
U87
15
DO NOT FOR 7-8
UART_GND
5
MAX3221CPWR
1
2
3
7
C
UART_GND
PROM_EVM_3V3
14
PROM_I2C0_SCL
PROM_I2C0_SDA
PROM_WP
UART_GND
10
P3
C333
1uF
0.1uF
2
4
6
8
10
10
C322
1uF
4
1
3
5
7
9
8
11
DM385 DB9
R463
10K
DNI
PROM_EVM_3V3
5
9
4
8
3
7
2
6
1
13
0E
PROM_GND
I2C0_SCL
I2C0_SDA
12
UART0_TXD_RS232
UART0_RXD
R303
J19
T_OUT
CON_DSUB_9_M
16
IR Rx
R438
10K
DNI
EVM_3V3
FORCEOFF
FORCEON
UART0_TXD
C273
4.7uF
3
IR_REMOTE_OFF
R477
10K
U84
15
3
1
2
C
8
8
22
22
EVM_3V3
R457
10K
C324
10uF
C288
0.1uF
1
SN74LVC1G125DCKR
I2C1_SCL
I2C1_SDA
HDMI_I2C1_SDA
HDMI_I2C1_SCL
EVM_3V3
R426
10K
U71
21,28,33,8,9
21,28,33,8,9
DNI 0E
DNI 0E
0E
0E
EVM_3V3
UART1_RXD
D
I2C0_SCL
I2C0_SDA
R251
R259
D2
D1
EVM_3V3
1
22
MMC1_SD_CD
R260
UART1_RXD
D30
D31
0E
UART0_RXD
UART0_TXD
R252
MMC1_SD_WP
PCF8575_INT_IO1
MMC1_POW
I2C2_SCL
J26
E28
47K _1%
15
18,21,24
D
0E
UART0,DCAN0,SPI0,SPI1,I2C0,I2C1
0E
R271
15
13,21
R257
I2C2_SDA
R241
R262
47K _1%
18,21,24
UART0_RXD
UART0_TXD
UART0_CTSn
UART0_RTSn
UART0_RXD
UART0_TXD
UART0_CTSn
UART0_RTSn
R268
R481 DNI 0E
U55L
14
14
14
14
2.2K
4
2.2K
5
11
T_IN
T_OUT
B
16
12
13
UART0_RTS_RS232
UART0_CTS_RS232
UART0_CTSn
20,21
UART0_OFF
9
UART0_OFF
1
2
R_OUT
EN
R_IN
INVALID
C1+
C2+
C1-
C2-
8
10
5
C381
1uF
C382
1uF
4
V+
14
GND
V-
6
3
7
C687
1uF
MAX3221CPWR
C686
1uF
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
DM385_SERIALINTERFACES
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
92
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
20
of
39
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SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-20. SPI Flash
5
4
3
2
EVM_3V3
1
EVM_3V3
EVM_3V3
EVM_3V3
SPI FLASH
C161
0.1uF
A
4
B
7
14,20
1
14,20
OE
SN74CBTLV1G125DBVR
SPI0_MISO
SPI0_MOSI
SPI0_MISO
15
SPI0_MOSI
8
CS
DIO
DO
USER_SW1
USER_SW2
USER_SW3
USER_SW4
1
2
3
4
8
7
6
5
ON
1
2
3
4
RA23 5
6
7
8
4 1K
3
2
1
USER_LED1
USER_LED2
USER_LED3
USER_LED4
2
R156
330E
2
2
SW9
LD4
LD5
D
GDH04S04
10
SPI_BOOTn
GND
SPI_BOOTn
W25X32VSFIG
R189
10K
DNI
3
13
CLK
R155
330E
LD3
1
LTST-C150GKT
2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
HOLD
16
R154
330E
LD2
1
LTST-C150GKT
SPI0_nCS0
SPI0_SCLK
SPI0_SCLK
3
4
5
6
11
12
13
14
1
LTST-C150GKT
SPI0_nCS0
VCC
14,20
WP
1
14,20
5
U41
D
R153
330E
RA45
10K
VCC
9
GND
R224
10K
C155
0.1uF
2
U40
R229
10K
2
R190
10K
8
7
6
5
R227
10K
1
LTST-C150GKT
EVM_3V3
EVM_3V3
1
2
3
4
EVM_3V3
SW GPIO
IO EXPANDER -2
IO EXPANDER -1
EVM_3V3
EVM_3V3
EVM_3V3
EVM_3V3
EVM_3V3
C194 0.1uF
20
IR_REMOTE_OFF
R315
0E
R186 DNI 0E
R193
0E
13
14
15
16
17
18
19
20
SCL
SDA
R206
10K
DNI
13,20
R217
10K
DNI
R214
10K
DNI
7
7
14
14
21
2
3
8
22
R211
23
0E
R216
0E
I2C0_SCL
I2C0_SDA
20,21,28,33,8,9
14
6
6
6
7
6,7
20,21,28,33,8,9
PCF8575PWR
R325 22E
IO_EXP2_GP3
MCA5_MUX_OE
GPIO_VC_1
GPIO_VC_2
MCA1_MUX2_nOE
MCA1_MUX_SEL
TP76
TP75
I2C0 ADDRESS : 0X20
13
14
15
16
17
18
19
20
SMD
SMD
MCA0_AXR9 IS USED AS A GPIO
ON APPLICATION BOARD.
SO WE ARE PROVIDING ANOTHER
GPIO ON EXPANSION CONNECTOR
EVM_3V3
4
5
6
7
8
9
10
11
24
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
EVM_3V3
R340
10K
VCC
24
P10
P11
P12
P13
P14
P15
P16
P17
PCF8575_INT_IO1
GPIO_VS_1
MCA0_DEC_A
MCA0_DEC_B
MCA0/1/3_RSEL_A
MCA0/1/3_RSEL_B
IO_EXP2_GP1
IO_EXP2_GP2
MCA0_AXR9
INT
A0
A1
A2
SCL
SDA
C
1
PCF8575_INT_IO2
6
R280
10K
R321
10K
R324
10K
DNI
R275
0E
DNI
R322
0E
DNI
R323
0E
21
2
3
22
R298
0E
I2C0_SCL
20,21,28,33,8,9
23
R299
0E
I2C0_SDA
20,21,28,33,8,9
I2C0 ADDRESS : 0X23
12
EXP_ETH_RESET
28
MSP430_INT
30,33
TPS_INT1
TPS_SLEEP
PCI_SW_RESETn
A0
A1
A2
1
14
7
7
0E R209
GPMC_ADD_SELn
33
25
INT
0E R220
13
11,12
P00
P01
P02
P03
P04
P05
P06
P07
EVM_3V3
0E R201
R175
10K
4
5
6
7
8
9
10
11
U50
GND
USER_SW1
USER_SW2
USER_SW3
USER_SW4
USER_LED1
USER_LED2
USER_LED3
USER_LED4
VCC
U39
12
EVM_3V3
C
R200 R555
10K
10K
R223
10K
GND
C156
0.1uF
PCF8575PWR
EVM_3V3
1
5
U67
20
UART0_OFF
4
C279
0.1uF
2
R403
10K
EXP_UART_EN#
IO EXPANDER -3
14
SN74LVC1G04DCKR
B
B
3
EVM_3V3
EVM_3V3
0.1uF
DISABLE_SD
DISABLE_SF
BYPASS_SD
BYPASS_SF
FILTER1
FILTER2
VOUT_FLD_SEL1
VOUT_FLD_SEL2
22
22
HDMI_CT_HPD
HDMI_LS_OE
TP32
TP27
TP24
TP22
TP21
TP17
SMD
SMD
SMD
SMD
SMD
SMD
13
14
15
16
17
18
19
20
24
P00
P01
P02
P03
P04
P05
P06
P07
INT
P10
P11
P12
P13
P14
P15
P16
P17
SCL
PCF8575PWR
A0
A1
A2
SDA
GND
24
24
24
24
24
24
18
18
EVM_3V3
R67
10K
VCC
U14
4
5
6
7
8
9
10
11
1
TP12
SMD
R83
10K
DNI
R72
10K
DNI
R77
10K
DNI
R82
0E
R71
0E
R76
0E
21
2
3
22
R97
0E
I2C2_SCL
18,20,24
23
R98
0E
I2C2_SDA
18,20,24
I2C2 ADDRESS : 0X20
12
C68
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
SPI FLASH_I2C EXP
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Monday, March 05, 2012
21
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
93
Appendix A
www.ti.com
Figure A-21. DM385 HDMI, SATA, USB0, and USB1
5
4
EVM_3V3
3
EVM_5V0
C6
0.1uF
2
5V_OUT_HDMI
C387
0.1uF
C385
10uF
1
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
C386
0.1uF
J2
U55J
HDMI_D1-_FLT
HDMI_D0+_FLT
HDMI_D1+_FLT
HDMI_D1-_FLT
21
20
HDMI_D0-_FLT
HDMI_CLK+_FLT
HDMI_D2+_FLT
HDMI_D2-_FLT
23
22
HDMI_CLK-_FLT
CE_REMOTE_OUT
HDMI_CLK+_FLT
HDMI_CLK-_FLT
16
15
11
24
D0+
D0-
VCCA
18
17
VCC5V
HDMI_D0+_FLT
HDMI_D0-_FLT
5V_OUT
HDMI_D2-_FLT
HDMI_D1+_FLT
D1+
D1-
CT_HPD
LS_OE
SCL_A
SDA_A
D2+
D2-
HPD_A
CEC_A
HDMI_CT_HPD
HDMI_LS_OE
12
5
HDMI_I2C1_SCL
HDMI_I2C1_SDA
2
3
HDMI_HP_IN
CE_REMOTE_IN
4
1
HDMI_CT_HPD
HDMI_LS_OE
HDMI_I2C1_SCL
HDMI_I2C1_SDA
21
21
20
20
10
7
HDDAC_VREF R273
HPD_B
CEC_B
CON_HDMI_19X1
R4
10K
B14
A14
HDMI_D1+
HDMI_D1-
B12
B13
A11
A12
A9
A8
B8
HDDAC_A
HDDAC_B
HDDAC_C
R250
TPD12S016PWR
C8
0.1uF
DNI
24
24
B7
B6
2.67K_1%
D9
E9
HDDAC_VSYNC
HDDAC_HSYNC
23
USB0_DP
23
USB0_DM
23
USB0_ID
19
TPD12S016PWR IS NEWLY USED HDMI ESD PROTECTION DIODE
AS REPLACEMNT TO TPD12S521DBTR
HDMI CON
HDMI_D0+
HDMI_D0-
0E
DNI
HDMI_HP_OUT
CE_REMOTE_OUT
DNI
SCL_B
SDA_B
1nF C688
HDMI_HP_OUT
8
9
GND1
GND2
GND3
DDC_CLK
DDC_DAT
A15
B15
24
24
24
5V_OUT_HDMI
DDC_CLK
DDC_DAT
HDMI_CLK+
HDMI_CLK-
HDMI_D2+
HDMI_D2-
HDMI_HP_IN
13
CE_REMOTE_IN
13
CLK+
CLK-
6
14
19
23
22
21
20
D
U4
13
HDMI, SATA, USB0, USB1
HDMI_D2+_FLT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
23
A21
B21
HDMI_CLKP
HDMI_CLKN
SATA_AMUX
SATA_TXP0
SATA_TXN0
HDMI_DP0
HDMI_DN0
SATA_RXP0
SATA_RXN0
HDMI_DP1
HDMI_DN1
SATA1_AMUX
HDMI_DP2
HDMI_DN2
SATA1_TXP0
SATA1_TXN0
HDDAC_A
HDDAC_B
HDDAC_C
SATA1_RXP0
SATA1_RXN0
HDDAC_VREF
HDDAC_IREF
USB1_DP
USB1_DM
HDDAC_VSYNC
HDDAC_HSYNC
USB1_ID
USB1_CE
USB0_DP
USB0_DM
USB1_VBUSIN
USB0_DRVVBUS/GP0[7]
TP66
USB0_CE
A20
B20
USB0_VBUS
B22
J25
DNI
N31
N30
SATA0_TXP0
SATA0_TXN0
C377
C378
0.01uF
0.01uF
SATA0_TXP0_CON
SATA0_TXN0_CON
M30
L30
SATA0_RXP0
SATA0_RXN0
C379
C380
0.01uF
0.01uF
SATA0_RXP0_CON
SATA0_RXN0_CON
H24
D
DNI
T30
R30
SATA1_TXP0
SATA1_TXN0
C373
C374
0.01uF
0.01uF
P30
P31
SATA1_RXP0
SATA1_RXN0
C375
C376
0.01uF
0.01uF
A23
B23
SATA1_TXP0_CON
SATA1_TXN0_CON
SATA1_RXP0_CON
SATA1_RXN0_CON
USB1_DP
USB1_DM
A24
C21
USB1_ID
USB1_CE
TP53
USB1_VBUS
B24
K23
SATA CON
23
23
23
19
23
USBB0_DRV_VBUS
23
USB0_ID
USB0_CE
USB0_VBUSIN
TMS320DM385
EVM_3V3
EVM_3V3
HDMI_HP_IN
C
SATA INTERFACE IS NOT AVAILABLE IN DM385/DM388.
HENCE IT IS NOT TO BE POPULATED ON THIS DESIGN
DDC_CLK
R96
10K
HDMI_CT_HPD
1.7K_1%
DDC_DAT
R100
10K
HDMI_LS_OE
R307
1K_1%
IP_EVM_12V
C319
1.7K_1%
R9
5
R278
4.99K_0.1%
DNI
DNI
10uF_16V
HDDAC_VREF
7.5K_1%
1uF
R290
C195
0.1uF
A 7-pin Serial ATA data cable
+
DNI
0.1uF
4
TLV431AQDBVR
L4
R305
0E
D7
DNI
10uF_20V
3
+
2
1
IP_EVM_12V
EVM_5V0
J23
J25
8
9
CON_PWR_4
4
1
HDMI_CLK+
HDMI_D0+_FLT
4
1
HDMI_D0+
HDMI_CLK-_FLT
3
2
HDMI_CLK-
HDMI_D0-_FLT
3
2
HDMI_D0-
HDMI_D1+_FLT
4
1
HDMI_D1+
HDMI_D2+_FLT
4
1
HDMI_D2+
HDMI_D1-_FLT
3
2
HDMI_D1-
HDMI_D2-_FLT
3
2
HDMI_D2-
IP_EVM_12V
SATA0_TXP0_CON
SATA0_TXN0_CON
SATA0_RXN0_CON
SATA0_RXP0_CON
CON_7X1
DNI
EVM_5V0
1
2
3
4
5
6
7
MH1 1
2
3
4
5
6
MH9 7
1
2
3
4
+12V
GND1
GND2
+5V
C196
0.1uF
L3
HDMI_CLK+_FLT
Pin # Function
1 Ground
2 A+ (Transmit)
3 A- (Transmit)
4 Ground
5 B- (Receive)
6 B+ (Receive)
7 Ground
- coding notch
EVM_5V0
C344
EVM_3V3
R13
C351
EVM_3V3
CE_REMOTE_IN
DNI
10uF
47K _1%
C323
100K
R27
DNI
0.1uF
EVM_5V0
R21
C343
CE_REMOTE_OUT
27K
C350
R16
C
DNI
C335
C348
C321
C334
C318
+
ACM2012H-900-2P
IP_EVM_12V
+
EVM_5V0
DNI
10uF
DNI
0.1uF
DNI
10uF_16V
1uF
DNI
J24
L1
DNI
0.1uF
L2
DNI
10uF_20V
ACM2012H-900-2P
B
C349
SATA PWR
0.5V IS GENERATED FOR HD_DAC VREF
AND R250 VALUE NEEDS VERIFICATION
J26
8
+12V
GND1
GND2
+5V
1
2
3
4
9
ACM2012H-900-2P
CON_PWR_4
ACM2012H-900-2P
MH1 1
2
3
4
5
6
MH9 7
1
2
3
4
5
6
7
B
SATA1_TXP0_CON
SATA1_TXN0_CON
SATA1_RXN0_CON
SATA1_RXP0_CON
CON_7X1
DNI
DNI
PLACE FILTERS CLOSE TO HDMI CONNECTOR
SATA PWR
EVM_3V3
EVM_3V3
VDDA_1V8
BCK2_3V3
vout= 1.224(1+80/169)= 1.8V
LD11
LTST-C190GKT
DNI
C683 0.1uF
4
U86A
U86B
4.7uF 0.1uF
20
TPS76901DBVT
SATA_ACT0_LED
ACT0_LED
R479
1
0E
Open drain
6
DNI
DNI
SN74LVC2G06DCKR
6
SATA_ACT1_LED
ACT1_LED
R482
0E
3
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
4
DNI
SN74LVC2G06DCKR
NATURE OF CHANGE
Open drain
DNI
2
R73
169K_1%
LTST-C190GKT
1
C50
5
C54
SN74LVC1G126DBVR
REV NO.
LD10
DNI
DNI
R65
80K
1
EN
TP13
5
5
OUT
NC/FB
A
2
C61
0.1uF 1uF
GND
OE
3
1
R68
10K
DNI
IN
GND
3
2
Y
4
C62
A
1
5
VCC
A
R485
330E_1%
EVM_3V3
2
100mA
R86
10K
VDDA_1V8
DNI
SATA LED INDICATOR
2
LDO_EVM_1V8
U12
0.1uF
U11
R486
330E_1%
DNI
EVM_3V3
C55
2
SATA LED INDICATOR
DM385_HDMI-SATA-USB0-USB1
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
94
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Monday, August 08, 2016
22
of
39
1
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-22. USB Interface
5
4
3
2
1
J10
1
2
EVM_5V0
C3
150uF_10V
+
HDR_2X1
22
EVM_5V0
TP6
FL3
7
R5
100K
8
+
600E
C2
4.7uF_10V
CON_MUSB-AB_5_F
C11
0.1uF
22
22
22
USBB0_DRV_VBUS
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
C
1
2
3
4
5
USB0_DM
USB0_DP
USB0_ID
USB0_DM
USB0_DP
USB0_ID
J12
1
2
U2
3
HDR_2X1
IO2
GND
1
2
C
J11
1
2
C4
150uF_10V
FL2
8
USB1-OTG
600E
CON_MUSB-AB_5_F
C1
4.7uF_10V
9
+
EVM_5V0
C9
0.1uF
TPS2065DR
22
22
22
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
1
2
3
4
5
USB1_DM
USB1_DP
USB1_ID
USB1_DM
USB1_DP
USB1_ID
VCC
DD+
ID
GND
J13
U3
1
2
3
C383
0.1uF
IO1
HDR_2X1
2
IO2
SH3
SH2
8
B
7
6
OC
USB1_VBUS_CONN
2
R10
100K
SH4
OUT3
1
7
SH1
EN
USB1_VBUS
6
VCC
100uF_10V
R1
10K
OUT2
1
5
+
OUT1
IN2
1
4
IN1
GND
C5
3
USBB1_DRV_VBUS
FL1
U1
2
6
2
7
J1
HDR_2X1
DNI
+
B
1
J3
HDR_2X1
USB1_VBUS
SH2
8
5
4
TPD2E001DRLR
22
SH3
NC.2
PLACE JUMPER ON J12
ONLY FOR HOST MODE
OF OPERATION
EVM_5V0
VCC
DD+
ID
GND
C384
0.1uF
IO1
2
600E
9
EVM_5V0
TPS2065DR
SH4
OC
USB0-OTG
SH1
OUT3
VCC
R37
10K
OUT2
EN
USB0_VBUS_CONN
2
6
5
IN2
1
1
+
OUT1
USB0_VBUS
6
1
4
100uF_10V
C16
3
D
IN1
GND
2
22
USB0_VBUS
U6
D
J4
5
NC.2
4
GND
PLACE JUMPER ON J13
ONLY FOR HOST MODE
OF OPERATION
TPD2E001DRLR
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
USB INTERFACE
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
SPRUI85 – August 2016
Submit Documentation Feedback
2
Rev
B
Sheet
23
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
95
Appendix A
www.ti.com
Figure A-23. DM385 PCIe, JTAG, and Video
5
4
3
2
1
EVM_3V3
B10
2.7K_1%
B9
R514
D
25
25
CON.PCIE_TXP0
CON.PCIE_TXN0
25
25
CON.PCIE_RXP0
CON.PCIE_RXN0
B11
4.7K
CON.PCIE_TXP0 C296 0.1uF
CON.PCIE_TXN0
C290 0.1uF
PCIE_TXP0
PCIE_TXN0
CON.PCIE_RXP0
CON.PCIE_RXN0
PCIE_RXP0
PCIE_RXN0
R427
R409
0E
0E
L31
K31
K30
J30
H28
N28
U26
T31
T29
TDI
TDO
TMS
TCLK
TV_VFB0
TV_OUT0
TV_RSET
R264
N29
RTCK
TDI
TDO
TMS
TCK
22E
R263
22E
TRSTn
A18
B19
EMU0
EMU1
TMS
TDI
R166
4.7K
RTCK
U24
TRSTn
PCIE_TXP0
PCIE_TXN0
J18
EVM_3V3
PCIE AND JTAG
R240
TV_OUT0
JTAG HDR
R184
0E
U55A
R518
R519
27
EMU0
EMU1
22E
22E
EMU_RSTn
18
EMU2
18
EMU4
1
3
5
7
9
11
13
15
17
19
R185 22E
TDO
RTCK
TCK R183
EMU0
EMU_RSTn
EMU2
EMU4
22E
EVM_3V3
TMS
TDI
TVD
TDO
TCKRTN
TCLK
EMU0
SRST
EMU2
EMU4
PCIE_RXP0
PCIE_RXN0
TRSTn
TDIS
KEY
GND.1
GND.2
GND.3
EMU1
GND.4
EMU3
GND.5
2
4
6
8
10
12
14
16
18
20
TRSTn
R222
R221
4.7K
0E
R239
4.7K
D
EMU1
EMU3
EMU3
18
HDR_10X2
PCIE_AMUX
TMS320DM385
EMU0,1,2,3,4 SHOULD MATCH THE TRACE LENGTH TO REDUCE SKEW...
EVM_5V0
EVM_3V3
0.1uF
1uF
0.01uF
C33
C37
R58
C31
VIDEO AMPLIFIER
R18
0E
0E
VGA_G
TV_OUT0
J8
5
U5
R62
HDDAC_A
0E
R43
1
48.7K_1%
R579
2
R45
165E_1%
DNI
3
26.7K_1%
VS+
DNI
22
SD1_IN
TP4
SMD
CON_RCAJACK3_RCJ-014
SD1_OUT
SD2_IN
SD2_OUT
SD3_IN
SD3_OUT
SF1_IN
SF1_OUT
SF2_IN
SF2_OUT
SF3_IN
SF3_OUT
20
R26
DNI 75E_1%
COMPOSITE_Y
1
11
TP5
SMD
R20
12
13
VGA_HSYNC
14
VGA_VSYNC
15
17
R19
0E
R17
0E
I2C2_SDA_BUF
24
I2C2_SCL_BUF
24
C
0E
19
4
3
2
C
VGA_B
COMPOSITE
P1
6
1
7
2
8
3
9
4
10
5
16
VGA_R
EVM_3V3
18
CON_DSUB_15_F
7
8
0E
9
R46
165E_1%
21
R61
HDDAC_C
17
DISABLE_SF
15
21
FILTER1
6
21
FILTER2
4
21
22
DISABLE_SD
DISABLE_SD BYPASS_SD
DISABLE_SF
BYPASS_SF
14
VID_AMP_R
R33
75E_1%
13
VID_AMP_G
R28
75E_1%
12
VID_AMP_B
R23
75E_1%
R6
75E_1%
R7
75E_1%
R8
75E_1%
10
11
BYPASS_SD
21
BYPASS_SF
21
R36
COMP_R
1
0E
FILTER2
16
R44
165E_1%
FILTER1
J6
CON_RCAJACK3_RCJ-012
0E
GND_VIDEO
GND
4
3
2
R60
HDDAC_B
GND
22
COMP_G
THS7360IPW
1
J7
4
3
2
CON_RCAJACK3_RCJ-016
GND_VIDEO
COMP_B
1
J9
CON_RCAJACK3_RCJ-015
B
4
3
2
B
EVM_5V0
EVM_5V0
EVM_3V3
BAV99
BAV99
2
2
3
4
5
SYNC_IN1
SYNC_IN2
VIDEO1
VIDEO2
VIDEO3
TPD7S019-15DBQR
BYP
14
16
I2C2_SDA_BUF
I2C2_SCL_BUF
1
3
D4
TPD1E10B09DPY
D8
24
24
COMP_R
D3
TPD1E10B09DPY
D11
2
2
1
SYNC_OUT1
SYNC_OUT2
9
12
VGA_VSYNC
VGA_HSYNC
EVM_3V3
EVM_3V3
8
BAV99
BAV99
2
C14
0.22uF
2
3
COMP_G
1
3
D2
TPD1E10B09DPY
D5
TPD1E10B09DPY
D9
2
D10
COMP_B
1
2
VGA_R
VGA_G
VGA_B
DDC_OUT1
DDC_OUT2
1
1
TP15
SMD
13
15
VCC_DDC
TP14
SMD
DDC_IN1
DDC_IN2
VCC_SYNC
HDDAC_VSYNC
HDDAC_HSYNC
0E
0E
10
11
VCC_VIDEO
R56
R57
I2C2_SDA
I2C2_SCL
GND
22
22
I2C2_SDA
I2C2_SCL
COMPOSITE_Y
1
6
18,20,21
18,20,21
7
3
U7
2
47K _1%
0.1uF
47K _1%
C13
R55
0.1uF
R54
EVM_3V3
C12
1
EVM_3V3
0.1uF
1
EVM_5V0
C15
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
DM385_PCIe-JTAG-VIDEO
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
96
4
3
Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
24
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-24. PCIe Connector
5
4
3
2
1
R386
IP_EVM_12V
EVM_3V3
10K R387
0.1uF C267
C300
0E
PRSNT#
PCI CON
10K R474
SN74CBTLV1G125DBVR
EVM_3V3
RESET_GPIO
EVM_3V3
GDH04S04
C341
U82
5
1
U73
PCI_CON_PORz
2
A
PCI_3V3
0.1uF
B
4
PCI_PORz
27
C653
R436 C229 0.1uFPCI_CONN_REFP
0E
DNI
C228 0.1uFPCI_CONN_REFN
REFCLKp
REFCLKn
CON.PCIE_RXP0
CON.PCIE_RXN0
10K R472
18
13
0.1uF
SW_VOUT_EN
GPMC_nWP
5
8
7
6
5
C
EVM_3V3
VCC
4
3
10K R432
3
OE
0.1uF C297
R471
2
0.1uF C320
VCC
3
1
2
PCI_CONN_REFP
26
PCI_CONN_REFN
26
4
1
OE
GND
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
1
PCI_CON_PORz
4
3
GND.13
REFCLK+
REFCLKGND.14
PERp0
PERn0
GND.15
RSVD.3
GND.16
PERp1
PERn1
GND.17
GND.18
PERp2
PERn2
GND.19
GND.20
PERp3
PERn3
GND.21
RSVD.4
1
2
3
4
ON
B
3
CON.PCIE_TXP0
CON.PCIE_TXN0
R413
RSVD.1
GND.3
PETp0
PETn0
GND.4
PRSNT2
GND.5
PETp1
PETn1
GND.6
GND.7
PETp2
PETn2
GND.8
GND.9
PETp3
PETn3
GND.10
RSVD.2
PRSNT2.2
GND.11
10K
PCI_CON_PORz
SH1
SH2
PRSNT#
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
R475
10K
PRSNT1
+12V.4
+12V.5
GND.12
TCK
TDI
TDO
TMS
+3.3V.2
+3.3V.3
PERSTn
PRSNT#
R473
+12V.1
+12V.2
+12V.3
GND.1
SMCLK
SMDAT
GND.2
+3.3V.1
TRSTn
3.3VAUX
WAKEn
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
1uF C362
1uF C359
0.1uF C363
0.1uF C352
U72
0.1uF C358
SW11
2
CON.PCIE_TXP0
CON.PCIE_TXN0
TP9
10K
GND
PCI_3V3
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
A
TPS3808G09DBVRG4
IP_EVM_12V
5
0.1uF
5
2
GND
GND
2
0.1uF C260
4
2
KEY
24
24
U83
1
PCI_SW_RESETn
SN74LVC1G08
SH1
SH2
10K
U74
21
IP_EVM_12V
R470
PCI_3V3
B
1
1
TPS3808G09DBVRG4
0.1uF
C272
CT
CT
EVM_3V3
EVM_3V3
RESET
4
C
RESET
C286
MR
SENSE
VDD
3
TP101
EVM_3V3
MR
4
5
6
U69
U62
3
TP94
0.1uF
1K_1% R406
1nF C285
10K
EVM_5V0
D
EVM_3V3
5
6
R404
PCI_3V3
SENSE
VDD
D
1K_1% R394
1nF C268
10K
EVM_5V0
CON.PCIE_RXP0
CON.PCIE_RXN0
SN74CBTLV1G125DBVR
SN74LVC1G04DCKR
24
24
B
Check arrangement to be done
CON64_PCI
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
PCIe CONNECTOR
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Monday, March 05, 2012
3
SPRUI85 – August 2016
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Rev
B
Sheet
25
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
97
Appendix A
www.ti.com
Figure A-25. SerDes Clocks
5
4
3
2
1
EVM_3V3
TP84
VDD_CDC
3V3_VDDA
3V3_VDDA
3V3_VDDA
D
D
DNI
10K R293
DNI
10K R296
10K R350
DNI
10K R349
10K R348
DNI
10K R346
10K R347
TP73
EVM_3V3
3V3_VDDA
FL7
1
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
2
C236
10uF
1KE
C548
0.1uF
C531
100pF
C546
0.1uF
0E R294
C
U56
3V3_VDDA
10K R539
15
14
13
10
11
11,12,14,27,9
7
12
RSTOUTn
VCC_PLL1
VCC_PLL2
VCC_VCO
VCC_IN
OD2
OD1
OD0
VCC_OUT.1
VCC_OUT.2
OS1
OS0
OUTP1
OUTN1
OUTP0
OUTN0
CE
RSTn
XIN
10K R333
8
GND.1
NC.8
REG_CAP2
REG_CAP1
27
30
NC.27
NC.30
PWR_PAD
NC.28
NC.29
NC.31
NC.32
33
DNI
C510
C536
C537
0.1uF
0.1uF
2.2uF
0.1uF
0.1uF
18
16
9
20
1
4
3
2
SERDES_IN_REFP
SERDES_IN_REFN
6
5
PCI_CONN_REFP
PCI_CONN_REFN
SERDES_IN_REFP
SERDES_IN_REFN
PCI_CONN_REFP
PCI_CONN_REFN
15
15
DNI
C222 1uF
25
25
OSCOUT
21
1
22
25MHz Y5
3
R311
0E
17
19
23
TP79
C227
10uF
B
C234
10uF
28
29
31
32
B
PR1
PR0
NC.24
C509
2
26
25
24
C508
4
0E R295
DNI
10K R370
0E R369
DNI
10K R368
C
0E R366
DNI
10K R367
VDD_CDC
CDCM61002RHBR
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
SERDES CLOCKS
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
98
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
Schematics
2
Rev
B
Sheet
26
of
39
1
SPRUI85 – August 2016
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Appendix A
www.ti.com
Figure A-26. DM385 Clocks
5
4
3
2
1
D
D
EVM_3V3
FL8
2
1
EVM_3V3
220E
C259
0.1uF
VDD
4
U58
EVM_3V3
EVM_3V3
32.768KHz
TP74
TP48
CLOCKS
R353 DNI 0E
CLK32OUT
OSC_WAKE
14
OSC_WAKE
R182
AJ31
U28
0E
10K
F30
G31
OSC_WAKE
V30
U31
EVQ9P105M
C191 18pF
3
C
B
B1
RESETn
RSTOUTn_WD_OUTn
SW12
A
A1
CLKIN32/CLKOUT0/TIM3_IO/GP3[31]
DEVOSC_WAKE/SPI[1]_SCS[1]n/TIM5_IO/GP1[7]
14
PORn
6
AJ30
R396
AH30
RSTOUTn
2.2K
11,12,14,26,9
Y
SN74LV21A
PORz
VSSA_DEVOSC
VSSA_AUXOSC
G30
U30
8
Y
1
SN74LV21A
Y6
27.000MHz
EVQ9P105M
SW4
R88
10K
U17B
9
A
10
APP_PORz
PCI_PORz
B
C
D
12
13
B
B1
CPU_PORz
0E
EVM_1V8
EVM_3V3
R215
10K
SW7
C124
R195
3
TPS_EVM_5V0
C25
4
9
EVM_3V3
0.1uF
U8
R161
604K_1%
5
6
1nF
C18
0E
need to
set the
Value of
resistors
3
TP8
MR
2
C26
SENSE2
SENSE3
MR
RESET
0E
CORE_RST
0.1uF
8
#MAN_RST
7
6
B
GND
RESET
5
R172
0E
EP
TPS3307-33DGN
CORE_RST
TPS3808G09DBVRG4
0.1uF
CT
VDD
A
A1
EVQ9P105M
GND
RESET
4
1
SENSE1
B
B1
SUPERVISOR CIRCUIT
R38
10K
SENSE
VDD
B
DNI
1K_1% R22
R24
2
R171
0.1uF
U28
R152
220K
1
0E
R174 DNI 0E
C147
XTAL_GND2
TPS_CORE_VDD
33
BCK2_3V3
EVM_3V3 EVM_5V0
RESET
A
A1
14
25
nRESPWRON2
PWR ON RST
XTAL_GND1
3
R124
10K
C59
0.1uF
R316
14
EVM_3V3
TMS320DM385
C232 18pF
XTAL_GND2
24
EXP_WARM_RESET
EVM_3V3
XTAL_GND2
C233 18pF
EMU_RSTn
4
5
BCK2_3V3
0E
2
4
U17A
1
2
C
D
C
AUXOSC_MXI
AUXOSC_MXO
R344 DNI 0E
AUXOSC_MXI
A
B
XTAL_GND1
R282
1
4
C192 18pF
Y3
2 20.000MHz
DEVOSC_MXI/DEV_CLKIN
DEVOSC_MXO
AH29
14
11
14,33
R578
10K
C60
0.1uF
14
11
U55K
EVM_3V3
TP62
R393
10K
DNI
7 GND VCC
3
TP90
OSC_WAKE SWITCH
R132
BCK2_3V3
R134
0E
R133
R354
10K
3
4.7K
OUT
7 GND VCC
3
Tri State
2
1
GND
R380
10K
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
DM385_CLOCKS
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
SPRUI85 – August 2016
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C
Date:
Document Number
MS_TI_DM385EVM_REVA_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
27
of
39
1
Schematics
Copyright © 2016, Texas Instruments Incorporated
99
Appendix A
www.ti.com
Figure A-27. Power Monitor CPU
5
4
3
2
1
EVM_3V3
C493
1uF
EVM_3V3EVM_3V3
C492
0.1uF
EVM_3V3
D
0E
0E
MSP430_TXD
MSP430_RXD
EVM_3V3
R306
10K
MSP430_INT
21
22
23
24
25
26
27
28
2
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/TA1.0/A6
P3.7/TA1.1/A7
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/SMCLK/A1/CA3
P2.2/TA0.0/A2/CA4/CAOUT
P2.3/TA0.1/A3/VREF-/VeREF-/CA0
P2.4/TA0.2/A4/VREF+/VeREF+/CA1
P2.5/ROSC/CA5
XIN/P2.6/CA6
XOUT/P2.7/CA7
P1.0/TACLK/ADC10CLK/CAOUT
P1.1/TA0.0/TA1.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/SMCLK/TCK
P1.5/TA0.0/TMS
P1.6/TA0.1/TDI/TCLK
P1.7/TA0.2/TDO/TDI
TEST/SBWTCK
RST/NMI/SBWTDIO
C223
10pF
R289
100K
8
9
10
19
20
3
EVM_3V3
R284
47K _1%
Y4
32.768KHz
JP2
6
5
C211
10pF
C197
1nF
1
R283
1
3
5
7
9
11
13
330E
MSP430_TDO/TDI
7
MSP430F2132IPWR
4
C
2
4
6
8
10
12
14
HDR_7X2
MSP430_TCK
DVSS
21
11
12
13
14
15
16
17
18
2
R328
R342
D
EVM_3V3
1
14,19,29,8
PM_I2C_SDA
20,21,33,8,9
I2C0_SDA
20,21,33,8,9
I2C0_SCL
14,19,29,8
PM_I2C_SCL
U54
R341
2K
DVCC
R317
2K
MSP JTAG HDR
C
EVM_3V3
EVM_3V3
EVM_3V3
R356
10K
C238
1uF
C239
10uF
15
VCC
FORCEOFF
FORCEON
MSP430_TXD
R378
10K
U59
11
T_IN
T_OUT
16
CON_DSUB_9_M
12
5
9
4
8
3
7
2
6
1
13
R281
0E
MSP430_RXD
9
B
1
R_OUT
EN
R_IN
INVALID
8
11
PM_UART_GND
10
B
10
P2
PM_UART_GND
MSP DB9
R371
10K
R236
2
C1+
C2+
0E
5
C249
1uF
C257
1uF
4
C1-
C2V+
14
GND
V-
PM_UART_GND
6
3
7
MAX3221CPWR
C261
1uF
C237
1uF
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
POWER MONITOR CPU
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
100 Schematics
2
Rev
B
Sheet
28
of
39
1
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-28. Power Monitors
3
2
VIN-
D
8
ALERT
A0
A1
7
VBUS
4
5
PM_I2C_SDA
PM_I2C_SCL
36
10
I_MON_PLL_1V8_HIGH
6
VS+
SDA
SCL
VIN+
PLL_1V8
3
2
1
9
EVM_3V3
TP40
SMD
8
ADDRESS 1000100
C49
0.1uF
U18
PM_I2C_SDA
PM_I2C_SCL
4
5
SDA
SCL
36
10
I_MON_DVDD_HIGH
VIN-
3
2
1
ALERT
A0
A1
VBUS
INA226AIDGSR
EVM_3V3
VIN+
DVDD
9
GND
6
VIN+
9
U10
7
10
DVDD_GPMC
VS+
I_MON_DVDD_GPMC_HIGH
ADDRESS 1000000
C415
0.1uF
GND
36
EVM_3V3
TP20
SMD
8
C66
0.1uF
6
ADDRESS 1000110
U24
1
EVM_3V3
SDA
SCL
VINALERT
A0
A1
VBUS
7
EVM_3V3
VS+
4
GND
5
INA226AIDGSR
EVM_3V3
4
5
PM_I2C_SDA
PM_I2C_SCL
3
2
1
TP28
SMD
EVM_3V3
D
INA226AIDGSR
EVM_3V3
ADDRESS 1000001
VBUS
INA226AIDGSR
EVM_3V3
PM_I2C_SDA
PM_I2C_SCL
14,19,28,29,8
14,19,28,29,8
36
10
I_MON_CVDD_ARM_HIGH
3
2
1
TP16
SMD
8
INA226AIDGSR
VS+
6
C
INA226AIDGSR
U63
PM_I2C_SDA
PM_I2C_SCL
4
5
36
I_MON_VMMC_HIGH
10
9
ALERT
A0
A1
VIN+
VMMC
3
2
1
TP115
SMD
8
C577
0.1uF
SDA
SCL
VINVBUS
ALERT
A0
A1
INA226AIDGSR
PM_I2C_SDA
PM_I2C_SCL
4
5
3
2
1
TP93
SMD
INA226AIDGSR
B
EVM_3V3
VIN-
GND
ALERT
A0
A1
7
VBUS
3
2
1
PM_I2C_SDA
PM_I2C_SCL
TP116
SMD
PM_I2C_SDA
PM_I2C_SCL
14,19,28,29,8
36
14,19,28,29,8
10
I_MON_VDDQ_DM385_1V5_OUT_HIGH
VIN+
VDDQ_DM_1V5
9
EVM_3V3
8
VS+
4
5
C435
0.1uF
SDA
SCL
VINVBUS
ALERT
A0
A1
GND
SDA
SCL
U92
7
6
C410
0.1uF
VS+
VIN+
VDDA_1V8
8
SDA
SCL
VINVBUS
EVM_3V3
TP65
SMD
3
2
1
ADDRESS 1000011
U89
9
6
VIN+
CVDD_ARM
EVM_3V3
10
VBUS
ALERT
A0
A1
PM_I2C_SDA
PM_I2C_SCL
ADDRESS 1001010
C408
0.1uF
VS+
PM_I2C_SDA
PM_I2C_SCL
ADDRESS 1000101
I_MON_VDDA_1V8_HIGH
VIN-
7
GND
ALERT
A0
A1
7
VBUS
4
5
U88
9
B
36
8
SDA
SCL
4
5
EVM_3V3
GND
SDA
SCL
VIN-
8
9
INA226AIDGSR
7
VIN+
CORE_VDD
9
C43
0.1uF
VS+
10
TP33
SMD
EVM_3V3
6
U9
I_MON_CORE_VDD_HIGH
3
2
1
ADDRESS 1000010
ADDRESS 1001000
36
ALERT
A0
A1
VIN+
DVDD_C
GND
8
I_MON_DVDD_C_HIGH
EVM_3V3
VIN-
TP117
SMD
36
C428
0.1uF
7
9
SDA
SCL
10
6
3
2
1
VIN+
HDMI_CSI_1V8
PM_I2C_SDA
PM_I2C_SCL
VS+
I_MON_HDMI_CSI_1V8_HIGH
U29
4
5
GND
36
VS+
14,19,28,29,8
14,19,28,29,8
GND
VBUS
ALERT
A0
A1
7
C
PM_I2C_SDA
PM_I2C_SCL
10
EVM_3V3
VIN-
8
PM_I2C_SDA
PM_I2C_SCL
ADDRESS 1000111
C74
0.1uF
6
9
SDA
SCL
4
5
U15
7
VIN+
CVDD_DSP
VS+
I_MON_CVDD_DSP_HIGH
GND
36
10
C429
0.1uF
6
U90
6
ADDRESS 1001001
INA226AIDGSR
4
5
PM_I2C_SDA
PM_I2C_SCL
3
2
1
TP118
SMD
INA226AIDGSR
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
POWER MONITORS
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
2
Rev
B
Sheet
29
of
39
1
Schematics 101
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-29. DM385 Power
5
4
3
2
1
C486 1uF
K20
L19
C483 1uF
AA19
T23
W10
W11
C512 1uF
Y24
U9
T22
AB10
C517 1uF
C499 1uF
C545 1uF
M26
VDDA_1V8
N27
M28
VDDA33_USB1-1
VDDA33_USB1-2
VDDA_REF_1P8V
VDDA_AUDIO_DSS
VDDA_VIDEO0_VIDEO1
VDDA_HD_1P1V
VDDA_HD_1P8V
VDDRAM_ARM
VDDA_ARM_PLL
VDD_IVA1
VDD_IVA2
VDD_IVA3
VDD_IVA4
VDD_IVA5
VDDA_DDR
VDDA_IVA
VDDA_CSI21
VDDA_ISS_L3L4
VDDS18V1
VDDS18V2
VDDS18V3
VDDS18V4
VDDS18V5
VDDS18V6
VDDS18V7
VDDRAM_IVA
VDDRAM_CORE0
VDDRAM_CORE1
VDDRAM_CORE2
VDDQ_DM_1V5
VDAC_1V8
VHD_1V1
L15
K16
L14
CVDD_DSP
U20
U21
V20
V21
W22
VDDA_1V8
M25
N22
N25
P23
R9
T9
T10
DVDD
VDDD_PCIE
VDDD_SATA
VDDD_SATA1
NMIn
TMS320DM385
21,33
AH31
R355
TPS_INT1
R372
10K
DNI
0E
VDDSHV-2
VDDSHV-3
VDDSHV-4
VDDSHV-5
VDD-1
VDD-2
VDD-3
VDD-4
VDD-5
VDD-6
VDD-7
VDD-8
VDD-9
VDD-10
VDD-11
VDD-12
VDD-13
VDD-14
VDD-15
VDD-16
VDD-17
VDD-18
VDD-19
VDD-20
VDD-21
VDD-22
VDD-23
AB14
AB15
AB17
AB18
AC15
AC17
AC18
AE15
AE16
AF16
AG15
AH16
R373
10K
TP92
VDD POWERVDDSHV-1
VDD1
VDDSHV1-1
VDDSHV1-2
VDDSHV1-3
VDDSHV1-4
VDDSHV1-5
VDDSHV2-1
VDDSHV2-2
VDDSHV2-3
VDDSHV2-4
VDDSHV2-5
VDDSHV2-6
VDDSHV2-7
VDDSHV2-8
VDDSHV2-9
VDDSHV2-10
VDDSHV2-11
VDDSHV2-12
VDDSHV3-1
VDDSHV3-2
VDDSHV3-3
VDDSHV3-4
VDDSHV3-5
VDDS2-1
VDDS2-2
VDDS2-3
VDDS2-4
VDDS2-5
VDDS2-6
VDDS2-7
VDDS2-8
VDDS2-9
VDDS2-10
VDDS2-11
VDDS2-12
VDDSHV9-1
VDDSHV9-2
CVDD_ARM
W5
W7
Y4
Y6
Y7
TP47
DVDD_GPMC
CVDD_DSP
R5
R7
T4
T6
T7
TP67
D
DVDD
DVDD
D16
E17
F16
L5
M4
M6
M7
N10
N11
T26
T28
U27
DVDD_C
D12
E13
F12
G12
G13
DVDD_SD
TP55
EVM_1V8
TP10
PLL_1V8
TP25
VDAC_1V8
TP26
VDDA_1V8
U25
T25
VDDA_1V8
VDDS_OSC1
VDDS_OSC0
TP49
P20
P21
VDDA_USB_1V8
TMS320DM385
C220
V9
L13
VDDA18_USB0
VDDA18_USB1
P15
P17
R15
R17
T13
T17
T18
U11
U12
U15
U17
V11
V12
V15
V17
W13
W14
W19
W20
Y13
Y14
Y19
Y20
C221
M19
M20
PLL_1V8
VDD_ARM1
VDD_ARM2
VDD_ARM3
VDD_ARM4
VDD_ARM5
VDD_ARM6
POWER
M24
0.1uF
K19
J17
VDAC_3V3
VDDA_AVDAC
VDDA_HDMI
K17
L17
L18
M13
M14
M17
CORE_VDD
0.1uF
VDDA_USB_1V8
D
CVDD_ARM
U55N
J14
K14
DVDD
U55H
VDAC_1V8
HDMI_CSI_1V8
TP39
VDDQ_1V5
TP72
DVDD_SD
C
C
TP89
DVDD_GPMC
HDMI_CSI_1V8
VDDA_USB_1V8
VDAC_1V8
VDAC_3V3
PLL_1V8
CVDD_ARM
CVDD_DSP
DVDD_C
DVDD_GPMC
DVDD_SD
C505
CORE_VDD
1nF C506
0.1uF
1nF C208
C497
1nF C214
C490
0.1uF
1nF C498
0.1uF
C206
C212
0.1uF
1nF C454
+
33uF_6.3V
1nF C485
1nF C180
C484
1nF C205
C528
0.1uF
C201
1nF C487
C453
0.1uF
C200
C529
0.1uF
0.1uF
C470
0.1uF
0.1uF
C544
0.1uF
0.1uF
C479
0.1uF
1nF C533
C522
0.1uF
C494
1nF C210
C461
0.1uF
C496
1nF C209
C184
0.1uF
C495
0.1uF
C539
0.1uF
0.1uF
C535
0.1uF
C187
0.1uF
33uF_6.3V
C172
0.1uF
1nF C182
C466
1nF C455
C511
0.1uF
1nF C176
C514
0.1uF
C168
0.1uF
33uF_6.3V
C458
C476
0.1uF
C190
C189
0.1uF
1nF C475
C504
0.1uF
0.1uF
C502
0.1uF
1nF
C477
1nF
TP19
1nF C541
1nF C173
1nF C521
1nF C532
C171
C185
0.1uF
1nF C516
C462
0.1uF
1nF C178
C471
0.1uF
1nF C472
C186
0.1uF
1nF C474
C463
0.1uF
1nF C520
C188
0.1uF
1nF C542
C175
0.1uF
1nF C473
C179
0.1uF
1nF C451
C538
0.1uF
+
33uF_6.3V
C452
0.1uF
C513
1nF C174
C515
C177
+
+
CORE_VDD
0.1uF
1nF C224
C507
0.1uF
1nF C527
C534
0.1uF
1nF C518
C526
0.1uF
1nF C207
C524
0.1uF
1nF C491
C523
33uF_6.3V
B
+
DVDD
0.1uF
33uF_6.3V
C215
VDDA_1V8
1nF C467
C503
0.1uF
1nF C183
0.1uF
C450
1nF C478
0.1uF
C181
1nF C464
C549
0.1uF
1nF C465
0.1uF
TP52
+
B
C557
C559
C242
C256
C248
C251
C255
C570
C243
C566
C562
C246
C547
C253
C244
C556
C552
C558
C567
C568
C540
C247
C555
C565
C560
C561
C252
C254
C245
C550
C543
C241
C569
C240
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C564
C553
33uF_6.3V
+
0.1uF
VDDQ_DM_1V5
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
DM385_POWER
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
102 Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVA_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
30
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-30. DM385 VSS
5
4
3
2
1
U55I
A1
A31
D8
D25
E7
E8
E21
E25
F7
F8
F20
F25
G4
G5
G6
G7
G8
G20
G23
G24
G25
G26
G27
H7
H26
J7
L16
M16
N13
N14
N16
N17
P11
P12
P14
P18
R11
R12
R14
R18
R20
R21
T11
T12
T14
T15
T16
T19
T20
T21
U14
U18
U23
V18
W16
W17
Y16
Y17
Y25
D
C
B
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VPP
VPP1
VSSA_AVDAC
VSSA_USB1-1
VSSA_USB1-2
VSSA_USB1-3
VSSA_HDMI-1
VSSA_HDMI-2
VSSA_CSI21-1
VSSA_CSI21-2
Y26
Y28
AA13
AA14
AA15
AA16
AA17
AA18
AA27
AC25
AD3
AD4
AD5
AD6
AD7
AD24
AD25
AE5
AE6
AE7
AE8
AE9
AE12
AE19
AE20
AE23
AE24
AE25
AE26
AE27
AE28
AF7
AF12
AF20
AF24
AF25
AG7
AG11
AG19
AG24
AG25
AH7
AH12
AH20
AL1
AL31
D
C
G17
TP119
SMD
TP120
SMD
G16
C8
D20
N19
N20
G9
H8
V14
AC7
B
TMS320DM385
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
DM385_VSS
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
2
Rev
B
Sheet
31
of
39
1
Schematics 103
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-31. TPS659113-A
5
4
3
2
1
VBACKUP
U25-1
R490
2K
TPS65911
TPS_EVM_5V0
BGA
TPS_LDO5_SPARE
M3
DCDC CTRL
DRVH
+
A8
A7
A2
DRVL
VFB
TRIP
A6
R488
C405
2.2uF
C390
C391 0.1uF
2.2uF
C77
C81 0.1uF
2.2uF
C129
C20
C21
C41
330uF_2V
BCK2_3V3
4
C5
C392 330pF
TP45
SOURCE
3
SOURCE
2
SOURCE
1
TPS659113_EVM_12V
5
TP3
GND_DC-DC
B3
R102
TPS_BCK2_3V3
39K_1%
GND_DC-DC
TP44
FDMC7660DC
VFB1
VDD1
SW1_a
SW1_b
SW1_c
D4
TPS_CVDD_ARM
E2
D2
D1
L7
2.2uH
D3
C2
C1
1.1V GENERATION FOR HD DAC
EVM_3V3
TPS_VHD_1V1
L9
2.2uH
J2
J1
GND_VDD2
VCCIO_a
VFBIO
GNDIO_a
GNDIO_b
K8
K7
L8
EN
OUT
NR/FB
5
4
TPS71711DCKR
B
C361
1nF
AGND2_a
AGND2_b
GND_VIO
N8
M8
AGND_a
AGND_b
AGND_c
AGND_d
AGND_e
AGND_f
AGND_g
AGND_h
AGND_i
AGND_j
AGND_k
D6
E6
E5
F5
G4
H6
J3
J4
J6
K3
H5
DGND_a
DGND_b
DGND_c
2.2uH
GND_VDD2
J8
J7
GND_VIO
GND
B2
B1
A1
C425 10uF
C423 0.1uF
IN
C120 10uF
SWIO_a
SWIO_b
VDDIO
C117 0.1uF
VIO
1.5V/1.8V/2.2V/3.3V-1500mA
GND_VIO
3
VCCIO_b
DVDD
N7
TPS_VDDA_1V8
H8
1
2
H2
H1
1uF
GND_VDD1
SW2_a
SW2_b
GND2_a
GND2_b
C336 0.1uF
Output range 0.6V/1.5V-1.5A
U85
C325
K2
GND
VFB2
C346 0.1uF
VDD2
C111 10uF
VCC2_a
VCC2_b
1uF C342
TPS_CVDD_DSP
C112 0.1uF
G2
G1
C103 10uF
C101 0.1uF
C414 10uF
C100 0.1uF
C413
+
GATE
0E
Output range 0.6V/1.5V-1.5A
GND1_a
GND1_b
GND1_c
L7
C118 10uF
C
TPS_BCK2_3V3
L8
C121 0.1uF
2.2uH
B4
GND_VDD2 TPS_BCK2_3V3
GND_VIO
C19
C127
C116 0.1uF
C126
L6
C69 0.1uF
C402 10uF
C88 0.1uF
C403 0.1uF
GND_DC-DC
TPS_CORE_VDD
GND_VDD1
B
DRAIN
GND_DC-DC
TPS_BCK2_3V3
GND_VDD1
5
FDMC7660DC
C393 0.1uF
SMPS
C86 10uF
1
0E
TPS_CORE_VDD
GND_DC-DC
GND_DC-DC
C87 0.1uF
2
SOURCE
A4
GND_CTRL_b
VCC1_a
VCC1_b
VCC1_c
3
SOURCE
Q2
GND_CTRL_a
VOUT
F3
F2
E1
SOURCE
AGND
C70 10uF
1uF_16V
SW
C64
C76 0.1uF
VBST
4
AGND
TPS_EVM_5V0
V5IN
Q1
GATE
AGND
A3
R489
A5
AGND
TPS659113_EVM_12V
1uF
TP23
TP37
TP18
4.7uF
C6
D5
C4
AGND
1uF
TRAN
EN
PGOOD
External FET range 0.6V/1.45V-6A
C
C115 0.1uF
VCCS
C404
E8
4.7uF
C406 0.1uF
0E
TPS_HDMI_CSI_1V8
N4
4.7uF
C424
4.7uF
C420 0.1uF
TPS_EVM_5V0
N6
AGND
AGND
AGND
TPS_VDAC_1V8
LDO1
VCC6
LDO2
R496
D
TPS_GPIO_3V3
TPS_VDD_CDC
M2
C134
LDO6
BCK2_3V3
M1
C130 0.1uF
TPS_PLL_1V8
TPS_LDO5_SPARE
K1
2.2uF
C8
C133 0.1uF
LDO7
N5
VRTC
1uF
LDO8
E7
2.2uF
N3
TPS_PLL_1V8
C24
VCC3
TPS_GPIO_3V3
C23 0.1uF
LDO5
B5
10uF
VCC4
TPS_LDO7_SPARE
TPS_USB_1V8
C419
C418 0.1uF
C125 4.7uF
LDO3
VCC5
4.7uF
C89 0.1uF
C400 4.7uF
VRTC
LDO4
L1
C114 0.1uF
VCC7
C407 0.1uF
D8
TPS_EVM_5V0
TPS_USB_1V8
VRTC
2.2uF
B6
TPS_EVM_5V0
VBACKUP
C426
TP31
C427 0.1uF
D7
2.2uF
C71 0.1uF
D
AGND
R170
0E_1%
A
A
GND_VIO
NATURE OF CHANGE
REV NO.
GND_VDD2
GND_VDD1
GND_DC-DC
APPROVED BY
AGND
DATE
Mistral Solutions [P] Ltd.
Title
TPS659113-A
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
104 Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVA_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
32
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-32. TPS659113-B
5
4
3
2
1
U25-2
TPS65911
D
TP42
D
C95
AGND_XTAL
C90
22pF
22pF
2
0E
R128
1
BGA
R125
Y1
32.768KHz
R123
0E
0E
F8
F7
OSC32KIN
CLK32KOUT
CLOCK
F4
R497
0E
CLK32OUT
14,27
OSC32KOUT
23pF
TP38
AGND_XTAL
REFERENCE
G8
C409
VREF
0.1uF
G7
C
TPS_EVM_5V0
TPS_EVM_5V0
R39
10K
20,21,28,8,9
20,21,28,8,9
R158
R157
I2C0_SDA
I2C0_SCL
M6
M7
TP59
TP56
R12
10K
DNI
N1
TP60
SW2
R498
A
A1
AGND_XTAL
0E
M5
M4
0E
B
B1
10K
N2
L6
VRTC
REFGND
GPIO
SDA
SCL
GPIO1
EN2
EN1
GPIO2
GPIO3
PWRHOLD
GPIO4
PWRDN
HDRST
CONTROL
PMIC RST
R11
100K
R487
GPIO5
GPIO6
EVQ9P105M
R49
0E
DNI
C
GPIO0
J5
10K
GPIO7
BOOT1
GPIO8
L5
F6
0E
EN_TPS51116
R160
0E
EN_BCK3_TPS65232
34
TP34
L2
B7
TP29
H7
TP54
G6
TP50
G3
TP63
L4
R141
R162
K5
35
TPS_GPIO_3V3
R163
10K
0E
EN_BCK2_LS
35
TP58
DVDD
VDD_CDC
B
E4
TP35
NRESPWRON1
PWRON
NRESPWRON2
21
TPS_SLEEP
F1
INT1
H4
C7
L3
TP64
R103
R164
B
R104
10K
R218 DNI 0E
0E
0E
nRESPWRON2
TPS_INT1
27
21,30
SLEEP
TEST
TEST
B8
TP30
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
TPS659113-B
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
2
Rev
B
Sheet
33
of
39
1
Schematics 105
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-33. TPS51116
5
D
4
3
2
1
D
VDDQ_SET
TPS_VDDQ_1V5
VDDQ_SET
TPS_EVM_5V0
TPS51116_EVM_12V
+5V
+12V
Q5
JP1
1
2
3
5
TPS_VDDQ_1V5
0.1uF C149
R234
75K_0.1%
100uF C142
100uF C135
TPS_VDDQ_1V5
HDR_3X1
R233
75K_0.1%
PGOOD
VTTSNS
VTT
VTTREF
NC1
NC2
22
1
2
V5FILT
3
12.1K_1%
TPS_VDDQ_1V5
C
C439 0.1uF
21
L12
4.7uH
19
13
PGOOD
TPS_VREF
24
C140
DRVL
VLDOIN
R501
20
4
8
V5FILT
TPS51116
TPS_EVM_5V0
9
DRVH
VTTGND
10uF C154
4.7uF C169
22uF C163
TP70
0.1uF C158
2
22uF C160
DNI
10K R243
23
V5IN
16
C152
1nF
+
Q4
VD_VREF
5
330uF_2V
14
VBST
6
5
V5FILT
LL
S5
GND
R235
5.1E_1%
TPS_VDDQ_1V5
CS
TAB
15
COMP
R197
1.5E
7
12
C167
0.033uF
25
11
VDDQSET
S5
VDDQSNS
R247 0E
S3
PGND
10
CS_GND
S3
18
R242 0E
MODE
17
4
3
4.7uF C164
TPS_VREF
S3
0.1uF C165
DNI
U46
TPS_EVM_5V0
10K R244
TPS_EVM_5V0
C
CSD16406Q3
EN_TPS51116
1
33
B
1
2
4
CURRENT MONITOR
10K R245
DNI
3
V5FILT
CSD16406Q3
R502
100K
B
S5
10K R246
PGOOD
DNI
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
TPS51116
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
106 Schematics
2
Rev
B
Sheet
34
of
39
1
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix A
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Figure A-34. TPS65232
5
4
3
2
1
TPS65232_EVM_12V
TPS_EVM_5V0
Place close to input pins
C85
C56
C92
C53
10uF
10uF
10uF C107
10uF
10uF
0.1uF
CMP2
20K
CMP3
32
V3P3
17
0E
HDRV
1
4.7uH
22uF C145
BG
18
R130
PH1
V6V
19
C401 0.22uF
6
5
L11
BST1
SS
16
0E
LDRV
D
EN_BCK1
22
Q3B
FB1
EN_BCK2
21
CMP1
3
FDS6982
24
TRIP
EN_BCK3
25
C57
1
C398 1uF
3
C396 1uF
23
C394 3300pF
20
C99
7
C395 1nF
33
C388 1nF
1uF
C38
C46
C42
1nF
1nF
PGND2.1
PGND2.2
DGND
PWR PAD
AGND.13
AGND.12
AGND.11
AGND.10
AGND.9
AGND.8
AGND.7
AGND.6
AGND.5
AGND.4
AGND.3
AGND.2
AGND.1
PGND3.2
PGND3.1
G
S
B
8
9
15
49
48
47
46
45
44
43
42
41
30
29
28
27
26
35
34
22.1K_1%
B
R178
4
1nF C137
22uF C144
R131
100pF
2
G
FDS6982
C
C51
Q3A
S
C36
31
0.1uF
37
6.98K_1%
R136
D
TPS_EVM_5V0
R64
12
13
39
38
2.2uH
100pF
6
C102 1nF
FB3
L5
R75
C94
PH3.2
BST2
C389 0.1uF
36
20K
8
7
C
22uF C122
22uF C123
TPS65232_EVM_12V
PH2.2
40
C39
14
C399 0.1uF
PH3.1
22uF
11
2.2uH
BST3
PH2.1
22uF
L10
FB2
1nF
10
R74
BCK2_3V3
0.001E_1%
TPS_PCI_3V3
22.1K_1%
5
TPS_BCK2_3V3
R145
D
VINB3.2
VINB3.1
VINBQ
4
100uF
Place close to input pins
2
U16
C83
22.1K_1%
C108 1nF
VIN
R142
D
VINB2.1
VINB2.2
6.98K_1%
1uF C397
R135
C73
TPS_EVM_5V0
EN_BCK3_TPS65232
33
R173
4.22K_1%
MIC94062YC6
C93
C78
1nF
C693
C692
TP61
1nF
1
4.7uF
NC
VOUT
0.1uF
EN
2
6
VIN
GND2
3
GND1
EN_BCK2_LS
5
4
33
215K_1% R107
LS_EVM_3V3
U27
100pF
C91 20K R119
TPS65232A2DCAR
BCK2_3V3
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
TPS65232
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Monday, March 05, 2012
3
2
Rev
B
Sheet
35
of
39
1
Schematics 107
SPRUI85 – August 2016
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Appendix A
www.ti.com
Figure A-35. Power Selection
4
3
2
1
I_MON_DVDD_GPMC_HIGH
29
5
D
PCI_3V3 SW
IP_EVM_12V
LDO_EVM_1V8
EVM_1V8
TPS51116_EVM_12V
TPS_USB_1V8
TPS_PCI_3V3
IP_EVM_12V
R3
VDDA_USB_1V8
PCI_3V3
TPS_VDD_CDC
VDAC_3V3
TPS659113_EVM_12V
DVDD_GPMC
D
R138
0.025E_1%
0.001E_1%
R15
0.001E_1%
R40
0.01E_1%
R66
0.01E_1%
R114
EVM_3V3
0.01E_1%
R95
EVM_1V8
0.01E_1%
R137
0.01E_1%
R115
DNI
0.01E_1%
TPS65232_12V SW
3
PLL_1V8
HDMI_CSI_1V8
R101
0.025E_1%
TPS_VDD_CDC
29
EG-1218
1
VDD_CDC
I_MON_DVDD_HIGH
SW3
2
I_MON_PLL_1V8_HIGH
TPS65232_EVM_12V
IP_EVM_12V
29
29
I_MON_HDMI_CSI_1V8_HIGH
OVERLAP THESE TWO PADS
R69
0.025E_1%
R232
0.01E_1%
TPS_HDMI_CSI_1V8
EVM3V3 SW
R99
EVM_3V3
0.025E_1%
EVM_1V8
TPS_PLL_1V8
0.01E_1%
C
EVM_3V3
EXP_EVM_3V3
R70
TPS_VDAC_1V8
0.01E_1%
R139
VDAC_1V8
0.01E_1%
R117
DNI 0.01E_1%
OVERLAP THESE TWO PADS
SW6
R187
R140
EVM_3V3
C
LS_EVM_3V3
DVDD
3
0.01E_1%
2
1
EVM_5V0
CORE_VDD
R59
0.008E_1%
29
0.01E_1%
CVDD_ARM
I_MON_DVDD_C_HIGH
29
I_MON_CORE_VDD_HIGH
EVM_5V SW
EVM_5V0
29
I_MON_CVDD_ARM_HIGH
R81
EG-1218
R112
0.025E_1%
TPS_VHD_1V1
VHD_1V1
TPS_CORE_VDD
EXP_EVM_5V0
R150
0.025E_1%
EVM_3V3
TPS_EVM_5V0
EVM_1V8
TPS_CVDD_ARM
SW8
R30
0.001E_1%
R476
0E
3
R167
4W RESISOTR
2
R207
DVDD_C
R91
0.01E_1% R151 DNI
0.01E_1%
OVERLAP THESE TWO PADS
0.01E_1%
1
0.01E_1%
SWITCH POSITION
POSITION FOR APPLICATION BOARDS
SWITCH
VCAM
VCON
VS
VDDA_1V8
R116
0.025E_1%
CVDD_DSP
R165
0.025E_1%
B
29
I_MON_CVDD_DSP_HIGH
I_MON_VDDA_1V8_HIGH
29
B
VDDQ_DM_1V5
VMMC
I_MON_VMMC_HIGH
29
I_MON_VDDQ_DM385_1V5_OUT_HIGH
29
EG-1218
R205
0.025E_1%
TPS_VDDA_1V8
CAT
TPS_CVDD_DSP
VDDQ_1V5
R400
0.025E_1%
TPS_VDDQ_1V5
EVM_3V3
SW6
1
3
3
1
R80
R147
SW8
1
3
3
EVM_1V8
0.01E_1%
0.01E_1%
R575
0.01E_1% R188
0.01E_1%
R565
0.01E_1% R566 DNI
0.01E_1%
3
3
THE NUMBER INDICATE THE POSITION OF
SWITCH AS IN DIAGRAM
2
1
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
POWER SELECTION
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
108 Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVA_SCH
Wednesday, January 25, 2012
Rev
B
Sheet
36
of
39
1
SPRUI85 – August 2016
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Appendix A
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Figure A-36. Power In
5
4
3
2
TP1
THRU HOLE
D
D6
IP_EVM_12V
D
SW1
F1
4A
3
1
2
J5
CON_PWRJACK3_RAPC712
1
2
2
LD1
2
7201MD9AQE
C35
C34
1uF
DPDT
10uF
+12V DC JACK
C7
5
4
SMCJ15CA
C10
1
D1
0.1uF
6
B520C-13-F
0.1uF
TP107
R2
2K
C30
1
+
47uF_20V
2
2
3
1
1
1
PWR ON SW
LTST-C150GKT
C
C
TP57
TP11
1
2
3
4
5
6
B
DM385 SOCKET
NAND SOCKET
ACC2
ACC1
TP103
TP68
TP114
1
2
3
4
5
6
1
2
TP113
1
2
TP96
TP7
C10738
B
TP69
SKT-02-0406
TP88
TP2
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
POWER IN
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVA_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
2
Rev
B
Sheet
37
of
39
1
Schematics 109
SPRUI85 – August 2016
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Appendix A
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Figure A-37. Changes in Schematics
5
SL NO#
4
3
2
CHANGES IN THE SCHEMATICS COMPARED TO CENTAURUS.
SL NO#
1
CHANGES IN THE SCHEMATICS COMPARED TO CENTAURUS.
1
MLB SIGNALS ARE REMOVED.
39
CLOCK DRIVER IC
2
ONE MORE SATA (SATA1) CONNECTOR ADDED.
40
3
S-VIDEO SIGNALS REMOVED.
CODEC SIGNALS FROM MCASP MUXING STAGE IS PASSED THROUGH BUFFER ICs SN74AVCH1T45DBVR
(U19,U20,U21) & SN74AVCH2T45DCTR (U22). BUFFER ICs ARE MADE DNI.OE RESISTOR OPTION IS GIVEN
TO BYPASS THE BUFFER STAGE.
IDT74FCT38075DCGI(U65) IS CHANGED TO CDCV304PW.
4
NEW DDR PART IS ADDED(ONLY FOR DDR0). DDR1 IS REMOVED.
41
RESISTOR DIVIDER CKT TO GET VREF FOR DDR INTERFACE IS REMOVED AND VD_VREF IS TAKEN FROM
TPS51116(PIN 5) DIRECTLY.
5
COMPOSITE VIDEO SIGNALS ARE TAKEN THROUGH VIDEO AMPLIFIER IC PROVIDING OPTION
FOR DIRECT CONNECTION.
42
A15 & B15 SIGNALS ARE SWAPPED.N30 & N31 SIGNALS ARE SWAPPED.P20 & P21 ARE CHANGED FROM VSS TO
VDDS_OSC1 & VDDS_OSC0 respectively.
6
HDDAC SIGANLS ARE CONNECTED TO VIDEO AMPLIFIER THS7360IPW AND THEN THE OUTPUT ARE
CONNECTED TO VGA CONN AND ALSO TO COMPONENT VIDEO CONNECTORS(RGB).
43
TESTPOINTS TP128,TP129 & TP130 ARE REMOVED AND J25,H24 & H28 OF DM385 IS MADE NC.
7
27 MHz CRYSTAL IS ADDED INSTEAD OF 22.579MHz.
44
GPIO_VS_1 FROM IO EXPANDER-2 IS ADDED TO COMPENSATE FOR MLBP_CLKp SIGNAL ON CENTAURUS.
THIS SIGNAL IS USED AS GPIO ON VS BOARD.
8
IO EXPANDER-3 WITH I2C2 ADDRESS 0X20 IS ADDED.
INTERRUPT PCF8575_INT_VA FROM THIS IC IS GIVEN TO SD0_DAT[6]/GP0[12].
45
HDMI ESD SUPPRESSOR TPD12S016RKTR IS ADDED INSTEAD OF TPD12S521DBTR.
HDMI_CT_HPD AND HDMI_LS_OE SIGNALS ARE TAKEN FROM NEWLY ADDED IO EXPANDER-2 WHOSE
INTERRUPT IS CONNECTED TO SD0_DAT[7]/GP0[13].
AN OR-GATE(U53) IS ADDED TO ENABLE THE WAKE-on-LAN FUNCTIONALITY OF ATHEROS CHIP.
PCF8575_INT_VA INTERRUPT FROM IO EXPANDER-3 IS TERMINATED TO A TESTPOINT.INSTEAD OF THIS SIGNAL,
ENET_WoL_INT INTERRUPT IS CONNECTED TO GP0[12] OF DM385.
9
46
C64 IS CHANGED TO PART NO# F931C105MAA. RJ-45 SYMBOL UPDATED.
FL10,FL11,FL12,FL13 (TCE1210) IS REPLACED WITH TCM1210.
47
TPD2E001(U122) ESD PROTECTION DEVICE FOR COMPOSITE VIDEO SIGNAL IS ADDED.
TPD3E001(U123) ESD PROTECTION DEVICE FOR COMPONENT VIDEO SIGNALS IS ADDED.
48
R59 IS CHANGED TO 8mE.
49
INA226 DEVICES ARE ADDED TO MONITOR DVDD,DVDD_C AND VMMC
50
PLL_1V8,HDMI_CSI_1V8 & DVDD_GPMC POWER LINES ARE MONITORED INSTEAD OF BCK2_3V3,EVM_5V0
& VDDQ_1V5 POWER LINES USING U10,U15 & U24 RESPECTIVELY.
51
20MHz CRYSTAL (Y3) IS CHANGED TO SMALLER SIZE PACKAGE CRYSTAL WITH PN# 403C11A20M00000.
52
L6 IS CHANGED FROM 2.7uH TO 2.2uH. Q1 & Q2 IS CHANGED TO FDMC7660DC FROM FDS8812NZ.
53
R179 & R427 ARE REMOVED FROM THE DESIGN.
D
D
10
MCASP0 AND MCASP1 MUXING IS ADDED. 2:4 DECODER IS USED TO ENABLE SWITCHING.
IO EXPANDER-2 IS USED TO ENABLE DECODER.
11
EXPANSION CONNECTOR( DRI ) TO GET POWER TO THE BB IS REMOVED.
POWER SELETION SECTION IS MODIFIED ACCORDINGLY.
12
OPTION TO SELECT I2C2 OR UART2 SIGNALS IS PROVIDED.BUFFERS USED ARE ENABLED
BY I2C2/UART2_SEL SIGNAL FROM IO EXPANDER-1.
13
SINCE THE MLB_DAT AND MLB_SIG IS NOT AVAILABLE IN DM385 TWO GPIOs FROM IO EXPANDER -2
IS GIVEN TO EXPANSION CONNECTOR WHICH ARE USED AS GPIOs ON THE CATLOG BOARD.
14
POWER VDDQ_CENT_1V5 IS CHANGED TO VDDQ_DM_1V5
C
15
B
SATA INDICATOR LED IS ADDED.
16
MCA_AXR[6:8] SIGNALS ARE REMOVED FROM THE CONNECTOR SIDE.
17
MCA_AXR[9] SIGNAL WHICH IS USED AS GPIO IN VC BOARD IS TAKEN FROM IO EXPANDER-2
18
BUS FET SWITCH IS ADDED THROUGH WHICH UART0 SIGNALS ARE CONNECTED TO EXPANSION CONNECTOR.
19
I2C2 BUFFER IS ADDED AND SIGNALS ARE GIVEN TO IO EXPANDER-3 AND VGA CONNECTOR.
20
POWER MONITORING IC INA220 IS UPDATED WITH INA226.
21
SN74CBTLV3384PW(U3 & U40) ICs ARE REPLACED WITH SN74CB3Q3257PWR.DECODER USED
FOR MCASP1 MUXING IS REMOVED.
22
R399,R392,R254,R248,R522 ---0E RESISTORS ARE REPLACED WITH 22E.
R579,R494 ARE REMOVED.
23
PCA9306(U85 & U102) ICs ARE REPLACED WITH TCA4311A.
24
OPTION FOR SELECTING MCA5_AFSR/AXR0 OR GPIOs FOR VC BOARD FROM IO EXPANDER-2 IS
PROVIDED USING MUX.
25
GPIO (IO_EXP2_GP3) FROM IO EXPANDER-2 IS PROVIDED TO COMPENSATE FOR MLB_CLK SIGNAL.
26
0E OPTION IS GIVEN FOR VIN[0]A_VSYNC/GP2[4](C13).0E OPTION IS GIVEN FOR VIN[0]A_HSYNC/GP2[3] (D13)
27
IO EXPANDER-1 INTERRUPT PCF8575_INT_IO1 IS CHANGED FROM GP1[8] TO GP1[4].
28
MUXING OPTION IS GIVEN TO SELECT DIFFERENT FUNCTIOS OF VOUT0/1_FLD PINS.ONE MORE DECODER
IS ADDED TO SELECT ONE FUNCTION AT A TIME.
29
I2C2/UART2_SEL SIGNAL IS REMOVED FROM THE IO EXPANDER-1 & IS TAKEN FROM DECDER WHICH BY DEFAULT
SELECT VOUT0/1_FLD SIGNAL.
30
IO EXPANDER-1 INTERRUPT IS TAKEN FROM GP1[4] INSTEAD OF GP[8].
31
U68 & ITS BIASING CIRCUITRY (1.2V FOR TPS_CVDD_HDVICP) OF CENTARAUS IS REMOVED
AND ALSO U22(INA226) IS REMOVED
32
TPS71711DCKR IS ADDED NEWLY TO GENERATE 1.1V FOR HD DAC
33
TPD6E001 ESD SUPPRESSOR IS ADDED
34
INA220 IS UPDATED TO INA226
35
U80,U81,U106 & U112 ARE DELETED.TPD7S019 (U7) IS ADDED.
36
RA86 IS REPLACED WITH 0E SERIES RESISTORS. R476 PACKAGE ISCHANGED TO 0402.
37
EN_TPS62350 SIGNAL FROM TPS659113 IS REMOVED AS WE HAVE HAVE REMOVED TPS62350 IC.
38
Q6 & Q7 ARE REMOVED.SN74LVC2G06DCK(U86) IS ADDED IN THE SATA LED INDICATOR SECTION.
Y6 CRYSTAL MA-506 27.0000M-C0: (FUND):ROHS IS REPLACED WITH NEW PART ABM8-27.000MHZ-B2-T.
C
B
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
DATE
Mistral Solutions [P] Ltd.
Title
SCH_CHANGES
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80-2535 6444
Drawn by: MISTRAL DESIGN TEAM
Date: Monday, May 31, 2010
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Design file path: D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
5
4
3
110 Schematics
2
Size
C
Date:
Document Number
MS_TI_DM385EVM_REVB_SCH
Rev
B
Sheet
Tuesday, January 24, 2012
38
of
39
1
SPRUI85 – August 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Appendix A
www.ti.com
Figure A-38. DDR3_TP
5
4
16,17
DDR0_CKE
TP_DDR0_CKE
SMD
TP_DDR1_CKE
SMD
TP_DDR2_CKE
SMD
TP_DDR3_CKE
SMD
16,17
DDR0_CLK0
TP_DDR0_CLK0
SMD
TP_DDR1_CLK0
SMD
TP_DDR2_CLK0
SMD
TP_DDR3_CLK0
SMD
16,17
3
TP_DDR0_BA2
SMD
TP_DDR1_BA2
SMD
TP_DDR2_BA2
SMD
TP_DDR3_BA2
SMD
DDR0_BA2
2
16,17
DDR0_A6
TP_DDR0_A6
SMD
TP_DDR1_A6
SMD
TP_DDR2_A6
SMD
TP_DDR3_A6
SMD
16,17
DDR0_A7
TP_DDR0_A7
SMD
TP_DDR1_A7
SMD
TP_DDR2_A7
SMD
TP_DDR3_A7
SMD
1
16,17
TP_DDR0_A14
SMD
TP_DDR1_A14
SMD
TP_DDR2_A14
SMD
TP_DDR3_A14
SMD
DDR0_A14
D
D
16,17
16,17
TP_DDR0_CLK0N
SMD
TP_DDR1_CLK0N
SMD
TP_DDR2_CLK0N
SMD
TP_DDR3_CLK0N
SMD
DDR0_CLK0N
TP_DDR0_RASn
SMD
TP_DDR1_RASn
SMD
TP_DDR2_RASn
SMD
TP_DDR3_RASn
SMD
DDR0_RASn
C
16,17
16,17
TP_DDR0_CASn
SMD
TP_DDR1_CASn
SMD
TP_DDR2_CASn
SMD
TP_DDR3_CASn
SMD
DDR0_CASn
TP_DDR0_WEn
SMD
TP_DDR1_WEn
SMD
TP_DDR2_WEn
SMD
TP_DDR3_WEn
SMD
DDR0_WEn
B
16,17
16,17
TP_DDR0_CSN0
SMD
TP_DDR1_CSN0
SMD
TP_DDR2_CSN0
SMD
TP_DDR3_CSN0
SMD
DDR0_CSN0
TP_DDR0_BA0
SMD
TP_DDR1_BA0
SMD
TP_DDR2_BA0
SMD
TP_DDR3_BA0
SMD
DDR0_BA0
16,17
DDR0_BA1
TP_DDR0_BA1
SMD
TP_DDR1_BA1
SMD
TP_DDR2_BA1
SMD
TP_DDR3_BA1
SMD
16,17
DDR0_A0
TP_DDR0_A0
SMD
TP_DDR1_A0
SMD
TP_DDR2_A0
SMD
TP_DDR3_A0
SMD
16,17
16,17
DDR0_A1
TP_DDR0_A1
SMD
TP_DDR1_A1
SMD
TP_DDR2_A1
SMD
TP_DDR3_A1
SMD
16,17
DDR0_A2
TP_DDR0_A2
SMD
TP_DDR1_A2
SMD
TP_DDR2_A2
SMD
TP_DDR3_A2
SMD
16,17
DDR0_A3
TP_DDR0_A3
SMD
TP_DDR1_A3
SMD
TP_DDR2_A3
SMD
TP_DDR3_A3
SMD
16,17
DDR0_A4
TP_DDR0_A4
SMD
TP_DDR1_A4
SMD
TP_DDR2_A4
SMD
TP_DDR3_A4
SMD
16,17
DDR0_A5
TP_DDR0_A5
SMD
TP_DDR1_A5
SMD
TP_DDR2_A5
SMD
TP_DDR3_A5
SMD
16,17
16,17
TP_DDR0_A8
SMD
TP_DDR1_A8
SMD
TP_DDR2_A8
SMD
TP_DDR3_A8
SMD
DDR0_A8
NOTE:
1) Through Hole Test points are used to
check compliance with the routing guidelines.
This helps to generate the Net length Report.
2) Designers need to replace Test point with
a Via of the same size.
TP_DDR0_A9
SMD
TP_DDR1_A9
SMD
TP_DDR2_A9
SMD
TP_DDR3_A9
SMD
DDR0_A9
16,17
DDR0_A10
TP_DDR0_A10
SMD
TP_DDR1_A10
SMD
TP_DDR2_A10
SMD
TP_DDR3_A10
SMD
16,17
DDR0_A11
TP_DDR0_A11
SMD
TP_DDR1_A11
SMD
TP_DDR2_A11
SMD
TP_DDR3_A11
SMD
16,17
DDR0_A12
TP_DDR0_A12
SMD
TP_DDR1_A12
SMD
TP_DDR2_A12
SMD
TP_DDR3_A12
SMD
16,17
DDR0_A13
TP_DDR0_A13
SMD
TP_DDR1_A13
SMD
TP_DDR2_A13
SMD
TP_DDR3_A13
SMD
TP_DDR0_ODT
SMD
TP_DDR1_ODT
SMD
TP_DDR2_ODT
SMD
TP_DDR3_ODT
SMD
DDR0_ODT0
C
B
A
A
NATURE OF CHANGE
REV NO.
APPROVED BY
Mistral Solutions [P] Ltd.
DATE
Title
DDR3_TP
#60 Adarsh regent,100 Feet Ring Road, Domlur Extension
Bangalore 560 071, Ph : +91-80-30912600, Fax :+91-80
-2535 6444
MISTRAL DESIGN TEAM
Drawn by:
Date:
Monday, May 31, 2010
Design file path:
5
4
Approved by:
Date
KRISHNA PRASAD A
Monday, August 08, 2016
Size
B
Document Number
MS_TI_DM385EVM_REVB_SCH
D:\SVN\TI_DM3XX_50\07_HARDWARE\SCsEMATICS\DM385\MS_TI_DM385EVM_REVB_SCH.DSN
Date:
Tuesday, January 24, 2012
3
2
Rev
B
Sheet
39
of
39
1
Schematics 111
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix B
SPRUI85 – August 2016
Assembly Drawings
The assembly prints for the DM388 device are the same as the assembly prints for the DM385 device.
Figure B-1 and Figure B-2 show the assembly prints.
112
Assembly Drawings
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix B
www.ti.com
Figure B-1. Assembly Drawing (Top Side)
Assembly Drawings 113
SPRUI85 – August 2016
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Copyright © 2016, Texas Instruments Incorporated
Appendix B
www.ti.com
Figure B-2. Assembly Drawing (Bottom Side)
D11
C383
C384
D10
D9
C385
D8
C386
R487
R494
R495
U89
R492
R491
U88
TP116
C405
C414
R496 C409
C413
C424
C425
C412
C411
C410
C416
C417
C415
C421
C422
R498
C420
C423
C408
C419
C418
R497
C407
C406
R493
R490
C402
C403
R488
R489
TP115
C391
C392
C393
C400
C404
C397
C390
C398
C395
C389
C399
C396
C394
C401
C388
R579
C387
C426
C427
J28
J27
C428
R499
R500
U90
TP117
C429
C430
RA43
TP118
U91
C432
C434
RA44
C431
U92
C435
C440
C437
C441
R501
C448
C447
RA45
C446
C444
C445
C443
C449
R503
R511
R504
R505
R506
R517
R528
C488
R529
C517
C489
C500
R532
R530
C501
R536
C482
C481
R525
R527
C480
C490
R287 R524
R581
C491 R531
C519
R533
R537
C530
R541
R544
R542
C551
R547
R548
R546
C554
R550
C545
C573
R554
C570
C574
R551
C564
C572
C478
C539
C544
C547
C558
C559
C553
C561
C567
C560
C565
C566
C571
R553
C557
R552
C563
R545
R549
C555
J31
C552
R540
R543
C568
R538
R539
C548
C439
R502
R521
R523
C484
C485
C487
C497
C498
C507
C518
C562
C502
C511
C524
C526
C533
C541
TP119
TP120
R520
R526
C504
C514
C522
C529
C535
C516
C515
C523
C520
C527
C534
C538
C540
C542
C543
C549
C550
C503
C513
C521
C528
C532
C569
C494
C495
C496
R534
R535
C499
C512
C506
C505
C508
C509
C510
C537
C531
C536
C492
C493
C546
C486
C477
C475
C476
R519
R522
C483
C556
C473
C474
R518
C479
J30
R515
C465
C467
C466
R516
C525
R514
C468
C472
C471
C470
R512
R509
R510
C450
C455
C451
C452
C453
C454
C458
C461
C462
C463
C460
C459
C457
C469 C456
R513
R508
R507
J29
C442
C438
C436
C433
C575
C579
R556
C609
C641
C662
C681
R573
R574
R571
R572
R567
R569
R570
C685
C680
RA54
C664
RA55
C654
C661
C667
C666
C651
C657
C660
RA56
C592
C600
C608
C607
C639
C624
C627
C615
C635
C634
C648
C655
C677
C682
C684
C603
C585
C594
C591
C646
C614
C590
C596
C613
C602
C618
C633
C638
C626
C671
C676
C632
C643
C672
C656
RA53
C673
C645
C619
C612
C636
C644
C611
C625
C647 C650
C659
C674
C589
C588
C601
C630 C628
C582
C583
RA46
RA48
C670
C658
C678
C598
C631
C595
C610
C622
C623
C605
C606
C617
C652
C649
C663
C669
C629
RA47
RA52
C668
R460
RA51
C586
C683
R456
C597
C593
C642
C665
C675
C679
C587
C599
C604
C637 C621
C640
R461
20
C6
C616
R458
R462
RA50
RA49
R459
C653
R568
C578
C580
R564
R455
R454
C691
C576
R559
R566
C584
R560
R561
R562
C577
R565
R563
U93
C581
R558
R555
U94
R557
C686
C687
114 Assembly Drawings
SPRUI85 – August 2016
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