Texas Instruments | OMAP-L138 C6000 DSP ARM Processor (Rev. C) | User Guides | Texas Instruments OMAP-L138 C6000 DSP ARM Processor (Rev. C) User guides

Texas Instruments OMAP-L138 C6000 DSP ARM Processor (Rev. C) User guides
OMAP-L138
C6000 DSP+ARM Processor
Technical Reference Manual
Literature Number: SPRUH77C
April 2013 – Revised September 2016
Contents
Preface....................................................................................................................................... 81
1
Overview ........................................................................................................................... 82
1.1
1.2
1.3
2
ARM Subsystem ................................................................................................................. 85
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
3.3
3.4
93
94
94
94
99
99
99
99
Introduction ................................................................................................................ 101
System Interconnect Block Diagram ................................................................................... 102
Introduction ................................................................................................................
ARM Memories ............................................................................................................
DSP Memories ............................................................................................................
Peripherals .................................................................................................................
104
104
104
105
Memory Protection Unit (MPU) ........................................................................................... 106
6.1
6.2
2
Introduction ..................................................................................................................
TMS320C674x Megamodule .............................................................................................
3.2.1 Internal Memory Controllers .....................................................................................
3.2.2 Internal Peripherals ...............................................................................................
Memory Map ................................................................................................................
3.3.1 DSP Internal Memory .............................................................................................
3.3.2 External Memory ..................................................................................................
Advanced Event Triggering (AET) .......................................................................................
System Memory ................................................................................................................ 103
5.1
5.2
5.3
5.4
6
86
87
87
88
89
89
90
90
90
91
System Interconnect ......................................................................................................... 100
4.1
4.2
5
Introduction ..................................................................................................................
Operating States/Modes ...................................................................................................
Processor Status Registers ...............................................................................................
Exceptions and Exception Vectors .......................................................................................
The 16-BIS/32-BIS Concept ..............................................................................................
16-BIS/32-BIS Advantages ...............................................................................................
Co-Processor 15 (CP15) ..................................................................................................
2.7.1 Addresses in an ARM926EJ-S System ........................................................................
2.7.2 Memory Management Unit (MMU) ..............................................................................
2.7.3 Caches and Write Buffer ........................................................................................
DSP Subsystem ................................................................................................................. 92
3.1
3.2
4
Introduction .................................................................................................................. 83
DSP Subsystem ............................................................................................................ 83
ARM Subsystem ............................................................................................................ 83
Introduction ................................................................................................................
6.1.1 Purpose of the MPU .............................................................................................
6.1.2 Features ...........................................................................................................
6.1.3 Block Diagram ....................................................................................................
6.1.4 MPU Default Configuration .....................................................................................
Architecture ................................................................................................................
6.2.1 Privilege Levels ..................................................................................................
6.2.2 Memory Protection Ranges ....................................................................................
6.2.3 Permission Structures ...........................................................................................
6.2.4 Protection Check .................................................................................................
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6.3
7
111
111
112
112
112
112
113
115
115
116
117
118
118
119
119
120
121
122
123
124
125
126
Device Clocking................................................................................................................ 127
7.1
7.2
7.3
8
6.2.5 DSP L1/L2 Cache Controller Accesses .......................................................................
6.2.6 MPU Register Protection .......................................................................................
6.2.7 Invalid Accesses and Exceptions ..............................................................................
6.2.8 Reset Considerations ...........................................................................................
6.2.9 Interrupt Support .................................................................................................
6.2.10 Emulation Considerations .....................................................................................
MPU Registers ............................................................................................................
6.3.1 Revision Identification Register (REVID) .....................................................................
6.3.2 Configuration Register (CONFIG) .............................................................................
6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................
6.3.4 Interrupt Enable Status/Clear Register (IENSTAT)..........................................................
6.3.5 Interrupt Enable Set Register (IENSET) ......................................................................
6.3.6 Interrupt Enable Clear Register (IENCLR) ...................................................................
6.3.7 Fixed Range Start Address Register (FXD_MPSAR) .......................................................
6.3.8 Fixed Range End Address Register (FXD_MPEAR) ........................................................
6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ...............................
6.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR) ...................................
6.3.11 Programmable Range n End Address Registers (PROGn_MPEAR) ....................................
6.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA).............
6.3.13 Fault Address Register (FLTADDRR) ........................................................................
6.3.14 Fault Status Register (FLTSTAT).............................................................................
6.3.15 Fault Clear Register (FLTCLR) ...............................................................................
Overview ...................................................................................................................
Frequency Flexibility ......................................................................................................
Peripheral Clocking .......................................................................................................
7.3.1 USB Clocking.....................................................................................................
7.3.2 DDR2/mDDR Memory Controller Clocking ...................................................................
7.3.3 EMIFA Clocking ..................................................................................................
7.3.4 EMAC Clocking ..................................................................................................
7.3.5 uPP Clocking .....................................................................................................
7.3.6 McASP Clocking .................................................................................................
7.3.7 I/O Domains ......................................................................................................
128
130
131
131
133
135
136
138
139
140
Phase-Locked Loop Controller (PLLC) ................................................................................ 141
8.1
8.2
8.3
Introduction ................................................................................................................
PLL Controllers ............................................................................................................
8.2.1 Device Clock Generation .......................................................................................
8.2.2 Steps for Programming the PLLs ..............................................................................
PLLC Registers ...........................................................................................................
8.3.1 PLLC0 Revision Identification Register (REVID) ............................................................
8.3.2 PLLC1 Revision Identification Register (REVID) ............................................................
8.3.3 Reset Type Status Register (RSTYPE) .......................................................................
8.3.4 PLLC0 Reset Control Register (RSCTRL) ...................................................................
8.3.5 PLLC0 Control Register (PLLCTL) ............................................................................
8.3.6 PLLC1 Control Register (PLLCTL) ............................................................................
8.3.7 PLLC0 OBSCLK Select Register (OCSEL) ..................................................................
8.3.8 PLLC1 OBSCLK Select Register (OCSEL) ..................................................................
8.3.9 PLL Multiplier Control Register (PLLM) .......................................................................
8.3.10 PLLC0 Pre-Divider Control Register (PREDIV) .............................................................
8.3.11 PLLC0 Divider 1 Register (PLLDIV1) ........................................................................
8.3.12 PLLC1 Divider 1 Register (PLLDIV1) ........................................................................
8.3.13 PLLC0 Divider 2 Register (PLLDIV2) ........................................................................
8.3.14 PLLC1 Divider 2 Register (PLLDIV2) ........................................................................
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8.3.15
8.3.16
8.3.17
8.3.18
8.3.19
8.3.20
8.3.21
8.3.22
8.3.23
8.3.24
8.3.25
8.3.26
8.3.27
8.3.28
8.3.29
8.3.30
8.3.31
8.3.32
8.3.33
8.3.34
8.3.35
8.3.36
8.3.37
9
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158
159
159
160
160
161
161
162
162
163
164
165
166
167
168
168
169
170
171
172
173
173
Power and Sleep Controller (PSC) ...................................................................................... 174
9.1
9.2
9.3
9.4
9.5
9.6
4
PLLC0 Divider 3 Register (PLLDIV3) ........................................................................
PLLC1 Divider 3 Register (PLLDIV3) ........................................................................
PLLC0 Divider 4 Register (PLLDIV4) ........................................................................
PLLC0 Divider 5 Register (PLLDIV5) ........................................................................
PLLC0 Divider 6 Register (PLLDIV6) ........................................................................
PLLC0 Divider 7 Register (PLLDIV7) ........................................................................
PLLC0 Oscillator Divider 1 Register (OSCDIV).............................................................
PLLC1 Oscillator Divider 1 Register (OSCDIV).............................................................
PLL Post-Divider Control Register (POSTDIV) .............................................................
PLL Controller Command Register (PLLCMD) .............................................................
PLL Controller Status Register (PLLSTAT) .................................................................
PLLC0 Clock Align Control Register (ALNCTL) ............................................................
PLLC1 Clock Align Control Register (ALNCTL) ............................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .............................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .............................................
PLLC0 Clock Enable Control Register (CKEN) .............................................................
PLLC1 Clock Enable Control Register (CKEN) .............................................................
PLLC0 Clock Status Register (CKSTAT) ....................................................................
PLLC1 Clock Status Register (CKSTAT) ....................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ................................................................
Emulation Performance Counter 0 Register (EMUCNT0) .................................................
Emulation Performance Counter 1 Register (EMUCNT1) .................................................
Introduction ................................................................................................................
Power Domain and Module Topology ..................................................................................
9.2.1 Power Domain States ...........................................................................................
9.2.2 Module States ....................................................................................................
Executing State Transitions .............................................................................................
9.3.1 Power Domain State Transitions ..............................................................................
9.3.2 Module State Transitions .......................................................................................
IcePick Emulation Support in the PSC .................................................................................
PSC Interrupts.............................................................................................................
9.5.1 Interrupt Events ..................................................................................................
9.5.2 Interrupt Registers ...............................................................................................
9.5.3 Interrupt Handling ................................................................................................
PSC Registers.............................................................................................................
9.6.1 Revision Identification Register (REVID) .....................................................................
9.6.2 Interrupt Evaluation Register (INTEVAL) .....................................................................
9.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ...................................
9.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ...................................
9.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ......................................
9.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ......................................
9.6.7 Power Error Pending Register (PERRPR) ...................................................................
9.6.8 Power Error Clear Register (PERRCR) .......................................................................
9.6.9 Power Domain Transition Command Register (PTCMD)...................................................
9.6.10 Power Domain Transition Status Register (PTSTAT)......................................................
9.6.11 Power Domain 0 Status Register (PDSTAT0) ..............................................................
9.6.12 Power Domain 1 Status Register (PDSTAT1) ..............................................................
9.6.13 Power Domain 0 Control Register (PDCTL0) ...............................................................
9.6.14 Power Domain 1 Control Register (PDCTL1) ...............................................................
9.6.15 Power Domain 0 Configuration Register (PDCFG0) .......................................................
9.6.16 Power Domain 1 Configuration Register (PDCFG1) .......................................................
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9.6.17 Module Status n Register (MDSTATn)....................................................................... 197
9.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................ 198
9.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................ 199
10
Power Management........................................................................................................... 200
Introduction ................................................................................................................
Power Consumption Overview ..........................................................................................
PSC and PLLC Overview ................................................................................................
Features ....................................................................................................................
Clock Management .......................................................................................................
10.5.1 Module Clock ON/OFF .........................................................................................
10.5.2 Module Clock Frequency Scaling.............................................................................
10.5.3 PLL Bypass and Power Down ................................................................................
10.6 ARM Sleep Mode Management ........................................................................................
10.6.1 ARM Wait-For-Interrupt Sleep Mode .........................................................................
10.6.2 ARM Clock OFF ................................................................................................
10.6.3 ARM Subsystem Clock ON ....................................................................................
10.7 DSP Sleep Mode Management .........................................................................................
10.7.1 DSP Sleep Modes ..............................................................................................
10.7.2 C674x DSP CPU Sleep Mode ................................................................................
10.7.3 C674x Megamodule Sleep Mode .............................................................................
10.7.4 C674x Megamodule Clock ON/OFF .........................................................................
10.8 RTC-Only Mode ...........................................................................................................
10.9 Dynamic Voltage and Frequency Scaling (DVFS) ...................................................................
10.9.1 Frequency Scaling Considerations ...........................................................................
10.9.2 Voltage Scaling Considerations...............................................................................
10.10 Deep Sleep Mode ........................................................................................................
10.10.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ............................
10.10.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up ..................................
10.10.3 Deep Sleep Sequence........................................................................................
10.10.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking......................................
10.11 Additional Peripheral Power Management Considerations .........................................................
10.11.1 USB PHY Power Down Control ............................................................................
10.11.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode ..............................
10.11.3 SATA PHY Power Down .....................................................................................
10.11.4 LVCMOS I/O Buffer Receiver Disable ......................................................................
10.11.5 Pull-Up/Pull-Down Disable ...................................................................................
10.1
10.2
10.3
10.4
10.5
11
201
201
201
202
203
203
203
204
204
204
205
206
207
207
207
207
207
209
210
210
211
211
211
212
213
214
215
215
215
216
216
216
System Configuration (SYSCFG) Module ............................................................................. 217
11.1
11.2
11.3
11.4
11.5
Introduction ................................................................................................................
Protection ..................................................................................................................
11.2.1 Privilege Mode Protection .....................................................................................
11.2.2 Kicker Mechanism Protection .................................................................................
Master Priority Control ...................................................................................................
Interrupt Support ..........................................................................................................
11.4.1 Interrupt Events and Requests................................................................................
11.4.2 Interrupt Multiplexing ...........................................................................................
11.4.3 ARM-DSP Communication Interrupts ........................................................................
SYSCFG Registers .......................................................................................................
11.5.1 Revision Identification Register (REVID) ....................................................................
11.5.2 Device Identification Register 0 (DEVIDR0).................................................................
11.5.3 Boot Configuration Register (BOOTCFG) ...................................................................
11.5.4 Chip Revision Identification Register (CHIPREVIDR) .....................................................
11.5.5 Kick Registers (KICK0R-KICK1R) ............................................................................
11.5.6 Host 0 Configuration Register (HOST0CFG) ...............................................................
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11.5.7
11.5.8
11.5.9
11.5.10
11.5.11
11.5.12
11.5.13
11.5.14
11.5.15
11.5.16
11.5.17
11.5.18
11.5.19
11.5.20
11.5.21
11.5.22
11.5.23
11.5.24
11.5.25
11.5.26
12
ARM Interrupt Controller (AINTC)
12.1
12.2
12.3
12.4
6
Host 1 Configuration Register (HOST1CFG) ...............................................................
Interrupt Registers ..............................................................................................
Fault Registers ..................................................................................................
Master Priority Registers (MSTPRI0-MSTPRI2) ..........................................................
Pin Multiplexing Control Registers (PINMUX0-PINMUX19) .............................................
Suspend Source Register (SUSPSRC) ....................................................................
Chip Signal Register (CHIPSIG) ............................................................................
Chip Signal Clear Register (CHIPSIG_CLR) ..............................................................
Chip Configuration 0 Register (CFGCHIP0) ...............................................................
Chip Configuration 1 Register (CFGCHIP1) ...............................................................
Chip Configuration 2 Register (CFGCHIP2) ...............................................................
Chip Configuration 3 Register (CFGCHIP3) ...............................................................
Chip Configuration 4 Register (CFGCHIP4) ...............................................................
VTP I/O Control Register (VTPIO_CTL) ...................................................................
DDR Slew Register (DDR_SLEW) ..........................................................................
Deep Sleep Register (DEEPSLEEP) .......................................................................
Pullup/Pulldown Enable Register (PUPD_ENA) ..........................................................
Pullup/Pulldown Select Register (PUPD_SEL) ............................................................
RXACTIVE Control Register (RXACTIVE) .................................................................
Power Down Control Register (PWRDN) ..................................................................
....................................................................................... 297
Introduction ................................................................................................................
Interrupt Mapping .........................................................................................................
AINTC Methodology ......................................................................................................
12.3.1 Interrupt Processing ............................................................................................
12.3.2 Interrupt Enabling ...............................................................................................
12.3.3 Interrupt Status Checking ......................................................................................
12.3.4 Interrupt Channel Mapping ....................................................................................
12.3.5 Host Interrupt Mapping Interrupts ............................................................................
12.3.6 Interrupt Prioritization ..........................................................................................
12.3.7 Interrupt Nesting ................................................................................................
12.3.8 Interrupt Vectorization .........................................................................................
12.3.9 Interrupt Status Clearing .......................................................................................
12.3.10 Interrupt Disabling .............................................................................................
AINTC Registers ..........................................................................................................
12.4.1 Revision Identification Register (REVID) ....................................................................
12.4.2 Control Register (CR) ..........................................................................................
12.4.3 Global Enable Register (GER) ................................................................................
12.4.4 Global Nesting Level Register (GNLR) ......................................................................
12.4.5 System Interrupt Status Indexed Set Register (SISR) .....................................................
12.4.6 System Interrupt Status Indexed Clear Register (SICR) ..................................................
12.4.7 System Interrupt Enable Indexed Set Register (EISR) ....................................................
12.4.8 System Interrupt Enable Indexed Clear Register (EICR)..................................................
12.4.9 Host Interrupt Enable Indexed Set Register (HIEISR) .....................................................
12.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR) .................................................
12.4.11 Vector Base Register (VBR) .................................................................................
12.4.12 Vector Size Register (VSR) ..................................................................................
12.4.13 Vector Null Register (VNR) ..................................................................................
12.4.14 Global Prioritized Index Register (GPIR) ...................................................................
12.4.15 Global Prioritized Vector Register (GPVR) ................................................................
12.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1) ...................................................
12.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2) ...................................................
12.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3) ...................................................
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12.4.19
12.4.20
12.4.21
12.4.22
12.4.23
12.4.24
12.4.25
12.4.26
12.4.27
12.4.28
12.4.29
12.4.30
12.4.31
12.4.32
12.4.33
12.4.34
12.4.35
12.4.36
12.4.37
12.4.38
12.4.39
13
Introduction ................................................................................................................ 328
DSP Wake Up ............................................................................................................. 329
Programmable Real-Time Unit Subsystem (PRUSS) .............................................................. 330
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
15
316
316
317
317
318
318
319
319
320
320
321
321
322
322
323
323
324
324
325
326
326
Boot Considerations ......................................................................................................... 327
13.1
13.2
14
System Interrupt Status Raw/Set Register 4 (SRSR4) ...................................................
System Interrupt Status Enabled/Clear Register 1 (SECR1) ............................................
System Interrupt Status Enabled/Clear Register 2 (SECR2) ............................................
System Interrupt Status Enabled/Clear Register 3 (SECR3) ............................................
System Interrupt Status Enabled/Clear Register 4 (SECR4) ............................................
System Interrupt Enable Set Register 1 (ESR1) ..........................................................
System Interrupt Enable Set Register 2 (ESR2) ..........................................................
System Interrupt Enable Set Register 3 (ESR3) ..........................................................
System Interrupt Enable Set Register 4 (ESR4) ..........................................................
System Interrupt Enable Clear Register 1 (ECR1) .......................................................
System Interrupt Enable Clear Register 2 (ECR2) .......................................................
System Interrupt Enable Clear Register 3 (ECR3) .......................................................
System Interrupt Enable Clear Register 4 (ECR4) .......................................................
Channel Map Registers (CMR0-CMR25) ..................................................................
Host Interrupt Prioritized Index Register 1 (HIPIR1) ......................................................
Host Interrupt Prioritized Index Register 2 (HIPIR2) ......................................................
Host Interrupt Nesting Level Register 1 (HINLR1) ........................................................
Host Interrupt Nesting Level Register 2 (HINLR2) ........................................................
Host Interrupt Enable Register (HIER) .....................................................................
Host Interrupt Prioritized Vector Register 1 (HIPVR1) ...................................................
Host Interrupt Prioritized Vector Register 2 (HIPVR2) ...................................................
Overview ...................................................................................................................
Description .................................................................................................................
Constants Table...........................................................................................................
PRU Module Interface ....................................................................................................
14.4.1 Event Out Mapping (R31): PRU System Events ...........................................................
14.4.2 Status Mapping (R31): Interrupt Events Input ..............................................................
14.4.3 General Purpose Inputs (R31) ................................................................................
14.4.4 General Purpose Outputs (R30) ..............................................................................
Instruction Set .............................................................................................................
Instruction Formats .......................................................................................................
PRU Interrupt Controller .................................................................................................
14.7.1 Introduction ......................................................................................................
14.7.2 Interrupt Mapping ...............................................................................................
14.7.3 PRUSS System Events ........................................................................................
14.7.4 ARM and DSP Interrupt Controller Mapping ................................................................
14.7.5 INTC Methodology ..............................................................................................
Registers ...................................................................................................................
14.8.1 PRUSS Memory Map ..........................................................................................
14.8.2 INTC Registers ..................................................................................................
331
333
334
335
335
335
335
335
336
339
357
357
357
358
360
361
364
365
372
DDR2/mDDR Memory Controller ......................................................................................... 383
15.1
15.2
Introduction ................................................................................................................
15.1.1 Purpose of the Peripheral .....................................................................................
15.1.2 Features..........................................................................................................
15.1.3 Functional Block Diagram .....................................................................................
15.1.4 Supported Use Case Statement ..............................................................................
15.1.5 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
15.2.1 Clock Control ....................................................................................................
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15.3
15.4
16
387
388
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397
402
405
405
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406
407
408
408
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414
419
420
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425
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427
428
429
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433
434
434
435
436
437
Enhanced Capture (eCAP) Module ...................................................................................... 438
16.1
16.2
16.3
16.4
8
15.2.2 Signal Descriptions .............................................................................................
15.2.3 Protocol Description(s) .........................................................................................
15.2.4 Memory Width and Byte Alignment ..........................................................................
15.2.5 Address Mapping ...............................................................................................
15.2.6 DDR2/mDDR Memory Controller Interface ..................................................................
15.2.7 Refresh Scheduling .............................................................................................
15.2.8 Self-Refresh Mode ..............................................................................................
15.2.9 Partial Array Self Refresh for Mobile DDR ..................................................................
15.2.10 Power-Down Mode ............................................................................................
15.2.11 Reset Considerations .........................................................................................
15.2.12 VTP IO Buffer Calibration ....................................................................................
15.2.13 Auto-Initialization Sequence .................................................................................
15.2.14 Interrupt Support ..............................................................................................
15.2.15 DMA Event Support ...........................................................................................
15.2.16 Power Management ..........................................................................................
15.2.17 Emulation Considerations ....................................................................................
Supported Use Cases ....................................................................................................
Registers ...................................................................................................................
15.4.1 SDRAM Status Register (SDRSTAT) ........................................................................
15.4.2 SDRAM Configuration Register (SDCR) ....................................................................
15.4.3 SDRAM Refresh Control Register (SDRCR) ................................................................
15.4.4 SDRAM Timing Register 1 (SDTIMR1) ......................................................................
15.4.5 SDRAM Timing Register 2 (SDTIMR2) ......................................................................
15.4.6 SDRAM Configuration Register 2 (SDCR2) .................................................................
15.4.7 Peripheral Bus Burst Priority Register (PBBPR)............................................................
15.4.8 Performance Counter 1 Register (PC1) .....................................................................
15.4.9 Performance Counter 2 Register (PC2) .....................................................................
15.4.10 Performance Counter Configuration Register (PCC) .....................................................
15.4.11 Performance Counter Master Region Select Register (PCMRS) .......................................
15.4.12 DDR PHY Reset Control Register (DRPYRCR) ..........................................................
15.4.13 Interrupt Raw Register (IRR) ................................................................................
15.4.14 Interrupt Masked Register (IMR) ............................................................................
15.4.15 Interrupt Mask Set Register (IMSR) ........................................................................
15.4.16 Interrupt Mask Clear Register (IMCR) ......................................................................
15.4.17 DDR PHY Control Register (DRPYC1R) ...................................................................
Introduction ................................................................................................................
16.1.1 Purpose of the Peripheral .....................................................................................
16.1.2 Features..........................................................................................................
Architecture ................................................................................................................
16.2.1 Capture and APWM Operating Mode ........................................................................
16.2.2 Capture Mode Description .....................................................................................
Applications ...............................................................................................................
16.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example .........................................
16.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ...........................
16.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example .......................................
16.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example .........................
16.3.5 Application of the APWM Mode ..............................................................................
Registers ...................................................................................................................
16.4.1 Time-Stamp Counter Register (TSCTR) .....................................................................
16.4.2 Counter Phase Control Register (CTRPHS) ................................................................
16.4.3 Capture 1 Register (CAP1) ....................................................................................
16.4.4 Capture 2 Register (CAP2) ....................................................................................
Contents
439
439
439
440
441
442
449
450
452
454
456
458
465
465
466
466
467
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16.4.5
16.4.6
16.4.7
16.4.8
16.4.9
16.4.10
16.4.11
16.4.12
16.4.13
17
467
468
468
470
471
473
474
475
476
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 477
17.1
17.2
17.3
17.4
18
Capture 3 Register (CAP3) ....................................................................................
Capture 4 Register (CAP4) ....................................................................................
ECAP Control Register 1 (ECCTL1) .........................................................................
ECAP Control Register 2 (ECCTL2) .........................................................................
ECAP Interrupt Enable Register (ECEINT) .................................................................
ECAP Interrupt Flag Register (ECFLG) ....................................................................
ECAP Interrupt Clear Register (ECCLR) ...................................................................
ECAP Interrupt Forcing Register (ECFRC) ................................................................
Revision ID Register (REVID) ...............................................................................
Introduction ................................................................................................................
17.1.1 Introduction ......................................................................................................
17.1.2 Submodule Overview ..........................................................................................
17.1.3 Register Mapping ...............................................................................................
Architecture ................................................................................................................
17.2.1 Overview .........................................................................................................
17.2.2 Proper Interrupt Initialization Procedure .....................................................................
17.2.3 Time-Base (TB) Submodule ...................................................................................
17.2.4 Counter-Compare (CC) Submodule ..........................................................................
17.2.5 Action-Qualifier (AQ) Submodule .............................................................................
17.2.6 Dead-Band Generator (DB) Submodule .....................................................................
17.2.7 PWM-Chopper (PC) Submodule..............................................................................
17.2.8 Trip-Zone (TZ) Submodule ....................................................................................
17.2.9 Event-Trigger (ET) Submodule ...............................................................................
17.2.10 High-Resolution PWM (HRPWM) Submodule.............................................................
Applications to Power Topologies ......................................................................................
17.3.1 Overview of Multiple Modules ................................................................................
17.3.2 Key Configuration Capabilities ................................................................................
17.3.3 Controlling Multiple Buck Converters With Independent Frequencies ...................................
17.3.4 Controlling Multiple Buck Converters With Same Frequencies ...........................................
17.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ......................................................
17.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................
17.3.7 Practical Applications Using Phase Control Between PWM Modules ...................................
17.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ......................................................
17.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter......................................
Registers ...................................................................................................................
17.4.1 Time-Base Submodule Registers ............................................................................
17.4.2 Counter-Compare Submodule Registers ....................................................................
17.4.3 Action-Qualifier Submodule Registers .......................................................................
17.4.4 Dead-Band Generator Submodule Registers ...............................................................
17.4.5 PWM-Chopper Submodule Register .........................................................................
17.4.6 Trip-Zone Submodule Registers ..............................................................................
17.4.7 Event-Trigger Submodule Registers .........................................................................
17.4.8 High-Resolution PWM Submodule Registers ...............................................................
478
478
478
482
483
483
486
487
496
501
519
523
527
531
535
542
542
543
544
547
550
553
557
558
563
566
566
570
573
577
580
581
585
588
Enhanced Direct Memory Access (EDMA3) Controller ........................................................... 591
18.1
18.2
Introduction ................................................................................................................
18.1.1 Overview .........................................................................................................
18.1.2 Features..........................................................................................................
18.1.3 Functional Block Diagram .....................................................................................
18.1.4 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
18.2.1 Functional Overview ............................................................................................
18.2.2 Types of EDMA3 Transfers ...................................................................................
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Contents
592
592
592
595
595
597
597
600
9
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18.3
18.4
18.5
18.6
19
603
613
616
617
620
622
623
630
632
635
636
638
639
639
639
640
640
640
642
643
645
657
657
664
703
724
724
725
726
EMAC/MDIO Module .......................................................................................................... 727
19.1
19.2
10
18.2.3 Parameter RAM (PaRAM) .....................................................................................
18.2.4 Initiating a DMA Transfer ......................................................................................
18.2.5 Completion of a DMA Transfer................................................................................
18.2.6 Event, Channel, and PaRAM Mapping ......................................................................
18.2.7 EDMA3 Channel Controller Regions .........................................................................
18.2.8 Chaining EDMA3 Channels ...................................................................................
18.2.9 EDMA3 Interrupts ...............................................................................................
18.2.10 Event Queue(s) ................................................................................................
18.2.11 EDMA3 Transfer Controller (EDMA3TC)...................................................................
18.2.12 Event Dataflow ................................................................................................
18.2.13 EDMA3 Prioritization ..........................................................................................
18.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................
18.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................
18.2.16 Reset Considerations .........................................................................................
18.2.17 Power Management ..........................................................................................
18.2.18 Emulation Considerations ....................................................................................
Transfer Examples........................................................................................................
18.3.1 Block Move Example ...........................................................................................
18.3.2 Subframe Extraction Example ................................................................................
18.3.3 Data Sorting Example ..........................................................................................
18.3.4 Peripheral Servicing Example .................................................................................
Registers ...................................................................................................................
18.4.1 Parameter RAM (PaRAM) Entries ............................................................................
18.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................
18.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ........................................................
Tips .........................................................................................................................
18.5.1 Debug Checklist ................................................................................................
18.5.2 Miscellaneous Programming/Debug Tips ...................................................................
Setting Up a Transfer ....................................................................................................
Introduction ................................................................................................................
19.1.1 Purpose of the Peripheral .....................................................................................
19.1.2 Features..........................................................................................................
19.1.3 Functional Block Diagram .....................................................................................
19.1.4 Industry Standard(s) Compliance Statement................................................................
19.1.5 Terminology .....................................................................................................
Architecture ................................................................................................................
19.2.1 Clock Control ....................................................................................................
19.2.2 Memory Map ....................................................................................................
19.2.3 Signal Descriptions .............................................................................................
19.2.4 Ethernet Protocol Overview ...................................................................................
19.2.5 Programming Interface .........................................................................................
19.2.6 EMAC Control Module .........................................................................................
19.2.7 MDIO Module ...................................................................................................
19.2.8 EMAC Module ...................................................................................................
19.2.9 MAC Interface ...................................................................................................
19.2.10 Packet Receive Operation ...................................................................................
19.2.11 Packet Transmit Operation ..................................................................................
19.2.12 Receive and Transmit Latency ..............................................................................
19.2.13 Transfer Node Priority ........................................................................................
19.2.14 Reset Considerations .........................................................................................
19.2.15 Initialization .....................................................................................................
19.2.16 Interrupt Support ..............................................................................................
Contents
728
728
728
729
730
730
731
731
732
732
735
736
747
748
753
755
759
764
765
765
766
767
769
SPRUH77C – April 2013 – Revised September 2016
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19.3
20
19.2.17 Power Management ..........................................................................................
19.2.18 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
19.3.1 EMAC Control Module Registers .............................................................................
19.3.2 MDIO Registers .................................................................................................
19.3.3 EMAC Module Registers.......................................................................................
773
773
774
774
788
801
External Memory Interface A (EMIFA) .................................................................................. 851
20.1
20.2
20.3
20.4
Introduction ................................................................................................................
20.1.1 Purpose of the Peripheral .....................................................................................
20.1.2 Features..........................................................................................................
20.1.3 Functional Block Diagram .....................................................................................
Architecture ................................................................................................................
20.2.1 Clock Control ....................................................................................................
20.2.2 EMIFA Requests ................................................................................................
20.2.3 Pin Descriptions .................................................................................................
20.2.4 SDRAM Controller and Interface .............................................................................
20.2.5 Asynchronous Controller and Interface ......................................................................
20.2.6 Data Bus Parking ...............................................................................................
20.2.7 Reset and Initialization Considerations ......................................................................
20.2.8 Interrupt Support ................................................................................................
20.2.9 EDMA Event Support ..........................................................................................
20.2.10 Pin Multiplexing ................................................................................................
20.2.11 Memory Map ...................................................................................................
20.2.12 Priority and Arbitration ........................................................................................
20.2.13 System Considerations .......................................................................................
20.2.14 Power Management ..........................................................................................
20.2.15 Emulation Considerations ....................................................................................
Example Configuration ...................................................................................................
20.3.1 Hardware Interface .............................................................................................
20.3.2 Software Configuration .........................................................................................
Registers ...................................................................................................................
20.4.1 Module ID Register (MIDR) ...................................................................................
20.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) ...............................................
20.4.3 SDRAM Configuration Register (SDCR) ....................................................................
20.4.4 SDRAM Refresh Control Register (SDRCR) ................................................................
20.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
20.4.6 SDRAM Timing Register (SDTIMR) ..........................................................................
20.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ..................................................
20.4.8 EMIFA Interrupt Raw Register (INTRAW) ...................................................................
20.4.9 EMIFA Interrupt Masked Register (INTMSK) ...............................................................
20.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET).......................................................
20.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ....................................................
20.4.12 NAND Flash Control Register (NANDFCR) ...............................................................
20.4.13 NAND Flash Status Register (NANDFSR) .................................................................
20.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ..........................................
20.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) .......................................
20.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..................................................
20.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..................................................
20.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..................................................
20.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..................................................
20.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) .................................
20.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) .................................
20.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1).....................................
SPRUH77C – April 2013 – Revised September 2016
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Contents
852
852
852
852
852
853
853
853
855
867
886
886
887
888
888
888
889
890
891
892
893
893
893
915
916
916
918
920
921
923
924
925
926
927
928
929
931
932
933
934
934
935
935
936
936
937
11
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20.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)..................................... 937
21
General-Purpose Input/Output (GPIO) ................................................................................. 938
21.1
21.2
21.3
22
939
939
939
939
939
940
940
940
940
940
941
944
945
945
946
946
947
947
947
948
949
950
951
953
955
957
959
961
963
965
967
969
Host Port Interface (HPI) .................................................................................................... 971
22.1
22.2
12
Introduction ................................................................................................................
21.1.1 Purpose of the Peripheral .....................................................................................
21.1.2 Features..........................................................................................................
21.1.3 Functional Block Diagram .....................................................................................
21.1.4 Industry Standard(s) Compliance Statement................................................................
Architecture ................................................................................................................
21.2.1 Clock Control ....................................................................................................
21.2.2 Signal Descriptions .............................................................................................
21.2.3 Pin Multiplexing .................................................................................................
21.2.4 Endianness Considerations ...................................................................................
21.2.5 GPIO Register Structure .......................................................................................
21.2.6 Using a GPIO Signal as an Output ...........................................................................
21.2.7 Using a GPIO Signal as an Input .............................................................................
21.2.8 Reset Considerations ..........................................................................................
21.2.9 Initialization ......................................................................................................
21.2.10 Interrupt Support ..............................................................................................
21.2.11 EDMA Event Support .........................................................................................
21.2.12 Power Management ..........................................................................................
21.2.13 Emulation Considerations ....................................................................................
Registers ...................................................................................................................
21.3.1 Revision ID Register (REVID) .................................................................................
21.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ......................................................
21.3.3 GPIO Direction Registers (DIRn) .............................................................................
21.3.4 GPIO Output Data Registers (OUT_DATAn) ...............................................................
21.3.5 GPIO Set Data Registers (SET_DATAn) ....................................................................
21.3.6 GPIO Clear Data Registers (CLR_DATAn) .................................................................
21.3.7 GPIO Input Data Registers (IN_DATAn) ....................................................................
21.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) ...........................................
21.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ........................................
21.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................
21.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) .....................................
21.3.12 GPIO Interrupt Status Registers (INTSTATn) .............................................................
Introduction ................................................................................................................
22.1.1 Purpose of the Peripheral .....................................................................................
22.1.2 Features..........................................................................................................
22.1.3 Functional Block Diagram .....................................................................................
22.1.4 Industry Standard(s) Compliance Statement................................................................
22.1.5 Terminology Used in This Document ........................................................................
Architecture ................................................................................................................
22.2.1 Clock Control ....................................................................................................
22.2.2 Memory Map ....................................................................................................
22.2.3 Signal Descriptions .............................................................................................
22.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks ................................................
22.2.5 Protocol Description ............................................................................................
22.2.6 Operation ........................................................................................................
22.2.7 Reset Considerations ..........................................................................................
22.2.8 Initialization ......................................................................................................
22.2.9 Interrupt Support ................................................................................................
22.2.10 EDMA Event Support .........................................................................................
22.2.11 Power Management ..........................................................................................
Contents
972
972
972
973
974
974
975
975
975
975
976
977
977
992
992
993
994
994
SPRUH77C – April 2013 – Revised September 2016
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22.3
23
22.2.12 Emulation Considerations .................................................................................... 995
Registers ................................................................................................................... 995
22.3.1 Revision Identification Register (REVID) .................................................................... 996
22.3.2 Power and Emulation Management Register (PWREMU_MGMT) ...................................... 996
22.3.3 GPIO Enable Register (GPIO_EN) .......................................................................... 997
22.3.4 GPIO Direction 1 Register (GPIO_DIR1) .................................................................... 998
22.3.5 GPIO Data 1 Register (GPIO_DAT1) ........................................................................ 998
22.3.6 GPIO Direction 2 Register (GPIO_DIR2) .................................................................... 999
22.3.7 GPIO Data 2 Register (GPIO_DAT2)....................................................................... 1000
22.3.8 Host Port Interface Control Register (HPIC) ............................................................... 1001
22.3.9 Host Port Interface Write Address Register (HPIAW) .................................................... 1003
22.3.10 Host Port Interface Read Address Register (HPIAR) ................................................... 1003
Inter-Integrated Circuit (I2C) Module .................................................................................. 1004
23.1
23.2
23.3
Introduction ...............................................................................................................
23.1.1 Purpose of the Peripheral ....................................................................................
23.1.2 Features ........................................................................................................
23.1.3 Functional Block Diagram ....................................................................................
23.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
23.2.1 Bus Structure ..................................................................................................
23.2.2 Clock Generation ..............................................................................................
23.2.3 Clock Synchronization ........................................................................................
23.2.4 Signal Descriptions............................................................................................
23.2.5 START and STOP Conditions ...............................................................................
23.2.6 Serial Data Formats...........................................................................................
23.2.7 Operating Modes ..............................................................................................
23.2.8 NACK Bit Generation .........................................................................................
23.2.9 Arbitration ......................................................................................................
23.2.10 Reset Considerations .......................................................................................
23.2.11 Initialization ...................................................................................................
23.2.12 Interrupt Support .............................................................................................
23.2.13 DMA Events Generated by the I2C Peripheral ..........................................................
23.2.14 Power Management .........................................................................................
23.2.15 Emulation Considerations ..................................................................................
Registers .................................................................................................................
23.3.1 I2C Own Address Register (ICOAR) .......................................................................
23.3.2 I2C Interrupt Mask Register (ICIMR) .......................................................................
23.3.3 I2C Interrupt Status Register (ICSTR) .....................................................................
23.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) .....................................................
23.3.5 I2C Data Count Register (ICCNT) ..........................................................................
23.3.6 I2C Data Receive Register (ICDRR) .......................................................................
23.3.7 I2C Slave Address Register (ICSAR).......................................................................
23.3.8 I2C Data Transmit Register (ICDXR) .......................................................................
23.3.9 I2C Mode Register (ICMDR) .................................................................................
23.3.10 I2C Interrupt Vector Register (ICIVR) .....................................................................
23.3.11 I2C Extended Mode Register (ICEMDR) .................................................................
23.3.12 I2C Prescaler Register (ICPSC) ...........................................................................
23.3.13 I2C Revision Identification Register (REVID1) ...........................................................
23.3.14 I2C Revision Identification Register (REVID2) ..........................................................
23.3.15 I2C DMA Control Register (ICDMAC).....................................................................
23.3.16 I2C Pin Function Register (ICPFUNC) ...................................................................
23.3.17 I2C Pin Direction Register (ICPDIR) .....................................................................
23.3.18 I2C Pin Data In Register (ICPDIN) .......................................................................
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Contents
1005
1005
1005
1006
1006
1007
1007
1008
1009
1009
1010
1011
1013
1014
1015
1016
1016
1017
1018
1018
1018
1019
1020
1021
1022
1025
1026
1027
1028
1029
1030
1034
1035
1036
1037
1037
1038
1039
1040
1041
13
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23.3.19 I2C Pin Data Out Register (ICPDOUT) .................................................................. 1042
23.3.20 I2C Pin Data Set Register (ICPDSET) ................................................................... 1043
23.3.21 I2C Pin Data Clear Register (ICPDCLR) ................................................................ 1044
24
Liquid Crystal Display Controller (LCDC) ........................................................................... 1045
24.1
24.2
24.3
25
1046
1046
1047
1047
1047
1047
1049
1050
1051
1053
1063
1063
1064
1066
1069
1071
1072
1073
1074
1081
1083
1087
1091
1093
1094
1094
Multichannel Audio Serial Port (McASP) ............................................................................ 1095
25.1
14
Introduction ...............................................................................................................
24.1.1 Purpose of the Peripheral ....................................................................................
24.1.2 Features ........................................................................................................
24.1.3 Terminology ....................................................................................................
Architecture ..............................................................................................................
24.2.1 Clocking ........................................................................................................
24.2.2 LCD External I/O Signals.....................................................................................
24.2.3 DMA Engine ...................................................................................................
24.2.4 LIDD Controller ................................................................................................
24.2.5 Raster Controller ..............................................................................................
Registers .................................................................................................................
24.3.1 LCD Revision Identification Register (REVID) ............................................................
24.3.2 LCD Control Register (LCD_CTRL) ........................................................................
24.3.3 LCD Status Register (LCD_STAT)..........................................................................
24.3.4 LCD LIDD Control Register (LIDD_CTRL) .................................................................
24.3.5 LCD LIDD CSn Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF) ..............
24.3.6 LCD LIDD CSn Address Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR) ......
24.3.7 LCD LIDD CSn Data Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA) ...........
24.3.8 LCD Raster Control Register (RASTER_CTRL) ..........................................................
24.3.9 LCD Raster Timing Register 0 (RASTER_TIMING_0) ...................................................
24.3.10 LCD Raster Timing Register 1 (RASTER_TIMING_1) .................................................
24.3.11 LCD Raster Timing Register 2 (RASTER_TIMING_2) .................................................
24.3.12 LCD Raster Subpanel Display Register (RASTER_SUBPANEL) .....................................
24.3.13 LCD DMA Control Register (LCDDMA_CTRL) ..........................................................
24.3.14 LCD DMA Frame Buffer n Base Address Registers
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE) .......................................................
24.3.15 LCD DMA Frame Buffer n Ceiling Address Registers
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING) ................................................
25.0.16 Features ......................................................................................................
25.0.17 Protocols Supported ........................................................................................
25.0.18 Functional Block Diagram ..................................................................................
25.0.19 Definition of Terms ..........................................................................................
25.0.20 Overview .....................................................................................................
25.0.21 Clock and Frame Sync Generators .......................................................................
25.0.22 Reset Considerations .......................................................................................
25.0.23 EDMA Event Support .......................................................................................
25.0.24 Power Management .........................................................................................
Registers .................................................................................................................
25.1.1 Register Bit Restrictions ......................................................................................
25.1.2 Revision Identification Register (REV) .....................................................................
25.1.3 Pin Function Register (PFUNC) .............................................................................
25.1.4 Pin Direction Register (PDIR) ...............................................................................
25.1.5 Pin Data Output Register (PDOUT) ........................................................................
25.1.6 Pin Data Input Register (PDIN)..............................................................................
25.1.7 Pin Data Set Register (PDSET) .............................................................................
25.1.8 Pin Data Clear Register (PDCLR) ..........................................................................
25.1.9 Global Control Register (GBLCTL) .........................................................................
25.1.10 Audio Mute Control Register (AMUTE) ...................................................................
Contents
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1097
1098
1106
1109
1109
1150
1150
1150
1151
1154
1155
1156
1158
1160
1162
1164
1166
1168
1170
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25.1.11
25.1.12
25.1.13
25.1.14
25.1.15
25.1.16
25.1.17
25.1.18
25.1.19
25.1.20
25.1.21
25.1.22
25.1.23
25.1.24
25.1.25
25.1.26
25.1.27
25.1.28
25.1.29
25.1.30
25.1.31
25.1.32
25.1.33
25.1.34
25.1.35
25.1.36
25.1.37
25.1.38
25.1.39
25.1.40
25.1.41
25.1.42
25.1.43
25.1.44
25.1.45
25.1.46
25.1.47
25.1.48
26
Digital Loopback Control Register (DLBCTL) ............................................................
Digital Mode Control Register (DITCTL) ..................................................................
Receiver Global Control Register (RGBLCTL)...........................................................
Receive Format Unit Bit Mask Register (RMASK) ......................................................
Receive Bit Stream Format Register (RFMT) ............................................................
Receive Frame Sync Control Register (AFSRCTL) .....................................................
Receive Clock Control Register (ACLKRCTL) ...........................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) .....................................
Receive TDM Time Slot Register (RTDM) ...............................................................
Receiver Interrupt Control Register (RINTCTL) .........................................................
Receiver Status Register (RSTAT) ........................................................................
Current Receive TDM Time Slot Registers (RSLOT) ...................................................
Receive Clock Check Control Register (RCLKCHK)....................................................
Receiver DMA Event Control Register (REVTCTL) .....................................................
Transmitter Global Control Register (XGBLCTL) ........................................................
Transmit Format Unit Bit Mask Register (XMASK) ......................................................
Transmit Bit Stream Format Register (XFMT) ...........................................................
Transmit Frame Sync Control Register (AFSXCTL) ....................................................
Transmit Clock Control Register (ACLKXCTL) ..........................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ....................................
Transmit TDM Time Slot Register (XTDM) ...............................................................
Transmitter Interrupt Control Register (XINTCTL) ......................................................
Transmitter Status Register (XSTAT) .....................................................................
Current Transmit TDM Time Slot Register (XSLOT) ....................................................
Transmit Clock Check Control Register (XCLKCHK) ...................................................
Transmitter DMA Event Control Register (XEVTCTL) ..................................................
Serializer Control Registers (SRCTLn) ...................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ..........................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ........................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) .....................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ...................................
Transmit Buffer Registers (XBUFn) .......................................................................
Receive Buffer Registers (RBUFn) ........................................................................
AFIFO Revision Identification Register (AFIFOREV) ...................................................
Write FIFO Control Register (WFIFOCTL) ...............................................................
Write FIFO Status Register (WFIFOSTS) ................................................................
Read FIFO Control Register (RFIFOCTL) ................................................................
Read FIFO Status Register (RFIFOSTS).................................................................
1172
1173
1174
1175
1176
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
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1191
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1198
1199
1200
1201
1201
1202
1202
1203
1203
1204
1205
1206
1207
1208
Multichannel Buffered Serial Port (McBSP) ........................................................................ 1209
26.1
26.2
Introduction ...............................................................................................................
26.1.1 Purpose of the Peripheral ....................................................................................
26.1.2 Features ........................................................................................................
26.1.3 Functional Block Diagram ....................................................................................
26.1.4 Industry Standard Compliance Statement .................................................................
Architecture ..............................................................................................................
26.2.1 Clock Control ..................................................................................................
26.2.2 Signal Descriptions............................................................................................
26.2.3 Pin Multiplexing ................................................................................................
26.2.4 Endianness Considerations ..................................................................................
26.2.5 Clock, Frames, and Data .....................................................................................
26.2.6 McBSP Buffer FIFO (BFIFO) ................................................................................
26.2.7 McBSP Standard Operation .................................................................................
26.2.8 μ-Law/A-Law Companding Hardware Operation ..........................................................
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1212
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1213
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26.3
27
1243
1251
1251
1252
1256
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1259
1260
1260
1261
1263
1265
1267
1268
1272
1274
1276
1278
1279
1280
1281
1282
Multimedia Card (MMC)/Secure Digital (SD) Card Controller ................................................. 1283
27.1
27.2
27.3
16
26.2.9 Multichannel Selection Modes ...............................................................................
26.2.10 SPI Operation Using the Clock Stop Mode ..............................................................
26.2.11 Resetting the Serial Port: RRST, XRST, GRST, and RESET .........................................
26.2.12 McBSP Initialization Procedure ............................................................................
26.2.13 Interrupt Support .............................................................................................
26.2.14 EDMA Event Support .......................................................................................
26.2.15 Power Management .........................................................................................
26.2.16 Emulation Considerations ..................................................................................
Registers .................................................................................................................
26.3.1 Data Receive Register (DRR) ...............................................................................
26.3.2 Data Transmit Register (DXR)...............................................................................
26.3.3 Serial Port Control Register (SPCR)........................................................................
26.3.4 Receive Control Register (RCR) ............................................................................
26.3.5 Transmit Control Register (XCR)............................................................................
26.3.6 Sample Rate Generator Register (SRGR) .................................................................
26.3.7 Multichannel Control Register (MCR) ......................................................................
26.3.8 Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) ..................................
26.3.9 Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) ..................................
26.3.10 Pin Control Register (PCR) .................................................................................
26.3.11 BFIFO Revision Identification Register (BFIFOREV) ...................................................
26.3.12 Write FIFO Control Register (WFIFOCTL) ...............................................................
26.3.13 Write FIFO Status Register (WFIFOSTS) ................................................................
26.3.14 Read FIFO Control Register (RFIFOCTL) ................................................................
26.3.15 Read FIFO Status Register (RFIFOSTS).................................................................
Introduction ...............................................................................................................
27.1.1 Purpose of the Peripheral ....................................................................................
27.1.2 Features ........................................................................................................
27.1.3 Functional Block Diagram ....................................................................................
27.1.4 Supported Use Case Statement ............................................................................
27.1.5 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
27.2.1 Clock Control ..................................................................................................
27.2.2 Signal Descriptions............................................................................................
27.2.3 Protocol Descriptions .........................................................................................
27.2.4 Data Flow in the Input/Output FIFO ........................................................................
27.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ...........................................
27.2.6 FIFO Operation During Card Read Operation.............................................................
27.2.7 FIFO Operation During Card Write Operation .............................................................
27.2.8 Reset Considerations .........................................................................................
27.2.9 Initialization .....................................................................................................
27.2.10 Interrupt Support .............................................................................................
27.2.11 DMA Event Support .........................................................................................
27.2.12 Power Management .........................................................................................
27.2.13 Emulation Considerations ..................................................................................
Procedures for Common Operations .................................................................................
27.3.1 Card Identification Operation ................................................................................
27.3.2 MMC/SD Mode Single-Block Write Operation Using CPU ..............................................
27.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ........................................
27.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ..........................................
27.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ............................................
27.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU .............................................
27.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA...........................................
Contents
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SPRUH77C – April 2013 – Revised September 2016
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27.4
28
27.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................
27.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA ..........................................
27.3.10 SDIO Card Function .........................................................................................
Registers .................................................................................................................
27.4.1 MMC Control Register (MMCCTL) ..........................................................................
27.4.2 MMC Memory Clock Control Register (MMCCLK) .......................................................
27.4.3 MMC Status Register 0 (MMCST0) .........................................................................
27.4.4 MMC Status Register 1 (MMCST1) .........................................................................
27.4.5 MMC Interrupt Mask Register (MMCIM) ...................................................................
27.4.6 MMC Response Time-Out Register (MMCTOR) ..........................................................
27.4.7 MMC Data Read Time-Out Register (MMCTOD) .........................................................
27.4.8 MMC Block Length Register (MMCBLEN) .................................................................
27.4.9 MMC Number of Blocks Register (MMCNBLK) ...........................................................
27.4.10 MMC Number of Blocks Counter Register (MMCNBLC) ...............................................
27.4.11 MMC Data Receive Register (MMCDRR) ................................................................
27.4.12 MMC Data Transmit Register (MMCDXR) ...............................................................
27.4.13 MMC Command Register (MMCCMD) ...................................................................
27.4.14 MMC Argument Register (MMCARGHL) .................................................................
27.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ...................................................
27.4.16 MMC Data Response Register (MMCDRSP) ............................................................
27.4.17 MMC Command Index Register (MMCCIDX) ............................................................
27.4.18 SDIO Control Register (SDIOCTL) ........................................................................
27.4.19 SDIO Status Register 0 (SDIOST0) .......................................................................
27.4.20 SDIO Interrupt Enable Register (SDIOIEN) ..............................................................
27.4.21 SDIO Interrupt Status Register (SDIOIST) ...............................................................
27.4.22 MMC FIFO Control Register (MMCFIFOCTL) ...........................................................
1310
1312
1312
1313
1314
1315
1316
1318
1319
1321
1322
1323
1324
1324
1325
1325
1326
1328
1329
1331
1331
1332
1333
1334
1334
1335
Real-Time Clock (RTC) ..................................................................................................... 1336
28.1
28.2
28.3
Introduction ...............................................................................................................
28.1.1 Purpose of the Peripheral ....................................................................................
28.1.2 Features ........................................................................................................
28.1.3 Block Diagram .................................................................................................
Architecture ..............................................................................................................
28.2.1 Clock Source ...................................................................................................
28.2.2 Signal Descriptions............................................................................................
28.2.3 Isolated Power Supply ........................................................................................
28.2.4 Operation .......................................................................................................
28.2.5 Interrupt Requests ............................................................................................
28.2.6 Register Protection Against Spurious Writes ..............................................................
28.2.7 General-Purpose Scratch Registers ........................................................................
28.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) ..............................
28.2.9 Emulation Modes of the Real-Time Clock .................................................................
28.2.10 Reset Considerations .......................................................................................
Registers .................................................................................................................
28.3.1 Second Register (SECOND).................................................................................
28.3.2 Minute Register (MINUTE) ...................................................................................
28.3.3 Hour Register (HOUR) .......................................................................................
28.3.4 Day of the Month Register (DAY) ...........................................................................
28.3.5 Month Register (MONTH) ....................................................................................
28.3.6 Year Register (YEAR) ........................................................................................
28.3.7 Day of the Week Register (DOTW) .........................................................................
28.3.8 Alarm Second Register (ALARMSECOND) ...............................................................
28.3.9 Alarm Minute Register (ALARMMINUTE) ..................................................................
28.3.10 Alarm Hour Register (ALARMHOUR) .....................................................................
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28.3.11
28.3.12
28.3.13
28.3.14
28.3.15
28.3.16
28.3.17
28.3.18
28.3.19
28.3.20
28.3.21
29
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1352
1352
1353
1354
1355
1356
1357
1358
1359
1359
Serial ATA (SATA) Controller............................................................................................ 1360
29.1
29.2
29.3
29.4
18
Alarm Day of the Month Register (ALARMDAY) ........................................................
Alarm Month Register (ALARMMONTH) .................................................................
Alarm Year Register (ALARMYEAR)......................................................................
Control Register (CTRL) ....................................................................................
Status Register (STATUS) .................................................................................
Interrupt Register (INTERRUPT) ..........................................................................
Compensation (LSB) Register (COMPLSB) .............................................................
Compensation (MSB) Register (COMPMSB) ............................................................
Oscillator Register (OSC) ...................................................................................
Scratch Registers (SCRATCH0-SCRATCH2) ...........................................................
Kick Registers (KICK0R, KICK1R) ........................................................................
Introduction ...............................................................................................................
29.1.1 Purpose of the Peripheral ....................................................................................
29.1.2 Features Supported ...........................................................................................
29.1.3 Features Not Supported ......................................................................................
29.1.4 Functional Block Diagram ....................................................................................
29.1.5 Terminology Used in this Document ........................................................................
29.1.6 Industry Standard(s) Compliance ...........................................................................
Architecture ..............................................................................................................
29.2.1 Clock Control ..................................................................................................
29.2.2 Signal Description .............................................................................................
29.2.3 Pin Multiplexing ................................................................................................
29.2.4 Interfacing to Single and Multiple Devices .................................................................
29.2.5 DMA .............................................................................................................
29.2.6 Transport Layer ................................................................................................
29.2.7 Link Layer ......................................................................................................
29.2.8 Phy ..............................................................................................................
29.2.9 Reset ............................................................................................................
29.2.10 Initialization ...................................................................................................
29.2.11 Interrupt Support .............................................................................................
29.2.12 EDMA Event Support .......................................................................................
29.2.13 Power Management .........................................................................................
Use Cases................................................................................................................
29.3.1 General Utilities: Structures and Subroutines Sample Program Uses ................................
29.3.2 Example on Initialization and Spinning Up Device........................................................
29.3.3 Example of DMA Write Transfer ............................................................................
29.3.4 Example of DMA Read Transfer ............................................................................
Registers .................................................................................................................
29.4.1 HBA Capabilities Register (CAP) ...........................................................................
29.4.2 Global HBA Control Register (GHC)........................................................................
29.4.3 Interrupt Status Register (IS) ................................................................................
29.4.4 Ports Implemented Register (PI) ............................................................................
29.4.5 AHCI Version Register (VS) .................................................................................
29.4.6 Command Completion Coalescing Control Register (CCC_CTL) ......................................
29.4.7 Command Completion Coalescing Ports Register (CCC_PORTS) ....................................
29.4.8 BIST Active FIS Register (BISTAFR) .......................................................................
29.4.9 BIST Control Register (BISTCR) ............................................................................
29.4.10 BIST FIS Count Register (BISTFCTR)....................................................................
29.4.11 BIST Status Register (BISTSR)............................................................................
29.4.12 BIST DWORD Error Count Register (BISTDECR) ......................................................
29.4.13 BIST DWORD Error Count Register (TIMER1MS) ......................................................
29.4.14 Global Parameter 1 Register (GPARAM1R) .............................................................
Contents
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SPRUH77C – April 2013 – Revised September 2016
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29.4.15
29.4.16
29.4.17
29.4.18
29.4.19
29.4.20
29.4.21
29.4.22
29.4.23
29.4.24
29.4.25
29.4.26
29.4.27
29.4.28
29.4.29
29.4.30
29.4.31
29.4.32
29.4.33
29.4.34
29.4.35
30
Global Parameter 2 Register (GPARAM2R) .............................................................
Port Parameter Register (PPARAMR) ....................................................................
Test Register (TESTR) ......................................................................................
Version Register (VERSIONR) ............................................................................
ID Register (IDR) ............................................................................................
Port Command List Base Address Register (P0CLB) ..................................................
Port FIS Base Address Register (P0FB) .................................................................
Port Interrupt Status Register (P0IS) ......................................................................
Port Interrupt Enable Register (P0IE) .....................................................................
Port Command Register (P0CMD) ........................................................................
Port Task File Data Register (P0TFD) ....................................................................
Port Signature Register (P0SIG) ..........................................................................
Port Serial ATA Status (SStatus) Register (P0SSTS) ..................................................
Port Serial ATA Control (SControl) Register (P0SCTL) ................................................
Port Serial ATA Error (SError) Register (P0SERR) .....................................................
Port Serial ATA Active (SActive) Register (P0SACT) ...................................................
Port Command Issue Register (P0CI) ....................................................................
Port Serial ATA Notification Register (P0SNTF).........................................................
Port DMA Control Register (P0DMACR) .................................................................
Port PHY Control Register (P0PHYCR) ..................................................................
Port PHY Status Register (P0PHYSR) ...................................................................
1404
1405
1406
1407
1407
1408
1408
1409
1411
1412
1415
1415
1416
1417
1418
1420
1420
1421
1422
1424
1428
Serial Peripheral Interface (SPI) ........................................................................................ 1429
30.1
30.2
30.3
Introduction ...............................................................................................................
30.1.1 Purpose of the Peripheral ....................................................................................
30.1.2 Features ........................................................................................................
30.1.3 Functional Block Diagram ....................................................................................
30.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
30.2.1 Clock ............................................................................................................
30.2.2 Signal Descriptions............................................................................................
30.2.3 Operation Modes ..............................................................................................
30.2.4 Programmable Registers .....................................................................................
30.2.5 Master Mode Settings ........................................................................................
30.2.6 Slave Mode Settings ..........................................................................................
30.2.7 SPI Operation: 3-Pin Mode ..................................................................................
30.2.8 SPI Operation: 4-Pin with Chip Select Mode .............................................................
30.2.9 SPI Operation: 4-Pin with Enable Mode ...................................................................
30.2.10 SPI Operation: 5-Pin Mode .................................................................................
30.2.11 Data Formats .................................................................................................
30.2.12 Interrupt Support .............................................................................................
30.2.13 DMA Events Support ........................................................................................
30.2.14 Robustness Features .......................................................................................
30.2.15 Reset Considerations .......................................................................................
30.2.16 Power Management .........................................................................................
30.2.17 General-Purpose I/O Pin....................................................................................
30.2.18 Emulation Considerations ..................................................................................
30.2.19 Initialization ...................................................................................................
30.2.20 Timing Diagrams .............................................................................................
Registers .................................................................................................................
30.3.1 SPI Global Control Register 0 (SPIGCR0) .................................................................
30.3.2 SPI Global Control Register 1 (SPIGCR1) .................................................................
30.3.3 SPI Interrupt Register (SPIINT0) ............................................................................
30.3.4 SPI Interrupt Level Register (SPILVL) ......................................................................
SPRUH77C – April 2013 – Revised September 2016
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Contents
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30.3.5
30.3.6
30.3.7
30.3.8
30.3.9
30.3.10
30.3.11
30.3.12
30.3.13
30.3.14
30.3.15
30.3.16
30.3.17
30.3.18
30.3.19
31
64-Bit Timer Plus
31.1
31.2
32
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1466
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1468
1469
1470
1471
1472
1473
1474
1476
1477
1480
1481
1483
............................................................................................................ 1484
Introduction ...............................................................................................................
31.1.1 Purpose of the Peripheral ....................................................................................
31.1.2 Features ........................................................................................................
31.1.3 Block Diagram .................................................................................................
31.1.4 Industry Standard Compatibility Statement ................................................................
31.1.5 Architecture – General-Purpose Timer Mode .............................................................
31.1.6 Architecture – Watchdog Timer Mode ......................................................................
31.1.7 Reset Considerations .........................................................................................
31.1.8 Interrupt Support ..............................................................................................
31.1.9 DMA Event Support ...........................................................................................
31.1.10 TM64P_OUT Event Support ...............................................................................
31.1.11 Interrupt/DMA Event Generation Control and Status ...................................................
31.1.12 Power Management .........................................................................................
31.1.13 Emulation Considerations ..................................................................................
Registers .................................................................................................................
31.2.1 Revision ID Register (REVID) ...............................................................................
31.2.2 Emulation Management Register (EMUMGT) .............................................................
31.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ............................................
31.2.4 GPIO Data and Direction Register (GPDATGPDIR) .....................................................
31.2.5 Timer Counter Registers (TIM12 and TIM34) .............................................................
31.2.6 Timer Period Registers (PRD12 and PRD34) .............................................................
31.2.7 Timer Control Register (TCR) ...............................................................................
31.2.8 Timer Global Control Register (TGCR).....................................................................
31.2.9 Watchdog Timer Control Register (WDTCR) ..............................................................
31.2.10 Timer Reload Register 12 (REL12) .......................................................................
31.2.11 Timer Reload Register 34 (REL34) .......................................................................
31.2.12 Timer Capture Register 12 (CAP12) ......................................................................
31.2.13 Timer Capture Register 34 (CAP34) ......................................................................
31.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) ..........................................
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1485
1485
1486
1486
1486
1498
1500
1500
1500
1501
1502
1502
1502
1503
1505
1505
1506
1507
1508
1509
1510
1512
1513
1514
1514
1515
1515
1516
....................................................... 1518
Introduction ............................................................................................................... 1519
32.1.1 Purpose of the Peripheral .................................................................................... 1519
32.1.2 Features ........................................................................................................ 1519
32.1.3 Functional Block Diagram .................................................................................... 1519
32.1.4 Industry Standard(s) Compliance Statement .............................................................. 1519
Peripheral Architecture ................................................................................................. 1521
32.2.1 Clock Generation and Control ............................................................................... 1521
Universal Asynchronous Receiver/Transmitter (UART)
32.1
32.2
20
SPI Flag Register (SPIFLG) .................................................................................
SPI Pin Control Register 0 (SPIPC0) ......................................................................
SPI Pin Control Register 1 (SPIPC1) .......................................................................
SPI Pin Control Register 2 (SPIPC2) .......................................................................
SPI Pin Control Register 3 (SPIPC3) .......................................................................
SPI Pin Control Register 4 (SPIPC4) .....................................................................
SPI Pin Control Register 5 (SPIPC5) .....................................................................
SPI Transmit Data Register 0 (SPIDAT0) ................................................................
SPI Transmit Data Register 1 (SPIDAT1) ................................................................
SPI Receive Buffer Register (SPIBUF) ...................................................................
SPI Emulation Register (SPIEMU) ........................................................................
SPI Delay Register (SPIDELAY) ..........................................................................
SPI Default Chip Select Register (SPIDEF) ..............................................................
SPI Data Format Registers (SPIFMTn) ...................................................................
SPI Interrupt Vector Register 1 (INTVEC1) ..............................................................
Contents
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32.3
33
32.2.2 Signal Descriptions............................................................................................
32.2.3 Pin Multiplexing ................................................................................................
32.2.4 Protocol Description ..........................................................................................
32.2.5 Operation .......................................................................................................
32.2.6 Reset Considerations .........................................................................................
32.2.7 Initialization .....................................................................................................
32.2.8 Interrupt Support ..............................................................................................
32.2.9 DMA Event Support ...........................................................................................
32.2.10 Power Management .........................................................................................
32.2.11 Emulation Considerations ..................................................................................
32.2.12 Exception Processing .......................................................................................
Registers .................................................................................................................
32.3.1 Receiver Buffer Register (RBR) .............................................................................
32.3.2 Transmitter Holding Register (THR) ........................................................................
32.3.3 Interrupt Enable Register (IER) .............................................................................
32.3.4 Interrupt Identification Register (IIR) ........................................................................
32.3.5 FIFO Control Register (FCR) ................................................................................
32.3.6 Line Control Register (LCR) .................................................................................
32.3.7 Modem Control Register (MCR) .............................................................................
32.3.8 Line Status Register (LSR) ..................................................................................
32.3.9 Modem Status Register (MSR) ..............................................................................
32.3.10 Scratch Pad Register (SCR) ...............................................................................
32.3.11 Divisor Latches (DLL and DLH) ............................................................................
32.3.12 Revision Identification Registers (REVID1 and REVID2) ..............................................
32.3.13 Power and Emulation Management Register (PWREMU_MGMT) ...................................
32.3.14 Mode Definition Register (MDR) ...........................................................................
Universal Parallel Port (uPP)
33.1
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33.3
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Introduction ...............................................................................................................
33.1.1 Purpose of the Peripheral ....................................................................................
33.1.2 Features ........................................................................................................
33.1.3 Functional Block Diagram ....................................................................................
Architecture ..............................................................................................................
33.2.1 Clock Generation and Control ...............................................................................
33.2.2 Signal Description .............................................................................................
33.2.3 Pin Multiplexing ................................................................................................
33.2.4 Internal DMA Controller Description ........................................................................
33.2.5 Protocol Description ..........................................................................................
33.2.6 Initialization and Operation ...................................................................................
33.2.7 Reset Considerations .........................................................................................
33.2.8 Interrupt Support ..............................................................................................
33.2.9 Power Management ..........................................................................................
33.2.10 Emulation Considerations ..................................................................................
33.2.11 Transmit and Receive FIFOs...............................................................................
Registers .................................................................................................................
33.3.1 uPP Peripheral Identification Register (UPPID) ...........................................................
33.3.2 uPP Peripheral Control Register (UPPCR) ................................................................
33.3.3 uPP Digital Loopback Register (UPDLB) ..................................................................
33.3.4 uPP Channel Control Register (UPCTL) ...................................................................
33.3.5 uPP Interface Configuration Register (UPICR)............................................................
33.3.6 uPP Interface Idle Value Register (UPIVR) ................................................................
33.3.7 uPP Threshold Configuration Register (UPTCR) .........................................................
33.3.8 uPP Interrupt Raw Status Register (UPISR) ..............................................................
33.3.9 uPP Interrupt Enabled Status Register (UPIER) ..........................................................
SPRUH77C – April 2013 – Revised September 2016
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33.3.10
33.3.11
33.3.12
33.3.13
33.3.14
33.3.15
33.3.16
33.3.17
33.3.18
33.3.19
33.3.20
33.3.21
33.3.22
33.3.23
33.3.24
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34.2
34.3
Introduction ...............................................................................................................
34.1.1 Purpose of the Peripheral ....................................................................................
Architecture ..............................................................................................................
34.2.1 Clock and Reset ..............................................................................................
34.2.2 Open Host Controller Interface Functionality ..............................................................
34.2.3 Differences From OHCI Specification for USB ............................................................
34.2.4 Implementation of OHCI Specification for USB1.1 .......................................................
34.2.5 OHCI Interrupts ................................................................................................
34.2.6 USB1.1 Host Controller Access to System Memory ......................................................
34.2.7 Physical Addressing ..........................................................................................
Registers .................................................................................................................
34.3.1 OHCI Revision Number Register (HCREVISION) ........................................................
34.3.2 HC Operating Mode Register (HCCONTROL) ............................................................
34.3.3 HC Command and Status Register (HCCOMMANDSTATUS)..........................................
34.3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) ...........................................
34.3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) ...............................................
34.3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) ..............................................
34.3.7 HC HCAA Address Register (HCHCCA) ...................................................................
34.3.8 HC Current Periodic Register (HCPERIODCURRENTED) ..............................................
34.3.9 HC Head Control Register (HCCONTROLHEADED) ....................................................
34.3.10 HC Current Control Register (HCCONTROLCURRENTED)...........................................
34.3.11 HC Head Bulk Register (HCBULKHEADED) ............................................................
34.3.12 HC Current Bulk Register (HCBULKCURRENTED) ....................................................
34.3.13 HC Head Done Register (HCDONEHEAD) ..............................................................
34.3.14 HC Frame Interval Register (HCFMINTERVAL) .........................................................
34.3.15 HC Frame Remaining Register (HCFMREMAINING) ..................................................
34.3.16 HC Frame Number Register (HCFMNUMBER) .........................................................
34.3.17 HC Periodic Start Register (HCPERIODICSTART) .....................................................
34.3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD) .............................................
34.3.19 HC Root Hub A Register (HCRHDESCRIPTORA) ......................................................
34.3.20 HC Root Hub B Register (HCRHDESCRIPTORB) ......................................................
34.3.21 HC Root Hub Status Register (HCRHSTATUS) .........................................................
34.3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .....................................
34.3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .....................................
Universal Serial Bus 2.0 (USB) Controller
35.1
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Universal Serial Bus OHCI Host Controller ......................................................................... 1597
34.1
35
uPP Interrupt Enable Set Register (UPIES) ..............................................................
uPP Interrupt Enable Clear Register (UPIEC) ...........................................................
uPP End of Interrupt Register (UPEOI) ...................................................................
uPP DMA Channel I Descriptor 0 Register (UPID0) ....................................................
uPP DMA Channel I Descriptor 1 Register (UPID1) ....................................................
uPP DMA Channel I Descriptor 2 Register (UPID2) ....................................................
uPP DMA Channel I Status 0 Register (UPIS0) .........................................................
uPP DMA Channel I Status 1 Register (UPIS1) .........................................................
uPP DMA Channel I Status 2 Register (UPIS2) .........................................................
uPP DMA Channel Q Descriptor 0 Register (UPQD0) .................................................
uPP DMA Channel Q Descriptor 1 Register (UPQD1) .................................................
uPP DMA Channel Q Descriptor 2 Register (UPQD2) .................................................
uPP DMA Channel Q Status 0 Register (UPQS0) ......................................................
uPP DMA Channel Q Status 1 Register (UPQS1) ......................................................
uPP DMA Channel Q Status 2 Register (UPQS2) ......................................................
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.......................................................................... 1623
Introduction ............................................................................................................... 1624
35.1.1 Purpose of the Peripheral .................................................................................... 1624
Contents
SPRUH77C – April 2013 – Revised September 2016
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35.2
35.3
35.4
35.1.2 Features ........................................................................................................
35.1.3 Functional Block Diagram ....................................................................................
35.1.4 Industry Standard(s) Compliance Statement ..............................................................
Architecture ..............................................................................................................
35.2.1 Clock Control ..................................................................................................
35.2.2 Signal Descriptions............................................................................................
35.2.3 Indexed and Non-Indexed Registers .......................................................................
35.2.4 USB PHY Initialization ........................................................................................
35.2.5 VBUS Voltage Sourcing Control ............................................................................
35.2.6 Dynamic FIFO Sizing .........................................................................................
35.2.7 USB Controller Host and Peripheral Modes Operation ..................................................
35.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ............................
35.2.9 Test Modes.....................................................................................................
35.2.10 Reset Considerations .......................................................................................
35.2.11 Interrupt Support .............................................................................................
35.2.12 DMA Event Support .........................................................................................
35.2.13 Power Management .........................................................................................
Use Cases................................................................................................................
35.3.1 User Case 1: Example of How to Initialize the USB Controller .........................................
35.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode .................
35.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode........................
35.3.4 User Case 4: Example of How to Program the USB DMA Controller ..................................
Registers .................................................................................................................
35.4.1 Revision Identification Register (REVID) ...................................................................
35.4.2 Control Register (CTRLR)....................................................................................
35.4.3 Status Register (STATR) .....................................................................................
35.4.4 Emulation Register (EMUR) .................................................................................
35.4.5 Mode Register (MODE) ......................................................................................
35.4.6 Auto Request Register (AUTOREQ) .......................................................................
35.4.7 SRP Fix Time Register (SRPFIXTIME) ....................................................................
35.4.8 Teardown Register (TEARDOWN)..........................................................................
35.4.9 USB Interrupt Source Register (INTSRCR) ...............................................................
35.4.10 USB Interrupt Source Set Register (INTSETR)..........................................................
35.4.11 USB Interrupt Source Clear Register (INTCLRR) .......................................................
35.4.12 USB Interrupt Mask Register (INTMSKR) ................................................................
35.4.13 USB Interrupt Mask Set Register (INTMSKSETR) ......................................................
35.4.14 USB Interrupt Mask Clear Register (INTMSKCLRR) ...................................................
35.4.15 USB Interrupt Source Masked Register (INTMASKEDR) ..............................................
35.4.16 USB End of Interrupt Register (EOIR) ....................................................................
35.4.17 Generic RNDIS EP1 Size Register (GENRNDISSZ1) .................................................
35.4.18 Generic RNDIS EP2 Size Register (GENRNDISSZ2) .................................................
35.4.19 Generic RNDIS EP3 Size Register (GENRNDISSZ3) .................................................
35.4.20 Generic RNDIS EP4 Size Register (GENRNDISSZ4) .................................................
35.4.21 Function Address Register (FADDR) .....................................................................
35.4.22 Power Management Register (POWER) .................................................................
35.4.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................
35.4.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .............................................
35.4.25 Interrupt Enable Register for INTRTX (INTRTXE) ......................................................
35.4.26 Interrupt Enable Register for INTRRX (INTRRXE) ......................................................
35.4.27 Interrupt Register for Common USB Interrupts (INTRUSB)............................................
35.4.28 Interrupt Enable Register for INTRUSB (INTRUSBE) ..................................................
35.4.29 Frame Number Register (FRAME) ........................................................................
35.4.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX)..................
SPRUH77C – April 2013 – Revised September 2016
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35.4.31 Register to Enable the USB 2.0 Test Modes (TESTMODE) ...........................................
35.4.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)...........................
35.4.33 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..........................
35.4.34 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...............................
35.4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ..........................
35.4.36 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...............................
35.4.37 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ...........................
35.4.38 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..........................
35.4.39 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...............................
35.4.40 Count 0 Register (COUNT0) ...............................................................................
35.4.41 Receive Count Register (RXCOUNT) .....................................................................
35.4.42 Type Register (Host mode only) (HOST_TYPE0) ......................................................
35.4.43 Transmit Type Register (Host mode only) (HOST_TXTYPE) .........................................
35.4.44 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ..........................................
35.4.45 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................
35.4.46 Receive Type Register (Host mode only) (HOST_RXTYPE) .........................................
35.4.47 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................
35.4.48 Configuration Data Register (CONFIGDATA) ...........................................................
35.4.49 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .........................................
35.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .........................................
35.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .........................................
35.4.52 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .........................................
35.4.53 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .........................................
35.4.54 Device Control Register (DEVCTL) .......................................................................
35.4.55 Transmit Endpoint FIFO Size (TXFIFOSZ)...............................................................
35.4.56 Receive Endpoint FIFO Size (RXFIFOSZ) ...............................................................
35.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR) ......................................................
35.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) ......................................................
35.4.59 Hardware Version Register (HWVERS) ..................................................................
35.4.60 Transmit Function Address (TXFUNCADDR) ............................................................
35.4.61 Transmit Hub Address (TXHUBADDR) ...................................................................
35.4.62 Transmit Hub Port (TXHUBPORT) ........................................................................
35.4.63 Receive Function Address (RXFUNCADDR) ............................................................
35.4.64 Receive Hub Address (RXHUBADDR) ...................................................................
35.4.65 Receive Hub Port (RXHUBPORT) ........................................................................
35.4.66 CDMA Revision Identification Register (DMAREVID) ..................................................
35.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ................................
35.4.68 CDMA Emulation Control Register (DMAEMU) .........................................................
35.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3]) ...............
35.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3]) ...............
35.4.71 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]RXHPCRA[3]) ...................................................................................................
35.4.72 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]RXHPCRB[3]) ...................................................................................................
35.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL) ............................................
35.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63]) ...................................
35.4.75 Queue Manager Revision Identification Register (QMGRREVID) ....................................
35.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................
35.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ...................
35.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ...................
35.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ...................
35.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ...................
35.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ..................
35.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ..............................
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SPRUH77C – April 2013 – Revised September 2016
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35.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ..................
35.4.84 Queue Manager Queue Pending Register 0 (PEND0) .................................................
35.4.85 Queue Manager Queue Pending Register 1 (PEND1) .................................................
35.4.86 Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]QMEMRBASE[15]) .............................................................................................
35.4.87 Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ...
35.4.88 Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]) ..............................
35.4.89 Queue Manager Queue N Status Register A (QSTATA[0]-QSTATA[63]) ...........................
35.4.90 Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) ...........................
35.4.91 Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) ...........................
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Video Port Interface (VPIF) ............................................................................................... 1775
36.1
36.2
36.3
Introduction ...............................................................................................................
36.1.1 Overview .......................................................................................................
36.1.2 Features ........................................................................................................
36.1.3 Features Not Supported ......................................................................................
36.1.4 Functional Block Diagram ....................................................................................
Architecture ..............................................................................................................
36.2.1 Clock Control ..................................................................................................
36.2.2 Signal Descriptions............................................................................................
36.2.3 Memory Interface ..............................................................................................
36.2.4 Video Transmit ................................................................................................
36.2.5 Video Receive .................................................................................................
36.2.6 Raw Data Capture ............................................................................................
36.2.7 VBI Ancillary Data .............................................................................................
36.2.8 Reset Considerations .........................................................................................
36.2.9 Initialization .....................................................................................................
36.2.10 Interrupt Support .............................................................................................
Registers .................................................................................................................
36.3.1 VPIF Revision Register ID (REVID) ........................................................................
36.3.2 Channel 0 Control Register (C0CTRL) .....................................................................
36.3.3 Channel 1 Control Register (C1CTRL) .....................................................................
36.3.4 Channel 2 Control Register (C2CTRL) .....................................................................
36.3.5 Channel 3 Control Register (C3CTRL) .....................................................................
36.3.6 Interrupt Enable Register (INTEN) ..........................................................................
36.3.7 Interrupt Enable Set Register (INTSET)....................................................................
36.3.8 Interrupt Enable Clear Register (INTCLR) .................................................................
36.3.9 Interrupt Status Register (INTSTAT) .......................................................................
36.3.10 Interrupt Status Clear Register (INTSTATCLR) .........................................................
36.3.11 Emulation Suspend Control Register (EMUCTRL) ......................................................
36.3.12 DMA Size Control Register (REQSIZE) ..................................................................
36.3.13 Channel n Top Field Luminance Address Register (CnTLUMA) ......................................
36.3.14 Channel n Bottom Field Luminance Address Register (CnBLUMA) ..................................
36.3.15 Channel n Top Field Chrominance Address Register (CnTCHROMA) ...............................
36.3.16 Channel n Bottom Field Chrominance Address Register (CnBCHROMA)...........................
36.3.17 Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) ............................
36.3.18 Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) ........................
36.3.19 Channel n Top Field Vertical Ancillary Address Register (CnTVANC) ...............................
36.3.20 Channel n Bottom Field Vertical Ancillary Address Register (CnBVANC) ...........................
36.3.21 Channel n Image Address Offset Register (CnIMGOFFSET) .........................................
36.3.22 Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) .......................
36.3.23 Channel n Horizontal Size Configuration Register (C0HCFG and C1HCFG) .......................
36.3.24 Channel n Vertical Size Configuration 0 Register (C0VCFG0 and C1VCFG0) .....................
36.3.25 Channel n Vertical Size Configuration 1 Register (C0VCFG1 and C1VCFG1) .....................
SPRUH77C – April 2013 – Revised September 2016
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36.3.26 Channel n Vertical Size Configuration 2 Register (C0VCFG2 and C1VCFG2) .....................
36.3.27 Channel n Vertical Image Size Register (C0VSIZE and C1VSIZE) ...................................
36.3.28 Channel n Horizontal Size Configuration Register (C2HCFG and C3HCFG) .......................
36.3.29 Channel n Vertical Size Configuration 0 Register (C2VCFG0 and C3VCFG0) .....................
36.3.30 Channel n Vertical Size Configuration 1 Register (C2VCFG1 and C3VCFG1) .....................
36.3.31 Channel n Vertical Size Configuration 2 Register (C2VCFG2 and C3VCFG2) .....................
36.3.32 Channel n Vertical Image Size Register (C2VSIZE and C3VSIZE) ...................................
36.3.33 Channel n Top Field Horizontal Ancillary Position Register (C2THANCPOS and
C3THANCPOS) ................................................................................................
36.3.34 Channel n Top Field Horizontal Ancillary Size Register (C2THANCSIZE and C3THANCSIZE) ..
36.3.35 Channel n Bottom Field Horizontal Ancillary Position Register (C2BHANCPOS and
C3BHANCPOS) ................................................................................................
36.3.36 Channel n Bottom Field Horizontal Ancillary Size Register (C2BHANCSIZE and
C3BHANCSIZE) ................................................................................................
36.3.37 Channel n Top Field Vertical Ancillary Position Register (C2TVANCPOS and C3TVANCPOS) .
36.3.38 Channel n Top Field Vertical Ancillary Size Register (C2TVANCSIZE and C3TVANCSIZE) .....
36.3.39 Channel n Bottom Field Vertical Ancillary Position Register (C2BVANCPOS and
C3BVANCPOS) ................................................................................................
36.3.40 Channel n Bottom Field Vertical Ancillary Size Register (C2BVANCSIZE and C3BVANCSIZE) .
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Revision History ...................................................................................................................... 1836
26
Contents
SPRUH77C – April 2013 – Revised September 2016
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List of Figures
1-1.
OMAP-L138 Applications Processor Block Diagram .................................................................. 83
3-1.
TMS320C674x Megamodule Block Diagram ........................................................................... 93
4-1.
System Interconnect Block Diagram ................................................................................... 102
6-1.
MPU Block Diagram ...................................................................................................... 107
6-2.
Permission Fields ......................................................................................................... 110
6-3.
Revision ID Register (REVID) ........................................................................................... 115
6-4.
Configuration Register (CONFIG) ...................................................................................... 115
6-5.
Interrupt Raw Status/Set Register (IRAWSTAT)
6-6.
Interrupt Enable Status/Clear Register (IENSTAT)................................................................... 117
6-7.
Interrupt Enable Set Register (IENSET) ............................................................................... 118
6-8.
Interrupt Enable Clear Register (IENCLR)
6-9.
Fixed Range Start Address Register (FXD_MPSAR) ................................................................ 119
6-10.
Fixed Range End Address Register (FXD_MPEAR) ................................................................. 119
6-11.
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ........................................ 120
6-12.
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) ...................................... 121
6-13.
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) ...................................... 121
6-14.
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) ....................................... 122
6-15.
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ....................................... 122
6-16.
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) ......................... 123
6-17.
Fault Address Register (FLTADDRR) .................................................................................. 124
6-18.
Fault Status Register (FLTSTAT) ....................................................................................... 125
6-19.
Fault Clear Register (FLTCLR)
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
.....................................................................
............................................................................
.........................................................................................
Overall Clocking Diagram................................................................................................
USB Clocking Diagram...................................................................................................
DDR2/mDDR Memory Controller Clocking Diagram .................................................................
EMIFA Clocking Diagram ................................................................................................
EMAC Clocking Diagram ................................................................................................
uPP Clocking Diagram ...................................................................................................
McASP Clocking Diagram ...............................................................................................
PLLC Structure ............................................................................................................
PLLC0 Revision Identification Register (REVID) .....................................................................
PLLC1 Revision Identification Register (REVID) .....................................................................
Reset Type Status Register (RSTYPE) ................................................................................
Reset Control Register (RSCTRL) .....................................................................................
PLLC0 Control Register (PLLCTL) .....................................................................................
PLLC1 Control Register (PLLCTL) .....................................................................................
PLLC0 OBSCLK Select Register (OCSEL) ...........................................................................
PLLC1 OBSCLK Select Register (OCSEL) ...........................................................................
PLL Multiplier Control Register (PLLM) ................................................................................
PLLC0 Pre-Divider Control Register (PREDIV) .......................................................................
PLLC0 Divider 1 Register (PLLDIV1) ..................................................................................
PLLC1 Divider 1 Register (PLLDIV1) ..................................................................................
PLLC0 Divider 2 Register (PLLDIV2) .................................................................................
PLLC1 Divider 2 Register (PLLDIV2) .................................................................................
PLLC0 Divider 3 Register (PLLDIV3) .................................................................................
PLLC1 Divider 3 Register (PLLDIV3) .................................................................................
PLLC0 Divider 4 Register (PLLDIV4) ..................................................................................
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8-19.
PLLC0 Divider 5 Register (PLLDIV5) .................................................................................. 159
8-20.
PLLC0 Divider 6 Register (PLLDIV6) .................................................................................. 160
8-21.
PLLC0 Divider 7 Register (PLLDIV7) .................................................................................. 160
8-22.
PLLC0 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 161
8-23.
PLLC1 Oscillator Divider 1 Register (OSCDIV) ....................................................................... 161
8-24.
PLL Post-Divider Control Register (POSTDIV) ....................................................................... 162
8-25.
PLL Controller Command Register (PLLCMD)
162
8-26.
PLL Controller Status Register (PLLSTAT)
163
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
10-1.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
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.......................................................................
...........................................................................
PLLC0 Clock Align Control Register (ALNCTL) ......................................................................
PLLC1 Clock Align Control Register (ALNCTL) ......................................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) .......................................................
PLLC0 Clock Enable Control Register (CKEN) .......................................................................
PLLC1 Clock Enable Control Register (CKEN) .......................................................................
PLLC0 Clock Status Register (CKSTAT) ..............................................................................
PLLC1 Clock Status Register (CKSTAT) ..............................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ..........................................................................
PLLC1 SYSCLK Status Register (SYSTAT) ..........................................................................
Emulation Performance Counter 0 Register (EMUCNT0) ...........................................................
Emulation Performance Counter 1 Register (EMUCNT1) ...........................................................
Revision Identification Register (REVID) ..............................................................................
Interrupt Evaluation Register (INTEVAL) ..............................................................................
PSC0 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC1 Module Error Pending Register 0 (MERRPR0) ...............................................................
PSC0 Module Error Clear Register 0 (MERRCR0) ..................................................................
PSC1 Module Error Clear Register 0 (MERRCR0) ..................................................................
Power Error Pending Register (PERRPR) ............................................................................
Power Error Clear Register (PERRCR) ................................................................................
Power Domain Transition Command Register (PTCMD)............................................................
Power Domain Transition Status Register (PTSTAT) ................................................................
Power Domain 0 Status Register (PDSTAT0) ........................................................................
Power Domain 1 Status Register (PDSTAT1) ........................................................................
Power Domain 0 Control Register (PDCTL0) .........................................................................
Power Domain 1 Control Register (PDCTL1) .........................................................................
Power Domain 0 Configuration Register (PDCFG0) .................................................................
Power Domain 1 Configuration Register (PDCFG1) .................................................................
Module Status n Register (MDSTATn) .................................................................................
PSC0 Module Control n Register (MDCTLn) .........................................................................
PSC1 Module Control n Register (MDCTLn) .........................................................................
Deep Sleep Mode Sequence ............................................................................................
Revision Identification Register (REVID) ..............................................................................
Device Identification Register 0 (DEVIDR0) ...........................................................................
Boot Configuration Register (BOOTCFG) .............................................................................
Chip Revision Identification Register (CHIPREVIDR)................................................................
Kick 0 Register (KICK0R) ................................................................................................
Kick 1 Register (KICK1R) ................................................................................................
Host 0 Configuration Register (HOST0CFG) .........................................................................
Host 1 Configuration Register (HOST1CFG) .........................................................................
Interrupt Raw Status/Set Register (IRAWSTAT) .....................................................................
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SPRUH77C – April 2013 – Revised September 2016
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11-10. Interrupt Enable Status/Clear Register (IENSTAT)................................................................... 229
11-11. Interrupt Enable Register (IENSET) .................................................................................... 230
............................................................................
.........................................................................................
Fault Address Register (FLTADDRR) ..................................................................................
Fault Status Register (FLTSTAT) .......................................................................................
Master Priority 0 Register (MSTPRI0) .................................................................................
Master Priority 1 Register (MSTPRI1) .................................................................................
Master Priority 2 Register (MSTPRI2) .................................................................................
Pin Multiplexing Control 0 Register (PINMUX0) ......................................................................
Pin Multiplexing Control 1 Register (PINMUX1) ......................................................................
Pin Multiplexing Control 2 Register (PINMUX2) ......................................................................
Pin Multiplexing Control 3 Register (PINMUX3) ......................................................................
Pin Multiplexing Control 4 Register (PINMUX4) ......................................................................
Pin Multiplexing Control 5 Register (PINMUX5) ......................................................................
Pin Multiplexing Control 6 Register (PINMUX6) ......................................................................
Pin Multiplexing Control 7 Register (PINMUX7) ......................................................................
Pin Multiplexing Control 8 Register (PINMUX8) ......................................................................
Pin Multiplexing Control 9 Register (PINMUX9) ......................................................................
Pin Multiplexing Control 10 Register (PINMUX10) ...................................................................
Pin Multiplexing Control 11 Register (PINMUX11) ...................................................................
Pin Multiplexing Control 12 Register (PINMUX12) ...................................................................
Pin Multiplexing Control 13 Register (PINMUX13) ...................................................................
Pin Multiplexing Control 14 Register (PINMUX14) ...................................................................
Pin Multiplexing Control 15 Register (PINMUX15) ...................................................................
Pin Multiplexing Control 16 Register (PINMUX16) ...................................................................
Pin Multiplexing Control 17 Register (PINMUX17) ...................................................................
Pin Multiplexing Control 18 Register (PINMUX18) ...................................................................
Pin Multiplexing Control 19 Register (PINMUX19) ...................................................................
Suspend Source Register (SUSPSRC) ................................................................................
Chip Signal Register (CHIPSIG) ........................................................................................
Chip Signal Clear Register (CHIPSIG_CLR) ..........................................................................
Chip Configuration 0 Register (CFGCHIP0) ..........................................................................
Chip Configuration 1 Register (CFGCHIP1) ..........................................................................
Chip Configuration 2 Register (CFGCHIP2) ..........................................................................
Chip Configuration 3 Register (CFGCHIP3) ..........................................................................
Chip Configuration 4 Register (CFGCHIP4) ..........................................................................
VTP I/O Control Register (VTPIO_CTL) ...............................................................................
DDR Slew Register (DDR_SLEW) .....................................................................................
Deep Sleep Register (DEEPSLEEP) ...................................................................................
Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................................
Pullup/Pulldown Select Register (PUPD_SEL) .......................................................................
RXACTIVE Control Register (RXACTIVE) ............................................................................
Power Down Control Register (PWRDN) ..............................................................................
AINTC Interrupt Mapping ................................................................................................
Flow of System Interrupts to Host ......................................................................................
Revision Identification Register (REVID) ..............................................................................
Control Register (CR) ....................................................................................................
Global Enable Register (GER) ..........................................................................................
11-12. Interrupt Enable Clear Register (IENCLR)
230
11-13. End of Interrupt Register (EOI)
231
11-14.
231
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
11-26.
11-27.
11-28.
11-29.
11-30.
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
11-44.
11-45.
11-46.
11-47.
11-48.
11-49.
11-50.
11-51.
11-52.
11-53.
12-1.
12-2.
12-3.
12-4.
12-5.
SPRUH77C – April 2013 – Revised September 2016
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List of Figures
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12-6.
Global Nesting Level Register (GNLR) ................................................................................ 308
12-7.
System Interrupt Status Indexed Set Register (SISR) ............................................................... 309
12-8.
System Interrupt Status Indexed Clear Register (SICR)
12-9.
System Interrupt Enable Indexed Set Register (EISR) .............................................................. 310
............................................................
309
12-10. System Interrupt Enable Indexed Clear Register (EICR) ............................................................ 310
12-11. Host Interrupt Enable Indexed Set Register (HEISR) ................................................................ 311
12-12. Host Interrupt Enable Indexed Clear Register (HIEICR)
............................................................
311
12-13. Vector Base Register (VBR)............................................................................................. 312
312
12-15.
313
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
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12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
30
.............................................................................................
Vector Null Register (VNR) ..............................................................................................
Global Prioritized Index Register (GPIR) ..............................................................................
Global Prioritized Vector Register (GPVR) ............................................................................
System Interrupt Status Raw/Set Register 1 (SRSR1) ..............................................................
System Interrupt Status Raw/Set Register 2 (SRSR2) ..............................................................
System Interrupt Status Raw/Set Register 3 (SRSR3) ..............................................................
System Interrupt Status Raw/Set Register 4 (SRSR4) ..............................................................
System Interrupt Status Enabled/Clear Register 1 (SECR1) .......................................................
System Interrupt Status Enabled/Clear Register 2 (SECR2) .......................................................
System Interrupt Status Enabled/Clear Register 3 (SECR3) .......................................................
System Interrupt Status Enabled/Clear Register 4 (SECR4) .......................................................
System Interrupt Enable Set Register 1 (ESR1)......................................................................
System Interrupt Enable Set Register 2 (ESR2)......................................................................
System Interrupt Enable Set Register 3 (ESR3)......................................................................
System Interrupt Enable Set Register 4 (ESR4)......................................................................
System Interrupt Enable Clear Register 1 (ECR1) ...................................................................
System Interrupt Enable Clear Register 2 (ECR2) ...................................................................
System Interrupt Enable Clear Register 3 (ECR3) ...................................................................
System Interrupt Enable Clear Register 4 (ECR4) ...................................................................
Channel Map Registers (CMRn) ........................................................................................
Host Interrupt Prioritized Index Register 1 (HIPIR1) .................................................................
Host Interrupt Prioritized Index Register 2 (HIPIR2) .................................................................
Host Interrupt Nesting Level Register 1 (HINLR1) ...................................................................
Host Interrupt Nesting Level Register 2 (HINLR2) ...................................................................
Host Interrupt Enable Register (HIER) .................................................................................
Host Interrupt Prioritized Vector Register 1 (HIPVR1) ...............................................................
Host Interrupt Prioritized Vector Register 2 (HIPVR2) ...............................................................
PRU Block Diagram ......................................................................................................
Format 1a: (All Arithmetic and Logical Functions – Register Op2).................................................
Format 1b: (All Arithmetic and Logical Functions – Immediate Op2) ..............................................
Format 2 ...................................................................................................................
Format 2a: (JMP,JAL – Register Op2) .................................................................................
Format 2b: (JMP, JAL – Immediate Op2) .............................................................................
Format 2c: (LDI)...........................................................................................................
Format 2d: (LMBD - Leftmost Bit Detect - Register Op2) ...........................................................
Format 2e: (LMBD - Immediate Op2) ..................................................................................
Format 2f: (SCAN - Register Op2) .....................................................................................
Format 2g: (SCAN - Immediate Op2) ..................................................................................
Format 2h: (HALT) ........................................................................................................
Format 2i: (SLP) ..........................................................................................................
12-14. Vector Size Register (VSR)
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14-14. Format 4a: (Quick Arithmetic Test and Branch – Register Op2) ................................................... 350
14-15. Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2)................................................. 351
14-16. Format 5a: (Quick Bit Test and Branch – Register Op2) ............................................................ 352
.........................................................
Format 6a: (LBBO/SBBO - Register Offset)...........................................................................
Format 6b: (LBBO/SBBO - Immediate Offset) ........................................................................
Format 6c: (LBCO/SBCO - Register Offset) ..........................................................................
Format 6d: (LBCO/SBCO - Immediate Offset) ........................................................................
..............................................................................................................................
..............................................................................................................................
CONTROL Register ......................................................................................................
STATUS Register .........................................................................................................
WAKEUP Register ........................................................................................................
CYCLECNT Register .....................................................................................................
STALLCNT Register ......................................................................................................
CONTABBLKIDX0 Register .............................................................................................
CONTABPROPTR0 Register ...........................................................................................
CONTABPROPTR1 Register ...........................................................................................
INTGPR0 to INTGPR31 Register .......................................................................................
INTCTER0 to INTCTER31 Register ....................................................................................
Data Paths to DDR2/mDDR Memory Controller ......................................................................
DDR2/mDDR Memory Controller Clock Block Diagram .............................................................
DDR2/mDDR Memory Controller Signals .............................................................................
Refresh Command........................................................................................................
DCAB Command..........................................................................................................
DEAC Command..........................................................................................................
ACTV Command ..........................................................................................................
DDR2/mDDR READ Command.........................................................................................
DDR2/mDDR WRT Command ..........................................................................................
DDR2/mDDR MRS and EMRS Command ............................................................................
Byte Alignment ............................................................................................................
DDR2/mDDR SDRAM Column, Row, and Bank Access ............................................................
Address Mapping Diagram (IBANKPOS = 1) .........................................................................
SDRAM Column, Row, Bank Access (IBANKPOS = 1) .............................................................
DDR2/mDDR Memory Controller FIFO Block Diagram ..............................................................
DDR2/mDDR Memory Controller Reset Block Diagram .............................................................
DDR2/mDDR Memory Controller Power Sleep Controller Diagram ...............................................
Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory .........................................
Revision ID Register (REVID) ...........................................................................................
SDRAM Status Register (SDRSTAT) .................................................................................
SDRAM Configuration Register (SDCR) ..............................................................................
SDRAM Refresh Control Register (SDRCR) .........................................................................
SDRAM Timing Register 1 (SDTIMR1) ................................................................................
SDRAM Timing Register 2 (SDTIMR2) ................................................................................
SDRAM Configuration Register 2 (SDCR2) ..........................................................................
Peripheral Bus Burst Priority Register (PBBPR) ......................................................................
Performance Counter 1 Register (PC1) ...............................................................................
Performance Counter 2 Register (PC2) ...............................................................................
Performance Counter Configuration Register (PCC) ................................................................
14-17. Format 5b: (Quick Bit Test and Branch – Immediate Op2)
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
SPRUH77C – April 2013 – Revised September 2016
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List of Figures
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16-6.
16-7.
16-8.
16-9.
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17-2.
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17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
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..................................................
Performance Counter Time Register (PCT) ...........................................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) ............................................................................................
Interrupt Masked Register (IMR)........................................................................................
Interrupt Mask Set Register (IMSR) ....................................................................................
Interrupt Mask Clear Register (IMCR) .................................................................................
DDR PHY Control Register 1 (DRPYC1R) ............................................................................
Multiple eCAP Modules ..................................................................................................
Capture and APWM Modes of Operation..............................................................................
Capture Function Diagram...............................................................................................
Event Prescale Control...................................................................................................
Prescale Function Waveforms ..........................................................................................
Continuous/One-shot Block Diagram ..................................................................................
Counter and Synchronization Block Diagram .........................................................................
Interrupts in eCAP Module ..............................................................................................
PWM Waveform Details Of APWM Mode Operation ................................................................
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ................................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ..................................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect .............................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ...............................
PWM Waveform Details of APWM Mode Operation .................................................................
Multichannel PWM Example Using 4 eCAP Modules................................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules .......................................
Time-Stamp Counter Register (TSCTR) ...............................................................................
Counter Phase Control Register (CTRPHS) .........................................................................
Capture 1 Register (CAP1) .............................................................................................
Capture 2 Register (CAP2) ..............................................................................................
Capture 3 Register (CAP3) ..............................................................................................
Capture 4 Register (CAP4) ..............................................................................................
ECAP Control Register 1 (ECCTL1) ...................................................................................
ECAP Control Register 2 (ECCTL2) ...................................................................................
ECAP Interrupt Enable Register (ECEINT)............................................................................
ECAP Interrupt Flag Register (ECFLG)................................................................................
ECAP Interrupt Clear Register (ECCLR) ..............................................................................
ECAP Interrupt Forcing Register (ECFRC)............................................................................
Revision ID Register (REVID) ...........................................................................................
Multiple ePWM Modules .................................................................................................
Submodules and Signal Connections for an ePWM Module........................................................
ePWM Submodules and Critical Internal Signal Interconnects .....................................................
Time-Base Submodule Block Diagram ................................................................................
Time-Base Submodule Signals and Registers ........................................................................
Time-Base Frequency and Period ......................................................................................
Time-Base Counter Synchronization Scheme 1 ......................................................................
Time-Base Up-Count Mode Waveforms ...............................................................................
Time-Base Down-Count Mode Waveforms ...........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event .....
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ........
Counter-Compare Submodule ..........................................................................................
15-30. Performance Counter Master Region Select Register (PCMRS)
List of Figures
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17-13. Counter-Compare Submodule Signals and Registers ............................................................... 496
17-14. Counter-Compare Event Waveforms in Up-Count Mode ............................................................ 499
17-15. Counter-Compare Events in Down-Count Mode
.....................................................................
499
17-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................... 500
17-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ....................................................................................................................... 500
.............................................................................................
Action-Qualifier Submodule Inputs and Outputs ......................................................................
Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ...........................................
Up-Down-Count Mode Symmetrical Waveform .......................................................................
17-18. Action-Qualifier Submodule
501
17-19.
502
17-20.
17-21.
503
506
17-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................. 507
17-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................... 509
17-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............. 511
17-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................. 513
17-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ........................................................................................... 515
17-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ......................................................................................................................... 517
17-28. Dead-Band Generator Submodule ..................................................................................... 519
17-29. Configuration Options for the Dead-Band Generator Submodule .................................................. 520
17-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................... 522
17-31. PWM-Chopper Submodule .............................................................................................. 523
17-32. PWM-Chopper Submodule Signals and Registers ................................................................... 524
17-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................ 525
17-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
.......
525
17-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ...................................................................................................................... 526
17-36. Trip-Zone Submodule .................................................................................................... 527
17-37. Trip-Zone Submodule Mode Control Logic ............................................................................ 530
17-38. Trip-Zone Submodule Interrupt Logic .................................................................................. 530
17-39. Event-Trigger Submodule
...............................................................................................
531
17-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller ............................................... 532
17-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ........................................ 532
17-42. Event-Trigger Interrupt Generator ...................................................................................... 534
17-43. HRPWM System Interface ............................................................................................... 535
17-44. Resolution Calculations for Conventionally Generated PWM ....................................................... 536
17-45. Operating Logic Using MEP ............................................................................................. 537
.........................................................
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ................................
High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ................................
Simplified ePWM Module ................................................................................................
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ......................................
Control of Four Buck Stages. (Note: FPWM1≠ FPWM2≠ FPWM3≠ FPWM4) ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .........................................................
Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) .............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1).............................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) ...........................................................
17-46. Required PWM Waveform for a Requested Duty = 40.5%
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
SPRUH77C – April 2013 – Revised September 2016
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List of Figures
539
541
541
542
543
544
545
547
548
550
33
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17-56. Half-H Bridge Waveforms for (Note: FPWM2 = FPWM1) .................................................................. 551
17-57. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................... 553
17-58. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ....................................................... 554
17-59. Configuring Two PWM Modules for Phase Control .................................................................. 557
17-60. Timing Waveforms Associated With Phase Control Between 2 Modules ......................................... 558
17-61. Control of a 3-Phase Interleaved DC/DC Converter ................................................................. 559
17-62. 3-Phase Interleaved DC/DC Converter Waveforms for
.............................................................
560
17-63. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1 ) .................................................................... 563
17-64. ZVS Full-H Bridge Waveforms .......................................................................................... 564
17-65. Time-Base Control Register (TBCTL) .................................................................................. 566
17-66. Time-Base Status Register (TBSTS) ................................................................................... 568
17-67. Time-Base Phase Register (TBPHS) .................................................................................. 569
17-68. Time-Base Counter Register (TBCNT)
................................................................................
569
17-69. Time-Base Period Register (TBPRD) .................................................................................. 570
17-70. Counter-Compare Control Register (CMPCTL) ....................................................................... 571
................................................................................
Counter-Compare B Register (CMPB) .................................................................................
Action-Qualifier Output A Control Register (AQCTLA)...............................................................
Action-Qualifier Output B Control Register (AQCTLB)...............................................................
Action-Qualifier Software Force Register (AQSFRC) ................................................................
Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................
Dead-Band Generator Control Register (DBCTL) ....................................................................
Dead-Band Generator Rising Edge Delay Register (DBRED) ......................................................
Dead-Band Generator Falling Edge Delay Register (DBFED) .....................................................
PWM-Chopper Control Register (PCCTL) .............................................................................
Trip-Zone Select Register (TZSEL) ....................................................................................
Trip-Zone Control Register (TZCTL) ...................................................................................
Trip-Zone Enable Interrupt Register (TZEINT) ........................................................................
Trip-Zone Flag Register (TZFLG).......................................................................................
Trip-Zone Clear Register (TZCLR) .....................................................................................
Trip-Zone Force Register (TZFRC).....................................................................................
Event-Trigger Selection Register (ETSEL) ............................................................................
Event-Trigger Prescale Register (ETPS) ..............................................................................
Event-Trigger Flag Register (ETFLG) ..................................................................................
Event-Trigger Clear Register (ETCLR) ................................................................................
Event-Trigger Force Register (ETFRC) ................................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) ..........................................................
Counter-Compare A High-Resolution Register (CMPAHR) .........................................................
HRPWM Configuration Register (HRCNFG) ..........................................................................
EDMA3 Controller Block Diagram ......................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram ...........................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................
Definition of ACNT, BCNT, and CCNT ................................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................
PaRAM Set ................................................................................................................
Linked Transfer Example ................................................................................................
Link-to-Self Transfer Example ..........................................................................................
QDMA Channel to PaRAM Mapping ...................................................................................
17-71. Counter-Compare A Register (CMPA)
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
17-88.
17-89.
17-90.
17-91.
17-92.
17-93.
17-94.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
34
List of Figures
572
573
574
575
576
577
578
579
579
580
581
582
582
583
584
584
585
586
587
587
588
589
589
590
595
598
599
600
601
602
603
611
612
619
SPRUH77C – April 2013 – Revised September 2016
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18-11. Shadow Region Registers ............................................................................................... 621
18-12. Interrupt Diagram ......................................................................................................... 626
18-13. Error Interrupt Operation ................................................................................................. 629
18-14. EDMA3 Prioritization ..................................................................................................... 636
18-15. Block Move Example ..................................................................................................... 640
18-16. Block Move Example PaRAM Configuration .......................................................................... 641
18-17. Subframe Extraction Example
..........................................................................................
642
18-18. Subframe Extraction Example PaRAM Configuration................................................................ 642
18-19. Data Sorting Example .................................................................................................... 643
18-20. Data Sorting Example PaRAM Configuration ......................................................................... 644
18-21. Servicing Incoming McBSP Data Example ............................................................................ 645
18-22. Servicing Incoming McBSP Data Example PaRAM .................................................................. 646
18-23. Servicing Peripheral Burst Example .................................................................................... 647
18-24. Servicing Peripheral Burst Example PaRAM.......................................................................... 647
18-25. Servicing Continuous McBSP Data Example ......................................................................... 648
18-26. Servicing Continuous McBSP Data Example PaRAM ............................................................... 649
18-27. Servicing Continuous McBSP Data Example Reload PaRAM ...................................................... 649
18-28. Ping-Pong Buffering for McBSP Data Example
......................................................................
652
18-29. Ping-Pong Buffering for McBSP Example PaRAM ................................................................... 653
18-30. Ping-Pong Buffering for McBSP Example Pong PaRAM ............................................................ 653
18-31. Ping-Pong Buffering for McBSP Example Ping PaRAM ............................................................. 654
18-32. Intermediate Transfer Completion Chaining Example ............................................................... 656
18-33. Single Large Block Transfer Example
.................................................................................
656
18-34. Smaller Packet Data Transfers Example .............................................................................. 657
18-35. Channel Options Parameter (OPT)..................................................................................... 658
..........................................................................
A Count/B Count Parameter (A_B_CNT) ..............................................................................
Channel Destination Address Parameter (DST) ......................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ...............................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) ......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ...............................................
C Count Parameter (CCNT) .............................................................................................
Revision ID Register (REVID) ...........................................................................................
EDMA3CC Configuration Register (CCCFG) .........................................................................
QDMA Channel n Mapping Register (QCHMAPn) ...................................................................
DMA Channel Queue Number Register n (DMAQNUMn) ...........................................................
QDMA Channel Queue Number Register (QDMAQNUM) ..........................................................
Event Missed Register (EMR)...........................................................................................
Event Missed Clear Register (EMCR) .................................................................................
QDMA Event Missed Register (QEMR)................................................................................
QDMA Event Missed Clear Register (QEMCR) ......................................................................
EDMA3CC Error Register (CCERR) ...................................................................................
EDMA3CC Error Clear Register (CCERRCLR).......................................................................
Error Evaluate Register (EEVAL) .......................................................................................
DMA Region Access Enable Register for Region m (DRAEm) .....................................................
QDMA Region Access Enable for Region m (QRAEm) .............................................................
Event Queue Entry Registers (QxEy) ..................................................................................
Queue n Status Register (QSTATn) ...................................................................................
Queue Watermark Threshold A Register (QWMTHRA) .............................................................
18-36. Channel Source Address Parameter (SRC)
660
18-37.
660
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
661
661
662
663
663
667
667
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
35
www.ti.com
................................................................................
18-61. Event Register (ER) ......................................................................................................
18-62. Event Clear Register (ECR) .............................................................................................
18-63. Event Set Register (ESR)................................................................................................
18-64. Chained Event Register (CER) .........................................................................................
18-65. Event Enable Register (EER) ...........................................................................................
18-66. Event Enable Clear Register (EECR) ..................................................................................
18-67. Event Enable Set Register (EESR) ....................................................................................
18-68. Secondary Event Register (SER) .......................................................................................
18-69. Secondary Event Clear Register (SECR) .............................................................................
18-70. Interrupt Enable Register (IER) .........................................................................................
18-71. Interrupt Enable Clear Register (IECR) ................................................................................
18-72. Interrupt Enable Set Register (IESR) ..................................................................................
18-73. Interrupt Pending Register (IPR)........................................................................................
18-74. Interrupt Clear Register (ICR) ...........................................................................................
18-75. Interrupt Evaluate Register (IEVAL) ....................................................................................
18-76. QDMA Event Register (QER) ...........................................................................................
18-77. QDMA Event Enable Register (QEER) ................................................................................
18-78. QDMA Event Enable Clear Register (QEECR) .......................................................................
18-79. QDMA Event Enable Set Register (QEESR) .........................................................................
18-80. QDMA Secondary Event Register (QSER) ............................................................................
18-81. QDMA Secondary Event Clear Register (QSECR) ..................................................................
18-82. Revision ID Register (REVID) ...........................................................................................
18-83. EDMA3TC Configuration Register (TCCFG) ..........................................................................
18-84. EDMA3TC Channel Status Register (TCSTAT) ......................................................................
18-85. Error Status Register (ERRSTAT) ......................................................................................
18-86. Error Enable Register (ERREN) ........................................................................................
18-87. Error Clear Register (ERRCLR) ........................................................................................
18-88. Error Details Register (ERRDET) .......................................................................................
18-89. Error Interrupt Command Register (ERRCMD) .......................................................................
18-90. Read Command Rate Register (RDRATE)............................................................................
18-91. Source Active Options Register (SAOPT) .............................................................................
18-92. Source Active Source Address Register (SASRC) ...................................................................
18-93. Source Active Count Register (SACNT) ...............................................................................
18-94. Source Active Destination Address Register (SADST) ..............................................................
18-95. Source Active B-Index Register (SABIDX) ............................................................................
18-96. Source Active Memory Protection Proxy Register (SAMPPRXY) ..................................................
18-97. Source Active Count Reload Register (SACNTRLD) ................................................................
18-98. Source Active Source Address B-Reference Register (SASRCBREF) ............................................
18-99. Source Active Destination Address B-Reference Register (SADSTBREF) .......................................
18-100. Destination FIFO Set Count Reload Register (DFCNTRLD) ......................................................
18-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) ..................................
18-102. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) .............................
18-103. Destination FIFO Options Register n (DFOPTn) ....................................................................
18-104. Destination FIFO Source Address Register n (DFSRCn) ..........................................................
18-105. Destination FIFO Count Register n (DFCNTn) ......................................................................
18-106. Destination FIFO Destination Address Register n (DFDSTn) .....................................................
18-107. Destination FIFO B-Index Register n (DFBIDXn) ...................................................................
18-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) .........................................
18-60. EDMA3CC Status Register (CCSTAT)
36
List of Figures
684
686
687
688
689
690
691
691
692
692
693
694
694
695
696
697
698
699
700
700
701
702
704
705
706
707
708
709
710
711
712
713
714
714
715
715
716
717
717
718
718
719
719
720
721
721
722
722
723
SPRUH77C – April 2013 – Revised September 2016
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www.ti.com
19-1.
EMAC and MDIO Block Diagram ....................................................................................... 729
19-2.
Ethernet Configuration—MII Connections ............................................................................. 732
19-3.
Ethernet Configuration—RMII Connections ........................................................................... 734
19-4.
Ethernet Frame Format .................................................................................................. 735
19-5.
Basic Descriptor Format ................................................................................................. 736
19-6.
Typical Descriptor Linked List ........................................................................................... 737
19-7.
Transmit Buffer Descriptor Format ..................................................................................... 740
19-8.
Receive Buffer Descriptor Format ...................................................................................... 743
19-9.
EMAC Control Module Block Diagram ................................................................................. 747
19-10. MDIO Module Block Diagram ........................................................................................... 749
..........................................................................................
EMAC Control Module Revision ID Register (REVID) ...............................................................
EMAC Control Module Software Reset Register (SOFTRESET) ..................................................
EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................
19-11. EMAC Module Block Diagram
753
19-12.
775
19-13.
19-14.
776
777
19-15. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 778
19-16. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 779
19-17. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 780
19-18. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 781
19-19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 782
19-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 783
19-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 784
19-22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
.........
785
19-23. EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........ 786
.......
MDIO Revision ID Register (REVID) ...................................................................................
MDIO Control Register (CONTROL) ...................................................................................
PHY Acknowledge Status Register (ALIVE) ..........................................................................
PHY Link Status Register (LINK) .......................................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ......................................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .....................................
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) .............................
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)............................
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ..........................
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ....................
MDIO User Access Register 0 (USERACCESS0) ...................................................................
MDIO User PHY Select Register 0 (USERPHYSEL0) ...............................................................
MDIO User Access Register 1 (USERACCESS1) ...................................................................
MDIO User PHY Select Register 1 (USERPHYSEL1) ...............................................................
Transmit Revision ID Register (TXREVID) ............................................................................
Transmit Control Register (TXCONTROL) ............................................................................
Transmit Teardown Register (TXTEARDOWN) ......................................................................
Receive Revision ID Register (RXREVID) ............................................................................
Receive Control Register (RXCONTROL) .............................................................................
Receive Teardown Register (RXTEARDOWN) .......................................................................
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)...............................................
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .............................................
Transmit Interrupt Mask Set Register (TXINTMASKSET) ...........................................................
19-24. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX)
787
19-25.
788
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
789
790
790
791
792
793
794
795
796
797
798
799
800
804
804
805
806
806
807
808
809
810
37
www.ti.com
19-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)..................................................... 811
19-49. MAC Input Vector Register (MACINVECTOR)
.......................................................................
812
19-50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................................ 813
19-51. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ............................................... 814
19-52. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
.............................................
815
19-53. Receive Interrupt Mask Set Register (RXINTMASKSET) ........................................................... 816
19-54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ..................................................... 817
19-55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
................................................
818
19-56. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................... 818
19-57. MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................. 819
819
19-59.
820
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
19-73.
19-74.
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
19-82.
19-83.
19-84.
19-85.
19-86.
19-87.
19-88.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
38
......................................................
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......................
Receive Unicast Enable Set Register (RXUNICASTSET) ..........................................................
Receive Unicast Clear Register (RXUNICASTCLEAR) .............................................................
Receive Maximum Length Register (RXMAXLEN) ...................................................................
Receive Buffer Offset Register (RXBUFFEROFFSET) ..............................................................
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ..............................
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) .....................................
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ............................................
MAC Control Register (MACCONTROL) ..............................................................................
MAC Status Register (MACSTATUS) ..................................................................................
Emulation Control Register (EMCONTROL) ..........................................................................
FIFO Control Register (FIFOCONTROL) ..............................................................................
MAC Configuration Register (MACCONFIG) .........................................................................
Soft Reset Register (SOFTRESET) ....................................................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO)...................................................
MAC Source Address High Bytes Register (MACSRCADDRHI) ...................................................
MAC Hash Address Register 1 (MACHASH1) ........................................................................
MAC Hash Address Register 2 (MACHASH2) ........................................................................
Back Off Random Number Generator Test Register (BOFFTEST) ................................................
Transmit Pacing Algorithm Test Register (TPACETEST) ...........................................................
Receive Pause Timer Register (RXPAUSE) ..........................................................................
Transmit Pause Timer Register (TXPAUSE)..........................................................................
MAC Address Low Bytes Register (MACADDRLO)..................................................................
MAC Address High Bytes Register (MACADDRHI) ..................................................................
MAC Index Register (MACINDEX) .....................................................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ..........................................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) ..........................................
Transmit Channel n Completion Pointer Register (TXnCP) .........................................................
Receive Channel n Completion Pointer Register (RXnCP) .........................................................
Statistics Register .........................................................................................................
EMIFA Functional Block Diagram ......................................................................................
Timing Waveform of SDRAM PRE Command ........................................................................
EMIFA to 2M × 16 × 4 bank SDRAM Interface .......................................................................
EMIFA to 512K × 16 × 2 bank SDRAM Interface ....................................................................
Timing Waveform for Basic SDRAM Read Operation ...............................................................
Timing Waveform for Basic SDRAM Write Operation ...............................................................
EMIFA Asynchronous Interface .........................................................................................
EMIFA to 8-bit/16-bit Memory Interface................................................................................
19-58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
List of Figures
823
824
825
825
826
826
827
828
830
832
832
833
833
834
834
835
835
836
836
837
837
838
839
839
840
840
841
841
842
852
856
857
857
864
865
867
868
SPRUH77C – April 2013 – Revised September 2016
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20-9.
Common Asynchronous Interface ...................................................................................... 868
20-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 873
20-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode .............................................. 875
20-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...................................... 877
20-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 879
20-14. EMIFA to NAND Flash Interface ........................................................................................ 881
20-15. ECC Value for 8-Bit NAND Flash ....................................................................................... 883
20-16. EMIFA Reset Block Diagram ............................................................................................ 886
20-17. EMIFA PSC Block Diagram ............................................................................................. 891
20-18. Example Configuration Interface ........................................................................................ 894
20-19. SDRAM Timing Register (SDTIMR) .................................................................................... 895
20-20. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 896
20-21. SDRAM Refresh Control Register (SDRCR) .......................................................................... 896
20-22. SDRAM Configuration Register (SDCR)............................................................................... 897
................................................................................
................................................................................
Timing Waveform of an ASRAM Read with PCB Delays............................................................
Timing Waveform of an ASRAM Write with PCB Delays ............................................................
Timing Waveform of a NAND Flash Read ............................................................................
Timing Waveform of a NAND Flash Command Write ...............................................................
Timing Waveform of a NAND Flash Address Write .................................................................
Timing Waveform of a NAND Flash Data Write .....................................................................
Module ID Register (MIDR)..............................................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) .......................................................
SDRAM Configuration Register (SDCR)...............................................................................
SDRAM Refresh Control Register (SDRCR) ..........................................................................
Asynchronous n Configuration Register (CEnCFG) ..................................................................
SDRAM Timing Register (SDTIMR) ....................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................
EMIFA Interrupt Raw Register (INTRAW) .............................................................................
EMIFA Interrupt Mask Register (INTMSK) ............................................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) ..................................................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) ................................................................
NAND Flash Control Register (NANDFCR) ...........................................................................
NAND Flash Status Register (NANDFSR) ............................................................................
NAND Flash n ECC Register (NANDFnECC) ........................................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ..................................................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..............................................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..............................................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..............................................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..............................................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1).............................................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2).............................................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ................................................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ................................................
GPIO Block Diagram .....................................................................................................
Revision ID Register (REVID) ...........................................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) ................................................................
GPIO Banks 0 and 1 Direction Register (DIR01) .....................................................................
20-23. Timing Waveform of an ASRAM Read
899
20-24. Timing Waveform of an ASRAM Write
900
20-25.
902
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
21-1.
21-2.
21-3.
21-4.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
903
908
910
910
911
916
916
918
920
921
923
924
925
926
927
928
929
931
932
933
934
934
935
935
936
936
937
937
940
949
950
951
39
www.ti.com
21-5.
GPIO Banks 2 and 3 Direction Register (DIR23) ..................................................................... 951
21-6.
GPIO Banks 4 and 5 Direction Register (DIR45) ..................................................................... 951
21-7.
GPIO Banks 6 and 7 Direction Register (DIR67) ..................................................................... 951
21-8.
GPIO Bank 8 Direction Register (DIR8) ............................................................................... 952
21-9.
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) ....................................................... 953
21-10. GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) ....................................................... 953
21-11. GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) ....................................................... 953
21-12. GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) ....................................................... 953
954
21-14.
955
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
40
.................................................................
GPIO Banks 0 and 1 Set Data Register (SET_DATA01)............................................................
GPIO Banks 2 and 3 Set Data Register (SET_DATA23)............................................................
GPIO Banks 4 and 5 Set Data Register (SET_DATA45)............................................................
GPIO Banks 6 and 7 Set Data Register (SET_DATA67)............................................................
GPIO Bank 8 Set Data Register (SET_DATA8) ......................................................................
GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) .........................................................
GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .........................................................
GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) .........................................................
GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) .........................................................
GPIO Bank 8 Clear Data Register (CLR_DATA8) ...................................................................
GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ............................................................
GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ............................................................
GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ............................................................
GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ............................................................
GPIO Bank 8 Input Data Register (IN_DATA8).......................................................................
GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01) .............................................
GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) .............................................
GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) .............................................
GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) .............................................
GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) ........................................................
GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ...........................................
GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) ...........................................
GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ...........................................
GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ...........................................
GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) .....................................................
GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) .............................................
GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) .............................................
GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) .............................................
GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) .............................................
GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8) .......................................................
GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) ..........................................
GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) ..........................................
GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) ..........................................
GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) ..........................................
GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) .....................................................
GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ......................................................
GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ......................................................
GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) ......................................................
GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) ......................................................
GPIO Bank 8 Interrupt Status Register (INTSTAT8) .................................................................
21-13. GPIO Bank 8 Output Data Register (OUT_DATA8)
List of Figures
955
955
955
956
957
957
957
957
958
959
959
959
959
960
961
961
961
961
962
963
963
963
963
964
965
965
965
965
966
967
967
967
967
968
969
969
969
969
970
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
.......................................................................................................
Example of Host-Processor Signal Connections .....................................................................
HPI Strobe and Select Logic ............................................................................................
Multiplexed-Mode Host Read Cycle ....................................................................................
Multiplexed-Mode Host Write Cycle ....................................................................................
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) ...................................................
UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode .........................
HPI Block Diagram
973
978
980
982
983
984
985
22-8.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle) .......................................................... 985
22-9.
UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles) .............................................................. 985
22-10. UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode ................................... 986
22-11. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1:
No Autoincrementing) .................................................................................................... 986
22-12. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2:
Autoincrementing Selected, FIFO Empty Before Write) ............................................................. 986
22-13. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 3:
Autoincrementing Selected, FIFO Not Empty Before Write) ........................................................ 987
22-14. FIFOs in the HPI .......................................................................................................... 988
22-15. Host-to-CPU Interrupt State Diagram .................................................................................. 993
22-16. CPU-to-Host Interrupt State Diagram .................................................................................. 994
22-17. Revision Identification Register (REVID) .............................................................................. 996
22-18. Power and Emulation Management Register (PWREMU_MGMT)
................................................
996
22-19. GPIO Enable Register (GPIO_EN) ..................................................................................... 997
22-20. GPIO Direction 1 Register (GPIO_DIR1) .............................................................................. 998
22-21. GPIO Data 1 Register (GPIO_DAT1) .................................................................................. 998
22-22. GPIO Direction 2 Register (GPIO_DIR2) .............................................................................. 999
22-23. GPIO Data 2 Register (GPIO_DAT2) ................................................................................. 1000
22-24. Host Port Interface Control Register (HPIC)–Host Access Permissions ......................................... 1001
22-25. Host Port Interface Control Register (HPIC)–CPU Access Permissions......................................... 1001
22-26. Host Port Interface Write Address Register (HPIAW) .............................................................. 1003
..............................................................
I2C Peripheral Block Diagram .........................................................................................
Multiple I2C Modules Connected ......................................................................................
Clocking Diagram for the I2C Peripheral .............................................................................
Synchronization of Two I2C Clock Generators During Arbitration ................................................
Bit Transfer on the I2C-Bus ............................................................................................
I2C Peripheral START and STOP Conditions .......................................................................
I2C Peripheral Data Transfer ..........................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) ..........................................
22-27. Host Port Interface Read Address Register (HPIAR)
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
1003
1006
1007
1008
1009
1010
1010
1011
1011
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR) ....................................................................................................... 1012
23-10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR) ............................................................ 1012
23-11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR) .. 1012
23-12. Arbitration Procedure Between Two Master-Transmitters ......................................................... 1015
23-13. I2C Own Address Register (ICOAR).................................................................................. 1020
.................................................................................
I2C Interrupt Status Register (ICSTR) ................................................................................
I2C Clock Low-Time Divider Register (ICCLKL) ....................................................................
I2C Clock High-Time Divider Register (ICCLKH) ...................................................................
23-14. I2C Interrupt Mask Register (ICIMR)
1021
23-15.
1022
23-16.
23-17.
SPRUH77C – April 2013 – Revised September 2016
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List of Figures
1025
1025
41
www.ti.com
1026
23-19.
1027
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
42
....................................................................................
I2C Data Receive Register (ICDRR)..................................................................................
I2C Slave Address Register (ICSAR) .................................................................................
I2C Data Transmit Register (ICDXR) .................................................................................
I2C Mode Register (ICMDR) ...........................................................................................
Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ...................................
I2C Interrupt Vector Register (ICIVR) ................................................................................
I2C Extended Mode Register (ICEMDR) .............................................................................
I2C Prescaler Register (ICPSC) .......................................................................................
I2C Revision Identification Register 1 (REVID1) ....................................................................
I2C Revision Identification Register 2 (REVID2) ....................................................................
I2C DMA Control Register (ICDMAC) ................................................................................
I2C Pin Function Register (ICPFUNC) ...............................................................................
I2C Pin Direction Register (ICPDIR) ..................................................................................
I2C Pin Data In Register (ICPDIN) ....................................................................................
I2C Pin Data Out Register (ICPDOUT) ...............................................................................
I2C Pin Data Set Register (ICPDSET) ...............................................................................
I2C Pin Data Clear Register (ICPDCLR) .............................................................................
LCD Controller ...........................................................................................................
Input and Output Clocks ................................................................................................
Logical Data Path for Raster Controller ..............................................................................
Frame Buffer Structure .................................................................................................
16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP)...............................................................
256-Entry Palette/Buffer Format (8 BPP) ............................................................................
16-BPP Data Memory Organization (TFT Mode Only)—Little Endian ...........................................
12-BPP Data Memory Organization—Little Endian .................................................................
8-BPP Data Memory Organization ...................................................................................
4-BPP Data Memory Organization ....................................................................................
2-BPP Data Memory Organization ....................................................................................
1-BPP Data Memory Organization ....................................................................................
Monochrome and Color Output........................................................................................
Raster Mode Display Format ..........................................................................................
LCD Revision Identification Register (REVID).......................................................................
LCD Control Register (LCD_CTRL) ..................................................................................
LCD Status Register (LCD_STAT) ....................................................................................
LCD LIDD Control Register (LIDD_CTRL) ...........................................................................
LCD LIDD CSn Configuration Register (LIDD_CSn_CONF) ......................................................
LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR) ..............................................
LCD LIDD CSn Data Read/Write Register (LIDD_CSn_DATA)...................................................
LCD Raster Control Register (RASTER_CTRL) ....................................................................
Monochrome Passive Mode Pixel Clock and Data Pin Timing....................................................
Color Passive Mode Pixel Clock and Data Pin Timing .............................................................
Active Mode Pixel Clock and Data Pin Timing ......................................................................
TFT Alternate Signal Mapping Output ................................................................................
12-Bit STN Data in Frame Buffer .....................................................................................
16-Bit STN Data in Frame Buffer .....................................................................................
16-BPP STN Mode ......................................................................................................
LCD Raster Timing Register 0 (RASTER_TIMING_0) .............................................................
LCD Raster Timing Register 1 (RASTER_TIMING_1) .............................................................
23-18. I2C Data Count Register (ICCNT)
List of Figures
1028
1029
1030
1033
1034
1035
1036
1037
1037
1038
1039
1040
1041
1042
1043
1044
1046
1047
1054
1055
1056
1057
1057
1058
1058
1058
1059
1059
1061
1062
1063
1064
1066
1069
1071
1072
1073
1074
1077
1077
1078
1079
1080
1080
1080
1081
1083
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
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......................................................
Vertical Front Porch (VFP) .............................................................................................
Vertical Back Porch (VBP) .............................................................................................
LCD Raster Timing Register 2 (RASTER_TIMING_2) .............................................................
SYNC_CTRL = 0, IPC = 1 in TFT Mode .............................................................................
SYNC_CTRL = 1, SYNC_EDGE = 0, and IPC = 1 .................................................................
LCD Raster Subpanel Display Register (RASTER_SUBPANEL) ................................................
Subpanel Display: SPEN = 1, HOLS = 1 ............................................................................
Subpanel Display: SPEN = 1, HOLS = 0 ............................................................................
LCD DMA Control Register (LCDDMA_CTRL) ......................................................................
LCD DMA Frame Buffer n Base Address Register (LCDDMA_FBn_BASE) ....................................
LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) ..............................
McASP Block Diagram .................................................................................................
McASP to Parallel 2-Channel DACs .................................................................................
McASP to 6-Channel DAC and 2-Channel DAC ....................................................................
McASP to Digital Amplifier .............................................................................................
McASP as Digital Audio Encoder ....................................................................................
TDM Format–6 Channel TDM Example ..............................................................................
TDM Format Bit Delays from Frame Sync ...........................................................................
Inter-IC Sound (I2S) Format ...........................................................................................
Biphase-Mark Code (BMC) ............................................................................................
S/PDIF Subframe Format ..............................................................................................
S/PDIF Frame Format ..................................................................................................
Definition of Bit, Word, and Slot .......................................................................................
Bit Order and Word Alignment Within a Slot Examples ............................................................
Definition of Frame and Frame Sync Width .........................................................................
Transmit Clock Generator Block Diagram ...........................................................................
Receive Clock Generator Block Diagram ............................................................................
Frame Sync Generator Block Diagram ..............................................................................
Individual Serializer and Connections Within McASP ..............................................................
Receive Format Unit ....................................................................................................
Transmit Format Unit ...................................................................................................
McASP I/O Pin Control Block Diagram ...............................................................................
McASP I/O Pin to Control Register Mapping ........................................................................
Burst Frame Sync Mode................................................................................................
Transmit DMA Event (AXEVT) Generation in TDM Time Slots ...................................................
DSP Service Time Upon Transmit DMA Event (AXEVT) ..........................................................
DSP Service Time Upon Receive DMA Event (AREVT) ...........................................................
DMA Events in an Audio Example–Two Events ....................................................................
McASP Audio FIFO (AFIFO) Block Diagram ........................................................................
Data Flow Through Transmit Format Unit ...........................................................................
Data Flow Through Receive Format Unit ............................................................................
Audio Mute (AMUTE) Block Diagram .................................................................................
Transmit Clock Failure Detection Circuit Block Diagram ...........................................................
Receive Clock Failure Detection Circuit Block Diagram ...........................................................
Serializers in Loopback Mode .........................................................................................
Revision Identification Register (REV) ...............................................................................
Pin Function Register (PFUNC) .......................................................................................
Pin Direction Register (PDIR)..........................................................................................
24-32. Vertical Synchronization Pulse Width (VSW) - Active Mode
1084
24-33.
1085
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
SPRUH77C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1086
1087
1089
1090
1091
1092
1092
1093
1094
1094
1098
1099
1099
1100
1100
1101
1102
1102
1103
1104
1105
1106
1107
1108
1110
1111
1112
1113
1114
1115
1117
1118
1123
1126
1131
1133
1135
1136
1139
1141
1143
1147
1148
1149
1155
1156
1158
43
www.ti.com
25-38. Pin Data Output Register (PDOUT)................................................................................... 1160
25-39. Pin Data Input Register (PDIN) ........................................................................................ 1162
25-40. Pin Data Set Register (PDSET) ....................................................................................... 1164
25-41. Pin Data Clear Register (PDCLR)..................................................................................... 1166
25-42. Global Control Register (GBLCTL).................................................................................... 1168
25-43. Audio Mute Control Register (AMUTE) ............................................................................... 1170
25-44. Digital Loopback Control Register (DLBCTL)
.......................................................................
1172
25-45. Digital Mode Control Register (DITCTL) ............................................................................. 1173
25-46. Receiver Global Control Register (RGBLCTL) ...................................................................... 1174
25-47. Receive Format Unit Bit Mask Register (RMASK) .................................................................. 1175
25-48. Receive Bit Stream Format Register (RFMT) ....................................................................... 1176
1178
25-50. Receive Clock Control Register (ACLKRCTL)
1179
25-51.
1180
25-52.
25-53.
25-54.
25-55.
25-56.
25-57.
25-58.
25-59.
25-60.
25-61.
25-62.
25-63.
25-64.
25-65.
25-66.
25-67.
25-68.
25-69.
25-70.
25-71.
25-72.
25-73.
25-74.
25-75.
25-76.
25-77.
25-78.
25-79.
25-80.
25-81.
26-1.
26-2.
26-3.
26-4.
26-5.
44
................................................................
......................................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ................................................
Receive TDM Time Slot Register (RTDM) ...........................................................................
Receiver Interrupt Control Register (RINTCTL) .....................................................................
Receiver Status Register (RSTAT) ...................................................................................
Current Receive TDM Time Slot Registers (RSLOT) ..............................................................
Receive Clock Check Control Register (RCLKCHK) ...............................................................
Receiver DMA Event Control Register (REVTCTL) ................................................................
Transmitter Global Control Register (XGBLCTL) ...................................................................
Transmit Format Unit Bit Mask Register (XMASK) .................................................................
Transmit Bit Stream Format Register (XFMT) .......................................................................
Transmit Frame Sync Control Register (AFSXCTL) ................................................................
Transmit Clock Control Register (ACLKXCTL) ......................................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ................................................
Transmit TDM Time Slot Register (XTDM) ..........................................................................
Transmitter Interrupt Control Register (XINTCTL) ..................................................................
Transmitter Status Register (XSTAT).................................................................................
Current Transmit TDM Time Slot Register (XSLOT) ...............................................................
Transmit Clock Check Control Register (XCLKCHK)...............................................................
Transmitter DMA Event Control Register (XEVTCTL)..............................................................
Serializer Control Registers (SRCTLn) ...............................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .....................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ....................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5).................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ...............................................
Transmit Buffer Registers (XBUFn) ...................................................................................
Receive Buffer Registers (RBUFn) ...................................................................................
AFIFO Revision Identification Register (AFIFOREV) ...............................................................
Write FIFO Control Register (WFIFOCTL) ...........................................................................
Write FIFO Status Register (WFIFOSTS) ............................................................................
Read FIFO Control Register (RFIFOCTL) ...........................................................................
Read FIFO Status Register (RFIFOSTS) ............................................................................
McBSP Block Diagram .................................................................................................
Clock and Frame Generation ..........................................................................................
Transmit Data Clocking .................................................................................................
Receive Data Clocking .................................................................................................
Sample Rate Generator Block Diagram ..............................................................................
25-49. Receive Frame Sync Control Register (AFSRCTL)
List of Figures
1181
1182
1183
1184
1185
1186
1187
1188
1189
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1201
1202
1202
1203
1203
1204
1205
1206
1207
1208
1211
1213
1214
1214
1215
SPRUH77C – April 2013 – Revised September 2016
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26-6.
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ........................... 1218
26-7.
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ........................... 1218
26-8.
Digital Loopback Mode ................................................................................................. 1219
26-9.
Programmable Frame Period and Width ............................................................................. 1221
26-10. Dual-Phase Frame Example ........................................................................................... 1223
26-11. Single-Phase Frame of Four 8-Bit Elements ........................................................................ 1224
26-12. Single-Phase Frame of One 32-Bit Element......................................................................... 1225
26-13. Data Delay
...............................................................................................................
1225
26-14. 2-Bit Data Delay Used to Discard Framing Bit ...................................................................... 1226
...........................................................................................
......................................................................................................
Transmit Operation ......................................................................................................
Maximum Frame Frequency for Transmit and Receive ............................................................
Unexpected Frame Synchronization With (R/X)FIG = 0 ...........................................................
Unexpected Frame Synchronization With (R/X)FIG = 1 ...........................................................
Maximum Frame Frequency Operation With 8-Bit Data ...........................................................
Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ................................................
Serial Port Receive Overrun ...........................................................................................
Serial Port Receive Overrun Avoided ................................................................................
Decision Tree Response to Receive Frame Synchronization Pulse .............................................
Unexpected Receive Frame Synchronization Pulse ................................................................
Transmit With Data Overwrite .........................................................................................
Transmit Empty ..........................................................................................................
Transmit Empty Avoided ...............................................................................................
Decision Tree Response to Transmit Frame Synchronization Pulse.............................................
Unexpected Transmit Frame Synchronization Pulse ...............................................................
McBSP Buffer FIFO (BFIFO) Block Diagram ........................................................................
Companding Flow .......................................................................................................
Companding Data Formats ............................................................................................
Transmit Data Companding Format in DXR .........................................................................
Companding of Internal Data ..........................................................................................
DX Timing for Multichannel Operation................................................................................
Alternating Between the Channels of Partition A and the Channels of Partition B .............................
Reassigning Channel Blocks Throughout a McBSP Data Transfer ..............................................
McBSP Data Transfer in the 8-Partition Mode ......................................................................
Activity on McBSP Pins for the Possible Values of XMCM ........................................................
Data Receive Register (DRR) .........................................................................................
Data Transmit Register (DXR) .........................................................................................
Serial Port Control Register (SPCR) ..................................................................................
Receive Control Register (RCR) ......................................................................................
Transmit Control Register (XCR) ......................................................................................
Sample Rate Generator Register (SRGR) ...........................................................................
Multichannel Control Registers (MCR) ...............................................................................
Enhanced Receive Channel Enable Register n (RCEREn) .......................................................
Enhanced Transmit Channel Enable Register n (XCEREn) .......................................................
Pin Control Register (PCR) ............................................................................................
BFIFO Revision Identification Register (BFIFOREV) ...............................................................
Write FIFO Control Register (WFIFOCTL) ...........................................................................
Write FIFO Status Register (WFIFOSTS) ............................................................................
26-15. McBSP Standard Operation
1227
26-16. Receive Operation
1228
26-17.
1228
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
26-25.
26-26.
26-27.
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
26-34.
26-35.
26-36.
26-37.
26-38.
26-39.
26-40.
26-41.
26-42.
26-43.
26-44.
26-45.
26-46.
26-47.
26-48.
26-49.
26-50.
26-51.
26-52.
26-53.
26-54.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1229
1230
1231
1231
1232
1233
1233
1234
1235
1235
1236
1236
1238
1238
1239
1241
1241
1241
1242
1244
1246
1246
1247
1250
1260
1260
1261
1263
1265
1267
1268
1272
1274
1276
1278
1279
1280
45
www.ti.com
26-55. Read FIFO Control Register (RFIFOCTL) ........................................................................... 1281
26-56. Read FIFO Status Register (RFIFOSTS) ............................................................................ 1282
27-1.
MMC/SD Card Controller Block Diagram ............................................................................ 1284
27-2.
MMC/SD Controller Interface Diagram ............................................................................... 1285
27-3.
MMC Configuration and SD Configuration Diagram ................................................................ 1286
27-4.
MMC/SD Controller Clocking Diagram ............................................................................... 1287
27-5.
MMC/SD Mode Write Sequence Timing Diagram .................................................................. 1288
27-6.
MMC/SD Mode Read Sequence Timing Diagram .................................................................. 1289
27-7.
FIFO Operation Diagram ............................................................................................... 1290
27-8.
Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA...................................... 1291
27-9.
FIFO Operation During Card Read Diagram ........................................................................ 1293
1295
27-11. MMC Card Identification Procedure
1302
27-12.
1303
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
27-28.
27-29.
27-30.
27-31.
27-32.
27-33.
27-34.
27-35.
27-36.
27-37.
27-38.
27-39.
27-40.
27-41.
27-42.
28-1.
28-2.
28-3.
28-4.
28-5.
46
........................................................................
..................................................................................
SD Card Identification Procedure .....................................................................................
MMC/SD Mode Single-Block Write Operation .......................................................................
MMC/SD Mode Single-Block Read Operation.......................................................................
MMC/SD Multiple-Block Write Operation ............................................................................
MMC/SD Mode Multiple-Block Read Operation .....................................................................
MMC Control Register (MMCCTL) ....................................................................................
MMC Memory Clock Control Register (MMCCLK)..................................................................
MMC Status Register 0 (MMCST0) ...................................................................................
MMC Status Register 1 (MMCST1) ...................................................................................
MMC Interrupt Mask Register (MMCIM) .............................................................................
MMC Response Time-Out Register (MMCTOR) ....................................................................
MMC Data Read Time-Out Register (MMCTOD) ...................................................................
MMC Block Length Register (MMCBLEN) ...........................................................................
MMC Number of Blocks Register (MMCNBLK) .....................................................................
MMC Number of Blocks Counter Register (MMCNBLC) ...........................................................
MMC Data Receive Register (MMCDRR)............................................................................
MMC Data Transmit Register (MMCDXR) ...........................................................................
MMC Command Register (MMCCMD) ...............................................................................
Command Format .......................................................................................................
MMC Argument Register (MMCARGHL) .............................................................................
MMC Response Register 0 and 1 (MMCRSP01) ...................................................................
MMC Response Register 2 and 3 (MMCRSP23) ...................................................................
MMC Response Register 4 and 5 (MMCRSP45) ...................................................................
MMC Response Register 6 and 7 (MMCRSP67) ...................................................................
MMC Data Response Register (MMCDRSP) .......................................................................
MMC Command Index Register (MMCCIDX) .......................................................................
SDIO Control Register (SDIOCTL)....................................................................................
SDIO Status Register 0 (SDIOST0) ..................................................................................
SDIO Interrupt Enable Register (SDIOIEN)..........................................................................
SDIO Interrupt Status Register (SDIOIST) ...........................................................................
MMC FIFO Control Register (MMCFIFOCTL) .......................................................................
Real-Time Clock Block Diagram ......................................................................................
32-kHz Oscillator Counter Compensation............................................................................
Kick State Machine......................................................................................................
Second Register (SECOND) ...........................................................................................
Minute Register (MINUTE) .............................................................................................
27-10. FIFO Operation During Card Write Diagram
List of Figures
1305
1307
1309
1311
1314
1315
1316
1318
1319
1321
1322
1323
1324
1324
1325
1325
1326
1327
1328
1329
1329
1329
1329
1331
1331
1332
1333
1334
1334
1335
1337
1341
1342
1345
1345
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
28-6.
Hour Register (HOUR).................................................................................................. 1346
28-7.
Days Register (DAY) .................................................................................................... 1347
28-8.
Month Register (MONTH) .............................................................................................. 1347
28-9.
Year Register (YEAR) .................................................................................................. 1348
28-10. Day of the Week Register (DOTW) ................................................................................... 1348
.........................................................................
Alarm Minute Register (ALARMMINUTE) ............................................................................
Alarm Hour Register (ALARMHOUR) ................................................................................
Alarm Day Register (ALARMDAY) ....................................................................................
Alarm Month Register (ALARMMONTH) .............................................................................
Alarm Year Register (ALARMYEAR) .................................................................................
Control Register (CTRL)................................................................................................
Status Register (STATUS) .............................................................................................
Interrupt Register (INTERRUPT) ......................................................................................
Compensation (LSB) Register (COMPLSB) .........................................................................
Compensation (MSB) Register (COMPMSB)........................................................................
Oscillator Register (OSC) ..............................................................................................
Scratch Registers (SCRATCHn) ......................................................................................
Kick Registers (KICKnR) ...............................................................................................
HBA Capabilities Register (CAP) .....................................................................................
Global HBA Control Register (GHC) ..................................................................................
Interrupt Status Register (IS) ..........................................................................................
Ports Implemented Register (PI) ......................................................................................
AHCI Version Register (VS) ...........................................................................................
Command Completion Coalescing Control Register (CCC_CTL) ................................................
Command Completion Coalescing Ports Register (CCC_PORTS)...............................................
BIST Active FIS Register (BISTAFR) .................................................................................
BIST Control Register (BISTCR) ......................................................................................
BIST FIS Count Register (BISTFCTR) ...............................................................................
BIST Status Register (BISTSR) .......................................................................................
BIST DWORD Error Count Register (BISTDECR)..................................................................
BIST DWORD Error Count Register (TIMER1MS) .................................................................
Global Parameter 1 Register (GPARAM1R) .........................................................................
Global Parameter 2 Register (GPARAM2R) .........................................................................
Port Parameter Register (PPARAMR) ................................................................................
Test Register (TESTR) .................................................................................................
Version Register (VERSIONR) ........................................................................................
ID Register (IDR) ........................................................................................................
Port Command List Base Address Register (P0CLB) ..............................................................
Port FIS Base Address Register (P0FB) .............................................................................
Port Interrupt Status Register (P0IS) .................................................................................
Port Interrupt Enable Register (P0IE) ................................................................................
Port Command Register (P0CMD) ....................................................................................
Port Task File Data Register (P0TFD) ...............................................................................
Port Signature Register (P0SIG) ......................................................................................
Port Serial ATA Status Register (P0SSTS) ..........................................................................
Port Serial ATA Control Register (P0SCTL) .........................................................................
Port Serial ATA Error Register (P0SERR) ...........................................................................
Port Serial ATA Active Register (P0SACT) ..........................................................................
28-11. Alarm Second Register (ALARMSECOND)
1349
28-12.
1349
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
29-26.
29-27.
29-28.
29-29.
29-30.
SPRUH77C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1350
1351
1352
1352
1353
1354
1355
1356
1357
1358
1359
1359
1392
1393
1394
1395
1395
1396
1397
1398
1399
1401
1401
1402
1402
1403
1404
1405
1406
1407
1407
1408
1408
1409
1411
1412
1415
1415
1416
1417
1418
1420
47
www.ti.com
29-31. Port Serial ATA Active (SActive) Register (P0SACT) .............................................................. 1420
29-32. Port Serial ATA Notification Register (POSNTF).................................................................... 1421
29-33. Port DMA Control Register (P0DMACR) ............................................................................. 1422
29-34. Port PHY Control Register (P0PHYCR) .............................................................................. 1424
29-35. Port PHY Status Register (P0PHYSR) ............................................................................... 1428
30-1.
SPI Block Diagram ...................................................................................................... 1431
30-2.
SPI 3-Pin Option......................................................................................................... 1437
30-3.
SPI 4-Pin Option with SPIx_SCS[n]
1439
30-4.
SPI 4-Pin Option with SPIx_ENA
1441
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
30-34.
30-35.
30-36.
30-37.
30-38.
30-39.
30-40.
31-1.
31-2.
31-3.
31-4.
48
..................................................................................
.....................................................................................
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ...............................................................
Format for Transmitting 12-Bit Word..................................................................................
Format for 10-Bit Received Word .....................................................................................
Clock Mode with POLARITY = 0 and PHASE = 0 ..................................................................
Clock Mode with POLARITY = 0 and PHASE = 1 ..................................................................
Clock Mode with POLARITY = 1 and PHASE = 0 ..................................................................
Clock Mode with POLARITY = 1 and PHASE = 1 ..................................................................
Five Bits per Character (5-Pin Option) ...............................................................................
SPI 3-Pin Master Mode with WDELAY ...............................................................................
SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY .............................
SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY ....................................
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY .......................................
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY ....................................................
SPI Global Control Register 0 (SPIGCR0) ...........................................................................
SPI Global Control Register 1 (SPIGCR1) ...........................................................................
SPI Interrupt Register (SPIINT0) ......................................................................................
SPI Interrupt Level Register (SPILVL) ................................................................................
SPI Flag Register (SPIFLG) ...........................................................................................
SPI Pin Control Register 0 (SPIPC0) .................................................................................
SPI Pin Control Register 1 (SPIPC1) .................................................................................
SPI Pin Control Register 2 (SPIPC2) .................................................................................
SPI Pin Control Register 3 (SPIPC3) .................................................................................
SPI Pin Control Register 4 (SPIPC4) .................................................................................
SPI Pin Control Register 5 (SPIPC5) .................................................................................
SPI Data Register 0 (SPIDAT0) .......................................................................................
SPI Data Register 1 (SPIDAT1) .......................................................................................
SPI Buffer Register (SPIBUF) .........................................................................................
SPI Emulation Register (SPIEMU) ....................................................................................
SPI Delay Register (SPIDELAY) ......................................................................................
Example: tC2TDELAY = 8 SPI Module Clock Cycles ....................................................................
Example: tT2CDELAY = 4 SPI Module Clock Cycles ....................................................................
Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout ...........................................................
Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout...........................................................
SPI Default Chip Select Register (SPIDEF) .........................................................................
SPI Data Format Register (SPIFMTn) ................................................................................
SPI Interrupt Vector Register 1 (INTVEC1) ..........................................................................
Timer Block Diagram ...................................................................................................
Timer Clock Source Block Diagram...................................................................................
64-Bit Timer Mode Block Diagram ....................................................................................
Dual 32-Bit Timers Chained Mode Block Diagram .................................................................
List of Figures
1443
1444
1444
1445
1446
1446
1446
1447
1452
1453
1454
1456
1457
1458
1459
1461
1463
1464
1466
1467
1468
1469
1470
1471
1472
1473
1474
1476
1477
1478
1479
1479
1479
1480
1481
1483
1486
1487
1488
1491
SPRUH77C – April 2013 – Revised September 2016
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31-5.
Dual 32-Bit Timers Chained Mode Example ......................................................................... 1491
31-6.
Dual 32-Bit Timers Unchained Mode Block Diagram ............................................................... 1493
31-7.
Dual 32-Bit Timers Unchained Mode Example ...................................................................... 1494
31-8.
32-Bit Timer Counter Overflow Example ............................................................................. 1497
31-9.
Watchdog Timer Mode Block Diagram ............................................................................... 1499
31-10. Watchdog Timer Operation State Diagram .......................................................................... 1499
31-11. Timer Operation in Pulse Mode (CPn = 0) ........................................................................... 1501
31-12. Timer Operation in Clock Mode (CPn = 1) ........................................................................... 1501
31-13. Revision ID Register (REVID) ......................................................................................... 1505
31-14. Emulation Management Register (EMUMGT) ....................................................................... 1505
31-15. GPIO Interrupt Control and Enable Register (GPINTGPEN) ...................................................... 1506
31-16. GPIO Data and Direction Register (GPDATGPDIR)
...............................................................
1507
31-17. Timer Counter Register 12 (TIM12)................................................................................... 1508
31-18. Timer Counter Register 34 (TIM34)................................................................................... 1508
31-19. Timer Period Register 12 (PRD12) ................................................................................... 1509
31-20. Timer Period Register 34 (PRD34) ................................................................................... 1509
31-21. Timer Control Register (TCR)
.........................................................................................
1510
31-22. Timer Global Control Register (TGCR) ............................................................................... 1512
31-23. Watchdog Timer Control Register (WDTCR) ........................................................................ 1513
31-24. Timer Reload Register 12 (REL12) ................................................................................... 1514
31-25. Timer Reload Register 34 (REL34) ................................................................................... 1514
31-26. Timer Capture Register 12 (CAP12) .................................................................................. 1515
31-27. Timer Capture Register 34 (CAP34) .................................................................................. 1515
31-28. Timer Interrupt Control and Status Register (INTCTLSTAT) ...................................................... 1516
31-29. Timer Compare Register (CMPn) ..................................................................................... 1517
32-1.
UART Block Diagram ................................................................................................... 1520
32-2.
UART Clock Generation Diagram ..................................................................................... 1521
32-3.
Relationships Between Data Bit, BCLK, and UART Input Clock .................................................. 1522
32-4.
UART Protocol Formats ................................................................................................ 1524
32-5.
UART Interface Using Autoflow Diagram ............................................................................ 1527
32-6.
Autoflow Functional Timing Waveforms for UARTn_RTS
32-7.
32-8.
32-9.
32-10.
32-11.
32-12.
32-13.
32-14.
32-15.
32-16.
32-17.
32-18.
32-19.
32-20.
32-21.
32-22.
32-23.
32-24.
........................................................
Autoflow Functional Timing Waveforms for UARTn_CTS ........................................................
UART Interrupt Request Enable Paths ...............................................................................
Receiver Buffer Register (RBR) .......................................................................................
Transmitter Holding Register (THR) ..................................................................................
Interrupt Enable Register (IER)........................................................................................
Interrupt Identification Register (IIR) ..................................................................................
FIFO Control Register (FCR) ..........................................................................................
Line Control Register (LCR) ...........................................................................................
Modem Control Register (MCR) .......................................................................................
Line Status Register (LSR).............................................................................................
Modem Status Register (MSR) ........................................................................................
Scratch Pad Register (SCR) ...........................................................................................
Divisor LSB Latch (DLL) ................................................................................................
Divisor MSB Latch (DLH) ..............................................................................................
Revision Identification Register 1 (REVID1) .........................................................................
Revision Identification Register 2 (REVID2) .........................................................................
Power and Emulation Management Register (PWREMU_MGMT) ...............................................
Mode Definition Register (MDR) ......................................................................................
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1528
1528
1530
1533
1534
1535
1536
1538
1539
1541
1542
1545
1546
1547
1547
1548
1548
1549
1550
49
www.ti.com
33-1.
uPP Functional Block Diagram ........................................................................................ 1553
33-2.
Data Flow for Single-Channel Receive Mode ....................................................................... 1553
33-3.
Data Flow for Single-Channel Transmit Mode
33-4.
Data Flow for Digital Loopback (DLB) Mode (Duplex Mode 0).................................................... 1554
33-5.
Data Flow for Single-Channel Transmit with Data Interleave ..................................................... 1554
33-6.
Clock Generation for a Channel Configured in Transmit Mode ................................................... 1555
33-7.
Clock Generation for a Channel Configured in Receive Mode .................................................... 1555
33-8.
Structure of DMA Window and Lines in Memory.................................................................... 1558
33-9.
Signal Timing for uPP Channel in Receive Mode with Single Data Rate ........................................ 1561
......................................................................
1553
33-10. Signal Timing for uPP Channel in Transmit Mode with Single Data Rate ....................................... 1562
33-11. Signal Timing for uPP Channel in Receive Mode with Double Data Rate ....................................... 1562
33-12. Signal Timing for uPP Channel in Transmit Mode with Double Data Rate ...................................... 1562
33-13. Signal Timing for uPP Channel in Receive Mode with Double Data Rate and Data Interleave Enabled
(via UPCTL.DDRDEMUX).............................................................................................. 1563
33-14. Signal Timing for uPP Channel in Transmit Mode with Double Data Rate and Data Interleave Enabled
(via UPCTL.DDRDEMUX).............................................................................................. 1563
33-15. Signal Timing for uPP Channel in Transmit Mode with Single Data Rate and Data Interleave Enabled
(via UPCTL.SDRTXIL) .................................................................................................. 1563
33-16. uPP Peripheral Identification Register (UPPID) ..................................................................... 1572
33-17. uPP Peripheral Control Register (UPPCR) .......................................................................... 1573
33-18. uPP Digital Loopback Register (UPDLB)
............................................................................
1574
33-19. uPP Channel Control Register (UPCTL) ............................................................................. 1575
33-20. uPP Interface Configuration Register (UPICR) ...................................................................... 1577
33-21. uPP Interface Idle Value Register (UPIVR) .......................................................................... 1579
33-22. uPP Threshold Configuration Register (UPTCR) ................................................................... 1580
33-23. uPP Interrupt Raw Status Register (UPISR)
........................................................................
1581
33-24. uPP Interrupt Enabled Status Register (UPIER) .................................................................... 1583
33-25. uPP Interrupt Enable Set Register (UPIES) ......................................................................... 1585
33-26. uPP Interrupt Enable Clear Register (UPIEC) ....................................................................... 1587
33-27. uPP End of Interrupt Register (UPEOI) .............................................................................. 1589
33-28. uPP DMA Channel I Descriptor 0 Register (UPID0) ................................................................ 1589
33-29. uPP DMA Channel I Descriptor 1 Register (UPID1) ................................................................ 1590
33-30. uPP DMA Channel I Descriptor 2 Register (UPID2) ................................................................ 1590
1591
33-32. uPP DMA Channel I Status 1 Register (UPIS1)
1591
33-33.
33-34.
33-35.
33-36.
33-37.
33-38.
33-39.
34-1.
34-2.
34-3.
34-4.
34-5.
34-6.
34-7.
34-8.
50
....................................................................
....................................................................
uPP DMA Channel I Status 2 Register (UPIS2) ....................................................................
uPP DMA Channel Q Descriptor 0 Register (UPQD0) .............................................................
uPP DMA Channel Q Descriptor 1 Register (UPQD1) .............................................................
uPP DMA Channel Q Descriptor 2 Register (UPID2) ..............................................................
uPP DMA Channel Q Status 0 Register (UPQS0) ..................................................................
uPP DMA Channel Q Status 1 Register (UPQS1) ..................................................................
uPP DMA Channel Q Status 2 Register (UPQS2) ..................................................................
Relationships Between Virtual Address Physical Address.........................................................
OHCI Revision Number Register (HCREVISION) ..................................................................
HC Operating Mode Register (HCCONTROL) ......................................................................
HC Command and Status Register (HCCOMMANDSTATUS) ....................................................
HC Interrupt and Status Register (HCINTERRUPTSTATUS) .....................................................
HC Interrupt Enable Register (HCINTERRUPTENABLE) .........................................................
HC Interrupt Disable Register (HCINTERRUPTDISABLE) ........................................................
HC HCAA Address Register (HCHCCA) .............................................................................
33-31. uPP DMA Channel I Status 0 Register (UPIS0)
List of Figures
1592
1593
1593
1594
1595
1595
1596
1602
1604
1604
1606
1607
1608
1609
1610
SPRUH77C – April 2013 – Revised September 2016
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34-9.
HC Current Periodic Register (HCPERIODCURRENTED) ........................................................ 1610
34-10. HC Head Control Register (HCCONTROLHEADED) .............................................................. 1611
34-11. HC Current Control Register (HCCONTROLCURRENTED) ...................................................... 1611
34-12. HC Head Bulk Register (HCBULKHEADED) ........................................................................ 1612
34-13. HC Current Bulk Register (HCBULKCURRENTED) ................................................................ 1612
34-14. HC Head Done Register (HCDONEHEAD) .......................................................................... 1613
34-15. HC Frame Interval Register (HCFMINTERVAL) .................................................................... 1613
34-16. HC Frame Remaining Register (HCFMREMAINING) .............................................................. 1614
34-17. HC Frame Number Register (HCFMNUMBER) ..................................................................... 1614
34-18. HC Periodic Start Register (HCPERIODICSTART)................................................................. 1615
........................................................
HC Root Hub A Register (HCRHDESCRIPTORA) .................................................................
HC Root Hub B Register (HCRHDESCRIPTORB) .................................................................
HC Root Hub Status Register (HCRHSTATUS) ....................................................................
HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .................................................
HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .................................................
Functional Block Diagram ..............................................................................................
USB Clocking Diagram .................................................................................................
Interrupt Service Routine Flow Chart .................................................................................
CPU Actions at Transfer Phases ......................................................................................
Sequence of Transfer ...................................................................................................
Service Endpoint 0 Flow Chart ........................................................................................
IDLE Mode Flow Chart .................................................................................................
TX Mode Flow Chart ....................................................................................................
RX Mode Flow Chart....................................................................................................
Setup Phase of a Control Transaction Flow Chart..................................................................
IN Data Phase Flow Chart .............................................................................................
OUT Data Phase Flow Chart ..........................................................................................
Completion of SETUP or OUT Data Phase Flow Chart ............................................................
Completion of IN Data Phase Flow Chart ............................................................................
USB Controller Block Diagram ........................................................................................
Host Packet Descriptor Layout ........................................................................................
Host Buffer Descriptor Layout .........................................................................................
Teardown Descriptor Layout ...........................................................................................
Relationship Between Memory Regions and Linking RAM ........................................................
High-Level Transmit and Receive Data Transfer Example ........................................................
Transmit Descriptors and Queue Status Configuration ............................................................
Transmit USB Data Flow Example (Initialization) ...................................................................
Transmit USB Data Flow Example (Completion) ...................................................................
Receive Descriptors and Queue Status Configuration .............................................................
Receive USB Data Flow Example (Initialization) ....................................................................
Receive USB Data Flow Example (Completion) ....................................................................
Revision Identification Register (REVID) .............................................................................
Control Register (CTRLR) ..............................................................................................
Status Register (STATR) ...............................................................................................
Emulation Register (EMUR) ...........................................................................................
Mode Register (MODE) ................................................................................................
Auto Request Register (AUTOREQ)..................................................................................
SRP Fix Time Register (SRPFIXTIME) ..............................................................................
34-19. HC Low-Speed Threshold Register (HCLSTHRESHOLD)
1615
34-20.
1616
34-21.
34-22.
34-23.
34-24.
35-1.
35-2.
35-3.
35-4.
35-5.
35-6.
35-7.
35-8.
35-9.
35-10.
35-11.
35-12.
35-13.
35-14.
35-15.
35-16.
35-17.
35-18.
35-19.
35-20.
35-21.
35-22.
35-23.
35-24.
35-25.
35-26.
35-27.
35-28.
35-29.
35-30.
35-31.
35-32.
35-33.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
1617
1618
1619
1621
1624
1625
1630
1635
1635
1637
1638
1639
1640
1650
1652
1654
1656
1658
1665
1668
1671
1673
1676
1682
1683
1684
1685
1686
1686
1687
1711
1711
1712
1712
1713
1715
1716
51
www.ti.com
35-34. Teardown Register (TEARDOWN).................................................................................... 1716
35-35. USB Interrupt Source Register (INTSRCR).......................................................................... 1717
35-36. USB Interrupt Source Set Register (INTSETR) ..................................................................... 1718
35-37. USB Interrupt Source Clear Register (INTCLRR) ................................................................... 1719
35-38. USB Interrupt Mask Register (INTMSKR)............................................................................ 1720
1721
35-40.
1722
35-41.
35-42.
35-43.
35-44.
35-45.
35-46.
35-47.
35-48.
35-49.
35-50.
35-51.
35-52.
35-53.
35-54.
35-55.
35-56.
35-57.
35-58.
35-59.
35-60.
35-61.
35-62.
35-63.
35-64.
35-65.
35-66.
35-67.
35-68.
35-69.
35-70.
35-71.
35-72.
35-73.
35-74.
35-75.
35-76.
35-77.
35-78.
35-79.
35-80.
35-81.
35-82.
52
.................................................................
USB Interrupt Mask Clear Register (INTMSKCLRR) ...............................................................
USB Interrupt Source Masked Register (INTMASKEDR) ..........................................................
USB End of Interrupt Register (EOIR) ................................................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1)..............................................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2)..............................................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3)..............................................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4)..............................................................
Function Address Register (FADDR) .................................................................................
Power Management Register (POWER) .............................................................................
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ...........................................
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ........................................................
Interrupt Enable Register for INTRTX (INTRTXE) ..................................................................
Interrupt Enable Register for INTRRX (INTRRXE) .................................................................
Interrupt Register for Common USB Interrupts (INTRUSB) .......................................................
Interrupt Enable Register for INTRUSB (INTRUSBE) ..............................................................
Frame Number Register (FRAME) ....................................................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX) .............................
Register to Enable the USB 2.0 Test Modes (TESTMODE) ......................................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ......................................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ......................................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...........................................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .....................................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...........................................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP).......................................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ......................................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...........................................
Count 0 Register (COUNT0) ...........................................................................................
Receive Count Register (RXCOUNT) ................................................................................
Type Register (Host mode only) (HOST_TYPE0) ..................................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) .....................................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ......................................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ............................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .....................................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL).............................................
Configuration Data Register (CONFIGDATA) .......................................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .....................................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) .....................................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .....................................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) .....................................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) .....................................................
Device Control Register (DEVCTL) ...................................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ) ..........................................................................
Receive Endpoint FIFO Size (RXFIFOSZ) ...........................................................................
35-39. USB Interrupt Mask Set Register (INTMSKSETR)
List of Figures
1723
1724
1724
1725
1725
1726
1726
1727
1728
1729
1730
1730
1731
1732
1732
1733
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1742
1743
1743
1744
1744
1745
1746
1747
1748
1748
1749
1749
1750
1750
1751
1751
SPRUH77C – April 2013 – Revised September 2016
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www.ti.com
35-83. Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................. 1752
35-84. Receive Endpoint FIFO Address (RXFIFOADDR) .................................................................. 1752
35-85. Hardware Version Register (HWVERS) .............................................................................. 1753
35-86. Transmit Function Address (TXFUNCADDR) ....................................................................... 1754
35-87. Transmit Hub Address (TXHUBADDR)
..............................................................................
1754
35-88. Transmit Hub Port (TXHUBPORT).................................................................................... 1754
35-89. Receive Function Address (RXFUNCADDR) ........................................................................ 1755
35-90. Receive Hub Address (RXHUBADDR) ............................................................................... 1755
35-91. Receive Hub Port (RXHUBPORT) .................................................................................... 1755
35-92. CDMA Revision Identification Register (DMAREVID) .............................................................. 1756
...........................................
35-94. CDMA Emulation Control Register (DMAEMU) .....................................................................
35-95. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) ........................................
35-96. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) ........................................
35-97. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) ....................................
35-98. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) ....................................
35-99. CDMA Scheduler Control Register (DMA_SCHED_CTRL) .......................................................
35-100. CDMA Scheduler Table Word n Registers (WORD[n]) ...........................................................
35-101. Queue Manager Revision Identification Register (QMGRREVID) ...............................................
35-102. Queue Manager Queue Diversion Register (DIVERSION).......................................................
35-103. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) .............................
35-104. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) .............................
35-105. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) .............................
35-106. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) .............................
35-107. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) .............................
35-108. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .........................................
35-109. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) .............................
35-110. Queue Manager Queue Pending Register 0 (PEND0) ...........................................................
35-111. Queue Manager Queue Pending Register 1 (PEND1) ...........................................................
35-112. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) ............................
35-113. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) ....................................
35-114. Queue Manager Queue N Control Register D (CTRLD[N]) ......................................................
35-115. Queue Manager Queue N Status Register A (QSTATA[N]) .....................................................
35-116. Queue Manager Queue N Status Register B (QSTATB[N]) .....................................................
35-117. Queue Manager Queue N Status Register C (QSTATC[N]) .....................................................
36-1. Input and Output Channels of VPIF ..................................................................................
36-2. Video Port Interface (VPIF) Block Diagram ..........................................................................
36-3. VPIF Architecture Block Diagram .....................................................................................
36-4. Interlaced Video .........................................................................................................
36-5. Progressive Video .......................................................................................................
36-6. Memory Storage Modes for Interlaced Video........................................................................
36-7. Functional Image of Raw Data Capturing Mode ....................................................................
36-8. Raw Capture Progressive Mode ......................................................................................
36-9. Raw Capture Interlaced Mode .........................................................................................
36-10. Stuffing Manner in Storage Memory ..................................................................................
36-11. VBI Result Data Transmit Image for Interlaced Image .............................................................
36-12. Module Performance with Emulation Suspend Signal .............................................................
36-13. Emulation Suspend Function on Channels 2 and 3 (Transmit) ...................................................
36-14. Method for Turning off Module Channel..............................................................................
35-93. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)
SPRUH77C – April 2013 – Revised September 2016
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List of Figures
1756
1757
1757
1758
1759
1760
1761
1761
1763
1763
1764
1765
1766
1767
1767
1768
1768
1769
1769
1770
1771
1772
1773
1773
1774
1776
1777
1778
1781
1782
1783
1786
1787
1788
1788
1789
1794
1795
1796
53
www.ti.com
36-15. Clock Control on Video Input and Output with SDTV Encoding .................................................. 1797
36-16. Clock Control on Video Input and Output with HDTV Encoding .................................................. 1799
36-17. Clock Control on Video Input and Output with HDTV Encoding .................................................. 1800
1804
36-19.
1804
36-20.
36-21.
36-22.
36-23.
36-24.
36-25.
36-26.
36-27.
36-28.
36-29.
36-30.
36-31.
36-32.
36-33.
36-34.
36-35.
36-36.
36-37.
36-38.
36-39.
36-40.
36-41.
36-42.
36-43.
36-44.
36-45.
36-46.
36-47.
36-48.
36-49.
36-50.
36-51.
36-52.
36-53.
36-54.
36-55.
36-56.
36-57.
54
..................................................................................
Channel 0 Control Register (C0CTRL) ...............................................................................
Channel 1 Control Register (C1CTRL) ...............................................................................
Channel 2 Control Register (C2CTRL) ...............................................................................
Channel 3 Control Register (C3CTRL) ...............................................................................
Interrupt Enable Register (INTEN) ....................................................................................
Interrupt Enable Set Register (INTSET) ..............................................................................
Interrupt Enable Clear Register (INTCLR) ...........................................................................
Interrupt Status Register (INTSTAT)..................................................................................
Interrupt Status Clear Register (INTSTATCLR) .....................................................................
Emulation Suspend Control Register (EMUCTRL) .................................................................
DMA Size Control Register (REQSIZE) ..............................................................................
Channel n Top Field Luminance Address Register (CnTLUMA)..................................................
Channel n Bottom Field Luminance Address Register (CnBLUMA) .............................................
Channel n Top Field Chrominance Address Register (CnTCHROMA) ..........................................
Channel n Bottom Field Chrominance Address Register (CnBCHROMA) ......................................
Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) .......................................
Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) ...................................
Channel n Top Field Vertical Ancillary Address Register (CnTVANC) ...........................................
Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register (CnBVANC) ..................
Channel n Image Address Offset Register (CnIMGOFFSET) .....................................................
Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET)...................................
Channel n Horizontal Size Configuration Register (CnHCFG) ....................................................
Channel n Vertical Size Configuration 0 Register (CnVCFG0) ...................................................
Channel n Vertical Data Size Configuration 1 Register (CnVCFG1) .............................................
Channel n Vertical Size Configuration 2 Register (CnVCFG2) ...................................................
Channel n Vertical Image Size Register (CnVSIZE)................................................................
Channel n Horizontal Size Configuration Register (CnHCFG) ....................................................
Channel n Vertical Size Configuration 0 Register (CnVCFG0) ...................................................
Channel n Vertical Size Configuration 1 Register (CnVCFG1) ...................................................
Channel n Vertical Size Configuration 2 Register (CnVCFG2) ...................................................
Channel n Vertical Image Size Register (CnVSIZE)................................................................
Channel n Top Field Horizontal Ancillary Position Register (CnTHANCPOS) ..................................
Channel n Top Field Horizontal Ancillary Size Register (CnTHANCSIZE) ......................................
Channel n Bottom Field Horizontal Ancillary Position Register (CnBHANCPOS) ..............................
Channel n Bottom Field Horizontal Ancillary Size Register (CnBHANCSIZE) ..................................
Channel n Top Field Vertical Ancillary Position Register (CnTVANCPOS) .....................................
Channel n Top Field Vertical Ancillary Size Register (CnTVANCSIZE) .........................................
Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) .................................
Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) .....................................
36-18. VPIF Revision ID Register (REVID)
List of Figures
1806
1807
1809
1811
1812
1813
1814
1815
1816
1816
1817
1817
1818
1818
1819
1819
1820
1820
1821
1821
1822
1823
1823
1824
1824
1825
1826
1826
1827
1827
1828
1829
1830
1831
1832
1833
1834
1835
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
List of Tables
2-1.
Exception Vector Table for ARM ......................................................................................... 88
2-2.
Different Address Types in ARM System ............................................................................... 90
3-1.
DSP Interrupt Map ......................................................................................................... 94
4-1.
OMAP-L138 Applications Processor System Interconnect Matrix.................................................. 101
6-1.
MPU Memory Regions ................................................................................................... 108
6-2.
MPU Default Configuration .............................................................................................. 108
6-3.
Device Master Settings
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
..................................................................................................
Request Type Access Controls .........................................................................................
MPU_BOOTCFG_ERR Interrupt Sources .............................................................................
Memory Protection Unit 1 (MPU1) Registers .........................................................................
Memory Protection Unit 2 (MPU2) Registers .........................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
Configuration Register (CONFIG) Field Descriptions ................................................................
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ...............................................
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................
Interrupt Enable Set Register (IENSET) Field Descriptions .........................................................
Interrupt Enable Clear Register (IENCLR) Field Descriptions ......................................................
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions ..................
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions.................
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions.................
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions ...
Fault Address Register (FLTADDRR) Field Descriptions ...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Fault Clear Register (FLTCLR) Field Descriptions ...................................................................
Device Clock Inputs ......................................................................................................
System Clock Domains ..................................................................................................
Example PLL Frequencies ..............................................................................................
USB Clock Multiplexing Options ........................................................................................
DDR2/mDDR Memory Controller MCLK Frequencies ...............................................................
EMIFA Frequencies ......................................................................................................
EMAC Reference Clock Frequencies ..................................................................................
uPP Transmit Clock Selection ..........................................................................................
Peripherals .................................................................................................................
System PLLC Output Clocks ............................................................................................
PLL Controller 0 (PLLC0) Registers ....................................................................................
PLL Controller 1 (PLLC1) Registers ....................................................................................
PLLC0 Revision Identification Register (REVID) Field Descriptions ...............................................
PLLC1 Revision Identification Register (REVID) Field Descriptions ...............................................
Reset Type Status Register (RSTYPE) Field Descriptions .........................................................
Reset Control Register (RSCTRL) Field Descriptions ...............................................................
PLLC0 Control Register (PLLCTL) Field Descriptions ...............................................................
PLLC1 Control Register (PLLCTL) Field Descriptions ...............................................................
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions .....................................................
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions .....................................................
PLL Multiplier Control Register (PLLM) Field Descriptions..........................................................
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
108
110
112
113
113
115
115
116
117
118
118
120
121
121
122
122
123
124
125
126
128
128
131
132
134
135
137
138
140
144
147
148
148
149
149
150
151
152
153
154
155
55
www.ti.com
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
56
................................................
PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................
PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions ............................................................
PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................
PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions ............................................................
PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................
PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions ............................................................
PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions ............................................................
PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ............................................................
PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ............................................................
PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ............................................................
PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions ................................................
PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions ................................................
PLL Post-Divider Control Register (POSTDIV) Field Descriptions .................................................
PLL Controller Command Register (PLLCMD) Field Descriptions .................................................
PLL Controller Status Register (PLLSTAT) Field Descriptions .....................................................
PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .................................
PLLC0 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ................................................
PLLC0 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC1 Clock Status Register (CKSTAT) Field Descriptions ........................................................
PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ....................................................
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions ....................................
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions ....................................
PSC0 Default Module Configuration ...................................................................................
PSC1 Default Module Configuration ...................................................................................
Module States .............................................................................................................
IcePick Emulation Commands ..........................................................................................
PSC Interrupt Events .....................................................................................................
Power and Sleep Controller 0 (PSC0) Registers .....................................................................
Power and Sleep Controller 1 (PSC1) Registers .....................................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions ........................................................
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions .........................................
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ............................................
Power Error Pending Register (PERRPR) Field Descriptions ......................................................
Power Error Clear Register (PERRCR) Field Descriptions .........................................................
Power Domain Transition Command Register (PTCMD) Field Descriptions .....................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions .........................................
Power Domain 0 Status Register (PDSTAT0) Field Descriptions ..................................................
Power Domain 1 Status Register (PDSTAT1) Field Descriptions ..................................................
Power Domain 0 Control Register (PDCTL0) Field Descriptions ...................................................
Power Domain 1 Control Register (PDCTL1) Field Descriptions ...................................................
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ...........................................
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ...........................................
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
List of Tables
155
156
156
157
157
158
158
159
159
160
160
161
161
162
162
163
164
165
166
167
168
168
169
170
171
172
173
173
176
176
179
181
181
184
184
185
185
186
187
188
188
189
190
191
192
193
194
195
196
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
9-22.
Module Status n Register (MDSTATn) Field Descriptions .......................................................... 197
9-23.
PSC0 Module Control n Register (MDCTLn) Field Descriptions ................................................... 198
9-24.
PSC1 Module Control n Register (MDCTLn) Field Descriptions ................................................... 199
10-1.
Power Management Features ........................................................................................... 202
11-1.
Master IDs ................................................................................................................. 219
11-2.
Default Master Priority
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
11-12.
11-13.
11-14.
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
11-26.
11-27.
11-28.
11-29.
11-30.
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
11-44.
11-45.
...................................................................................................
System Configuration Module 0 (SYSCFG0) Registers .............................................................
System Configuration Module 1 (SYSCFG1) Registers .............................................................
Revision Identification Register (REVID) Field Descriptions ........................................................
Device Identification Register 0 (DEVIDR0) Field Descriptions ....................................................
Boot Configuration Register (BOOTCFG) Field Descriptions .......................................................
Chip Revision Identification Register (CHIPREVIDR) Field Descriptions .........................................
Kick 0 Register (KICK0R) Field Descriptions .........................................................................
Kick 1 Register (KICK1R) Field Descriptions .........................................................................
Host 0 Configuration Register (HOST0CFG) Field Descriptions ...................................................
Host 1 Configuration Register (HOST1CFG) Field Descriptions ...................................................
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ...............................................
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................
Interrupt Enable Register (IENSET) Field Descriptions..............................................................
Interrupt Enable Clear Register (IENCLR) Field Descriptions ......................................................
End of Interrupt Register (EOI) Field Descriptions ...................................................................
Fault Address Register (FLTADDRR) Field Descriptions ...........................................................
Fault Status Register (FLTSTAT) Field Descriptions ................................................................
Master Priority 0 Register (MSTPRI0) Field Descriptions ...........................................................
Master Priority 1 Register (MSTPRI1) Field Descriptions ...........................................................
Master Priority 2 Register (MSTPRI2) Field Descriptions ...........................................................
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ................................................
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ................................................
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ................................................
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ................................................
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ................................................
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ................................................
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ................................................
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ................................................
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ................................................
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ................................................
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions .............................................
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions .............................................
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions .............................................
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions .............................................
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions .............................................
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions .............................................
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions .............................................
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions .............................................
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions .............................................
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions .............................................
Suspend Source Register (SUSPSRC) Field Descriptions .........................................................
Chip Signal Register (CHIPSIG) Field Descriptions..................................................................
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ...................................................
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
220
221
223
223
223
224
224
225
225
226
227
228
229
230
230
231
231
232
233
234
235
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
269
271
273
275
277
280
281
57
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11-46. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions .................................................... 282
11-47. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions .................................................... 284
11-48. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions .................................................... 286
11-49. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions .................................................... 288
11-50. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions .................................................... 289
11-51. VTP I/O Control Register (VTPIO_CTL) Field Descriptions ......................................................... 290
11-52. DDR Slew Register (DDR_SLEW) Field Descriptions ............................................................... 292
11-53. Deep Sleep Register (DEEPSLEEP) Field Descriptions ............................................................ 293
11-54. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions................................................ 294
11-55. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions ................................................. 294
11-56. Pullup/Pulldown Select Register (PUPD_SEL) Default Values ..................................................... 295
11-57. RXACTIVE Control Register (RXACTIVE) Field Descriptions ...................................................... 296
11-58. Power Down Control Register (PWRDN) Field Descriptions
.......................................................
296
12-1.
AINTC System Interrupt Assignments ................................................................................. 299
12-2.
ARM Interrupt Controller (AINTC) Registers .......................................................................... 305
12-3.
Revision Identification Register (REVID) Field Descriptions ........................................................ 306
12-4.
Control Register (CR) Field Descriptions .............................................................................. 307
12-5.
Global Enable Register (GER) Field Descriptions .................................................................... 308
12-6.
Global Nesting Level Register (GNLR) Field Descriptions .......................................................... 308
12-7.
System Interrupt Status Indexed Set Register (SISR) Field Descriptions ......................................... 309
12-8.
System Interrupt Status Indexed Clear Register (SICR) Field Descriptions ...................................... 309
12-9.
System Interrupt Enable Indexed Set Register (EISR) Field Descriptions ........................................ 310
12-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions ..................................... 310
311
12-12.
311
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
58
.........................................
Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions ......................................
Vector Base Register (VBR) Field Descriptions ......................................................................
Vector Size Register (VSR) Field Descriptions .......................................................................
Vector Null Register (VNR) Field Descriptions........................................................................
Global Prioritized Index Register (GPIR) Field Descriptions ........................................................
Global Prioritized Vector Register (GPVR) Field Descriptions ......................................................
System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions ........................................
System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions ........................................
System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions ........................................
System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions ........................................
System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions .................................
System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions .................................
System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions .................................
System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions .................................
System Interrupt Enable Set Register 1 (ESR1) Field Descriptions ...............................................
System Interrupt Enable Set Register 2 (ESR2) Field Descriptions ...............................................
System Interrupt Enable Set Register 3 (ESR3) Field Descriptions ...............................................
System Interrupt Enable Set Register 4 (ESR4) Field Descriptions ...............................................
System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions .............................................
System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions .............................................
System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions .............................................
System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions .............................................
Channel Map Registers (CMRn) Field Descriptions .................................................................
Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions ...........................................
Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions ...........................................
12-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions
List of Tables
312
312
313
313
314
314
315
315
316
316
317
317
318
318
319
319
320
320
321
321
322
322
323
323
SPRUH77C – April 2013 – Revised September 2016
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12-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions ............................................. 324
12-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions ............................................. 324
12-39. Host Interrupt Enable Register (HIER) Field Descriptions
..........................................................
325
12-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions ......................................... 326
12-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions ......................................... 326
14-1.
Constants Table........................................................................................................... 334
14-2.
Abbreviations for Instruction Descriptions ............................................................................. 336
14-3.
Load/Store Instructions
14-4.
Arithmetic Instructions .................................................................................................... 336
14-5.
Logical Instructions ....................................................................................................... 337
14-6.
Program Flow Control Instructions ..................................................................................... 338
14-7.
Format 1a: (All Arithmetic and Logical Functions – Register Op2)................................................. 339
14-8.
Format 1b: (All Arithmetic and Logical Functions – Immediate Op2) .............................................. 341
14-9.
Format 2
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
..................................................................................................
...................................................................................................................
Format 2a: (JMP,JAL – Register Op2) .................................................................................
Format 2b: (JMP, JAL – Immediate Op2) .............................................................................
Format 2c: (LDI)...........................................................................................................
Format 2d: (LMBD - Leftmost Bit Detect - Register Op2) ...........................................................
Format 2e: (LMBD - Immediate Op2) ..................................................................................
Format 2f: (SCAN - Register Op2) .....................................................................................
Format 2g: (SCAN - Immediate Op2) ..................................................................................
Format 2h: (HALT) ........................................................................................................
Format 2i: (SLP) ..........................................................................................................
Format 4a: (Quick Arithmetic Test and Branch – Register Op2) ...................................................
Format 4b: (Quick Arithmetic Test and Branch – Immediate Op2).................................................
Format 5a: (Quick Bit Test and Branch – Register Op2) ............................................................
Format 5b: (Quick Bit Test and Branch – Immediate Op2) .........................................................
Format 6a: (LBBO/SBBO - Register Offset)...........................................................................
Format 6b: (LBBO/SBBO - Immediate Offset) ........................................................................
Format 6c: (LBCO/SBCO - Register Offset) ..........................................................................
Format 6d: (LBCO/SBCO - Immediate Offset) ........................................................................
PRUSS System Events [0:31] Assignments ..........................................................................
ARM Interrupt Controller Mapping ......................................................................................
DSP Interrupt Controller Mapping ......................................................................................
Local Instruction Space Memory Map .................................................................................
Local Data Space Memory Map ........................................................................................
Subsystem Global Memory Map ........................................................................................
PRU Control/Status Register Memory Map ..........................................................................
CONTROL Register Field Descriptions ................................................................................
STATUS Register Field Descriptions ..................................................................................
WAKEUP Register Field Descriptions .................................................................................
CYCLECNT Register Field Descriptions...............................................................................
STALLCNT Register Field Descriptions ...............................................................................
CONTABBLKIDX0 Register Field Descriptions .......................................................................
CONTABPROPTR0 Register Field Descriptions .....................................................................
CONTABPROPTR1 Register Field Descriptions .....................................................................
INTGPR0 to INTGPR31 Register Field Descriptions ................................................................
INTCTER0 to INTCTER31 Register Field Descriptions .............................................................
Instruction RAM Memory Region .......................................................................................
SPRUH77C – April 2013 – Revised September 2016
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List of Tables
336
342
343
344
345
346
347
348
349
349
349
350
351
352
353
354
355
356
357
359
360
360
365
365
365
366
366
368
368
369
369
370
370
370
371
371
372
59
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14-45. PRUSS Interrupt Controller (INTC) Registers......................................................................... 372
14-46. REVID Register ........................................................................................................... 373
14-47. REVID Register Field Descriptions ..................................................................................... 373
14-48. CONTROL Register ...................................................................................................... 373
14-49. CONTROL Register Field Descriptions ................................................................................ 373
14-50. GLBLEN Register ......................................................................................................... 373
..................................................................................
..................................................................................................
GLBLNSTLVL Register Field Descriptions ............................................................................
STATIDXSET Register ...................................................................................................
STATIDXSET Register Field Descriptions ............................................................................
STATIDXCLR Register ...................................................................................................
STATIDXCLR Register Field Descriptions ............................................................................
ENIDXSET Register ......................................................................................................
ENIDXSET Register Field Descriptions ................................................................................
ENIDXCLR Register ......................................................................................................
ENIDXCLR Register Field Descriptions ...............................................................................
HSTINTENIDXSET Register ............................................................................................
HSTINTENIDXSET Register Field Descriptions ......................................................................
HSTINTENIDXCLR Register ............................................................................................
HSTINTENIDXCLR Register Field Descriptions ......................................................................
GLBLPRIIDX Register....................................................................................................
GLBLPRIIDX Register Field Descriptions .............................................................................
STATESETINT0 Register ................................................................................................
STATESETINT0 Register Field Descriptions .........................................................................
STATESETINT1 Register ................................................................................................
STATESETINT1 Register Field Descriptions .........................................................................
STATCLRINT0 Register .................................................................................................
STATCLRINT0 Register Field Descriptions ...........................................................................
STATCLRINT1 Register .................................................................................................
STATCLRINT1 Register Field Descriptions ...........................................................................
ENABLESET0 Register ..................................................................................................
ENABLESET0 Register Field Descriptions ............................................................................
ENABLESET1 Register ..................................................................................................
ENABLESET1 Register Field Descriptions ............................................................................
ENABLECLR0 Register ..................................................................................................
ENABLECLR0 Register Field Descriptions............................................................................
ENABLECLR1 Register ..................................................................................................
ENABLECLR1 Register Field Descriptions............................................................................
CHANMAP0 to CHANMAP15 Register ................................................................................
CHANMAP0 to CHANMAP15 Register Field Descriptions ..........................................................
HOSTMAP0 to HOSTMAP2 Register ..................................................................................
HOSTMAP0 to HOSTMAP2 Register Field Descriptions............................................................
HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register ...................................................................
HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register Field Descriptions.............................................
POLARITY0 Register.....................................................................................................
POLARITY0 Register Field Descriptions ..............................................................................
POLARITY1 Register.....................................................................................................
POLARITY1 Register Field Descriptions ..............................................................................
14-51. GLBLEN Register Field Descriptions
374
14-53.
374
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
14-81.
14-82.
14-83.
14-84.
14-85.
14-86.
14-87.
14-88.
14-89.
14-90.
14-91.
14-92.
14-93.
60
374
14-52. GLBLNSTLVL Register
List of Tables
374
374
375
375
375
375
375
375
376
376
376
376
376
376
377
377
377
377
377
377
378
378
378
378
378
378
379
379
379
379
379
379
380
380
380
380
380
381
381
381
SPRUH77C – April 2013 – Revised September 2016
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14-94. TYPE0 Register ........................................................................................................... 381
14-95. TYPE0 Register Field Descriptions..................................................................................... 381
14-96. TYPE1 Register ........................................................................................................... 381
14-97. TYPE1 Register Field Descriptions..................................................................................... 382
14-98. HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register
................................................................
382
14-99. HOSTINTNSTLVL0 to HOSTINTNSTLVL9 Register Field Descriptions .......................................... 382
14-100. HOSTINTEN Register
..................................................................................................
382
14-101. HOSTINTEN Register Field Descriptions ............................................................................ 382
15-1.
DDR2/mDDR SDRAM Commands ..................................................................................... 388
15-2.
Truth Table for DDR2/mDDR SDRAM Commands
15-3.
Addressable Memory Ranges ........................................................................................... 396
15-4.
Configuration Register Fields for Address Mapping.................................................................. 397
15-5.
Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM
15-6.
Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) ................................................... 400
15-7.
DDR2/mDDR Memory Controller FIFO Description .................................................................. 402
15-8.
Refresh Urgency Levels
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
.................................................................
.....................................
.................................................................................................
Configuration Bit Field for Partial Array Self-refresh .................................................................
Reset Sources.............................................................................................................
DDR2 SDRAM Configuration by MRS Command ....................................................................
DDR2 SDRAM Configuration by EMRS(1) Command ...............................................................
Mobile DDR SDRAM Configuration by MRS Command.............................................................
Mobile DDR SDRAM Configuration by EMRS(1) Command .......................................................
SDCR Configuration ......................................................................................................
DDR2 Memory Refresh Specification .................................................................................
SDRCR Configuration ....................................................................................................
SDTIMR1 Configuration..................................................................................................
SDTIMR2 Configuration..................................................................................................
DRPYC1R Configuration.................................................................................................
DDR2/mDDR Memory Controller Registers ...........................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................
SDRAM Configuration Register (SDCR) Field Descriptions ........................................................
SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
SDRAM Timing Register 1 (SDTIMR1) Field Descriptions ..........................................................
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ..........................................................
SDRAM Configuration Register 2 (SDCR2) Field Descriptions ....................................................
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ...............................................
Performance Counter 1 Register (PC1) Field Descriptions .........................................................
Performance Counter 2 Register (PC2) Field Descriptions .........................................................
Performance Counter Configuration Register (PCC) Field Descriptions ..........................................
Performance Counter Filter Configuration .............................................................................
Performance Counter Master Region Select Register (PCMRS) Field Descriptions ............................
Performance Counter Time Register (PCT) Field Description ......................................................
DDR PHY Reset Control Register (DRPYRCR) ......................................................................
Interrupt Raw Register (IRR) Field Descriptions ......................................................................
Interrupt Masked Register (IMR) Field Descriptions .................................................................
Interrupt Mask Set Register (IMSR) Field Descriptions ..............................................................
Interrupt Mask Clear Register (IMCR) Field Descriptions ...........................................................
DDR PHY Control Register 1 (DRPYC1R) Field Descriptions ......................................................
SPRUH77C – April 2013 – Revised September 2016
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List of Tables
389
398
405
406
407
409
409
409
410
415
416
416
417
417
418
419
419
420
421
424
425
426
427
428
429
429
430
431
432
433
433
434
434
435
436
437
61
www.ti.com
16-1.
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger........................................... 451
16-2.
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
16-3.
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ............................................... 455
16-4.
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers ............................... 457
16-5.
ECAP Initialization for APWM Mode ................................................................................... 459
16-6.
ECAP1 Initialization for Multichannel PWM Generation with Synchronization
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
62
............................
...................................
ECAP2 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP3 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP4 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP1 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP2 Initialization for Multichannel PWM Generation with Phase Control .....................................
ECAP3 Initialization for Multichannel PWM Generation with Phase Control .....................................
Control and Status Register Set ........................................................................................
Time-Stamp Counter Register (TSCTR) Field Descriptions ........................................................
Counter Phase Control Register (CTRPHS) Field Descriptions ....................................................
Capture 1 Register (CAP1) Field Descriptions........................................................................
Capture 2 Register (CAP2) Field Descriptions........................................................................
Capture 3 Register (CAP3) Field Descriptions........................................................................
Capture 4 Register (CAP4) Field Descriptions........................................................................
ECAP Control Register 1 (ECCTL1) Field Descriptions .............................................................
ECAP Control Register 2 (ECCTL2) Field Descriptions .............................................................
ECAP Interrupt Enable Register (ECEINT) Field Descriptions .....................................................
ECAP Interrupt Flag Register (ECFLG) Field Descriptions .........................................................
ECAP Interrupt Clear Register (ECCLR) Field Descriptions .......................................................
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions .....................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
ePWM Module Control and Status Registers Grouped by Submodule ............................................
Submodule Configuration Parameters .................................................................................
Time-Base Submodule Registers.......................................................................................
Key Time-Base Signals ..................................................................................................
Counter-Compare Submodule Registers .............................................................................
Counter-Compare Submodule Key Signals ...........................................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Submodule Possible Input Events ..................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode ...........................................................
Action-Qualifier Event Priority for Up-Count Mode ...................................................................
Action-Qualifier Event Priority for Down-Count Mode ................................................................
Behavior if CMPA/CMPB is Greater than the Period ................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
EPWMx Run Time Changes for ........................................................................................
EPWMx Initialization for .................................................................................................
List of Tables
453
461
461
461
461
464
464
464
465
465
466
466
467
467
468
468
470
472
473
474
475
476
482
483
488
489
497
497
501
502
504
504
504
505
508
508
510
510
512
512
514
514
516
516
518
SPRUH77C – April 2013 – Revised September 2016
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........................................................................................
Dead-Band Generator Submodule Registers .........................................................................
Classical Dead-Band Operating Modes ...............................................................................
PWM-Chopper Submodule Registers ..................................................................................
Trip-Zone Submodule Registers ........................................................................................
Possible Actions On a Trip Event.......................................................................................
Event-Trigger Submodule Registers ..................................................................................
Resolution for PWM and HRPWM......................................................................................
HRPWM Submodule Registers .........................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution .............................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ........................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
EPWM3 Initialization for .................................................................................................
EPWM1 Initialization for .................................................................................................
EPWM2 Initialization for .................................................................................................
Submodule Registers ....................................................................................................
Time-Base Submodule Registers.......................................................................................
Time-Base Control Register (TBCTL) Field Descriptions ...........................................................
Time-Base Status Register (TBSTS) Field Descriptions ............................................................
Time-Base Phase Register (TBPHS) Field Descriptions ............................................................
Time-Base Counter Register (TBCNT) Field Descriptions ..........................................................
Time-Base Period Register (TBPRD) Field Descriptions ............................................................
Counter-Compare Submodule Registers ..............................................................................
Counter-Compare Control Register (CMPCTL) Field Descriptions ................................................
Counter-Compare A Register (CMPA) Field Descriptions...........................................................
Counter-Compare B Register (CMPB) Field Descriptions...........................................................
Action-Qualifier Submodule Registers .................................................................................
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .......................................
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .......................................
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions ..........................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions .........................
Dead-Band Generator Submodule Registers .........................................................................
Dead-Band Generator Control Register (DBCTL) Field Descriptions..............................................
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions ...............................
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ...............................
PWM-Chopper Control Register (PCCTL) Bit Descriptions .........................................................
Trip-Zone Submodule Registers ........................................................................................
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ...............................................
17-24. EPWMx Run Time Changes for
518
17-25.
519
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
521
523
528
529
531
536
537
538
539
546
546
546
549
549
552
552
555
555
556
561
561
562
565
565
566
566
567
568
569
569
570
570
571
572
573
573
574
575
576
577
577
578
579
579
580
581
581
63
www.ti.com
17-73. Trip-Zone Control Register (TZCTL) Field Descriptions ............................................................. 582
17-74. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions ................................................. 582
17-75. Trip-Zone Flag Register (TZFLG) Field Descriptions ................................................................ 583
..............................................................
Trip-Zone Force Register (TZFRC) Field Descriptions ..............................................................
Event-Trigger Submodule Registers ...................................................................................
Event-Trigger Selection Register (ETSEL) Field Descriptions .....................................................
Event-Trigger Prescale Register (ETPS) Field Descriptions .......................................................
Event-Trigger Flag Register (ETFLG) Field Descriptions ...........................................................
Event-Trigger Clear Register (ETCLR) Field Descriptions ..........................................................
Event-Trigger Force Register (ETFRC) Field Descriptions .........................................................
High-Resolution PWM Submodule Registers .........................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions ....................................
Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions ...................................
HRPWM Configuration Register (HRCNFG) Field Descriptions ....................................................
EDMA3 Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ....................................................................................
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .....................................
Expected Number of Transfers for Non-Null Transfer ...............................................................
EDMA3 DMA Channel to PaRAM Mapping ...........................................................................
Shadow Region Registers ...............................................................................................
Chain Event Triggers .....................................................................................................
EDMA3 Transfer Completion Interrupts ...............................................................................
EDMA3 Error Interrupts ..................................................................................................
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping .................................................
Number of Interrupts .....................................................................................................
EDMA3 Transfer Controller Configurations ...........................................................................
Read/Write Command Optimization Rules ............................................................................
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries.....................................
Channel Options Parameters (OPT) Field Descriptions .............................................................
Channel Source Address Parameter (SRC) Field Descriptions ....................................................
A Count/B Count Parameter (A_B_CNT) Field Descriptions .......................................................
Channel Destination Address Parameter (DST) Field Descriptions ...............................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .........................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ........................
C Count Parameter (CCNT) Field Descriptions.......................................................................
EDMA3 Channel Controller (EDMA3CC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3CC Configuration Register (CCCFG) Field Descriptions ...................................................
QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions .............................................
DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ....................................
Bits in DMAQNUMn ......................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ....................................
Event Missed Register (EMR) Field Descriptions ....................................................................
Event Missed Clear Register (EMCR) Field Descriptions ...........................................................
QDMA Event Missed Register (QEMR) Field Descriptions .........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................
EDMA3CC Error Register (CCERR) Field Descriptions .............................................................
17-76. Trip-Zone Clear Register (TZCLR) Field Descriptions
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
64
List of Tables
584
584
585
585
586
587
587
588
588
589
589
590
604
607
608
616
618
620
623
623
624
624
625
632
638
657
658
660
660
661
661
662
663
663
664
667
668
669
670
670
671
672
673
674
675
676
SPRUH77C – April 2013 – Revised September 2016
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18-35. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................ 677
18-36. Error Evaluate Register (EEVAL) Field Descriptions................................................................. 678
18-37. DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions .............................. 679
18-38. QDMA Region Access Enable for Region m (QRAEm) Field Descriptions ....................................... 680
18-39. Event Queue Entry Registers (QxEy) Field Descriptions ............................................................ 681
18-40. Queue n Status Register (QSTATn) Field Descriptions ............................................................. 682
18-41. Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................... 683
18-42. EDMA3CC Status Register (CCSTAT) Field Descriptions .......................................................... 684
18-43. Event Register (ER) Field Descriptions ................................................................................ 686
18-44. Event Clear Register (ECR) Field Descriptions ....................................................................... 687
18-45. Event Set Register (ESR) Field Descriptions ......................................................................... 688
18-46. Chained Event Register (CER) Field Descriptions ................................................................... 689
18-47. Event Enable Register (EER) Field Descriptions ..................................................................... 690
18-48. Event Enable Clear Register (EECR) Field Descriptions ............................................................ 691
.............................................................
................................................................
Secondary Event Clear Register (SECR) Field Descriptions .......................................................
Interrupt Enable Register (IER) Field Descriptions ...................................................................
Interrupt Enable Clear Register (IECR) Field Descriptions..........................................................
Interrupt Enable Set Register (IESR) Field Descriptions ............................................................
Interrupt Pending Register (IPR) Field Descriptions .................................................................
Interrupt Clear Register (ICR) Field Descriptions.....................................................................
Interrupt Evaluate Register (IEVAL) Field Descriptions .............................................................
QDMA Event Register (QER) Field Descriptions .....................................................................
QDMA Event Enable Register (QEER) Field Descriptions ..........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions .................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ...................................................
QDMA Secondary Event Register (QSER) Field Descriptions .....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................
EDMA3 Transfer Controller (EDMA3TC) Registers ..................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................
Error Status Register (ERRSTAT) Field Descriptions ...............................................................
Error Enable Register (ERREN) Field Descriptions ..................................................................
Error Clear Register (ERRCLR) Field Descriptions ..................................................................
Error Details Register (ERRDET) Field Descriptions ................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions.................................................
Read Command Rate Register (RDRATE) Field Descriptions .....................................................
Source Active Options Register (SAOPT) Field Descriptions.......................................................
Source Active Source Address Register (SASRC) Field Descriptions ............................................
Source Active Count Register (SACNT) Field Descriptions .........................................................
Source Active Destination Address Register (SADST) Field Descriptions ........................................
Source Active B-Index Register (SABIDX) Field Descriptions ......................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................
Source Active Count Reload Register (SACNTRLD) Field Descriptions ..........................................
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions .....................
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions .................
Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions .................................
18-49. Event Enable Set Register (EESR) Field Descriptions
691
18-50. Secondary Event Register (SER) Field Descriptions
692
18-51.
692
18-52.
18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
18-63.
18-64.
18-65.
18-66.
18-67.
18-68.
18-69.
18-70.
18-71.
18-72.
18-73.
18-74.
18-75.
18-76.
18-77.
18-78.
18-79.
18-80.
18-81.
18-82.
18-83.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
693
694
694
695
696
697
698
699
700
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
714
715
715
716
717
717
718
718
65
www.ti.com
18-84. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions ............. 719
18-85. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions ........ 719
18-86. Destination FIFO Options Register n (DFOPTn) Field Descriptions ............................................... 720
18-87. Destination FIFO Source Address Register n (DFSRCn) Field Descriptions ..................................... 721
18-88. Destination FIFO Count Register n (DFCNTn) Field Descriptions ................................................. 721
18-89. Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions ................................ 722
18-90. Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions .............................................. 722
18-91. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions .................... 723
18-92. Debug List ................................................................................................................. 724
19-1.
EMAC and MDIO Signals for MII Interface ............................................................................ 733
19-2.
EMAC and MDIO Signals for RMII Interface .......................................................................... 734
19-3.
Ethernet Frame Description ............................................................................................. 735
19-4.
Basic Descriptor Description ............................................................................................ 737
19-5.
Receive Frame Treatment Summary
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
..................................................................................
Middle of Frame Overrun Treatment ...................................................................................
Emulation Control .........................................................................................................
EMAC Control Module Registers .......................................................................................
EMAC Control Module Revision ID Register (REVID) Field Descriptions .........................................
EMAC Control Module Software Reset Register (SOFTRESET) ..................................................
EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................
762
763
773
774
775
776
777
19-12. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 778
19-13. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ...................... 779
19-14. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 780
19-15. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 781
19-16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) ................................................................................................... 782
19-17. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 783
19-18. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ................... 784
19-19. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)
.........
785
19-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........ 786
19-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX)
.......
787
19-22. Management Data Input/Output (MDIO) Registers................................................................... 788
19-23. MDIO Revision ID Register (REVID) Field Descriptions............................................................. 788
19-24. MDIO Control Register (CONTROL) Field Descriptions ............................................................. 789
19-25. PHY Acknowledge Status Register (ALIVE) Field Descriptions .................................................... 790
19-26. PHY Link Status Register (LINK) Field Descriptions ................................................................. 790
19-27. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................ 791
19-28. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
..............
792
19-29. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ....... 793
19-30. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ..... 794
19-31. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .... 795
19-32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ............................................................................................................... 796
19-33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................. 797
19-34. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ........................................ 798
19-35. MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................. 799
19-36. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ........................................ 800
19-37. Ethernet Media Access Controller (EMAC) Registers ............................................................... 801
19-38. Transmit Revision ID Register (TXREVID) Field Descriptions ...................................................... 804
66
List of Tables
SPRUH77C – April 2013 – Revised September 2016
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19-39. Transmit Control Register (TXCONTROL) Field Descriptions ...................................................... 804
19-40. Transmit Teardown Register (TXTEARDOWN) Field Descriptions ................................................ 805
19-41. Receive Revision ID Register (RXREVID) Field Descriptions ...................................................... 806
19-42. Receive Control Register (RXCONTROL) Field Descriptions ...................................................... 806
19-43. Receive Teardown Register (RXTEARDOWN) Field Descriptions
................................................
807
19-44. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ........................ 808
19-45. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions....................... 809
19-46. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
....................................
810
19-47. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions .............................. 811
19-48. MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................. 812
19-49. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions .................................. 813
19-50. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ......................... 814
19-51. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ....................... 815
19-52. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ..................................... 816
19-53. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................... 817
19-54. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .......................... 818
19-55. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions......................... 818
19-56. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...................................... 819
19-57. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................ 819
19-58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 820
19-59. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 823
19-60. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 824
19-61. Receive Maximum Length Register (RXMAXLEN) Field Descriptions
............................................
825
19-62. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions........................................ 825
19-63. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 826
19-64. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............... 826
19-65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ...................... 827
19-66. MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 828
...........................................................
Emulation Control Register (EMCONTROL) Field Descriptions ....................................................
FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................
MAC Configuration Register (MACCONFIG) Field Descriptions ...................................................
Soft Reset Register (SOFTRESET) Field Descriptions ..............................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions.............................
MAC Hash Address Register 1 (MACHASH1) Field Descriptions .................................................
MAC Hash Address Register 2 (MACHASH2) Field Descriptions .................................................
Back Off Test Register (BOFFTEST) Field Descriptions ............................................................
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions .....................................
Receive Pause Timer Register (RXPAUSE) Field Descriptions ....................................................
Transmit Pause Timer Register (TXPAUSE) Field Descriptions ...................................................
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ...........................................
MAC Address High Bytes Register (MACADDRHI) Field Descriptions............................................
MAC Index Register (MACINDEX) Field Descriptions ...............................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ....................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ....................
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions ..................................
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ...................................
EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories........................................
19-67. MAC Status Register (MACSTATUS) Field Descriptions
830
19-68.
832
19-69.
19-70.
19-71.
19-72.
19-73.
19-74.
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
19-82.
19-83.
19-84.
19-85.
19-86.
20-1.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
832
833
833
834
834
835
835
836
836
837
837
838
839
839
840
840
841
841
853
67
www.ti.com
20-2.
EMIFA Pins Specific to SDRAM ........................................................................................ 854
20-3.
EMIFA Pins Specific to Asynchronous Memory ...................................................................... 854
20-4.
EMIFA SDRAM Commands ............................................................................................. 855
20-5.
Truth Table for SDRAM Commands ................................................................................... 855
20-6.
16-bit EMIFA Address Pin Connections ............................................................................... 857
20-7.
Description of the SDRAM Configuration Register (SDCR) ......................................................... 858
20-8.
Description of the SDRAM Refresh Control Register (SDRCR) .................................................... 858
20-9.
Description of the SDRAM Timing Register (SDTIMR) .............................................................. 859
20-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ...................................... 859
20-11. SDRAM LOAD MODE REGISTER Command ........................................................................ 860
861
20-13.
866
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
68
.................................................................................................
Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM .................................................
Normal Mode vs. Select Strobe Mode .................................................................................
Description of the Asynchronous m Configuration Register (CEnCFG) ...........................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCC) ..................................
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ............................................
Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) ..........................................
Asynchronous Read Operation in Normal Mode .....................................................................
Asynchronous Write Operation in Normal Mode .....................................................................
Asynchronous Read Operation in Select Strobe Mode ..............................................................
Asynchronous Write Operation in Select Strobe Mode ..............................................................
Description of the NAND Flash Control Register (NANDFCR) .....................................................
Reset Sources.............................................................................................................
Interrupt Monitor and Control Bit Fields ................................................................................
SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface ................................................
SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface ..................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface .................................................
SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface ..........................................
EMIFA Input Timing Requirements .....................................................................................
ASRAM Output Timing Characteristics ................................................................................
ASRAM Input Timing Requirement for a Read .......................................................................
ASRAM Input Timing Requirements for a Write .....................................................................
ASRAM Timing Requirements With PCB Delays.....................................................................
EMIFA Timing Requirements for TC5516100FT-12 Example .....................................................
ASRAM Timing Requirements for TC5516100FT-12 Example .....................................................
Measured PCB Delays for TC5516100FT-12 Example .............................................................
Configuring CE3CFG for TC5516100FT-12 Example ...............................................................
Recommended Margins..................................................................................................
EMIFA Read Timing Requirements ....................................................................................
NAND Flash Read Timing Requirements .............................................................................
NAND Flash Write Timing Requirements .............................................................................
EMIFA Timing Requirements for HY27UA081G1M Example .......................................................
NAND Flash Timing Requirements for HY27UA081G1M Example ................................................
Configuring CE2CFG for HY27UA081G1M Example ................................................................
Configuring NANDFCR for HY27UA081G1M Example..............................................................
External Memory Interface (EMIFA) Registers .......................................................................
Module ID Register (MIDR) Field Descriptions .......................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions .................................
20-12. Refresh Urgency Levels
List of Tables
867
869
870
872
872
872
874
876
878
880
886
888
893
895
896
896
897
898
898
898
899
901
904
904
904
906
906
907
907
909
912
912
914
914
915
916
917
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
20-51. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................ 918
20-52. SDRAM Refresh Control Register (SDRCR) Field Descriptions
...................................................
920
20-53. Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... 921
20-54. SDRAM Timing Register (SDTIMR) Field Descriptions.............................................................. 923
20-55. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ...................................... 924
20-56. EMIFA Interrupt Raw Register (INTRAW) Field Descriptions....................................................... 925
20-57. EMIFA Interrupt Mask Register (INTMSK) Field Descriptions ...................................................... 926
20-58. EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ............................................ 927
20-59. EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions ......................................... 928
20-60. NAND Flash Control Register (NANDFCR) Field Descriptions ..................................................... 929
20-61. NAND Flash Status Register (NANDFSR) Field Descriptions ...................................................... 931
20-62. NAND Flash n ECC Register (NANDFnECC) Field Descriptions .................................................. 932
20-63. NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ............................ 933
20-64. NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions ........................................ 934
20-65. NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions ........................................ 934
20-66. NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions ........................................ 935
20-67. NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions ........................................ 935
20-68. NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ...................... 936
20-69. NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ...................... 936
20-70. NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions .......................... 937
20-71. NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions .......................... 937
21-1.
GPIO Register Bits and Banks Associated With GPIO Signals .................................................... 941
21-2.
GPIO Registers
21-3.
Revision ID Register (REVID) Field Descriptions
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
........................................................................................................... 948
.................................................................... 949
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions .......................................... 950
GPIO Direction Register (DIRn) Field Descriptions .................................................................. 952
GPIO Output Data Register (OUT_DATAn) Field Descriptions .................................................... 954
GPIO Set Data Register (SET_DATAn) Field Descriptions ......................................................... 956
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ...................................................... 958
GPIO Input Data Register (IN_DATAn) Field Descriptions.......................................................... 960
GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions ...................... 962
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions ............................. 964
GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions ..................... 966
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions ............................ 968
GPIO Interrupt Status Register (INTSTATn) Field Descriptions .................................................... 970
HPI Pins .................................................................................................................... 975
Value on Optional Pins when Configured as General-Purpose I/O ................................................ 976
Options for Connecting Host and HPI Data Strobe Pins ............................................................ 980
Access Types Selectable With the UHPI_HCNTL Signals .......................................................... 981
Cycle Types Selectable With the UHPI_HCNTL and UHPI_HR/W Signals....................................... 981
HPI Registers.............................................................................................................. 995
Revision Identification Register (REVID) Field Descriptions ........................................................ 996
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions .......................... 996
GPIO Enable Register (GPIO_EN) Field Descriptions............................................................... 997
GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions ........................................................ 998
GPIO Data 1 Register (GPIO_DAT1) Field Descriptions ............................................................ 998
GPIO Direction 2 Register (GPIO_DIR2) Field Descriptions ........................................................ 999
GPIO Data 2 Register (GPIO_DAT2) Field Descriptions .......................................................... 1000
Host Port Interface Control Register (HPIC) Field Descriptions .................................................. 1002
SPRUH77C – April 2013 – Revised September 2016
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List of Tables
69
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22-15. Host Port Interface Write Address Register (HPIAW) Field Descriptions ........................................ 1003
22-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions ........................................ 1003
23-1.
Operating Modes of the I2C Peripheral .............................................................................. 1013
23-2.
Ways to Generate a NACK Bit ........................................................................................ 1014
23-3.
Descriptions of the I2C Interrupt Events
23-4.
Inter-Integrated Circuit (I2C) Registers ............................................................................... 1019
23-5.
I2C Own Address Register (ICOAR) Field Descriptions ........................................................... 1020
23-6.
I2C Interrupt Mask Register (ICIMR) Field Descriptions ........................................................... 1021
23-7.
I2C Interrupt Status Register (ICSTR) Field Descriptions
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
70
.............................................................................
.........................................................
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions ..............................................
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions .............................................
I2C Data Count Register (ICCNT) Field Descriptions ..............................................................
I2C Data Receive Register (ICDRR) Field Descriptions ...........................................................
I2C Slave Address Register (ICSAR) Field Descriptions ..........................................................
I2C Data Transmit Register (ICDXR) Field Descriptions ...........................................................
I2C Mode Register (ICMDR) Field Descriptions ....................................................................
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits .................................
How the MST and FDF Bits Affect the Role of TRX Bit ............................................................
I2C Interrupt Vector Register (ICIVR) Field Descriptions ..........................................................
I2C Extended Mode Register (ICEMDR) Field Descriptions ......................................................
I2C Prescaler Register (ICPSC) Field Descriptions ................................................................
I2C Revision Identification Register 1 (REVID1) Field Descriptions ..............................................
I2C Revision Identification Register 2 (REVID2) Field Descriptions ..............................................
I2C DMA Control Register (ICDMAC) Field Descriptions ..........................................................
I2C Pin Function Register (ICPFUNC) Field Descriptions .........................................................
I2C Pin Direction Register (ICPDIR) Field Descriptions ...........................................................
I2C Pin Data In Register (ICPDIN) Field Descriptions .............................................................
I2C Pin Data Out Register (ICPDOUT) Field Descriptions ........................................................
I2C Pin Data Set Register (ICPDSET) Field Descriptions .........................................................
I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ......................................................
LCD External I/O Signals ...............................................................................................
Register Configuration for DMA Engine Programming .............................................................
LIDD I/O Name Map ....................................................................................................
Operation Modes Supported by Raster Controller ..................................................................
Bits-Per-Pixel Encoding for Palette Entry 0 Buffer ..................................................................
Frame Buffer Size According to BPP .................................................................................
Color/Grayscale Intensities and Modulation Rates .................................................................
Number of Colors/Shades of Gray Available on Screen ...........................................................
LCD Controller (LCDC) Registers .....................................................................................
LCD Revision Identification Register (REVID) Field Descriptions ................................................
LCD Control Register (LCD_CTRL) Field Descriptions ............................................................
Pixel Clock Frequency Programming Limitations ...................................................................
LCD Status Register (LCD_STAT) Field Descriptions .............................................................
LCD LIDD Control Register (LIDD_CTRL) Field Descriptions ....................................................
LCD LIDD CSn Configuration Register (LIDD_CSn_CONF) Field Descriptions ................................
LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR) Field Descriptions........................
LCD LIDD CSn Data Read/Write Register (LIDD_CSn_DATA) Field Descriptions ............................
LCD Raster Control Register (RASTER_CTRL) Field Descriptions ..............................................
LCD Controller Data Pin Utilization for Mono/Color Passive/Active Panels .....................................
List of Tables
1018
1022
1025
1025
1026
1027
1028
1029
1030
1032
1032
1034
1035
1036
1037
1037
1038
1039
1040
1041
1042
1043
1044
1049
1050
1052
1053
1055
1056
1060
1060
1063
1063
1064
1065
1066
1069
1071
1072
1073
1074
1076
SPRUH77C – April 2013 – Revised September 2016
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24-20. LCD Raster Timing Register 0 (RASTER_TIMING_0) Field Descriptions ....................................... 1081
24-21. LCD Raster Timing Register 1 (RASTER_TIMING_1) Field Descriptions ....................................... 1083
24-22. LCD Raster Timing Register 2 (RASTER_TIMING_2) Field Descriptions ....................................... 1087
24-23. LCD Raster Subpanel Display Register (RASTER_SUBPANEL) Field Descriptions .......................... 1091
24-24. LCD DMA Control Register (LCDDMA_CTRL) Field Descriptions
...............................................
1093
24-25. LCD DMA Frame Buffer n Base Address Register (LCDDMA_FBn_BASE) Field Descriptions .............. 1094
24-26. LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) Field Descriptions ........ 1094
25-1.
Biphase-Mark Encoder ................................................................................................. 1103
25-2.
Preamble Codes ......................................................................................................... 1104
25-3.
Channel Status and User Data for Each DIT Block
25-4.
Transmit Bitstream Data Alignment ................................................................................... 1138
25-5.
Receive Bitstream Data Alignment.................................................................................... 1140
25-6.
EDMA Events - McASP
25-7.
McASP Registers Accessed by CPU/EDMA Through Peripheral Configuration Port .......................... 1151
25-8.
McASP Registers Accessed by CPU/EDMA Through DMA Port ................................................. 1154
25-9.
McASP AFIFO Registers Accessed Through Peripheral Configuration Port .................................... 1154
................................................................
................................................................................................
1130
1150
25-10. Revision Identification Register (REV) Field Descriptions ......................................................... 1155
25-11. Pin Function Register (PFUNC) Field Descriptions ................................................................. 1157
25-12. Pin Direction Register (PDIR) Field Descriptions ................................................................... 1159
25-13. Pin Data Output Register (PDOUT) Field Descriptions ............................................................ 1161
.................................................................
Pin Data Set Register (PDSET) Field Descriptions .................................................................
Pin Data Clear Register (PDCLR) Field Descriptions ..............................................................
Global Control Register (GBLCTL) Field Descriptions .............................................................
Audio Mute Control Register (AMUTE) Field Descriptions ........................................................
Digital Loopback Control Register (DLBCTL) Field Descriptions .................................................
Digital Mode Control Register (DITCTL) Field Descriptions .......................................................
Receiver Global Control Register (RGBLCTL) Field Descriptions ................................................
Receive Format Unit Bit Mask Register (RMASK) Field Descriptions ...........................................
Receive Bit Stream Format Register (RFMT) Field Descriptions .................................................
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions ..........................................
Receive Clock Control Register (ACLKRCTL) Field Descriptions ................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ..........................
Receive TDM Time Slot Register (RTDM) Field Descriptions.....................................................
Receiver Interrupt Control Register (RINTCTL) Field Descriptions ...............................................
Receiver Status Register (RSTAT) Field Descriptions .............................................................
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions ........................................
Receive Clock Check Control Register (RCLKCHK) Field Descriptions .........................................
Receiver DMA Event Control Register (REVTCTL) Field Descriptions ..........................................
Transmitter Global Control Register (XGBLCTL) Field Descriptions .............................................
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ...........................................
Transmit Bit Stream Format Register (XFMT) Field Descriptions ................................................
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions .........................................
Transmit Clock Control Register (ACLKXCTL) Field Descriptions................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions..........................
Transmit TDM Time Slot Register (XTDM) Field Descriptions ....................................................
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions ............................................
Transmitter Status Register (XSTAT) Field Descriptions ..........................................................
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions .........................................
25-14. Pin Data Input Register (PDIN) Field Descriptions
1163
25-15.
1165
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
SPRUH77C – April 2013 – Revised September 2016
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List of Tables
1167
1168
1170
1172
1173
1174
1175
1176
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1191
1192
1193
1194
1195
1196
1197
71
www.ti.com
25-43. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ........................................ 1198
25-44. Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions ....................................... 1199
25-45. Serializer Control Registers (SRCTLn) Field Descriptions......................................................... 1200
1204
25-47.
1205
25-48.
25-49.
25-50.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
26-25.
26-26.
26-27.
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
26-34.
26-35.
26-36.
26-37.
26-38.
26-39.
27-1.
27-2.
72
........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions .....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions ......................................................
McBSP Interface Signals ...............................................................................................
Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits ..............
Receive Clock Selection................................................................................................
Transmit Clock Selection ...............................................................................................
Receive Frame Synchronization Selection...........................................................................
Transmit Frame Synchronization Selection ..........................................................................
RCR/XCR Fields Controlling Elements per Frame and Bits per Element .......................................
Receive/Transmit Frame Length Configuration .....................................................................
Receive/Transmit Element Length Configuration ...................................................................
Effect of RJUST Bit Values With 12-Bit Example Data ABCh.....................................................
Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh .................................................
Justification of Expanded Data in DRR...............................................................................
Receive Channel Assignment and Control When Two Receive Partitions are Used ..........................
Transmit Channel Assignment and Control When Two Transmit Partitions are Used .........................
Receive Channel Assignment and Control When Eight Receive Partitions are Used .........................
Transmit Channel Assignment and Control When Eight Transmit Partitions are Used ........................
Selecting a Transmit Multichannel Selection Mode With the XMCM Bits........................................
Reset State of McBSP Pins ............................................................................................
Receiver Clock and Frame Configurations ..........................................................................
Transmitter Clock and Frame Configurations .......................................................................
McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR ................................
McBSP Registers........................................................................................................
Data Receive Register (DRR) Field Descriptions ...................................................................
Data Transmit Register (DXR) Field Descriptions ..................................................................
Serial Port Control Register (SPCR) Field Descriptions ...........................................................
Receive Control Register (RCR) Field Descriptions ...............................................................
Transmit Control Register (XCR) Field Descriptions ..............................................................
Sample Rate Generator Register (SRGR) Field Descriptions .....................................................
Multichannel Control Register (MCR) Field Descriptions ..........................................................
Enhanced Receive Channel Enable Register n (RCEREn) Field Descriptions .................................
Use of the Receive Channel Enable Registers......................................................................
Enhanced Transmit Channel Enable Register n (XCEREn) Field Descriptions ................................
Use of the Transmit Channel Enable Registers .....................................................................
Pin Control Register (PCR) Field Descriptions ......................................................................
BFIFO Revision Identification Register (BFIFOREV) Field Descriptions ........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions .....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions .....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions ......................................................
MMC/SD Controller Pins Used in Each Mode .......................................................................
MMC/SD Mode Write Sequence ......................................................................................
25-46. AFIFO Revision Identification Register (AFIFOREV) Field Descriptions
List of Tables
1206
1207
1208
1212
1216
1219
1220
1221
1222
1223
1223
1224
1226
1226
1242
1245
1245
1247
1247
1248
1251
1252
1252
1258
1259
1260
1260
1261
1263
1265
1267
1268
1272
1273
1274
1275
1276
1278
1279
1280
1281
1282
1287
1288
SPRUH77C – April 2013 – Revised September 2016
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27-3.
MMC/SD Mode Read Sequence ...................................................................................... 1289
27-4.
Description of MMC/SD Interrupt Requests
27-5.
Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers........................................... 1313
27-6.
MMC Control Register (MMCCTL) Field Descriptions.............................................................. 1314
27-7.
MMC Memory Clock Control Register (MMCCLK) Field Descriptions ........................................... 1315
27-8.
MMC Status Register 0 (MMCST0) Field Descriptions
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
27-28.
27-29.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
.........................................................................
............................................................
MMC Status Register 1 (MMCST1) Field Descriptions ............................................................
MMC Interrupt Mask Register (MMCIM) Field Descriptions .......................................................
MMC Response Time-Out Register (MMCTOR) Field Descriptions .............................................
MMC Data Read Time-Out Register (MMCTOD) Field Descriptions .............................................
MMC Block Length Register (MMCBLEN) Field Descriptions .....................................................
MMC Number of Blocks Register (MMCNBLK) Field Descriptions ...............................................
MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions ....................................
MMC Data Receive Register (MMCDRR) Field Descriptions .....................................................
MMC Data Transmit Register (MMCDXR) Field Descriptions .....................................................
MMC Command Register (MMCCMD) Field Descriptions .........................................................
Command Format .......................................................................................................
MMC Argument Register (MMCARGHL) Field Descriptions ......................................................
R1, R3, R4, R5, or R6 Response (48 Bits) ..........................................................................
R2 Response (136 Bits) ................................................................................................
MMC Data Response Register (MMCDRSP) Field Descriptions .................................................
MMC Command Index Register (MMCCIDX) Field Descriptions .................................................
SDIO Control Register (SDIOCTL) Field Descriptions .............................................................
SDIO Status Register 0 (SDIOST0) Field Descriptions ............................................................
SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions ...................................................
SDIO Interrupt Status Register (SDIOIST) Field Descriptions ....................................................
MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions ................................................
Real-Time Clock Signals ...............................................................................................
Real-Time Clock (RTC) Registers ....................................................................................
Second Register (SECOND) Field Descriptions ....................................................................
Minute Register (MINUTE) Field Descriptions.......................................................................
Hour Register (HOUR) Field Descriptions ...........................................................................
Day Register (DAY) Field Descriptions ...............................................................................
Month Register (MONTH) Field Descriptions ........................................................................
Year Register (YEAR) Field Descriptions ............................................................................
Day of the Week Register (DOTW) Field Descriptions .............................................................
Alarm Second Register (ALARMSECOND) Field Descriptions ...................................................
Alarm Minute Register (ALARMMINUTE) Field Descriptions .....................................................
Alarm Hour Register (ALARMHOUR) Field Descriptions ..........................................................
Alarm Day Register (ALARMDAY) Field Descriptions..............................................................
Alarm Month Register (ALARMMONTH) Field Descriptions ......................................................
Alarm Years Register (ALARMYEARS) Field Descriptions ........................................................
Control Register (CTRL) Field Descriptions .........................................................................
Status Register (STATUS) Field Descriptions .......................................................................
Interrupt Register (INTERRUPT) Field Descriptions................................................................
Compensations Register (COMPLSB) Field Descriptions .........................................................
Compensations Register (COMPMSB) Field Descriptions ........................................................
Oscillator Register (OSC) Field Descriptions ........................................................................
Scratch Registers (SCRATCHn) Field Descriptions ................................................................
SPRUH77C – April 2013 – Revised September 2016
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List of Tables
1299
1316
1318
1319
1321
1322
1323
1324
1324
1325
1325
1326
1327
1328
1330
1330
1331
1331
1332
1333
1334
1334
1335
1338
1344
1345
1345
1346
1347
1347
1348
1348
1349
1349
1350
1351
1352
1352
1353
1354
1355
1356
1357
1358
1359
73
www.ti.com
28-23. Kick Registers (KICKnR) Field Descriptions ......................................................................... 1359
29-1.
MPY Bit Field of P0PHYCR ............................................................................................ 1365
29-2.
Signal Descriptions ...................................................................................................... 1366
29-3.
SATASS Memory Summary ........................................................................................... 1390
29-4.
SATA Controller Registers ............................................................................................. 1391
29-5.
HBA Capabilities Register (CAP) Field Descriptions ............................................................... 1392
29-6.
Global HBA Control Register (GHC) Field Descriptions
29-7.
Interrupt Status Register (IS) Field Descriptions .................................................................... 1394
29-8.
Ports Implemented Register (PI) Field Descriptions ................................................................ 1395
29-9.
AHCI Version Register (VS) Field Descriptions ..................................................................... 1395
...........................................................
1393
29-10. Command Completion Coalescing Control Register (CCC_CTL) Field Descriptions .......................... 1396
29-11. Command Completion Coalescing Ports Register (CCC_PORTS) Field Description.......................... 1397
29-12. BIST Active FIS Register (BISTAFR) Field Descriptions
..........................................................
1398
29-13. BIST Control Register (BISTCR) Field Descriptions ................................................................ 1399
29-14. BIST FIS Count Register (BISTFCTR) Field Description .......................................................... 1401
29-15. BIST Status Register (BISTSR) Field Description .................................................................. 1401
29-16. BIST DWORD Error Count Register (BISTDECR) Field Description ............................................. 1402
29-17. BIST DWORD Error Count Register (TIMER1MS) Field Description ............................................ 1402
..................................................
Global Parameter 2 Register (GPARAM2R) Field Descriptions ..................................................
Port Parameter Register (PPARAMR) Field Descriptions .........................................................
Test Register (TESTR) Field Descriptions ...........................................................................
Version Register (VERSIONR) Field Description ...................................................................
ID Register (IDR) Field Description ...................................................................................
Port Command List Base Address Register (P0CLB) Field Description .........................................
Port FIS Base Address Register (P0FB) Field Description ........................................................
Port Interrupt Status Register (P0IS) Field Descriptions ...........................................................
Port Interrupt Enable Register (P0IE) Field Descriptions ..........................................................
Port Command Register (P0CMD) Field Descriptions .............................................................
Port Task File Data Register (P0TFD) Field Descriptions .........................................................
Port Signature Register (P0SIG) Field Description .................................................................
Port Serial ATA Status Register (P0SSTS) Field Descriptions ...................................................
Port Serial ATA Control Register (P0SCTL) Field Descriptions ...................................................
Port Serial ATA Error Register (P0SERR) Field Descriptions .....................................................
Port Serial ATA Active Register (P0SACT) Field Description .....................................................
Port Serial ATA Active (SActive) Register (P0SACT) Field Description .........................................
Port Serial ATA Notification Register (POSNTF) Field Description...............................................
Port DMA Control Register (P0DMACR) Field Description ........................................................
Port PHY Control Register (P0PHYCR) Field Descriptions .......................................................
Port PHY Status Register (P0PHYSR) Field Description ..........................................................
SPI Pins ..................................................................................................................
SPI Registers ............................................................................................................
SPI Register Settings Defining Master Modes ......................................................................
Allowed SPI Register Settings in Master Modes ....................................................................
SPI Register Settings Defining Slave Modes ........................................................................
Allowed SPI Register Settings in Slave Modes .....................................................................
Clocking Modes..........................................................................................................
SPI Registers ............................................................................................................
SPI Global Control Register 0 (SPIGCR0) Field Descriptions ....................................................
29-18. Global Parameter 1 Register (GPARAM1R) Field Descriptions
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
29-26.
29-27.
29-28.
29-29.
29-30.
29-31.
29-32.
29-33.
29-34.
29-35.
29-36.
29-37.
29-38.
29-39.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
74
List of Tables
1403
1404
1405
1406
1407
1407
1408
1408
1409
1411
1412
1415
1415
1416
1417
1418
1420
1420
1421
1422
1424
1428
1432
1433
1434
1434
1436
1436
1445
1458
1458
SPRUH77C – April 2013 – Revised September 2016
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....................................................
SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................
SPI Interrupt Level Register (SPILVL) Field Descriptions .........................................................
SPI Flag Register (SPIFLG) Field Descriptions .....................................................................
SPI Pin Control Register 0 (SPIPC0) Field Descriptions...........................................................
SPI Pin Control Register 1 (SPIPC1) Field Descriptions...........................................................
SPI Pin Control Register 2 (SPIPC2) Field Descriptions...........................................................
SPI Pin Control Register 3 (SPIPC3) Field Descriptions...........................................................
SPI Pin Control Register 4 (SPIPC4) Field Descriptions...........................................................
SPI Pin Control Register 5 (SPIPC5) Field Descriptions...........................................................
SPI Data Register 0 (SPIDAT0) Field Descriptions.................................................................
SPI Data Register 1 (SPIDAT1) Field Descriptions.................................................................
SPI Buffer Register (SPIBUF) Field Descriptions ...................................................................
SPI Emulation Register (SPIEMU) Field Descriptions..............................................................
SPI Delay Register (SPIDELAY) Field Descriptions ................................................................
SPI Default Chip Select Register (SPIDEF) Field Descriptions ...................................................
SPI Data Format Register (SPIFMTn) Field Descriptions .........................................................
SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions ...................................................
Timer Clock Source Selection .........................................................................................
64-Bit Timer Configurations ............................................................................................
32-Bit Timer Chained Mode Configurations .........................................................................
32-Bit Timer Unchained Mode Configurations.......................................................................
Counter and Period Registers Used in GP Timer Modes ..........................................................
TSTAT Parameters in Pulse and Clock Modes .....................................................................
Timer Emulation Modes Selection ....................................................................................
Timer Registers ..........................................................................................................
Revision ID Register (REVID) Field Descriptions ...................................................................
Emulation Management Register (EMUMGT) Field Descriptions ................................................
GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions ...............................
GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions .........................................
Timer Counter Register 12 (TIM12) Field Descriptions ............................................................
Timer Counter Register 34 (TIM34) Field Descriptions ............................................................
Timer Period Register (PRD12) Field Descriptions .................................................................
Timer Period Register (PRD34) Field Descriptions .................................................................
Timer Control Register (TCR) Field Descriptions ...................................................................
Timer Global Control Register (TGCR) Field Descriptions ........................................................
Watchdog Timer Control Register (WDTCR) Field Descriptions ..................................................
Timer Reload Register 12 (REL12) Field Descriptions .............................................................
Timer Reload Register 34 (REL34) Field Descriptions .............................................................
Timer Capture Register 12 (CAP12) Field Descriptions ...........................................................
Timer Capture Register 34 (CAP34) Field Descriptions ...........................................................
Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ................................
Timer Compare Register (CMPn) Field Descriptions ...............................................................
Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode ........................
Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode ........................
UART Signal Descriptions .............................................................................................
Character Time for Word Lengths ....................................................................................
UART Interrupt Requests Descriptions ...............................................................................
UART Registers .........................................................................................................
30-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
31-1.
31-2.
31-3.
31-4.
31-5.
31-6.
31-7.
31-8.
31-9.
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
31-19.
31-20.
31-21.
31-22.
31-23.
31-24.
31-25.
32-1.
32-2.
32-3.
32-4.
32-5.
32-6.
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1459
1461
1463
1464
1466
1467
1468
1469
1470
1471
1472
1473
1474
1476
1477
1480
1481
1483
1487
1489
1492
1495
1497
1501
1503
1503
1505
1505
1506
1507
1508
1508
1509
1509
1510
1512
1513
1514
1514
1515
1515
1516
1517
1522
1522
1523
1526
1530
1532
75
www.ti.com
32-7.
Receiver Buffer Register (RBR) Field Descriptions ................................................................. 1533
32-8.
Transmitter Holding Register (THR) Field Descriptions ............................................................ 1534
32-9.
Interrupt Enable Register (IER) Field Descriptions ................................................................. 1535
32-10. Interrupt Identification Register (IIR) Field Descriptions............................................................ 1536
32-11. Interrupt Identification and Interrupt Clearing Information
.........................................................
1537
32-12. FIFO Control Register (FCR) Field Descriptions .................................................................... 1538
32-13. Line Control Register (LCR) Field Descriptions ..................................................................... 1539
32-14. Relationship Between ST, EPS, and PEN Bits in LCR............................................................. 1540
32-15. Number of STOP Bits Generated ..................................................................................... 1540
32-16. Modem Control Register (MCR) Field Descriptions
................................................................
1541
32-17. Line Status Register (LSR) Field Descriptions ...................................................................... 1542
32-18. Modem Status Register (MSR) Field Descriptions.................................................................. 1545
32-19. Scratch Pad Register (MSR) Field Descriptions .................................................................... 1546
1547
32-21.
1547
32-22.
32-23.
32-24.
32-25.
33-1.
33-2.
33-3.
33-4.
33-5.
33-6.
33-7.
33-8.
33-9.
33-10.
33-11.
33-12.
33-13.
33-14.
33-15.
33-16.
33-17.
33-18.
33-19.
33-20.
33-21.
33-22.
33-23.
33-24.
33-25.
33-26.
33-27.
33-28.
33-29.
33-30.
76
.........................................................................
Divisor MSB Latch (DLH) Field Descriptions ........................................................................
Revision Identification Register 1 (REVID1) Field Descriptions ...................................................
Revision Identification Register 2 (REVID2) Field Descriptions ...................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions .........................
Mode Definition Register (MDR) Field Descriptions ................................................................
I/O Clock Speeds for Channel in Transmit Mode Given 150 MHz Transmit Clock .............................
uPP Signal Descriptions ................................................................................................
DATA and XDATA Pin Assignments to Channels A and B According to Operating Mode ....................
Interface and DMA Channel Mapping for Various Operating Modes .............................................
Required Signals for Various Modes .................................................................................
Data Packing Examples for 12-Bit Data Words .....................................................................
Basic Operating Mode Selection ......................................................................................
Sample uPP Parameters for Duplex Mode 0 .......................................................................
uPP Parameters Useful for System Tuning .........................................................................
uPP Registers ...........................................................................................................
uPP Peripheral Identification Register (UPPID) Field Descriptions ...............................................
uPP Peripheral Control Register (UPPCR) Field Descriptions ....................................................
uPP Digital Loopback Register (UPDLB) Field Descriptions ......................................................
uPP Channel Control Register (UPCTL) Field Descriptions .......................................................
uPP Interface Configuration Register (UPICR) Field Descriptions ...............................................
uPP Interface Idle Value Register (UPIVR) Field Descriptions ...................................................
uPP Threshold Configuration Register (UPTCR) Field Descriptions .............................................
uPP Interrupt Raw Status Register (UPISR) Field Descriptions ..................................................
uPP Interrupt Enabled Status Register (UPIER) Field Descriptions ..............................................
uPP Interrupt Enable Set Register (UPIES) Field Descriptions ...................................................
uPP Interrupt Enable Clear Register (UPIEC) Field Descriptions ................................................
uPP End of Interrupt Register (UPEOI) Field Descriptions ........................................................
uPP DMA Channel I Descriptor 0 Register (UPID0) Field Descriptions .........................................
uPP DMA Channel I Descriptor 1 Register (UPID1) Field Descriptions .........................................
uPP DMA Channel I Descriptor 2 Register (UPID2) Field Descriptions .........................................
uPP DMA Channel I Status 0 Register (UPIS0) Field Descriptions ..............................................
uPP DMA Channel I Status 1 Register (UPIS1) Field Descriptions ..............................................
uPP DMA Channel I Status 2 Register (UPIS2) Field Descriptions ..............................................
uPP DMA Channel Q Descriptor 0 Register (UPQD0) Field Descriptions .......................................
uPP DMA Channel Q Descriptor 1 Register (UPQD1) Field Descriptions .......................................
32-20. Divisor LSB Latch (DLL) Field Descriptions
List of Tables
1548
1548
1549
1550
1556
1556
1557
1559
1560
1564
1566
1567
1568
1572
1572
1573
1574
1575
1577
1579
1580
1581
1583
1585
1587
1589
1589
1590
1590
1591
1591
1592
1593
1593
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
33-31. uPP DMA Channel Q Descriptor 2 Register (UPID2) Field Descriptions ........................................ 1594
...........................................
...........................................
uPP DMA Channel Q Status 2 Register (UPQS2) Field Descriptions ...........................................
USB1.1 Host Controller Registers ....................................................................................
OHCI Revision Number Register (HCREVISION) Field Descriptions ............................................
HC Operating Mode Register (HCCONTROL) Field Descriptions ................................................
HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions .............................
HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions...............................
HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions ...................................
HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions ..................................
HC HCAA Address Register (HCHCCA) Field Descriptions.......................................................
HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions..................................
HC Head Control Register (HCCONTROLHEADED) Field Descriptions ........................................
HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions ................................
HC Head Bulk Register (HCBULKHEADED) Field Descriptions ..................................................
HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions .........................................
HC Head Done Register (HCDONEHEAD) Field Descriptions ...................................................
HC Frame Interval Register (HCFMINTERVAL) Field Descriptions ..............................................
HC Frame Remaining Register (HCFMREMAINING) Field Descriptions ........................................
HC Frame Number Register (HCFMNUMBER) Field Descriptions ...............................................
HC Periodic Start Register (HCPERIODICSTART) Field Descriptions ..........................................
HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions ..................................
HC Root Hub A Register (HCRHDESCRIPTORA) Field Descriptions ...........................................
HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions ...........................................
HC Root Hub Status Register (HCRHSTATUS) Field Descriptions ..............................................
HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions ..........................
HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions ..........................
USB Clock Multiplexing Options.......................................................................................
PHY PLL Clock Frequencies Supported .............................................................................
USB Terminal Functions ...............................................................................................
PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ..............................................
PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ...........................................
PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions .....................................
PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ..................................
Host Packet Descriptor Word 0 (HPD Word 0) ......................................................................
Host Packet Descriptor Word 1 (HPD Word 1) ......................................................................
Host Packet Descriptor Word 2 (HPD Word 2) ......................................................................
Host Packet Descriptor Word 3 (HPD Word 3) ......................................................................
Host Packet Descriptor Word 4 (HPD Word 4) ......................................................................
Host Packet Descriptor Word 5 (HPD Word 5) ......................................................................
Host Packet Descriptor Word 6 (HPD Word 6) ......................................................................
Host Packet Descriptor Word 7 (HPD Word 7) ......................................................................
Host Buffer Descriptor Word 0 (HBD Word 0) .......................................................................
Host Buffer Descriptor Word 1 (HBD Word 1) .......................................................................
Host Buffer Descriptor Word 2 (HBD Word 2) .......................................................................
Host Buffer Descriptor Word 3 (HBD Word 3) .......................................................................
Host Buffer Descriptor Word 4 (HBD Word 4) .......................................................................
Host Buffer Descriptor Word 5 (HBD Word 5) .......................................................................
33-32. uPP DMA Channel Q Status 0 Register (UPQS0) Field Descriptions
1595
33-33. uPP DMA Channel Q Status 1 Register (UPQS1) Field Descriptions
1595
33-34.
1596
34-1.
34-2.
34-3.
34-4.
34-5.
34-6.
34-7.
34-8.
34-9.
34-10.
34-11.
34-12.
34-13.
34-14.
34-15.
34-16.
34-17.
34-18.
34-19.
34-20.
34-21.
34-22.
34-23.
34-24.
35-1.
35-2.
35-3.
35-4.
35-5.
35-6.
35-7.
35-8.
35-9.
35-10.
35-11.
35-12.
35-13.
35-14.
35-15.
35-16.
35-17.
35-18.
35-19.
35-20.
35-21.
SPRUH77C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1603
1604
1605
1606
1607
1608
1609
1610
1610
1611
1611
1612
1612
1613
1613
1614
1614
1615
1615
1616
1617
1618
1619
1621
1626
1626
1627
1642
1643
1645
1647
1668
1668
1669
1669
1669
1669
1670
1670
1671
1671
1671
1671
1672
1672
77
www.ti.com
35-22. Host Buffer Descriptor Word 6 (HBD Word 6) ....................................................................... 1672
35-23. Host Buffer Descriptor Word 7 (HBD Word 7) ....................................................................... 1672
35-24. Teardown Descriptor Word 0 .......................................................................................... 1673
......................................................................................
Allocation of Queues ....................................................................................................
Interrupts Generated by the USB Controller .........................................................................
USB Interrupt Conditions ...............................................................................................
USB Interrupts ...........................................................................................................
Universal Serial Bus OTG (USB0) Registers ........................................................................
Revision Identification Register (REVID) Field Descriptions ......................................................
Control Register (CTRLR) Field Descriptions .......................................................................
Status Register (STATR) Field Descriptions.........................................................................
Emulation Register (EMUR) Field Descriptions .....................................................................
Mode Register (MODE) Field Descriptions ..........................................................................
Auto Request Register (AUTOREQ) Field Descriptions ...........................................................
SRP Fix Time Register (SRPFIXTIME) Field Descriptions ........................................................
Teardown Register (TEARDOWN) Field Descriptions .............................................................
USB Interrupt Source Register (INTSRCR) Field Descriptions ...................................................
USB Interrupt Source Set Register (INTSETR) Field Descriptions ...............................................
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................
USB Interrupt Mask Register (INTMSKR) Field Descriptions .....................................................
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions ...........................................
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions.........................................
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ...................................
USB End of Interrupt Register (EOIR) Field Descriptions .........................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions .......................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions .......................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions .......................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions .......................................
Function Address Register (FADDR) Field Descriptions ...........................................................
Power Management Register (POWER) Field Descriptions .......................................................
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)Field Descriptions ..............
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ..................................
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ...........................................
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions .......................................
Frame Number Register (FRAME) Field Descriptions .............................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)Field Descriptions ........
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions ................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions .....................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ...............
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions .....................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions ................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions................
Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions .....................
Count 0 Register (COUNT0) Field Descriptions ....................................................................
35-25. Teardown Descriptor Words 1-7
35-26.
35-27.
35-28.
35-29.
35-30.
35-31.
35-32.
35-33.
35-34.
35-35.
35-36.
35-37.
35-38.
35-39.
35-40.
35-41.
35-42.
35-43.
35-44.
35-45.
35-46.
35-47.
35-48.
35-49.
35-50.
35-51.
35-52.
35-53.
35-54.
35-55.
35-56.
35-57.
35-58.
35-59.
35-60.
35-61.
35-62.
35-63.
35-64.
35-65.
35-66.
35-67.
35-68.
35-69.
35-70.
78
List of Tables
1673
1674
1688
1688
1691
1704
1711
1711
1712
1712
1713
1715
1716
1716
1717
1718
1719
1720
1721
1722
1723
1724
1724
1725
1725
1726
1726
1727
1728
1729
1730
1730
1731
1732
1732
1733
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
35-71. Receive Count Register (RXCOUNT) Field Descriptions .......................................................... 1742
35-72. Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................ 1743
35-73. Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ............................... 1743
35-74. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................ 1744
35-75. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ...................... 1744
35-76. Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions ............................... 1745
35-77. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions ...................... 1746
35-78. Configuration Data Register (CONFIGDATA) Field Descriptions ................................................. 1747
35-79. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions .............................. 1748
35-80. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions .............................. 1748
35-81. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions .............................. 1749
35-82. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions .............................. 1749
35-83. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions .............................. 1750
35-84. Device Control Register (DEVCTL) Field Descriptions ............................................................. 1750
35-85. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions .................................................... 1751
35-86. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions .................................................... 1751
35-87. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions ........................................... 1752
35-88. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions
...........................................
1752
35-89. Hardware Version Register (HWVERS) Field Descriptions........................................................ 1753
35-90. Transmit Function Address (TXFUNCADDR) Field Descriptions ................................................. 1754
35-91. Transmit Hub Address (TXHUBADDR) Field Descriptions ........................................................ 1754
35-92. Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................. 1754
35-93. Receive Function Address (RXFUNCADDR) Field Descriptions
.................................................
1755
35-94. Receive Hub Address (RXHUBADDR) Field Descriptions......................................................... 1755
35-95. Receive Hub Port (RXHUBPORT) Field Descriptions .............................................................. 1755
35-96. CDMA Revision Identification Register (DMAREVID) Field Descriptions ........................................ 1756
35-97. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ..................... 1756
35-98. CDMA Emulation Control Register (DMAEMU) Field Descriptions ............................................... 1757
.................
CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions ................
Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ............
Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ............
CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions ................................
CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions .....................................
Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions ........................
Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions .......
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions .......
Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions ......
Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ...................
Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions ......
Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions .....................................
Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions .....................................
Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions .....
Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions ..............
Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions ................................
Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions ...............................
35-99. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions
35-100.
35-101.
35-102.
35-103.
35-104.
35-105.
35-106.
35-107.
35-108.
35-109.
35-110.
35-111.
35-112.
35-113.
35-114.
35-115.
35-116.
35-117.
35-118.
35-119.
SPRUH77C – April 2013 – Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
1757
1758
1759
1760
1761
1761
1763
1763
1764
1765
1766
1767
1767
1768
1768
1769
1769
1770
1771
1772
1773
79
www.ti.com
35-120. Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions ............................... 1773
35-121. Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions ............................... 1774
36-1.
Supported Formats on VPIF ........................................................................................... 1779
36-2.
Input and Output Usage Combinations on VPIF .................................................................... 1779
36-3.
Receive Pin Multiplexing Control ...................................................................................... 1780
36-4.
Transmit Pin Multiplexing Control ..................................................................................... 1780
36-5.
Video Port Interface (VPIF) Registers ................................................................................ 1801
36-6.
VPIF Revision ID Register (REVID) Field Descriptions ............................................................ 1804
36-7.
Channel 0 Control Register (C0CTRL) Field Descriptions ......................................................... 1804
36-8.
Channel 1 Control Register (C1CTRL) Field Descriptions ......................................................... 1806
36-9.
Channel 2 Control Register (C2CTRL) Field Descriptions ......................................................... 1807
36-10. Channel 3 Control Register (C3CTRL) Field Descriptions ......................................................... 1809
36-11. Interrupt Enable Register (INTEN) Field Descriptions .............................................................. 1811
36-12. Interrupt Enable Set Register (INTSET) Field Descriptions ....................................................... 1812
36-13. Interrupt Enable Clear Register (INTCLR) Field Descriptions ..................................................... 1813
36-14. Interrupt Status Register (INTSTAT) Field Descriptions ........................................................... 1814
36-15. Interrupt Status Clear Register (INTSTATCLR) Field Descriptions ............................................... 1815
36-16. Emulation Suspend Control Register (EMUCTRL) Field Descriptions ........................................... 1816
36-17. DMA Size Control Register (REQSIZE) Field Descriptions ........................................................ 1816
36-18. Channel n Top Field Luminance Address Register (CnTLUMA) Field Descriptions ........................... 1817
36-19. Channel n Bottom Field Luminance Address Register (CnBLUMA) Field Descriptions ....................... 1817
36-20. Channel n Top Field Chrominance Address Register (CnTCHROMA) Field Descriptions .................... 1818
36-21. Channel n Bottom Field Chrominance Address Register (CnBCHROMA) Field Descriptions ................ 1818
36-22. Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) Field Descriptions ................. 1819
36-23. Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) Field Descriptions ............. 1819
36-24. Channel n Top Field Vertical Ancillary Address Register (CnTVANC) Field Descriptions
....................
1820
36-25. Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register (CnBVANC) Field
Descriptions .............................................................................................................. 1820
36-26. Channel n Image Address Offset Register (CnIMGOFFSET) Field Descriptions
..............................
1821
36-27. Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) Field Descriptions ............ 1821
36-28. Channel n Horizontal Size Configuration Register (CnHCFG) Field Descriptions .............................. 1822
36-29. Channel n Vertical Size Configuration 0 Register (CnVCFG0) Field Descriptions ............................. 1823
36-30. Channel n Vertical Size Configuration 1 Register (CnVCFG1) Field Descriptions ............................. 1823
36-31. Channel n Vertical Size Configuration 2 Register (CnVCFG2) Field Descriptions ............................. 1824
36-32. Channel n Vertical Image Size Register (CnVSIZE) Field Descriptions ......................................... 1824
36-33. Channel n Horizontal Size Configuration Register (CnHCFG) Field Descriptions .............................. 1825
36-34. Channel n Vertical Size Configuration 0 Register (CnVCFG0) Field Descriptions ............................. 1826
36-35. Channel n Vertical Size Configuration 1 Register (CnVCFG1) Field Descriptions ............................. 1826
36-36. Channel n Vertical Size Configuration 2 Register (CnVCFG2) Field Descriptions ............................. 1827
36-37. Channel n Vertical Image Size Register (CnVSIZE) Field Descriptions ......................................... 1827
36-38. Channel n Top Field Horizontal Ancillary Position Register (CnTHANCPOS) Field Descriptions ............ 1828
36-39. Channel n Top Field Horizontal Ancillary Size Register (CnTHANCSIZE) Field Descriptions ................ 1829
36-40. Channel n Bottom Field Horizontal Ancillary Position Register (CnBHANCPOS) Field Descriptions ........ 1830
36-41. Channel n Bottom Field Horizontal Ancillary Size Register (CnBHANCSIZE) Field Descriptions ............ 1831
36-42. Channel n Top Field Vertical Ancillary Position Register (CnTVANCPOS) Field Descriptions ............... 1832
36-43. Channel n Top Field Vertical Ancillary Size Register (CnTVANCSIZE) Field Descriptions ................... 1833
36-44. Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) Field Descriptions ........... 1834
36-45. Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) Field Descriptions ............... 1835
80
List of Tables
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Preface
SPRUH77C – April 2013 – Revised September 2016
Read This First
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components
• ARM subsystem and associated memories
• DSP subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box provided at www.ti.com.
The current documentation that describes related peripherals and other technical collateral, is available in
the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
Code Composer Studio is a trademark of Texas Instruments.
ARM926EJ-S, Jazelle are trademarks of ARM Limited.
SPI is a trademark of Motorola, Inc..
SD is a trademark of SanDisk Corporation.
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Chapter 1
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Overview
Topic
...........................................................................................................................
1.1
1.2
1.3
82
Overview
Page
Introduction ....................................................................................................... 83
DSP Subsystem ................................................................................................. 83
ARM Subsystem................................................................................................. 83
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1.1
Introduction
The OMAP-L138 Applications Processor contains two primary CPU cores: an ARM RISC CPU for
general-purpose processing and systems control; and a powerful DSP to efficiently handle communication
and audio processing tasks. The OMAP-L138 Applications Processor consists of the following primary
components:
• ARM subsystem and associated memories
• DSP subsystem and associated memories
• A set of I/O peripherals
• A powerful DMA subsystem and SDRAM EMIF interface
Block Diagram
A block diagram for the OMAP-L138 Applications Processor is shown in Figure 1-1.
1.2
DSP Subsystem
The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks of
internal memory (L1P, L1D, and L2). The DSP Subsystem chapter describes the DSPSS components.
1.3
ARM Subsystem
The ARM926EJ-S™ 32-bit RISC CPU in the ARM subsystem (ARMSS) acts as the overall system
controller. The ARM CPU performs general system control tasks, such as system initialization,
configuration, power management, user interface, and user command implementation. The ARM
Subsystem chapter describes the ARMSS components and system control functions that the ARM core
performs.
Figure 1-1. OMAP-L138 Applications Processor Block Diagram
ARM Subsystem
DSP Subsystem
ARM926EJ-S CPU
With MMU
C674x™
DSP CPU
JTAG Interface
System Control
PLL/Clock
Generator
w/OSC
Input
Clock(s)
Memory Protection
GeneralPurpose
Timer (x4)
Power/Sleep
Controller
RTC/
32-kHz
OSC
4KB ETB
AET
16KB
16KB
I-Cache D-Cache
Pin
Multiplexing
32KB
L1 Pgm
32KB
L1 RAM
8KB RAM
(Vector Table)
256KB L2 RAM
64KB ROM
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
EDMA3
(x2)
McASP
w/FIFO
Serial Interfaces
McBSP
(x2)
I2C
(x2)
SPI
(x2)
eCAP
(x3)
Video
Parallel
Port
Shared
Memory
Customizable
Interface
LCD
Ctlr
VPIF
uPP
128KB
RAM
PRU
Subsystem
UART
(x3)
Connectivity
Control Timers
eHRPWM
(x2)
Display
USB2.0
OTG Ctlr
PHY
USB1.1
OHCI Ctlr
PHY
EMAC
10/100 MDIO
(MII/RMII)
External Memory Interfaces
HPI
MMC/SD
(8b)
(x2)
SATA
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/mDDR
Memory
Controller
Note: Not all peripherals are available at the same time due to multiplexing.
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DMA Subsystem
The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more
information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter.
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Chapter 2
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ARM Subsystem
Topic
2.1
2.2
2.3
2.4
2.5
2.6
2.7
...........................................................................................................................
Introduction .......................................................................................................
Operating States/Modes ......................................................................................
Processor Status Registers .................................................................................
Exceptions and Exception Vectors .......................................................................
The 16-BIS/32-BIS Concept ..................................................................................
16-BIS/32-BIS Advantages ...................................................................................
Co-Processor 15 (CP15) ......................................................................................
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86
87
87
88
89
89
90
85
Introduction
2.1
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Introduction
This chapter describes the ARM subsystem and its associated memories. The ARM subsystem consists of
the following components:
• ARM926EJ-S™ 32-bit RISC CPU
• 16-KB Instruction cache
• 16-KB Data cache
• Memory Management Unit (MMU)
• Co-Processor 15 (CP15) to control MMU, cache, etc.
• Jazelle™ Java Accelerator
• ARM Internal Memory
– 8 KB RAM
– 64 KB built-in ROM
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer
– Support for 32-bit ARM/16-bit THUMB instruction sets
– Fixed little-endian memory format
– Enhanced DSP instructions
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The
ARM926EJ-S processor targets multi-tasking applications where full memory management, high
performance, low die size, and low power are all important.
The ARM926EJ-S processor supports the 32-bit ARM and the 16-bit THUMB instruction sets, enabling
you to trade off between high performance and high code density. This includes features for efficient
execution of Java byte codes and providing Java performance similar to Just in Time (JIT) Java interpreter
without associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard architecture and provides
a complete high performance subsystem, including the following:
• An ARM926EJ-S integer core
• A Memory Management Unit (MMU)
• Separate instruction and data Advanced Microcontroller Bus Architecture (AHBA) Advanced High
Performance Bus (AHB) bus interfaces
NOTE: There is no TCM memory and interface on this device.
The ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM core also has 8 KB RAM (typically used for vector table) and 64 KB ROM (for boot images)
associated with it. The RAM/ROM locations are not accessible by the DSP or any other master
peripherals. Furthermore, the ARM has DMA and CFG bus master ports via the AHB interface.
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Operating States/Modes
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2.2
Operating States/Modes
The ARM can operate in two states: ARM (32-bit) mode and THUMB (16-bit) mode. You can switch the
ARM926EJ-S processor between ARM mode and THUMB mode using the BX instruction.
The ARM can operate in the following modes:
• User mode (USR): Non-privileged mode, usually for the execution of most application programs.
• Fast interrupt mode (FIQ): Fast interrupt processing
• Interrupt mode (IRQ): Normal interrupt processing
• Supervisor mode (SVC): Protected mode of execution for operating systems
• Abort mode (ABT): Mode of execution after a data abort or a pre-fetch abort
• System mode (SYS): Privileged mode of execution for operating systems
• Undefined mode (UND): Executing an undefined instruction causes the ARM to enter undefined mode.
You can only enter privileged modes (system or supervisor) from other privileged modes.
To enter supervisor mode from user mode, generate a software interrupt (SWI). An IRQ interrupt causes
the processor to enter the IRQ mode. An FIQ interrupt causes the processor to enter the FIQ mode.
Different stacks must be set up for different modes. The stack pointer (SP) automatically changes to the
SP of the mode that was entered.
2.3
Processor Status Registers
The processor status register (PSR) controls the enabling and disabling of interrupts and setting the mode
of operation of the processor. The 8 least-significant bits PSR[7:0] are the control bits of the processor.
PSR[27:8] are reserved bits and PSR[31:28] are status registers. The details of the control bits are:
• Bit 7 - I bit: Disable IRQ (I =1) or enable IRQ (I = 0)
• Bit 6 - F bit: Disable FIQ (F = 1) or enable FIQ (F = 0)
• Bit 5 - T bit: Controls whether the processor is in thumb mode (T = 1) or ARM mode (T = 0)
• Bits 4:0 Mode: Controls the mode of operation of the processor
– PSR [4:0] = 10000 : User mode
– PSR [4:0] = 10001 : FIQ mode
– PSR [4:0] = 10010 : IRQ mode
– PSR [4:0] = 10011 : Supervisor mode
– PSR [4:0] = 10111 : Abort mode
– PSR [4:0] = 11011 : Undefined mode
– PSR [4:0] = 11111 : System mode
Status bits show the result of the most recent ALU operation. The details of status bits are:
• Bit 31 - N bit: Negative or less than
• Bit 30 - Z bit: Zero
• Bit 29 - C bit: Carry or borrow
• Bit 28 - V bit: Overflow or underflow
NOTE: See the Programmer’s Model of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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Exceptions and Exception Vectors
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Exceptions and Exception Vectors
Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that
occur in an ARM system are given below:
• Reset exception: processor reset
• FIQ interrupt: fast interrupt
• IRQ interrupt: normal interrupt
• Abort exception: abort indicates that the current memory access could not be completed. The abort
could be a pre-fetch abort or a data abort.
• SWI interrupt: use software interrupt to enter supervisor mode.
• Undefined exception: occurs when the processor executes an undefined instruction
The exceptions in the order of highest priority to lowest priority are: reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction, and SWI. SWI and undefined instruction have the same priority. The ARM is
configured with the VINITHI signal set high (VINITHI = 1), such that the vector table is located at address
FFFF 0000h. This address maps to the beginning of the ARM local RAM (8 KB).
NOTE: The VINITHI signal is configurable by way of the register setting in CP15. However, it is not
recommended to set VINITHI = 0, as the device has no physical memory in the 0000 0000h
address region.
The default vector table is shown in Table 2-1.
Table 2-1. Exception Vector Table for ARM
Vector Offset Address
88
Exception
Mode on entry
I Bit State on Entry
F Bit State on Entry
0h
Reset
Supervisor
Set
Set
4h
Undefined instruction
Undefined
Set
Unchanged
8h
Software interrupt
Supervisor
Set
Unchanged
Ch
Pre-fetch abort
Abort
Set
Unchanged
10h
Data abort
Abort
Set
Unchanged
14h
Reserved
—
—
—
18h
IRQ
IRQ
Set
Unchanged
1Ch
FIQ
FIQ
Set
Set
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The 16-BIS/32-BIS Concept
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2.5
The 16-BIS/32-BIS Concept
The key idea behind 16-BIS is that of a super-reduced instruction set. Essentially, the ARM926EJ
processor has two instruction sets:
• ARM mode or 32-BIS: the standard 32-bit instruction set
• THUMB mode or 16-BIS: a 16-bit instruction set
The 16-bit instruction length (16-BIS) allows the 16-BIS to approach twice the density of standard 32-BIS
code while retaining most of the 32-BIS’s performance advantage over a traditional 16-bit processor using
16-bit registers. This is possible because 16-BIS code operates on the same 32-bit register set as 32-BIS
code. 16-bit code can provide up to 65% of the code size of the 32-bit code and 160% of the performance
of an equivalent 32-BIS processor connected to a 16-bit memory system.
2.6
16-BIS/32-BIS Advantages
16-bit instructions operate with the standard 32-bit register configuration, allowing excellent interoperability between 32-BIS and 16-BIS states. Each 16-bit instruction has a corresponding 32-bit
instruction with the same effect on the processor model. The major advantage of a 32-bit architecture over
a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a
large address space efficiently. When processing 32-bit data, a 16-bit architecture takes at least two
instructions to perform the same task as a single 32-bit instruction. However, not all of the code in a
program processes 32-bit data (for example, code that performs character string handling), and some
instructions (like branches) do not process any data at all. If a 16-bit architecture only has 16-bit
instructions, and a 32-bit architecture only has 32-bit instructions, then the 16-bit architecture has better
code density overall, and has better than one half of the performance of the 32-bit architecture. Clearly,
32-bit performance comes at the cost of code density. The 16-bit instruction breaks this constraint by
implementing a 16-bit instruction length on a 32-bit architecture, making the processing of 32-bit data
efficient with compact instruction coding. This provides far better performance than a 16-bit architecture,
with better code density than a 32-bit architecture. The 16-BIS also has a major advantage over other 32bit architectures with 16-bit instructions. The advantage is the ability to switch back to full 32-bit code and
execute at full speed. Thus, critical loops for applications such as fast interrupts and DSP algorithms can
be coded using the full 32-BIS and linked with 16-BIS code. The overhead of switching from 16-bit code to
32-bit code is folded into sub-routine entry time. Various portions of a system can be optimized for speed
or for code density by switching between 16-BIS and 32-BIS execution, as appropriate.
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Co-Processor 15 (CP15)
2.7
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Co-Processor 15 (CP15)
The system control coprocessor (CP15) is used to configure and control instruction and data caches,
Tightly-Coupled Memories (TCMs), Memory Management Units (MMUs), and many system functions. The
CP15 registers are only accessible with MRC and MCR instructions by the ARM in a privileged mode like
supervisor mode or system mode.
2.7.1 Addresses in an ARM926EJ-S System
Three different types of addresses exist in an ARM926EJ-S system. They are listed in Table 2-2.
Table 2-2. Different Address Types in ARM System
Domain
ARM9EJ-S
Caches and MMU
TCM and AMBA Bus
Address type
Virtual Address (VA)
Modified Virtual Address (MVA)
Physical Address (PA)
An example of the address manipulation that occurs when the ARM9EJ-S core requests an instruction is
shown in Example 2-1
Example 2-1. Address Manipulation
The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated to the MVA. The Instruction Cache (Icache) and Memory Management Unit (MMU) detect
the MVA.
If the protection check carried out by the MMU on the MVA does not abort and the MVA tag is in the Icache,
the instruction data is returned to the ARM9EJ-S core.
If the protection check carried out by the MMU on the MVA does not abort, and the MVA tag is not in the
cache, then the MMU translates the MVA to produce the PA.
NOTE: See the Programmers Model of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
2.7.2 Memory Management Unit (MMU)
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as
SymbianOS, WindowsCE, and Linux. A single set of two level page tables stored in main memory controls
the address translation, permission checks, and memory region attributes for both data and instruction
accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information
held in the page tables.
The MMU features are as follows:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access protection scheme.
• Mapping sizes are 1 MB (sections), 64 KB (large pages), 4 KB (small pages) and 1 KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10
NOTE: See the Memory Management Unit of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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2.7.3 Caches and Write Buffer
The ARM926EJ-S processor includes:
• An Instruction cache (Icache)
• A Data cache (Dcache)
• A write buffer
The size of the data cache is 16 KB, instruction cache is 16 KB, and write buffer is 17 bytes.
The caches have the following features:
• Virtual index, virtual tag, addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32 bytes per line), and two
dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
• Perform critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown and controlling cache pollution.
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the
TAGRAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
• Cache maintenance operations to provide efficient invalidation of the following:
– The entire Dcache or Icache
– Regions of the Dcache or Icache
– The entire Dcache
– Regions of virtual memory
• They also provide operations for efficient cleaning and invalidation of the following:
– The entire Dcache
– Regions of the Dcache
– Regions of virtual memory
The write buffer is used for all writes to a non-cachable bufferable region, write-through region, and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines.
The main write buffer has a 16-word data buffer and a four-address buffer.
The Dcache write-back has eight data word entries and a single address entry.
The MCR drain write buffer enables both write buffers to be drained under software control.
The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be
put into a low power state until an interrupt occurs.
NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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Chapter 3
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DSP Subsystem
Topic
3.1
3.2
3.3
3.4
92
...........................................................................................................................
Introduction .......................................................................................................
TMS320C674x Megamodule .................................................................................
Memory Map ......................................................................................................
Advanced Event Triggering (AET) ........................................................................
DSP Subsystem
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99
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Introduction
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3.1
Introduction
The DSP subsystem (Figure 3-1) includes TI’s standard TMS320C674x megamodule and several blocks
of internal memory (L1P, L1D, and L2). This chapter provides an overview of the DSP subsystem and the
following considerations associated with it:
• Memory mapping
• Interrupts
• Power management
For more information on the TMS320C674x megamodule, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5), the TMS320C674x DSP CPU and Instruction Set Reference Guide
(SPRUFE8), and the TMS320C674x DSP Cache User’s Guide (SPRUG82).
Figure 3-1. TMS320C674x Megamodule Block Diagram
32K bytes
L1P RAM/
cache
256K bytes
L2 RAM
256
256
1M bytes
L2 ROM
256
256
Cache control
Memory protect
Bandwidth Mgmt
Cache control
Memory protect
Bandwidth Mgmt
L1P
256
256
256
256
Instruction fetch
Power down
Interrupt
Controller
C674x
Fixed/floating point CPU
Register
file A
Register
file B
64
64
Bandwidth Mgmt
Memory protect
Cache control
L2
IDMA
256
Port
EMC
L1D
MDMA Port
8x32
64
32K bytes
L1D RAM/
cache
64
32
Configuration
peripherals
bus
SDMA Port
64
64
High performance
switch fabric
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TMS320C674x Megamodule
The C674x megamodule (Figure 3-1) consists of the following components:
• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)
For more information about each of these controllers, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5).
3.2.1 Internal Memory Controllers
The C674x megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory (L1) is split into separate program memory (L1P memory) and data
memory (L1D memory). L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also
be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory
locations. The internal direct memory access controller (IDMA) manages DMA among the L1P, L1D, and
L2 memories.
3.2.2 Internal Peripherals
The C674x megamodule includes the following internal peripherals:
• DSP interrupt controller (INTC)
• DSP power-down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA) controller
This section briefly describes the INTC, PDC, BWM, and IDMA controller. For more information on these
internal peripherals, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
3.2.2.1
Interrupt Controller (INTC)
The C674x megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps DSP device events to 12 CPU interrupts. All DSP device events are listed in Table 3-1. The INTC is
fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
The interrupt events listed in Table 3-1 are for the DSP interrupt controller (INTC) only. For the ARM
interrupt controller (AINTC) event mappings, see the ARM Interrupt Controller (AINTC) chapter.
Table 3-1. DSP Interrupt Map
Event
94
Interrupt Name
Source
0
EVT0
C674x Interrupt Control 0
1
EVT1
C674x Interrupt Control 1
2
EVT2
C674x Interrupt Control 2
3
EVT3
C674x Interrupt Control 3
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Table 3-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
4
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
5
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
6
PRU_EVTOUT0
PRUSS Interrupt
7
EHRPWM0
HiResTimer/PWM0 Interrupt
8
EDMA3_0_CC0_INT1
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
9
EMU-DTDMA
C674x-ECM
10
EHRPWM0TZ
HiResTimer/PWM0 Trip Zone Interrupt
11
EMU-RTDXRX
C674x-RTDX
12
EMU-RTDXTX
C674x-RTDX
13
IDMAINT0
C674x-EMC
14
IDMAINT1
C674x-EMC
15
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
16
MMCSD0_INT1
MMCSD0 SDIO Interrupt
17
PRU_EVTOUT1
PRUSS Interrupt
18
EHRPWM1
HiResTimer/PWM1 Interrupt
19
USB0_INT
USB0 (USB2.0) Interrupt
20
USB1_HCINT
USB1 (USB1.1) OHCI Host Controller Interrupt
21
USB1_R/WAKEUP
USB1 (USB1.1) Remote Wakeup Interrupt
22
PRU_EVTOUT2
PRUSS Interrupt
23
EHRPWM1TZ
HiResTimer/PWM1 Trip Zone Interrupt
24
SATA_INT
SATA Controller Interrupt
25
T64P2_TINTALL
Timer64P2 Combined Interrupt (TINT12 and TINT34)
26
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
27
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
28
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
29
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
30
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
31
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
32
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
33
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
34
UHPI_DSPINT
HPI DSP Interrupt
35
PRU_EVTOUT3
PRUSS Interrupt
36
IIC0_INT
I2C0 Interrupt
37
SPI0_INT
SPI0 Interrupt
38
UART0_INT
UART0 Interrupt
39
PRU_EVTOUT5
PRUSS Interrupt
40
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
41
GPIO_B1INT
GPIO Bank 1 Interrupt
42
IIC1_INT
I2C1 Interrupt
43
SPI1_INT
SPI1 Interrupt
44
PRU_EVTOUT6
PRUSS Interrupt
45
ECAP0
ECAP0 Interrupt
46
UART_INT1
UART1 Interrupt
47
ECAP1
ECAP1 Interrupt
48
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
49
GPIO_B2INT
GPIO Bank 2 Interrupt
50
PRU_EVTOUT7
PRUSS Interrupt
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Table 3-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
51
ECAP2
ECAP2 Interrupt
52
GPIO_B3INT
GPIO Bank 3 Interrupt
53
MMCSD1_INT1
MMCSD1 SDIO Interrupt
54
GPIO_B4INT
GPIO Bank 4 Interrupt
55
EMIFA_INT
EMIFA Interrupt
56
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrrupt
57
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrrupt
58
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrrupt
59
GPIO_B5INT
GPIO Bank 5 Interrupt
60
DDR2_MEMERR
DDR2 Memory Error Interrupt
61
MCASP0_INT
McASP0 Combined RX/TX Interrupt
62
GPIO_B6INT
GPIO Bank 6 Interrupt
63
RTC_IRQS
RTC Combined Interrupt
64
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
65
GPIO_B0INT
GPIO Bank 0 Interrupt
66
PRU_EVTOUT4
PRUSS Interrupt
67
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
68
MMCSD1_INT0
MMCSD1 MMC/SD Interrupt
69
UART2_INT
UART2 Interrupt
70
PSC0_ALLINT
PSC0
71
PSC1_ALLINT
PSC1
72
GPIO_B7INT
GPIO Bank 7 Interrupt
73
LCDC_INT
LCD Controller Interrupt
74
PROTERR
SYSCFG Protection Shared Interrupt
75
GPIO_B8INT
GPIO Bank 8 Interrupt
76-77
—
Reserved
78
T64P2_CMPINT0
Timer64P2 - Compare Interrupt 0
79
T64P2_CMPINT1
Timer64P2 - Compare Interrupt 1
80
T64P2_CMPINT2
Timer64P2 - Compare Interrupt 2
81
T64P2_CMPINT3
Timer64P2 - Compare Interrupt 3
82
T64P2_CMPINT4
Timer64P2 - Compare Interrupt 4
83
T64P2_CMPINT5
Timer64P2 - Compare Interrupt 5
84
T64P2_CMPINT6
Timer64P2 - Compare Interrupt 6
85
T64P2_CMPINT7
Timer64P2 - Compare Interrupt 7
86
T64P3_TINTALL
Timer64P3 Combined Interrupt (TINT12 and TINT34)
87
MCBSP0_RINT
McBSP0 Receive Interrupt
88
MCBSP0_XINT
McBSP0 Transmit Interrupt
89
MCBSP1_RINT
McBSP1 Receive Interrupt
90
MCBSP1_XINT
McBSP1 Transmit Interrupt
91
EDMA3_1_CC0_INT1
EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
92
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrrupt
93
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrrupt
94
UPP_INT
uPP Combined Interrupt
95
VPIF_INT
VPIF Combined Interrupt
96
INTERR
C674x-Interrupt Control
97
EMC_IDMAERR
C674x-EMC
—
Reserved
98-112
96
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Table 3-1. DSP Interrupt Map (continued)
Event
113
114-115
Interrupt Name
Source
PMC_ED
C674x-PMC
—
Reserved
116
UMC_ED1
C674x-UMC
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
C674x-SYS
120
PMC_CMPA
C674x-PMC
121
PMC_CMPA
C674x-PMC
122
DMC_CMPA
C674x-DMC
123
DMC_CMPA
C674x-DMC
124
UMC_CMPA
C674x-UMC
125
UMC_CMPA
C674x-UMC
126
EMC_CMPA
C674x-EMC
127
EMC_BUSERR
C674x-EMC
3.2.2.1.1 Interrupt Controller Registers
For more information on the DSP interrupt controller (INTC) registers, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
3.2.2.1.2 NMI Interrupt
In addition to the interrupts listed in Table 3-1, the DSP also supports a special interrupt that behaves
more like an exception, non-maskable interrupt (NMI). The NMI interrupt is controlled by two registers in
the System Configuration Module, the chip signal register (CHIPSIG) and the chip signal clear register
(CHIPSIG_CLR).
The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. The NMI interrupt is cleared
by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. For more information on CHIPSIG and
CHIPSIG_CLR, see the System Configuration (SYSCFG) Module chapter.
3.2.2.2
Power-Down Controller (PDC)
The C674x megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C674x megamodule and internal memories of the DSP subsystem:
• C674x CPU
• Level 1 program memory controller (PMC)
• Level 1 data memory controller (DMC)
• Level 2 unified memory controller (UMC)
• Extended memory controller (EMC)
• Internal direct memory access (IDMA) controller
• L1P memory
• L1D memory
• L2 memory
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This device supports the static power-down feature from the C674x megamodule. The TMS320C674x
DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail.
• Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and
all internal memories immediately upon command from software.
Static power-down (clock gating) affects all components of the C674x megamodule and all internal
memories. Software can initiate static power-down by way of a register bit in the power-down controller
command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
3.2.2.3
Bandwidth Manager (BWM)
The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA3-initiated DMA transfers (and resulting coherency operations)
• DSP subsystem IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of the C674x megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA3, DSP subsystem IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The
programmable priority level has a single meaning throughout the system. There are a total of nine priority
levels, where priority zero is the highest priority and priority eight is the lowest priority. When requests for
a single resource contend, access is granted to the highest-priority requestor. When the contention occurs
for multiple successive cycles, a contention counter assures that the lower-priority requestor gets access
to the resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1
represents a transfer whose priority has been increased due to expiration of the contention counter or a
transfer that is fixed as the highest-priority transfer to a given resource.
3.2.2.4
Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) port. The IDMA cannot
transfer data to or from the internal DSP memory-mapped register space. The IDMA is fully described in
the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
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3.3
Memory Map
Refer to your device-specific data manual for the addresses of the memory-map registers.
3.3.1 DSP Internal Memory
See the System Memory chapter for a description of the DSP internal memory.
3.3.2 External Memory
See the System Interconnect chapter and the System Memory chapter for a description of the additional
memory and peripherals that the DSP has access to.
3.4
Advanced Event Triggering (AET)
The C674x megamodule supports advanced event triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides
the following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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System Interconnect
Topic
4.1
4.2
100
...........................................................................................................................
Page
Introduction ..................................................................................................... 101
System Interconnect Block Diagram ................................................................... 102
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Introduction
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4.1
Introduction
The DSP, the ARM, the Programmable Real-Time Unit (PRU) subsystem, the EDMA3 transfer controllers,
and the device peripherals are interconnected through a switch fabric architecture (see Section 4.2). The
switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs
establish low-latency connectivity between master peripherals and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Through the SCRs, the DSP can send data to the EMIF without affecting a
data transfer between a device peripheral and internal shared memory. Bridges are mainly used to
perform bus-width conversion as well as bus operating frequency conversion.
The DSP, the ARM, the PRU subsystem, the EDMA3 transfer controllers, and the various device
peripherals can be classified into two categories: master peripherals and slave peripherals.
Master peripherals are typically capable of initiating read and write transfers in the system and do not rely
on the EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include
the DSP, the ARM, the EDMA3 transfer controllers, EMAC, HPI, LCDC, uPP, SATA, VPIF, PRU
subsystem, and USB DMAs. Not all master peripherals may connect to all slave peripherals. The
supported connections are designated by an X in Table 4-1.
Table 4-1. OMAP-L138 Applications Processor System Interconnect Matrix
Masters
Master
Slaves
Default
Priority
ARM
ROM,
AINTC
ARM
RAM
DSP
SDMA
EMIFA
DDR2/
mDDR
128K
RAM
EDMA3_0_
TC0/TC1
EDMA3_1_
TC0
Peripheral
Group (1)
EDMA3_0_CC0
0
EDMA3_1_CC0
0
X
EDMA3_0_TC0
0
X
X
X
X
X
X
X
EDMA3_0_TC1
0
X
X
X
X
X
X
X
PRU0
0
X
X
X
X
X
X
X
PRU1
0
X
X
X
X
X
X
X
ARM I
2
X
X
X
X
X
X
ARM D
2
X
X
X
X
X
X
X
X
X
DSP CFG
2
X
X
X
DSP MDMA
2
EDMA3_1_TC0
4
X
X
X
EMAC
4
SATA
uPP
X
X
X
X
X
X
X
X
X
X
X
X
X
4
X
X
X
X
4
X
X
X
X
USB1.1
4
X
X
X
X
USB2.0
4
X
X
X
X
VPIF
4
X
X
X
X
LCDC
5
HPI
6
(1)
(2)
X
X
X
X
X
X (2)
Peripheral group: SYSCFG, EMAC, eCAP0, eCAP1, eCAP2, eHRPWM0, eHRPWM1, GPIO, I2C0, I2C1, LCDC, McASP0,
McBSP0, McBSP1, MDIO, MMC/SD0, MMC/SD1, PLLC0, PLLC1, PRU RAM0, PRU RAM1, PRU Config, PSC0, PSC1, RTC,
SPI0, SPI1, TIMER64P0, TIMER64P1, TIMER64P2, TIMER64P3, EDMA3_0_CC0, EDMA3_1_CC0, UART0, UART1, UART2,
HPI, USB0 (USB2.0), USB1 (USB1.1), uPP, SATA, VPIF.
The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level.
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System Interconnect Block Diagram
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System Interconnect Block Diagram
Figure 4-1 shows a system interconnect block diagram.
Figure 4-1. System Interconnect Block Diagram
HPI
USB0 VBUSP
DSP SDMA (L1D/L2)
USB0 CDMA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
EMAC
SCR F1
USB1
SCR F0
BR F0
BR F6
EDMA3_0_TC1
EDMA3_1_TC0
128 KB
Shared RAM
MPU1
SCR F3
BR F7
LCDC
DSP MDMA
EDMA3_0_TC0
SCR F4
BR F1
rd
MPU2
DDR2/mDDR
EDMA3_1_CC0
wr
EDMA3_1_CC0
SCR1
EDMA3_1_TC0
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
rd
USB0 Cfg
wr
HPI
PSC0
rd
SCR5
wr
LCDC
SCR F5
PLLC0
uPP
SYSCFG0
VPIF
uPP DMA
VPIF DMA0
SCR F2
VPIF DMA1
SATA
SATA
BR5
MMC/SD1
BR F2
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 2 Clock Domain
SYSCFG1
Clock Domain: SYSCLK6 [CPU/1 Synchronous]
ARM-I
BR3
BR1
SCR0
ARM-D
EMAC
Timer64P0
BR4
SCR6
BR2
EMAC MDIO
Timer64P1
USB1 Cfg
I2C0
SCR F6
RTC
BR0
BR6
GPIO
PSC1
I2C1
BR8
PLLC1
Async 1 Clock Domain
AINTC
BR7
BR F3
EMIFA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 3 [PLL1] Clock Domain
PRU CFG
DSP CFG
McBSP0
ARM ROM
PRU0
McBSP1
ARM RAM
PRU1
BR F4
SCR F7
UART1
UART2
SCR2
MMC/SD0
SCR4
McASP0
SPI0
UART0
Legend:
32-bit BUS
64-bit BUS
eHRPWM0
EDMA3_0_TC0
IP Module
Synchronous Bridge
Asynchronous Bridge
SCR
eHRPWM1
EDMA3_0_TC1
Timer64P2
BR F5
SCR F8
Timer64P3
eCAP0
eCAP1
Paths with dashed lines cross the subchip boundary
eCAP2
SPI1
EDMA3_0_CC0
102
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Chapter 5
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System Memory
Topic
...........................................................................................................................
5.1
5.2
5.3
5.4
Introduction .....................................................................................................
ARM Memories .................................................................................................
DSP Memories..................................................................................................
Peripherals ......................................................................................................
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104
104
105
103
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Introduction
This device has multiple on-chip/off-chip memories and several external device interfaces associated with
its two CPUs and various subsystems. To help simplify software development, a unified memory-map is
used wherever possible to maintain a consistent view of device resources across all masters.
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
5.2
ARM Memories
The configuration for the ARM internal memory is:
• 8 KB ARM local RAM
• 64 KB ARM local ROM
• 16 KB Instruction Cache and 16 KB Data cache
The ARM RAM/ROM are only accessible by ARM and PRU0.
5.3
DSP Memories
The DSP internal memories are accessible by the ARM and other master peripherals (as dictated by the
connectivity matrix) via the system interconnect through the DSP SDMA port.
The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
• L1P memory includes 32 KB of RAM. The DSP program memory controller (PMC) allows you to
configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache
sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB
cache.
• L1D memory includes 32 KB of RAM. The DSP data memory controller (DMC) allows you to configure
part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB,
8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB cache.
• L2 memory includes 256 KB of RAM. The DSP unified memory controller (UMC) allows you to
configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0
KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, or 256 KB of the 256 KB of RAM. The default
configuration is 256 KB normal RAM.
• L2 memory also includes 1024 KB of ROM.
Shared RAM Memory
This device also offers an on-chip 128-KB shared single-port RAM, apart from the ARM and the DSP
internal memories. This shared RAM is accessible by both the ARM and the DSP, and is also accessible
by several master peripherals. Writes to this RAM by all masters is atomic.
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIF:
– 8/16-bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM,
NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space
• DDR2/mDDR memory controller:
– 16-bit DDR2 with up to 256-MB memory address space
– 16-bit mDDR with up to 256-MB memory address space
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Internal Peripherals
The following peripherals are internal to the DSP subsystem and are only accessible to the DSP:
• DSP interrupt controller (INTC)
• DSP power down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA)
For more information on the internal peripherals, see the TMS320C674x DSP Megamodule Reference
Guide (SPRUFK5).
The peripheral only accessible by the ARM is the ARM interrupt controller (AINTC). For more information
on the AINTC, see the ARM Interrupt Controller (AINTC) chapter.
5.4
Peripherals
The ARM and the DSP have access to all peripherals. This also includes system modules like the PLL
controller (PLLC), the power and sleep controller (PSC), and the system configuration module (SYSCFG).
See the device-specific data manual for the complete list of peripherals supported on your device.
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Memory Protection Unit (MPU)
Topic
6.1
6.2
6.3
106
...........................................................................................................................
Page
Introduction ..................................................................................................... 107
Architecture ..................................................................................................... 108
MPU Registers ................................................................................................. 113
Memory Protection Unit (MPU)
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6.1
Introduction
This device supports two memory protection units (MPU1 and MPU2). MPU1 supports the 128KB shared
RAM and MPU2 supports the DDR2/mDDR SDRAM.
6.1.1 Purpose of the MPU
The memory protection unit (MPU) is provided to manage access to memory. The MPU allows you to
define multiple ranges and limit access to system masters based on their privilege ID. The MPU can
record a detected fault, or invalid access, and notify the system through an interrupt.
6.1.2 Features
The MPU supports the following features:
• Supports multiple programmable address ranges
• Supports 0 or 1 fixed range
• Supports read, write, and execute access privileges
• Supports privilege ID associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• Supports L1/L2 cache accesses
• Supports protection of its own registers
6.1.3 Block Diagram
Figure 6-1 shows a block diagram of the MPU. An access to a protected memory must pass through the
MPU. During an access, the MPU checks the memory address on the input data bus against fixed and
programmable ranges. If allowed, the transfer is passed unmodified to the output data bus. If the transfer
fails the protection check then the MPU does not pass the transfer to the output bus but rather services
the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor
as well as generating an interrupt about the fault. The MPU generates two interrupts: an address error
interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).
Figure 6-1. MPU Block Diagram
MPU
Input
Data
Bus
Protection
Checks
Output
Data
Bus
MPU_ADDR_ERR_INT
MMRs
MPU_PROT_ERR_INT
MPU Register Bus
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6.1.4 MPU Default Configuration
Two MPUs are supported on the device, one for the 128KB shared RAM and one for the DDR2/mDDR
SDRAM. Table 6-1 shows the memory regions protected by each MPU. Table 6-2 shows the configuration
of each MPU.
Table 6-1. MPU Memory Regions
Memory Region
Unit
Memory Protection
Start Address
End Address
MPU1
128KB Shared RAM
8000 0000h
8001 FFFFh
MPU2
DDR2/mDDR SDRAM
C000 0000h
DFFF FFFFh
Table 6-2. MPU Default Configuration
Setting
MPU1
MPU2
Assume allowed
Assume allowed
Number of allowed IDs supported
12
12
Number of fixed ranges supported
1
0
Default permission
Number of programmable ranges supported
Compare width
6.2
6
12
1 KB granularity
64 KB granularity
Architecture
6.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
ARM and DSP CPU instruction and data accesses have a privilege level associated with them. The
privilege level is inherited from the code running on the CPU. See the TMS320C674x DSP CPU and
Instruction Set Reference Guide (SPRUFE8) and the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more details on privilege levels of the DSP
and ARM CPU.
Although master peripherals like the HPI do not execute code, they still have a privilege level associated
with them. Unlike the ARM and DSP CPU, the privilege level of this peripheral is fixed.
Table 6-3 shows the privilege ID of the CPU and every mastering peripheral. Table 6-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.
Table 6-3. Device Master Settings
Master
Privilege Level
Access Type
EDMA3_0_CC0
Inherited
Inherited
DMA
EDMA3_0_TC0 and EDMA3_0_TC1
Inherited
Inherited
DMA
EDMA3_1_CC0
Inherited
Inherited
DMA
EDMA3_1_TC0
Inherited
Inherited
DMA
Software dependant
Instruction
ARM (instruction access)
108 Memory Protection Unit (MPU)
Privilege ID
0
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Table 6-3. Device Master Settings (continued)
Master
Privilege Level
Access Type
ARM (data access)
Privilege ID
0
Software dependant
Data
DSP
1
Software dependant
Software dependant
PRU0/PRU1
2
Supervisor
DMA
HPI
3
User
DMA
EMAC
4
Supervisor
Data/DMA
USB1.1
5
Supervisor
DMA
USB2.0
6
Supervisor
DMA
LCD Controller
7
Supervisor
DMA
uPP
8
Supervisor
DMA
SATA
9
Supervisor
DMA
VPIF DMA0
10
Supervisor
DMA
VPIF DMA1
11
Supervisor
DMA
6.2.2 Memory Protection Ranges
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory. One of the programmable
address ranges could be used to detect accesses to this unpopulated memory.
The MPU divides its assigned memory into address ranges. Each MPU can support one fixed address
range and multiple programmable address ranges. The fixed address range is configured to an exact
address. The programmable address range allows software to program the start and end addresses.
Each address range has the following set of registers:
• Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending
address of the address range.
• Memory protection page attribute register (MPPA): Use to program the permission settings of the
address range.
It is allowed to configure ranges such that they overlap each other. In this case, all the overlapped ranges
must allow the access, otherwise the access is not allowed. The final permissions given to the access are
the lowest of each type of permission from any hit range.
Addresses not covered by a range are either allowed or disallowed based on the configuration of the
MPU. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the
ASSUME_ALLOWED bit in the configuration register (CONFIG).
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6.2.3 Permission Structures
The MPU defines a per-range permission structure with three permission fields in a 32-bit permission
entry. Figure 6-2 shows the structure of a permission entry.
Figure 6-2. Permission Fields
31
22
21
20
Reserved
15
14
13
12
11
10
9
8
Allowed IDs
AID5
AID4
6.2.3.1
AID3
AID2
6
AID11
AID10
5
4
Reserved
AID1
AID0
19
18
17
16
Allowed IDs
AIX
AID9
AID8
AID7
AID6
3
2
1
0
UW
UX
Access Types
SR
SW
SX
UR
Requestor-ID Based Access Controls
Each master on the device has an N-bit code associated with it that identifies it for privilege purposes.
This privilege ID accompanies all memory accesses made on behalf of that master. That is, when a
master triggers a memory access command, the privilege ID will be carried alongside the command.
Each memory protection range has an allowed ID (AID) field associated with it that indicates which
requestors may access the given address range. The MPU maps the privilege IDs of all the possible
requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA).
• AID0 through AID11 are used to specify the allowed privilege IDs.
• An additional allowed ID bit, AIDX, captures access made by all privilege IDs not covered by AID0
through AID11.
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies
access to the corresponding requestor.
6.2.3.2
Request-Type Based Permissions
The memory protection model defines three fundamental functional access types: read, write, and
execute. Read and write refer to data accesses -- accesses originating via the load/store units on the CPU
or via a master peripheral. Execute refers to accesses associated with an instruction fetch.
The memory protection model allows controlling read, write, and execute permissions independently for
both user and supervisor mode. This results in six permission bits, listed in Table 6-4. For each bit, a 1
permits the access type and a 0 denies access. For example, UX = 1 means that User Mode may execute
from the given page. The memory protection unit allows you to specify all six of these bits separately; 64
different encodings are permitted altogether, although programs might not use all of them.
Table 6-4. Request Type Access Controls
110
Bit
Field
Description
5
SR
Supervisor may read
4
SW
Supervisor may write
3
SX
Supervisor may execute
2
UR
User may read
1
UW
User may write
0
UX
User may execute
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6.2.4 Protection Check
During a memory access, the MPU checks if the address range of the input transfer overlaps one of the
address ranges. When the input transfer address is within a range the transfer parameters are checked
against the address range permissions.
The MPU first checks the transfers privilege ID against the AID settings. If the AID bit is 0, then the range
will not be checked; if the AID bit is 1, then the transfer parameters are checked against the memory
protection page attribute register (MPPA) values to detect an allowed access.
For non-debug accesses, the read, write, and execute permissions are also checked. There is a set of
permissions for supervisor mode and a set for user mode. For supervisor mode accesses, the SR, SW,
and SX bits are checked. For user mode accesses, the UR, UW, and UX bits are checked.
If the transfer address range does not match any address range then the transfer is either allowed or
disallowed based on the configuration of the MPU. The MPU can be configured for assumed allowed or
assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register
(CONFIG).
In the case that a transfer spans multiple address ranges, all the overlapped ranges must allow the
access, otherwise the access is not allowed. The final permissions given to the access are the lowest of
each type of permission from any hit range. Therefore, if a transfer matches 2 ranges, one that is RW and
one that is RX, then the final permission is just R.
The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses, see
Section 6.2.5 for more details.
6.2.5 DSP L1/L2 Cache Controller Accesses
A memory read access that originates from the DSP L1/L2 cache is treated differently to allow memory
protection to be enforced by the DSP level. This is because a subsequent memory access that hits in the
cache does not pass through the MPU. Instead the memory access is serviced directly by the L1/L2
memory controllers.
During a cache memory read, the permission settings stored in the memory protection page attribute
registers (MPPA) are passed to the L1/L2 memory controllers along with the read data. The permissions
settings returned by the MPU are taken from MPPA that covers the address range of the original
request—only the SR, SW, SX, UR, UW, and UX bits are passed. If the request address is covered by
multiple address ranges, then the returned value is the logical-AND of all MPPA permissions. If the
transfer address range is not covered by an address range then the transfer is either allowed or
disallowed based on the configuration of the MPU.
6.2.6 MPU Register Protection
Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page
attribute registers (MPPA) is also protected. All non-debug writes must be by a supervisor entity. A
protection fault can occur from a register write with invalid permissions and this triggers an interrupt just
like a memory access.
Faults are not recorded (nor interrupts generated) for debug accesses.
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6.2.7 Invalid Accesses and Exceptions
When a transfer fails the protection check, the MPU does not pass the transfer to the output bus. The
MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.
The behavior of the MPU depends on whether the access was a read or a write:
• For a read: The MPU returns 0s, a permission value is 0 (no access allowed), a protection error status.
• For a write: The MPU receives all the write data and returns a protection error status.
The MPU captures system faults due to addressing or protection violations in its registers. The MPU can
store the fault information for only one fault, so the first detected fault is recorded into the fault registers
and an interrupt is generated. Software must use the fault clear register (FLTCLR) to clear the fault status
so that another fault can be recorded. The MPU will not record another fault nor generate another interrupt
until the existing fault has been cleared. Also, additional faults will be ignored. Faults are not recorded (no
interrupts generated) for debug accesses.
6.2.8 Reset Considerations
After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection
features.
6.2.9 Interrupt Support
6.2.9.1
Interrupt Events and Requests
The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection
interrupt (MPU_PROT_ERR_INT). The MPU_ADDR_ERR_INT is generated when there is an addressing
violation due to an access to a non-existent location in the MPU register space. The
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined
ranges or to the MPU registers.
The transfer parameters that caused the violation are saved in the MPU registers.
6.2.9.2
Interrupt Multiplexing
The interrupts from both MPUs are combined with the boot configuration module into a single interrupt
called MPU_BOOTCFG_ERR. The combined interrupt is routed to the ARM and DSP interrupt controllers.
Table 6-5 shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR.
Table 6-5. MPU_BOOTCFG_ERR Interrupt Sources
Interrupt
Source
MPU1_ADDR_ERR_INT
MPU1 address error interrupt
MPU1_PROT_ERR_INT
MPU1 protection interrupt
MPU2_ADDR_ERR_INT
MPU2 address error interrupt
MPU2_PROT_ERR_INT
MPU2 protection interrupt
BOOTCFG_ADDR_ERR
Boot configuration address error
BOOTCFG_PROT_ERR
Boot configuration protection error
6.2.10 Emulation Considerations
Memory and MPU registers are not protected against emulation accesses.
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6.3
MPU Registers
There are two MPUs on the device. Each MPU contains a set of memory-mapped registers.
Table 6-6 lists the memory-mapped registers for the MPU1. Table 6-7 lists the memory-mapped registers
for the MPU2.
Table 6-6. Memory Protection Unit 1 (MPU1) Registers
Address
Acronym
Register Description
01E1 4000h
REVID
Revision identification register
Section 6.3.1
Section
01E1 4004h
CONFIG
Configuration register
Section 6.3.2
01E1 4010h
IRAWSTAT
Interrupt raw status/set register
Section 6.3.3
01E1 4014h
IENSTAT
Interrupt enable status/clear register
Section 6.3.4
01E1 4018h
IENSET
Interrupt enable set register
Section 6.3.5
01E1 401Ch
IENCLR
Interrupt enable clear register
01E1 4200h
PROG1_MPSAR
Programmable range 1 start address register
Section 6.3.10.1
01E1 4204h
PROG1_MPEAR
Programmable range 1 end address register
Section 6.3.11.1
01E1 4208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 4210h
PROG2_MPSAR
Programmable range 2 start address register
Section 6.3.10.1
01E1 4214h
PROG2_MPEAR
Programmable range 2 end address register
Section 6.3.11.1
01E1 4218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 4220h
PROG3_MPSAR
Programmable range 3 start address register
Section 6.3.10.1
01E1 4224h
PROG3_MPEAR
Programmable range 3 end address register
Section 6.3.11.1
01E1 4228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 4230h
PROG4_MPSAR
Programmable range 4 start address register
Section 6.3.10.1
01E1 4234h
PROG4_MPEAR
Programmable range 4 end address register
Section 6.3.11.1
01E1 4238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 4240h
PROG5_MPSAR
Programmable range 5 start address register
Section 6.3.10.1
01E1 4244h
PROG5_MPEAR
Programmable range 5 end address register
Section 6.3.11.1
01E1 4248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 4250h
PROG6_MPSAR
Programmable range 6 start address register
Section 6.3.10.1
01E1 4254h
PROG6_MPEAR
Programmable range 6 end address register
Section 6.3.11.1
01E1 4258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
Section 6.3.12
01E1 4300h
FLTADDRR
Fault address register
Section 6.3.13
01E1 4304h
FLTSTAT
Fault status register
Section 6.3.14
01E1 4308h
FLTCLR
Fault clear register
Section 6.3.15
Section 6.3.6
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Table 6-7. Memory Protection Unit 2 (MPU2) Registers
Address
Acronym
Register Description
01E1 5000h
REVID
Revision identification register
Section 6.3.1
01E1 5004h
CONFIG
Configuration register
Section 6.3.2
01E1 5010h
IRAWSTAT
Interrupt raw status/set register
Section 6.3.3
01E1 5014h
IENSTAT
Interrupt enable status/clear register
Section 6.3.4
01E1 5018h
IENSET
Interrupt enable set register
Section 6.3.5
01E1 501Ch
IENCLR
Interrupt enable clear register
Section 6.3.6
01E1 5100h
FXD_MPSAR
Fixed range start address register
Section 6.3.7
01E1 5104h
FXD_MPEAR
Fixed range end address register
Section 6.3.8
01E1 5108h
FXD_MPPA
Fixed range memory protection page attributes register
Section 6.3.9
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Table 6-7. Memory Protection Unit 2 (MPU2) Registers (continued)
114
Address
Acronym
Register Description
01E1 5200h
PROG1_MPSAR
Programmable range 1 start address register
Section 6.3.10.2
01E1 5204h
PROG1_MPEAR
Programmable range 1 end address register
Section 6.3.11.2
01E1 5208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 5210h
PROG2_MPSAR
Programmable range 2 start address register
Section 6.3.10.2
01E1 5214h
PROG2_MPEAR
Programmable range 2 end address register
Section 6.3.11.2
01E1 5218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 5220h
PROG3_MPSAR
Programmable range 3 start address register
Section 6.3.10.2
01E1 5224h
PROG3_MPEAR
Programmable range 3 end address register
Section 6.3.11.2
01E1 5228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 5230h
PROG4_MPSAR
Programmable range 4 start address register
Section 6.3.10.2
01E1 5234h
PROG4_MPEAR
Programmable range 4 end address register
Section 6.3.11.2
01E1 5238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 5240h
PROG5_MPSAR
Programmable range 5 start address register
Section 6.3.10.2
01E1 5244h
PROG5_MPEAR
Programmable range 5 end address register
Section 6.3.11.2
01E1 5248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 5250h
PROG6_MPSAR
Programmable range 6 start address register
Section 6.3.10.2
01E1 5254h
PROG6_MPEAR
Programmable range 6 end address register
Section 6.3.11.2
01E1 5258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
01E1 5260h
PROG7_MPSAR
Programmable range 7 start address register
Section 6.3.10.2
01E1 5274h
PROG7_MPEAR
Programmable range 7 end address register
Section 6.3.11.2
01E1 5268h
PROG7_MPPA
Programmable range 7 memory protection page attributes register
01E1 5270h
PROG8_MPSAR
Programmable range 8 start address register
Section 6.3.10.2
01E1 5274h
PROG8_MPEAR
Programmable range 8 end address register
Section 6.3.11.2
01E1 5278h
PROG8_MPPA
Programmable range 8 memory protection page attributes register
01E1 5280h
PROG9_MPSAR
Programmable range 9 start address register
Section 6.3.10.2
01E1 5284h
PROG9_MPEAR
Programmable range 9 end address register
Section 6.3.11.2
01E1 5288h
PROG9_MPPA
Programmable range 9 memory protection page attributes register
01E1 5290h
PROG10_MPSAR
Programmable range 10 start address register
Section 6.3.10.2
01E1 5294h
PROG10_MPEAR
Programmable range 10 end address register
Section 6.3.11.2
01E1 5298h
PROG10_MPPA
Programmable range 10 memory protection page attributes register
01E1 52A0h
PROG11_MPSAR
Programmable range 11 start address register
Section 6.3.10.2
01E1 52A4h
PROG11_MPEAR
Programmable range 11 end address register
Section 6.3.11.2
01E1 52A8h
PROG11_MPPA
Programmable range 11 memory protection page attributes register
01E1 52B0h
PROG12_MPSAR
Programmable range 12 start address register
Section 6.3.10.2
01E1 52B4h
PROG12_MPEAR
Programmable range 12 end address register
Section 6.3.11.2
01E1 52B8h
PROG12_MPPA
Programmable range 12 memory protection page attributes register
Section 6.3.12
01E1 5300h
FLTADDRR
Fault address register
Section 6.3.13
01E1 5304h
FLTSTAT
Fault status register
Section 6.3.14
01E1 5308h
FLTCLR
Fault clear register
Section 6.3.15
Memory Protection Unit (MPU)
Section
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
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6.3.1 Revision Identification Register (REVID)
The revision ID register (REVID) contains the MPU revision. The REVID is shown in Figure 6-3 and
described in Table 6-8.
Figure 6-3. Revision ID Register (REVID)
31
0
REV
R-4E81 0101h
LEGEND: R = Read only; -n = value after reset
Table 6-8. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E81 0101h
Description
Revision ID of the MPU.
6.3.2 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown
in Figure 6-4 and described in Table 6-9.
NOTE: Although the NUM_AIDS bit defaults to 12 (Ch), not all AIDs may be supported on your
device. Unsupported AIDs should be cleared to 0 in the memory page protection attributes
registers (MPPA). See for a list of AIDs supported on your device.
Figure 6-4. Configuration Register (CONFIG)
31
24
15
23
20
19
16
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-0 (1) or 6h (2)
R-0 (1) or 1 (2)
R-6h (1) or Ch (2)
12
11
1
0
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-Ch
R-0
R-1
LEGEND: R = Read only; -n = value after reset
(1)
(2)
For MPU1.
For MPU2.
Table 6-9. Configuration Register (CONFIG) Field Descriptions
Field
Value
Description
31-24
Bit
ADDR_WIDTH
0-FFh
Address alignment (2n KByte alignment) for range checking.
23-20
NUM_FIXED
0-Fh
Number of fixed address ranges.
19-16
NUM_PROG
0-Fh
Number of programmable address ranges.
15-12
NUM_AIDS
0-Fh
Number of supported AIDs.
11-1
Reserved
0
0
ASSUME_ALLOWED
Reserved
Assume allowed. When an address is not covered by any MPU protection range, this bit
determines whether the transfer is assumed to be allowed or not allowed.
0
Assume is disallowed.
1
Assume is allowed.
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6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 6-5 and described in Table 6-10.
Figure 6-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-10. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
116
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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6.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 6-6 and described in Table 611.
Figure 6-6. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-11. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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6.3.5 Interrupt Enable Set Register (IENSET)
Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Software can
write to IENSET to enable an interrupt. Writes of 0 have no effect. The IENSET is shown in Figure 6-7 and
described in Table 6-12.
Figure 6-7. Interrupt Enable Set Register (IENSET)
31
16
Reserved
R-0
15
2
1
0
ADDRERR_EN
PROTERR_EN
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-12. Interrupt Enable Set Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved
Address violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
PROTERR_EN
Protection violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
6.3.6 Interrupt Enable Clear Register (IENCLR)
Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Software can
write to IENCLR to clear/disable an interrupt. Writes of 0 have no effect. The IENCLR is shown in
Figure 6-8 and described in Table 6-13.
Figure 6-8. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-13. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
118
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved
Address violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
PROTERR_CLR
Protection violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
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6.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPSAR and the fixed range end
address register (FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in Figure 6-9.
Figure 6-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
6.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPEAR and the fixed range start
address register (FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 6-10.
Figure 6-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 6-11
and described in Table 6-14.
Figure 6-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-14. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
120
Controls access from ID = n.
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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6.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR)
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory, especially memory. One of the
programmable address ranges could be used to detect accesses to this unpopulated
memory.
The programmable range n start address register (PROGn_MPSAR) holds the start address for the range
n. The PROGn_MPSAR is writeable by a supervisor entity only.
The start address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 KBbyte; the page size for MPU2 is 64 KBytes. The size of the page determines
the width of the address field in PROGn_MPSAR and the programmable range n end address register
(PROGn_MPEAR). For example, to protect a 64-KB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
6.3.10.1 MPU1 Programmable Range n Start Address Register (PROG1_MPSAR-PROG6_MPSAR)
The PROGn_MPSAR for MPU1 is shown in Figure 6-12 and described in Table 6-15.
Figure 6-12. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
Reserved
R/W-20 0000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-15. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
START_ADDR
Reserved
20 0000h–
20 007Fh
0
Description
Start address for range N .
Reserved
6.3.10.2 MPU2 Programmable Range n Start Address Register (PROG1_MPSAR-PROG12_MPSAR)
The PROGn_MPSAR for MPU2 is shown in Figure 6-13 and described in Table 6-16.
Figure 6-13. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
31
16 15
0
START_ADDR
Reserved
R/W-C000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
Field
31-16
START_ADDR
15-0
Reserved
Value
C000h–DFFFh
0
Description
Start address for range N.
Reserved
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6.3.11 Programmable Range n End Address Registers (PROGn_MPEAR)
The programmable range n end address register (PROGn_MPEAR) holds the end address for the range
n. This register is writeable by a supervisor entity only.
The end address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 KByte; the page size for MPU2 is 64 KBytes. The size of the page determines the
width of the address field in the programmable range n start address register (PROGn_MPSAR) and
PROGn_MPEAR. For example, to protect a 64-KB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
6.3.11.1 MPU1 Programmable Range n End Address Register (PROG1_MPEAR-PROG6_MPEAR)
The PROGn_MPEAR for MPU1 is shown in Figure 6-14 and described in Table 6-17.
Figure 6-14. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
Reserved
R/W-20 007Fh
R-3FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-17. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
END_ADDR
Reserved
20 0000h–
20 007Fh
3FFh
Description
End address for range N.
Reserved
6.3.11.2 MPU2 Programmable Range n End Address Register (PROG1_MPEAR-PROG12_MPEAR)
The PROGn_MPEAR for MPU2 is shown in Figure 6-15 and described in Table 6-18.
Figure 6-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
31
16 15
0
END_ADDR
Reserved
R/W-DFFFh
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
Field
31-16
END_ADDR
15-0
Reserved
122
Value
C000h–DFFFh
FFFFh
Memory Protection Unit (MPU)
Description
Start address for range N.
Reserved
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6.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA)
The programmable range n memory protection page attributes register (PROGn_MPPA) holds the
permissions for the region n. This register is writeable only by a supervisor entity. The PROGn_MPPA is
shown in Figure 6-16 and described in Table 6-19.
Figure 6-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-19. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Controls access from ID = n.
0
Access is denied.
1
Access is granted.
AIDX
Controls access from ID > 11.
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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6.3.13 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) holds the address of the first protection fault transfer. The
FLTADDRR is shown in Figure 6-17 and described in Table 6-20.
Figure 6-17. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-20. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
124
Field
FLTADDR
Value
0-FFFF FFFFh
Memory Protection Unit (MPU)
Description
Memory address of fault.
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6.3.14 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in Figure 6-18 and described in Table 6-21.
Figure 6-18. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
Reserved
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-21. Fault Status Register (FLTSTAT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MSTID
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
Value
0
0-FFh
0
0-Fh
0
0-3Fh
Description
Reserved
Master ID of fault transfer.
Reserved
Privilege ID of fault transfer.
Reserved
Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).
0
No fault.
1h
User execute fault.
2h
User write fault.
3h
Reserved
4h
User read fault.
5h-7h
8h
9h-Fh
Reserved
Supervisor execute fault.
Reserved
10h
Supervisor write fault.
11h
Reserved
12h
Relaxed cache write back fault.
13h-1Fh
20h
21h-3Eh
3Fh
Reserved
Supervisor read fault.
Reserved
Relaxed cache line fill fault.
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6.3.15 Fault Clear Register (FLTCLR)
The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured
in the fault status register (FLTSTAT) as well as produce an interrupt. Only the TYPE bit field in FLTSTAT
is cleared when a 1 is written to the CLEAR bit. The FLTCLR is shown in Figure 6-19 and described in
Table 6-22.
Figure 6-19. Fault Clear Register (FLTCLR)
31
16
Reserved
R-0
15
1
0
Reserved
CLEAR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 6-22. Fault Clear Register (FLTCLR) Field Descriptions
Bit
31-1
0
126
Field
Reserved
Value
0
CLEAR
Description
Reserved
Command to clear the current fault. Writing 0 has no effect.
0
No effect.
1
Clear the current fault.
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Chapter 7
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Device Clocking
Topic
7.1
7.2
7.3
...........................................................................................................................
Page
Overview ......................................................................................................... 128
Frequency Flexibility ......................................................................................... 130
Peripheral Clocking .......................................................................................... 131
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Overview
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Overview
This device requires two primary reference clocks:
• One reference clock is required for the phase-locked loop controllers (PLLCs)
• One reference clock is required for the real-time clock (RTC) module.
These reference clocks may be sourced from either the on-board oscillator via an externally supplied
crystal or by a direct external oscillator input. For detailed specifications on clock frequency and voltage
requirements, see the electrical specifications in your device-specific data manual.
In addition to the reference clocks required for the PLLCs and RTC module, some peripherals, such as the
USB, may also require an input reference clock to be supplied. All possible input clocks are described in
Table 7-1. The CPU and the majority of the device peripherals operate at fixed ratios of the primary
system/CPU clock frequency, as listed in Table 7-2. However, there are two system clock domains that do
not require a fixed ratio to the CPU, these are PLL0_SYSCLK3 and PLL0_SYSCLK7. Figure 7-1 shows
the clocking architecture.
Table 7-1. Device Clock Inputs
Peripheral
Input Clock Signal Name
Oscillator/PLL
OSCIN
RTC
RTC_XI
JTAG
TCK, RTCK
EMAC RMII
RMII_MHZ_50_CLK
EMAC MII
MII_TXCLK, MII_RXCLK
USB2.0 and USB1.1
USB_REFCLKIN
I2Cs
I2Cn_SCL
Timers
TM64Pn_IN12
SATA
SATA_REFCLKP, SATA_REFCLKN
SPIs
SPIn_CLK
uPP
UPP_CHn_CLK
VPIF
VPIF_CLKINn
McBSPs
CLKSn, CLKRn, CLKXn
McASP0
ACLKR, AHCLKR, ACLKX, AHCLKX
Table 7-2. System Clock Domains
CPU/Device Peripherals
System Clock Domain
Fixed Ratio to
CPU Clock Required?
Default Ratio to
CPU Clock
DSP
PLL0_SYSCLK1
Yes
1:1
ARM RAM/ROM, DSP ports, Shared RAM, UART0,
EDMA, SPI0, MMC/SDs, VPIF, LCDC, SATA, uPP,
DDR2/mDDR (bus ports), USB2.0, HPI, PRU
subsystem
PLL0_SYSCLK2
Yes
1:2
EMIFA
PLL0_SYSCLK3
No
1:3
System configuration (SYSCFG), GPIO, PLLCs, PSCs, PLL0_SYSCLK4
I2C1, EMAC/MDIO, USB1.1, ARM INTC
Yes
1:4
ARM
PLL0_SYSCLK6
Yes
1:1
EMAC RMII clock
PLL0_SYSCLK7
No
1:6
I2C0, Timer64P0/P1, RTC, USB2.0 PHY, McASP0
serial clock
PLL0_AUXCLK
Not Applicable
Not Applicable
DDR2/mDDR PHY
PLL1_SYSCLK1
Not Applicable
Not Applicable
PLL0 input reference clock
(not configured by default)
PLL1_SYSCLK3
Not Applicable
Not Applicable
ECAPs, UART1/2, Timer64P2/3, eHRPWMs, McBSPs,
McASP0, SPI1
ASYNC3
Not Applicable
Not Applicable
128 Device Clocking
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Figure 7-1. Overall Clocking Diagram
PLL0 Multiplier Out
Div 4.5
1
EMIFA (C)
0+
SYSCLK3 (/3)
SYSCLK6 (/1)
ARM
SYSCLK1 (/1)
DSP
Shared RAM
CFGCHIP3[EMA_CLKSRC]
ARM RAM/ROM
EDMA
ARM INTC
SYSCLK4 (/4)
SPI0
System CFG
PLL0
Controller
MMC/SDs
PSCs
LCDC
I2C1
CLKSRC
HPI
USB1.1 (A)
USB2.0 (A)
EMAC/MDIO (D)
EXTCLKSRC
SATA
GPIO
uPP
I2C0
AUXCLK
UART0
Timers0/1
VPIF
RTC
PLL
Ref CLK
(E)
DDR2/mDDR (B)
SYSCLK2 (/2)
0+
SYSCLK2 (/2)
1
PRU
PLL1
Controller
CFGCHIP3[ASYNC3_CLKSRC]
SYSCLK3 (/3)
Timers2/3
UART1/2
+ Default Mux Selection
McASP0 (F)
CLKSRC
McBSPs
eHRPWMs
eCAPs
SPI1
A
See Section 7.3.1 for USB clocking.
B
See Section 7.3.2 for DDR2/mDDR clocking.
C
See Section 7.3.3 for EMIFA clocking.
D
See Section 7.3.4 for EMAC clocking.
E
See Section 7.3.5 for uPP clocking.
F
See Section 7.3.6 for McASP clocking.
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Frequency Flexibility
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Frequency Flexibility
There are two PLLs on the device with similar architecture and behavior. Each PLL has two clocking
modes:
• PLL Bypass
• PLL Active
When the PLL is in Bypass mode, the reference clock supplied on OSCIN serves as the clock source from
which all of the system clocks (SYSCLK1 to SYSCLK7) are derived. This means that when the PLL is in
Bypass mode, the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that
creates each of the system clocks. For PLL0 only, the EXTCLKSRC bit in PLLCTL can be configured to
use PLL1_SYSCLK3 as the Bypass mode reference clock.
When the PLL operates in Active mode, the PLL is enabled and the PLL multiplier setting is used to
multiply the input clock frequency supplied on the OSCIN pin up to the desired frequency. It is this
multiplied frequency that all system clocks are derived from in PLL Active mode.
The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the
system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1 to SYSCLK7). Each
SYSCLKn has a PLLDIVn block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter
for more details on the PLL.
The combination of the PLL multiplier, POSTDIV, and PLLDIV blocks provides flexibility in the frequencies
that the system clock domains support. This flexibility does have limitations, as follows:
• OSCIN input frequency is limited to a supported range.
• The output of the PLL Multiplier must be within the range specified in the device-specific data manual.
• The output of each PLLDIV block must be less than or equal to the maximum device frequency
specified in the device-specific data manual.
NOTE: The above limitations are provided here as an example and are used to illustrate the
recommended configuration of the PLL controller. These limitations may vary based on core
voltage and between devices. See the device-specific data manual for more details.
Table 7-3 shows examples of possible PLL multiplier settings, along with the available PLL post-divider
modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL
post-divider control register (POSTDIV). For Div1, Div2, Div3, and Div4 modes, the RATIO field would be
programmed to 0, 1, 2, and 3, respectively. The Div1, Div2, Div3, and Div4 modes are shown here as an
example. Additional post-divider modes are supported and are documented in the Phase-Locked Loop
Controller (PLLC) chapter.
NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases.
To decrease PLL power consumption, the lowest PLL multiplier (PLLM) setting should be
chosen that achieves the desired frequency. For example, if 200 MHz is the desired CPU
operating frequency and the OSCIN frequency is 25 MHz; lower power consumption is
achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2
instead of a PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these
modes would result in a CPU frequency of 200 MHz.
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Table 7-3. Example PLL Frequencies
7.3
OSCIN
Frequency
PLL Multiplier
Multiplier
Frequency
Div1
Div2
Div3
Div4
20
30
600 MHz
600
300
200
150
24
25
600 MHz
600
300
200
150
25
24
600 MHz
600
300
200
150
30
20
600 MHz
600
300
200
150
20
25
500 MHz
500
250
167
125
24
20
480 MHz
480
240
160
120
25
18
450 MHz
450
225
150
112.5
30
14
420 MHz
420
210
140
105
25
16
400 MHz
400
200
133
100
Peripheral Clocking
7.3.1 USB Clocking
Figure 7-2 shows the clock connections for the USB2.0 module. The USB2.0 subsystem requires a
reference clock for its internal PLL. This reference clock can be sourced from either the USB_REFCLKIN
pin or from the AUXCLK of the system PLL. The reference clock input to the USB2.0 subsystem is
selected by programming the USB0PHYCLKMUX bit in the chip configuration 2 register (CFGCHIP2) of
the System Configuration Module. The USB_REFCLKIN source should be selected when it is not possible
(such as when specific audio rates are required) to operate the device at one of the allowed input
frequencies to the USB2.0 subsystem. The USB2.0 subsystem peripheral bus clock is sourced from
PLL0_SYSCLK2.
The USB1.1 subsystem requires both a 48 MHz (CLK48) and a 12 MHz (CLK12) clock input. The 12 MHz
clock is derived from the 48 MHz clock. The 48 MHz clock required by the USB1.1 subsystem can be
sourced from either the USB_REFCLKIN or from the 48 MHz clock provided by the USB2.0 PHY. The
CLK48 source is selected by programming the USB1PHYCLKMUX bit in CFGCHIP2 of the System
Configuration Module. The USB1.1 subsystem peripheral bus clock is sourced from PLL0_SYSCLK4. See
Table 7-4.
NOTE:
If the USB1.1 subsystem is used and the 48 MHz clock input is sourced from the USB2.0
PHY, then the USB2.0 must be configured to always generate the 48 MHz clock. The
USB0PHY_PLLON bit in CFGCHIP2 controls the USB2.0 PHY, allowing or preventing it from
stopping the 48 MHz clock during USB SUSPEND. When the USB0PHY_PLLON bit is set to
1, the USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND;
when the USB0PHY_PLLON bit is cleared to 0, the USB2.0 PHY is allowed to stop the
48 MHz clock during USB SUSPEND.
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Figure 7-2. USB Clocking Diagram
USB_
AUXCLK REFCLKIN
CFGCHIP2[USB0PHYCLKMUX]
1
0
USB 2.0
Subsystem
(USB0)
CLK48MHz From
USB2.0 PHY
0
1
CFGCHIP2[USB1PHYCLKMUX]
/4
CLK12
CLK48
USB 1.1
Subsystem
(USB1)
Table 7-4. USB Clock Multiplexing Options
CFGCHIP2.
CFGCHIP2.
USB0PHYCLKMUX USB1PHYCLKMUX
bit
bit
132
USB2.0
Clock
Source
USB1.1
Clock
Source
Additional Conditions
0
0
USB_REFCLKIN
CLK48MHz output
from USB2.0 PHY
USB_REFCLKIN must be 12, 24, 48,
19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies.
0
1
USB_REFCLKIN
USB_REFCLKIN
USB_REFCLKIN must be 48 MHz. The
PLL inside the USB2.0 PHY can be
configured to accept this input clock
frequency.
1
0
PLL0_AUXCLK
CLK48MHz output
from USB2.0 PHY
PLL0_AUXCLK must be 12, 24, 48, 19.2,
38.4, 13, 26, 20, or 40 MHz. The PLL
inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies.
1
1
PLL0_AUXCLK
USB_REFCLKIN
PLL0_AUXCLK must be 12, 24, 48, 19.2,
38.4, 13, 26, 20, or 40 MHz. The PLL
inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies. USB_REFCLKIN must
be 48 MHz.
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7.3.2 DDR2/mDDR Memory Controller Clocking
The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see
Figure 7-3):
• VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO, write FIFO, and read FIFO of
the DDR2/mDDR memory controller. From this, VCLK drives the interface to the peripheral bus.
• 2X_CLK is sourced from PLL1_SYSCLK1.
2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
Table 7-5 shows example PLL register settings based on the OSCIN reference clock frequency of
25 MHz. From these example configurations, the following observations are made:
• To achieve the maximum frequency (150 MHz) supported by the DDR2/mDDR memory controller and
the typical CPU frequency of 300 MHz, the output of the PLL multiplier should be set to be 300 MHz
and the DDR_CLK source should be set to PLL1_SYSCLK1.
• The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier
block.
• The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock
frequencies.
• For certain PLL1 multiplier and PLL1 post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK1 as the clock source for 2X_CLK.
If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the
application as a free running clock that could be used by an FPGA or for some other purpose, then
2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. This
allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while
still providing a clock on the DDR_CLK and DDR_CLK.
NOTE: DDR_CLK and DDR_CLK are output clock signals.
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Figure 7-3. DDR2/mDDR Memory Controller Clocking Diagram
On Chip
PLL0_SYSCLK2/2
DDR2/mDDR
Memory
Controller
LPSC #6
DDR_CLK
DDR_CLK
VCLK
PLL1_SYSCLK1
2X_CLK
DDR
PHY
MCLK
Table 7-5. DDR2/mDDR Memory Controller MCLK Frequencies
OSCIN
Frequency
PLL1
Multiplier
Register
Setting
PLL1
Multiplier
Frequency
PLL1 Post
Divider
Mode (1)
PLL1
POSTDIV
Output
Frequency
PLL1
PLLDIV1
Register
Setting
PLL1_SYSCLK1
MCLK
24
18h
600 MHz
Div2
300 MHz
8000h
300 MHz
150 MHz
24
15h
528 MHz
Div2
264 MHz
8000h
264 MHz
132 MHz
24
14h
504 MHz
Div2
252 MHz
8000h
252 MHz
126 MHz
(1)
134
See Section 7.2 for explanation of POSTDIV divider modes.
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7.3.3 EMIFA Clocking
EMIFA requires a single input clock source. The EMIFA clock can be sourced from either PLL0_SYSCLK3
or DIV4P5 (see Figure 7-4). The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the
System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock
source for EMIFA.
Selecting the appropriate clock source for EMIFA is determined by the desired clock rate. Table 7-6 shows
example PLL register settings and the resulting DIV4P5 and PLL0_SYSCLK3 frequencies based on the
OSCIN reference clock frequency of 25 MHz. From these example configurations, the following
observations can be made:
• To achieve a typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300
MHz, the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be
set to PLL0_SYSCLK3 with the PLLDIV3 register set to 3.
• The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided
by 4.5.
• The PLLDIV3 block that sets the divider ratio for PLL0_SYSCLK3 can be changed to achieve various
clock frequencies.
Figure 7-4. EMIFA Clocking Diagram
LPSC
PLL Controller
SYSCLK3
0
DIV4P5 CLK
1
EMIFA
CFGCHIP3[EMA_CLKSRC]
Table 7-6. EMIFA Frequencies
OSCIN
Frequency
PLL Multiplier
Register
Multiplier
Setting
Frequency
Post Divider
Mode (1)
POSTDIV
Output
Frequency
25
24
Div2
300 MHz
Div3
200 MHz
25
25
(1)
18
16
600 MHz
450 MHz
400 MHz
DIV4P5
PLLDIV3
Register
Setting
PLL0_SYSCLK3
133 MHz
2
100 MHz
133 MHz
2
66.6 MHz
1
100 MHz
Div4
150 MHz
133 MHz
1
75 MHz
Div2
225 MHz
100 MHz
3
56.3 MHz
2
75 MHz
Div3
150 MHz
100 MHz
1
75 MHz
Div4
112.5 MHz
100 MHz
1
56.3 MHz
0
112.5 MHz
Div2
200 MHz
89 MHz
2
66.6 MHz
1
100 MHz
Div3
133 MHz
89 MHz
1
66.5 MHz
Div4
100 MHz
89 MHz
0
100 MHz
See Section 7.2 for explanation of POSTDIV divider modes.
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7.3.4 EMAC Clocking
The EMAC module sources its peripheral bus interface reference clock from PLL0_SYSCLK4 that is at a
fixed ratio of the CPU clock. The external clock requirement for EMAC varies with the interface used.
When the MII interface is active, the MII_TXCLK and MII_RXCLK signals must be provided from an
external source. When the RMII interface is active, the RMII 50 MHz reference clock is sourced either
from an external clock on the RMII_MHZ_50_CLK pin or from PLL0_SYSCLK7 (as shown in Figure 7-5).
The PINMUX15_3_0 bits in the pin multiplexing control 15 register (PINMUX15) of the System
Configuration Module control this clock selection:
• PINMUX15_3_0 = 0: enables sourcing of the 50 MHz reference clock from an external source on the
RMII_MHZ_50_CLK pin.
• PINMUX15_3_0 = 8h: enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7. Also,
PLL0_SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin.
Table 7-7 shows example PLL register settings and the resulting PLL0_SYSCLK7 frequencies based on
the OSCIN reference clock frequency of 25 MHz.
Figure 7-5. EMAC Clocking Diagram
On Chip
PLL Controller 0
LPSC
EMAC
SYSCLK4
SYSCLK7
50 MHz Reference Clock
PINMUX15[3:0]
1000 0000
3-State
0000 1000
RMII_MHZ_50_CLK
Signal
NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of
50 MHz +/-50 ppm.
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Table 7-7. EMAC Reference Clock Frequencies
OSCIN
Frequency
PLL Multiplier
Register Setting
Multiplier
Frequency
Post Divider
Mode (1)
POSTDIV Output
Frequency
PLLDIV7
Register
Setting
PLL0_SYSCLK7
25
24
600 MHz
Div2
300 MHz
5
50 MHz
Div3
200 MHz
3
50 MHz
Div4
150 MHz
2
50 MHz
Div2
225 MHz
Div3
150 MHz
Div4
112.5 MHz
25
(1)
(2)
18
450 MHz
Not Applicable (2)
2
50 MHz
Not Applicable (2)
See Section 7.2 for explanation of POSTDIV divider modes.
Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7.
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7.3.5 uPP Clocking
Figure 7-6 displays the clock connections for the uPP module. The uPP subsystem requires a module
clock to drive its internal logic and a transmit clock to drive I/O signals in transmit mode. The module clock
is always sourced by PLL0_SYSCLK2. The transmit clock is sourced by three different clocks:
PLL0_SYSCLK2 (default), PLL1_SYSCLK2, or the externally driven UPP_2xTXCLK pin. The transmit
clock source is selected by the UPP_TX_CLKSRC and ASYNC3_CLKSRC bits in the chip configuration 3
register (CFGCHIP3) of the System Configuration Module. Table 7-8 lists the register values that select
each of the three possible clock sources.
Regardless of the source, the uPP transmit clock speed cannot exceed the uPP module clock speed. The
module clock speed must be greater than or equal to the transmit clock speed.
Figure 7-6. uPP Clocking Diagram
Module
Clock
LPSC
PLL0_SYSCLK2
CFGCHIP3[UPP_TX_CLKSRC]
uPP
PLL0_SYSCLK2
0
0
1
PLL1_SYSCLK2
Transmit
Clock
1
CFGCHIP3[ASYNC3_CLKSRC]
UPP_2xTXCLK pin
Table 7-8. uPP Transmit Clock Selection
138
CFGCHIP3.UPP_TX_CLKSRC bit
CFGCHIP3.ASYNC3_CLKSRC bit
uPP Transmit Clock Source
0
0
PLL0_SYSCLK2
0
1
PLL1_SYSCLK2
1
x
UPP_2xTXCLK pin
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7.3.6 McASP Clocking
As shown in Figure 7-7, the McASP peripheral requires multiple clock sources. Internally, the module
clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC
bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module.
The transmit and receive clocks are sourced internally or externally by configuring the McASP clock
control registers ACLKRCTL, AHCLKRCTL, ACLKXCTL, and AHCLKXCTL. If an external clock is driven
into a high-frequency master clock (AHCLKX or AHCLKR), the McASP module allows for a mixed clock
mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the highfrequency master clock through a programmable divider.
When the internal clock source option is selected, the transmit and receive clocks are derived from the
PLL0_AUXCLK clock through programmable dividers.
Figure 7-7. McASP Clocking Diagram
On Chip
CFGCHIP3[ASYNC3_CLKSRC]
PLL0_SYSCLK2
0
PLL1_SYSCLK2
1
LPSC
Module
Clock
McASP0
PLL0_AUXCLK
TX/RX
Reference
Clock
Clock
Generator
Frame Sync
Generator
ACLKX
AHCLKX
AFSX
AFSR
ACLKR
AHCLKR
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7.3.7 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
The peripherals can be divided into the following groups, depending upon their clock requirements, as
shown in Table 7-9.
Table 7-9. Peripherals
Source of Peripheral Clock
RTC
—
Peripheral Group
Peripheral Group Definition
RTC
Operates off of a dedicated 32 kHz
crystal oscillator.
Fixed-Frequency Peripherals
As the name suggests, fixedTimer64P0/P1
frequency peripherals have a fixedI2C0
frequency. They are fed the
AUXCLK directly from the oscillator
input.
—
Synchronous peripherals have their
frequencies derived from the CPU
clock frequency. The peripheral
system clock frequency changes
accordingly, if the PLL0 frequency
changes. Most synchronous
peripherals have internal dividers
so they can generate their required
clock frequencies.
MMC/SDs
PLL0_SYSCLK2
HPI
PLL0_SYSCLK2
UART0
PLL0_SYSCLK2
LCDC
PLL0_SYSCLK2
GPIO
PLL0_SYSCLK4
Asynchronous peripherals are not
required to operate at a fixed ratio
of the CPU clock.
eCAPs
ASYNC3
eHRPWMs
ASYNC3
UART1/2
ASYNC3
Timer64P2/P3
ASYNC3
EMIFA
DIV_4P5 or PLL0_SYSCLK3
SATA
Peripheral Serial Clock
DDR2/mDDR
PLL1_SYSCLK1 or
PLL1 Direct Output
McASP0
ASYNC3 or
Peripheral Serial Clock
McBSPs
ASYNC3 or
Peripheral Serial Clock
SPI0
PLL0_SYSCLK2 or
Peripheral Serial Clock
SPI1
ASYNC3 or
Peripheral Serial Clock
I2C1
PLL0_SYSCLK4 or
Peripheral Serial Clock
EMAC
PLL0_SYSCLK4 or
RMII_MHZ_50_CLK
uPP
PLL0_SYSCLK2 or
Peripheral Serial Clock
VPIF
PLL0_SYSCLK2 or
Peripheral Serial Clock
USBs
USB_REFCLKIN or AUXCLK
Synchronous Peripherals
Asynchronous Peripherals
Synchronous/Asynchronous
Peripherals
140
Peripherals
Contained
within Group
Device Clocking
Synchronous/asynchronous
peripherals can be run with either
internally generated synchronous
clocks, or externally generated
asynchronous clocks.
—
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Chapter 8
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Phase-Locked Loop Controller (PLLC)
Topic
8.1
8.2
8.3
...........................................................................................................................
Page
Introduction ..................................................................................................... 142
PLL Controllers ................................................................................................ 142
PLLC Registers ................................................................................................ 147
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Introduction
8.1
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Introduction
This device has two phase-locked loop (PLL) controllers, PLLC0 and PLLC1. These PLL controllers
provide clock signals to most of the components of the device through various clock dividers.
Both PLL0 and PLL1 provide the following:
• Glitch-free transitions when clock settings are changed
• Domain clock alignment
• Clock gating
• PLL power-down
The clock outputs generated by the PLL controllers are:
• Domain clocks: PLL0_SYSCLK[1-7] and PLL1_SYSCLK[1-3]
• Auxiliary clock (PLL0_AUXCLK) from the PLLC0 reference clock source
Dividers that can be used for the PLL controllers are:
• Pre-PLL divider: PREDIV
• Post-PLL divider: POSTDIV
• SYSCLK divider: D1, …, Dn
Various other control signals supported are:
• PLL multiplier: PLLM
• Software-programmable PLL bypass: PLLEN
8.2
PLL Controllers
PLL0 and PLL1 share the same internal architecture so they also share the same approach for mode
configuration.
PLL0 provides the primary system clock to the device. PLL0 operations are software programmable
through the PLL controller 0 (PLLC0) registers.
PLL1 provides the reference clocks to various peripherals (including DDR2/mDDR) and may generate
clocks that are asynchronous to the PLL0 clocks. PLL1 operations are software programmable through the
PLL controller 1 (PLLC1) registers.
Figure 8-1 shows the PLLC0 and PLLC1 architecture.
The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register (PLLM).
The PLLM defaults to a multiplier value of 13h at power-up, which results in a PLL multiplier of 20×. The
PLL0 and PLL1 output clocks may be divided-down for slower device operation using the PLL post-divider
control register (POSTDIV). The POSTDIV has a default value of /2, but may be modified through
software (using the RATIO field in POSTDIV) to achieve lower device operation frequencies. The default
PLLM and POSTDIV settings produce a 300-MHz PLL output clock when given a 30-MHz clock source.
At power-up, PLL0 and PLL1 are powered-down/disabled and must be powered-up by software through
the PLLPWRDN bit in their respective PLL control register (PLLCTL). Before each PLL completes the
power-up and frequency-lock sequence, the system operates in bypass mode by default and the system
clock (OSCIN) is provided directly from an input reference clock (square wave or internal oscillator)
selected by the CLKMODE bit in PLLCTL. After the power-up and frequency-lock sequences are
complete, software can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
The PLL controller registers are listed in Section 8.3.
142
Phase-Locked Loop Controller (PLLC)
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Figure 8-1. PLLC Structure
PLL Controller 0
PLLCTL[EXTCLKSRC]
PLL1_SYSCLK3
PLLCTL[CLKMODE]
1
PLLCTL[PLLEN]
0
OSCIN
0
Square
Wave
1
Crystal
0
PREDIV
POSTDIV
PLL
1
PLLM
DEEPSLEEP
Enable
PLLDIV1 (/1)
SYSCLK1
PLLDIV2 (/2)
SYSCLK2
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
PLLDIV3 (/3)
SYSCLK3
EMIFA
Internal
Clock
Source
0
1
DIV4.5
CFGCHIP3[EMA_CLKSRC]
AUXCLK
PLLC0 OBSCLK
(CLKOUT Pin)
DIV4.5
OSCDIV
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
PLLC1 OBSCLK
OCSEL[OCSRC]
PLLCTL[PLLEN]
0
POSTDIV
PLL
1
PLLM
SYSCLK1
SYSCLK2
SYSCLK3
PLL Controller 1
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV1 (/1)
SYSCLK1
DDR2/mDDR
Internal
Clock
Source
14h
17h
18h
19h
OSCDIV
PLLC1 OBSCLK
OCSEL[OCSRC]
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8.2.1 Device Clock Generation
The PLL controllers (PLLC0 and PLLC1) manage the clock ratios, alignment, and gating for the device
system clocks. Various PLL mode attributes such as pre-division, multiplier, and post-division are software
programmable through the PLL controller registers. Additionally, the reset controller in PLLC0 manages
reset propagation through the device, clock alignment, and test points.
The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the
SYSCLK dividers can handle. The POSTDIV stage should be programmed to keep the input to the
SYSCLK dividers within operating limits. See the device datasheet for the maximum operating
frequencies.
PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. These
reference clocks are summarized in Table 8-1. Some output clock dividers require fixed values so that
clock ratios between various device components are maintained regardless of PLL or bypass frequency.
Table 8-1. System PLLC Output Clocks
Output Clock
Used by
Default Ratio
(relative to PLLn_SYSCLK1)
Fixed Clock
Ratio
PLLC0 (1)
PLL0_SYSCLK1
DSP
/1
Yes
PLL0_SYSCLK2
ARM RAM/ROM, DSP ports, Shared RAM,
UART0, EDMA, SPI0, MMC/SDs, VPIF,
LCDC, SATA, uPP, DDR2/mDDR (bus ports),
USB2.0, HPI, PRU
/2
Yes
PLL0_SYSCLK3 (2)
EMIFA
/3
No
PLL0_SYSCLK4
System configuration (SYSCFG), GPIO,
PLLCs, PSCs, I2C1, EMAC/MDIO, USB1.1,
ARM INTC
/4
Yes
PLL0_SYSCLK5
Not used
/3
No
PLL0_SYSCLK6
ARM
/1
Yes
PLL0_SYSCLK7
EMAC RMII clock
PLL0_AUXCLK
I2C0, Timer64P0/P1, RTC, USB2.0 PHY,
McASP0 serial clock
PLL0_OBSCLK
Observation clock (OBSCLK) source
/6
No
PLL bypass clock
No
Pin configurable
No
PLLC1
PLL1_SYSCLK1
DDR2/mDDR PHY
/1 or disabled
No
PLL1_SYSCLK2 (3)
ECAPs, UART1/2, Timer64P2/3, eHRPWMs,
McBSPs, McASP0, SPI1 (all these modules
use PLL0_SYSCLK2 by default)
/2 or disabled
No
PLL1_SYSCLK3 (4)
PLL0 input reference clock
(not configured by default)
/3 or disabled
No
(1)
(2)
(3)
(4)
144
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
PLLC0 supports an additional post-divider value of /4.5 that can be used for EMIFA clock generation. When this /4.5 value is
used, the resulting clock will not have a 50% duty cycle. Instead, the duty cycle will be 44.4%. The EMIFA uses PLL0_SYSCLK3
by default, but can be configured to use a /4.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the
EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG)
module.
The ASYNC3 modules use PLL0_SYSCLK2 by default, but all these modules can be configured as a group to use
PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system
configuration (SYSCFG) module.
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit
in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN.
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8.2.2 Steps for Programming the PLLs
Note that there is a lock mechanism implemented to protect the PLL controller registers. See
Section 8.2.2.1 for information on unlocking the PLL controller registers.
Refer to the appropriate subsection on how to program the PLL clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 8.2.2.2.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 8.2.2.3 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and only the SYSCLK dividers will be updated,
follow the sequence in Section 8.2.2.4.
Note that the PLLs are powered down after a Power-on Reset (POR). The PLLs are not powered down
after a Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the
PLLDIVx registers are reset to default values.
8.2.2.1
Locking/Unlocking PLL Register Access
A lock mechanism is implemented on the device to prevent inadvertent writes to the PLL controller
registers. This provides protection from stopping modules when the module clocks are disabled. For
example, the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally
disabled.
The PLL lock bits are located within the system configuration (SYSCFG) module:
• When set, the PLL_MASTER_LOCK bit in the chip configuration 0 register (CFGCHIP0) locks PLLC0.
• When set, the PLL1_MASTER_LOCK bit in the chip configuration 3 register (CFGCHIP3) locks PLLC1.
Because the SYSCFG module has its own lock mechanism, the SYSCFG module must be unlocked first
by writing to the KICK0R and KICK1R registers before the PLL lock bits can be cleared. Like the KICK
registers, the PLL lock bits can only be modified while in a privileged mode. See the System Configuration
(SYSCFG) Module chapter for information on privilege type and the KICK0R and KICK1R registers.
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 and the PLL1_MASTER_LOCK bit in
CFGCHIP3 default to unlocked after reset, so the following procedure is only required if the
PLLs have been locked (set to 1).
To modify the PLL controller registers, use the following sequence:
1. Write the correct key values to KICK0R and KICK1R registers.
2. Clear the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
3. Configure the desired PLL controller register values.
4. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
5. Write an incorrect key value to the KICK0R and KICK1R registers.
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Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Program the CLKMODE bit in PLLC0 PLLCTL.
2. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
3. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 (brings PLL out of power-down mode).
5. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
6. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
8. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
8.2.2.3
Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), perform the following
procedure to change the PLL multiplier:
1. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
2. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
3. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
4. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
5. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
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8.2.2.4
Changing SYSCLK Dividers
If the PLL is already operating at the desired multiplier mode, perform the following procedure to change
the SYSCLK divider values:
1. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress).
2. Program the RATIO field in PLLDIVn.
3. Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
8.3
PLLC Registers
Table 8-2 lists the memory-mapped registers for the PLLC0 and Table 8-3 lists the memory-mapped
registers for the PLLC1.
Table 8-2. PLL Controller 0 (PLLC0) Registers
Address
Acronym
Register Description
01C1 1000h
REVID
PLLC0 Revision Identification Register
Section 8.3.1
01C1 10E4h
RSTYPE
PLLC0 Reset Type Status Register
Section 8.3.3
01C1 10E8h
RSCTRL
PLLC0 Reset Control Register
Section 8.3.4
01C1 1100h
PLLCTL
PLLC0 Control Register
Section 8.3.5
01C1 1104h
OCSEL
PLLC0 OBSCLK Select Register
Section 8.3.7
01C1 1110h
PLLM
PLLC0 PLL Multiplier Control Register
Section 8.3.9
01C1 1114h
PREDIV
PLLC0 Pre-Divider Control Register
Section 8.3.10
01C1 1118h
PLLDIV1
PLLC0 Divider 1 Register
Section 8.3.11
01C1 111Ch
PLLDIV2
PLLC0 Divider 2 Register
Section 8.3.13
01C1 1120h
PLLDIV3
PLLC0 Divider 3 Register
Section 8.3.15
01C1 1124h
OSCDIV
PLLC0 Oscillator Divider 1 Register
Section 8.3.21
01C1 1128h
POSTDIV
PLLC0 PLL Post-Divider Control Register
Section 8.3.23
01C1 1138h
PLLCMD
PLLC0 PLL Controller Command Register
Section 8.3.24
01C1 113Ch
PLLSTAT
PLLC0 PLL Controller Status Register
Section 8.3.25
01C1 1140h
ALNCTL
PLLC0 Clock Align Control Register
Section 8.3.26
01C1 1144h
DCHANGE
PLLC0 PLLDIV Ratio Change Status Register
Section 8.3.28
01C1 1148h
CKEN
PLLC0 Clock Enable Control Register
Section 8.3.30
01C1 114Ch
CKSTAT
PLLC0 Clock Status Register
Section 8.3.32
01C1 1150h
SYSTAT
PLLC0 SYSCLK Status Register
Section 8.3.34
01C1 1160h
PLLDIV4
PLLC0 Divider 4 Register
Section 8.3.17
01C1 1164h
PLLDIV5
PLLC0 Divider 5 Register
Section 8.3.18
01C1 1168h
PLLDIV6
PLLC0 Divider 6 Register
Section 8.3.19
01C1 116Ch
PLLDIV7
PLLC0 Divider 7 Register
Section 8.3.20
01C1 11F0h
EMUCNT0
PLLC0 Emulation Performance Counter 0 Register
Section 8.3.36
01C1 11F4h
EMUCNT1
PLLC0 Emulation Performance Counter 1 Register
Section 8.3.37
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Table 8-3. PLL Controller 1 (PLLC1) Registers
Address
Acronym
Register Description
01E1 A000h
REVID
PLLC1 Revision Identification Register
Section 8.3.2
Section
01E1 A100h
PLLCTL
PLLC1 Control Register
Section 8.3.6
01E1 A104h
OCSEL
PLLC1 OBSCLK Select Register
Section 8.3.8
01E1 A110h
PLLM
PLLC1 PLL Multiplier Control Register
Section 8.3.9
01E1 A118h
PLLDIV1
PLLC1 Divider 1 Register
Section 8.3.12
01E1 A11Ch
PLLDIV2
PLLC1 Divider 2 Register
Section 8.3.14
01E1 A120h
PLLDIV3
PLLC1 Divider 3 Register
Section 8.3.16
01E1 A124h
OSCDIV
PLLC1 Oscillator Divider 1 Register
Section 8.3.22
01E1 A128h
POSTDIV
PLLC1 PLL Post-Divider Control Register
Section 8.3.23
01E1 A138h
PLLCMD
PLLC1 PLL Controller Command Register
Section 8.3.24
01E1 A13Ch
PLLSTAT
PLLC1 PLL Controller Status Register
Section 8.3.25
01E1 A140h
ALNCTL
PLLC1 Clock Align Control Register
Section 8.3.27
01E1 A144h
DCHANGE
PLLC1 PLLDIV Ratio Change Status Register
Section 8.3.29
01E1 A148h
CKEN
PLLC1 Clock Enable Control Register
Section 8.3.31
01E1 A14Ch
CKSTAT
PLLC1 Clock Status Register
Section 8.3.33
01E1 A150h
SYSTAT
PLLC1 SYSCLK Status Register
Section 8.3.35
01E1 A1F0h
EMUCNT0
PLLC1 Emulation Performance Counter 0 Register
Section 8.3.36
01E1 A1F4h
EMUCNT1
PLLC1 Emulation Performance Counter 1 Register
Section 8.3.37
8.3.1 PLLC0 Revision Identification Register (REVID)
The PLLC0 revision identification register (REVID) is shown in Figure 8-2 and described in Table 8-4.
Figure 8-2. PLLC0 Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -n = value after reset
Table 8-4. PLLC0 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 3C00h
148
Description
Peripheral revision ID for PLLC0.
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8.3.2 PLLC1 Revision Identification Register (REVID)
The PLLC1 revision identification register (REVID) is shown in Figure 8-3 and described in Table 8-5.
Figure 8-3. PLLC1 Revision Identification Register (REVID)
31
0
REV
R-4481 4400h
LEGEND: R = Read only; -n = value after reset
Table 8-5. PLLC1 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 4400h
Description
Peripheral revision ID for PLLC1.
8.3.3 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) latches the cause of the last reset. If multiple reset sources are
asserted simultaneously, RSTYPE records the reset source that deasserts last. If multiple reset sources
are asserted and deasserted simultaneously, RSTYPE latches the highest priority reset source. RSTYPE
is shown in Figure 8-4 and described in Table 8-6.
Figure 8-4. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
PLLSWRST
XWRST
POR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
PLLSWRST
Description
Reserved
PLL software reset.
0
PLL soft reset was not the last reset to occur.
1
PLL soft was the last reset to occur.
XWRST
External warm reset.
0
External warm reset was not the last reset to occur.
1
External warm reset was the last reset to occur.
POR
Power on reset.
0
Power On Reset (POR) was not the last reset to occur.
1
Power On Reset (POR) was the last reset to occur.
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8.3.4 PLLC0 Reset Control Register (RSCTRL)
The reset control register (RSCTRL) allows the device to perform a software-initiated reset. Before writing
to the SWRST bit, the register must be unlocked by writing the key value of 5A69h to the KEY bit field.
The KEY bit field reads back as Ch when the register is unlocked; any other key value is invalid and
indicates that the register is locked. Any write to the register following a successful unlock relocks the
register. RSCTRL is shown in Figure 8-5 and described in Table 8-7.
Figure 8-5. Reset Control Register (RSCTRL)
31
17
16
Reserved
SWRST
R-0
R/W-1
15
0
KEY
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-7. Reset Control Register (RSCTRL) Field Descriptions
Bit
31-17
16
15-0
Field
Reserved
Value
0
SWRST
KEY
Reserved
PLL software reset. Register must be unlocked before writing to this bit. Writes are possible only
when qualified with a valid key.
0
In software reset
1
Not in software reset
0-FFFFh
RSCTRL unlock key. Key used to enable writes to RSCTRL.
3h
Register is locked when read value is 3h.
Ch
Register is unlocked when read value is Ch.
5A69h
150
Description
RSCTRL unlock key
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8.3.5 PLLC0 Control Register (PLLCTL)
The PLLC0 control register (PLLCTL) is shown in Figure 8-6 and described in Table 8-8.
Figure 8-6. PLLC0 Control Register (PLLCTL)
31
16
Reserved
R-0
15
10
7
6
9
8
Reserved
EXTCLKSRC
CLKMODE
R-0
R/W-0
R/W-0
5
4
3
2
1
0
Reserved
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-8. PLLC0 Control Register (PLLCTL) Field Descriptions
Bit
31-10
9
8
Field
Reserved
Value
0
EXTCLKSRC
Description
Reserved
External clock source selection.
0
Use OSCIN for the PLL bypass clock.
1
Use PLL1_SYSCLK3 for the PLL bypass clock.
CLKMODE
Reference clock selection.
0
Internal oscillator (crystal)
1
Square wave
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
7-6
2
Reserved
1
PLLPWRDN
0
PLL0 reset.
0
PLL0 reset is asserted.
1
PLL0 reset is not asserted.
0
Reserved
PLL0 power-down.
0
PLL0 is operating.
1
PLL0 is powered-down.
PLLEN
PLL0 mode enables.
0
PLL0 is in bypass mode.
1
PLL0 mode is enabled, not bypassed.
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8.3.6 PLLC1 Control Register (PLLCTL)
The PLLC1 control register (PLLCTL) is shown in Figure 8-7 and described in Table 8-9.
Figure 8-7. PLLC1 Control Register (PLLCTL)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
6
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-9. PLLC1 Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
2
Reserved
1
PLLPWRDN
0
152
PLL1 reset.
0
PLL1 reset is asserted.
1
PLL1 reset is not asserted.
0
Reserved
PLL1 power-down.
0
PLL1 is operating.
1
PLL1 is powered-down.
PLLEN
PLL1 mode enables.
0
PLL1 is in bypass mode.
1
PLL1 mode is enabled, not bypassed.
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8.3.7 PLLC0 OBSCLK Select Register (OCSEL)
The PLLC0 OBSCLK select register (OCSEL) controls which clock is output on the CLKOUT pin so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 8-8 and described in Table 8-10.
Figure 8-8. PLLC0 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-10. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC0 OBSCLK source. Output on CLKOUT pin.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL0_SYSCLK1
18h
PLL0_SYSCLK2
19h
PLL0_SYSCLK3
1Ah
PLL0_SYSCLK4
1Bh
PLL0_SYSCLK5
1Ch
PLL0_SYSCLK6
1Dh
PLL0_SYSCLK7
1Eh
PLLC1 OBSCLK
1Fh
Disabled
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8.3.8 PLLC1 OBSCLK Select Register (OCSEL)
The PLLC1 OBSCLK select register (OCSEL) controls which clock is output on PLLC1 OBSCLK so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 8-9 and described in Table 8-11.
Figure 8-9. PLLC1 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC1 OBSCLK source.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL1_SYSCLK1
18h
PLL1_SYSCLK2
19h
PLL1_SYSCLK3
1A-1Fh Reserved
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8.3.9 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 8-10 and described in Table 8-12.
Figure 8-10. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PLLM
Value
0
0-1Fh
Description
Reserved
PLL multiplier select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
8.3.10 PLLC0 Pre-Divider Control Register (PREDIV)
The PLLC0 pre-divider control register (PREDIV) is shown in Figure 8-11 and described in Table 8-13.
Figure 8-11. PLLC0 Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-14
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
PLLC0 pre-divider enable.
0
PLLC0 pre-divider is disabled. Clock output from the PREDIV stage is disabled.
1
PLLC0 pre-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
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8.3.11 PLLC0 Divider 1 Register (PLLDIV1)
The PLLC0 divider 1 register (PLLDIV1) controls the divider for PLL0_SYSCLK1. PLLDIV1 is shown in
Figure 8-12 and described in Table 8-14.
Figure 8-12. PLLC0 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-14. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
8.3.12 PLLC1 Divider 1 Register (PLLDIV1)
The PLLC1 divider 1 register (PLLDIV1) controls the divider for PLL1_SYSCLK1. PLLDIV1 is shown in
Figure 8-13 and described in Table 8-15.
Figure 8-13. PLLC1 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-15. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D1EN
14-5
Reserved
4-0
RATIO
156
Value
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
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8.3.13 PLLC0 Divider 2 Register (PLLDIV2)
The PLLC0 divider 2 register (PLLDIV2) controls the divider for PLL0_SYSCLK2. PLLDIV2 is shown in
Figure 8-14 and described in Table 8-16.
Figure 8-14. PLLC0 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-16. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
8.3.14 PLLC1 Divider 2 Register (PLLDIV2)
The PLLC1 divider 2 register (PLLDIV2) controls the divider for PLL1_SYSCLK2. PLLDIV2 is shown in
Figure 8-15 and described in Table 8-17.
Figure 8-15. PLLC1 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-17. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
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8.3.15 PLLC0 Divider 3 Register (PLLDIV3)
The PLLC0 divider 3 register (PLLDIV3) controls the divider for PLL0_SYSCLK3. PLLDIV3 is shown in
Figure 8-16 and described in Table 8-18.
Figure 8-16. PLLC0 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
8.3.16 PLLC1 Divider 3 Register (PLLDIV3)
The PLLC1 divider 3 register (PLLDIV3) controls the divider for PLL1_SYSCLK3. PLLDIV3 is shown in
Figure 8-17 and described in Table 8-19.
Figure 8-17. PLLC1 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-0
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D3EN
14-5
Reserved
4-0
RATIO
158
Value
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
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8.3.17 PLLC0 Divider 4 Register (PLLDIV4)
The PLLC0 divider 4 register (PLLDIV4) controls the divider for PLL0_SYSCLK4. PLLDIV4 is shown
inFigure 8-18 and described in Table 8-20.
Figure 8-18. PLLC0 Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-20. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D4EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 4 enable.
0
Divider 4 is disabled.
1
Divider 4 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4).
8.3.18 PLLC0 Divider 5 Register (PLLDIV5)
The PLLC0 divider 5 register (PLLDIV5) controls the divider for PLL0_SYSCLK5. PLLDIV5 is shown in
Figure 8-19 and described in Table 8-21.
Figure 8-19. PLLC0 Divider 5 Register (PLLDIV5)
31
16
Reserved
R-0
15
14
5
4
0
D5EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-21. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D5EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 5 enable.
0
Divider 5 is disabled.
1
Divider 5 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
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8.3.19 PLLC0 Divider 6 Register (PLLDIV6)
The PLLC0 divider 6 register (PLLDIV6) controls the divider for PLL0_SYSCLK6. PLLDIV6 is shown in
Figure 8-20 and described in Table 8-22.
Figure 8-20. PLLC0 Divider 6 Register (PLLDIV6)
31
16
Reserved
R-0
15
14
5
4
0
D6EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-22. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D6EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 6 enable.
0
Divider 6 is disabled.
1
Divider 6 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
8.3.20 PLLC0 Divider 7 Register (PLLDIV7)
The PLLC0 divider 7 register (PLLDIV7) controls the divider for PLL0_SYSCLK7. PLLDIV7 is shown in
Figure 8-21 and described in Table 8-23.
Figure 8-21. PLLC0 Divider 7 Register (PLLDIV7)
31
16
Reserved
R-0
15
14
5
4
0
D7EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D7EN
14-5
Reserved
4-0
RATIO
160
Value
Description
Reserved
Divider 7 enable.
0
Divider 7 is disabled.
1
Divider 7 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).
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8.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)
The PLLC0 oscillator divider 1 register (OSCDIV) controls the divider for PLLC0 OBSCLK, dividing down
the clock selected as the PLLC0 OBSCLK source. The PLLC0 OBSCLK is connected to the CLKOUT pin.
The OSCDIV is shown in Figure 8-22 and described in Table 8-24.
Figure 8-22. PLLC0 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC0 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC0 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
8.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)
The PLLC1 oscillator divider 1 register (OSCDIV) controls the divider for PLLC1 OBSCLK, dividing down
the clock selected as the PLLC1 OBSCLK source. The PLLC1 OBSCLK signal may be selected as the
output on the CLKOUT pin. The OSCDIV is shown in Figure 8-23 and described in Table 8-25.
Figure 8-23. PLLC1 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-25. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC1 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC1 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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8.3.23 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 8-24 and described in Table 8-26.
Figure 8-24. PLL Post-Divider Control Register (POSTDIV)
31
16
Reserved
R-0
15
14
5
4
0
POSTDEN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
POSTDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Post-divider enable.
0
Post-divider is disabled.
1
Post-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
8.3.24 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) contains the command bit for phase alignment. A write of
1 initiates the command; a write of 0 clears the bit, but has no effect. PLLCMD is shown in Figure 8-25
and described in Table 8-27.
Figure 8-25. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 8-27. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
162
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for phase alignment.
0
Clear bit (no effect)
1
Phase alignment
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8.3.25 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 8-26 and described in Table 8-28.
Figure 8-26. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
STABLE
Reserved
GOSTAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-28. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation. If 1, indicates GO operation is in progress.
0
GO operation is not in progress.
1
GO operation is in progress.
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8.3.26 PLLC0 Clock Align Control Register (ALNCTL)
The PLLC0 clock align control register (ALNCTL) indicates which PLL0_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 8-27 and described in Table 8-29.
Figure 8-27. PLLC0 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-3h
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-29. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
164
Field
Reserved
Value
3h
ALN7
Description
Reserved
PLL0_SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN6
PLL0_SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN5
PLL0_SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN4
PLL0_SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN3
PLL0_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL0_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL0_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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8.3.27 PLLC1 Clock Align Control Register (ALNCTL)
The PLLC1 clock align control register (ALNCTL) indicates which PLL1_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 8-28 and described in Table 8-30.
Figure 8-28. PLLC1 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-30. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
ALN3
Description
Reserved
PLL1_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL1_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL1_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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8.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC0 PLLDIV ratio change status register (DCHANGE) indicates if the PLL0_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 8-29 and described in Table 8-31.
Figure 8-29. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-31. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
166
Field
Reserved
Value
0
SYS7
Description
Reserved
PLL0_SYSCLK7 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS6
PLL0_SYSCLK6 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS5
PLL0_SYSCLK5 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS4
PLL0_SYSCLK4 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS3
PLL0_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL0_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL0_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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8.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC1 PLLDIV ratio change status register (DCHANGE) indicates if the PLL1_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 8-30 and described in Table 8-32.
Figure 8-30. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-32. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
SYS3
Description
Reserved
PLL1_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL1_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL1_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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8.3.30 PLLC0 Clock Enable Control Register (CKEN)
The PLLC0 clock enable control register (CKEN) controls the PLLC0 OBSCLK and AUXCLK clock. CKEN
is shown in Figure 8-31 and described in Table 8-33.
Figure 8-31. PLLC0 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-33. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK enable. Actual PLLC0 OBSCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 OBSCLK is disabled.
1
PLLC0 OBSCLK is enabled. For PLLC0 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC0 oscillator divider 1 register (OSCDIV) must be set to 1.
AUXEN
AUXCLK enable. Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 AUXCLK is disabled.
1
PLLC0 AUXCLK is enabled.
8.3.31 PLLC1 Clock Enable Control Register (CKEN)
The PLLC1 clock enable control register (CKEN) controls the PLLC1 OBSCLK clock. CKEN is shown in
Figure 8-32 and described in Table 8-34.
Figure 8-32. PLLC1 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-34. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
168
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK enable. Actual PLLC1 OBSCLK status is shown in the PLLC1 clock status register (CKSTAT).
0
PLLC1 OBSCLK is disabled.
1
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1.
0
Reserved
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8.3.32 PLLC0 Clock Status Register (CKSTAT)
The PLLC0 clock status register (CKSTAT) indicates the PLLC0 OBSCLK and AUXCLK on/off status. The
PLL0_SYSCLK status is shown in the PLLC0 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 8-33 and described in Table 8-35.
Figure 8-33. PLLC0 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R-1
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-35. PLLC0 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK on status. PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC0 clock enable control register (CKEN).
0
PLLC0 OBSCLK is off.
1
PLLC0 OBSCLK is on.
AUXEN
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control
register (CKEN).
0
PLLC0 AUXCLK is off.
1
PLLC0 AUXCLK is on.
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8.3.33 PLLC1 Clock Status Register (CKSTAT)
The PLLC1 clock status register (CKSTAT) indicates the PLLC1 OBSCLK on/off status. The
PLL1_SYSCLK status is shown in the PLLC1 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 8-34 and described in Table 8-36.
Figure 8-34. PLLC1 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-2h
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-36. PLLC1 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
170
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK on status. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC1 clock enable control register (CKEN).
0
PLLC1 OBSCLK is off.
1
PLLC1 OBSCLK is on.
0
Reserved
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8.3.34 PLLC0 SYSCLK Status Register (SYSTAT)
The PLLC0 SYSCLK status register (SYSTAT) indicates the PLL0_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC0 PLLDIVn.
SYSTAT is shown in Figure 8-35 and described in Table 8-37.
Figure 8-35. PLLC0 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-1
7
6
5
4
3
2
1
0
Reserved
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-37. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-7
Reserved
6
SYS7ON
5
4
3
2
1
0
Value
3h
Description
Reserved
PLL0_SYSCLK7 on status.
0
Off
1
On
SYS6ON
PLL0_SYSCLK6 on status.
0
Off
1
On
SYS5ON
PLL0_SYSCLK5 on status.
0
Off
1
On
SYS4ON
PLL0_SYSCLK4 on status.
0
Off
1
On
SYS3ON
PLL0_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL0_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL0_SYSCLK1 on status.
0
Off
1
On
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8.3.35 PLLC1 SYSCLK Status Register (SYSTAT)
The PLLC1 SYSCLK status register (SYSTAT) indicates the PLL1_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC1 PLLDIVn.
SYSTAT is shown in Figure 8-36 and described in Table 8-38.
Figure 8-36. PLLC1 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-0
7
2
1
0
Reserved
3
SYS3ON
SYS2ON
SYS1ON
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
SYS3ON
1
0
172
Value
0
Description
Reserved
PLL1_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL1_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL1_SYSCLK1 on status.
0
Off
1
On
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8.3.36 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 8-37 and described in
Table 8-39. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 8-37. Emulation Performance Counter 0 Register (EMUCNT0)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-39. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit
31-0
Field
Value
COUNT
0-FFFF FFFFh
Description
Counter value for lower 64-bits.
8.3.37 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 8-38 and described in
Table 8-40. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 8-38. Emulation Performance Counter 1 Register (EMUCNT1)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit
31-0
Field
COUNT
Value
0-FFFF FFFFh
Description
Counter value for upper 64-bits.
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Topic
...........................................................................................................................
9.1
9.2
9.3
9.4
9.5
9.6
Introduction .....................................................................................................
Power Domain and Module Topology ..................................................................
Executing State Transitions ...............................................................................
IcePick Emulation Support in the PSC ................................................................
PSC Interrupts..................................................................................................
PSC Registers ..................................................................................................
Power and Sleep Controller (PSC)
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175
175
180
181
181
184
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9.1
Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupts, a state machine for each
peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and
provides clock and reset control. Many of the operations of the PSC are transparent to user (software),
such as power on and reset control. However, the PSC module(s) also provide you with interface to
control several important power, clock and reset operations. The module level power, clock and reset
operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for DSP memories and L3 RAM)
• Supports IcePick emulation features: power, clock and reset
9.2
Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of:
• an Always On power domain
• an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in
the DSP subsystem and the L3 RAM, respectively
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 9-1 and Table 9-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 9.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have an LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
NOTE: There are no LPSCs for peripherals in the Async2 clock domain (this includes RTC,
Timer64P0/P1, and I2C0); from a power savings stand point, clock-gating these peripherals
does not result in significant power savings.
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Table 9-1. PSC0 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_0 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3_0 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3_0 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4
SPI0
AlwaysON (PD0)
SwRstDisable
—
5
MMC/SD0
AlwaysON (PD0)
SwRstDisable
—
6
ARM Interrupt Controller
AlwaysON (PD0)
Enable
—
7
ARM RAM/ROM
AlwaysON (PD0)
Enable
Yes
8
Not Used
—
—
—
9
UART0
AlwaysON (PD0)
SwRstDisable
—
10
SCR0 (BR0, BR1, BR2, BR8)
AlwaysON (PD0)
Enable
Yes
11
SCR1 (BR4)
AlwaysON (PD0)
Enable
Yes
12
SCR2 (BR3, BR5, BR6)
AlwaysON (PD0)
Enable
Yes
13
PRU
AlwaysON (PD0)
SwRstDisable
—
14
ARM
AlwaysON (PD0)
SwRstDisable
—
15
DSP
PD_DSP (PD1)
Enable
—
Table 9-2. PSC1 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_1 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
USB1 (USB1.1)
AlwaysON (PD0)
SwRstDisable
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
HPI
AlwaysON (PD0)
SwRstDisable
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
DDR2/mDDR
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 (+ McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
(1)
8
SATA
AlwaysON (PD0)
SwRstDisable
—
9
VPIF
AlwaysON (PD0)
SwRstDisable
—
10
SPI1
AlwaysON (PD0)
SwRstDisable
—
11
I2C1
AlwaysON (PD0)
SwRstDisable
—
12
UART1
AlwaysON (PD0)
SwRstDisable
—
13
UART2
AlwaysON (PD0)
SwRstDisable
—
14
McBSP0 (+ McBSP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
15
McBSP1 (+ McBSP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
16
LCDC
AlwaysON (PD0)
SwRstDisable
—
17
eHRPWM0/1
AlwaysON (PD0)
SwRstDisable
—
18
MMC/SD1
AlwaysON (PD0)
SwRstDisable
—
19
uPP
AlwaysON (PD0)
SwRstDisable
—
20
eCAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
EDMA3_1 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
(1)
Note that the SATA module requires forced state transitions.
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Table 9-2. PSC1 Default Module Configuration (continued)
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
24
SCR F0
AlwaysON (PD0)
Enable
Yes
25
SCR F1
AlwaysON (PD0)
Enable
Yes
26
SCR F2
AlwaysON (PD0)
Enable
Yes
27
SCR F6
AlwaysON (PD0)
Enable
Yes
28
SCR F7
AlwaysON (PD0)
Enable
Yes
29
SCR F8
AlwaysON (PD0)
Enable
Yes
30
BR F7
AlwaysON (PD0)
Enable
Yes
31
Shared RAM
PD_SHRAM
Enable
—
9.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In this device, for both PSC0 and PSC1, the Always ON domain (or PD0 power domain), is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state (See details on
PDCTL register).
Additionally, for both PSC0 and PSC1, the PD1 power domains, the internal/pseudo power domain can
either be in the ON state or OFF state. Furthermore, for these power domains the transition from ON to
OFF state is further qualified by the PSC0/1.PDCTL1.PDMODE settings. The PDCTL1.PDMODE settings
determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
• On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128KB Shared RAM
NOTE: Currently programming the PD1 power domain state to OFF is not supported. You should
leave both the PDCTL1.NEXT and PDCTL1.PDMODE values at default/power on reset
values.
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of
the device. There is no capability to individually remove voltage/power from the DSP or
Shared RAM power domains .
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9.2.2 Module States
The PSC defines several possible states for a module. This various states are essentially a combination of
the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The various
module states are defined in Table 9-3.
The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in
Auto Sleep mode, it will transition back to the clock disabled state (automatically sleep) after servicing the
internal read/write access request where as in Auto Wake mode, on receiving the first internal read/write
access request, the module will permanently transition from the clock disabled to clock enabled state
(automatically wake).
When the module state is programmed to Disable, SwRstDisable, Auto Sleep or Auto Wake modes,
where in the module clocks are off/disabled, an external event or I/O request cannot enable the clocks.
For the module to appropriately respond to such external request, it would need to be reconfigured to the
Enable state.
9.2.2.1
Auto Sleep/Wake Only Configurations and Limitation
NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes. If the
module clocks need to gated/disabled for power savings, you should program the module
state to Disable. For Auto Sleep/Auto Wake Only modules, disabling the clock is not
supported and they should be kept in their default “Enable” state.
Table 9-1 and Table 9-2 each have a column to indicate whether or not the LPSC configuration for a
module is Auto Sleep/Wake Only. Modules that have a “Yes” marked for the Auto Sleep/Wake Only
column can be programmed in software to be in Enable, Auto Sleep and Auto Wake states only; that is, if
the software tries to program these modules to Disable, SyncReset, or SwRstDisable state the power
sleep controller ignores these transition requests and transitions the module state to Enable.
9.2.2.2
Local Reset
In addition to module reset, the following modules can be reset using a special local reset that is also a
part of the PSC module control for resets.
• DSP: When the DSP local reset is asserted the DSP internal memories (L1P, L1D and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of DSP subsystem, as the DSP
module reset would. Local Reset is useful in cases where the DSP is in enable or disable state; since
when module is in SyncReset or SwRstDisable state the module reset is asserted, and the module
reset takes precedence over the local reset.
• ARM: When the ARM local reset is asserted the entire ARM processor is reset , including cache etc.
This does not include the ARM RAM/ROM or ARM interrupt controller module as these exist outside
the ARM core. The local reset for ARM additionally ensures that any outstanding requests are
completed before ARM is reset, therefore for scenarios where it is needed to just reset the ARM locally
but not change the state of clocks, user can use ARM local reset feature.
The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the
module that supports local reset):
1. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset.
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset.
If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted.
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Table 9-3. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has
its clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has
its module clock off. This state is typically used for disabling a module
clock to save power. This device is designed in full static CMOS, so when
you stop a module clock, it retains the module’s state. When the clock is
restarted, the module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it
has its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it
has its clock disabled. After initial power-on, several modules come up in
the SwRstDisable state. Generally, software is not expected to initiate this
state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it
can “automatically” transition to “Enable” state whenever there is an
internal read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re deasserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data. See Section 9.2.2.1 for
additional considerations, constraints, limitations around this mode.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from
then on (with module reset re de-asserted and module clock on), without
any software intervention. The transition from sleep to enabled state has
some cycle latency associated with it. It is not envisioned to use this mode
when peripherals are fully operational and moving data. See
Section 9.2.2.1 for additional considerations, constraints, limitations around
this mode.
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9.3
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Executing State Transitions
This section describes how to execute the state transitions modules.
9.3.1 Power Domain State Transitions
This device consists of two types of domain (in each PSC controller):
• Always On domain(s)
• pseudo/RAM power domain(s)
The Always On power domains are always in the ON state when the chip is powered on. You are not
allowed to change the power domain state to OFF.
The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with
these domains (L1/L2 for PD_DSP in PSC0 and Shared RAM for PD_SHRAM in PSC1) so that these
RAMs can run in lower power sleep modes via the power sleep controller.
NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported;
therefore, these domains and the RAM should be left in their default power on state.
As mentioned in Section 9.2, the pseudo/RAM power domains are powered down internally,
and in this context powering down does not imply removing the core voltage from pins
externally.
9.3.2 Module State Transitions
This section describes the procedure for transitioning the module state (clock and reset control). Note that
some peripherals have special programming requirements and additional recommended steps you must
take before you can invoke the PSC module state transition. See the individual peripheral user guides for
more details. For example, the external memory controller requires that you first place the SDRAM
memory in self-refresh mode before you invoke the PSC module state transitions, if you want to maintain
the memory contents.
The following procedure is directly applicable for all modules that are controlled via the PSC (shown in
Table 9-1 and Table 9-2), except for the core(s). To transition the DSP or ARM module state, there are
additional system considerations and constraints that you should be aware of. These system
considerations and the procedure for transitioning the DSP or ARM module state are described in details
in the Power Management chapter.
NOTE: In the following procedure, x is 0 for modules in PD0 (Power Domain 0 or Always On
domain) and x is 1 for modules in PD1 (Power Domain 1). See Table 9-1 and Table 9-2 for
power domain associations.
The procedure for module state transitions is:
1. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), Enable (3h), Auto
Sleep (4h) or Auto Wake (5h).
NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[x] bit in PTCMD in a later step.
3. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
after the GOSTAT[x] bit in PTSTAT is cleared to 0.
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9.4
IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the
state of power domains and modules. This IcePick support only applies to the following modules:
• DSP [MDCTL15]
• ARM [MDCTL14]
In particular, Table 9-4 shows IcePick emulation commands recognized by the PSC.
Table 9-4. IcePick Emulation Commands
Power On and
Enable Features
Power On and Enable Descriptions
Reset Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the
module’s local reset.
Force Power
Allows emulation to force the power domain into
an on state. Not applicable as AlwaysOn power
domain is always on.
Wait Reset
Allows emulation to keep local
reset asserted for an extended
period of time after software
initiates local reset de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block
software initiated local and
module resets.
NOTE: When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in
MDCTLn, as set by software.
9.5
PSC Interrupts
The PSC has an interrupt that is tied to the core interrupt controller. This interrupt is named PSCINT in the
interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.
9.5.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Power Domain Emulation Event (applies to pseudo/RAM power domain only)
• Module State Emulation event
• Module Local Reset Emulation event
These interrupt events are summarized in Table 9-5 and described in more detail in this section.
Table 9-5. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Enable Bit
Interrupt Condition
PDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the power domain state
MDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the module state
MDCTLn
EMURSTIE
Interrupt occurs when the emulation tries to alter the module’s local reset
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the userprogrammed state in the NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the
modules listed in Section 9.4; therefore, the PSC interrupt conditions only apply to those modules listed.
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Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTATn. In particular, a power
domain emulation event occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
• When force power is asserted by emulation and power domain is not already in the on state
• When force active is asserted by emulation and power domain is not already in the on state
NOTE:
9.5.1.2
Putting the pseudo/RAM power domain associated with the DSP (PD_DSP) to the off state
currently is not supported.
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTATn). In particular, a module state emulation event
occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
• When force active is asserted by emulation and module is not already in the enable state
9.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTATn). In particular, a module local reset emulation
event occurs under the following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset
• When wait reset is asserted by emulation
• When block reset is asserted by emulation and software attempts to change the state of local reset
9.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support, as specified in
Section 9.4).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled appropriately in the ARM interrupt controller. For
details on the ARM interrupt controller, see the ARM Interrupt Controller (AINTC) chapter.
The PSC interrupt status bits are:
• For DSP:
– The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).
– The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain
associated with DSP memories.
• For ARM:
– The M[14] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for ARM (MDSTAT14).
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The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.
The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register. When set, this bit forces the
PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set)
when the ALLEV bit in the INTEVAL is set to 1, the PSC interrupt is re-asserted to the interrupt controller.
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do
not miss any PSC interrupts.
See Section 9.6 for a description of the PSC registers.
9.5.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt:
1. Set the EMUIHBIE bit in PDCTLn, the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the
interrupt events that you want.
NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event
becomes active.
2. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. To
interrupt the CPU, PSCn_ALLINT must be enabled in the device interrupt controller. See the ARM
Interrupt Controller (AINTC) chapter for more information on interrupts.
The CPU enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the P[n] bit in PERRPR, and/or the M[n] bit in MERRPR0, the M[n] bit in MERRPR1, to
determine the source of the interrupt(s).
2. For each active event that you want to service:
(a) Read the event status bits in PDSTATn and MDSTATn, depending on the status bits read in the
previous step to determine the event that caused the interrupt.
(b) Service the interrupt as required by your application.
(c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status.
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt
controller, if there are still any active interrupt events.
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Table 9-6 lists the memory-mapped registers for the PSC0 and Table 9-7 lists the memory-mapped
registers for the PSC1.
Table 9-6. Power and Sleep Controller 0 (PSC0) Registers
Address
Acronym
Register Description
01C1 0000h
REVID
Revision Identification Register
Section 9.6.1
Section
01C1 0018h
INTEVAL
Interrupt Evaluation Register
Section 9.6.2
01C1 0040h
MERRPR0
Module Error Pending Register 0 (module 0-15)
Section 9.6.3
01C1 0050h
MERRCR0
Module Error Clear Register 0 (module 0-15)
Section 9.6.5
01C1 0060h
PERRPR
Power Error Pending Register
Section 9.6.7
01C1 0068h
PERRCR
Power Error Clear Register
Section 9.6.8
01C1 0120h
PTCMD
Power Domain Transition Command Register
Section 9.6.9
01C1 0128h
PTSTAT
Power Domain Transition Status Register
Section 9.6.10
01C1 0200h
PDSTAT0
Power Domain 0 Status Register
Section 9.6.11
01C1 0204h
PDSTAT1
Power Domain 1 Status Register
Section 9.6.12
01C1 0300h
PDCTL0
Power Domain 0 Control Register
Section 9.6.13
01C1 0304h
PDCTL1
Power Domain 1 Control Register
Section 9.6.14
01C1 0400h
PDCFG0
Power Domain 0 Configuration Register
Section 9.6.15
01C1 0404h
PDCFG1
Power Domain 1 Configuration Register
Section 9.6.16
01C1 0800h01C1 083Ch
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15)
Section 9.6.17
01C1 0A00h01C1 0A3Ch
MDCTL0MDCTL15
Module Control n Register (modules 0-15)
Section 9.6.18
Table 9-7. Power and Sleep Controller 1 (PSC1) Registers
184
Address
Acronym
Register Description
01E2 7000h
REVID
Revision Identification Register
Section 9.6.1
01E2 7018h
INTEVAL
Interrupt Evaluation Register
Section 9.6.2
01E2 7040h
MERRPR0
Module Error Pending Register 0 (module 0-31)
Section 9.6.4
01E2 7050h
MERRCR0
Module Error Clear Register 0 (module 0-31)
Section 9.6.6
01E2 7060h
PERRPR
Power Error Pending Register
Section 9.6.7
01E2 7068h
PERRCR
Power Error Clear Register
Section 9.6.8
01E2 7120h
PTCMD
Power Domain Transition Command Register
Section 9.6.9
01E2 7128h
PTSTAT
Power Domain Transition Status Register
Section 9.6.10
01E2 7200h
PDSTAT0
Power Domain 0 Status Register
Section 9.6.11
01E2 7204h
PDSTAT1
Power Domain 1 Status Register
Section 9.6.12
01E2 7300h
PDCTL0
Power Domain 0 Control Register
Section 9.6.13
01E2 7304h
PDCTL1
Power Domain 1 Control Register
Section 9.6.14
01E2 7400h
PDCFG0
Power Domain 0 Configuration Register
Section 9.6.15
01E2 7404h
PDCFG1
Power Domain 1 Configuration Register
Section 9.6.16
01E2 7800h01E2 787Ch
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31)
Section 9.6.17
01E2 7A00h01E2 7A7Ch
MDCTL0MDCTL31
Module Control n Register (modules 0-31)
Section 9.6.19
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9.6.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 9-1 and described in Table 9-8.
Figure 9-1. Revision Identification Register (REVID)
31
0
REV
R-4482 5A00h
LEGEND: R = Read only; -n = value after reset
Table 9-8. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4482 5A00h
Description
Peripheral revision ID.
9.6.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 9-2 and described in Table 9-9.
Figure 9-2. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 9-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt (PSCn_ALLINT).
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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9.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 9-3 and described in Table 910.
Figure 9-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31
16
Reserved
R-0
15
14
M[15]
M[14]
13
Reserved
0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit
31-16
15
14
13-0
Field
Reserved
Value
0
M[15]
Reserved
Module interrupt status bit for module 15 (DSP).
0
Module 15 does not have an error condition.
1
Module 15 has an error condition. See the module status 15 register (MDSTAT15) for the error
condition.
M[14]
Reserved
Description
Module interrupt status bit for module 14 (ARM).
0
Module 14 does not have an error condition.
1
Module 14 has an error condition. See the module status 14 register (MDSTAT14) for the error
condition.
0
Reserved
9.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 9-4.
Figure 9-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
186
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9.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 9-5 and described in Table 9-11.
Figure 9-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31
16
Reserved
R-0
15
14
M[15]
M[14]
13
Reserved
0
W-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 9-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit
31-16
15
14
13-0
Field
Reserved
Value
0
M[15]
Reserved
Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 15 register (MDSTAT15).
0
A write of 0 has no effect.
1
A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15.
M[14]
Reserved
Description
Clears the interrupt status bit (M[14]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 14 register (MDSTAT14).
0
A write of 0 has no effect.
1
A write of 1 clears the M[14] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT14.
0
Reserved
9.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 9-6.
Figure 9-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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9.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 9-7 and described in Table 9-12.
Figure 9-7. Power Error Pending Register (PERRPR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
RAM/Pseudo (PD1) power domain interrupt status.
0
RAM/Pseudo power domain does not have an error condition.
1
RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0
Reserved
9.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 9-8 and described in Table 9-13.
Figure 9-8. Power Error Clear Register (PERRCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 9-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit
31-2
1
0
188
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0
A write of 0 has no effect.
1
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0
Reserved
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9.6.9 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 9-9 and described in Table 914.
Figure 9-9. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 9-14. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GO[1]
Description
Reserved
RAM/Pseudo (PD1) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
PDCTL.NEXT for this domain, and MDCTL.NEXT for all the modules residing on this domain). If any of
the NEXT fields are not matching the corresponding current state (PDSTAT.STATE, MDSTAT.STATE),
the PSC will transition those respective domain/modules to the new NEXT state.
GO[0]
Always ON (PD0) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching
the corresponding current state (MDSTAT.STATE), the PSC will transition those respective
domain/modules to the new NEXT state.
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9.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 9-10 and described in Table 915 .
Figure 9-10. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
190
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
RAM/Pseudo (PD1) power domain transition status.
0
No transition in progress.
1
RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
GOSTAT[0]
Always ON (PD0) power domain transition status.
0
No transition in progress.
1
Modules in Always ON power domain are transitioning. Always On power domain is transitioning.
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9.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 9-11 and described in Table 9-16.
Figure 9-11. Power Domain 0 Status Register (PDSTAT0)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Reserved
Emulation alters domain state.
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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9.6.12 Power Domain 1 Status Register (PDSTAT1)
The power domain 1 status register (PDSTAT1) is shown in Figure 9-12 and described in Table 9-17.
Figure 9-12. Power Domain 1 Status Register (PDSTAT1)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Emulation alters domain state.
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
192
Reserved
0
POR
7-5
Description
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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9.6.13 Power Domain 0 Control Register (PDCTL0)
The power domain 0 control register (PDCTL0) is shown in Figure 9-13 and described in Table 9-18.
Figure 9-13. Power Domain 0 Control Register (PDCTL0)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
Reserved
9
EMUIHBIE
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
0-Fh
Power down mode.
0-Eh
Reserved
Fh
11-10
Description
0
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
NEXT
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect
since internally this power domain always remains in the on state.
0
Power domain off.
1
Power domain on.
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9.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 9-14 and described in Table 9-19.
Figure 9-14. Power Domain 1 Control Register (PDCTL1)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
0-Fh
Core off, RAM array retention, RAM periphery off (deep sleep).
Reserved
4h
Core retention, RAM array off, RAM periphery off.
5h
Core retention, RAM array retention, RAM periphery off (deep sleep).
Reserved
8h
Core on, RAM array off, RAM periphery off.
9h
Core on, RAM array retention, RAM periphery off (deep sleep).
Ah
Core on, RAM array retention, RAM periphery off (light sleep).
Bh
Core on, RAM array retention, RAM periphery on.
Fh
EMUIHBIE
Power down mode.
Core off, RAM array off, RAM periphery off.
Ch-Eh
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
1h
6h-7h
9
Reserved
0
2h-3h
11-10
Description
0
Reserved
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
194
NEXT
User-desired power domain next state.
0
Power domain off.
1
Power domain on.
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9.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 9-15 and described in Table 920.
Figure 9-15. Power Domain 0 Configuration Register (PDCFG0)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 9-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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9.6.16 Power Domain 1 Configuration Register (PDCFG1)
The power domain 1 configuration register (PDCFG1) is shown in Figure 9-16 and described in Table 921.
Figure 9-16. Power Domain 1 Configuration Register (PDCFG1)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 9-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
196
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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9.6.17 Module Status n Register (MDSTATn)
The module status n register (MDSTATn) is shown in Figure 9-17 and described in Table 9-22.
Figure 9-17. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
Reserved
MCKOUT
Rsvd
MRST
LRSTDONE
LRST
Reserved
7
6
5
STATE
0
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-22. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in the module control
14 register (MDCTL14) and the module control 15 register (MDCTL15).
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL14 and MDCTL15. If
you desire to generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL14 and
MDCTL15.
Emulation alters module reset. This bit applies to ARM module (module 14) and DSP module
(module 15). This field is 0 for all other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state. If you desire to generate a PSCINT upon this
event, you must set the EMURSTIE bit in the module control 14 register (MDCTL14) and the
module control 15 register (MDCTL15).
0
Reserved
Module clock output status. Shows status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to ARM module (module 14) and DSP module (module 15). This field is 1
for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Reserved
0
LRSTDONE
7-6
Description
Emulation alters module state. This bit applies to ARM module (module 14) and DSP module
(module 15). This field is 0 for all other modules.
EMURST
15-13
9
Value
Module local reset status. This bit applies to ARM module (module 14) and DSP module (module
15).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
Module state status: indicates current module status.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
Indicates transition
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9.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)
The PSC0 module control n register (MDCTLn) is shown in Figure 9-18 and described in Table 9-23.
Figure 9-18. PSC0 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
10
9
8
Reserved
11
EMUIHBIE
EMURSTIE
LRST
7
Reserved
3
2
NEXT
0
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14) and the module control 15 register (MDCTL15), ignoring and bypassing all the
clock stop request handshakes managed by the PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-11
Reserved
10
EMUIHBIE
9
8
Force is disabled.
1
Force is enabled.
0
Reserved
Interrupt enable for emulation alters module state. This bit applies to ARM module (module 14) and
DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
EMURSTIE
Interrupt enable for emulation alters reset. This bit applies to ARM module (module 14) and DSP
module (module 15).
0
Disable interrupt.
1
Enable interrupt.
LRST
7-3
Reserved
2-0
NEXT
198
0
Module local reset control. This bit applies to ARM module (module 14) and DSP module (module 15).
0
Assert local reset
1
De-assert local reset
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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9.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn)
The PSC1 module control n register (MDCTLn) is shown in Figure 9-19 and described in Table 9-24.
Figure 9-19. PSC1 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
3
2
0
Reserved
NEXT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14) and the module control 15 register (MDCTL15), ignoring and bypassing all the
clock stop request handshakes managed by the PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-3
Reserved
2-0
NEXT
0
Force is disabled.
1
Force is enabled.
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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Power Management
Topic
...........................................................................................................................
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
200
Introduction .....................................................................................................
Power Consumption Overview ...........................................................................
PSC and PLLC Overview ...................................................................................
Features ..........................................................................................................
Clock Management ...........................................................................................
ARM Sleep Mode Management ...........................................................................
DSP Sleep Mode Management............................................................................
RTC-Only Mode ................................................................................................
Dynamic Voltage and Frequency Scaling (DVFS)..................................................
Deep Sleep Mode ............................................................................................
Additional Peripheral Power Management Considerations ...................................
Power Management
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201
201
202
203
204
207
209
210
211
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10.1 Introduction
Power management is an important aspect for most embedded applications. For several applications and
target markets, there may be a specific power budget and requirements to minimize power consumption
for both power supply sizing and battery life considerations. Additionally, lower power consumption results
in more optimal and efficient designs from cost, design, and energy perspectives. This device has several
means of managing the power consumption. This chapter discusses the various power management
features.
10.2 Power Consumption Overview
Power consumed by semiconductor devices has two components: dynamic and static. This can be shown
as:
Ptotal = Pdynamic + Pstatic
The dynamic power is the power consumed to perform work when the device is in active modes (clocks
applied, busses, and I/O switching), that is, analog circuits changing states. The dynamic power is defined
by:
Pdynamic = Capacitance × Voltage2 × Frequency
From the above formula, the dynamic power scales with the clock frequency (device/module frequency for
core operations and switching frequency for I/O). Dynamic power can be reduced by controlling the clocks
in such a way as to either operate at a clock setting just high enough to complete the required operation in
the required timeline or to run at a clock setting until the work is complete and then drastically reduce the
clock frequency or cut off the clocks until additional work must be performed.
In the formula, the dynamic power varies with the voltage squared, so the voltage of operations has
significant impact on overall power consumption and, thus, on the battery life. Dynamic power can be
reduced by scaling the operating voltage, when the performance requirements are not that high and the
device can be operated at a corresponding lower frequency.
The capacitance is the capacitance of the switching nodes, or the load capacitances on the switching I/O
pins.
The static power, as the name suggests, is independent of the switching frequency of the logic. It can be
shown as:
Pstatic = f(leakage current)
It is essentially a function of the “leakage”, or the power consumed by the logic when it is not switching or
is not performing any work. Leakage current is dependent mostly on the manufacturing process used, the
size of the die, etc. Leakage current is unavoidable while power is applied and scales roughly with the
operating junction temperatures. Leakage power can only be avoided by removing power completely from
a device or subsystem. The static power consumption plays a significant role in the Standby Modes (when
the application is not running and in a dormant state) and plays an important role in the battery life for
portable applications, etc.
10.3 PSC and PLLC Overview
The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling
of the clocks to the core and various peripheral modules. The PSC provides a granular support to turn
on/off clocks on a module by module basis. Similarly, the two PLL controllers (PLLC0 and PLLC1) play an
important role in device and module clock generation, and manage the frequency scaling operations for
the device. Together these modules play a significant role in managing the clocks from a power
management feature standpoint. For detailed information on the PSC, see the Power and Sleep Controller
(PSC) chapter. For detailed information on the PLLC0 and PLLC1, see the Device Clocking chapter and
the Phase-Locked Loop Controller (PLLC) chapter.
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10.4 Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 10-1 describes the power management features.
Table 10-1. Power Management Features
Power Management
Description
Features
PLL bypass and powerdown
Both PLLs can be powered-down and run in
bypass mode when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON
Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic power consumption of the
core and I/O (if any free running I/O clocks).
ARM subsystem
sleep modes
The ARM CPU can be put in sleep mode.
Additionally, the ARM subsystem clock can be
completely gated when not in use.
Reduces the dynamic power consumption.
DSP subsystem
sleep mode
The DSP CPU can be put in sleep (IDLE) mode.
Additionally, the DSP subsystem clock can be
completely gated when not in use.
Reduces the dynamic power consumption.
RTC-only mode
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Dynamic Voltage and
Frequency Scaling
(DVFS)
The operating voltage and frequency of the device
can be dynamically scaled to meet the
requirements of the application.
Clock Management
Core Sleep Management
Voltage Management
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Dynamic Voltage and Frequency Scaling
Reduces the dynamic power consumption of the
core and I/O as well as standby power
System/Device Sleep Management
Deep Sleep Mode
All internal clocks of the device can be turned
on/off at the OSCIN level. The deep sleep function
can be controlled externally through the
DEESLEEP pin or internally through the
RTC_ALARM pin.
Reduces the dynamic power consumption of the
core and I/O.
USB PHY power-down
The USB2.0 PHY can be powered-down.
Minimizes the USB2.0 I/O power consumption
when not in use.
DDR2/mDDR selfrefresh mode
Allows memory to retain its contents while the rest
of the system is powered down.
mDDR and DDR2 can be clock gated to reduce the
dynamic power consumption or the entire device
can be powered down to reduce the static power
consumption.
SATA PHY power-down
The SATA PHY can be placed in standby mode.
Minimizes the SATA I/O power consumption when
not in use.
LVCMOS I/O buffer
receiver disable
LVCMOS I/O buffer receivers are disabled.
Minimizes the I/O power consumption.
Internal pull-up and pulldown resistor control
The internal pull-ups and pull-downs are
enabled/disabled by groups.
Reduces the I/O leakage power.
Peripheral I/O Power Management
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10.5 Clock Management
10.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
NOTE: To preserve the state of the module, the module state in the PSC must be set to Disable. In
this state, the module reset is not asserted and only the module clock is turned off.
Furthermore, special consideration must be given to DSP/ARM clock on/off. The procedure to turn the
core clock on/off is further described in Section 10.7.4.
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module, when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
10.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
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10.5.3 PLL Bypass and Power Down
You can bypass each PLL in this device. Bypassing the PLL sends a bypass clock instead of the PLL
VCO output (PLLOUT) to the system clocks of the PLLC. For PLLC0, the bypass clock is selected from
either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. For PLLC1, the bypass clock is always
OSCIN. The OSCIN frequency is typically, at most, up to 50 MHz.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. This can lower the
overall dynamic power consumption, which is linearly proportional to the frequency.
When the PLL controller is placed in bypass mode, the PLL retains its frequency lock. This allows you to
switch between bypass mode and PLL mode without having to wait for the PLL to relock. However,
keeping the PLL locked consumes power. You can also power-down the PLL when bypassing it to
minimize the overall power consumed by the PLL module. The advantage of bypassing the PLL without
powering it down is that you do not have to incur the PLL lock time when switching back to a normal
operating level.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
10.6 ARM Sleep Mode Management
10.6.1 ARM Wait-For-Interrupt Sleep Mode
The ARM module can be put into a low-power state using a special sleep mode called wait-for-interrupt
(WFI). When the wait-for-interrupt mode is enabled, all internal clocks within the ARM9 module are shut
off, the core is completely inactive and only resumes operation after receiving an interrupt. This is a
feature for dynamic power management of the ARM processor itself, it does not impact the static power.
NOTE: To enable the WFI mode, the ARM needs to be in supervisor mode.
You can enable the WFI mode via the CP15 register #7 using the following instruction:
• MCR p15, #0, <Rd>, c7, c0, #4
Once the ARM module transitions into the WFI mode, it will remain in this state until an interrupt request
(IRQ/FIQ) occurs.
The following sequence exemplifies how to enter the WFI mode:
• Enable any interrupt (for example, an external interrupt) that you plan to use as the wake-up interrupt
to exit from the WFI mode.
• Enable the WFI mode using the following CP15 instruction:
– MCR p15, #0, r3, c7, c0, #4
The following sequence describes the procedure to wake-up from the WFI mode:
• To wake-up from the WFI mode, trigger any enabled interrupt (for example, an external interrupt).
• The ARM’s PC jumps to the IRQ/FIQ vector and you must handle the interrupt in an interrupt service
routine (ISR).
Exit the ISR and continue normal program execution starting from the instruction immediately following the
instruction that enabled the WFI mode.
NOTE: The ARM interrupt controller (AINTC) and the module sourcing the wake-up interrupt (for
example, GPIO or watchdog timer) must not be disabled, or the device will never wake up.
For more information on this sleep mode, see the ARM926EJ-S Technical Reference Manual
(TRM), downloadable from http://infocenter.arm.com/help/index.jsp.
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10.6.2 ARM Clock OFF
The software must be structured such that no peripheral is allowed to access the ARM resources before
disabling the clocks to the ARM subsystem. The ARM must check for the completion of all its master
peripheral initiated requests (that is, CFG and DMA port operations, etc.). The DSP must check for the
completion of all transactions initiated by it and the peripherals controls by the DSP to the ARM resources.
ARM module clock off sequence:
1. The DSP stops all masters from accessing the ARM and ARM memory.
2. The DSP polls all masters for write-completion status (or wait n number of cycles, if the transfer
completion status is not implemented).
3. The ARM must have the ARM Clock Stop Request interrupt (ARMCLKSTOPREQ, ARM interrupt # 90)
enabled and the associated interrupt service routine (ISR) set up before the DSP initiates the following
ARM clock shutdown procedure.
(a) Initiate the ARM clock off sequence by issuing the ARM clock stop command (PSC DISABLE
Command) to the ARM subsystem by writing a 2h to the NEXT bit field in the ARM local power
sleep controller (LPSC) module control register (PSC0.MDCTL14).
(b) Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power
domain transition command register (PSC0.PTCMD) to start the state transition sequence for the
ARM module. This generates the ARMCLKSTOPREQ interrupt to the ARM.
(c) Check (poll for 0) the GOSTAT[0] bit in the power domain transition status register (PSC0.PTSTAT)
for power transition sequence completion. The GOSTAT[0] bit transitions to 0 when the ARM
executes the wait-for-interrupt instruction from inside its interrupt service routine (ISR).
(d) Check (poll for 2h) the STATE bit field in the ARM LPSC module status register
(PSC0.MDSTAT14) indicating the ARM clock stop sequence completion (STATE: Disable).
The following sequence should be executed by the ARM within the ARM Clock Stop Request interrupt
ISR:
1. Check for completion of all ARM master requests (the ARM polls transfer completion statuses of all
Master peripherals).
2. Enable the interrupt to be used as the “wake-up” interrupt (for example, one of the CHIPSIG interrupts
controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module
chapter—CHIPSIG[0], CHIPSIG[1], etc.) that will be used to wake-up the ARM during the ARM clockon sequence.
3. Execute the wait-for-interrupt (WFI) ARM instruction.
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10.6.3 ARM Subsystem Clock ON
The ARM module defaults to the SwRstDisable state; therefore, the DSP side software is responsible for
enabling the clock and releasing the reset to the ARM at power-on reset. If the DSP has put the ARM in
the clock off/Disable state, the following clock on sequence is applicable only when it is required to wakeup the ARM. Perform the following sequence for the DSP to enable clocks to the ARM:
1. Wait for the GOSTAT[0] bit in the power domain transition status register (PSC0.PTSTAT) to clear to
0. You must wait for the power domain to finish any previously initiated transitions before initiating a
new transition.
2. Write a 3h to the NEXT bit in the ARM local power sleep controller (LPSC) module control register
(PSC0.MDCTL14) to prepare the ARM module for an enable transition.
3. Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power
domain transition command register (PSC0.PTCMD) to start the state transition sequence for the ARM
module.
4. Check (poll for 0) the GOSTAT[0] bit in PSC0.PTSTAT for power transition sequence completion. The
domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0.
5. Wait for the STATE bit field in the ARM LPSC module status register (PSC0.MDSTAT14) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
NOTE: This only applies if you are transitioning from the Disable state. If previously in the Disable
state, a wake-up interrupt must be triggered in order to wake the ARM (to exit the wait-forinterrupt mode). This example assumes that the ARM enabled this interrupt before entering
its wait-for-interrupt sleep mode state.
For the DSP to wake the ARM if transitioning from the Disable state, trigger an ARM interrupt that has
previously been configured as a wake-up interrupt.
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10.7 DSP Sleep Mode Management
10.7.1 DSP Sleep Modes
The C674x megamodule has an internal power down controller (PDC) module that provides additional
power management features in addition to clock management control provided by the device-level power
and sleep controller (PSC) module. For information on the PDC module, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
10.7.2 C674x DSP CPU Sleep Mode
The DSP CPU can be put in a low-power state by executing the IDLE instruction. For information on the
IDLE instruction, see the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8).
10.7.3 C674x Megamodule Sleep Mode
The IDLE instruction is used as part of the procedure for shutting down the entire C674x megamodule, by
the power-down controller (PDC) module. In shutting down the entire C674x megamodule, the PDC can
internally clock gate off the following components of the megamodule and internal memories of the DSP
subsystem:
• C674x CPU
• Level 1 Program Memory Controller (PMC)
• Level 1 Data Memory Controller (DMC)
• Level 2 Unified Memory Controller (UMC)
• Extended Memory Controller (EMC)
• L1P Memory
• L1D Memory
• L2 Memory
Putting the entire C674x megamodule into the low-power sleep mode is typically more useful and saves a
lot more power, as compared to just executing the IDLE instruction to put only the CPU in idle mode.
For information on putting the C674x megamodule in the low-power mode using the PDC, see the
TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
10.7.4 C674x Megamodule Clock ON/OFF
The C674x megamodule can clock gate its own components to save power. Additional power saving can
be achieved by stopping the clock sourced (PLL output) to the C674x megamodule by programming the
power and sleep controller (PSC) module to place the megamodule in the Disable state. The DSP cannot
perform this programming task on its own, because the DSP will not be able to complete the PSC
programming sequence if its clock source is gated in the middle of the process.
If additional power saving is desired (more then just power savings obtained by using the power down
controller), then you can choose to disable the clock to the DSP using the PSC. The ARM is responsible
for programming the PSC to disable the clock going to the C674x megamodule at the root level (stopping
PLL0_SYSCLK1 at the PLL output). By clock gating the megamodule at the root, this enables saving
additional clock tree power (for the path from the PLL to the megamodule boundary). The ARM is also
responsible for programming the PSC to enable the C674x megamodule.
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10.7.4.1 C674x Megamodule Clock OFF
The software must be structured such that no peripheral is allowed to access the DSP resources before
disabling the DSP clocks. The DSP must check for the completion of all its master peripheral initiated
requests (that is, IDMA, MDMA, EDMA, cache operations, etc.). The ARM must check for the completion
of all transactions initiated by it and the peripherals controls by it to the DSP resources.
1. The ARM stops all masters from accessing the DSP and DSP memory.
2. The ARM polls all masters for write-completion status (or wait n number of cycles, if the transfer
completion status is not implemented).
3. The DSP must have the power-down controller interrupt PDC_INT (DSP interrupt #118) enabled and
the PDC interrupt service routine (ISR) set up before the ARM initiates the following DSP clock
shutdown procedure.
(a) Initiate the DSP clock off sequence by issuing the DSP clock stop command (PSC DISABLE
Command) to the DSP subsystem by writing a 2h to the NEXT bit field in the DSP local power
sleep controller (LPSC) module control register (PSC0.MDCTL15).
(b) Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP
module. This generates the PDC_INT interrupt to the DSP.
(c) Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT)
for power transition sequence completion. The GOSTAT[1] bit transitions to 0 when the DSP
executes the IDLE instruction from inside its interrupt service routine (ISR).
(d) Check (poll for 2h) the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15)
indicating the DSP clock stop sequence completion (STATE: Disable).
The following sequence should be executed by the DSP within the PDC interrupt ISR:
1. Check for completion of all DSP master requests (the DSP polls transfer completion statuses of all
Master peripherals).
2. Enable the interrupt to be used as “wake-up” interrupt (for example, one of the CHIPSIG interrupts
controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module
chapter—CHIPSIG[2], CHIPSIG[3], or CHIPSIG[4]/NMI interrupt) that will be used to wake-up the DSP
during the DSP clock-on sequence.
NOTE: The power-down command register (PDCCMD) in the power-down controller (PDC) can only
be written while the DSP is in Supervisor mode.
3. Write a 0001 5555h to PDCCMD.
4. Execute the IDLE instruction.
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10.7.4.2 C674x Megamodule Clock ON
The C674x megamodule defaults to the Enable state; therefore, the DSP subsystem clock is on, and the
following sequence is typically not needed. This clock on sequence is only required to wake-up the DSP, if
the ARM put the DSP in a clock off state. Perform the following sequence for the ARM to enable clocks to
the DSP:
1. Wait for the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) to clear to
0. You must wait for the power domain to finish any previously initiated transitions before initiating a
new transition.
2. Write a 3h to the NEXT bit field in the DSP local power sleep controller (LPSC) module control register
(PSC0.MDCTL15) to prepare the DSP module for an enable transition.
3. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP module.
4. Check (poll for 0) the GOSTAT[1] bit in PSC0.PTSTAT for power transition sequence completion. The
domain is only safely in the new state after the GOSTAT[1] bit is cleared to 0.
5. Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
NOTE: This only applies if you are transitioning from the Disable state. If previously in the Disable
state, a wake-up interrupt must be triggered in order to wake the DSP. This example
assumes that the DSP enabled this interrupt before entering its IDLE state. See the DSP
Subsystem chapter for more information on DSP interrupts.
For the ARM to wake the DSP if transitioning from the Disable state, trigger a DSP interrupt that has
previously been configured as a wake-up interrupt.
10.8 RTC-Only Mode
In real-time clock (RTC)-only mode, the RTC is powered on and the rest of the device is completely
powered off (all supplies except the RTC supply are removed). In this mode, the RTC is fully functional
and keeps track of date, hours, minutes, and seconds. In this mode, the overall power consumption would
be significantly lower, as voltage from the rest of the core and I/O logic can be completely removed,
eliminating most of the active and static power of the device, except for what is consumed by the RTC
module, running at 32 kHz.
NOTE: To put the device in RTC-only mode, there is no software control sequence. You can put the
device in the RTC-only mode by removing the power supply from all core and I/O logic,
except for the RTC core logic supply (RTC_CVDD). During wake up, all power sequencing
requirements described in the device-specific data manual must be followed.
Some limitations apply in the RTC-only mode. First, the RTC_ALARM pin is not available as an option for
use as a control to signal an external power supply to reapply power to the rest of the device. This is
because the RTC_ALARM pin is powered by the I/O supply that is powered down in RTC-only mode.
Second, in RTC-only mode, only the RTC register contents are preserved, all other internal memory and
register contents are lost. Mobile DDR and DDR2 contents can be preserved through the use of selfrefresh (see Section 10.10.2). However, software must be in place to restore the context of the device, for
example, reinitialize internal registers, setup cache memory configurations, interrupt vectors, etc.
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10.9 Dynamic Voltage and Frequency Scaling (DVFS)
Dynamic voltage and frequency scaling (DVFS) consists of minimizing the idle time of the system. The
DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a task to be
performed in the required amount of time. This reduces the total power consumption of the device while
still meeting task requirements. DVFS requires control over the clock frequency and the operating voltage
of the device elements. By intelligently switching these elements to their optimal operating points, it is
possible to minimize the power consumption of the device for a given task.
For reasons related to the device (clock architecture, process, etc.), DVFS is used only for a few discrete
steps, not over a continuum of voltage and frequency values. Each step, or operating performance point
(OPP), is composed of a voltage and frequency pair. For an OPP, the frequency corresponds to the
maximum frequency allowed at a voltage, or reciprocally; the voltage corresponds to the minimum voltage
allowed for a frequency. See your device data manual for a list of the OPPs supported by the device.
When applying DVFS, a processor or system always runs at the lowest OPP that meets the performance
requirement at a given time. You determine the optimal OPP for a given task and then switch to that OPP
to save power.
10.9.1 Frequency Scaling Considerations
The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1).
Through a series of multipliers and dividers you can change the frequencies of various clocks throughout
the device. See the Device Clocking chapter for information on the clock architecture of the device and
see the Phase-Locked Loop Controller (PLLC) chapter for information on the PLL controllers. A few things
must be noted when changing the various internal frequencies of the device:
• Changing the SYSCLK frequency
The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier. A series of dividers
divide PLLOUT to generate the various device SYSCLKs.
To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK
divider ratio. When changing the PLL multiplier, you must put the PLL controller in bypass mode while
the PLL multiplier value is modified and a lock on the new frequency is reached. The lock time is given
in the device data manual. When changing the divider ratios it is not required to put the PLL controller
in bypass mode.
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the
PLL. However, the SYSCLK frequency will depend solely on the divider ratios used.
• SYSCLK domain fixed ratios
Certain SYSCLK domains need to operate at a fixed ratio with respect to the CPU clock. Care should
be taken to ensure that these fixed ratios are maintained. For additional details, see the Device
Clocking chapter.
• PLLC0 bypass clock
When switching the PLL multiplier, the PLL controller must be placed in bypass mode. Bypassing the
PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of
the PLL controller.
For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or
PLL1_SYSCLK3. For PLLC1, the bypass clock is always OSCIN. The OSCIN frequency is typically, at
most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity.
It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved
bandwidth during frequency scaling transitions. For this reason, the PLLC0 bypass clock can be set to
PLL1_SYSCLK3. This selection is made through the EXTCLKSRC bit in the PLLCTL register of
PLLC0.
• Peripheral immunity from CPU clock frequency changes
Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency.
The PLL0_AUXCLK is derived from OSCIN.
Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2.
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Furthermore, PLL0_SYSCLK2 must always be /2 of the CPU clock frequency. To keep these
peripherals immune from changes in PLL0 frequency (such as when the CPU frequency is modified),
you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. PLL1 is mainly used to
clock the DDR2/mDDR memory controller.
When peripherals are immune to changes in the CPU clock frequency, their internal clock dividers do
not have to be adjusted for changes in their input clock frequencies.
10.9.2 Voltage Scaling Considerations
The operating voltage of the device must be totally controlled through mechanisms outside the device. I2C
ports on the device can be used to communicate with external power management chips. A few things
must be noted when changing the operating voltage of the device:
• Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating
performance point (OPP) transitions. See the device data manual for ramp rate specifications.
• Switching to a lower voltage: When switching to a lower voltage, the maximum operating frequency
changes. Care must be taken such that the maximum operating frequency supported at the new
voltage is not violated. For this reason, it is recommended to change the operating frequency before
switching the operating voltage.
10.10 Deep Sleep Mode
This device supports a Deep Sleep mode where all device clocks are stopped and the on-chip oscillator is
shut down to save power. Registers and memory contents are preserved, thus, upon recovery, the
program may continue from where it left off with minimal overhead involved.
The Deep Sleep mode is initiated when the DEEPSLEEP pin is driven low. The device wakes up from
Deep Sleep mode when the DEEPSLEEP pin is driven high. The DEEPSLEEP pin can be driven by an
external controller or it can be driven internally by the real-time clock (RTC). The RTC method allows for
automatic wake-up at a programmed time.
NOTE: Due to pin multiplexing, the DEEPSLEEP pin can only be driven by an external controller or
its internal real-time clock (RTC). The DEEPSLEEP pin cannot be driven by both an external
controller and its internal real-time clock at the same time.
10.10.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
10.10.1.1 Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep mode if an external signal is used to wake-up the
device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The SATA PHY should be disabled (see Section 10.11.3).
3. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 10.11.1).
4. The USB1.1 (USB1) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 10.11.1).
5. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
6. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
7. Configure the DEEPSLEEP pin as input-only using the PINMUX0_31_28 bits in the PINMUX0 register
in the System Configuration (SYSCFG) Module chapter.
8. The external controller should drive the DEEPSLEEP pin high (not in Deep Sleep).
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9. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
10. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
11. Begin polling the SLEEPCOMPLETE bit until it is set to 1. This bit is set once the device is woken up
from Deep Sleep mode.
12. The external controller drives the DEEPSLEEP pin low to initiate Deep Sleep mode.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.1.2 Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if an external signal is used to wake-up the
device:
1. The external controller drives the DEEPSLEEP pin high.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 8.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
10.10.2.1 Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep state if the RTC is used to wake-up the device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The SATA PHY should be disabled (see Section 10.11.3).
3. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 10.11.1).
4. The USB1.1 (USB1) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 10.11.1).
5. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
6. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
7. Configure the desired wake-up time as an alarm in the RTC.
8. Configure the DEEPSLEEP/RTC_ALARM pin to output RTC_ALARM using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. The pin is driven low
since the alarm has not yet occurred.
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9. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
10. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
Also, the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.2.2 Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if the RTC is used to wake-up the device:
1. The RTC alarm occurs and the RTC_ALARM pin is driven high (which is internally connected to the
DEEPSLEEP pin). This causes the Deep Sleep logic to exit the Deep Sleep mode.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 8.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.3 Deep Sleep Sequence
Figure 10-1 illustrates the Deep Sleep sequence:
1. Software sets the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System
Configuration (SYSCFG) Module chapter.
2. The DEEPSLEEP pin is driven low by either an external device or the RTC_ALARM pin. The Deep
Sleep mode begins.
3. The PLL controller reference clock is gated.
4. The on-chip oscillator is disabled. If the device is being clocked by an external source, this clock may
stay enabled; the power savings from turning off this clock is minimal.
5. The DEEPSLEEP pin is driven high and the on-chip oscillator is enabled.
6. The Deep Sleep counter beings counting valid clock cycles.
7. The count has reached the number specified in the SLEEPCOUNT bit field and the
SLEEPCOMPLETE bit is set. The PLL reference clock is enabled and the Deep Sleep mode ends.
8. Software clears the SLEEPENABLE bit. The SLEEPCOMPLETE bit is automatically cleared.
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Figure 10-1. Deep Sleep Mode Sequence
See Note:
1
2
3
4
5
6
7
8
SLEEPENABLE
(internal)
DEEPSLEEP
CLKGATE
(internal)
PLLC Ref Clk
(internal)
OSC_GZ
(internal)
OSCIN
SLEEPCOMPLETE
(internal)
10.10.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking
Entering the Deep Sleep mode stops all of the clocks to the device so it is the responsibility of the
software to ensure that all peripheral accesses have been completed and peripheral interfaces
appropriately configured for clocks to stop. Therefore, before an external controller drives the
DEESPLEEP pin, a handshaking mechanism must be in place to give software time to prepare the device
for Deep Sleep mode. The implementation of the handshake mechanism is up to the system designer.
10.10.4.1 Entering Deep Sleep Mode
The following example sequence can be used to activate the Deep Sleep mode using a handshaking
mechanism between your device and an external device:
1. Clear the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter to 0. The DEEPSLEEP pin has no effect until software running on the
device sets this bit.
2. Configure the GP0[8]/DEEPSLEEP/RTC_ALARM pin to output GP0[8] using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. When the pin is
configured for GPIO functionality, the internal DEEPSLEEP signal is still driven by the value on the pin.
3. Configure the GP0[8] pin to generate interrupts on the falling edge of the GPIO signal.
4. An external device drives the GP0[8] pin low.
5. Software prepares the device for Deep Sleep mode.
6. Set the SLEEPENABLE bit in DEEPSLEEP to 1. The Deep Sleep mode is immediately started and all
device clocks are stopped. Also, the SLEEPCOMPLETE bit is automatically cleared.
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10.10.4.2 Exiting Deep Sleep Mode
To exit the Deep Sleep mode, follow this sequence:
1. An external device drives the GP0[8] pin high.
2. The device exits the Deep Sleep mode. When the SLEEPCOUNT delay is complete, the Deep Sleep
logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register
(DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.
10.11 Additional Peripheral Power Management Considerations
This section lists additional power management features and considerations that might be part of other
chip-level or peripheral logic, apart from the features supported by the core, PLL controller (PLLC), and
power and sleep controller (PSC).
10.11.1 USB PHY Power Down Control
The USB modules can be clock gated using the PSC; however, this does not power down/clock gate the
PHY logic. You can put the USB2.0 PHY and OTG module in the lowest power state, when not in use, by
writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the Chip Configuration 2 Register
(CFGCHIP2) in the System Configuration (SYSCFG) Module chapter.
NOTE: If the USB1.1 subsystem is used and the 48 MHz clock input is sourced from the
USB2.0 PHY, then the USB2.0 PHY should not be powered down.
10.11.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode
The DDR2/mDDR memory controller supports different methods for reducing its power consumption
including self-refresh mode, power-down mode, and clock gating. Additionally, the DDR2/mDDR memory
controller DLL, PHY, and the receivers at the I/O pins can be disabled. Even if the PHY is active, the
receivers can be configured to disable whenever writes are in progress and the receivers are not needed.
Self-refresh mode can be used to preserve the contents of DDR2/mDDR memory when the DDR2/mDDR
memory controller is clock gated or when the device is placed in RTC-only mode. However, in the RTConly mode, care must be taken to correctly take the DDR2/mDDR out of self-refresh mode.
NOTE: To preserve the contents of the external memory while the DDR2/mDDR memory controller
is clock gated, its self-refresh mode must be enabled before the DDR2/mDDR memory
controller clock is turned off.
In RTC-only mode, all portions of the device except for the RTC are powered down, including the
DDR2/mDDR memory controller. During power-up, the DDR2/mDDR memory controller defaults to its
reset state. When the DDR2/mDDR memory controller is taken out of reset, it automatically runs its
memory initialization routine; the self-refresh state of the memory is ignored. This hardware sequence
cannot be stopped by software running on the device.
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To correctly take the memory out of self-refresh after coming back from RTC-only mode, follow these
steps:
1. Before going into RTC-only mode, disconnect the DDR2/mDDR memory controller CKE output pin
from the memory; ensure the memory’s CKE input pin continues to be driven low.
2. After coming back from RTC-only mode, configure the device to the desired operating state.
3. Program the DDR2/mDDR memory controller following the normal sequence.
4. Enable the self-refresh mode of the DDR2/mDDR memory controller.
5. Connect the DDR2/mDDR memory controller CKE output pin to the memory.
6. Disable the self-refresh mode of the DDR2/mDDR memory controller.
After this sequence, the DDR2/mDDR memory controller is ready for use. Note that hardware logic is
needed to disconnect the CKE output pin from the memory and to drive the memory’s CKE input pin low.
For more details on the power management features of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.11.3 SATA PHY Power Down
The SATA PHY supports a standby power mode that yields significant power reduction during periods in
which the PHY is not used. In applications in which the SATA is not used at all, the power supply to the
SATA PHY can be left unconnected.
10.11.4 LVCMOS I/O Buffer Receiver Disable
This device supports two types of LVCMOS I/Os: 1.8V I/Os and low-static current dual-voltage I/Os that
operate at either 1.8V or 3.3V. The receivers on the LCVMOS I/Os are enabled and disabled by software
(see the RXACTIVE Control Register (RXACTIVE) in the System Configuration (SYSCFG) Module
chapter). In the event that certain receivers are not used (such as in a low-power state), they can be
disabled to conserve power.
10.11.5 Pull-Up/Pull-Down Disable
In general, you must ensure that all input pins are always pulled to a logic-high or a logic-low voltage level.
A floating input pin can consume a small amount of I/O leakage current. The I/O leakage current can be
greatly multiplied in the case of several floating inputs pins.
This device includes internal pull-up and pull-down resistors that prevent floating input pins. These internal
resistors are generally very weak and their use is intended for pins that are not connected on the board
design. For pins that are connected, external pull-up and pull-down resistors are recommended.
When an input pin is externally driven to a valid logic level, through an external pull-up resistor or by an
external device for example, it is recommended to disable the internal resistor. Opposing an internal pullup or pull-down resistor can consume a small amount of current. Internal resistors are disabled through
the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module chapter.
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System Configuration (SYSCFG) Module
Topic
11.1
11.2
11.3
11.4
11.5
...........................................................................................................................
Introduction .....................................................................................................
Protection ........................................................................................................
Master Priority Control ......................................................................................
Interrupt Support ..............................................................................................
SYSCFG Registers ............................................................................................
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11.1 Introduction
The system configuration (SYSCFG) module is a system-level module containing status and top level
control logic required by the device. The system configuration module consists of a set of memorymapped status and control registers, accessible by the CPU, supporting all of the following system
features, and miscellaneous functions and operations.
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device Boot Configuration Status
• Master Priority Control
– Controls the system priority for all master peripherals (including EDMA3TC)
• Emulation Control
– Emulation suspend control for peripherals that support the feature
• Special Peripheral Status and Control
– Locking of PLL control settings
– Default burst size configuration for EDMA3 transfer controllers
– Event source selection for the eCAP peripheral input capture
– McASP0 AMUTEIN selection and clearing of AMUTE
– USB PHY Control
– Clock source selection for EMIFA and DDR2/mDDR
– HPI Control
• ARM-DSP Integration
– On-chip inter-processor interrupts and status for signaling between ARM and DSP
The system configuration module controls several global operations of the device; therefore, the module
supports protection against erroneous and illegal accesses to the registers in its memory-map. The
protection mechanisms that are present in the module are:
• A special key sequence that needs to be written into a set of registers in the system configuration
module, to allow write ability to the rest of registers in the system configuration module.
• Several registers in the module are only accessible when the CPU requesting read/write access is in
privileged mode.
11.2 Protection
The SYSCFG module controls several global operations of the device; therefore, it has a protection
mechanism that prevents spurious and illegal accesses to the registers in its memory map. The protection
mechanism enables accesses to these registers only if certain conditions are met.
11.2.1 Privilege Mode Protection
The CPU supports two privilege levels: Supervisor and User. Several registers in the SYSCFG memorymap can only be accessed when the accessing host (CPU or master peripheral) is operating in privileged
mode, that is, in Supervisor mode. The registers that can only be accessed in privileged mode are listed in
Section 11.5. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) and the
ARM926EJ-S Technical Reference Manual (TRM), downloadable from
http://infocenter.arm.com/help/index.jsp for details on privilege levels.
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11.2.2 Kicker Mechanism Protection
NOTE: The Kick registers are disabled in silicon revision 2 and later. The SYSCFG registers are
always unlocked and writes to the Kick registers have no functional effect.
The Kick registers (KICK0R and KICK1R) can only be accessed in privileged mode (the host
needs to be in Supervisor mode). Any number of accesses may be performed to the
SYSCFG module, while the module is unlocked.
The SYSCFG module remains unlocked after the unlock sequence, until locked again.
Locking the module is accomplished by writing any value other then the key values to either
KICK0R or KICK1R.
To access any registers in the SYSCFG module, it is required to follow a special sequence of writes to the
Kick registers (KICK0R and KICK1R) with correct key values. Writing the correct key value to the kick
registers unlocks the registers in the SYSCFG memory-map. In order to access the SYSCFG registers,
the following unlock sequence needs to be executed in software:
1. Write the key value of 83E7 0B13h to KICK0R.
2. Write the key value of 95A4 F1E0h to KICK1R.
After steps 1 and 2, the SYSCFG module registers are accessible and can be configured as per the
application requirements.
11.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the ARM, DSP, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or
EDMA3 for initiating the data transfer to/from them. In order to determine allowed connection between
masters and slave, each master request source must have a unique master ID (mstid) associated with it.
The master ID is shown in Table 11-1. See the device-specific data manual to determine the masters
present on your device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 11-2. Application software is expected to modify these values
to obtain the desired performance.
Table 11-1. Master IDs
Master ID
Peripheral
0
ARM - Instruction
1
ARM - Data
2
DSP MDMA
3
DSP CFG
4-7
Reserved
8
PRU0
9
PRU1
10
EDMA3_0_CC0
11
EDMA3_1_CC0
12-15
Reserved
16
EDMA3_0_TC0 - read
17
EDMA3_0_TC0 - write
18
EDMA3_0_TC1 - read
19
EDMA3_0_TC1 - write
20
EDMA3_1_TC0 – read
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Table 11-1. Master IDs (continued)
Master ID
21
22-33
Peripheral
EDMA3_1_TC0 – write
Reserved
34
USB2.0 CFG
35
USB2.0 DMA
36
Reserved
37
HPI
38
EMAC
39
USB1.1
40-65
Reserved
66
uPP
67
SATA
68
VPIF DMA0
69
VPIF DMA1
70-95
96
97-255
Reserved
LCDC
Reserved
Table 11-2. Default Master Priority
Master
Default Priority (1)
Master Priority Register
PRU0
0
MSTPRI1
PRU1
0
MSTPRI1
EDMA3_0_TC0 (2)
0
MSTPRI1
EDMA3_0_TC1 (2)
0
MSTPRI1
ARM - Instruction
2
MSTPRI0
ARM - Data
2
MSTPRI0
DSP MDMA (3)
2
MSTPRI0
DSP CFG
(3)
2
MSTPRI0
SATA
4
MSTPRI0
uPP
4
MSTPRI0
EDMA3_1_TC0 (2)
4
MSTPRI1
VPIF DMA0
4
MSTPRI1
VPIF DMA1
4
MSTPRI1
EMAC
4
MSTPRI2
USB2.0 CFG
4
MSTPRI2
USB2.0 DMA
4
MSTPRI2
USB1.1
4
MSTPRI2
(4)
5
MSTPRI2
6
MSTPRI2
LCDC
HPI
(1)
(2)
(3)
(4)
220
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
The priority for EDMA3_0_TC0, EDMA3_0_TC1, and EDMA3_1_TC0 is configurable through fields in the master priority 1
register (MSTPRI1), not the EDMA3CC QUEPRI register.
The priority for DSP MDMA and DSP CFG is controlled by fields in the master priority 0 register (MSTPRI0) and not
DSP.MDMAARBE.PRI (DSP Bandwidth manager module).
LCDC traffic is typically real-time sensitive, therefore, the default priority of 5, which is lower as compared to the default priority of
several masters, is not recommended. You should reconfigure the LCDC priority to the highest or equal to other high-priority
masters in an application to ensure that the throughput/latency requirements for the LCDC are met.
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11.4 Interrupt Support
11.4.1 Interrupt Events and Requests
The SYSCFG module generates two interrupts: an address error interrupt (BOOTCFG_ADDR_ERR) and
a protection interrupt (BOOTCFG_PROT_ERR). The BOOTCFG_ADDR_ERR is generated when there is
an addressing violation due to an access to a non-existent location in the SYSCFG register space. The
BOOTCFG_PROT_ERR interrupt is generated when there is a protection violation of either in the defined
ranges or to the SYSCFG registers. It is required to write a value of 0 to the end of interrupt register (EOI)
after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of completion
of the SYSCFG interrupt so that the module can reliably generate subsequent interrupts.
The transfer parameters that caused the violation are saved in the fault address register (FLTADDRR) and
the fault status register (FLTSTAT).
11.4.2 Interrupt Multiplexing
The interrupts from the SYSCFG module are combined with the interrupts from the MPU module into a
single interrupt called MPU_BOOTCFG_ERR. The combined interrupt is routed to the ARM and DSP
interrupt controllers.
11.4.3 ARM-DSP Communication Interrupts
The SYSCFG module also has a set of registers, the chip signal register (CHIPSIG) and the chip signal
clear register (CHIPSIG_CLR), to facilitate interprocessor communication. This is generally used to allow
the ARM and the DSP to coordinate. For example, the ARM may interrupt the DSP when it is ready to
have the DSP process some data buffer in shared memory. A typical sequence, often referred to as ARMDSP communication, is as follows:
1. ARM writes command in shared memory.
2. ARM interrupts DSP.
3. DSP responds to interrupt and reads command in shared memory.
4. DSP executes a task based on the command.
5. DSP interrupts ARM upon completion of the task.
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other
processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller.
11.5 SYSCFG Registers
Table 11-3 lists the memory-mapped registers for the system configuration module 0 (SYSCFG0) and
Table 11-4 lists the memory-mapped registers for the system configuration module 1 (SYSCFG1). These
tables also indicate whether a particular register can be accessed only when the CPU is in privileged
mode.
Table 11-3. System Configuration Module 0 (SYSCFG0) Registers
Address
Acronym
Register Description
Access
01C1 4000h
REVID
Revision Identification Register
—
Section 11.5.1
01C1 4008h
DIEIDR0 (1)
Die Identification Register 0
—
—
01C1 400Ch
DIEIDR1 (1)
Die Identification Register 1
—
—
01C1 4010h
DIEIDR2
(1)
Die Identification Register 2
—
—
01C1 4014h
DIEIDR3 (1)
Die Identification Register 3
—
01C1 4018h
DEVIDR0
Device Identification Register 0
Privileged mode
Section 11.5.2
01C1 4020h
BOOTCFG
Boot Configuration Register
Privileged mode
Section 11.5.3
01C1 4024h
CHIPREVIDR
Chip Revision Identification Register
Privileged mode
Section 11.5.4
(1)
Section
—
This register is for internal-use only.
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Table 11-3. System Configuration Module 0 (SYSCFG0) Registers (continued)
222
Address
Acronym
Register Description
Access
01C1 4038h
KICK0R
Kick 0 Register
Privileged mode
Section 11.5.5.1
01C1 403Ch
KICK1R
Kick 1 Register
Privileged mode
Section 11.5.5.2
01C1 4040h
HOST0CFG
Host 0 Configuration Register
—
01C1 4044h
HOST1CFG
Host 1 Configuration Register
—
01C1 40E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
Section 11.5.8.1
01C1 40E4h
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
Section 11.5.8.2
01C1 40E8h
IENSET
Interrupt Enable Register
Privileged mode
Section 11.5.8.3
01C1 40ECh
IENCLR
Interrupt Enable Clear Register
Privileged mode
Section 11.5.8.4
01C1 40F0h
EOI
End of Interrupt Register
Privileged mode
Section 11.5.8.5
01C1 40F4h
FLTADDRR
Fault Address Register
Privileged mode
Section 11.5.9.1
01C1 40F8h
FLTSTAT
Fault Status Register
—
Section 11.5.9.2
01C1 4110h
MSTPRI0
Master Priority 0 Register
Privileged mode
Section 11.5.10.1
01C1 4114h
MSTPRI1
Master Priority 1 Register
Privileged mode
Section 11.5.10.2
01C1 4118h
MSTPRI2
Master Priority 2 Register
Privileged mode
Section 11.5.10.3
01C1 4120h
PINMUX0
Pin Multiplexing Control 0 Register
Privileged mode
Section 11.5.11.1
01C1 4124h
PINMUX1
Pin Multiplexing Control 1 Register
Privileged mode
Section 11.5.11.2
01C1 4128h
PINMUX2
Pin Multiplexing Control 2 Register
Privileged mode
Section 11.5.11.3
01C1 412Ch
PINMUX3
Pin Multiplexing Control 3 Register
Privileged mode
Section 11.5.11.4
01C1 4130h
PINMUX4
Pin Multiplexing Control 4 Register
Privileged mode
Section 11.5.11.5
01C1 4134h
PINMUX5
Pin Multiplexing Control 5 Register
Privileged mode
Section 11.5.11.6
01C1 4138h
PINMUX6
Pin Multiplexing Control 6 Register
Privileged mode
Section 11.5.11.7
01C1 413Ch
PINMUX7
Pin Multiplexing Control 7 Register
Privileged mode
Section 11.5.11.8
01C1 4140h
PINMUX8
Pin Multiplexing Control 8 Register
Privileged mode
Section 11.5.11.9
01C1 4144h
PINMUX9
Pin Multiplexing Control 9 Register
Privileged mode
Section 11.5.11.10
01C1 4148h
PINMUX10
Pin Multiplexing Control 10 Register
Privileged mode
Section 11.5.11.11
01C1 414Ch
PINMUX11
Pin Multiplexing Control 11 Register
Privileged mode
Section 11.5.11.12
01C1 4150h
PINMUX12
Pin Multiplexing Control 12 Register
Privileged mode
Section 11.5.11.13
01C1 4154h
PINMUX13
Pin Multiplexing Control 13 Register
Privileged mode
Section 11.5.11.14
01C1 4158h
PINMUX14
Pin Multiplexing Control 14 Register
Privileged mode
Section 11.5.11.15
01C1 415Ch
PINMUX15
Pin Multiplexing Control 15 Register
Privileged mode
Section 11.5.11.16
01C1 4160h
PINMUX16
Pin Multiplexing Control 16 Register
Privileged mode
Section 11.5.11.17
01C1 4164h
PINMUX17
Pin Multiplexing Control 17 Register
Privileged mode
Section 11.5.11.18
01C1 4168h
PINMUX18
Pin Multiplexing Control 18 Register
Privileged mode
Section 11.5.11.19
01C1 416Ch
PINMUX19
Pin Multiplexing Control 19 Register
Privileged mode
Section 11.5.11.20
01C1 4170h
SUSPSRC
Suspend Source Register
Privileged mode
Section 11.5.12
01C1 4174h
CHIPSIG
Chip Signal Register
—
Section 11.5.13
01C1 4178h
CHIPSIG_CLR
Chip Signal Clear Register
—
Section 11.5.14
01C1 417Ch
CFGCHIP0
Chip Configuration 0 Register
Privileged mode
Section 11.5.15
01C1 4180h
CFGCHIP1
Chip Configuration 1 Register
Privileged mode
Section 11.5.16
01C1 4184h
CFGCHIP2
Chip Configuration 2 Register
Privileged mode
Section 11.5.17
01C1 4188h
CFGCHIP3
Chip Configuration 3 Register
Privileged mode
Section 11.5.18
01C1 418Ch
CFGCHIP4
Chip Configuration 4 Register
Privileged mode
Section 11.5.19
System Configuration (SYSCFG) Module
Section
Section 11.5.6
Section 11.5.7
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Table 11-4. System Configuration Module 1 (SYSCFG1) Registers
Address
Acronym
Register Description
Access
01E2 C000h
VTPIO_CTL
VTP I/O Control Register
Privileged mode
Section 11.5.20
Section
01E2 C004h
DDR_SLEW
DDR Slew Register
Privileged mode
Section 11.5.21
01E2 C008h
DEEPSLEEP
Deep Sleep Register
Privileged mode
Section 11.5.22
01E2 C00Ch
PUPD_ENA
Pullup/Pulldown Enable Register
Privileged mode
Section 11.5.23
01E2 C010h
PUPD_SEL
Pullup/Pulldown Selection Register
Privileged mode
Section 11.5.24
01E2 C014h
RXACTIVE
RXACTIVE Control Register
Privileged mode
Section 11.5.25
01E2 C018h
PWRDN
Power Down Control Register
Privileged mode
Section 11.5.26
11.5.1 Revision Identification Register (REVID)
The revision identification register (REVID) provides the revision information for the SYSCFG module. The
REVID is shown in Figure 11-1 and described in Table 11-5.
Figure 11-1. Revision Identification Register (REVID)
31
0
REV
R-4E84 0102h
LEGEND: R = Read only; -n = value after reset
Table 11-5. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
Description
31-0
REV
4E84 0102h
Revision ID. Revision information for the SYSCFG module.
11.5.2 Device Identification Register 0 (DEVIDR0)
The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID
device. Software can use this register to determine the version of the device on which it is executing. The
DEVIDR0 is shown in Figure 11-2 and described in Table 11-6.
Figure 11-2. Device Identification Register 0 (DEVIDR0)
31
0
DEVID0
R-1B7D 102Fh
LEGEND: R = Read only; -n = value after reset
Table 11-6. Device Identification Register 0 (DEVIDR0) Field Descriptions
Bit
31-0
Field
DEVID0
Value
1B7D 102Fh
Description
Device identification.
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11.5.3 Boot Configuration Register (BOOTCFG)
The device boot and configuration settings are latched at device reset, and captured in the boot
configuration register (BOOTCFG). See your device-specific data manual and the Boot Considerations
chapter for details on boot and configuration settings. The BOOTCFG is shown in Figure 11-3 and
described in Table 11-7.
Figure 11-3. Boot Configuration Register (BOOTCFG)
31
16
Reserved
R-0
15
0
BOOTMODE
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-7. Boot Configuration Register (BOOTCFG) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
BOOTMODE
0
Description
Reserved
0-FFFFh
Boot Mode. This reflects the state of the boot mode pins.
11.5.4 Chip Revision Identification Register (CHIPREVIDR)
The chip revision identification register (CHIPREVIDR) provides the software-readable silicon revision
information for the device. The CHIPREVID is shown in Figure 11-4 and described in Table 11-8.
Figure 11-4. Chip Revision Identification Register (CHIPREVIDR)
31
16
Reserved
R-x
15
6
5
0
Reserved
CHIPREVID
R-x
R-4h
LEGEND: R = Read only; -n = value after reset; x = value is indeterminate after reset
Table 11-8. Chip Revision Identification Register (CHIPREVIDR) Field Descriptions
Bit
Field
31-6
Reserved
5-0
CHIPREVID
Value
0
Reserved
Identifies silicon revision of device.
0-3h
4h
224
Description
Older silicon revision
Silicon revision 2.2
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11.5.5 Kick Registers (KICK0R-KICK1R)
NOTE: The kick registers are disabled in silicon revision 2 and later. The SYSCFG registers are
always unlocked and writes to the kick registers have no functional effect.
The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of
the modules memory-mapped registers. At power-on reset, none of the SYSCFG module registers are
writeable (they are readable). To allow writing to the registers in the module, it is required to “unlock” the
registers by writing to two memory-mapped registers in the SYSCFG module, Kick0 and Kick1, with exact
data values. Once these values are written, then all the registers in the SYSCFG module that are
writeable can be written to. See Section 11.2.2 for the exact key values and sequence of steps. Writing
any other data value to either of these kick registers will cause the memory mapped registers to be
“locked” again and block out any write accesses to registers in the SYSCFG module.
11.5.5.1 Kick 0 Register (KICK0R)
The KICK0R is shown in Figure 11-5 and described in Table 11-9.
Figure 11-5. Kick 0 Register (KICK0R)
31
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-9. Kick 0 Register (KICK0R) Field Descriptions
Bit
Field
Value
31-0
KICK0
0-FFFF FFFFh
Description
KICK0R allows writing to unlock the kick0 data. The written data must be 83E7 0B13h to unlock
this register. It must be written before writing to the kick1 register. Writing any other value will lock
the other MMRs.
11.5.5.2 Kick 1 Register (KICK1R)
The KICK1R is shown in Figure 11-6 and described in Table 11-10.
Figure 11-6. Kick 1 Register (KICK1R)
31
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-10. Kick 1 Register (KICK1R) Field Descriptions
Bit
Field
Value
31-0
KICK1
0-FFFF FFFFh
Description
KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written
before writing to the kick1 register. Writing any other value will lock the other MMRs.
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11.5.6 Host 0 Configuration Register (HOST0CFG)
The ARM subsystem is held in reset when 0 is written to the BOOTRDY bit in the host 0 configuration
register (HOST0CFG). In a typical application, the BOOTRDY bit should not be cleared.
The HOST0CFG is shown in Figure 11-7 and described in Table 11-11.
NOTE: In addition to writing to HOST0CFG, the ARM subsystem must be enabled via the power
and sleep controller (PSC) module. By default, the ARM subsystem is in a SwRstDisable
state (see the Power and Sleep Controller (PSC) chapter for additional details).
Figure 11-7. Host 0 Configuration Register (HOST0CFG)
31
16
Reserved
R-0
15
1
0
Reserved
BOOTRDY
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-11. Host 0 Configuration Register (HOST0CFG) Field Descriptions
Bit
31-1
0
226
Field
Reserved
Value
0
BOOTRDY
Description
Reserved
ARM boot ready bit allowing ARM to boot.
0
ARM held in reset mode.
1
ARM released from wait in reset mode.
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11.5.7 Host 1 Configuration Register (HOST1CFG)
The host 1 configuration register (HOST1CFG) provides information on the DSP boot address value at
power-on reset. The boot address defaults to 0070 0000h (DSP ROM) on power-up. The address field is
read/writeable after reset and can be modified to allow execution from an alternate location after a module
level or local reset on the DSP. The HOST1CFG is shown in Figure 11-8 and described in Table 11-12.
Figure 11-8. Host 1 Configuration Register (HOST1CFG)
31
16
DSP_ISTP_RST_VAL
R/W-0070h
15
10
9
0
DSP_ISTP_RST_VAL
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-12. Host 1 Configuration Register (HOST1CFG) Field Descriptions
Bit
Field
31-10 DSP_ISTP_RST_VAL
9-0
Reserved
Value
0-3F FFFFh
0
Description
DSP boot address vector.
Reserved
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11.5.8 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
11.5.8.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 11-9 and described in
Table 11-13.
Figure 11-9. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-13. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
228
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
PROTERR
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
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11.5.8.2 Interrupt Enable Status/Clear Register (IENSTAT)
The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows
clearing of the interrupt status. The IENSTAT is shown in Figure 11-10 and described in Table 11-14.
Figure 11-10. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-14. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
PROTERR
Protection violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
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11.5.8.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 11-11 and described in Table 11-15.
Figure 11-11. Interrupt Enable Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-15. Interrupt Enable Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
PROTERR_EN
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
11.5.8.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 11-12 and described in Table 11-16.
Figure 11-12. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-16. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
230
Field
Reserved
Value
0
ADDRERR_CLR
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
PROTERR_CLR
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
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11.5.8.5 End of Interrupt Register (EOI)
The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of
the SYSCFG interrupt (for address/protection violation). It is required to write a value of 0 to the EOI
register after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of
completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts.
The EOI is shown in Figure 11-13 and described in Table 11-17.
Figure 11-13. End of Interrupt Register (EOI)
31
16
Reserved
R-0
15
8
7
0
Reserved
EOIVECT
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-17. End of Interrupt Register (EOI) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
EOIVECT
0-FFh
Description
Reserved. Always read 0.
EOI vector value. Write the interrupt distribution value of the chip.
11.5.9 Fault Registers
The fault registers are a group of registers responsible for capturing the details on the faulty
(address/protection violation errors) accesses, such as address and type of error.
11.5.9.1 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) captures the address of the first transfer that causes the address
or memory violation error. The FLTADDRR is shown in Figure 11-14 and described in Table 11-18.
Figure 11-14. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-18. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
Field
FLTADDR
Value
0-FFFF FFFFh
Description
Fault address for the first fault transfer.
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11.5.9.2 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous
transaction. This includes things like the master id for the master that caused the address/memory
violation error, details on whether it is a user or supervisor level read/write or execute fault. The FLTSTAT
is shown in Figure 11-15 and described in Table 11-19.
Figure 11-15. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
ID
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-19. Fault Status Register (FLTSTAT) Field Descriptions
Field
Value
Description
31-24
Bit
ID
0-FFh
Transfer ID of the first fault transfer.
23-16
MSTID
0-FFh
Master ID of the first fault transfer.
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
0
0-Fh
0
Privilege ID of the first fault transfer.
Reserved. Always read 0
Fault type of first fault transfer.
0
No transfer fault
1h
User execute fault
2h
User write fault
3h
Reserved
4h
User read fault
5h-7h
8h
9h-Fh
10h
11h-1Fh
20h
21h-3Fh
232
Reserved. Always read 0
Reserved
Supervisor execute fault
Reserved
Supervisor write fault
Reserved
Supervisor read fault
Reserved
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11.5.10 Master Priority Registers (MSTPRI0-MSTPRI2)
11.5.10.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 11-16 and described in Table 11-20.
Figure 11-16. Master Priority 0 Register (MSTPRI0)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
SATA
Rsvd
UPP
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
DSP_CFG
Rsvd
DSP_MDMA
Rsvd
ARM_D
Rsvd
ARM_I
R/W-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-20. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
19
18-16
SATA
Reserved
UPP
0-7h
0
0-7h
15
Reserved
0
14-12
DSP_CFG
0-7h
11
Reserved
0
10-8
7
6-4
3
2-0
DSP_MDMA
Reserved
ARM_D
Reserved
ARM_I
0-7h
0
0-7h
0
0-7h
SATA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
uPP port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
DSP CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
DSP DMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
ARM_D port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
ARM_I port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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11.5.10.2 Master Priority 1 Register (MSTPRI1)
The master priority 1 register (MSTPRI1) is shown in Figure 11-17 and described in Table 11-21.
Figure 11-17. Master Priority 1 Register (MSTPRI1)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
VPIF_DMA_1
Rsvd
VPIF_DMA_0
Rsvd
Reserved
Rsvd
EDMA31TC0
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
EDMA30TC1
Rsvd
EDMA30TC0
Rsvd
PRU1
Rsvd
PRU0
R/W-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-21. Master Priority 1 Register (MSTPRI1) Field Descriptions
Bit
Field
31
Reserved
30-28
27
26-24
VPIF_DMA_1
Reserved
VPIF_DMA_0
Value
0
0-7h
0
0-7h
Description
Reserved. Write the default value when modifying this register.
VPIF DMA1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
VPIF DMA0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
15
14-12
11
10-8
7
6-4
3
2-0
234
EDMA31TC0
Reserved
EDMA30TC1
Reserved
EDMA30TC0
Reserved
PRU1
Reserved
PRU0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
EDMA3_1_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
EDMA3_0_TC1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
EDMA3_0_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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11.5.10.3 Master Priority 2 Register (MSTPRI2)
The master priority 2 register (MSTPRI2) is shown in Figure 11-18 and described in Table 11-22.
Figure 11-18. Master Priority 2 Register (MSTPRI2)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
LCDC
Rsvd
USB1
Rsvd
UHPI
Rsvd
Reserved
R/W-0
R/W-5h
R/W-0
R/W-4h
R/W-0
R/W-6h
R/W-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
USB0CDMA
Rsvd
USB0CFG
Rsvd
Reserved
Rsvd
EMAC
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-0
R/W-0
R/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-22. Master Priority 2 Register (MSTPRI2) Field Descriptions
Bit
Field
31
Reserved
30-28
27
26-24
23
22-20
LCDC
Reserved
USB1
Reserved
UHPI
Value
0
0-7h
0
0-7h
0
0-7h
Description
Reserved. Write the default value when modifying this register.
LCDC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
USB1 (USB1.1) port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
HPI port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
USB0CDMA
0-7h
11
Reserved
0
10-8
USB0CFG
0-7h
USB0 (USB2.0) CDMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
USB0 (USB2.0) CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Write the default value when modifying this register.
2-0
EMAC
0-7h
EMAC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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11.5.11 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the
smallest possible package. On the device, pin multiplexing can be controlled on a pin by pin basis. This is
done by the pin multiplexing registers (PINMUX0-PINMUX19). Each pin that is multiplexed with several
different functions has a corresponding 4-bit field in PINMUXn. Pin multiplexing selects which of several
peripheral pin functions control the pins I/O buffer output data and output enable values only. Note that the
input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers
have no effect on input from a pin. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used. Detailed information about the pin
multiplexing and control is covered in the device-specific data manual. Access to the pin multiplexing utility
is available in OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility Application Report
(SPRAB63).
11.5.11.1 Pin Multiplexing Control 0 Register (PINMUX0)
Figure 11-19. Pin Multiplexing Control 0 Register (PINMUX0)
31
28
27
24
23
20
19
16
PINMUX0_31_28
PINMUX0_27_24
PINMUX0_23_20
PINMUX0_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX0_15_12
PINMUX0_11_8
PINMUX0_7_4
PINMUX0_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-23. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
Bit
Field
31-28
Value
PINMUX0_31_28
RTC_ALARM/UART2_CTS/GP0[8]/DEEPSLEEP Control
0
Selects Function DEEPSLEEP
I
1h
Reserved
X
2h
Selects Function RTC_ALARM
O
3h
Reserved
X
4h
Selects Function UART2_CTS
I
5h-7h
8h
9h-Fh
27-24
PINMUX0_27_24
X
Selects Function GP0[8]
I/O
Reserved
X
AMUTE/PRU0_R30[16]/UART2_RTS/GP0[9]/PRU0_R31[16] Control
Selects Function PRU0_R31[16]
1h
Selects Function AMUTE
I/O
2h
Selects Function PRU0_R30[16]
O
3h
Reserved
X
4h
Selects Function UART2_RTS
O
Reserved
X
8h
9h-Fh
236
Reserved
0
5h-7h
(1)
Type (1)
Description
I
Selects Function GP0[9]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-23. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit
23-20
Field
Value
PINMUX0_23_20
AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10]/PRU0_R31[17] Control
0
Selects Function PRU0_R31[17]
1h
Selects Function AHCLKX
2h
Selects Function USB_REFCLKIN
I
3h
Reserved
X
4h
Selects Function UART1_CTS
I
Reserved
X
5h-7h
8h
9h-Fh
19-16
PINMUX0_19_16
Reserved
X
1h
Selects Function AHCLKR
I/O
2h
Selects Function PRU0_R30[18]
O
3h
Reserved
X
4h
Selects Function UART1_RTS
O
PINMUX0_15_12
I
Reserved
X
Selects Function GP0[11]
I/O
Reserved
X
AFSX/GP0[12]/PRU0_R31[19] Control
0
Selects Function PRU0_R31[19]
1h
Selects Function AFSX
2h-7h
8h
9h-Fh
PINMUX0_11_8
I
I/O
Reserved
X
Selects Function GP0[12]
I/O
Reserved
X
AFSR/GP0[13]/PRU0_R31[20] Control
0
Selects Function PRU0_R31[20]
1h
Selects Function AFSR
2h-7h
8h
9h-Fh
PINMUX0_7_4
I
I/O
Reserved
X
Selects Function GP0[13]
I/O
Reserved
X
ACLKX/PRU0_R30[19]/GP0[14]/PRU0_R31[21] Control
0
Selects Function PRU0_R31[21]
1h
Selects Function ACLKX
2h-3h
4h
5h-7h
8h
9h-Fh
3-0
I/O
Selects Function PRU0_R31[18]
9h-Fh
7-4
Selects Function GP0[10]
0
8h
11-8
I
I/O
AHCLKR/PRU0_R30[18]/UART1_RTS/GP0[11]/PRU0_R31[18] Control
5h-7h
15-12
Type (1)
Description
PINMUX0_3_0
I
I/O
Reserved
X
Selects Function PRU0_R30[19]
O
Reserved
X
Selects Function GP0[14]
I/O
Reserved
X
ACLKR/PRU0_R30[20]/GP0[15]/PRU0_R31[22] Control
0
Selects Function PRU0_R31[22]
1h
Selects Function ACLKR
2h-3h
4h
5h-7h
8h
9h-Fh
I
I/O
Reserved
X
Selects Function PRU0_R30[20]
O
Reserved
X
Selects Function GP0[15]
I/O
Reserved
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11.5.11.2 Pin Multiplexing Control 1 Register (PINMUX1)
Figure 11-20. Pin Multiplexing Control 1 Register (PINMUX1)
31
28
27
24
23
20
19
16
PINMUX1_31_28
PINMUX1_27_24
PINMUX1_23_20
PINMUX1_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX1_15_12
PINMUX1_11_8
PINMUX1_7_4
PINMUX1_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-24. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
Bit
Field
31-28
Value
PINMUX1_31_28
AXR8/CLKS1/ECAP1_APWM1/GP0[0]/PRU0_R31[8] Control
0
Selects Function PRU0_R31[8]
1h
Selects Function AXR8
2h
Selects Function CLKS1
I
3h
Reserved
X
4h
Selects Function ECAP1_APWM1
5h-7h
8h
9h-Fh
27-24
PINMUX1_27_24
Selects Function GP0[0]
I/O
Reserved
X
Pin is 3-stated.
Selects Function AXR9
I/O
2h
Selects Function DX1
O
PINMUX1_23_20
Z
Reserved
X
Selects Function GP0[1]
I/O
Reserved
X
AXR10/DR1/GP0[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR10
2h
Selects Function DR1
3h-7h
8h
9h-Fh
PINMUX1_19_16
Z
I/O
I
Reserved
X
Selects Function GP0[2]
I/O
Reserved
X
AXR11/FSX1/GP0[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR11
I/O
2h
Selects Function FSX1
I/O
3h-7h
8h
9h-Fh
238
X
0
9h-Fh
(1)
I/O
Reserved
1h
8h
19-16
I
I/O
AXR9/DX1/GP0[1] Control
3h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP0[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-24. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX1_15_12
AXR12/FSR1/GP0[4] Control
0
Pin is 3-stated.
1h
Selects Function AXR12
I/O
2h
Selects Function FSR1
I/O
3h-7h
8h
9h-Fh
11-8
PINMUX1_11_8
Reserved
X
Selects Function GP0[4]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function AXR13
I/O
2h
Selects Function CLKX1
I/O
8h
9h-Fh
PINMUX1_7_4
Z
Reserved
X
Selects Function GP0[5]
I/O
Reserved
X
AXR14/CLKR1/GP0[6] Control
0
Pin is 3-stated.
1h
Selects Function AXR14
I/O
2h
Selects Function CLKR1
I/O
3h-7h
8h
9h-Fh
3-0
Z
AXR13/CLKX1/GP0[5] Control
3h-7h
7-4
Type (1)
Description
PINMUX1_3_0
Z
Reserved
X
Selects Function GP0[6]
I/O
Reserved
X
AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR15
2h
Selects Function EPWM0TZ[0]
3h
Reserved
4h
Selects Function ECAP2_APWM2
5h-7h
8h
9h-Fh
Z
I/O
I
X
I/O
Reserved
X
Selects Function GP0[7]
I/O
Reserved
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11.5.11.3 Pin Multiplexing Control 2 Register (PINMUX2)
Figure 11-21. Pin Multiplexing Control 2 Register (PINMUX2)
31
28
27
24
23
20
19
16
PINMUX2_31_28
PINMUX2_27_24
PINMUX2_23_20
PINMUX2_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX2_15_12
PINMUX2_11_8
PINMUX2_7_4
PINMUX2_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-25. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
Type
Bit
Field
3128
PINMUX2
_31_28
Value
0
Selects Function CLKS0
I
1h
Selects Function AXR0
I/O
2h
Selects Function ECAP0_APWM0
I/O
3h
Reserved
4h
Selects Function GP8[7]
8h
9h-Fh
PINMUX2
_27_24
X
Selects Function MII_TXD[0]
O
Reserved
X
0
Pin is 3-stated.
Selects Function AXR1
I/O
2h
Selects Function DX0
O
3h
Reserved
4h
Selects Function GP1[9]
9h-Fh
PINMUX2
_23_20
Z
X
I/O
Reserved
X
Selects Function MII_TXD[1]
O
Reserved
X
AXR2/DR0/GP1[10]/MII_TXD[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR2
2h
Selects Function DR0
I
3h
Reserved
X
4h
Selects Function GP1[10]
5h-7h
8h
9h-Fh
240
Reserved
1h
8h
(1)
X
I/O
AXR1/DX0/GP1[9]/MII_TXD[1] Control
5h-7h
2320
(1)
AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLK
S0 Control
5h-7h
2724
Description
Z
I/O
I/O
Reserved
X
Selects Function MII_TXD[2]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-25. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued)
Type
Bit
Field
1916
PINMUX2
_19_16
Value
AXR3/FSX0/GP1[11]/MII_TXD[3] Control
Pin is 3-stated.
1h
Selects Function AXR3
I/O
2h
Selects Function FSX0
I/O
3h
Reserved
4h
Selects Function GP1[11]
8h
9h-Fh
PINMUX2
_15_12
Reserved
X
Selects Function MII_TXD[3]
O
Reserved
X
0
Pin is 3-stated.
Selects Function AXR4
I/O
2h
Selects Function FSR0
I/O
3h
Reserved
4h
Selects Function GP1[12]
9h-Fh
Z
X
I/O
Reserved
X
Selects Function MII_COL
I
Reserved
X
AXR5/CLKX0/GP1[13]/MII_TXCLK Control
0
Pin is 3-stated.
1h
Selects Function AXR5
I/O
2h
Selects Function CLKX0
I/O
3h
Reserved
4h
Selects Function GP1[13]
5h-7h
8h
9h-Fh
PINMUX2
_7_4
Reserved
Z
X
I/O
X
Selects Function MII_TXCLK
I
Reserved
X
AXR6/CLKR0/GP1[14]/MII_TXEN/PRU0_R31[6]
Control
0
Selects Function PRU0_R31[6]
1h
Selects Function AXR6
I/O
2h
Selects Function CLKR0
I/O
3h
Reserved
4h
Selects Function GP1[14]
5h-7h
8h
9h-Fh
3-0
X
I/O
1h
8h
7-4
Z
AXR4/FSR0/GP1[12]/MII_COL Control
5h-7h
11-8 PINMUX2
_11_8
(1)
0
5h-7h
1512
Description
PINMUX2
_3_0
I
X
I/O
Reserved
X
Selects Function MII_TXEN
O
Reserved
X
AXR7/EPWM1TZ[0]/PRU0_R30[17]/GP1[15]/PR
U0_R31[7] Control
0
Selects Function PRU0_R31[7]
1h
Selects Function AXR7
2h
Selects Function EPWM1TZ[0]
I
3h
Reserved
X
4h
Selects Function PRU0_R30[17]
O
5h-7h
8h
9h-Fh
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Reserved
Selects Function GP1[15]
Reserved
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I
I/O
X
I/O
X
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11.5.11.4 Pin Multiplexing Control 3 Register (PINMUX3)
Figure 11-22. Pin Multiplexing Control 3 Register (PINMUX3)
31
28
27
24
23
20
19
16
PINMUX3_31_28
PINMUX3_27_24
PINMUX3_23_20
PINMUX3_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX3_15_12
PINMUX3_11_8
PINMUX3_7_4
PINMUX3_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-26. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
Bit
Field
31-28
Value
PINMUX3_31_28
SPI0_SCS[2]/UART0_RTS/GP8[1]/MII_RXD[0]/SATA_CP_DET Control
0
Selects Function SATA_CP_DET
1h
Selects Function SPI0_SCS[2]
I/O
2h
Selects Function UART0_RTS
O
3h
Reserved
4h
Selects Function GP8[1]
5h-7h
8h
9h-Fh
27-24
PINMUX3_27_24
Reserved
X
Selects Function MII_RXD[0]
I
Reserved
X
0
Selects Function SATA_MP_SWITCH
Selects Function SPI0_SCS[3]
I/O
2h
Selects Function UART0_CTS
I
3h
Reserved
4h
Selects Function GP8[2]
9h-Fh
PINMUX3_23_20
I
X
I/O
Reserved
X
Selects Function MII_RXD[1]
I
Reserved
X
SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[4]
I/O
2h
Selects Function UART0_TXD
O
3h
Reserved
X
4h
Selects Function GP8[3]
5h-7h
8h
9h-Fh
242
X
I/O
1h
8h
(1)
I
SPI0_SCS[3]/UART0_CTS/GP8[2]/MII_RXD[1]/SATA_MP_SWITCH Control
5h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function MII_RXD[2]
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-26. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX3_19_16
SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[5]
2h
Selects Function UART0_RXD
I
3h
Reserved
X
4h
Selects Function GP8[4]
5h-7h
8h
9h-Fh
15-12
PINMUX3_15_12
X
Selects Function MII_RXD[3]
I
Reserved
X
Pin is 3-stated.
1h
Selects Function SPI0_SIMO
I/O
2h
Selects Function EPWMSYNCO
O
3h
Reserved
4h
Selects Function GP8[5]
9h-Fh
PINMUX3_11_8
Z
X
I/O
Reserved
X
Selects Function MII_CRS
I
Reserved
X
SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SOMI
2h
Selects Function EPWMSYNCI
I
3h
Reserved
X
4h
Selects Function GP8[6]
5h-7h
8h
9h-Fh
PINMUX3_7_4
Z
I/O
I/O
Reserved
X
Selects Function MII_RXER
I
Reserved
X
SPI0_ENA/EPWM0B/PRU0_R30[6]/MII_RXDV Control
0
Pin is 3-stated.
1h
Selects Function SPI0_ENA
I/O
2h
Selects Function EPWM0B
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[6]
O
Reserved
X
Selects Function MII_RXDV
I
Reserved
X
5h-7h
8h
9h-Fh
3-0
I/O
Reserved
0
8h
7-4
Z
I/O
SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS Control
5h-7h
11-8
Type (1)
Description
PINMUX3_3_0
Z
SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK Control
0
Pin is 3-stated.
1h
Selects Function SPI0_CLK
I/O
2h
Selects Function EPWM0A
I/O
3h
Reserved
4h
Selects Function GP1[8]
5h-7h
8h
9h-Fh
Z
X
I/O
Reserved
X
Selects Function MII_RXCLK
I
Reserved
X
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11.5.11.5 Pin Multiplexing Control 4 Register (PINMUX4)
Figure 11-23. Pin Multiplexing Control 4 Register (PINMUX4)
31
28
27
24
23
20
19
16
PINMUX4_31_28
PINMUX4_27_24
PINMUX4_23_20
PINMUX4_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX4_15_12
PINMUX4_11_8
PINMUX4_7_4
PINMUX4_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-27. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
Bit
Field
31-28
Value
PINMUX4_31_28
SP1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0] Control
0
Pin is 3-stated.
1h
Selects Function SP1_SCS[2]
I/O
2h
Selects Function UART1_TXD
O
3h
Reserved
X
4h
Selects Function SATA_CP_POD
O
Reserved
X
5h-7h
8h
9h-Fh
27-24
PINMUX4_27_24
I/O
Reserved
X
0
Pin is 3-stated.
Selects Function SPI1_SCS[3]
I/O
2h
Selects Function UART1_RXD
I
3h
Reserved
X
4h
Selects Function SATA_LED
O
9h-Fh
PINMUX4_23_20
Z
Reserved
X
Selects Function GP1[1]
I/O
Reserved
X
SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[4]
I/O
2h
Selects Function UART2_TXD
O
3h
Reserved
X
4h
Selects Function I2C1_SDA
5h-7h
8h
9h-Fh
244
Selects Function GP1[0]
1h
8h
(1)
Z
SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1] Control
5h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP1[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-27. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX4_19_16
SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[5]
2h
Selects Function UART2_RXD
I
3h
Reserved
X
4h
Selects Function I2C1_SCL
5h-7h
8h
9h-Fh
15-12
PINMUX4_15_12
X
Selects Function GP1[3]
I/O
Reserved
X
Pin is 3-stated.
1h
Selects Function SPI1_SCS[6]
I/O
2h
Selects Function I2C0_SDA
I/O
3h
Reserved
X
4h
Selects Function TM64P3_OUT12
O
9h-Fh
PINMUX4_11_8
Z
Reserved
X
Selects Function GP1[4]
I/O
Reserved
X
SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[7]
I/O
2h
Selects Function I2C0_SCL
I/O
3h
Reserved
X
4h
Selects Function TM64P2_OUT12
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX4_7_4
Z
Selects Function GP1[5]
I/O
Reserved
X
SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 Control
0
Selects Function TM64P1_IN12
I
1h
Selects Function SPI0_SCS[0]
I/O
2h
Selects Function TM64P1_OUT12
O
3h
Reserved
4h
Selects Function GP1[6]
5h-7h
8h
9h-Fh
3-0
I/O
Reserved
0
8h
7-4
Z
I/O
SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] Control
5h-7h
11-8
Type (1)
Description
PINMUX4_3_0
X
I/O
Reserved
X
Selects Function MDIO_D
I/O
Reserved
X
SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 Control
0
Selects Function TM64P0_IN12
I
1h
Selects Function SPI0_SCS[1]
I/O
2h
Selects Function TM64P0_OUT12
O
3h
Reserved
X
4h
Selects Function GP1[7]
5h-7h
8h
9h-Fh
I/O
Reserved
X
Selects Function MDIO_CLK
O
Reserved
X
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11.5.11.6 Pin Multiplexing Control 5 Register (PINMUX5)
Figure 11-24. Pin Multiplexing Control 5 Register (PINMUX5)
31
28
27
24
23
20
19
16
PINMUX5_31_28
PINMUX5_27_24
PINMUX5_23_20
PINMUX5_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX5_15_12
PINMUX5_11_8
PINMUX5_7_4
PINMUX5_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-28. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
Bit
Field
31-28
Value
PINMUX5_31_28
EMA_BA[0]/GP2[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_BA[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX5_27_24
X
Z
Selects Function EMA_BA[1]
O
Reserved
X
PINMUX5_23_20
Selects Function GP2[9]
I/O
Reserved
X
SPI1_SIMO/GP2[10] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SIMO
8h
9h-Fh
PINMUX5_19_16
Z
I/O
Reserved
X
Selects Function GP2[10]
I/O
Reserved
X
SPI1_SOMI/GP2[11] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SOMI
2h-7h
8h
9h-Fh
PINMUX5_15_12
Z
I/O
Reserved
X
Selects Function GP2[11]
I/O
Reserved
X
SPI1_ENA/GP2[12] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_ENA
2h-7h
8h
9h-Fh
246
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP2[8]
1h
9h-Fh
19-16
Reserved
EMA_BA[1]/GP2[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP2[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-28. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX5_11_8
SPI1_CLK/GP2[13] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_CLK
2h-7h
8h
9h-Fh
7-4
PINMUX5_7_4
Z
I/O
Reserved
X
Selects Function GP2[13]
I/O
Reserved
X
SPI1_SCS[0]/EPWM1B/PRU0_R30[7]/GP2[14]/TM64P3_IN12 Control
0
Selects Function TM64P3_IN12
I
1h
Selects Function SPI1_SCS[0]
I/O
2h
Selects Function EPWM1B
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[7]
O
5h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX5_3_0
Reserved
X
Selects Function GP2[14]
I/O
Reserved
X
SPI1_SCS[1]/EPWM1A/PRU0_R30[8]/GP2[15]/TM64P2_IN12 Control
0
Selects Function TM64P2_IN12
I
1h
Selects Function SPI1_SCS[1]
I/O
2h
Selects Function EPWM1A
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[8]
O
5h-7h
8h
9h-Fh
Reserved
X
Selects Function GP2[15]
I/O
Reserved
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X
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11.5.11.7 Pin Multiplexing Control 6 Register (PINMUX6)
Figure 11-25. Pin Multiplexing Control 6 Register (PINMUX6)
31
28
27
24
23
20
19
16
PINMUX6_31_28
PINMUX6_27_24
PINMUX6_23_20
PINMUX6_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX6_15_12
PINMUX6_11_8
PINMUX6_7_4
PINMUX6_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-29. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
Bit
Field
31-28
Value
PINMUX6_31_28
EMA_CS[0]/GP2[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX6_27_24
X
Selects Function EMA_WAIT[1]
I
Reserved
X
Selects Function PRU0_R30[1]
O
9h-Fh
PINMUX6_23_20
I
Reserved
X
Selects Function GP2[1]
I/O
Reserved
X
EMA_WE_DQM[1]/GP2[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[1]
O
2h-7h
8h
9h-Fh
PINMUX6_19_16
Reserved
X
Selects Function GP2[2]
I/O
Reserved
X
EMA_WE_DQM[0]/GP2[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[0]
O
2h-7h
8h
9h-Fh
PINMUX6_15_12
Reserved
X
Selects Function GP2[3]
I/O
Reserved
X
EMA_CAS/PRU0_R30[2]/GP2[4]/PRU0_R31[2] Control
0
Selects Function PRU0_R31[2]
I
1h
Selects Function EMA_CAS
O
Reserved
X
Selects Function PRU0_R30[2]
O
2h-3h
4h
5h-7h
8h
9h-Fh
248
Reserved
Selects Function PRU0_R31[1]
8h
(1)
I/O
0
4h
15-12
X
Selects Function GP2[0]
1h
5h-7h
19-16
Reserved
EMA_WAIT[1]/PRU0_R30[1]/GP2[1]/PRU0_R31[1] Control
2h-3h
23-20
Type (1)
Description
Reserved
X
Selects Function GP2[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-29. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX6_11_8
EMA_RAS/PRU0_R30[3]/GP2[5]/PRU0_R31[3] Control
0
Selects Function PRU0_R31[3]
I
1h
Selects Function EMA_RAS
O
2h-3h
4h
5h-7h
8h
9h-Fh
7-4
PINMUX6_7_4
Reserved
X
Selects Function PRU0_R30[3]
O
Reserved
X
Selects Function GP2[5]
I/O
Reserved
X
EMA_SDCKE/PRU0_R30[4]/GP2[6]/PRU0_R31[4] Control
0
Selects Function PRU0_R31[4]
I
1h
Selects Function EMA_SDCKE
O
2h-3h
4h
5h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX6_3_0
Reserved
X
Selects Function PRU0_R30[4]
O
Reserved
X
Selects Function GP2[6]
I/O
Reserved
X
EMA_CLK/PRU0_R30[5]/GP2[7]/PRU0_R31[5] Control
0
Selects Function PRU0_R31[5]
I
1h
Selects Function EMA_CLK
O
2h-3h
4h
5h-7h
8h
9h-Fh
Reserved
X
Selects Function PRU0_R30[5]
O
Reserved
X
Selects Function GP2[7]
I/O
Reserved
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11.5.11.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 11-26. Pin Multiplexing Control 7 Register (PINMUX7)
31
28
27
24
23
20
19
16
PINMUX7_31_28
PINMUX7_27_24
PINMUX7_23_20
PINMUX7_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX7_15_12
PINMUX7_11_8
PINMUX7_7_4
PINMUX7_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-30. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit
Field
31-28
Value
PINMUX7_31_28
EMA_WAIT[0]/PRU0_R30[0]/GP3[8]/PRU0_R31[0] Control
0
Selects Function PRU0_R31[0]
I
1h
Selects Function EMA_WAIT[0]
I
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX7_27_24
X
Selects Function GP3[8]
I/O
Reserved
X
1h
Selects Function EMA_A_RW
O
PINMUX7_23_20
Reserved
X
Selects Function GP3[9]
I/O
Reserved
X
EMA_OE/GP3[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_OE
O
8h
9h-Fh
PINMUX7_19_16
Reserved
X
Selects Function GP3[10]
I/O
Reserved
X
EMA_WE/GP3[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE
O
2h-7h
8h
9h-Fh
PINMUX7_15_12
Reserved
X
Selects Function GP3[11]
I/O
Reserved
X
EMA_CS[5]/GP3[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[5]
O
Reserved
X
2h-7h
8h
9h-Fh
250
Reserved
Z
2h-7h
(1)
O
Pin is 3-stated.
9h-Fh
15-12
X
Selects Function PRU0_R30[0]
0
8h
19-16
Reserved
EMA_A_RW/GP3[9] Control
2h-7h
23-20
Type (1)
Description
Selects Function GP3[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-30. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX7_11_8
EMA_CS[4]/GP3[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[4]
O
2h-7h
8h
9h-Fh
7-4
PINMUX7_7_4
Reserved
X
Selects Function GP3[13]
I/O
Reserved
X
EMA_CS[3]/GP3[14] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[3]
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX7_3_0
Reserved
X
Selects Function GP3[14]
I/O
Reserved
X
EMA_CS[2]/GP3[15] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[2]
O
2h-7h
8h
9h-Fh
Reserved
X
Selects Function GP3[15]
I/O
Reserved
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11.5.11.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 11-27. Pin Multiplexing Control 8 Register (PINMUX8)
31
28
27
24
23
20
19
16
PINMUX8_31_28
PINMUX8_27_24
PINMUX8_23_20
PINMUX8_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX8_15_12
PINMUX8_11_8
PINMUX8_7_4
PINMUX8_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-31. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit
Field
31-28
Value
PINMUX8_31_28
EMA_D[8]/GP3[0] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[8]
2h-7h
8h
9h-Fh
27-24
PINMUX8_27_24
Selects Function EMA_D[9]
PINMUX8_23_20
X
Z
I/O
Reserved
X
Selects Function GP3[1]
I/O
Reserved
X
EMA_D[10]/GP3[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[10]
8h
9h-Fh
PINMUX8_19_16
Z
I/O
Reserved
X
Selects Function GP3[2]
I/O
Reserved
X
EMA_D[11]/GP3[3] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[11]
2h-7h
8h
9h-Fh
PINMUX8_15_12
Z
I/O
Reserved
X
Selects Function GP3[3]
I/O
Reserved
X
EMA_D[12]/GP3[4] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[12]
2h-7h
8h
9h-Fh
252
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP3[0]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[9]/GP3[1] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP3[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-31. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX8_11_8
EMA_D[13]/GP3[5] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[13]
2h-7h
8h
9h-Fh
7-4
PINMUX8_7_4
Z
I/O
Reserved
X
Selects Function GP3[5]
I/O
Reserved
X
EMA_D[14]/GP3[6] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[14]
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX8_3_0
Z
I/O
Reserved
X
Selects Function GP3[6]
I/O
Reserved
X
EMA_D[15]/GP3[7] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[15]
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP3[7]
I/O
Reserved
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11.5.11.10 Pin Multiplexing Control 9 Register (PINMUX9)
Figure 11-28. Pin Multiplexing Control 9 Register (PINMUX9)
31
28
27
24
23
20
19
16
PINMUX9_31_28
PINMUX9_27_24
PINMUX9_23_20
PINMUX9_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX9_15_12
PINMUX9_11_8
PINMUX9_7_4
PINMUX9_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-32. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
Bit
Field
31-28
Value
PINMUX9_31_28
EMA_D[0]/GP4[8] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[0]
2h-7h
8h
9h-Fh
27-24
PINMUX9_27_24
Selects Function EMA_D[1]
PINMUX9_23_20
X
Z
I/O
Reserved
X
Selects Function GP4[9]
I/O
Reserved
X
EMA_D[2]/GP4[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[2]
8h
9h-Fh
PINMUX9_19_16
Z
I/O
Reserved
X
Selects Function GP4[10]
I/O
Reserved
X
EMA_D[3]/GP4[11] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[3]
2h-7h
8h
9h-Fh
PINMUX9_15_12
Z
I/O
Reserved
X
Selects Function GP4[11]
I/O
Reserved
X
EMA_D[4]/GP4[12] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[4]
2h-7h
8h
9h-Fh
254
I/O
Reserved
Pin is 3-stated.
2h-7h
(1)
X
Selects Function GP4[8]
0
8h
15-12
Reserved
1h
9h-Fh
19-16
Z
I/O
EMA_D[1]/GP4[9] Control
2h-7h
23-20
Type (1)
Description
Z
I/O
Reserved
X
Selects Function GP4[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-32. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX9_11_8
EMA_D[5]/GP4[13] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[5]
2h-7h
8h
9h-Fh
7-4
PINMUX9_7_4
Z
I/O
Reserved
X
Selects Function GP4[13]
I/O
Reserved
X
EMA_D[6]/GP4[14] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[6]
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX9_3_0
Z
I/O
Reserved
X
Selects Function GP4[14]
I/O
Reserved
X
EMA_D[7]/GP4[15] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[7]
2h-7h
8h
9h-Fh
Z
I/O
Reserved
X
Selects Function GP4[15]
I/O
Reserved
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11.5.11.11 Pin Multiplexing Control 10 Register (PINMUX10)
Figure 11-29. Pin Multiplexing Control 10 Register (PINMUX10)
31
28
27
24
23
20
19
16
PINMUX10_31_28
PINMUX10_27_24
PINMUX10_23_20
PINMUX10_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX10_15_12
PINMUX10_11_8
PINMUX10_7_4
PINMUX10_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-33. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
Bit
Field
31-28
Value
PINMUX10_31_28
EMA_A[16]/MMCSD0_DAT[5]/PRU1_R30[24]/GP4[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[16]
O
2h
Selects Function MMCSD0_DAT[5]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[24]
O
Reserved
X
5h-7h
8h
9h-Fh
27-24
PINMUX10_27_24
X
0
Pin is 3-stated.
Z
Selects Function EMA_A[17]
O
2h
Selects Function MMCSD0_DAT[4]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[25]
O
9h-Fh
PINMUX10_23_20
Reserved
X
Selects Function GP4[1]
I/O
Reserved
X
EMA_A[18]/MMCSD0_DAT[3]/PRU1_R30[26]/GP4[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[18]
O
2h
Selects Function MMCSD0_DAT[3]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[26]
O
5h-7h
8h
9h-Fh
256
I/O
Reserved
1h
8h
(1)
Selects Function GP4[0]
EMA_A[17]/MMCSD0_DAT[4]/PRU1_R30[25]/GP4[1] Control
5h-7h
23-20
Type (1)
Description
Z
Reserved
X
Selects Function GP4[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-33. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX10_19_16
EMA_A[19]/MMCSD0_DAT[2]/PRU1_R30[27]/GP4[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[19]
O
2h
Selects Function MMCSD0_DAT[2]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[27]
O
5h-7h
8h
9h-Fh
15-12
PINMUX10_15_12
I/O
Reserved
X
Pin is 3-stated.
1h
Selects Function EMA_A[20]
O
2h
Selects Function MMCSD0_DAT[1]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[28]
O
9h-Fh
PINMUX10_11_8
Z
Reserved
X
Selects Function GP4[4]
I/O
Reserved
X
EMA_A[21]/MMCSD0_DAT[0]/PRU1_R30[29]/GP4[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[21]
O
2h
Selects Function MMCSD0_DAT[0]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[29]
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX10_7_4
Selects Function GP4[5]
I/O
Reserved
X
EMA_A[22]/MMCSD0_CMD/PRU1_R30[30]/GP4[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[22]
O
2h
Selects Function MMCSD0_CMD
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[30]
O
5h-7h
8h
9h-Fh
3-0
X
Selects Function GP4[3]
0
8h
7-4
Reserved
EMA_A[20]/MMCSD0_DAT[1]/PRU1_R30[28]/GP4[4] Control
5h-7h
11-8
Type (1)
Description
PINMUX10_3_0
Reserved
X
Selects Function GP4[6]
I/O
Reserved
X
MMCSD0_CLK/PRU1_R30[31]/GP4[7] Control
0
Pin is 3-stated.
1h
Reserved
X
2h
Selects Function MMCSD0_CLK
O
3h
Reserved
X
4h
Selects Function PRU1_R30[31]
O
5h-7h
8h
9h-Fh
Z
Reserved
X
Selects Function GP4[7]
I/O
Reserved
X
11.5.11.12 Pin Multiplexing Control 11 Register (PINMUX11)
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Figure 11-30. Pin Multiplexing Control 11 Register (PINMUX11)
31
28
27
24
23
20
19
16
PINMUX11_31_28
PINMUX11_27_24
PINMUX11_23_20
PINMUX11_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX11_15_12
PINMUX11_11_8
PINMUX11_7_4
PINMUX11_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-34. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
Bit
Field
31-28
Value
PINMUX11_31_28
EMA_A[8]/PRU1_R30[16]/GP5[8] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[8]
O
Reserved
X
Selects Function PRU1_R30[16]
O
2h-3h
4h
5h-7h
8h
9h-Fh
27-24
PINMUX11_27_24
Reserved
X
Pin is 3-stated.
Z
Selects Function EMA_A[9]
O
8h
9h-Fh
PINMUX11_23_20
Reserved
X
Selects Function PRU1_R30[17]
O
Reserved
X
Selects Function GP5[9]
I/O
Reserved
X
EMA_A[10]/PRU1_R30[18]/GP5[10]/PRU1_R31[18] Control
0
Selects Function PRU1_R31[18]
I
1h
Selects Function EMA_A[10]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX11_19_16
Reserved
X
Selects Function PRU1_R30[18]
O
Reserved
X
Selects Function GP5[10]
I/O
Reserved
X
EMA_A[11]/PRU1_R30[19]/GP5[11]/PRU1_R31[19] Control
0
Selects Function PRU1_R31[19]
I
1h
Selects Function EMA_A[11]
O
2h-3h
4h
5h-7h
8h
9h-Fh
258
I/O
0
5h-7h
(1)
X
Selects Function GP5[8]
1h
4h
19-16
Reserved
EMA_A[9]/PRU1_R30[17]/GP5[9] Control
2h-3h
23-20
Type (1)
Description
Reserved
X
Selects Function PRU1_R30[19]
O
Reserved
X
Selects Function GP5[11]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-34. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued)
Bit
15-12
Field
Value
PINMUX11_15_12
EMA_A[12]/PRU1_R30[20]/GP5[12]/PRU1_R31[20] Control
0
Selects Function PRU1_R31[20]
I
1h
Selects Function EMA_A[12]
O
2h-3h
4h
5h-7h
8h
9h-Fh
11-8
PINMUX11_11_8
X
Selects Function PRU1_R30[20]
O
Reserved
X
Selects Function GP5[12]
I/O
Reserved
X
EMA_A[13]/PRU0_R30[21]/PRU1_R30[21]/GP5[13]/PRU1_R31[21] Control
Selects Function PRU1_R31[21]
I
1h
Selects Function EMA_A[13]
O
2h
Selects Function PRU0_R30[21]
O
3h
Reserved
X
4h
Selects Function PRU1_R30[21]
O
Reserved
X
8h
9h-Fh
PINMUX11_7_4
Selects Function GP5[13]
I/O
Reserved
X
EMA_A[14]/MMCSD0_DAT[7]/PRU1_R30[22]/GP5[14]/PRU1_R31[22] Control
0
Selects Function PRU1_R31[22]
I
1h
Selects Function EMA_A[14]
O
2h
Selects Function MMCSD0_DAT[7]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[22]
O
5h-7h
8h
9h-Fh
3-0
Reserved
0
5h-7h
7-4
Type (1)
Description
PINMUX11_3_0
Reserved
X
Selects Function GP5[14]
I/O
Reserved
X
EMA_A[15]/MMCSD0_DAT[6]/PRU1_R30[23]/GP5[15]/PRU1_R31[23] Control
0
Selects Function PRU1_R31[23]
1h
Selects Function EMA_A[15]
O
2h
Selects Function MMCSD0_DAT[6]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[23]
O
5h-7h
8h
9h-Fh
I
Reserved
X
Selects Function GP5[15]
I/O
Reserved
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11.5.11.13 Pin Multiplexing Control 12 Register (PINMUX12)
Figure 11-31. Pin Multiplexing Control 12 Register (PINMUX12)
31
28
27
24
23
20
19
16
PINMUX12_31_28
PINMUX12_27_24
PINMUX12_23_20
PINMUX12_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX12_15_12
PINMUX12_11_8
PINMUX12_7_4
PINMUX12_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-35. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
Bit
Field
31-28
Value
PINMUX12_31_28
EMA_A[0]/GP5[0] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[0]
O
2h-7h
8h
9h-Fh
27-24
PINMUX12_27_24
X
Z
Selects Function EMA_A[1]
O
Reserved
X
PINMUX12_23_20
Selects Function GP5[1]
I/O
Reserved
X
EMA_A[2]/GP5[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[2]
O
8h
9h-Fh
PINMUX12_19_16
Reserved
X
Selects Function GP5[2]
I/O
Reserved
X
EMA_A[3]/GP5[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[3]
O
2h-7h
8h
9h-Fh
PINMUX12_15_12
Reserved
X
Selects Function GP5[3]
I/O
Reserved
X
EMA_A[4]/GP5[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[4]
O
2h-7h
8h
9h-Fh
260
Reserved
Pin is 3-stated.
2h-7h
(1)
I/O
0
8h
15-12
X
Selects Function GP5[0]
1h
9h-Fh
19-16
Reserved
EMA_A[1]/GP5[1] Control
2h-7h
23-20
Type (1)
Description
Reserved
X
Selects Function GP5[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-35. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX12_11_8
EMA_A[5]/GP5[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[5]
O
2h-7h
8h
9h-Fh
7-4
PINMUX12_7_4
Reserved
X
Selects Function GP5[5]
I/O
Reserved
X
EMA_A[6]/GP5[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[6]
O
2h-7h
8h
9h-Fh
3-0
Type (1)
Description
PINMUX12_3_0
Reserved
X
Selects Function GP5[6]
I/O
Reserved
X
EMA_A[7]/PRU1_R30[15]/GP5[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[7]
O
2h-3h
4h
5h-7h
8h
9h-Fh
Reserved
X
Selects Function PRU1_R30[15]
O
Reserved
X
Selects Function GP5[7]
I/O
Reserved
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11.5.11.14 Pin Multiplexing Control 13 Register (PINMUX13)
Figure 11-32. Pin Multiplexing Control 13 Register (PINMUX13)
31
28
27
24
23
20
19
16
PINMUX13_31_28
PINMUX13_27_24
PINMUX13_23_20
PINMUX13_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX13_15_12
PINMUX13_11_8
PINMUX13_7_4
PINMUX13_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-36. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
Bit
Field
31-28
Value
PINMUX13_31_28
PRU0_R30[26]/ UHPI_HRW/UPP_CHA_WAIT/GP6[8]/PRU1_R31[17] Control
0
Selects Function PRU1_R31[17]
I
1h
Selects Function PRU0_R30[26]
O
2h
Selects Function UHPI_HRW
I
3h
Reserved
X
4h
Selects Function UPP_CHA_WAIT
5h-7h
8h
9h-Fh
27-24
PINMUX13_27_24
Selects Function GP6[8]
I/O
Reserved
X
0
Pin is 3-stated.
Z
Selects Function PRU0_R30[27]
O
2h
Selects Function UHPI_HHWIL
I
3h
Reserved
4h
Selects Function UPP_CHA_ENABLE
9h-Fh
PINMUX13_23_20
X
I/O
Reserved
X
Selects Function GP6[9]
I/O
Reserved
X
PRU0_R30[28]/UHPI_HCNTL1/UPP_CHA_START/GP6[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[28]
O
2h
Selects Function UHPI_HCNTL1
I
3h
Reserved
X
4h
Selects Function UPP_CHA_START
5h-7h
8h
9h-Fh
262
X
1h
8h
(1)
I/O
Reserved
PRU0_R30[27]/UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9] Control
5h-7h
23-20
Type (1)
Description
I/O
Reserved
X
Selects Function GP6[10]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-36. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX13_19_16
PRU0_R30[29]/UHPI_HCNTL0/UPP_CHA_CLOCK/GP6[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[29]
O
2h
Selects Function UHPI_HCNTL0
I
3h
Reserved
X
4h
Selects Function UPP_CHA_CLOCK
5h-7h
8h
9h-Fh
15-12
PINMUX13_15_12
I/O
Reserved
X
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[30]
O
2h
Selects Function UHPI_HINT
O
3h
Reserved
X
4h
Selects Function PRU1_R30[11]
O
9h-Fh
PINMUX13_11_8
Reserved
X
Selects Function GP6[12]
I/O
Reserved
X
PRU0_R30[31]/UHPI_HRDY/PRU1_R30[12]/GP6[13] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[31]
O
2h
Selects Function UHPI_HRDY
O
3h
Reserved
X
4h
Selects Function PRU1_R30[12]
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX13_7_4
Selects Function GP6[13]
I/O
Reserved
X
CLKOUT/UHPI_HDS2/PRU1_R30[13]/GP6[14] Control
0
Pin is 3-stated.
Z
1h
Selects Function CLKOUT
O
2h
Selects Function UHPI_HDS2
I
3h
Reserved
X
4h
Selects Function PRU1_R30[13]
O
5h-7h
8h
9h-Fh
3-0
X
Selects Function GP6[11]
0
8h
7-4
I/O
Reserved
PRU0_R30[30]/UHPI_HINT/PRU1_R30[11]/GP6[12] Control
5h-7h
11-8
Type (1)
Description
PINMUX13_3_0
Reserved
X
Selects Function GP6[14]
I/O
Reserved
X
RESETOUT/UHPI_HAS/PRU1_R30[14]/GP6[15] Control
0
Selects Function RESETOUT
O
1h
Selects Function RESETOUT
O
2h
Selects Function UHPI_HAS
I
3h
Reserved
X
4h
Selects Function PRU1_R30[14]
O
5h-7h
8h
9h-Fh
Reserved
X
Selects Function GP6[15]
I/O
Reserved
X
11.5.11.15 Pin Multiplexing Control 14 Register (PINMUX14)
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Figure 11-33. Pin Multiplexing Control 14 Register (PINMUX14)
31
28
27
24
23
20
19
16
PINMUX14_31_28
PINMUX14_27_24
PINMUX14_23_20
PINMUX14_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX14_15_12
PINMUX14_11_8
PINMUX14_7_4
PINMUX14_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-37. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
Bit
Field
31-28
Value
PINMUX14_31_28
VP_DIN[2]/UHPI_HD[10]/UPP_D[10]/RMII_RXER/PRU0_R31[24] Control
0
Selects Function PRU0_R31[24]
1h
Selects Function VP_DIN[2]
2h
Selects Function UHPI_HD[10]
3h
Reserved
4h
Selects Function UPP_D[10]
5h-7h
8h
9h-Fh
27-24
PINMUX14_27_24
X
I/O
X
Selects Function RMII_RXER
I
Reserved
X
Selects Function PRU0_R31[25]
1h
Selects Function VP_DIN[3]
2h
Selects Function UHPI_HD[11]
3h
Reserved
4h
Selects Function UPP_D[11]
9h-Fh
PINMUX14_23_20
I
I
I/O
X
I/O
Reserved
X
Selects Function RMII_RXD[0]
I
Reserved
X
VP_DIN[4]/UHPI_HD[12]/UPP_D[12]/RMII_RXD[1]/PRU0_R31[26] Control
0
Selects Function PRU0_R31[26]
I
1h
Selects Function VP_DIN[4]
I
2h
Selects Function UHPI_HD[12]
3h
Reserved
4h
Selects Function UPP_D[12]
5h-7h
8h
9h-Fh
264
I
I/O
VP_DIN[3]/UHPI_HD[11]/UPP_D[11]/RMII_RXD[0]/PRU0_R31[25] Control
8h
(1)
I
Reserved
0
5h-7h
23-20
Type (1)
Description
I/O
X
I/O
Reserved
X
Selects Function RMII_RXD[1]
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-37. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX14_19_16
VP_DIN[5]/UHPI_HD[13]/UPP_D[13]/RMII_TXEN/PRU0_R31[27] Control
0
Selects Function PRU0_R31[27]
1h
Selects Function VP_DIN[5]
2h
Selects Function UHPI_HD[13]
3h
Reserved
4h
Selects Function UPP_D[13]
5h-7h
8h
9h-Fh
15-12
PINMUX14_15_12
X
I/O
X
Selects Function RMII_TXEN
O
Reserved
X
Selects Function PRU0_R31[28]
1h
Selects Function VP_DIN[6]
2h
Selects Function UHPI_HD[14]
3h
Reserved
4h
Selects Function UPP_D[14]
9h-Fh
PINMUX14_11_8
I
I
I/O
X
I/O
Reserved
X
Selects Function RMII_TXD[0]
O
Reserved
X
VP_DIN[7]/UHPI_HD[15]/UPP_D[15]/RMII_TXD[1]/PRU0_R31[29] Control
0
Selects Function PRU0_R31[29]
I
1h
Selects Function VP_DIN[7]
I
2h
Selects Function UHPI_HD[15]
3h
Reserved
4h
Selects Function UPP_D[15]
5h-7h
8h
9h-Fh
PINMUX14_7_4
I/O
X
I/O
Reserved
X
Selects Function RMII_TXD[1]
O
Reserved
X
VP_CLKIN1/UHPI_HDS1/PRU1_R30[9]/GP6[6]/PRU1_R31[16] Control
0
Selects Function PRU1_R31[16]
I
1h
Selects Function VP_CLKIN1
I
2h
Selects Function UHPI_HDS1
I
3h
Reserved
X
4h
Selects Function PRU1_R30[9]
O
5h-7h
8h
9h-Fh
3-0
I
I/O
Reserved
0
8h
7-4
I
VP_DIN[6]/UHPI_HD[14]/UPP_D[14]/RMII_TXD[0]/PRU0_R31[28] Control
5h-7h
11-8
Type (1)
Description
PINMUX14_3_0
Reserved
X
Selects Function GP6[6]
I/O
Reserved
X
VP_CLKIN0/UHPI_HCS/PRU1_R30[10]/GP6[7]/UPP_2xTXCLK Control
0
Selects Function UPP_2xTXCLK
I
1h
Selects Function VP_CLKIN0
I
2h
Selects Function UHPI_HCS
I
3h
Reserved
X
4h
Selects Function PRU1_R30[10]
O
5h-7h
8h
9h-Fh
Reserved
X
Selects Function GP6[7]
I/O
Reserved
X
11.5.11.16 Pin Multiplexing Control 15 Register (PINMUX15)
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Figure 11-34. Pin Multiplexing Control 15 Register (PINMUX15)
31
28
27
24
23
20
19
16
PINMUX15_31_28
PINMUX15_27_24
PINMUX15_23_20
PINMUX15_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX15_15_12
PINMUX15_11_8
PINMUX15_7_4
PINMUX15_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-38. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
Bit
Field
31-28
Value
PINMUX15_31_28
VP_DIN[10]/UHPI_HD[2]/UPP_D[2]/PRU0_R30[10]/PRU0_R31[10] Control
0
Selects Function PRU0_R31[10]
1h
Selects Function VP_DIN[10]
I
2h
Selects Function UHPI_HD[2]
I/O
3h
Reserved
4h
Selects Function UPP_D[2]
5h-7h
8h
9h-Fh
27-24
PINMUX15_27_24
Reserved
X
Selects Function PRU0_R30[10]
O
Reserved
X
Selects Function PRU0_R31[11]
1h
Selects Function VP_DIN[11]
I
2h
Selects Function UHPI_HD[3]
I/O
3h
Reserved
4h
Selects Function UPP_D[3]
9h-Fh
PINMUX15_23_20
I
X
I/O
Reserved
X
Selects Function PRU0_R30[11]
O
Reserved
X
VP_DIN[12]/UHPI_HD[4]/UPP_D[4]/PRU0_R30[12]/PRU0_R31[12] Control
0
Selects Function PRU0_R31[12]
I
1h
Selects Function VP_DIN[12]
I
2h
Selects Function UHPI_HD[4]
I/O
3h
Reserved
4h
Selects Function UPP_D[4]
5h-7h
8h
9h-Fh
266
X
I/O
0
8h
(1)
I
VP_DIN[11]/UHPI_HD[3]/UPP_D[3]/PRU0_R30[11]/PRU0_R31[11] Control
5h-7h
23-20
Type (1)
Description
X
I/O
Reserved
X
Selects Function PRU0_R30[12]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-38. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
19-16
Field
Value
PINMUX15_19_16
VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_D[5]/PRU0_R30[13]/PRU0_R31[13] Control
0
Selects Function PRU0_R31[13]
1h
Selects Function VP_DIN[13]_FIELD
2h
Selects Function UHPI_HD[5]
3h
Reserved
4h
Selects Function UPP_D[5]
5h-7h
8h
9h-Fh
15-12
PINMUX15_15_12
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[13]
O
Reserved
X
0
Selects Function PRU0_R31[14]
1h
Selects Function VP_DIN[14]_HSYNC
2h
Selects Function UHPI_HD[6]
3h
Reserved
4h
Selects Function UPP_D[6]
8h
9h-Fh
PINMUX15_11_8
I
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[14]
O
Reserved
X
VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_D[7]/PRU0_R30[15]/PRU0_R31[15]
Control
0
Selects Function PRU0_R31[15]
1h
Selects Function VP_DIN[15]_VSYNC
2h
Selects Function UHPI_HD[7]
3h
Reserved
4h
Selects Function UPP_D[7]
5h-7h
8h
9h-Fh
7-4
I
VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_D[6]/PRU0_R30[14]/PRU0_R31[14]
Control
5h-7h
11-8
Type (1)
Description
PINMUX15_7_4
I
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[15]
O
Reserved
X
VP_DIN[0]/UHPI_HD[8]/UPP_D[8]/RMII_CRS_DV/PRU1_R31[29] Control
0
Selects Function PRU1_R31[29]
I
1h
Selects Function VP_DIN[0]
I
2h
Selects Function UHPI_HD[8]
3h
Reserved
4h
Selects Function UPP_D[8]
5h-7h
8h
9h-Fh
I/O
X
I/O
Reserved
X
Selects Function RMII_CRS_DV
I
Reserved
X
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Table 11-38. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
Field
3-0
PINMUX15_3_0
Value
VP_DIN[1]/UHPI_HD[9]/UPP_D[9]/RMII_MHZ_50_CLK/PRU0_R31[23] Control
0
Selects Function PRU0_R31[23]. Enables sourcing of the 50 MHz reference clock
from an external source on the RMII_MHZ_50_CLK pin to the EMAC.
1h
Selects Function VP_DIN[1]
2h
Selects Function UHPI_HD[9]
3h
Reserved
4h
Selects Function UPP_D[9]
5h-7h
8h
9h-Fh
268
Type (1)
Description
I
I
I/O
X
I/O
Reserved
X
Selects Function RMII_MHZ_50_CLK. Enables sourcing of the 50 MHz reference
clock from PLL0_SYSCLK7 to the EMAC. Also, PLL0_SYSCLK7 is driven out on the
RMII_MHZ_50_CLK pin. Note that the SYSCLK7 output clock does not meet the
RMII reference clock specification of 50 MHz +/-50 ppm. See Section 7.3.4 for more
information.
O
Reserved
X
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11.5.11.17 Pin Multiplexing Control 16 Register (PINMUX16)
Figure 11-35. Pin Multiplexing Control 16 Register (PINMUX16)
31
28
27
24
23
20
19
16
PINMUX16_31_28
PINMUX16_27_24
PINMUX16_23_20
PINMUX16_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX16_15_12
PINMUX16_11_8
PINMUX16_7_4
PINMUX16_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-39. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
Bit
31-28
Field
Value
PINMUX16_31_28
VP_DOUT[2]/LCD_D[2]/UPP_XD[10]/GP7[10]/PRU1_R31[10] Control
0
Selects Function PRU1_R31[10]
I
1h
Selects Function VP_DOUT[2]
O
2h
Selects Function LCD_D[2]
I/O
3h
Reserved
4h
Selects Function UPP_XD[10]
5h-7h
8h
9h-Fh
27-24
PINMUX16_27_24
Reserved
X
Selects Function GP7[10]
I/O
Reserved
X
0
Selects Function PRU1_R31[11]
I
1h
Selects Function VP_DOUT[3]
O
2h
Selects Function LCD_D[3]
I/O
3h
Reserved
4h
Selects Function UPP_XD[11]
8h
9h-Fh
PINMUX16_23_20
X
I/O
Reserved
X
Selects Function GP7[11]
I/O
Reserved
X
VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12]/PRU1_R31[12] Control
0
Selects Function PRU1_R31[12]
1h
Selects Function VP_DOUT[4]
O
2h
Selects Function LCD_D[4]
I/O
3h
Reserved
4h
Selects Function UPP_XD[12]
5h-7h
8h
9h-Fh
(1)
X
I/O
VP_DOUT[3]/LCD_D[3]/UPP_XD[11]/GP7[11]/PRU1_R31[11] Control
5h-7h
23-20
Type (1)
Description
I
X
I/O
Reserved
X
Selects Function GP7[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-39. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX16_19_16
VP_DOUT[5]/LCD_D[5]/UPP_XD[13]/GP7[13]/PRU1_R31[13] Control
0
Selects Function PRU1_R31[13]
I
1h
Selects Function VP_DOUT[5]
O
2h
Selects Function LCD_D[5]
I/O
3h
Reserved
4h
Selects Function UPP_XD[13]
5h-7h
8h
9h-Fh
15-12
PINMUX16_15_12
X
Selects Function GP7[13]
I/O
Reserved
X
Selects Function PRU1_R31[14]
1h
Selects Function VP_DOUT[6]
O
2h
Selects Function LCD_D[6]
I/O
3h
Reserved
4h
Selects Function UPP_XD[14]
9h-Fh
PINMUX16_11_8
I
X
I/O
Reserved
X
Selects Function GP7[14]
I/O
Reserved
X
VP_DOUT[7]/LCD_D[7]/UPP_XD[15]/GP7[15]/PRU1_R31[15] Control
0
Selects Function PRU1_R31[15]
I
1h
Selects Function VP_DOUT[7]
O
2h
Selects Function LCD_D[7]
I/O
3h
Reserved
4h
Selects Function UPP_XD[15]
5h-7h
8h
9h-Fh
PINMUX16_7_4
X
I/O
Reserved
X
Selects Function GP7[15]
I/O
Reserved
X
VP_DIN[8]/UHPI_HD[0]/UPP_D0/GP6[5]/PRU1_R31[0] Control
0
Selects Function PRU1_R31[0]
1h
Selects Function VP_DIN[8]
2h
Selects Function UHPI_HD[0]
3h
Reserved
4h
Selects Function UPP_D[0]
5h-7h
8h
9h-Fh
3-0
I/O
Reserved
0
8h
7-4
X
VP_DOUT[6]/LCD_D[6]/UPP_XD[14]/GP7[14]/PRU1_R31[14] Control
5h-7h
11-8
Type (1)
Description
PINMUX16_3_0
I
I
I/O
X
I/O
Reserved
X
Selects Function GP6[5]
I/O
Reserved
X
VP_DIN[9]/UHPI_HD[1]/UPP_D[1]/PRU0_R30[9]/PRU0_R31[9] Control
0
Selects Function PRU0_R31[9]
1h
Selects Function VP_DIN[9]
2h
Selects Function UHPI_HD[1]
3h
Reserved
4h
Selects Function UPP_D[1]
5h-7h
8h
9h-Fh
I
I
I/O
X
I/O
Reserved
X
Selects Function PRU0_R30[9]
O
Reserved
X
11.5.11.18 Pin Multiplexing Control 17 Register (PINMUX17)
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Figure 11-36. Pin Multiplexing Control 17 Register (PINMUX17)
31
28
27
24
23
20
19
16
PINMUX17_31_28
PINMUX17_27_24
PINMUX17_23_20
PINMUX17_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX17_15_12
PINMUX17_11_8
PINMUX17_7_4
PINMUX17_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-40. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
Bit
31-28
Field
Value
PINMUX17_31_28
VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2]/BOOT[2] Control
0
Selects Function BOOT[2]
I
1h
Selects Function VP_DOUT[10]
O
2h
Selects Function LCD_D[10]
I/O
3h
Reserved
4h
Selects Function UPP_XD[2]
5h-7h
8h
9h-Fh
27-24
PINMUX17_27_24
Reserved
X
Selects Function GP7[2]
I/O
Reserved
X
0
Selects Function BOOT[3]
1h
Selects Function VP_DOUT[11]
O
2h
Selects Function LCD_D[11]
I/O
3h
Reserved
4h
Selects Function UPP_XD[3]
8h
9h-Fh
PINMUX17_23_20
I
X
I/O
Reserved
X
Selects Function GP7[3]
I/O
Reserved
X
VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4]/BOOT[4] Control
0
Selects Function BOOT[4]
I
1h
Selects Function VP_DOUT[12]
O
2h
Selects Function LCD_D[12]
I/O
3h
Reserved
4h
Selects Function UPP_XD[4]
5h-7h
8h
9h-Fh
(1)
X
I/O
VP_DOUT[11]/LCD_D[11]/UPP_XD[3]/GP7[3]/BOOT[3] Control
5h-7h
23-20
Type (1)
Description
X
I/O
Reserved
X
Selects Function GP7[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-40. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX17_19_16
VP_DOUT[13]/LCD_D[13]/UPP_XD[5]/GP7[5]/BOOT[5] Control
0
Selects Function BOOT[5]
I
1h
Selects Function VP_DOUT[13]
O
2h
Selects Function LCD_D[13]
I/O
3h
Reserved
4h
Selects Function UPP_XD[5]
5h-7h
8h
9h-Fh
15-12
PINMUX17_15_12
X
Selects Function GP7[5]
I/O
Reserved
X
Selects Function BOOT[6]
1h
Selects Function VP_DOUT[14]
O
2h
Selects Function LCD_D[14]
I/O
3h
Reserved
4h
Selects Function UPP_XD[6]
9h-Fh
PINMUX17_11_8
I
X
I/O
Reserved
X
Selects Function GP7[6]
I/O
Reserved
X
VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7]/BOOT[7] Control
0
Selects Function BOOT[7]
I
1h
Selects Function VP_DOUT[15]
O
2h
Selects Function LCD_D[15]
I/O
3h
Reserved
4h
Selects Function UPP_XD[7]
5h-7h
8h
9h-Fh
PINMUX17_7_4
X
I/O
Reserved
X
Selects Function GP7[7]
I/O
Reserved
X
VP_DOUT[0]/LCD_D[0]/UPP_XD[8]/GP7[8]/PRU1_R31[8] Control
0
Selects Function PRU1_R31[8]
I
1h
Selects Function VP_DOUT[0]
O
2h
Selects Function LCD_D[0]
I/O
3h
Reserved
4h
Selects Function UPP_XD[8]
5h-7h
8h
9h-Fh
3-0
I/O
Reserved
0
8h
7-4
X
VP_DOUT[14]/LCD_D[14]/UPP_XD[6]/GP7[6]/BOOT[6] Control
5h-7h
11-8
Type (1)
Description
PINMUX17_3_0
X
I/O
Reserved
X
Selects Function GP7[8]
I/O
Reserved
X
VP_DOUT[1]/LCD_D[1]/UPP_XD[9]/GP7[9]/PRU1_R31[9] Control
0
Selects Function PRU1_R31[9]
1h
Selects Function VP_DOUT[1]
O
2h
Selects Function LCD_D[1]
I/O
3h
Reserved
4h
Selects Function UPP_XD[9]
5h-7h
8h
9h-Fh
I
X
I/O
Reserved
X
Selects Function GP7[9]
I/O
Reserved
X
11.5.11.19 Pin Multiplexing Control 18 Register (PINMUX18)
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Figure 11-37. Pin Multiplexing Control 18 Register (PINMUX18)
31
28
27
24
23
20
19
16
PINMUX18_31_28
PINMUX18_27_24
PINMUX18_23_20
PINMUX18_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX18_15_12
PINMUX18_11_8
PINMUX18_7_4
PINMUX18_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-41. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
Bit
31-28
Field
Value
PINMUX18_31_28
MMCSD1_DAT[6]/LCD_MCLK/PRU1_R30[6]/GP8[10]/PRU1_R31[7] Control
0
Selects Function PRU1_R31[7]
1h
Selects Function MMCSD1_DAT[6]
I/O
2h
Selects Function LCD_MCLK
O
3h
Reserved
X
4h
Selects Function PRU1_R30[6]
O
Reserved
X
5h-7h
8h
9h-Fh
27-24
PINMUX18_27_24
Selects Function GP8[10]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function MMCSD1_DAT[7]
I/O
2h
Selects Function LCD_PCLK
O
3h
Reserved
X
4h
Selects Function PRU1_R30[7]
O
8h
9h-Fh
PINMUX18_23_20
Z
Reserved
X
Selects Function GP8[11]
I/O
Reserved
X
PRU0_R30[22]/PRU1_R30[8]/UPP_CHB_WAIT/GP8[12]/PRU1_R31[24] Control
0
Selects Function PRU1_R31[24]
I
1h
Selects Function PRU0_R30[22]
O
2h
Selects Function PRU1_R30[8]
O
3h
Reserved
4h
Selects Function UPP_CHB_WAIT
5h-7h
8h
9h-Fh
(1)
I
MMCSD1_DAT[7]/LCD_PCLK/PRU1_R30[7]/GP8[11] Control
5h-7h
23-20
Type (1)
Description
X
I/O
Reserved
X
Selects Function GP8[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-41. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX18_19_16
PRU0_R30[23]/MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13]/PRU1_R31[25]
Control
0
Selects Function PRU1_R31[25]
I
1h
Selects Function PRU0_R30[23]
O
2h
Selects Function MMCSD1_CMD
I/O
3h
Reserved
4h
Selects Function UPP_CHB_ENABLE
5h-7h
8h
9h-Fh
15-12
PINMUX18_15_12
Selects Function GP8[13]
I/O
Reserved
X
Selects Function PRU1_R31[26]
I
Selects Function PRU0_R30[24]
O
2h
Selects Function MMCSD1_CLK
O
3h
Reserved
4h
Selects Function UPP_CHB_START
PINMUX18_11_8
X
I/O
Reserved
X
Selects Function GP8[14]
I/O
Reserved
X
PRU0_R30[25]/MMCSD1_DAT[0]/UPP_CHB_CLOCK/GP8[15]/PRU1_R31[27]
Control
0
Selects Function PRU1_R31[27]
I
1h
Selects Function PRU0_R30[25]
O
2h
Selects Function MMCSD1_DAT[0]
I/O
3h
Reserved
4h
Selects Function UPP_CHB_CLOCK
5h-7h
8h
9h-Fh
PINMUX18_7_4
X
I/O
Reserved
X
Selects Function GP8[15]
I/O
Reserved
X
VP_DOUT[8]/LCD_D[8]/UPP_XD[0]/GP7[0]/BOOT[0] Control
0
Selects Function BOOT[0]
1h
Selects Function VP_DOUT[8]
O
2h
Selects Function LCD_D[8]
I/O
3h
Reserved
4h
Selects Function UPP_XD[0]
5h-7h
8h
9h-Fh
PINMUX18_3_0
I
X
I/O
Reserved
X
Selects Function GP7[0]
I/O
Reserved
X
VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1]/BOOT[1] Control
0
Selects Function BOOT[1]
I
1h
Selects Function VP_DOUT[9]
O
2h
Selects Function LCD_D[9]
I/O
3h
Reserved
4h
Selects Function UPP_XD[1]
5h-7h
8h
9h-Fh
274
X
0
8h
3-0
Reserved
1h
9h-Fh
7-4
X
I/O
PRU0_R30[24]/MMCSD1_CLK/UPP_CHB_START/GP8[14]/PRU1_R31[26]
Control
5h-7h
11-8
Type (1)
Description
X
I/O
Reserved
X
Selects Function GP7[1]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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11.5.11.20 Pin Multiplexing Control 19 Register (PINMUX19)
Figure 11-38. Pin Multiplexing Control 19 Register (PINMUX19)
31
28
27
24
23
20
19
16
PINMUX19_31_28
PINMUX19_27_24
PINMUX19_23_20
PINMUX19_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX19_15_12
PINMUX19_11_8
PINMUX19_7_4
PINMUX19_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-42. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
Bit
31-28
Field
Value
PINMUX19_31_28
RTCK/GP8[0] Control
0
Selects Function RTCK
O
1h
Selects Function RTCK
O
2h-7h
8h
9h-Fh
27-24
PINMUX19_27_24
I/O
Reserved
X
0
Selects Function PRU1_R31[28]
I
Reserved
X
2h
Selects Function LCD_AC_ENB_CS
O
9h-Fh
PINMUX19_23_20
Reserved
X
Selects Function GP6[0]
I/O
Reserved
X
VP_CLKOUT3/PRU1_R30[0]/GP6[1]/PRU1_R31[1] Control
0
Selects Function PRU1_R31[1]
I
1h
Selects Function VP_CLKOUT3
O
Reserved
X
Selects Function PRU1_R30[0]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX19_19_16
Reserved
X
Selects Function GP6[1]
I/O
Reserved
X
VP_CLKIN3/MMCSD1_DAT[1]/PRU1_R30[1]/GP6[2]/PRU1_R31[2] Control
0
Selects Function PRU1_R31[2]
1h
Selects Function VP_CLKIN3
2h
Selects Function MMCSD1_DAT[1]
3h
Reserved
X
4h
Selects Function PRU1_R30[1]
O
5h-7h
8h
9h-Fh
(1)
X
Selects Function GP8[0]
1h
8h
19-16
Reserved
LCD_AC_ENB_CS/GP6[0]/PRU1_R31[28] Control
3h-7h
23-20
Type (1)
Description
I
I
I/O
Reserved
X
Selects Function GP6[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-42. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX19_15_12
VP_CLKOUT2/MMCSD1_DAT[2]/PRU1_R30[2]/GP6[3]/PRU1_R31[3] Control
0
Selects Function PRU1_R31[3]
I
1h
Selects Function VP_CLKOUT2
O
2h
Selects Function MMCSD1_DAT[2]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[2]
O
5h-7h
8h
9h-Fh
11-8
PINMUX19_11_8
I/O
Reserved
X
Selects Function PRU1_R31[4]
1h
Selects Function VP_CLKIN2
2h
Selects Function MMCSD1_DAT[3]
3h
Reserved
X
4h
Selects Function PRU1_R30[3]
O
9h-Fh
PINMUX19_7_4
I
I
I/O
Reserved
X
Selects Function GP6[4]
I/O
Reserved
X
MMCSD1_DAT[4]/LCD_VSYNC/PRU1_R30[4]/GP8[8]/PRU1_R31[5] Control
0
Selects Function PRU1_R31[5]
1h
Selects Function MMCSD1_DAT[4]
I/O
2h
Selects Function LCD_VSYNC
O
3h
Reserved
X
4h
Selects Function PRU1_R30[4]
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX19_3_0
I
Selects Function GP8[8]
I/O
Reserved
X
MMCSD1_DAT[5]/LCD_HSYNC/PRU1_R30[5]/GP8[9]/PRU1_R31[6] Control
0
Selects Function PRU1_R31[6]
1h
Selects Function MMCSD1_DAT[5]
I/O
2h
Selects Function LCD_HSYNC
O
3h
Reserved
X
4h
Selects Function PRU1_R30[5]
O
5h-7h
8h
9h-Fh
276
X
Selects Function GP6[3]
0
8h
3-0
Reserved
VP_CLKIN2/MMCSD1_DAT[3]/PRU1_R30[3]/GP6[4]/PRU1_R31[4] Control
5h-7h
7-4
Type (1)
Description
I
Reserved
X
Selects Function GP8[9]
I/O
Reserved
System Configuration (SYSCFG) Module
X
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11.5.12 Suspend Source Register (SUSPSRC)
The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals
that support emulation suspend. A value of 1 (default) for a SUSPSRC bit corresponding to the peripheral,
indicates that the DSP emulator controls the peripheral's emulation suspend signal. You should maintain
this register with its default values. The flexibility of the device architecture allows either the ARM or the
DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is a
matter of software convention, during an emulation halt, the device must know which peripherals are
associated with the halting processor, so that only those modules receive the suspend signal. This allows
peripherals associated with the other (unhalted) processor to continue normal operation.
The SUSPSRC is shown in Figure 11-39 and described in Table 11-43.
Figure 11-39. Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
Reserved
Reserved
TIMER64P_2SRC
TIMER64P_1SRC
TIMER64P_0SRC
Reserved
Reserved
EPWM1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
23
22
21
20
19
18
17
16
EPWM0SRC
SPI1SRC
SPI0SRC
UART2SRC
UART1SRC
UART0SRC
I2C1SRC
I2C0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
Reserved
VPIFSRC
SATASRC
HPISRC
Reserved
Reserved
USB0SRC
MCBSP1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
MCBSP0SRC
PRUSRC
EMACSRC
UPPSRC
TIMER64P_3SRC
ECAP2SRC
ECAP1SRC
ECAP0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-43. Suspend Source Register (SUSPSRC) Field Descriptions
Bit
31-30
29
28
27
26-25
24
23
22
Field
Reserved
Value
1
TIMER64P_2SRC
Reserved. Write the default value to all bits when modifying this register.
Timer2 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64P_1SRC
Timer1 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64P_0SRC
Reserved
Description
Timer0 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
EPWM1SRC
EPWM1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
EPWM0SRC
EPWM0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
SPI1SRC
SPI1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 11-43. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
Field
21
SPI0SRC
20
19
18
17
16
USB0SRC
4
278
1
DSP is the source of the emulation suspend.
UART1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
UART0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
I2C1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
I2C0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
VPIF Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
SATA Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
HPISRC
Reserved
5
ARM is the source of the emulation suspend.
SATASRC
9
6
UART2 Emulation Suspend Source.
0
I2C0SRC
11-10
7
DSP is the source of the emulation suspend.
I2C1SRC
VPIFSRC
8
ARM is the source of the emulation suspend.
1
UART0SRC
Reserved
12
0
UART1SRC
14
Description
SPI0 Emulation Suspend Source.
UART2SRC
15
13
Value
HPI Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
USB0 (USB 2.0) Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
MCBSP1SRC
McBSP1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
MCBSP0SRC
McBSP0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
PRUSRC
PRU Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
EMACSRC
EMAC Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
UPPSRC
uPP Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 11-43. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
3
2
1
0
Field
Value
TIMER64P_3SRC
Description
Timer3 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP2SRC
ECAP2 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP1SRC
ECAP1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP0SRC
ECAP0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
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11.5.13 Chip Signal Register (CHIPSIG)
The DSP has access to 4 ARM interrupt events in the ARM interrupt map: SYSCFG_CHIPINT0,
SYSCFG_CHIPINT1, SYSCFG_CHIPINT2, and SYSCFG_CHIPINT3. The ARM has access to 3 DSP
interrupt events in the DSP interrupt event map: SYSCFG_CHIPINT2, SYSCFG_CHIPINT3, and NMI.
NOTE: SYSCFG_CHIPINT2 and SYSCFG_CHIPINT3 are essentially for the ARM to interrupt the
DSP. However, these are additionally mapped to the ARM interrupt controller (AINTC), so
that it can be used as debug interrupts, in case there is a need to halt both processors
simultaneously.
The ARM may generate an interrupt to the DSP by setting one of the two CHIPSIG[3-2] bits or an NMI
interrupt by setting the CHIPSIG[4] bit in the chip signal register (CHIPSIG). The DSP may generate an
interrupt to the ARM by setting one of the four CHIPSIG[3-0] bits. Writing a 1 to these bits sets the
interrupts, writing a 0 has no effect. Reads return the value of these bits and can also be used as status
bits. The CHIPSIG is shown in Figure 11-40 and described in Table 11-44.
Figure 11-40. Chip Signal Register (CHIPSIG)
31
16
Reserved
R-0
15
5
Reserved
4
3
CHIPSIG4 CHIPSIG3
R-0
R/W-0
R/W-0
2
1
CHIPSIG2 CHIPSIG1
R/W-0
R/W-0
0
CHIPSIG0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-44. Chip Signal Register (CHIPSIG) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1
0
280
Value
0
Description
Reserved
Asserts DSP NMI interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG3
Asserts SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG2
Asserts SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG1
Asserts SYSCFG_CHIPINT1 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG0
Asserts SYSCFG_CHIPINT0 interrupt.
0
No effect
1
Asserts interrupt
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11.5.14 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 11-41 and described in Table 11-45.
For more information on ARM interrupts, see the ARM Interrupt Controller (AINTC) chapter. For more
information on DSP interrupts, see the DSP Subsystem chapter.
Figure 11-41. Chip Signal Clear Register (CHIPSIG_CLR)
31
16
Reserved
R-0
15
5
Reserved
4
3
CHIPSIG4 CHIPSIG3
R-0
R/W-0
R/W-0
2
1
CHIPSIG2 CHIPSIG1
R/W-0
R/W-0
0
CHIPSIG0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-45. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1
0
Value
0
Description
Reserved
Clears DSP NMI interrupt.
0
No effect
1
Clears interrupt
CHIPSIG3
Clears SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG2
Clears SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG1
Clears SYSCFG_CHIPINT1 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG0
Clears SYSCFG_CHIPINT0 interrupt.
0
No effect
1
Clears interrupt
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11.5.15 Chip Configuration 0 Register (CFGCHIP0)
The chip configuration 0 register (CFGCHIP0) controls the following functions:
• PLL Controller 0 memory-mapped register lock: Used to lock out writes to the PLLC0 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC0 register space.
• EDMA3_0 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP0
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_0 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
The CFGCHIP0 is shown in Figure 11-42 and described in Table 11-46.
Figure 11-42. Chip Configuration 0 Register (CFGCHIP0)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PLL_MASTER_LOCK
EDMA30TC1DBS
EDMA30TC0DBS
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-46. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
Bit
31-5
4
3-2
1-0
282
Field
Reserved
Value
0
PLL_MASTER_LOCK
Description
Reserved.
PLLC0 MMRs lock.
0
PLLC0 MMRs are freely accessible.
1
All PLLC0 MMRs are locked.
EDMA30TC1DBS
EDMA3_0_TC1 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
EDMA30TC0DBS
EDMA3_0_TC0 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
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11.5.16 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• eCAP0/1/2 event input source: Allows using McASP0 TX/RX events or various EMAC TX/RX
threshold, pulse, or miscellaneous interrupt events as eCAP event input sources.
• HPI Control: Allows HPIEN bit control that determines whether or not the HPI module has control over
the HPI pins (multiplexed with other peripheral pins). It also provides configurability to select whether
the host address is a word address or a byte address mode.
• EDMA3_1 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP1
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_1 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
• McASP0 AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP0 AMUTEIN signal.
The CFGCHIP1 is shown in Figure 11-43 and described in Table 11-47.
Figure 11-43. Chip Configuration 1 Register (CFGCHIP1)
31
27
15
26
22
21
17
16
CAP2SRC
CAP1SRC
CAP0SRC
HPIBYTEAD
R/W-0
R/W-0
R/W-0
R/W-0
14
13
12
11
8
HPIENA
EDMA31TC0DBS
TBCLKSYNC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
7
4
3
0
Reserved
AMUTESEL0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 11-47. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
Bit
31-27
Field
Value
CAP2SRC
Selects the eCAP2 module event input.
0
eCAP2 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
CAP1SRC
Reserved
Selects the eCAP1 module event input.
0
eCAP1 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
Reserved
7h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
284
Reserved
7h
13h-1Fh
26-22
Description
Reserved
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Table 11-47. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued)
Bit
21-17
Field
Value
CAP0SRC
Selects the eCAP0 module event input.
0
eCAP0 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
15
14-13
12
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
HPIBYTEAD
HPI Byte/Word Address Mode select.
Host address is a word address.
1
Host address is a byte address.
HPI Enable Bit.
0
HPI is disabled.
1
HPI is enabled.
EDMA31TC0DBS
EDMA3_1_TC0 Default Burst Size.
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
TBCLKSYNC
Reserved
3-0
AMUTESEL0
Reserved
0
HPIENA
11-4
Reserved
7h
13h-1Fh
16
Description
eHRPWM Module Time Base Clock Synchronization. Allows you to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
0
Time base clock (TBCLK) within each enabled eHRPWM module is stopped.
1
All enabled eHRPWM module clocks are started with the first rising edge of TBCLK aligned. For
perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each eHRPWM
module must be set identically.
0
Reserved. Write the default value to all bits when modifying this register.
Selects the source of McASP0 AMUTEIN signal.
0
Drive McASP0 AMUTEIN signal low.
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
Reserved
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11.5.17 Chip Configuration 2 Register (CFGCHIP2)
The chip configuration 2 register (CFGCHIP2) controls the following functions:
• USB1.1 OHCI
• USB2.0 OTG PHY
The CFGCHIP2 is shown in Figure 11-44 and described in Table 11-48.
Figure 11-44. Chip Configuration 2 Register (CFGCHIP2)
31
24
Reserved
R-0
23
18
15
14
17
16
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
R-0
R-0
R-0
12
11
10
9
8
RESET
USB0OTGMODE
13
USB1PHYCLKMUX
USB0PHYCLKMUX
USB0PHYPWDN
USB0OTGPWRDN
USB0DATPOL
R/W-1
R/W-3h
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
3
7
6
5
4
USB1SUSPENDM
USB0PHY_PLLON
USB0SESNDEN
USB0VBDTCTEN
USB0REF_FREQ
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-48. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
Bit
31-18
17
16
15
14-13
12
11
10
286
Field
Reserved
Value
0
USB0PHYCLKGD
Description
Reserved
Status of USB2.0 PHY.
0
Clock is not present, power is not good, and PLL has not locked.
1
Clock is present, power is good, and PLL has locked.
USB0VBUSSENSE
Status of USB2.0 PHY VBUS sense.
0
PHY is not sensing voltage presence on the VBUS pin.
1
PHY is sensing voltage presence on the VBUS pin.
RESET
USB2.0 PHY reset.
0
Not in reset.
1
USB2.0 PHY in reset.
USB0OTGMODE
USB2.0 OTG subsystem mode.
0
No override. PHY drive signals to controller based on its comparators for VBUS and ID pins.
1h
Override phy values to force USB host operation.
2h
Override phy values to force USB device operation.
3h
Override phy values to force USB host operation with VBUS low.
USB1PHYCLKMUX
USB1.1 PHY reference clock input mux. Controls clock mux to USB1.1.
0
USB1.1 PHY reference clock is sourced by output of USB2.0 PHY.
1
USB1.1 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
USB0PHYCLKMUX
USB2.0 PHY reference clock input mux.
0
USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
1
USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL.
USB0PHYPWDN
USB2.0 PHY operation state control.
0
USB2.0 PHY is enabled and is in operating state (normal operation).
1
USB2.0 PHY is disabled and powered down.
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Table 11-48. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions (continued)
Bit
9
8
7
6
5
4
3-0
Field
Value
USB0OTGPWRDN
Description
USB2.0 OTG subsystem (SS) operation state control.
0
OTG SS is enabled and is in operating state (normal operation).
1
OTG SS is disabled and is powered down.
USB0DATPOL
USB2.0 differential data lines polarity selector.
0
Differential data polarities are inverted (USB_DP is connected to D- and USB_DM is
connected to D+).
1
Differential data polarity are not altered (USB_DP is connected to D+ and USB_DM is
connected to D-).
USB1SUSPENDM
USB1.1 suspend mode.
0
Needs to be 0 whenever USB1.1 PHY is unpowered.
1
Enable USB1.1 PHY.
USB0PHY_PLLON
Drives USB2.0 PHY, allowing or preventing it from stopping the 48 MHz clock during
USB SUSPEND.
0
USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND.
1
USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND
USB0SESNDEN
USB2.0 Session End comparator enable.
0
Session End comparator is disabled.
1
Session End comparator is enabled.
USB0VBDTCTEN
USB2.0 VBUS line comparators enable.
0
All VBUS line comparators are disabled.
1
All VBUS line comparators are enabled.
USB0REF_FREQ
USB2.0 PHY reference clock input frequencies.
0
Reserved
1h
12 MHz
2h
24 MHz
3h
48 MHz
4h
19.2 MHz
5h
38.4 MHz
6h
13 MHz
7h
26 MHz
8h
20 MHz
9h
40 MHz
Ah-Fh
Reserved
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11.5.18 Chip Configuration 3 Register (CFGCHIP3)
The chip configuration 3 register (CFGCHIP3) controls the following peripheral/module functions:
• EMAC MII/RMII Mode Select.
• uPP Clock Source Control: Allows control for the source of the uPP 2x transmit clock.
• PLL Controller 1 memory-mapped register lock: Used to lock out writes to the PLLC1 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC1 register space.
• ASYNC3 Clock Source Control: Allows control for the source of the ASYNC3 clock.
• PRU Event Input Select.
• DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.5) hardware clock divider is provided to generate
133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this
clock divider.
• EMIFA Module Clock Source Control: Allows control for the source of the EMIFA module clock.
The CFGCHIP3 is shown in Figure 11-45 and described in Table 11-49.
Figure 11-45. Chip Configuration 3 Register (CFGCHIP3)
31
16
Reserved
R-0
15
9
8
Reserved
RMII_SEL
R/W-7Fh
R/W-1
7
6
5
4
3
2
1
0
Reserved
UPP_TX_CLKSRC
PLL1_MASTER_LOCK
ASYNC3_CLKSRC
PRUEVTSEL
DIV45PENA
EMA_CLKSRC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-49. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-9
Reserved
7Fh
8
RMII_SEL
7
Reserved
6
UPP_TX_CLKSRC
5
4
3
288
Description
Reserved
Reserved. Write the default value to all bits when modifying this register.
EMAC MII/RMII mode select.
0
MII mode
1
RMII mode
0
Reserved. Write the default value when modifying this register.
Clock source for uPP 2x transmit clock.
0
Clock driven by ASYNC3.
1
Clock driven by external signal, 2xTXCLK.
PLL1_MASTER_LOCK
PLLC1 MMRs lock.
0
PLLC1 MMRs are freely accessible.
1
All PLLC1 MMRs are locked.
ASYNC3_CLKSRC
Clock source for ASYNC3.
0
Clock driven by PLL0_SYSCLK2.
1
Clock driven by PLL1_SYSCLK2.
PRUEVTSEL
PRU event input select.
0
Normal mode
1
Alternate mode
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Table 11-49. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions (continued)
Bit
2
1
0
Field
Value
DIV45PENA
Description
Controls the fixed DIV4.5 divider in the PLL controller.
0
Divide by 4.5 is disabled.
1
Divide by 4.5 is enabled.
EMA_CLKSRC
Clock source for EMIFA clock domain.
Reserved
0
Clock driven by PLL0_SYSCLK3
1
Clock driven by DIV4.5 PLL output
0
Reserved. Write the default value when modifying this register.
11.5.19 Chip Configuration 4 Register (CFGCHIP4)
The chip configuration 4 register (CFGCHIP4) is used for clearing the AMUNTEIN signal for McASP0.
Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0, if it was
previously set; reads always return a value of 0. The CFGCHIP4 is shown in Figure 11-46 and described
in Table 11-50.
Figure 11-46. Chip Configuration 4 Register (CFGCHIP4)
31
16
Reserved
R-0
15
8
7
1
0
Reserved
Reserved
AMUTECLR0
R/W-FFh
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-50. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
Reserved
FFh
Reserved. Write the default value to all bits when modifying this register.
7-1
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
0
AMUTECLR0
Reserved
Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1.
0
No effect
1
Clears interrupt
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11.5.20 VTP I/O Control Register (VTPIO_CTL)
The VTP I/O control register (VTPIO_CTL) is used to control the calibration of the DDR2/mDDR memory
controller I/Os with respect to voltage, temperature, and process (VTP). The voltage, temperature, and
process information is used to control the IO's output impedance. The VTPIO_CTL is shown in Figure 1147 and described in Table 11-51.
Figure 11-47. VTP I/O Control Register (VTPIO_CTL)
31
24
Reserved
R-0
23
19
18
17
16
Reserved
VREFEN
VREFTAP
R-0
R/W-0
R/W-0
15
14
13
12
9
READY
IOPWRDN
CLKRZ
Reserved
PWRSAVE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
5
7
6
LOCK
POWERDN
D
3
F
R/W-0
R/W-1
R/W-6h
R/W-7h
8
2
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-51. VTP I/O Control Register (VTPIO_CTL) Field Descriptions
Bit
Field
31-19
Reserved
18
VREFEN
17-16
Value
0
Internal DDR I/O Vref enable.
Connected to pad, external reference.
1
Reserved
VREFTAP
Selection for internal reference voltage level.
1h-3h
14
13
12-9
8
7
6
290
Reserved
0
0
15
Description
READY
Vref = 50.0% of VDDS
Reserved
VTP Ready status.
0
VTP is not ready.
1
VTP is ready.
IOPWRDN
Power down enable for DDR input buffer.
0
Disable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
1
Enable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
CLKRZ
0
VTP clear. Write 0 to clear VTP flops.
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
PWRSAVE
VTP power save mode. Turn off power to the external resistor when it is not needed. The
PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0.
0
Disable power save mode.
1
Enable power save mode.
LOCK
VTP impedance lock. Lock impedance value so that the VTP controller can be powered down.
0
Unlock impedance.
1
Lock impedance.
POWERDN
VTP power down. Power down the VTP controller. The PWRSAVE bit setting is only valid when
the POWERDN bit is cleared to 0.
0
Disable power down.
1
Enable power down.
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Table 11-51. VTP I/O Control Register (VTPIO_CTL) Field Descriptions (continued)
Bit
Field
5-3
D
Value
Drive strength control bit.
0-5h
2-0
Description
Reserved
6h
100% drive strength
7h
Reserved
F
Digital filter control bit.
0-6h
7h
Reserved
Digital filter is enabled.
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11.5.21 DDR Slew Register (DDR_SLEW)
The DDR slew register (DDR_SLEW) reflects the DDR I/O timing as programmed in the device eFuse.
The CMOSEN field configures the DDR I/O cells into an LVCMOS buffer (this makes it mDDR
compatible). The DDR_SLEW is shown in Figure 11-48 and described in Table 11-52.
Figure 11-48. DDR Slew Register (DDR_SLEW)
31
16
Reserved
R-0
15
12
7
11
10
9
8
Reserved
ODT_TERMON
ODT_TERMOFF
R-0
R/W-0
R/W-0
5
4
Reserved
6
DDR_PDENA
CMOSEN
3
DDR_DATASLEW
2
1
DDR_CMDSLEW
0
R-0
R/W-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-52. DDR Slew Register (DDR_SLEW) Field Descriptions
Bit
Field
31-12
Reserved
11-10
ODT_TERMON
Value
0
0
ODT_TERMOFF
5
4
3-2
Reserved
No termination
Reserved
0
Reserved
DDR_PDENA
Enables pull downs for mDDR mode (should be disabled for DDR2).
0
Pull downs are disabled. Disable pull downs when using DDR2.
1
Pull downs are enabled. Enable pull downs when using mDDR.
CMOSEN
Selects mDDR LVCMOS RX / SSTL18 differential RX.
0
SSTL Receiver. Select SSTL when using DDR2.
1
LVCMOS Receiver. Select LVCMOS when using mDDR.
DDR_DATASLEW
Slew rate mode control status for data macro. Slew rate control is not supported on this
device.
0
DDR_CMDSLEW
Slew rate control is off.
Reserved
Slew rate mode control status for command macro. Slew rate control is not supported on
this device.
0
1h-3h
292
Reserved
1h-3h
1h-3h
1-0
No termination
Controls Thevenin termination mode while I/O is not in read or write mode. Termination is
not supported on this device.
0
7-6
Reserved
Controls Thevenin termination mode while I/O is in read or write mode. Termination is not
supported on this device.
1h-3h
9-8
Description
Slew rate control is off.
Reserved
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11.5.22 Deep Sleep Register (DEEPSLEEP)
The deep sleep register (DEEPSLEEP) control the Deep Sleep logic. See your device-specific data
manual and the Boot Considerations chapter for details on boot and configuration settings. The
DEEPSLEEP is shown in Figure 11-49 and described in Table 11-53.
Figure 11-49. Deep Sleep Register (DEEPSLEEP)
31
30
SLEEPENABLE
SLEEPCOMPLETE
29
Reserved
16
R/W-0
R-0
R-0
15
0
SLEEPCOUNT
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-53. Deep Sleep Register (DEEPSLEEP) Field Descriptions
Bit
Field
31
SLEEPENABLE
30
Value
Deep sleep enable. The software must clear this bit to 0 when the device is awakened from
deep sleep.
0
Device is in normal operating mode; DEEPSLEEP pin has no effect.
1
Deep sleep mode is enabled; setting DEEPSLEEP pin low initiates oscillator shut down.
SLEEPCOMPLETE
29-16
Reserved
15-0
SLEEPCOUNT
Description
Deep sleep complete. Once the deep sleep process starts, the software must poll the
SLEEPCOMPLETE bit; when the SLEEPCOMPLETE bit is read as 1, the software should
clear the SLEEPENABLE bit and continue operation.
0
SLEEPCOUNT delay is not complete.
1
SLEEPCOUNT delay is complete.
0
Reserved
0-FFFFh
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16
bits are tied directly to the counter in the Deep Sleep logic.
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11.5.23 Pullup/Pulldown Enable Register (PUPD_ENA)
The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin
group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 11-50 and
described in Table 11-54.
Figure 11-50. Pullup/Pulldown Enable Register (PUPD_ENA)
31
0
PUPDENA[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-54. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions
Bit
31-0
Field
Value
PUPDENA[n]
Description
Enables internal pull-up or pull-down functionality for pin group CP[n]. See your devicespecific data manual for pin group information. The internal pull-up or pull-down functionality
selection for bit position n in PUPD_ENA is set in the same bit position n of the pullup/pulldown
select register (PUPD_SEL).
0
Internal pull-up or pull-down functionality for pin group n is disabled.
1
Internal pull-up or pull-down functionality for pin group n is enabled.
11.5.24 Pullup/Pulldown Select Register (PUPD_SEL)
The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for
the pin group n defined in your device-specific data manual. The PUPD_SEL is shown in Figure 11-51 and
described in Table 11-55 and Table 11-56.
NOTE: The PUPD_SEL settings are not active until the device is out of reset. During reset, all of the
CP[n] pins are pulled down. If the application requires a pull-up during reset, an external pullup should be used.
Figure 11-51. Pullup/Pulldown Select Register (PUPD_SEL)
31
0
PUPDSEL[n]
R/W-C3FF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-55. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions
Bit
31-0
294
Field
Value
PUPDSEL[n]
Description
Selects between the internal pull-up or pull-down functionality for pin group CP[n]. See your
device-specific data manual for pin group information. The selection for bit position n in PUPD_SEL
is only valid when the same bit position n is set in the pullup/pulldown enable register
(PUPD_ENA).
0
Internal pull-down functionality for pin group n is disabled.
1
Internal pull-up functionality for pin group n is enabled.
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Table 11-56. Pullup/Pulldown Select Register (PUPD_SEL) Default Values
Default
Value
Bit
Field
31
PUPDSEL[31]
1
Description
Pin Group CP[31] is configured for pull-up by default.
30
PUPDSEL[30]
1
Pin Group CP[30] is configured for pull-up by default.
29
PUPDSEL[29]
0
Pin Group CP[29] is configured for pull-down by default.
28
PUPDSEL[28]
0
Pin Group CP[28] is configured for pull-down by default.
27
PUPDSEL[27]
0
Pin Group CP[27] is configured for pull-down by default.
26
PUPDSEL[26]
0
Pin Group CP[26] is configured for pull-down by default.
25
PUPDSEL[25]
1
Pin Group CP[25] is configured for pull-up by default.
24
PUPDSEL[24]
1
Pin Group CP[24] is configured for pull-up by default.
23
PUPDSEL[23]
1
Pin Group CP[23] is configured for pull-up by default.
22
PUPDSEL[22]
1
Pin Group CP[22] is configured for pull-up by default.
21
PUPDSEL[21]
1
Pin Group CP[21] is configured for pull-up by default.
20
PUPDSEL[20]
1
Pin Group CP[20] is configured for pull-up by default.
19
PUPDSEL[19]
1
Pin Group CP[19] is configured for pull-up by default.
18
PUPDSEL[18]
1
Pin Group CP[18] is configured for pull-up by default.
17
PUPDSEL[17]
1
Pin Group CP[17] is configured for pull-up by default.
16
PUPDSEL[16]
1
Pin Group CP[16] is configured for pull-up by default.
15
PUPDSEL[15]
1
Pin Group CP[15] is configured for pull-up by default.
14
PUPDSEL[14]
1
Pin Group CP[14] is configured for pull-up by default.
13
PUPDSEL[13]
1
Pin Group CP[13] is configured for pull-up by default.
12
PUPDSEL[12]
1
Pin Group CP[12] is configured for pull-up by default.
11
PUPDSEL[11]
1
Pin Group CP[11] is configured for pull-up by default.
10
PUPDSEL[10]
1
Pin Group CP[10] is configured for pull-up by default.
9
PUPDSEL[9]
1
Pin Group CP[9] is configured for pull-up by default.
8
PUPDSEL[8]
1
Pin Group CP[8] is configured for pull-up by default.
7
PUPDSEL[7]
1
Pin Group CP[7] is configured for pull-up by default.
6
PUPDSEL[6]
1
Pin Group CP[6] is configured for pull-up by default.
5
PUPDSEL[5]
1
Pin Group CP[5] is configured for pull-up by default.
4
PUPDSEL[4]
1
Pin Group CP[4] is configured for pull-up by default.
3
PUPDSEL[3]
1
Pin Group CP[3] is configured for pull-up by default.
2
PUPDSEL[2]
1
Pin Group CP[2] is configured for pull-up by default.
1
PUPDSEL[1]
1
Pin Group CP[1] is configured for pull-up by default.
0
PUPDSEL[0]
1
Pin Group CP[0] is configured for pull-up by default.
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11.5.25 RXACTIVE Control Register (RXACTIVE)
The RXACTIVE control register (RXACTIVE) enables or disables the LVCMOS receivers for the pin group
n defined in your device-specific data manual. The RXACTIVE is shown in Figure 11-52 and described in
Table 11-57.
Figure 11-52. RXACTIVE Control Register (RXACTIVE)
31
0
RXACTIVE[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-57. RXACTIVE Control Register (RXACTIVE) Field Descriptions
Bit
31-0
Field
Value
RXACTIVE[n]
Description
Enables the LVCMOS receivers on pin group n. See your device-specific data manual for pin group
information. Receivers should only be disabled if the associated pin group is not being used.
0
LVCMOS receivers for pin group n are disabled.
1
LVCMOS receivers for pin group n are enabled.
11.5.26 Power Down Control Register (PWRDN)
The power down control register (PWRDN) enables or disables the SATA clock receiver. The PWRDN is
shown in Figure 11-53 and described in Table 11-58.
Figure 11-53. Power Down Control Register (PWRDN)
31
16
Reserved
R-FFFF FFFEh
15
1
0
Reserved
SATACLK_PWRDN
R-FFFF FFFEh
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-58. Power Down Control Register (PWRDN) Field Descriptions
Bit
31-1
0
296
Field
Reserved
Value
FFFF FFFEh
SATACLK_PWRDN
Description
Reserved
Enables SATA clock receiver. The SATA clock receiver should only be disabled if
the SATA is not being used.
0
Power down feature disabled (SATA clock input circuitry is enabled).
1
Power down feature enabled (SATA clock input circuitry is disabled).
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Chapter 12
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ARM Interrupt Controller (AINTC)
Topic
12.1
12.2
12.3
12.4
...........................................................................................................................
Introduction .....................................................................................................
Interrupt Mapping .............................................................................................
AINTC Methodology ..........................................................................................
AINTC Registers ...............................................................................................
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12.1 Introduction
The ARM interrupt controller (AINTC) is an interface between interrupts coming from different parts of the
system (these are referred to as system interrupts in this document), and the ARM9 interrupt interface.
ARM9 supports two types of interrupts: FIQ and IRQ (these are referred to as host interrupts in this
document). The AINTC has the following features:
• Supports up to 101 system interrupts.
• Supports up to 32 interrupt channels.
• Channels 0 and 1 are mapped (hard-wired) to the FIQ ARM interrupt and channels 2-31 are mapped to
IRQ ARM interrupt.
• Each system interrupt can be enabled and disabled.
• Each host interrupt can be enabled and disabled.
• Hardware prioritization of interrupts.
• Combining of interrupts from IPs to a single system interrupt.
• Supports two active low debug interrupts.
See the ARM926EJ Technical Reference Manual for information about the ARM's FIQ and IRQ interrupts.
12.2 Interrupt Mapping
The AINTC supports up to 101 system interrupts from different peripherals to be mapped to 32 channels
inside the AINTC (see Figure 12-1). Interrupts from these 32 channels are further mapped to either an
ARM FIQ interrupt or an ARM IRQ interrupt.
•
•
•
•
•
•
•
Any of the 101 system interrupts can be mapped to any of the 32 channels.
Multiple interrupts can be mapped to a single channel.
An interrupt should not be mapped to more than one channel.
Interrupts from channels 0 and 1 are mapped to FIQ ARM interrupt on host side.
Interrupts from channels 2 to 31 are mapped to IRQ ARM interrupt on host side.
For I < k, interrupts on channel-I have higher priority than interrupts on channel-k.
For interrupts on same channel, priority is determined by the hardware interrupt number. The lower the
interrupt number, the higher the priority.
Table 12-1 shows the system interrupt assignments for the AINTC.
Figure 12-1. AINTC Interrupt Mapping
Host Interrupt Mapping
of Channels
AINTC
ARM
Channel 0
Channel Mapping
of System Interrupts
Intr 0
Peripheral A
Intr 1
FIQ
Channel 1
Channel 2
Intr (n–1)
IRQ
Channel m
Peripheral Z
Intr n
n ≤ 100
m ≤ 31
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Table 12-1. AINTC System Interrupt Assignments
Event
Interrupt Name
Source
0
COMMTX
ARM
1
COMMRX
ARM
2
NINT
ARM
3
PRU_EVTOUT0
PRUSS Interrupt
4
PRU_EVTOUT1
PRUSS Interrupt
5
PRU_EVTOUT2
PRUSS Interrupt
6
PRU_EVTOUT3
PRUSS Interrupt
7
PRU_EVTOUT4
PRUSS Interrupt
8
PRU_EVTOUT5
PRUSS Interrupt
9
PRU_EVTOUT6
PRUSS Interrupt
10
PRU_EVTOUT7
PRUSS Interrupt
11
EDMA3_0_CC0_INT0
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
12
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrupt
13
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrupt
14
EMIFA_INT
EMIFA Interrupt
15
IIC0_INT
I2C0 interrupt
16
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
17
MMCSD0_INT1
MMCSD0 SDIO Interrupt
18
PSC0_ALLINT
PSC0 Interrupt
19
RTC_IRQS[1:0]
RTC Interrupt
20
SPI0_INT
SPI0 Interrupt
21
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
22
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
23
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
24
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
25
UART0_INT
UART0 Interrupt
26
—
Reserved
27
PROTERR
SYSCFG Protection Shared Interrupt
28
SYSCFG_CHIPINT0
SYSCFG CHIPSIG Register
29
SYSCFG_CHIPINT1
SYSCFG CHIPSIG Register
30
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
31
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
32
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrupt
33
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
34
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
35
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
36
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
37
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
38
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
39
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
40
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
41
DDR2_MEMERR
DDR2 Controller Interrupt
42
GPIO_B0INT
GPIO Bank 0 Interrupt
43
GPIO_B1INT
GPIO Bank 1 Interrupt
44
GPIO_B2INT
GPIO Bank 2 Interrupt
45
GPIO_B3INT
GPIO Bank 3 Interrupt
46
GPIO_B4INT
GPIO Bank 4 Interrupt
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Table 12-1. AINTC System Interrupt Assignments (continued)
Event
Interrupt Name
Source
47
GPIO_B5INT
GPIO Bank 5 Interrupt
48
GPIO_B6INT
GPIO Bank 6 Interrupt
49
GPIO_B7INT
GPIO Bank 7 Interrupt
50
GPIO_B8INT
GPIO Bank 8 Interrupt
51
IIC1_INT
I2C1 Interrupt
52
LCDC_INT
LCD Controller Interrupt
53
UART_INT1
UART1 Interrupt
54
MCASP_INT
McASP0 Combined RX/TX Interrupt
55
PSC1_ALLINT
PSC1 Interrupt
56
SPI1_INT
SPI1 Interrupt
57
UHPI_ARMINT
HPI ARM Interrupt
58
USB0_INT
USB0 (USB2.0) Interrupt
59
USB1_HCINT
USB1 (USB1.1) OHCI Host Controller Interrupt
60
USB1_R/WAKEUP
USB1 (USB1.1) Remote Wakeup Interrupt
61
UART2_INT
UART2 Interrupt
62
—
Reserved
63
EHRPWM0
HiResTimer / PWM0 Interrupt
64
EHRPWM0TZ
HiResTimer / PWM0 Trip Zone Interrupt
65
EHRPWM1
HiResTimer / PWM1 Interrupt
66
EHRPWM1TZ
HiResTimer / PWM1 Trip Zone Interrupt
67
SATA_INT
SATA Controller Interrupt
68
T64P2_ALL
Timer64P2 Combined Interrupt (TINT12 and TINT34)
69
ECAP0
eCAP0 Interrupt
70
ECAP1
eCAP1 Interrupt
71
ECAP2
eCAP2 Interrupt
72
MMCSD1_INT0
MMCSD1 MMC/SD Interrupt
73
MMCSD1_INT1
MMCSD1 SDIO Interrupt
74
T64P2_CMPINT0
Timer64P2 - Compare Interrupt 0
75
T64P2_CMPINT1
Timer64P2 - Compare Interrupt 1
76
T64P2_CMPINT2
Timer64P2 - Compare Interrupt 2
77
T64P2_CMPINT3
Timer64P2 - Compare Interrupt 3
78
T64P2_CMPINT4
Timer64P2 - Compare Interrupt 4
79
T64P2_CMPINT5
Timer64P2 - Compare Interrupt 5
80
T64P2_CMPINT6
Timer64P2 - Compare Interrupt 6
81
T64P2_CMPINT7
Timer64P2 - Compare Interrupt 7
82
T64P3_CMPINT0
Timer64P3 - Compare Interrupt 0
83
T64P3_CMPINT1
Timer64P3 - Compare Interrupt 1
84
T64P3_CMPINT2
Timer64P3 - Compare Interrupt 2
85
T64P3_CMPINT3
Timer64P3 - Compare Interrupt 3
86
T64P3_CMPINT4
Timer64P3 - Compare Interrupt 4
87
T64P3_CMPINT5
Timer64P3 - Compare Interrupt 5
88
T64P3_CMPINT6
Timer64P3 - Compare Interrupt 6
89
T64P3_CMPINT7
Timer64P3 - Compare Interrupt 7
90
ARMCLKSTOPREQ
PSC0 Interrupt
91
uPP_ALLINT
uPP Combined Interrupt
92
VPIF_ALLINT
VPIF Combined Interrupt
93
EDMA3_1_CC0_INT0
EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
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Table 12-1. AINTC System Interrupt Assignments (continued)
Event
Interrupt Name
Source
94
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrupt
95
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrupt
96
T64P3_ALL
Timer64P3 Combined Interrupt (TINT12 and TINT34)
97
MCBSP0_RINT
McBSP0 Receive Interrupt
98
MCBSP0_XINT
McBSP0 Transmit Interrupt
99
MCBSP1_RINT
McBSP1 Receive Interrupt
100
MCBSP1_XINT
McBSP1 Transmit Interrupt
12.3 AINTC Methodology
The AINTC module controls the system interrupt mapping to the host interrupt interface. System interrupts
are generated by the device peripherals. The AINTC receives the system interrupts and maps them to
internal channels. The channels are used to combine and prioritize system interrupts. These channels are
then mapped onto the host interface that is typically a smaller number of host interrupts or a vector input.
Interrupts from system side are active high in polarity. Also, they are pulse type of interrupts.
The AINTC encompasses many functions to process the system interrupts and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, vectorization, debug, and host interfacing. Figure 12-2 illustrates the flow of system interrupts
through the functions to the host. The following subsections describe each part of the flow.
Figure 12-2. Flow of System Interrupts to Host
Status
Enabling
Processing
System
Interrupts
Prioritization
Channel
Mapping
Vectorization
Host
Interfacing
Host Interrupts
Host Int
Mapping
12.3.1 Interrupt Processing
The interrupt processing block does the following tasks:
• Synchronization of slower and asynchronous interrupts
• Conversion of polarity to active high
• Conversion of interrupt type to pulse interrupts
After the processing block, all interrupts will be active-high pulses.
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12.3.2 Interrupt Enabling
The AINTC interrupt enable system allows individual interrupts to be enabled or disabled. Use the
following sequence to enable interrupts:
1. Enable global host interrupts. All host interrupts are enabled by setting the ENABLE bit in the global
enable register (GER). Individual host interrupts are enabled or disabled from their individual enables
and are not overridden by the global enable.
2. Enable host interrupt lines. Host interrupt lines (FIQ and IRQ) can be enabled through one of two
methods:
(a) Set the desired mapped bit(s) in the host interrupt enable register (HIER), or
(b) Write the host interrupt index (0-1) to the host interrupt enable indexed set register (HIEISR) for
every interrupt line to enable.
3. Enable system interrupts. System interrupts can be individually enabled through one of two methods:
(a) Set the desired mapped bit(s) in the system interrupt enable set registers (ESR1-ESR4), or
(b) Write the system interrupt index (0-100) to the system interrupt enable indexed set register (EISR)
for every system interrupt to enable.
12.3.3 Interrupt Status Checking
The next stage is to capture which system interrupts are pending. There are two kinds of pending status:
raw status and enabled status. Raw status is the pending status of the system interrupt without regards to
the enable bit for the system interrupt. Enabled status is the pending status of the system interrupts with
the enable bits active. When the enable bit is inactive, the enabled status will always be inactive.
The enabled status of system interrupts is captured in system interrupt status enabled/clear registers
(SECR1-SECR4). Status of system interrupt 'N' is indicated by the Nth bit of SECR1-SECR4. Since there
exists 101 system interrupts, four 32-bit registers are used to capture the enabled status of interrupts.
The pending status reflects whether the system interrupt occurred since the last time the status register bit
was cleared. Each bit in the status register is individually clearable.
12.3.4 Interrupt Channel Mapping
The AINTC has 32 internal channels to which enabled system interrupts can be mapped. Higher priority
interrupts should be mapped to channels 0 and 1. Other interrupts can be mapped to any of the channels
from 2 to 31. Channel 0 has highest priority and channel 31 has the lowest priority. Channels 0 and 1 are
connected to FIQ ARM interrupt. Channels 2 to 31 are connected to IRQ ARM interrupt. Channels are
used to group the system interrupts into a smaller number of priorities that can be given to a host interface
with a very small number of interrupt inputs. When multiple system interrupts are mapped to the same
channel their interrupts are ORed together so that when either is active the output is active.
The channel map registers (CMRm) define the channel for each system interrupt. There is one register
per 4 system interrupts; therefore, there are 26 channel map registers (CMR0-CMR25) for a system of
101 interrupts. Channel for each system interrupt can be set using these registers.
12.3.5 Host Interrupt Mapping Interrupts
The Host is ARM9, which has two lines: FIQ and IRQ. The 32 channels from the AINTC are mapped to
these two lines. The AINTC has a fixed host interrupt mapping scheme. Channels 0 and 1 are mapped to
FIQ and channels 2-31 are mapped to IRQ. Thus, system interrupts mapped to channels 0 and 1 are
propagated as FIQ to the host and system interrupts mapped to channels 2-31 are propagated as IRQ to
the host. When multiple channels are mapped to the same host interrupt, then prioritization is done to
select which interrupt is in the highest-priority channel and which should be sent first to the host.
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12.3.6 Interrupt Prioritization
The next stage of the AINTC is prioritization. Since multiple interrupts feed into a single channel and
multiple channels feed into a single host interrupt, it is necessary to prioritize between all the system
interrupts/channels to decide on a single system interrupt to handle. The AINTC provides hardware to
perform this prioritization with a given scheme so that software does not have to do this. There are two
levels of prioritizations:
1. The first level of prioritization is between the active channels for a host interrupt. Channel 0 has the
highest priority and channel 31 has the lowest. So the first level of prioritization picks the lowest
numbered active channel.
2. The second level of prioritization is between the active system interrupts for the prioritized channel.
The system interrupt in vector position 0 has the highest priority and system interrupt 100 has the
lowest priority. So the second level of prioritization picks the lowest vector position active system
interrupt.
The prioritized system interrupt for each host interrupt line (FIQ and IRQ) can be obtained from the host
interrupt prioritized index registers (HIPIR1 and HIPIR2). The host interrupt prioritized index register
values update dynamically as interrupts arrive at AINTC so care should be taken to avoid register race
conditions.
The AINTC features a prioritization hold mode that is intended to prevent race conditions while servicing
interrupts. This mode is enabled by setting the priority hold mode (PRHOLDMODE) bit in the control
register (CR). When enabled, a read of either the host interrupt prioritized index register (HIPIRn) or the
host interrupt prioritized vector register (HIPVRn) will freeze both the HIPIRn and HIPVRn values for the
respective host interrupt n. The values are frozen until one of the following actions is taken to release the
registers:
1. Write to the host interrupt prioritized index register (HIPIRn)
2. Write to the host interrupt prioritized vector register (HIPVRn)
3. Write-set bit n of the host interrupt enable register (HIER)
4. Write-set the active interrupt index to the host interrupt enable index set register (HIEISR)
5. Write-clear the active interrupt index to the host interrupt enable index clear register (HIEICR)
12.3.7 Interrupt Nesting
If interrupt service routines (ISRs) consume a large number of CPU cycles and may delay the servicing of
other interrupts, the AINTC can perform a nesting function in its prioritization. Nesting is a method of
disabling certain interrupts (usually lower-priority interrupts) when an interrupt is taken so that only those
desired interrupts can trigger to the host while it is servicing the current interrupt. The typical usage is to
nest on the current interrupt and disable all interrupts of the same or lower priority (or channel). Then the
host will only be interrupted from a higher priority interrupt.
Nesting is available in 1 of 3 methods selectable by the NESTMODE bit in the control register (CR):
1. Nesting for all host interrupts, based on channel priority: When an interrupt is taken, the nesting level is
set to its channel priority. From then, that channel priority and all lower priority channels will be
disabled from generating host interrupts and only higher priority channels are allowed. When the
interrupt is completely serviced, the nesting level is returned to its original value. When there is no
interrupt being serviced, there are no channels disabled due to nesting. The global nesting level
register (GNLR) allows the checking and setting of the global nesting level across all host interrupts.
The nesting level is the channel (and all of lower priority channels) that are nested out because of a
current interrupt.
2. Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority
for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting
level is set to its channel priority for just that host interrupt, and other host interrupts do not have their
nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host
but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting
level for the host interrupt is returned to its original value. The host interrupt nesting level registers
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level
controls which channel and lower priority channels are nested. There is one register per host interrupt.
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3. Software manually performs the nesting of interrupts. When an interrupt is taken, the software will
disable all the host interrupts, manually update the enables for any or all the system interrupts, and
then re-enable all the host interrupts. This now allows only the system interrupts that are still enabled
to trigger to the host. When the interrupt is completely serviced the software must reverse the changes
to re-enable the nested out system interrupts. This method requires the most software interaction but
gives the most flexibility if simple channel based nesting mechanisms are not adequate.
The recommended approach is the automatic host interrupt nesting method (second method). Because
higher priority interrupts can preempt lower priority interrupts in this method, a software stack is used to
keep track of nest priorities. The base stack value should be initialized to the default nest priority of the
application. Take the following steps within the ARM hardware interrupt service routine to handle interrupts
using host interrupt priority nesting:
1. Disable the ARM hardware interrupt.
2. Clear the OVERRIDE bit in the host interrupt nesting level register n (HINLRn) to expose the priority
level of the active interrupt.
3. Push the active (or desired) interrupt priority value into the nest priority stack.
4. Write the active (or desired) priority level into HINLRn by setting the OVERRIDE bit.
5. Calculate and store the ISR address for the active interrupt. Unfreeze the host interrupt prioritized
index register n (HIPIRn) and the host interrupt prioritized vector register n (HIPVRn), if the
PRHOLDMODE bit in the control register (CR) is set.
6. Clear the system interrupt status by setting the appropriate bit in the system interrupt status
enabled/clear register n (SECRn) or by writing the appropriate index to the system interrupt status
indexed clear register (SICR).
7. Acknowledge and enable the ARM hardware interrupt.
8. Execute the ISR at the address stored from step 5. During this step, interrupts enabled by the new
nest priority level will be able to preempt the ISR.
9. Disable the ARM hardware interrupt.
10. Discard the most recent priority level in the nest priority stack and restore the previous priority level to
HINLRn by setting the OVERRIDE bit.
11. Enable the ARM hardware interrupt.
12.3.8 Interrupt Vectorization
The next stage of the AINTC is vectorization. Vectorization is an advanced feature that allows the host to
receive an interrupt service routine (ISR) address in addition to just the interrupt status. Without
vectorization the host would receive the interrupt and enter a general ISR that gets the prioritized system
interrupt to service from the AINTC, looks up the specific ISR address for that system interrupt, and then
jumps to that address. With vectorization the host can read a register that has the ISR address already
calculated and jump to that address immediately.
Vectorization uses a base and universal size where all the ISR code is placed in a contiguous memory
region with each ISR code a standard size. For this calculation, the vector base register (VBR) is
programmed by software to hold the base address of all the ISR code and the vector size register (VSR)
is programmed for the size in words between ISR code for each system interrupt. The index number of
each system interrupt is used to calculate the final offset. The specific system interrupt ISR address is
then calculated as:
ISR address = base + (index × size)
There is also a special case when there is no interrupt pending and then the ISR address is the ISR Null
address. This is in case the vector address is executed when there is no pending interrupt so that a Null
handler can be in place to just return from the interrupt. The vector null address register (VNR) holds the
address of the ISR null address. When there is a pending interrupt then the ISR address is calculated as
exact base + offset for that interrupt number.
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12.3.9 Interrupt Status Clearing
After servicing the interrupt (after execution of the ISR), interrupt status is to be cleared. If a system
interrupt status is not cleared, then another host interrupt may not be triggered or another host interrupt
may be triggered incorrectly. For clearing the status of an interrupt, whose interrupt number is N, write a 1
to the Nth bit position in the system interrupt status enabled/clear registers (SECR1-SECR4). System
interrupt N can also be cleared by writing the value N into the system interrupt status indexed clear
register (SICR).
12.3.10 Interrupt Disabling
At any time, if any interrupt is not to be propagated to the host, then that interrupt should be disabled. For
disabling an interrupt whose interrupt number is N, write a 1 to the Nth bit in the system interrupt enable
clear registers (ECR1-ECR4). System interrupt N can also be disabled by writing the value N in the
system interrupt enable indexed clear register (EICR).
12.4 AINTC Registers
Table 12-2 lists the memory-mapped registers for the AINTC.
Table 12-2. ARM Interrupt Controller (AINTC) Registers
Address
Acronym
Register Description
FFFE E000h
REVID
Revision Identification Register
Section 12.4.1
FFFE E004h
CR
Control Register
Section 12.4.2
FFFE E010h
GER
Global Enable Register
Section 12.4.3
FFFE E01Ch
GNLR
Global Nesting Level Register
Section 12.4.4
FFFE E020h
SISR
System Interrupt Status Indexed Set Register
Section 12.4.5
FFFE E024h
SICR
System Interrupt Status Indexed Clear Register
Section 12.4.6
FFFE E028h
EISR
System Interrupt Enable Indexed Set Register
Section 12.4.7
FFFE E02Ch
EICR
System Interrupt Enable Indexed Clear Register
Section 12.4.8
FFFE E034h
HIEISR
Host Interrupt Enable Indexed Set Register
Section 12.4.9
FFFE E038h
HIEICR
Host Interrupt Enable Indexed Clear Register
Section 12.4.10
FFFE E050h
VBR
Vector Base Register
Section 12.4.11
FFFE E054h
VSR
Vector Size Register
Section 12.4.12
FFFE E058h
VNR
Vector Null Register
Section 12.4.13
FFFE E080h
GPIR
Global Prioritized Index Register
Section 12.4.14
FFFE E084h
GPVR
Global Prioritized Vector Register
Section 12.4.15
FFFE E200h
SRSR1
System Interrupt Status Raw/Set Register 1
Section 12.4.16
FFFE E204h
SRSR2
System Interrupt Status Raw/Set Register 2
Section 12.4.17
FFFE E208h
SRSR3
System Interrupt Status Raw/Set Register 3
Section 12.4.18
FFFE E20Ch
SRSR4
System Interrupt Status Raw/Set Register 4
Section 12.4.19
FFFE E280h
SECR1
System Interrupt Status Enabled/Clear Register 1
Section 12.4.20
FFFE E284h
SECR2
System Interrupt Status Enabled/Clear Register 2
Section 12.4.21
FFFE E288h
SECR3
System Interrupt Status Enabled/Clear Register 3
Section 12.4.22
FFFE E28Ch
SECR4
System Interrupt Status Enabled/Clear Register 4
Section 12.4.23
FFFE E300h
ESR1
System Interrupt Enable Set Register 1
Section 12.4.24
FFFE E304h
ESR2
System Interrupt Enable Set Register 2
Section 12.4.25
FFFE E308h
ESR3
System Interrupt Enable Set Register 3
Section 12.4.26
FFFE E30Ch
ESR4
System Interrupt Enable Set Register 4
Section 12.4.27
FFFE E380h
ECR1
System Interrupt Enable Clear Register 1
Section 12.4.28
FFFE E384h
ECR2
System Interrupt Enable Clear Register 2
Section 12.4.29
FFFE E388h
ECR3
System Interrupt Enable Clear Register 3
Section 12.4.30
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Table 12-2. ARM Interrupt Controller (AINTC) Registers (continued)
Address
Acronym
Register Description
FFFE E38Ch
ECR4
System Interrupt Enable Clear Register 4
Section 12.4.31
Section
FFFE E400h–
FFFE E464h
CMR0-CMR25
Channel Map Registers 0-25
Section 12.4.32
FFFE E900h
HIPIR1
Host Interrupt Prioritized Index Register 1
Section 12.4.33
FFFE E904h
HIPIR2
Host Interrupt Prioritized Index Register 2
Section 12.4.34
FFFE F100h
HINLR1
Host Interrupt Nesting Level Register 1
Section 12.4.35
FFFE F104h
HINLR2
Host Interrupt Nesting Level Register 2
Section 12.4.36
FFFE F500h
HIER
Host Interrupt Enable Register
Section 12.4.37
FFFE F600h
HIPVR1
Host Interrupt Prioritized Vector Register 1
Section 12.4.38
FFFE F604h
HIPVR2
Host Interrupt Prioritized Vector Register 2
Section 12.4.39
12.4.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 25-35 and described in Table 12-3.
Figure 12-3. Revision Identification Register (REVID)
31
0
REV
R-4E82 A900h
LEGEND: R = Read only; -n = value after reset
Table 12-3. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E82 A900h
306
Description
Revision ID of the AINTC.
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12.4.2 Control Register (CR)
The control register (CR) holds global control parameters. The CR is shown in Figure 12-4 and described
in Table 12-4.
Figure 12-4. Control Register (CR)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PRHOLDMODE
NESTMODE
Reserved
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-4. Control Register (CR) Field Descriptions
Bit
31-5
4
3-2
1-0
Field
Reserved
Value
0
PRHOLDMODE
NESTMODE
Reserved
Description
Reserved
Enables priority holding mode.
0
No priority holding. Prioritized MMRs will continually update.
1
Priority holding enabled. Prioritized Index and Vector Address MMRs will hold their value after the
first is read. See Section 12.3.6 for details.
0-3h
Nesting mode.
0
No nesting
1h
Automatic individual nesting (per host interrupt)
2h
Automatic global nesting (over all host interrupts)
3h
Manual nesting
0
Reserved
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12.4.3 Global Enable Register (GER)
The global enable register (GER) enables all the host interrupts. Individual host interrupts are still enabled
or disabled from their individual enables and are not overridden by the global enable. The GER is shown
in Figure 12-5 and described in Table 12-5.
Figure 12-5. Global Enable Register (GER)
31
16
Reserved
R-0
15
1
0
Reserved
ENABLE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-5. Global Enable Register (GER) Field Descriptions
Bit
Field
Value
31-1
Reserved
0
0
ENABLE
0-1
Description
Reserved
The current global enable value when read. Writes set the global enable.
12.4.4 Global Nesting Level Register (GNLR)
The global nesting level register (GNLR) allows the checking and setting of the global nesting level across
all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of
lower priority) that are nested out because of a current interrupt. The GNLR is shown in Figure 12-6 and
described in Table 12-6.
Figure 12-6. Global Nesting Level Register (GNLR)
31
30
16
OVERRIDE
Reserved
R/W-0
R-0
15
9
8
0
Reserved
NESTLVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-6. Global Nesting Level Register (GNLR) Field Descriptions
Bit
Field
31
OVERRIDE
Value
0-1
30-9
Reserved
0
8-0
NESTLVL
0-1FFh
308
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Description
Always read as 0. Writes of 1 override the automatic nesting and set the NESTLVL to the written
data.
Reserved
The current global nesting level (highest channel that is nested). Writes set the nesting level. In
autonesting mode this value is updated internally, unless the auto_override bit is set.
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12.4.5 System Interrupt Status Indexed Set Register (SISR)
The system interrupt status indexed set register (SISR) allows setting the status of an interrupt. The
interrupt to set is the INDEX value written. This sets the Raw Status Register bit of the given INDEX. The
SISR is shown in Figure 12-7 and described in Table 12-7.
Figure 12-7. System Interrupt Status Indexed Set Register (SISR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-7. System Interrupt Status Indexed Set Register (SISR) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
INDEX
Description
0
Reserved
0-7Fh
Writes set the status of the interrupt given in the INDEX value. Reads return 0.
12.4.6 System Interrupt Status Indexed Clear Register (SICR)
The system interrupt status indexed clear register (SICR) allows clearing the status of an interrupt. The
interrupt to clear is the INDEX value written. This clears the Raw Status Register bit of the given INDEX.
The SICR is shown in Figure 12-8 and described in Table 12-8.
Figure 12-8. System Interrupt Status Indexed Clear Register (SICR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-8. System Interrupt Status Indexed Clear Register (SICR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INDEX
Value
0
0-7Fh
Description
Reserved
Writes clear the status of the interrupt given in the INDEX value. Reads return 0.
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12.4.7 System Interrupt Enable Indexed Set Register (EISR)
The system interrupt enable indexed set register (EISR) allows enabling an interrupt. The interrupt to
enable is the INDEX value written. This sets the Enable Register bit of the given INDEX. The EISR is
shown in Figure 12-9 and described in Table 12-9.
Figure 12-9. System Interrupt Enable Indexed Set Register (EISR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-9. System Interrupt Enable Indexed Set Register (EISR) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
INDEX
Description
0
Reserved
0-7Fh
Writes set the enable of the interrupt given in the INDEX value. Reads return 0.
12.4.8 System Interrupt Enable Indexed Clear Register (EICR)
The system interrupt enable indexed clear register (EICR) allows disabling an interrupt. The interrupt to
disable is the INDEX value written. This clears the Enable Register bit of the given INDEX. The EICR is
shown in Figure 12-10 and described in Table 12-10.
Figure 12-10. System Interrupt Enable Indexed Clear Register (EICR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INDEX
310
Value
0
0-7Fh
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Description
Reserved
Writes clear the enable of the interrupt given in the INDEX value. Reads return 0.
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12.4.9 Host Interrupt Enable Indexed Set Register (HIEISR)
The host interrupt enable indexed set register (HIEISR) allows enabling a host interrupt output. The host
interrupt to enable is the INDEX value written. This enables the host interrupt output or triggers the output
again if already enabled. The HEISR is shown in Figure 12-11 and described in Table 12-11.
Figure 12-11. Host Interrupt Enable Indexed Set Register (HEISR)
31
16
Reserved
R-0
15
1
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
INDEX
Description
Reserved
Writes set the enable of the host interrupt given in the INDEX value. Reads return 0.
0
Writing a 0 sets FIQ.
1
Writing a 1 sets IRQ.
12.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR)
The host interrupt enable indexed clear register (HIEICR) allows disabling a host interrupt output. The host
interrupt to disable is the INDEX value written. This disables the host interrupt output. The HIEICR is
shown in Figure 12-12 and described in Table 12-12.
Figure 12-12. Host Interrupt Enable Indexed Clear Register (HIEICR)
31
16
Reserved
R-0
15
1
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-12. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
INDEX
Description
Reserved
Writes clear the enable of the host interrupt given in the INDEX value. Reads return 0.
0
Writing a 0 clears FIQ.
1
Writing a 1 clears IRQ.
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12.4.11 Vector Base Register (VBR)
The vector base register (VBR) holds the base address of the ISR vector addresses. The VBR is shown in
Figure 12-13 and described in Table 12-13.
Figure 12-13. Vector Base Register (VBR)
31
0
BASE
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-13. Vector Base Register (VBR) Field Descriptions
Bit
Field
Value
Description
31-0
BASE
0-FFFF FFFFh
ISR Base Address.
12.4.12 Vector Size Register (VSR)
The vector size register (VSR) holds the sizes of the individual ISR routines in the vector table. This is
only the sizes to space the calculated vector addresses for the initial ISR targets (the ISR targets could
branch off to the full ISR routines). The VSR is shown in Figure 12-14 and described in Table 12-14.
NOTE: The VSR must be configured even if the desired value is equal to the default value.
Figure 12-14. Vector Size Register (VSR)
31
16
Reserved
R-0
15
8
7
0
Reserved
SIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-14. Vector Size Register (VSR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
SIZE
Value
0
0-FFh
Description
Reserved
Size of ISR address spaces.
0
4 bytes
1h
8 bytes
2h
16 bytes
3h
32 bytes
4h
64 bytes
5h-FFh ...
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12.4.13 Vector Null Register (VNR)
The vector null register (VNR) holds the address of the ISR null address that handles no pending
interrupts (if accidentally branched to when no interrupts are pending). The VNR is shown in Figure 12-15
and described in Table 12-15.
Figure 12-15. Vector Null Register (VNR)
31
0
NULL
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-15. Vector Null Register (VNR) Field Descriptions
Bit
Field
Value
31-0
NULL
0-FFFF FFFFh
Description
ISR Null Address.
12.4.14 Global Prioritized Index Register (GPIR)
The global prioritized index register (GPIR) shows the interrupt number of the highest priority interrupt
pending across all the host interrupts. The GPIR is shown in Figure 12-16 and described in Table 12-16.
Figure 12-16. Global Prioritized Index Register (GPIR)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-16. Global Prioritized Index Register (GPIR) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are
pending.
Reserved
The currently highest priority interrupt index pending across all the host interrupts.
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12.4.15 Global Prioritized Vector Register (GPVR)
The global prioritized vector register (GPVR) shows the interrupt vector address of the highest priority
interrupt pending across all the host interrupts. The GPVR is shown in Figure 12-17 and described in
Table 12-17.
Figure 12-17. Global Prioritized Vector Register (GPVR)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-17. Global Prioritized Vector Register (GPVR) Field Descriptions
Bit
Field
Value
Description
31-0
ADDR
0-FFFF FFFFh
The currently highest priority interrupts vector address across all the host interrupts.
12.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1)
The system interrupt status raw/set register 1 (SRSR1) shows the pending enabled status of the system
interrupts 0 to 31. Software can write to SRSR1 to set a system interrupt without a hardware trigger. There
is one bit per system interrupt. The SRSR1 is shown in Figure 12-18 and described in Table 12-18.
Figure 12-18. System Interrupt Status Raw/Set Register 1 (SRSR1)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-18. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions
Bit
31-0
314
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n.
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12.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2)
The system interrupt status raw/set register 2 (SRSR2) shows the pending enabled status of the system
interrupts 32 to 63. Software can write to SRSR2 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR2 is shown in Figure 12-19 and described in Table 12-19.
Figure 12-19. System Interrupt Status Raw/Set Register 2 (SRSR2)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-19. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions
Bit
31-0
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 32.
12.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3)
The system interrupt status raw/set register 3 (SRSR3) shows the pending enabled status of the system
interrupts 64 to 95. Software can write to SRSR3 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR3 is shown in Figure 12-20 and described in Table 12-20.
Figure 12-20. System Interrupt Status Raw/Set Register 3 (SRSR3)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-20. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions
Bit
31-0
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 64 to 95. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 64.
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12.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4)
The system interrupt status raw/set register 4 (SRSR4) shows the pending enabled status of the system
interrupts 96 to 100. Software can write to SRSR4 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR4 is shown in Figure 12-21 and described in Table 12-21.
Figure 12-21. System Interrupt Status Raw/Set Register 4 (SRSR4)
31
5
4
0
Reserved
RAW_STATUS[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
RAW_STATUS[n]
Description
0
Reserved
System interrupt raw status and setting of the system interrupts 96 to 100. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 96.
12.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1)
The system interrupt status enabled/clear register 1 (SECR1) shows the pending enabled status of the
system interrupts 0 to 31. Software can write to SECR1 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR1 is
shown in Figure 12-22 and described in Table 12-22.
Figure 12-22. System Interrupt Status Enabled/Clear Register 1 (SECR1)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions
Bit
31-0
316
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n.
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12.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2)
The system interrupt status enabled/clear register 2 (SECR2) shows the pending enabled status of the
system interrupts 32 to 63. Software can write to SECR2 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR2 is
shown in Figure 12-23 and described in Table 12-23.
Figure 12-23. System Interrupt Status Enabled/Clear Register 2 (SECR2)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions
Bit
31-0
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 32.
12.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3)
The system interrupt status enabled/clear register 3 (SECR3) shows the pending enabled status of the
system interrupts 64 to 95. Software can write to SECR3 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR3 is
shown in Figure 12-24 and described in Table 12-24.
Figure 12-24. System Interrupt Status Enabled/Clear Register 3 (SECR3)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions
Bit
31-0
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 64 to 95. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 64.
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12.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4)
The system interrupt status enabled/clear register 4 (SECR4) shows the pending enabled status of the
system interrupts 96 to 100. Software can write to SECR4 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR4 is
shown in Figure 12-25 and described in Table 12-25.
Figure 12-25. System Interrupt Status Enabled/Clear Register 4 (SECR4)
31
5
4
0
Reserved
ENBL_STATUS[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
0
4-0
ENBL_STATUS[n]
Description
Reserved
System interrupt enabled status and clearing of the system interrupts 96 to 100. Reads return
the enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 96.
12.4.24 System Interrupt Enable Set Register 1 (ESR1)
The system interrupt enable set register 1 (ESR1) enables system interrupts 0 to 31 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR1 is shown in Figure 12-26 and described in Table 12-26.
Figure 12-26. System Interrupt Enable Set Register 1 (ESR1)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-26. System Interrupt Enable Set Register 1 (ESR1) Field Descriptions
Bit
31-0
318
Field
Value
ENABLE[n]
Description
System interrupt 0 to 31 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n.
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12.4.25 System Interrupt Enable Set Register 2 (ESR2)
The system interrupt enable set register 2 (ESR2) enables system interrupts 32 to 63 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR2 is shown in Figure 12-27 and described in Table 12-27.
Figure 12-27. System Interrupt Enable Set Register 2 (ESR2)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-27. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions
Bit
31-0
Field
Value
ENABLE[n]
Description
System interrupt 32 to 63 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 32.
12.4.26 System Interrupt Enable Set Register 3 (ESR3)
The system interrupt enable set register 3 (ESR3) enables system interrupts 64 to 95 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR3 is shown in Figure 12-28 and described in Table 12-28.
Figure 12-28. System Interrupt Enable Set Register 3 (ESR3)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-28. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions
Bit
31-0
Field
Value
ENABLE[n]
Description
System interrupt 64 to 95 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 64.
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12.4.27 System Interrupt Enable Set Register 4 (ESR4)
The system interrupt enable set register 4 (ESR4) enables system interrupts 96 to 100 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR4 is shown in Figure 12-29 and described in Table 12-29.
Figure 12-29. System Interrupt Enable Set Register 4 (ESR4)
31
5
4
0
Reserved
ENABLE[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-29. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
ENABLE[n]
0
Description
Reserved
System interrupt 96 to 100 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 96.
12.4.28 System Interrupt Enable Clear Register 1 (ECR1)
The system interrupt enable clear register 1 (ECR1) disables system interrupts 0 to 31 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR1 is shown in Figure 12-30 and described in Table 12-30.
Figure 12-30. System Interrupt Enable Clear Register 1 (ECR1)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-30. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions
Bit
31-0
320
Field
Value
DISABLE[n]
Description
System interrupt 0 to 31 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n.
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12.4.29 System Interrupt Enable Clear Register 2 (ECR2)
The system interrupt enable clear register 2 (ECR2) disables system interrupts 32 to 63 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR2 is shown in Figure 12-31 and described in Table 12-31.
Figure 12-31. System Interrupt Enable Clear Register 2 (ECR2)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-31. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions
Bit
31-0
Field
Value
DISABLE[n]
Description
System interrupt 32 to 63 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 32.
12.4.30 System Interrupt Enable Clear Register 3 (ECR3)
The system interrupt enable clear register 3 (ECR3) disables system interrupts 64 to 95 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR3 is shown in Figure 12-32 and described in Table 12-32.
Figure 12-32. System Interrupt Enable Clear Register 3 (ECR3)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-32. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions
Bit
27-0
Field
Value
DISABLE[n]
Description
System interrupt 64 to 95 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 64.
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12.4.31 System Interrupt Enable Clear Register 4 (ECR4)
The system interrupt enable clear register 4 (ECR4) disables system interrupts 96 to 100 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR4 is shown in Figure 12-33 and described in Table 12-33.
Figure 12-33. System Interrupt Enable Clear Register 4 (ECR4)
31
5
4
0
Reserved
DISABLE[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-33. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions
Bit
Field
31-5
Reserved
4-0
DISABLE[n]
Value
0
Description
Reserved
System interrupt 96 to 100 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 96.
12.4.32 Channel Map Registers (CMR0-CMR25)
The channel map registers (CMR0-CMR25) define the channel for each system interrupt. There is one
register per 4 system interrupts. The CMRn is shown in Figure 12-34 and described in Table 12-34.
Figure 12-34. Channel Map Registers (CMRn)
31
24
23
16
CHNL_NPLUS3
CHNL_NPLUS2
R/W-0
R/W-0
15
8
7
0
CHNL_NPLUS1
CHNL_N
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-34. Channel Map Registers (CMRn) Field Descriptions
Bit
Field
Value
Description
31-24
CHNL_NPLUS3
0-FFh
Sets the host interrupt for channel N + 3.
23-16
CHNL_NPLUS2
0-FFh
Sets the host interrupt for channel N + 2.
15-8
CHNL_NPLUS1
0-FFh
Sets the host interrupt for channel N + 1.
7-0
CHNL_N
0-FFh
Sets the channel for the system interrupt N. (N ranges from 0 to 100).
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12.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1)
The host interrupt prioritized index register 1 (HIPIR1) shows the highest priority current pending interrupt
for the FIQ interrupt. The HIPIR1 is shown in Figure 12-35 and described in Table 12-35.
Figure 12-35. Host Interrupt Prioritized Index Register 1 (HIPIR1)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending.
Reserved
Interrupt number of the highest priority pending interrupt for FIQ host interrupt.
12.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2)
The host interrupt prioritized index register 2 (HIPIR2) shows the highest priority current pending interrupt
for the IRQ interrupt. The HIPIR2 is shown in Figure 12-36 and described in Table 12-36.
Figure 12-36. Host Interrupt Prioritized Index Register 2 (HIPIR2)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending.
Reserved
Interrupt number of the highest priority pending interrupt for IRQ host interrupt.
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12.4.35 Host Interrupt Nesting Level Register 1 (HINLR1)
The host interrupt nesting level register 1 (HINLR1) displays and controls the nesting level for FIQ host
interrupt. The nesting level controls which channel and lower priority channels are nested. The HINLR1 is
shown in Figure 12-37 and described in Table 12-37.
Figure 12-37. Host Interrupt Nesting Level Register 1 (HINLR1)
31
30
16
OVERRIDE
Reserved
W-0
R-0
15
9
8
0
Reserved
NEST_LVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 12-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions
Bit
Field
31
OVERRIDE
Value
30-9
Reserved
8-0
NEST_LVL
0-1
0
0-1FFh
Description
Reads return 0. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.
Reserved
Reads return the current nesting level for the FIQ host interrupt. Writes set the nesting level for the
FIQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and
then the write data is used.
12.4.36 Host Interrupt Nesting Level Register 2 (HINLR2)
The host interrupt nesting level register 2 (HINLR2) displays and controls the nesting level for IRQ host
interrupt. The nesting level controls which channel and lower priority channels are nested. The HINLR2 is
shown in Figure 12-38 and described in Table 12-38.
Figure 12-38. Host Interrupt Nesting Level Register 2 (HINLR2)
31
30
16
OVERRIDE
Reserved
W-0
R-0
15
9
8
0
Reserved
NEST_LVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 12-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions
Bit
Field
31
OVERRIDE
30-9
Reserved
8-0
NEST_LVL
324
Value
0-1
0
0-1FFh
ARM Interrupt Controller (AINTC)
Description
Reads return 0. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.
Reserved
Reads return the current nesting level for the IRQ host interrupt. Writes set the nesting level for the
IRQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and
then the write data is used.
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12.4.37 Host Interrupt Enable Register (HIER)
The host interrupt enable register (HIER) enables or disables individual host interrupts (FIQ and IRQ).
These work separately from the global enables. There is one bit per host interrupt. These bits are updated
when writing to the host interrupt enable indexed set register (HIEISR) and the host interrupt disable
indexed clear register (HIDISR). The HIER is shown in Figure 12-39 and described in Table 12-39.
Figure 12-39. Host Interrupt Enable Register (HIER)
31
16
Reserved
R-0
15
1
0
Reserved
2
IRQ
FIQ
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-39. Host Interrupt Enable Register (HIER) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
IRQ
Description
Reserved
Enable of IRQ
0
IRQ is disabled.
1
IRQ is enabled.
FIQ
Enable of FIQ
0
FIQ is disabled.
1
FIQ is enabled.
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12.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1)
The host interrupt prioritized vector register 1 (HIPVR1) shows the interrupt vector address of the highest
priority interrupt pending for FIQ host interrupt. The HIPVR1 is shown in Figure 12-40 and described in
Table 12-40.
Figure 12-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions
Bit
Field
Value
31-0
ADDR
0-FFFF FFFFh
Description
The currently highest priority interrupt vector address across for the FIQ host interrupt.
12.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2)
The host interrupt prioritized vector register 2 (HIPVR2) shows the interrupt vector address of the highest
priority interrupt pending for IRQ host interrupt. The HIPVR2 is shown in Figure 12-41 and described in
Table 12-41.
Figure 12-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions
Bit
Field
Value
31-0
ADDR
0-FFFF FFFFh
326
Description
The currently highest priority interrupt vector address across for the IRQ host interrupt.
ARM Interrupt Controller (AINTC)
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Chapter 13
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Boot Considerations
Topic
13.1
13.2
...........................................................................................................................
Page
Introduction ..................................................................................................... 328
DSP Wake Up ................................................................................................... 329
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13.1 Introduction
This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ARM ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• HPI boot
• I2C0/I2C1 boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI0/SPI1 boot
– Serial Flash (Master Mode)
– Serial EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0/1/2 boot
– External Host
• MMC/SD0 boot
See Using the OMAP-L132/L138 Bootloader Application Report (SPRAB41) for more details on the ROM
Boot Loader, a list of boot pins used, and the complete list of supported boot modes.
328
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13.2 DSP Wake Up
Following deassertion of device reset, the DSP intializes the ARM296 so that it can execute the ARM
ROM bootloader. Upon successful wake up, the ARM places the DSP in a reset and clock gated
(SwRstDisable) state that is controlled by the LPSC and the SYSCFG modules.
Perform the following steps to wake up the DSP:
1. Write a 83E7 0B13h to the KICK0R register in the SYSCFG module.
2. Write a 95A4 F1E0h to the KICK1R register in the SYSCFG module.
3. Write the truncated DSP boot address vector to the DSP_ISTP_RST_VAL field in the host 1
configuration register (HOST1CFG) of the SYSCFG module. The least-significant bits of the boot
address are fixed at 0.
4. Write a 3h to the NEXT bit in the DSP local power sleep controller (LPSC) module control register
(PSC0.MDCTL15) to prepare the DSP module for an enable transition (to enable the clocks and all
transitioning from the SwRstDisable state to Enable state).
5. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP module.
6. Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) for
power transition sequence completion. The domain is only safely in the new state after the GOSTAT[1]
bit is cleared to 0.
7. Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
8. Write a 1 to the LRST bit in PSC0.MDCTL15 to release the DSP local reset controlled by the PSC
module.
NOTE: Step 8 can also be combined with Step 4. You can write a 103h to the PSC0.MDCTL15 in
Step 4 to release the DSP local reset and transition it from a SwRstDisable to Enable state.
The steps to release the DSP reset by the SYSCFG module (Steps 1-3) are only required at
device reset/system reset/warm reset. Disabling/enabling clocks to the DSP module at any
other time can be independently controlled by the PSC module alone. Guidelines to
enable/disable clocks for power management are provided in the Power Management
chapter.
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Chapter 14
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Programmable Real-Time Unit Subsystem (PRUSS)
Topic
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
330
...........................................................................................................................
Overview .........................................................................................................
Description ......................................................................................................
Constants Table ...............................................................................................
PRU Module Interface .......................................................................................
Instruction Set..................................................................................................
Instruction Formats ..........................................................................................
PRU Interrupt Controller ....................................................................................
Registers .........................................................................................................
Programmable Real-Time Unit Subsystem (PRUSS)
Page
331
333
334
335
336
339
357
364
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Overview
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The Programmable Real-Time Unit Subsystem (PRUSS) consists of:
• Two programmable real-time units (PRU0 and PRU1) and their associated memories.
• An interrupt controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The two PRUs
can also work in coordination with the device level host CPU. This is determined by the nature of the
program that is loaded into the two PRUs instruction memory. Several different signaling mechanisms are
available between the two PRUs and the device level host CPU.
The two PRUs are optimized for performing embedded tasks that require manipulation of packed memorymapped data structures, handling of system events that have tight real-time constraints and interfacing
with systems external to the device.
14.1 Overview
The PRU is a optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the DSP/SoC. The PRU is both very small and very efficient at handling such tasks.
The major attributes of the PRU are as follows:
Attribute
Value
IO Architecture
Load / Store
Data Flow Architecture
Register to Register
Core Level Bus Architecture
Type
4-Bus Harvard (1 Instruction, 3 Data)
Instruction I/F
32-Bit
Memory I/F 0
32-Bit
Memory I/F 1
32-Bit
Issue Type
Scalar
Pipelining
None
Ordering
In-order
ALU Type
Unsigned Integer
Execution Model
Registers
General Purpose (GP)
30 (R1 – R30)
External Status
1 (R31)
GP / Indexing
1 (R0)
Addressability
Bit, Byte (8-bit), Halfword (16-bit), Word (32-bit), Pointer
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Attribute
Value
Addressing Modes
Load Immediate
16-bit Immediate
Register Base + Register Offset
Register Base + 8-bit Immediate Offset
Register Base with auto increment / decrement
Load / Store – Memory
Constant Table Base + Register Offset
Constant Table Base + 8-bit Immediate Offset
Constant Table Base with auto increment / decrement
332
Data Path Width
32-Bits
Instruction Width
32-Bits
Accessibility to Internal PRU
Structures
Provides 32-bit Slave with 3 regions:
• Instruction RAM
• Control / Status registers
• Debug access to internal registers (R0-R31) and constant table
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14.2 Description
The processor is based on a four bus architecture which allows instructions to be fetched and executed
concurrently with data transfers. Additionally, an input is provided in order to allow external status
information to be reflected in the internal processor status register. The figure below shows a block
diagram of the processing element and the associated instruction RAM/ROM that contains the code that is
to be executed.
Figure 14-1. PRU Block Diagram
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14.3 Constants Table
The PRU Constants Table is a structure connected to a dedicated interface on the PRU core within the
PRU that is used to provide the base address for the Load Burst Constant + Offset (LBCO) and Store
Burst Constant + Offset (SBCO) instructions. The PRU Constants Table is provided in order to maximize
the usage of the PRU register file for embedded processing applications by moving many of the commonly
used constant or deterministically calculated base addresses from the internal register file to an external
table. Since this table is accessed using a dedicated interface, no performance difference is realized
between the LBCO and LBBO or SBCO and SBBO instructions. The constants in the table are provided in
Table 2.
Table 14-1. Constants Table (1)
Entry #
(1)
Region Pointed To
Value [31:0]
0
PRU0/1 Local INTC
0x00004000
1
Timer64P0
0x01C20000
2
I2C0
0x01C22000
3
PRU0/1 Local Data
0x00000000
4
PRU1/0 Local Data
0x00002000
5
MMC/SD
0x01C40000
6
SPI0
0x01C41000
7
UART0
0x01C42000
8
McASP0 DMA
0x01D02000
9
Reserved
0x01D06000
10
Reserved
0x01D0A000
11
UART1
0x01D0C000
12
UART2
0x01D0D000
13
USB0
0x01E00000
14
USB1
0x01E25000
15
UHPI Config
0x01E10000
16
Reserved
0x01E12000
17
I2C1
0x01E28000
18
EPWM0
0x01F00000
19
EPWM1
0x01F02000
20
Reserved
0x01F04000
21
ECAP0
0x01F06000
22
ECAP1
0x01F07000
23
ECAP2
0x01F08000
24
PRU0/1 Local Data
0x00000n00, n = c24_blk_index[3:0]
25
McASP0 Control
0x01D00n00, n = c25_blk_index[3:0]
26
Reserved
0x01D04000
27
Reserved
0x01D08000
28
DSP Megamodule RAM/ROM
0x11nnnn00, nnnn = c28_pointer[15:0]
29
EMIFA SDRAM
0x40nnnn00, nnnn = c29_pointer[15:0]
30
Shared RAM
0x80nnnn00, nnnn = c30_pointer[15:0]
31
mDDR/DDR2 Data
0xC0nnnn00, nnnn = c31_pointer[15:0]
These constants cannot be used due to memory map restrictions.
1. Constants not in this table can be created ’on the fly’ by two consecutive LDI
#16 instructions. These constants are just ones that are expected to be
commonly used, enough so to be hard-coded into the PRU constants table.
2. Constants table entries 24 through 31 are not fully hard-coded, but contain a
programmable bitfield (ex. c24_blk_index[3:0]) that is programmable through
the PRU control register space (0x01C3_7000 - 0x01C3_73FF for PRU0 and
0x01C3_7800 - 0x01C3_7BFF for PRU1).
334
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14.4 PRU Module Interface
14.4.1 Event Out Mapping (R31): PRU System Events
PRU Event Interface directly feeds pulsed event information out of the PRU’s internal ALU. This provides
the interface logic between the PRU R31 event_out[5:0] and the system interrupts for the PRUSS Interrupt
controller(INTC).
Bits
31-6
5
4-0
Name
Description
Reserved
pruX_vec_valid
Valid strobe for vector output
pruX_vec[4:0]
Vector output
Writing a ’1’ to pruX_vec_valid (R31 bit 5) simultaneously with a channel number from 0 to 31 written to
pruX_vec[4:0] (R31 bits 4:0) creates a pulse on the output of the appropriate de-multiplexer output. For
example, writing ’100000’ will generate a pulse on demux channel 0, writing ’100001’ will generate a pulse
on demux channel 1, ... writing ’111111’ will generate a pulse on demux channel 31, and writing ’0xxxxx’
will not generate any pulse on the demux output. The demultiplexed values from both of the PRUs are
logically ORed together. The composite demultiplexed output channels 0 through 31 are connected to
system interrupts 32 through 63 respectively.
This allows the PRU to assert one of the systems interrupts 32-63 by writing to its own R31 register. The
system interrupt is used to either post a completion event to one of the host CPUs (ARM, DSP) or to
signal the other PRU. The host to be signaled is determined by the system interrupt to interrupt channel
mapping (programmable). Refer to Section 14.7 for more details.
14.4.2 Status Mapping (R31): Interrupt Events Input
The PRU Real Time Status Interface directly feeds information into register 31(R31) of the PRU’s internal
register file. The firmware on the PRU uses the status information to make decisions during execution.
The status interface is comprised of signals from different modules inside of the PRUSS which require
some level of interaction with the PRU. More details on the Host interrupts imported into bit 30 and 31 of
register R31 of both the PRUs is provided in the chapter 3, PRUSS Interrupt Controller (INTC).
Bits
Name
Description
31
pru_intr_in[1]
PRU Interrupt 1 from INTC
30
pru_intr_in[0]
PRU Interrupt 0 from INTC
pruX_r31_status[29:0]
Status inputs from primary input
29-0
14.4.3 General Purpose Inputs (R31)
The pruX_r31_status[29:0] are mapped out of the PRUSS and are brought out as general purpose input
pins. The values input to the pins "pruX_R31[29:0]" are reflected in the R31 register on bits [29:0] to be
used by the program running on the PRU. Each PRU of the PRUSS has a separate mapping to pins, so
that there are 60 total general purpose inputs to the PRUSS.
14.4.4 General Purpose Outputs (R30)
The pruX_r30[31:0] bits are exported out of the PRUSS and are brought out as general purpose output
pins. The values written to register R30 will be reflected on the general purpose output pins
"pruX_R30[31:0]" to be used by the program running on the PRU. Each PRU of the PRUSS has a
separate mapping to pins, so that there are 64 total general purpose outputs from the PRUSS.
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14.5 Instruction Set
The instruction set is divided into four major categories:
1. Instructions which move data in or out of the processors internal registers
2. Instructions which perform an arithmetic operation
3. Instructions which perform a logical operation
4. Instructions which control program flow
The following sections give a complete list and short description of all of the supported instructions. In
these descriptions, the following abbreviations are used:
Table 14-2. Abbreviations for Instruction Descriptions
Abbreviation
Description
Rs1
Source register 1 from the instruction
Op2
Operand 2 from the instruction – can be either a register (Rs2) or an 8-bit immediate
value
Rd
Destination register from the instruction
BrOff
WdCnt
CPI
Branch offset from the instruction – a 10-bit 2’s complement relative offset
Word count – the # of 32-bit data phases that occur in the burst on an external
memory interface
Clock Cycles Per Instruction
Table 14-3. Load/Store Instructions
Mnemonic
LDI
Instruction
Description
Load Immediate
Load 16-bit immediate value into internal register
CPI
1
LBBO
Load Burst, Base + Offset
Load variable length burst of bytes through one of the memory
interfaces into internal register(s) using a register as the base
address and a register or an 8-bit immediate as the offset
1 + WdCnt
(VBUS)
2 + WdCnt
(VBUSP)
SBBO
Store variable length burst of bytes through one of the memory
Store Burst, Base + Offset interfaces from internal register(s) using a register as the base
address and a register or 8-bit immediate as the offset
1 + WdCnt
LBCO
Load Burst, Constant +
Offset
Load variable length burst of bytes through one of the memory
interfaces into internal register(s) using an indexed constant as
the base address and a register or an 8-bit immediate as the
offset
1 + WdCnt
(VBUS)
2 + WdCnt
(VBUSP)
SBCO
Store Burst, Constant +
Offset
Store variable length burst of bytes through one of the memory
interfaces from internal register(s) using an indexed constant as
the base address and a register or 8-bit immediate as the offset
1 + WdCnt
Table 14-4. Arithmetic Instructions
Mnemonic
ADD
336
Instruction
Description
CPI
Integer Add
Adds Rs1 and Op2, writes result to Rd, and saves carry.
1
ADC
Integer Add With Carry
Adds Rs1, Op2 and the saved carry, writes result to Rd, and
saves carry.
1
SUB
Integer Subtract
Subtracts Op2 from Rs1 and writes result to Rd and saves carry
(borrow).
1
SUC
Integer Subtract With
Carry
Subtracts Op2 from Rs1 then subtracts the saved carry (borrow)
and writes result to Rd and saves carry (borrow).
1
RSB
Integer Reverse Subtract
Subtracts Rs1 from Op2 and writes result to Rd and saves carry
(borrow).
1
RSC
Interger Reverse Subtract
With Carry
Subtracts Rs1 from Op2 then subtracts the saved carry (borrow)
and writes result to Rd and saves carry (borrow).
1
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Table 14-5. Logical Instructions
Mnemonic
Instruction
Description
CPI
AND
Bitwise And
Bitwise ANDs Rs1 with Op2 and stores to Rd.
1
OR
Bitwise Or
Bitwise ORs Rs1 with Op2 and stores to Rd.
1
XOR
Bitwise Exclusive Or
Bitwise exclusive ORs Rs1 with Op2 and stores to Rd.
1
NOT
Bitwise Invert
Bitwise inverts Rs1 and stores to Rd.
1
LSR
Logical Shift Right
Shifts Rs1 right (with zero fill) by the value given in the 5 LSBs of
Op2 and stores to Rd.
1
LSL
Logical Shift Left
Shifts Rs1 left (with zero fill) by the value given in the 5 LSBs of
Op2 and stores to Rd.
1
MIN
Minimum
Compares Rs1 and Op2 and the smaller value is copied to Rd.
1
MAX
Maximum
Compares Rs1 and Op2 and the larger value is copied to Rd.
1
CLR
Clear Bit
Copies Rs1 to Rd but with a bit specied by the 5 LSBs of Op2
cleared during the copy.
1
SET
Set Bit
Copies Rs1 to Rd but with a bit specied by the 5 LSBs of Op2
set during the copy.
1
LMBD
Left-most Bit Detect
Scans Rs1 from the leftmost bit for a bit equal to bit 0 of Rs2.
When found, the bit number (0 to 31) is written to Rd. If not
found, the value 32 is written to Rd.
1
Scan Register File
Scans the register file for a byte pattern of a programmable
length (up to 4 bytes) with a programmable field count and field
stride.
The Op1 register contains 4 fields: Rn.b0 = offset in the register
file from R0.b0 to start scanning Rn.b1 = fc (field count), the
number of fields to scan Rn.b2 = fw (field width), the size in bytes
of the field to scan for (1, 2, or 4 bytes) Rn.b3 = fs (field stride),
the number of bytes to advance to the next field in the register
file (1 to 4 bytes)
Op1 is updated after the scan with the offset of the match (or
0xFF if no match) in Rn.b0, and the fields remaining in the scan
(including the matching field) in Rn.b1.
The Op2 is the field to scan for.
SCAN
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IF fw = fs
2+((fc*fw+3)/4)
ELSE 2+fc
This is a worst
case cycle
count. Matching
scans could take
fewer cycles.
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Table 14-6. Program Flow Control Instructions
Mnemonic
Description
CPI
QBBS
Quick Branch – Bit Set
Adds BrOff to the program counter if the bit in Rs1 specified by
the 5 LSBs of Op2 is a 1
QBBC
Quick Branch –
Bit Clear
Adds BrOff to the program counter if the bit in Rs1 specified by
the 5 LSBs of Op2 is a 0
1
QBGT
Quick Branch –
Greater Than
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is greater than Rs1.
1
QBGE
Quick Branch –
Greater Than or Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is greater than or equal to Rs1.
1
QBLT
Quick Branch –
Less Than
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is less than Rs1.
1
QBLE
Quick Branch –
Less Than or Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is less than or equal to Rs1.
1
QBEQ
Quick Branch – Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is equal to Rs1.
1
QBNE
Quick Branch – Not Equal
Compares Op2 to Rs1 and adds BrOff to the program counter if
Op2 is not equal to Rs1.
1
JMP
Unconditional Jump
Sets the program counter equal to either the contents of a
register or to a 16-bit immediate value
1
JAL
Unconditional Jump and
Link
Saves the current program counter into Rd and sets the program
counter equal to either the contents of a register or to a 16-bit
immediate value.
1
Halt Processor
Disables the PRU and does not increment the program counter.
When the PRU is re-enabled, it will continue processing at this
instruction.
1
Sleep
Pauses execution of the current program and disables the clock
for the majority of the core until a specified external event (unmasked status bit) is asserted.
1 to infinity
HALT
SLP
338
Instruction
Programmable Real-Time Unit Subsystem (PRUSS)
1
SPRUH77C – April 2013 – Revised September 2016
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Instruction Formats
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14.6 Instruction Formats
A total of 7 different instruction formats are supported for the various operations. The following sections
describe the position, size, and function of each of the fields within the various formats.
Figure 14-2. Format 1a: (All Arithmetic and Logical Functions – Register Op2)
31
29
28
OP
15
24
IO
8
ALUOP
13
12
Rs1Sel
Rs1
23
21
20
Rs2Sel
7
16
Rs2
5
RdSel
4
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-7. Format 1a: (All Arithmetic and Logical Functions – Register Op2)
Bit
Field
Description
31-29
OP
0b000 = Specifies Format 1
28-25
ALUOP
0 = ADD
1 = ADC
2 = SUB
3 = SUC
4 = LSL
5 = LSR
6 = RSB
7 = RSC
8 = AND
9 = OR
10 = XOR
11 = NOT
12 = MIN
13 = MAX
14 = CLR
15 = SET
24
IO
0 = Op2 is a register
23-21
Rs2Sel
0
1
2
3
4
5
6
7
20-16
Rs2
0 – 31 = This field selects the register number which contains the second source operand
15-13
Rs1Sel
0
1
2
3
4
5
6
7
12-8
Rs1
0-31 = This field selects the register number which contains the first source operand
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
SPRUH77C – April 2013 – Revised September 2016
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bits 7:0 from the source register 2
bits 15:8 from the source register 2
bits 23:16 from the source register 2
bits 31:24 from the source register 2
bits 15:0 from the source register 2
bits 23:8 from the source register 2
bits 31:16 from the source register 2
bits 31:0 from the source register 2
bits 7:0 from the source register 1
bits 15:8 from the source register 1
bits 23:16 from the source register 1
bits 31:24 from the source register 1
bits 15:0 from the source register 1
bits 23:8 from the source register 1
bits 31:16 from the source register 1
bits 31:0 from the source register 1
Programmable Real-Time Unit Subsystem (PRUSS)
Copyright © 2013–2016, Texas Instruments Incorporated
339
Instruction Formats
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Table 14-7. Format 1a: (All Arithmetic and Logical Functions – Register Op2) (continued)
Bit
Field
Description
7-5
RdSel
0
1
2
3
4
5
6
7
4-0
Rd
0-31 = This field selects the destination register number to which the result should be written.
340
= Select
= Select
= Select
= Select
= Select
= Select
= Select
= Select
bits 7:0 of the destination register
bits 15:8 of the destination register
bits 23:16 of the destination register
bits 31:24 of the destination register
bits 15:0 of the destination register
bits 23:8 of the destination register
bits 31:16 of the destination register
bits 31:0 of the destination register
Programmable Real-Time Unit Subsystem (PRUSS)
SPRUH77C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Instruction Formats
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Figure 14-3. Format 1b: (All Arithmetic and Logical Functions – Immediate Op2)
31
29
28
OP
15
ALUOP
13
12
Rs1Sel
24
IO
8
Rs1
23
16
Imm2
7
5
RdSel
4
0
Rd
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-8. Format 1b: (All Arithmetic and Logical Functions – Immediate Op2)
Bit
Field
Description
31-29
OP
0b000 = Spe