Texas Instruments | DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) (Rev. A) | User Guides | Texas Instruments DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) (Rev. A) User guides

Texas Instruments DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) (Rev. A) User guides
DM38x and TMS320DM8127 DaVinci™
Digital Media Processor
Imaging Subsystem (ISS)
User's Guide
Literature Number: SPRUHL6A
January 2013 – Revised June 2016
Contents
Preface....................................................................................................................................... 26
1
1
2
3
2
Imaging Subsystem (ISS) .................................................................................................... 27
ISS Overview ..................................................................................................................... 27
1.1
ISS Integration .......................................................................................................... 30
1.2
ISS Functional Description ............................................................................................ 33
1.3
ISS Registers............................................................................................................ 49
ISS Interfaces..................................................................................................................... 62
2.1
ISS Interfaces Overview ............................................................................................... 63
2.2
ISS Interfaces Environment ........................................................................................... 66
2.3
ISS CSI2 PHY........................................................................................................... 68
....................................................................................... 77
....................................................................................... 78
2.6
ISS CSI2 ............................................................................................................... 107
2.7
ISS TCTRL ............................................................................................................. 194
2.8
ISS BTE ................................................................................................................ 212
2.9
ISS CBUFF ............................................................................................................ 251
ISS ISP ............................................................................................................................ 295
3.1
ISS ISP Overview ..................................................................................................... 295
3.2
ISS ISP Integration.................................................................................................... 297
3.3
ISS ISP Functional Description...................................................................................... 303
3.4
ISS ISP Programming Model ........................................................................................ 455
3.5
ISS ISP Registers ..................................................................................................... 494
2.4
ISS Stall Controller Integration
2.5
ISS SC Functional Description
Table of Contents
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
List of Figures
...............................................................................................................
1
ISS Overview
2
ISS Integration .............................................................................................................. 30
3
ISS Interrupt Merger ....................................................................................................... 34
4
ISS Local Interconnect Data Network ................................................................................... 43
5
ISS Power Management
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
27
.................................................................................................. 46
ISS_HL_REVISION Register ............................................................................................. 49
ISS_HL_HWINFO Register ............................................................................................... 50
ISS_HL_SYSCONFIG Register .......................................................................................... 51
ISS_HL_IRQSTATUS_RAW_i_Register ................................................................................ 52
ISS_HL_IRQSTATUS_i_Register ........................................................................................ 53
ISS_HL_IRQENABLE_SET_i Register .................................................................................. 55
ISS_HL_IRQENABLE_CLR_i Register .................................................................................. 57
ISS_CTRL Register ........................................................................................................ 59
ISS_CLKCTRL Register ................................................................................................... 60
ISS_CLKSTAT Register ................................................................................................... 61
ISS_PM_STATUS Register ............................................................................................... 62
ISS Interfaces and Interconnects Highlights ............................................................................ 63
ISS CSI2-A Serial Interface and Parallel Interface Configuration .................................................... 67
ISS Interfaces CSI2-A PHY Diagram Four D-PHY Data Lane Configuration ...................................... 68
ISS CSI2 Complex I/O Power FSM ...................................................................................... 69
ISS CSI2 RxMode and StopState FSM ................................................................................. 70
ISS_CSI2_PHY_REGISTER0 ............................................................................................ 74
ISS_CSI2_PHY_REGISTER1 ............................................................................................ 75
ISS_CSI2_PHY_REGISTER2 ............................................................................................ 76
ISS Stall Controller Integration ........................................................................................... 77
ISS SC Receiver Block Diagram ......................................................................................... 78
ISS SC VP_PCLK Gating During Blanking Periods .................................................................. 79
ISS SC Data Organization in Memory ................................................................................... 84
ISS SC Data Organization Packing in Memory ........................................................................ 85
ISS SC Data Organization in Memory ................................................................................... 86
SC_CTRL.VP_CLK_POL Settings ....................................................................................... 89
SC_REVISION Register ................................................................................................... 92
ISS CSI2 One Data-Lane Configuration ............................................................................... 109
ISS CSI2 Two Data-Lane Merger Configuration ...................................................................... 109
ISS CSI2 Three Data-Lane Merger Configuration .................................................................... 110
ISS CSI2 Four Data-Lane Merger Configuration ..................................................................... 111
ISS CSI2 Protocol Layer With Short and Long Packets ............................................................. 112
ISS CSI2 Short Packet Structure ....................................................................................... 112
ISS CSI2 Long Packet Structure ....................................................................................... 113
ISS CSI2 Data Identifier Structure ...................................................................................... 114
ISS CSI2 Virtual Channel ................................................................................................ 114
ISS CSI2 General Frame Structure (Informative) .................................................................... 116
ISS CSI2 Digital Interlaced Video Frame (Informative) .............................................................. 117
ISS CSI2 YUV4:2:0 8-Bit ................................................................................................ 118
ISS CSI2 YUV4:2:0 10-Bit ............................................................................................... 119
ISS CSI2 YUV4:2:0 8-Bit Legacy ....................................................................................... 120
ISS CSI2 YUV4:2:0 8-Bit + CSPS ...................................................................................... 121
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
3
www.ti.com
48
Camera ISP CSI2 Byte Swap ........................................................................................... 122
49
ISS CSI2 YUV4:2:0 10-Bit + CSPS
123
50
ISS CSI2 YUV4:2:2 8-Bit
124
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
4
....................................................................................
................................................................................................
ISS CSI2 YUV4:2:2 10-Bit ...............................................................................................
ISS CSI2 RGB565 ........................................................................................................
ISS CSI2 RGB888 ........................................................................................................
ISS CSI2 RGB666 ........................................................................................................
ISS CSI2 RGB444 ........................................................................................................
ISS CSI2 RGB555 ........................................................................................................
ISS CSI2 RAW6...........................................................................................................
ISS CSI2 RAW7...........................................................................................................
ISS CSI2 RAW8...........................................................................................................
ISS CSI2 RAW10 .........................................................................................................
ISS CSI2 RAW12 .........................................................................................................
ISS CSI2 RAW14 .........................................................................................................
ISS CSI2 JPEG8 ..........................................................................................................
ISS CSI2 Generic Format................................................................................................
ISS CSI2-A Integration ...................................................................................................
ISS CSI2-A Receiver Block Diagram...................................................................................
ISS CSI2 SHORT_PACKET Bit Field Format .........................................................................
ISS CSI2 Virtual Channel to Context ...................................................................................
ISS CSI2 Pixel Data Destination Setting in Progressive and Interlaced Mode ...................................
ISS CSI2 Frame Processing ............................................................................................
ISS CSI2 Frame Cropping ...............................................................................................
ISS CSI2 Horizontal Scaler ..............................................................................................
ISS CSI2 Receiver Global Reset Flow Chart .........................................................................
ISS TCTRL Integration ...................................................................................................
TCTRL Control-Signal Generation......................................................................................
ISS TCTRL Use of cam_global_reset With Global Reset Release Camera Modules ...........................
cam_strobe Signal-Generation for Red-Eye Removal ...............................................................
ISS BTE Integration ......................................................................................................
ISS BTE Logical Overview ..............................................................................................
ISS BTE Burst Translation Principle ...................................................................................
ISS BTE Context Mapping ...............................................................................................
ISS BTE Expected Access Locations in the Virtual Space..........................................................
ISS BTE Context Alignment Constraints ..............................................................................
ISS BTE TILER Mode Addressing in 90- or 270-Degree Orientation ..............................................
BTE Bandwidth Limiter Example .......................................................................................
ISS BTE Buffer Fill-Level Padding......................................................................................
ISS BTE 2D Burst Generation ..........................................................................................
ISS BTE Tiler Mode Addressing in 90- or 270-Degree Orientation (S = 1) .......................................
ISS CBUFF Integration...................................................................................................
ISS CBUFF Top-Level Diagram ........................................................................................
ISS CBUFF Write Mode CPU Interaction Example ..................................................................
ISS CBUFF CPU Writes Data Faster Than it Is Read by the OCPI Initiator ......................................
CBUFF Read Mode CPU Interaction Example .......................................................................
ISS CBUFF Read/Write Mode Example ...............................................................................
ISS CBUFF Write Mode CPU Interaction Example BCF Used .....................................................
ISS CBUFF Read Mode CPU Interaction Example (1) ..............................................................
List of Figures
125
126
127
128
129
129
131
133
135
136
137
138
139
139
144
145
147
148
150
151
152
153
155
195
196
198
202
212
214
215
216
217
218
219
220
221
223
226
252
255
256
257
257
258
260
260
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
97
ISS CBUFF Read Mode CPU Interaction Example (2) .............................................................. 261
98
ISS CBUFF BCF Pretrigger Example: Write Mode................................................................... 262
99
ISS CBUFF BCF Pretrigger Example: Read Mode
100
ISS CBUFF Single-Slice Buffer (Write Mode) ......................................................................... 266
101
ISS CBUFF Single-Slice Buffer Example (Write Mode) ............................................................. 267
102
ISS CBUFF Extended-Slice Buffer Example .......................................................................... 267
103
ISS CBUFF FIFO Mode .................................................................................................. 268
..................................................................
262
104
ISS CBUFF FIFO Use Example ........................................................................................ 268
105
ISS ISP Block Diagram
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
..................................................................................................
ISS ISP High-Level Diagram ............................................................................................
ISS ISP VP High-Level Diagram ........................................................................................
ISS ISP VP VD Pulse ....................................................................................................
ISS ISP IPIPEIF High-Level Diagram ..................................................................................
ISS ISP IPIPEIF Top-Level Block Diagram ...........................................................................
ISS ISP IPIPEIF Global Frame Definition in SDRAM Input Modes (Except Dark Frame) ......................
ISS ISP IPIPEIF Global Frame Definition in Dark Frame Subtract Mode .........................................
ISS ISP IPIPEIF Double-Buffer Functionality .........................................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0 Data Path ......................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1 Data Path ......................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2 Data Paths .....................................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3 Data Paths: First Case .......................................
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3 Data Paths: Second Case ...................................
ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0 Data Path ......................................................
ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0 Data Path ......................................................
ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0 Data Path ......................................................
ISS ISP IPIPEIF Timing Generator Submodule ......................................................................
ISS ISP IPIPEIF DCPM Subblock ......................................................................................
ISS ISP IPIPEIF Dark-Frame Subtraction Subblock .................................................................
ISS ISP IPIPEIF Resizer Offset Definition .............................................................................
ISS ISP IPIPEIF YUV8P Settings ......................................................................................
ISS ISP IPIPE High-Level Diagram ....................................................................................
ISS ISP IPIPE Supported CFA Format ................................................................................
ISS ISP IPIPE Module Block Diagram .................................................................................
ISS ISP IPIPE Module Input Format ...................................................................................
ISS ISP IPIPE Module Processing Window Settings ................................................................
ISS ISP IPIPE Defect Pixel Correction.................................................................................
ISS ISP IPIPE Pixel Numbering in Defect Correction Algorithm ...................................................
ISS ISP IPIPE Mirroring in Defect Correction and Noise Filter .....................................................
ISS ISP IPIPE Adaptive OTF DPC Method 1 Defect Correction ...................................................
ISS ISP IPIPE Center Pixel d0 Replacement in Adaptive OTF DPC Method 2 Formula .......................
ISS ISP IPIPE Adaptive OTF DPC Method 2 Method Center Pixel Replaced With dmax ......................
ISS ISP IPIPE Adaptive OTF DPC Method 2 Method Center Pixel Replaced With dmax2 ....................
ISS ISP IPIPE DPC Activity Pixel Definition ..........................................................................
ISS ISP IPIPE Noise Filter Array .......................................................................................
ISS ISP IPIPE Noise Filter Module Block Diagram ..................................................................
ISS ISP IPIPE Edge Detection Formula ...............................................................................
ISS ISP IPIPE Edge Detection Formula 2 .............................................................................
ISS ISP IPIPE GIC Prefilter Pixels .....................................................................................
ISS ISP IPIPE GIC Threshold Calculation 1 ..........................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
296
303
304
306
308
309
310
311
312
314
315
316
317
318
319
320
321
322
323
325
328
329
332
333
333
334
335
335
336
337
338
338
339
339
340
340
341
342
343
344
344
5
www.ti.com
146
ISS ISP IPIPE GIC Threshold Calculation 2 .......................................................................... 345
147
ISS ISP IPIPE GIC Adaptive Prefilter Weight Function .............................................................. 345
148
ISS ISP IPIPE White Balance ........................................................................................... 345
149
ISS ISP IPIPE CFA Interpolation ....................................................................................... 346
150
ISS ISP IPIPE RGB2RGB Conversion Formula ...................................................................... 347
151
ISS ISP IPIPE Gamma Correction Module Block Diagram ......................................................... 347
152
ISS ISP IPIPE Gamma Curve Example ............................................................................... 348
153
ISS ISP IPIPE Gamma Table Offset/Slope Packing ................................................................. 348
154
ISS ISP IPIPE RGB2RGB 2nd Conversion Formula................................................................. 348
155
ISS ISP IPIPE 3D-LUT Color Conversion Formula
156
ISS ISP IPIPE 3D-LUT Entry Number Formula....................................................................... 349
157
ISS ISP IPIPE 3D-LUT Tetrahedral Interpolation Formula .......................................................... 349
158
ISS ISP IPIPE 3D-LUT Data Packing .................................................................................. 350
159
ISS ISP IPIPE RGB2RGB 2nd Conversion Formula................................................................. 350
160
ISS ISP IPIPE RGB2YCbCr Module Block Diagram ................................................................. 351
161
ISS ISP IPIPE GBCE Mode 1 Formula ................................................................................ 351
162
ISS ISP IPIPE GBCE Mode 2 Formula ................................................................................ 351
163
ISS ISP IPIPE GBCE Mode Off Formula .............................................................................. 352
164
ISS ISP IPIPE GBCE LUT Packing in Mode 1........................................................................ 352
165
ISS ISP IPIPE GBCE LUT Packing in Mode 2........................................................................ 352
166
ISS ISP IPIPE Chroma Subsampling Position ........................................................................ 353
167
ISS ISP IPIPE 4:2:2 Conversion Module Block Diagram ............................................................ 353
168
ISS ISP IPIPE 2D Edge-Enhancer Indexing .......................................................................... 354
169
ISS ISP IPIPE 2D Edge Intensity LUT Formula ...................................................................... 354
170
ISS ISP IPIPE 2D Edge-Enhancer LUT Packing ..................................................................... 355
171
ISS ISP IPIPE 2D Edge-Enhancer Block Diagram ................................................................... 355
172
ISS ISP IPIPE Edge Sharpener Details
355
173
ISS ISP IPIPE 2D Edge-Intensity Clipping Formula
356
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
6
..................................................................
...............................................................................
.................................................................
ISS ISP IPIPE 2D Edge Enhancer and Sharpener Merger Formula...............................................
ISS ISP IPIPE 2D Edge Chroma-Suppression Coefficient Sets ....................................................
ISS ISP IPIPE 2D Edge-Brightness and Contrast Adjustments Formula .........................................
ISS ISP IPIPE CAR Block Diagram (Cb Part) ........................................................................
ISS ISP IPIPE CAR Gain Control Mode Formula ....................................................................
ISS ISP IPIPE CAR Gain 1 and Gain 2 Functions ...................................................................
ISS ISP IPIPE CAR Gain Control Functions Output Formula ......................................................
ISS ISP IPIPE CGS Gain Value Formula .............................................................................
ISS ISP IPIPE CGS Gain 1..............................................................................................
ISS ISP IPIPE CGS Gain 2..............................................................................................
ISS ISP IPIPE Boxcar Operation (8 × 8 Block) .......................................................................
ISS ISP IPIPE Boxcar Operation (16 × 16 Block) ....................................................................
ISS ISP IPIPE Boxcar Data Packing in SDRAM .....................................................................
ISS ISP IPIPE Block Diagram of BSC Module........................................................................
ISS ISP IPIPE BSC Row Sum Vector Calculation ...................................................................
ISS ISP IPIPE BSC Column Sum Vector Calculation ...............................................................
ISS ISP RSZ High-Level Diagram ......................................................................................
ISS ISP RSZ Top-Level Block Diagram ...............................................................................
ISS ISP RSZ MTC DMA Bandwidth Control ..........................................................................
ISS ISP RSZ MTC Image Data Storage Pixel Order ................................................................
ISS ISP RSZ Typical Module Integration: High-Level Summary ...................................................
List of Figures
349
356
356
356
357
357
358
358
359
360
360
362
362
363
364
365
366
368
369
370
371
372
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
195
ISS ISP RSZ Operating Modes ......................................................................................... 375
196
ISS ISP RSZ Input Data Cropper Block Diagram .................................................................... 376
197
ISS ISP RSZ Input Data Cropping
198
ISS ISP RSZ-A/RSZ-B Input Data Buffering .......................................................................... 379
199
ISS ISP RSZ Data Requestor Module Behavior Example
200
ISS ISP RSZ Averager Memory Utilization ............................................................................ 381
201
ISS ISP RSZ Averager Border Conditions
202
ISS ISP RSZ Basic Interpolation Method .............................................................................. 383
203
ISS ISP RSZ Interpolation Filtering
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
.....................................................................................
..........................................................
............................................................................
....................................................................................
ISS ISP RSZ-A/RSZ-B Phase Averager Effect .......................................................................
ISS ISP RSZ Chroma Position and Upsampling .....................................................................
ISS ISP RSZ and Circular Buffer Settings.............................................................................
ISS ISP RSZ and Circular Buffer Settings – Example 1 .............................................................
ISS ISP RSZ and Circular Buffer Settings – Example 2 .............................................................
ISS ISP H3A High-Level Diagram ......................................................................................
ISS ISP H3A Top-Level Block Diagram ...............................................................................
ISS ISP H3A Frame Format Settings ..................................................................................
ISS ISP H3A Red, Green, and Blue Pixel Extraction Examples....................................................
ISS ISP H3A Horizontal/Vertical FV Paxel Configuration ...........................................................
ISS ISP H3A IIR Filter Model ...........................................................................................
ISS ISP H3A AE/AWB Window Configurations .......................................................................
ISS ISP H3A Black Row of Windows Before Regular Rows of Windows .........................................
ISS ISP H3A AE/AWB Window and Subsample Definition .........................................................
ISS ISP ISIF High-Level Diagram ......................................................................................
ISS ISP ISIF Top-Level Block Diagram ................................................................................
ISS ISP ISIF Interface Block Diagram .................................................................................
ISS ISP ISIF Sensor Linearization Block Diagram ...................................................................
ISS ISP ISIF Linearization LUT Memories ............................................................................
ISS ISP ISIF Linearization Block Diagram ............................................................................
ISS ISP ISIF Input Data Formatter Block Diagram ...................................................................
ISS ISP ISIF Splits an Input Line Into Three Output Lines ..........................................................
ISS ISP ISIF Input Data Formatter Area Settings ....................................................................
ISS ISP ISIF Data Formatter Output Control Example ..............................................................
ISS ISP ISIF Conventional Read-Out Pattern ........................................................................
ISS ISP ISIF Conventional Read-Out Pattern With 2-tap AFE .....................................................
ISS ISP ISIF Combine Three Input Lines Into Single Line ..........................................................
ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line .......................................
ISS ISP ISIF Color Space Converter Block Diagram ................................................................
ISS ISP ISIF Color Space Converter Operation ......................................................................
ISS ISP ISIF Color Space Converter Operation: CMYG to RGBG.................................................
ISS ISP ISIF Color Space Conversion Example......................................................................
ISS ISP ISIF 1st Pixel/1st Line Generation............................................................................
ISS ISP ISIF 2nd Pixel/1st Line Generation ...........................................................................
ISS ISP ISIF 2nd Last Pixel/1st Line Generation .....................................................................
ISS ISP ISIF Last Pixel/1st Line Generation ..........................................................................
ISS ISP ISIF 1st Pixel/Last Line Generation ..........................................................................
ISS ISP ISIF 2nd Pixel/Last Line Generation .........................................................................
ISS ISP ISIF 2nd Last Pixel/Last Line Generation ...................................................................
ISS ISP ISIF Last Pixel/Last Line Generation.........................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Figures
377
380
382
383
385
387
389
389
390
392
392
393
394
395
396
398
399
402
408
409
410
411
412
413
413
414
415
416
417
418
418
419
421
421
422
422
422
423
423
423
423
424
424
424
7
www.ti.com
244
ISS ISP ISIF Black Clamp Block Diagram............................................................................. 425
245
ISS ISP ISIF Clamp Value for Horizontal Direction
246
ISS ISP ISIF Clamp Value for Vertical Direction Calculation
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
8
..................................................................
.......................................................
ISS ISP ISIF Clamp Value for Vertical Direction With OB Region at the Left ....................................
ISS ISP ISIF Clamp Value for Vertical Direction With OB Region at the Right ..................................
ISS ISP ISIF Vertical Line Defect Correction Block Diagram .......................................................
ISS ISP ISIF Vertical Line Defects .....................................................................................
ISS ISP ISIF Vertical Line Defects .....................................................................................
ISS ISP ISIF 2D-LSC Block Diagram ..................................................................................
ISS ISP ISIF 2D-LSC Active Region for ISIF Input Frame ..........................................................
ISS ISP ISIF Gain and Offset Mask Upsampling via Bilinear Interpolation .......................................
ISS ISP ISIF White Balance Block Diagram ..........................................................................
ISS ISP ISIF Low-Pass Filter Block Diagram .........................................................................
ISS ISP ISIF A-Law Compression Block Diagram ...................................................................
ISS ISP ISIF A-Law Table Diagram ....................................................................................
ISS ISP ISIF A-Law Table Values ......................................................................................
ISS ISP ISIF Culling Block Diagram....................................................................................
ISS ISP ISIF Example for Decimation Pattern ........................................................................
ISS ISP ISIF Storage Formatter Block Diagram ......................................................................
ISS ISP ISIF Frame Image Format Conversion ......................................................................
ISS ISP ISIF VDINT0/VDINT1/VDINT2 Interrupt Behavior When VDPOL = 0 ...................................
ISS ISP ISIF VDINT0/VDINT1/VDINT2 Interrupt Behavior When VDPOL = 1 ...................................
ISS ISP BL High-Level Diagram ........................................................................................
ISS ISP BL Block Diagram ..............................................................................................
ISS ISP BL Address Alignment .........................................................................................
ISS ISP ISIF Initialization Flow Chart – Part One ....................................................................
ISS ISP ISIF Initialization Flow Chart – Part Two ....................................................................
ISS ISP RSZ Global Image Processing Settings – Subsequence 1 ...............................................
ISS ISP RSZ Global Image Processing Settings – Subsequence 2 ...............................................
ISS ISP RSZ Engines Interframe Image Processing Settings – Subsequence 1 ................................
ISS ISP RSZ Engines Interframe Image Processing Settings – Subsequence 2 ................................
List of Figures
426
427
428
428
429
429
430
431
432
433
436
437
438
438
439
441
441
442
444
446
446
447
449
450
456
457
483
484
486
487
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
List of Tables
1
ISS Integration Attributes .................................................................................................. 31
2
ISS Clocks and Resets .................................................................................................... 31
3
ISS Hardware Requests ................................................................................................... 32
4
ISS Local Clock Domains ................................................................................................. 32
5
ISS Interrupts ............................................................................................................... 33
6
ISS ISP Interrupts .......................................................................................................... 34
7
ISS CSI2-A Interrupts ...................................................................................................... 36
8
ISS CSI2-A Receivers Complex I/O Interrupts ......................................................................... 37
9
ISS CSI2-A Receiver CONTEXT Interrupts............................................................................. 37
10
ISS Stall Controller Interrupts ............................................................................................. 38
11
ISS CBUFF Interrupts
12
ISS BTE Interrupts ......................................................................................................... 39
13
ISS SIMCOP High-Level Interrupts ...................................................................................... 42
14
ISS Submodule Clock Gating ............................................................................................. 44
15
ISS TOP Register Mapping Summary ................................................................................... 49
16
ISS_HL_REVISION_Register Field Description........................................................................ 49
17
ISS_HL_HWINFO Field Descriptions .................................................................................... 50
18
ISS_HL_SYSCONFIG Field Descriptions ............................................................................... 51
19
ISS_HL_IRQSTATUS_RAW_i_Register Field Descriptions .......................................................... 52
20
ISS_HL_IRQSTATUS_i_Register Field Descriptions.................................................................. 53
21
ISS_HL_IRQENABLE_SET_i Field Descriptions
55
22
ISS_HL_IRQENABLE_CLR_i Register Field Descriptions
57
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
.....................................................................................................
......................................................................
...........................................................
ISS_CTRL Register Field Descriptions ..................................................................................
ISS_CLKCTRL Register Field Descriptions ............................................................................
ISS_CLKSTAT Register Field Descriptions .............................................................................
ISS_PM_STATUS Register Field Descriptions.........................................................................
ISS I/O Description .........................................................................................................
ISS CSI2 Possible Time-Out Value for RxMode Counter .............................................................
ISS CSI2 PHY Instance Summary .......................................................................................
ISS CSI2 PHY Registers Mapping Summary...........................................................................
ISS_CSI2_PHY_REGISTER0 Field Descriptions ......................................................................
ISS_CSI2_PHY_REGISTER1 Field Descriptions ......................................................................
ISS_CSI2_PHY_REGISTER2 Field Descriptions ......................................................................
ISS SC Video interface Signals ..........................................................................................
ISS SC Video Port Data Mapping ........................................................................................
ISS SC Memory-to-Memory Supported Operations ...................................................................
ISS SC Memory-to-Video Port Supported Formats ....................................................................
ISS SC Data Packing Benefit and Constraints ........................................................................
ISS SC Output Width Restrictions in Memory-to-Memory Operation ...............................................
ISS SC Configure Video Port .............................................................................................
ISS SC Configure Read Data From Memory ...........................................................................
ISS SC Instance Summary................................................................................................
ISS SC Registers Mapping Summary ...................................................................................
SC_REVISION Register Field Descriptions ............................................................................
SC_SYSCONFIG ...........................................................................................................
SC_SYSSTATUS ..........................................................................................................
SC_LCM_IRQENABLE ....................................................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
38
59
60
61
62
66
70
74
74
74
75
76
78
79
81
83
86
87
88
89
91
91
92
92
93
94
9
www.ti.com
48
SC_LCM_IRQSTATUS .................................................................................................... 95
49
SC_CTRL
50
SC_GNQ
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
10
................................................................................................................... 95
.................................................................................................................... 97
SC_CTRL1 .................................................................................................................. 98
SC_LCM_CTRL ............................................................................................................ 99
SC_LCM_VSIZE .......................................................................................................... 102
SC_LCM_HSIZE .......................................................................................................... 102
SC_LCM_PREFETCH ................................................................................................... 103
SC_LCM_SRC_ADDR ................................................................................................... 103
SC_LCM_SRC_OFST ................................................................................................... 104
SC_LCM_DST_ADDR ................................................................................................... 104
SC_LCM_DST_OFST .................................................................................................... 105
SC_LCM_HISTORY ...................................................................................................... 106
ISS CSI2 Pixel Format Modes .......................................................................................... 107
ISS CSI2-A I/O Description .............................................................................................. 108
ISS CSI2 Long Packet Structure Description ......................................................................... 113
ISS CSI2 Synchronization Codes....................................................................................... 114
ISS CSI2 MIPI Format Supported by the Protocol Engine .......................................................... 140
ISS CSI2 ECC Event Logging .......................................................................................... 147
ISS CSI2 Supported Transcoding Input Formats ..................................................................... 151
ISS CSI2 Transcode Alignment Constraints .......................................................................... 152
ISS CSI2-Supported Transcoding Output Formats .................................................................. 153
ISS CSI2 Global Initialization ............................................................................................ 156
ISS CSI2 Capture a Finite Number of Frames........................................................................ 157
ISS CSI2 Enable Debug Mode.......................................................................................... 158
ISS CSI2 Instance Summary ............................................................................................ 159
ISS CSI2 REGS1 Registers Mapping Summary ..................................................................... 159
CSI2_REVISION .......................................................................................................... 160
CSI2_SYSCONFIG ....................................................................................................... 161
CSI2_SYSSTATUS ....................................................................................................... 162
CSI2_IRQSTATUS ....................................................................................................... 163
CSI2_IRQENABLE ....................................................................................................... 165
CSI2_CTRL ................................................................................................................ 167
CSI2_DBG_H ............................................................................................................. 169
CSI2_COMPLEXIO_CFG................................................................................................ 170
CSI2_COMPLEXIO_IRQSTATUS ...................................................................................... 173
CSI2_SHORT_PACKET ................................................................................................. 176
CSI2_COMPLEXIO_IRQENABLE ...................................................................................... 177
CSI2_DBG_P .............................................................................................................. 179
CSI2_TIMING ............................................................................................................. 180
CSI2_CTX_CTRL1_i ..................................................................................................... 181
CSI2_CTX_CTRL2_i ..................................................................................................... 184
CSI2_CTX_DAT_OFST_i ................................................................................................ 187
CSI2_CTX_DAT_PING_ADDR_i ....................................................................................... 188
CSI2_CTX_DAT_PONG_ADDR_i ...................................................................................... 188
CSI2_CTX_IRQENABLE_i .............................................................................................. 189
CSI2_CTX_IRQSTATUS_i .............................................................................................. 190
CSI2_CTX_CTRL3_i ..................................................................................................... 191
ISS CSI2 REGS2 Registers Mapping Summary ..................................................................... 192
List of Tables
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
97
CSI2_CTX_TRANSCODEH_i ........................................................................................... 192
98
CSI2_CTX_TRANSCODEV_i ........................................................................................... 193
99
ISS TCTRL Control-Signal Generator: CNTCLK Frequencies...................................................... 197
100
ISS TCTRL Enabling the Control-Signal Generation in First Configuration ....................................... 199
101
ISS TCTRL Enabling the Control-Signal Generation in Second Configuration ................................... 200
102
ISS TCTRL Instance Summary ......................................................................................... 202
103
ISS TCTRL Registers Mapping Summary ............................................................................. 202
104
TCTRL_REVISION ....................................................................................................... 203
105
TCTRL_SYSCONFIG .................................................................................................... 204
106
TCTRL_SYSSTATUS .................................................................................................... 204
107
TCTRL_STRB_LENGTH
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
................................................................................................
TCTRL_PSTRB_LENGTH ...............................................................................................
TCTRL_SHUT_LENGTH ................................................................................................
TCTRL_GRESET_LENGTH.............................................................................................
TCTRL_STRB_DELAY...................................................................................................
TCTRL_PSTRB_DELAY .................................................................................................
TCTRL_SHUT_DELAY ..................................................................................................
TCTRL_CTRL .............................................................................................................
TCTRL_PSTRB_REPLAY ...............................................................................................
TCTRL_FRAME ...........................................................................................................
ISS BTE TILER Context Configuration Example .....................................................................
ISS BTE Supported TILER Formats and Views ......................................................................
ISS BTE Interrupt Events ................................................................................................
ISS BTE Configure/Manage Interrupts .................................................................................
TILER Address Format...................................................................................................
ISS BTE Change Context Configuration ...............................................................................
ISS BTE Instance Summary.............................................................................................
ISS BTE Registers Mapping Summary ................................................................................
BTE_HL_REVISION ......................................................................................................
BTE_HL_HWINFO ........................................................................................................
BTE_HL_SYSCONFIG ...................................................................................................
BTE_HL_IRQSTATUS_RAW ...........................................................................................
BTE_HL_IRQSTATUS ...................................................................................................
BTE_HL_IRQENABLE_SET ............................................................................................
BTE_HL_IRQENABLE_CLR ............................................................................................
BTE_CTRL ................................................................................................................
BTE_CTRL1 ...............................................................................................................
BTE_CONTEXT_CTRL_i ................................................................................................
BTE_CONTEXT_BASE_i ................................................................................................
BTE_CONTEXT_START_i ..............................................................................................
BTE_CONTEXT_END_i .................................................................................................
ISS CBUFF Interrupt Management .....................................................................................
ISS CBUFF-Generated Events .........................................................................................
ISS CBUFF Functional Modes ..........................................................................................
ISS CBUFF Internal Variables ..........................................................................................
ISS CBUFF Internal State After Reset .................................................................................
ISS CBUFF Address identification ......................................................................................
ISS CBUFF Address Translation .......................................................................................
ISS CBUFF Window-Level Increment..................................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
205
205
206
206
207
207
208
208
210
211
218
222
224
225
225
226
227
227
227
228
229
230
234
238
242
246
247
247
249
249
250
253
253
255
263
263
263
264
265
11
www.ti.com
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
265
269
270
270
271
271
272
273
277
281
285
288
289
291
291
292
292
293
293
294
297
305
307
169
ISS ISP IPIPEIF IPIPEIF_CFG1[15:14] INPSRC1 and IPIPEIF_CFG1[3:2] INPSRC2 Possible
Combinations .............................................................................................................. 312
170
ISS ISP IPIPEIF DCPM Block Possible Configuration ............................................................... 324
171
ISS ISP IPIPEIF DFS Modes Supported .............................................................................. 326
172
ISS ISP IPIPEIF Averaging Filter Conditions for YUV4:2:2 Data................................................... 327
173
ISS ISP IPIPE Input and Output Selections ........................................................................... 334
174
ISS ISP IPIPE Defect Information Packing ............................................................................ 336
175
ISS ISP IPIPE Correction Method Description ........................................................................ 336
176
ISS ISP IPIPE Edge-Enhancer LUT Mapping
177
ISS ISP IPIPE CGS Gain Value Formula Parameters ............................................................... 359
178
ISS ISP RSZ VP Supported Formats .................................................................................. 370
179
ISS ISP RSZ Data Flow vs. Input Data Format Constraints ........................................................ 372
180
ISS ISP RSZ Module Modes: Register Settings ...................................................................... 373
181
ISS ISP RSZ Module Input Control: Register Settings
182
ISS ISP RSZ-A/RSZ-B Output Format Selection ..................................................................... 374
183
ISS ISP RZA Input Data Buffering: Vertical Upscale Ratio = x1.1 ................................................. 378
184
ISS ISP RZA Input Data Buffering: Vertical Upscale Ratio = x2.7 ................................................. 378
185
ISS ISP RSZ Output Interface: Data Formats
186
187
188
189
190
191
192
193
12
..............................................................................
ISS CBUFF Setup Register .............................................................................................
ISS CBUFF Instance Summary .........................................................................................
ISS CBUFF Registers Mapping Summary ............................................................................
CBUFF_HL_REVISION ..................................................................................................
CBUFF_HL_HWINFO ....................................................................................................
CBUFF_HL_SYSCONFIG ...............................................................................................
CBUFF_HL_IRQSTATUS_RAW ........................................................................................
CBUFF_HL_IRQSTATUS ...............................................................................................
CBUFF_HL_IRQENABLE_SET .........................................................................................
CBUFF_HL_IRQENABLE_CLR ........................................................................................
CBUFF_FRAG_ADDR_j .................................................................................................
CBUFF_CTX_CTRL_i ....................................................................................................
CBUFF_CTX_START_i ..................................................................................................
CBUFF_CTX_END_i .....................................................................................................
CBUFF_CTX_WINDOWSIZE_i .........................................................................................
CBUFF_CTX_THRESHOLD_F_i .......................................................................................
CBUFF_CTX_THRESHOLD_S_i .......................................................................................
CBUFF_CTX_STATUS_i ................................................................................................
CBUFF_CTX_PHY_i .....................................................................................................
ISS ISP Interrupt Tree Table ............................................................................................
ISS ISP VP Format Mapping ............................................................................................
ISS ISP VP GCK_MMR to PCLK Clock Resynchronization ........................................................
ISS CBUFF Window-Level Comparison
........................................................................
..............................................................
........................................................................
ISS ISP H3A Paxel Register Field Descriptions ......................................................................
ISS ISP H3A AE/AWB Window Register Field Descriptions ........................................................
ISS ISP H3A AE/AWB Window with Additional Black Row Register Field Descriptions ........................
ISS ISP H3A AF Packet Format With Vertical AF Disabled ........................................................
ISS ISP H3A AF Packet Format With Vertical AF Enabled .........................................................
ISS ISP H3A AE/AWB Packet Format for Sum of Square Mode...................................................
ISS ISP H3A AE/AWB Packet Format for Minimum-Maximum Mode .............................................
ISS ISP H3A AE/AWB Packet Format for Sum-Only Mode .........................................................
List of Tables
354
374
387
395
399
399
400
401
402
404
406
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
194
ISS ISP ISIF Input Interface Signals ................................................................................... 410
195
ISS ISP ISIF Data Input Formats ....................................................................................... 410
196
ISS ISP ISIF Raw Data Connection: Selects MSB Position of Input Data ........................................ 411
197
ISS ISP ISIF Linearization LUT ......................................................................................... 412
198
ISS ISP ISIF LUT Memory Region ..................................................................................... 412
199
ISS ISP ISIF Input Data Formatter Area Setting Registers ......................................................... 415
200
ISS ISP ISIF Output Data Formatter Area Setting Registers ....................................................... 415
201
ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line: Register Setting Example ....... 419
202
ISS ISP ISIF Vertical Line Defect Table in Memory .................................................................. 430
203
ISS ISP ISIF Supported On-the-Fly LSC Configurations ............................................................ 436
204
ISS ISP ISIF RAW Data Shifting........................................................................................ 443
205
ISS ISP ISIF SDRAM Data Format..................................................................................... 443
206
ISS ISP ISIF SDRAM Data Format for 12-bit Packed ............................................................... 443
207
ISS ISP ISIF Memory Output Format for YUV Data
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
.................................................................
ISP ISIF ISIF Module: Write Port Bandwidth ..........................................................................
ISS ISP ISIF Read Port Bandwidth.....................................................................................
ISS ISP BL cpriority to MFlag With ISP5_CTRL[21] MFLAG = 1 ..................................................
ISS ISP BL MFlag Write Low- and High-Level Priority Thresholds ................................................
ISS ISP BL MFlag Read Low- and High-Level Priority Thresholds ................................................
ISS ISP Memory Mapping for Cortex-M3 Private Access ...........................................................
ISS ISP Memory Mapping for L3 Interconnect Access ..............................................................
ISS ISP ISIF Required Configuration Parameters ....................................................................
ISS ISP ISIF Maximum Line Width Versus M Value .................................................................
ISS ISP IPIPEIF Required Configuration Parameters ...............................................................
ISS Global Initialization ..................................................................................................
ISS ISP IPIPE LUT Defect Pixel Correction (LUT DPC) ............................................................
ISS ISP IPIPE OTF Defect Pixel Correction (OTF DPC) ............................................................
ISS ISP IPIPE Noise Filter Initialization ................................................................................
ISS ISP IPIPE Green Imbalance Correction (GIC) Initialization ....................................................
ISS ISP IPIPE White Balance Initialization ............................................................................
ISS ISP IPIPE Color Filter Array (CFA) Interpolation Initialization .................................................
ISS ISP IPIPE RGB2RGB Blending Module Initialization ...........................................................
ISS ISP IPIPE Gamma Correction Module Initialization .............................................................
ISS ISP IPIPE 2nd RGB2RGB Conversion Matrix Initialization ....................................................
ISP IPIPE 3D-LUT Color Conversion Initialization ...................................................................
ISS ISP IPIPE RGB2YCbCr Conversion Matrix Initialization .......................................................
ISS ISP IPIPE Global Brightness and Contrast Enhancement Initialization ......................................
ISS ISP IPIPE 4:2:2 Conversion Module Initialization ...............................................................
ISS ISP IPIPE 2D Edge Enhancer Initialization ......................................................................
ISS ISP IPIPE Chroma Artifact Reduction Initialization..............................................................
ISS ISP IPIPE Chroma Gain Suppression Initialization .............................................................
ISS ISP IPIPE Histogram Initialization .................................................................................
ISS ISP IPIPE Boxcar Initialization .....................................................................................
ISS ISP IPIPE Boundary Signal Calculator Initialization.............................................................
ISS ISP IPIPE Processing Path: Case 1 Configuration..............................................................
ISS ISP IPIPE Processing Path: Case 2 Configuration..............................................................
ISS ISP IPIPE Processing Path: Case 3 Configuration..............................................................
ISS ISP IPIPE Processing Path: Case 4 Configuration..............................................................
ISS ISP RSZ Surrounding Modules Global Initialization.............................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
444
445
445
451
451
452
453
454
457
464
464
468
468
468
469
470
470
470
471
471
472
472
472
472
473
473
473
474
474
475
475
476
477
477
477
478
13
www.ti.com
243
ISS ISP RSZ Initial Register Setup ..................................................................................... 479
244
ISS ISP RSZ Reset Behavior ........................................................................................... 480
245
ISS ISP RSZ Global Image Processing Settings ..................................................................... 480
246
Register Call Summary for ISS ISP RSZ Global Image Processing Settings – Subsequence 1
247
248
484
484
485
249
Register Call Summary for ISS ISP RSZ Engines Interframe Image Processing Settings – Subsequence
1 ............................................................................................................................. 487
250
Register Call Summary for ISS ISP RSZ Engines Interframe Image Processing Settings – Subsequence
2 ............................................................................................................................. 487
251
ISS ISP RSZ Nonshadowed Registers ................................................................................ 488
252
ISS ISP H3A AF Engine Required Configuration Parameters ...................................................... 489
253
ISS ISP H3A AEW Engine Required Configuration Parameters ................................................... 490
254
ISS ISP H3A Constraints When PCLK ISP_FCLK/2 and Vertical Focus Enabled ............................... 492
255
ISS ISP H3A Constraints When PCLK ISP_FCLK/2 and Vertical Focus Disabled .............................. 492
256
ISS ISP H3A Constraints When PCLK = ISP_FCLK/2 and Vertical Focus Enabled
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
14
..............
Register Call Summary for ISS ISP RSZ Global Image Processing Settings – Subsequence 2 ..............
ISS ISP RSZ Engines Interframe Image Processing Settings ......................................................
............................
ISS ISP H3A Constraints When PCLK = ISP_FCLK/2 and Vertical Focus Disabled ............................
ISS ISP BL Settings ......................................................................................................
ISS ISP Instance Summary .............................................................................................
ISS ISP5 SYS1 Registers Mapping Summary ........................................................................
ISP5_REVISION ..........................................................................................................
ISP5_HWINFO1 ..........................................................................................................
ISP5_HWINFO2 ..........................................................................................................
ISP5_SYSCONFIG .......................................................................................................
ISP5_IRQSTATUS_RAW_i..............................................................................................
ISP5_IRQSTATUS_i .....................................................................................................
ISP5_IRQENABLE_SET_i ...............................................................................................
ISP5_IRQENABLE_CLR_i ..............................................................................................
ISP5_DMAENABLE_SET................................................................................................
ISP5_DMAENABLE_CLR ...............................................................................................
ISP5_CTRL ................................................................................................................
ISP5_MPSR ...............................................................................................................
ISP5_BL_MTC_1 .........................................................................................................
ISP5_BL_MTC_2 .........................................................................................................
ISP5_BL_VBUSM.........................................................................................................
ISS ISP5 SYS2 Registers Mapping Summary ........................................................................
ISP5_KEY_EN1 ...........................................................................................................
ISP5_KEY_EN2 ...........................................................................................................
ISP5_KEY_EN3 ...........................................................................................................
ISP5_KEY_EN4 ...........................................................................................................
ISP5_KEY_EN5 ...........................................................................................................
ISP5_KEY_EN6 ...........................................................................................................
ISP5_IRQSTATUS_RAW2_i ............................................................................................
ISP5_IRQSTATUS2_i ....................................................................................................
ISP5_IRQENABLE_SET2_i .............................................................................................
ISP5_IRQENABLE_CLR2_i .............................................................................................
ISS RESIZER Registers Mapping Summary ..........................................................................
RSZ_REVISION ..........................................................................................................
RSZ_SYSCONFIG .......................................................................................................
List of Tables
492
492
494
494
495
495
496
496
497
499
504
509
514
519
521
523
528
532
532
533
534
534
535
535
536
536
537
538
540
542
543
545
547
548
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
....................................................................................................
RSZ_GNC .................................................................................................................
RSZ_FRACDIV............................................................................................................
RSZ_SRC_EN ............................................................................................................
RSZ_SRC_MODE ........................................................................................................
RSZ_SRC_FMT0 .........................................................................................................
RSZ_SRC_FMT1 .........................................................................................................
RSZ_SRC_VPS ...........................................................................................................
RSZ_SRC_VSZ ...........................................................................................................
RSZ_SRC_HPS ...........................................................................................................
RSZ_SRC_HSZ ...........................................................................................................
RSZ_DMA_RZA ..........................................................................................................
RSZ_DMA_RZB ..........................................................................................................
RSZ_DMA_STA ...........................................................................................................
RSZ_GCK_MMR..........................................................................................................
RSZ_GCK_SDR ..........................................................................................................
RSZ_IRQ_RZA ............................................................................................................
RSZ_IRQ_RZB ............................................................................................................
RSZ_YUV_Y_MIN ........................................................................................................
RSZ_YUV_Y_MAX .......................................................................................................
RSZ_YUV_C_MIN ........................................................................................................
RSZ_YUV_C_MAX .......................................................................................................
RSZ_YUV_PHS ...........................................................................................................
RSZ_SEQ ..................................................................................................................
RZA_EN ....................................................................................................................
RZA_MODE ...............................................................................................................
RZA_420 ...................................................................................................................
RZA_I_VPS ................................................................................................................
RZA_I_HPS................................................................................................................
RZA_O_VSZ...............................................................................................................
RZA_O_HSZ ..............................................................................................................
RZA_V_PHS_Y ...........................................................................................................
RZA_V_PHS_C ...........................................................................................................
RZA_V_DIF ................................................................................................................
RZA_V_TYP ...............................................................................................................
RZA_V_LPF ...............................................................................................................
RZA_H_PHS ..............................................................................................................
RZA_H_PHS_ADJ ........................................................................................................
RZA_H_DIF................................................................................................................
RZA_H_TYP ...............................................................................................................
RZA_H_LPF ...............................................................................................................
RZA_DWN_EN ............................................................................................................
RZA_DWN_AV ............................................................................................................
RZA_RGB_EN ............................................................................................................
RZA_RGB_TYP ...........................................................................................................
RZA_RGB_BLD ...........................................................................................................
RZA_SDR_Y_BAD_H ....................................................................................................
RZA_SDR_Y_BAD_L ....................................................................................................
RZA_SDR_Y_SAD_H ....................................................................................................
RSZ_IN_FIFO_CTRL
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
549
550
550
551
552
553
554
555
555
556
556
557
557
558
558
559
560
560
561
561
562
562
563
564
565
565
566
567
567
568
568
569
569
570
570
571
571
572
572
573
573
574
575
576
577
578
578
579
580
15
www.ti.com
339
RZA_SDR_Y_SAD_L .................................................................................................... 581
340
RZA_SDR_Y_OFT
341
RZA_SDR_Y_PTR_S .................................................................................................... 582
342
RZA_SDR_Y_PTR_E .................................................................................................... 583
343
RZA_SDR_C_BAD_H .................................................................................................... 583
344
RZA_SDR_C_BAD_L .................................................................................................... 584
345
RZA_SDR_C_SAD_H .................................................................................................... 584
346
RZA_SDR_C_SAD_L .................................................................................................... 585
347
RZA_SDR_C_OFT ....................................................................................................... 585
348
RZA_SDR_C_PTR_S .................................................................................................... 586
349
RZA_SDR_C_PTR_E .................................................................................................... 586
350
RZB_EN .................................................................................................................... 587
351
RZB_MODE ............................................................................................................... 587
352
RZB_420 ................................................................................................................... 588
353
RZB_I_VPS ................................................................................................................ 589
354
RZB_I_HPS................................................................................................................ 589
355
RZB_O_VSZ............................................................................................................... 590
356
RZB_O_HSZ
357
RZB_V_PHS_Y ........................................................................................................... 591
358
RZB_V_PHS_C ........................................................................................................... 591
359
RZB_V_DIF ................................................................................................................ 592
360
RZB_V_TYP ............................................................................................................... 592
361
RZB_V_LPF ............................................................................................................... 593
362
RZB_H_PHS
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
16
.......................................................................................................
..............................................................................................................
..............................................................................................................
RZB_H_PHS_ADJ ........................................................................................................
RZB_H_DIF................................................................................................................
RZB_H_TYP ...............................................................................................................
RZB_H_LPF ...............................................................................................................
RZB_DWN_EN ............................................................................................................
RZB_DWN_AV ............................................................................................................
RZB_RGB_EN ............................................................................................................
RZB_RGB_TYP ...........................................................................................................
RZB_RGB_BLD ...........................................................................................................
RZB_SDR_Y_BAD_H ....................................................................................................
RZB_SDR_Y_BAD_L ....................................................................................................
RZB_SDR_Y_SAD_H ....................................................................................................
RZB_SDR_Y_SAD_L ....................................................................................................
RZB_SDR_Y_OFT .......................................................................................................
RZB_SDR_Y_PTR_S ....................................................................................................
RZB_SDR_Y_PTR_E ....................................................................................................
RZB_SDR_C_BAD_H ....................................................................................................
RZB_SDR_C_BAD_L ....................................................................................................
RZB_SDR_C_SAD_H ....................................................................................................
RZB_SDR_C_SAD_L ....................................................................................................
RZB_SDR_C_OFT .......................................................................................................
RZB_SDR_C_PTR_S ....................................................................................................
RZB_SDR_C_PTR_E ....................................................................................................
ISS IPIPE Registers Mapping Summary ..............................................................................
IPIPE_SRC_EN ...........................................................................................................
List of Tables
582
590
593
594
594
595
595
596
597
598
599
600
600
601
602
603
604
604
605
606
606
607
607
608
608
609
610
616
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
388
IPIPE_SRC_MODE....................................................................................................... 616
389
IPIPE_SRC_FMT ......................................................................................................... 617
390
IPIPE_SRC_COL ......................................................................................................... 618
391
IPIPE_SRC_VPS ......................................................................................................... 619
392
IPIPE_SRC_VSZ
393
IPIPE_SRC_HPS ......................................................................................................... 620
394
IPIPE_SRC_HSZ ......................................................................................................... 620
395
IPIPE_SEL_SBU .......................................................................................................... 621
396
IPIPE_SRC_STA
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
.........................................................................................................
.........................................................................................................
IPIPE_GCK_MMR ........................................................................................................
IPIPE_GCK_PIX ..........................................................................................................
IPIPE_DPC_LUT_EN ....................................................................................................
IPIPE_DPC_LUT_SEL ...................................................................................................
IPIPE_DPC_LUT_ADR ..................................................................................................
IPIPE_DPC_LUT_SIZ ....................................................................................................
IPIPE_DPC_OTF_EN ....................................................................................................
IPIPE_DPC_OTF_TYP...................................................................................................
IPIPE_DPC_OTF_2_D_THR_R ........................................................................................
IPIPE_DPC_OTF_2_D_THR_GR ......................................................................................
IPIPE_DPC_OTF_2_D_THR_GB ......................................................................................
IPIPE_DPC_OTF_2_D_THR_B ........................................................................................
IPIPE_DPC_OTF_2_C_THR_R ........................................................................................
IPIPE_DPC_OTF_2_C_THR_GR ......................................................................................
IPIPE_DPC_OTF_2_C_THR_GB ......................................................................................
IPIPE_DPC_OTF_2_C_THR_B ........................................................................................
IPIPE_DPC_OTF_3_SHF ...............................................................................................
IPIPE_DPC_OTF_3_D_THR ............................................................................................
IPIPE_DPC_OTF_3_D_SPL ............................................................................................
IPIPE_DPC_OTF_3_D_MIN ............................................................................................
IPIPE_DPC_OTF_3_D_MAX ...........................................................................................
IPIPE_DPC_OTF_3_C_THR ............................................................................................
IPIPE_DPC_OTF_3_C_SLP ............................................................................................
IPIPE_DPC_OTF_3_C_MIN ............................................................................................
IPIPE_DPC_OTF_3_C_MAX ...........................................................................................
IPIPE_LSC_VOFT ........................................................................................................
IPIPE_LSC_VA2 ..........................................................................................................
IPIPE_LSC_VA1 ..........................................................................................................
IPIPE_LSC_VS............................................................................................................
IPIPE_LSC_HOFT ........................................................................................................
IPIPE_LSC_HA2 ..........................................................................................................
IPIPE_LSC_HA1 ..........................................................................................................
IPIPE_LSC_HS ...........................................................................................................
IPIPE_LSC_GAN_R ......................................................................................................
IPIPE_LSC_GAN_GR ....................................................................................................
IPIPE_LSC_GAN_GB ....................................................................................................
IPIPE_LSC_GAN_B ......................................................................................................
IPIPE_LSC_OFT_R ......................................................................................................
IPIPE_LSC_OFT_GR ....................................................................................................
IPIPE_LSC_OFT_GB ....................................................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
619
621
622
623
624
624
625
625
626
626
627
627
628
628
629
629
630
630
631
631
632
632
633
633
634
634
635
635
636
636
637
637
638
638
639
639
640
640
641
641
642
642
17
www.ti.com
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
18
......................................................................................................
IPIPE_LSC_SHF ..........................................................................................................
IPIPE_LSC_MAX .........................................................................................................
IPIPE_D2F_1ST_EN .....................................................................................................
IPIPE_D2F_1ST_TYP....................................................................................................
IPIPE_D2F_1ST_THR_00 ...............................................................................................
IPIPE_D2F_1ST_THR_01 ...............................................................................................
IPIPE_D2F_1ST_THR_02 ...............................................................................................
IPIPE_D2F_1ST_THR_03 ...............................................................................................
IPIPE_D2F_1ST_THR_04 ...............................................................................................
IPIPE_D2F_1ST_THR_05 ...............................................................................................
IPIPE_D2F_1ST_THR_06 ...............................................................................................
IPIPE_D2F_1ST_THR_07 ...............................................................................................
IPIPE_D2F_1ST_STR_00 ...............................................................................................
IPIPE_D2F_1ST_STR_01 ...............................................................................................
IPIPE_D2F_1ST_STR_02 ...............................................................................................
IPIPE_D2F_1ST_STR_03 ...............................................................................................
IPIPE_D2F_1ST_STR_04 ...............................................................................................
IPIPE_D2F_1ST_STR_05 ...............................................................................................
IPIPE_D2F_1ST_STR_06 ...............................................................................................
IPIPE_D2F_1ST_STR_07 ...............................................................................................
IPIPE_D2F_1ST_EDG_MIN.............................................................................................
IPIPE_D2F_1ST_EDG_MAX ............................................................................................
IPIPE_D2F_2ND_EN .....................................................................................................
IPIPE_D2F_2ND_TYP ...................................................................................................
IPIPE_D2F_2ND_THR00 ................................................................................................
IPIPE_D2F_2ND_THR01 ................................................................................................
IPIPE_D2F_2ND_THR02 ................................................................................................
IPIPE_D2F_2ND_THR03 ................................................................................................
IPIPE_D2F_2ND_THR04 ................................................................................................
IPIPE_D2F_2ND_THR05 ................................................................................................
IPIPE_D2F_2ND_THR06 ................................................................................................
IPIPE_D2F_2ND_THR07 ................................................................................................
IPIPE_D2F_2ND_STR_00 ..............................................................................................
IPIPE_D2F_2ND_STR_01 ..............................................................................................
IPIPE_D2F_2ND_STR_02 ..............................................................................................
IPIPE_D2F_2ND_STR_03 ..............................................................................................
IPIPE_D2F_2ND_STR_04 ..............................................................................................
IPIPE_D2F_2ND_STR_05 ..............................................................................................
IPIPE_D2F_2ND_STR_06 ..............................................................................................
IPIPE_D2F_2ND_STR_07 ..............................................................................................
IPIPE_D2F_2ND_EDG_MIN ............................................................................................
IPIPE_D2F_2ND_EDG_MAX ...........................................................................................
IPIPE_GIC_EN ............................................................................................................
IPIPE_GIC_TYP ..........................................................................................................
IPIPE_GIC_GAN ..........................................................................................................
IPIPE_GIC_NFGAIN .....................................................................................................
IPIPE_GIC_THR ..........................................................................................................
IPIPE_GIC_SLP ..........................................................................................................
IPIPE_LSC_OFT_B
List of Tables
643
643
644
644
645
645
646
646
647
647
648
648
649
649
650
650
651
651
652
652
653
653
654
654
655
656
656
657
657
658
658
659
659
660
660
661
661
662
662
663
663
664
664
665
665
666
666
667
667
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
486
IPIPE_WB2_OFT_R ...................................................................................................... 668
487
IPIPE_WB2_OFT_GR.................................................................................................... 668
488
IPIPE_WB2_OFT_GB .................................................................................................... 669
489
IPIPE_WB2_OFT_B ...................................................................................................... 669
490
IPIPE_WB2_WGN_R
670
491
IPIPE_WB2_WGN_GR
670
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
....................................................................................................
..................................................................................................
IPIPE_WB2_WGN_GB...................................................................................................
IPIPE_WB2_WGN_B .....................................................................................................
IPIPE_CFA_MODE .......................................................................................................
IPIPE_CFA_2DIR_HPF_THR ...........................................................................................
IPIPE_CFA_2DIR_HPF_SLP ...........................................................................................
IPIPE_CFA_2DIR_MIX_THR ...........................................................................................
IPIPE_CFA_2DIR_MIX_SLP ............................................................................................
IPIPE_CFA_2DIR_DIR_TRH ............................................................................................
IPIPE_CFA_2DIR_DIR_SLP ............................................................................................
IPIPE_CFA_2DIR_NDWT ...............................................................................................
IPIPE_CFA_MONO_HUE_FRA ........................................................................................
IPIPE_CFA_MONO_EDG_THR ........................................................................................
IPIPE_CFA_MONO_THR_MIN .........................................................................................
IPIPE_CFA_MONO_THR_SLP .........................................................................................
IPIPE_CFA_MONO_SLP_MIN..........................................................................................
IPIPE_CFA_MONO_SLP_SLP .........................................................................................
IPIPE_CFA_MONO_LPWT..............................................................................................
IPIPE_RGB1_MUL_RR ..................................................................................................
IPIPE_RGB1_MUL_GR ..................................................................................................
IPIPE_RGB1_MUL_BR ..................................................................................................
IPIPE_RGB1_MUL_RG ..................................................................................................
IPIPE_RGB1_MUL_GG ..................................................................................................
IPIPE_RGB1_MUL_BG ..................................................................................................
IPIPE_RGB1_MUL_RB ..................................................................................................
IPIPE_RGB1_MUL_GB ..................................................................................................
IPIPE_RGB1_MUL_BB ..................................................................................................
IPIPE_RGB1_OFT_OR ..................................................................................................
IPIPE_RGB1_OFT_OG ..................................................................................................
IPIPE_RGB1_OFT_OB ..................................................................................................
IPIPE_GMM_CFG ........................................................................................................
IPIPE_RGB2_MUL_RR ..................................................................................................
IPIPE_RGB2_MUL_GR ..................................................................................................
IPIPE_RGB2_MUL_BR ..................................................................................................
IPIPE_RGB2_MUL_RG ..................................................................................................
IPIPE_RGB2_MUL_GG ..................................................................................................
IPIPE_RGB2_MUL_BG ..................................................................................................
IPIPE_RGB2_MUL_RB ..................................................................................................
IPIPE_RGB2_MUL_GB ..................................................................................................
IPIPE_RGB2_MUL_BB ..................................................................................................
IPIPE_RGB2_OFT_OR ..................................................................................................
IPIPE_RGB2_OFT_OG ..................................................................................................
IPIPE_RGB2_OFT_OB ..................................................................................................
IPIPE_3DLUT_EN ........................................................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
671
671
672
672
673
673
674
674
675
675
676
676
677
677
678
678
679
679
680
680
681
681
682
682
683
683
684
684
685
686
687
687
688
688
689
689
690
690
691
691
692
692
693
19
www.ti.com
535
IPIPE_YUV_ADJ .......................................................................................................... 693
536
IPIPE_YUV_MUL_RY .................................................................................................... 694
537
IPIPE_YUV_MUL_GY .................................................................................................... 694
538
IPIPE_YUV_MUL_BY .................................................................................................... 695
539
IPIPE_YUV_MUL_RCB .................................................................................................. 695
540
IPIPE_YUV_MUL_GCB .................................................................................................. 696
541
IPIPE_YUV_MUL_BCB .................................................................................................. 696
542
IPIPE_YUV_MUL_RCR .................................................................................................. 697
543
IPIPE_YUV_MUL_GCR .................................................................................................. 697
544
IPIPE_YUV_MUL_BCR .................................................................................................. 698
545
IPIPE_YUV_OFT_Y ...................................................................................................... 698
546
IPIPE_YUV_OFT_CB .................................................................................................... 699
547
IPIPE_YUV_OFT_CR .................................................................................................... 699
548
IPIPE_YUV_PHS ......................................................................................................... 700
549
IPIPE_GBCE_EN ......................................................................................................... 701
550
IPIPE_GBCE_TYP
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
20
.......................................................................................................
IPIPE_YEE_EN ...........................................................................................................
IPIPE_YEE_TYP ..........................................................................................................
IPIPE_YEE_SHF..........................................................................................................
IPIPE_YEE_MUL_00 .....................................................................................................
IPIPE_YEE_MUL_01 .....................................................................................................
IPIPE_YEE_MUL_02 .....................................................................................................
IPIPE_YEE_MUL_10 .....................................................................................................
IPIPE_YEE_MUL_11 .....................................................................................................
IPIPE_YEE_MUL_12 .....................................................................................................
IPIPE_YEE_MUL_20 .....................................................................................................
IPIPE_YEE_MUL_21 .....................................................................................................
IPIPE_YEE_MUL_22 .....................................................................................................
IPIPE_YEE_THR .........................................................................................................
IPIPE_YEE_E_GAN ......................................................................................................
IPIPE_YEE_E_THR_1 ...................................................................................................
IPIPE_YEE_E_THR_2 ...................................................................................................
IPIPE_YEE_G_GAN......................................................................................................
IPIPE_YEE_G_OFT ......................................................................................................
IPIPE_CAR_EN ...........................................................................................................
IPIPE_CAR_TYP .........................................................................................................
IPIPE_CAR_SW ..........................................................................................................
IPIPE_CAR_HPF_TYP...................................................................................................
IPIPE_CAR_HPF_SHF ..................................................................................................
IPIPE_CAR_HPF_THR ..................................................................................................
IPIPE_CAR_GN1_GAN ..................................................................................................
IPIPE_CAR_GN1_SHF ..................................................................................................
IPIPE_CAR_GN1_MIN ...................................................................................................
IPIPE_CAR_GN2_GAN ..................................................................................................
IPIPE_CAR_GN2_SHF ..................................................................................................
IPIPE_CAR_GN2_MIN ...................................................................................................
IPIPE_CGS_EN ...........................................................................................................
IPIPE_CGS_GN1_L_THR ...............................................................................................
IPIPE_CGS_GN1_L_GAIN ..............................................................................................
List of Tables
702
702
703
703
704
704
705
705
706
706
707
707
708
708
709
709
710
710
711
711
712
712
713
713
714
714
715
715
716
716
717
717
718
718
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
584
IPIPE_CGS_GN1_L_SHF ............................................................................................... 719
585
IPIPE_CGS_GN1_L_MIN................................................................................................ 719
586
IPIPE_CGS_GN1_H_THR
720
587
IPIPE_CGS_GN1_H_GAIN
720
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
..............................................................................................
.............................................................................................
IPIPE_CGS_GN1_H_SHF ...............................................................................................
IPIPE_CGS_GN1_H_MIN ...............................................................................................
IPIPE_CGS_GN2_L_THR ...............................................................................................
IPIPE_CGS_GN2_L_GAIN ..............................................................................................
IPIPE_CGS_GN2_L_SHF ...............................................................................................
IPIPE_CGS_GN2_L_MIN................................................................................................
IPIPE_BOX_EN ...........................................................................................................
IPIPE_BOX_MODE.......................................................................................................
IPIPE_BOX_TYP .........................................................................................................
IPIPE_BOX_SHF .........................................................................................................
IPIPE_BOX_SDR_SAD_H ..............................................................................................
IPIPE_BOX_SDR_SAD_L ...............................................................................................
IPIPE_HST_EN ...........................................................................................................
IPIPE_HST_MODE .......................................................................................................
IPIPE_HST_SEL ..........................................................................................................
IPIPE_HST_PARA ........................................................................................................
IPIPE_HST_0_VPS.......................................................................................................
IPIPE_HST_0_VSZ .......................................................................................................
IPIPE_HST_0_HPS ......................................................................................................
IPIPE_HST_0_HSZ.......................................................................................................
IPIPE_HST_1_VPS.......................................................................................................
IPIPE_HST_1_VSZ .......................................................................................................
IPIPE_HST_1_HPS ......................................................................................................
IPIPE_HST_1_HSZ.......................................................................................................
IPIPE_HST_2_VPS.......................................................................................................
IPIPE_HST_2_VSZ .......................................................................................................
IPIPE_HST_2_HPS ......................................................................................................
IPIPE_HST_2_HSZ.......................................................................................................
IPIPE_HST_3_VPS.......................................................................................................
IPIPE_HST_3_VSZ .......................................................................................................
IPIPE_HST_3_HPS ......................................................................................................
IPIPE_HST_3_HSZ.......................................................................................................
IPIPE_HST_TBL ..........................................................................................................
IPIPE_HST_MUL_R ......................................................................................................
IPIPE_HST_MUL_GR ....................................................................................................
IPIPE_HST_MUL_GB ....................................................................................................
IPIPE_HST_MUL_B ......................................................................................................
IPIPE_BSC_EN ...........................................................................................................
IPIPE_BSC_MODE .......................................................................................................
IPIPE_BSC_TYP..........................................................................................................
IPIPE_BSC_ROW_VCT .................................................................................................
IPIPE_BSC_ROW_SHF .................................................................................................
IPIPE_BSC_ROW_VPOS ...............................................................................................
IPIPE_BSC_ROW_VNUM ...............................................................................................
IPIPE_BSC_ROW_VSKIP ...............................................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
721
721
722
722
723
723
724
724
725
725
726
726
727
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
747
748
748
749
749
750
751
751
752
752
753
21
www.ti.com
633
IPIPE_BSC_ROW_HPOS ............................................................................................... 753
634
IPIPE_BSC_ROW_HNUM ............................................................................................... 754
635
IPIPE_BSC_ROW_HSKIP ............................................................................................... 754
636
IPIPE_BSC_COL_VCT
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
22
..................................................................................................
IPIPE_BSC_COL_SHF ..................................................................................................
IPIPE_BSC_COL_VPOS ................................................................................................
IPIPE_BSC_COL_VNUM ................................................................................................
IPIPE_BSC_COL_VSKIP ................................................................................................
IPIPE_BSC_COL_HPOS ................................................................................................
IPIPE_BSC_COL_HNUM ................................................................................................
IPIPE_BSC_COL_HSKIP ................................................................................................
ISS ISIF Registers Mapping Summary ................................................................................
ISIF_SYNCEN.............................................................................................................
ISIF_MODESET ..........................................................................................................
ISIF_HDW .................................................................................................................
ISIF_VDW..................................................................................................................
ISIF_PPLN .................................................................................................................
ISIF_LPFR .................................................................................................................
ISIF_SPH ..................................................................................................................
ISIF_LNH ..................................................................................................................
ISIF_LNV...................................................................................................................
ISIF_CULH ................................................................................................................
ISIF_CULV .................................................................................................................
ISIF_HSIZE ................................................................................................................
ISIF_CADU ................................................................................................................
ISIF_CADL .................................................................................................................
ISIF_LINCFG0 ............................................................................................................
ISIF_LINCFG1 ............................................................................................................
ISIF_CCOLP...............................................................................................................
ISIF_CRGAIN .............................................................................................................
ISIF_CGRGAIN ...........................................................................................................
ISIF_CGBGAIN ...........................................................................................................
ISIF_CBGAIN .............................................................................................................
ISIF_COFSTA .............................................................................................................
ISIF_VDINT0 ..............................................................................................................
ISIF_VDINT1 ..............................................................................................................
ISIF_VDINT2 ..............................................................................................................
ISIF_MISC .................................................................................................................
ISIF_CGAMMAWD .......................................................................................................
ISIF_REC656IF ...........................................................................................................
ISIF_CCDCFG ............................................................................................................
ISIF_DFCCTL .............................................................................................................
ISIF_VDFSATLV ..........................................................................................................
ISIF_DFCMEMCTL .......................................................................................................
ISIF_DFCMEM0 ..........................................................................................................
ISIF_DFCMEM1 ..........................................................................................................
ISIF_DFCMEM2 ..........................................................................................................
ISIF_DFCMEM3 ..........................................................................................................
ISIF_DFCMEM4 ..........................................................................................................
List of Tables
755
755
756
756
757
757
758
758
759
762
763
765
765
766
766
767
767
768
768
769
770
771
771
772
773
774
776
776
777
777
778
779
779
780
780
781
782
783
785
786
787
788
788
789
789
790
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
682
ISIF_CLAMPCFG ......................................................................................................... 791
683
ISIF_CLDCOFST ......................................................................................................... 792
684
ISIF_CLSV ................................................................................................................. 792
685
ISIF_CLHWIN0 ............................................................................................................ 793
686
ISIF_CLHWIN1 ............................................................................................................ 794
687
ISIF_CLHWIN2 ............................................................................................................ 794
688
ISIF_CLVRV ............................................................................................................... 795
689
ISIF_CLVWIN0 ............................................................................................................ 796
690
ISIF_CLVWIN1 ............................................................................................................ 797
691
ISIF_CLVWIN2 ............................................................................................................ 797
692
ISIF_CLVWIN3 ............................................................................................................ 798
693
ISIF_LSCHOFST
694
ISIF_LSCVOFST.......................................................................................................... 799
695
..............................................................................................................................
ISIF_LSCVVAL ............................................................................................................
ISIF_2DLSCCFG .........................................................................................................
ISIF_2DLSCOFST ........................................................................................................
ISIF_2DLSCINI ............................................................................................................
ISIF_2DLSCGRBU .......................................................................................................
ISIF_2DLSCGRBL ........................................................................................................
ISIF_2DLSCGROF .......................................................................................................
ISIF_2DLSCORBU .......................................................................................................
ISIF_2DLSCORBL ........................................................................................................
ISIF_2DLSCOROF .......................................................................................................
ISIF_2DLSCIRQEN.......................................................................................................
ISIF_2DLSCIRQST .......................................................................................................
ISIF_FMTCFG.............................................................................................................
ISIF_FMTPLEN ...........................................................................................................
ISIF_FMTSPH .............................................................................................................
ISIF_FMTLNH .............................................................................................................
ISIF_FMTLSV .............................................................................................................
ISIF_FMTLNV .............................................................................................................
ISIF_FMTRLEN ...........................................................................................................
ISIF_FMTHCNT ...........................................................................................................
ISIF_FMTAPTR0..........................................................................................................
ISIF_FMTAPTR1..........................................................................................................
ISIF_FMTAPTR2..........................................................................................................
ISIF_FMTAPTR3..........................................................................................................
ISIF_FMTAPTR4..........................................................................................................
ISIF_FMTAPTR5..........................................................................................................
ISIF_FMTAPTR6..........................................................................................................
ISIF_FMTAPTR7..........................................................................................................
ISIF_FMTAPTR8..........................................................................................................
ISIF_FMTAPTR9..........................................................................................................
ISIF_FMTAPTR10 ........................................................................................................
ISIF_FMTAPTR11 ........................................................................................................
ISIF_FMTAPTR12 ........................................................................................................
ISIF_FMTAPTR13 ........................................................................................................
ISIF_FMTAPTR14 ........................................................................................................
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
.........................................................................................................
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
799
800
800
801
803
804
805
805
806
806
807
807
808
809
811
812
813
813
814
814
815
815
816
816
817
817
818
818
819
819
820
820
821
821
822
822
823
23
www.ti.com
731
ISIF_FMTAPTR15 ........................................................................................................ 823
732
ISIF_FMTPGMVF0 ....................................................................................................... 824
733
ISIF_FMTPGMVF1 ....................................................................................................... 826
734
ISIF_FMTPGMAPU0 ..................................................................................................... 828
735
ISIF_FMTPGMAPU1 ..................................................................................................... 830
736
ISIF_FMTPGMAPS0 ..................................................................................................... 832
737
ISIF_FMTPGMAPS1 ..................................................................................................... 832
738
ISIF_FMTPGMAPS2 ..................................................................................................... 833
739
ISIF_FMTPGMAPS3 ..................................................................................................... 833
740
ISIF_FMTPGMAPS4 ..................................................................................................... 834
741
ISIF_FMTPGMAPS5 ..................................................................................................... 834
742
ISIF_FMTPGMAPS6 ..................................................................................................... 835
743
ISIF_FMTPGMAPS7 ..................................................................................................... 835
744
ISIF_CSCCTL ............................................................................................................. 836
745
ISIF_CSCM0
837
746
ISIF_CSCM1
837
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
24
..............................................................................................................
..............................................................................................................
ISIF_CSCM2 ..............................................................................................................
ISIF_CSCM3 ..............................................................................................................
ISIF_CSCM4 ..............................................................................................................
ISIF_CSCM5 ..............................................................................................................
ISIF_CSCM6 ..............................................................................................................
ISIF_CSCM7 ..............................................................................................................
ISIF_CLKCTL .............................................................................................................
ISS IPIPEIF Registers Mapping Summary ............................................................................
IPIPEIF_ENABLE .........................................................................................................
IPIPEIF_CFG1 ............................................................................................................
IPIPEIF_PPLN ............................................................................................................
IPIPEIF_LPFR.............................................................................................................
IPIPEIF_HNUM ...........................................................................................................
IPIPEIF_VNUM............................................................................................................
IPIPEIF_ADDRU ..........................................................................................................
IPIPEIF_ADDRL ..........................................................................................................
IPIPEIF_ADOFS ..........................................................................................................
IPIPEIF_RSZ ..............................................................................................................
IPIPEIF_GAIN .............................................................................................................
IPIPEIF_DPCM............................................................................................................
IPIPEIF_CFG2 ............................................................................................................
IPIPEIF_INIRSZ ...........................................................................................................
IPIPEIF_OCLIP ...........................................................................................................
IPIPEIF_DTUDF ..........................................................................................................
IPIPEIF_CLKDIV ..........................................................................................................
IPIPEIF_DPC1 ............................................................................................................
IPIPEIF_DPC2 ............................................................................................................
IPIPEIF_RSZ3A ...........................................................................................................
IPIPEIF_INIRSZ3A .......................................................................................................
ISS H3A Registers Mapping Summary ................................................................................
H3A_PID ...................................................................................................................
H3A_PCR ..................................................................................................................
H3A_AFPAX1 .............................................................................................................
List of Tables
838
838
839
839
840
840
841
842
843
844
846
846
847
847
848
848
849
849
850
850
851
853
853
854
854
855
855
856
857
858
859
860
862
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
www.ti.com
780
H3A_AFPAX2 ............................................................................................................. 863
781
H3A_AFPAXSTART ...................................................................................................... 864
782
H3A_AFIIRSH ............................................................................................................. 865
783
H3A_AFBUFST ........................................................................................................... 865
784
H3A_AFCOEF010 ........................................................................................................ 866
785
H3A_AFCOEF032 ........................................................................................................ 866
786
H3A_AFCOEF054 ........................................................................................................ 867
787
H3A_AFCOEF076 ........................................................................................................ 867
788
H3A_AFCOEF098 ........................................................................................................ 868
789
H3A_AFCOEF0010....................................................................................................... 868
790
H3A_AFCOEF110 ........................................................................................................ 869
791
H3A_AFCOEF132 ........................................................................................................ 869
792
H3A_AFCOEF154 ........................................................................................................ 870
793
H3A_AFCOEF176 ........................................................................................................ 870
794
H3A_AFCOEF198 ........................................................................................................ 871
795
H3A_AFCOEF1010....................................................................................................... 871
796
H3A_AEWWIN1 ........................................................................................................... 872
797
H3A_AEWINSTART ...................................................................................................... 873
798
H3A_AEWINBLK.......................................................................................................... 874
799
H3A_AEWSUBWIN....................................................................................................... 875
800
H3A_AEWBUFST......................................................................................................... 875
801
H3A_AEWCFG ............................................................................................................ 876
802
H3A_LINE_START ....................................................................................................... 877
803
H3A_VFV_CFG1.......................................................................................................... 878
804
H3A_VFV_CFG2.......................................................................................................... 878
805
H3A_VFV_CFG3.......................................................................................................... 879
806
H3A_VFV_CFG4.......................................................................................................... 879
807
H3A_HVF_THR ........................................................................................................... 880
808
H3A_ADVANCED......................................................................................................... 880
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
List of Tables
25
Preface
SPRUHL6A – January 2013 – Revised June 2016
Read This First
About This Manual
This document describes the operation of the Imaging Subsystem (ISS) in the DM38x and
TMS320DM8127 DaVinci™ Digital Media Processor.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for the
properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing non-default values to the Reserved bits could cause unexpected behavior and should be
avoided.
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For product information, visit the Texas Instruments website at http://www.ti.com.
SPRS821 — DM385 and DM388 DaVinci™ Digital Media Processor
SPRS712 — TMS320DM8127 DaVinci™ Video Processor
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community— TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore
ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster innovation
and growth of general knowledge about the hardware and software surrounding these devices.
26
Preface
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
SPRUHL6A – January 2013 – Revised June 2016
Imaging Subsystem (ISS)
1
ISS Overview
The imaging subsystem (ISS) deals with the processing of the pixel data coming from an external image
sensor, data from memory (image format encoding and decoding can be done to and from memory), or
data from SL2 in IVA-HD for hardware encoding. With its subparts, such as interfaces and interconnects,
image signal processor (ISP), and still image coprocessor (SIMCOP), the ISS is a key component for the
following multimedia applications: camera viewfinder, video record, and still image capture. Figure 1
shows an overview of the ISS.
Figure 1. ISS Overview
CSI2
protocol engine
A
LDC LUT
512 bytes
LDC
2x
4MAC iMX
COEFF b
16KB
IBUFF
#a
IBUFF
#b
IBUFF
#nn
4x512x16b
IBUFF
4x512x16b
4x512x16b
4x512x16b
IBUFF
#a
IBUFF
#b
IBUFF
#nn
4x512x16b
IBUFF
4x512x16b
4x512x16b
4x512x16b
CMD b
8KB
IPIPEIF
COEFF a
16KB
ISIF
CMD a
4KB
H3A
Bitstream
2KB
Huffman
4KB
DMA
HW SEQ
Slave interface
VBUS
Buffer logic
Slave port
Master port
Cortex-M3
Quant
512 bytes
IPIPE
General purpose or image
VLCD
ISP
RSZ2
DCT
CPI
Stall control for M2M operation
ROT
Interconnect
NSF2
Stall Control
VP
TCTRL
RSZ1
Imaging subsystem
VBUS2OCP
ISS interconnect (128b)
Burst translation engine
ISS top-level resources
Circular buffer and BW control
Bridge
Master interface
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Bridge
Slave interface
Imaging Subsystem (ISS)
27
ISS Overview
www.ti.com
The direction of the arrows shows the command flow direction from the master (initiator) to the slave
(target). The following color conventions are used for the connections:
• Blue: Bidirectional, 128-bit-wide interface data connection
• Green: Write (ISS → system memory) data connection. Either 64-bit interface, 128-bit interface, or 32bit MTC (inside ISP5).
• Red: Read (system memory → ISS) data connection. 128-bit interface port or 32-bit MTC (inside
ISP5).
• Gray: 32-bit interface configuration connection
• Solid black: Video port and camera interface related signals
• Dotted black: Data flow stall control signal. Used to slow down ISP for memory-to-memory operation.
The ISS is mainly composed of a CSI2-A camera interface, a parallel interface (CPI), an ISP, and a blockbased imaging accelerator (SIMCOP).
The ISS is designed to reach high throughput and low latency with large image sensors. In highperformance mode, the ISS supports a pixel throughput of 200 MPix/s.
The ISS is tightly coupled with a low-interrupt latency microprocessor unit (MPU) subsystem (Cortex™-M3
MPU) that runs a real-time operating system (OS) to reach optimal performance. Mainly, the Cortex-M3
MPU can quickly change the ISS configuration during frame blanking periods and run some sequencing
tasks.
The ISS targets the following major use cases:
• Viewfinder with digital zoom, video stabilization, and rotations
• Up to 1080p video record at 30 fps with digital zoom, video stabilization, and rotation
• Up to 16 MPix still image capture with digital zoom and rotation
– High performance mode: Up to 200 MPix/s throughput
– High quality and low light modes: Up to 50 MPix/s throughput
• Still image capture during video record
NOTE: The ISS is not limited to 16 Mpix. Higher resolution can be achieved through multiple
passes.
NOTE: For a detailed list of features of a certain submodule, see the related subsection.
The ISS offers the following features:
• SIMCOP:
– Memory-to-memory operation
– JPEG encode and decode hardware acceleration
– High-ISO noise filtering (NSF 2.0)
– Rotation accelerator
– Warping accelerator
– Lens distortion correction (YUV space)
• ISP:
– On-the-fly or memory-to-memory processing
– Up to 200-MHz pixel throughput
– Statistic data collection
– Image pipe interface front-end raw data processing
– RGB and YUV data processing through ISIF and IPIPE
– Hardware 3A (H3A) statistics block for real-time auto focus (AF), auto exposure (AE), and auto
white balance (AWB)
28
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
•
•
– Two image continuous real-time resizers
– Video port (VP) for interfacing with the receivers and directing data to the ISP
ISS interfaces:
– 128-bit-wide data interface to the level 3 (L3) interconnect
– Burst translation engine (BTE) tightly coupled with the TILER to support efficient rotation
– Circular buffer for linear space, physically located in memory
– The ISS relies on the centralized memory management unit (MMU).
– CSI2 camera interface
– Parallel interface (CPI) (16-bit wide, with up to 162 MPix/s throughput, and supporting BT656,
SYNC modes)
– System memory data read-back port (supported by the stall controller (SC) module)
ISS interconnect:
– 128-bit-wide network for image data (full speed)
– 32-bit-wide network for configuration (half speed)
– Hard and soft real-time data flows
– CSI2-A, CPI, ISP, and SIMCOP data flow management
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
29
ISS Overview
1.1
www.ti.com
ISS Integration
This section describes the integration of the module in the device, including information about clocks,
resets, and hardware requests. Figure 2 shows the ISS integration.
Figure 2. ISS Integration
CSI2
CPIOIF
VS
CSI2-A
complex I/O
HS
DATA [15:0]
PCLK
WEN
FLD
Shutter
Strobe
GlobalReset
Device
DSP
ISS_IRQ[4]
CAM_RST
Standby protocol
D_IRQ[56]
CAM_RESET
Idle protocol
PRCM
ISS_CLK
MPU_M3_ISS_CLK
CAM_PHY_CTRL_CLK
FUNC_96M_FCLK
ISS_FCLK
CAM_PHY_CTRL_FCLK
EDMA
ISS_DMA[3:0]
Imaging subsystem
ASYNC
ISS_IRQ[5]
MM_IRQ[24]
Slave interface
ASYNC
32-bit
config. line
ISS_IRQ[5:0]
Master interface
ASYNC
Disconnect
sconnect
protocol
Disconnect
protocol
128-bit
data line
64 bits
MM_IRQ[16:11]
Cortex-A8
MPU
subsystem
32-bit master
interface
sconne
Disconnect
protocol
Cortex-M3
MPU
subsystem
S_DMA[12, 11, 9, 8]
ASYNC
L3 interconnect
TILER and
EMIF
IVA-HD
shared L2
SDRAM
NOTE: For more information about the IDLE hardware handshake and wake-up request, see section
Clock Management, in chapter, Power, Reset, and Clock Management.
This section gives an overview of typical uses of the module. For more information about the
relationship of the power, reset, and clock management (PRCM) module to the ISS clocks
and the reset settings, see the detailed functional description in the Power, Reset, and Clock
Management chapter of the TRM.
The ISS is part of ISS hardware and power management, which comprises the Cortex-M3 MPU, ISS, and
a clock generator. These are all independent power domains. The ISS is part of the CAM power domain.
The PRCM module provides a single clock (MPU_M3_ISS_CLK) to ISS power management. This clock
generates the clocks for the Cortex-M3 MPU, ISS, and the bridges to L3.
The ISS also supports software reset. A software reset has the same function as a hardware reset except
that it does not reset the power-management protocols.
30
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
When enabled, MPU_M3_ISS_CLK is gated to provide ISS_CLK, which, after entering the ISS boundary,
is named ISS_FCLK. MPU_M3_ISS_CLK is provided as long as the Cortex-M3 MPU or ISS modules
within the ISS require it.
CAM_PHY_CTRL_CLK is gated from FUNC_96M_FCLK, which comes from the PRCM module. When
enabled and inside the ISS boundary, it is called CAM_PHY_CTRL_FCLK.
NOTE: For more information about the device clocks and how they are handled by the PRCM
module before going into the ISS, see CM2 Clock Generator in the Power, Reset, and Clock
Management chapter of the TRM.
Table 1. ISS Integration Attributes
Attributes
Module Instance
ISS
Power Domain
Wake-Up Capability
PD_CAM
No
Interconnect
Table 2. ISS Clocks and Resets
Clocks
Module
Instance
ISS
Destination Signal
Name
Source Signal
Name
Source
Description
ISS_FLCK
ISS_CLK
PRCM
ISS global functional clock from the PRCM
module
CAM_PHY_CTRL_
FCLK
CAM_PHY_
CTRL_CLK
PRCM
Physical layer functional clock from the
PRCM module
Destination Signal
Name
Source Signal
Name
Source
Description
CAM_RESET
CAM_RST
PRCM
ISS global reset
Resets
Module
Instance
ISS
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
31
ISS Overview
www.ti.com
Table 3. ISS Hardware Requests
Interrupt Requests
Module
Instance
Source Signal Name
ISS
Destination
Signal Name
Destination
Description
ISS_IRQ4
D_IRQ_56
DSP INTC
ISS_IRQ5
MM_IRQ_24
Cortex-A8 INTC
Interrupt generated by ISS to DSP
Interrupt generated by ISS to Cortex-A8
ISS_IRQ0
MM_IRQ_11
Cortex-M3 INTC
Interrupt generated by ISS to Cortex-M3
ISS_IRQ1
MM_IRQ_12
Cortex-M3 INTC
Interrupt generated by ISS to Cortex-M3
ISS_IRQ2
MM_IRQ_13
Cortex-M3 INTC
Interrupt generated by ISS to Cortex-M3
ISS_IRQ3
MM_IRQ_14
Cortex-M3 INTC
Interrupt generated by ISS to Cortex-M3
ISS_IRQ4
MM_IRQ_15
Cortex-M3 INTC
Interrupt generated by ISS to Cortex-M3
ISS_IRQ5
MM_IRQ_16
Cortex-M3 INTC
Interrupt generated by ISS to Cortex-M3
DMA Requests
Module
Instance
Source Signal Name
Destination
Signal Name
Destination
ISS_DMA0
S_DMA_8
EDMA
Signal connected
provided by ISP.
to
the
EDMA
directly
ISS_DMA1
S_DMA_9
EDMA
Signal connected
provided by ISP
to
the
EDMA
directly
ISS_DMA2
S_DMA_11
EDMA
Signal connected
provided by ISP
to
the
EDMA
directly
ISS_DMA3
S_DMA_12
EDMA
Signal connected
provided by ISP
to
the
EDMA
directly
ISS
1.1.1
Description
ISS PRCM Interface Integration
1.1.1.1
ISS Clock Domains
The ISS has five asynchronous clock domains. Most of the logic uses ISS_FCLK; the other clock domains
are used for interfaces.
Table 4 provides a high-level view of clocks.
Table 4. ISS Local Clock Domains
Name
Description
PCLK
Parallel interface (CPI) pixel clock provided by the camera external sensor. The CSI2-A and SC
modules also have video port outputs, each having its own pixel clock. These pixel clocks are
generated from the functional clock (ISS_FCLK). Then all three pixel clock sources are multiplexed
into one clock provided to the ISP.
CSI2_A_BC
Byte clock provided by the CSI2-A complex I/O. Used by the CSI2-A receiver.
ISS_FCLK
Functional clock provided by ISS_CLK from the PRCM module. It is used by all ISS submodules and
ISS top-level resources.
CAM_PHY_CTRL_FCLK
Functional clock provided by the PRCM module. It is used by the CSI2-A complex I/Os.
To save power, the ISS can divide the received functional clock (ISS_CLK) by 2 or 4 from Figure 13, [4:5]
ISS_CLK_DIV. The configuration clock is always half the functional clock.
The functional clock of some submodules can be cut by software to reduce power consumption by cutting
off or turning on the modules from the Figure 14 . Also, the pixel clocks sent by submodules to ISP can be
cut off from Figure 14, VPORTx_CLK.
32
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.2
ISS Functional Description
This section provides only a top-level overview of the ISS. The ISS submodules are described in:
ISS:SIMCOP,ISS:Interfaces, and ISS:ISP.
Section 1.2.1 describes the ISS power-management mechanisms and gives an introduction to and a
functional description of the ISP submodules.
1.2.1
ISS Interrupts
Section 1.2.1.2 lists the events generated by the submodules and the top level of the ISS.
Each event that generates an interrupt can be individually enabled by setting the appropriate bit in the
ISS_HL_IRQENABLE_SET_i register. The interrupt is disabled by setting the appropriate bit in the
ISS_HL_IRQENABLE_CLR_i register.
When an event occurs, the corresponding bit in the ISS_HL_IRQSTATUS_RAW_i register is set
regardless of whether or not the event is enabled. Bits in the ISS_HL_IRQSTATUS_i registers are set only
when an enabled event occurs.
Software can clear a pending HS_VS_IRQ event by setting the ISS_HL_IRQSTATUS_i [17] HS_VS_IRQ
bit. Events generated by submodules are automatically cleared at the ISS level when they are cleared at
the submodule level.
1.2.1.1
ISS Interrupt Merger
The ISS merges the following eight interrupt sources into six physical interrupt lines. All six lines support
level and pulse modes.
Table 5. ISS Interrupts
Interrupt
Source
Description
ISP_IRQ[3:0]
ISP
Interrupt generated by the ISP
CSIA_IRQ
CSI2-A
Interrupt generated by the CSI2-A receiver (1)
SC_IRQ[8]
SC
Interrupt generated by the SC receiver (1)
CBUFF_IRQ
CBUFF
Interrupt generated by the circular buffer (1)
BTE_IRQ
BTE
Interrupt generated by the BTE
SIMCOP_IRQ[3:0]
SIMCOP
Interrupt generated by SIMCOP
HS_VS_IRQ
ISS
HS or VS synchronization event.
This event is triggered if a rising or falling edge is detected on the HS or VS
signal. The rising or falling edge and the HS or VS signal selection are chosen
using the ISP_CTRL[0:1] SYNC_DETECT bit field.
(1)
(1)
(1)
For more information, see Section 1.2.1.2.
Software can select which interrupt sources are routed to each output line (ISS_IRQ[0:5]). All six physical
interrupt outputs have equivalent functions. Software can use different interrupt lines to group events
together by type and therefore reduce interrupt latencies. Typically, one interrupt line is used for lowpriority events (errors), and the other interrupt lines are used for high-priority events (for example,
SIMCOP sequencing and end-of-frame events to trigger configuration load). The ISS internal interrupt
request (IRQ) merger (see Figure 3) relies only on level interrupts provided by submodules. Pulse
interrupts provided by submodules are ignored. Typically, all of the interrupts are routed to the Cortex-M3
running the camera driver. In addition, one interrupt is routed to Cortex-A8, which may run the imaging
software. Software does not need to clear events from submodules at the ISS level: it clears only the
events at the submodule level; the IRQ merger automatically clears the IRQ at this level.
NOTE: Only the HS_VS_IRQ top-level event is cleared at the ISS level.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
33
ISS Overview
www.ti.com
IRQ merger
(ISS_HL_IRQENABLE_SET_i)
i = line number
CBUFF
(1IRQ)
ISS_IRQ1
ISS_IRQ2
ISS_IRQ3
ISS_IRQ4
ISS_IRQ5
BTE
(1IRQ)
IRQ merger
(SIMCOP_HL_IRQENABLE_SET_i)
i = line number
SIMCOP
(4IRQ)
SIMCOP_IRQ
ISS
top level
(1IRQ)
ISP_IRQ
IRQ merger
(BTE_HL_IRQENABLE_SET)
HS_VS_IRQ
IRQ merger
(CBUFF_HL_IRQENABLE_SET)
ISP_IRQ
SC
(1IRQ)
CSIA_IRQ
IRQ merger
SC_LCM_IRQENABLE)
ISS lines
ISS_IRQ0
SC_IRQ
CSI2-A
(1IRQ)
ISP_IRQ
IRQ merger
(CSI2_IRQENABLE
from ISS_CSI2_A_REGS1)
CBUFF_IRQ
ISP
(4IRQ)
BTE_IRQ
IRQ merger
(ISP5_IRQENABLE_SET_ i
or ISP5_IRQENABLE_SET2_i)
i = line number
ISP_IRQ
Figure 3. ISS Interrupt Merger
NOTE: For more information about mapping the six lines to the outside ISS device modules, see
Table 5. Only the ISP, SIMCOP, and HL ISS merger IRQ lines are configurable. Each
interrupt can be mapped to the required line.
1.2.1.2
ISS Submodule Interrupts
The ISS shown in Figure 3 and listed in Table 3 can generate six interrupts.
1.2.1.2.1
ISS ISP Interrupts
Table 6 summarizes events that cause ISP interrupts.
Table 6. ISS ISP Interrupts
Event and Register (1)
Description
ISP5_IRQENABLE_SET_i[[31] OCP_ERR_IRQ
An interface port error has been received on the ISP master port.
ISP5_IRQENABLE_SET_i[29] IPIPE_INT_DPC_RNEW1
HD interrupt signal to indicate the need to renew the defect pixel
correction (DPC) table with new entries. The second 128 entries in
the DPC table must be updated when this event triggers. This event is
triggered when the 255th entry in the look-up table (LUT) is used.
This interrupt is not synchronous to the HD signal.
(1)
34
i = 0 to 3
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
Table 6. ISS ISP Interrupts (continued)
Event and Register
(1)
Description
ISP5_IRQENABLE_SET_i[28] IPIPE_INT_DPC_RNEW0
VD interrupt signal to indicate the need to renew the DPC table with
new entries. The first 128 entries in the DPC table must be updated
when the event triggers. This event is triggered when the 127th entry
in the LUT is used. This interrupt is not synchronous to the HD signal.
ISP5_IRQENABLE_SET_i[27] IPIPE_INT_DPC_INI
Interrupt to signal the need to initialize the DPC table. The DPC table
contains two tables of 128 entries. When this signal is used, software
must ensure that the 256 table entries are updated with the DPC
information.
ISP5_IRQENABLE_SET_i[25] IPIPE_INT_EOF
End of frame interrupt signal
ISP5_IRQENABLE_SET_i[24] H3A_INT_EOF
End of frame interrupt signal
ISP5_IRQENABLE_SET_i[22] RSZ_INT_EOF1
See Section 1.3 and ISS ISP Register Manual.
ISP5_IRQENABLE_SET_i[23] RSZ_INT_EOF0
ISP5_IRQENABLE_SET_i[19] RSZ_FIFO_IN_BLK_ERR
ISP5_IRQENABLE_SET_i[18] RSZ_FIFO_IN_OVF
ISP5_IRQENABLE_SET_i[17] RSZ_INT_CYC_RZB
ISP5_IRQENABLE_SET_i[16] RSZ_INT_CYC_RZA
ISP5_IRQENABLE_SET_i[15] RSZ_INT_DMA
ISP5_IRQENABLE_SET_i[14] RSZ_INT_LAST_PIX
ISP5_IRQENABLE_SET_i[13] RSZ_INT_REG
ISP5_IRQENABLE_SET_i[12] H3A_INT
Interrupt generated by the AF and AE/AWB blocks inside the H3A
module. It indicates the end of processing a frame and is active high
for one configuration bus clock cycle.
ISP5_IRQENABLE_SET_i[11] AF_INT
AF inside generates an interrupt at the end of processing frame; a
third interrupt is generated at the same time as the last process to
finish.
ISP5_IRQENABLE_SET_i[10] AEW_INT
AEW inside generates an interrupt at the end of processing frame; a
third interrupt is generated at the same time as the last process to
finish.
ISP5_IRQENABLE_SET_i[9] IPIPEIF_IRQ
IPIPEIF module interrupt is generated at the start position of a frame
and is active high for one configuration bus clock cycle.
ISP5_IRQENABLE_SET_i[8] IPIPE_INT_HST
IPIPE module interrupt is generated when histogram is done.
ISP5_IRQENABLE_SET_i[7] IPIPE_INT_BSC
IPIPE module interrupt is generated when boundary signal calculation
is done.
ISP5_IRQENABLE_SET_i[6] IPIPE_INT_DMA
IPIPE module interrupt is issued when the SDRAM transfer of boxcar
is done. At this time, IPIPE EOF is sent to buffer logic.
ISP5_IRQENABLE_SET_i[5] IPIPE_INT_LAST_PIX
IPIPE module interrupt is issued when the last pixel of a frame comes
into IPIPE.
ISP5_IRQENABLE_SET_i[4] IPIPE_INT_REG
IPIPE module interrupt is issued when the register update of the
module is allowed.
ISP5_IRQENABLE_SET_i[0] ISIF_INT_0
See Section 1.3 and ISS ISP Register Manual.
ISP5_IRQENABLE_SET_i[1] ISIF_INT_1
ISP5_IRQENABLE_SET_i[2] ISIF_INT_2
ISP5_IRQENABLE_SET_i[3] ISIF_INT_3
ISP5_IRQENABLE_SET2_i[0] H3A_OVF
ISP5_IRQENABLE_SET2_i[1] IPIPEIF_UDF
ISP5_IRQENABLE_SET2_i[2] IPIPE_BOXCAR_OVF
ISP5_IRQENABLE_SET2_i[3] ISIF_OVF
ISP5_IRQENABLE_SET2_i[4] IPIPE_HST_ERR
ISP5_IRQENABLE_SET2_i[5] IPIPE_BSC_ERR
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
35
ISS Overview
1.2.1.2.2
www.ti.com
ISS CSI2-A Complex I/O Interrupts
Table 7 lists the event generation of the CSI2-A receiver through the CSI2 interrupt status and interrupt
enable registers. The events are checked for status using the CSI2_IRQSTATUS and CSI2_IRQENABLE
registers.
Table 7. ISS CSI2-A Interrupts
36
Event and Register
Description
CSI2_IRQENABLE[14] OCP_ERR_IRQ
Interface port error
CSI2_IRQENABLE[13] SHORT_PACKET_IRQ
Short packet reception (other than sync events: line start, line end,
frame start, and frame end; only data types from 0x8 to 0xF are
considered)
CSI2_IRQENABLE[12] ECC_CORRECTION_IRQ
ECC was used to correct a 1-bit error (short packet only).
CSI2_IRQENABLE[11] ECC_NO_CORRECTION_IRQ
ECC was not used to correct the header because the error is larger
than 1 bit (short and long packets).
CSI2_IRQENABLE[9] COMPLEXIO_ERR_IRQ
Error signaling from complex I/O: This interrupt is triggered when any
error is received from the complex I/O (events are defined in
CSI2_COMPLEXIO_IRQSTATUS [see Table 8]).
CSI2_IRQENABLE[8] FIFO_OVF_IRQ
FIFO overflow error: This interrupt is triggered when a FIFO overflow
is detected. An overflow can occur if there is a mismatch between the
data input and output rates. A reset of the module is required to
restart correctly.
CSI2_IRQENABLE[7] CONTEXT7
At least one interrupt event enabled from Context 7 occurred
(see Table 9).
CSI2_IRQENABLE[6] CONTEXT6
At least one interrupt event enabled from Context 6 occurred
(see Table 9).
CSI2_IRQENABLE[5] CONTEXT5
At least one interrupt event enabled from Context 5 occurred
(see Table 9).
CSI2_IRQENABLE[4] CONTEXT4
At least one interrupt event enabled from Context 4 occurred
(see Table 9).
CSI2_IRQENABLE[3] CONTEXT3
At least one interrupt event enabled from Context 3 occurred
(see Table 9).
CSI2_IRQENABLE[2] CONTEXT2
At least one interrupt event enabled from Context 2 occurred
(see Table 9).
CSI2_IRQENABLE[1] CONTEXT1
At least one interrupt event enabled from Context 1 occurred
(see Table 9).
CSI2_IRQENABLE[0] CONTEXT0
At least one interrupt event enabled from Context 0 occurred
(see Table 9).
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
Table 8 lists CSI2 receiver event generation through the CSI2-A complex I/O interrupt status and interrupt
enable registers. The events are checked and controlled from the CSI2_COMPLEXIO_IRQSTATUS and
CSI2_COMPLEXIO_IRQENABLE registers.
Table 8. ISS CSI2-A Receivers Complex I/O Interrupts
Event and Register
Description
CSI2_COMPLEXIO_IRQENABLE[0] ERRSOTHS1
Start of transmission error for lane 1
CSI2_COMPLEXIO_IRQENABLE[1] ERRSOTHS2
Start of transmission error for lane 2
CSI2_COMPLEXIO_IRQENABLE[2] ERRSOTHS3
Start of transmission error for lane 3
CSI2_COMPLEXIO_IRQENABLE[5] ERRSOTSYNCHS1
Start of transmission sync error for lane 1
CSI2_COMPLEXIO_IRQENABLE[6] ERRSOTSYNCHS2
Start of transmission sync error for lane 2
CSI2_COMPLEXIO_IRQENABLE[7] ERRSOTSYNCHS3
Start of transmission sync error for lane 3
CSI2_COMPLEXIO_IRQENABLE[10] ERRESC1
Escape entry error for lane 1
CSI2_COMPLEXIO_IRQENABLE[11] ERRESC2
Escape entry error for lane 2
CSI2_COMPLEXIO_IRQENABLE[12] ERRESC3
Escape entry error for lane 3
CSI2_COMPLEXIO_IRQENABLE[15] ERRCONTROL1
Control error for lane 1
CSI2_COMPLEXIO_IRQENABLE[16] ERRCONTROL2
Control error for lane 2
CSI2_COMPLEXIO_IRQENABLE[17] ERRCONTROL3
Control error for lane 3
CSI2_COMPLEXIO_IRQENABLE[20] STATEULPM1
Lane 1 in ULPM
CSI2_COMPLEXIO_IRQENABLE[21] STATEULPM2
Lane 2 in ULPM
CSI2_COMPLEXIO_IRQENABLE[22] STATEULPM3
Lane 3 in ULPM
CSI2_COMPLEXIO_IRQENABLE[25] STATEALLULPMENTER
All active lanes are entering the ULPM.
CSI2_COMPLEXIO_IRQENABLE[26] STATEALLULPMEXIT
At least one active lane exited the ULPM.
Because the CSI2-A receiver supports eight contexts, the CSI2_CTX_IRQSTATUS_i and
CSI2_CTX_IRQENABLE_i registers are present eight times (one time per context).
The events are generated only for the enabled context(s). Table 9 describes the generation of the CS12
receiver event through the CSI2_CTX_IRQSTATUS_i and CSI2_CTX_IRQENABLE_i registers.
Table 9. ISS CSI2-A Receiver CONTEXT Interrupts
Event (1)
Description
CSI2_CTX_IRQENABLE_i[0] FS_IRQ
Frame start: This interrupt is triggered when a frame-start synchronization
code is detected in the CSI2 data stream.
CSI2_CTX_IRQENABLE_i[1] FE_IRQ
Frame end: This interrupt is triggered when a frame-end synchronization
code is detected in the CSI2 data stream.
CSI2_CTX_IRQENABLE_i[2] LS_IRQ
Line start: This interrupt is triggered when a line-start synchronization
code is detected in the CSI2 data stream.
CSI2_CTX_IRQENABLE_i[3] LE_IRQ
Line end: This interrupt is triggered when a line-end synchronization code
is detected in the CSI2 data stream.
CSI2_CTX_IRQENABLE_i[5] CS_IRQ
CS error: This interrupt is triggered when a mismatch between the
transmitter and receiver checksums (payload) is detected.
CSI2_CTX_IRQENABLE_i[6] FRAME_NUMBER_IRQ
Frame counter reached: This interrupt is triggered when the frame counter
reaches its programmable target value.
CSI2_CTX_IRQENABLE_i[7] LINE_NUMBER_IRQ
Line number reached: The programmable line number is received. The
modulo feature can be selected (CSI2_CTX_CTRL1_i.LINE_MODULO).
When selected, the interrupt is generated for each line number multiple of
the programmed line number (CSI2_CTX_CTRL3_i.LINE_NUMBER);
otherwise, the interrupt is generated only for the line number.
CSI2_CTX_IRQENABLE_i[8]
ECC_CORRECTION_IRQ
ECC was used to correct a 1-bit error (long packets only).
(1)
i = 0 to 7
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
37
ISS Overview
1.2.1.2.3
www.ti.com
ISS Stall Controller (SC) Interrupts
Table 10 summarizes the stall controller (SC) interrupts.
Table 10. ISS Stall Controller Interrupts
Event and Register
Description
SC_LCM_IRQENABLE[1] LCM_OCPERROR
SC an interface error occurred on the master read port. This
interrupt is triggered when an OCP error is detected on the
master read port.
SC_LCM_IRQENABLE[0] LCM_EOF
Memory read channel – end of frame: This interrupt is triggered
when a frame is read completely from memory.
1.2.1.2.4
ISS CBUFF Interrupts
Table 11 summarizes the CBUFF interrupts.
Table 11. ISS CBUFF Interrupts
38
Event and Register
Description
CBUFF_HL_IRQENABLE_SET[31] IRQ_CTX7_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[30] IRQ_CTX6_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[29] IRQ_CTX5_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[28] IRQ_CTX4_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[27] IRQ_CTX3_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[26] IRQ_CTX2_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[25] IRQ_CTX1_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[24] IRQ_CTX0_OVR
CBUFF overflow
CBUFF_HL_IRQENABLE_SET[23] IRQ_CTX7_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[22] IRQ_CTX6_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[21] IRQ_CTX5_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[20] IRQ_CTX4_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[19] IRQ_CTX3_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[18] IRQ_CTX2_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[17] IRQ_CTX1_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[16] IRQ_CTX0_INVALID
CBUFF invalid access
CBUFF_HL_IRQENABLE_SET[15] IRQ_CTX7_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[14] IRQ_CTX6_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[13] IRQ_CTX5_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[12] IRQ_CTX4_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[11] IRQ_CTX3_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[10] IRQ_CTX2_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[9] IRQ_CTX1_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[8] IRQ_CTX0_READY
CBUFF WB physical window ready for access by the CPU
CBUFF_HL_IRQENABLE_SET[0] IRQ_OCP_ERR
CBUFF master interface port error
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.2.1.2.5
ISS BTE Interrupts
Table 12 summarizes the BTE interrupts.
Table 12. ISS BTE Interrupts
Event and Register
Description
BTE_HL_IRQENABLE_SET[31] IRQ_CTX7_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 7 is received, but not enough frame lines
have been prefetched in the buffer. See IiSS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[30] IRQ_CTX6_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 6 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[29] IRQ_CTX5_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 5 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[28] IRQ_CTX4_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 4 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[27] IRQ_CTX3_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 3 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[26] IRQ_CTX2_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 2 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[25] IRQ_CTX1_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 1 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[24] IRQ_CTX0_ERR
Writes enable notification for read request before enough data is
prefetched. Reads notify when a read request that requires
translation on Context 0 is received, but not enough frame lines
have been prefetched in the buffer. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[23] IRQ_CTX7_INVALID
Writes enable invalid access to Context 7. Reads notify when
access to an unexpected location in Context 7 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 7 end. See ISS BTE Virtual Address Space and
Context Mapping.
BTE_HL_IRQENABLE_SET[22] IRQ_CTX6_INVALID
Writes enable invalid access to Context 6. Reads notify when
access to an unexpected location in Context 6 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 6 end. See ISS BTE Virtual Address Space and
Context Mapping.
BTE_HL_IRQENABLE_SET[21] IRQ_CTX5_INVALID
Writes enable invalid access to Context 5. Reads notify when
access to an unexpected location in Context 5 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 5 end. See ISS BTE Virtual Address Space and
Context Mapping
BTE_HL_IRQENABLE_SET[20] IRQ_CTX4_INVALID
Writes enable invalid access to Context 4. Reads notify when
access to an unexpected location in Context 4 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 4 end. See ISS BTE Virtual Address Space and
Context Mapping.
BTE_HL_IRQENABLE_SET[19] IRQ_CTX3_INVALID
Writes enable invalid access to Context 3. Reads notify when
access to an unexpected location in Context 3 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 3 end. See ISS BTE Virtual Address Space and
Context Mapping.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
39
ISS Overview
www.ti.com
Table 12. ISS BTE Interrupts (continued)
40
Event and Register
Description
BTE_HL_IRQENABLE_SET[18] IRQ_CTX2_INVALID
Writes enable invalid access to Context 2. Reads notify when
access to an unexpected location in Context 2 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 2 end. See ISS BTE Virtual Address Space and
Context Mapping.
BTE_HL_IRQENABLE_SET[17] IRQ_CTX1_INVALID
Writes enable invalid access to Context 1. Reads notify when
access to an unexpected location in Context 1 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 1 end. See ISS BTE Virtual Address Space and
Context Mapping.
BTE_HL_IRQENABLE_SET[16] IRQ_CTX0_INVALID
Writes enable invalid access to Context 0. Reads notify when
access to an unexpected location in Context 0 is requested, or the
start context location access is valid, but the burst length exceeds
the Context 0 end. See ISS BTE Virtual Address Space and
Context Mapping.
BTE_HL_IRQENABLE_SET[15] IRQ_CTX7_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 7 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[14] IRQ_CTX6_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 6 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[13] IRQ_CTX5_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 5 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[12] IRQ_CTX4_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 4 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[11] IRQ_CTX3_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 3 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[10] IRQ_CTX2_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 2 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[9] IRQ_CTX1_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 1 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
BTE_HL_IRQENABLE_SET[8] IRQ_CTX0_DONE
Writes enable notification for context that has been fully and
successfully transferred to TILER. Reads notify when enough
frame lines have been prefetched into the buffer and Context 0 is
translated to TILER. This interrupt is triggered when flushing
completes (if enabled) in one-shot mode. It is triggered once per
frame in continuous mode. See ISS BTE Buffer Prefetch.
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
Table 12. ISS BTE Interrupts (continued)
Event and Register
Description
BTE_HL_IRQENABLE_SET[1] IRQ_INVALID
Writes enable Invalid virtual space access notification. Reads notify
when access falls into a translated from the BTE region, but it is 2D
access or it does not map to an active context. See ISS BTE
Virtual Address Space and Context Mapping.
BTE_HL_IRQENABLE_SET[1] IRQ_OCP_ERR
Writes enable notification for error on the master output interface.
Reads notify when an error has occurred on the master output
interface.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
41
ISS Overview
1.2.1.2.6
www.ti.com
ISS SIMCOP Interrupts
Table 13 summarizes the SIMCOP high-level interrupts mapped to the outer boundaries of the SIMCOP.
For more information about interrupts generated from inside the SIMCOP modules, see the SIMCOP
section.
Table 13. ISS SIMCOP High-Level Interrupts
42
Event and Register
Description
SIMCOP_HL_IRQENABLE_SET_i[19]
CPU_PROC_START_IRQ
Interrupt used when CPU data processing is used in a
macroblock processing pipeline. When the CPU receives this
IRQ, data is ready to be processed. When the CPU finishes
processing the data, it acknowledges by setting the
SIMCOP_HWSEQ_CTRL.CPU_PROC_DONE bit.
SIMCOP_HL_IRQENABLE_SET_i[18] SIMCOP_DMA_IRQ1
Interrupt triggered by SIMCOP DMA
SIMCOP_HL_IRQENABLE_SET_i[16] OCP_ERR_IRQ
SIMCOP master port interface error
SIMCOP_HL_IRQENABLE_SET_i[15]
VLCDJ_DECODE_ERR_IRQ
A decode error has been signaled by the VLCDJ module.
SIMCOP_HL_IRQENABLE_SET_i[14] DONE_IRQ
Event triggered when hardware sequencer finishes the
sequence:
• The sequence step counter has reached the limit.
• All accelerator and DMA events for the last sequence step
have been received.
SIMCOP_HL_IRQENABLE_SET_i[13] STEP3_IRQ
Event triggered when a SIMCOP Context 3 is activated by the
hardware sequencer.
SIMCOP_HL_IRQENABLE_SET_i[12] STEP2_IRQ
Event triggered when a SIMCOP Context 2 is activated by the
hardware sequencer.
SIMCOP_HL_IRQENABLE_SET_i[11] STEP1_IRQ
Event triggered when a SIMCOP Context 1 is activated by the
hardware sequencer.
SIMCOP_HL_IRQENABLE_SET_i[10] STEP0_IRQ
Event triggered when a SIMCOP Context 0 is activated by the
hardware sequencer.
SIMCOP_HL_IRQENABLE_SET_i[9] LDC_BLOCK_IRQ
A macroblock has been processed.
SIMCOP_HL_IRQENABLE_SET_i[7] ROT_A
Rotational engine interrupt
SIMCOP_HL_IRQENABLE_SET_i[6] IMX_B_IRQ
Event triggered when iMX has executed a SLEEP instruction
SIMCOP_HL_IRQENABLE_SET_i[5] IMX_A_IRQ
Event triggered when iMX has executed a SLEEP instruction
SIMCOP_HL_IRQENABLE_SET_i[4] NSF_IRQ
Event triggered by the NSF2 imaging accelerator when
processing of a block is done
SIMCOP_HL_IRQENABLE_SET_i[3] VLCDJ_BLOC_IRQ
A macroblock has been processed (that is, encode and decode).
SIMCOP_HL_IRQENABLE_SET_i[2] DCT_IRQ
DCT operating is complete (configured number of MCUs for
YUV4:2:0/4:2:2 mode, or number of blocks for sequential block
mode).
SIMCOP_HL_IRQENABLE_SET_i[1] LDC_FRAME_IRQ
A full frame has been processed.
SIMCOP_HL_IRQENABLE_SET_i[0] SIMCOP_DMA_IRQ0
Interrupt triggered by SIMCOP DMA
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.2.2
ISS Interconnect
Figure 4 shows the ISS local interconnect data network.
ISP
SC
SIMCOP
W
W
RW
R
RW
FIFO
FIFO
FIFO
FIFO
FIFO
128b to 64b
64b
64b
CSI2-A
128b
SC
128b
Figure 4. ISS Local Interconnect Data Network
Switch
64b to 128b
FIFO
packing for bursts
5 × 128
Switch 128-bit
128b
ISS interconnect
BTE
The data network collects requests from CSI2-A, SC, ISP, and SIMCOP and forwards them to the BTE.
A first level of arbitration occurs between 64-bit initiators using a round-robin algorithm. Arbitration is done
at the interface transaction level (up to 16 × 64-bit burst). The ISS interconnect packs bursts into up to 8 ×
128-bit bursts before forwarding them to the second level of arbitration. The ISS interconnect uses a 5 ×
128-bit first in first out (FIFO) for burst packing. Burst packing avoids inserting IDLE cycles into requests
sent to the CBUFF.
A second level of arbitration occurs between 128-bit initiators. Again, a round-robin algorithm is used.
Arbitration is done at bus transaction level (up to 8 × 128-bit burst). The ISS interconnect has no data
FIFOs on the request or response paths. This implies the following for the ISP master, SC master, and
SIMCOP master ports:
• The request and data phases can be stalled by the ISS interconnect when the port connected to the
CBUFF becomes stalled.
• Read masters must be able to accept the data they have requested without stalling the response flow.
CSI2, SC, ISP, and SIMCOP can generate up to 16 tags per master port. The number of tags that can be
used per initiator is set by software (the ISS_CTRL.TAG_CNT register). The ISS interconnect compresses
the 6 × 16 internal ISS tags into 16 tags. Tag compression occurs after the 128-bit switch. When all 16
tags are used, the switch output is stalled. This stalls requests from ISS internal initiators.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
43
ISS Overview
www.ti.com
NOTE: There is another internal 32-bit configuration interconnect within the ISS. There is no
physical link between the data and the configuration interconnect.
1.2.3
ISS Clocks
The clocks of ISS submodules can be cut individually using the ISS_CLKCTRL register. Software can poll
the module status reading the appropriate bit in the ISS_CLKSTAT register.
When software wants to enable a submodule:
• Software sets the appropriate bit in the ISS_CLKCTRL register.
• Hardware enables the submodule functional and interface clocks (expected to take a few cycles).
• Hardware sets the appropriate bit in the ISS_CLKSTAT register.
Software must enable the modules in the correct order. The hardware imposes no particular constraint.
For example, when data must be provided by the CSI2-A receiver and processed by the ISP, both
modules must be enabled and correctly configured before data arrives. An example of configuration order
is: enabling the CSI2-A receiver powers up the complex I/O connected to the external sensor. Additionally,
the ISP must be configured and the source interface must be selected. For details and the order of
configuration, see the programming module of the particular submodule.
When software wants to shut down a submodule:
• Software ensures that the submodule is idle. Mainly:
– The submodule must not generate new events.
– The submodule must not have any pending events.
– For initiators: The submodule must stop the generation of an interface bridge transaction.
• Software clears the appropriate bit in the ISS_CLKCTRL register.
• For modules having only a master port: Hardware waits until the submodule to be disconnected
asserts the MStandBy signal on its master port. It asserts MWait of the submodule.
NOTE: The ISS does not assert the MWait signal when a shutdown of the module is not requested
by software.
•
•
Hardware cuts the submodule clocks.
Hardware clears the appropriate bit in the ISS_CLKSTAT register.
Table 14 describes the clock gating of the ISS submodule.
Table 14. ISS Submodule Clock Gating
ISS Resource
Feature On/Off Control
ISS top-level resources
Not applicable. ISS top-level resources cannot be cut. However, top-level resources support
the autogating feature.
SIMCOP
ISS_CLKCTRL[0] SIMCOP
ISP
ISS_CLKCTRL[1] ISP
CSI2-A
ISS_CLKCTRL[2] CSI2_A
SC
ISS_CLKCTRL[4] SC
ISS interconnect
BTE
CBUFF
TCTRL
These modules cannot be switched off individually. They are required for any processing
performed by SIMCOP because they are on the main data path. However, they support
autogating to reduce power consumption when activity is low.
When the clock of a submodule is cut and an interface bridge request for this module is received from the
ISS configuration interconnect, the ISS clock manager temporarily enables the module clock to handle the
access properly.
All ISS submodules are off after reset; software must enable them before they can be used.
44
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.2.4
ISS Reset
The ISS can accept a general software reset, propagated through all the hierarchy. This reset can be
done to initialize the module and has the same effect as the hardware reset.
1. Set the ISS_HL_SYSCONFIG[0] SOFTRESET bit to 1.
2. Read the ISS_HL_SYSCONFIG[0] SOFTRESET bit to check whether it equals 0, which means the
reset occurred.
If after five reads, ISS_HL_SYSCONFIG[0] SOFTRESET still returns 1, it can be assumed that an error
occurred during the reset stage.
A software reset must not reset the power manager protocols (must not reset the IDLE and STANDBY
generic IPs).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
45
ISS Overview
1.2.5
www.ti.com
ISS Power Management
1.2.5.1
ISS Power-Management Infrastructure Overview
Figure 5 provides an overview of the ISS power management.
Figure 5. ISS Power Management
clk to ISS modules
M
M
M
S
S
S
M
S
S
M
S
BTE
TCTRL
ISS regs
M
S
M
ISS data interconnect
M
M
M
Cortex-M3
MPU
subsystem
IRQ merger
M
S
M
ISS PM
ISS configuration interconnect
M
M
L3
(config)
S
SIMCOP
IA
M
S
ISP
M
S
CSI2
S
TA
S
SC
M
per port clkreq
ISS CM
M
S
S
S
CBUFF
M
IA
TA
IDLE protocol
S
L3
(data)
STANDBY protocol
DISCONNECT protocol
M
PRCM
IA
master
TA
S
slave
Asynchronous bridge
NOTE: For power savings, the PRCM module can request idle mode from the ISS. When the ISS is
not functional, software must decide when the PRCM module can send the request. For
more information, see Module Level Clock Management in the Power, Reset, and Clock
Management chapter of the TRM.
1.2.5.2
ISS STANDBY Mechanism
The power manager receives STANDBY information from the SC, CSI2-A, ISP, and SIMCOP modules.
These modules assert a standby signal when they have no more transactions to perform. The ISS power
manager acknowledges by asserting a wait signal.
When those modules are in standby mode, the ISS power manager initiates a STANDBY sequence for the
ISS:
1. The ISS waits while the SC, CSI2-A, ISP, and SIMCOP MStandby is asserted.
2. The ISS power manager acknowledges by asserting the SC, CSI2-A, ISP, and SIMCOP MWait signal.
3. The ISS initiators assert only the MStandBy signal when they receive responses to all sent requests.
Therefore, when all initiators have asserted MStandBy, the ISS interconnect has no more pending
traffic (although configurable, only nonposted writes must be used for error reporting).
46
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
4. The ISS power manager sends an IDLE request to the BTE. This IDLE request is used to drain BTE
data. It does not affect the configuration port.
5. The BTE drains all transactions.
6. The BTE acknowledges the IDLE request.
7. The ISS power manager sends an IDLE request to the CBUFF. This IDLE request is used to drain
CBUFF data. It does not affect the configuration port.
8. CBUFF drains all transactions.
9. CBUFF disconnects the interface master port connected to the L3 interconnect.
10. CBUFF acknowledges the IDLE request.
11. The ISS power manager asserts the MStandBy signals connected to the system PRCM module.
12. The PRCM module acknowledges by asserting the MWait signal.
A functional standby transition can be aborted when one of the SC, CSI2-A, ISP, or SIMCOP modules
deasserts the MStandBy signal. The corresponding MWait signal is deasserted only when the ISS
interconnect, BTE, CBUFF, and ISS interface master port are ready to receive requests.
When one of the SC, CSI2-A, ISP, or SIMCOP modules must perform accesses to the ISS interface
master port, it deasserts the MStandBy signal. The ISS power manager executes the following sequence
to leave the STANDBY state:
1. The ISS power manager deasserts the MStandby signal.
2. The ISS waits until the PRCM module deasserts the MWait signal.
3. The ISS power manager requests CBUFF to go into functional mode.
4. CBUFF connects the interface port.
5. The ISS power manager requests the BTE to go into functional mode.
6. The ISS power manager waits until CBUFF and BTE acknowledge functional mode.
7. The ISS deasserts the MWait signal of the module requesting access.
Abort of the standby-to-functional mode transition is not supported. The ISS power manager completes
the standby-to-functional transition and then allows a new functional-to-standby transition.
Typically, the MStandby signal is used for two purposes. Software chooses one of the following behaviors
through PRCM configuration:
• During blanking periods: The ISS asserts the MStandBy signal between frames when it has no more
data to send. The PRCM module can use this information to switch off the L3 interconnect and save
some dynamic power. However, the PRCM module is not allowed to cut the ISS functional clock in that
case, because it is needed to receive the next frame.
• For ISS shutdown: The ISS asserts MStandBy when it has no more transactions to perform. The
PRCM module then initiates an IDLE sequence. Once the ISS acknowledges the transition into idle
mode, the PRCM module can cut the ISS clock and power.
The internal standby mode can be reached only when SC, CSI2-A, SIMCOP,ISP, ISS data interconnect,
BTE, and CBUFF are in IDLE or STANDBY state. Choosing no-idle or no-standby mode for any of these
modules prevents the ISS from going into STANDBY state.
Four modes for standby control are supported:
• Smart-standby-wakeup mode: This is the mode normally used. When in this mode, the ISS asserts the
MStandBy signal when the MStandBy of all ISS internal initiators is asserted and the ISS data
interconnect, BTE, and CBUFF are in IDLE state.
• Smart-standby mode: The ISS has no wake-up event. This mode is equivalent to smart-standbywakeup mode.
• Force-standby mode: This is a backup mode. When in this mode, the ISS asserts MStandBy
unconditionally. Software must ensure that the ISS is in a correct quiet state before programming this
mode.
• No-standby mode: This is a backup mode. When in this mode, the ISS never asserts the MStandBy
signal.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
47
ISS Overview
1.2.5.3
www.ti.com
ISS IDLE Mechanism
The PRCM module can request the ISS to go into IDLE state when the ISS has asserted its MStandBy
output.
In
to
•
•
•
a normal case, software must ensure that the ISS is in a quiet state before allowing the PRCM module
send an IDLE request to the ISS:
The ISS has no more traffic to generate.
The ISS cannot generate any new interrupts.
The ISS has no pending interrupts.
When an IDLE request is received from the PRCM module, the ISS power manager verifies that the ISS
MWait input has been asserted and that all ISS interrupt outputs are deasserted. It then starts the
STANDBY-to-IDLE transition:
1. Send IDLE request to the ISS configuration interconnect.
2. The ISS configuration interconnect requests disconnection of both ISS interface slave ports.
Disconnection is done by the master:
• It stops accepting new requests and drains currently ongoing ones.
• It waits for completion of all ongoing transactions.
3. The ISS configuration interconnect acknowledges the IDLE transition.
4. The ISS power manager acknowledges the IDLE request from the PRCM module.
5. The PRCM module can cut the ISS clock and power.
The PRCM module first enables the ISS power and clock before requesting the ISS to go into functional
state by deasserting the SIdleReq signal. The ISS power manager then executes the wake-up sequence:
1. Request the ISS interconnect to go into functional state.
2. The ISS interconnect connects the ISS slave ports.
3. The ISS interconnect acknowledges transition into functional mode.
4. The ISS power manager acknowledges transition into functional mode (ISS output SIdleAck = 00).
Four modes for IDLE control are supported:
• Smart-idle-wakeup mode [b11]: This is the mode normally used. When in this mode, the ISS
acknowledges a request to go idle from the power manager after having performed all hardware
operations necessary for the IAF to be in a correct quiet state.
• Smart-idle mode [b10]: This is equivalent to smart-idle-wakeup mode.
• Force-idle mode [b00]: This is a backup mode intended to be used only if smart-idle mode is bugged.
When in this mode, the ISS acknowledges a request to go idle from the power manager with no
hardware condition. Software must ensure that the ISS is in a correct quiet state before requesting a
force-idle transition.
• No-idle mode [b01]: When in this mode, the ISS disregards any request to go idle from the power
manager.
48
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.3
ISS Registers
Table 15 summarizes the ISS TOP register mapping.
Table 15. ISS TOP Register Mapping Summary
Register Name
Type
Register
Width
(Bits)
Address Offset
ISS_TOP
Base Address
Cortex-M3
Private Access
ISS_TOP
Base Address
L3 Interconnect
ISS_HL_REVISION
R
32
0x0000 0000
0x5504 0000
0x5C00 0000
ISS_HL_HWINFO
R
32
0x0000 0004
0x5504 0004
0x5C00 0004
ISS_HL_SYSCONFIG
RW
32
0x0000 0010
0x5504 0010
0x5C00 0010
RESERVED
RW
32
0x0000 001C
0x5504 001C
0x5C00 001C
ISS_HL_IRQSTATUS_RAW_i (1)
RW
32
0x0000 0020 +
(0x10 * i)
0x5504 0020 +
(0x10 * i)
0x5C00 0020 +
(0x10 * i)
ISS_HL_IRQSTATUS_i (1)
RW
32
0x0000 0024 +
(0x10 * i)
0x5504 0024 +
(0x10 * i)
0x5C00 0024 +
(0x10 * i)
ISS_HL_IRQENABLE_SET_i (1)
RW
32
0x0000 0028 +
(0x10 * i)
0x5504 0028 +
(0x10 * i)
0x5C00 0028 +
(0x10 * i)
ISS_HL_IRQENABLE_CLR_i (1)
RW
32
0x0000 002C +
(0x10 * i)
0x5504 002C +
(0x10 * i)
0x5C00 002C +
(0x10 * i)
ISS_CTRL
RW
32
0x0000 0080
0x5504 0080
0x5C00 0080
ISS_CLKCTRL
W
32
0x0000 0084
0x5504 0084
0x5C00 0084
ISS_CLKSTAT
R
32
0x0000 0088
0x5504 0088
0x5C00 0088
ISS_PM_STATUS
R
32
0x0000 008C
0x5504 008C
0x5C00 008C
(1)
1.3.1
i = 0 to 5
ISS_HL_REVISION Register
Figure 6. ISS_HL_REVISION Register
31
0
REVISION
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. ISS_HL_REVISION_Register Field Description
Bit
31-0
(1)
Field
REVISION
Value
Description
IP Revision (1)
TI internal data.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
49
ISS Overview
1.3.2
www.ti.com
ISS_HL_HWINFO
Figure 7. ISS_HL_HWINFO Register
31
3
2
0
RESERVED
BRIDGE_BUFF
R-0
R-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. ISS_HL_HWINFO Field Descriptions
Bit
50
Field
31-3
Reserved
2-0
BRIDGE_BUFF
Value
Description
Reserved
Size of the reordering buffer in the SC read bridge.
0h
8x128-bits
1h
16x128-bits
2h
32x128-bits
3h
64x128-bits
4h
128x128-bits
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.3.3
ISS_HL_SYSCONFIG
Figure 8. ISS_HL_SYSCONFIG Register
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
STANDBYMODE
IDLEMODE
Reserved
SOFTRESET
R-0
R/W-2h
R/W-2h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. ISS_HL_SYSCONFIG Field Descriptions
Bit
Field
Value
Description
31-6
Reserved
Reserved
5-4
STANDBYMODE
Master interface power management, standby/Wait control
3-2
0h
Force-standby.
MStandby is asserted unconditionally.
1h
No-standby.
MStandby is never asserted.
2h
Smart-standby
3h
Smart-standby
IDLEMODE
1
Reserved
0
SOFTRESET
IDLE protocol configuration
0h
Force-idle
1h
No-idle
2h
Smart-idle
3h
Smart-idle
Resrved
Software reset.
W-0h
No action
W-1h
Initiate software reset
R-1h
Reset (software or other) ongoing
R-0h
Reset done, no pending action
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
51
ISS Overview
1.3.4
www.ti.com
ISS_HL_IRQSTATUS_RAW_i
Figure 9. ISS_HL_IRQSTATUS_RAW_i_Register
31
24
Reserved
R-0
23
18
17
16
Reserved
HS_VS_IRQ
SC_IRQ8
R-0
R/W-0
R-0
15
14
13
12
11
10
SIMCOP_IRQ3
SIMCOP_IRQ2
SIMCOP_IRQ1
SIMCOP_IRQ0
BTE_IRQ
CBUFF_IRQ
Reserved
R-0
R-0
R-0
R-0
R-0
R-0
R-0
7
5
9
8
4
3
2
1
0
Reserved
CSIA_IRQ
ISP_IRQ3
ISP_IRQ2
ISP_IRQ1
ISP_IRQ0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. ISS_HL_IRQSTATUS_RAW_i_Register Field Descriptions
Bit
31-18
17
Field
Value
Description
Reserved
Reserved
HS_VS_IRQ
HS or VS synchronization event. RW 0
This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video
port mux).
The rising or falling edge and the HS or VS signal selection is chosen with the
ISS_CTRL.SYNC_DETECT bit field.
16
15
14
13
12
11
52
W-0h
No action
W-1h
Set event (debug)
R-1h
Event pending
R-0h
No event pending
SC_IRQ8
Event generated by the Stall controller
1h
Event pending
0h
No event pending
SIMCOP_IRQ3
Event generated by SIMCOP
1h
Event pending
0h
No event pending
SIMCOP_IRQ2
Event generated by SIMCOP
1h
Event pending
0h
No event pending
SIMCOP_IRQ1
SIMCOP_IRQ0
Event
Event generated by SIMCOP
1h
Event pending
0h
No event pending
Event generated by SIMCOP
1h
Event pending
0h
No event pending
BTE_IRQ
Event generated by the burst translation engine
1h
Event pending
0h
No event pending
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
Table 19. ISS_HL_IRQSTATUS_RAW_i_Register Field Descriptions (continued)
Bit
Field
10
CBUFF_IRQ
Value
Description
Event generated by the circular buffer
1h
Event pending
0h
No event pending
9-5
Reserved
Reserved
4
CSIA_IRQ
Event generated by the CSI2 receiver #a
3
1h
Event pending
0h
No event pending
ISP_IRQ3
2
Combined interrupt event provided by the ISP.
1h
Event pending
0h
No event pending
ISP_IRQ2
1
Combined interrupt event provided by the ISP.
1h
Event pending
0h
No event pending
ISP_IRQ1
0
Combined interrupt event provided by the ISP.
1h
Event pending
0h
No event pending
ISP_IRQ0
1.3.5
Combined interrupt event provided by the ISP.
1h
Event pending
0h
No event pending
ISS_HL_IRQSTATUS_i
Figure 10. ISS_HL_IRQSTATUS_i_Register
31
24
Reserved
R-0
23
17
16
Reserved
18
HS_VS_IRQ
SC_IRQ8
R-0
R/W1S-0
R-0
9
8
15
14
13
12
11
10
SIMCOP_IRQ3
SIMCOP_IRQ2
SIMCOP_IRQ1
SIMCOP_IRQ0
BTE_IRQ
CBUFF_IRQ
Reserved
R-0
R-0
R-0
R-0
R-0
R-0
R-0
7
4
3
2
1
0
Reserved
5
CSIA_IRQ
ISP_IRQ3
ISP_IRQ2
ISP_IRQ1
ISP_IRQ0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. ISS_HL_IRQSTATUS_i_Register Field Descriptions
Bit
31-18
Field
Reserved
Value
Description
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
53
ISS Overview
www.ti.com
Table 20. ISS_HL_IRQSTATUS_i_Register Field Descriptions (continued)
Bit
Field
17
HS_VS_IRQ
Value
Description
HS or VS synchronization event.
This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video
port mux).
The rising or falling edge and the HS or VS signal selection is chosen with the
ISS_CTRL.SYNC_DETECT bit field.
16
15
14
13
12
11
10
No action
W-1h
Clear (raw) event
R-0h
No (enabled) event pending
R-1h
Event pending
SC_IRQ8
Event generated by the Stall controller
0h
No (enabled) event pending
1h
Event pending
SIMCOP_IRQ3
Event generated by SIMCOP
0h
No (enabled) event pending
1h
Event pending
SIMCOP_IRQ2
Event generated by SIMCOP
0h
No (enabled) event pending
1h
Event pending
SIMCOP_IRQ1
SIMCOP_IRQ0
Event
Event generated by SIMCOP
0h
No (enabled) event pending
1h
Event pending
Event generated by SIMCOP
0h
No (enabled) event pending
1h
Event pending
BTE_IRQ
Event generated by the burst translation engine
0h
No (enabled) event pending
1h
Event pending
CBUFF_IRQ
Event generated by the circular buffer
0h
No (enabled) event pending
1h
Event pending
9-5
Reserved
Reserved
4
CSIA_IRQ
Event generated by the CSI2 receiver #a
3
2
1
0
54
W-0h
0h
No (enabled) event pending
1h
Event pending
ISP_IRQ3
Combined interrupt event provided by the ISP.
0h
No (enabled) event pending
1h
Event pending
ISP_IRQ2
Combined interrupt event provided by the ISP.
0h
No (enabled) event pending
1h
Event pending
ISP_IRQ1
Combined interrupt event provided by the ISP.
0h
No (enabled) event pending
1h
Event pending
ISP_IRQ0
Combined interrupt event provided by the ISP.
0h
No (enabled) event pending
1h
Event pending
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.3.6
ISS_HL_IRQENABLE_SET_i
Figure 11. ISS_HL_IRQENABLE_SET_i Register
31
24
Reserved
R-0
23
18
17
16
Reserved
HS_VS_IRQ
SC_IRQ8
R-0
R/W1S-0
R/W1S-0
9
8
15
14
13
12
11
10
SIMCOP_IRQ3
SIMCOP_IRQ2
SIMCOP_IRQ1
SIMCOP_IRQ0
BTE_IRQ
CBUFF_IRQ
Reserved
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R-0
6
5
7
4
3
2
1
0
Reserved
CSIA_IRQ
ISP_IRQ3
ISP_IRQ2
ISP_IRQ1
ISP_IRQ0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. ISS_HL_IRQENABLE_SET_i Field Descriptions
Bit
31-18
17
Field
Value
Description
Reserved
Reserved
HS_VS_IRQ
HS or VS synchronization event.
This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video
port mux).
The rising or falling edge and the HS or VS signal selection is chosen with the
ISS_CTRL.SYNC_DETECT bit field.
16
15
14
13
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SC_IRQ8
Event generated by the Stall controller
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SIMCOP_IRQ3
Event generated by SIMCOP
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SIMCOP_IRQ2
Event generated by SIMCOP
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SIMCOP_IRQ1
Event generated by SIMCOP
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
55
ISS Overview
www.ti.com
Table 21. ISS_HL_IRQENABLE_SET_i Field Descriptions (continued)
Bit
Field
12
SIMCOP_IRQ0
11
10
Reserved
CSIA_IRQ
2
1
0
56
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
Event generated by the burst translation engine
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
CBUFF_IRQ
4
Description
Event generated by SIMCOP
BTE_IRQ
9-5
3
Value
Event generated by the circular buffer
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
Reserved
Event generated by the CSI2 receiver #a RW
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ3
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ2
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ1
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ0
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.3.7
ISS_HL_IRQENABLE_CLR_i
Figure 12. ISS_HL_IRQENABLE_CLR_i Register
31
24
Reserved
R-0
23
18
17
16
Reserved
HS_VS_IRQ
SC_IRQ8
R-0
R/W1C-0
R/W1S-0
9
8
15
14
13
12
11
10
SIMCOP_IRQ3
SIMCOP_IRQ2
SIMCOP_IRQ1
SIMCOP_IRQ0
BTE_IRQ
CBUFF_IRQ
Reserved
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R-0
6
5
7
4
3
2
1
0
Reserved
CSIA_IRQ
ISP_IRQ3
ISP_IRQ2
ISP_IRQ1
ISP_IRQ0
R-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; R/W1 to set
Table 22. ISS_HL_IRQENABLE_CLR_i Register Field Descriptions
Bit
31-18
17
Field
Value
Description
Reserved
Reserved
HS_VS_IRQ
HS or VS synchronization event.
This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video
port mux).
The rising or falling edge and the HS or VS signal selection is chosen with the
ISS_CTRL.SYNC_DETECT bit field.
16
15
14
13
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SC_IRQ8
Event generated by the Stall controller
W-0h
No action
W-1h
Enable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SIMCOP_IRQ3
Event generated by SIMCOP
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SIMCOP_IRQ2
Event generated by SIMCOP
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SIMCOP_IRQ1
Event generated by SIMCOP
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
57
ISS Overview
www.ti.com
Table 22. ISS_HL_IRQENABLE_CLR_i Register Field Descriptions (continued)
Bit
Field
12
SIMCOP_IRQ0
11
10
Reserved
CSIA_IRQ
2
1
0
58
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
Event generated by the BTE
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
CBUFF_IRQ
4
Description
Event generated by SIMCOP
BTE_IRQ
9-5
3
Value
Event generated by the CBUFF
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
Reserved
Event generated by the CSI2 receiver a
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ3
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ2
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled(masked)
R-1h
Interrupt enabled
ISP_IRQ1
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt disabled (masked)
R-1h
Interrupt enabled
ISP_IRQ0
Combined interrupt event provided by the ISP.
W-0h
No action
W-1h
Disable interrupt
R-0h
Interrupt enabled
R-1h
Interrupt disabled (masked)
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.3.8
ISS_CTRL
Figure 13. ISS_CTRL Register
31
28
27
24
23
20
19
16
Reserved
CSI2_A_TAG_CNT
SCW_TAG_CNT
SCR_TAG_CNT
R-0
R/W-0
R/W-0
R/W-0
15
6
5
4
3
2
1
0
Reserved
ISS_CLK_DIV
INPUT_SEL
SYNC_
DETECT
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. ISS_CTRL Register Field Descriptions
Bit
Field
Value
Description
31-28
Reserved
27-24
CSI2_A_TAG_CN
T
0h
Defines the maximum number of tags that could be used by the CSI2 a write bridge.
Note: Tag count must be set to 16 for best performance
23-20
SCW_TAG_CNT
0h
Defines the maximum number of tags that could be used by the SC write bridge
Note: Tag count must be set to 16 for best performance.
19-16
SCR_TAG_CNT
0h
Defines the maximum number of tags that could be used by the SC read bridge
Note: Tag count must be set to 16 for best performance.
15-6
Reserved
Reserved
5-4
ISS_CLK_DIV
ISS functional clock division
CLK refers to the input clock provided to the ISS. FCLK is the functional clock provided to ISS top
level and submodules.
CFGCLK is the clock used for the configuration network
3-2
1-0
Reserved
0h
FCLK=CLK
CFGCLK=CLK/2
1h
FCLK=CLK/2
CFGCLK=CLK/4
2h
FCLK=CLK/4
CFGCLK=CLK/8
3h
Reserved
INPUT_SEL
Selects ISP input
0h
CSI2-A
2h
SC
3h
Parallel interface
SYNC_DETECT
Chooses among rising and falling edge for the HS_VS_IRQ synchronization even
0h
HS falling edge
1h
HS raising edge
2h
VS falling edge
3h
VS raising edge
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
59
ISS Overview
1.3.9
www.ti.com
ISS_CLKCTRL
Figure 14. ISS_CLKCTRL Register
31
30
29
28
VPORT3_CLK
VPORT2_CLK
Reserved
VPORT0_CLK
Reserved
R-1
R-1
R-1
R-1
R-0
15
5
27
16
4
3
2
1
0
Reserved
SC
Reserved
R-0
W-0
R-0
CSI2_A
ISP
SIMCOP
W-0
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. ISS_CLKCTRL Register Field Descriptions
Bit
Field
31
VPORT3_CLK
30
Reserved
28
VPORT0_CLK
4
60
Disabled
1h
Enabled
Enables the pixel clock from the Stall controller
0h
Disabled
1h
Enabled
Reserved
Enables the pixel clock from the CSI2_A protocol engine
0h
Disabled
1h
Enabled
Reserved
SC
Stall controller
Reserved
2
CSI2_A
0
Enables the pixel clock from the parallel interface
Reserved
3
1
Description
0h
VPORT2_CLK
29
27-5
Value
0h
Request shutdown of the submodule.
No effect if the submodule clock is already off.
1h
Request enable of the submodule.
No effect if the submodule clock is already off.
Reserved
CSI2_A
0h
Request shutdown of the submodule.
No effect if the submodule clock is already off.
1h
Request enable of the submodule.
No effect if the submodule clock is already off.
ISP
ISP
0h
Request shutdown of the submodule.
No effect if the submodule clock is already off.
1h
Request enable of the submodule.
No effect if the submodule clock is already off.
SIMCOP
SIMCOP
0h
Request shutdown of the submodule.
No effect if the submodule clock is already off.
1h
Request enable of the submodule.
No effect if the submodule clock is already off.
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Overview
www.ti.com
1.3.10
ISS_CLKSTAT
Figure 15. ISS_CLKSTAT Register
31
30
29
28
VPORT3_CLK
VPORT2_CLK
Reserved
VPORT0_CLK
Reserved
R-1
R-1
R-1
R-1
R-0
15
5
27
16
4
3
2
1
0
Reserved
SC
Reserved
CSI2_A
ISP
SIMCOP
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. ISS_CLKSTAT Register Field Descriptions
Bit
Field
31
VPORT3_CLK
30
Reserved
28
VPORT0_CLK
4
Disabled
1h
Enabled
Status of the pixel clock from the Stall controller
0h
Disabled
1h
Enabled
Reserved
Status of the pixel clock from the CSI2_A protocol engine.
0h
Disabled
1h
Enabled
Reserved
SC
Stall Controller
Reserved
2
CSI2_A
0
Status of the pixel clock from the parallel interface
Reserved
3
1
Description
0h
VPORT2_CLK
29
27-5
Value
0h
The submodule is off.
1h
The submodule is on.
Reserved
CSI2_A
0h
The submodule is off.
1h
The submodule is on.
ISP
ISP
0h
The submodule is off.
1h
The submodule is on.
SIMCOP
SIMCOP
0h
The submodule is off.
1h
The submodule is on.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
61
ISS Overview
1.3.11
www.ti.com
ISS_PM_STATUS
Figure 16. ISS_PM_STATUS Register
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
CBUFF_PM
BTE_PM
SIMCOP_PM
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
ISP_PM
SC_PM
Reserved
CSI2_A_PM
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. ISS_PM_STATUS Register Field Descriptions
Bit
Field
31-14
Reserved
13-12
CBUFF_PM
11-10
9-8
7-6
5-4
62
Value
Reserved
Power status of the CBUFF.
0h
Idle
1h
Transition
2h
Functional
BTE_PM
Power status of the BTE.
0h
Idle
1h
Transition
2h
Funcitonal
SIMCOP_PM
Power status of the SIMCOP.
0h
Standby
1h
Transition
2h
Functional
ISP_PM
Power status of the ISP.
0h
Standby
1h
Transition
2h
Functional
SC_PM
3-2
Reserved
1-0
CSI2_A_PM
Description
Power status of the CS.
0h
Standby
1h
Transition
2h
Functional
Reserved
Power status of the CSI2 module A
0h
Standby
1h
Transition
2h
Functional
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2 ISS Interfaces
2.1
ISS Interfaces Overview
Along with the submodules, the ISS has a serial camera interface and a parallel interface. The serial
interface (CSI2-A) supports MIPI® CSI2 protocol with four data lanes. The parallel interface (CPI) supports
up to 16 data lanes. All interfaces can use the image signal processor (ISP), but not concurrently. When
one interface uses the ISP, the other must send data to memory. However, the ISP can still be used to
process this data in memory-to-memory. Time multiplex processing is also possible.
Figure 17 shows the ISS interfaces and interconnects.
Figure 17. ISS Interfaces and Interconnects Highlights
ISS
cam2_pclk
cam2_wen
cam2_f d
cam2_vs
am2_vs
ISS interfaces and
interconnects
cam2_hs
cam2_d[15:0]
ISS
interconnect
CSI2-A
CPI
CBUFF
csi2a_dx0
E
BTE
csi2a_dy0
CSIA_IRQ
ISS IRQ merger
BTE_IRQ
CBUFF_IRQ
CSI2A CAMERARX
csi2a_dx1
csi2a_dy1
csi2a_dx2
csi2a_dy2
csi2a_dx3
csi2a_dy3
csi2a_dx4
csi2a_dy4
ISS_FCLK
CAM_PHY_CTRL_FCLK
PRCM
cam_strobe
cam_global_reset
STANDBY
hardware
handshake
cam_shutter
NOTE: In the device, the number 2 in the cam2 interface name does not mean there are two
camera parallel interfaces available in the device. The cam2 interface name defines the
camera parallel interface available in the device versus the legacy device.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
63
ISS Interfaces
2.1.1
www.ti.com
ISS Interface Features
The camera subsystem supports the following features:
• System interfaces and interconnects:
– Two 32-bit-wide configuration interfaces:
• Interface to Cortex™-M3 microprocessor unit (MPU): Synchronous to the functional clock
• Interface to Cortex™-A8 MPU and system direct memory access (EDMA): Asynchronous from
the functional clock
– 128-bit-wide data interface to level 3 (L3) interconnect: Asynchronous from the functional clock
• Shared interface level 2 (L2) (256KB) in IVA-HD module for hardware encoding
• Outside connection using the L3 interconnect through the TILER to the synchronous dynamic
random access memory (SDRAM) controller (SDRC), which acts as the primary interface
between the SDRAM and the ISS functional block
– The ISS has a local interconnect that connects all modules inside the ISS.
– BTE:
• Tightly coupled with the TILER to support efficient rotation
– CBUFF:
• Maps a linear space into a circular buffer
• The buffer is physically located in system memory.
– TCTRL:
• Control signal generation for flash prestrobe and strobe
• Camera global reset control
• Camera interfaces:
– CSI2 camera interfaces: CSI2-A
• Transfer pixels and data received by the CSI2 digital physical layer receiver to the system
memory or to the ISP
• Use unidirectional data link
• CSI2-A supports four configurable data links in addition to the clock signaling.
• Maximum data rate of 1 Gbps per data lane
• Data merger for 2-, 3-, or 4-data lane configuration
• Maximum data rate of 1 Gbps per data lane, possible configurations are:
• One data lane: 1000 Mbps
• Two data lanes: 2 × 1000 Mbps
• Three data lanes: 3 × 1000 Mbps
• Four data lanes: 4 × 824 Mbps
• Error detection and correction by the protocol engine
• Direct memory access (DMA) engine integrated with dedicated first in first out (FIFO)
• One-dimensional (1D) and two-dimensional (2D) addressing mode
• Burst support
• Streaming burst support (64- or 32-bit)
• Eight contexts to support eight dedicated configurations of virtual channel ID and data types
• Ping-pong mechanism for double-buffering
• All primary and secondary MIPI-defined formats are supported.
• Conversion of the RGB formats
• On-the-fly differential pulse code modulation (DPCM) decompression
• On-the-fly image cropping and A-law/DPCM compression
64
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
– Parallel interface (CPI)
• 16 bits wide
• up to 162 MPix/s
• BT656 and SYNC mode (HS, VS, FIELD, WEN)
– System memory data read back port (supported by the Stall controller)
• RAW 6, 7, 8, 10, 12, 14, 16 formats supported
• DPCM and A-law decompression
• Supports image cropping for compressed or uncompressed data
NOTE: Rotated DPCM data is not supported.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
65
ISS Interfaces
2.2
www.ti.com
ISS Interfaces Environment
2.2.1
ISS Interfaces Signal Descriptions
Table 27 summarizes the I/O signals.
Table 27. ISS I/O Description
Signal Name
Description
Serial Mode CSI2
cam_strobe
O
Flash strobe control signal
x
cam_shutter
O
Mechanical shutter control
signal
x
cam_global_reset
I/O
Global reset release shutter
signal
x
Parallel Mode CPI
csi2a_dx0
I
Serial CSI2-A mode:
Differential clock positive
input
x
csi2a_dy0
I
Serial CSI2-A mode:
Differential clock negative
input
x
csi2a_dx1
I
Serial CSI2-A mode:
Differential data lane
positive input
x
csi2a_dy1
I
Serial CSI2-A mode:
Differential data lane
negative input
x
csi2a_dx2
I
Serial CSI2-A mode:
Differential data lane
positive input
x
csi2a_dy2
I
Serial CSI2-A mode:
Differential data lane
negative input
x
csi2a_dx3
I
Serial CSI2-A mode:
Differential data lane
positive input
x
csi2a_dy3
I
Serial CSI2-A mode:
Differential data lane
negative input
x
csi2a_dx4
I
Serial CSI2-A mode:
Differential data lane
positive input
x
csi2a_dy4
I
Serial CSI2-A mode:
Differential data lane
negative input
x
cam2_pclk
I
Parallel mode pixel clock
input
x
cam2_wen
I
Parallel mode write enable
signal input
x
cam2_fld
I/O
Parallel mode pixel clock
field signal
x
cam2_vs
I/O
Parallel mode vertical frame
synchronization
x
cam2_hs
I/O
Parallel mode horizontal
frame synchronization
x
Parallel mode data lanes (16
signals)
x
cam2_d[15:0]
(1)
66
I/O (1)
I
I = Input; O = Output
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
NOTE: Lane polarity can be changed in complex I/O. For more information, see Section 2.2.2, ISS
Interface Modes.
NOTE: At least one data lane must be configured for using the CSI2-A interface. The signals are
also configurable from the control module. Thus, they are not required to be at a certain
location to act as clock or data; this can be configured.
2.2.2
ISS Interface Modes
The camera subsystem can manage a parallel and serial interface. Depending on the configuration of the
shared pins, two of the interfaces can be active at the same time. However, only one data flow can use
the ISP. Moreover, if the parallel interface is used data from it goes to ISP and the other used interface
must send it to memory. Figure 18 shows an example block diagram of the interface configuration. Each
serial port clock lane is configurable. The MIPI CSI2 protocol requires only a clock lane setup. The data
lane configuration is optional. For more information, see Section 2.6.1.1, ISS CSI2 Protocol and Data
Format.
Figure 18. ISS CSI2-A Serial Interface and Parallel Interface Configuration
required
optional
ISS interfaces and
interconnects
cam2_pclk
cam2_wen
cam2_fld
ISS
cam2_vs
cam2_hs
cam2_d[15:0]
ISS
interconnect
csi2a_dx0
ISS IRQ merger
PRCM
SC_IRQ[8]
CSIA_IRQ
BTE_IRQ
CBUFF_IRQ
ISS_FCLK
CAM_PHY_CTRL_FCLK
CSI2-A CAMERARX
csi2a_dy0
csi2a_dx1
csi2a_dy1
csi2a_dx2
csi2a_dy2
csi2a_dx3
csi2a_dy3
csi2a_dx4
csi2a_dy4
cam_strobe
STANDBY
hardware
handshake
cam
cam_global_reset
cam_shutter
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
CLK
WEN
FIELD
VSYNC
Parallel
image
sensor
HSYNC
DATA [15:0]
CLK+
CLKDATA1+
DATA1DATA2+
DATA2DATA3+
DATA3DATA4+
DATA4-
CSI2
image
sensor
module
FLASH STROBE
(optional)
GLOBAL_RESET
MECH SHUTTER
(optional)
Imaging Subsystem (ISS)
67
ISS Interfaces
2.3
2.3.1
www.ti.com
ISS CSI2 PHY
ISS CSI2 PHY Overview
A MIPI D-PHY-compliant CAMERARX PHY receiver immediately before the ISS interfaces acts as a
physical connection and configuration of clock/data lanes with external sensors. CAMERARX PHY
supports up to four configurations, depending on the required number of D-PHY data lane external
sensors. The receivers are compatible with the MIPI D-PHY Specification v0.92. The selection of
CAMERARX in D-PHY mode or parallel mode must be done before reset and not on the fly.
The PHY is controlled and must be configured first from the control module for pad configuration. The
PHY is developed as two modules: CAMERARX_CORE and CAMERARX_ADDON. The CSI2-A
CAMERARX contains four data lanes, as shown in Figure 19.
Figure 19. ISS Interfaces CSI2-A PHY Diagram Four D-PHY Data Lane Configuration
ISS interfaces and
interconnects
cam2_pclk
cam2_wen
cam2_fld
ISS
cam2_vs
cam2_hs
cam2_d[15:0]
cam
CSI2-A CAMERARX
core
addon addon
CSI2-A
CPI
DX
DY
addon
ISS
interconnect
DX
DY
DX
DY
DX
DY
DX
DY
csi2a_dx0
csi2a_dy0
lane 0
csi2a_dx1
csi2a_dy1
csi2a_dx2
csi2a_dy2
lane 1
lane22
lane
csi2a_dx3
csi2a_dy3
lane 3
lane1
csi2a_dx4
csi2a_dy4
lane
lane04
NOTE: LANE 4 can be used only as a data lane, never as a clock lane. All other configurations are
possible. Also, a speed restriction is present when lane 4 is used; then all data lanes perform
at up to 824 Mbps instead of 1000 Mbps.
CSI2-A CAMERARX represents the overall PHY solution for connecting external sensors to feed the ISS.
The MIPI D-PHY function can support up to four data lane modules and one clock lane module. Reverse
direction escape mode is not supported. The lane module polarity and positions are configurable; that is,
any lane module can be chosen as the clock lane module, and the DX/DY data pad for each lane module
can be configured as DP or DN pins defined. The configuration and the selection of D-PHY mode,
data/clock, or data/strobes are done through the control module. The only exception is the four-data-lane
use case, in which one corner lane is allowed to be only a data lane.
68
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.3.2
ISS CSI2 PHY Functional Description
2.3.2.1
ISS CSI2 PHY Functional Configuration
The CSI2 PHY converts the bitstream, divided into 1 to 4 serial data lanes, into a bitstream compatible
with the CSI2 receiver and one clock lane.
The CSI2_COMPLEXIO_IRQSTATUS register logs complex I/O events of the following types:
• Line power-state change (all lanes in ultralow-power mode [ULPM], at least one lane exits ULPM, etc.)
• Error on one lane
The CSI2 receiver embeds two registers to configure/read some complex I/O parameters:
• The REGISTER0 register detects clock miss with respect to the MIPI D-PHY Specification v0.92 and
control timing.
• The REGISTERO register reports completion of reset on the different parts of the module and
configures the timing parameters.
• The CS12_COMPLEXIO_CFG registers contain the PWR_AUTO and PWR_CMD bit fields, which
affect the power management of the complex I/O.
The complex I/O has three power modes: on, off, and ultralow power (ULP). These modes can reflect the
ON or ULP states of the five differential lines if the CS12_COMPLEXIO_CFG [24] PWR_AUTO bit is set to
1. If the PWR_AUTO bit is at reset value (0), the complex I/O power state is controlled by the
CS12_COMPLEXIO_CFG [28:27] PWR_CMD bit field, which directly defines the power state. Figure 20
shows the complex I/O power finite state-machine (FSM).
Figure 20. ISS CSI2 Complex I/O Power FSM
Reset
CSI2_COMPLEXIOi_CFG[28:27] PWR_CMD = 0x1
(CSI2_COMPLEXIOi_CFG[24] PWR_AUTO is ignored)
CSI2_COMPLEXIOi_CFG[28:27] PWR_CMD = 0x2 and
CSI2_COMPLEXIOi_CFG[24] PWR_AUTO = 0x0
or
All the enabled lanes are in ULPM
and CSI2_COMPLEXIOo_CFG[24] PWR_AUTO = 0x1
ON
CSI2_COMPLEXIOi_CFG[28:27] PWR_CMD = 0x0
(CSI2_COMPLEXIOi_CFG[24] PWR_AUTO is ignored)
U
ULP
CSI2_COMPLEXIOi_CFG[28:27] PWR_CMD = 0x1 and
CSI2_COMPLEXIOi_CFG[24] PWR_AUTO = 0x0
or
At least one of the enabled lanes is not in ULPM
Oo_CFG[24] PWR_AUTO = 0x1
and CSI2_COMPLEXIOo_CFG[24]
Another register, CS12_TIMING is used to control the power state of the complex I/O modules with regard
to the differential line state. This register controls the mode of the complex I/O (RxMode and NoRxMode)
and the delay between the differential lanes in STOP state and the complex I/O on NoRxMode. The
CS12_TIMING[15] FORCE_RX_MODE_IO1 bit sets the complex I/O in RxMode or NoRxMode (stopped
mode). The FORCE_RX_MODE_IO bit is automatically reset to 0 by hardware when the counter ends and
the FSM returns to NoRxMode. Three bits (CS12_TIMING[14] STOP_STATE_X16_IO1,
CS12_TIMING[13] STOP_STATE_X4_IO1, and the CS12_TIMING[12:0] STOP_STATE_COUNTER_IO1
bit field) configure the delay between line stop mode and complex I/O stop mode. The delay represents
the number of functional clock (ISS_FCLK) cycles and can be calculated as follows:
Total delay in ISS_FCLK cycle = CS12_TIMING.STOP_STATE_COUNTER_IO x
(1+CS12_TIMING.STOP_STATE_X16_IO x 15) x (1+CS12_TIMING.STOP_STATE_X4_IO x 3).
Table 28 lists the possible values of the delay, in terms of the ISS_FCLK cycles, depending on the values
of the STOP_STATE_X16_IO and STOP_STATE_X4_IO bits.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
69
ISS Interfaces
www.ti.com
Table 28. ISS CSI2 Possible Time-Out Value for RxMode Counter
STOP_STATE_X16_IO
STOP_STATE_X4_IO
0x0
0x0
Possible Delay Value (in Functional Clock Cycles)
8191 (with step of 1)
0x0
0x1
32764 (with step of 4)
0x1
0x0
131056 (with step of 16)
0x1
0x1
524224 (with step of 64)
The FORCERXMODE signal is used at initialization time (complex I/O). Figure 21 describes the
ForceRxMode and StopState FSM to assert and deassert the FORCERXMODE signal and to monitor
STOPSTATE from the complex I/O.
Figure 21. ISS CSI2 RxMode and StopState FSM
Reset
Stop state detected
(all lanes)
CSI2_TIMING.FORCERXMODE_IO
= 0x1
CSI2_TIMI
Assertion
+
Timer loaded
Deassertion
D
CSI2_TIMING.FORCERXMODE_IO = 0x0
No stop state detected
(at least 1 lane)
CSI2_TIMING.FORCERXMODE_IO = 0x0
or
time-out
2.3.2.2
ISS CSI2 PHY and Link Initialization Sequence
The MIPI D-PHY initialization sequence is not implemented within CAMERARX. The CSI2-A receiver is
expected to coordinate the PHY initialization. The controller must ensure that the PHY is held in
RESET/WAIT for RX mode until the D-PHY transmitter is powered up and the link comes to the defined
state. The controller can use the STOPSTATE and FORCERXMODE signals of CAMERARX for this
purpose. STOPSTATE indicates the line states, while FORCERXMODE forces the receiver state-machine
into "wait for stop state." One possible initialization sequence is:
To fully initialize the CSIPHY, perform the following steps:
1. Configure all CSI2 receiver registers to be ready to receive signals/data from the CSIPHY:
(a) Configure all needed CSI2 registers:
(i) Set CSI2_COMPLEXIO_CFG[18:16] DATA4_POSITION.
(ii) Set CSI2_COMPLEXIO_CFG[14:12] DATA3_POSITION.
(iii) Set CSI2_COMPLEXIO_CFG[10:8] DATA2_POSITION.
(iv) Set CSI2_COMPLEXIO_CFG[6:4] DATA1_POSITION.
(v) Set CSI2_COMPLEXIO_CFG[2:0] CLOCK_POSITION.
(vi) Set the CONTROL_CAMERA_RX[17:16] CAMERARX_CSI21_CAMMODE.
CAUTION
This must be done before the CSIPHY is active.
70
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2. CSIPHY and link initialization sequence:
(a) Deassert the CSIPHY reset.
(i) Set CSI2_COMPLEXIO_CFG[30] RESET_CTRL to 0x1.
The following registers can be set only after deasserting the CSIPHY reset and before asserting the
FORCERXMODE signal:
• REGISTER0
• REGISTER1
• REGISTER2
(b) Assert the FORCERXMODE signal:
(i) Set CSI2_TIMING[15] FORCE_RX_MODE_IO1 to 0x1.
(c) Connect pulldown on link (UP/DN) by asserting the respective PIPD* signals (PIPD* = 0):
For CSI2-A CAMERARX pulldown on signals through padconf registers:
• csi21_dx4:
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[8] CSI21_DX4_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[4]
CSI21_DX4_PULLTYPESELECT = 0x0
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[3]
CSI21_DX4_PULLUDENABLE = 0x1
• csi21_dy4:
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[24] CSI21_DY4_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[20]
CSI21_DY4_PULLTYPESELECT = 0x0
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[19]
CSI21_DY4_PULLUDENABLE = 0x1
• csi21_dx3:
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[8] CSI21_DX3_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[4]
CSI21_DX3_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[3]
CSI21_DX3_PULLUDENABLE = 0x1
• csi21_dy3:
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[24] CSI21_DY3_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[20]
CSI21_DY3_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[19]
CSI21_DY3_PULLUDENABLE = 0x1
• csi21_dx2:
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[8] CSI21_DX2_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[4]
CSI21_DX2_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[3]
CSI21_DX2_PULLUDENABLE = 0x1
• csi21_dy2:
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[24] CSI21_DY2_INPUTENABLE
= 0x1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
71
ISS Interfaces
www.ti.com
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[20]
CSI21_DY2_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY3[19]
CSI21_DY2_PULLUDENABLE = 0x1
• csi21_dx1:
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[8] CSI21_DX1_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[4]
CSI21_DX1_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[3]
CSI21_DX1_PULLUDENABLE = 0x1
• csi21_dy1:
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[24] CSI21_DY1_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[20]
CSI21_DY1_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[19]
CSI21_DY1_PULLUDENABLE = 0x1
• csi21_dx0:
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[8] CSI21_DX0_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[4]
CSI21_DX0_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[3]
CSI21_DX0_PULLUDENABLE = 0x1
• csi21_dy0:
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[24] CSI21_DY0_INPUTENABLE
= 0x1
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[20]
CSI21_DY0_PULLTYPESELECT= 0x0
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[19]
CSI21_DY0_PULLUDENABLE = 0x1
(d) Power up the CSIPHY:
(i) Set CSI2_COMPLEXIO_CFG[28:27] PWR_CMD to 0x1.
(e) Check whether the state status reaches the ON state:
• CSI2_COMPLEXIO_CFG[26:25] PWR_STATUS = 0x1
(f) Wait for STOPSTATE = 1 (for all enabled lane modules):
(i) The timer is set through the CSI2_TIMING[14:0] bit field. The reset value can be kept.
(ii) Wait until CSI2_TIMING[15] FORCE_RX_MODE_IO1 = 0x0. It is automatically put at 0 when
all enabled lanes are in STOPSTATE and the timer is finished.
(g) Release PIPD* (= 1).
For CSI2-A CAMERARX pullup on signals through padconf registers:
• csi21_dx4:
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[4]
CSI21_DX4_PULLTYPESELECT = 0x1
• csi21_dy4:
– CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[20]
CSI21_DY4_PULLTYPESELECT = 0x1
• csi21_dx3:
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[4]
72
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
CSI21_DX3_PULLTYPESELECT = 0x1
csi21_dy3:
– CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[20]
CSI21_DY3_PULLTYPESELECT = 0x1
• csi21_dx2:
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[4]
CSI21_DX2_PULLTYPESELECT = 0x1
• csi21_dy2:
– CONTROL_CORE_PAD0_CSI21_DX2_PAD1_CSI21_DY2[20]
CSI21_DY2_PULLTYPESELECT = 0x1
• csi21_dx1:
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[4]
CSI21_DX1_PULLTYPESELECT = 0x1
• csi21_dy1:
– CONTROL_CORE_PAD0_CSI21_DX1_PAD1_CSI21_DY1[20]
CSI21_DY1_PULLTYPESELECT = 0x1
• csi21_dx0:
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[4]
CSI21_DX0_PULLTYPESELECT = 0x1
• csi21_dy0:
– CONTROL_CORE_PAD0_CSI21_DX0_PAD1_CSI21_DY0[20]
CSI21_DY0_PULLTYPESELECT = 0x1
3. The CSIPHY is initialized and ready/active in CSI2 mode.
•
2.3.2.3
ISS CSI PHY Error Signals
In D-PHY mode, the CSIPHY supports the following error detection and signaling to the associated
receiver:
• ERRSOTHS: Flags 1-bit errors in the HS start of transmission synchronization pattern. In this error
scenario, the CSIPHY continues to receive the data and pass it to the receiver, but confidence in the
data may be low, because of the 1-bit error seen in sync. This signal, if asserted, is high for one cycle
of RXBYTECLKHS.
• ERRSOTSYNCHS: Flags multiple bit errors in the HS start of transmission synchronization pattern. In
this case, the CSIPHY cannot achieve proper synchronization and does not pass the received data to
the receiver. This signal, if asserted, is high for one cycle of RXBYTECLKHS.
• ERRCONTROL: Flags the control sequence error; that is, when the LP sequence observed on line is
not recognized as a valid control sequence. This signal, if asserted, is high until the next change in the
state of the LP line.
• ERRESC: Flags the escape entry error; that is, when the escape entry sequence is unrecognized. This
signal, if asserted, is high until the next change in the state of the LP line.
• ERRSYNCESC: Flags the low-power data transmission synchronization error. This error is flagged if
the number of bits received during a low-power data transmission is not a multiple of 8 bits. This
signal, if asserted, is high until the next change in the state of the LP line. In case the number of
received bits is 1 less than a multiple of 8, RXVALIDESC is also asserted together with
ERRSYNCESC, and an erroneous data byte is output on RXDATAESC. In other cases of this error,
RXVALIDESC is not asserted and an erroneous data byte is not sent out.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
73
ISS Interfaces
2.3.3
www.ti.com
ISS CSI2 PHY Registers
Table 29 lists the CSI2 PHY instance.
Table 29. ISS CSI2 PHY Instance Summary
Module Name
Base Address
Cortex-M3 Private Access
Base Address
L3 Interconnect
Size
0x5504 1170
0x5C00 1170
32 bytes
ISS_CAMERARX_CORE1
Table 30 summarizes the ISS CSI2 PHY register mapping.
Table 30. ISS CSI2 PHY Registers Mapping Summary
Register Name
2.3.3.1
Type
Register
Width
(Bits)
Address Offset
ISS_CAMERARX_CORE1
Base Address
Cortex-M3 Private
Access
ISS_CAMERARX_CORE1
Base Address
L3 Interconnect
REGISTER0
RW
32
0x0000 0000
0x5504 1170
0x5C00 1170
REGISTER1
RW
32
0x0000 0004
0x5504 1174
0x5C00 1174
REGISTER2
RW
32
0x0000 0008
0x5504 1178
0x5C00 1178
ISS_CSI2_PHY_REGISTER0
Figure 22. ISS_CSI2_PHY_REGISTER0
31
25
24
23
16 15
8
7
0
Reserved
HSCLOCKCONFIG
Reserved
THS_TERM
THS_SETTLE
R-0
R/W-0
R-0
R/W-0x24
R/W-0x27
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. ISS_CSI2_PHY_REGISTER0 Field Descriptions
Bit
31-25
24
Field
Value
Reserved
HSCLOCKCONFIG
Description
Reserved
0h
Disable clock missing detector
23-16
Reserved
15-8
THS_TERM
4h
THS_TERM timing parameter in multiples of DDR clock
Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay +
combinational routing delay ~ (1–2)* DDRCLK + THS-TERM + ~ (1 –15) ns
Programmed value = ceil(12.5 / DDR clock period) –1
7-0
THS_SETTLE
27h
THS_SETTLE timing parameter in multiples of DDR clock frequency
Effective THS_SETTLE seen on line (starting to look for sync pattern) = synchronizer delay +
timer delay + LPRX delay + combinational routing delay – pipeline delay in HS data path. ~
(1–2)* DDRCLK + THS-SETTLE + ~ (1–15) ns –1*DDRCLK
Programmed value = ceil(90 ns / DDR clock period) + 3
74
Imaging Subsystem (ISS)
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.3.3.2
ISS_CSI2_PHY_REGISTER1
Figure 23. ISS_CSI2_PHY_REGISTER1
31
30
29
28
27
26
25
24
18
17
16
Reserved
RESET_DONE_
STATUS
Reserved
CLOCK_MISS_
DETECTOR_STATUS
TCLK_TERM
DPHY_HS_SYNC_
PATTERN
R-0
R-0x0
R-0
R-0
R/W-0x00
R/W-0xB8
15
10
9
8
7
0
DPHY_HS_SYNC_PATTERN
CTRLCLK_DIV_
FACTOR
TCLK_SETTLE
R/W-0xB8
R/W-0x1
R/W-0x0E
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. ISS_CSI2_PHY_REGISTER1 Field Descriptions
Bit
Field
Value
Description
31-30
Reserved
Reserved
29-28
RESET_DONE_
STATUS
Reset done read bits.
28: RESETDONERXBYTECLK Note: BYTECLK is provided to the ISS CSI2-A
29: RESETDONECTRLCLK Note: This is the CAM_PHY_CTRL_FCLK provided to the PHY
from the PRCM module.
27-26
25
24-18
Reserved
CLOCK_MISS_
DETECTOR_
STATUSW
TCLK_TERM
Reserved
Clock missing detector
0h
Clock missing detector successful
1h
Error in clock missing detector.
0h
TCLK_TERM timing parameter in multiples of CTRLCLK
Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay +
combinational routing delay ~ (1–2)* CTRLCLK + TCLK_TERM + ~ (1–15) ns
Programmed value = ceil(9.5 / CTRLCLK period) – 1
17-10
DPHY_HS_SYNC_
PATTERN
B8h
DPHY mode HS sync pattern in byte order (reverse of received order) See ISS CSI PHY Error
Signals.
9-8
CTRLCLK_DIV_
FACTOR
1h
Divide factor for CTRLCLK for CLKMISS detector
7-0
TCLK_SETTLE
Eh
TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock
Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational
routing delay ~ (1–2)* CTRLCLK + Tclk-settle + ~ (1 –15) ns
Programmed value = max[3, ceil(155 ns/CTRLCLK period) –1]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
75
ISS Interfaces
2.3.3.3
www.ti.com
ISS_CSI2_PHY_REGISTER2
Figure 24. ISS_CSI2_PHY_REGISTER2
31
30
29
28
27
26
25
24
23
16
TRIGGER_CMD_
RXTRIGESC0
TRIGGER_CMD_
RXTRIGESC1
TRIGGER_CMD_
RXTRIGESC2
TRIGGER_CMD_
RXTRIGESC3
Reserved
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R-0
15
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. ISS_CSI2_PHY_REGISTER2 Field Descriptions
Bit
31-30
Field
TRIGGER_CMD_
RXTRIGESC0
29-28
TRIGGER_CMD_
RXTRIGESC1
27-26
TRIGGER_CMD_
RXTRIGESC2
25-24
23-0
76
TRIGGER_CMD_
RXTRIGESC3
Value
Description
Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0
0h
Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1
0h
Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2
0h
Mapping of Trigger escape entry command to PPI output RW 0x0 RXTRIGGERESC3
0h
Reserved
Imaging Subsystem (ISS)
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.4
ISS Stall Controller Integration
Figure 25 is a top-level block diagram of the Stall controller interface. The stall controller can get its data
from memory using a dedicated interface read master port.
Figure 25. ISS Stall Controller Integration
ISS
ISS interfaces and
interconnects
Read
Write
128b to 64b
+ config
ISS
interconnect
SC
ISS IRQ merger
SC_IRQ[8]
VP
STANDBY
hardware
handshake
STALL
CBUFF
ISP
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
EOF
ISS_FCLK
CAM_PHY_CTRL_FCLK
PRCM
TCTRL
Imaging Subsystem (ISS)
77
ISS Interfaces
2.5
www.ti.com
ISS SC Functional Description
Figure 26 is the top-level block diagram of the Stall controller. The SC can also read data from memory
getting burst packets from the BTE. For read data from memory, see Section 2.5.3, ISS SC Memory Read
Channel.
The Staller controller video port interface is connected to the video preprocessing hardware.
Figure 26. ISS SC Receiver Block Diagram
VP
Interface
A-Law
decode
Unpacking
VP_HS
VP_VS
VP_DATA[15:0]
VP_PCLK
DPCM
decode
DPCM
encode
F
I
F
O
Packing
To BTE
SC_CTRL[4] MODE
From BTE
DPCM
encode
2.5.1
Video
port
ISS SC VP Interface
Table 34 summarizes the video interface signals. The video interface connects the Stall controller module
to the video preprocessing hardware (ISP). The interface is connected to a 16-bit video port. On the other
side of the video port is the ISIF inside of the ISP. The ISIF also uses the signals listed in Table 34 to
synchronize pixel data sent to it by the Stall controller.
Table 34. ISS SC Video interface Signals
(1)
Pin
Type (1)
VP_HS
O
Line trigger output signal
VP_VS
O
Frame trigger output signal
VP_DATA[15:0]
O
Parallel output data: bits 0 to 15
VP_PCLK
O
Video port pixel clock. The frequency can
be configured.
VP_STALL
I
Stalls data flow
Description
I = Input; O = Output
When data is sent to the video port, the data flow can be stalled by asserting the VP_STALL signal. Doing
so does not overflow internal FIFOs: the SC module adapts its read rate automatically.
The response time to the VP_STALL signal must not exceed two cycles: when VP_STALL is asserted, the
SC module can send 0, 1, or 2 pixels to the video port.
VP_STALL is asserted and deasserted synchronous to the functional clock.
The pixel clock is generated from the functional clock. Clock pulses are gated based on the selected clock
division factor and pixel availability. In other words, software must set the Stall controller to ensure that the
pixel clock:
• Never exceeds what the ISP can support: the top value set in the SC_CTRL[31:15] FRACDIV bit field
• Is sent only when valid pixels or blanking data must be sent
78
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Also, software must set the number of clock pulses during horizontal blanking periods using the
SC_CTRL1[1:0] BLANKING bit field.
• The Stall controller stops generating horizontal blanking clock pulses when the number of pulses
defined in the SC_CTRL1[1:0] BLANKING bit field are generated.
• The Stall controller ensures that the number of horizontal blanking pulses defined in the
SC_CTRL1[1:0] BLANKING bit field is received. The Stall controller stops generating horizontal
blanking clock pulses when then number of pulses defined in the SC_CTRL1[1:0] BLANKING bit field
is generated.
NOTE:
To work properly, the ISP requires a minimum of eight clock cycles in the horizontal
blanking period and a minimum of 16 lines in the vertical blanking period. The pixel clock can
be gated only when these intervals are respected. This is required to flush the pipeline of the
different ISP modules. Figure 27 shows VP_PCLK gating during blanking periods.
Figure 27. ISS SC VP_PCLK Gating During Blanking Periods
Vertical blanking clock gating
VD
[
...
]
16 lines required
PCLK
Gated clock
Horizontal blanking clock gating
HD
8 clock cycles required
PCLK
Gated clock
Vertical blanking generation is controlled through the SC_CTRL[9] VP_CLK_FORCE_ON bit. The
VP_PCLK clock is enabled during vertical blanking periods when this bit is set. This pushes pixels through
the ISP processing pipe. It is needed, for example, when the ISP resizer uses the averager. Otherwise,
hardware ensures only that at least four clock pulses are generated before the first pixel of each frame. It
may be necessary for the clock to keep running after the frame end to flush internal pipelines. In that case,
an interrupt request (IRQ) or status bit is typically present in the attached hardware that indicates when
the VP_PCLK clock is no longer needed (for example, an end of processing interrupt). The module leaves
the vertical blanking state when new data is received from the memory read channel.
The configured pixel clock is used for active and blanking periods.
Table 35 shows how RAW and YUV data is sent over the video port. The data is sent to the ISIF if ISP is
used. For the ISIF details about video port data, see Section 3 ISS: ISP.
Table 35. ISS SC Video Port Data Mapping
Format
Video Port DATA[15:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RAW6
0
0
0
0
0
0
0
0
0
0
R5
R4
R3
R2
R1
R0
RAW7
0
0
0
0
0
0
0
0
0
R6
R5
R4
R3
R2
R1
R0
RAW8
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
RAW10
0
0
0
0
0
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
RAW12
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
RAW14
0
0
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
RAW16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
79
ISS Interfaces
www.ti.com
Table 35. ISS SC Video Port Data Mapping (continued)
Format
Video Port DATA[15:0]
YUV4:2:2
2.5.2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
U7
U6
U5
U4
U3
U2
U1
U0
0
0
0
0
0
0
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
0
0
0
0
0
0
0
0
V7
V6
V5
V4
V3
V2
V1
V0
0
0
0
0
0
0
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
ISS SC Data Compression
The data compression technique used is DPCM and A-Law.
The Stall controller performs on-the-fly compression and decompression. The compressed/decompressed
data is passed to the video preprocessing hardware or stored in memory.
The data compression method is lossy and does not require any information outside the current
encoded/decoded line. This means that all the image lines can be encoded and decoded separately.
Two different predictors are used:
• The simple predictor
This predictor uses only the previous same color component value as a prediction value. Therefore,
only 2-pixel memory is required.
• The advanced predictor
This predictor uses four previous pixel values, when the prediction value is evaluated. This means that
also the other color component values are used, when the prediction value is defined.
The preferable use is that the simple predictor is used with 10 bits to 8 bits or 12 bits to 8 bits conversion
(10810 or 12812) and the advanced predictor is used with 10 bits to 7 bits and 10 bits to 6 bits
conversions (10710 and 10610). The advanced predictor gives slightly better prediction for pixel value;
thus, the image quality can be improved with it. Because the simple predictor is very simple, the
processing power and memory requirements are reduced with it, when the image quality is already high
enough.
Select the predictor with the SC_LCx_CTRL[10] DPCM_PRED bit.
2.5.3
ISS SC Memory Read Channel
The memory channel can perform the following operations:
• Reads data from memory. It is unpacked and DPCM or A-Law decompressed if necessary.
• Sends data to the video preprocessing hardware
• Sends data back to memory. It can be DPCM or A-Law compressed and packed before it is sent to
memory.
Table 36 summarizes supported modes for memory-to-memory operations.
NOTE: Video port and memory destinations are mutually exclusive.
80
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 36. ISS SC Memory-to-Memory Supported Operations
Memory
Input
Memory Output
RAW
6
RAW
6+PA
CK
RAW
6+DP
CM
RAW RAW RAW
6+PA 6+DP 6+PA
CK+D CM_A CK+D
PCM
DV
PCM_
ADV
RAW
7
RAW
7+PA
CK
RAW
7+DP
CM
RAW RAW RAW
7+PA 7+DP 7+PA
CK+D CM_A CK+D
PCM
DV
PCM_
ADV
RAW
8
RAW
8+DP
CM
RAW RAW
8+DP 8+AL
CM12 AW10
RAW
10
RAW
10+P
ACK
RAW6 +
DPCM
X
X
RAW6 +
PACK +
DPCM
X
X
RAW6 +
DPCM_
ADV
X
X
RAW6 +
PACK +
DPMC_
ADV
X
X
RAW7 +
DPCM
X
X
RAW7 +
PACK +
DPCM
X
X
RAW7 +
DPCM_
ADV
X
X
RAW7 +
PACK +
DPMC_
ADV
X
X
X
X
RAW
12
RAW
12+P
ACK
X
X
RAW
14
RAW
16
RAW6
RAW6 +
PACK
RAW7
RAW7 +
PACK
RAW8
RAW8 +
DPCM
RAW8 +
DPCM1
2
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Imaging Subsystem (ISS)
Copyright © 2013–2016, Texas Instruments Incorporated
81
ISS Interfaces
www.ti.com
Table 36. ISS SC Memory-to-Memory Supported Operations (continued)
Memory
Input
Memory Output
RAW
6
RAW
6+PA
CK
RAW
6+DP
CM
RAW RAW RAW
6+PA 6+DP 6+PA
CK+D CM_A CK+D
PCM
DV
PCM_
ADV
RAW
7
RAW
7+PA
CK
RAW
7+DP
CM
RAW RAW RAW
7+PA 7+DP 7+PA
CK+D CM_A CK+D
PCM
DV
PCM_
ADV
RAW
8
RAW
8+DP
CM
RAW8 +
ALAW1
0
RAW10
X
X
X
X
X
X
X
X
X
RAW10
+ PACK
X
X
X
X
X
X
X
X
X
RAW RAW
8+DP 8+AL
CM12 AW10
RAW
10
RAW
10+P
ACK
X
X
RAW
12
RAW
12+P
ACK
RAW
14
RAW
16
RAW12
RAW12
+ PACK
RAW14
RAW16
82
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 37 summarizes supported modes for memory-to-video port operations.
Table 37. ISS SC Memory-to-Video Port Supported Formats
Memory Input
Video Port Output
RAW6
RAW7
RAW8
RAW10
RAW6
X
RAW6 + PACK
X
RAW6 +DPCM
X
RAW6 + PACK + DPCM
X
RAW6 + DPCM_ADV
X
RAW6 + DPCM_ADV +
PACK
X
RAW7
X
RAW7 + PACK
X
RAW7 + DPCM
X
RAW7 + PACK + DPCM
X
RAW7 + DPCM_ADV
X
RAW7 + DPCM_ADV +
PACK
X
RAW8
X
RAW8 + DPCM
X
RAW8 + DPCM12
RAW12
RAW14
RAW16
X
RAW10
X
RAW10 + PACK
X
RAW12
X
RAW12 + PACK
X
RAW14
X
RAW16
X
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
83
ISS Interfaces
2.5.3.1
www.ti.com
ISS SC Read Data From Memory
Figure 28 shows the data organization in memory.
Figure 28. ISS SC Data Organization in Memory
HS
SC_LCM_SRC_ADDR
SC_LCM_VSIZE
SC_LCM_HSIZE[11:0]
SKIP
SC_LCM_HSIZE[27:16]
COUNT
SC_LCM_SRC_OFST
The user chooses the start address and the line length using the SC_LCM_SRC_ADDR and
SC_LCM_SRC_OFST registers. The image start address normally must point to the beginning of a line
because of packing constraints. However, it does not necessarily point to the first line of the frame in
memory. The SC_LCM_VSIZE[27:16] COUNT bit field specifies the total line count to be read from
memory.
It is also possible to skip a certain pixel count SC_LCM_HSIZE[11:0] SKIP) from the start of the line.
Thus, they are not sent to the video port or back to memory. The SC_LCM_HSIZE[27:16] COUNT bit field
specifies the horizontal size of the image. The pixels after the right boundary of the image are not read
from memory.
When data are sent to the video port, throughput is imposed by the selected VP_PCLK. Otherwise, it is
imposed by the selected interconnect read port clock. The interconnect read rate can be throttled (limiting
the maximum data read speed for memory-to-memory operation) using the SC_LCM_CTRL[4:3]
READ_THROTTLE bit field. Therefore, it is possible to read the unused data at a higher rate than the
used video port data rate. This provides better performance than framing the image in the video
preprocessing hardware.
The data storage format in memory is defined by the SC_LCM_CTRL[18:16] SRC_FORMAT and
SC_LCM_CTRL[23] SRC_PACK bit fields.
Not all I/O format combinations are valid. For more information, see Table 36 and Table 37.
Figure 29 shows how data are packed in memory. Pixel order (left to right in the image) is alphabetical (a,
b, c). Therefore, data storage is little endian.
84
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 29. ISS SC Data Organization Packing in Memory
addr = 3
addr = 2
f
e
1
RAW6
packed
0
5
4
3
2
1
k
0
5
2
1
5
4
0
5
4
3
2
1
3
2
1
0
5
4
3
RAW7
unpacked
RAW8
2
5
4
3
2
1
0
1
0
6
5
4
d
3
d
0s
2
4
3
2
1
4
3
2
1
2
1
0
5
4
5
5
4
3
0
5
4
3
2
1
3
2
1
0
5
4
3
3
a
2
1
0
6
5
0
5
2
1
0
5
4
0
5
4
3
2
1
2
1
0
5
4
4
c
3
2
6
5
1
0
3
2
1
0
2
0
5
4
3
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
4
b
3
2
1
5
4
a
3
2
1
0
4
l
b
0s
4
f
m
c
1
4
g
n
0s
2
0
h
5
k
a
0s
0
6
2
1
0
6
e
5
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
4
d
3
4
c
3
4
b
3
4
a
3
2
1
0
3
2
1
0
4
3
0s
5
6
2
1
0
0s
5
6
d
7
6
5
4
8
7
3
6
9
8
7
2
1
0
7
6
5
4
4
3
2
9
8
7
8
7
4
3
2
9
8
7
p
5
6
8
7
4
3
2
9
1
0
5
4
3
m
1
0
8
1
2
1
0
9
10
9
0
3
1
1
1
9
8
8
0
0s
15
14
13
13
6
2
9
5
8
3
2
9
12
12
4
7
8
0
9
8
7
1
6
8
7
6
5
4
6
5
4
3
2
3
3
0
3
2
1
0
6
5
4
11
10
9
8
2
1
0
11
10
11
10
9
8
7
6
7
b
6
11
11
10
10
9
8
0
1
0
4
3
2
2
1
1
9
8
9
b
8
7
6
2
1
0
7
6
5
4
6
3
2
9
5
8
4
7
4
3
1
2
1
6
0
1
b
0
e
0
1
6
9
8
7
4
3
10
9
3
0
9
8
7
6
2
9
8
7
6
5
4
3
2
9
8
5
4
5
4
3
2
1
0
3
3
2
2
7
1
11
10
1
1
9
8
0s
15
14
13
13
1
0
5
4
3
2
5
4
3
2
6
5
4
3
2
8
7
6
5
4
3
2
1
0
7
6
5
4
7
6
5
4
a
7
3
0
8
6
5
4
11
10
9
8
2
d
1
0
11
10
9
8
f
7
6
5
4
3
2
11
10
9
8
7
e
1
0
3
2
1
0
6
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
a
0s
0
0
9
0
a
c
2
1
h
n
0s
11
2
a
k
5
6
5
c
g
6
4
7
d
d
7
5
0
b
8
4
4
5
0
7
0
9
5
1
f
h
3
5
6
l
e
7
2
5
6
a
1
0s
a
g
i
b
7
0
o
5
4
1
a
3
6
7
h
b
0s
RAW14
4
5
0
g
2
7
b
h
RAW12
unpacked
3
j
f
11
0
p
c
10
1
4
5
6
2
e
k
l
0s
11
5
6
b
5
6
7
l
o
RAW10
unpacked
2
i
m
9
0s
f
5
6
0
b
3
6
j
9
1
c
5
6
2
c
g
RAW16
5
f
3
9
RAW12
packed
0
0
d
RAW10
packed
1
o
e
RAW7
packed
3
b
i
p
3
4
addr = 0
c
j
3
RAW6
unpacked
addr = 1
d
12
12
11
11
10
10
9
8
7
a
6
9
a
8
7
6
Table 38 summarizes the storage reduction versus unpacked format and image width restrictions when
data packing is used. The image width applies to the data width multiple in pixels that must be stored to
have storage reduction. Moreover, because each address is 8 bits long, the percentage shows how many
bits out of 8 are to be packed in the empty space from another pixel address. A pixel is selected and split.
One of the parts is put into another pixel address empty space. When unpacked, each pixel bit is stored
continuously again.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
85
ISS Interfaces
www.ti.com
Table 38. ISS SC Data Packing Benefit and Constraints
Bits Per Pixel
2.5.3.2
Storage Reduction
Width Multiple
(Pixels)
8
25%
16
7
8
13%
3
8
8
0%
4
RAW10
10
16
38%
16
RAW12
12
16
25%
8
Packed
Unpacked
RAW6
6
RAW7
RAW8
ISS SC Memory Read Port Burst Generation
Hardware always uses the largest possible burst size according to the setup. The amount of data read
from memory can be higher than what is actually used by the Stall controller. Only full 64-bit burst words
are read back from memory. Figure 30 shows the data organization and the relationship between the
different parameters controlling the burst generation.
Figure 30. ISS SC Data Organization in Memory
SC_LCM_CTRL[7:5] BURST_SIZE
SC_LCM_PREFETCH[13:3] HWORDS
FST[31:5] OFST
SC_LCM_VSIZE[27:16]
COUNT
1
5
1
3
2
6
3
7
4
8
Maximum allowed burst size used
Smaller burst used
Read data
Un
Unused data
NOTE:
•
•
A minimum burst size of 2 must be selected for correct operation.
The HWORDS bit field must be even for correct operation.
The SC_LCM_SRC_ADDR register address of the first data to read is aligned to a 32-byte boundary. The
read port fetches SC_LCM_PREFETCH[13:3] HWORDS of 64-bit words per line using the longest
possible burst computed from the SC_LCM_CTRL[7:5] BURST_SIZE bit field and the remaining data to
be fetched. Burst size of 128 bytes is preferred. When the Stall controller is configured to fetch more data
than required, extra data are dropped internally.
86
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.3.3
ISS SC Video Port
The video port always receives unpacked data. It can be enabled using the SC_LCM_CTRL[2]
DST_PORT bit. Its clock can be selected with the SC_LCM_CTRL[31:15] FRACDIV bit field and gated or
not during frame blanking periods using the SC_LCM_CTRL[9] VP_CLK_FORCE_ON bit.
The data format used by the video port is defined by the SC_LCM_CTRL[26:24] DST_FORMAT bit field.
For a list of supported modes, see Table 37.
2.5.3.4
ISS SC Encode, Pack, and Store Data
This stage is used only when data are sent to memory. Memory destination is selected using the
SC_LCM_CTRL[2] DST_PORT bit. The output data format is defined by the SC_LCM_CTRL[26:24]
DST_FORMAT bit field and the SC_LCM_CTRL[31] DST_PACK bit. Not all possible combinations are
supported; see Table 39 for details.
The destination address and offset for the output data of the memory channel are set by the
SC_LCM_DST_ADDR and SC_LCM_DST_OFSTC registers.
Because of alignment constraints on the interconnect port, the output image width restrictions in Table 39
apply.
Table 39. ISS SC Output Width Restrictions in Memory-to-Memory Operation
Format
Bits per Pixel
Width Multiple of (1)
RAW6
8
1
RAW6 packed
6
1
RAW7
8
1
RAW7 packed
7
1
RAW8
8
1
RAW10
16
1
RAW10 packed
10
16
RAW12
16
1
RAW12 packed
12
8
(1)
Note
Full 32-bit words are written at
the end of the line. This last
word can eventually include 0s.
Same constraints as RAW8
In continuous mode, lines must be multiples of 128 bits. In 2D mode, lines must start on 128-bit boundaries.
For example, when RAW6 packed data are written to memory, any output width is allowed. However, only
full 32-bit words are written to memory. This eventually overwrites some data in memory at the end of a
line.
The supported output width is restricted for packed RAW10 and RAW12 data because of the particular bit
ordering in those formats (see Figure 29).
When the DST_OFST bit is set to 0, start of lines are aligned on 4-byte boundaries. When DST_OFST is
not set to 0, data are aligned on 32-byte boundaries.
2.5.3.5
ISS SC DPCM Decompression History
The DPCM compression algorithm can encode the difference between consecutive samples in a line
instead of the actual samples value to reduce the amount of data to store. The drawback is that lines must
always be decoded from the beginning (the first samples of a line are always encoded as PCM).
The Stall controller has a mechanism to preserve the DPCM decode history for each line to avoid
decoding the same samples multiple times when vertical frame division mode is used.
The typical use case (also known as vertical frame division mode) is when an image is wider than the ISP
can process on the fly, but the image must be processed. Therefore, the image is cut into multiple vertical
slices that are processed sequentially by the ISP. The slices are stitched together in the SDRAM through
proper address generation in the ISP. Because of various alignment constraints in the ISP, the slices must
overlap. Without preserving the DPCM history, all lines from the beginning of the second (and other
consecutive) vertical slice would have to be recoded, which would lead to performance degradation.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
87
ISS Interfaces
www.ti.com
Writing DPCM history information into the system memory is enabled by setting the
SC_LCM_HISTORY[16] EN_HIST_WR bit. The SC_LCM_HISTORY[15:0] HIST_EXPORT bit field defines
the position at which history data is written to memory. The position is counted from the beginning line.
The first decoded pixel has position 0. The last decoded pixel has position SC_LCM_HSIZE[14:0] SKIP +
SC_LCM_HSIZE [30:16] COUNT. The SC_LCM_HISTORY [15:0] HIST_EXPORT bit field is used to
choose the resume position and allows support of overlapping vertical slices. History data is written to the
SDRAM at ADDR = SC_LCM_DST_ADDR[31:5] ADDR + Y × 8 bytes (where Y is the line number). The
Stall controller always writes 8 bytes of history data per line to the SDRAM regardless of the chosen
DPCM format. The Stall controller receiver uses the interface bursts to send history data to memory.
DPCM history data holds the decoded value of four samples. The Stall controller exports samples of
positions:
• SC_LCM_HISTORY[15:0] HIST_EXPORT – 3
• SC_LCM_HISTORY[15:0] HIST_EXPORT – 2
• SC_LCM_HISTORY[15:0] HIST_EXPORT – 1
• SC_LCM_HISTORY[15:0] HIST_EXPORT
Every sample is coded on 16 bits, and several MSBs are unused. The valid range for SC_LCM_HISTORY
[15:0] HIST_EXPORT is [3.. SC_LCM_HSIZE[14:0] SKIP + SC_LCM_HSIZE[30:16] COUNT – 1]. History
data can be exported even when data is not sent to the video port (SC_LCM_HISTORY[15:0]
HIST_EXPORT SC_LCM_HSIZE14:0] SKIP is valid).
2.5.3.6
ISS SC Programming Model
This section describes the programming model of the Stall controller
2.5.3.7
ISS SC Reset Behavior
On hardware or software reset of the ISS, all registers in the Stall controller are reset to their reset value.
2.5.3.8
ISS SC Video Port
Table 40 lists the procedure to configure the video port.
Table 40. ISS SC Configure Video Port
88
Step
Bit Field
Value
Set the video port output frequency. It varies from
ISS_FLCK down to ISS_FLCK/65,536 MHz.
SC_CTRL[31:15] FRACDIV
From 1 to 65,536
Enable video port clock during vertical blanking
periods or not.
SC_CTRL[9] VP_CLK_FORCE_ON
0x0: The video port clock is
gated during vertical blanking
periods.
0x1: The video port clock is
free-running during vertical
blanking periods.
Controls whether the video-port output is the only
output interface enabled and applies for all
channels. When SC_CTRL[11] VP_ONLY_EN =
0x1, the data are output only to the video port; the
interface master port is not used.
SC_CTRL[11] VP_ONLY_EN
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 40. ISS SC Configure Video Port (continued)
Step
Bit Field
Value
Control the video port pixel clock polarity:
(Recommended setting: rising edge)
SC_CTRL[12] VP_CLK_POL
0x0: The Stall controller writes
the data on the video port on
the pixel-clock falling edge.
The module connected to the
video port samples the data on
the pixel clock rising edge.
0x1: The Stall controllerr writes
the data on the video port on
the pixel-clock rising edge. The
module connected to the video
port samples the data on the
pixel clock falling edge.
Figure 31 shows the settings
for SC_CTRL.VP_CLK_POL.
Figure 31 shows the settings for SC_CTRL.VP_CLK_POL.
Figure 31. SC_CTRL.VP_CLK_POL Settings
PCLK
DATA[11:0]
DATA[11:0]
2.5.3.9
DAT0
DAT1
DAT0
VP_CLK_POL = 0x1
DAT2
DAT1
DAT2
VP_CLK_POL = 0x0
ISS SC Memory Read Channel
2.5.3.9.1
ISS SC Read Data From Memory
Table 41 lists the procedure to configure read data from memory.
Table 41. ISS SC Configure Read Data From Memory
Step
Bit Field
Value
SC_CTRL[0] IF_EN
0x0
SC_CTRL[3] FRAME
0x1
Configure the burst size to 16 × 64-bit bursts.
SC_LCM_CTRL[7:5] BURST_SIZE
0x4
Configure the source data format, location, and
framing.
In addition to the SC_LCM_HSIZE[11:0] SKIP and
SC_LCM_HSIZE[27:16] COUNT bit fields, firmware
must specify the amount of data to be fetched from
memory. This value is set in 64-bit word steps and
must be a multiple of 32 bytes (four words of 64 bits).
The value is computed with the following formula:
SC_LCM_CTRL, SC_LCM_HSIZE, SC_LCM_VSIZE,
SC_LCM_PREFETCH, SC_LCM_SRC_ADDR,
SC_LCM_SRC_OFST
HWORDS = 4 × ceil( ((SKIP + COUNT) x
bits_per_pixel)/(8 × 32) )
(1)
The SC_LCM_SRC_ADDR and
SC_LCM_SRC_OFST registers must be aligned on
32-byte boundaries for correct operation. For best
performance, both registers must be aligned on 256byte boundaries. See the example following this table.
Select destination.
SC_LCM_CTRL[2] DST_PORT
If destination = video port, configure clock frequency
and its gating during frame blanking periods.
SC_CTRL[31:15] FRACDIV,
SC_CTRL[9] VP_CLK_FORCE_ON
0x0: Video port
0x1: Memory
If needed, configure READ_THROTTLE to reduce the SC_LCM_CTRL[4:3] READ_THROTTLE
bandwidth in memory-to-memory operation to prevent
system overload. It has no effect when data are sent
to the video port (controlled by video port clock in this
case).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
89
ISS Interfaces
www.ti.com
Table 41. ISS SC Configure Read Data From Memory (continued)
Step
Bit Field
If the memory write port is used, the destination
format and address must be configured.
SC_LCM_DST_ADDR, SC_LCM_DST_OFST
Value
Enable memory read channel. After processing a full
frame, this bit is automatically cleared by hardware
and an EOF event is triggered.
SC_LCM_CTRL[0] CHAN_EN
0x1
Example:
• SC_LCM_CTRL[7:5] BURST_SIZE is set to 16 × 64 bits
• SC_LCM_HSIZE[11:0] SKIP = 0
• SC_LCM_HSIZE[27:16] COUNT = 1000
• SC_LCM_CTRL[23] SRC_PACK = YES
• SC_LCM_CTRL[18:16] SRC_FORMAT = RAW6
• SC_LCM_PREFETCH[13:3] HWORDS = 96 (=94)
Setting the size to 94 produces the following burst sequence: 16, 16, 16, 16, 16, 8, and 4 (7
interconnect requests). However, when it is set to 96, the burst sequence is 6 × 16 (6 interconnect
requests).
90
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4
ISS SC Registers
Table 42 lists the SC instance.
Table 42. ISS SC Instance Summary
Module Name
Base Address
Cortex-M3 Private Access
Base Address
L3 Interconnect
Size
0x5504 1C00
0x5C00 1C00
512 bytes
ISS_SC
Table 43 lists the ISS SC registers.
Table 43. ISS SC Registers Mapping Summary
Register Name
Type
Register
Width
(Bits)
Address Offset
ISS_SC
Base Address
Cortex-M3 Private
Access
ISS_SC
Base Address
L3 Interconnect
SC_REVISION
R
32
0x0000 0000
0x5504 1C00
0x5C00 1C00
SC_SYSCONFIG
RW
32
0x0000 0004
0x5504 1C04
0x5C00 1C04
SC_SYSSTATUS
R
32
0x0000 0008
0x5504 1C08
0x5C00 1C08
0x0000 000C 0x0000 0018
0x5504 1C0C 0x5504 1C18
0x5C00 1C0C 0x5C00 1C18
Reserved
SC_LCM_IRQENABLE
RW
32
0x0000 002C
0x5504 1C2C
0x5C00 1C2C
SC_LCM_IRQSTATUS
RW
32
0x0000 0030
0x5504 1C30
0x5C00 1C30
SC_CTRL
RW
32
0x0000 0040
0x5504 1C40
0x5C00 1C40
Reserved
W
32
0x0000 0044
0x5504 1C44
0x5C00 1C44
SC_GNQ
R
32
0x0000 0048
0x5504 1C48
0x5C00 1C48
SC_CTRL1
RW
32
0x0000 004C
0x5504 1C4C
0x5C00 1C4C
Reserved
RW
32
0x0000 0050 0x0000 0078
0x5504 1C50 0x5504 1C78 +
(x * 0x30)
0x5C00 1C50 0x5C00 1C78 +
(x * 0x30)
SC_LCM_CTRL
RW
32
0x0000 01D0
0x5504 1DD0
0x5C00 1DD0
SC_LCM_VSIZE
RW
32
0x0000 01D4
0x5504 1DD4
0x5C00 1DD4
SC_LCM_HSIZE
RW
32
0x0000 01D8
0x5504 1DD8
0x5C00 1DD8
SC_LCM_PREFETCH
RW
32
0x0000 01DC
0x5504 1DDC
0x5C00 1DDC
SC_LCM_SRC_ADDR
RW
32
0x0000 01E0
0x5504 1DE0
0x5C00 1DE0
SC_LCM_SRC_OFST
RW
32
0x0000 01E4
0x5504 1DE4
0x5C00 1DE4
SC_LCM_DST_ADDR
RW
32
0x0000 01E8
0x5504 1DE8
0x5C00 1DE8
SC_LCM_DST_OFST
RW
32
0x0000 01EC
0x5504 1DEC
0x5C00 1DEC
SC_LCM_HISTORY
RW
32
0x0000 01F0
0x5504 1DF0
0x5C00 1DF0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Imaging Subsystem (ISS)
91
ISS Interfaces
2.5.4.1
www.ti.com
SC_Revision
Figure 32. SC_REVISION Register (1)
31
0
REVISION
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
TI internal data
Table 44. SC_REVISION Register Field Descriptions
Bit
Field
31-0
Value
REVISION
2.5.4.2
Description
IP Revision
SC SYSCONFIG
Table 45. SC_SYSCONFIG
Physical Address
0x5504 1C04
0x5C00 1C04
Description
SYSCONFIG REGISTER
Type
RW
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
RESERVED
Bits
Field Name
31:14
RESERVED
13:12
MSTANDBY_MODE
9
8
MSTANDBY_MODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
7
6
5
4
3
2
RESERVED
Description
Sets the behavior of the master port power management
signals.
Type
Reset
R
0x00000
RW
0x0
1
0
AUTO_IDLE
0x0000 0004
SOFT_RESET
Address Offset
0x0: Force-standby. MStandby is only asserted when the
module is disabled.
0x1: No-standby. MStandby is never asserted.
0x2: Smart-standby: MStandby is asserted based on the
activity of the module. The module will try to go to
standby during the vertical blanking period.
11:2
1
RESERVED
SOFT_RESET
Software reset. Set the bit to 1 to trigger a module reset.
The bit is automatically reset by the hardware. During
reads return 0.
R
0x000
RW
0
RW
1
0x0: Normal mode.
0x1: The module is reset
0
AUTO_IDLE
Internal OCP clock gating strategy.
0x0: OCP clock is free-running.
0x1: Automatic OCP clock gating strategy is applied
based on the OCP interface activity.
92
Imaging Subsystem (ISS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4.3
SC SYSSTATUS
Table 46. SC_SYSSTATUS
0x0000 0008
Physical Address
0x5504 1C08
0x5C00 1C08
Description
SYSSTATUS REGISTER
Type
R
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_SC_CORTEX-M3
ISS_SC_L3
9
8
7
6
5
4
3
2
1
RESERVED
Bits
Field Name
Description
Type
Reset
31:1
RESERVED
Write 0's for future compatibility.
Reads returns 0.
R
0x0000 0000
RESET_DONE
Internal reset monitoring
R
1
0
0
RESET_DONE
Address Offset
Read 0x1: Reset completed.
Read 0x0: Internal module reset is on going.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
93
ISS Interfaces
2.5.4.4
www.ti.com
SC LCM IRQENABLE
Table 47. SC_LCM_IRQENABLE
Address Offset
0x0000 002C
Physical Address
0x5504 1C2C
0x5C00 1C2C
Description
INTERRUPT ENABLE REGISTER - Memory channel
This register regroups all the events related to the memory channel 2. The events related to memory
channel trigger SINTERRUPTN[8]. The channel shall be enabled for events to be generated on that
channel.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
Bits
Field Name
31:2
RESERVED
1
LCM_OCPERROR
Description
An interconnect error has been returned for a read
(interconnect read master) or write (interconnect write
master) transaction related to LCM operation
1
0
LCM_EOF
ISS_SC_CORTEX-M3
ISS_SC_L3
LCM_OCPERROR
Instance
Type
Reset
R
0x0000 0000
RW
0
RW
0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
0
LCM_EOF
Memory read channel - End of frame
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
94
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4.5
SC LCM IRQSTATUS
Table 48. SC_LCM_IRQSTATUS
Address Offset
0x0000 0030
Physical Address
0x5504 1C30
0x5C00 1C30
Description
INTERRUPT STATUS REGISTER - Memory channel
This register regroups all the events related to memory channel. The events related to memory channel
trigger SINTERRUPTN[8]. The channel shall be enabled for events to be generated on that channel.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
Bits
Field Name
31:2
RESERVED
1
Description
LCM_OCPERROR
An interconnect error has been returned for a read
(interconnect read master) or write (interconnect write
master) transaction related to LCM operation
Type
Reset
1
0
LCM_EOF
ISS_SC_CORTEX-M3
ISS_SC_L3
LCM_OCPERROR
Instance
R
0x0000 0000
RW
W1toClr
0
RW
W1toClr
0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
0
LCM_EOF
Memory read channel - End of frame
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
2.5.4.6
SC CTRL
Table 49. SC_CTRL
Address Offset
0x0000 0040
Physical Address
0x5504 1C40
0x5C00 1C40
Description
GLOBAL CONTROL REGISTER
This register controls the Stall controller. This register shall not be modified dynamically (except IF_EN
bit field).
Type
RW
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
BURST
5
4
3
2
1
0
Reserved
6
RESERVED
7
RESERVED
8
FRAME
9
MODE
RESERVED
VP_ONLY_EN
VP_CLK_POL
FRACDIV
DBG_EN
POSTED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
ISS_SC_CORTEX-M3
ISS_SC_L3
VP_CLK_FORCE_ON
Instance
95
ISS Interfaces
Bits
www.ti.com
Field Name
Description
Type
Reset
31:15
FRACDIV
Fractional clock divider control for the video port.
The mean video port clock is VPBASECLOCK *
FRACDIV/65536.
Valid range: 1-65536
RW
0x10000
14
POSTED
Selects between posted and non posted writes.
RW
0
RW
0
RW
0
RW
0
0x0: Non posted
0x1: Posted
13
DBG_EN
Enables the debug mode.
0x0: Disable
0x1: Enable
12
VP_CLK_POL
VP clock polarity
0x0: The Stall controller writes the data on the VP on the
L3 falling edge before the next falling PCLK edge.
0x1: The Stall controller writes the data on the VP on the
L3 rising edge before the next rising PCLK edge.
11
VP_ONLY_EN
VP only enable.
0x0: The VP is enabled and the OCP master port are
enabled.
0x1: The VP is enabled and the OCP master port is
disabled.
The embedded data and pixel data are output on the VP.
10
RESERVED
Read returns reset value
RW
0
9
VP_CLK_FORCE_ON
Controls VP_PCLK gating during frame blanking periods.
RW
0
0x0: The VP_PCLK is gated during vertical blanking
periods.
0x1: The VP_PCLK is free-running during vertical
blanking periods.
8
7:5
RESERVED
BURST
Forces the write burst size used by the module.
The write burst size shall never exceed the output FIFO
size. The output FIFO size can be read with the
SC_GNQ.FIFODEPTH bit field.
R
0
RW
0x0
0x0: 1x 64-bit burst = single request.
0x1: 2x 64-bit bursts.
0x3: 8x 64-bit bursts.
0x4: 16x 64-bit bursts.
0x2: 4x 64-bit bursts.
4
MODE
0x1: SC compatible mode
RW
0
3
FRAME
Set the modality in which IF_EN works.
RW
0
0x0: When software writes IF_EN = 0 the interface is
disabled immediately.
0x1: When software writes IF_EN = 0 the interface is
disabled after the next FEC sync code.
96
2
RESERVED
Read returns reset value
RW
0
1
RESERVED
Read returns reset value
RW
0
0
Reserved
R
0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4.7
SC GNQ
Table 50. SC_GNQ
Address Offset
0x0000 0048
Physical Address
0x5504 1C48
0x5C00 1C48
Description
GENERIC PARAMETER REGISTER
This register provide a way to read the generic parameters used in the design.
Type
R
8
7
6
RESERVED
Bits
Field Name
31:6
RESERVED
5
4:2
Description
5
4
3
2
1
0
NBCHANNELS
9
FIFODEPTH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_SC_CORTEX-M3
ISS_SC_L3
OCPREADPORT
Instance
Type
Reset
R
0x0000000
OCPREADPORT
The OCP master read port, the DPCM encoder and
ALAW decompression are only present when this bit is
set.
R
1
FIFODEPTH
Output FIFO size in multiple of 64 bits.
R
0x5
R
0x2
Read 0x0: 2 x 64 bits
Read 0x1: 4 x 64 bits
Read 0x2: 8 x 64 bits
Read 0x3: 16 x 64 bits
Read 0x4: 32 x 64 bits
Read 0x5: 64 x 64 bits
1:0
NBCHANNELS
Number of logical channels supported by the module.
Read 0x0: 1 logical channel
Read 0x1: 2 logical channels
Read 0x2: 4 logical channels
Read 0x3: 8 logical channels
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
97
ISS Interfaces
2.5.4.8
www.ti.com
SC CTRL1
Table 51. SC_CTRL1
0x0000 004C
Physical Address
0x5504 1C4C
0x5C00 1C4C
Description
GLOBAL CONTROL REGISTER (2)
This register controls the Stall controller.
Type
RW
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
LEVH
RESERVED
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LEVL
Bits
Field Name
Description
31
RESERVED
Reserved
LEVH
Controls generation of MFlag[1:0]:
30:24
9
8
7
6
5
4
3
2
1
0
BLANKING
Address Offset
RESERVED
Type
Reset
RO
Rreturns
0s
0
RW
0x00
RO
Rreturns
0s
0
00: FIFO_LEV=LEVL
01: Unused
10: LEVLFIFO_LEV and FIFO_LEV=LEVH
11: LEVHFIFO_LEV
Allowed values 0..FIFO_SIZE.
23
22:16
RESERVED
Reserved
LEVL
Controls generation of MFlag[1:0]:
RW
00:FIFO_LEV=LEVL
0X00
01: Unused
10: LEVLFIFO_LEV and FIFO_LEV=LEVH
11: LEVHFIFO_LEV
Allowed values 0..FIFO_SIZE.
15:2
RESERVED
Reserved
1:0
BLANKING
Controls the number of clock pulses provided during
vertical and horizontal clock periods.
When the blanking period provided by the camera is
lower than the value set here, the blanking period is
shortened by the Stall controller to prevent internal FIFO
overflow. Software must increase the sensor blanking
period in that case.
RO
Rreturns
0s
0x0000
RW
0x0
0x0: 4 video port clock cycles
0x1: 16 video port clock cycles
0x2: 64 video port clock cycles
0x3: Free running
98
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4.9
SC LCM_CTRL
Table 52. SC_LCM_CTRL
Address Offset
0x0000 01D0
Physical Address
0x5504 1DD0
0x5C00 1DD0
Description
Control register for the memory channel. It defines the data format of the source frame stored in
memory and how this frame is processed.
Type
RW
RESERVED
Bits
Field Name
Description
31
DST_PACK
Data is packed before it is sent to memory.
Applies to RAW6, RAW7, RAW10, and RAW12 only.
7
6
5
4
3
2
1
0
CHAN_EN
8
RESERVED
SRC_FORMAT
9
READ_THROTTLE
SRC_DECOMPR
SRC_DPCM_PRED
SRC_PACK
DST_FORMAT
RESERVED
DST_COMPR
DST_PACK
DST_DPCM_PRED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DST_PORT
ISS_SC_CORTEX-M3
ISS_SC_L3
BURST_SIZE
Instance
Type
Reset
RW
0
RW
0
RW
0x0
0x0: Disabled
0x1: Enabled
30
DST_DPCM_PRED
Selects the DPCM predictor to be used for the
RAW6+DPCM10 and RAW7+DPCM10 data formats.
The RAW8+DPCM10 data format always use the simple
predictor.
0x0: The advanced predictor is used
0x1: The simple predictor is used.
29:28
DST_COMPR
Enables data compression of data sent to memory
0x0: No compression
0x1: A-Law compression
RAW10 - RAW8 A-Law when DST_FORMAT=RAW8
other destination formats are invalid.
0x2: DPCM compression
RAW10 - RAW6 DPCM when DST_FORMAT=RAW6
RAW10 - RAW7 DPCM when DST_FORMAT=RAW7
RAW10 - RAW8 DPCM when DST_FORMAT=RAW8
other destination formats are invalid.
27
26:24
RESERVED
DST_FORMAT
Output format selection.
Not every combination between input and output formats
are possible.
R
0
RW
0x0
RW
0
0x0: RAW6
0x1: RAW7
0x2: RAW8
0x3: RAW10
0x4: RAW12
0x5: RAW14
0x6: RAW16
23
SRC_PACK
Data stored in memory is packed and must be unpacked.
0x0: Disabled
0x1: Enabled
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
99
ISS Interfaces
Bits
22
www.ti.com
Field Name
Description
SRC_DPCM_PRED
Selects the DPCM predictor to be used for the
RAW6+DPCM10, RAW7+DPCM10 and RAW8+DPCM12
data formats.
The RAW8+DPCM10 and RAW6 + DPCM12 data format
always use the simple predictor.
Type
Reset
RW
0
RW
0x0
RW
0x0
0x0: The advanced predictor is used
0x1: The simple predictor is used.
21:20
SRC_DECOMPR
Enable decompression of incoming data
0x0: No decompression
0x1: A-Law decompression
RAW8 A-Law - RAW10 when SRC_FORMAT=RAW8
other source formats are invalid.
0x3: DPCM decompression
RAW6 DPCM - RAW12 when SRC_FORMAT=RAW6
RAW8 DPCM - RAW12 when SRC_FORMAT=RAW8
other source formats are invalid.
0x2: DPCM decompression
RAW6 DPCM - RAW10 when SRC_FORMAT=RAW6
RAW7 DPCM - RAW10 when SRC_FORMAT=RAW7
RAW8 DPCM - RAW10 when SRC_FORMAT=RAW8
other source formats are invalid.
19:16
SRC_FORMAT
Data format of the data stored in memory.
As there is no header embedded in the data sent to
memory the user is responsible of choosing the adequate
format.
0x0: RAW6.
0x1: RAW7
0x2: RAW8
0x3: RAW10
0x4: RAW12
0x5: RAW14
0x6: RAW16
0x7: Reserved
0x8: Reserved
0x9: Reserved
0xA: Reserved
0xB: Reserved
0xC: Reserved
0xD: Reserved
0xE: Reserved
0xF: Reserved
15:8
RESERVED
7:5
BURST_SIZE
Defines the burst size of the master read port
R
0x00
RW
0x0
RW
0x0
0x0: 1x 64-bit burst = single request.
0x1: 2x 64-bit bursts.
0x3: 8x 64-bit bursts.
0x4: 16x 64-bit bursts.
0x2: 4x 64-bit bursts.
4:3
READ_THROTTLE
Limit maximum data read speed for memory to memory
operation
0x0: Full speed. Throughput is limited by internal
processing capabilities.
0x1: 1/2 speed
0x3: 1/8 speed
0x2: 1/4 speed
100
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
Field Name
Description
2
DST_PORT
Select the destination port
Type
Reset
RW
0
R
0
RW
0
0x0: Data is send to video port, it is always send without
compression or packing. The DST_COMPR,
DST_DPCM_PRED, DST_PACK,
SC_LCM_DST_WRITE, and SC_LCM_DST_OFST
registers have no effect.
0x1: Data is send to memory.
1
RESERVED
0
CHAN_EN
Enables the read from memory channel.
Before enabling the memory read channel software shall:
Read from memory starts as soon as this bit is set,
therefore all SC_LCM_x registers must be configured
correctly before.
This bit is cleared by hardware at the end of the frame.
0x0: Disabled
0x1: Enabled
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
101
ISS Interfaces
2.5.4.10
www.ti.com
SC LCM VSIZE
Table 53. SC_LCM_VSIZE
Address Offset
0x0000 01D4
Physical Address
0x5504 1DD4
0x5C00 1DD4
Description
Memory channel vertical framing register
Type
RW
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNT
Bits
Field Name
31:29
RESERVED
28:16
COUNT
15:0
RESERVED
2.5.4.11
9
8
7
6
5
4
3
2
1
0
1
0
RESERVED
Description
Defines the line count to be read from memory.
From 1 to 8191 lines.
Type
Reset
R
0x0
RW
0x0001
R
0x0000
SC LCM HSIZE
Table 54. SC_LCM_HSIZE
0x0000 01D8
Physical Address
0x5504 1DD8
0x5C00 1DD8
Description
Memory read channel horizontal framing register.
Type
RW
COUNT
Bits
Field Name
31
RESERVED
30:16
15
14:0
102
COUNT
14
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
RESERVED
31
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
13 12 11 10
9
8
RESERVED
30
Address Offset
6
5
4
3
2
SKIP
Description
Type
Reset
R
0x0
Horizontal count of samples to output after the skipped
pixels.
Valid values: 1 to 32767.
RW
0x0001
R
0x0
Horizontal count of samples to skip after the start of the
line.
When DPCM compressed data is read from memory
using this feature is the only valid way to set a horizontal
starting position.
Valid values: 0 to 32767.
0 disables pixel skipping
RW
0x0000
RESERVED
SKIP
7
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4.12
SC LCM_PREFETCH
Table 55. SC_LCM_PREFETCH
Address Offset
0x0000 01DC
Physical Address
0x5504 1DDC
0x5C00 1DDC
Description
This register defines the amount of data to be fetched from memory.
It must be consistent with the SC_LCM_HSIZE register (check programming model).
Type
RW
14 13 12 11 10
RESERVED
Bits
Field Name
31:16
RESERVED
15:3
HWORDS
2:0
RESERVED
2.5.4.13
ISS_SC_CORTEX-M3
ISS_SC_L3
9
8
7
6
5
4
3
2
1
0
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
15
Instance
HWORDS
Description
64 bit words to read from memory for each line of the
image.
Possible values 1..8191
Type
Reset
R
0x0000
RW
0x0001
R
0x0
SC_LCM_SRC_ADDR
Table 56. SC_LCM_SRC_ADDR
Address Offset
0x0000 01E0
Physical Address
0x5504 1DE0
0x5C00 1DE0
Description
Memory channel source address register
This register sets the 32-bit memory address where the pixel data are stored.
The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary.
Type
RW
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_SC_CORTEX-M3
ISS_SC_L3
9
8
7
6
ADDR
Bits
Field Name
Description
31:5
ADDR
27 most-significant bits of the 32-bit address
4:0
RESERVED
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x00
103
ISS Interfaces
2.5.4.14
www.ti.com
SC_LCM_SRC_OFST
Table 57. SC_LCM_SRC_OFST
Address Offset
0x0000 01E4
Physical Address
0x5504 1DE4
0x5C00 1DE4
Description
Memory channel source offset register.
This register sets the offset, which is applied on the source address after each line is read from memory.
For example, it enables to perform 2D data transfers of the pixel data from a frame buffer. In such case,
the pixel data and frame buffer data shall have the same data format.
The 5 LSBs are ignored: the offset shall be a multiple of 32 bytes.
Type
RW
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
OFST
Bits
Field Name
Description
31:5
OFST
Line offset programmed in bytes.
If OFST = 0, the data is read contiguously from memory.
Otherwise, OFST sets the source offset between the first
pixel of the previous line and the first pixel of the current
line.
4:0
RESERVED
2.5.4.15
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x00
SC_LCM_DST_ADDR
Table 58. SC_LCM_DST_ADDR
Address Offset
0x0000 01E8
Physical Address
0x5504 1DE8
0x5C00 1DE8
Description
Memory channel destination address.
This register sets the 32-bit memory address where the pixel data are stored.
The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary.
Type
RW
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
ADDR
Bits
Field Name
Description
31:5
ADDR
27 most significant bits of the 32-bit address.
4:0
RESERVED
104
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x00
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.5.4.16
SC_LCM_DST_OFST
Table 59. SC_LCM_DST_OFST
Address Offset
0x0000 01EC
Physical Address
0x5504 1DEC
0x5C00 1DEC
Description
Memory channel destination offset register.
This register sets the offset, which is applied on the destination address after each line is written to
memory.
For example, it enables to perform 2D data transfers of the pixel data into a frame buffer. In such case,
the pixel data and frame buffer data shall have the same data format.
The 5 LSBs are ignored: the offset shall be a multiple of 32 bytes.
Type
RW
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_SC_CORTEX-M3
ISS_SC_L3
9
8
7
6
OFST
Bits
Field Name
Description
31:5
OFST
Line offset programmed in bytes.
If OFST = 0, the data is written contiguously to memory if
possible. At the end of a line only full 32 bit words will be
written, creating eventually gaps at the end of lines.
Otherwise, OFST sets the destination offset between the
first pixel of the previous line and the first pixel of the
current line.
4:0
RESERVED
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x00
105
ISS Interfaces
2.5.4.17
www.ti.com
SC_LCM_HISTORY
Table 60. SC_LCM_HISTORY
Address Offset
0x0000 01F0
Physical Address
0x5504 1DF0
0x5C00 1DF0
Description
Controls operation of the DPCM history read/write feature
Type
RW
Instance
ISS_SC_CORTEX-M3
ISS_SC_L3
RESERVED
Bits
Field Name
31:18
RESERVED
17
EN_HIST_RD
EN_HIST_WR
EN_HIST_RD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HIST_EXPORT
Description
Enable DPCM history read
Type
Reset
R
0x0000
RW
0
RW
0
RW
0x0000
0x0: Disable
0x1: Enable
16
EN_HIST_WR
Enable DPCM history write
0x0: Disable
0x1: Enable
15:0
106
HIST_EXPORT
Defines the horizontal position at which DPCM history
information is written.
The first decoded sample of a line has position 0
The last decoded sample has position SKIP+COUNT–1
Valid range [3..SKIP+COUNT–1]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6
ISS CSI2
2.6.1
ISS CSI2 Environment
2.6.1.1
ISS CSI2 Protocol and Data Format
The CSI2 supports MIPI CSI2 multiple data type formats. This section describes MIPI CSI2 protocol and
data formats. The CSI2 is compatible with the MIPI CSI2 Specification v1.0-01-00 r0.03. Table 61 lists the
MIPI CSI2 supported by CSI2 formats in addition to JPEG8. Shading in the MIPI CSI2-defined formats
indicates special format extensions of the CSI2 receiver.
Table 61 summarizes the pixel formats supported by the CSI2 receiver interface.
Table 61. ISS CSI2 Pixel Format Modes
CSI2_CTX_CT
RL2_i[9:0]
Format
CSI2 Data Format
Bits per Pixel (BPP) Data Size Increases
in Memory
2D Mode
Availability
0x18
YUV4:2:0 8 bit
12
0%
Yes
0x19
YUV4:2:0 10 bit
12
0%
Yes
0x1E
YUV4:2:2 8 bit
16
0%
Yes
0x1F
YUV4:2:2 10 bit
16
0%
Yes
0x22
RGB565
16
0%
Yes
0x24
RGB888
24
0%
Yes
0x29
RAW7
7
0%
Yes
0x2A
RAW8
8
8%
Yes
0x2B
RAW10
10
0%
Yes
0x2C
RAW12
12
0%
Yes
0x2D
RAW14
14
0%
Yes
0xA3
RGB666 + EXP32
32
77%
Yes
0x68
RAW6 + EXP8
8
33%
Yes
0x69
RAW7 + EXP8
8
14%
Yes
0xA0
RGB444 + EXP16
16
33%
Yes
Comments
0xA1
RGB555 + EXP16
16
6%
Yes
0xAB
RAW10 + EXP16
16
60%
Yes
0xAC
RAW12 + EXP16
16
33%
Yes
0xAD
RAW14 + EXP16
16
14%
Yes
0xE3
RGB666 + EXP32
32
77%
Yes
0xE4
RGB888 + EXP32
32
33%
Yes
0x2A8
RAW6 + DPCM10 +
EXP16
16
166%
Yes
DPCM
decompression
0x229
RAW7 + DPCM10 +
EXP16
16
128%
Yes
DPCM
decompression
0x2AA
RAW8 + DPCM10 +
EXP16
16
100%
Yes
DPCM
decompression
0x369
RAW7 + DPCM12 +
EXP16
16
128%
Yes
DPCM
decompression
0x36A
RAW8 + DPCM12 +
EXP16
16
100%
Yes
DPCM
decompression
0x3A8
RAW6 + DPCM12 +
EXP16
16
166%
Yes
DPCM
decompression
0x12
JPEG8
8
0%
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
107
ISS Interfaces
www.ti.com
For more information about how the data formats are transmitted and how the data are stored in memory,
see Section 2.6.1.1.4, CSI2 Operating Modes.
NOTE: The VP formats are not included in Table 61, because they are not sent to memory; instead
they are sent to the ISP for further processing.
NOTE: Data written by CSI2 can be read back by the SC read channel. For more information about
supported memory operations, see Table 36.
2.6.1.1.1
ISS CSI2 Physical Layer
The CSI2-A receiver is tightly connected to a PHY layer (for more information about the PHY, see
Section 2.3, ISS CSI2 PHY). Table 62 lists the CSI2-A receiver I/O. The CSI2_RECEIVER provides
access to the complex I/O register through a serial configuration port interface. The CSI2_RECEIVER can
access up to eight 32-bit registers in complex I/O.
Table 62. ISS CSI2-A I/O Description
I/O (1)
Signal Name
csi2a_dx0
Description
lane 0
(position 1)
I
Serial data/clock input
lane 1
(position 2)
I
Serial data/clock input
lane 2
(position 3)
I
Serial data/clock input
lane 3
(position 4)
I
Serial data/clock input
lane 4
(position 5)
I
Serial data input only
csi2a_dy0
csi2a_dx1
csi2a_dy1
csi2a_dx2
csi2a_dy2
csi2a_dx3
csi2a_dy3
csi2a_dx4
csi2a_dy4
(1)
I = Input
NOTE: The serial lane can be used as clock lane or data lane (excluding lane 4 on the CSI2-A I/O).
The MIPI CSI2 protocol requires one clock lane (others are data lane or unused lane).
Lanes support the two operating modes:
• HS mode: High-speed transmit mode
• Off mode: Lane is off.
108
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.2
ISS CSI2 Lane Merger
The layer consists of lane merger logic to merge the incoming serial stream into a byte stream. The lane
merger can merge up to four lanes (CSI2-A) into a single byte stream. The bits are sent with the LSB first.
The order of the lanes at the CSI2-A receiver core depends on the lane configuration. The merger is not
used for a single lane.
The number of lanes and their configuration can be changed only in ULPM or when all data lanes are in
off mode.
Figure 33 to Figure 36 show the byte position into each serial link for one to four data lane configurations.
The byte stream always starts from lane 1. It finishes on one of the lanes, depending on the number of
bytes to receive and the number of lanes.
Figure 33. ISS CSI2 One Data-Lane Configuration
Data
lane 1
ULPM
SoT
Byte 0
Byte 1
Key:
ULPM: Ultralow-power mode
Byte 2
Byte N–3 Byte N–2 Byte N–1
SoT: Start of transmission
EoT
ULPM
EoT: End of transmission
Figure 34. ISS CSI2 Two Data-Lane Merger Configuration
The number of bytes, N, is an integer multiple of the number of lanes (2).
Data
lane 1
All data lanes finish at the
e same time.
me.
ULPM
SoT
Byte 0
Byte 2
Byte 4
Byte N–6 Byte N–4 Byte N–2
EoT
ULPM
ULPM
SoT
Byte 1
Byte 3
Byte 5
Byte N–5 Byte N–3 Byte N–1
EoT
ULPM
U
Data
lane 2
The number of bytes, N, is not an integer multiple of the number of lanes
es (2).
Data
lane 1
Data lane 2 finishes 1 byte earlier than lane 1.
ULPM
SoT
Byte 0
Byte 2
Byte 4
Byte N–5 Byte N–3 Byte N–1
ULPM
SoT
Byte 1
Byte 3
Byte 5
Byte N–4 Byte N–2
EoT
ULPM
Data
lane 2
Key:
ULPM: Ultralow-power mode
SoT: Start of transmission
EoT
ULPM
EoT: End of transmission
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
109
ISS Interfaces
www.ti.com
Figure 35. ISS CSI2 Three Data-Lane Merger Configuration
Number of bytes, N, transmitted is an integer multiple of the number of data lanes:
All data lanes finish at the
e same time.
Data
lane 1:
LPS
SoT
Byte 0
Byte 3
Byte 6
Byte N–9 Byte N–6 Byte N–3
EoT
LPS
LPS
SoT
Byte 1
Byte 4
Byte 7
Byte N–8 Byte N–5 Byte N–2
EoT
LPS
LPS
SoT
Byte 2
Byte 5
Byte 8
Byte N–7 Byte N–4
EoT
LPS
Data
lane 2:
Data
lane 3:
Number of bytes, N, transmitted is not an integer multiple of the number of data lanes (Example 1):
Data lanes 2 and 3 finish 1 byte earlier than data lane 1.
Data
lane 1:
LPS
SoT
Byte 0
Byte 3
Byte 6
Byte N–7
LPS
SoT
Byte 1
Byte 4
Byte 7
Byte N–6 Byte N–3
EoT
LPS
SoT
Byte 2
Byte 5
Byte 8
Byte N–5 Byte N–2
EoT
Byte N–4 Byte N–1
Data
lane 2:
Data
lane 3:
EoT
LPS
LPS
LPS
Number of bytes, N, transmitted is not an integer multiple of the number of data lanes (Example 2):
Data lanes 2 and 3 finish 1 byte earlier than data lane 1.
Data
lane 1:
LPS
SoT
Byte 0
Byte 3
Byte 6
Byte N–8 Byte N–5 Byte N–2
EoT
LPS
LPS
SoT
Byte 1
Byte 4
Byte 7
Byte N–7 Byte N–4 Byte N–1
EoT
LPS
LPS
SoT
Byte 2
Byte 5
Byte 8
Byte N–7
Data
lane 2:
Data
lane 3:
Key:
LPM: Low-power mode
110
Byte N–3
SoT: Start of transmission
EoT
LPS
EoT: End of transmission
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 36. ISS CSI2 Four Data-Lane Merger Configuration
Number of bytes, N, transmitted is not an integer multiple of the number of data lanes:
Data
lane 1:
All data lanes finish at the same time.
LPS
SoT
Byte 0
Byte 4
Byte 8
Byte N–12 Byte N–8 Byte N–4
EoT
LPS
LPS
SoT
Byte 1
Byte 5
Byte 9
Byte N–11 Byte N–7 Byte N–3
EoT
LPS
L
LPS
SoT
Byte 2
Byte 6
Byte 10
Byte N–10 Byte N–6 Byte N–2
EoT
LPS
LPS
SoT
Byte 3
Byte 7
Byte 11
Byte N–9 Byte N–5 Byte N–1
EoT
LPS
Data
lane 2:
Data
lane 3:
Data
lane 4:
Number of bytes, N, transmitted is not an integer multiple of the number of data lanes:
Data
lane 1:
Data lanes 2, 3, and 4 finish 1 byte earlier than data lane 1.
LPS
SoT
Byte 0
Byte 4
Byte 8
Byte N–9 Byte N–5 Byte N–1
LPS
SoT
Byte 1
Byte 5
Byte 9
Byte N–8 Byte N–4
LPS
SoT
Byte 2
Byte 6
Byte 10
EoT
LPS
SoT
Byte 3
Byte 7
Byte 11
EoT
EoT
LPS
Data
lane 2:
EoT
LPS
Data
lane 3:
LPS
Data
Key:
LPS: Low-power mode
2.6.1.1.3
SoT: Start of transmission
LPS
EoT: End of transmission
ISS CSI2 Protocol Layer
The low-level protocol (LLP) is a byte-oriented protocol from the lane merger layer. It supports short and
long packet formats.
The CSI2 protocol layer defines how image-sensor data is transported onto the physical layer.
The feature set of the protocol layer implemented by the CSI2 receiver is:
• Transport of arbitrary data (payload-independent)
• 8-bit word size
• Support for up to four interleaved virtual channels on the same link
• Special packets for frame-start, frame-end, line-start, and line-end information
• Descriptor for the type, pixel depth, and format of application-specific payload data
• Error-correction code (ECC) for 1-bit error correction or 2-bit error detection in the header
• 16-bit checksum code for payload error detection
Figure 37 shows the CSI2 protocol layer with short and long packets.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
111
ISS Interfaces
www.ti.com
Figure 37. ISS CSI2 Protocol Layer With Short and Long Packets
Long
packet
Short
packet
ST SP ET
ULPM
ST PH
Data
Long
packet
PF ET
ULPM
Data
ST PH
Shortt
packet
PF ET
ULPM
ST SP ET
Key:
ST: Start of transmission
PH: Packet header
ULPM: Ultralow-power mode
ET: End of transmission
PF: Packet footer
SP: Short packet
Two packets are always separated from each other with a sequence of ET, ULPM, and ST.
2.6.1.1.3.1 ISS CSI2 Short Packet
A short packet is identified by data types 0x00 to 0x0F. A short packet can be used for frame or line
synchronization or for generic data. Figure 38 shows the structure of a short packet.
ECC
Short packet
data field
Data ID
Figure 38. ISS CSI2 Short Packet Structure
32-bit short packet (SP)
Data type (DT) = 0x99 - 0x0F
For frame-synchronization data types, the short packet data field is the frame number. For linesynchronization data types, the short packet data field is the line number. For generic short packet data
types, the content of the short packet data field is user-defined.
The 16-bit frame number, when used, is always nonzero to distinguish it from the use case where the
frame number is inoperative and remains set to 0. The behavior of the 16-bit frame number is one of the
following:
• The frame number is always 0 and is inoperative.
• The frame number increments by 1 for every FS packet within the same virtual channel and is
periodically reset to 1 (1, 2, 1, 2, 1, 2, 1, 2 or 1, 2, 3, 4, 1, 2, 3, 4).
For LSC and LEC synchronization packets, the short packet data field contains a 16-bit line number. This
line number is the same for the LS and LE packets corresponding to a given line. Line numbers are logical
line numbers and do not necessarily equal physical line numbers. The 16-bit line number, when used, is
always nonzero to distinguish it from the use case where the line number is inoperative and remains set to
0.
The behavior of the 16-bit line number is one of the following:
• The line number is always 0 and is inoperative.
• The line number increments by 1 for every LS packet within the same virtual channel and the same
data type. The line number is periodically reset to 1 for the first LS packet after an FS packet. The
intended use is for progressive scan (noninterlaced) video data streams. The line number must be a
nonzero value.
• The line number increments by the same arbitrary step value greater than 1 for every LS packet within
the same virtual channel and the same data type. The line number is periodically reset to a nonzero
arbitrary start value for the first LS packet after an FS packet. The arbitrary start value can be different
between successive frames. The intended use is for interlaced video data streams.
112
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The ECC byte allows single-bit errors to be corrected and 2-bit errors to be detected in the short packet.
Short packets apply to all contexts using the same virtual channel ID (up to eight contexts support eight
dedicated configurations of virtual channel ID and data types). The data type associated with the context
is not used to distinguish which context is used when receiving short packets.
2.6.1.1.3.2 ISS CSI2 Long Packet
A
•
•
•
long packet is identified by data types 0x10 to 0x37. A long packet consists of three elements:
A 32-bit packet header (PH)
An application-specific data payload with a variable number of 8-bit data words
A 16-bit packet footer (PF)
The packet header is composed of three elements:
• An 8-bit data identifier
• A 16-bit word count field
• An 8-bit ECC
The packet footer has one element, a 16-bit checksum.
Figure 39 and Table 63 show the structure of a long packet.
32-bit
packet
header
(PH)
Packet data:
Length = word count (WC) × data word
width (8 bits). There are no restrictions
on the values of the data words.
16-bit
Checksum
Data WC-1
Data WC-2
Data WC-3
Data 2
Data 1
Data 0
ECC
Word count
(WC)
Data ID
Figure 39. ISS CSI2 Long Packet Structure
16-bit
packet
footer
(PF)
Table 63. ISS CSI2 Long Packet Structure Description
Packet Part
Field Name
Size (Bits)
Header
Data ID
8
Contains the virtual channel identifier and the data-type information
Word count
16
Number of data words in the packet data. A word is 8 bits.
ECC
8
ECC for data ID and WC field. Allows 1-bit error recovery and 2-bit
error detection.
Data
Data
WC-8
Footer
Checksum
16
Description
Application-specific payload (WC words of 8 bits)
16-bit CRC for packet data
There are no restrictions on the size of the packet data, but each data format can impose additional
restrictions on the length of the payload data (for example, a multiple of 4 bytes).
2.6.1.1.3.3 ISS CSI2 Data Identifier
The data identifier byte contains the virtual channel (VC) value and the data-type (DT) value, as shown in
Figure 40. The VC value is in the 2 MSBs of the data identifier byte. The DT value is in the 6 LSBs of the
data identifier byte.
Figure 40 shows the data identifier structure.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
113
ISS Interfaces
www.ti.com
Figure 40. ISS CSI2 Data Identifier Structure
Data identifier (DI) byte
B6
B7
B5
B4
B3
B2
VC
DT
Virtual channel
(VC)
Data type
(DT)
B1
B0
Virtual Channel
The CSI2 protocol layer transports virtual channels. Virtual channels are built of frames. A frame can
comprise embedded data and image-sensor data. Two contexts are used to send the two types of data
separately. Each frame is identified by unique mandatory synchronization codes: frame start and frame
end. Line start and line end synchronization codes are optional for the transmitter. A set of registers is
associated with each context defined by the virtual channel ID and the data type. Figure 41 shows a
virtual channel.
Figure 41. ISS CSI2 Virtual Channel
Channel identifier
Channel configuration
Data in
Virtual channel control
Channel 0
Channel
annel
nel
detect
det
Channel 1
Channel 2
Channel 3
2.6.1.1.3.4 ISS CSI2 Synchronization Codes
Data reception from the image-sensor module uses four synchronization codes embedded in the serial
bitstream:
• FSC: Identifies the start of a new frame
• LSC: Identifies the start of a new line; received for every line
• LEC: Identifies the end of a line; received for every line
• FEC: Identifies the end of the last line and the end of the current frame
Table 64 summarizes the synchronization code values.
Table 64. ISS CSI2 Synchronization Codes
114
Synchronization Code
Value
Comments
FSC
0x0
Mandatory
FEC
0x1
Mandatory
LSC
0x2
Optional
LEC
0x3
Optional
Reserved
0x4 to 0x7
Not used
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.3.5 ISS CSI2 Generic Short Packet Codes
When the synchronization code value is from 0x8 to 0xF, the short packet is called a generic short packet.
Short packets are not processed by the camera interface hardware. A generic short packet is stored in a
register without the ECC and an interrupt can be generated. Therefore, generic short packets must be
handled by software.
2.6.1.1.3.6 ISS CSI2 Generic Long Packet Codes
The code value 0x10 indicates null packets, which can be received at any time. They are discarded by the
protocol engine.
The code value 0x11 indicates blanking packets, which can be received at any time. They are discarded
by the protocol engine.
The code value 0x12 indicates embedded 8-bit nonimage data typically used for JPEG.
Code values from 0x13 to 0x17 are reserved.
2.6.1.1.3.7 ISS CSI2 Frame Structure
Each frame consists of short packets to indicate SOF and EOF. Optional short packets for start of line and
end of line can be sent by the image sensor.
Some information before and after the picture data can be sent as SOF and EOF information by the image
sensor to the memory through the L3 port.
For each frame, the pixel data (arbitrary data or user-defined byte data) are valid only after an SOF short
packet. If the data are invalid, they are discarded by the protocol engine.
A frame contains embedded data and image-sensor data. Figure 42 shows where the embedded data and
image-sensor data are in the frame. The frame is scanned in raster order starting from the top-left corner,
as shown in Figure 42 and Figure 43. The following definitions for a frame apply:
• Zero or more SOF status lines (SOF lines) can be embedded at the beginning of a CSI2 frame.
• The image embedded data is carried using separate data types and virtual channels (see
Section 2.6.3.3.4, ISS CSI2 Virtual Channel and Context).
• Zero or more EOF status lines (EOF lines) can be embedded at the end of a CSI2 frame.
• The SOF lines, pixel data, and EOF lines do not overlap.
The CSI2 receiver does not use the information in the status lines. However, it extracts it and stores it in
memory for use by software.
Because the data types are different, the data is carried using separate data types called virtual channels.
Those must be mapped to the adequate context. The CSI2 receiver uses a different context for embedded
data and image-sensor data. See Section 2.6.3.3.4, ISS CSI2 Virtual Channel and Context.
Embedded data is supported as a context by the CSI2 receiver; therefore, there is no specific hardware
support for embedded data.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
115
ISS Interfaces
www.ti.com
Figure 42. ISS CSI2 General Frame Structure (Informative)
Frame blanking
Line blanking
Zero or more lines of embedded data
Packet header (PH)
Packet footer (PF)
FS
Frame of arbitrary pixels and/or
user-defined byte-based data
Zero or more lines of embedded data
FE
Frame blanking
Line blanking
Zero or more lines of embedded data
Packet header (PH)
Packet footer (PF)
FS
Frame of arbitrary pixels and/or
user-defined byte-based data
Zero or more lines of embedded data
FE
Frame blanking
Data per line is a multiple of 8 bits.
Key:
PH: Packet header
FS: Frame start
PF: Packet footer
FE: Frame end
Figure 43 shows the frame structure of a YUV4:2:2 interlaced video frame without embedded data.
116
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 43. ISS CSI2 Digital Interlaced Video Frame (Informative)
Blanking lines
Packet header (PH)
FS
Line start (LS)
FE
Frame 1
(odd, frame number = 1)
YUV4:2:2 image data
Line blanking
Line end (LE)
Packet footer (PF)
Line blanking
FE
Blanking lines
Frame 2
(odd, frame number = 2)
YUV4:2:2 image data
FE
Blanking lines
Data per line is a multiple of 16 bits (YUV4:2:2).
D
Key:
PH: Packet header
FS: Frame start
LS: Line start
PF: Packet footer
FE: Frame end
LE: Line end
The period between the LEC and the new LSC is the line blanking period. The time between the FEC and
the new FSC is the frame blanking period. The receiver works with the line blanking period set to 0. The
image data is stored in memory by selecting one of the various operating modes. Section 2.6.1.1.4, ISS
CSI2 Operating Modes, explains storing image data frames into memory.
2.6.1.1.4
ISS CSI2 Operating Modes
2.6.1.1.4.1 ISS CSI2 YUV Operating Modes
2.6.1.1.4.1.1 ISS CSI2 YUV4:2:0 8-Bit
YUV4:2:0 8-bit data can be stored to memory in little-endian and big-endian format. To set the endianness
for YUV4:2:0 use the CSI2_CTRL[4] ENDIANNESS bit. The line length sent through the CSI2 physical
protocol is a multiple of 16 bits for odd lines and 32 bits for even lines.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
117
ISS Interfaces
www.ti.com
For correct pixel reconstruction, the line length must be a multiple of 32 bits and the number of lines must
be even. Figure 44 shows the storage format for YUV4:2:0 8-bit data. It is shown as little endian. If the
data format is big endian, the figure changes accordingly. Set the CSI2_CTX_CTRL2_i[9:0] FORMAT bit
field to 0x18 to select YUV4:2:0 8-bit mode. Even and odd lines do not have the same length. Offset must
be set accordingly with the CSI2_CTX_DAT_OFST_i[16:5] OFST bit field; for example, if the offset is 0,
the data is written in a contiguous way (bit-to-bit of odd and even lines). If the data has an offset, set the
destination offset between the first pixel of the previous line and the first pixel of the current line being
written to memory.
Figure 44. ISS CSI2 YUV4:2:0 8-Bit
YUV4:2:0 8-bit
Transmitter (odd line)
Y1
Y2
Y3
Y4
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t31
t0
Y5
Y6
Y7
Y8
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t63
t32
Time
Receiver (odd line)
Y4
Y3
Y2
Y1
0
31
d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7
Y8
Y7
Y5
Y6
0
31
FIFO data
memory
organization
h0 h1 h2 h3 h4 h5 h6 h7 g0 g1 g2 g3 g4 g5 g6 g7 f0 f1 f2 f3 f4 f5 f6 f7 e0 e1 e2 e3 e4 e5 e6 e7
Transmitter (even line)
U1
Y1
V1
Y2
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t31
t0
U3
Y3
V3
Y4
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t63
t32
Time
Receiver (even line)
Y2
V1
Y1
U1
0
31
d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7
Y4
V3
Y3
U3
0
31
FIFO data
memory
organization
h0 h1 h2 h3 h4 h5 h6 h7 g0 g1 g2 g3 g4 g5 g6 g7 f0 f1 f2 f3 f4 f5 f6 f7 e0 e1 e2 e3 e4 e5 e6 e7
t0: VP_DATA = [0 0 0 0 0 0 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0]
2.6.1.1.4.1.2 ISS CSI2 YUV4:2:0 10-Bit
YUV4:2:0 10-bit data can be stored to memory in little-endian and big-endian format. The line length sent
through the CSI2 physical protocol is a multiple of 40 bits for odd lines and 80 bits for even lines.
Figure 45 shows the storage format for YUV4:2:0 10-bit data. Set the CSI2_CTX_CTRL2_i[9:0] FORMAT
bit field to 0x19 to select YUV4:2:0 10-bit mode. Even and odd lines do not have the same length. Offset
must be set accordingly with the CSI2_CTX_DAT_OFST_i[16:5] OFST bit field.
118
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 45. ISS CSI2 YUV4:2:0 10-Bit
YUV4:2:0 10-bit
Transmitter (odd line)
Y1[9:2]
Y2[9:2]
Y4[9:2]
Y3[9:2]
a2 a3 a4 a5 a6 a7 a8 a9 b2 b3 b4 b5 b6 b7 b8 b9 c2 c3 c4 c5 c6 c7 c8 c9 d2 d3 d4 d5 d6 d7 d8 d9
t0
t31
Y5[9:2]
Y1[1:0] Y2[1:0]Y3[1:0]Y4[1:0]
Y7[9:2]
Y6[9:2]
a0 a1 b0 b1 c0 c1 d0 d1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f5 f6 f7 f8 f9 g2 g3 g4 g5 g6 g7 g8 g9
t32
t63
Y8[9:2]
Y5[1:0] Y6[1:0]Y7[1:0]Y8[1:0]
Y10[9:2]
Y9[9:2]
h2 h3 h4 h5 h6 h7 h8 h9 e0 e1 f0 f1 g0 g1 h0 h1 I2 I3 I4 I5 I6 I7 I8 I9 J2 J3 J4 J5 J6 J7 J8 J9
t64
t95
Time
Receiver (odd line)
Y4[9:2]
Y3[9:2]
Y1[9:2]
Y2[9:2]
31
0
d9 d8 d7 d6 d5 d4 d3 d2 c9 c8 c7 c6 c5 c4 c3 c2 b9 b8 b7 b6 b5 b4 b3 b2 a9 a8 a7 a6 a5 a4 a3 a2
Y7[9:2]
Y6[9:2]
Y5[9:2]
2]
Y1[1:0] Y2[1:0
Y2[1:0]Y3[1:0]Y4[1:0]
31
0
g9 g8 g7 g6 g5 g4 g3 g2 f9 f8 f7 f6 f5 f4 f3 f2 e9 e8 e7 e6 e5 e4 e3 e2
Y10[9:2]
Y9[9:2]
d0 c1 c1 c1 c1 c1 c1
FIFO data
memory
organization
Y8[9:2]
Y5[1:0] Y6[1:0]Y7[1:0]Y8[1:0]
31
0
J9 J8 J7 J6 J5 J4 J3 J2 I9 I8 I7 I6 I5 I4 I3 I2
h0 g1 g0 f1 f0 e1 e0 h9 h8 h7 h6 h5 h4 h3 h2
Transmitter (even line)
U1[9:2]
Y1[9:2]
Y2[9:2]
V1[9:2]
a2 a3 a4 a5 a6 a7 a8 a9 b2 b3 b4 b5 b6 b7 b8 b9 c2 c3 c4 c5 c6 c7 c8 c9 d2 d3 d4 d5 d6 d7 d8 d9
t0
t31
U3[9:2]
U1[1:0] Y1[1:0]V1[1:0]Y2[1:0]
a0 a1 b0 b1 c0 c1 d0
V3[9:2]
Y3[9:2]
e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f5 f6 f7 f8 f9 g2 g3 g4 g5 g6 g7 g8 g9
t32
t63
Y4[9:2]
U3[1:0] Y3[1:0]V3[1:0]Y4[1:0]
e1
h2 h3 h4 h5 h6 h7 h8 h90e0
Y5[9:2]
U5[9:2]
f0 f1 g0 g1 h0 h1 I2 I3 I4 I5 I6 I7 I8 I9 J2 J3 J4 J5 J6 J7 J8 J9
t64
t95
Time
Receiver (odd line)
Y2[9:2]
V1[9:2]
U1[9:2]
Y1[9:2]
31
0
d9 d8 d7 d6 d5 d4 d3 d2 c9 c8 c7 c6 c5 c4 c3 c2 b9 b8 b7 b6 b5 b4 b3 b2 a9 a8 a7 a6 a5 a4 a3 a2
V3[9:2]
Y3[9:2]
U3[9:2]
Y2[1:0] V1[1:0]Y1[1:0]U1[1:0]
31
0
g9 g8 g7 g6 g5 g4 g3 g2 f9 f8 f7 f6 f5 f4 f3 f2 e9 e8 e7 e6 e5 e4 e3 e2 d1 d0 c1 c0 b1 b0 a1 a0
Y5[9
Y5[9:2]
U5[9:2]
Y4[1:0] V3[1:0]Y3[1:0]U3[1:0]
31
FIFO data
memory
organization
Y4[9:2]
0
J9 J8 J7 J6 J5 J4 J3 J2 I9 I8 I7 I6 I5 I4 I3 I2 h1 h0 g1 g0 f1 f0 e1 e0 h9 h8 h7 h6 h5 h4 h3 h2
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
119
ISS Interfaces
www.ti.com
2.6.1.1.4.1.3 CSI2 YUV4:2:0 8-Bit Legacy
YUV4:2:0 8-bit legacy data can be stored to memory in little-endian and big-endian format. The line length
sent through the CSI2 physical protocol is a multiple of 4 bytes. Figure 46 shows the storage format for
YUV4:2:0 8-bit legacy data. Set the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0x1A to select
YUV4:2:0 8-bit legacy mode.
Figure 46. ISS CSI2 YUV4:2:0 8-Bit Legacy
YUV4:2:0 8-bit legacy
Transmitter (odd line)
U1
Y1
U3
Y2
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t0
t31
Y3
Y4
Y5
U5
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t63
t32
Time
Receiver (odd line)
U1
Y1
U3
Y1
31
0
a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0
Y3
Y4
Y5
U5
31
0
FIFO data
memory
organization
e7 e6 e5 e4 e3 e2 e1 e0 f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g6 g6 g5 g4 h7 h6 h5 h4 h3 h2 h1 h0
Transmitter (even line)
V1
Y1
V3
Y2
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t0
t31
Y3
Y4
Y5
V5
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t32
t63
Time
Receiver (even line)
V1
Y1
V3
Y2
31
0
a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0
Y3
Y4
Y5
V5
31
e7 e6 e5 e4 e3 e2 e1 e0
120
0
FIFO data
memory
organization
f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0 h7 h6 h5 h4 h3 h2 h1 h0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.4.1.4 ISS CSI2 YUV4:2:0 8-Bit + CSPS
YUV4:2:0 8-bit CSPS data can be stored to memory in little-endian and big-endian format. The line length
sent through the CSI2 physical protocol is a multiple of 16 bits for odd lines and 32 bits for even lines.
For correct pixel reconstruction, the line length must be a multiple of 3 32 bits and the number of lines
must be even. Figure 47 shows the storage format for YUV4:2:0 8-bit + CSPS data. Set the
CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0x1C to select YUV4:2:0 8-bit + CSPS mode.
Figure 47. ISS CSI2 YUV4:2:0 8-Bit + CSPS
YUV4:2:0 8-bit + CSPS
Transmitter (odd line)
Y1
Y2
Y4
Y3
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t31
t0
Y5
Y6
Y8
Y7
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2
h4
h6
t63
t32
Time
Rreceiver (odd line)
Y4
Y3
Y1
Y2
0
31
d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
Y8
Y7
Y5
Y6
31
0
h7 h6 h5 h4 h3 h2 h1 h0 g7 g6 g5 g4 g3 g2 g1 g0 f7 f6 f5 f4
FIFO data
memory
organization
e6 e5 e4 e3 e2 e1 e0
Transmitter (even line)
U1
Y2
V1
Y1
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3
c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t0
t31
U3
V3
Y3
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4
g0
Y4
g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t32
t63
Time
Receiver (even line)
Y2
V1
Y1
U1
31
0
d7 d6 d5 d4 d3 d2 d1 d0
c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
c6 c5
Y4
V3
Y3
31
h7 h6 h5 h4 h3 h2
U3
0
h0 g7 g6 g5 g4
FIFO data
memory
organization
g1 g0 f7 f6 f5 f4 f3 f2 f1 f0 e7 e6 e5 e4 e3 e2 e1 e0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
121
ISS Interfaces
www.ti.com
2.6.1.1.4.1.5 Camera ISP CSI2 Byte Swap
The CSI2 receiver incorporates a byte-swapping function. Software can optionally enable byte-swapping
of the payload data by setting the CSI2_CTx_CTRL1[31] BYTESWAP bit. This feature must be used only
when the amount of payload data per packet is a multiple of 16 bits. The byte-swapping is performed
before pixel reconstruction.
Figure 48. Camera ISP CSI2 Byte Swap
ISS CSI2 byte-swap
For example, CSI2_CTx_CTRL2[9:0] FORMAT = RAW8
Transmitter
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t31
t0
Time
Receiver when CSI2_CTx_CTRL1[31] BYTESWAP = 0x0
31
0
d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
FIF
FIFO
data memory
organization
or
Receiver when CSI2_CTx_CTRL1[31] BYTESWAP = 0x1
31
0
c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0
FIFO
data memory
organization
2.6.1.1.4.1.6 ISS CSI2 YUV4:2:0 10-Bit + CSPS
YUV4:2:0 10-bit CSPS data can be stored to memory in little-endian and big-endian format. The line
length sent through the CSI2 physical protocol is a multiple of 40 bits for odd lines and 80 bits for even
lines.
For correct pixel reconstruction, the line length must be a multiple of 3 32 bits and the number of lines
must be even. Figure 49 shows the storage format for YUV4:2:0 10-bit + CSPS data. Set the
CSI2_CTX_CTRL2_i [9:0] FORMAT bit field to 0x1D to select YUV4:2:0 10-bit + CSPS mode.
122
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 49. ISS CSI2 YUV4:2:0 10-Bit + CSPS
YUV4:2:0 10-bit + CSPS
Transmitter (odd line)
Y1[9:2]
Y2[9:2]
Y4[9:2]
Y3[9:2]
a2 a3 a4 a5 a6 a7 a8 a9 b2 b3 b4 b5 b6 b7 b8 b9 c2 c3 c4 c5 c6 c7 c8 c9 d2 d3 d4 d5 d6 d7 d8 d9
t0
t31
Y1[1:0] Y2[1:0]Y3[1:0]Y4[1:0]
Y5[9:2]
Y7[9:2]
Y6[9:2]
a0 a1b0 b1c0 c1d0 d1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f5 f6 f7 f8 f9 g2 g3 g4 g5 g6 g7 g8 g9
t32
t63
Y8[9:2]
Y5[1:0] Y6[1:0]Y7[1:0]Y8[1:0]
Y10[9:2]
Y9[9:2]
h2 h3 h4 h5 h6 h7 h8 h9 e0 e1 f0 f1 g0 g1 h0 h1 I2 I3 I4 I5 I6 I7 I8 I9 J2 J3 J4 J5 J6 J7 J8 J9
t64
t95
Time
Receiver (odd line)
Y4[9:2]
Y3[9:2]
Y1[9:2]
Y2[9:2]
31
0
b8 a7
b7 b6
a6 a5 a4 a3 a2
d9 d8 d7 d6 d5 d4 d3 d2 c9 c8 c7 c6 c5 c4 c3 c2 b9 b8 b7 b6 b5 b4 b3 b2 b9
a9 a8
Y7[9:2]
Y6[9:2]
Y5[9:2]
Y1[1:0] Y2[1:0
Y2[1:0]Y3[1:0]Y4[1:0]
31
0
g9 g8 g7 g6 g5 g4 g3 g2 f9 f8 f7 f6 f5 f4 f3 f2 e9 e8 e7 e6 e5 e4 e3 e2 d1 d0 c1 c0 b1 b0 a1 a0
Y10[9:2]
Y9[9:2]
FIFO data
memory
organization
Y8[9:2]
Y5[1:0] Y6[1:0]Y7[1:0]Y8[1:0]
31
0
e0e0 h9 h8 h7 h6 h5 h4 h3 h2
J9 J8 J7 J6 J5 J4 J3 J2 I9 I8 I7 I6 I5 I4 I3 I2 h1 h0 g1 g0 f1 f0 e1
Transmitter (even line)
U1[9:2]
Y1[9:2]
Y2[9:2]
V1[9:2]
3 c4 c5 c6 c7 c8 c9 d2 d3 d4 d5 d6 d7 d8 d9
a2 a3 a4 a5 a6 a7 a8 a9 b2 b3 b4 b5 b6 b7 b8 b9 c2 c3
t0
t31
U1[1:0] Y1[1:0]V1[1:0]Y2[1:0]
U3[9:2]
V3[9:2]
Y3[9:2]
a0 a1 b0 b1 c0 c1 d0 d1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f5 f6 f7 f8 f9 g2 g3 g4 g5 g6 g7 g8 g9
t32
t63
Y4[9:2]
U3[1:0] Y3[1:0]V3[1:0]Y
Y3[1:0]V3[1:0]Y4[1:0]
Y5[9:2]
U5[9:2]
h2 h3 h4 h5 h6 h7 h8 h9 e0 e1 f0 f1 g0 g1 h0 h1 I2 I3 I4 I5 I6 I7 I8 I9 J2J9J3 J4 J5 J6 J7 J8
t64
t95
Time
eceiver (odd line)
Receiver
Y2[9:2]
V1[9:2]
U1[9:2]
Y1[9:2]
31
0
d9 d8 d7 d6 d5 d4 d3 d2 c9 c8 c7 c6 c5 c4 c3 c2 b9 b8 b7 b6 b5 b4 b3 b2 a9 a8 a7 a6 a5 a4 a3 a2
V3[9:2]
Y3[9:2]
U3[9:2]
Y2[1:0] V1[1:0]Y1[1:0]U1[1:0]
31
0
g9 g8 g7 g6 g5 g4 g3 g2 f9 f8 f7 f6 f5 f4 f3 f2 e9 e8 e7 e6 e5 e4 e3 e2 d1 d0 c1 c0 b1 b0 a1 a0
Y5[9
Y5[9:2]
U5[9:2]
Y4[1:0] V3[1:0]Y3[1:0]U3[1:0]
31
FIFO data
memory
organization
Y4[9:2]
0
J9 J8 J7 J6 J5 J4 J3 J2 I9 I8 I7 I6 I5 I4 I3 I2 h1 h0 g1 g0 f1 f0 e1 e0 h9 h8 h7 h6 h5 h4 h3 h2
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
123
ISS Interfaces
www.ti.com
2.6.1.1.4.1.7 ISS CSI2 YUV4:2:2 8-Bit
YUV4:2:2 data can be stored to memory in little-endian and big-endian format. To set the endianness for
YUV4:2:2 use the CSI2_CTRL[4] ENDIANNESS bit. The line length sent through the CSI2 physical
protocol is a multiple of 32 bits. Figure 50 shows the storage format for YUV4:2:2 8-bit data. Set the
CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0x1E to select YUV4:2:2 8-bit mode.
Figure 50. ISS CSI2 YUV4:2:2 8-Bit
YUV4:2:2 8-bit
Transmitter
U1
Y1
Y2
V1
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t0
t31
U3
Y3
Y4
V3
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t32
t63
Time
Receiver
U1
Y1
Y2
V1
0
31
a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0
U3
Y3
Y4
V3
31
0
e7 e6 e5 e4 e3 e2 e1 e0 f7g2g3
f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4
124
FIFO data
memory
organization
g1 g0 h7 h6 h5 h4 h3 h2 h1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.4.1.8 CSI2 YUV4:2:2 10-Bit
YUV4:2:2 data can be stored to memory in little-endian and big-endian format. The line length sent
through the CSI2 physical protocol is a multiple of 40 bits. Figure 51 shows the storage format for
YUV4:2:2 10-bit data. Set the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0x1F to select YUV4:2:2 10bit mode.
Figure 51. ISS CSI2 YUV4:2:2 10-Bit
YUV4:2:2 10-bit
Transmitter
U1[9:2]
Y1[9:2]
Y2[9:2]
V1[9:2]
a2 a3 a4 a5 a6 a7 a8 a9 b2 b3 b4 b5 b6 b7 b8 b9 c2 c3 c4 c5 c6 c7 c8 c9 d2 d3 d4 d5 d6 d7 d8 d9
t0
t31
U1[1:0] Y1[1:0]V1[1:0]Y2[1:0]
U3[9:2]
V3[9:2]
Y3[9:2]
a0 a1b0 b1c0 c1d0 d1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f5 f6 f7 f8 f9 g2 g3 g4 g5 g6 g7 g8 g9
t32
t63
Y4[9:2]
U3[1:0] Y3[1:0]V3[1:0]Y4[1:0]
Y5[9:2]
U5[9:2]
h2 h3 h4 h5 h6 h7 h8 h9 e0 e1 f0 f1 g0 g1 h0 h1 I2 I3 I4 I5 I6 I7 I8 I9 J2J9J3 J4 J5 J6 J7 J8
t64
t95
Tim
Time
Receiver
Y2[9:2]
V1[9:2]
U1[9:2]
Y1[9:2]
2]
31
0
d9 d8 d7 d6 d5 d4 d3 d2 c9 c8 c7 c6 c5 c4 c3 c2 b9 b8 b7 b6 b5 b4 b3 b2 a9 a8 a7 a6 a5 a4 a3 a2
V3[9:2]
Y3[9:2]
U3[9:2]
Y2[1:0] V1[1:
V1[1:0]Y1[1:0]U1[1:0]
31
0
g9 g8 g7 g6 g5 g4 g3 g2 f9 f8 f7 f6 f5 f4 f3 f2 e9 e8 e7 e6 e5 e4 e3 e2 d1 d0 c1 c0 b1 b0 a1 a0
Y5[9:2]
U5[9:2]
Y4[1:0] V3[1:0]Y3[1:0]U3[1:0]
31
FIFO data
memory
organization
Y4[9:2]
0
e0e0 h9 h8 h7 h6 h5 h4 h3 h2
J9 J8 J7 J6 J5 J4 J3 J2 I9 I8 I7 I6 I5 I4 I3 I2 h1 h0 g1 g0 f1 f0 e1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
125
ISS Interfaces
www.ti.com
2.6.1.1.4.2 ISS CSI2 RGB Operating Modes
2.6.1.1.4.2.1 ISS CSI2 RGB565
RGB565 data is output to memory without data expansion. The line length sent through the CSI2 physical
layer is always a multiple of 16 bits. Figure 52 shows the storage format for RGB565 data. Set the
CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0x22 to select RGB565 mode.
Figure 52. ISS CSI2 RGB565
RGB565
Transmitter
B1[4:0]
G1[5:0]
R1[4:0]
B2[4:0]
G2[5:0]
R2[4:0]
a0 a1 a2 a3 a4 b0 b1 b2 b3 b4 b5 c0 c1 c2 c3 c4 d0 d1 d2 d3 d4 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4
t0
t31
B3[4:0]
G3[5:0]
R3[4:0]
B4[4:0]
G4[5:0]
R4[4:0]
g0 g1 g2 g3 g4 h0 h1 h2 h3 h4 h5 i0 i1 i2 i3 i4 j0 j1 j2 j3 j4 k0 k1 k2 k3 k4 k5 l0 l1 l2 l3 l4
t63 Time
t32
Receiver
R2[4:0
R2[4:0]
G2[5:0]
B2[4:0]
R1[4:0]
G1[5:0]
B1[4:0]
31
0
f4 f3 f2 f1 f0 e5 e4 e3 e2 e1 e0 d4 d3 d2 d1 d0 c4 c3 c2 c1 c0 b5 b4 b3 b2 b1 b0 a4 a3 a2 a1 a0
R4[4:0]
G4[5:0]
B4[4:0]
R3[4:0]
G3[5:0]
B3[4:0]
31
0
FIFO data
memory
organization
l4 l3 l2 l1 l0 k5 k4 k3 k2 k1 k0 j4 j3 j2 j1 j0 i4 i3 i2 i1 i0 h5 h4 h3 h2 h1 h0 g4 g3 g2 g1 g0
126
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.4.2.2 ISS CSI2 RGB888
RGB888 data can be output to memory in two formats: with or without data expansion. If data expansion
is used, the value of the 8 upper bits is programmable and can be set with an alpha value for computer
graphics applications (the CSI2_CTX_CTRL3_i[29:16] ALPHA bit field). Figure 53 shows the storage
format for RGB888 data. Set the CSI2_CTX_CTRL2_i [9:0] FORMAT bit field to 0x24 to select RGB888
mode.
Figure 53. ISS CSI2 RGB888
RGB888
Transmitter
B1
G1
R1
B2
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t0
t31
G2
R2
B3
G3
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t32
t63
Time
Receiver
B2
R1
G1
B1
B
31
0
d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b1 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
G3
B3
R2
G2
31
0
h7 h6 h5 h4 h3 h2 h1 h0 g7 g6 g5 g4 g3 g2 g1 g0 f7 f6 f5 f4 f3 f2 f1 f0 e7 e6 e5 e4 e3 e2 e1 e0
Receiver
R1
G1
FIFO
data memory
organization
without data
expansion
B1
31
0
X X X X X X X X c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
R2
G2
G
31
B2
0
X X X X X X X X f7 f6 f5 f4 f3 f2 f1 f0 e7 e6 e5 e4 e3 e2 e1 e0 d7 d6 d5 d4 d3 d2 d1 d0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
FIFO
data memory
organization
with 32-bit data
expansion
127
ISS Interfaces
www.ti.com
2.6.1.1.4.2.3 ISS CSI2 RGB666
RGB666 data is always output to memory with data expansion. The value of the 14 upper bits is
programmable and can be set with an alpha value for computer graphics applications (the
CSI2_CTX_CTRL3_i[29:16] ALPHA bit field). The line length sent through the CSI2 physical protocol is a
multiple of 8 bits. Furthermore, the line length is a multiple of 9 × 8 bits to finish the pixel reconstruction
correctly. Figure 54 shows the storage format for RGB666 data. Set the CSI2_CTX_CTRL2_i[9:0]
FORMAT bit field to 0x33 to select RGB666 mode.
Figure 54. ISS CSI2 RGB666
RGB666
Transmitter
B1
G1
G2
B2
R1
R2
a0 a1 a2 a3 a4 a5 b0 b1 b2 b3 b4 b5 c0 c1 c2 c3 c4 c5 d0 d1 d2 d3 d4 d5 e0 e1 e2 e3 e4 e5 f0 f1
t0
t31
R2
G3
B3
R3
B4
G4
f2 f3 f4 f5 g0 g1 g2 g3 g4 g5 h0 h1 h2 h3 h4 h5 i0 i1 i2 i3 i4 i5 j0 j1 j2 j3 j4 j5 k0 k1 k2 k3
t32
G4
t63
R4
B5
G5
R5
B6
k4 k5 l0 l1 l2 l3 l4 l5 m0 m1m2 m3m4 m5 n0 n1 n2 n3 n4 n5 o0 o1 o2 o3 o4 o5 p0 p1 p2 p3 p4 p5
t64
t95
Time
Receiver
R1
B1
G1
31
0
X X X X X X X X c5 c4 c3 c2 c1 c0 0 0 b5 b4 b3 b2 b1 b0 0 0 a5 a4 a3
G2
R2
a2 a0 0 0
B2
31
0
X X X X X X X X f5 f4 f3 f2 f1 f0 0 0 e5 e4 e3 e2 e1 e0 0 0 d5 d4 d3 d2 d1 d0 0 0
FIFO
data memory
organization
with 24-bit data
expansion
on 32-bit word
Receiver
R1
B1
G1
31
0
X X X X X X X X X X X X X X c5 c4 c3 c2 c1 c0 b5 b4 b3 b2 b1 b0 a5 a4 a3 a2 a1 a0
R2
2
G2
B2
31
0
X X X X X X X X X X X X X X f5 f4 f3 f2 f1 f0 e5 e4 e3 e2 e1 e0 d5 d4 d3 d2 d1 d0
128
FIFO
data memory
organization
with 32-bit data
expansion
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.4.2.4 ISS CSI2 RGB444
RGB444 data is output to memory with data expansion. When data expansion is used, the value of the 4
upper bits is programmable and can be set with an alpha value for computer graphics applications (the
CSI2_CTX_CTRL3_i[29:16] ALPHA bit field). Figure 55 shows the storage format for RGB444 data. Set
the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0xA0 to select RGB444 mode.
Figure 55. ISS CSI2 RGB444
RGB444
Transmitter
G1[5:0]
B1[4:0]
1 a0 a1 a2 a3 0
R1[4:0]
G2[5:0]
B2[4:0]
1 b0 b1 b2 b3 1 c0 c1 c2 c3 1 d0 d1 d2 d3 0
R2[4:0]
1 e0 e1 e2 e3 1 f0 f1 f2 f3
t0
t31
G3[5:0]
B3[4:0]
1 g0 g1g2g3
0
R3[4:0]
G4[5:0]
B4[4:0]
1 h0 h1 h2 h3 1 i0 i1 i2 i3 1 j0 j1 j2 j3 0
R4[4:0]
1 k0 k1 k2 k3 1 l0 l1 l2 l3
t32
t63
Time
Receiver
G2[5:0]
R2[4:0]
B2[4:0]
G1[5:0]
R1[4:0]
B1[4:0]
31
0
X X X X f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 X X X X c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0
G4[5:0]
R4[4:0]
B4[4:0]
G3[5:0]
R3[4:0]
3[4:0]
B3[4:0]
31
0
X X X X l3 l2 l1 l0 k3 k2 k1 k0 j3 j2 j1 j0 X X X X i3 i2 i1 i0 h3 h2 h1 h0 g3 g2 g1 g0
FIFO
data memory
organization
with 16-bit data
expansion
2.6.1.1.4.2.5 ISS CSI2 RGB555
RGB555 data is output to memory with data expansion. Figure 56 shows the storage format for RGB555
data. Set the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field to 0xA1 to select RGB555 mode.
Figure 56. ISS CSI2 RGB555
RGB555
Transmitter
B1[4:0]
G1[5:0]
R1[4:0]
B2[4:0]
B2[4:0
G2[5:0]
R2[4:0]
a0 a1 a2 a3 a4 0 b0 b1 b2 b3 b4 c0 c1 c2 c3 c4 d0 d1 d2 d3 d4 0 e0 e1 e2 e3 e4 f0 f1 f2 f3 f4
t0
t31
B3[4:0]
G3[5:0]
R3[4:0]
B4[4:0]
G4[5:0]
R4[4:0]
g0 g1 g2 g3 g4 0 h0 h1 h2 h3 h4 i0 i1 i2 i3 i4 j0 j1 j2 j3 j4 0 k0 k1 k2 k3 k4 l0 l1 l2 l3 l4
t32
t63
Time
Receiver
R2[4:0]
G2[5:0]
B2[4:0]
R1[4:0]
G1[5:0]
B1[4:0]
31
0
f4 f3 f2 f1 f0 e4 e3 e2 e1 e0 0 d4 d3 d2 d1 d0 c4 c3 c2 c1 c0 b4 b3 b2 b1 b0 0 a4 a3 a2 a1 a0
R4[4:0]
G4[5:0]
B4[4:0]
R3[4:0]
G3[5:0]
31
B3[4:0]
0
l4 l3 l2 l1 l0 k4 k3 k2 k1 k0 0 j4 j3 j2 j1 j0 i4 i3 i2 i1 i0 h4 h3 h2 h1 h0 0 g4
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
FIFO
data memory
organization
with 16-bit data
expansion
129
ISS Interfaces
www.ti.com
2.6.1.1.4.3 ISS CSI2 RAW Bayer RGB Operating Modes
2.6.1.1.4.3.1 ISS CSI2 RAW6
RAW6 data can be output to memory with or without data expansion. The line length sent through the
CSI2 physical layer is a multiple of 8 bits (6-bit image data + 2-bit expansion). Furthermore, the line length
is a multiple of 3 × 8 bits to complete the pixel reconstruction correctly (the lowest common multiple of 8
and 6 is 24, so 3 × 8 bits). Figure 57 shows the storage format for RAW6 data. Set the
CSI2_CTX_CTRL2_i[9:0] FORMAT bit field as follows:
• To 0x28 to select RAW6 mode
• To 0x68 for RAW6 + 8-bit expansion
• To 0xE8 for RAW6 + DPCM decompression to 10-bit to video port
• To 0x2A8 for RAW6 + DPCM decompression to 10-bit expanded to 16-bit
• To 0x3A8 for RAW6 + DPCM decompression to 12-bit expanded to 16-bit
• To 0x368 for RAW6 + DPCM decompression to 12-bit to video port
130
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 57. ISS CSI2 RAW6
RAW6
P1
P2
P5
P4
P3
P6
a0 a1 a2 a3 a4 a5 b0 b1 b2 b3 b4 b5 c0 c1 c2 c3 c4 c5 d0 d1 d2 d3 d4 d5 e0 e1 e2 e3 e4 e5 f0 f1
t0
t31
P6
P7
P8
P9
P10
P11
f2 f3 f4 f5 g0 g1 g2 g3 g4 g5 h0 h1 h2 h3 h4 h5 i0 i1 i2 i3 i4 i5 j0 j1 j2 j3 j4 j5 k0 k1 k2 k3
t32
t63
Time
Transmitter
Receiver
P3
P4
P1
P2
31
0
0 0 d5 d4 d3 d2 d1 d0 0 0 c5 c4 c3 c2 c1 c0 0 0 b5 b4 b3 b2 b1 b0 0 0 a5 a4 a3 a2 a1 a0
P6
P7
P8
P5
31
0
0 0 h5 h4 h3 h2 h1 h0 0 0 g5 g4 g3 g2 g1 g0 0 0 f5 f4 f3 f2 f1 f0 0 0 e5 e4 e3 e2 e1 e0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW6 + EXP8
Receiver
P2
31
0
P1
0
0 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0
0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P3
P4
31
0
0
0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0
0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW6 + DPCM10 + EXP16
Receiver
P2
31
P1
0
0 0 0 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0
0
0 0 0 a11a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P3
P4
31
0
0
0 0
0 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1
d1 d0 0 0 0
0 c11c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW6 + DPCM12 + EXP16
Receiver
P6
P5
P4
P3
P
P1
P2
f1 f0 e5 e4 e3 e2 e1 e0 d5 d4 d3 d2 d1 d0 c5 c4 c3 c2 c1 c0 b5 b4 b3 b2 b1 b0 a5 a4 a3 a2 a1 a0
P11
P10
P9
P8
P7
P6
k3 k2 k1 k0 j5 j4 j3 j2 j1 j0 i5 i4 i3 i2 i1 i0 h5 h4 h3 h2 h1 h0 g5 g4 g3 g2 g1 g0 f5 f4 f3 f2
t0:
a7 a6 a5 a4 a3 a2 a1 a0]
0: VP_DATA = [0 0 0 0 a9 a8 a
b8 b7 b6 b5 b4 b3 b2 b1 b0]
t1: VP_DATA = [0 0 0 0 b9 b
t2: VP_DATA = [0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
t3: VP_DATA = [0 0 0 0 d
t0: VP_DATA = [0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW6
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW6 + DPCM10 + VP
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW6 + DPCM12 + VP
131
ISS Interfaces
www.ti.com
2.6.1.1.4.3.2 ISS CSI2 RAW7
RAW7 data can be output to memory with or without data expansion. The line length sent through the
CSI2 physical layer is a multiple of 8 bits. Furthermore, the line length is a multiple of 7 × 8 bits to
complete the pixel reconstruction correctly (the lowest common multiple of 8 and 7 is 56, so 7 × 8 bits).
Figure 58 shows the storage format for RAW7 data. Set the CSI2_CTX_CTRL2_i [9:0] FORMAT bit field
as follows:
• To 0x29 to select RAW7 mode
• To 0x69 for RAW7 + 8-bit expansion
• To 0x329 for RAW7 + DPCM decompression to 10-bit to video port
• To 0x229 for RAW7 + DPCM decompression to 10-bit expanded to 16-bit
• To 0x369 for RAW7 + DPCM decompression to 12-bit expanded to 16-bit
• To 0x3A9 for RAW7 + DPCM decompression to 12-bit to video port
132
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 58. ISS CSI2 RAW7
RAW7
Transmitter
P1
P2
P5
P4
P3
a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6 c0 c1 c2 c3 c4 c5 c6 d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3
t0
t31
P5
P6
P7
e4 e5 e6 f0 f1 f2 f3 f4 f5 f6 g0 g1g2g3
P8
P9
P10
g4 g5 g6 h0 h1 h2 h3 h4 h5 h6 i0 i1 i2 i3 i4 i5 i6 j0
t32
t63
Time
Receiver
P3
P4
P1
P2
31
0
0 d6 d5 d4 d3 d2 d1 d0 0 c6 c5 c4 c3 c2 c1 c0 0 b6 b5 b4 b3 b2 b1 b0 0 a6 a5 a4 a3 a2 a1 a0
P6
P7
P8
P5
31
0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW7 + EXP8
0 h6 h5 h4 h3 h2 h1 h0 0 g6 g5 g4 g3 g2 g1 g0 0 f6 f5 f4 f3 f2 f1 f0 0 e6 e5 e4 e3 e2 e1 e0
Receiver
P2
31
P1
0
0 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0
0
0 0
0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P3
P4
31
0
0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW7 + DPCM10 + EXP16
Receiver
P2
31
P1
0
0 0 0 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0
0
0 0 0 a11a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P3
P4
31
0
0 0 0 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0
0
0 0 0 c11c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW7 + DPCM12 + EXP16
Receiver
P3
P4
P5
P1
P2
e3 e2 e1 e0 d6 d5 d4 d3 d2 d1 d0 c6 c5 c4 c3 c2 c1 c0 b6 b5 b4 b3 b2 b1 b0 a6 a5 a4 a3 a2 a1 a0
P10
P9
P8
P7
P6
P5
j0 i6 i5 i4 i3 i2 i1 i0 h6 h5 h4 h3 h2 h1 h0 g6 g5 g4 g3 g2 g1 g0 f6 f5 f4 f3 f2 f1 f0 e6 e5 e4
t0: VP_DATA = [0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 0 0 cc9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
t0: VP_DATA = [0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW7
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW7 + DPCM10 + VP
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW7 + DPCM12 + VP
133
ISS Interfaces
www.ti.com
2.6.1.1.4.3.3 ISS CSI2 RAW8
RAW8 data can be output to memory with or without data expansion. The line length sent through the
CSI2 physical layer is always a multiple of 8 bits. Figure 59 shows the storage format for RAW8 data. Set
the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field as follows:
• To 0x2A to select RAW8 mode
• To 0x12A for RAW8 to video port
• To 0x32A for RAW8 + DPCM decompression to 10-bit to video port
• To 0x2AA for RAW8 + DPCM decompression to 10-bit expanded to 16-bit
• To 0x36A for RAW8 + DPCM decompression to 12-bit expanded to 16-bit
• To 0x3AA for RAW8 + DPCM decompression to 12-bit to video port
134
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 59. ISS CSI2 RAW8
RAW8
P1
P2
P4
P3
7
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t0
t31
P5
P6
P8
P7
e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7
t32
t63
Time
Receiver
P4
P3
Transmitter
P1
P2
31
0
d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
P8
P7
P5
P6
31
0
CSI2_CTX_CTRL [9:0]
CS
FORMAT
=
RAW8
h7 h6 h5 h4 h3 h2 h1 h0 g7 g6 g5 g4 g3 g2 g1 g0 f7 f6 f5 f4 f3 f2 f1 f0 e7 e6 e5 e4 e3 e2 e1 e0
Receiver
P2
31
0
P1
0
0 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0
0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P4
P3
31
0
0
0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW8 + DPCM10 + EXP16
Receiver
31
0
P1
P2
0
0 0 0 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0
0 0 0 a11a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P4
P3
31
0
0
0 0 0 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0
0 0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
t0: VP_DATA = [0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
a
t1: VP_DATA = [0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
t0: VP_DATA = [0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA
TA = [0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA
ATA = [0 0 c11 c10 c9 c8 c7 cc6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA
_DATA = [0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
t0:: VP_DATA = [0 0 0 0 0 0 a7 a
a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW8 + DPCM12 + EXP16
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW8 + DPCM10 + VP
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW8 + DPCM12 + VP
CSI2_CTX_CTRL2[9:0]
FORMAT
=
RAW8 + VP
135
ISS Interfaces
www.ti.com
2.6.1.1.4.3.4 ISS CSI2 RAW10
RAW10 data can be output memory in two formats: with or without data expansion. It can also be sent to
the video port. If data expansion is used, the 10-bit data are padded with 0s on a 16-bit word. The line
length sent through the CSI2 physical layer is a multiple of 8 bits. Furthermore, the line length is a multiple
of 5 × 8 bits to complete the pixel reconstruction correctly (the lowest common multiple of 8 and 10 is 40,
so 5 × 8 bits). Figure 60 shows the storage format for RAW10 data. Set the CSI2_CTX_CTRL2_i[9:0]
FORMAT bit field as follows:
• To 0x2B to select RAW10 mode
• To 0xAB for RAW10 + 16-bit expansion
• To 0x12F for RAW10 to video port
Figure 60. ISS CSI2 RAW10
RAW12
Transmitter
P1[11:4]
P2[11:4]
P1[3:0]
P2[3:0]
P3[11:4]
a4 a5 a6 a7 a8 a9 a10a11 b4 b5 b6 b7 b8 b9 b10 b11 a0 a1 a2 a3 b0 c8 b2 b3 c4 c5 c6 c7
c10c11
c11
c9 c10
t0
t31
P4[10:4]
P3[3:0]
P4[3:0]
P5[11:4]
P6[11:4]
d4 d5 d6 d7 d8 d9 d10d11 c0 c1 c2 c3 d0 d1 d2 d3 e4 e5 e6 e7 e8 e9 e10 e11 f4 f5 f6 f7 f8 f9 f10
t32
t63
P5[3:0]
P6[3:0]
P7[11:4]
P8[11:4]
P7[3:0]
P8[3:0]
e0 e1 e2 e3 f0 f1 f2 f3 g4 g5 g6 g7 g8 g9 g10 g11 h4 h5 h6 h7 h8 h9 h10 h11 g0 g1 g2 g3 h0 h1 h2 h3
t64
t95
Time
Receiver
P3[11:4]
P1[3:0]
P2[11:4]
P2[
P1[11:4]
P1[
31
0
c11 c10 c9 c8 c7 c6 c5 c4 b3 b2 b1 b0 a3 a2 a1 a0 b11 b10 b9 b8 b7 b6 b5 b4 a11 a10 a9 a8 a7 a6 a5 a4
P6[11:4]
P5[11:4]
P4[3:0]
P3[3:0]
P4[10:4]
31
0
f11 f10 f9 f8 f7 f6 f5 f4 e11 e10 e9 e8 e7 e6 e5 e4 d3 d2 d1 d0 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4
P8[3:0]
P7[3:0]
P8[11:4]]
P7[11:4]
P6[3:0]
P5[3:0]
0
31
h3 h2 h1 h0 g3 g2 g1 g0 h11 h10 h9 h8 h7 h6 h5 h4
FIFO
data memory
organization
without data
expansion
g10 g9 g8 g7 g6 g5 g4 f3 f2 f1 f0 e3 e2 e1 e0
Receiver
P2[11:0]
P1[11:0]
0
31
0 0 0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P4[11:0]
P3[11:0]
0
31
0 0 0 0 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
FIFO
data memory
organization
with 16-bit data
expansion
t0: VP_DATA = [0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
136
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.4.3.5 ISS CSI2 RAW12
RAW12 data can be output to memory in two formats: with or without data expansion. It can also be sent
to the video port. If data expansion is used, the 12-bit data are padded with 0s on a 16-bit word. The line
length sent through the CSI2 physical layer is a multiple of 8 bits. Furthermore, the line length is a multiple
of 3 × 8 bits to complete the pixel reconstruction correctly (the lowest common multiple of 8 and 12 is 24,
so 3 × 8 bits). Figure 61 shows the storage format for RAW12 data. Set the CSI2_CTX_CTRL2_i[9:0]
FORMAT bit field as follows:
• To 0x2C to select RAW12 mode
• To 0xAC for RAW12 + 16-bit expansion
• To 0x12C for RAW12 to video port
Figure 61. ISS CSI2 RAW12
RAW12
Transmitter
P1[11:4]
P2[11:4]
P1[3:0]
P2[3:0]
P3[11:4]
a4 a5 a6 a7 a8 a9 a10a11 b4 b5 b6 b7 b8 b9 b10 b11 a0 a1 a2 a3 b0 c8 b2 b3 c4 c5 c6 c7
c10c11
c11
c9 c10
t0
t31
P4[10:4]
P3[3:0]
P4[3:0]
P5[11:4]
P6[11:4]
d4 d5 d6 d7 d8 d9 d10d11 c0 c1 c2 c3 d0 d1 d2 d3 e4 e5 e6 e7 e8 e9 e10 e11 f4 f5 f6 f7 f8 f9 f10
t32
t63
P5[3:0]
P6[3:0]
P7[11:4]
P8[11:4]
P7[3:0]
P8[3:0]
e0 e1 e2 e3 f0 f1 f2 f3 g4 g5 g6 g7 g8 g9 g10 g11 h4 h5 h6 h7 h8 h9 h10 h11 g0 g1 g2 g3 h0 h1 h2 h3
t64
t95
Time
Receiver
P3[11:4]
P1[3:0]
P2[11:4]
P2[
P1[11:4]
P1[
31
0
c11 c10 c9 c8 c7 c6 c5 c4 b3 b2 b1 b0 a3 a2 a1 a0 b11 b10 b9 b8 b7 b6 b5 b4 a11 a10 a9 a8 a7 a6 a5 a4
P6[11:4]
P5[11:4]
P4[3:0]
P3[3:0]
P4[10:4]
31
0
f11 f10 f9 f8 f7 f6 f5 f4 e11 e10 e9 e8 e7 e6 e5 e4 d3 d2 d1 d0 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4
P8[3:0]
P7[3:0]
P8[11:4]]
P7[11:4]
P6[3:0]
P5[3:0]
0
31
h3 h2 h1 h0 g3 g2 g1 g0 h11 h10 h9 h8 h7 h6 h5 h4
FIFO
data memory
organization
without data
expansion
g10 g9 g8 g7 g6 g5 g4 f3 f2 f1 f0 e3 e2 e1 e0
Receiver
P2[11:0]
P1[11:0]
0
31
0 0 0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
P4[11:0]
P3[11:0]
0
31
0 0 0 0 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
FIFO
data memory
organization
with 16-bit data
expansion
t0: VP_DATA = [0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1: VP_DATA = [0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
t2: VP_DATA = [0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
137
ISS Interfaces
www.ti.com
2.6.1.1.4.3.6 ISS CSI2 RAW14
RAW14 data can be output to memory in two formats: with or without data expansion. It can also be sent
to the video port. If data expansion is used, the 14-bit data are padded with 0s on a 16-bit word. The line
length sent through the CSI2 physical layer is a multiple of 8 bits. Furthermore, the line length is a multiple
of 7 × 8 bits to complete the pixel reconstruction correctly (the lowest common multiple of 8 and 14 is 56,
so 7 × 8 bits). Figure 62 shows the storage format for RAW14 data. Set the CSI2_CTX_CTRL2_i[9:0]
FORMAT bit field as follows:
• To 0x2D to select RAW14 mode
• To 0xAD for RAW14 + 16-bit expansion
• To 0x12D for RAW12 to video port
Figure 62. ISS CSI2 RAW14
Transmitter
P1[13:6]
P2[13:6]
P4[13:6]
P3[13:6]
a6 a7 a8 a9 a10 a11 a12a13 b6 b7 b8 b9 b10b11 b12b13 c6 c7 c8 c9 c10c11 c12c13 d6 d7 d8 d9 d10 d11 d12 d13
t0
t31
P2[5:0]
P1[5:0]
P5[13:6]
P4[5:0]
P3[5:0]
a0 a1 a2 a3 a4 a5 b0 b1 b2 b3 b4 b5 c0 c1 c2 c3 c4 c5 d0 d1 d2 d3 d4 d5 e6 e7 e8 e9 e10 e11 e12e13
t32
t63
P6[13:6]
5[5:0]
P5[5:0]
P8[13:6]
P7[13:6]
P6[1:0]
f6 f7 f8 f9 f10 f11 f12 f13 g6 g7 g8 g9 g10 g11 g12g13 h6 h7 h8 h9 h10 h11 h12h13 e0 e1 e2 e3 e4 e5 f0 f1
t64
t95
P7[5:0]
P6[5:2]
P8[5:0]
f2 f3 f4 f5 g0 g1 g2 g3 g4 g5 h0 h1 h2 h3 h4 h5
t96
t111
Time
Receiver
P4[13:6]
P3[13:6]
P1[13:6]
P1[1
P2[13:6]
31
d13 d12 d11
b11 b10 b9 b8 b7 b6 a13 a12 a11 a10 a9 a8 a7 a6
d9d10
d8 d7 d6 c13 c12 c11 c10 c9 c8 c7 c6 b13 b12b11
P5[13:6]
P4[5:0]
P2[5:0]
P3[5:0]
P1[5:0]
e13 e12 e11 e10 e9 e8 e7 e6 d5 d4 d3 d2 d1 d0 c5 c4 c3 c2 c1 c0 b5 b4 b3 b2 b1 b0 a5 a4 a3 a2 a1 a0
P6[1:0]
P5[5:0]
P8[13:6]
P6[13:6]
P7[13:6]
f1 f0 e5 e4 e3 e2 e1 e0 h13 h12 h11 h10 h9 h8 h7 h6 g13 g12 g11 g10 g9 g8 g7 g6 f13 f12 f11 f10 f9 f8 f7 f6
P8[5:0]
P7[5:0]
FIFO
data memory
organization
without data
expansion
P6[5:2]
h5 h4 h3 h2 h1 h0 g5 g4 g3 g2 g1 g0 f5 f4 f3 f2
Receiver
P1[13:0]
P2[13:0]
0
31
0 0 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 a13 a12 a11
P4[13:0]
a10a8 a7 a6 a5 a4 a3 a2 a1 a0
a9
P3[13:0]
0
31
0 0 d13 d12 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
FIFO
data memory
organization
with 16-bit data
expansion
t0: VP_DATA = [a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0]
t1:
b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0]
1: VP_DATA = [b13 b12 b11 b
t2: VP_DATA = [c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0]
t3: VP_DATA = [d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0]
138
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.1.1.4.4 ISS CSI2 JPEG8 Operating Modes
The size of a compressed stream can be known in advance. Figure 63 shows the format for storing
JPEG8 data.
Figure 63. ISS CSI2 JPEG8
JPEG8 (Embedded 8-bit non image data)
Transmitter
a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10a11 a12 a13 a14 a15 a16 a17 a18 a19 a20a21a22 a23 a24 a25 a26 a27 a28 a29 a30 a31
t0
t31
Time
0
FIFO
data memory
organization
Receiver
31
a31 a30 a29 a28 a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
2.6.1.1.4.5 ISS CSI2 Generic Format
The CSI2 receiver supports a generic format to send data to memory and/or the video port. The generic
mode is entered by setting the CSI2_CTX_CTRL1_i[30] GENERIC bit. The CSI2_CTX_CTRL2_i [9:0]
FORMAT bit field defines how the data stream is decoded. When generic mode is enabled (GENERIC =
1), the MIPI data type code is ignored and data is decoded using the FORMAT bit. Whatever the MIPI
data type code, it is ignored (the data stream is processed even if the FORMAT bit does not match the
MIPI data type code.) When generic mode is not used (GENERIC = 0), the data stream is processed only
when the MIPI data type code matches the FORMAT setting of the enabled context. If not matched, the
data stream is not processed by the CSI2 engine. Only the virtual channel information is used to map a
received data stream to a context. Software must ensure that a MIPI virtual channel used in generic mode
is mapped only to a single context.
Figure 64 shows the ISS CSI2 generic format.
Figure 64. ISS CSI2 Generic Format
ISS CSI2 Generic: CSI2_CTX_CTRL1_i[30] GENERIC = 0x1
Transmitter
a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7
t31
t0
Time
Receiver when, for example, CSI2_CTx_CTRL2[9:0] FORMAT = RAW8
31
0
d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
FIFO
data memory
organization
139
ISS Interfaces
www.ti.com
2.6.1.1.4.6 ISS CSI2 MIPI Format Supported Summary
Table 65 summarizes the CSI2 MIPI-supported formats and their output category. By setting the
CSI2_CTX_CTRL2_i register format, the CSI2 outputs certain types of pixel packet data.
Table 65. ISS CSI2 MIPI Format Supported by the Protocol Engine
MIPI
CSI2 Protocol Engine Support
Category
Abbreviation
Register Setting Format Description
Configuration Value for
CSI2_CTX_CTRL2_i[9:0] FORMAT
Sync short packet
data types (1)
Short packet sync
code
Mandatory FSC
0x000
Short packet sync
code
Mandatory FEC
0x001
Short packet sync
code
Optional LSC
0x002
Short packet sync
code
Optional LEC
0x003
0x004
0x005
0x006
0x007
Generic short
packet data
types (1)
Generic Long
packet data
types (2)
YUV data
(1)
(2)
140
Short packet
32-bit without ECC is stored in a
register with code value 0x008.
0x008
Short packet
32-bit without ECC is stored in a
register with code value 0x009.
0x009
Short packet
32-bit without ECC is stored in a
register with code value 0x00A.
0x00A
Short packet
32-bit without ECC is stored in a
register with code value 0x00B.
0x00B
Short packet
32-bit without ECC is stored in a
register with code value 0x00C.
0x00C
Short packet
32-bit without ECC is stored in a
register with code value 0x00D.
0x00D
Short packet
32-bit without ECC is stored in a
register with code value 0x00E.
0x00E
Short packet
32-bit without ECC is stored in a
register with code value 0x00.
0x00F
Null
Discarded
0x010
Blanking data
Discarded
0x011
Embedded 8-bit
nonimage data (for
example, JPEG)
0x12: Embedded 8-bit nonimage data
(for example, JPEG)
0x012
Send to memory when FORMAT = 0
0x013
Send to memory when FORMAT = 0
0x014
Send to memory when FORMAT = 0
0x015
Send to memory when FORMAT = 0
0x016
Send to memory when FORMAT = 0
0x017
YUV4:2:0 8-bit
YUV4:2:0 8-bit
0x018
YUV4:2:0 10-bit
YUV4:2:0 10-bit
0x019
YUV4:2:0 8-bit
legacy
YUV4:2:0 8-bit legacy
0x01A
Reserved
Send to memory when FORMAT = 0
0x01B
To understand ISS synchronization codes and short packets, see Section 2.6.3.3.3, ISS CSI2 Short Packet.
To understand ISS synchronization codes and long packets, see Section 2.6.1.1.3.2, ISS CSI2 Long Packet.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 65. ISS CSI2 MIPI Format Supported by the Protocol Engine (continued)
MIPI
Category
Register Setting Format Description
Configuration Value for
CSI2_CTX_CTRL2_i[9:0] FORMAT
YUV4:2:0 8-bit +
CSPS
YUV4:2:0 8 bit + CSPS
0x01C
YUV4:2:0 10-bit +
CSPS
YUV4:2:0 10 bit + CSPS
0x01D
YUV4:2:2 8-bit
RGB data
YUV4:2:2 8-bit
0x01E
YUV4:2:2 8-bit + VP
0x09E
YUV4:2:2 8-bit + VP16
0x0DE
YUV4:2:2 10-bit
YUV4:2:2 10-bit
0x01F
RGB444
RGB444 + EXP16
0x0A0
RGB555
RGB555 + EXP16
0x0A1
RGB565
RGB565
0x022
RGB666
RGB666 + EXP32
0x0E3
RGB666 + EXP32_24
0x033
RGB888
RAW data
CSI2 Protocol Engine Support
Abbreviation
RGB888
0x024
RGB888 + EXP32
0x0E4
Reserved
Send to memory when FORMAT = 0
0x025
Reserved
Send to memory when FORMAT = 0
0x026
Reserved
Send to memory when FORMAT = 0
0x027
RAW6
RAW6
0x028
RAW6 + EXP8
0x068
RAW7
RAW8
RAW10
RAW12
RAW14
Reserved
RAW6 + DPCM10 + VP
0x0E8
RAW6 + DPCM10 + EXP16
0x2A8
RAW6 + DPCM12 + VP
0x368
RAW6 + DPCM12 + EXP16
0x3A8
RAW7
0x029
RAW7 + EXP8
0x069
RAW7 + DPCM10 + EXP16
0x229
RAW7 + DPCM10 + VP
0x329
RAW7 + DPCM12 + EXP16
0x369
RAW7 + DPCM12 + VP
0x3A9
RAW8
0x02A
RAW8 + VP
0x12A
RAW8 + DPCM10 + EXP16
0x2AA
RAW8 + DPCM10 + VP
0x32A
RAW8 + DPCM12 + EXP16
0x36A
RAW8 + DPCM12 + VP
0x3AA
RAW10
0x02B
RAW10 + EXP16
0x0AB
RAW10 + VP
0x12F
RAW12
0x02C
RAW12 + EXP16
0x0AC
RAW12 + VP
0x12C
RAW14
0x02D
RAW14 + EXP16
0x0AD
RAW14 + VP
0x12D
Send to memory when FORMAT = 0
0x02E
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
141
ISS Interfaces
www.ti.com
Table 65. ISS CSI2 MIPI Format Supported by the Protocol Engine (continued)
MIPI
Category
User-defined bytebased data
142
CSI2 Protocol Engine Support
Abbreviation
Register Setting Format Description
Configuration Value for
CSI2_CTX_CTRL2_i[9:0] FORMAT
Reserved
Send to memory when FORMAT = 0
0x02F
USER_DEFINED_BYTE_DATA
0x040
USER_DEFINED_BYTE_DATA +
EXP8
0x080
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C0
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x340
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C0
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x140
USER_DEFINED_BYTE_DATA
0x041
USER_DEFINED_BYTE_DATA +
EXP8
0x081
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C1
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x341
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C1
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x141
USER_DEFINED_BYTE_DATA
0x042
USER_DEFINED_BYTE_DATA +
EXP8
0x082
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C2
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x342
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C2
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x142
USER_DEFINED_BYTE_DATA
0x043
USER_DEFINED_BYTE_DATA +
EXP8
0x083
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C3
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x343
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C3
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x143
USER_DEFINED_BYTE_DATA
0x044
USER_DEFINED_BYTE_DATA +
EXP8
0x084
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C4
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x344
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 65. ISS CSI2 MIPI Format Supported by the Protocol Engine (continued)
MIPI
Category
Abbreviation
Reserved
CSI2 Protocol Engine Support
Register Setting Format Description
Configuration Value for
CSI2_CTX_CTRL2_i[9:0] FORMAT
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C4
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x144
USER_DEFINED_BYTE_DATA
0x045
USER_DEFINED_BYTE_DATA +
EXP8
0x085
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C5
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x345
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C5
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x145
USER_DEFINED_BYTE_DATA
0x046
USER_DEFINED_BYTE_DATA +
EXP8
0x086
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C6
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x346
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C6
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x146
USER_DEFINED_BYTE_DATA
0x047
USER_DEFINED_BYTE_DATA +
EXP8
0x087
USER_DEFINED_BYTE_DATA +
DPCM10 + EXP16
0x2C7
USER_DEFINED_BYTE_DATA +
DPCM10 + VP
0x347
USER_DEFINED_BYTE_DATA +
DPCM12 + EXP16
0x1C7
USER_DEFINED_BYTE_DATA +
DPCM12 + VP
0x147
Send to memory when FORMAT = 0
0x038
Send to memory when FORMAT = 0
0x039
Send to memory when FORMAT = 0
0x03A
Send to memory when FORMAT = 0
0x03B
Send to memory when FORMAT = 0
0x03C
Send to memory when FORMAT = 0
0x03D
Send to memory when FORMAT = 0
0x03E
Send to memory when FORMAT = 0
0x03F
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
143
ISS Interfaces
2.6.2
www.ti.com
ISS CSI2 Integration
Figure 65 is an overview of the integration of the CSI2-A interface in the device. The figure is the top-level
block diagram of the CSI2-A receiver. The receiver receives the serial data coming from a CSI2
compatible image sensor, converts it to parallel data, extracts the logical channels, detects and extracts
the synchronization codes, reformats the data, and outputs it through the video port or the ISS
interconnect interface.
Figure 65. ISS CSI2-A Integration
ISS
ISS interfaces and
interconnects
Write
64b to 128b
+ config
ISS
interconnect
CSI2-A
csi2a_dx0
csi2a_dy0
CSI2-A CAMERARX
csi2a_dx1
CSI2A_IRQ[0]
ISS IRQ merger
csi2a_dy1
csi2a_dx2
csi2a_dy2
csi2a_dx3
csi2a_dy3
csi2a_dx4
VP
STANDBY
hardware
handshake
ISP
EOF
PRCM
144
csi2a_dy4
ISS_FCLK
CAM_PHY_CTRL_FCLK
TCTRL
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The CSI2-A receiver can send data directly to system memory using the master port or send it to the
camera ISP using the video port.
For power domain, clocks, reset, and hardware requests, see Section 1.2.5, ISS Power Management.
2.6.3
ISS CSI2 Functional Description
2.6.3.1
ISS CSI2 Overview
Figure 66 is the CSI2-A receiver block diagram (it assumes there are four CSI2 image sensor data lines).
The CSI2 receiver receives the byte data coming from a CSI2 D-PHY receiver (up to four data pairs),
converts it to byte stream, detects and corrects errors, extracts the virtual channel ID, detects and extracts
the synchronization codes, reformats the data, and outputs it through the video port or the ISS
interconnect interface. Data communication between CSI2 and ISP is done through the video port.
A
Figure 66. ISS CSI2-A Receiver Block Diagram
VP_HS
VP_H
Lane 0
VP
VP
interface
interface
V
VP_DATA[15:0]
VP_PCLK
Video
port
VP_STALL
FIFO
DATA
CTRL
Data handler
Lane 1
Lane-level protocol
Lane 2
Lane merger
Lane 3
Image
sensor
CSI2-A complex I/O
VP
V
VP_VS
Lane 4
To BTE
Register – control logic
2.6.3.2
Interrupt
Interr
Wait
Standby
CSI2-A receiver
Interface
slave
ISS CSI2 Features
The CSI2 receiver is a master on the L3 interconnect for storing data in memory and a slave on the level 4
(L4) interconnect for register access.
The main features of the CSI2 receiver are:
• Transfer pixels and data received by the CSI2 PHY to the system memory or video processor
• Unidirectional data link
• Supports up to four data-configurable links in addition to the clock signaling (minimum of one data link
and maximum of four depending on the speed)
• Data merger for two, three, or four data lane configurations
• Error detection and correction by the protocol engine
• DMA engine integrated with dedicated FIFO
• 1D and 2D addressing modes
• Up to eight contexts to support eight dedicated configurations of virtual channel ID and data types
• Ping-pong mechanism for double-buffering
• JPEG support for unknown length transfer (no extraction of the thumbnail)
• Supports all primary and secondary MIPI-defined formats (RGB, RAW, and YUV)
• Storage in progressive mode for interlaced stream (using line numbering)
• Conversion to the RGB formats
• Decompressions of the RAW formats
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
145
ISS Interfaces
•
•
2.6.3.3
2.6.3.3.1
www.ti.com
RAW frame transcoding, including DPCM and A-Law compression
Fully configurable interface of the complex PHY I/O: position of the clock and data and order of ±
differential signals for each pair
ISS CSI2 Functional Description
ISS CSI2 Physical Layer Lane Configuration
The CSI2 serial interface is a unidirectional differential serial interface with data/clock for the physical
layer.
The maximum CSI2 receiver data transfer capacity is 1000 Mbps per data lane.
Data-clock signaling consists of two to five differential signal pairs: from one to four data lanes and one
clock lane:
• The data signal carries the bit-serial data. The CSI2 transmitter in the image sensor sends the data inquadrature with the dual-data rate (DDR) clock in HS mode; otherwise, the clock is extracted from the
received data in LS mode. Data is transmitted byte-wise, LSB first. The CSI2 complex I/O receives the
data and sends the byte stream to the CSI2 receiver.
• The clock signal carries the DDR clock signal.
Each physical lane can be a data or clock lane with a restriction to the fourth line, which can only be data
(see Section 2.3.1, ISS CSI2 PHY Overview). The clock/data lane must be configured before transmission
to indicate the byte order, while merging the received bytes into a byte stream shows the reachable speed
per data lane function of data lane numbers.
Lanes are configured through the CSI2_COMPLEXIO_CFG registers for CSI2-A and PHY. The
CSI2_COMPLEXIO_CFG[2:0] CLOCK_POSITION bit field and the CSI2_COMPLEXIO_CFG[3]
CLOCK_POL bit configure which lane transmits the clock and define its polarity. DATAl_POSITION and
DATAl_POL configure the data lanes and their polarity, where l is the number of the data lane (l = 1 to 4).
When the DATAl_POSITION field is set to 0, data lane l is not used.
CAUTION
Lane 4 (position 5) supports only data. The CLOCK_POSITION must not be set
at position 5.
2.6.3.3.2
ISS CSI2 ECC and Checksum Generation
The CSI2 receiver includes an ECC in the packet header and a checksum in the packet footer for longpacket transmission. These two fields can be used to detect and/or correct errors in the received packet.
2.6.3.3.2.1 ISS CSI2 ECC
To detect and correct transmission errors of the header of short and long packets, an 8-bit ECC is
included in the header of packets (short and long packet).
The ECC concerns all the fields for a short packet (data ID and short-packet data field) and the packet
header for a long packet (data ID and word count). The ECC can only correct one error. Additional errors
cannot be repaired, but they are flagged.
The CSI2 receiver ECC is compared against the CSI2 transmitter ECC embedded in the bitstream. If the
ECC does not match, an interrupt is triggered to the host central processing unit (CPU).
For long and short packets, the correction is always done if there is only one error per packet header.
An ECC error with or without correction can be reported at two levels, depending on the type of packet.
Table 66 describes the field in which events are logged. Logging cannot be disabled, but users can set the
corresponding bit in the CSI2_IRQENABLE and CSI2_CTX_IRQENABLE registers to prevent event
generation at a higher level.
146
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The ECC check can be disabled (short and long packet) by setting the CSI2_CTRL[2] ECC_EN bit to 0.
Setting the bit to 1 enables the ECC check.
Table 66. ISS CSI2 ECC Event Logging
Short Packet
Long Packet
With correction
Global
CSI2_IRQSTATUS[12] ECC_CORRECTION_IRQ
Context
CSI2_CTX_IRQSTATUSIi[8]
ECC_CORRECTION_IRQ
Without correction
Global
CSI2_IRQSTATUS[11]
ECC_NO_CORRECTION_IRQ
Global
CSI2_IRQSTATUS[11]
ECC_NO_CORRECTION_IRQ
2.6.3.3.2.2 ISS CSI2 Checksum
To detect errors in transmission of the payload of long packets, a 16-bit CRC checksum is computed on
the payload of the long packets in the transmitter. This CRC is stored in the packet footer. A CRC is also
computed in the CSI2 receiver. If the checksums do not match, an interrupt is triggered to the host CPU.
CRC errors are logged in the CS_IRQ field of the corresponding context register,
CSI2_CTX_IRQSTATUS_i. Logging cannot be disabled, but users can set the corresponding bit in the
CSI2_CTX_IRQSTATUS_i register to prevent event generation at a higher level.
The CRC can be disabled for a specific context by setting the CSI2_CTRL[5] CS_EN bit to 0. Setting the
bit to 1 enables the CRC.
2.6.3.3.3
ISS CSI2 Short Packet
There are two types of short packets in the CSI2 receiver:
• Synchronization short packet: Used by the protocol engine to synchronize frame and line (data ID from
0x0 to 0x7)
• Generic short packet: User-dependent; not treated by the protocol engine (data ID from 0x8 to 0xF)
When a generic short packet is received by the CSI2 receiver, the ECC check is performed if it is enabled.
Then, the short packet is written in the CSI2_SHORT_PACKET[23:0] SHORT_PACKET bit field. The ECC
field is deleted from the short packet. Figure 67 shows the SHORT_PACKET bit field format.
Figure 67. ISS CSI2 SHORT_PACKET Bit Field Format
23
16 15
Data ID
0
Short packet data field
When a short packet is stored, an event is logged in the CSI2_IRQSTATUS [13] SHORT_PACKET_IRQ
bit. Logging cannot be disabled, but users can set the corresponding bit in the CSI2_IRQENABLE register
to prevent event generation at a higher level.
The application reads the CSI2_SHORT_PACKET register before the next short packet with a code from
0x8 to 0xF. There is a single register for capturing the generic short packet, because no data type in it is
associated with context.
2.6.3.3.4
ISS CSI2 Virtual Channel and Context
The CSI2 protocol layer transports virtual channels. The virtual channels separate different data flows
interleaved in the same data stream. Each virtual channel is identified by a unique channel identification
number in the packet header. This channel identification number is encoded in the 2-bit code.
The CSI2 receiver monitors the channel identifier number and demultiplexes the interleaved data streams.
The CSI2 receiver supports up to four concurrent virtual channels.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
147
ISS Interfaces
www.ti.com
The CSI2 receiver supports eight contexts with their events to control the four possible virtual channels
and the different data transmitted through them. A context is linked to a specific data type transported by a
given virtual channel. The following bit fields permit configuration of a context:
• CSI2_CTX_CTRL2_i[12:11] VIRTUAL_ID: Configures the virtual ID linked to the current context
• CSI2_CTX_CTRL2_i[9:0] FORMAT: Configures the data format linked to the current context
Figure 68 shows the relationships between virtual channels and contexts.
Figure 68. ISS CSI2 Virtual Channel to Context
Data ID (format)
Context 0
Virtual channel 0
Context 1
Virtual channel 1
Context 2
Virtual channel 2
Virtual channel 3
Context
xt 3
Context 4
Context 5
Context 6
C
Context 7
Each context consists of eight registers: six registers to control the corresponding context and two to log
and enable events from the context. All registers in a context can be modified at any time; however,
modifications apply only from the start of the following frame.
A context can be enabled independently by setting the CSI2_CTX_CTRL1_i[0] CTX_EN bit to 1; setting
this bit to 0 disables the corresponding context.
When acquiring frames on a context, users can write the number of frames to capture in the
CSI2_CTX_CTRL1_i[15:8] COUNT bit field. Acceptable values are 0 to 255; 0 stands for infinite capture
(no count). After each frame is acquired, the count value is decremented by 1. When the count value
reaches 0, the CSI2_CTX_IRQSTATUS_i[6] FRAME_NUMBER_IRQ event is set and the CTX_EN bit is
set to 0. To write a value in the COUNT bit field, the CSI2_CTX_CTRL1_i[4] COUNT_UNLOCK bit must
be set to 1. If the value of the COUNT_UNLOCK bit is 0, a write in the COUNT bit field has no effect.
The CSI2_CTX_CTRL3_i [15:0] LINE_NUMBER bit field configures the generation of the
CSI2_CTX_IRQSTATUS_i [7] LINE_NUMBER_IRQ event. The CSI2_CTX_CTRL1_i [1] LINE_MODULO
bit configures how the LINE_NUMBER event is generated:
• 0: The event is generated one time by frame.
• 1: The event is generated modulo LINE_NUMBER (the event can be generated more than once in a
frame).
During a frame capture, the CSI2_CTX_CTRL2_i[31:16] FRAME_NUMBER bit field shows the number
that identifies the frame received.
2.6.3.3.5
ISS CSI2 DMA Engine
The CSI2 receiver integrates its own DMA engine with dedicated FIFO.
Global DMA configuration is common to the eight channels and is defined in the CSI2_CTRL register.
Configuration of the ping-pong address and the offset between lines is specific for a given context;
therefore, each context has its own DMA configuration registers.
The DMA engine supports:
• 1D addressing mode (no address line offset, CSI2_CTX_DAT_OFST_i = 0)
• 2D addressing mode (address line offset different than 0, CSI2_CTX_DAT_OFST_i = 0)
148
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The burst size is defined in the CSI2_CTRL [6:5] BURST_SIZE bit field and the CSI2_CTRL[16]
BURST_SIZE_EXPAND bit. The DMA uses the burst size or smaller sizes down to single open-core
protocol (OCP) writes depending on the alignment at the end of lines. The DMA engine can handle burst
requests. When the burst requests can be used, as soon as one burst of data is present in the FIFO, the
DMA engine initiates a burst write. The burst size is defined in the CSI2_CTRL [6:5] BURST_SIZE bit field
and the CSI2_CTRL [16] BURST_SIZE_EXPAND bit.
NOTE: Unless there are specific requirements, CSI2 (also applies to all other ISS initiators) must be
configured to use only a burst size of 128 bytes and nonposted writes.
When single requests must be used, as soon as one element (the size depends on the data type and the
post-processing: DPCM, EXT, etc.) is present in the FIFO, the DMA engine initiates a single write.
Interleave mode is dedicated by the CSI2 receiver only when the line numbers are received (short
packets). The line number is used to calculate the start address of the line.
The DMA starts to write in memory using the CSI2_CTX_DAT_PING_ADDR_i[31:5] ADDR bit field for the
first frame to be transferred, and then uses the CSI2_CTX_DAT_PONG_ADDR_i [31:5] ADDR bit field
and the ping address alternately. Thus, the first frame uses the ping address, the second frame uses the
pong address, the third frame uses the ping address, and so on.
The CSI2_CTX_CTRL_i [3] PING_PONG status bit indicates whether the ping address
(CSI2_CTX_DAT_PING_ADDR_i) or the pong address (CSI2_CTX_DAT_PONG_ADDR_i) was used to
store the pixel data of the last frame. After reset or after a 0-to-1 edge transition in the CSI2_CTRL[0]
IF_EN bit, the pixel data is written in the ping buffer and the CSI2_CTX_CTRL1_i[3] PING_PONG bit =
PONG. When the number of FECs received equals the value programmed in the
CSI2_CTX_CTRL1_i[23:16] FEC_NUMBER bit field, the pixel data are written in the pong buffer and
CSI2_CTX_CTRL1_i [3] PING_PONG = PING. CSI2_CTX_CTRL1_i[3] PING_PONG toggles after the
CSI2_CTX_CTRL1_i[23:16] FEC_NUMBER FEC sync code with the virtual channel ID defined is received
in the CSI2_CTX_CTRL2_i [12:11] VIRTUAL_ID bit field.
The CSI2_CTX_CTRL1_i[23:16] FEC_NUMBER bit field must be set as follows:
• In progressive mode, set to 1.
• In interlaced mode, set to the number of interlaced frames to recreate a progressive image in the
PING_PONG buffer.
2.6.3.3.5.1 ISS CSI2 Progressive Frame to Progressive Storage
After each line, a new start line address is computed, depending on the value of the
CSI2_CTX_DAT_OFST_i[31:5] OFST bit field:
• If OFST = 0, the new line starts immediately after the last pixel (data are written contiguously in
memory).
• Otherwise, the value of OFST sets the offset between the first pixel of the previous line and the first
pixel of the current line in memory.
For the ping frame:
@Line0 = CSI2_CTX_DAT_PING_ADDR_i@Line1 = @Line0 + CSI2_CTX_DAT_OFST_i@Line2 = @Line1 +
CSI2_CTX_DAT_OFST_i
For the pong frame:
@Line0 = CSI2_CTX_DAT_PONG_ADDR_i@Line1 = @Line0 + CSI2_CTX_DAT_OFST_i@Line2 = @Line1 +
CSI2_CTX_DAT_OFST_i
2.6.3.3.5.2 ISS CSI2 Interlaced Frame to Progressive Storage
The mode is functional only when the line numbers are transmitted. It is automatically enabled without
setting.
For the ping frame:
@LineX = CSI2_CTX_DAT_PING_ADDR_i + CSI2_CTX_DAT_OFST_i * Line_Number
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
149
ISS Interfaces
www.ti.com
For the pong frame:
@LineX = CSI2_CTX_DAT_PONG_ADDR_i + CSI2_CTX_DAT_OFST_i * Line_Number
Figure 69 shows how data are stored in memory regarding the DMA configuration.
Figure 69. ISS CSI2 Pixel Data Destination Setting in Progressive and Interlaced Mode
Progressive frame
(FEC_NUMBER = 1)
Interlaced frame
(FEC_NUMBER = 2)
FRAME_BUFFER_WIDTH
FRAME_BUFFER_WIDTH
CSI2_CTX_DAT_PING_ADDR
CSI2_CTX_DAT_PING_ADDR
@line0
@line1
CSI2_CTX_DAT_OFST
@line0
@line1
CSI2_CTX_DAT_OFST * 1
@line1
@line2
CSI2_CTX_DAT_OFST * 2
@line2
@line2
CSI2_CTX_DAT_OFST* 3
@line3
Pixel data
Pixel data
IMAGE_WIDTH
IMAGE_WIDTH
Frame buffer
Frame buffer
Frame n
Frame n +
The burst size is defined in the CSI2_CTRL[6:5] BURST_SIZE bit field for bursts up to 16 × 64 bits or the
CSI2_CTRL[16] BURST_SIZE_EXPAND bit for 16 × 128-bit bursts. It can be changed only while the
CSI2_CTRL[0] IF_EN bit is reset to 0. The recommended value is the CSI2_CTRL[16]
BURST_SIZE_EXPAND bit set to 1, which defines a burst of 16 × 64 bits (the maximum value); otherwise,
by default it is set to 8 × 64 bits. When the BURST_SIZE_EXPAND bit is set, the BURST_SIZE setting
has no effect. The DMA uses nonposted writes by default. The CSI2_CTRL[13] NON_POSTED_WRITE
bit must be set to 1 to match DMA default configuration. It can be changed only while the CSI2_CTRL[0]
IF_EN bit is reset to 0.
2.6.3.3.6
ISS CSI2 Transcoding
Image transcoding is used mainly to reduce memory footprint and bandwidth when:
• The sensor does not support DPCM compression. In fact, A-Law and DPCM compressed pixels
occupy only 6, 7, or 8 BPP of storage.
• Digital zoom is used
– Data that is not going to be used by further processing does not need to the stored in system
memory.
– Pixels cannot be accessed from random locations in a DPCM-compressed frame. Transcoding
avoids memory-to-memory processing of unused pixels.
Figure 70 shows the logical representation of the image transcoding operation.
• Data is extracted from the CSI2 stream by the protocol engine.
• It is DPCM decompressed if necessary. That is the case when the received stream is DPCMcompressed and transcoding has been enabled using the CSI2_CTRL1_i[27:24] TRANSCODE bit
field.
• Data sent to the video port cannot be compressed: it is intended to be processed by the ISS ISP. Data
sent to system memory can be optionally compressed.
• Internal data are aligned on MSB when they enter the cropping stage. For example:
– 4 LSBs are 0s when RAW10 data are handled.
– 2 LSBs are 0s when RAW12 data are handled.
150
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 70. ISS CSI2 Frame Processing
CSI2_CTX_CTRL2.FORMAT
CSI2_CTX_CTRL1.TRANSCODE
DPCM6 -> RAW10
DPCM7 -> RAW10
DPCM8 -> RAW10
Crop
CSI2_CTX_TRANSCODEH
DPCM6 -> RAW12
DPCM7 -> RAW12
DPCM8 -> RAW12
CSI2_CTX_TRANSCODEV
Data
from
sensor
RAW10 -> DPCM8
OCP
port
64b
RAW12 -> DPCM8
RAW10 -> ALAW
CSI2_CTX_
CSI2_CTX_CTRL2.FORMAT
CSI2_CTRLVP_ONLY
Video 16b
port
Table 67 shows the input format provided to the cropping engine for a given pixel format provided by the
sensor. Formats not listed in the table are not supported for transcoding. The FORMAT and
Corresponding Setting Value column corresponds to the value set in the CSI2_CTX_CTRL2_i[9:0]
FORMAT register.
Table 67. ISS CSI2 Supported Transcoding Input Formats
CSI2_CTX_CTRL2_i[9:0] FORMAT and Corresponding Setting
Value
0x028
RAW6
0x058
RAW6 + EXP8
0x029
RAW7
0x059
RAW7 + EXP8
0x02A
RAW8
0x12A
RAW8 + VP
0x02B
RAW10
0x0AB
RAW10 + EXP16
0x0E8
RAW6 + DPCM10 + VP
0x12F
RAW10 + VP
Cropping
Engine Input
Format
DPCM
Decomposition
Enabled
Video Port
Enabled
RAW6
RAW7
RAW8
Yes
RAW10
Yes
Yes
Yes
0x229
RAW7 + DPCM10 + EXP16
Yes
0x2A8
RAW6 + DPCM10 + EXP16
Yes
0x2AA
RAW8 + DPCM10 + EXP16
Yes
0x329
RAW7 + DPCM10 + VP
Yes
Yes
0x32A
RAW8 + DPCM10 + VP
Yes
Yes
0x2Cn
USER_DEFINED_BYTE_DATA + DPCM10 + EXP16
Yes
0x34n
USER_DEFINED_BYTE_DATA + DPCM10 + VP
0x02C
RAW12
0x0AC
RAW12 + EXP16
0x12C
RAW12 + VP
Yes
Yes
RAW12
Yes
0x35A
RAW8 DPCM12 + EXP16
Yes
0x3AA
RAW8 DPCM12 + VP
Yes
0x1Cn
USER_DEFINED_BYTE_DATA + DPCM12 + EXP16
Yes
0x14n
USER_DEFINED_BYTE_DATA + DPCM12 + VP
Yes
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Yes
Yes
151
ISS Interfaces
www.ti.com
Table 67. ISS CSI2 Supported Transcoding Input Formats (continued)
CSI2_CTX_CTRL2_i[9:0] FORMAT and Corresponding Setting
Value
Cropping
Engine Input
Format
DPCM
Decomposition
Enabled
0x3A8
RAW6 + DPCM12 + EXP16
Yes
0x358
RAW6 + DPCM12 + VP
Yes
0x359
RAW7 + DPCM12 + EXP16
Yes
0x3A9
RAW7 + DPCM12 + VP
0x02D
RAW14
0x0AD
RAW14 + EXP16
0x12D
RAW14 + VP
Video Port
Enabled
Yes
Yes
Yes
RAW14
Yes
Image cropping parameters are controlled by software. Figure 71 shows the cropping operation.
Figure 71. ISS CSI2 Frame Cropping
VP_HS
HS
HSKIP
HCOUNT
COUNT
OUNT
VSKIP
VP_VS
Frame sent to video port/
memory
VCOUNT
F
Frame received from
camera
CAUTION
Hardware does not check for validity of the settings. The following rules must
be respected:
• CSI2_CTX_TRANSCODEH_i[12:0] HSKIP +
CSI2_CTX_TRANSCODEH_i[28:16] HCOUNT = image width
• CSI2_CTX_TRANSCODEV_i[12:0] VSKIP +
CSI2_CTX_TRANSCODEV_i[28:16] VCOUNT = image height
Furthermore, the CSI2_CTX_TRANSCODEH_i[28:16] HCOUNT bit field must comply with the following
alignment constraints; otherwise, undefined behavior occurs. Table 68 shows the transcode alignment
constraints
Table 68. ISS CSI2 Transcode Alignment Constraints
152
CSI2_CTX_CTRLi[27:24] TRANSCODE
Value
Transcode
HCOUNT Must Be Multiple of
0x0
Disabled
1
0x1
DPCM10 RAW8
1
0x2
DPCM12 RAW8
1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 68. ISS CSI2 Transcode Alignment Constraints (continued)
CSI2_CTX_CTRLi[27:24] TRANSCODE
Value
Transcode
HCOUNT Must Be Multiple of
0x3
ALAW10 RAW8
1
0x4
RAW8
1
0x5
RAW10 + EXP16
1
0x6
RAW10
4
0x7
RAW12 + EXP16
1
0x8
RAW12
2
0x9
RAW10 + EXP16
4
The CSI2_CTX_CTRL1_i[28] HSCALE configuration register enables horizontal downscaling of RAW
data. It reduces the horizontal size and pixel clock by a factor of 2. The scaler uses a 2-tap horizontal filter
operating on samples of the same color plane. The coefficients are: [1/2 ; 0 ; 1/2]
Figure 72 shows the scaler operation.
Figure 72. ISS CSI2 Horizontal Scaler
The scaler can send data to the video port or the interface port. When data goes to the video port, no
additional alignment constraints apply. But when data goes to the interface port, HCOUNT/2 must comply
with the constraints from Table 68 (for example, for RAW10, HCOUNT must be a multiple of 8).
Table 69 lists possible combinations of input and output formats supported by the transcoding engine. The
Transcode column corresponds to the CSI2_CTX_CTRL1_i[27:24] TRANSCODE bit field of a context.
Table 69. ISS CSI2-Supported Transcoding Output Formats
Cropping
Engine
Output
RAW6
Transcode
Supported
Cropping
Engine
Output
Yes
RAW10
Transcode
Supported
0
Disabled
0
Disabled
Yes
1
DPCM10 RAW8
1
DPCM10 RAW8
Yes
2
DPCM12 RAW8
2
DPCM12 RAW8
3
ALAW10 RAW8
3
ALAW10 RAW8
4
RAW8
4
RAW8
5
RAW10 + EXP16
5
RAW10 + EXP16
Yes
6
RAW10
6
RAW10
Yes
7
RAW12 + EXP16
7
RAW12 + EXP16
8
RAW12
8
RAW12
9
RAW14
9
RAW14
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Yes
153
ISS Interfaces
www.ti.com
Table 69. ISS CSI2-Supported Transcoding Output Formats (continued)
Cropping
Engine
Output
RAW7
RAW8
Transcode
Supported
Cropping
Engine
Output
Yes
RAW12
Transcode
Supported
0
Disabled
0
Disabled
1
DPCM10 RAW8
1
DPCM10 RAW8
2
DPCM12 RAW8
2
DPCM12 RAW8
3
ALAW10 RAW8
3
ALAW10 RAW8
4
RAW8
4
RAW8
5
RAW10 + EXP16
5
RAW10 + EXP16
6
RAW10
6
RAW10
7
RAW12 + EXP16
7
RAW12 + EXP16
Yes
8
RAW12
8
RAW12
Yes
9
RAW14
9
RAW14
0
Disabled
0
Disabled
1
DPCM10 RAW8
1
DPCM10 RAW8
2
DPCM12 RAW8
2
DPCM12 RAW8
3
ALAW10 RAW8
3
ALAW10 RAW8
4
RAW8
4
RAW8
5
RAW10 + EXP16
5
RAW10 + EXP16
6
RAW10
6
RAW10
7
RAW12 + EXP16
7
RAW12 + EXP16
8
RAW12
8
RAW12
9
RAW14
9
RAW14
Yes
RAW14
Yes
Yes
Yes
Yes
Yes
RAW pixels are packed into 64-bit words sent to the OCP master port, as defined in:
• Section 2.6.1.1.4.3.3, ISS CSI2 RAW8
• Section 2.6.1.1.4.3.4, ISS CSI2 RAW10
• Section 2.6.1.1.4.3.5, ISS CSI2 RAW12
• Section 2.6.1.1.4.3.6, ISS CSI2 RAW14
For RAW10 and RAW12, software can choose among packed and nonpacked storage. A-Law and DPCMcompressed pixels are stored as RAW8 data: each RAW8 container holds a compressed data point.
Similarly, RAW data is sent over the video port, as described in:
• Section 2.6.1.1.4.3.3, ISS CSI2 RAW8
• Section 2.6.1.1.4.3.4, ISS CSI2 RAW10
• Section 2.6.1.1.4.3.5, ISS CSI2 RAW12
• Section 2.6.1.1.4.3.6, ISS CSI2 RAW14
Enabling of the OCP/video port is controlled by the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field and the
CSI2_CTRL[11] VP_ONLY_EN and CSI2_CTX_CTRL1_i[2] VPFORCE bits.
To enable transcoding, software configures the context normally and also configures the framing using the
CSI2_CTX_TRANSCODEV_i and CSI2_CTX_TRANSCODEH_i registers. Software defines the after
transcoding with the CSI2_CTX_CTRL1_i[27:24] TRANSCODE bit field.
2.6.3.3.7
ISS CSI2 EndOfFrame and EndOfLine (EOF and EOL) Pulses
The CSI2 receiver generates two signals to qualify the last pixel of a frame and the last pixel of a line to
the TCTRL. It is active during or after the adequate interface bridge transaction and becomes inactive
before the first transaction of the next line. Software can enable/disable generation of those signals for
each context using the CSI2_CTX_CTRL1_i[7] EOF_EN and CSI2_CTX_CTRL1_i [6] EOL_EN bits. When
data is sent to both OCP and video ports, the EOL/EOF timing defined for the OCP port is used.
154
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.3.3.8
ISS CSI2 Data Decompression
The data compression technique used is DPCM and PCM.
To select the DPCM decompression predictor for the CSI2 Interface, set the CSI2_CTX_CTRL2_i[10]
DPCM_PRED bit to 1 for simple predictor or to 0 for advanced predictor.
2.6.4
ISS CSI2 Programming Model
2.6.4.1
ISS CSI2 Reset Management
The CSI2 receiver accepts a general software reset, propagated throughout the hierarchy. This reset can
be done to initialize the CSI2 receiver and the complex I/O and has the same effect as a hardware reset.
Figure 73 shows how to reset CSI2 globally.
Figure 73. ISS CSI2 Receiver Global Reset Flow Chart
Start
Set
CSI2_SYSCONFIG.SOFT_RESET
No
CSI2_SYSSTATUS.
SYSSTATUS.
RESET_DONE
ET_DONE = 1?
No
Fifth time we
pass here?
Yes
Yes
No
Error occurred
during reset stage
CSI2_COMPLEXIO_CFG.
RESET_DONE = 1?
Yes
Y
CSI2 is reset correctly
NOTE: Before setting the software reset bit to 1 in the CSI2_SYSCONFIG register, the user must
have access to a CSI2 receiver register.
NOTE:
The CSI2_COMPLEXIO_CFG[29] RESET_DONE bit is set to 1 only after the initialization of
the CSI2 receiver, CSI2 complex I/O, and external camera completes.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
155
ISS Interfaces
2.6.4.2
www.ti.com
ISS CSI2 Enable Video/Picture Acquisition
Before using the receiver, a CSIPHY initialization in CSI2 mode must be made for CSI2-A CAMERARX,
which is associated with the CSI2 receiver. See Section 2.3.2.2, ISS CSI2 PHY and Link Initialization
Sequence. To start a video/picture acquisition, perform the steps listed in Table 70.
Table 70. ISS CSI2 Global Initialization
Step
Register/Bit Field/Programming Model
Reset the CSI2 receiver.
See Section 2.6.4.1, Reset Management.
Configure the module power management. The
module tries to enter smart-standby mode during the
vertical blanking period. The CSI2_SYSCONFIG[0]
AUTO_IDLE bit keeps its reset value; by default, an
automatic port clock gating strategy is applied based
on port interface activity.
CSI2_SYSCONFIG[13:12] MSTANDBY_MODE
Configure the interrupt generation as required. To
enable context and/or complex I/O event reporting,
enable the corresponding bit field in the
CSI2_IRQENABLE register. If the enable bit is at 0,
logging is still effective if an event occurs, but is not
reported to a higher level.
CSI2_IRQSTATUS and CSI2_IRQENABLE
Configure the complex I/O interrupt generation as
required. If the enable bit is at 0, logging is still
effective if an event occurs, but is not reported to a
higher level.
CSI2_COMPLEXIO_IRQSTATUS and
CSI2_COMPLEXIO_IRQENABLE)
Start complex I/O: Set the
CSI2_COMPLEXIO_CFG[28:27] PWR_CMD bit field
to 0x1 to pass the complex I/O to the ON state, and
then check that the state status reaches the ON state
(CSI2_COMPLEXIO_CFG[26:25] PWR_STATUS =
0x1) (for complex I/O A).
CSI2_COMPLEXIO_CFG[28:27] PWR_CMD
Configure the complex I/O:
• The complex I/O is fully functional with
CSI2_COMPLEX_CFG set at its reset value.
• CSI2_COMPLEX_CFG must be changed
according to the data rate being used.
CSI2_COMPLEXIO_CFG
Set RXMODE and STOPSTATE FSM to RXMODE
state. Users can also configure the delay for the FSM
to return from RXMODE to NORXMODE when all
lines reach STOPSTATE.
CSI2_TIMING[15] FORCE_RX_MODE_IO1
Value
0x2
0x1
0x1
Activate ECC correction and error detection on short
CSI2_CTRL[2] ECC_EN
packets and packet headers. The ECC check corrects
the packet if there is one error and generates an error
if there is more than one error (unrecoverable error).
0x1
Start the CSI2 receiver.
0x1
CSI2_CTRL[0] IF_EN
Configure the different contexts to be used.
156
Link the context to a virtual channel and a data type.
See Section 2.6.4.6, Linking a Context to a Virtual
Channel and a Data Type.
Set the FEC_NUMBER bit field to 0x1 for a
progressive video and to 0x2 for an interlaced video.
For more information, see Section 2.6.3.3.5, DMA
Engine.
CSI2_CTX_CTRL1_i[26:23] FEC_NUMBER
0x1 or 0x2
Capture an infinite number of frames (until the
interface or the context is disabled).
CSI2_CTX_CTRL1_i[15:8] COUNT and
CSI2_CTX_CTRL1_i[4] COUNT_UNLOCK
0x0
Enable the CRC checksum on long packet payload.
This allows detection of errors, but cannot correct
errors like the ECC for header and short packet. On
error detection, an event is triggered (the
CSI2_CTX_IRQSTATUS_i[5] CS_IRQ bit).
CSI2_CTX_CTRL1_i[5] CS_EN
Configure the DMA engine for the current channel:
Configure the ping and pong addresses.
CSI2_CTX_DAT_PING_ADDR_i[31:5] ADDR and
CSI2_CTX_DAT_PING_ADDR_i[31:5] ADDR
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 70. ISS CSI2 Global Initialization (continued)
Step
2.6.4.3
Register/Bit Field/Programming Model
Set the CSI2_CTx_DAT_OFST_i[15:5] OFST bit field
to 0x0 so consecutive lines are stored consecutively
in memory (image width and frame-buffer width are
equal).
CSI2_CTX_DAT_OFST_i[15:5] OFST
Keep the ALPHA setting at its reset value (0x0) for
RGB padding.
CSI2_CTX_CTRL3_i[29:16] ALPHA
Enable the contexts.
CSI2_CTX_CTRL1_i[0] CTX_EN
Value
0x1
ISS CSI2 Disable Video/Picture Acquisition
There are two ways to end picture acquisition:
• Disable the corresponding context by setting the CSI2_CTX_CTRL1_i[0] CTX_EN bit to 0. This stops
the acquisition for the current context. Other enabled contexts are still capturing frames and writing
them in memory.
• Disable the CSI2 receiver interface by setting the CSI2_CTRL[0] IF_EN bit to 0. This can have an
immediate effect if the CSI2_CTRL[3] FRAME bit is set to 0, or it can be effective after all the enabled
contexts receive the FEC if the CSI2_CTRL[3] FRAME bit is set to 1.
2.6.4.4
ISS CSI2 Capture a Finite Number of Frames
The CSI2 receiver can be configured to capture a finite number of frames. To configure the CSI2 receiver
in this mode, perform the steps listed in Table 71.
Table 71. ISS CSI2 Capture a Finite Number of Frames
Bit Field
Value
Enable a write to the COUNT bit field.
Step
CSI2_CTX_CTRL1_i[4] COUNT_UNLOCK
0x1
Set the bit field to the number of frames the CSI2
receiver must capture.
CSI2_CTX_CTRL1_i[15:8] COUNT
Valid values are 0 to
255; 0 is infinite capture
and 1 to 255 defines the
number of frames to
capture.
Disable a write to the COUNT bit field.
CSI2_CTX_CTRL1_i[4] COUNT_UNLOCK
0x0
During frame capture, the COUNT bit field is decremented by 1 at each frame capture. Software reads the
COUNT bit field to know how many frames must still be captured.
The COUNT bit can be updated during capture if the COUNT_UNLOCK bit is set to 1.
2.6.4.5
ISS CSI2 Configure a Periodic Event During Frame Acquisition
The CSI2 receiver can generate a periodic event. This line number is defined in the
CSI2_CTX_CTRL3_i[15:0] LINE_NUMBER bit field. The event can be generated once or multiple times
per frame, depending on the value of the CSI2_CTX_CTRL1_i[1] LINE_MODULO bit:
• If the LINE_MODULO bit = 0, the event is generated when the line number corresponding to the
LINE_NUMBER bit field is received.
• If the LINE_MODULO bit = 1, the event is generated when the line number received corresponds to a
multiple of the LINE_NUMBER value (LINE_NUMBER is used as a modulo).
2.6.4.6
ISS CSI2 Linking a Context to a Virtual Channel and a Data Type
The CSI2 receiver supports eight contexts and the CSI2 protocol defines four virtual channels. Therefore,
a CSI2 receiver context can be associated with a virtual channel and a data type. Virtual channels are
defined by a 2-bit field. Valid data types for the CSI2 receiver with their associated values are described in
the CSI2_CTX_CTRL2_i[9:0] FORMAT bit field.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
157
ISS Interfaces
www.ti.com
For each context, a CSI2_CTX_CTRL2_i register defines with which channel and data type the context is
associated:
• The VIRTUAL_ID bit field defines the associated virtual ID transported by the CSI2 protocol from the
camera sensor.
• The FORMAT bit field defines the associated data type. The data type is a combination of the data
type transported by the CSI2 protocol and the type of storage in memory. A given data type (RGB888)
can be stored in memory in different ways (RGB888 or RGB888 + EXP32). Therefore, the FORMAT bit
field also defines how DMA stores data in memory.
For example, for the current context to capture a frame from virtual channel 2 and data type RAW12 with
data expansion (RAW12 + EXP16), write the value 0x10AC (0x2 11 + 0xAC) in the 16 LSBs of the
CSI2_CTX_CTRL2_i register.
2.6.4.7
ISS CSI2 Progressive and Interleaved Frame Configuration
The CSI2 receiver can treat progressive and interlaced frames. There is no progressive or interleaved
mode, but the CSI2_CTX_CTRL1_i[23:16] FEC_NUMBER bit field controls the number of FECs before
swapping to the other (ping or pong) buffer. Therefore, two modes are possible:
• FEC_NUMBER = 1: This is equivalent to progressive mode. After a FEC on the context, the current
buffer is switched (ping to pong or pong to ping). The image in the memory buffer consists of one
transmitted frame.
• FEC_NUMBER 1: The current buffer is switched (ping to pong or pong to ping) after the
FEC_NUMBER FEC is received for the context. The image in the memory buffer consists of the
FEC_NUMBER transmitted frame.
For more information about how data is stored in memory through the DMA, see Section 2.6.3.3.5, DMA
Engine.
NOTE: If FEC_NUMBER 1, the camera sensor must send the line number information with the
current line. Otherwise, the CSI2 receiver cannot calculate each line address.
2.6.4.8
ISS CSI2 Progressive and Interleaved Frame Configuration
Table 72 lists the procedure to enable debug mode.
Table 72. ISS CSI2 Enable Debug Mode
•
•
•
Step
Bit
Value
Enable debug mode.
CSI2_CTRL[7] DBG_EN
0x1
During debug mode the input does not come from the CSI2 receiver interface but from the
CSI2_DBG_H and CSI2_DBG_P registers. The full CSI2 receiver function can be debugged in debug
mode. Full 32-bit values must always be written to the CSI2_DBG_H register. The CSI2_CTRL[0]
IF_EN bit has no affect during debug mode. To reset the FIFO in case of overflow, the CSI2_CTRL[7]
DBG_EN bit must be reset to 0, and the interface must be enabled by setting the CSI2_CTRL[0] IF_EN
bit to 0x1.
The CSI2_DBG_H register is used to provide short packet and long packet headers.
The CSI2_DBG_P register is used to provide long packet payload.
The following examples apply to the CSI2_DBG_H register:
• The sync codes for virtual channel 0 are written as CSI2_DBG_H = 0xFF00 0000 or 0xFF00 0001, or
0xFF00 0002 or 0xFF00 0003. To send the RAW12 pixels 0x673, 0x452, 0x01d, 0xefc, 0xab0, 0x891,
0x326, 0x547, write CSI2_DBG_H = 0x0123 4567, followed by CSI2_DBG_H = 0x89abcdef, and
CSI2_DBG_H = 0x7654 3210.
158
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5
ISS CSI2 Registers
Table 73 lists the CSI2 instances.
Table 73. ISS CSI2 Instance Summary
Module Name
Base Address
Cortex-M3 Private Access
Base Address
L3 Interconnect
Size
ISS_CSI2_A_REGS1
0x5504 1000
0x5C00 1000
368 bytes
ISS_CSI2_A_REGS2
0x5504 11C0
0x5C00 11C0
64 bytes
2.6.5.1
ISS CSI2 REGS1 Registers
Table 74 summarizes the CSI2 REGS1 registers.
Table 74. ISS CSI2 REGS1 Registers Mapping Summary
Register Name
Type
Register
Width
(Bits)
Address Offset
ISS_CSI2_A_REGS1
Base Address
Cortex-M3 Private
Access
ISS_CSI2_A_REGS1
Base Address
L3 Interconnect
CSI2_REVISION
R
32
0x0000 0000
0x5504 1000
0x5C00 1000
RW
32
0x0000 0010
0x5504 1010
0x5C00 1010
CSI2_SYSSTATUS
R
32
0x0000 0014
0x5504 1014
0x5C00 1014
CSI2_IRQSTATUS
RW
32
0x0000 0018
0x5504 1018
0x5C00 1018
CSI2_IRQENABLE
RW
32
0x0000 001C
0x5504 101C
0x5C00 101C
CSI2_CTRL
CSI2_SYSCONFIG
RW
32
0x0000 0040
0x5504 1040
0x5C00 1040
CSI2_DBG_H
W
32
0x0000 0044
0x5504 1044
0x5C00 1044
RESERVED
R
32
0x0000 0048
0x5504 1048
0x5C00 1048
RESERVED
RW
32
0x0000 004C
0x5504 104C
0x5C00 104C
CSI2_COMPLEXIO_CFG
RW
32
0x0000 0050
0x5504 1050
0x5C00 1050
CSI2_COMPLEXIO_IRQSTATUS
RW
32
0x0000 0054
0x5504 1054
0x5C00 1054
RESERVED
RW
32
0x0000 0058
0x5504 1058
0x5C00 1058
CSI2_SHORT_PACKET
R
32
0x0000 005C
0x5504 105C
0x5C00 105C
CSI2_COMPLEXIO_IRQENABLE
RW
32
0x0000 0060
0x5504 1060
0x5C00 1060
RESERVED
RW
32
0x0000 0064
0x5504 1064
0x5C00 1064
CSI2_DBG_P
W
32
0x0000 0068
0x5504 1068
0x5C00 1068
CSI2_TIMING
RW
32
0x0000 006C
0x5504 106C
0x5C00 106C
CSI2_CTX_CTRL1_i
(1)
RW
32
0x0000 0070 +
(0x20 * i)
0x5504 1070 +
(0x20 * i)
0x5C00 1070 +
(0x20 * i)
CSI2_CTX_CTRL2_i
(1)
RW
32
0x0000 0074 +
(0x20 * i)
0x5504 1074 +
(0x20 * i)
0x5C00 1074 +
(0x20 * i)
RW
32
0x0000 0078 +
(0x20 * i)
0x5504 1078 +
(0x20 * i)
0x5C00 1078 +
(0x20 * i)
RW
32
0x0000 007C +
(0x20 * i)
0x5504 107C +
(0x20 * i)
0x5C00 107C +
(0x20 * i)
RW
32
0x0000 0080 +
(0x20 * i)
0x5504 1080 +
(0x20 * i)
0x5C00 1080 +
(0x20 * i)
CSI2_CTX_DAT_OFST_i
(1)
CSI2_CTX_DAT_PING_ADDR_i
(1)
CSI2_CTX_DAT_PONG_ADDR_i
(1)
CSI2_CTX_IRQENABLE_i
(1)
RW
32
0x0000 0084 +
(0x20 * i)
0x5504 1084 +
(0x20 * i)
0x5C00 1084 +
(0x20 * i)
CSI2_CTX_IRQSTATUS_i
(1)
RW
32
0x0000 0088 +
(0x20 * i)
0x5504 1088 +
(0x20 * i)
0x5C00 1088 +
(0x20 * i)
RW
32
0x0000 008C +
(0x20 * i)
0x5504 108C +
(0x20 * i)
0x5C00 108C +
(0x20 * i)
CSI2_CTX_CTRL3_i
(1)
(1)
i = 0 to 7
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
159
ISS Interfaces
2.6.5.1.1
www.ti.com
CSI2_REVISION
Table 75. CSI2_REVISION
Address Offset
0x0000 0000
Physical Address
0x5504 1000
0x5C00 1000
Description
IP Revision Identifier (X.Y.R)
Used by software to track features, bugs, and compatibility
Type
R
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
REVISION
Bits
Field Name
Description
Type
Reset
31:0
REVISION
IP Revision
R
See (1)
(1)
160
TI internal data
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.2
CSI2_SYSCONFIG
Table 76. CSI2_SYSCONFIG
Address Offset
0x0000 0010
Physical Address
0x5504 1010
0x5C00 1010
Description
SYSTEM CONFIGURATION REGISTER
This register is the OCP-socket system configuration register.
Type
RW
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
8
RESERVED
Bits
Field Name
Description
31:14
RESERVED
Reserved
13:12
MSTANDBY_MODE
Sets the behavior of the master port power management
signals.
7
6
5
4
3
2
1
RESERVED
Type
Reset
R
0x00000
RW
0x0
R
0x000
RW
0
RW
1
0
AUTO_IDLE
9
MSTANDBY_MODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SOFT_RESET
Instance
0x0: Force-standby. MStandby is only asserted when the
module is disabled.
0x1: No-standby. MStandby is never asserted.
0x2: Smart-standby: MStandby is asserted based on the
activity of the module. The module will try to go to
standby during the vertical blanking period.
11:2
1
RESERVED
Reserved
SOFT_RESET
Software reset. Set the bit to 1 to trigger a module reset.
The bit is automatically reset by the hardware. During
reads return 0.
0x0: Normal mode.
0x1: The module is reset
Note: Before setting the software reset bit to 1 in
CSI2_SYSCONFIG register, the user must have access
to a CSI2 receiver register.
0
AUTO_IDLE
Internal OCP gating strategy
0x0: OCP clock is free-running.
0x1: Automatic OCP clock gating strategy is applied
based on the OCP interface activity.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
161
ISS Interfaces
2.6.5.1.3
www.ti.com
CSI2_SYSSTATUS
Table 77. CSI2_SYSSTATUS
Address Offset
0x0000 0014
Physical Address
0x5504 1014
0x5C00 1014
Description
SYSTEM STATUS REGISTER
This register provides status information about the module, excluding the interrupt status register.
Type
R
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
9
8
7
6
5
4
3
2
1
RESERVED
Bits
Field Name
Description
Type
Reset
31:1
RESERVED
Reads returns 0.
R
0x0000 0000
RESET_DONE
Internal reset monitoring
R
1
0
0
RESET_DONE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Read 0x1: Reset completed.
Read 0x0: Internal module reset is on going.
162
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.4
CSI2_IRQSTATUS
Table 78. CSI2_IRQSTATUS
Address Offset
0x0000 0018
Physical Address
0x5504 1018
0x5C00 1018
Description
INTERRUPT STATUS REGISTER - All contexts
This register associates one bit for each context in order to determine which context has generated the
interrupt. The context shall be enabled for events to be generated on that context.
If the context is disabled, the interrupt is not generated.
Type
RW
Bits
Field Name
Description
31:15
RESERVED
Reserved
OCP_ERR_IRQ
OCP Error Interrupt
14
0x0: READS: Event is false.
WRITES: Status bit unchanged.
3
CONTEXT3
2
1
Type
Reset
R
0x00000
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
0
CONTEXT0
4
CONTEXT1
5
CONTEXT2
6
CONTEXT4
7
CONTEXT5
8
CONTEXT6
9
CONTEXT7
RESERVED
ECC_NO_CORRECTION_IRQ
ECC_CORRECTION_IRQ
RESERVED
SHORT_PACKET_IRQ
OCP_ERR_IRQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FIFO_OVF_IRQ
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
COMPLEXIO_ERR_IRQ
Instance
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
13
SHORT_PACKET_IRQ
Short packet reception status (other than synch events:
Line Start, Line End, Frame Start, and Frame End: data
type between 0x8 and x0F only shall be considered).
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
12
ECC_CORRECTION_IRQ
ECC has been used to do the correction of the only 1-bit
error status (short packet only).
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
11
ECC_NO_CORRECTION_IRQ
ECC error status (short and long packets). No correction
of the header because of more than 1-bit error.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
10
RESERVED
Reserved
R
0
9
COMPLEXIO_ERR_IRQ
Error signaling from complex I/O: status of the PHY
errors received from the complex I/O (events are defined
in CSI2_COMPLEXIO_IRQSTATUS for the complex I/O).
R
0
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
163
ISS Interfaces
Bits
8
www.ti.com
Field Name
Description
FIFO_OVF_IRQ
FIFO overflow error status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
Type
Reset
RW
W1toClr
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
7
CONTEXT7
Context 7
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
6
CONTEXT6
Context 6
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
5
CONTEXT5
Context 5
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
4
CONTEXT4
Context 4
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
3
CONTEXT3
Context 3
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
2
CONTEXT2
Context 2
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
1
CONTEXT1
Context 1
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
0
CONTEXT0
Context 0
Read 0x1: READS: Event is true (pending).
Read 0x0: READS: Event is false.
164
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.5
CSI2_IRQENABLE
Table 79. CSI2_IRQENABLE
Address Offset
0x0000 001C
Physical Address
0x5504 101C
#INTFC_CSI2_IRQENABLE_Call_4
Description
INTERRUPT ENABLE REGISTER - All contexts
This register associates one bit for each context in order to enable/disable each context individually.
Type
RW
Bits
Field Name
Description
31:15
RESERVED
Reserved
OCP_ERR_IRQ
OCP Error Interrupt
14
3
CONTEXT3
2
1
Type
Reset
R
0x00000
RW
0
RW
0
RW
0
RW
0
0
CONTEXT0
4
CONTEXT1
5
CONTEXT2
6
CONTEXT4
7
CONTEXT5
8
CONTEXT6
9
CONTEXT7
RESERVED
ECC_NO_CORRECTION_IRQ
ECC_CORRECTION_IRQ
RESERVED
SHORT_PACKET_IRQ
OCP_ERR_IRQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FIFO_OVF_IRQ
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
COMPLEXIO_ERR_IRQ
Instance
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
13
SHORT_PACKET_IRQ
Short packet reception (other than synch events: Line
Start, Line End, Frame Start, and Frame End: data type
between 0x8 and x0F only shall be considered).
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
12
ECC_CORRECTION_IRQ
ECC has been used to correct the only 1-bit error (short
packet only).
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
11
ECC_NO_CORRECTION_IRQ
ECC error (short and long packets). No correction of the
header because of more than 1-bit error.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
10
RESERVED
Reserved
RW
0
9
COMPLEXIO_ERR_IRQ
Error signaling from complex I/O: the interrupt is triggered
when any error is received from the complex I/O (events
are defined in CSI2_COMPLEXIO_IRQSTATUS for the
complex I/O).
RW
0
RW
0
RW
0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
8
FIFO_OVF_IRQ
FIFO overflow enable
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
7
CONTEXT7
Context 7
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
165
ISS Interfaces
www.ti.com
Bits
Field Name
Description
6
CONTEXT6
Context 6
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
5
CONTEXT5
Context 5
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
4
CONTEXT4
Context 4
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
3
CONTEXT3
Context 3
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
2
CONTEXT2
Context 2
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
1
CONTEXT1
Context 1
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
0
CONTEXT0
Context 0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
166
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.6
CSI2_CTRL
Table 80. CSI2_CTRL
Address Offset
0x0000 0040
Physical Address
0x5504 1040
0x5C00 1040
Description
GLOBAL CONTROL REGISTER
This register controls the CSI2 RECEIVER module. This register shall not be modified dynamically (except
IF_EN bit field).
Type
RW
Bits
Field Name
Description
31:23
RESERVED
Reserved
22:20
MFLAG_LEVH
Controls assertion of the MFlag[1:0] OCP sideband
signal.
Check the OCP master port definition for details.
3
2
1
Type
Reset
R
0x000
RW
0x0
RW
0x0
RW
0
RW
0
RW
0
0
IF_EN
4
RESERVED
5
ECC_EN
6
FRAME
7
BURST_SIZE
8
VP_OUT_CTRL
9
STREAMING_32_BIT
VP_ONLY_EN
RESERVED
NON_POSTED_WRITE
RESERVED
VP_CLK_EN
BURST_SIZE_EXPAND
MFLAG_LEVL
RESERVED
MFLAG_LEVH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ENDIANNESS
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
DBG_EN
Instance
0x0: 8/8 of the FIFO size
0x1: 7/8 of the FIFO size
0x2: 6/8 of the FIFO size
0x3: 5/8 of the FIFO size
0x4: 4/8 of the FIFO size
0x5: 3/8 of the FIFO size
0x6: 2/8 of the FIFO size
0x7: 1/8 of the FIFO size
19:17
MFLAG_LEVL
Controls assertion of the MFlag[1:0] OCP sideband
signal.
Check the OCP master port definition for details
0x0: 8/8 of the FIFO size
0x1: 7/8 of the FIFO size
0x2: 6/8 of the FIFO size
0x3: 5/8 of the FIFO size
0x4: 4/8 of the FIFO size
0x5: 3/8 of the FIFO size
0x6: 2/8 of the FIFO size
0x7: 1/8 of the FIFO size
16
BURST_SIZE_EXPAND
Sets the DMA burst size on the L3 interconnect.
0x0: Use the burst size defined in the BURST_SIZE
register
0x1: Allow generation of 16x64-bit bursts
15
VP_CLK_EN
VP clock enable.
0x0: The VP clock is disabled.
0x1: The VP clock is enabled.
14
RESERVED
Read returns reset value
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
167
ISS Interfaces
Bits
13
www.ti.com
Field Name
Description
NON_POSTED_WRITE
Not posted writes
Type
Reset
RW
0
R
0
RW
0
RW
0
RW
0x0
RW
0
RW
0x0
RW
0
RW
0
RW
0
RW
0
0x0: Disable
0x1: Enable
12
RESERVED
Reserved
11
VP_ONLY_EN
VP only enable.
0x0: The VP is enabled and the OCP master port is
enabled.
0x1: The VP is enabled and the OCP master port is
disabled.
10
STREAMING_32_BIT
Indicates if 64-bit or 32-bit streaming burst is used.
Valid only if CSI2_CTRL.STREAMING=1
0x0: 64-bit streaming burst is used; byte enable pattern is
0xFF
0x1: 32-bit streaming burst is used; byte enable pattern is
0x0F
9:8
VP_OUT_CTRL
VP_PCLK control.
Sets the VP_PCLK as a function of the ISS interconnect
interface clock (OCPCLK).
0x0: No division: VP_PCLK = OCPCLK.
0x1: Division by 2: VP_PCLK = OCPCLK / 2.
0x3: Division by 4: VP_PCLK = OCPCLK / 4.
0x2: Division by 3: VP_PCLK = OCPCLK / 3.
Example scenarios:
- Low VP_PCLK, Memory - VP: Same as typical memory
- VP, but VP_PCLK = OCPCLK/2
- Typical sensor - VP: Autoidle enabled, FCLK at optimal
rate, sensor provides DPCM compressed RAW12 data at
650 Mbps. Image timings VP_PCLK = (OCPCLK/2) and
SC_CTRL[31:15] FRACDIV = 0xD000 2600 active
pixels/line, 128 blanking pixels, no vertical blanking. (This
scenario corresponds to the OTF operation at maximum
SC speed.)
7
DBG_EN
Enables the debug mode.
0x0: Disable
0x1: Enable
6:5
BURST_SIZE
Sets the DMA burst size on the L3 interconnect.
0x0: 1x64 OCP writes
0x1: 2x64 OCP writes
0x2: 4x64 OCP writes
0x3: 8x64 OCP writes
4
ENDIANNESS
Select endianness for YUV4:2:2 8 bit and YUV4:2:0
legacy formats.
0x0: Use native MIPI CSI2 endianness:
Little endian for all formats except for YUV4:2:2 8b and
YUV4:2:0 Legacy which a big endian.
0x1: Store all pixel formats little endian.
3
FRAME
Set the modality in which IF_EN works.
0x0: If IF_EN = 0 the interface is disabled immediately.
0x1: If IF_EN = 1 the interface is disabled after all FEC
sync code have been received for the active contexts.
2
ECC_EN
Enables the Error Correction Code check for the received
header (short and long packets for all virtual channel ids).
0x0: Disabled
0x1: Enabled
1
168
RESERVED
Read returns reset value
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
0
Field Name
Description
IF_EN
Enables the physical interface to the module.
Type
Reset
RW
0
0x0: The interface is disabled. If FRAME = 0, it is
disabled immediately. If FRAME = 1, it is disabled when
each context has received the FEC sync code.
0x1: The interface is enabled immediately, the data
acquisition starts on the next FSC sync code.
Writing 1 to this register when the current value is 0 has
the effect to clear the output FIFO. The pixel data of the
following frame will be written in the PING buffer, that is,
the CSI2_CTX_CTRL.PING_PONG bits are reset to 0 as
well.
2.6.5.1.7
CSI2_DBG_H
Table 81. CSI2_DBG_H
Address Offset
0x0000 0044
Physical Address
0x5504 1044
0x5C00 1044
Description
DEBUG REGISTER (Header)
This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the
module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The
register is used to write short packets and header of long packets.
Type
W
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
9
8
7
6
5
4
3
2
1
0
DBG
Bits
Field Name
Description
31:0
DBG
32-bit input value.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Type
Reset
W
0x0000 0000
169
ISS Interfaces
2.6.5.1.8
www.ti.com
CSI2_COMPLEXIO_CFG
Table 82. CSI2_COMPLEXIO_CFG
Address Offset
0x0000 0050
Physical Address
0x5504 1050
0x5C00 1050
Description
COMPLEXIO CONFIGURATION REGISTER for the complex I/O
This register contains the lane configuration for the order and position of the lanes (clock and data) and the
polarity order for the control of the PHY differential signals in addition to the control bit for the power FSM.
Type
RW
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
Bits
Field Name
Description
31
RESERVED
Reserved
30
RESET_CTRL
Controls the reset of the complex I/O
6
5
4
3
2
1
0
CLOCK_POSITION
7
CLOCK_POL
8
DATA1_POSITION
9
DATA2_POSITION
DATA2_POL
DATA3_POSITION
DATA3_POL
DATA4_POSITION
RESERVED
DATA4_POL
PWR_AUTO
PWR_STATUS
PWR_CMD
RESET_DONE
RESERVED
RESET_CTRL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA1_POL
Instance
Type
Reset
R
0
RW
0
R
0
RW
0x0
R
0x0
RW
0
R
0x0
RW
0
0x0: Complex I/O reset active.
0x1: Complex I/O reset deasserted.
29
RESET_DONE
Internal reset monitoring of the power domain using the
byte clock provided by the associated CSIPHY (see
Section 1.1.1.1, ISS Clock Domains.
Read 0x1: Reset completed.
Read 0x0: Internal module reset is on going.
28:27
PWR_CMD
Command for power control of the complex I/O
0x0: Command to change to OFF state
0x1: Command to change to ON state
0x2: Command to change to Ultralow-Power state
26:25
PWR_STATUS
Status of the power control of the complex I/O
Read 0x0: Complex I/O in OFF state
Read 0x1: Complex I/O in ON state
Read 0x2: Complex I/O in Ultralow-Power state
24
PWR_AUTO
Automatic switch between ULP and ON states based on
ULPM signals from complex I/O
0x0: Disable
0x1: Enable
23:20
RESERVED
Reserved
19
DATA4_POL
+/- differential pin order of data lane 4.
0x0: +/- pin order
0x1: -/+ pin order
170
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
18:16
Field Name
Description
DATA4_POSITION
Position and order of the data lane 4. The values 6 and 7
are reserved.
Type
Reset
RW
0x0
RW
0
RW
0x0
RW
0
RW
0x0
RW
0
RW
0x0
RW
0
0x0: Not used/connected
0x1: Data lane 4 is at the position 1.
0x2: Data lane 4 is at the position 2.
0x3: Data lane 4 is at the position 3.
0x4: Data lane 4 is at the position 4.
0x5: Data lane 4 is at the position 5.
15
DATA3_POL
+/- differential pin order of data lane 3.
0x0: +/- pin order
0x1: -/+ pin order
14:12
DATA3_POSITION
Position and order of the data lane 3. The values 6 and 7
are reserved.
0x0: Not used/connected
0x1: Data lane 3 is at the position 1.
0x2: Data lane 3 is at the position 2.
0x3: Data lane 3 is at the position 3.
0x4: Data lane 3 is at the position 4.
0x5: Data lane 3 is at the position 5.
11
DATA2_POL
+/- differential pin order of DATA lane 2.
0x0: +/- pin order (csi2_dx=+ and csi2_dy=-)
0x1: -/+ pin order (csi2_dx=- and csi2_dy=+)
10:8
DATA2_POSITION
Position and order of the data lane 2. The values 6 and 7
are reserved.
0x0: Not used/connected
0x1: Data lane 2 is at the position 1.
0x2: Data lane 2 is at the position 2.
0x3: Data lane 2 is at the position 3.
0x4: Data lane 2 is at the position 4.
0x5: Data lane 2 is at the position 5.
7
DATA1_POL
+/- differential pin order of data lane 1.
0x0: +/- pin order (csi2_dx=+ and csi2_dy=-)
0x1: -/+ pin order (csi2_dx=- and csi2_dy=+)
6:4
DATA1_POSITION
Position and order of the DATA lane 1. 0, 6 and 7 are
reserved. The data lane 1 is always present.
0x0: Not used/connected
0x1: Data lane 1 is at the position 1.
0x2: Data lane 1 is at the position 2.
0x3: Data lane 1 is at the position 3.
0x4: Data lane 1 is at the position 4.
0x5: Data lane 1 is at the position 5.
3
CLOCK_POL
+/- differential pin order of clock lane.
0x0: +/- pin order (csi2_dx=+ and csi2_dy=-)
0x1: -/+ pin order (csi2_dx=- and csi2_dy=+)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
171
ISS Interfaces
www.ti.com
Bits
Field Name
Description
2:0
CLOCK_POSITION
Position and order of the clock lane. 0, 6 and 7 are
reserved. The clock lane is always present.
Type
Reset
RW
0x0
0x0: Not used/connected
0x1: Clock lane is at the position 1.
0x2: Clock lane is at the position 2.
0x3: Clock lane is at the position 3.
0x4: Clock lane is at the position 4.
0x5: Reserved
172
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.9
CSI2_COMPLEXIO_IRQSTATUS
Table 83. CSI2_COMPLEXIO_IRQSTATUS
Address Offset
0x0000 0054
Physical Address
0x5504 1054
0x5C00 1054
Description
INTERRUPT STATUS REGISTER - All errors from complex I/O #1
Type
RW
Bits
Field Name
Description
31:27
RESERVED
Reserved
STATEALLULPMEXIT
At least one of the active lanes has exit the ULPM
26
0x0: READS: Event is false.
WRITES: Status bit unchanged.
3
ERRSOTHS4
2
1
Type
Reset
R
0x00
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
0
ERRSOTHS1
4
ERRSOTHS2
5
ERRSOTHS3
6
ERRSOTHS5
7
ERRSOTSYNCHS1
8
ERRSOTSYNCHS2
9
ERRSOTSYNCHS3
ERRESC1
ERRESC2
ERRESC3
ERRESC4
ERRESC5
ERRCONTROL1
ERRCONTROL2
ERRCONTROL3
ERRCONTROL4
ERRCONTROL5
STATEULPM1
STATEULPM2
STATEULPM3
STATEULPM4
STATEULPM5
STATEALLULPMENTER
RESERVED
STATEALLULPMEXIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERRSOTSYNCHS4
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
ERRSOTSYNCHS5
Instance
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
25
STATEALLULPMENTER
All active lanes are entering in ULPM.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
24
STATEULPM5
Lane 5 in ULPM
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
23
STATEULPM4
Lane 4 in ULPM
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
22
STATEULPM3
Lane 3 in ULPM
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
21
STATEULPM2
Lane 2 in ULPM
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
173
ISS Interfaces
Bits
20
www.ti.com
Field Name
Description
STATEULPM1
Lane 1 in ULPM
0x0: READS: Event is false.
WRITES: Status bit unchanged.
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
19
ERRCONTROL5
Control error for lane 5
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
18
ERRCONTROL4
Control error for lane 4
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
17
ERRCONTROL3
Control error for lane 3
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
16
ERRCONTROL2
Control error for lane 2
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
15
ERRCONTROL1
Control error for lane 1
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
14
ERRESC5
Escape entry error for lane 5
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
13
ERRESC4
Escape entry error for lane 4
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
12
ERRESC3
Escape entry error for lane 3
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
11
ERRESC2
Escape entry error for lane 2
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
10
ERRESC1
Escape entry error for lane 1
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
174
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
9
Field Name
Description
ERRSOTSYNCHS5
Start of transmission sync error for lane 5
0x0: READS: Event is false.
WRITES: Status bit unchanged.
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
8
ERRSOTSYNCHS4
Start of transmission sync error for lane 4
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
7
ERRSOTSYNCHS3
Start of transmission sync error for lane 3
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
6
ERRSOTSYNCHS2
Start of transmission sync error for lane 2
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
5
ERRSOTSYNCHS1
Start of transmission sync error for lane 1
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
4
ERRSOTHS5
Start of transmission error for lane 5
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
3
ERRSOTHS4
Start of transmission error for lane 4
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
2
ERRSOTHS3
Start of transmission error for lane 3
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
1
ERRSOTHS2
Start of transmission error for lane 2
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
0
ERRSOTHS1
Start of transmission error for lane 1
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
175
ISS Interfaces
www.ti.com
2.6.5.1.10 CSI2_SHORT_PACKET
Table 84. CSI2_SHORT_PACKET
Address Offset
0x0000 005C
Physical Address
0x5504 105C
0x5C00 105C
Description
SHORT PACKET INFORMATION This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F
Type
R
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
7
6
5
4
3
2
1
SHORT_PACKET
Bits
Field Name
Description
31:24
RESERVED
Reads returns 0.
R
0x00
23:0
SHORT_PACKET
Short Packet information: DATA ID + DATA FIELD
R
0x000000
176
0
Type
Reset
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.11 CSI2_COMPLEXIO_IRQENABLE
Table 85. CSI2_COMPLEXIO_IRQENABLE
Address Offset
0x0000 0060
Physical Address
0x5504 1060
0x5C00 1060
Description
INTERRUPT ENABLE REGISTER - All errors from complex I/O
Type
RW
Bits
Field Name
Description
31:27
RESERVED
Reserved
STATEALLULPMEXIT
At least one of the active lanes has exit the ULPM
26
3
ERRSOTHS4
2
1
Type
Reset
R
0x00
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0
ERRSOTHS1
4
ERRSOTHS2
5
ERRSOTHS3
6
ERRSOTHS5
7
ERRSOTSYNCHS1
8
ERRSOTSYNCHS2
9
ERRSOTSYNCHS3
ERRESC1
ERRESC2
ERRESC3
ERRESC4
ERRESC5
ERRCONTROL1
ERRCONTROL2
ERRCONTROL3
ERRCONTROL4
ERRCONTROL5
STATEULPM1
STATEULPM2
STATEULPM3
STATEULPM4
STATEULPM5
STATEALLULPMENTER
RESERVED
STATEALLULPMEXIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERRSOTSYNCHS4
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
ERRSOTSYNCHS5
Instance
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
25
STATEALLULPMENTER
All active lanes are entering in ULPM.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
24
STATEULPM5
Lane 5 in ULPM
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
23
STATEULPM4
Lane 4 in ULPM
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
22
STATEULPM3
Lane 3 in ULPM
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
21
STATEULPM2
Lane 2 in ULPM
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
20
STATEULPM1
Lane 1 in ULPM
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
19
ERRCONTROL5
Control error for lane 5
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
18
ERRCONTROL4
Control error for lane 4
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
177
ISS Interfaces
Bits
17
www.ti.com
Field Name
Description
ERRCONTROL3
Control error for lane 3
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
16
ERRCONTROL2
Control error for lane 2
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
15
ERRCONTROL1
Control error for lane 1
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
14
ERRESC5
Escape entry error for lane 5
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
13
ERRESC4
Escape entry error for lane 4
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
12
ERRESC3
Escape entry error for lane 3
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
11
ERRESC2
Escape entry error for lane 2
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
10
ERRESC1
Escape entry error for lane 1
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
9
ERRSOTSYNCHS5
Start of transmission sync error for lane 5
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
8
ERRSOTSYNCHS4
Start of transmission sync error for lane 4
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
7
ERRSOTSYNCHS3
Start of transmission sync error for lane 3
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
6
ERRSOTSYNCHS2
Start of transmission sync error for lane 2
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
5
ERRSOTSYNCHS1
Start of transmission sync error for lane 1
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
4
ERRSOTHS5
Start of transmission error for lane 5
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
3
ERRSOTHS4
Start of transmission error for lane 4
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
2
ERRSOTHS3
Start of transmission error for lane 3
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
178
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
1
Field Name
Description
ERRSOTHS2
Start of transmission error for lane 2
Type
Reset
RW
0
RW
0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
0
ERRSOTHS1
Start of transmission error for lane 1
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
2.6.5.1.12 CSI2_DBG_P
Table 86. CSI2_DBG_P
Address Offset
0x0000 0068
Physical Address
0x5504 1068
0x5C00 1068
Description
DEBUG REGISTER (Payload)
This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the
module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The
register is used to write payload of long packets.
Type
W
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
9
8
7
6
5
4
3
2
1
0
DBG
Bits
Field Name
Description
31:0
DBG
32-bit input value.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Type
Reset
W
0x0000 0000
179
ISS Interfaces
www.ti.com
2.6.5.1.13 CSI2_TIMING
Table 87. CSI2_TIMING
Address Offset
0x0000 006C
Physical Address
0x5504 106C
0x5C00 106C
Description
TIMING REGISTER
This register controls the CSI2 RECEIVER module. This register shall not be modified while
CSI2_CTRL.IF_EN is set to 1.
It is used to indicate the number of L3 cycles for the Stop State monitoring.
Type
RW
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
STOP_STATE_X4_IO1
STOP_STATE_X16_IO1
RESERVED
FORCE_RX_MODE_IO1
RESERVED
RESERVED
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
STOP_STATE_COUNTER_IO1
Bits
Field Name
Description
Type
Reset
31
RESERVED
Read returns reset value
RW
0
30
RESERVED
Read returns reset value
RW
1
29
RESERVED
Read returns reset value
RW
1
28:16
RESERVED
Read returns reset value
RW
0x1FFF
FORCE_RX_MODE_IO1
Control of ForceRxMode signal
RW
0
RW
1
RW
1
RW
0x1FFF
15
1
0x0: Deassertion of ForceRxMode. The hardware reset
the bit at the end of the Force RX Mode assertion.
The software can reset the bit in order to stop the
assertion of the ForceRXMode signal prior to the
completion of the period.
0x1: Assertion of ForceRxMode
14
STOP_STATE_X16_IO1
Multiplication factor for the number of L3 cycles defined in
STOP_STATE_COUNTER bit field
0x0: The number of L3 cycles defined in STOP_STATE
_COUNTER is multiplied by 1x
0x1: The number of L3 cycles defined in STOP_STATE
_COUNTER is multiplied by 16x
13
STOP_STATE_X4_IO1
Multiplication factor for the number of L3 cycles defined in
STOP_STATE_COUNTER bit field
0x0: The number of L3 cycles defined in STOP_STATE
_COUNTER is multiplied by 1x
0x1: The number of L3 cycles defined in STOP_STATE
_COUNTER is multiplied by 4x
12:0
180
STOP_STATE_COUNTER_IO1
Stop State counter for monitoring. It indicates the number
of L3 to monitor for Stop State before deasserting
ForceRxMode (complex I/O 1).
The value is from 0 to 8191.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.14 CSI2_CTX_CTRL1_i
Table 88. CSI2_CTX_CTRL1_i
TRANSCODE
FEC_NUMBER
9
8
COUNT
Bits
Field Name
Description
31
BYTESWAP
Allows swapping bytes two by two in the payload data.
It does not affect:
- short packets
- long packet header or footers
- CRC calculation
The purpose is to by swap data send to the OCP port
and/or video port
7
6
5
4
3
2
1
Type
Reset
RW
0
RW
0
R
0x0
RW
0x0
0
CTX_EN
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EOF_EN
RESERVED
GENERIC
31 30 29
LINE_MODULO
RW
VP_FORCE
Type
PING_PONG
CONTROL REGISTER - Context
This register controls the Context. This register is shadowed: modifications are taken into account after the
next FSC sync code.
COUNT_UNLOCK
Description
CS_EN
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
EOL_EN
i = 0 to 7
Instance
28
Index
0x5504 1070 + (0x20 * i)
0x5C00 1070 + (0x20 * i)
HSCALE
0x0000 0070 + (0x20 * i)
Physical Address
BYTESWAP
Address Offset
0x0: Disabled
0x1: Enabled
30
GENERIC
Enables the generic mode.
0x0: Disabled.
Data is received according to
CSI2_CTX_CTRL1.FORMAT and
the long packet code transmitted in the MIPI stream is
used.
0x1: Enabled.
Data is received according to
CSI2_CTX_CTRL1.FORMAT and
the long packet code transmitted in the MIPI stream is
ignored.
29
RESERVED
Reserved
28
HSCALE
Enable horizontal downscaling by a factor of two. Applies
to RAW data when transcoding is enabled.
0x0: Disable
0x1: Enable
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
181
ISS Interfaces
Bits
27:24
www.ti.com
Field Name
Description
TRANSCODE
Enables image transcoding.
When this features is enabled:
- the data format from the camera is defined by the
FORMAT register
- the format after transcode is defined by the
TRANSCODE register. The memory storage / video port
formats is defined by the TRANSCODE register
Type
Reset
RW
0x0
0x0: Feature disabled.
0x1: Outputs DPCM compressed RAW10 data.
After compression, pixels are coded on 8 bits.
Data in memory is organized as regular RAW8 data
0x2: Outputs DPCM compressed RAW12 data.
After compression, pixels are coded on 8 bits.
Data in memory is organized as regular RAW8 data
0x3: Outputs A-Law compressed RAW10 data.
After compression, pixels are coded on 8 bits.
Data in memory is organized as regular RAW8 data.
0x4: Outputs uncompressed RAW8 data.
Data in memory is organized as regular RAW8 data
0x5: Outputs uncompressed RAW10 data.
Data in memory is organized as regular RAW10+EXP16
data
0x6: Outputs uncompressed RAW10 data.
Data in memory is organized as regular packed RAW10
data
0x7: Outputs uncompressed RAW12 data.
Data in memory is organized as regular RAW12+EXP16
data
0x8: Outputs uncompressed RAW12 data.
Data in memory is organized as regular packed RAW12
data
0x9: Outputs uncompressed RAW14 data.
23:16
FEC_NUMBER
Number of FEC to receive between using swap of
CSI2_CTX_DAT_PING_ADDR and
CSI2_CTX_DAT_PONG_ADDR for the calculation of the
address in memory (must be used only in interlace mode,
otherwise set to 1).
RW
0x01
15:8
COUNT
Sets the number of frame to acquire. Once the frame
acquisition starts, the COUNT value is decremented after
every frame. When COUNT reaches 0, the
FRAME_NUMBER_IRQ interrupt is triggered and
CTX_EN is set to 0.
Writes to this bit field are controlled by the
COUNT_UNLOCK bit. During the same OCP write
access, the bit field COUNT_UNLOCK shall be written in
addition to COUNT bit field in order to change the
COUNT value. COUNT can be overwritten dynamically
with a new count value.
0: Infinite number of frames (no count).
1: 1 frame to acquire
...
255: 255 frames to acquire
RW
0x00
7
EOF_EN
Indicates if the end of frame signal shall be asserted at
the end of the line.
RW
0
Read 0x1: The end of frame signal is asserted at the end
of each frame.
Read 0x0: The end of frame signal is not asserted at the
end of each frame.
182
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
6
Field Name
Description
EOL_EN
Indicates if the end of line signal shall be asserted at the
end of the line.
Type
Reset
RW
0
RW
0
W
0
R
1
RW
0
RW
0
RW
0
Read 0x1: The end of line signal is asserted at the end of
each frame.
Read 0x0: The end of line signal is not asserted at the
end of each frame.
5
CS_EN
Enables the checksum check for the received payload
(long packet only).
0x0: Disabled
0x1: Enabled
4
COUNT_UNLOCK
Unlock writes to the COUNT bit field.
Write 0x0: COUNT bit field is locked. Writes have no
effect
Write 0x1: COUNT bit field is unlocked. Writes are
possible.
3
PING_PONG
Indicates whether the PING or PONG destination
address (CSI2_CTX_DAT_PING_ADDR or
CSI2_CTX_DAT_PONG_ADDR) was used to write the
last frame.
This bit field toggles after every FEC_NUMBER FEC
sync code received for the current context.
Read 0x1: PONG buffer
Read 0x0: PING buffer
2
VP_FORCE
Forces sending of the data to both VPORT and OCP.
Only applies to formats that existing in two versions:
- One sending data to OCP port only
- One sending data to VPORT only (tagged with the +VP
extension)
The format version sending data only to OCP should be
chosen.
0x0: Disabled
0x1: Enabled
1
LINE_MODULO
Line modulo configuration
0x0: CSI2_CTX_CTRL3.LINE_NUMBER is used once
per frame for the generation of the LINE_NUMBER_IRQ.
0x1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a
modulo number for the generation of the
LINE_NUMBER_IRQ (multiple times the interrupt can be
generated for each frame)
0
CTX_EN
Enables the context
0x0: Disabled
0x1: Enabled
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
183
ISS Interfaces
www.ti.com
2.6.5.1.15 CSI2_CTX_CTRL2_i
Table 89. CSI2_CTX_CTRL2_i
Address Offset
0x0000 0074 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1074 + (0x20 * i)
0x5C00 1074 + (0x20 * i)
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
Description
CONTROL REGISTER - Context
This register controls the Context. This register is shadowed: modifications are taken into account after the
next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and
FORMAT has to occur only when the context is disabled (CSI2_CTX_CTRL1.CTX_EN).
Type
RW
Bits
31:16
15
14:13
9
8
7
6
DPCM_PRED
VIRTUAL_ID
FRAME
USER_DEF_MAPPING
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
5
4
3
2
1
0
FORMAT
Field Name
Description
Type
Reset
FRAME
Frame number received
R
0x0000
RESERVED
Reserved
R
0
USER_DEF_MAPPING
Selects the pixel format of USER_DEFINED in FORMAT
RW
0x0
RW
0x0
RW
0
RW
0x000
0x0: RAW6
0x1: RAW7
0x2: RAW8 (not valid if FORMAT is
USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x
from 1 to 8)
12:11
VIRTUAL_ID
Virtual channel ID
0x0: Virtual Channel ID 0
0x1: Virtual Channel ID 1
0x2: Virtual Channel ID 2
0x3: Virtual Channel ID 3
10
DPCM_PRED
Selects the DPCM predictor.
0x0: The advanced predictor is used.
Not supported for 10- 8- 10 algorithm.
Performance limited to 1 pixel/cycle.
0x1: The simple predictor is used.
9:0
FORMAT
Data format selection.
0x0: OTHERS (except NULL and BLANKING packets)
0x12: Embedded 8-bit nonimage data (that is, JPEG)
0x18: YUV4:2:0 8 bit
0x19: YUV4:2:0 10 bit
0x1A: YUV4:2:0 8bit legacy
0x1C: YUV4:2:0 8 bit + CSPS
0x1D: YUV4:2:0 10bit + CSPS
0x1E: YUV4:2:2 8 bit
0x1F: YUV4:2:2 10 bit
0x22: RGB565
0x24: RGB888
184
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
Field Name
Description
Type
Reset
0x28: RAW6
0x29: RAW7
0x2A: RAW8
0x2B: RAW10
0x2C: RAW12
0x2D: RAW14
0x33: RGB666 + EXP32_24
0x40: USER_DEFINED_8_BIT_DATA_TYPE_1
0x41: USER_DEFINED_8_BIT_DATA_TYPE_2
0x42: USER_DEFINED_8_BIT_DATA_TYPE_3
0x43: USER_DEFINED_8_BIT_DATA_TYPE_4
0x44: USER_DEFINED_8_BIT_DATA_TYPE_5
0x45: USER_DEFINED_8_BIT_DATA_TYPE_6
0x46: USER_DEFINED_8_BIT_DATA_TYPE_7
0x47: USER_DEFINED_8_BIT_DATA_TYPE_8
0x68: RAW6 + EXP8
0x69: RAW7 + EXP8
0x80: USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8
0x81: USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8
0x82: USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8
0x83: USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8
0x84: USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8
0x85: USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8
0x86: USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8
0x87: USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8
0x9E: YUV4:2:2 8bit + VP
0xA0: RGB444 + EXP16
0xA1: RGB555 + EXP16
0xAB: RAW10 + EXP16
0xAC: RAW12 + EXP16
0xAD: RAW14 + EXP16
0xDE: Same as YUV4:2:2 8bit + VP, but data is sent as
16-bit wide words to video port.
Could be used together with the GENERIC and
BYTESWAP features.
0xE3: RGB666 + EXP32
0xE4: RGB888 + EXP32
0xE8: RAW6 + DPCM10 + VP
0x12A: RAW8 + VP
0x12C: RAW12 + VP
0x12D: RAW14 + VP
0x12F: RAW10 + VP
0x140:
USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP
0x141:
USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP
0x142:
USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP
0x143:
USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP
0x144:
USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
185
ISS Interfaces
Bits
Field Name
www.ti.com
Description
Type
Reset
0x145:
USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP
0x146:
USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP
0x147:
USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP
0x1C0:
USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP
16
0x1C1:
USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP
16
0x1C2:
USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP
16
0x1C3:
USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP
16
0x1C4:
USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP
16
0x1C5:
USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP
16
0x1C6:
USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP
16
0x1C7:
USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP
16
0x229: RAW7 + DPCM10 + EXP16
0x2A8: RAW6 + DPCM10 + EXP16
0x2AA: RAW8 + DPCM10 + EXP16
0x2C0: USER_DEFINED_8_BIT_DATA_TYPE_1 +
DPCM10 + EXP16
0x2C1: USER_DEFINED_8_BIT_DATA_TYPE_2 +
DPCM10 + EXP16
0x2C2: USER_DEFINED_8_BIT_DATA_TYPE_3 +
DPCM10 + EXP16
0x2C3: USER_DEFINED_8_BIT_DATA_TYPE_4 +
DPCM10 + EXP16
0x2C4: USER_DEFINED_8_BIT_DATA_TYPE_5 +
DPCM10 + EXP16
0x2C5: USER_DEFINED_8_BIT_DATA_TYPE_6 +
DPCM10 + EXP16
0x2C6: USER_DEFINED_8_BIT_DATA_TYPE_7 +
DPCM10 + EXP16
0x2C7: USER_DEFINED_8_BIT_DATA_TYPE_8 +
DPCM10 + EXP16
0x329: RAW7 + DPCM10 + VP
0x32A: RAW8 + DPCM10 + VP
0x340: USER_DEFINED_8_BIT_DATA_TYPE_1 +
DPCM10 + VP
0x341: USER_DEFINED_8_BIT_DATA_TYPE_2 +
DPCM10 + VP
0x342: USER_DEFINED_8_BIT_DATA_TYPE_3 +
DPCM10 + VP
0x343: USER_DEFINED_8_BIT_DATA_TYPE_4 +
DPCM10 + VP
186
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
Field Name
Description
Type
Reset
0x344: USER_DEFINED_8_BIT_DATA_TYPE_5 +
DPCM10 + VP
0x345: USER_DEFINED_8_BIT_DATA_TYPE_6 +
DPCM10 + VP
0x346: USER_DEFINED_8_BIT_DATA_TYPE_7 +
DPCM10 + VP
0x347: USER_DEFINED_8_BIT_DATA_TYPE_8 +
DPCM10 + VP
0x368: RAW6 DPCM12 + VP
0x369: RAW7 DPCM12 + EXP16
0x36A: RAW8 DPCM12 + EXP16
0x3A8: RAW6 DPCM12 + EXP16
0x3A9: RAW7 DPCM12 + VP
0x3AA: RAW8 DPCM12 + VP
2.6.5.1.16 CSI2_CTX_DAT_OFST_i
Table 90. CSI2_CTX_DAT_OFST_i
Address Offset
0x0000 0078 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1078 + (0x20 * i)
0x5C00 1078 + (0x20 * i)
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
Description
DATA MEM ADDRESS OFFSET REGISTER - Context
This register sets the offset, which is applied on the destination address after each line is written to memory.
This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR.
For example, it enables to perform 2D data transfers of the pixel data into a frame buffer. In such case, the
pixel data and frame buffer data shall have the same data format.
The 5 LSBs are ignored: the offset shall be a multiple of 32 bytes.
This register is shadowed: modifications are taken into account after the next FSC sync code. Only full 32-bit
values shall be written.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
7
6
OFST
Bits
Field Name
Description
31:17
RESERVED
Reserved
16:5
OFST
Line offset programmed in bytes (signed value 2s
complement).
If OFST = 0, the data is written contiguously in memory.
Otherwise, OFST sets the destination offset between the
first pixel of the previous line and the first pixel of the
current line.
4:0
RESERVED
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
5
4
3
2
1
0
RESERVED
Type
Reset
R
0x0000
RW
0x000
R
0x00
187
ISS Interfaces
www.ti.com
2.6.5.1.17 CSI2_CTX_DAT_PING_ADDR_i
Table 91. CSI2_CTX_DAT_PING_ADDR_i
Address Offset
0x0000 007C + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 107C + (0x20 * i)
0x5C00 107C + (0x20 * i)
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
Description
DATA MEM PING ADDRESS REGISTER - Context
This register sets the 32-bit memory address where the pixel data are stored. The destination is double
buffered: this register sets the PING address. Double buffering is enabled when the addresses
CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR are different.
The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary.
This register is shadowed: modifications are taken into account after the next FSC sync code. Only full 32-bit
values shall be written.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
ADDR
3
2
1
0
RESERVED
Bits
Field Name
Description
31:5
ADDR
27 most-significant bits of the 32-bit address.
4:0
RESERVED
Reserved
Type
Reset
RW
0x0000000
R
0x00
2.6.5.1.18 CSI2_CTX_DAT_PONG_ADDR_i
Table 92. CSI2_CTX_DAT_PONG_ADDR_i
Address Offset
0x0000 0080 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1080 + (0x20 * i)
0x5C00 1080 + (0x20 * i)
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
Description
DATA MEM PONG ADDRESS REGISTER - Context
This register sets the 32-bit memory address where the pixel data are stored. The destination is doublebuffered: this register sets the PONG address. Double-buffering is enabled when the addresses
CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR are different.
The 5 LSBs are ignored: the address shall be aligned on a 32-byte boundary.
This register is shadowed: modifications are taken into account after the next FSC sync code. Only full 32-bit
values shall be written.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
ADDR
Bits
Field Name
Description
31:5
ADDR
27 most-significant bits of the 32-bit address.
4:0
RESERVED
Reserved
188
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x00
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.1.19 CSI2_CTX_IRQENABLE_i
Table 93. CSI2_CTX_IRQENABLE_i
RW
9
RESERVED
Bits
Field Name
Description
31:9
RESERVED
Reserved
ECC_CORRECTION_IRQ
Context - ECC has been used to correct the only 1-bit
error (long packet only).
8
8
7
6
5
4
3
LE_IRQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
Type
Reset
R
0x000000
RW
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
0
FS_IRQ
Type
FE_IRQ
INTERRUPT ENABLE REGISTER - Context
This register regroups all the events related to context.
LS_IRQ
Description
RESERVED
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
CS_IRQ
i = 0 to 7
Instance
FRAME_NUMBER_IRQ
Index
0x5504 1084 + (0x20 * i)
0x5C00 1084 + (0x20 * i)
LINE_NUMBER_IRQ
0x0000 0084 + (0x20 * i)
Physical Address
ECC_CORRECTION_IRQ
Address Offset
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
7
LINE_NUMBER_IRQ
Context - Line number is reached.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
6
FRAME_NUMBER_IRQ
Context - Frame counter reached.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
5
CS_IRQ
Context - Check-Sum of the payload mismatch detection
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
4
RESERVED
Reserved
3
LE_IRQ
Context - Line end sync code detection.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
2
LS_IRQ
Context - Line start sync code detection.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
1
FE_IRQ
Context - Frame end sync code detection.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
0
FS_IRQ
Context - Frame start sync code detection.
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
189
ISS Interfaces
www.ti.com
2.6.5.1.20 CSI2_CTX_IRQSTATUS_i
Table 94. CSI2_CTX_IRQSTATUS_i
RW
RESERVED
9
8
7
Bits
Field Name
Description
31:9
RESERVED
Reserved
ECC_CORRECTION_IRQ
Context - ECC has been used to do the correction of the
only 1-bit error status (long packet only).
8
6
5
4
3
LE_IRQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
FS_IRQ
Type
FE_IRQ
INTERRUPT STATUS REGISTER - Context
This register regroups all the events related to Context.
LS_IRQ
Description
RESERVED
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
CS_IRQ
i = 0 to 7
Instance
FRAME_NUMBER_IRQ
Index
0x5504 1088 + (0x20 * i)
0x5C00 1088 + (0x20 * i)
LINE_NUMBER_IRQ
0x0000 0088 + (0x20 * i)
Physical Address
ECC_CORRECTION_IRQ
Address Offset
Type
Reset
R
0x000000
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
R
0
RW
W1toClr
0
RW
W1toClr
0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
7
LINE_NUMBER_IRQ
Context - Line number reached status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
6
FRAME_NUMBER_IRQ
Context - Frame counter reached status
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
5
CS_IRQ
Context - Check-Sum mismatch status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
4
RESERVED
Reserved
3
LE_IRQ
Context - Line end sync code detection status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
2
LS_IRQ
Context - Line start sync code detection status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
190
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
1
Field Name
Description
FE_IRQ
Context - Frame end sync code detection status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
0
FS_IRQ
Context - Frame start sync code detection status.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
2.6.5.1.21 CSI2_CTX_CTRL3_i
Table 95. CSI2_CTX_CTRL3_i
Address Offset
0x0000 008C + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 108C + (0x20 * i)
0x5C00 108C + (0x20 * i)
Instance
ISS_CSI2_A_REGS1_CORTEX-M3
ISS_CSI2_A_REGS1_L3
Description
CONTROL REGISTER - Context
This register controls the Context. This register is shadowed: modifications are taken into account after the
next FSC sync code.
Type
RW
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ALPHA
9
8
7
6
5
4
3
2
1
0
LINE_NUMBER
Bits
Field Name
Description
31:30
RESERVED
Reserved
29:16
ALPHA
15:0
LINE_NUMBER
Type
Reset
R
0x0
Alpha value for RGB888, RGB666 and RBG444.
RW
0x0000
Line number for the interrupt generation
RW
0x0000
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
191
ISS Interfaces
2.6.5.2
www.ti.com
ISS CSI2 REGS2 Registers
Table 96 summarizes the CSI2 REGS2 registers.
Table 96. ISS CSI2 REGS2 Registers Mapping Summary
Register Name
Type
Register
Width
(Bits)
Address Offset
ISS_CSI2_A_REGS2
Base Address
Cortex-M3 Private
Access
ISS_CSI2_A_REGS2
Base Address
L3 Interconnect
CSI2_CTX_TRANSCODEH_i
RW
32
0x0000 0000 +
(0x8 * i)
0x5504 11C0 +
(0x8 * i)
0x5C00 11C0 +
(0x8 * i)
CSI2_CTX_TRANSCODEV_i
RW
32
0x0000 0004 +
(0x8 * i)
0x5504 11C4 +
(0x8 * i)
0x5C00 11C4 +
(0x8 * i)
2.6.5.2.1
CSI2_CTX_TRANSCODEH_i
Table 97. CSI2_CTX_TRANSCODEH_i
Address Offset
0x0000 0000 + (0x8 * i)
Index
i = 0 to 7
Physical Address
0x5504 11C0 + (0x8 * i)
0x5C00 11C0 + (0x8 * i)
Instance
ISS_CSI2_A_REGS2_CORTEX-M3
ISS_CSI2_A_REGS2_L3
Description
Transcode configuration register: defines horizontal frame cropping
Type
RW
9
RESERVED
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
HCOUNT
7
6
5
4
3
2
1
0
HSKIP
Bits
Field Name
Description
31:29
RESERVED
Reserved
28:16
HCOUNT
Pixels to output per line when the values is between 1
and 8191.
Pixels HSKIP-WIDTH pixels are output when
HCOUNT=0.
WIDTH corresponds to the image width provided by the
sensor.
15:13
RESERVED
Reserved
12:0
HSKIP
Pixel to skip horizontally.
Valid values: 0-8191
192
8
Type
Reset
R
0x0
RW
0x0000
R
0x0
RW
0x0000
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.6.5.2.2
CSI2_CTX_TRANSCODEV_i
Table 98. CSI2_CTX_TRANSCODEV_i
Address Offset
0x0000 0004 + (0x8 * i)
Index
i = 0 to 7
Physical Address
0x5504 11C4 + (0x8 * i)
0x5C00 11C4 + (0x8 * i)
Instance
ISS_CSI2_A_REGS2_CORTEX-M3
ISS_CSI2_A_REGS2_L3
Description
Transcode configuration register: defines vertical frame cropping
Type
RW
9
8
RESERVED
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VCOUNT
Bits
Field Name
Description
31:29
RESERVED
Reserved
28:16
VCOUNT
Lines to output per frame when the values is between 1
and 8191.
Pixels VSKIP-HEIGHT pixels are output when
VCOUNT=0.
HEIGHT corresponds to the image height provided by the
sensor.
15:13
RESERVED
Reserved
12:0
VSKIP
Pixel to skip vertically
Valid values: 0-8191
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
7
6
5
4
3
2
1
0
VSKIP
Type
Reset
R
0x0
RW
0x0000
R
0x0
RW
0x0000
193
ISS Interfaces
2.7
2.7.1
www.ti.com
ISS TCTRL
ISS TCTRL Environment
There are no particular environment attributes. See Section 2.2, ISS Interfaces Environment.
2.7.2
ISS TCTRL Integration
Figure 74 shows the integration of the TCTRL.
For information about the power domain, clocks, reset, and hardware requests, see Section 1.2.5, ISS
Power Management.
194
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 74. ISS TCTRL Integration
ISS
ISS interfaces and
interconnects
Config
32b
ISS
interconnect
TCTRL
cam_strobe
cam_global_reset
cam_shutter
ISS_FCLK
CAM_PHY_CTRL_FCLK
PRCM
EOF
VS
STANDBY
STAND
hardware
hardwa
handshake
shake
CPI
CSI2-A
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
195
ISS Interfaces
2.7.3
www.ti.com
ISS TCTRL Functional Description
2.7.3.1
ISS TCTRL Features
The TCTRL generates the control signals (cam_strobe and cam_shutter) for the flash prestrobe, flash
strobe, and mechanical shutters.
The TCTRL includes a timing generator and a control-signal generator.
2.7.3.2
ISS TCTRL Control-Signal Generator
The control-signal generator generates the prestrobe, strobe, and shutter signals: cam_strobe and
cam_shutter. Figure 75 shows the principle of control-signal generation.
Figure 75. TCTRL Control-Signal Generation
Control-signal generator
Shutter
frame
counter
Prestrobe
frame
counter
CAMEVT0
CAMEVT2
Global reset
Strobe
frame
counter
CNTCLK
Shutter
delay
counter
CNTCLK
Shutter
length
counter
Prestrobe
replay
counter
CNTCLK
Prestrobe
replay
counter
CNTCLK
Prestrobe
length
counter
Prestrobe
delay
CNTCLK counter
CNTCLK
NTCLK
Strobe
delay
counter
CNTCLK
Strobe
length
counter
CNTCLK
Reset
length
counter
SHUTTER
PRESTROBE
cam_shutter
cam_strobe
STROBE
TCTRL_CTRL[28:27] N
I SEL
cam_global_reset
CPI_VS
CSI2A_VS
CSI2A_EOF
TCTRL_CTRL[31] GRESETDIR
The control-signal generator gathers precise timings for the cam_strobe and cam_shutter signals, to
assert and deassert the signals at known times. The timing control-signal generator can be synchronized
on the vertical synchronization signal coming from the CSI2-A, parallel interface (CPI), or on an externally
generated cam_global_reset signal.
This multiplexer can also select the externally generated cam_global_reset signal as the trigger event. The
TCTRL_CTRL[31] GRESETDIR bit defines the direction of cam_global_reset.
• The externally generated cam_global_reset is used as a trigger when TCTRL_CTRL[31] GRESETDIR
= 0 and TCTRL_CTRL[28:27] INSEL = 3.
196
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
•
The internally generated cam_global_reset is used as a trigger when TCTRL_CTRL[31] GRESETDIR
= 1 and TCTRL_CTRL[28:27] INSEL = 3.
The cam_global_reset signal can also be generated internally by the control-signal generator under
software control. In this case, the prestrobe and shutter signals are synchronized on internally generated
cam_global_reset . The multiplexer controls whether control-signal generation must be triggered by the
internal or external cam_global_reset.
The prestrobe-, strobe-, and shutter-control signals can be individually enabled at any time. These signals
must not be disabled by software.
The clock divider generates the CNTCLK clock based on the functional clock. The clock divider is
programmable. Table 99 lists the possible frequencies as a function of the divisor values.
Table 99. ISS TCTRL Control-Signal Generator: CNTCLK Frequencies
Divisor Value TCTRL_CTRL[18:10]
DIVC
CNTCLK Clock
CNTCLK Precision (ns)
0 (default)
Clock gated. No clock.
N/A
1
200 MHz
5
2
100 MHz
10
3
66,667 MHz
15
20
4
50 MHz
...
...
...
510
0.392 MHz
2550
511
0.391 MHz
2555
There are three counters per control signal, for a total of nine counters. Each counter is programmable.
• The frame counter is decreased each time a full new frame is received.
– A new frame is detected by the TCTRL module when CAMEVTx is received.
– The frame counter determines how many whole frames must be ignored before the delay counter is
triggered. The frame counters can be set to 0 to bypass the frame counters.
• The delay counter determines the control-signal activation delay. The counter is decreased at every
CNTCLK clock cycle. When the counter reaches 0, the control signal is asserted. If the delay counter is
set to 0, the control signal is asserted immediately.
• The activation-length counter determines the length of control-signal assertion. The counter is
decreased at every CNTCLK clock cycle. When the counter reaches 0, the signal is deasserted and
the control-signal enable bit is disabled. If the activation length is set to 0, the control signal is not
asserted and the control-signal enable bit is disabled.
The polarity of the following signals can be individually selected:
• TCTRL_CTRL[26] STRBPSTRBPOL for the prestrobe and strobe signals
• TCTRL_CTRL[24] SHUTPOL for the shutter signal
• TCTRL_CTRL[30] GRESETPOL for cam_global_reset
Software can trigger the generation of cam_global_reset to the camera module. The length of signalactivation is programmable. The counter is decreased at every CNTCLK clock cycle. When the counter
reaches 0, the signal is deasserted and the global reset enable bit is disabled (the TCTRL_CTRL[29]
GRESETEN bit). If the activation length is set to 0, the control signal is not asserted and the control-signal
enable bit is disabled. The polarity of cam_global_reset can be selected (the TCTRL_CTRL[30]
GRESETPOL bit).
Figure 76 shows the use of cam_global_reset set as an input or output signal. cam_global_reset is
asynchronous, edge-sensitive, and asserted for at least one interconnect clock cycle.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
197
ISS Interfaces
www.ti.com
Figure 76. ISS TCTRL Use of cam_global_reset With Global Reset Release Camera Modules
A. cam_global_reset is set as an ISS output signal.
Electronic
shutter
Mechanical shutter
ERS
RESET
Electronic shutter
INTEGRATION
ERS
READOUT
Max integration time
Effective integration time
Register write
cam_global_reset (OUT)
OPEN
cam_shutter (OUT)
cam_strobe (OUT)
CLOSE
ON
OFF
OPEN
OFF
B. cam_global_reset is set as an ISS input signal.
Electronic
shutter
ERS
Mechanical shutter
RESET
Electronic shutter
INTEGRATION
ERS
READOUT
Max integration time
Effective integration time
cam_global_reset (INPUT)
OUT))
cam_shutter (OUT)
_strobe (OUT)
cam_strobe
OPEN
OFF
CLOSE
ON
OPEN
OFF
There are two types of shutter mechanisms: mechanical and electronic. A mechanical shutter is used only
for high-resolution sensors. The three control signals (cam_global_reset, cam_shutter, and cam_strobe)
are useful with a mechanical shutter. High frame rates can be achieved only with an electronic shutter.
When an electronic shutter is used, none of the three control signals is used.
• Mechanical shutter mechanism:
– Reset: All pixels of the sensor are reset to their black value. When the sensor has a global reset
feature, the mechanical shutter can be open during reset.
– Integration: The light received by the sensor is transformed into electrical charges that are stored
inside pixels. At the end of the integration time, the shutter must be closed. Exposure time is
defined by the time between reset release and shutter close.
198
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
•
2.7.4
– Readout: The charges accumulated in pixels are converted to digital values that are sent to the
camera receiver.
Electronic rolling shutter (ERS) mechanism:
– Each line of the sensor is reset separately and read after a fixed amount of time. Exposure time is
defined by the time between reset and read.
ISS TCTRL Programming Model
The following settings must be done before enabling the TCTRL.
2.7.4.1
ISS TCTRL Camera-Control Signal Generator
Two configurations apply:
• First configuration: The control signals are based on the vertical synchronization information coming
from the camera module or from externally generated cam_global_reset.
• Second configuration: The control signals are based on internally generated cam_global_reset.
2.7.4.1.1
ISS TCTRL Vertical Sync-Based Control-Signal Generation or Externally Generated
cam_global_reset
To enable control-signal generation in the first configuration, follow the procedure listed in Table 100.
Table 100. ISS TCTRL Enabling the Control-Signal Generation in First Configuration
Step
Bit Field
Value
Select the input that triggers the control signals.
The trigger signal can come from the CSI2-A,
Parallel interface (CPI) or the externally generated
cam_global_reset signal.
TCTRL_CTRL[28:27] INSEL
0x0: CSI2A
0x2: VS signal
0x3: Global reset
Set the global reset as input signal. Writes to the
TCTRL_CTRL[29] GRESETEN bit do not trigger
the CAM_STROBE and CAM_SHUTTER signals
and do not generate the CAM_GLOBAL_RESET
signal.
TCTRL_CTRL[31] GRESETDIR
0x0
The following bits are cleared automatically to 0
after the signal assertion:
• TCTRL_CTRL[21] SHUTEN
• TCTRL_CTRL[22] PSTRBEN
• TCTRL_CTRL[23] STRBEN
Set the polarity of the SHUTTER,
STROBE/PRESTROBE, and cam_global_reset
signals.
• TCTRL_CTRL[24] SHUTPOL
• TCTRL_CTRL[26] STRBPSTRBPOL
• TCTRL_CTRL[30] GRESETPOL
Set the clock divisor value, which generates the
CNTCLK clock The clock is set by CNTCLK =
ISS_FCLK/TCTRL_CTRL[18:10] DIVC.
TCTRL_CTRL[18:10] DIVC
0x0: Disable CNTCLK
0 to 511: Divider
Set the frame counters.
• TCTRL_FRAME[5:0] SHUT
• TCTRL_FRAME[11:6] PSTRB
• TCTRL_FRAME[17:12] STRB
0: TCTRL does not
delay any frame in input.
1 to 63
Set the delay counters.
• TCTRL_SHUT_DELAY
• TCTRL_PSTRB_DELAY
• TCTRL_STRB_DELAY
The possible values are
0 to 225 1 cycles. The
cycles are at the
CNTCLK clock
frequency. The
maximum signal
duration is (225 1) x
511/200 MHz =
85.73157376 s
(TCTRL_CTRL[18:10]
DIVC = 511).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
199
ISS Interfaces
www.ti.com
Table 100. ISS TCTRL Enabling the Control-Signal Generation in First Configuration (continued)
Step
Bit Field
Set the signal durations.
Value
• TCTRL_SHUT_LENGTH
• TCTRL_PSTRB_LENGTH
• TCTRL_STRB_LENGTH
The possible values are
0 to 224 1 cycles. The
cycles are at the
CNTCLK clock
frequency. The
maximum signal
duration for a 200 MHz
input clock is (224 1) x
511/200 MHz =
42.865784325 s
(TCTRL_CTRL.DIVC =
511).
Enable the SHUTTER signal.
TCTRL_CTRL[21] SHUTEN
0x1
Enable the PRESTROBE signal.
TCTRL_CTRL[22] PSTRBEN
0x1
Enable the STROBE signal.
TCTRL_CTRL[23] STRBEN
0x1
2.7.4.1.2
ISS TCTRL Internally Generated cam_global_reset-Based Control-Signal Generation
To enable control-signal generation in the second configuration, follow the procedure listed in Table 101.
Table 101. ISS TCTRL Enabling the Control-Signal Generation in Second Configuration
Bit Field
Value
Select the input to global reset, to loop back the
internally generated GLOBAL_RESET. Vertical
synchronization events do not trigger the
CAM_STROBE and CAM_SHUTTER signals.
Step
TCTRL_CTRL[28:27] INSEL
0x3: Global reset
Set the global reset as output signal.
TCTRL_CTRL[31] GRESETDIR
0x1
The following bits are cleared automatically to 0
after the signal assertion:
•
•
•
•
Set the polarity of the SHUTTER,
STROBE/PRESTROBE, and cam_global_reset
signals.
• TCTRL_CTRL[24] SHUTPOL
• TCTRL_CTRL[26] STRBPSTRBPOL
• TCTRL_CTRL[30] GRESETPOL
Set the clock divisor value, which generates the
CNTCLK clock The clock is set by CNTCLK =
ISS_FCLK/TCTRL_CTRL[18:10] DIVC.
200
TCTRL_CTRL[21]
TCTRL_CTRL[22]
TCTRL_CTRL[23]
TCTRL_CTRL[29]
SHUTEN
PSTRBEN
STRBEN
GRESETEN
TCTRL_CTRL[18:10] DIVC
0x0
0x0: Disable CNTCLK
0 to 511: Divider
Set the frame counters.
• TCTRL_FRAME[5:0] SHUT
• TCTRL_FRAME[11:6] PSTRB
• TCTRL_FRAME[17:12] STRB
0: TCTRL does not
delay any frame in input.
1 to 63
Set the delay counters.
• TCTRL_SHUT_DELAY
• TCTRL_PSTRB_DELAY
• TCTRL_STRB_DELAY
The possible values are
0 to 225 1 cycles. The
cycles are at the
CNTCLK clock
frequency. The
maximum signal
duration is (225 1) x
511/200 MHz =
85.73157376 s
(TCTRL_CTRL[18:10]
DIVC = 511).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 101. ISS TCTRL Enabling the Control-Signal Generation in Second Configuration (continued)
Step
Bit Field
Set the signal durations.
• TCTRL_SHUT_LENGTH
• TCTRL_PSTRB_LENGTH
• TCTRL_STRB_LENGTH
Value
The possible values are
0 to 224 1 cycles. The
cycles are at the
CNTCLK clock
frequency. The
maximum signal
duration for a 200 MHz
input clock is (224 1) x
511/200 MHz =
42.865784325 s
(TCTRL_CTRL.DIVC =
511).
Set the cam_global_reset assertion time.
TCTRL_GRESET_LENGTH
The possible values are
0 to 224 1 cycles. The
cycles are at the
CNTCLK clock
frequency. The
maximum signal
duration for a 200 MHz
input clock is (224 1) x
511/200 MHz =
42.865784325 s
(TCTRL_CTRL.DIVC =
511).
Enable the SHUTTER signal.
TCTRL_CTRL[21] SHUTEN
0x1
Enable the PRESTROBE signal.
TCTRL_CTRL[22] PSTRBEN
0x1
Enable the STROBE signal.
TCTRL_CTRL[23] STRBEN
0x1
Enable the cam_global_reset control-signal
generation.
TCTRL_CTRL[29] GRESETEN
0x1
NOTE: Setting the following bits to 1 simultaneously leads to unpredictable behavior:
•
TCTRL_CTRL[21] SHUTEN
•
TCTRL_CTRL[22] PSTRBEN
•
TCTRL_CTRL[23] STRBEN
•
TCTRL_CTRL [29] GRESETEN
The following bits must be set before TCTRL_CTRL[29] GRESETEN is enabled:
•
•
•
2.7.4.1.3
TCTRL_CTRL[21] SHUTEN
TCTRL_CTRL[22] PSTRBEN
TCTRL_CTRL[23] STRBEN
ISS TCTRL STROBE and PRESTROBE Signal Generation for Red-Eye Removal
The STROBE and PRESTROBE signal generation enables a strobe flash for red-eye removal. The
process is shown in Figure 77. The dotted line corresponds to known timings from which the delay
counters start decreasing: cam_global_reset event.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
201
ISS Interfaces
www.ti.com
Figure 77. cam_strobe Signal-Generation for Red-Eye Removal
cam_global_reset event
t1
t2
t5
PRESTROBE
t4
t3
STROBE
OFF
cam_strobe=PRESTROBE or STROBE
•
•
•
•
•
2.7.5
ON OFF ON OFF ON
OFF
ON
t1: Set by the TCTRL_PSTRB_DELAY register
t2: Set by the TCTRL_PSTRB_LENGTH register
t5: Set by the TCTRL_PSTRB_REPLAY[24:0] DELAY bit field. The number of times the pulse is
repeated is controlled by the TCTRL_PSTRB_REPLAY[31:25] COUNTER bit field.
In the previous example, TCTRL_PSTRB_REPLAY[31:25] COUNTER = 2.
– The possible delay values are 0 to 225 1 cycle. The cycles are at the CNTCLK clock frequency. The
maximum signal duration is (225 1) x 511/200 MHz = 85.73157376 s (TCTRL_CTRL[18:11] DIVC =
511).
– The possible count values are 0 to 127 additional pulses.
t3: Set by the TCTRL_STRB_DELAY register
t4: Set by the TCTRL_STRB_LENGTH register
ISS TCTRL Registers
Table 102 lists the TCTRL instance.
Table 102. ISS TCTRL Instance Summary
Module Name
Base Address
Cortex-M3 Private Access
Base Address
L3 Interconnect
Size
0x5504 0400
0x5C00 0400
256 bytes
ISS_TCTRL
Table 103 summarizes the TCTRL registers.
Table 103. ISS TCTRL Registers Mapping Summary
Register Name
TCTRL_REVISION
202
Type
Register
Width
(Bits)
Address Offset
ISS_TCTRL
Base Address
Cortex-M3 Private
Access
ISS_TCTRL
Base Address
L3 Interconnect
R
32
0x0000 0000
0x5504 0400
0x5C00 0400
TCTRL_SYSCONFIG
RW
32
0x0000 0004
0x5504 0404
0x5C00 0404
TCTRL_SYSSTATUS
R
32
0x0000 0008
0x5504 0408
0x5C00 0408
TCTRL_STRB_LENGTH
RW
32
0x0000 0010
0x5504 0410
0x5C00 0410
TCTRL_PSTRB_LENGTH
RW
32
0x0000 0014
0x5504 0414
0x5C00 0414
TCTRL_SHUT_LENGTH
RW
32
0x0000 0018
0x5504 0418
0x5C00 0418
TCTRL_GRESET_LENGTH
RW
32
0x0000 001C
0x5504 041C
0x5C00 041C
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 103. ISS TCTRL Registers Mapping Summary (continued)
Register Name
Type
Register
Width
(Bits)
Address Offset
ISS_TCTRL
Base Address
Cortex-M3 Private
Access
ISS_TCTRL
Base Address
L3 Interconnect
TCTRL_STRB_DELAY
RW
32
0x0000 0020
0x5504 0420
0x5C00 0420
TCTRL_PSTRB_DELAY
RW
32
0x0000 0024
0x5504 0424
0x5C00 0424
TCTRL_SHUT_DELAY
RW
32
0x0000 0028
0x5504 0428
0x5C00 0428
TCTRL_CTRL
RW
32
0x0000 0030
0x5504 0430
0x5C00 0430
TCTRL_PSTRB_REPLAY
RW
32
0x0000 0034
0x5504 0434
0x5C00 0434
TCTRL_FRAME
RW
32
0x0000 0038
0x5504 0438
0x5C00 0438
2.7.5.1
TCTRL_REVISION
Table 104. TCTRL_REVISION
Address Offset
0x0000 0000
Physical Address
0x5504 0400
0x5C00 0400
Description
IP Revision Identifier (X.Y.R)
Used by software to track features, bugs, and compatibility
Type
R
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
9
8
7
6
5
4
3
2
1
0
REVISION
(1)
Bits
Field Name
Description
31:0
REVISION
IP revision
Type
Reset
R
See (1)
TI internal data
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
203
ISS Interfaces
2.7.5.2
www.ti.com
TCTRL_SYSCONFIG
Table 105. TCTRL_SYSCONFIG
0x5504 0404
0x5C00 0404
Description
OCP-SOCKET SYSTEM CONFIGURATION REGISTER
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
Bits
Field Name
Description
31:2
RESERVED
Reserved
SOFT_RESET
Software reset. Set the bit to 1 to trigger the module
reset. The bit is automatically reset be the hardware.
During reads return 0.
1
Type
Reset
1
0
AUTO_IDLE
0x0000 0004
Physical Address
SOFT_RESET
Address Offset
R
0x0000 0000
RW
0
RW
1
0x0: Normal mode.
0x1: The module is reset.
0
AUTO_IDLE
Internal OCP and functional clock gating strategy
0x0: OCP and functional clocks are free-running
0x1: Automatic clock gating strategy is applied, based on
the OCP interface activity for interface clock and on the
functional activity for functional clocks.
2.7.5.3
TCTRL_SYSSTATUS
Table 106. TCTRL_SYSSTATUS
Address Offset
0x0000 0008
Physical Address
0x5504 0408
0x5C00 0408
Description
OCP-SOCKET SYSTEM STATUS REGISTER
Type
R
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
9
8
7
6
5
4
3
2
1
RESERVED
Bits
Field Name
Description
Type
Reset
31:1
RESERVED
Reserved
R
0x0000 0000
RESET_DONE
Internal reset monitoring
R
0
0
0
RESET_DONE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Read 0x1: Reset completed.
Read 0x0: Internal module reset is ongoing.
204
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.7.5.4
TCTRL_STRB_LENGTH
Table 107. TCTRL_STRB_LENGTH
Address Offset
0x0000 0010
Physical Address
0x5504 0410
0x5C00 0410
Description
TIMING CONTROL - STROBE LENGTH REGISTER
This register is used by the TIMING CTRL module to generate the STROBE signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
6
5
4
3
2
1
0
LENGTH
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:0
LENGTH
Sets the length of the CAM_STROBE signal assertion in
cycles of the CNTCLK clock. The CNTCLK frequency is
generated with the TCTRL_CTRL.DIVC bit field. After
signal assertion, the TCTRL_CTRL.STRBEN bit is
automatically cleared. The possible values are 0 to 224-1
cycles.
2.7.5.5
7
Type
Reset
R
0x00
RW
0x000000
TCTRL_PSTRB_LENGTH
Table 108. TCTRL_PSTRB_LENGTH
Address Offset
0x0000 0014
Physical Address
0x5504 0414
0x5C00 0414
Description
TIMING CONTROL - PRESTROBE LENGTH REGISTER
This register is used by the TIMING CTRL module to generate the PRESTROBE signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
7
6
5
4
3
2
1
0
LENGTH
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:0
LENGTH
Sets the length of the CAM_PRESTROBE signal
assertion in cycles of the CNTCLK clock. The CNTCLK
frequency is generated with the TCTRL_CTRL.DIVC bit
field. After signal assertion, the TCTRL_CTRL.PSTRBEN
bit is automatically cleared. The possible values are 0 to
224-1 cycles.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Type
Reset
R
0x00
RW
0x000000
205
ISS Interfaces
2.7.5.6
www.ti.com
TCTRL_SHUT_LENGTH
Table 109. TCTRL_SHUT_LENGTH
Address Offset
0x0000 0018
Physical Address
0x5504 0418
0x5C00 0418
Description
TIMING CONTROL - SHUTTER LENGTH REGISTER
This register is used by the TIMING CTRL module to generate the SHUTTER signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
6
5
4
3
2
1
0
LENGTH
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:0
LENGTH
Sets the length of the CAM_SHUTTER signal assertion in
cycles of the CNTCLK clock. The CNTCLK frequency is
generated with the TCTRL_CTRL.DIVC bit field. After
signal assertion, the TCTRL_CTRL.SHUTEN bit is
automatically cleared. The possible values are 0 to 224-1
cycles.
2.7.5.7
7
Type
Reset
R
0x00
RW
0x000000
TCTRL_GRESET_LENGTH
Table 110. TCTRL_GRESET_LENGTH
Address Offset
0x0000 001C
Physical Address
0x5504 041C
0x5C00 041C
Description
TIMING CONTROL - GLOBAL SHUTTER LENGTH REGISTER
This register is used by the TIMING CTRL module to generate the CAM.GRESET signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:0
LENGTH
Sets the length of the CAM_GLOBAL_RESET signal
assertion in cycles of the CNTCLK clock.
The CNTCLK frequency is generated with the
TCTRL_CTRL.DIVC bit field. After signal assertion, the
TCTRL_CTRL.GRESETEN bit is automatically cleared.
The possible values are 0 to 224-1 cycles.
The polarity of the CAM_GLOBAL_RESET signal is set
by the TCTRL_CTRL.GRESETPOL bit.
206
8
7
6
5
4
3
2
1
0
LENGTH
Type
Reset
R
0x00
RW
0x000000
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.7.5.8
TCTRL_STRB_DELAY
Table 111. TCTRL_STRB_DELAY
Address Offset
0x0000 0020
Physical Address
0x5504 0420
0x5C00 0420
Description
TIMING CONTROL - STROBE DELAY REGISTER
This register is used by the TIMING CTRL module to generate the STROBE signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
6
5
4
3
2
1
0
DELAY
Bits
Field Name
Description
31:25
RESERVED
Reserved
24:0
DELAY
Sets the delay for the CAM_STROBE signal assertion in
cycles of the CNTCLK clock. The CNTCLK frequency is
generated with the TCTRL_CTRL.DIVC bit field. The
possible values are 0 to 225-1 cycles.
2.7.5.9
7
Type
Reset
R
0x00
RW
0x0000000
TCTRL_PSTRB_DELAY
Table 112. TCTRL_PSTRB_DELAY
Address Offset
0x0000 0024
Physical Address
0x5504 0424
0x5C00 0424
Description
TIMING CONTROL - PRE STROBE DELAY REGISTER
This register is used by the TIMING CTRL module to generate the PRESTROBE signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
7
6
5
4
3
2
1
0
DELAY
Bits
Field Name
Description
31:25
RESERVED
Reserved
24:0
DELAY
Sets the delay for the CAM_PSTROBE signal assertion
in cycles of the CNTCLK clock. The CNTCLK frequency
is generated with the TCTRL_CTRL.DIVC bit field. The
possible values are 0 to 225-1 cycles.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Type
Reset
R
0x00
RW
0x0000000
207
ISS Interfaces
2.7.5.10
www.ti.com
TCTRL_SHUT_DELAY
Table 113. TCTRL_SHUT_DELAY
Address Offset
0x0000 0028
Physical Address
0x5504 0428
0x5C00 0428
Description
TIMING CONTROL - SHUTTER DELAY REGISTER
This register is used by the TIMING CTRL module to generate the SHUTTER signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
6
5
4
3
2
1
0
DELAY
Bits
Field Name
Description
31:25
RESERVED
Reserved
24:0
DELAY
Sets the delay for the CAM_SHUTTER signal assertion in
cycles of the CNTCLK clock. The CNTCLK frequency is
generated with the TCTRL_CTRL.DIVC bit field. The
possible values are 0 to 225-1 cycles.
2.7.5.11
7
Type
Reset
R
0x00
RW
0x0000000
TCTRL_CTRL
Table 114. TCTRL_CTRL
Address Offset
0x0000 0030
Physical Address
0x5504 0430
0x5C00 0430
Description
TIMING CONTROL - CONTROL REGISTER
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
RESERVED
SHUTEN
PSTRBEN
STRBEN
SHUTPOL
RESERVED
INSEL
STRBPSTRBPOL
GRESETEN
GRESETDIR
GRESETPOL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
DIVC
7
6
5
4
3
2
0
RESERVED
Bits
Field Name
Description
Type
Reset
31
GRESETDIR
Sets the direction of the GLOBAL_RESET signal.
0x0: INPUT – GLOBAL_RESET is an input to the
TIMING CONTROL module. GLOBAL_RESET is
externally generated.
0x1: OUTPUT – GLOBAL_RESET is an output of the
TIMING CONTROL module. GLOBAL_RESET is
internally generated. If GRESETEN is set to 1, the
internally generated GLOBAL_RESET will trigger the
generation of the PRESTROBE, STROBE and SHUTTER
signals. The frame counters are ignored.
RW
0
30
GRESETPOL
Sets the polarity of the global reset signal:
CAM_GLOBAL_RESET. It applies whatever the direction
of the GLOBAL_RESET signal: input or output.
0x0: active high
0x1: active low
RW
0
208
1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
Field Name
Description
29
GRESETEN
INSEL
28:27
Type
Reset
Triggers the generation of the CAM_GLOBAL_RESET
signal. The signal is asserted immediately. If enabled, the
CAM_GLOBAL_RESET signal will be asserted for
TCTRL_GRESET_LENGTH cycles. After the signal
assertion, the enable bit is automatically cleared to 0.
The polarity of the GLOBAL_RESET signal is set with
TCTRL_CTRL.GRESETPOL.
Enabling this bit triggers the generation of the
CAM_SHUTTER and CAM_STROBE signals (if
previously enabled). The frame counters shall be set to 0
when this bit is set to 1 and GRESETDIR is set a
OUTPUT.
RW
0
Sets the mode that will trigger the SHUTTER,
PRESTROBE and STROBE signals.
RW
0x0
RW
0
R
0
RW
0
0x0: Synchronization event from camera 0
0x1: Synchronization event from camera 1
0x3: GRESET – The CAM_GLOBAL_RESET input signal
will trigger the SHUTTER, PRESTROBE and STROBE
signals. In this mode, there are no frame counters. The
delay counters start decrementing as soon as the
GLOBAL_RESET signal is asserted.
The polarity of the GLOBAL_RESET signal is set with
TCTRL_CTRL.GRESETPOL.
0x2: Synchronization event from camera 2 (serial
interfaces muxed with the camera Parallel interface
(CPI))
26
STRBPSTRBPOL
Sets the polarity of the strobe and prestrobe signals.
0x0: Active high
0x1: Active low
25
RESERVED
Reserved
24
SHUTPOL
Sets the polarity of the mechanical shutter signal:
CAM_SHUTTER
0x0: Active high
0x1: Active low
23
STRBEN
Flash strobe signal enable. If enabled, the STROBE
signal will be asserted after TCTRL_FRAME.STRB
frames have been received and a delay of
TCTRL_STRB_DELAY cycles have passed. The
STROBE signal is asserted for TCTRL_STRB_LENGTH
cycles. After the signal assertion, the enable bit is
automatically cleared to 0.
This signal shall not be disabled by software.
RW
0
22
PSTRBEN
Flash prestrobe signal enable. If enabled, the
PRESTROBE signal will be asserted after
TCTRL_FRAME.PSTRB frames have been received and
a delay of TCTRL_PSTRB_DELAY cycles have passed.
The PRESTROBE signal is asserted for
TCTRL_PSTRB_LENGTH cycles. After the signal
assertion, the enable bit is automatically cleared to 0.
This signal shall not be disabled by software.
RW
0
21
SHUTEN
Mechanical shutter signal enable. If enabled, the
SHUTTER signal will be asserted after
TCTRL_FRAME.SHUT frames have been received and a
delay of TCTRL_SHUT_DELAY cycles have passed. The
SHUTTER signal is asserted for TCTRL_SHUT_LENGTH
cycles. After the signal assertion, the enable bit is
automatically cleared to 0.
This signal shall not be disabled by software.
RW
0
RESERVED
Reserved
R
0x0
20:19
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
209
ISS Interfaces
Bits
18:10
www.ti.com
Field Name
Description
DIVC
Sets the clock divisor value for the CNTCLK clock
generation based on the CLK input clock.
CNTCLK is an internal clock used by the TIMING CTRL
module counters.
Usually, CNTCLK = CLK / DIVC, except for some
particular values shown hereafter.
Type
Reset
RW
0x000
R
0x000
0x0: No clock. CNTCLK is gated.
9:0
RESERVED
2.7.5.12
Reserved
TCTRL_PSTRB_REPLAY
Table 115. TCTRL_PSTRB_REPLAY
Address Offset
0x0000 0034
Physical Address
0x5504 0434
0x5C00 0434
Description
TIMING CONTROL - PRESTROBE REPLAY REGISTER
This register is used by the TIMING CTRL module to generate the prestrobe signal.
Type
RW
Instance
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNTER
9
8
7
6
5
4
3
2
1
Bits
Field Name
Description
Type
Reset
31:25
COUNTER
Sets the number of PRESTROBE pulses after the original
pulse.
If this bit is set to 0, the PRESTROBE signal behavior is
only controlled by TCTRL_FRAME.STRB,
TCTRL_PSTRB_DELAY, and TCTRL_PSTRB_LENGTH.
If TCTRL_PSTRB_LENGTH=0, there is no replay.
This bit is useful when one wants to enable red-eye
removal.
RW
0x00
24:0
DELAY
Sets the delay for the PRESTROBE signal reassertion in
cycles of the CNTCLK clock. The CNTCLK frequency is
generated with the TCTRL_CTRL.DIVC bit field. The
possible values are 0 to 225-1 cycles.
If TCTRL_PSTRB_LENGTH=0, there is no replay. This
bit field shall not be set to 0 if the COUNTER is set to a
value different of 0.
This bit is useful when one wants to enable red-eye
removal.
RW
0x0000000
210
0
DELAY
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.7.5.13
TCTRL_FRAME
Table 116. TCTRL_FRAME
Address Offset
0x0000 0038
Physical Address
0x5504 0438
0x5C00 0438
Description
TIMING CONTROL - FRAME REGISTER
This register is used by the TIMING CTRL module to generate the SHUTTER, PRESTROBE, and
STROBE signals.
Type
RW
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
STRB
Bits
Field Name
Description
31:18
RESERVED
Reserved
17:12
STRB
11:6
5:0
ISS_TCTRL_CORTEX-M3
ISS_TCTRL_L3
9
8
7
6
PSTRB
5
4
3
2
Reset
R
0x0000
Frame counter for the STROBE signal generation. From
0 to 63 frames.
This bit field is ignored if TCTRL.INSEL=GRESET.
RW
0x00
PSTRB
Frame counter for the PRESTROBE signal generation.
From 0 to 63 frames.
This bit field is ignored if TCTRL.INSEL=GRESET.
RW
0x00
SHUT
Frame counter for the SHUTTER signal generation. From
0 to 63 frames.
This bit field is ignored if TCTRL.INSEL=GRESET.
RW
0x00
Copyright © 2013–2016, Texas Instruments Incorporated
0
SHUT
Type
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
1
211
ISS Interfaces
2.8
2.8.1
www.ti.com
ISS BTE
ISS BTE Environment
There are no particular environment attributes (see Section 2.2, ISS Interfaces Environment).
2.8.2
ISS BTE Integration
Figure 78. ISS BTE Integration
ISS
ISS interfaces and
interconnects
ISS
interconnect
TO/FROM
interfaces and ISP
Read
Write
+ Config
BTE
Target
(L3 interconnect + Tiler)
ISS IRQ merger
BTE_IRQ[0]
ISS_FCLK
CAM_PHY_CTRL_FCLK
PRCM
M
STANDBY
hardware
handshake
212
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
For power domain, clocks, reset, and hardware requests, see Section 1.2.5, ISS Power Management.
2.8.2.1
2.8.2.1.1
ISS BTE PRCM Interface
ISS BTE PRCM Handshake
The BTE supports the IDLE protocol to flush outstanding transactions. When an IDLE request is received,
the BTE:
• Completes ongoing requests on OCPI (request, data and response phases) and stalls the port
(SCmdAccept = 0)
• Flushes all contexts (same behavior than when the BTE_CONTEXT_CTRL_i[2] FLUSH bit is set by
software) when the BTE_CONTEXT_CTRL_i[11] AUTOFLUSH bit is set. Otherwise, no context
flushing is triggered by an IDLE request.
• Completes ongoing requests on OCPO (request, data and response phases)
• Acknowledges the IDLE request.
2.8.3
ISS BTE Functional Description
2.8.3.1
ISS BTE Features
The BTE increases access efficiency of raster initiators to tiled SDRAM. In fact, the TILER expects 2Dbursts corresponding to a row or column of subtiles for maximal efficiency.
The BTE is connected between one or multiple raster initiators. It can translate reads and writes. For
reads, BTE prefetches sufficient data from tiled memory to translate raster requests. For writes, BTE
buffers raster requests until is has sufficient data to generate requests to tiled memory. The features of the
BTE are:
• Interfaces:
– 32-bit-wide configuration interface (OCPC)
– 128-bit-wide slave data port (OCPI)
– 128-bit-wide master data port (OCPO)
• Incrementing to 2D burst translation for read and writes:
– Four contexts. A context is a virtual frame buffer attached to a data flow requiring translation.
– One-shot and continuous mode
• Local memories for temporal storage:
– Cannot use external memories for temporal data storage
• Transparent for accesses that do not require translation. Requests are forwarded from OCPI to OCPO
without modification.
• Local buffer
2.8.3.2
ISS BTE Functional Description Details
The main tasks and capabilities of the BTE are:
• Forward OCP transactions that do not need translation.
• For OCP writes requiring translation:
– Store data received from OCPI to local buffers.
– Read data from local buffers and send it to OCPO.
• For OCP read requiring translation:
– Store data received from OCPO to local buffers.
– Read data from local buffers and send it to OCPI.
• BTE DMA capability
Figure 79 is a logical overview of the BTE.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
213
ISS Interfaces
www.ti.com
Dataf from
ISP, sensor interfaces
Data through ISS interconnect
to ISP and SIMCOP
Figure 79. ISS BTE Logical Overview
OCPI
RESP
REQ
DATA
Prefetch
Flush
Extract
context no.
Ac
Access
VIRT_ADDR
VI
Unexpected
ed
address error
rror
MUX
MUX
RESP
REQ
DATA
TILER_ ADDR
(DX D
Y)
(DX, DY)
ADDRGEN
PHY_ ADDR
DIN(128-bit)
Shared
buffer
DOUT(128-bit)
Dataf to
tiled memory
RESP
FIFO
Dataf from
tiled memory
214
MUX
MUX
MUX
Compare
address
(SX
S
Y)
( (SX,
SY)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.8.3.2.1
ISS BTE Burst Translation Principle
The BTE receives raster accesses from the OCPI port and generates TILER accesses on OCPO.
The BTE keeps track of the amount of data written into the local memories. For translated writes, 2D
bursts are sent to OCPO when there is sufficient data in the local memory to generate TILER accesses.
For translated reads, 2D burst are generated to fill the local memory with data that is returned when raster
accesses are received on OCPI. Figure 80 shows the BTE burst translation principle.
Figure 80. ISS BTE Burst Translation Principle
1D burst/raster access
M
2D burst/Tiler access
128 bits
In the following sections, three address spaces are described:
• Virtual: Corresponds to the translated address region on OCPI. Accesses performed to this address
space are translated by the BTE. It can be seen as a 64KB x 8 k lines frame buffer. Locations in this
space are expressed as byte addresses for OCP compliance. However, the access granularity is 128bit (4 LSBs expected to be zeros). For more information about this space, see Section 2.8.3.2.2, ISS
BTE Virtual Address Space and Context Mapping.
• Physical: Corresponds to the addresses used to access the physical buffer of the BTE. The physical
space is addressed in 128-bit-wide words. However, this document refers to byte addresses to
preserve homogeneity.
• Tiler: Corresponds to addresses used by translated accesses. Locations in this space are expressed
as byte addresses for OCP compliance. However, the access granularity is 128-bit (4 LSBs expected
to be zeros). For more information about this space, see Section 2.8.3.2.5, ISS BTE TILER Space
Accesses: 2D Burst Generation.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
215
ISS Interfaces
2.8.3.2.2
www.ti.com
ISS BTE Virtual Address Space and Context Mapping
The location of the virtual space in the address map of OCPI is set by the BTE_CTRL[11:8] BASE bit field.
It always occupies 64KB × 8k lines = 512MB. Software must map a virtual space into an unused region (a
region, for example, that the ISS top level cannot access).
The virtual space is decomposed into contexts. A context corresponds to a 2D region in the virtual space
that requires burst translation. It can also be seen as a virtual frame buffer.
Accesses to different contexts can be interleaved at OCP transaction level. OCP transactions spanning
multiple contexts are not allowed.
When the BTE receives an access from the OCPI port, it performs the following checks:
• If the access address is not between BASE 512MB and (BASE + 1) 512MB 1, it is handled as a
transparent: request and data phases are simply forwarded to the OCPO without modification.
• If the access falls into the translated region:
– If the access is a 2D burst, an IRQ_INVALID event is generated.
– If the access does not map to an active context, an IRQ_INVALID event is generated. The BTE
ignores bits [28:16] for this test.
– Otherwise, context mapping is performed (see Figure 81).
Invalid requests are not forwarded to the OCPO.
Software must ensure that contexts do not overlap. The BTE hardware does not check for this condition.
Wrong setup is likely to lead to corrupted data.
Figure 81. ISS BTE Context Mapping
BASE
BTE_CONTEXT_START_2.X
Context 0
Context 1
BTE_CONTEXT_END_0.Y
BTE_CONTEXT
_END_1.Y
BTE_CONTEXT_END_2.X
Context 2
BTE_CONTEXT
_END_2.Y
No access
expected
(IRQ_INVALID)
8k lines
BTE_CONTEXT_END_0.X
BTE_CONTEXT_START_0.X
No access expected
(IRQ_CTX0_INVALID)
64KB
The BTE internally keeps track of every context where the next access is expected. It internally maintains
a 2D pointer, referred to as (SX_i, SY_i) in the remainder of this document. The expected byte address for
an access into context x is:
ADDR =
BTE_CTRL[11:8] BASE 512MB +
SX_i 16 bytes + SY_i 64KB
If an access to an unexpected location in a given context is received from OCPI, the BTE generates an
IRQ_CTXx_INVALID event. The BTE provides a valid response on OCPI but does not store any data into
the internal buffer. Subsequent accesses are handled normally: in other words, the BTE does not enter
any specific error mode. When this happens, typically an initiator configuration is not aligned with the BTE
context configuration.
216
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The (SX_i, SY_i) pointer of a context is updated on every access to this context. It is reset to SX_i =
BTE_CONTEXT_START_i[15:7] X and SY_x = 0 when a context is enabled. SX_i is incremented by 1 for
every received 16-byte word, except when it equals BTE_CONTEXT_END_i[15:4] X. In that case it is
reset to BTE_CONTEXT_START_i[15:7] X and SY_i is incremented. SY_i is reset when it reaches the
bottom-right corner of the context.
Therefore, the BTE can only translate raster accesses:
• Image data must be provided line by line, starting from the top-left corner of the context.
• A line stride of 64KB is expected.
• The maximum supported image height is 8k lines.
Figure 82 is an example of an active context. There is only one location in an active context where an
access from OCPI is expected (green). Accesses to any other location trigger an IRQ_CTXx_INVALID
event. Reads to contexts in write mode (BTE_CONTEXT_CTRL_i[7:6] MODE = 0) or writes to contexts in
read mode (BTE_CONTEXT_CTRL_i[7:6] MODE = 1) trigger an IRQ_CTXx_INVALID event. When an
access to an expected location is received but the burst length exceeds the context end, an
IRQ_CTXx_INVALID event is triggered.
Figure 82. ISS BTE Expected Access Locations in the Virtual Space
BTE_CONTEXT_END__*.X
ND__*.X
Virtual space mapped to an active context.
No access expected. Data written here by
OCPI has already been forwarded to OCPO.
Write triggers IRQ_CTX0_INVALID.
Virtual space mapped to an active context.
No access expected. Data written here by
OCPI is currently stored in the local buffer.
Write triggers IRQ_CTX0_INVALID.
BTE_CONTEXT_END__*.Y
8k lines
BTE_CONTEXT_START__*.X
Virtual space mapped to an active context.
Next access to this context expected here.
The data is stored in the local buffer.
Virtual space mapped to an active context.
No access expected: previous locations must
be written first.
Write triggers IRQ_CTX0_INVALID.
Virtual space mapped to an active context but
the region is above the context end.
Write triggers IRQ_CTX0_INVALID.
Some alignment constraints are summarized as follows and are shown in Figure 83. They apply only to
translated accesses.
• The context start addresses are aligned on 16-byte boundaries.
• The context width is aligned on 16-byte boundaries.
• The OCPI initiator must not use BYTEEN to qualify subwords in the middle of lines. The BTE interprets
each BYTEEN as 0xFFFF. Access of partial words triggers an IRQ_CTXx_INVALID error.
• The line length sent by the initiator can be 1-byte aligned. The initiator can use BYTEEN to qualify
valid data for the last access of the line. The BTE treats those accesses as full 16-byte writes and
writes 0 data into its local buffers to complete the access. Those 0s are forwarded to OCPO when
burst translation is performed. Software must ensure this data is discarded when the buffer is read
back.
• The BTE does not impose any specific constraint on vertical alignment on the TILER tile and subtile
grids. However, it is strongly recommended to configure the burst generation in such a way the
requests performed to the TILER do not cross tile or subtile boundaries. For more information, see
Section 2.8.3.2.5, ISS BTE TILER Space Accesses: 2D Burst Generation.
• The BTE accepts only one outstanding transaction per OCP tag on the OCPI port. When an initiator
tries to generate an OCP request on a tag ID that is already used (no response has been returned on
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
217
ISS Interfaces
•
•
www.ti.com
OCPI), the OCPI port is stalled.
The amount of memory allocated for each context must be a multiple of 512 bytes. Software must
leave mod(BTE_CONTEXT_END_i BTE_CONTEXT_START_i + 1, 8) unused locations between the
end of the context and the start of the next one. No accesses to this space from OCPI are allowed, but
the BTE can use it to store data.
While programming a BTE context, the BTE context End X value of all contexts must be less than
MEMORY/64 in 128-bit address (equals MEMORY/4 in byte address)
NOTE: The generic BTE MEMORY size can be found by reading the BTE_HL_HWINFO[18:0]
MEMORY bit field.
•
While reading from a BTE-translated location, the SC read burst size must be greater than or equal to (
= ) 16 bytes (128 bits) for correct operation. Bus width translation is performed in the ISS. Therefore,
64-bit accesses lead to 128-bit accesses with BYTEEN = 0x00FF. On the BTE side, BYTEEN is
always processed as 0xFFFF; thus, access to a BTE-translated 128-bit location is not correct if
software uses 64-bit access.
Figure 83 shows the BTE context alignment constraints.
Figure 83. ISS BTE Context Alignment Constraints
BTE_CONTEXT_END__n.X
Last pixel of
the image line
16-byte
boundary
BTE_CONTEXT_START__(n+1).X
B
16-byte
boundary
Last pixel of
the image line
lin
BTE_CONTEXT_END__n.X
Pixel data for context n
Pixel data for context n+1
2.8.3.2.3
16-byte
boundary
0s
Reserved physical space
ISS BTE TILER Context Configuration Example
Global configuration and context configuration must be done before traffic from the master can be
enabled.
This section provides a configuration example used to write YUV4:2:0 data into a 90-degree rotated buffer
(S = 1,/Y = 1,/X = 0). The YUV frame is made up of two objects: Y data (8 bits) and UV data (16 bits).
The BTE provides data orientation and format information to the TILER using a 33-bit address. It can be
controlled by software using the BTE_CONTEXT_BASE_i and BTE_CONTEXT_CTRL_i[12] ADDR32 bits.
ADDR32 must be set to 1. Bits [31:27] of the address control the accessed view format. Table 117 is an
example of a BTE TILER context configuration.
Figure 84 shows BTE TILER mode addressing in 90- or 270-degree orientation.
Table 117. ISS BTE TILER Context Configuration Example
32
31
T
1
30
29
28
/X
M1
Orientation
S
/Y
27
Mode
26 ... 4
3 ... 0
Virtual Address
M0
A26 ... A4
0
For the example described here, the following settings are used:
218
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
90-degree view, 8-bit data
90-degree view, 16-bit data
ADDR[32:27] = 0b1 110 00
ADDR[32:27] = 0b1 110 01
Software must also configure the BTE_CONTEXT_CTRL_i[9:8] GRID bit field to match the view and
format set by the base address:
90-degree view, 8-bit data
90-degree view, 16-bit data
GRID = 1 Stride = 8k
GRID = 1 Stride = 8k
Figure 84. ISS BTE TILER Mode Addressing in 90- or 270-Degree Orientation
Bit no.
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
8 -bit tiled mode
yO
16 -bit tiled mode
yO
11
yO
32 -bit tiled mode
10
9
8
7
6
5
4 3 2 1 0
xO
xO
xO
Bits [26:0] of the BTE_CONTEXT_BASE_i register are used to address a pixel in the virtual space of
TILER. It must point to the top-left corner of the 2D object.
Software must also configure the other context register before it can start it by setting the
BTE_CONTEXT_CTRL_i[0] START bit.
2.8.3.2.4
ISS BTE Local Memory Management
2.8.3.2.4.1 ISS BTE Introduction
The amount of data buffered is defined by the BTE_CONTEXT_CTRL_i[29:16] TRIGGER bit field. In write
mode, translated 2D writes to OCPO are issued when the buffer fill level is greater than or equal to the
value of the BTE_CONTEXT_CTRL_i[29:16] TRIGGER bit field. In read mode, translated 2D reads are
sent to OCPO when the buffer level is less than the value of the BTE_CONTEXT_CTRL_i[29:16]
TRIGGER bit field.
2.8.3.2.4.2 ISS BTE Buffer Flushing
2.8.3.2.4.2.1 ISS BTE One-Shot Mode
One-shot mode is enabled by setting the BTE_CONTEXT_CTRL_i[10] ONESHOT bit.
During normal operation, a data transfer from local memory to the TILER is automatically triggered when
sufficient data is available in the buffer.
Three lines of data remain in the buffer once the OCPI initiator stops sending data into the context.
The BTE supports two ways to flush data remaining in the buffer:
• The last data (bottom-right corner) in a context is written. The last data is defined by the
BTE_CONTEXT_END_i[15:4] X and BTE_CONTEXT_END_i[28:16] Y bit fields.
• Software writes the BTE_CONTEXT_CTRL_i[2] FLUSH bit. This is typically done when the context has
been stopped before the full frame has been written.
An autoflush mode controls automatic context flushing when an IDLE request is received. It can be
activated by setting the BTE_CONTEXT_CTRL_i[11] AUTOFLUSH bit to 1.
During a context flush, all remaining data in the buffer are written to the TILER.
Buffer flushing has lower priority than burst translation active contexts or forwarding transparent accesses.
This prevents performance degradation.
If software wants to abort context operation at a random location, it must disable the context.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
219
ISS Interfaces
www.ti.com
2.8.3.2.4.2.2 ISS BTE Continuous Mode
When continuous mode is selected (the BTE_CONTEXT_CTRL_i[10] ONESHOT bit set to 0), reception of
frame n pushes the data remaining from frame 1 out of the memory to OCPO. This mode is particularly
useful when vertical blanking periods are too short to perform a buffer flush at the end of the frame. Also,
it avoids creating traffic peaks due to buffer flushing.
The frame height must be a multiple of eight lines and the BTE_CONTEXT_CTRL_i[14:13] INITSY bit field
must be 0x0 in continuous mode.
2.8.3.2.4.3 ISS BTE Buffer Prefetch
The buffer must be prefilled before read requests requiring translation can be accepted. Buffer prefetch
starts with the top-left corner of the frame when a context is enabled by setting the
BTE_CONTEXT_CTRL_i[0] START bit. When enough lines have been prefetched, an IRQ_CTXx_DONE
event is triggered to inform software that the context is ready to perform request translation. Typically,
software enables the data flow requiring translation in response to this event. Context ready for
transaction and last transaction can be controlled by BTE_CONTEXT_START and BTE_CONTEXT_END,
respectively.
When a read request requiring translation is received while prefetch is ongoing, an IRQ_CTXx_ERR event
is triggered. It informs software that the read traffic was enabled too early. The BTE returns 0s to OCPI for
the failing request (it does not hold the response until real data is available).
After prefetch completion, when a request requiring translation is received but the required data is missing
(the BTE is waiting for a response from OCPO), the BTE delays the response on OCPI until the missing
data is received on OCPI.
This behavior avoids stalling the OCPI port for too long (that is, a prefetch of up to 3.25 lines of data).
However, it avoids getting errors because of slow OCPI responses.
2.8.3.2.4.4 ISS BTE Bandwidth Limiter
Translated and transparent traffic has higher priority than prefetch and flushing traffic. However, overall
system bandwidth is limited. Requesting too much bandwidth for prefetch and flushing traffic may increase
latencies for higher priority traffic. That could affect higher priority traffic.
Software can limit the speed of prefetching and buffer flushing by using the BTE_CTRL[31:22]
BW_LIMITER bit field. Typically, this register is used to avoid the buffer prefetch and flush traffic using all
the available system bandwidth. This register does not slow down the translated or transparent traffic.
The example in Figure 85 assumes:
• 200-MHz functional clock
• 800 Mbps of transparent traffic = one 8 × 128-bit burst every 32 cycles
Without the bandwidth limiter, prefetch and flush traffic may use up to 3.2 0.8 = 2.4Gbps. Using
BTE_CTRL[31:22] BW_LIMITER = 24 ensures that at a maximum one flush/prefetch request is issued
every 32 cycles. A prefetch/flush request may be delayed by higher priority traffic of OCP port stalls. To
avoid excessive traffic slowdown, the BTE tries to catch up by requesting the next flush/prefetch
transaction earlier.
Figure 85. BTE Bandwidth Limiter Example
Transparent data
Flush attempt
Flush data
32 cycles
2.8.3.2.4.5 ISS BTE Direct Buffer Access
The local buffer can be directly accessed without any burst translation when the
BTE_CONTEXT_CTRL_i[7:6] MODE bit field is set to 2.
220
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The BTE local buffer can be used as general-purpose SRAM accessed from OCPI in this mode. It can
also be used for debug purposes.
2.8.3.2.5
ISS BTE TILER Space Accesses: 2D Burst Generation
2.8.3.2.5.1 ISS BTE Buffer Fill Level
The BTE maintains an internal counter to keep track of the buffer fill level. This internal counter is used to
detect when a translated OCP request is sent to the OCPO port. The counter also accounts for padding
data. Figure 86 shows the BTE buffer fill-level padding.
Figure 86. ISS BTE Buffer Fill-Level Padding
LINE_LENGTH
Top padding
LINE_LENGTH × BTE_CONTEXT_CTRL_i[14:13] INITSY
Payload data
Right padding
Left padding
BTE_CONTEXT_C
BTE_CONTEXT_CTRL_i[15]
INITSX
7 –(BTE_CONTEXT_END[15:7] X and 0xF)
Bottom padding
128-byte
aligned
LINE_LENGTH × 3 –(BTE_CONTEXT_END[28:16]Yand 0x3)
128-byte
aligned
LINE_LENGTH = BTE_CONTEXT_END_i[15:4] × 0xFF8 – (BTE_CONTEXT_START_i[15:7] × 0xFF8) + 8
words of 16 bytes.
Figure 86 is a visual representation of the following explanation about how read or write events are
triggered determined by the internal buffer size.
When context is started, the buffer fill level is initialized to LINE_LENGTH ×
BTE_CONTEXT_CTRL_i[14:13] INITSY + BTE_CONTEXT_CTRL_i[15] INITSX (see the previous
equation for the LINE_LENGTH calculation). If the BTE reads or writes, the level of the internal buffer is
incremented or decremented, respectively, by the burst size. Here, only full 16-byte accesses are
performed. Other OCP BYTEEN patterns are forced to 0xFF.
The BTE_CONTEXT_CTRL_i [29:16] TRIGGER bit field triggers a buffer level read or write even. In write
mode, if flushing, the data level is greater than 0; if not flushing, the BTE translates to OCPO when the
level is greater than or equal to the value set by the register. If the level is smaller than the
BTE_CONTEXT_CTRL_i[29:16] TRIGGER software setup, then the BTE reads data.
2.8.3.2.5.2 ISS BTE OCP Request Generation
Except on borders:
• TILER bursts are 32 bytes × 4 lines of data blocks.
• Bursts are aligned on subtile boundaries.
The BTE maintains an internal 2D pointer (DX_i, DY_i) that corresponds to the top-left corner of the next
access to be issued to the TILER. It is initialized to (0, 0) when a context is enabled or wraps around. It is
updated each time an access to the TILER is performed.
Table 118 lists all supported TILER formats and views.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
221
ISS Interfaces
www.ti.com
Table 118. ISS BTE Supported TILER Formats and Views
Mode
s
8-bit
16-bit
32-bit
View
Description
S
/Y
/X
0
0
0
0-degree view
0
0
1
0-degree view with
vertical mirror
0
1
0
0-degree view with
horizontal mirror
0
1
1
180-degree view
1
0
0
90-degree view with
vertical mirror
1
0
1
270-degree view
1
1
0
90-degree view
1
1
1
90-degree view with
horizontal mirror
0
0
0
0-degree view
0
0
1
0-degree view with
vertical mirror
0
1
0
0-degree view with
horizontal mirror
0
1
1
180-degree view
1
0
0
90-degree view with
vertical mirror
1
0
1
270-degree view
1
1
0
90-degree view
1
1
1
90-degree view with
horizontal mirror
0
0
0
0-degree view
0
0
1
0-degree view with
vertical mirror
0
1
0
0-degree view with
horizontal mirror
0
1
1
180-degree view
1
0
0
90-degree view with
vertical mirror
1
0
1
270-degree view
1
1
0
90-degree view
1
1
1
90-degree view with
horizontal mirror
OFST
Subtile
Grid
1KB
Tile Grid
X
Y
GRID
X
Y
X
Y
LSB
MSB
LSB
MSB
16384
4
4
32
32
0
13
14
26
8192
4
4
32
32
0
12
13
32768
8
2
64
16
0
14
8192
4
4
32
32
0
32768
8
2
64
16
16384
8
2
64
16
Subtile
Aligned
Tile
Aligned
X
Y
X
Y
0
[1:0]
[15:14]
[4:0]
[18:14]
26
1
[1:0]
[14:13]
[4:0]
[17:13]
15
26
2
[2:0]
[15]
[5:0]
[18:15]
12
13
26
1
[1:0]
[14:13]
[4:0]
[17:13]
0
14
15
26
2
[2:0]
[15]
[5:0]
[18:15]
0
13
14
26
3
[2:0]
[14]
[5:0]
[17:14]
222
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The BTE_CONTEXT_BASE_i and BTE_CONTEXT_CTRL_i[9:8] GRID registers must the configured by
software to choose the format and view. The format must match the data stored into the virtual space. The
choice of the view depends on the desired behavior.
The GRID bit field controls the used OCP stride and OCP address generation. The OCP address is
generated using the following formula:
OCP_ADDR = BTE_CONTEXT_BASE_n + DX_x + DY_x Y_LSB
Y_LSB corresponds to the Y LSB column of Table 118.
The OCP stride corresponds to the OFST column of Table 118. The tile and subtile grid information is
currently not used by hardware.
The BTE does not automatically realign 2D bursts on tile or subtile boundaries. However, software can
force the (SX_i, SY_i) (see Section 2.8.3.2.4, ISS BTE Local Memory Management, for the definition of
SY_i) reset value to be used. It is set through the BTE_CONTEXT_CTRL_i[15] INITSX bit and the
BTE_CONTEXT_CTRL_i[14:13] INITSY bit field.
The length and height of the 2D burst is adapted by the BTE to avoid sending dummy data to the TILER.
Figure 87 is an example of BTE 2D burst generation. The vertical start and end of the full 2D frame are
not vertically aligned on the grid.
Figure 87. ISS BTE 2D Burst Generation
BTE_CONTEXT_BASE__x
16 bytes
4 lines
BTE_CONTEXT_END__n.Y
BTE_CONTEXT_CTRL__x.INIT_SY
BTE_CONTEXT_CTRL__x.INIT_SX
1 OCP transaction
Full translated frame
2.8.3.2.6
ISS BTE Posted and Nonposted Write Support
The BTE can handle posted and nonposted writes received on OCPI. Normally, only nonposted writes
should be used.
For transparent accesses, posted and nonposted writes are forwarded to OCPO. The response provided
by OCPO is returned to OCPI.
For translated accesses, the response to posted and nonposted writes is provided by the BTE. It does not
wait for the response of the translated request that is sent to the TILER. In other words, the BTE has no
true nonposted write support for translated accesses. The BTE does not ensure that the data has
effectively been written to the destination memory when it returns the response to a nonposted translated
write.
True nonposted write support is ensured for transparent accesses. Only nonposted writes must be used.
Select nonposted write mode through the BTE_CTRL[5] POSTED bit.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
223
ISS Interfaces
2.8.3.2.7
www.ti.com
ISS BTE Error Reporting
Unexpected accesses are flagged using interrupts. Also, when an SResp = ERR is received on OCPO, an
interrupt is triggered. If the response corresponds to a transparent access, it is forwarded to OCPI.
The BTE is not an OCP checker: It expects only valid and supported transactions from the external world.
Also, it is not intended to detect all types of software errors; few cases are detected. Those cases are
described in the functional description sections.
2.8.3.2.8
ISS BTE Interrupts
All events generated by the module are merged into a single event at ISS level. This event can be
enabled from ISS level by the ISS_HL_IRQENABLE_SET_i[11] BTE_IRQ bit. Table 119 lists the BTE
interrupt events.
Table 119. ISS BTE Interrupt Events
Event
Description
IRQ_OCP_ERR
OCP error received from OCPO master port
IRQ_INVALID
An access to a location that is not mapped to any context has been performed.
For more information, see Section 2.8.3.2.2, ISS BTE Virtual Address Space and Context Mapping.
IRQ_CTXx_DONE
Context has been fully transferred to the TILER.
This interrupt is triggered when flushing completes in one-shot mode. It is triggered once per frame in
continuous mode.
IRQ_CTXx_INVALID
Unexpected address sequence or access direction (read of a context in write mode or write of a context in
read mode).
For more information, see Section 2.8.3.2.2, ISS BTE Virtual Address Space and Context Mapping.
IRQ_CTXx_ERR
Can occur only when a context is configured in read mode.
This request triggers when a read request is received but insufficient data is buffered to perform the
translation. For more information, see Section 2.8.3.2.4.3, ISS BTE Buffer Prefetch.
2.8.3.2.9
ISS BTE Debug Support
The BTE has no specific debug support.
2.8.4
ISS BTE Programming Model
2.8.4.1
ISS BTE Reset
The BTE can accept a general software reset, propagated through all the hierarchy. This reset can be
done to initialize the module and has the same effect as the hardware reset.
1. Set the BTE_HL_SYSCONFIG[0] SOFTRESET bit to 1.
2. Read the BTE_HL_SYSCONFIG[0] SOFTRESET bit to check whether it is set to 1, which means the
reset occurred.
If after five reads, the BTE_HL_SYSCONFIG[0] SOFTRESET bit still returns 0, assume that an error
occurred during the reset stage.
Programmers must not set the BTE_HL_SYSCONFIG[0] SOFTRESET bit to 1 if the BTE is integrated in a
subsystem; it is safer to use the software reset at subsystem level.
NOTE: A software reset does not reset the IDLE protocol signals.
224
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.8.4.2
ISS BTE Interrupts
All events are mapped to a single interrupt output, BTE_IRQ. Table 120 lists the procedure to configure or
manage the BTE interrupts.
Table 120. ISS BTE Configure/Manage Interrupts
Step
Bit Field
Value
Each event that generates an interrupt can be
individually enabled by setting the appropriate bit.
BTE_HL_IRQENABLE_SET
Each event that generates an interrupt can be
individually disabled by setting the adequate bit.
BTE_HL_IRQENABLE_CLR
When an event occurs, the corresponding bit in the BTE_HL_IRQSTATUS_RAW and
BTE_HL_IRQSTATUS_RAW register is set,
BTE_HL_IRQSTATUS
regardless of whether or not the event is enabled.
Bits in the BTE_HL_IRQSTATUS registers are set
only when an enabled event occurs.
Software can clear a pending event by setting the
adequate bit in the BTE_HL_IRQSTATUS register.
2.8.4.3
BTE_HL_IRQSTATUS
ISS BTE Context Configuration
Global configuration and context configuration must be done before traffic from the master can be
enabled.
This section provides a configuration example used to write YUV4:2:0 data into a 90-degree rotated buffer
(S = 1,/Y = 1,/X = 0). The YUV frame consists of two objects: Y data (8 bits) and UV data (16 bits).
The BTE provides data orientation and format information to the TILER using a 33-bit address. It can be
controlled by software using the BTE_CONTEXT_BASE_i and BTE_CONTEXT_CTRL_i[12] ADDR32
registers.
ADDR32 must be set to 1. Bits [31:27] of the address control the accessed view and data format.
Table 121 gives the format of the TILER address. Figure 88 shows BTE tiled mode addressing in 90- or
270-degree orientation.
Table 121. TILER Address Format
9
8
7
6
5
4
3
2
1
0
Virtual Address
M0
Mode
S
X
Orientation
1
Y
T
M1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A26 ... A4
0
For the example described here, the following settings are used.
90-degree view, 8-bit data
90-degree view, 16-bit data
ADDR[32:27] = 0b1 110 00
ADDR[32:27] = 0b1 110 01
Software must also configure the BTE_CONTEXT_CTRL_i[9:8] GRID bit field to match the view and
format set by the base address:
90-degree view, 8-bit data
90-degree view, 16-bit data
GRID = 1 Stride = 8k
GRID = 1 Stride = 8k
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
225
ISS Interfaces
www.ti.com
Figure 88. ISS BTE Tiler Mode Addressing in 90- or 270-Degree Orientation (S = 1)
Bit
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
8-bit tiled mode
yO
16-bit tiled mode
yO
11
10
8
7
6
5
4 3 2 1 0
xO
xO
yO
32-bit
bit tiled mode
9
xO
Bits [26:0] of the BTE_CONTEXT_BASE_i register are used to address a pixel in the virtual space of the
TILER. It must point to the top-left corner of the 2D object.
Software must also configure the other context registers before it can start it by setting the
BTE_CONTEXT_CTRL_i[0] START bit.
2.8.4.4
ISS BTE Change Context Configuration
All contexts operate independently. Software can change the configuration of an inactive context while
other contexts are active and perform request translation.
When software must change the configuration of an active context, it must follow the sequence in
Table 122.
Table 122. ISS BTE Change Context Configuration
Step
Bit Field
Value
Ensure that the initiator does not send any more
data to this context until it is re-enabled.
Disable the context.
• The STOP condition is considered on a valid
OCP boundary.
• It preserves the internal states so that buffer
flushing can be done.
• The BTE no longer translates requests
received for this context. Any transactions
received for an inactive context trigger error
interrupts.
• The BTE completes all outstanding
transactions on OCPO.
BTE_CONTEXT_CTRL_i[1] STOP
0x1
Flush all remaining data for the context, if needed.
If software simply wants to abort the transfer to
recover from some error condition, flushing is not
needed. The context is automatically reset when it
is enabled again.
BTE_CONTEXT_CTRL_i[2] FLUSH
0x1
Wait until the context completes pending OCP
transaction and buffer flush (if enabled). It sets the
IRQ_CTXx_DONE when it becomes idle.
BTE_HL_IRQSTATUS. IRQ_CTXx_DONE
Read 0x0
Change the context configuration.
Enable the context by setting the
BTE_CONTEXT_CTRL_i[0] START bit. Setting the
START bit resets the internal state-machine of the
context.
BTE_CONTEXT_CTRL_i[0] START
0x1
Alternatively, software can change the context mode to one-shot and wait until the CTXx_DONE_IRQ is
triggered.
NOTE: Once a context is disabled it cannot be resumed simply by writing the START bit. In fact,
doing so resets the internal FSM. If data is lost in the buffer, it will be lost.
226
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.8.5
ISS BTE Registers
Table 123 lists the BTE instance.
Table 123. ISS BTE Instance Summary
Module Name
Base Address
Cortex-M3 Private Access
Base Address
L3 Interconnect
Size
0x5504 2000
0x5C00 2000
512 bytes
ISS_BTE
Table 124 summarizes the BTE registers.
Table 124. ISS BTE Registers Mapping Summary
Register Name
BTE_HL_REVISION
BTE_HL_HWINFO
Type
Register
Width
(Bits)
Address Offset
ISS_BTE
Base Address
Cortex-M3 Private
Access
ISS_BTE
Base Address
L3 Interconnect
R
32
0x0000 0000
0x5504 2000
0x5C00 2000
0x5C00 2004
R
32
0x0000 0004
0x5504 2004
BTE_HL_SYSCONFIG
RW
32
0x0000 0010
0x5504 2010
0x5C00 2010
RESERVED
RW
32
0x0000 001C
0x5504 201C
0x5C00 201C
BTE_HL_IRQSTATUS_RAW
RW
32
0x0000 0020
0x5504 2020
0x5C00 2020
BTE_HL_IRQSTATUS
RW
32
0x0000 0024
0x5504 2024
0x5C00 2024
BTE_HL_IRQENABLE_SET
RW
32
0x0000 0028
0x5504 2028
0x5C00 2028
BTE_HL_IRQENABLE_CLR
RW
32
0x0000 002C
0x5504 202C
0x5C00 202C
BTE_CTRL
RW
32
0x0000 0030
0x5504 2030
0x5C00 2030
BTE_CTRL1
RW
32
0x0000 0034
0x5504 2034
0x5C00 2034
BTE_CONTEXT_CTRL_i
(1)
RW
32
0x0000 0040 +
(0x20 * i)
0x5504 2040 +
(0x20 * i)
0x5C00 2040 +
(0x20 * i)
BTE_CONTEXT_BASE_i
(1)
RW
32
0x0000 0044 +
(0x20 * i)
0x5504 2044 +
(0x20 * i)
0x5C00 2044 +
(0x20 * i)
RW
32
0x0000 0048 +
(0x20 * i)
0x5504 2048 +
(0x20 * i)
0x5C00 2048 +
(0x20 * i)
RW
32
0x0000 004C +
(0x20 * i)
0x5504 204C +
(0x20 * i)
0x5C00 204C +
(0x20 * i)
BTE_CONTEXT_START_i
BTE_CONTEXT_END_i
(1)
(1)
(1)
i = 0 to 7
2.8.5.1
BTE_HL_REVISION
Table 125. BTE_HL_REVISION
Address Offset
0x0000 0000
Physical Address
0x5504 2000
0x5C00 2000
Description
IP revision identifier (X.Y.R)
Used by software to track features, bugs, and compatibility
Type
R
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_BTE_CORTEX-M3
ISS_BTE_L3
9
8
7
6
5
4
3
2
1
0
REVISION
(1)
Bits
Field Name
Description
31:0
REVISION
IP revision
Type
Reset
R
See (1)
TI internal data
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
227
ISS Interfaces
2.8.5.2
www.ti.com
BTE_HL_HWINFO
Table 126. BTE_HL_HWINFO
Address Offset
0x0000 0004
Physical Address
0x5504 2004
0x5C00 2004
Description
Information about the hardware configuration of the IP module; that is, typically, the HDL generics (if
any) of the module.
Type
R
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
RESERVED
RESPFIFO
CONTEXTS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits
Field Name
Description
31:24
RESERVED
23:21
RESPFIFO
9
8
7
6
5
4
3
2
1
0
MEMORY
Type
Reset
Reserved
R
0x00
Response FIFO size
R
0x2
R
0x1
R
0x05800
Read 0x0: Reserved
Read 0x1: 16 x 128 bits
Read 0x2: 32 x 128 bits
Read 0x3: 64 x 128 bits
Read 0x4: 128 x 128 bits
Read 0x5: Reserved
Read 0x6: Reserved
Read 0x7: Reserved
20:19
CONTEXTS
Number of contexts
Read 0x0: 2 contexts
Read 0x1: 4 contexts
Read 0x2: 8 contexts
Read 0x3: Reserved
18:0
228
MEMORY
Memory size, in bytes
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.8.5.3
BTE_HL_SYSCONFIG
Table 127. BTE_HL_SYSCONFIG
Description
Clock management configuration
Type
RW
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_BTE_CORTEX-M3
ISS_BTE_L3
9
8
7
6
RESERVED
Bits
Field Name
Description
31:4
RESERVED
Reserved
3:2
IDLEMODE
Configuration of the local target state management mode.
By definition, target can handle read/write transaction as
long as it is out of IDLE state.
5
4
3
2
1
Type
Reset
R
0x0000000
RW
0x2
R
0
RW
0
0
SOFTRESET
0x5504 2010
0x5C00 2010
RESERVED
0x0000 0010
Physical Address
IDLEMODE
Address Offset
0x0: An IDLE request is acknowledged unconditionally
0x1: An IDLE request is never acknowledged
0x2: Smart-idle mode.
Acknowledgment to an IDLE request is given based on
the internal activity of the module.
0x3: Reserved. Do not use
1
RESERVED
Reserved
0
SOFTRESET
Software reset.
Write 0x0: No action
Write 0x1: Initiate software reset
Read 0x1: Reset (software or other) ongoing
Read 0x0: Reset done, no pending action
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
229
ISS Interfaces
2.8.5.4
www.ti.com
BTE_HL_IRQSTATUS_RAW
Table 128. BTE_HL_IRQSTATUS_RAW
Address Offset
0x0000 0020
Physical Address
0x5504 2020
0x5C00 2020
Description
Per-event raw interrupt status vector
Raw status is set even if event is not enabled.
Write 1 to set the (raw) status, mostly for debug.
Type
RW
Bits
31
8
Field Name
Description
IRQ_CTX7_ERR
Read request received before sufficient data has been
prefetched.
7
6
5
4
3
2
RESERVED
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
1
0
IRQ_OCP_ERR
9
IRQ_INVALID
IRQ_CTX2_DONE
IRQ_CTX3_DONE
IRQ_CTX4_DONE
IRQ_CTX5_DONE
IRQ_CTX6_DONE
IRQ_CTX7_DONE
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_ERR
IRQ_CTX1_ERR
IRQ_CTX2_ERR
IRQ_CTX3_ERR
IRQ_CTX4_ERR
IRQ_CTX5_ERR
IRQ_CTX6_ERR
IRQ_CTX7_ERR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_DONE
ISS_BTE_CORTEX-M3
ISS_BTE_L3
IRQ_CTX1_DONE
Instance
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
30
IRQ_CTX6_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
29
IRQ_CTX5_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
28
IRQ_CTX4_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
27
IRQ_CTX3_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
230
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
26
Field Name
Description
IRQ_CTX2_ERR
Read request received before sufficient data has been
prefetched.
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
25
IRQ_CTX1_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
24
IRQ_CTX0_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
231
ISS Interfaces
Bits
17
www.ti.com
Field Name
Description
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
16
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
15
IRQ_CTX7_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
14
IRQ_CTX6_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
13
IRQ_CTX5_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
12
IRQ_CTX4_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
11
IRQ_CTX3_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
10
IRQ_CTX2_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
9
IRQ_CTX1_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
232
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
8
Field Name
Description
IRQ_CTX0_DONE
Write mode: Context has been fully transferred to the
TILER
Read mode: Context prefetch has completed.
Type
Reset
RW
W1toSet
0
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
7:2
1
RESERVED
Reserved
IRQ_INVALID
Invalid access to the virtual space
Write 0x0: No action
R
0x00
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
0
IRQ_OCP_ERR
OCP error received from OCP master port.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
233
ISS Interfaces
2.8.5.5
www.ti.com
BTE_HL_IRQSTATUS
Table 129. BTE_HL_IRQSTATUS
Address Offset
0x0000 0024
Physical Address
0x5504 2024
0x5C00 2024
Description
Per-event "enabled" interrupt status vector.
Enabled status is not set unless event is enabled.
Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not
enabled).
Type
RW
Bits
31
8
Field Name
Description
IRQ_CTX7_ERR
Read request received before sufficient data has been
prefetched.
7
6
5
4
3
2
RESERVED
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
1
0
IRQ_OCP_ERR
9
IRQ_INVALID
IRQ_CTX2_DONE
IRQ_CTX3_DONE
IRQ_CTX4_DONE
IRQ_CTX5_DONE
IRQ_CTX6_DONE
IRQ_CTX7_DONE
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_ERR
IRQ_CTX1_ERR
IRQ_CTX2_ERR
IRQ_CTX3_ERR
IRQ_CTX4_ERR
IRQ_CTX5_ERR
IRQ_CTX6_ERR
IRQ_CTX7_ERR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_DONE
ISS_BTE_CORTEX-M3
ISS_BTE_L3
IRQ_CTX1_DONE
Instance
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
30
IRQ_CTX6_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
29
IRQ_CTX5_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
28
IRQ_CTX4_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
27
IRQ_CTX3_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
234
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
26
Field Name
Description
IRQ_CTX2_ERR
Read request received before sufficient data has been
prefetched.
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
25
IRQ_CTX1_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
24
IRQ_CTX0_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
235
ISS Interfaces
Bits
17
www.ti.com
Field Name
Description
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
16
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
15
IRQ_CTX7_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
14
IRQ_CTX6_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
13
IRQ_CTX5_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
12
IRQ_CTX4_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
11
IRQ_CTX3_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
10
IRQ_CTX2_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
9
IRQ_CTX1_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
236
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
8
Field Name
Description
IRQ_CTX0_DONE
Write mode: Context has been fully transferred to the
TILER
Read mode: Context prefetch has completed.
Type
Reset
RW
W1toClr
0
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
7:2
1
RESERVED
Reserved
IRQ_INVALID
Invalid access to the virtual space
Write 0x0: No action
R
0x00
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
0
IRQ_OCP_ERR
OCP error received from OCP master port.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
237
ISS Interfaces
2.8.5.6
www.ti.com
BTE_HL_IRQENABLE_SET
Table 130. BTE_HL_IRQENABLE_SET
Address Offset
0x0000 0028
Physical Address
0x5504 2028
0x5C00 2028
Description
Per-event interrupt enable bit vector
Write 1 to set (enable interrupt).
Readout equal to corresponding _CLR register.
Type
RW
Bits
31
8
Field Name
Description
IRQ_CTX7_ERR
Read request received before sufficient data has been
prefetched.
7
6
5
4
3
2
RESERVED
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
1
0
IRQ_OCP_ERR
9
IRQ_INVALID
IRQ_CTX2_DONE
IRQ_CTX3_DONE
IRQ_CTX4_DONE
IRQ_CTX5_DONE
IRQ_CTX6_DONE
IRQ_CTX7_DONE
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_ERR
IRQ_CTX1_ERR
IRQ_CTX2_ERR
IRQ_CTX3_ERR
IRQ_CTX4_ERR
IRQ_CTX5_ERR
IRQ_CTX6_ERR
IRQ_CTX7_ERR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_DONE
ISS_BTE_CORTEX-M3
ISS_BTE_L3
IRQ_CTX1_DONE
Instance
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
30
IRQ_CTX6_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
29
IRQ_CTX5_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
28
IRQ_CTX4_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
27
IRQ_CTX3_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
238
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
26
Field Name
Description
IRQ_CTX2_ERR
Read request received before sufficient data has been
prefetched.
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
25
IRQ_CTX1_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
24
IRQ_CTX0_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
239
ISS Interfaces
Bits
17
www.ti.com
Field Name
Description
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
16
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
15
IRQ_CTX7_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
14
IRQ_CTX6_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
13
IRQ_CTX5_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
12
IRQ_CTX4_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
11
IRQ_CTX3_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
10
IRQ_CTX2_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
9
IRQ_CTX1_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
240
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
8
Field Name
Description
IRQ_CTX0_DONE
Write mode: Context has been fully transferred to the
TILER
Read mode: Context prefetch has completed.
Type
Reset
RW
W1toSet
0
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
7:2
1
RESERVED
Reserved
IRQ_INVALID
Invalid access to the virtual space
Write 0x0: No action
R
0x00
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
0
IRQ_OCP_ERR
OCP error received from OCP master port.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
241
ISS Interfaces
2.8.5.7
www.ti.com
BTE_HL_IRQENABLE_CLR
Table 131. BTE_HL_IRQENABLE_CLR
Address Offset
0x0000 002C
Physical Address
0x5504 202C
0x5C00 202C
Description
Per-event interrupt enable bit vector
Write 1 to clear (disable interrupt).
Readout equal to corresponding _SET register.
Type
RW
Bits
31
8
Field Name
Description
IRQ_CTX7_ERR
Read request received before sufficient data has been
prefetched.
7
6
5
4
3
2
RESERVED
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
1
0
IRQ_OCP_ERR
9
IRQ_INVALID
IRQ_CTX2_DONE
IRQ_CTX3_DONE
IRQ_CTX4_DONE
IRQ_CTX5_DONE
IRQ_CTX6_DONE
IRQ_CTX7_DONE
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_ERR
IRQ_CTX1_ERR
IRQ_CTX2_ERR
IRQ_CTX3_ERR
IRQ_CTX4_ERR
IRQ_CTX5_ERR
IRQ_CTX6_ERR
IRQ_CTX7_ERR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_DONE
ISS_BTE_CORTEX-M3
ISS_BTE_L3
IRQ_CTX1_DONE
Instance
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
30
IRQ_CTX6_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
29
IRQ_CTX5_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
28
IRQ_CTX4_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
27
IRQ_CTX3_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
242
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
26
Field Name
Description
IRQ_CTX2_ERR
Read request received before sufficient data has been
prefetched.
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
25
IRQ_CTX1_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
24
IRQ_CTX0_ERR
Read request received before sufficient data has been
prefetched.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
243
ISS Interfaces
Bits
17
www.ti.com
Field Name
Description
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
16
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
15
IRQ_CTX7_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
14
IRQ_CTX6_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
13
IRQ_CTX5_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
12
IRQ_CTX4_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
11
IRQ_CTX3_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
10
IRQ_CTX2_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
9
IRQ_CTX1_DONE
Context has been fully transferred to the TILER
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
244
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
8
Field Name
Description
IRQ_CTX0_DONE
Write mode: Context has been fully transferred to the
TILER
Read mode: Context prefetch has completed.
Type
Reset
RW
W1toClr
0
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
7:2
1
RESERVED
Reserved
IRQ_INVALID
Invalid access to the virtual space
Write 0x0: No action
R
0x00
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
0
IRQ_OCP_ERR
OCP error received from OCP master port.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
245
ISS Interfaces
2.8.5.8
www.ti.com
BTE_CTRL
Table 132. BTE_CTRL
Description
BTE control register
Type
RW
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BW_LIMITER
Bits
RESERVED
9
8
BASE
Field Name
Description
31:22
BW_LIMITER
Minimum number of OCP cycles between two
consecutive buffer flushing or prefetch requests.
Used to limit the bandwidth used to fill/empty buffers.
0: Maximum speed. Up to 1 request every 8 cycles
(3.2GB @ 200 MHz)
1: Up to 1 request every 9 cycles.
1023: Minimum speed. Up to 1 request every 1031 cycles
(24MB @ 200 MHz)
21:12
RESERVED
Reserved
11:8
BASE
Base address of the virtual space translated by the BTE.
Start address = BASE*512MB
End address = (BASE+1)*512MB 1
For example: BASE=3 = 0x 0 6000 0000 - 0x 0 7FFF
FFFF
7:6
RESERVED
Reserved
POSTED
Select among posted and nonposted writes for translated
requests.
5
7
6
5
4
RESERVED
0x5504 2030
0x5C00 2030
POSTED
0x0000 0030
Physical Address
RESERVED
Address Offset
3
2
1
0
TAG_CNT
Type
Reset
RW
0x000
R
0x000
RW
0x0
R
0x0
RW
0
0x0: Use non posted writes
0x1: Use posted writes
4
3:0
246
RESERVED
Reserved
TAG_CNT
BTE could use up to TAG_CNT+1 tags on OCPO.
There could only be one outstanding request per tag.
TAG_CNT does not control the number of requests it
could handle on OCPI.
This register is internally shadowed.
Modifications are taken into account when there are no
outstanding transactions on OCPO.
TAG ID 0 to TAG_CNT are used on OCPO.
R
0
RW
0xF
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.8.5.9
BTE_CTRL1
Table 133. BTE_CTRL1
Address Offset
0x0000 0034
Physical Address
0x5504 2034
0x5C00 2034
Description
BTE control register
Type
RW
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
RESERVED
4
3
2
1
0
RESP_FIFO_THR
Bits
Field Name
Description
31:7
RESERVED
Reserved
6:0
RESP_FIFO_THR
The BTE stops accepting new requests from OCPI (on a
clean burst boundary)
when the response FIFO contains more than
RESP_FIFO_THR words.
The reset value is FIFO_SIZE - 16 - 1.
FIFO_SIZE = 8 * 2RESPFIFO
2.8.5.10
5
Type
Reset
R
0x0000000
RW
0x0F
BTE_CONTEXT_CTRL_i
Table 134. BTE_CONTEXT_CTRL_i
i = 0 to 7
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
Description
Context control register
Type
RW
9
8
GRID
7
6
MODE
4
3
2
1
Bits
Field Name
Description
31:30
RESERVED
Reserved
R
0x0
29:16
TRIGGER
Threshold used to trigger translated requests to OCPO.
Unit: words or 16 bytes
Valid range: 3 lines + 2 ... 4 lines
WRITE:
a 2D write is issued to OCPO when the internal buffer
level
(including masked accesses) is superior or equal to
TRIGGER
READ:
a 2D read is issued to OCPO when the internal buffer
level
(including masked accesses) is inferior to TRIGGER.
RW
0x0000
INITSX
Reset value to be used for SX__x.
Check the section describing the local buffer
management for details.
RW
0
15
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Type
5
RESERVED
ONESHOT
AUTOFLUSH
ADDR32
TRIGGER
INITSY
INITSX
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
START
Index
0x5504 2040 + (0x20 * i)
0x5C00 2040 + (0x20 * i)
STOP
0x0000 0040 + (0x20 * i)
Physical Address
FLUSH
Address Offset
Reset
247
ISS Interfaces
Bits
www.ti.com
Field Name
Description
INITSY
12
11
14:13
Type
Reset
Reset value to be used for SY__x.
Check the section describing the local buffer
management for details.
RW
0x0
ADDR32
Controls the value of the OCP address bit 32 to be used
for translated accesses
RW
1
AUTOFLUSH
Controls automatic context flushing when an IDLE
request is received
RW
0
RW
0
RW
0x0
RW
0x0
0x0: Disabled
0x1: Enabled
10
ONESHOT
Selects one-shot or continuous mode
0x0: The context is automatically re-enabled when its end
is reached.
0x1: The context is disabled when the end of a frame has
been reached.
9:8
GRID
Grid used to access the TILER
0x0: Stride = 16k
Subtile = 4x4 bytes
Tile = 32x32 bytes
0x1: Stride = 8k
Subtile = 4x4 bytes
Tile = 32x32 bytes
0x2: Stride = 32k
Subtile = 8x2 bytes
Tile = 64x16 bytes
0x3: Stride = 16k
Subtile = 8x2 bytes
Tile = 64x16 bytes
7:6
MODE
Select the translation mode for the context
0x0: Write translation
0x1: Read translation
0x2: Direct access to local buffer
0x3: reserved
5:3
2
RESERVED
Reserved
R
0x0
FLUSH
Flushes all remaining data of the context to the TILER.
W
0
W
0
W
0
Write 0x0: No effect
Write 0x1: Flush
1
STOP
Stops the context on a clean OCP transaction boundary.
Write 0x0: No effect
Write 0x1: Stop the context
0
START
Resets the contexts internal state and enables the
context on a clean OCP transaction boundary.
Write 0x0: No effect
Write 0x1: Reset + Enable
248
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.8.5.11
BTE_CONTEXT_BASE_i
Table 135. BTE_CONTEXT_BASE_i
Address Offset
0x0000 0044 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 2044 + (0x20 * i)
0x5C00 2044 + (0x20 * i)
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
Description
Address of the frame buffer in the TILER address space.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
ADDR
Bits
Field Name
Description
31:5
ADDR
Address
4:0
RESERVED
Reserved
2.8.5.12
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x00
BTE_CONTEXT_START_i
Table 136. BTE_CONTEXT_START_i
Address Offset
0x0000 0048 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 2048 + (0x20 * i)
0x5C00 2048 + (0x20 * i)
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
Description
Top-left corner of the context.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
8
7
6
X
Bits
Field Name
Description
31:16
RESERVED
Reserved
15:7
X
Address, in 128-byte words
6:0
RESERVED
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
5
4
3
2
1
0
RESERVED
Type
Reset
R
0x0000
RW
0x000
R
0x00
249
ISS Interfaces
2.8.5.13
www.ti.com
BTE_CONTEXT_END_i
Table 137. BTE_CONTEXT_END_i
Address Offset
0x0000 004C + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 204C + (0x20 * i)
0x5C00 204C + (0x20 * i)
Instance
ISS_BTE_CORTEX-M3
ISS_BTE_L3
Description
Bottom-right corner of the context.
Type
RW
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Y
8
7
6
X
Bits
Field Name
Description
31:29
RESERVED
Reserved
28:16
Y
15:4
3:0
250
9
5
4
3
2
1
0
RESERVED
Type
Reset
R
0x0
Last line number for the context
(0 corresponds to a context of 1 line)
RW
0x0000
X
Address, in 128-bit words, of the last column of the
context
RW
0x000
RESERVED
Reserved
R
0x0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9
ISS CBUFF
2.9.1
ISS CBUFF Environment
There are no particular environment attributes. See Section 2.2, ISS Interfaces Environment.
2.9.2
ISS CBUFF Integration
Figure 89 shows the integration of the CBUFF in the ISS. Because the CBUFF maps a virtual memory
space from the physical memory, it therefore communicates with the ISS ISP and ISS interface modules
for data to and from memory. This figure shows the normal data flow for further processing by the ISP
and/or still-image coprocessor (SIMCOP) (in green) and the stall functionality of CBUFF (in red), which
stall the data for a certain amount of time. An example of stalling is when the ISP processes the data
faster than the input from SC to memory. The CBUFF then must stall the data flow until a sufficient
amount of data can be read from memory by the ISP.
For power domain, clocks, reset, and hardware requests, see Section 1.2.5, ISS Power Management.
2.9.2.1
ISS CBUFF Reset and Idle Mechanism
A reset signal is provided by the PRCM module to the top-level ISS power and clock-management
module.
For standby, when none of the ISS modules require CBUFF execution actions, ISS PM executes the
standby sequence, which reaches the CBUFF. When an IDLE request arrives, the CBUFF data is drained.
After all transactions are drained, the CBUFF acknowledges the IDLE request to the ISS PM/CM. The
IDLE request/acknowledge steps are:
When an IDLE request is received in smart-idle mode:
1. CBUFF stops accepting any new OCP requests on a clean OCP transaction boundary.
2. Waits until the interrupt output becomes inactive (no more enabled event pending)
3. Waits until all outstanding OCP transactions are complete on OCPO and OCPI. CBUFF keeps track of
issued requests, data phases, and responses for that purpose.
4. CBUFF disconnects the OCPO port.
5. CBUFF acknowledges the IDLE request.
When a wake-up request is received in smart-idle mode:
1. CBUFF connects the OCPO port.
2. Starts accepting new requests from OCPI
3. Acknowledges the functional state
Idle mode is controlled through the CBUFF_HL_SYSCONFIG[3:2] IDLEMODE bit field. For software reset,
it is recommended to use the global ISS reset; if a reset is required, it can be set from the
CBUFF_HL_SYSCONFIG[0] SOFTRESET bit.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
251
ISS Interfaces
www.ti.com
Figure 89. ISS CBUFF Integration
ISS
ISS interfaces and
interconnects
ISS
interconnect
Configuration
32b
L3 intercon
interconnect
128-bit data
CBUFF
Physical data space
(SRAM or SDRAM)
ISS IRQ merger
RW data
from CPU
CBUFF_IRQ[0]
BTE
Stall
signal
SC
STANDBY
BY
hardware
ware
handshake
dshak
dshake
128-bit
data
ISS_FCLK
CAM_PHY_CTRL_FCLK
PRCM
ISP
RED- Stalled data flow
N - Normal data flow
GREEN
252
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.2.2
ISS CBUFF Interrupts
All events generated by the module are merged into a single event at ISS level. This event can be
mapped to the MPU subsystem by enabling the ISS_HL_IRQENABLE_SET_i[10] CBUFF_IRQ bit.
Table 138 lists the procedure to manage CBUFF interrupts.
Table 138. ISS CBUFF Interrupt Management
Description
Bit Field
Each event that generates an interrupt can be individually enabled by setting the
appropriate bit.
CBUFF_HL_IRQENABLE_SET
Each event that generates an interrupt can be individually disabled by setting the
appropriate bit.
CBUFF_HL_IRQENABLE_CLR
When an event occurs, the corresponding bit in the CBUFF_HL_IRQSTATUS_RAW
register is set regardless of whether or not the event is enabled. Bits in the
CBUFF_HL_IRQSTATUS registers are only set only when an enabled event occurs
CBUFF_HL_IRQSTATUS_RAW and
CBUFF_HL_IRQSTATUS
Software can clear a pending event by setting the appropriate bit in the
CBUFF_HL_IRQSTATUS register.
CBUFF_HL_IRQSTATUS
The CBUFF can generate three events per context and one global event. All events are merged into one
physical interrupt line. Table 139 describes the CBUFF-generated events.
Table 139. ISS CBUFF-Generated Events
Event
Description
IRQ_CTXx_READY
Write mode: CPU can read data from the physical window pointed by CBUFF_CTX_STATUS_i[3:0] WB.
mode: The OCPI initiator has completed writing a physical window.
IRQ_CTXx_INVALID
Invalid access
OCPI writes the virtual space of context i in read mode.
OCPI reads the virtual space of context i in write mode.
OCPI writes the virtual space of context i outside the CBUFF_CTX_STATUS_i[11:8] WA window in write
or read/write mode.
OCPI reads the virtual space of context i outside the CBUFF_CTX_STATUS_i[11:8] WA window in read
mode.
OCPI reads the virtual space of context i outside the CBUFF_CTX_STATUS_i[3:0] WB window in
read/write mode.
CPU writes the DONE bit when physical windows are not ready for the CPU.
This event indicates a wrong configuration of the CBUFF, the OCPI initiator or bogus software. When it
happens, context i goes into an error state. In this state all accesses to the virtual space of context i are
cancelled: they are not forwarded to the physical space. The purpose is to prevent corruption of the
physical memory. Of course, the CBUFF still returns OCP responses to OCPI to ensure the integrity of
the OCP.
The error state can be left by disabling the context i and re-enabling it. Before doing so, software must
ensure that there are no more outstanding requests to the virtual space of context i.
IRQ_CTXx_OVR
Physical space overflow or underflow event
This event indicates a bandwidth mismatch between data producer and data consumer. When it
happens, context i does not go into error state. However, the data in the physical space is likely to be
corrupted.
IRQ_OCP_ERR
OCP error received in the OCPO master port. The OCP response is forwarded to OCPI normally.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
253
ISS Interfaces
2.9.3
www.ti.com
ISS CBUFF Functional Description
The CBUFF maps a virtual space to a physical space by address translation. It does not change the data
or store it locally.
2.9.3.1
ISS CBUFF Features
The ISS CBUFF features are:
• Fully transparent for accesses out of the configured virtual space
• Three functional modes :
– Read mode: Read requests received from OCPI and forwarded after translation to OCPO. Writes
are handled by an external process and acknowledged by the CPU.
– Write mode: Write request received from OCPI and forwarded after translation to OCPO. Reads are
handled by an external process and acknowledged by the CPU.
– Read/write mode: Read and write requests received from OCPI and forwarded after translation to
OCPO
• Four independent contexts
• Virtual address space (linear) mapped into a physical space (circular)
• Maximum physical buffer size of 16 × 16MB:
– Physical space consists of 2, 4, 8, or 16 windows.
– Maximum allowed window size is 16MB.
• Support of 2D addressing modes
• Strong error detection mechanisms to prevent data corruption caused by bogus configuration
• Addresses are 128-bit aligned, but window fill level managing is byte accurate
• Bandwidth control feedback loop to stall in initiator connected to OCPI
2.9.3.2
ISS CBUFF Functional Description
The CBUFF maps a virtual address space to a physical space also called circular buffer.
The CBUFF can handle up to eight contexts. For most data formats, primarily four contexts are used. In
cases where YUV4:2:0 data is exchanged, two contexts are consumed by the SIMCOP (JPEG encode)
coming from the resizer module, which is the ISP output module. Moreover, a context is a virtual full-frame
buffer that maps to a configurable number of physical windows.
This section gives an overview of typical uses of the CBUFF.
254
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.3.2.1
ISS CBUFF Top-Level Diagram
Figure 90 shows the functional principle diagram. It does not include an exhaustive list of the interface
signals or internal status registers.
A more detailed functional description is provided in the following sections.
Figure 90. ISS CBUFF Top-Level Diagram
Slave RW interface
to ISS initiators
OCPI
CBUFF_CTX_START_i[31:4] ADDR
START
END
Invalid err
CBUFF_HL_IRQSTATUS[...]
IRQ_CTXi_INVALID
CBUFF_CTX_END_i[31:4] ADDR
Check
access
CBUFF_CTX_STATUS_i[11:8] WA
CBUFF_CTX_STATUS_i[3:0] WB or transparent
CBUFF_CTX_WINDOWSIZE_i[23:4] SIZE
ADDR
Offset
Buffer
level
DATA
Physical
space
CMD
CBUFF_CTX_THRESHOLD
CBUFF_HL_IRQSTATUS[...]
IRQ_CTXi_INVALID
CPU
acknowledge
Monitor window state
READY
Overflow
CBUFF_CTX_CTRL_i[9:8] WCOUNT
CBUFF_BCF
Master RW interface
to memory
OCPO
2.9.3.2.2
ISS CBUFF Functional Modes
The CBUFF supports three functional modes (see Table 140).
Table 140. ISS CBUFF Functional Modes
Mode
Data Written by
Data Read by
Write mode
ISS initiator
CPU-controlled process
Read mode
CPU-controlled process
ISS initiator
Read/write mode
ISS initiator
ISS initiator
2.9.3.2.2.1 ISS CBUFF Write Mode
In write mode, the physical space is written by the CBUFF and it is read by the CPU. An
IRQ_CTXx_READY event is set each time a physical window is available to be read by the CPU. This
happens when the CBUFF_CTX_STATUS_i[11:8] WA pointer is moved by the CBUFF.
The CBUFF sets an IRQ_CTXx_READY event to inform the CPU that it can access the
CBUFF_CTX_STATUS_i[3:0] WB physical window. The CBUFF cannot monitor CPU accesses to the
physical window. The CPU must indicate when it has completed the processing of the
CBUFF_CTX_STATUS_i[3:0] WB window by setting the CBUFF_CTX_CTRL_i[2:1] DONE bit field. This
increments the window index CBUFF_CTX_STATUS_i[3:0] WB by one modulo the window count (defined
by the CBUFF_CTX_CTRL_i[9:8] WCOUNT bit field).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
255
ISS Interfaces
www.ti.com
The CBUFF ensures that one IRQ_CTXx_READY event is sent to the CPU per physical window to be
read. In other words, when a new IRQ_CTXx_READY event occurs before the previous one(s) is
acknowledged by the CPU, it is not lost. The CBUFF memorizes the event and triggers the interrupt line
again when the CPU clears it.
When the CPU reads the physical space too slowly, the CBUFF_CTX_STATUS_i[11:8] WA window
pointer falls into the CBUFF_CTX_STATUS_i[3:0] WB window. This generates an IRQ_CTXx_OVR event
when the OCPI initiator performs an access to that window. The CPU receives the IRQ_CTXx_READY
event only if it is allowed to access a physical window. Therefore, it cannot generate an IRQ_CTXx_OVR
event in a normal case. The OCPI initiator accesses are tracked based on activity on the OCP port.
When an IRQ_CTXx_OVR event occurs, the buffer content is likely to be corrupted. However, the CBUFF
context continues processing data normally; it does not go into error state. Software must reset data
generation and the CBUFF in a clean manner.
Figure 91 shows an example scenario with CBUFF_CTX_CTRL_i[9:8] WCOUNT = 1 (four windows). In
normal operation, the CPU processes data at least at the same speed as it is written to the physical
space. When this is not true, the number of windows to be read by the CPU increases. When no more
physical windows are available for OCPI writes, an overflow occurs.
In the following example, the CPU takes more time than expected to read the third buffer. Therefore,
physical windows are not freed up. The OPCI initiator continues to write data into the physical window.
That leads to an overflow when the OCPI initiator writes into the physical window that is read by the CPU
(CBUFF_CTX_STATUS_i[11:8] WA = CBUFF_CTX_STATUS_i[3:0] WB and writes into
CBUFF_CTX_STATUS_i[11:8] WA detected).
Figure 91. ISS CBUFF Write Mode CPU Interaction Example
THRESHOLD_F
WA level
Data ready for CPU
W0
WA
W1
U
WA
WA
0
1
WB
FREE
WB
WA
R
WB
WB
WA
0
0
R
0
1
CPU has completed a physical buffer
WB
OVERFLOW event
1
0
1
CPU clear IRQ and starts processing
R
0
1
1
WA
1
0
2
R
1
0
1
WA
Current window: could be
written by OCPI
WB
Window accessed by CPU
0
STALL
IRQ
R
Window available for CPU read
U
Window unused
(1)
When there is no physical window available to be read by the CPU and the CPU writes the DONE bit, an
IRQ_CTXx_INVALID event occurs.
(2)
The bandwidth control feedback (BCF) feature can be used to prevent overflow. It must be supported by the
module writing data into the virtual space (typically, an ISS).
2.9.3.2.2.2 ISS CBUFF Read Mode
In read mode, the physical space is read by the CBUFF and it is written by the CPU. An
IRQ_CTXx_READY event is set each time a physical window is available to be written by the CPU. This is
true until all free buffers are used.
The CBUFF sets an IRQ_CTXx_READY event to inform the CPU that it can write the
CBUFF_CTX_STATUS_i[3:0] WB window. The CBUFF cannot monitor CPU accesses to the physical
space. It must indicate when it completes writing the CBUFF_CTX_STATUS_i[3:0] WB window by setting
the CBUFF_CTX_CTRL_i[2:1] DONE bit field. This increments the CPU window index
CBUFF_CTX_STATUS_i[3:0] WB by one modulo the window count (defined by the
CBUFF_CTX_CTRL_i[9:8] WCOUNT bit field).
The CBUFF ensures that one IRQ_CTXx_READY event is sent to the CPU per physical window to be
written. In other words, when a new IRQ_CTXx_READY event occurs before the previous one(s) is
acknowledged by the CPU, it is not lost. The CBUFF memorizes the event and triggers the interrupt line
again when the CPU clears it.
256
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The following is an example of a normal operation in which the CPU writes data faster than it is read by
the OCPI initiator. Figure 92 uses two physical windows (CBUFF_CTX_CTRL_i[9:8] WCOUNT = 0).
Figure 92. ISS CBUFF CPU Writes Data Faster Than it Is Read by the OCPI Initiator
Software starts the OCPI initiator when the first physical buffer has
been written.
Context enabled by software
Tell CPU to write data
starts processing
CPU cclear IRQ and start
WA level
CPU h
has completed a physical buffer
W0
WB
W1
U
WA
WB
WA
WB
R
0
WA
WA
0
WB
R
WB
1
1
WB
R
WA
WA
0
0
R
WB
1
1
OVERFLOW
VERFLOW ev
event
R
0
0
1
0
WA
Windo
Window can be read by OCPI
WB
Window
W
can be written by CPU
IRQ
R
Data ready to be read
U
Window unused
Software must enable the ISS initiator only when at least one window is written by the CPU. Otherwise, an
OVERFLOW event occurs when BCF is not used.
The CPU receives an interrupt each time a physical window is available to receive data. It clears the
interrupt and then starts filling the physical window. When the buffer is completely written, it sets the
CBUFF_CTX_CTRL_i[2:1] DONE bit field. This happens before the OCPI initiator has read all data from
the previous physical window: the CPU must wait until the next IRQ_CTXx_READY event is received
before it can write again to the physical space.
When the CPU writes buffers too slowly, the CBUFF_CTX_STATUS_i[11:8] WA window falls into the
CBUFF_CTX_STATUS_i[3:0] WB window. This generates an IRQ_CTXx_OVR event only when the OCPI
initiator performs reads to that window. The CPU receives the IRQ_CTXx_READY event only if it is
allowed to access a physical window. Therefore, it does not generate an IRQ_CTXx_OVR event in a
normal case. ISS accesses are tracked based on activity on the OCPI port.
When no buffer is available to be written by the CPU and the CPU writes the DONE bit, an
IRQ_CTXx_INVALID event occurs.
When an IRQ_CTXx_OVR event occurs, the OPCI initiator reading the virtual space is likely to receive
dummy data. However, the CBUFF context continues to process data normally; it does not go into error
state. Software must reset the data consumer (OCPI initiator) and CBUFF context in a clean manner.
Figure 93 is an example of CBUFF read mode CPU interaction.
The BCF feature can be used to prevent overflow. It must be supported by the module reading data from
the virtual space (typically, an ISS).
Figure 93. CBUFF Read Mode CPU Interaction Example
OCPI initiators start
reading data
Tell CPU to write data
WA level
W0
0
WB
W1
U
W2
W
R
WB
U
WA
B
WB
R
WB
U
W3
WA
U
WB
WA
U
1
2
WA
WB
R
WA
1
2
3
3
0
WA
WA
WB
U
U
0
1
CPU clear IRQ and starts processing
U
WB
R
0
0
R
1
2
CPU has completed a physical buffer
U
WA
U
WB
U
2
3
OVERFLOW event
WA
Window can be read by OCPI
WB
Window can be written by CPU
3
IRQ
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
R
Data ready to be read
U
Window unused
257
ISS Interfaces
www.ti.com
2.9.3.2.2.3 ISS CBUFF Read/Write Mode
Reads and writes are performed by OCPI initiators such as a camera interface, ISP, or SIMCOP. Address
translation is performed for read and write data flows. The WA pointer is used for the write data flow, and
the WB pointer is used for the read data flow. Therefore, address translation for the write data flow is the
same as for write mode.
In this mode, the OCPI read data flow is stalled when there is not enough data to read in the physical
space. A typical application is to store data from the camera in a CBUFF and to read it back by the ISP.
When the camera is slower than the ISP, the ISP stalls.
This mode does not rely on CPU synchronization. Synchronization is always performed using the BCF
hardware mechanism. IRQ_CTXx_READY events are triggered in this mode when the OPCI write initiator
has filled a physical window. Software can use this event for debug or performance bench marking
purposes. Writes to the CBUFF_CTX_CTRL_i[2:1] DONE bit field are ignored in this mode.
The IRQ_CTXx_OVR event is triggered when an underflow occurs. In a normal case this should not
occur, because the BCF signal is used to stall the read data flow when insufficient data is available in the
physical space.
Figure 94 assumes:
• Read/write mode
• Four physical windows
• CBUFF_CTX_THRESHOLD_S_i = CBUFF_CTX_THRESHOLD_F_i
• The OCPI read initiator is faster than the OCPI write initiator. The BCF feature is used to stall the read
initiator. CBUFF_CTX_CTRL_i[7:4] BCF = 2
Figure 94. ISS CBUFF Read/Write Mode Example
WA level
WB level
W0
WA
R
W1
U
WA
W2
FULL
WB
WA
1
1
0
2
1
WB
1
1
Window can be written by OCPI
WB
Window can be read by OCPI
R
Data ready to be read
U
Window unused
0
0
2
WA
U
R
0
1
0
1
WB
WA
0
0
R
WA
U
R
U
WA
WA
U
R
U
W3
WB
WB
1
2
1
0
2
BCF
2.9.3.2.3
ISS CBUFF Events and Status Checking
2.9.3.2.3.1 ISS CBUFF Operations
A CBUFFx_READY_IRQ event is generated each time the CPU can read data from the CBUFF. The CPU
can clear the event when it starts processing the data to avoid masking other events. The CPU can keep
track of the location on the data internally or use the CBUFF registers to compute it.
The formula used is: ADDR = CBUFF_CTX_STATUS_i[3:0] WB CBUFF_CTX_WINDOWSIZE_i +
CBUFF_CTX_PHY_i
When the CPU is done with processing, it must free the buffer by setting the CBUFF_CTX_CTRL_i[10]
DONE bit. Otherwise, an overflow event may occur.
258
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
The CBUFF does not keep track of EOF events. They must be managed by the CPU using the EOF event
of the module that writes into the CBUFF. At the EOF, data may remain in the current write windows. For
example, when the window size is set to 8 lines and the image size is 20 lines, only two window-ready
events are generated for a linear addressing scheme. The remaining four lines can be read after the EOF
event.
No automatic reset of the CBUFF FSM occurs at the end of the image frame. Software must reset the
context by clearing the CBUFF_CTX_CTRL_i[0] ENABLE bit when the frame is completely processed. A
new frame can start only when the CBUFF_CTX_CTRL_i[0] ENABLE bit is set.
2.9.3.2.3.2 ISS CBUFF Status Checking
The CBUFF provides read-only access to the CBUFF_CTX_STATUS_i[11:8] WA and
CBUFF_CTX_STATUS_i[3:0] WB pointers through the CBUFF_CTX_STATUS_i register. For example,
the CBUFF_CTX_STATUS_i[3:0] WB index can be used by the CPU to compute the address of a physical
window. Those indexes can also be used to evaluate latency margins.
2.9.3.2.3.3 ISS CBUFF Register Accessibility During Frame Processing
All registers are busy-writeable registers. These registers/fields can be read or written even if the module
is busy. Changes to the underlying settings occur instantly. However, module behavior is unpredictable
when registers are changed during processing.
For correct operation, software must:
1. Disable all accesses to the virtual space managed by the context.
2. Disable the context by clearing the CBUFF_CTX_CTRL_i[0] ENABLE bit.
3. Change the configuration.
4. Re-enable CBUFFx by setting the CBUFF_CTX_CTRL_i[0] ENABLE bit.
2.9.3.2.4
ISS CBUFF Memory-to-Memory Operation BCF
The BCF mechanism matches the bandwidth between two processes.
The BCF feature can be used in all three CBUFF modes:
• Read mode: A CPU-controlled process writes data into physical space. The BCF signal is deasserted
when the physical space contains enough data to start the read initiator connected to OCPI.
• Write mode: The BCF signal controls the write initiator connected to OCPI. When the CPU-controlled
process does not read the data fast enough from the physical space, the BCF signal is asserted to stall
filling of the buffer. It is deasserted when enough space is available in the physical space.
• Read/write mode: The BCF signal controls the read initiator connected to OCPI. Another initiator
connected to OCPI fills the physical space. The BCF signal is deasserted when the physical space
contains data that can be read by the read initiator. It is deasserted when insufficient data is available
in the physical space.
The CBUFF_BCF output is controlled based on two factors:
• The window count available for the OCPI initiator to write
• The amount of data in the last available window (pretrigger)
The CBUFF_BCF signal is enabled by the CBUFF_CTX_CTRL_i[7:4] BCF bit field. It defines:
• Write mode: The amount of required free windows to allow writing from the ISS. In other words, when
less than the required amount of BCF windows is available for ISS writes, the stall mechanism is
triggered. The number of free windows is initialized to the total window count of the context. It is
decreased by 1 each time the OCPI initiator finishes writing a window. It is increased by 1 each time
the CPU finishes reading a window.
• Read and read/write modes: The minimum amount of required full windows to allow reading from the
OCPI. When fewer than CBUFF_CTX_CTRL_i[7:4] BCF windows are available for ISS read, the stall
mechanism is triggered. The number of full windows is initialized to 0. It is decreased by 1 each time
the OCPI initiator completes reading a window. It is increased by 1 each time the CPU/OCPI initiator
finishes writing a window.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
259
ISS Interfaces
www.ti.com
Figure 95 is an example of BCF use. It assumes:
• Write mode: OCPI writes data into physical space and the CPU reads it.
• Two physical windows
• CBUFF_CTX_THRESHOLD_S_i = CBUFF_CTX_THRESHOLD_F_i
• The OCPI write initiator is faster than the CPU.
• CBUFF_CTX_CTRL_i[7:4] BCF = 1
Figure 95. ISS CBUFF Write Mode CPU Interaction Example BCF Used
THRESHOLD_F
WA level
Data ready for CPU
W0
WA
W1
U
WA
0
WB
WA
R
1
WB
FREE
WA
R
WB
WB
WA
WA
0
R
0
1
CPU has completed a physical buffer
WB
1
0
CPU clear IRQ and starts processing
R
OVERFLOW event
1
0
1
Current window: could be
written by OCPI
WA
2
1
0
1
0
1
0
1
0
Window accessed by CPU
WB
STALL
IRQ
R
Window available for CPU read
U
Window unused
Figure 96 is another example. It assumes:
• Read mode: The CPU writes data into physical space and the OCPI reads it.
• Four physical windows
• CBUFF_CTX_THRESHOLD_S_i = CBUFF_CTX_THRESHOLD_F_i
• The OCPI read initiator is faster than the CPU. It starts after the CPU.
• CBUFF_CTX_CTRL_i[7:4] BCF = 2
Figure 96. ISS CBUFF Read Mode CPU Interaction Example (1)
OCPI initiators start
reading data
Tell CPU to write data
WA level
W0
WB
W1
U
W2
WB
U
W3
WA
R
WA
R
U
R
WB
0
0
R
WB
WB
WA
WB
WA
R
WA
WB
R
U
WB
WA
WB
WA
Window can be read by OCPI
WB
Window can be written by CPU
1
1
0
OVERFLOW event
R
0
1
CPU has completed a physical buffer
WA
U
2
CPU clear IRQ and starts processing
U
2
3
R
Data ready to be read
U
Window unused
STALL
FULL
0
1
3
2
1
2
1
2
1
2
1
2
IRQ
260
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 97 is another example. It assumes:
• Read mode: The CPU writes data into physical space and the OCPI reads it.
• Two physical windows
• CBUFF_CTX_THRESHOLD_S_i = CBUFF_CTX_THRESHOLD_F_i
• The OCPI read initiator is faster than the CPU. It starts after the CPU.
• CBUFF_CTX_CTRL_i[7:4] BCF = 1
Figure 97. ISS CBUFF Read Mode CPU Interaction Example (2)
Tell CPU to write data
WA level
W0
WB
W1
U
WB
WA
0
1
WB
FULL
U
WA
0
1
0
0
OVERFLOW event
1
0
1
CPU has completed a physical buffer
WB
0
1
1
CPU clear IRQ and starts processing
U
WA
U
WA
0
1
WB
WB
0
1
1
U
WA
U
WA
0
0
WB
0
1
1
WA
Window can be read by OCPI
WB
Window can be written by CPU
0
STALL
IRQ
R
Data ready to be read
U
Window unused
Figure 98 is another example. It assumes:
• Read mode: The CPU writes data into physical space and the OCPI reads it.
• Four physical windows
• CBUFF_CTX_THRESHOLD_S_i = CBUFF_CTX_THRESHOLD_F_i
• The OCPI read initiator is faster than the CPU. It starts after the CPU.
• CBUFF_CTX_CTRL_i[7:4] BCF = 1
CBUFF supports pretriggering the BCF signal for finer latency compensation control. This mechanism is
active only for the last window available for OCPI access. It typically improves the physical space use,
which is particularly useful when on-chip SRAM is used as a ping-pong buffer.
Pretriggering is controlled through the CBUFF_CTX_THRESHOLD_S_i register. It defines:
• Write mode: When the fill level of the last window available for ISS writes is greater than or equal to
CBUFF_CTX_THRESHOLD_S_i, the CBUFF_BCF signal is asserted.
• Read mode: When the amount of data in the last window available for ISS reads is less than
CBUFF_CTX_THRESHOLD_F_i/CBUFF_CTX_THRESHOLD_S_i, the CBUFF_BCF signal is
asserted.
BCF pretriggering is disabled by setting CBUFF_CTX_THRESHOLD_S_i =
CBUFF_CTX_THRESHOLD_F_i.
Figure 98 is an example of BCF pretriggering, assuming the following:
• Write mode: The CPU reads data from the physical space and the OCPI writes it.
• Two physical windows
• CBUFF_CTX_THRESHOLD_S_i = 1/3 CBUFF_CTX_THRESHOLD_F_i
• CBUFF_CTX_CTRL_i[7:4] BCF = 1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
261
ISS Interfaces
www.ti.com
Figure 98. ISS CBUFF BCF Pretrigger Example: Write Mode
THRESHOLD_F
WA level
W0
WA
W1
U
WA
WB
WA
U
WB
WB
WA
0
WB
1
CPU has completed a physical buffer
OVERFLOW event
1
1
0
2
0
2
CPU clear IRQ and starts processing
U
WA
U
0
FREE
Data ready for CPU
THRESHOLD_S
1
1
2
1
WA
Current window: could be
written by ISP
WB
Window accessed by CPU
2
BCF
R
Window available for CPU read
U
Window unused
IRQ
BCF stall
latency
BCF resume
latency
The CBUFF_BCF output signal is a logical OR of all internal BCF signals of CBUFF contexts. For
example, when contexts 0 and 1 have enabled the BCF feature, both contexts can request a data flow
stall.
Figure 99 is an example of pretriggering in read mode:
• Read mode: CPU writes data into the physical space and the OCPI reads it.
• Four physical windows
• CBUFF_CTX_THRESHOLD_S_i = 2/3 CBUFF_CTX_THRESHOLD_F_i
• The OCPI read initiator is faster than the CPU. It starts after the CPU.
• CBUFF_CTX_CTRL_i[7:4] BCF = 2
Figure 99. ISS CBUFF BCF Pretrigger Example: Read Mode
Tell CPU to write data
WA level
W0
WB
W1
U
WB
WA
0
1
WB
FULL
U
WA
0
1
0
0
OVERFLOW event
1
0
1
CPU has completed a physical buffer
WB
0
1
1
CPU clear IRQ and starts processing
U
WA
U
WA
0
1
WB
WB
0
1
1
U
WA
U
WA
0
0
WB
0
1
1
WA
Window can be read by OCPI
WB
Window can be written by CPU
0
STALL
IRQ
2.9.3.2.5
R
Data ready to be read
U
Window unused
ISS CBUFF TILER Support
The CBUFF can translate 2D (BLOCK) bursts intended for the TILER. However, software must ensure
that a given burst fits in a window.
The expected value for ADDR[32] is defined by the CBUFF_CTX_CTRL_i[11] TILERMODE bit.
• When ADDR[32] = CBUFF_CTX_CTRL_i[11] TILERMODE, the access is processed normally.
ADDR[32] is not used for further processing.
• Otherwise, the access is treated as transparent.
2.9.3.2.6
ISS CBUFF Window Management and Address Remapping Details
This section explains the internal address remapping and windows management algorithm. Internally, the
module maintains some variables in addition to the configuration registers. The module manages multiple
contexts in parallel. Table 141 lists the CBUFF internal variables.
262
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Table 141. ISS CBUFF Internal Variables
Variable
Description
WAx
Current window index for context x. Possible values are 0 to allowed window count. The current value can be
read using the CBUFF_CTX_STATUS_i[11:8] WA bit field.
WBx
Window in the physical space that can be accessed by the CPU in read/write modes . Window that is read from
OCPI in read/write mode. Possible values are 0 to allowed window count. The current value can be read using
the CBUFF_CTX_STATUS_i[3:0] WB bit field.
VPAx
Start address, in the virtual space, of the CBUFF_CTX_STATUS_i[11:8] WA window
Used as a base pointer for the read (read mode) or write data flow (write , read/write modes)
This is an internal quantity that cannot be accessed by software.
VPBx
Start address, in the virtual space, of the CBUFF_CTX_STATUS_i[3:0] WB window
Used as a base pointer for the read data flow.
This is an internal quantity that cannot be accessed by software.
OFFSETAx
This is an internal quantity that cannot be accessed by software.
OFFSETBx
Address offset used when WAx or WBx is accessed
LEVELAx
This is an internal quantity that cannot be accessed by software.
LEVELBx
Address offset used when WAx or WBx is accessed
2.9.3.2.6.1 ISS CBUFF Startup
The status of a CBUFF context is reset when it is disabled. This does not affect the configuration registers
or the CBUFF_IRQSTATUS register. Table 142 lists the internal state after reset.
Table 142. ISS CBUFF Internal State After Reset
Variable
Description
WAx
0
WBx
0
VPAx
VPBx
CBUFF_CTX_START_i
OFFSETAx
OFFSETBx
CBUFF_CTX_START_i – CBUFF_CTX_PHY_i
LEVELAx
LEVELBx
0
2.9.3.2.6.2 ISS CBUFF Access Identification
For each access to the virtual space (OCPI slave port), the CBUFF first checks the address to classify the
transaction into one of the categories listed in Table 143.
Table 143. ISS CBUFF Address identification
Address ID
Variable
Condition
0+2*x
WA_CBUFFx
CBUFF_CTX_CTRL_i[0] ENABLE = 1 and
ADDR = VPAx and
ADDR VPAx + CBUFF_CTX_WINDOWSIZE_i and
ADDR = CBUFF_CTX_END_i and
Access type = write when read/write mode is selected
1+2*x
WB_CBUFFx
CBUFF_CTX_CTRL_i[0] ENABLE = 1 and
CBUFF_CTX_CTRL_i[2:1] MODE = 2 and
Access type = read and
ADDR=VPBx and
ADDRVPBx + CBUFF_CTX_WINDOWSIZE_i and
ADDR= CBUFF_CTX_END_i
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
263
ISS Interfaces
www.ti.com
Table 143. ISS CBUFF Address identification (continued)
Address ID
Variable
Condition
16+x
ERR_CBUFFx
CBUFF_CTX_CTRL_i[0] ENABLE = 1 and
ADDR= CBUFF_CTX_START_i and
ADDR= CBUFF_CTX_END_i
24
TRANSPARENT
Always true
Lower IDs correspond to higher priorities if multiple conditions are true. For example, when the current
virtual window of CBUFF 0 is accessed, at least the tests for categories WA_CBUFFx and ERR_CBUFFx
are true. The final category is WA_CBUFFx, because it has a higher priority.
NOTE: Tests must be performed in parallel to match the desired performance.
Further processing depends on the category:
• TRANSPARENT: Accesses flow though the module without changing its internal state or any
translation.
• ERR_CBUFFx: The module goes into error state for the concerned context and sets the
CBUFF_HL_IRQSTATUS.IRQ_CTXx_INVALID bit. When the module is in error state for CBUFFx, all
accesses to that buffer are cancelled. In other words, any access that has an address between
CBUFF_CTX_START_i and CBUFF_CTX_END_i is not transmitted to the OCPO master port. There
are two ways to leave the error state:
– Hardware reset
– Disable and re-enable the context in error state.
Accesses outside of the virtual space from the context in error state are not affected.
• WA_CBUFFx and WB_CBUFFx: The internal state is updated and address translation is performed
when the performed access type (read or write) is compatible with the current mode (read, write, or
read/write mode). Otherwise, a CBUFF_HL_IRQSTATUS.IRQ_CTXx_INVALID event is set and
CBUFFx goes into the error state.
2.9.3.2.6.3 ISS CBUFF Address Translation
An offset is selected depending on the access category (see Section 2.9.3.2.6.1, ISS CBUFF Startup) and
the internal state of the accessed buffer. Table 144 lists possible cases.
Table 144. ISS CBUFF Address Translation
Condition
Address Translation
CBUFF_CTX_CTRL_i[0] ENABLE = 1 and
Access cancelled
ADDR = CBUFF_CTX_START_i and
ADDR = CBUFF_CTX_END_i and
CBUFFx in error state
Category = WA_CBUFFx
ADDROUT = ADDRIN-OFFSETAx
Category = WB_CBUFFx
Read/write mode only
ADDROUT = ADDRIN-OFFSETBx
264
Category = ERR_CBUFFx
Access cancelled
Category = TRANSPARENT
ADDROUT = ADDRIN
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.3.2.6.4 ISS CBUFF Window Fill Level
Each time an access is performed into an active window (WA_CBUFFx when context x is enabled) the
window level is updated. The corresponding LEVELy is incremented according to the BYTEEN input of the
OCPI slave port. All possible BYTEEN patterns, including nonaligned ones, are supported. Table 145
shows some examples. The basic idea is to count the number of 1s in the BYTEEN input for each 128-bit
word and to sum the values.
Table 145. ISS CBUFF Window-Level Increment
BYTEEN
LEVELy Increment
Comment
0x0000
0
No access
0x0001
1
8-bit access
0x0002
1
8-bit access
0x0003
2
16-bit access
...
...
...
0x0007
3
24-bit access
...
...
...
0x000F
4
32-bit access
...
...
...
0x00F0
4
32-bit access
...
...
...
0xFFFF
16
128-bit access
The window level is compared to CBUFFx_THRESHOLD. Table 146 lists the situations that may occur:
Table 146. ISS CBUFF Window-Level Comparison (1)
Condition
Description
LEVELAx = CBUFF_CTX_THRESHOLD_F_i
The CBUFF_CTX_STATUS_i[11:8] WA bit field of context x is full (write mode) or
empty (read mode).
Internal window indexes, levels, and offsets are updated.
LEVELBx = CBUFF_CTX_THRESHOLD_F_i
Read/write mode only
Window used to handle the read flow of context x is empty.
Internal window indexes, levels, and offsets are updated.
(1)
All situations described in Table 146 are mutually exclusive because only one level is updated each cycle.
2.9.3.2.6.5 ISS CBUFF Window Pointer and Offset Update
The following description refers to the update of WA in write mode:
When the current window of a context is full:
• A new window is opened. The update is done in a circular manner: the first physical window in is
reused after the last one.
– WA (WA + 1) modulo the number defined by CBUFF_CTX_CTRL_i[9:8] WCOUNT
– LEVELA - 0
– VPA - VPA + CBUFF_CTX_WINDOWSIZE_i
• When the window is moved from the last buffer to the first:
– OFFSETA - OFFSETA + CBUFF_CTX_WINDOWSIZE_i (CBUFF_CTX_CTRL_i[9:8] WCOUNT +
1)
• Otherwise, OFFSETA does not change.
The algorithm used to update WA in read mode is the same, except that full refers to all data of the
window has been read or window empty.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
265
ISS Interfaces
www.ti.com
For read/write mode, the same algorithm is used to translate reads to the WBx window. Make the
following changes:
• Replace WA with WB.
• Replace LEVELA with LEVELB.
• Replace VPA with VPB.
• Replace OFFSETA with OFFSETB.
2.9.3.2.7
ISS CBUFF Error State
Contexts may go into error state when they receive unexpected accesses. In that case, the CBUFF does
not send dummy transactions to the OCPO port. It does not forward the failing transactions to OCPO and
returns valid responses (SResp = DVA) on OCPI to preserve the integrity of the OCP.
Responses may be received on OCPO while the CBUFF responds to failing transactions on OCPI. The
OCPO response phase is stalled (MRespAccept = 0) during that time to prevent corruption. OCPO cannot
be stalled longer than one full OCP transaction. Responses received on OCPO are handled before
another internally generated response can be sent back to the OCPI. In that case, command and data
phases are eventually stalled. Not stalling OCPO for too long is required to avoid affecting system
performance.
During normal operation (that is, no context is in error state), the OCPO response phase is never stalled.
2.9.3.2.8
ISS CBUFF Typical Configurations
2.9.3.2.8.1 ISS CBUFF Single-Slice Buffer
An OCP master (typically, the ISS) writes data with an incremental addressing scheme to the virtual
space. The physical space is smaller than the virtual space. Therefore, physical space locations are read
and written multiple times. Figure 100 shows the CBUFF single-slice buffer in write mode.
Figure 100. ISS CBUFF Single-Slice Buffer (Write Mode)
Virtual
space
pace
Physical space
(SDRAM)
JPEG
codec
Camera ISP
The camera
ISP writes a full
frame to the
virtual space.
Another module uses
data stored in SDRAM. It
informs the CBUFF
when it is done
with a physical buffer.
The CBUFF
maps virtual
addresses to
physical addresses
in SDRAM. Data is
stored in SDRAM.
Physically, this CBUFF is in on-chip SRAM or SDRAM. The virtual space is defined by a start and end
addresses. The physical space is defined by a start address, a window size, and a window count. It is
contiguous in memory. When the CPU accesses physical memory for processing, it must know if the
SDRAM is available for it to access and if the CBUFF is not using it. The CPU and CBUFF cannot track
each other. For example, an interrupt must be triggered from the SIMCOP to the CBUFF to notify it when
the processor is done working with SDRAM. For more information about the software configuration for
these interrupts, see Section 2.9.3.2.2.1, ISS CBUFF Write Mode.
Figure 101 shows the buffer organization for a 4-window buffer.
266
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Figure 101. ISS CBUFF Single-Slice Buffer Example (Write Mode)
Virtual space
Physical space
CBUFF
CBUFF_CTX_PHY_x
CBUFF_CTX_START
Mapped to W0
Window 0
Mapped to W1
Read
pointer (managed
ARM/DSP/
by ARM
EDMA)
WBx
Mapped to W2
Mapped to W3
Window 1
Win
Mapped to W0
WAx
Mapped to W1
Mapped to W2
Mapped to W3
CBUFF_CTX_END_x
The CBUFF can manage multiple contexts in single-slice mode.
2.9.3.2.8.2 ISS CBUFF Extended-Slice Buffer
In extended-slice mode, at least two contexts managed by the CBUFF are used together. The two
contexts provide address translation, one for the read data flow and the other for a write data flow.
Figure 102 is an example of the CBUFF extended-slice buffer.
Figure 102. ISS CBUFF Extended-Slice Buffer Example
Physical
space 1
(SDRAM)
Virtual
space 1
2.9.3.2.9
Physical
space 2
(SDRAM)
Camera
ISP
Software
preprocessing
software and stored in
SDRAM. If informs
the circular buffer
when a buffer is filled.
Virtual
space 2
ISP reads a full
frame from virtual
space 1. Addresses
are remapped into
the physical space
by the circular buffer.
ISP may be
stalled to wait
for the codec
or the software
preprocessing
step
JPEG
codec
The camera
ISP writes a full
frame to the
virtual space.
The CBUFF
Another module uses
maps virtual
data stored in SDRAM.
addresses to
It informs the CBUFF
physical addresses
when it is done
in SDRAM. Date is with a physical buffer.
stored in SDRAM.
ISS CBUFF FIFO Mode
The CBUFF can behave like a FIFO to buffer data between two initiators connected to the OCPI. A typical
use case is a camera interface writing data to the FIFO and an ISP reading data from the FIFO.
Figure 103 shows the CBUFF FIFO mode.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
267
ISS Interfaces
www.ti.com
Figure 103. ISS CBUFF FIFO Mode
Virtual
space
Physical
space
(SDRAM)
Virtual
space
Camera
ISP
Camera
The CBUFF is used as a FIFO when the camera provides data at a higher rate than the ISP can process.
To avoid storing one or multiple full-frame buffers, a FIFO buffer is used to store the data that cannot be
processed immediately.
For this example, assume that the camera provides 16 MPix at 15 frames per second. A new frame is
provided every 66 ms. The ISP needs 80 ms to process this frame. Therefore, the processing cannot be
done on the fly, and each other frame must be dropped.
Figure 104 shows the accumulated amount of data provided by the camera since the start of the frame;
the amount of data consumed by the ISP since it has started processing the frame; and the difference
between the two, which must be stored in the FIFO.
Figure 104. ISS CBUFF FIFO Use Example
Amount of data
provided by the
camera
Camera provides data
@ 15fps
Each other frame dropped
VBlank= 6ms
Amount of data
consumed by
the ISP
Full
frame
size
FIFO
size
Amount of data
he
stored in the
FIFO
Frame = 60 ms
Processing = 80ms
The FIFO is emulated as 16 windows (CBUFF_CTX_CTRL_i[9:8] WCOUNT = 0x3). The ISP is started by
software when a few kilobytes of data are written to the physical space. Alternatively, the BCF mechanism
can be used, but the minimum FIFO size is more complex to calculate.
The FIFO level reaches its maximum when the camera performs the last write of the frame. The camera
provides the data at 1 byte/pixel 16 MPix/60 ms = 266 Mbps. The ISP reads data at 1 byte/pixel × 16
MPix/80 ms = 200 Mbps. Therefore, the minimum FIFO size is 60 ms × (266 Mbps – 200 Mbps) = 3.96
Mbps, which is four times less than a full-frame buffer.
Each window holds 256KB of data. The camera starts writing to a new physical window every 256KB/266
Mbps = 962 µs. The ISP starts reading from a new physical window every 1280 µs.
The FIFO mode can also be used when the ISP is faster than the camera. In that case, the ISP is stalled
when insufficient data is available in the physical space.
268
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.4
ISS CBUFF Programming Model
2.9.4.1
ISS CBUFF Reset Behavior
Upon hardware or software reset of the CBUFF, all registers in the CBUFF are reset to their reset values
This software reset has the same effect as a hardware reset. ISS high-level software reset ensures that
traffic is stopped on clear boundary because the CBUFF is sending data to and from other modules. ISS
top-level reset is preferred. For more information about ISS software reset, see Section 1.2.4, ISS Reset.
Submodule reset is not preferred but is available through the following registers:
1. Set the CBUFF_HL_SYSCONFIG[0] SOFTRESET bit to 1.
2. Read the CBUFF_HL_SYSCONFIG[0] SOFTRESET bit to check whether it is set to 1, which means
the reset occurred.
The reset is performed without waiting until all OCP traffic stops. To avoid OCP corruption, software must
ensure there is no more ongoing traffic before performing a reset.
2.9.4.2
ISS CBUFF Register Setup
All registers of the context to be used must be initialized for correct operation. Table 147 lists the
procedure for the CBUFF register setup.
Table 147. ISS CBUFF Setup Register
Step
Bit Field
Value
Set operation mode.
CBUFF_CTX_CTRL_i[2:1] MODE
0x0: Write mode
0x1: Read mode
0x2: Read/write mode
0x3: Reserved
Define the virtual address range managed by the
CBUFF. It usually corresponds to the address
region where one image frame is written by the
OCPI initiator.
CBUFF_CTX_START_i and CBUFF_CTX_END_i
Define the start address of the physical buffer.
CBUFF_CTX_PHY_i
Set the window count and size. The window size
usually depends on the use of the buffer. 8 or 16
video lines correspond to a current size for JPEG
video compression. A higher window count
provides better latency-related overflow protection.
CBUFF_CTX_CTRL_i[9:8] WCOUNT and
CBUFF_CTX_WINDOWSIZE_i
When the 2D addressing capability is not used, set
to the window size in
CBUFF_CTX_THRESHOLD_F_i. Otherwise, it is
set to a smaller value depending on the buffer
organization. For example, when each window
corresponds to lines by 4096 pixels, but the ISP
sends lines of only 2560 pixels,
CBUFF_CTX_WINDOWSIZE_i = 8 4096 and
CBUFF_CTX_THRESHOLD_F_i = 8 2560.
CBUFF_CTX_THRESHOLD_F_i
BCF signal-generation configuration is optional.
CBUFF_CTX_THRESHOLD_S_i and
CBUFF_CTX_CTRL_i[7:4] BCF
Enable the module. It can be disabled by clearing
CBUFF_CTX_CTRL_i[0] ENABLE
the ENABLE bit. This must be done only when
there are no more outstanding requests to the
virtual space managed by CBUFFx. All internal
FSMs and counters of the CBUFF are reset when it
is disabled. Pending interrupts are not affected.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
269
ISS Interfaces
2.9.5
www.ti.com
ISS CBUFF Registers
Table 148 lists the CBUFF instance.
Table 148. ISS CBUFF Instance Summary
Module Name
Base Address
Cortex-M3 Private Access
Base Address
L3 Interconnect
Size
0x5504 1800
0x5C00 1800
512 bytes
ISS_CBUFF
Table 149 summarizes the CBUFF registers.
Table 149. ISS CBUFF Registers Mapping Summary
Register Name
CBUFF_HL_REVISION
CBUFF_HL_HWINFO
Register
Width
(Bits)
Address Offset
ISS_CBUFF
Base Address
Cortex-M3 Private
Access
ISS_CBUFF
Base Address
L3 Interconnect
R
32
0x0000 0000
0x5504 1800
0x5C00 1800
0x5C00 1804
R
32
0x0000 0004
0x5504 1804
CBUFF_HL_SYSCONFIG
RW
32
0x0000 0010
0x5504 1810
0x5C00 1810
RESERVED
RW
32
0x0000 001C
0x5504 181C
0x5C00 181C
CBUFF_HL_IRQSTATUS_RAW
RW
32
0x0000 0020
0x5504 1820
0x5C00 1820
CBUFF_HL_IRQSTATUS
RW
32
0x0000 0024
0x5504 1824
0x5C00 1824
CBUFF_HL_IRQENABLE_SET
RW
32
0x0000 0028
0x5504 1828
0x5C00 1828
CBUFF_HL_IRQENABLE_CLR
RW
32
0x0000 002C
0x5504 182C
0x5C00 182C
RW
32
0x0000 0080 +
(0x4 * j)
0x5504 1880 +
(0x4 * j)
0x5C00 1880 +
(0x4 * j)
RW
32
0x0000 0100 +
(0x20 * i)
0x5504 1900 +
(0x20 * i)
0x5C00 1900 +
(0x20 * i)
RW
32
0x0000 0104 +
(0x20 * i)
0x5504 1904 +
(0x20 * i)
0x5C00 1904 +
(0x20 * i)
RW
32
0x0000 0108 +
(0x20 * i)
0x5504 1908 +
(0x20 * i)
0x5C00 1908 +
(0x20 * i)
RW
32
0x0000 010C +
(0x20 * i)
0x5504 190C +
(0x20 * i)
0x5C00 190C +
(0x20 * i)
(1)
CBUFF_FRAG_ADDR_j
CBUFF_CTX_CTRL_i
(2)
CBUFF_CTX_START_i
CBUFF_CTX_END_i
(2)
(2)
CBUFF_CTX_WINDOWSIZE_i
(2)
CBUFF_CTX_THRESHOLD_F_i
(2)
RW
32
0x0000 0110 +
(0x20 * i)
0x5504 1910 +
(0x20 * i)
0x5C00 1910 +
(0x20 * i)
CBUFF_CTX_THRESHOLD_S_i
(2)
RW
32
0x0000 0114 +
(0x20 * i)
0x5504 1914 +
(0x20 * i)
0x5C00 1914 +
(0x20 * i)
R
32
0x0000 0118 +
(0x20 * i)
0x5504 1918 +
(0x20 * i)
0x5C00 1918 +
(0x20 * i)
RW
32
0x0000 011C +
(0x20 * i)
0x5504 191C +
(0x20 * i)
0x5C00 191C +
(0x20 * i)
CBUFF_CTX_STATUS_i
CBUFF_CTX_PHY_i
(1)
(2)
270
Type
(2)
(2)
j = 0 to 15
i = 0 to 7
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.1
CBUFF_HL_REVISION
Table 150. CBUFF_HL_REVISION
Address Offset
0x0000 0000
Physical Address
0x5504 1800
0x5C00 1800
Description
IP revision identifier (X.Y.R)
Used by software to track features, bugs, and compatibility
Type
R
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
9
8
7
6
5
4
3
2
1
0
1
0
REVISION
(1)
Bits
Field Name
Description
Type
Reset
31:0
REVISION
IP Revision
R
See (1)
TI internal data
2.9.5.2
CBUFF_HL_HWINFO
Table 151. CBUFF_HL_HWINFO
Physical Address
0x5504 1804
0x5C00 1804
Description
Information about the IP module's hardware configuration.
Type
R
Instance
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
9
8
7
6
5
4
3
2
RESERVED
Bits
Field Name
Description
Type
Reset
31:3
RESERVED
Reserved
R
0x0000 0000
2:1
CONTEXTS
Number of contexts
R
0x1
R
0
ENABLE_FRAGMENTATION
0x0000 0004
CONTEXTS
Address Offset
Read 0x0: 2 contexts
Read 0x1: 4 contexts
Read 0x2: 8 contexts
Read 0x3: Reserved
0
ENABLE_FRAGMENTATION
Provides information to software if fragmentation support
is available
Read 0x1: Yes
Read 0x0: No
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
271
ISS Interfaces
2.9.5.3
www.ti.com
CBUFF_HL_SYSCONFIG
Table 152. CBUFF_HL_SYSCONFIG
0x5504 1810
0x5C00 1810
Description
Clock management configuration
Type
RW
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
9
8
7
6
5
4
3
2
IDLEMODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bits
Field Name
Description
31:4
RESERVED
Reserved
3:2
IDLEMODE
Configuration of the local target state management mode.
By definition, target can handle read/write transaction as
long as it is out of IDLE state.
1
0
SOFTRESET
0x0000 0010
Physical Address
RESERVED
Address Offset
Type
Reset
R
0x0000000
RW
0x2
R
0
RW
0
0x0: Force-idle mode: local target's idle state follows
(acknowledges) the system's idle requests
unconditionally, that is, regardless of the IP module's
internal requirements.
Backup mode, for debug only.
0x1: No-idle mode: local target never enters IDLE state.
Backup mode, for debug only.
0x2: Smart-idle mode: local target's IDLE state eventually
follows (acknowledges) the system's IDLE requests,
depending on the IP module's internal requirements.
IP module shall not generate (IRQ- or DMA-requestrelated) wake-up events.
0x3: Reserved
1
RESERVED
Reserved
0
SOFTRESET
Software reset
Write 0x0: No action
Write 0x1: Initiate software reset
Read 0x1: Reset (software or other) ongoing
Read 0x0: Reset done, no pending action
272
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.4
CBUFF_HL_IRQSTATUS_RAW
Table 153. CBUFF_HL_IRQSTATUS_RAW
Address Offset
0x0000 0020
Physical Address
0x5504 1820
0x5C00 1820
Description
Per-event raw interrupt status vector.
Raw status is set even if event is not enabled.
Write 1 to set the (raw) status, mostly for debug.
Type
RW
Bits
31
Field Name
Description
IRQ_CTX7_OVR
Buffer overflow event.
Write 0x0: No action
9
8
7
6
5
4
3
2
1
0
IRQ_OCP_ERR
IRQ_CTX2_READY
IRQ_CTX3_READY
IRQ_CTX4_READY
IRQ_CTX5_READY
IRQ_CTX6_READY
IRQ_CTX7_READY
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_OVR
IRQ_CTX1_OVR
IRQ_CTX2_OVR
IRQ_CTX3_OVR
IRQ_CTX4_OVR
IRQ_CTX5_OVR
IRQ_CTX6_OVR
IRQ_CTX7_OVR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_READY
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
IRQ_CTX1_READY
Instance
RESERVED
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
30
IRQ_CTX6_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
29
IRQ_CTX5_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
28
IRQ_CTX4_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
27
IRQ_CTX3_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
26
IRQ_CTX2_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
273
ISS Interfaces
Bits
25
www.ti.com
Field Name
Description
IRQ_CTX1_OVR
Buffer overflow event.
Write 0x0: No action
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
24
IRQ_CTX0_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
17
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
274
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
16
Field Name
Description
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
15
IRQ_CTX7_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
14
IRQ_CTX6_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
13
IRQ_CTX5_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
12
IRQ_CTX4_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
11
IRQ_CTX3_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
10
IRQ_CTX2_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
9
IRQ_CTX1_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
275
ISS Interfaces
Bits
8
www.ti.com
Field Name
Description
IRQ_CTX0_READY
The WB physical window is ready to be accessed by the
CPU.
Type
Reset
RW
W1toSet
0
R
0x00
RW
W1toSet
0
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
7:1
0
RESERVED
Reserved
IRQ_OCP_ERR
OCP error received in the master port.
Write 0x0: No action
Write 0x1: Set event (debug)
Read 0x1: Event pending
Read 0x0: No event pending
276
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.5
CBUFF_HL_IRQSTATUS
Table 154. CBUFF_HL_IRQSTATUS
Address Offset
0x0000 0024
Physical Address
0x5504 1824
0x5C00 1824
Description
Per-event "enabled" interrupt status vector.
Enabled status is not set unless event is enabled.
Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not
enabled).
Type
RW
Bits
31
Field Name
Description
IRQ_CTX7_OVR
Buffer overflow event.
Write 0x0: No action
9
8
7
6
5
4
3
2
1
0
IRQ_OCP_ERR
IRQ_CTX2_READY
IRQ_CTX3_READY
IRQ_CTX4_READY
IRQ_CTX5_READY
IRQ_CTX6_READY
IRQ_CTX7_READY
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_OVR
IRQ_CTX1_OVR
IRQ_CTX2_OVR
IRQ_CTX3_OVR
IRQ_CTX4_OVR
IRQ_CTX5_OVR
IRQ_CTX6_OVR
IRQ_CTX7_OVR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_READY
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
IRQ_CTX1_READY
Instance
RESERVED
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
30
IRQ_CTX6_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
29
IRQ_CTX5_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
28
IRQ_CTX4_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
27
IRQ_CTX3_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
26
IRQ_CTX2_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
277
ISS Interfaces
Bits
25
www.ti.com
Field Name
Description
IRQ_CTX1_OVR
Buffer overflow event.
Write 0x0: No action
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
24
IRQ_CTX0_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
17
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
278
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
16
Field Name
Description
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
15
IRQ_CTX7_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
14
IRQ_CTX6_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
13
IRQ_CTX5_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
12
IRQ_CTX4_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
11
IRQ_CTX3_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
10
IRQ_CTX2_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
9
IRQ_CTX1_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
279
ISS Interfaces
Bits
8
www.ti.com
Field Name
Description
IRQ_CTX0_READY
The WB physical window is ready to be accessed by the
CPU.
Type
Reset
RW
W1toClr
0
R
0x00
RW
W1toClr
0
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
7:1
0
RESERVED
Reserved
IRQ_OCP_ERR
OCP error received in the master port.
Write 0x0: No action
Write 0x1: Clear (raw) event
Read 0x1: Event pending
Read 0x0: No (enabled) event pending
280
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.6
CBUFF_HL_IRQENABLE_SET
Table 155. CBUFF_HL_IRQENABLE_SET
Address Offset
0x0000 0028
Physical Address
0x5504 1828
0x5C00 1828
Description
Per-event interrupt enable bit vector.
Write 1 to set (enable interrupt).
Readout equal to corresponding _CLR register.
Type
RW
Bits
31
Field Name
Description
IRQ_CTX7_OVR
Buffer overflow event.
Write 0x0: No action
9
8
7
6
5
4
3
2
1
0
IRQ_OCP_ERR
IRQ_CTX2_READY
IRQ_CTX3_READY
IRQ_CTX4_READY
IRQ_CTX5_READY
IRQ_CTX6_READY
IRQ_CTX7_READY
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_OVR
IRQ_CTX1_OVR
IRQ_CTX2_OVR
IRQ_CTX3_OVR
IRQ_CTX4_OVR
IRQ_CTX5_OVR
IRQ_CTX6_OVR
IRQ_CTX7_OVR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_READY
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
IRQ_CTX1_READY
Instance
RESERVED
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
30
IRQ_CTX6_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
29
IRQ_CTX5_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
28
IRQ_CTX4_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
27
IRQ_CTX3_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
26
IRQ_CTX2_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
281
ISS Interfaces
Bits
25
www.ti.com
Field Name
Description
IRQ_CTX1_OVR
Buffer overflow event.
Write 0x0: No action
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
24
IRQ_CTX0_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
17
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
282
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
16
Field Name
Description
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
RW
W1toSet
0
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
15
IRQ_CTX7_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
14
IRQ_CTX6_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
13
IRQ_CTX5_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
12
IRQ_CTX4_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
11
IRQ_CTX3_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
10
IRQ_CTX2_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
9
IRQ_CTX1_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
283
ISS Interfaces
Bits
8
www.ti.com
Field Name
Description
IRQ_CTX0_READY
The WB physical window is ready to be accessed by the
CPU.
Type
Reset
RW
W1toSet
0
R
0x00
RW
W1toSet
0
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
7:1
0
RESERVED
Reserved
IRQ_OCP_ERR
OCP error received in the master port.
Write 0x0: No action
Write 0x1: Enable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
284
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.7
CBUFF_HL_IRQENABLE_CLR
Table 156. CBUFF_HL_IRQENABLE_CLR
Address Offset
0x0000 002C
Physical Address
0x5504 182C
0x5C00 182C
Description
Per-event interrupt enable bit vector, line 0.
Write 1 to clear (disable interrupt).
Readout equal to corresponding _SET register.
Type
RW
Bits
31
Field Name
Description
IRQ_CTX7_OVR
Buffer overflow event.
Write 0x0: No action
9
8
7
6
5
4
3
2
1
0
IRQ_OCP_ERR
IRQ_CTX2_READY
IRQ_CTX3_READY
IRQ_CTX4_READY
IRQ_CTX5_READY
IRQ_CTX6_READY
IRQ_CTX7_READY
IRQ_CTX0_INVALID
IRQ_CTX1_INVALID
IRQ_CTX2_INVALID
IRQ_CTX3_INVALID
IRQ_CTX4_INVALID
IRQ_CTX5_INVALID
IRQ_CTX6_INVALID
IRQ_CTX7_INVALID
IRQ_CTX0_OVR
IRQ_CTX1_OVR
IRQ_CTX2_OVR
IRQ_CTX3_OVR
IRQ_CTX4_OVR
IRQ_CTX5_OVR
IRQ_CTX6_OVR
IRQ_CTX7_OVR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IRQ_CTX0_READY
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
IRQ_CTX1_READY
Instance
RESERVED
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
30
IRQ_CTX6_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
29
IRQ_CTX5_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
28
IRQ_CTX4_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
27
IRQ_CTX3_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
26
IRQ_CTX2_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
285
ISS Interfaces
Bits
25
www.ti.com
Field Name
Description
IRQ_CTX1_OVR
Buffer overflow event.
Write 0x0: No action
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
24
IRQ_CTX0_OVR
Buffer overflow event.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
23
IRQ_CTX7_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
22
IRQ_CTX6_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
21
IRQ_CTX5_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
20
IRQ_CTX4_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
19
IRQ_CTX3_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
18
IRQ_CTX2_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
17
IRQ_CTX1_INVALID
Invalid access.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
286
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
Bits
16
Field Name
Description
IRQ_CTX0_INVALID
Invalid access.
Write 0x0: No action
Type
Reset
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
RW
W1toClr
0
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
15
IRQ_CTX7_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
14
IRQ_CTX6_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
13
IRQ_CTX5_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
12
IRQ_CTX4_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
11
IRQ_CTX3_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
10
IRQ_CTX2_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
9
IRQ_CTX1_READY
The WB physical window is ready to be accessed by the
CPU.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
287
ISS Interfaces
Bits
8
www.ti.com
Field Name
Description
IRQ_CTX0_READY
The WB physical window is ready to be accessed by the
CPU.
Type
Reset
RW
W1toClr
0
R
0x00
RW
W1toClr
0
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
7:1
0
RESERVED
Reserved
IRQ_OCP_ERR
OCP error received in the master port.
Write 0x0: No action
Write 0x1: Disable interrupt
Read 0x1: Interrupt enabled
Read 0x0: Interrupt disabled (masked)
2.9.5.8
CBUFF_FRAG_ADDR_j
Table 157. CBUFF_FRAG_ADDR_j
Address Offset
0x0000 0080 + (0x4 * j)
Index
j = 0 to 15
Physical Address
See Table 149.
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Start address of the physical buffer of the CBUFF context 0.
This register only exists when fragmentation support is enabled.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
ADDR
Bits
Field Name
Description
31:4
ADDR
Address in 128-bit words
3:0
RESERVED
Reserved
288
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.9
CBUFF_CTX_CTRL_i
Table 158. CBUFF_CTX_CTRL_i
Index
i = 0 to 7
0x5504 1900 + (0x20 * i)
0x5C00 1900 + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Context control register
Type
RW
8
7
6
WCOUNT
9
DONE
RESERVED
TILERMODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits
Field Name
Description
31:12
RESERVED
Reserved
11
TILERMODE
Sets the expected value for ADDR[32].
If ADDR[32]=TILERMODE, ADDR[31:4] is processed and
eventually translated.
Otherwise, the access is handled as transparent,
regardless of the other address bits.
10
DONE
Write this bit to 1 to indicate the CPU has finished
processing its physical buffer.
This bit is automatically cleared by hardware, reads
always return 0.
This bit has no effect when MODE=2 (read/write)
5
BCF
4
3
2
MODE
Type
Reset
R
0x00000
RW
0
W
0
RW
0x0
RW
0x0
R
0
1
0
ENABLE
0x0000 0100 + (0x20 * i)
Physical Address
RESERVED
Address Offset
Write 0x0: No effect.
Write 0x1: The CPU has completely processed the WB
physical buffer.
9:8
WCOUNT
Window count
0x0: 2 windows
0x1: 4 windows
0x2: 8 windows
0x3: 16 windows
7:4
3
BCF
This register controls the bandwidth control feedback
loop output.
0: Control loop disabled.
1-15: The control feedback loop enabled.
Behavior depends on functional mode, see
Section 2.9.3.2.4, ISS CBUFF Memory-to-Memory
Operation BCF.
RESERVED
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
289
ISS Interfaces
www.ti.com
Bits
Field Name
Description
2:1
MODE
Selects the functional mode of this context
Type
Reset
RW
0x0
RW
0
0x0: Write mode.
ISS writes and CPU reads the physical space.
CPU accesses are out of the scope of the CBUFF
module;
therefore, only writes are permitted between
CBUFF_CTX_START__x and CBUFF_CTX_END__x.
0x1: Read mode.
Hardware reads and CPU writes the physical space.
CPU accesses are out of the scope of the CBUFF
module;
therefore, only reads are permitted between
CBUFF_CTX_START__x and CBUFF_CTX_END__x.
0x2: Read/Write mode.
Read and writes are monitored by the CBUFF.
WB is used to track current read positions
WA is used to track current write position.
0
ENABLE
Enable/disable
0x0: Disables the context.
This resets the internal state of the context.
All accesses received on OCPI are transmitted to OCPO
without modification.
Disabling the context takes effect immediately.
Software must ensure that no more accesses to the
context are outstanding before disabling it.
Otherwise memory corruption may occur.
0x1: Enable the context.
All accesses between CBUFF_CTX_START__x and
CBUFF_CTX_END__x are processed by the CBUFF.
290
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.10
CBUFF_CTX_START_i
Table 159. CBUFF_CTX_START_i
Address Offset
0x0000 0104 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1904 + (0x20 * i)
0x5C00 1904 + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Start address of the virtual space managed by the context
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
ADDR
2
1
0
RESERVED
Bits
Field Name
Description
31:4
ADDR
Address in 128-bit words
3:0
RESERVED
Reserved
2.9.5.11
3
Type
Reset
RW
0x0000000
R
0x0
CBUFF_CTX_END_i
Table 160. CBUFF_CTX_END_i
Address Offset
0x0000 0108 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1908 + (0x20 * i)
0x5C00 1908 + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
End address of the virtual space managed by the context
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
ADDR
Bits
Field Name
Description
31:4
ADDR
Address in 128-bit words
3:0
RESERVED
Reserved
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x0
291
ISS Interfaces
2.9.5.12
www.ti.com
CBUFF_CTX_WINDOWSIZE_i
Table 161. CBUFF_CTX_WINDOWSIZE_i
Address Offset
0x0000 010C + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 190C + (0x20 * i)
0x5C00 190C + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Defines the size of a window
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:4
SIZE
Size in 128-bit words
3:0
RESERVED
Reserved
2.9.5.13
9
8
7
6
5
4
SIZE
3
2
1
0
RESERVED
Type
Reset
R
0x00
RW
0x00000
R
0x0
CBUFF_CTX_THRESHOLD_F_i
Table 162. CBUFF_CTX_THRESHOLD_F_i
Address Offset
0x0000 0110 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1910 + (0x20 * i)
0x5C00 1910 + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Threshold value used to check if a write window is full
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
8
7
6
5
4
3
2
1
0
THRESHOLD
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:0
THRESHOLD
Threshold value, in bytes
292
9
Type
Reset
R
0x00
RW
0x000000
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS Interfaces
www.ti.com
2.9.5.14
CBUFF_CTX_THRESHOLD_S_i
Table 163. CBUFF_CTX_THRESHOLD_S_i
Address Offset
0x0000 0114 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1914 + (0x20 * i)
0x5C00 1914 + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Threshold value used to control the BCF synchronization mechanism
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bits
Field Name
Description
31:24
RESERVED
Reserved
23:0
THRESHOLD
Threshold value, in bytes
2.9.5.15
9
8
7
6
5
4
3
2
1
0
THRESHOLD
Type
Reset
R
0x00
RW
0x000000
CBUFF_CTX_STATUS_i
Table 164. CBUFF_CTX_STATUS_i
Address Offset
0x0000 0118 + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 1918 + (0x20 * i)
0x5C00 1918 + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Status register
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
WA
8
7
6
5
4
RESERVED
3
2
Bits
Field Name
Description
Type
Reset
31:12
RESERVED
Reserved
R
0x00000
11:8
WA
Valid values depend on the
CBUFF_CTX_CTRL__x.WCOUNT register.
R
0x0
7:4
RESERVED
Reserved
R
0x0
3:0
WB
Valid values depend on the
CBUFF_CTX_CTRL__x.WCOUNT register.
R
0x0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
1
0
WB
293
ISS Interfaces
2.9.5.16
www.ti.com
CBUFF_CTX_PHY_i
Table 165. CBUFF_CTX_PHY_i
Address Offset
0x0000 011C + (0x20 * i)
Index
i = 0 to 7
Physical Address
0x5504 191C + (0x20 * i)
0x5C00 191C + (0x20 * i)
Instance
ISS_CBUFF_CORTEX-M3
ISS_CBUFF_L3
Description
Start address of the first physical buffer managed by the context when fragmentation support is
disabled.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
ADDR
Bits
Field Name
Description
31:4
ADDR
Address in 128-bit words.
3:0
RESERVED
Reserved
294
5
4
3
2
1
0
RESERVED
Type
Reset
RW
0x0000000
R
0x0
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3
ISS ISP
This section describes the image signal processor.
3.1
ISS ISP Overview
The image signal processor (ISP) is part of the image subsystem (ISS) of the device and is a key
component for imaging and video applications. This section describes all ISP modules in the multimedia
device; that is, the video port (VP), image pipe interface (IPIPEIF), image pipe module (IPIPE), resizer
(RSZ), hardware 3A (H3A), image sensor interface (ISIF), and buffer logic (BL).For better understanding,
see the first top-level ISS diagram and feature list in , ISS Overview.
3.1.1
ISS ISP Features
The video-processing hardware removes the need for expensive camera modules to perform processing
functions. The ISS can support the following features:
• On-the-fly or memory-to-memory processing
• Up to 200-MHz pixel throughput.
• Statistic data collection
– On-the-fly or memory-to-memory operation
– Data collection for auto exposure
– Data collection for auto white balance
– Data collection for auto focus
– Boundary signal calculation for video stabilization
• IPIPE front end: RAW data processing
– On-the-fly or memory-to-memory processing
– 16-bit-wide RAW BAYER data path between image and sensor linearization module
– 12-bit-wide RAW BAYER data path between sensor linearization module and gamma correction
module. Gamma correction module outputs 10-bit data.
– Programmable Bayer RGB positions
– Sensor data linearization for dynamic range extension
– Programmable 2D lens shading compensation (LSC)
– Per-pixel gain and offset control
– Black level compensation
– Boxcar filter
– Data collection for histogram generation
– Defect pixel correction (LUT_DPC) with look-up table (LUT)
– Defect pixel correction (OTF_DPC) with on-the-fly detection and correction
– 2D noise filtering
– Green imbalance correction (GIC)
– Digital gains and offset
– 8- to 10-bit A-law decompression and 10- to 8-bit A-law compression
• IPIPE back end: RGB and YUV data processing
– RGB-to-RGB color correction
– Gamma correction (GC).
– 3D LUT for color correction
– 2D edge enhancement (EE)
– RGB - YUV4:2:2: Color conversion, cosited chroma filtering and downsampling
– False chroma suppression (FCS)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
295
ISS ISP
•
www.ti.com
Two resizers
– Performance: input and output rates up to 200 MPix/s
– YUV4:2:2 to RGB565, ARGB888, YUV4:2:2, and YUV4:2:0 data output
– YUV4:2:0 to YUV4:2:0 data output
– RAW to RAW data output
– Range from x1/4096 to x20. Supports memory-to-memory rescaling.
The ISP comprises the following modules:
• IPIPE interface (IPIPEIF)
• Image sensor interface (ISIF) accelerator
• Auto exposure, auto white balance, and auto focus engine (H3A)
• Image pipe accelerator (IPIPE)
• Two resizer (RSZ) accelerators
• Buffer logic (BL): Receives module requests, performs arbitration, and creates read/write bursts to the
memory subsystem
3.1.2
ISS ISP Block Diagram
Figure 105 is the ISP top-level block diagram. The ISS supports three simultaneous pixel flows (Stall
controller, CSI2 A, and parallel interface [CPI]), but only one of them at a time can use the videoprocessing hardware; the others can go directly to memory (CPI must always use ISP).
The ISP master port is connected to the level 3 (L3) interconnect, and the slave port is connected to the
level 4 (L4) interconnect.
Figure 105. ISS ISP Block Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
296
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.2
ISS ISP Integration
This section describes the integration of the ISP modules in the ISP and includes information about
clocks, resets, and hardware requests.
The ISP is part of the ISS of the device and is a key component for imaging and video applications such
as camera viewfinder, video record, and still image capture.
ISS is coupled with a low interrupt latency ISS microprocessor unit (MPU) subsystem running a real-time
operating system to reach optimal performance. Primarily, the ISS MPU subsystem can quickly change
the ISS configuration during frame blanking periods and run some sequencing tasks.
3.2.1
ISS ISP PRCM Interface
The ISP and its internal modules, as integrated in the ISS, use the same power and clock management
details.
3.2.1.1
ISS ISP Clocks
The PRCM module, through the local power and clock management inside the ISS, provides a unique
PCLK that can be enabled from the ISP5_CTRL register.
The modules inside the ISP require three clocks:
• PCLK: This clock is asynchronous to the other clocks. It is provided by the module sending the data to
the IPIPEIF module on the VP.
• ISS_ FCLK: This clock is synchronous with the configuration clock domain. This is the clock used for
the MTC interface.
• GCK_MMR: This is the clock for the configuration bus. It is created from the ISS_FCLK and runs at
half the speed of the ISS_FCLK.
3.2.1.2
ISS ISP Reset
The ISP supports global software reset along with internal hardware reset, if needed.
Software reset is done through the ISP5_SYSCONFIG[1] SOFTRESET bit. Before issuing a software
reset, the ISP must be in standby mode. The following must be done:
1. Ensure that the interfaces are stopped from sending data and/or the ISP modules are disabled. Before
reset, the last interrupt triggered by the ISP when the frame processing completes is RSZ_INT_DMA.
RSZ_INT_DMA must be used to enable clean termination of the processing. Software must wait a few
hundred cycles to trigger a soft reset after RSZ_INT_DMA is asserted; this is to ensure that the BL is
completely drained.
2. Ensure that ISP5_SYSCONFIG[5:4] STANDBYMODE = 2 (smart standby). Write the ISP5_CTRL[24]
MSTANDBY bit to 1 and poll for ISP5_CTRL[20] MSTANDBY_WAIT = 1. Then, the soft reset can be
applied (ISP5_SYSCONFIG[1] SOFTRESET = 1).
In case an ISP overflow or underflow event happens (for example, RSZ_FIFO_OVF, ISIF_OVF, etc.), it is
not sufficient to reset the ISP. In that case a reset must take place at the ISS level.
3.2.2
ISS ISP Interrupt Tree
Table 166 summarizes the submodule interrupts that can be mapped to the four ISP interrupt output lines.
After this, these output lines are mapped to the ISS top interrupt request (IRQ) merger (for more
information, see ). Software enables the explained before merger from the top-level ISS resources
registers in .
Table 166. ISS ISP Interrupt Tree Table
Register
ISP5_IRQENABLE_SET_i[9] IPIPEIF_IRQ
Module
Destination
Comments
IPIPEIF
ISP to ISS merger four
IRQ lines
See Section 3.2.3.1.
ISP5_IRQENABLE_SET2_i[1] IPIPEIF_UDF
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
297
ISS ISP
www.ti.com
Table 166. ISS ISP Interrupt Tree Table (continued)
Register
Module
ISP5_IRQENABLE_SET_i[29]
IPIPE_INT_DPC_RNEW1
Destination
Comments
IPIPE
See Section 3.2.4.1.
H3A
See Section 3.2.6.
RSZ
See Section 3.2.5.2.
ISIF
See Section 3.2.7.1.
ISP5_IRQENABLE_SET_i[28]
IPIPE_INT_DPC_RNEW0
ISP5_IRQENABLE_SET_i[27] IPIPE_INT_DPC_INI
ISP5_IRQENABLE_SET_i[8] IPIPE_INT_HST
ISP5_IRQENABLE_SET_i[7] IPIPE_INT_BSC
ISP5_IRQENABLE_SET_i[6] IPIPE_INT_DMA
ISP5_IRQENABLE_SET_i[5] IPIPE_INT_LAST_PIX
ISP5_IRQENABLE_SET_i[4] IPIPE_INT_REG
ISP5_IRQENABLE_SET_i[25] IPIPE_INT_EOF
ISP5_IRQENABLE_SET2_i[5] IPIPE_BSC_ERR
ISP5_IRQENABLE_SET2_i[4] IPIPE_HST_ERR
ISP5_IRQENABLE_SET2_i[2] IPIPE_BOXCAR_OVF
ISP5_IRQENABLE_SET_i[12] H3A_INT
ISP5_IRQENABLE_SET_i[24] H3A_INT_EOF
ISP5_IRQENABLE_SET2_i[0] H3A_OVF
ISP5_IRQENABLE_SET_i[23] RSZ_INT_EOF1
ISP5_IRQENABLE_SET_i[22] RSZ_INT_EOF0
ISP5_IRQENABLE_SET_i[19]
RSZ_FIFO_IN_BLK_ERR
ISP5_IRQENABLE_SET_i[18] RSZ_FIFO_OVF
ISP5_IRQENABLE_SET_i[17] RSZ_INT_CYC_RZB
ISP5_IRQENABLE_SET_i[16] RSZ_INT_CYC_RZA
ISP5_IRQENABLE_SET_i[15] RSZ_INT_DMA
ISP5_IRQENABLE_SET_i[14] RSZ_INT_LAST_PIX
ISP5_IRQENABLE_SET_i[13] RSZ_INT_REG
ISP5_IRQENABLE_SET_i[3] ISIF_INT_3
ISP5_IRQENABLE_SET_i[2] ISIF_INT_2
ISP5_IRQENABLE_SET_i[1] ISIF_INT_1
ISP5_IRQENABLE_SET_i[0] ISIF_INT_0
ISP5_IRQENABLE_SET2_i[3] ISIF_OVF
3.2.3
ISS ISP IPIPEIF Integration
3.2.3.1
ISS ISP IPIPEIF Interrupts
The IPIPEIF module generates two interrupts:
• IPIPEIF_IRQ: This event is triggered to the BL module when a new frame starts (VS signal). The
interrupt is active low and is asserted for one GCK_MMR clock cycle.
• IPIPEIF_UDF: Interrupt generated when an underflow happens in the IPIPEIF module. Underflow
events are nonrecoverable at the ISP level and a soft reset is required at the ISS level.
The interrupts are enabled from the ISP5_IRQENABLE_SET_i[9] IPIPEIF_IRQ and
ISP5_IRQENABLE_SET2_i[1] IPIPEIF_UDF bits (where i = 0 to 3 for the line that will be mapped to the
four lines of the ISP). Then, each line from the ISP is sent to the ISS top level, where it is muxed with
other ISS modules for a total output of six interrupt lines.
298
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.2.4
ISS ISP IPIPE Integration
3.2.4.1
ISS ISP IPIPE Interrupts
IPIPE can generate several interrupts:
• IPIPE_INT_DPC_RNEW: This event is triggered when there is permission to initialize LUT-DPC table
lines 0 and 1.
• IPIPE_INT_DPC_INI: This event is triggered when the defect pixel correction (DPC) table is initialized.
• IPIPE_INT_HST: This event is triggered when the histogram is done.
• IPIPE_INT_BSC: This event is triggered when boundary signal calculation is done.
• IPIPE_INT_DMA: This event is triggered when the boxcar SDRAM transfer is done. On this timing,
IPIPE_INT_EOF is sent to the BL. This event is active high for one GCK_MMR clock cycle.
• IPIPE_INT_LAST_PIX: This event is triggered when the last pixel of a frame comes into IPIPE. This
event is active high for one GCK_MMR clock cycle.
• IPIPE_INT_EOF: This event is triggered for end of frame.
• IPIPE_BOXCAR_OVF: This event is generated when an overflow happens in the IPIPE-BOXCAR
output buffer. The interrupt avoids polling the IPIPE_SRC_STA[0] VAL0 bit for errors. Overflow events
are nonrecoverable at the ISP level and a soft reset is required at the ISS level.
• IPIPE_HST_ERR: This event is triggered when the MPU or system direct memory access (EDMA) is
still reading the memory that is being used by the module. This is an indication that the read operation
was not fast enough.
• IPIPE_BSC_ERR: This error happens when the BSC data is not read fast enough by the MPUs or the
EDMA.
The interrupts are enabled from the ISP5_IRQENABLE_SET_i and ISP5_IRQENABLE_SET2_i registers
(where i = 0 to 3 for the line that will be mapped to the four lines of the ISP). Then, each line from the ISP
is sent to the ISS top level, where it is muxed with other ISS modules for a total output of six interrupt
lines.
3.2.4.2
ISS ISP DMA Requests
The ISP generally outputs four direct memory access (DMA) requests, which can be used to read or write
memories inside the IPIPE module. These memories are:
• BSC memory: This memory must be read during a vertical blanking period. It is used by the video
stabilization application.
• HIST memory: This memory must be read during a vertical blanking period. It is used by the 3A
application. The HIST data is double-buffered from frame-to-frame. Software must select the memory
that is to be used by setting the IPIPE_HST_TBL[0] SEL bit.
• GAMMA memory: This memory must be set during a vertical blanking period. The imaging application
typically uses multiple gamma tables.
• DPC memory: This memory must be set during a frame acquisition. The memory is not big enough to
store all faulty pixels for a given frame.
To generate the DMA requests, the following events must be used:
• The IPIPE_INT_BSC event is used to generate the DMA request for the BSC memory. It maps on
DMA line 0, ISS_DMA0.
NOTE: If the BSC memory is not read fast enough the ISP5_IRQSTATUS2_i[5] IPIPE_BSC_ERR
event is set. This event is available whether memory read takes place with a DMA request or
an MPU read.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
299
ISS ISP
•
www.ti.com
The IPIPE_INT_HST event is used to generate the DMA request for the HIST memory. It maps on
DMA line 1, ISS_DMA1. The HIST data is double-buffered from frame-to-frame. Software must select
the memory that is to be used by setting the IPIPE_HST_TBL[0] SEL bit. When the DMA request is
set, it is required to read 4KB from the ping buffer address (0x2000) or the pong buffer address
(0x3000). Software must ensure that when one buffer is selected no other accesses (for example,
MPU) take place in the other buffer.
NOTE: If the HST memory is not read quickly enough the ISP5_IRQSTATUS2_i[5]
IPIPE_HST_ERR event is set. This event is available whether memory read takes place with
a DMA request or a CPU read.
•
•
The IPIPE_INT_LAST_PIX event is used to generate the DMA request for the GAMMA memory. This
same event can also be used to initialize the DPC LUT (not the preferred method; it is better to use
IPIPE_INT_DPC_INI). Basically, when the last pixel is output from the IPIPE module, it is safe to
modify the IPIPE memories. It maps on DMA line 3, ISS_DMA3.
The IPIPE_INT_DPC_INI event signals that DPC table memory initialization can take place.
IPIPE_INT_DPC_INI is used to generate two back-to-back DMA requests, the first one mapping on
IPIPE_INT_DPC_RNEW0 and the second one mapping on IPIPE_INT_DPC_RNEW1. After
initialization (steady state), the IPIPE_INT_DPC_RNEW0 and IPIPE_INT_DPC_RNEW1 events are
used to generate the DMA request for the DPC LUT renewal. It maps on DMA line 2, ISS_DMA2. To
select which event is used to initialize the DPC (IPIPE_INT_LAST_PIX or IPIPE_INT_DPC_INI), set
the ISP5_CTRL[25] DPC_EVT_INI bit.
NOTE: The size of the DPC table in SDRAM must be a multiple of the number of DMA requests. It
ensures that during burst capture mode the DMA always loads the correct data from frameto-frame. The DMA automatically warps back to the start of the table after all expected DMA
requests are received. There is a total of ceil(nb_faulty_pixel/128) + 2 DMA requests per
frame when the IPIPE_INT_DPC_INI EVENT is used. Hence, the size of the DPC table in
the SDRAM is (ceil(nb_faulty_pixel/128) + 2) × 128 × 32 bits.
NOTE: If DMA channels are not used but the MPU is used, an error check must be performed for
IPIPE HST and IPIPE BSC. See ISP5_CTRL[26] HST_RD_CHK and ISP5_CTRL[27]
BSC_RD_CHK for details.
The DMA request assertion and deassertion to the EDMA is automatic and no software intervention is
needed. The ISP contains two registers (ISP5_DMAENABLE_SET and ISP5_DMAENABLE_CLR) that
must be used to enable or disable generation of the DMA requests.
The DMA request deassertion is based on late deassertion; that is, the DMA request is disabled only
when all the data corresponding to the transfer size have been read or written. To deassert the DMA
request and generate the hw_eoi signal, hardware counts the number of 32-bit accesses that are done in
the memory range of the corresponding DMA request through the ISP slave port. When the number of
accesses corresponding to the DMA request is done, the DMA request is cleared. Multiple DMA requests
can be active simultaneously.
Software must not attempt to read or write in the memory range of the DMA requests that are enabled
because CPU accesses, instead of EDMA accesses, will be counted. Software can freely access ISP
memories for which the DMA request is disabled, and can access registers while the EDMA performs the
transfers.
300
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.2.5
ISS ISP RSZ Integration
3.2.5.1
3.2.5.1.1
ISS ISP RSZ PRCM Interface
ISS ISP RSZ Reset
The resizer module has no standalone software reset. RSZ must be reset at the ISP level. See
Section 3.2.1.2, ISS ISP Reset.
3.2.5.2
ISS ISP RSZ Interrupts
RSZ can generate several interrupts:
• RSZ_INT_EOF0: This event is triggered for end of frame.
• RSZ_INT_EOF1: This event is triggered for end of frame.
• RSZ_FIFO_IN_BLK_ERR: This event is triggered when the minimum vertical blanking period has not
been respected, thus causing errors in the input data buffering submodule. This event is triggered
when the RSZ_INT_REG event of frame N is triggered before RSZ_INT_DMA of frame N + 1. This
event typically happens at the transition between two frames because there is not enough vertical
blanking between frames. Hardware cannot recover from this error. It requires a reset. It is a
requirement that despite the error the RSZ module must finish correctly: ongoing requests are
completed and further requests are blocked.
• RSZ_FIFO_OVF: This event is triggered when overflow happens in the input data buffering
submodule. It typically occurs while processing a frame, because the VP pixel clock is too high.
Because hardware cannot recover from this error, a reset is required. It is a requirement that despite
the error the RSZ module must finish correctly: ongoing requests are completed and further requests
are blocked.
This event can be also triggered at the master write interface (MTC), where an MTC stall signal is
generated.
• RSZ_INT_CYC_RZA/RSZ_INT_CYC_RZB: This event is triggered as circular interrupt every time that
RSZ_IRQ_RZA/RSZ_IRQ_RZB output lines are written out to the RZA_SDR_Y/RZB_SDR_Y buffer.
The range can go from 1 to 8192 lines. Usually, this value must be such that the circular buffer vertical
size (set by the RZBA_SDR_Y_PTR_E/RZBB_SDR_Y_PTR_E register) is a multiple of
RSZ_IRQ_RZA/RSZ_IRQ_RZA.
• RSZ_INT_DMA: This event is triggered when the last EOF (of the two MTC interfaces) is sent out to
the BL and the RSZ core returns to idle. This event is active high for one GCK_MMR clock cycle.
• RSZ_INT_LAST_PIX: This event is triggered when the last pixel of the valid area is received. This
event is active high for one GCK_MMR clock cycle.
• RSZ_INT_REG: This event is triggered when the new value of the shadowed registers, if updated,
takes effect on the next RSZ_INT_REG event. Then again, shadowed registers can be updated for the
next frame after the RSZ_INT_REG event is triggered. This event is active high for one GCK_MMR
clock cycle.
The interrupts are enabled from the ISP5_IRQENABLE_SET_i register (where i = 0 to 3 for the line that
will be mapped to the four lines of the ISP). Then, each line from the ISP is sent to the ISS top level,
where it is muxed with other ISS modules for a total output of six interrupt lines.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
301
ISS ISP
3.2.6
www.ti.com
ISS ISP H3A Integration
3.2.6.1
ISS ISP H3A Interrupts
H3A can generate the following interrupts:
• H3A_INT: This event is triggered at the end of the last window or last paxel, whichever completes last.
This always triggers at the same time as H3A_INT_EOF.
• H3A_INT_EOF: This event is triggered and generated at the end of the last window. This event is
active high for one GCK_MMR clock cycle.
• H3A_OVF: This interrupt is generated when an overflow happens in the H3A output buffer. The
interrupt avoids polling the H3A_PCR[21] OVF bit for errors. Overflow events are nonrecoverable at
the ISP level and a soft reset is required at the ISS level. The event is active high for one GCK_MMR
clock cycle.
The interrupts are enabled from ISP5_IRQENABLE_SET_i and ISP5_IRQENABLE_SET2_i (where i = 0
to 3 for the line that will be mapped to the four lines of the ISP). Then, each line from the ISP is sent to the
ISS top level, where it is muxed with other ISS modules for a total output of six interrupt lines.
3.2.7
ISS ISP ISIF Integration
3.2.7.1
ISS ISP ISIF Interrupts
The ISIF can generate several interrupts:
• ISIF_INT_0: This event is triggered when the VD0 interrupt on line 0 is configured. The VD0 interrupt
can be configured based on the VD position. It is asserted after receiving the number of horizontal
lines (horizontal pulse signals) set in VDINT0. See Section 3.3.6.19.1 for more information.
• ISIF_INT_1: This event is triggered when the VD1 interrupt on line 1 is configured. The VD1 interrupt
can be configured based on the VD position. It is asserted after receiving the number of horizontal
lines (horizontal pulse signals) set in VDINT1. See Section 3.3.6.19.1 for more information.
• ISIF_INT_2: This event is triggered when the VD2 interrupt on line 2 is configured. The VD2 interrupt
can be configured based on the VD position. It is asserted after receiving the number of horizontal
lines (horizontal pulse signals) set in VDINT2. See Section 3.3.6.19.1 for more information.
• ISIF_INT_3: This event is triggered LSC interrupt is an interrupt issued by the 2D-LSC block. See
Section 3.3.6.10.1.5 for more information.
• ISIF_OVF: This Interrupt is generated when an underflow happens in the ISIF module. The interrupt
avoids polling the ISIF_MODESET[11] OVF bit for errors.
The interrupts are enabled from the ISP5_IRQENABLE_SET_i and ISP5_IRQENABLE_SET2_i registers
(where i = 0 to 3 for the line that will be mapped to the four lines of the ISP). Then, each line from ISP is
sent to the ISS top level where it is muxed with other ISS modules for a total output of six interrupt lines.
3.2.8
ISS ISP BL Integration
See Section 3.2, ISS ISP Integration.
302
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3
ISS ISP Functional Description
The functionality of the ISP is part of the overall performance of the ISS. For the top-level ISS diagram
with ISP inside and for a features list, see , ISS Overview. Figure 106 is an overview of the ISP module. It
outputs DMA and interrupt requests, has clocks coming in, and a stall signal to the SC in the ISS sensor
interfaces from the resizer. It also shows the top-level configuration for input to IPIPEIF. For the scaled-in
functional details of each submodule inside the ISP, see its functional description section.
Figure 106. ISS ISP High-Level Diagram
Imaging
subsystem
(ISS)
ISS sensor
interfaces
STALL
Video port
ISP
VD, HD, FLD
ISP5_CTRL[23] VD_PULSE_EXT
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
MTC STALL
Buffer logic
ISS_FLCK
PCLK
GCK_MMR
RESET
ISS_DMA[0:3]
ISP_IRQ[0:3]
Data
Bridge
Config
ISP registers
ISS interconnect
camss-707u
3.3.1
ISS ISP VP Functional Description
3.3.1.1
ISS ISP VP Overview
The VP supports a parallel interface that is used for interfacing with image sensors. The ISP VP can
transport 8- to 16-bit RAW data and 8-/16-bit YCbCr data.
Figure 107 shows the VP module connections to other submodules of the ISP.
3.3.1.2
ISS ISP VP Data Formats
The VP can be used to connect external camera receivers to the ISS. Data paths inside the ISP hardware
depend on the image format sourced by the sensor (RAW RGB, YUV4:2:2, JPEG, etc.). Table 167 shows
how the CSI2/SC modules are connected to the VP in function of the image format.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
303
ISS ISP
www.ti.com
Figure 107. ISS ISP VP High-Level Diagram
Imaging subsystem
(ISS)
ISS sensor
interfaces
ISP
Horizonta Sync (HS)
Vertical Sync (VS)
Field (FLD)
CAM_PCLK
pixel data
VD, HD, FLD
Video port
STALL
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
MTC STALL
Buffer logic
ISP registers
Data
Config
Bridge
ISS interconnect
camss-699
304
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 167. ISS ISP VP Format Mapping
Source
SC
CSI2
X
X
X
X
X
X
X
X
X
X
For
mat
Connected to
ISIF
Data Provided to ISIF Linearization Engine
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GW
DI
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RA
W16
R1
5
R1
4
R1
3
R1
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
R1
5
R1
4
R1
3
R1
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
RA
W14
R1
3
R1
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
R1
3
R1
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
R1
3
R1
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
1
R1
3
R1
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
1
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
R1
1
R1
0
R9
R8
R7
R5
R5
R4
R3
R2
R1
R0
0
0
0
0
2
R1
1
R1
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
0
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
0
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
1
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
R9
R8
R7
R5
R5
R4
R3
R2
R1
R0
0
0
0
0
2
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
3
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
1
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
R1
R0
2
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
3
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
4
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
0
0
0
0
0
RA
W12
RA
W10
RA
W8
YUV
16bit
R7
R6
R5
R4
R3
R2
R7
R6
R5
R4
R3
R2
R1
R0
R7
R5
R5
R4
R3
R2
R1
R0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
YUV
8-bit
C7
C6
C5
C4
C3
C2
C1
C0
0
YC YC YC YC YC YC YC YC
7
6
5
4
3
2
1
0
0
305
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
3.3.1.3
www.ti.com
ISS ISP VP Top-Level Communication With SC and CSI2 RX
At the ISS level, the VP is connected to the VP of the SC and CSI2 RX modules. VP implementation
differences force the introduction of a bridge between the SC/CIS2 RX modulesand the VP. The role of
the bridge is to perform VD pulse extension. The SC module assumes that the VD signal is active for at
least one pixel clock cycle, and the CSI2 RX module assumes that the VD signal is asserted for four pixel
clock cycles. However, the ISP assumes that the VD pulse is active on at least one line.
Figure 108 shows how the VD pulse extension works. Assume that VD-IN is the VD signal at the input of
the pulse extension bridge, and VD-OUT is the VD signal at the output of the pulse extension bridge.
The VD-OUT signal is asserted at the same time as VD-IN. The VD-OUT signal is kept high until one full
line is received. A line is delimited by two rising edges of the HD signal. The VD-OUT pulse is deasserted
on the next cycle after the falling edge of the HD signal.
Figure 108. ISS ISP VP VD Pulse
PCLK
VD-IN-
1 line
HD IN
VD-OUT
1 line
camss-691
The ISP5_CTRL[23] VD_PULSE_EXT bit controls whether the VD extension bridge is enabled or
disabled. By default, the bridge is enabled. When the bridge is disabled, the VD pulse must be unmodified:
VD-OUT = VD-IN. At the ISS level, it is expected that ISP5_CTRL [23] VD_PULSE_EXT = 1 when the VP
gets data from the CSI2 RX modules and ISP5_CTRL[23] VD_PULSE_EXT = 0 when the VP gets data
from the parallel interface or SC module.
CAUTION
A minimum of four lines per frame is required on the VP when the VD pulse
extension bridge is enabled; therefore, the VD extension bridge is not functional
if a 1-/2-/3-line frame is sent to the VP.
306
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.1.4
ISS ISP VP Pixel Clock Inversion
The ISP always uses the rising edge of the pixel clock to sample the pixel data. The ISP provides the
capability to invert the pixel clock so it can shift the resampling of a pixel clock period by half. This is
controlled by the ISP5_CTRL[22] PCLK_INV bit. By default, the inversion is disabled. The 5 bits in
Table 168 are resynchronized from the GCK_MMR clock domain to the PCLK clock domain. There must
be at least three clock cycles between the time these bits are modified and the HD/VD pulse for start of
frame comes.
Table 168. ISS ISP VP GCK_MMR to PCLK Clock Resynchronization
Module
3.3.2
Register
Bit Field
ISP
ISP5_CTRL
VD_PULSE_EXT
ISIF
ISIF_MODESET
HDVDD
ISIF
ISIF_MODESET
FIDD
ISP
ISP5_CTRL
ISIF_CLK_ENABLE
ISS ISP IPIPEIF Functional Description
3.3.2.1
ISS ISP IPIPEIF Overview
The IPIPEIF module provides data and synchronization signals (HD, VD) for the ISIF, IPIPE, RSZ, and
H3A modules. The data source of this module is the VP, ISIF, or SDRAM using BL, and the selected data
is output to ISIF, IPIPE, H3A, and RSZ. This module supports:
• Up to 16-bpp data on the VP
• Up to 200-MHz pixel clock on the VP, up to 8K × 8K image resolution
• RAW and YUV data formats on the VP and BL ports
• Dark-frame subtract of 8-bit RAW image stored in SDRAM from image from VP
• Dark-frame subtract of 8-bit RAW image stored in SDRAM from image from ISIF
• Dark-frame subtract of 8-bit RAW image from VP from image read from SDRAM through the BL
• Simple defect correction to prevent the subtraction of defect pixels
• 8-10, 8-12 DPCM decompression of 10-8, 12-8 DPCM compressed data in SDRAM
• Simple and advanced DPCM predictor
• Inverse A-Law decompression of RAW data 10-8 A-Law compressed from SDRAM
• 8-bit, 12-bit unpacking of 8-bit,12-bit packed SDRAM data
• Gain multiply for output data to IPIPE module
• Horizontal Bayer rescaler in the data paths to the IPIPE and H3A modules: Supports (1, 2, 1)
averaging filter and supports horizontal pixel decimation
• Data rate control when reading data from SDRAM: Fraction clock divider
• (1, 2, 1) averaging filter and supports horizontal pixel decimation in the data path to the IPIPE for YUV
data.
Figure 109 show the IPIPEIF module connections to other submodules of the ISP.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
307
ISS ISP
www.ti.com
Figure 109. ISS ISP IPIPEIF High-Level Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
camss-003e
308
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.2
ISS ISP IPIPEIF Top-Level Block Diagram
The following sections describe the function of each subblock in the IPIPEIF, as shown in Figure 110.
Figure 110. ISS ISP IPIPEIF Top-Level Block Diagram
16 bits
IPIPEIF_CFG1[15:14] INPSRC1
Video port
0
2
RAW/YCbCr data
ISIF
D
E
Dark
frame
subtraction
F
3
B
32 bits
DCPM
16 bits
IPIPEIF_CFG1[3:2] INPSRC2
Read
buffer
interface
Buffer logic
16 bits
1
C
RSZ
A
3
1
RAW/YCbCr data
2
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
RAW else
data gain
and clip
3 16 bits
IPIPE
16 bits
0
IPIPEIF_CFG1[3:2] INPSRC2
(1,2,1)
Averaging
filter
10 bits
Horizontal
pixel
decimator
H3A
10 bits
Timing generator
camss-030
NOTE: When the IPIPEIF receives data from the VP, the timing generator must be configured for
HD, VD, and WEN. For more information, see Section 3.3.2.5, ISS ISP IPIPEIF Timing
Generation.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
309
ISS ISP
3.3.2.3
www.ti.com
ISS ISP IPIPEIF Input Interface
The IPIPEIF module comprises two major interface blocks: VP and BL. The data types can be RAW or
YUV.
3.3.2.3.1
ISS ISP IPIPEIF Input From VP
The VP typically receives data from the image sensor. At the ISS level, it is connected to the serial
interface receivers.
3.3.2.3.2
ISS ISP IPIPEIF Input From BL
The BL is the interface with the memory (SDRAM). In that case, the SDRAM address and line offset
registers must be programmed in units of 32 bytes.
• SDRAM start address (byte) = (IPIPEIF_ADDRU[10:0] ADDRU) <<16 + (IPIPEIF_ADDRL[15:0]
ADDRL)
• SDRAM address offset (byte) = IPIPEIF_ADOFS[11:0] ADOFS
Two types of data can be stored in memory: pixel data and dark frame data.
For pixel data, the HD and VD signals are reconstructed with:
• IPIPEIF_HNUM
• IPIPEIF_VNUM
• IPIPEIF_LPFR
• IPIPEIF_PPLN
The IPIPEIF_HNUM and IPIPEIF_VNUM registers define the number of pixels per line and lines per frame
to read from the SDRAM, and the IPIPEIF_LPFR and IPIPEIF_PPLN registers define the interval of VD
and HD, respectively.
Vertical blanking for the frame is defined with the following equation: IPIPEIF_LPFR - IPIPEIF_VNUM - 1.
Horizontal blanking for the frame is defined with the following equation: IPIPEIF_PPLN - IPIPEIF_HNUM.
Figure 111 shows the global frame definition for all SDRAM input modes, except for dark frame subtract.
Figure 111. ISS ISP IPIPEIF Global Frame Definition in SDRAM Input Modes (Except Dark Frame)
8 pixels
SDRAM start address
IPIPEIF_ADDRU
IPIPEIF_ADDRL
HD
ADOFS
PPLN
HNUM
1 line
VD
L
P
F
R
Valid data area
1 line
V
N
U
M
Dummy data area
Data not read by BL
Data read by BL
camss-031
310
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
For dark frame data, the HD and VD signals come from the VP through the ISIF. The IPIPEIF_PPLN and
IPIPEIF_LPFR registers must be used to indicate the horizontal and vertical start position of the
subtraction from the ISIF data, as shown in Figure 112. The value of the IPIPEIF_LPFR [12:0] LPFR bit
field must be greater than 0 because the first line from the VP or ISIF cannot be subtracted from. The
IPIPEIF_HNUM and IPIPEIF_VNUM registers must be used to set the number of valid pixels horizontally
and the number of valid lines vertically.
Figure 112. ISS ISP IPIPEIF Global Frame Definition in Dark Frame Subtract Mode
HD from ISIF
PPLN
HNUM
LPFR
VD from ISIF
V
N
U
M
Valid data area
Data read by BL
Dummy data area
Data not read by BL
camss-034
3.3.2.3.2.1 ISS ISP IPIPEIF Double-Buffer Input Function When Reading From BL
The IPIPEIF module supports a double-buffer input function. This feature is most useful when SDRAM
space is limited, because it enables to read continuously from two buffers and to push data to the rest of
the ISP (ISIF, H3A, etc.) for further processing.
Consider the following configuration where data are read from two buffers, A and B. The intent is not only
to read continuously from these buffers but also to ensure that the ISP modules consider the data as
being from the same frame; that is, VD is generated the first time buffer A is read, but it must not toggle
until all the frames are read.
The IPIPEIF module can mask the VD sync signal by writing the IPIPEIF_ENABLE[1] SYNCOFF bit but
such that the IPIPEIF module drives the data to the ISP modules as if it is a continuous frame data.
In the following example, there are 16 lines per trigger and input circular addressing. VNUM = 16 (see
Figure 111), and the VD signal is generated only for the first frame (see Figure 113).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
311
ISS ISP
www.ti.com
Figure 113. ISS ISP IPIPEIF Double-Buffer Functionality
Buffer A
16 line
DMA
IPIPEIF
Buffer B
16 line
VD
HD
IPIPEIF out
16
1
HOST
16
2
16
3
1
- Set buffer A
- IPIPEIF_ENABLE[1] SYNCOFF = 0x0
- IPIPEIF_ENABLE[0] ENABLE = 0x1
2
- Set buffer B
- IPIPEIF_ENABLE[1] SYNCOFF = 0x1
- IPIPEIF_ENABLE[0] ENABLE = 0x1
3
- Set buffer A
- IPIPEIF_ENABLE[1] SYNCOFF = 0x1
- IPIPEIF_ENABLE[0] ENABLE = 0x1
4
- Set buffer B
- IPIPEIF_ENABLE[1] SYNCOFF = 0x1
- IPIPEIF_ENABLE[0] ENABLE = 0x1
16
4
camss-615
3.3.2.4
ISS ISP IPIPEIF Data Path Selection
The data path configuration through the IPIPEIF module is set with the IPIPEIF_CFG1[15:14] INPSRC1
and IPIPEIF_CFG1[3:2] INPSRC2 bit fields. Table 169 lists the possible combinations for these two bit
fields.
Table 169. ISS ISP IPIPEIF IPIPEIF_CFG1[15:14] INPSRC1 and IPIPEIF_CFG1[3:2] INPSRC2
Possible Combinations
312
IPIPEIF_CFG1[15:1 IPIPEIF_CFG1[3:2]
4] INPSRC1
INPSRC2
Description
Common Use
0
0
This data path is described in
Section 3.3.2.4.1, ISS ISP IPIPEIF
INPSRC1 = 0 and INPSRC2 = 0 .
Video record, view finder, on-the-fly still
image capture applications
0
1
This data path is described in
Section 3.3.2.4.2, ISS ISP IPIPEIF
INPSRC1 = 0 and INPSRC2 = 1.
Memory-to IPIPE-to memory
0
2
This data path is described in
Section 3.3.2.4.3, ISS ISP IPIPEIF
INPSRC1 = 0 and INPSRC2 = 2.
Image capture with on-the-fly dark frame
subtraction
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 169. ISS ISP IPIPEIF IPIPEIF_CFG1[15:14] INPSRC1 and IPIPEIF_CFG1[3:2] INPSRC2
Possible Combinations (continued)
IPIPEIF_CFG1[15:1 IPIPEIF_CFG1[3:2]
4] INPSRC1
INPSRC2
Description
Common Use
0
3
This data path is described in
Section 3.3.2.4.4, ISS ISP IPIPEIF
INPSRC1 = 0 and INPSRC2 = 3.
On-the-fly data acquisition done in VP,
forwarded to the ISIF, and then to the
H3A through IPIPEIF while data from
memory is processed and forwarded to
the IPIPE module and then stored in
memory
YUV4:2:2 or RAW data processing with
the IPIPE and RESIZER modules from
memory to memory fetched by IPIPEIF
1
0
This data path is described in
Section 3.3.2.4.5, ISS ISP IPIPEIF
INPSRC1 = 1 and INPSRC2 = 0.
Memory-to-ISIF- to memory operation
1
1
This data path is possible but there is no
use case associated.
N/A
1
2
This data path is not supported.
N/A
1
3
This data path is not supported.
N/A
2
0
This data path is described in
Section 3.3.2.4.6, ISS ISP IPIPEIF
INPSRC1 = 2 and INPSRC2 = 0.
Dark frame subtraction is performed and
data sent to the ISIF module for further
processing, back to IPIPEIF, and then to
IPIPE and RSZ.
2
1
This data path is not supported.
N/A
2
2
This data path is not supported.
N/A
2
3
This data path is not supported.
N/A
3
0
This data path is described in
Section 3.3.2.4.7, ISS ISP IPIPEIF
INPSRC1 = 3 and INPSRC2 = 0.
Memory-to-ISIF-to memory operation
3
1
This data path is not supported.
N/A
3
2
This data path is not supported.
N/A
3
3
This data path is possible but there is no
use case associated.
N/A
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
313
ISS ISP
www.ti.com
3.3.2.4.1
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0
Set the IPIPEIF_CFG1[15:14] INPSRC1 bit field to 0 and the IPIPEIF_CFG1[3:2] INPSRC2 bit field to 0.
This configuration can be used for the video record, viewfinder, and on-the-fly still image capture
applications. The full ISP processing capability is used in a single pass.
Figure 114 shows the data path.
Figure 114. ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0 Data Path
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
Read
buffer
interface
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
RSZ
A
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-603
314
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.4.2
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1
Set the IPIPEIF_CFG1[15:14] INPSRC1 bit field to 0 and the IPIPEIF_CFG1[3:2] INPSRC2 bit field to 1.
This configuration can be used to process data with the IPIPE module from memory to memory. The data
stored in SDRAM can be decompressed (A-law or DPCM) before being forwarded to the IPIPE module.
NOTE: In this configuration, the ISIF and H3A modules are assumed to be disabled.
Figure 115 shows the data path.
Figure 115. ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1 Data Path
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
Read
buffer
interface
RSZ
A
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
Horizontal
pixel
decimator
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-604
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
315
ISS ISP
www.ti.com
3.3.2.4.3
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2
Set IPIPEIF_CFG1[15:14] INPSRC1 to 0 and IPIPEIF_CFG1[3:2] INPSRC2 to 2.
This configuration can be used for image capture with on-the-fly dark-frame subtraction. In the first case,
the dark frame can come from BL and data from the ISIF. In the second case, the dark frame can come
from the VP and data from BL.
Figure 116 shows the data path.
Figure 116. ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2 Data Paths
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
Read
buffer
interface
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
RSZ
A
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-610
316
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.4.4
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3
Set the IPIPEIF_CFG1[15:14] INPSRC1 bit field to 0 and the IPIPEIF_CFG1[3:2] INPSRC2 bit field to 3.
In the first case, on-the-fly data acquisition is done with the VP, forwarded to the ISIF, and then sent to the
H3A through the IPIPEIF while data from memory is processed and forwarded to the IPIPE module and
then stored in memory.
In the second case, the configuration can be used to process YUV4:2:2 or RAW data with the IPIPE and
RESIZER modules from memory-to-memory. The YUV4:2:2 or RAW data stored in the SDRAM is fetched
and forwarded to the IPIPE and RSZ modules. ISIF and H3A are assumed to be disabled in this
configuration.
Figure 117 and Figure 118 show the two possible data paths.
Figure 117. ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3 Data Paths: First Case
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
Read
buffer
interface
RSZ
A
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
Horizontal
pixel
decimator
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-606
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
317
ISS ISP
www.ti.com
Figure 118. ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3 Data Paths: Second Case
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
Read
buffer
interface
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
RSZ
A
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-605
318
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.4.5
ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0
Set the IPIPEIF_CFG1[15:14] INPSRC1 bit field to 1 and the IPIPEIF_CFG1[3:2] INPSRC2 bit field to 0.
This configuration is a memory-to-memory operation. RAW data is read by the BL interface,
decompressed, and pushed to the ISIF. The ISIF processes the data and sends it back to the IPIPEIF
module before the data is pushed to the IPIPE and H3A modules.
Figure 119 shows the data path.
Figure 119. ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0 Data Path
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
Read
buffer
interface
RSZ
A
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
Horizontal
pixel
decimator
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-607
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
319
ISS ISP
www.ti.com
3.3.2.4.6
ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0
Set the IPIPEIF_CFG1[15:14] INPSRC1 bit field to 2 and the IPIPEIF_CFG1[3:2] INPSRC2 bit field to 0.
In this configuration, dark frame subtraction is performed and data is sent to the ISIF module. The ISIF
processes the data and sends it back to the IPIPEIF module before the data is pushed to the IPIPE or
RSZ modules. There are two possible dark frame subtractions: the first is with data coming from the VP
and the dark frame coming from BL; the second is with data coming from BL and the dark frame coming
from the VP.
Figure 120 shows the data path.
Figure 120. ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0 Data Path
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
Read
buffer
interface
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
RSZ
A
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-608
320
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.4.7
ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0
Set the IPIPEIF_CFG1[15:14] INPSRC1 bit field to 3 and the IPIPEIF_CFG1[3:2] INPSRC2 bit field to 0.
This configuration is a memory-to-memory operation. Data is loaded from the SDRAM. Input data is
expected as 16 bpp. The ISIF processes the data and sends it back to the IPIPEIF module before the data
is pushed to the IPIPE or RSZ module.
In this configuration data is assumed to be YUV only, and H3A and RAW data gain are assumed to be
disabled.
Figure 121 shows the data path.
Figure 121. ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0 Data Path
IPIPEIF_CFG1[15:14] INPSRC1
Video port
16 bits
0
2
D
E
16 bits
ISIF
1
C
Dark
frame
subtraction
F
3
B
16 bits
Buffer logic
32 bits
DCPM
IPIPEIF_CFG1[3:2] INPSRC2
Read
buffer
interface
RSZ
A
3
1
32-bit RAW/YCbCr data
2
16 bits
(1,2,1)
Averaging
filter
RAW
data gain
and clip
else
16 bits
IPIPE
3
IPIPEIF_CFG1[3:2] INPSRC2
0
10 bits
Horizontal
pixel
decimator
(1,2,1)
Averaging
filter
Horizontal
pixel
decimator
10 bits
H3A
Timing generator
camss-609
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
321
ISS ISP
3.3.2.5
www.ti.com
ISS ISP IPIPEIF Timing Generation
Figure 122 shows the ISS ISP IPIPEIF timing generator submodule.
Figure 122. ISS ISP IPIPEIF Timing Generator Submodule
Timing generator
SYNC
generator
1
3
HD/VD/WEN
from video port
0
2
HD/VD/WEN
to ISIF
1
3
HD/VD/WEN
from ISIF
IPIPEIF_CFG1[15:14] INPSRC1
0
2
HD/VD/WEN
to IPIPE
IPIPEIF_CFG1[3:2] INPSRC2
camss-602
When the IPIPEIF module input source is from the VP (IPIPEIF_CFG1[15:14] INPSRC1 = 0 or 2) or the
ISIF (IPIPEIF_CFG1[3:2] INPSRC2 = 0 or 2) , the IPIPEIF_CFG1[10] CLKSEL bit must be set to 0 so that
data is latched using the PCLK, HD, and VD signals from the VP.
When the IPIPEIF module input source is not from the VP (IPIPEIF_CFG1[15:14] INPSRC1 = 1 or 3), the
IPIPEIF_CFG1[10] CLKSEL bit must be set to 1 so that the IPIPEIF module generates its proper PCLK,
HD, and VD signals (through the use of the SYNC generator). The IPIPEIF_CLKDIV register is then used
to select a divide ratio of the SDRAM (DMA) clock for the pixel clock frequency, which is used to clock the
data into the PCLK. See Section 3.3.2.5.1, ISS ISP IPIPEIF Fractional Clock Divider.
When the IPIPEIF_CFG1[15:14] INPSRC1 or IPIPEIF_CFG1[3:2] INPSRC2 bit field is not set to 0, the
IPIPEIF SDRAM data reading and timing generation can be enabled (IPIPEIF_ENABLE[0] ENABLE) in
one-shot mode or continuous mode (IPIPEIF_CFG1[0] ONESHOT).
3.3.2.5.1
ISS ISP IPIPEIF Fractional Clock Divider
When the input data of the IPIPEIF module does not come from the VP but from memory, it is useful to
have control of the rate at which the data is fetched from memory to avoid overflow conditions or to avoid
peak bandwidth requirements. The IPIPEIF_CFG1[10] CLKSEL bit is equal to 1 for fractional divider use.
The ISP clock ISS_FCLK is divided to generate the pixel clock, which goes to the ISIF and IPIPE modules
when data is read from memory (IPIPEIF_CFG1[15:14] INPSRC1 = IPIPEIF_CFG1[3:2] INPSRC2 = 1 or
3). The IPIPEIF_CLKDIV register selects the divider ratio: M and N values in the IPIPEIF_CLKDIV[15:0]
CLKDIV bit field.
Given an input clock of clock rate ISS_FCLK, the fractional clock divider generates an output clock with
average clock rate f_out.
Where f_out = ISS_FCLK x M/N, and M = 1 through 256, and N = 1 through 256.
The fractional clock divider logic is synchronous and uses only the positive clock edge of the input clock.
322
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.6
ISS ISP IPIPEIF Decompression (DCPM) Subblock: Unpack and Decompression Function
The IPIPEIF module can read RAW data from memory. The RAW data can be previously
packed/compressed into memory. Unpack, A-Law decompression, and DPCM decompression are
available in the IPIPEIF module.
Figure 123 shows the DCPM subblock.
Figure 123. ISS ISP IPIPEIF DCPM Subblock
DCPM block
IPIPEIF_DPCM[2] BITS
IPIPEIF_CFG1[15:14] INPSRC1
IPIPEIF_CFG1[3:2] INPSRC2
8 bits
8 bits
DPCM
decomp
10 bits
Inverse
A-law
10 bits
12 bits
Data
shift
<<n
12 bits
B
1
2
16 bits
8,12,16 bits
IPIPEIF_CFG1[13:11] DATASFT
from buffer logic (BL)
A
3
16 bits
16 bits
camss-032
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
323
ISS ISP
www.ti.com
Table 170 provides the possible configuration of the DCPM block.
Table 170. ISS ISP IPIPEIF DCPM Block Possible Configuration
Number of Bits per
Pixel at DCPM
Block Input
Number of Bits per
Pixel at DCPM
Block Output
Description
Registers
16
16
It can correspond to YUV4:2:2 or RAW16
data.
IPIPEIF_CFG1[9:8] UNPACK = 0x0
In this configuration, IPIPEIF_CFG1[3:2]
INPSRC2 = 0x3. In this configuration data
bypasses the DCPM block.
8
8
PACK8:
YUV
IPIPEIF_CFG1[9:8] UNPACK = 0x1
IPIPEIF_DPCM[0] ENA = 0x0
IPIPEIF_CFG1[13:11] DATASFT = 0x01.
In this configuration an 8-bit packed RAW
data is used in DFS mode or YUV4:2:0
pass through. (See Section 3.3.2.13, ISS
ISP IPIPEIF YUV4:2:2 8-bits Packed Data
Input Coming From ISIF Module.)
8
10
DPCM10:
The 8-bit input data are DPCMdecompressed in 10 bits.
IPIPEIF_CFG1[9:8] UNPACK = 0x1
IPIPEIF_DPCM[0] ENA = 0x1
IPIPEIF_DPCM[2] BITS= 0x0
Set the IPIPEIF_DPCM[1] PRED (1) (2)
IPIPEIF_CFG1[13:11] DATASFT = 0x2
8
12
DPCM12:
The 8-bit input data are DPCMdecompressed in 12 bits.
IPIPEIF_CFG1[9:8] UNPACK = 0x1
IPIPEIF_DPCM[0] ENA = 0x1
IPIPEIF_DPCM[2] = 0x1
Set the IPIPEIF_DPCM[1] PRED (1) (2)
IPIPEIF_CFG1[13:11] DATASFT = 0x0
8
10
ALAW10:
IPIPEIF_CFG1[9:8] UNPACK = 0x2
The 8-bit input data were previously A-law IPIPEIF_CFG1[13:11] DATASFT = 0x2
compressed.
The 8 bits are A-law decompressed and
padded with 0.
12
12
PACK12:
IPIPEIF_CFG1[9:8] UNPACK = 0x3
The input is coded on 12 bits and is
Set the IPIPEIF_CFG1[13:11] DATASFT
packed in the SDRAM.
This mode is compatible with the ISIF
module packing capability.
If inverse A-law and DPCM
decompression are not enabled, the data
read from the SDRAM can be shifted by
the IPIPEIF_CFG1[13:11] DATASFT bit
field to select which 12 bits to use.
MSB input data bit must be shifted such
that it corresponds to bit 11 after the shift.
(1)
(2)
324
The simple predictor uses only the value of the previous same color component as a prediction value. Therefore, only 2-pixel
memory is required. It is typically used for 10–8–10 or 12–8–12 bit conversions.
The advanced predictor uses four previous pixel values, when the prediction value is evaluated. This means that the values of
the other color components are also used, when the prediction value is defined. Therefore, the advanced predictor is slightly
better than the simple predictor but consumes more power and memory. It can, however, improve image quality. It is typically
used for 10–7–10 and 10–6–10 bit conversions.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.7
ISS ISP IPIPEIF Dark-Frame Subtraction Functionality
Figure 124. ISS ISP IPIPEIF Dark-Frame Subtraction Subblock
IPIPEIF_CFG2[5] DFSDIR
Video port (VP)
C
ISIF
Defect pixel
correction
DPC1
0
clip
F
D
1
1
Buffer logic (BL)
from SDRAM
E
Defect pixel
correction
DPC2
0
camss-033
The dark-frame subtract function is used to remove noise from the sensor. Typically, the ISIF module
previously writes a dark frame (frame captured when the shutter is closed) to SDRAM using 8 bits of linear
data packed into 2 pixels per 16 bits.
In this mode, RAW data from the ISIF and SDRAM is used. Data can also be read from SDRAM with the
IPIPEIF_CFG1[9:8] UNPACK bit field set to 1. Each pixel read from SDRAM is subtracted from each pixel
sent from the VP or ISIF.
The mux at the input of the dark-frame subtraction subblock is implicitly controlled by the selection of the
IPIPEIF_CFG1[15:14] INPSRC1 and IPIPEIF_CFG1[3:2] INPSRC2 bit fields:
• When IPIPEIF_CFG1[15:14] INPSRC1 = 0x2, the selected input ports are VP and BL. Therefore, the
dark frame operation can be:
– Dark frame = VP – BL
– Dark frame = BL – VP
• When IPIPEIF_CFG1[3:2] INPSRC2 = 0x2, the selected input ports are ISIF and BL. Therefore, the
dark frame operation can be:
– Dark frame = ISIF – BL
– Dark frame = BL – ISIF
The output of the dark frame subtract operation is 12-bits wide (U12Q0). There must be adequate SDRAM
bandwidth if this feature is enabled. If the data fetched from memory arrives late, an underflow bit
(IPIPEIF_DTUF) must be triggered to know it .
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
325
ISS ISP
www.ti.com
3.3.2.7.1
ISS ISP IPIPEIF Defect Pixel Correction
NOTE: For DPC memory access locations, see Section 3.3.8.
A simple DPC can be applied to the ISIF or VP input data path and SDRAM input data path, respectively.
This DPC algorithm is intended to correct hot pixels during RAW dark frame acquisition or dark frame
readout from SDRAM before dark frame subtraction.
The following code describes DPC algorithm:
If (image(n) TH) || ((image(2) TH) (image(n+2) TH)
image(n) = image(n)
Else if image(2) TH
image(n) = image(n+2)
Else if image(n+2) TH
image(n) = image(2)
Else
image(n) = (image(2)+ image(n+2))/2
// Where TH is equal to IPIPEIF_DPC1[11:0] TH for DPC1
// Where TH is equal to IPIPEIF_DPC2[11:0] TH for DPC2
The IPIPEIF_DPC1[12] ENA bit enables DPC for the VP/ISIF input path, and the IPIPEIF_DPC2[12] ENA
bit enables DPC for the SDRAM input path. The algorithm requires a threshold value that is set by the
IPIPEIF_DPC1[11:0] TH or IPIPEIF_DPC2[11:0] TH bit field that is a 12-bit unsigned value.
3.3.2.7.2
ISS ISP IPIPEIF DFS Subtraction Direction
The IPIPEIF_CFG2[5] DFSDIR bit selects how the DFS subtraction is performed.
• Set theIPIPEIF_CFG2[5] DFSDIR bit to 0 when the RAW data is coming from the VP/ISIF and the dark
frame is stored in SDRAM.
• Set the IPIPEIF_CFG2[5] DFSDIR bit to 1 when the RAW data is coming from SDRAM and the dark
frame is coming from the VP/ISIF.
After subtraction, a clip ensures that the value is not negative.
Table 171 lists the different modes supported in DFS.
Table 171. ISS ISP IPIPEIF DFS Modes Supported
Description
DFDIR Value
Dark frame subtract of 8-bit RAW image stored in SDRAM from
image from VP
IPIPEIF_CFG2[5] DFSDIR = 0x0
Dark frame subtract of 8-bit RAW image stored in SDRAM from
image from ISIF
IPIPEIF_CFG2[5] DFSDIR = 0x0
Dark frame subtract of 8-bit RAW image from VP from image
read from SDRAM through the BL
IPIPEIF_CFG2[5] DFSDIR = 0x1
NOTE: DFS input depends on the INPSRC1 and INPSRC2 settings.
326
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.8
ISS ISP IPIPEIF (1, 2, 1) Averaging Filter for IPIPE Data Path
The averaging filter acts as an anti-aliasing low-pass filter for the horizontal pixel decimator. Usually, when
horizontal pixel decimation is enabled (IPIPEIF_CFG1[1] DECIM), the averaging filter must also be
enabled to avoid aliasing artifacts. The averaging filter can be enabled by setting the IPIPEIF_CFG1[7]
AVGFILT bit. It operates on every other pixel (same color) in RAW Bayer input or every Y component in
YCbCr data in the following equation:
output = (input[i – 1] + 2 * input[i] + input[i + 1]) >>2
The averaging filter operates on every other pixel (same color) in RAW Bayer input or YUV data.
If the data is YUV4:2:2, the option to average and decimate is given under the conditions listed in
Table 172.
Table 172. ISS ISP IPIPEIF Averaging Filter Conditions for YUV4:2:2 Data
IPIPEIF_CFG1[3:2] INPSRC2
IPIPEIF_CFG2[3] YUV16
0
1
YUV4:2:2 data is coming from the ISIF
module.
Averager and decimation is possible on
the data path to the IPIPE module.
1
1
YUV4:2:2 data is read from SDRAM.
Averager and decimation is possible on
the data path to the IPIPE module.
3
Comments
YUV4:2:2 data is read from SDRAM.
Averager and decimation is possible on
the data path to the IPIPE module.
Other value
Other value
For YUV4:2:2 data, averager and
decimation is not possible on the data
path to the IPIPE module.
The averager implements a (1, 2, 1) FIR filter on Luma and Chroma. The following registers have a part in
the behavior of the YUV data averaging and decimation:
• IPIPEIF_INIRSZ[12:0] INIRSZ
• IPIPEIF_CFG1[7] AVGFILT
• IPIPEIF_CFG1[1] DECIM
3.3.2.9
ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for IPIPE Data Path
The IPIPE input is limited to 5376 pixels per horizontal line due to restrictions in the line memory width in
the IPIPE.
To process image sensor resolutions with more than 5376 pixels per line with no resolution loss, vertical
frame division mode (FDM) must be used; that is, the image must be divided into vertical chunks of less
than 5376 pixels, and each chunk must be processed sequentially by the ISP. FDM is memory-to-memory
processing and is not supported on the fly.
Alternatively, if a loss in resolution is acceptable, the line width decimator (the IPIPEIF_CFG1[1] DECIM
bit) can be enabled to downsample the input lines to a width equal to or less than the 5376 pixel
maximum. The resize ratio (16/RSZ) can be configured by programming the IPIPEIF_RSZ[6:0] RSZ bit
field to be within the range from 16 to 112 to give a resampling range from 1x to 1/7x.
When ALNSYNC is enabled (IPIPEIF_INIRSZ[13] ALNSYNC = 0x1), the IPIPEIF_INIRSZ[12:0] INIRSZ
pixels are skipped (from the HD position) before the horizontal pixel decimator, as shown in Figure 125.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
327
ISS ISP
www.ti.com
Figure 125. ISS ISP IPIPEIF Resizer Offset Definition
Before horizontal pixel decimator
VD
HD
Input DATA
IPIPEIF_INIRSZ[12:0] INIRSZ
After horizontal pixel decimator
VD
HD
Output DATA
camss-614
3.3.2.10
ISS ISP IPIPEIF RAW Data Gain for IPIPE Data Path
A gain factor ranging from 0.00195(1/512) to 1.99805(1023/512) is multiplied to the RAW output of the
IPIPEIF. The gain is not applied if the input data is YCbCr. The gain constant is set in the
IPIPEIF_GAIN[9:0] GAIN bit field using U10Q9 format.
The output value is clipped after gain control through the value of the IPIPEIF_OCLIP[11:0] OCLIP bit
field.
3.3.2.11
ISS ISP IPIPEIF (1, 2 ,1) Averaging Filter for H3A Data Path
The averaging filter acts as an anti-aliasing low-pass filter for the horizontal pixel decimator. Usually, when
horizontal pixel decimation is enabled (the IPIPEIF_RSZ3A[9] DECIM bit), the averaging filter must also
be enabled to avoid aliasing artifacts. The averaging filter can also be used to reduce noise before H3A
statistics generation. It operates on every other pixel (the same color) in a RAW Bayer input or every Y
component in YCbCr data. The averaging filter can be enabled by setting the IPIPEIF_RSZ3A[8] AVGFILT
bit, and it operates with the following equation:
output = (input[i – 1] + 2 * input[i] + input[i + 1]) >>2
3.3.2.12
ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for H3A Data Path
The H3A input is limited to 3008 pixels per horizontal line due to restrictions in the line memory width in
the H3A.
To process image-sensor resolutions with more than 3008 pixels per line with no resolution loss, vertical
frame division mode (FDM must be used); that is, the image must be divided into vertical chunks of less
than 3008 pixels, and each chunk must be processed sequentially by the ISP. FDM is memory-to-memory
processing and is not supported on the fly.
Alternatively, if loss of resolution is acceptable, the line width decimator (the IPIPEIF_RSZ3A[9] DECIM
bit) can be enabled to downsample the input lines to a width equal to or less than the 3008 pixel
maximum. The resize ratio (16/RSZ) can be configured by programming the IPIPEIF_RSZ3A[6:0] RSZ bit
field to be within the range from 16 to 112 to give a resampling range from 1x to 1/7x.
When ALNSYNC is enabled (IPIPEIF_INIRSZ3A[13] ALNSYNC = 0x1), the IPIPEIF_INIRSZ3A[12:0]
INIRSZ pixels are skipped (from the HD position) before the horizontal pixel decimator (see Figure 125).
328
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.2.13
ISS ISP IPIPEIF YUV4:2:2 8-bits Packed Data Input Coming From ISIF Module
This section applies when data coming from the ISIF is 8 bits (IPIPEIF_CFG2[6] YUV8 = 0x1). When
IPIPEIF_CFG1[3:2] INPSRC2 = 0 and IPIPEIF_CFG2[3] YUV16 = 1, the 8-bit YUV data are transformed
into 16-bit YUV data. The way the data are unpacked from 8 bits to 16 bits is controlled by the
IPIPEIF_CFG2[7] YUV8P bit. See Figure 126.
Figure 126. ISS ISP IPIPEIF YUV8P Settings
Y0 Y1 Y2
Cb0 Cr0 Cb2
Pix0 Pix1 Pix2 Pix3 ...
...
...
...
...
...
Packed pixels
Pixel 0 (even)
Pixel 1 (odd)
Y17
...
Y10
Cr07
...
Cr00
Y07
...
Y00
Cb07
...
Cb00
...
Y00
...
Y10
...
Cb00
...
Cr00
Consecutive 16 bits
Unpacked pixels when YUV8P = 0x1
Pixel 0 (even)
Pixel 1 (odd)
0
...
0
Cb07
...
Cb00
0
...
...
0
Cr07
Y07
Pixel2 (even)
Pixel 3 (odd)
0
0
...
Cr00
0
...
0
Y17
Unpacked pixels when YUV8P = 0x0
Pixel 0 (even)
Pixel 1 (odd)
0
...
0
Y07
...
Y00
0
...
...
0
Y17
Cb07
Pixel 2 (even)
Pixel 3 (odd)
0
0
...
Y10
0
...
0
Cr07
camss-616
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
329
ISS ISP
3.3.2.14
www.ti.com
ISS ISP IPIPEIF YUV4:2:0 Data Input for Memory-to-Memory Resize Operations
The ISP RSZ module can resize YUV4:2:0 data. The YUV4:2:0 data can come from the memory (through
BL) or from the VP through the SC module, which reads data from SDRAM and pushes it to the IPIPEIF
module VP. The possible data paths are:
• SDRAM - IPIPEIF (BL) - RESIZER - SDRAM
• SDRAM - SC - IPIPEIF (VP) - RESIZER - SDRAM
• SDRAM - IPIPEIF (BL) - IPIPE - RESIZER - SDRAM
• SDRAM - SC - IPIPEIF (BL) - IPIPE - RESIZER - SDRAM
When the data comes from BL, the IPIPEIF module must be set up to process the luminance data first,
and then the chrominance data.
• For 420Y (first pass):
– IPIPEIF_CFG1[15:14] INPSRC1 = 0x1 (SDRAM data input)
– IPIPEIF_CFG1[3:2] INPSRC2 = 0x1 (SDRAM data input)
– IPIPEIF_CFG1[13:11] DATASFT = 0x0 (no data shift)
– IPIPEIF_CFG1[9:8] UNPACK = 0x1 (data packed on 8 bits)
– IPIPEIF_CFG2[3] YUV16 = 0x1 (data_input [7:0] = 0 and data_input [15:8] = valid)
• For 420C (second pass):
– IPIPEIF_CFG1[15:14] INPSRC1 = 0x1 (SDRAM data input)
– IPIPEIF_CFG1[3:2] INPSRC2 = 0x1 (SDRAM data input)
– IPIPEIF_CFG1[13:11] DATASFT = 0x0 (no data shift)
– IPIPEIF_CFG1[9:8] UNPACK = 0x1 (data packed on 8 bits)
– IPIPEIF_CFG2[3] YUV16 = 0x0 (data_input[7:0] = valid and data_input [15:8] = 0)
3.3.2.15
ISS ISP IPIPEIF Module Events and Status Checking
The IPIPEIF module generates an IPIPEIF event through the IPIPEIF_IRQ interrupt at the end of each
frame. This interrupt is set through the ISP5_IRQENABLE_SET_i[9] IPIPEIF_IRQ bit. The input interrupt
source generation is selected through the IPIPEIF_CFG2[0] INTSW bit in a certain configuration. The
following pseudo code describes INTSW.
if (IPIPEIF_CFG2[0] INTSW==0) // Interrupt source from VP
if (IPIPEIF_CFG1[15:14] INPSRC1==1,2 or 3)
if (CFG1.ONESHOT==1) // In one shot mode
Interrupt happens at the end of frame
else // In continuous mode
Interrupt is the start position of VD which is generated by IPIPEIF timing generator
else // IPIPEIF_CFG1[15:14] INPSRC1==0, data is from VP
Interrupt is the start position of VD from VP
else // Interrupt source from ISIF: IPIPEIF_CFG2[0] INTSW==1
if (IPIPEIF_CFG1[3:2] INPSRC2==1,2 or 3)
if (CFG1.ONESHOT==1) // In one shot mode
Interrupt happens at the end of frame
else
Interrupt is the start position of VD which is generated by IPIPEIF timing generator
else // IPIPEIF_CFG1[3:2] INPSRC2==0, data is from ISIF
Interrupt is the start position of VD from ISIF
In addition to this interrupt, the host must check the IPIPEIF_DTUF status flag of the
ISP5_IRQSTATUS_RAW2_i[1] IPIPEIF_UDF bit (if this is enabled and mapped to the ISP IRQ lines) to
see if an underflow occurred. For more information, see Section 3.4.2.4.
330
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3
ISS ISP IPIPE Functional Description
3.3.3.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ISS ISP IPIPE Overview
The input interface extracts the valid region from the Bayer RAW data:
– Up to 12-bit input pixel resolution
– Requires at least 8 pixels for horizontal blanking and four lines for vertical blanking. In one-shot
mode, 16 blanking lines after processing area are required.
– The maximum horizontal and vertical offset of IPIPE processing area from synchronous signal is
65534.
– Supports RGB Bayer pattern for input
The DPC module fixes defect pixels using two methods: LUT-based and on-the-fly adaptive.
The 2D noise-filter module reduces noise in RAW data.
The green-imbalance-correction (GIC) module reduces Gb/Gr difference to remove line crawl noise.
The white balance module applies offset and gain adjustments to each color.
The color filter array (CFA) interpolation module implements CFA interpolation. The output from the
CFA interpolation module is RGB-4:4:4 formatted data. CFA also reduces aliasing caused by
undersampling by digital anti-aliasing (DAA).
The RGB2RGB blending module applies a 3 × 3 matrix transform to the RGB data generated by the
CFA interpolation module.
The gamma correction module independently applies gamma correction to each RGB component.
Gamma is implemented using a piece-wise linear interpolation approach with a 512-entry LUT for each
color.
The 2nd RGB2RGB blending module applies a 3 × 3 matrix transform to the RGB data after gamma
correction.
3D-LUT converts RGB data to RGB data using 9 × 9 × 9 table and tetrahedral interpolation.
The RGB2YCbCr conversion module applies 3 × 3 matrix transformation to the RGB data to convert it
to YCbCr data. This module also implements offset. The global brightness and contrast enhancement
module fixes brightness and contrast tone.
The 4:2:2 conversion module applies the chroma low pass filter and downsampling to Cb and Cr to
convert 4:4:4 data to 4:2:2 data.
The 2D edge-enhancer module improves image clarity with a luminance nonlinear filter.
The chroma artifact reduction module reduces color artifacts using gain control and a 2D median filter.
The output interface module transfers data from IPIPE to SDRAM in the form of one YCbCr (4:2:2 or
4:2:0), RGB (32/16 bits), or Bayer data.
The histogram function can record histograms of up to four distinct areas into up to 256 bins.
The boxcar function makes 1/8 or 1/16 size (1/64 or 1/256 in area) images.
The boundary signal calculator (BSC) makes vectors of row and column summations.
IPIPE has four different processing paths:
• Case 1: IPIPE reads BAYER RAW data and applies all IPIPE functions and stores the YCbCr (or RGB)
data to SDRAM.
• Case 2: IPIPE reads BAYER RAW data and stores the Bayer data after white balance to SDRAM.
• Case 3: IPIPE reads YCbCr-4:2:2 data and applies edge enhance, chroma suppression, and resize to
output YCbCr data to SDRAM.
• Case 4: IPIPE reads YCbCr-4:2:0 data and applies resize to output YCbCr data to SDRAM.
Figure 127 shows the connections from the IPIPE module to other submodules of the ISP.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
331
ISS ISP
www.ti.com
Figure 127. ISS ISP IPIPE High-Level Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
camss-003d
332
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.2
ISS ISP IPIPE Top-Level Block Diagram
The IPIPE is a programmable hardware image-processing module that generates image data in YCbCr4:2:2 or YCbCr-4:2:0 format from RAW CCD/CMOS data. The IPIPE module supports output of Bayer
data.
The IPIPE module supports RAW data in Bayer format, as shown in Figure 128. Other RGB formats or
complimentary color formats are not supported.
Figure 128. ISS ISP IPIPE Supported CFA Format
G
B
R
G
G
B
Ye
Cy
Ye
Cy
G
R
Gr
Mg
Gr
Ye
Supported
R
G
B
Not supported
camss-142
As shown in Figure 129, many internal modules are used to process Bayer data into YCbCr data
Figure 129. ISS ISP IPIPE Module Block Diagram
Boxcar
Histogram
5376 x 12 bits
x 4 lines
From
IPIPEIF
Video port
16
Boundary
signal
calculator
RAM 960 x 32 bits x 2
RAM 1024 data x 20 bits
Input
I/F
12
16
Line
memory
LUT DPC
OTF DPC 3.0
2Dn oise
filter-1
u8 x 3
Line
memory
198 x 30 bits x 4
5376 x 12 bits
x 4 lines
YCbCr data
or RAW data
5376 x 6 bits
x 1lines
u10
12 x 3
5 x 5 taps
2D noise
filter2
Buffer logic
5 x 5 taps
512 x 20
RAM:512 x 20 x 3
Line
memory
128 x 29 bits x 2
Green
imbalance
correction
White
balance
5 x 5 taps
Line
memory
12 x 3
5376 x 12 bits
x 5 lines
Line
memory
RAW data
RGB
color
correction
CFAI 2.0
RGB2RGB blending
5376 x 12 bits
x 2 lines
Gamma
Gamma
RGB
to
RGB
3D
LUT
RGB
to
YCbCr
u8
GBCE
Gamma
u8
10 x 3
10 x 3 10 x 3
16
4:4:4
to
4:2:2
24
RAM:512 x 18
5 x 5 taps
Y
Y
8
Line
8
memory
Edge
enhancer
Y
RSZ
8
CGS
Cb/Cr
8
8
Cb/Cr
5376 x 8 bits x 4 lines
5376 x 8 bits x 3 lines
(Y8+C8)
Chroma
artifact
reduction
Cb/Cr
Image pipe
camss-141
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
333
ISS ISP
3.3.3.3
www.ti.com
ISS ISP IPIPE Input Interface
The IPIPE module receives 12-bit RAW image data or 16-bit YCbCr data through the IPIPEIF module.
The IPIPE module can work with up to 5376 pixels in each horizontal line, except in RAW pass-through
mode. If the image width is larger than 5376, the image must be scaled down at the IPIPEIF module level.
Otherwise, the input image must be split into several blocks.
If the input data is YCbCr, all RGB processing modules are skipped, and only edge enhancer and chroma
suppression are applied to the input data.
If the input data is YCbCr-4:2:0, only Y or C can be processed at a time, and only the resizer process can
be applied. Because the resizer is outside the ISIF module, the data is passed to it directly by skipping the
RGB and YCbCr processing modules.
In RAW pass-through mode, images up to 8190 pixels per line can be processed. In RAW pass-through
mode, the input data is written out directly to SDRAM.
The IPIPE module is enabled through the IPIPE_SRC_EN[0] EN bit.
The IPIPEIF module must be selected as the IPIPE module source with the IPIPE_SRC_MODE[1] WRT
bit set to 1 from the input port of the IPIPEIF. This is required to enable and transfer data properly from
the interface to the IPIPE.
The IPIPE module has two processing modes, which can be selected through the IPIPE_SRC_MODE[0]
OST bit:
• One-shot mode: IPIPE_SRC_MODE[0] OST = 0x1
• Free-run mode: IPIPE_SRC_MODE[0] OST = 0x0
The input and output formats are selected in the IPIPE_SRC_FMT[1:0] FMT bit field (see Table 173).
Table 173. ISS ISP IPIPE Input and Output Selections
IPIPE_SRC_FMT[1:0] FMT
IPIPE Module Input
IPIPE Module Output
0x0
RAW Bayer
YCbCr or RGB
0x1
RAW Bayer
RAW Bayer
0x2
RAW Bayer
Disabled
0x3
YCbCr 16 bits
YCbCr
The input to the IPIPE module is in the formats (YCbCr-8bit is not allowed) shown in Figure 130.
Figure 130. ISS ISP IPIPE Module Input Format
RAW
IPIPE YCbCr 16b
input Y 8bit
CbCr 8bit
LOW LOW LOW LOW RAW11 RAW10 RAW9 RAW8 RAW7 RAW6 RAW5 RAW4 RAW3 RAW2 RAW1 RAW0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb/Cr7 Cb/Cr6 Cb/Cr5 Cb/Cr4 Cb/Cr3 Cb/Cr2 Cb/Cr1 Cb/Cr0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
LOW LOW
LOW LOW
LOW LOW
LOW LOW
LOW LOW LOW LOW LOW
LOW LOW LOW Cb/Cr7 Cb/Cr6 Cb/Cr5 Cb/Cr4 Cb/Cr3 Cb/Cr2 Cb/Cr1 Cb/Cr0
camss-143
The window to process can be defined by its vertical and horizontal start position (IPIPE_SRC_VPS and
IPIPE_SRC_HPS) and vertical and horizontal size (IPIPE_SRC_VSZ and IPIPE_SRC_HSZ). Figure 131
shows the window settings for processing.
334
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 131. ISS ISP IPIPE Module Processing Window Settings
HD
IPIPE_SRC_HPS[15:0]
VAL
IPIPE_SRC_HSZ[12:0]
VAL
IPIPE_SRC_VPS[15:0]
VAL
IPIPE_SRC_VSZ[12:0]
VAL
IPIPE processing window
VD
Global input frame
camss-639
3.3.3.4
ISS ISP IPIPE Defect Pixel Correction
The DPC module corrects defect pixels using two methods: look-up-table-based method (LUT DPC) and
on-the-fly adaptive method (OTF DPC). Figure 132 shows defect pixel correction.
Figure 132. ISS ISP IPIPE Defect Pixel Correction
From
IPIPEIF
Video port
16
Input
interface
16
12
Line buffer 0
Line buffer 1
LUT
defect
correction
(vertical)
Corrected
pixel
MinMax
defect
correction
Corrected
pixel
Noise
filter-1
2D noise
filter-2
Line buffer 2
Line buffer 3
Defect table
(Position + method)
Defect pixel correction
camss-146
3.3.3.4.1
ISS ISP IPIPE LUT Defect Pixel Correction (LUT DPC)
LUT DPC is the first stage of the IPIPE image-processing pipeline. The LUT DPC module corrects defects
in input data. It supports up to a 256-defect point table. However, the table can be renewed as required
during image processing. Therefore, the maximum amount of defect information is limited only by systemlevel performance.
The module uses two sets of 128 × 29 memories to hold defect information. The table contains the
information of horizontal position (13 bits), vertical position (13 bits), and correction method (3 bits), as
shown in Table 174. The LUT DPC is enabled through the IPIPE_DPC_LUT_EN[0] EN bit.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
335
ISS ISP
www.ti.com
Table 174. ISS ISP IPIPE Defect Information Packing
Correction Method
Vertical Position
Horizontal Position
28…26
25…13
12…0
The information must be listed in the order of "from left to right" and "from the top to bottom." The first
position in the defect information table and the number of defects that are used can be specified. The
address of the table must be programmed in the IPIPE_DPC_LUT_ADR[9:0] ADR bit field. Thus, the
address of the first valid data is stated.
The LUT type can be:
• With a finite number of entries:
– IPIPE_DPC_LUT_SEL[1] TBL = 0x0
– The size of the LUT is set in the IPIPE_DPC_LUT_SIZ[9:0] SIZ bit field.
• With an infinite number of entries:
– IPIPE_DPC_LUT_SEL[1] TBL = 0x1
The correction methods, set in Table 174, are described in Table 175.
Table 175. ISS ISP IPIPE Correction Method Description
Correction Method
d0 =
0
Black or white dot
Comment
1
d4
Copy from left
2
d5
Copy from right
3
(d4 + d5)/2
Horizontal interpolation
4
(d2 + d7)/2
Vertical interpolation
5
d2
Copy from top
6
d7
Copy from bottom
7
(d2 + d4 + d5 + d7)/2
Replace with a black (or white) dot to
force OTF-DPC to work on the pixel.
White or black dot replacement can be
selected through the
IPIPE_DPC_LUT_SEL[0] DOT field.
2D interpolation
The pixels in the defect correction algorithm are numbered as shown in Figure 133.
Figure 133. ISS ISP IPIPE Pixel Numbering in Defect Correction Algorithm
d1
d1
d2
d3
d4
d0
d5
d5
d7
d8
camss-145
The pixels at the edges are mirrored in the way described in Figure 134. The figure shows the typical
correction by overwriting far-edge pixels and mirroring them with other edge pixels. The example shows
how by using a noise filter the correct-by-definition pixels are copied over bad pixels.
336
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 134. ISS ISP IPIPE Mirroring in Defect Correction and Noise Filter
copy
copy
d1
d2
d3
d
d2
d3
d
d2
d3
d4
d0
d5
d
d0
d5
d
d0
d5
d5
d7
d8
d
d7
d8
d
d7
d8
left edge
left edge
(Right, top, and bottom edges have the same process.)
camss-147
3.3.3.4.2
ISS ISP IPIPE OTF Defect Pixel Correction (OTF DPC)
OTF DPC is enabled through the IPIPE_DPC_OTF_EN[0] EN bit.
In OTF DPC correction, each pixel is compared with the surrounding 8 pixels in the same color plane. The
defect pixel is detected and modified using one of the three correction methods:
• Adaptive OTF DPC method 1: IPIPE_DPC_OTF_TYP[1] TYP = 0x0 and IPIPE_DPC_OTF_TYP[0]
ALG = 0x0
• Adaptive OTF DPC method 2: IPIPE_DPC_OTF_TYP[1] TYP = 0x1 and IPIPE_DPC_OTF_TYP[0]
ALG = 0x0
• Adaptive OTF DPC method 3: IPIPE_DPC_OTF_TYP[1] TYP = 0x1 and IPIPE_DPC_OTF_TYP[0]
ALG = 0x1
3.3.3.4.2.1 ISS ISP IPIPE Adaptive OTF DPC Method 1
In adaptive OTF DPC method 1, if the center pixel d0 is larger than the maximum among them, the output
is the second largest value. If the center pixel d0 is the minimum, it is replaced by the second smallest
value. If the center pixel is not the maximum or minimum, it is the output.
The parameters for the different thresholds shall be set as below:
• IPIPE_DPC_OTF_2_D_THR_R[11:0] VAL = 0
• IPIPE_DPC_OTF_2_D_THR_GR[11:0] VAL = 0
• IPIPE_DPC_OTF_2_D_THR_GB[11:0] VAL = 0
• IPIPE_DPC_OTF_2_D_THR_B[11:0] VAL = 0
• IPIPE_DPC_OTF_2_C_THR_R[11:0] VAL = 4095
• IPIPE_DPC_OTF_2_C_THR_GR[11:0] VAL = 4095
• IPIPE_DPC_OTF_2_C_THR_GB[11:0] VAL = 4095
• IPIPE_DPC_OTF_2_C_THR_B[11:0] VAL = 4095
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
337
ISS ISP
www.ti.com
Figure 135. ISS ISP IPIPE Adaptive OTF DPC Method 1 Defect Correction
Intensity
Intensity
Center pixel
Replace
Maximum
Minimum
Center pixel
Replace
d0 d1 d2 d3 d4 d5 d6 d7
d0 d1 d2 d3 d4 d5 d6 d7
camss-148
3.3.3.4.2.2 ISS ISP IPIPE Adaptive OTF DPC Method 2
In adaptive OTF DPC method 2, the center pixel is compared with the second maximum and the second
minimum pixels among the surrounding 8 pixels.
The parameters for the different thresholds can be set independently for each color component.
Thresholds for each color are configured in this method:
• Detection threshold, thrD:
– IPIPE_DPC_OTF_2_D_THR_R[11:0] VAL
– IPIPE_DPC_OTF_2_D_THR_GR[11:0] VAL
– IPIPE_DPC_OTF_2_D_THR_GB[11:0] VAL
– IPIPE_DPC_OTF_2_D_THR_B[11:0] VAL
• Correction threshold, thrC:
– IPIPE_DPC_OTF_2_C_THR_R[11:0] VAL
– IPIPE_DPC_OTF_2_C_THR_GR[11:0] VAL
– IPIPE_DPC_OTF_2_C_THR_GB[11:0] VAL
– IPIPE_DPC_OTF_2_C_THR_B[11:0] VAL
After the comparison with thresholds, the center pixel d0 is replaced by d0' in the manner shown in
Figure 136
Figure 136. ISS ISP IPIPE Center Pixel d0 Replacement in Adaptive OTF DPC Method 2 Formula
ì dmax
ï
ïdmax 2
ï
d0¢ = í dmin
ïd
ï min 2
îï d0
(d0 > dmax 2 + thrD )and (dmax £ dmax 2 + thrC )
(d0 > dmax 2 + thrD )and (dmax > dmax 2 + thrC )
(d0 < dmin 2 - thrD )and (dmin ³ dmin 2 - thrC )
(d0 < dmin 2 - thrD )and (dmin < dmin 2 - thrC )
otherwise
camss-640
NOTE:
•
•
338
dmax and dmax2 are the maximum and second maximum of the surrounding pixels,
respectively.
dmin and dmin2 are the minimum and second minimum, respectively.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 137. ISS ISP IPIPE Adaptive OTF DPC Method 2 Method Center Pixel Replaced With dmax
Intensity
Center pixel
Replace
DPC detection
= thrD
threshold
dmax2
d0
d1
d2
d3
thrC =
dmax
d4
d5
d6
DPC correction
threshold
d7
If the center pixel (d0) is larger than dmax2 by more
than thrD , the center pixel is replaced with d max.
camss-149
Figure 138. ISS ISP IPIPE Adaptive OTF DPC Method 2 Method Center Pixel Replaced With dmax2
Intensity
Center pixel
Replace
dmax
DPC detection
= thrD
threshold
thrC =
dmax2
d0
d1
d2
d3
d4
d5
d6
DPC correction
threshold
d7
If dmax is larger than dmax2 by more than thrC , the
center pixel (d0) is replaced with dmax2.
camss-150
3.3.3.4.2.3 ISS ISP IPIPE Adaptive OTF DPC Method 3
The adaptive OTF DPC method 3 algorithm is the same as adaptive OTF DPC method 2, but the
threshold values (thrD and thrC) are calculated adaptively from the activity of the surrounding pixels.
Thresholds are configured in this method:
• Detection threshold, thrD:
– THR = IPIPE_DPC_OTF_3_D_THR[11:6] VAL
– SPL = IPIPE_DPC_OTF_3_D_SPL[5:0] VAL
– MIN = IPIPE_DPC_OTF_3_D_MIN[11:0] VAL
– MAX = IPIPE_DPC_OTF_3_D_MAX[11:0] VAL
• Correction threshold, thrC:
– THR = IPIPE_DPC_OTF_3_C_THR[11:6] VAL
– SLP = IPIPE_DPC_OTF_3_C_SLP[5:0] VAL
– MIN = IPIPE_DPC_OTF_3_C_MIN[11:0] VAL
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
339
ISS ISP
www.ti.com
– MAX = IPIPE_DPC_OTF_3_C_MAX[11:0] VAL
The threshold value depends on the set threshold minimum and maximum values, slope, and threshold.
The threshold is calculated depending on the activity of the surrounding pixels. Figure 139 is a graphical
representation of the activity definition. The activity value is specified by the following value.
Figure 139. ISS ISP IPIPE DPC Activity Pixel Definition
thrC or thrD
MAX
(u12)
SLP<<6
(u6)
MIN
(u12)
Activity
(u6)
THR
(u6)
camss-641
MAX, MIN, THR, and SLP are specified statically by registers and independently for thrC and thrD. All four
colors use the same set of values. THR is specified by the upper 6 bits of a register
(IPIPE_DPC_OTF_3_D_THR or IPIPE_DPC_OTF_3_C_THR).
The suffix, current, top, left, and top_left indicate the position where the calculation takes place. For
example, if the activity value at a coordinate of (x, y) is being calculated, (max3 – min3) left_top
calculation is carried out at (x–1, y–1). The shift value can be set from the IPIPE_DPC_OTF_3_SHF[1:0]
SHF bit field.
3.3.3.5
ISS ISP IPIPE 2D Noise Filter
The 2D noise filter reduces noise in RAW input data. In the device there are two 2D noise filters. Filter 1
and filter 2 can be enabled from the IPIPE_D2F_1ST_EN[0] EN and IPIPE_D2F_2ND_EN[0] EN bits,
respectively. Data does not pass through the second 2D notice filter if is to be sent to the buffer logic
module in RAW format. Moreover, if data is to be further processed in the IPIPE, it passes through the
second 2D noise filter, which can be enabled and set accordingly if more filtering is needed.
NOTE: In this section only the first 2D noise filter is explained, because the second 2D noise filter is
the same. The registers for both filters are also the same.
Figure 140 shows the data points used for this filtering. The pixel being filtered is d0; d0~d8 are same
color pixels. For green, two numbering methods are available, and can be selected in the
IPIPE_D2F_1ST_TYP[7] TYP bit.
Figure 140. ISS ISP IPIPE Noise Filter Array
d1
d2
d3
d1
d2
d3
d1
d3
d2
d1
d3
d2
d4
d0
d5
d4
d0
d5
d4
d5
d0
or
d4
d7
d6
d6
d7
d8
d6
d7
d8
d6
d7
d5
d0
d8
d8
(diamond mode)
Blue
Red
Green
camss-151
340
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
The basic concept of the 2D noise filter is area averaging by excluding far-apart-value neighbors. This
algorithm uses the following tables:
• Threshold table (10 bits, 8 entries: IPIPE_D2F_1ST_THR_0x, where x = 0 to 7): Used in the filtering
algorithm
• Intensity table (5 bits, 8 entries: IPIPE_D2F_1ST_STR_0x, where x = 0 to 7): Stores averaging weight
Threshold and intensity are read from the LUT and interpolated to make the intermediate value. The
spread factor (SPR) is set through the IPIPE_D2F_1ST_TYP[4:0] SPR bit field.
Figure 141 is the block diagram of the noise filter module.
Figure 141. ISS ISP IPIPE Noise Filter Module Block Diagram
Coordinate value
(x, y location)
Center pixel
from OTF-DPC
Radial-LSC
LUT
threshold
strength
OTF DPC 3.0
Surrounding
pixels
THR
SPR
STR
Center
pixel
(8 pixels)
Weight
calculation
Weighted
averaging
Blending
avg
Green
imbalance
correction
5 x 5 taps
Edge
detection
Noise filter
camss-152
NOTE:
Figure 141 is a generic visual representation of the 2D noise filter block. The actual 2D
noise filter 1 outputs data to a line of memory block, while the second 2D noise filter 2
outputs data to the green imbalance correction block.
The threshold value is multiplied by radial-LSC gain to compensate for the noise enhancement caused by
the LSC module in ISIF.The SPR value is a single value (IPIPE_D2F_1ST_TYP[4:0] SPR).
The LSC gain is applied to threshold values when IPIPE_D2F_1ST_TYP[8] LSC = 1.
Edge detection finds edges and controls the weight accordingly. If this function is enabled, the horizontal
or vertical edge is detected through the equations shown in Figure 142. The numbering in this equation is
always of box mode. Here, the minimum and maximum are specified in the 2D noise filter by the
IPIPE_D2F_1ST_EDG_MIN and IPIPE_D2F_1ST_EDG_MAX registers, respectively.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
341
ISS ISP
www.ti.com
Figure 142. ISS ISP IPIPE Edge Detection Formula
æ (d1 + 2d2 + d3 ) - (d6 + 2d7 + d8 ) ö
÷
hedge = abs ç
ç
÷
8
è
ø
æ (d1 + 2d4 + d6 ) - (d3 + 2d5 + d8 ) ö
÷
vedge = abs ç
ç
÷
8
è
ø
hedge > max,vedge < min Þ horizontal edge
hedge < min,vedge > max Þ vertical edge
camss-644
The threshold value is multiplied by radial-LSC gain g to compensate for the noise enhancement caused
by the LSC module in the ISIF. The gain from radial-LSC is calculated in the manner shown in Figure 143.
In the formula, x and y are the coordinates of the pixel of interest. The total gain (GAN) and offset (OFT)
values are specified independently for each color (R, Gr, Gb, and B) by IPIPE_LSC_GAN_x and
IPIPE_LSC_OFT_x (where x = R, GR, GB, or B). The other parameters are specified by the following
corresponding registers:
• IPIPE_LSC_VOFT, for vertical offset
• IPIPE_LSC_VA2
• IPIPE_LSC_VA1
• IPIPE_LSC_VS
• IPIPE_LSC_HOFT, for horizontal offset
• IPIPE_LSC_HA2
• IPIPE_LSC_HA1
• IPIPE_LSC_HS
• IPIPE_LSC_SHF
• IPIPE_LSC_MAX
Here again, for the second noise filter, THR0-7, STR0-7, and SPR are specified by the following:
• IPIPE_D2F_2ND_THR_00 to 07
• IPIPE_D2F_2ND_STR_00 to 07
• IPIPE_D2F_2ND_TYP[4:0] SPR
Under attention are the minimum and maximum, which are specified by IPIPE_D2F_2ND_EDG_MIN and
IPIPE_D2F_2ND_EDG_MAX, respectively.
342
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 143. ISS ISP IPIPE Edge Detection Formula 2
gain = limit
(((H + V )´ GAN >> SHF + OFT )S14 >> 1, MAX )
æ
ö
ö
h ææ h
ö
H = ç ´ ç ç ´ HA2 >> HS2 ÷
+ HA1 ÷
>> HS1 ÷
÷
ç 2 çè 2
÷
øS13
è
øS13
è
øS13
æ
ö
ö
v ææ v
ö
V = ç ´ ç ç ´ VA2 >> VS2 ÷
+ VA1 ÷
>> VS1 ÷
÷
ç 2 çè 2
÷
øS13
è
øS13
è
øS13
h = x + HOFT
v = y + VOFT
x<0
ì 0
ï
limit (x,max ) = í x
0 £ x £ max
ï max
max < x
î
x < -4096
ì -4096
-4096 £ x £ 4095
(x )S13 = ïí x
ï 4095
4095 < x
î
x < -8192
ì -8192
ï
-8192 £ x £ 8191
(x )S14 = í x
ï 8191
8191 < x
î
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
camss-645
343
ISS ISP
3.3.3.6
www.ti.com
ISS ISP IPIPE Green Imbalance Correction
GIC is implemented to reduce the effect of line-crawling (Gb-Gr difference), and it works only on Gb and
Gr. IPIPE contains two algorithms: simple low filtering with constant gain, and adaptive gain control.
Here, G0 is the output of the 2D noise filter, and Ga through Gd are the surrounding pixels from line
buffers, as shown in Figure 144. The GIC is enabled from the IPIPE_GIC_EN register.
Figure 144. ISS ISP IPIPE GIC Prefilter Pixels
G11
Line 0
Line 2
Line 3
Line 4
Gbb
G
Gaa
G
Line 1
Center pixel is from
2D noise filter output
G33
G
G00
GG22
Gcc
G
Gdd
G
Other G pixels are from
the line buffers
G44
G
camss-153
In Figure 144, the simple averaging algorithm is applied in the following way. When the center site is
green (Gb or Gr), the 2D prefilter mixes G0 and Gs2 = (Ga + Gb + Gc + Gd)/4 with a constant gain value
set by the IPIPE_GIC_GAN register.
To select the simple averaging algorithm, set the IPIPE_GIC_TYP[0] TYP bit to 0, and set the gain value
in the IPIPE_GIC_GAN register.
Another way to implement GIC Is to use the adaptive algorithm, which is applied in the following way. The
output data Gout is a weighted average of the center and the surrounding 4 pixels, as shown in
Figure 144.
To select the adaptive algorithm, set the IPIPE_GIC_TYP[0] TYP bit to 1, and set the gain value in the
IPIPE_GIC_GAN register.
The weight coefficients (w1, w2, w3, and w4) are determined by the function shown in Figure 147. The
output mixing ratio wt is determined by the register.
The threshold values are calculated in the manner shown in Figure 145. (LSC g is the radial-LSC gain
explained in Section 3.3.3.5, ISS ISP IPIPE 2D Noise Filter.) The following formula uses the
IPIPE_GIC_THR and IPIPE_GIC_SLP registers to set the start values for the calculated threshold.
Figure 145. ISS ISP IPIPE GIC Threshold Calculation 1
(
)
thr1 = clip (((GIC _THR + GIC _ SLP )´ gLSC ) >> 5 )
thr2 = clip (((GIC _THR + 2 ´ GIC _ SLP )´ gLSC ) >> 5 )
thr3 = clip (((GIC _THR + 3 ´ GIC _ SLP )´ gLSC ) >> 5 )
thr0 = clip (GIC _THR ´ gLSC ) >> 5
camss-648
The threshold values (thr1 to thr4) can be replaced with the threshold value of NF-2 by setting the
IPIPE_GIC_TYP[1] SEL bit to 1, as shown in the formula in Figure 146. (The parameters nf_thr and nf_dif
are identical to thr and dif in Section 3.3.3.5, ISS ISP IPIPE 2D Noise Filter.) GIC g is a U8Q5 gain
specified by a register value of GIC_NFGAN.
344
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 146. ISS ISP IPIPE GIC Threshold Calculation 2
(
)
thr1 = clip (((nf _ thr + nf _ dif )´ gGIC ) >> 5 )
thr2 = clip (((nf _ thr + 2 ´ nf _ dif )´ gGIC ) >> 5 )
thr3 = clip (((nf _ thr + 3 ´ nf _ dif )´ gGIC ) >> 5 )
thr0 = clip (nf _ thr ´ gGIC ) >> 5
camss-649
Figure 147. ISS ISP IPIPE GIC Adaptive Prefilter Weight Function
wi = f G0 - Gi
(
)
f (x)
ì4
ï
ï3
ï
f (x ) = í 2
ï1
ï
ïî0
x < thr1
4
x < thr2
3
x < thr3
2
x < thr4
1
thr4 £ x
(The first case has the highest priority.)
thr1
thr3
thr2
x
thr4
camss-154
The threshold value is multiplied by radial-LSC gain if the IPIPE_GIC_TYP[2] LSC bit is set to 1 to
compensate for the noise enhancement caused by the LSC module in the ISIF. For more information
about radial-LSC gain, see Section 3.3.3.5, ISS ISP IPIPE 2D Noise Filter.
3.3.3.7
ISS ISP IPIPE White Balance
The white balance module executes white balance to each color component. White balance gain adjusts
the ratio of each color existing in a CFA pattern. An offset can be applied before white balance correction
(IPIPE_WB2_OFT_R, GR, Gb, or B registers).
Figure 148 is a block diagram of the white balance module. In the white balance gain adjuster, the RAW
data is multiplied by a selected gain (IPIPE_WB2_WGN_R, Gr, Gb, or B registers) corresponding to the
color. The white balance gain can be selected from four 13-bit values. Firmware can assign any
combination of 4 pixels in horizontal and vertical directions. The precision of each gain is shown in the
figure.
Figure 148. ISS ISP IPIPE White Balance
Offset: –2048 to + 2047
WB GAIN: x0 –x 15.998 (step = 1/512)
WB GAIN
Green
imbalance
correction
5 x 5 taps
CLIP
u12
CLIP
u12
u25
gain for color0: u13
gain for color1: u13
gain for color2: u13
gain for color3: u13
offset for color0: s12
offset for color1: s12
offset for color2: s12
offset for color3: s12
>> 9
u16
u12
Line
memory
5376 x 12 bits
x 5 lines
RSZ
White balance
camss-155
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
345
ISS ISP
3.3.3.8
www.ti.com
ISS ISP IPIPE Color Filter Array Interpolation
The IPIPE color filter array (CFA) interpolation module generates RGB 4:4:4 data from the Bayer RGB
pattern. Figure 149 is the block diagram of the CFA interpolation module. The CFA consists of the line
delay block, edge-direction detector, and pixel interpolator. The edge-direction detector detects the most
probable edge direction of an object to which the target pixel belongs, and the pixel interpolator calculates
the missing color according to its edge direction within a 5 × 5 pixel window.
Figure 149. ISS ISP IPIPE CFA Interpolation
5x5
White
balance
Grad
lapl_h
lapl_v
Line buffer
Line buffer
5x5
Line buffer
mix_weight
Line buffer
5376 x 12 bits
x 5 lines
Weight
5x5
Hinterp
pixoutputH
pixoutputG
5x5
pixoutputV
Blend
u12
Gout
Line buffer
Vinterp
Line buffer
3x3
G
Rout
3x3
R/B mix
(3x3 input only)
Bout
RGB
color
correction
RGB2RGB blending
5376 x 12 bits
x 2 lines
Color filter array
camss-156
The CFA interpolation module also supports DAA, which reduces aliasing caused by undersampling.
CFA and DAA can be activated separately or together. The choice is made in the IPIPE_CFA_MODE[1:0]
MODE bit field. The low value of the HP threshold can be controlled from the
IPIPE_CFA_2DIR_HPF_THR register, and the HP slope can be set from the IPIPE_CFA_2DIR_HPF_SLP
register. A mixed threshold can be set from the IPIPE_CFA_2DIR_MIX_THR register, and the slope of the
HP can be set from the IPIPE_CFA_2DIR_MIX_SLP register. The directional threshold can be set from
the IPIPE_CFA_2DIR_DIR_TRH register, and the slope from the IPIPE_CFA_2DIR_DIR_SLP register.
CAUTION
The use of DAA only is not recommended.
If using only DAA, a series of settings can be applied. Hue fraction is set from the
IPIPE_CFA_MONO_HUE_FRA register, the edge of the threshold from the
IPIPE_CFA_MONO_EDG_THR register, and the threshold minimum and slope from the
IPIPE_CFA_MONO_THR_MIN and IPIPE_CFA_MONO_THR_SLP registers, respectively.
346
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.9
ISS ISP IPIPE RGB2RGB Blending Module
The RGB2RGB blending module transforms the RGB data generated by the CFA interpolation module
using a 3 × 3 square matrix transformation in combination with an added offset. The RGB-to-RGB
blending is calculated using the formula shown in Figure 150. Each gain range is from –8 to +7.996 with
step 1/256 = 0.004, and is set in the IPIPE_RGB1_MUL_RR to IPIPE_RGB1_MUL_BB registers. The
offset range for each component is from –4096 to 4095, and is set in the IPIPE_RGB1_OFT_OR to
IPIPE_RGB1_OFT_OB registers.
Figure 150. ISS ISP IPIPE RGB2RGB Conversion Formula
æ R _ out ö æ gain _ RR gain _GR gain _ BR ö æ R _ in ö æ offset _ r ö
ç
÷ ç
֍
÷ ç
÷
ç G _ out ÷ = ç gain _ RG gain _GG gain _ BG ÷ ç G _ in ÷ + ç offset _G ÷
ç B _ out ÷ ç gain _ RB gain _GB gain _ BB ÷ ç B _ in ÷ ç offset _ B ÷
è
ø è
øè
ø è
ø
camss-650
3.3.3.10
ISS ISP IPIPE Gamma Correction Module
NOTE: For the memory access locations of the gamma correction module, see Section 3.3.8.
The gamma correction module performs gamma correction independently for each color in the RGB color
space by using a piece-wise linear interpolation. ROM tables and RAM tables are selectable through the
IPIPE_GMM_CFG[4] TBL bit. Each ROM table and RAM table has 512-entries, and each entry
accommodates a 10-bit offset and 10-bit slope. The range of slope value is from –512 to +511. The ROM
table has 1024 entries and an output 8-bit value.
Figure 151 is a block diagram of the gamma correction module. It is composed of two tables and one
selector. When the BYPASS bit is asserted, the input data is divided by 16 (the IPIPE_GMM_CFG[0]
BYPR ,IPIPE_GMM_CFG[1] BYPG, and IPIPE_GMM_CFG[2] BYPB bits).
Figure 152 shows an example of the gamma curve. Figure 153 shows offset and slope packing.
Figure 151. ISS ISP IPIPE Gamma Correction Module Block Diagram
Unsigned 12 bits
Gamma
data_in
[11..3]
or
0 and [11..4]
or
00 and [11..5]
or
u9 bits
000 and [11..6]
Gamma
u6 bits
Gamma
12 x 3
[2..0] and 000
or
[3..0] and 00
or
[4..0] and 0
or
[5..0]
Gamma
table
RAM
Unsigned
10 bits
(0 ~ 1023)
Offset
Signed
10 bits
CLIP
s12
RAM
ROM
bypass
s10
s16
>> 6
512 x 20 bits Slope
u10
Unsigned 10 bits
(0 ~ 1023)
data_out
RGB
to
RGB
10 x 3
Gamma
table
ROM
>> 2
<< 2
1024 x 8 bits
u10
>> 2
Gamma correction
camss-157
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
347
ISS ISP
www.ti.com
Figure 152. ISS ISP IPIPE Gamma Curve Example
1023
Offset @ input = 1
Slope @ input = 0
Gamma table
input
0
1
2
511
camss-158
Figure 153. ISS ISP IPIPE Gamma Table Offset/Slope Packing
19..10
9..0
adr = 0
Offset[0]
Slope[0]
adr = 1
Offset[1]
Slope[1]
Offset[511]
Slope[511]
adr = 511
camss-159
3.3.3.11
ISS ISP IPIPE 2nd RGB2RGB Conversion Matrix
The second RGB2RGB blending module transforms the RGB data after gamma correction using the 3 × 3
square matrix transformation in combination with an added offset. The RGB-to-RGB blending is calculated
using the formula shown in Figure 154. Each gain range is from –4 to +3.996 with step 1/256 = 0.004
(s3.8), and is set in the IPIPE_RGB2_MUL_RR to IPIPE_RGB2_MUL_BB registers. The offset is –1024 to
1023 (s11), and is set in the IPIPE_RGB2_OFT_OR to IPIPE_RGB2_OFT_OB registers.
Figure 154. ISS ISP IPIPE RGB2RGB 2nd Conversion Formula
æ R _ out ö æ gain _ RR gain _GR gain _ BR ö æ R _ in ö æ offset _ r ö
ç
÷ ç
֍
÷ ç
÷
ç G _ out ÷ = ç gain _ RG gain _GG gain _ BG ÷ ç G _ in ÷ + ç offset _G ÷
ç B _ out ÷ ç gain _ RB gain _GB gain _ BB ÷ ç B _ in ÷ ç offset _ B ÷
è
ø è
øè
ø è
ø
camss-650
348
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.12
ISP IPIPE 3D-LUT Color Conversion
NOTE: For 3D-LUT memory access locations, see Section 3.3.8.
3D LUT converts RGB pixel data into another RGB data using a 9 × 9 × 9 entry 3D LUT, which is enabled
when the IPIPE_3DLUT_EN[0] EN bit is set to 1. Input and output are both in 10-bit format. If the input is
at the lattice point, the output is the value stored in the table shown in Figure 155.
Figure 155. ISS ISP IPIPE 3D-LUT Color Conversion Formula
Rout = LUTR ëéP (Rin / 128,Gin / 128,Bin / 128 )ûù
Rin mod 128 = 0
Gout = LUTG ëéP (Rin / 128,Gin / 128,Bin / 128 )ûù , when Gin mod 128 = 0
Bout = LUTB ëéP (Rin / 128,Gin / 128,Bin / 128 )ûù
Bin mod 128 = 0
camss-651
The entry number is determined by the formula shown in Figure 156.
Figure 156. ISS ISP IPIPE 3D-LUT Entry Number Formula
P (R,G,B ) = R + 9G + 81B
camss-652
If the input is not on the lattice point, the output is determined by the tetrahedral interpolation formula
shown in Figure 157.
Figure 157. ISS ISP IPIPE 3D-LUT Tetrahedral Interpolation Formula
R _dif = R mod 128, R _ i = (R - R _dif ) / 128
G _dif = G mod 128, G _ i = (G - G _dif ) / 128
B _dif = B mod 128, B _ = (B - B _ ) / 128
i
dif
R0 = LUTR éëP0 ùû G0 = LUTG éëP0 ùû B0 = LUTB éëP0 ùû
R1 = LUTR éëP1ùû , G1 = LUTG éëP1ùû , B1 = LUTB éëP1ùû ,
R2 = LUTR ëéP2 ûù G2 = LUTG ëéP2 ûù B2 = LUTB ëéP2 ûù
R3 = LUTR ëéP3 ûù G3 = LUTG ëéP3 ûù B3 = LUTB ëéP3 ûù
Rout = R0 + (R1 - R0 )× x + (R2 - R1 )× y + (R3 - R2 )× z
Gout = G0 + (G1 - G0 )× x + (G2 - G1 )× y + (G3 - G2 )× z
Bout = B0 + (B1 - B0 )× x + (B2 - B1 )× y + (B3 - B2 )× z
camss-653
P0-P3 and x, y, and z are determined by the following table.
Input/Output Condition
Input Condition
P0
P1
P2
P3
(X, Y, Z)
Rdif≥Gdif≥Bdif
(Ri, Gi, Bi)
(Ri +1, Gi, Bi)
(Ri +1, Gi +1, Bi)
(Ri +1, Gi +1, Bi +1)
(Rdif, Gdif, Bdif)
Rdif≥Bdif≥Gdif
(Ri, Gi, Bi)
(Ri +1, Gi, Bi)
(Ri +1, Gi, Bi +1)
(Ri +1, Gi +1, Bi +1)
(Rdif, Bdif, Gdif)
Gdif≥Rdif≥Bdif
(Ri, Gi, Bi)
(Ri, Gi +1, Bi)
(Ri +1, Gi +1, Bi)
(Ri +1, Gi +1, Bi +1)
(Gdif, Rdif, Bdif)
Gdif≥Bdif≥Rdif
(Ri, Gi, Bi)
(Ri, Gi +1, Bi)
(Ri, Gi +1, Bi +1)
(Ri +1, Gi +1, Bi +1)
Gdif, Bdif, Rdif)
Bdif≥Rdif≥Gdif
(Ri, Gi, Bi)
(Ri, Gi, Bi +1)
(Ri +1, Gi, Bi +1)
Ri +1, Gi +1, Bi +1)
(Bdif, Rdif, Gdif)
Bdif≥Gdif≥Rdif
(Ri, Gi, Bi)
(Ri, Gi, Bi +1)
(Ri, Gi +1, Bi +1)
(Ri +1, Gi +1, Bi +1)
(Bdif, Gdif, Rdif)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
349
ISS ISP
www.ti.com
P0, P1, P2, and P3 are always in different banks. The data in LUT are packed in a manner shown in
Figure 158.
Figure 158. ISS ISP IPIPE 3D-LUT Data Packing
Bit 29..20 19..10
9..0
29..20 19..10
9..0
29..20 19..10
9..0
29..20 19..10
9..0
adr = 0
R[0]
G[0]
B[0]
R[1]
G[1]
B[1]
R[2]
G[2]
B[2]
R[3]
G[3]
B[3]
adr = 1
R[4]
G[4]
B[4]
R[5]
G[5]
B[5]
R[6]
G[6]
B[6]
R[7]
G[7]
B[7]
adr = 182
R[728] G[728] B[728]
R[729] G[729] B[729]
R[730] G[730] B[730]
R[731] G[731] B[731]
adr = 191
R[764] G[764] B[764]
R[765] G[765] B[765]
R[766] G[766] B[766]
R[767] G[767] B[767]
Bank0
Bank1
Bank2
Bank3
camss-160
The LUT with its 9 × 9 × 9 entries are stored in four banks (total 192 × 30 bits × 3 ) in a local memory
bank table linked with the 3D-LUT converter. The entries at and above 729 are not used by the 3D-LUT
function.
3.3.3.13
ISS ISP IPIPE RGB2YCbCr Conversion Matrix
This module transforms the RGB data to YCbCr data format using a 3 × 3 matrix transformation in
combination with an added offset. While transferring, the brightness control and contrast control can be
adjusted using the IPIPE_YUV_ADJ[8:15] BRT and IPIPE_YUV_ADJ[8:15] CRT bit fields, respectively.
Then, the transform is calculated using the formula shown in Figure 159. Each gain range is from –8 to
+7.996 with step 1/256 = 0.004, configured in the IPIPE_YUV_MUL_RY to IPIPE_YUV_MUL_BCr
registers. The offset is –1024 to 1023 for Y, Cb, and Cr, configured in the IPIPE_YUV_OFT_Y to
IPIPE_YUV_OFT_Cr registers. Figure 160 is the block diagram of the RGB to RGB blending module. The
output is calculated by the equation.
Figure 159. ISS ISP IPIPE RGB2RGB 2nd Conversion Formula
gain _GY
gain _BY ö æ R _ in ö æ offset _Y ö
æY _out ö æ gain _RY
ç
÷ ç
÷ ç
÷ ç
÷
Cb
_out
=
gain
_RCb
gain
_GCb
gain
_BCb ÷ = ç G _ in ÷ + ç offset _Cb ÷
ç
÷ ç
ç Cr _out ÷ ç gain _RCr gain _GCr gain _BCr ÷ ç B _ in ÷ ç offset _Cr ÷
è
ø è
ø è
ø è
ø
350
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
R_in
unsigned 10 bits
s22
s15
>> 7
G_in
unsigned 10 bits
3D
LUT
B_in
unsigned 10 bits
10 x 3
gain_RY
signed 12 bits
+1
CLIP
s17
s18
>> 7
s17
>>1
gain_GY
Offset_Y
s14
signed 11 bits
<< 3
–1024 to +1023
>> 7
gain_BY
512 x 20
>> 7
gain_RCb
CLIP
s17
>> 7
s15
s16
>> 2
s15
/2
gain_GCb
Offset_Cb
signed 11 bits
>> 7
gain_BCb
–1024 to +1023
GBCE
s12
u8
-2048 to + 2046
s15
s16
>> 2
gain_GCr
u8
<< 1
CLIP
s17
>> 7
Cb_out
unsigned 8 bits
round to zero
>> 7
gain_RCr
Y_out
unsigned 10 bits
Boundary signal calc
histogram
Figure 160. ISS ISP IPIPE RGB2YCbCr Module Block Diagram
s15
/2
Cr_out
unsigned 8 bits
round to zero
Offset_Cr
s12
signed 11 bits
<< 1
–1024 to +1023
>> 7
gain_BCr
RGB2YCbCr module
camss-161
3.3.3.14
ISS ISP IPIPE Global Brightness and Contrast Enhancement
NOTE: For GBCE memory access locations, see Section 3.3.8.
GBCE applies adaptive tone mapping on the Y channel for best image quality and can be enabled through
the IPIPE_GBCE_EN[0] bit. When enabled, the Y channel is converted by a 1024 entry 8-bit output LUT.
The LUT is calculated by software and written to the IPIPE memory table before capturing the target frame
by setting the IPIPE_GBCE_TYP[0] bit to 0 for Y. See Figure 161.
Figure 161. ISS ISP IPIPE GBCE Mode 1 Formula
Youtput = LUT éëYinput ùû
Cboutput = Cbinput
(GBCE mode 1)
Croutput = Crinput
camss-656
GBCE also has another mode when the IPIPE_GBCE_TYP[0] bit is set to 1, where Y and C signals are
multiplied by a gain value. The gain value is a function of Y input and is in unsigned 10-bit format.
Figure 162 shows the second mode in greater detail.
Figure 162. ISS ISP IPIPE GBCE Mode 2 Formula
[
]
- 128)
ù
+ 128
Youtput = clipU 8 (gain ´ Yinput )>> 10
é gain ´ (Cbinput
Cboutput = clipU 8 ê
ú
256
ë
û
(
)
é gain ´ Crinput - 128
ù
+ 128ú
Croutput = clipU 8 ê
256
ë
û
gain = LUT [Yinput ]
(GBCE mode 2)
camss-657
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
351
ISS ISP
www.ti.com
If GBCE is off, Y value is converted to u8, and Cb and Cr are not changed, as shown in Figure 163.
Figure 163. ISS ISP IPIPE GBCE Mode Off Formula
(
)
Youtput = Yinput + 2 >> 2
(GBCE off)
Cboutput = Cbinput
Croutput = Crinput
camss-658
Then, after setting the mode, data is packed in 20 bits in the manner shown in Figure 164 and Figure 165
for mode 1 and mode 2, respectively.
Figure 164. ISS ISP IPIPE GBCE LUT Packing in Mode 1
19..18
17..10
9..8
7..0
adr = 0
LUT[1]
LUT[0]
adr = 1
LUT[3]
LUT[2]
LUT[1023]
LUT[1022]
adr = 511
camss-162
Figure 165. ISS ISP IPIPE GBCE LUT Packing in Mode 2
19..10
7..0
adr = 0
LUT[1]
LUT[0]
adr = 1
LUT[3]
LUT[2]
LUT[1023]
LUT[1022]
adr = 511
camss-659
352
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.15
ISS ISP IPIPE 4:2:2 Conversion Module
The 4:2:2 conversion module converts the image data to YCbCr-4:2:2 format by taking the average of
every two Cb and Cr components. Y and Cb/Cr sampling point of spatial cosited or spatial centering are
selectable using the IPIPE_YUV_PHS[0] POS register. Horizontal 3 taps and 4- or 2-tap filters are used
for spatial cosited and spatial centering, respectively. The module is enabled from the IPIPE_YUV_PHS[1]
PLF bit.
Figure 166. ISS ISP IPIPE Chroma Subsampling Position
Luminance samples
Chrominance samples
a) Spacial co-siting
b) Spacial centering
camss164
Figure 167 is a block diagram of the 4:2:2 conversion module.
Figure 167. ISS ISP IPIPE 4:2:2 Conversion Module Block Diagram
1:3:3:1
or
1:1
GBCE
u8
1:1 LPF
1:2:1 LPF
Line
memory
1:2:1
u8
through
4:2:2 Conversion module
camss-165
3.3.3.16
ISS ISP IPIPE 2D Edge Enhancer
NOTE: For the location of 2D edge-enhancer memory accesses, see Section 3.3.8.
The edge-enhancer module operates on the luminance (Y data) component of images to improve the
image quality and can be enabled from the IPIPE_YEE_EN[0] EN bit. Edges in input images are detected
by a 2D high-pass filter, and its sharpness is increased by the value from a non-linear table. Figure 168
shows a block diagram of the luminance non-linear edge-enhancer. Entry for the non-linear table is 10-bit
and the output is in signed 9-bit.
In edge-enhancer mode when IPIPE_YEE_TYP[0] SEL is set to 0, linear filter with programmable
coefficient is applied to the Y input. Here, M is a 5 × 5 matrix with programmable coefficients
(IPIPE_YEE_MUL_xx, where x = 00, 01, 02, 10, 11, 12, 20, 21, 22). A down shift of high pass filter is
applied to the edge enhancer from the IPIPE_YEE_SHF[3:0] SHF bit field (shgHPF in the formula).
Then, the HPF value is shrunk by a threshold value (u6) specified by the IPIPE_YEE_THR register
(thresholdHPF in the formula), and clipped to signed 10 bits to get the index for the LUT.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
353
ISS ISP
www.ti.com
Figure 168. ISS ISP IPIPE 2D Edge-Enhancer Indexing
(
index = clip shrink (HPF ,thresholdHPF ), -512,511
ì x + threshold
ï
shrink ( x,threshold ) = í
0
ï
î x - threshold
)
x < - threshold
- threshold £ x £ threshold
threshold < x
ì - lim itLOW
ï
clip (x,lim itLOW ,lim itHIGH ) = í
x
ï lim it
HIGH
î
x < - lim itLOW
- lim itLOW £ x £ lim itHIGH
lim itHIGH < x
camss-661
Moreover, the edge-enhancement intensity is looked up from the LUT through the formula shown in
Figure 169 and in Table 176.
Figure 169. ISS ISP IPIPE 2D Edge Intensity LUT Formula
Eint = LUT [index ]
camss-662
Table 176. ISS ISP IPIPE Edge-Enhancer LUT Mapping
Address (32-bit Word
Address)
0x00000h
0x00001h
0x00002h
0x00003h
.
.
.
0x000FFh
0x00100h
0x00101h
.
.
.
0x001FD
0x001FE
0x001FFh
354
Bit Position
LUT Index
8 .. 0
1
17 ..9
2
8 .. 0
2
17 .. 9
3
8 .. 0
4
17 .. 9
5
8 .. 0
6
17 .. 9
7
.
.
.
.
.
.
8 .. 0
510
17 .. 9
511
8 .. 0
–512
17 .. 0
–511
8 .. 0
–510
17 .. 9
–509
.
.
.
.
.
.
8 .. 0
–6
17 .. 9
–5
8 .. 0
-4
17 .. 9
-3
8 .. 0
-2
17 .. 9
-1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 170 shows the LUT packing, and Figure 171 shows the 2D edge-enhancer block diagram.
Figure 170. ISS ISP IPIPE 2D Edge-Enhancer LUT Packing
17..9
8..0
adr = 0
LUT[1]
LUT[0]
adr = 1
LUT[3]
LUT[2]
LUT[1023]
LUT[1022]
adr = 511
camss-166
Figure 171. ISS ISP IPIPE 2D Edge-Enhancer Block Diagram
2D
High-pass
filter
(3x3)
CLIP
Signed 11 bits
>> N1
u10
From
IPIPEIF
Video port
u16
Input
I/F
u8
Y (luminance)
u16
u6
unsigned 8 bits
5 x 5 kernel
2D
High-pass
filter
(5x5)
Line memory
4:4:4
to
4:2:2
Chroma
artifact
reduction
ABS
Line memory
LUT
(1024 x 9 bit)
>> shfHPF
u4
s9
shrink
Line memory
Line memory
mergeSel
Edge
sharpener
s7
absmax
s10
5 x 5 kernel
enEE
s10
u8
u8
u8
s11
CLIP
Y
CGS
2-D edge enhancer
camss-167
In edge sharpener mode, enabled when IPIPE_YEE_TYP[0] SEL = 1, edge clarity is enhanced without
producing a Halo artifact. In this module, edge intensity is derived by the 2D linear filter with fixed
coefficients shown in Figure 172.
Figure 172. ISS ISP IPIPE Edge Sharpener Details
æ 0 -1 -2 -1 0 ö
ç
÷
2
0 -1 ÷
ç -1 0
Si , j = ç -2 2
8
2 -2 ÷
ç
÷
2
0 -1 ÷
ç -1 0
ç 0 -1 -2 -1 0 ÷
è
ø
æ
æ
2
2
ç
sharpness (h,v ) = clip ç shrink ç g å å Si , jY (h + i ,v + j ), - thresholdLOW ,thresholdLOW
çç
ç
è j = -2 i = -2
è
ö
ö
÷
÷ >> 6,threshold
HIGH ÷
÷÷
÷
ø
ø
camss-663
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
355
ISS ISP
www.ti.com
The gain (g) and threshold values for the shrink/clip function (thresholdLOW, thresholdHIGH) are determined
by the IPIPE_YEE_E_GAN, IPIPE_YEE_THR_1 and IPIPE_YEE_THR_2 registers. The gain g is in
U12Q6, thresholdHIGH is in U6, and thresholdLOW is in U12Q6.
This edge intensity is then clipped by a threshold value in the formula shown in Figure 173.
Figure 173. ISS ISP IPIPE 2D Edge-Intensity Clipping Formula
ìïclip (sharpness,grad ) Halo reduction on
Sint = í
Halo reduction off
sharpness
ïî
camss-664
The threshold value (grad) is a function of the activity around the target pixel, which is derived from
gradient values. Gain and offset are specified by IPIPE_YEE_G_GAN and IPIPE_YEE_G_OFT
Capping with gradient value prevents overly enhancing edges, and suppresses halo artifacts around
edges.
The output from edge enhancer and edge sharpener are merged with the function shown in Figure 174.
Figure 174. ISS ISP IPIPE 2D Edge Enhancer and Sharpener Merger Formula
ì
ï
mergedsel = 0
Emerge = íEint + Sint
ï abs max (Eint , Sint ) mergedsel =1
î
ì
ï
abs max (x, y ) = í x
ïî y
abs (y ) £ abs (x )
otherwise
The Emerge value is added to the Y input value to make the final output.
For chroma suppression, another 2D high pass filter (HPF) is implemented. One of the four coefficient
sets shown in Figure 175 is selectable.
Figure 175. ISS ISP IPIPE 2D Edge Chroma-Suppression Coefficient Sets
æ0 0 0ö æ0 0 0ö æ0 1 0ö
ç
÷ ç
÷ ç
÷
ç 0 1 0 ÷ , ç 1 -2 1 ÷ , ç 0 -2 0 ÷ , or
ç0 0 0÷ ç0 0 0÷ ç0 1 0÷
è
ø è
ø è
ø
æ0 1 0ö
ç
÷
ç 1 -4 1 ÷
ç0 1 0÷
è
ø
camss-667
At the end of the edge enhancer process, brightness and contrast adjustment are applied to the Y signal.
The formula shown in Figure 176 describes the process.
Figure 176. ISS ISP IPIPE 2D Edge-Brightness and Contrast Adjustments Formula
Yctr_brt = clip8(clip8((YEE x CTR) >> 4) + BRT)
camss-668
356
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.17
ISS ISP IPIPE Chroma Artifact Reduction
Chroma artifact reduction (CAR) reduces color artifacts at the edges. Chroma reduction is enabled
through the IPIPE_CAR_EN[0] EN bit, but a resizer setting must be considered if Bayer input/output is set
from the resizer source register (for more information, see IPIPE_CAR_EN and section, RESIZER).
CAR has two methods: 3 × 3 median filter and chroma gain control. Also, dynamic switching between
these two methods is available to obtain the best performance of each method. The mode is configured
with the IPIPE_CAR_TYP[0] TYP bit.
Figure 172 shows the Cb part of the CAR block diagram.
Figure 177. ISS ISP IPIPE CAR Block Diagram (Cb Part)
Y
Edge
enhancer
u8
From
IPIPEIF
Video port
u16
Input
I/F
u16
Gain
control
Cb
input
Line memory
CGS
4:4:4
to
4:2:2
Line memory
Line memory
Cb/Cr output
3x3
Median
filter
Dynamic
switching
Cr input
(After 2 lines delay)
Chroma artifact reduction
camss-168
In gain control mode, the gain is calculated by the formula shown in Figure 178 (the gain, gain1, and gain2
values are in U9Q8 format.).
Figure 178. ISS ISP IPIPE CAR Gain Control Mode Formula
gain =
{
1
gain1 x gain2 >>8
|HPF| < IPIPE_CAR_HPF_THR
otherwise
camss-669
The type of HPF filter is determined by the IPIPE_CAR_HPF_TYP[2:0] TYP bit field. The gain values
(gain1 and gain2) are calculated by the functions shown in Figure 179. The parameters are the settings of
the following registers:
• IPIPE_CAR_HPF_THR
• IPIPE_CAR_HPF_SHF
• IPIPE_CAR_GN1_GAN
• IPIPE_CAR_GN1_SHF
• IPIPE_CAR_GN1_MIN
• IPIPE_CAR_GN2_GAN
• IPIPE_CAR_GN2_SHF
• IPIPE_CAR_FN2_MIN
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
357
ISS ISP
www.ti.com
Figure 179. ISS ISP IPIPE CAR Gain 1 and Gain 2 Functions
gain1 (U9Q8)
(slope = IPIPE_CAR_GN1_GAN >> IPIPE_CAR_GN1_SHF)
256
IPIPE_CAR_GN1_MIN
|HPF| >> IPIPE_CAR_HPF_SHF
IPIPE_CAR_HPF_THR
0
255
gain2 (U9Q8)
256
(IPIPE_CAR_GN2_GAN >> IPIPE_CAR_GN2_SHF)
IPIPE_CAR_GN2_MIN
2
0
2
Cb + Cr
camss-670
The output from the gain control functions is shown by the formula in Figure 180 (the fractional parts are
rounded down).
Figure 180. ISS ISP IPIPE CAR Gain Control Functions Output Formula
(Cbin - 128) x gain
Cbout =
Crout =
256
(Crin - 128) x gain
+ 128
+ 128
256
camss-671
The dynamic switching between the 3 × 3 median filter and gain control is done in the following way:
1. If (cb2 + cr2)/256 switch_limit, use the median filter.
2. If (switch_coef)x((cb2 + cr2)/256) = cb2, use gain control.
3. If both conditions are not met, do not apply any filter.
The values of switch_limit and switch_coef are determined by the values of the IPIPE_CAR_SW[7:0] SW0
and IPIPE_CAR_SW[15:8] SW1 bit fields, respectively. To prevent desaturation of colors, the first
condition limits the area where the median filter is applied to only an unsaturated area.
With the appropriate value, this condition selectively removes the purple artifact.
358
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.18
ISS ISP IPIPE Chroma Gain Suppression
The chroma gain suppression (CGS) module controls the gain of Cb and Cr in dark or overly bright
conditions. The function is enabled from the IPIPE_CGS_EN[0] EN bit.
Cboutput = (total_gain x Cbinput) / 256
Croutput = (total_gain x Crinput) / 256
The gain value is determined by the formula shown in Figure 181.
Figure 181. ISS ISP IPIPE CGS Gain Value Formula
(
)
(
)
ì max 256 - gY1 ´ (thrY1 - Y ) >> shfY1 ,min Y1
Y £ thrY1
ïï
thrY
gain1 = í
256
1 < Y < thrY2 ,
ï
thrY2 £ Y
ïî max 256 - gY 2 ´ (Y - thrY2 ) >> shfY 2 ,min Y2
ìï max (256 - g c ´ ( thrC - C ) >> shfc ,min C ) C £ thrC
gain2 = í
256
thrC < C '
îï
0 £ thrY1 ,thrY2 ,thrC £ 255
0 £ gY1 ,gY 2 ,gC £ 255
0 £ shfY1 ,shfY 2 ,shfC £ 7
camss-673
The parameters in the formula in Figure 181 are specified by registers. Table 177 lists these parameters
and registers.
Table 177. ISS ISP IPIPE CGS Gain Value Formula Parameters
Formula
Parameter
Register
thrY1
IPIPE_CGS_GN1_L_THR
gY1
IPIPE_CGS_GN1_L_GAIN
shfY1
IPIPE_CGS_GN1_L_SHF
thrY2
IPIPE_CGS_GN1_H_THR
gY2
IPIPE_CGS_GN1_H_GAIN
minY1
IPIPE_CGS_GN1_L_MIN
minY2
IPIPE_CGS_GN1_H_MIN
shfY2
IPIPE_CGS_GN2_L_SHF
thrC
IPIPE_CGS_GN2_L_THR
gC
IPIPE_CGS_GN2_L_GAIN
shfC
IPIPE_CGS_GN2_L_SHF
minC
IPIPE_CGS_GN2_L_MIN
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
359
ISS ISP
www.ti.com
Figure 182 and Figure 183 also show these functions.
Figure 182. ISS ISP IPIPE CGS Gain 1
gain1
Saturated
image
correction
gY1 >> shfY1
256
gY2 >> shfY2
minY1
Chroma
noise
reduction
minY2
thrY1
thrY2
camss-674
Figure 183. ISS ISP IPIPE CGS Gain 2
gain2
gC >> shfC
256
minC
Chroma
noise
reduction
thrC
camss-675
360
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.3.19
ISS ISP IPIPE Histogram
NOTE: The boxcar function can be used simultaneously with the histogram function if needed.
NOTE: For the locations of histogram memory access, see Section 3.3.8.
The histogram module counts the number of pixels that have a value in a region and can be enabled from
the IPIPE_HST_EN[0] EN bit. Moreover, if enabled, the IPIPE_HST_MODE register can be set to work
constantly or one time. If the IPIPE_HST_MODE[0] OST bit is set to 1, the histogram is disabled by
clearing the IPIPE_HST_EN[0] EN bit to 0 after one run (one-shot mode).
After enabling the module, the following features are available:
• The data to be summed is taken from the DPC memory or RGB2YCbCr module. The choice is made
in the IPIPE_HST_SEL[2] SEL bit.
• When data are collected from the DPC memory, the sampled colors are R/G/B/Y. Y is derived in the
following method:
Y = (HST_MUL_R*R + HST_MUL_GR*Gr + HST_MUL_GB*Gb + HST_MUL_B*B)
•
•
•
•
•
•
•
•
•
•
•
•
(2)
For the G histogram, Gb, Gr, or the average is used, through the IPIPE_HST_SEL[1:0] TYP bit field.
Two sets of 512 × 20-bit memory are used.
The number of bins can be set from 32 to 256 in the IPIPE_HST_PARA[13:12] BIN bit field.
The number of regions (areas) from 1 to 4; each region can be enabled through IPIPE_HST_PARA[x]
RGNx (where x = 0 to 3). The positions of the regions are defined in IPIPE_HST_x_VPS and
IPIPE_HST_x_HPS, and the vertical and horizontal size are defined by IPIPE_HST_x_VSZ and
IPIPE_HST_x_HSZ, respectively (where x = 0 to 3).
The number of regions × the number of bins = 256.
Each region can be turned on/off counting.
The regions have priority orders.
Each region has its own start coordinate X/Y (12 bits) and horizontal/vertical sizes (12 bits)
When regions are overlapped, the value in the overlapped region is accumulated only in the region
with the highest priority.
The number of colors to be counted is from 1 to 4. Each color in all regions can be turned off counting
(the IPIPE_HST_PARA[7:4] bit field).
The value of each pixel is down-shifted (0 ~ 11) before counting using the IPIPE_HST_PARA[11:8]
SHF bit field.
When the value of a bin reaches (220 – 1), the value is saturated until the memory is cleared.
Number of bins: 32, 64, 128, or 256
The histogram memory can be cleared at the VD signal. When the memory is cleared, the first line of each
frame cannot be sampled by the histogram if the width of the frame is larger than 512. If the width of the
frame is smaller than 512, the first ceil (512/width) lines cannot be collected, where ceil(x) is the smallest
integer value above x. If the clearing function is not enabled, the histogram bins are accumulated over the
previous values.
The histogram has two banks of memories, which can be switched alternatively. The two memory banks
are slipped into four histogram memory tables. Only two tables cam be used at a time: output memory
tables 0 and 1, or tables 2 and 3. To initialize tables, the IPIPE_HST_TBL[1] CLR bit is set to 1, and to
select which set of tables is to be used the IPIPE_HST_TBL[0] SEL bit can be switched between 0 and 1.
A gain for each color can be applied using the IPIPE_HST_MUL_x registers, where x = R, GR, GB, or B.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
361
ISS ISP
3.3.3.20
www.ti.com
ISS ISP IPIPE Boxcar
The boxcar module generates a boxcar by taking mosaic image data and averaging the red, green, and
blue pixels in an (8 × 8) or (16 × 16) block to produce one red, green, and blue output, as shown in
Figure 184 and in Figure 185. Here, similar to the histogram module, the boxcar is enabled from the
IPIPE_BOX_EN[0] EN bit, and if the mode is set to run once (one shot) (IPIPE_BOX_MODE[0] OST = 1),
the enable bit is cleared after the run. The size of the blocks is determined from the IPIPE_BOX_SHF[0]
SEL bit, where if set to 0 = 8 × 8, and 1 = 16 × 16.
The result of this operation is a full-color image with (1/64) or (1/256) area of the original image. The
maximum input horizontal width is 8190 pixels when a 16 ×16 block is used; the width is 4096 when an 8
× 8 block is used. Also, the image size (width and height) must be multiple of 16 for a 16 × 16 block, and
multiple of 8 for an 8 × 8 block. Boxcar operation works on 12-bit Bayer data and outputs 16-bit data. The
output data is 48-bit RGB data for each 8 × 8 or 16 × 16 block. The 48-bit data is aligned in 64-bit format
in SDRAM as shown in Section 3.3.3.20. The first address of SDRAM access is specified by the
IPIPE_BOX_SDR_SAD_H and IPIPE_BOX_SDR_SAD_L registers. The output data are written to
SDRAM continuously line by line; there is no address offset between lines. After the image transfer of
each frame completes, the ipipe_eof signal is sent to buffer logic. This signal is issued at the same timing
as ipipe_int_dma.
Figure 184. ISS ISP IPIPE Boxcar Operation (8 × 8 Block)
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G R G R G
G B G B G B G B
Average of 16 red pixels
R
Average of 32 green pixels
G
Average of 16 blue pixels
B
camss-192
Figure 185. ISS ISP IPIPE Boxcar Operation (16 × 16 Block)
16
R
G
R
G
R
16
G R G
B G B
G R G
B G B
G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G
G B
R G
G B
R G
G B
R G
G B
Average of 64 red pixels
R
Average of 128 green pixels
G
Average of 64 blue pixels
R G R G R G R G
G B G B G B G B
B
R G
G B
camss-193
362
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 186. ISS ISP IPIPE Boxcar Data Packing in SDRAM
255–192
Pixel 4N+3
191–128
Pixel 4N+2
127–64
Pixel 4N+1
63–0
Zeros
63–48
Red
47–32
Green
31–16
Blue
15–0
Pixel 4N+0
camss-194
The right shift value is specified by the IPIPE_BOX_SHF register, which has a range of 0 to 4. (The shift
down is performed to fit the 20-bit accumulated value into 16-bit output.) For green signal processing, a
divide-by-two operation rounds off the least-significant bit (LSB).
3.3.3.21
ISS ISP IPIPE Boundary Signal Calculator
NOTE: For the locations of BSC memory access, see Section 3.3.8.
The BSC generates the row summations and column summations from YCbCr 4:4:4 data. Figure 187 is
the block diagram of the BSC. The calculator can be initialized from the IPIPE_BSC_EN[0] EN bit, and the
mode can be set from the IPIPE_BSC_MODE[0] OST bit to free run or one shot (run once and then deinitialize itself by clearing the IPIPE_BSC_EN register).
BSC generates two kinds of vectors from one of Y, Cb, or Cr data:
• Vector of sums of row pixels (can be set from the IPIPE_BSC_TYP[2] REN bit)
• Vector of sums of column pixels (can be set from the IPIPE_BSC_TYP[3] CEN bit)
For both row and column sums, up to four vectors can be generated. Both row and column sums are 16bit values, which are stored to 960 × 32-bit memories, respectively. The maximum number of sums is
1920 for both row and column. The elements to be summed can also be selected. The
IPIPE_BSC_TYP[0:1] COL bit can be set to 0xX, where X = 0 to 2 for Y, Cb, and Cr.
In case the successive frames are to be processed, there is a limitation that some of the lines (more than
16 lines) between the frames cannot be used for calculation.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
363
ISS ISP
www.ti.com
Figure 187. ISS ISP IPIPE Block Diagram of BSC Module
R
G
B
Y
Cb
RGB
2YCbCr
Cr
8
8
8
Y
4:2:2
conversion Cb/Cr
Boundary
signal
calculator
Row sum
960 x 32 bits
Column sum
960 x 32 bits
camss-195
For row sum vectors, the following parameters are required:
• The position of the first pixel to be summed (the IPIPE_BSC_ROW_HPOS and
IPIPE_BSC_ROW_VPOS registers for horizontal and vertical, respectively)
• The spacing between adjacent sampling pixels (the IPIPE_BSC_ROW_HSKIP and
IPIPE_BSC_ROW_VSKIP registers for horizontal and vertical, respectively)
• The number of sampled pixels (the IPIPE_BSC_ROW_HNUM and IPIPE_BSC_ROW_VNUM registers
for horizontal and vertical, respectively)
• The number of row sum vectors (IPIPE_BSC_ROW_VCT)
• The down shift value of input data (IPIPE_BSC_ROW_SHF)
Figure 188 describes these parameters.
The number of row sums cannot exceed 1920. The IPIPE_BSC_ROW_VCT and
IPIPE_BSC_ROW_VNUM registers must be set according to the following equation:
( IPIPE_BSC_ROW _VCT +1 ) * ( IPIPE_BSC_ROW _VNUM +1 ) = 1920
364
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 188. ISS ISP IPIPE BSC Row Sum Vector Calculation
d00 d01 d 02 d 03
d10 d11 d 12 d 13
The first pixel is at
(ROW_HPOS, ROW_VPOS).
+
(ROW_VSKIP+1)
lines apart
+
(ROW_HSKIP+1)
pixels apart
+
+
+
Sum of (ROW_HNUM+1)
pixels = rowsum 0,0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
= rowsum 1,ROW_VNUM
= rowsum 0,ROW_VNUM
(ROWLH+1) pixels
+
(ROWLH+1) pixels
Vector-0
= {rowsum0,v}
Vector-1
= {rowsum1,v }
+
= rowsum 2,0
+
+
+
= rowsum 2,1
+
+
= rowsum 1,2
= rowsum 0,2
The (ROW_VNUM+1)th row
is the last row.
+
= rowsum 1,1
= rowsum 0,1
+
+
= rowsum 1,0
(ROWLV+1)
lines
+
= rowsum 2,2
+
+
+
= rowsum 2,ROW_VNUM
(ROWLH+1) pixels
Vector-2
= {rowsum2 ,v}
camss-196
For column sum vectors, the following parameters are required:
1. The position of the first pixel to be summed (the IPIPE_BSC_COL_HPOS and
IPIPE_BSC_COL_VPOS registers for horizontal and vertical, respectively)
2. The spacing between adjacent sampling pixels (the IPIPE_BSC_COL_HSKIP and
IPIPE_BSC_COL_VSKIP registers for horizontal and vertical, respectively)
3. The number of sampled pixels (the IPIPE_BSC_COL_HNUM and IPIPE_BSC_COL_VNUM registers
for horizontal and vertical, respectively)
4. The number of column sum vectors (IPIPE_BSC_COL_VCT)
5. The down shift value of input data (IPIPE_BSC_COL_SHF)
Figure 189 describes these parameters.
The number of column sums cannot exceed 1920. The IPIPE_COL_VCT and IPIPE_COL_HNUM
registers can be set according to the following equation:
(BSC_COL _VCT +1) * (BSC_COL _ HNUM +1)=1920
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
(3)
365
ISS ISP
www.ti.com
Figure 189. ISS ISP IPIPE BSC Column Sum Vector Calculation
d00 d01 d02 d03
d10 d11 d12 d13
The (COL_HNUM+1)th column
is the last column.
The first pixel is at
(COL_HPOS, COL_VPOS).
(COL_VSKIP+1)
lines apart
+
+
(COL_HSKIP+1)
pixels apart
Sum of
(COL_VNUM+1)
pixels
= colsum0, 0
+
+
+
+
+
+
= colsum0, 1
= colsum0, 2
= {colsum0 ,h}
+
+
+
+
+
+
+
= colsum1, 1
= colsum1, 2
Vector-0
= colsum0 COL_HNUM
+
= colsum1, 0
(COLLV+1)
lines
= colsum1, COL_HNUM
(COLLV+1)
lines
Vector-1
= {colsum1, h }
(COLLH+1) pixels
camss-197
3.3.4
ISS ISP RSZ Functional Description
3.3.4.1
•
•
366
ISS ISP RSZ Overview
The RSZ module rescales images into various sizes ranging from x1/4096 scale-down to x16 scale-up.
It also works in conjunction with the rotational engine (ROT) in SIMCOP for rotating images. The RSZ
data slave interfaces support a parallel video port (VP). The RSZ module can produce two output
images simultaneously, because there are two independent resizer engines. The input data used by
the two resizer engines is the same.
The RSZ module has the following capabilities:
Input/output data formats:
– Common input data for the two resizers
– Independent output data formats for the two resizers
– Supports YUV4:2:2 input and YUV4:2:2/YUV4:2:0 or RGB5:6:5/ARGB32 output.
– Supports YUV4:2:0 input data and YUV4:2:0
• YUV4:2:0 input format not supported natively
• Two passes required: luma followed by chroma or vice versa
• Only supported from memory to memory
– Supports RAW Bayer input and RAW Bayer output
• RAW format invariant. Takes whichever RAW format at the input and writes it out unmodified:
16 bits are read, 16 bits are written out.
• No resizing can take place on RAW data.
Resizer capabilities:
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
•
•
– Input image cropping
• Common for the two resizer engines: Same input data before and after cropping
• Supported on YUV4:2:2 and RAW data formats
• Supported on pass-through mode data path
• Supported on bypass mode data path
– Dual resizer engines: RSZ-A and RSZ-B
• Up to x20 upsampling and x1/4096 downsampling on both engines
• Up to 200-MHz pixel throughput on both resizer engines
• Programmable data rate control to smooth the peak memory bandwidth
– RSZ-A
• Horizontal resolution of up to 8K pixels on RSZ-A.
– RSZ-B
• Horizontal resolution of up to 8K pixels on resizer RSZ-B
– Independent Y and Cb/Cr phases on horizontal and vertical axis
• Enables to take care of different YUV4:2:0 phases used in different video formats
• Enables frame division mode: Images can be stitched together with the right phase.
– Rescaling: two modes supported
• Normal mode for upscale and downscale: Higher flexibility but lower downscale quality
• Downscale mode for downscale only: Lower flexibility but higher downscale quality
– Filtering: two modes supported
• Independent settings for the horizontal and vertical directions
• 3-tap low pass filter with 2-tap linear interpolation
• 4-tap cubic interpolation
– Flip support of the output image
• Horizontal flip
• Vertical flip
– Pixel duplication on the top/bottom, left/right sides
• Avoids losing pixels at the image boundaries because of the filtering
– Support pass-through and bypass modes: Resizer engines bypassed
• Pass-through mode
• RAW and YUV4:2:2 data support
• Lower power consumption mode to transfer data to memory
• Can transfer images larger than 8K pixels to memory
• Bypass mode
• RAW and YUV4:2:2 data support
• Input buffer used. Can benefit from additional buffering in case the BL module memory is not big
enough and back pressure occurs.
Slave data interface: VP interface
– Two VP interfaces: The programming model selects which VP is used to input data to the RSZ
module. Both VPs cannot be active simultaneously.
• VP 1: Typically connected to the IPIPE module.
• VP 2: Typically connected to the IPIPEIF module.
– Up to 200-MHz pixel clock
Master data interface:
– Two interfaces to the BL module
• Up to 200 MHz
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
367
ISS ISP
•
•
•
www.ti.com
• 32-bit wide, 32-byte long requests
• Accesses are aligned on 32-byte boundaries
• Used to transfer data to memory
• Each interface is dedicated to a single output image.
– Addressing modes
• Linear
• Circular
Configuration interface:
– Up to 100 MHz
– 32-bit wide
– Used to configure the resizer registers
Power management:
– Independent clock domains for the two resizers
• Each resizer engine can be gated off separately
Error management:
– FIFO overflow detection on the input buffers
Figure 190 show the RSZ module connections to other submodules of the ISP.
Figure 190. ISS ISP RSZ High-Level Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
camss-003c
3.3.4.2
ISS ISP RSZ Top-Level Block Diagram
Figure 191 is the top-level block diagram of the RSZ module. The RSZ module comprises the following
submodules: cropping, input data buffering, data requestor, averager, data saturation, and resizer
Interpolation (comprised of horizontal rescaler, vertical rescaler, color conversion, and output interface)
(see the following sections for more information).
368
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
The RSZ module comprises two independent resizer engines with the same capabilities (except for the
memory line size). The input data can come from VP 1 or VP 2. Software must determine and control
which interface is selected.
The RSZ module includes one VBUSP slave port, which is used to control the RSZ registers. It also
includes two MTC master ports, which are used to pass the pixels to the BL. The BL in turn creates the
burst requests to the memory subsystem (see Section 3.3.4.3, ISS ISP RSZ Interfaces).
Figure 191. ISS ISP RSZ Top-Level Block Diagram
Resizer bypass mode: RAW 16 bits and YUV 16 bits
YCbCr
16 bits
Horizontal
rescalers A
Averager B
Horizontal
rescalers B
rsz_fifo_in_ovf
Video
port1
IPIPE
Video
port2
Crop
Buffer
management
(3 x 5376 x 16b)
YCbCr
16 bits
Read
buffer
IPIPEIF
(Lines A) and
(Lines B)
YCbCr
16 bits
YCbCr
16 bits
WR IF 1
YCbCr
Vertical rescalers A
Color conversion
A
RGB
YCbCr
Memory lines B
(6 x 1168 x 16b)
Vertical rescalers B
Color conversion
B
Output interface
Memory lines A
(6 x 2688 x 16b)
Buffer logic
ISP IRQ
merger
Averager A
WR IF 2
RGB
Passthrough mode: RAW 16 bits and YUV 16 bits
camss-402
3.3.4.3
ISS ISP RSZ Interfaces
The RSZ module has the following data interfaces:
• One 32-bit read/write point-to-point pending VBUSP interface
• Two slave VP interfaces for transport YUV and RAW data
• Two MTC interfaces to BL for RZA A and RZA B, with only write capabilities
3.3.4.3.1
ISS ISP RSZ VBUSP interface
The VBUSP interface is a 32-bit read/write capable interface. The VBUSP interface must be programmed
in a way that back-to-back requests are possible for read and write. The RSZ_GCK_MMR[0] MMR bit
enables the memory register access from the VBUSP interface to enable transfer and signal such as
MMR request, direction, enable write/read data can be enabled.
3.3.4.3.2
ISS ISP RSZ Video Port Interfaces
The VP interfaces are slave interfaces; one is connected to IPIPE, and the other to IPIPEIF. These
interfaces are for data transfer. Table 178 lists the format supported across IPIPE/IPIPEIF and RSZ.
Signals coming from IPIPE and IPIPEIF can be write-enable signals. The RSZ_SRC_MODE[1] WRT bit is
set whether or not the write enable signals are considered. This is a line-valid qualifier. This signal is
sampled on the rising edge of HD, and the value is used for the full line.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
369
ISS ISP
www.ti.com
Table 178. ISS ISP RSZ VP Supported Formats
VP Signals: From IPIPE and IPIPEIF Modules (dat[15:0] Register)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RAW16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
YUV4:2:
2
16 bits
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7
Cr7
Cb6
Cr6
Cb5
Cr5
Cb4
Cr4
Cb3
Cr3
Cb2
Cr2
Cb1
Cr1
Cb0
Cr0
YUV4:2:
0
Y data
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Low
Low
Low
Low
Low
Low
Low
Low
YUV4:2:
0
Cb/Cr
data
Low
Low
Low
Low
Low
Low
Low
Low
Cb7
Cr7
Cb6
Cr6
Cb5
Cr5
Cb4
Cr4
Cb3
Cr3
Cb2
Cr2
Cb1
Cr1
Cb0
Cr0
NOTE: The formats are set from the IPIPE and IPIPEIF registers. For more information, see
Section 3.3.3 and Section 3.3.2.
3.3.4.3.3
ISS ISP RSZ MTC interfaces
The RSZ module includes two write-only MTC interfaces. Their implementation enables passing a
maximum of eight 32-byte requests in ten clock cycles. The RSZ must be programmed to obtain smooth
and average bandwidth to buffer logic module by setting a minimum interval between two successive
requests (set the RSZ_DMA_RZA[15:0] RZA and RSZ_DMA_RZB[15:0] RZB bit fields for the A and B
resizers as appropriate). This setting is not expected to be dynamic. It can be fixed setting from request to
request and frame to frame. When the bandwidth is set appropriately, between the first valid translated
pixel and the EOF signal sent to buffer logic, the RSZ_DMA_STA[0] STATUS bit can be seen, and it is
high if the transfer over the MTC interfaces is active. Figure 192 shows how RSZ_DMA_RZx for resizers A
and B affects the MTC data request generator.
Figure 192. ISS ISP RSZ MTC DMA Bandwidth Control
New request is prohibited for N clocks
RSZ CORE CLOCK
MTC REQUEST
1
MTC ENABLE
ADDRESS
WRITE DATA
2
3
4
5
7
6
8
a0
d0
a10
d1
d2
d3
d4
d5
d6
d7
a8
d0
d1
camss-680
Figure 193 shows the pixel order in memory written by the MTC. The arrows do not represent the order in
which data is written. Data are always written from left to right, whether horizontal reversal is enabled or
not.
370
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 193. ISS ISP RSZ MTC Image Data Storage Pixel Order
0
0
1
2
1
2
3
3
N–1
N–1
Normal
mode
Horizontal
reversal
N–1
N–1
3
2
3
2
1
0
1
0
Vertical
reversal
Horizontal and vertical
reversal
camss-684
3.3.4.4
ISS ISP RSZ Integration
Figure 194 shows how the VP and interfaces of the RSZ module are connected to surrounding modules at
the ISP level. The RSZ module gets data from the IPIPEIF module or IPIPE module.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
371
ISS ISP
www.ti.com
Figure 194. ISS ISP RSZ Typical Module Integration: High-Level Summary
IPIPE_MTC
W
IPIPE
ipipe_dat[15:0]
Video port
interface 1
RSZ_MTC1
W
ipipeif_wrt
ipipeif_hd
ipipeif_vd
ipipeif_dat[15:0]
ipipe_vd
ipipe_hd
ipipe_wrt
BL
RSZ
RSZ_MTC2
W
ipipeif_dat[15:0]
ipipeif_vd
ipipeif_hd
ipipeif_wrt
Video port
interface 2
IPIPEIF
IPIPEIF_MTC
R
camss-400
The following constraints apply to the RSZ module:
• The data coming from the IPIPEIF module can be RAW or YUV4:2:2 data. Because the RSZ module
can rescale only YUV4:2:2 data, the RSZ module must be configured in pass-through mode when
RAW data is received on VP 2. It is possible to bypass the RSZ engine, if YUV4:2:2 data is sent but
rescaling is not needed (bypass mode).
• The data coming from the IPIPE module can be RAW or YUV4:2:2 data. Eventually, YUV4:2:0 data
can be sent through this path, but the data must be sent in two passes. Because the RSZ module can
rescale only YUV4:2:2 data, the RSZ module must be configured in pass-through mode when RAW
data is received on VP 1. It is possible to bypass the RSZ engine if YUV4:2:2 data is sent but rescaling
is not needed (bypass mode).
VP 2 provides a way to bypass the IPIPE module when YUV4:2:2 data is received from the images sensor
or when YUV4:2:2 is read back from memory with the SC or ISIF module.
Table 179 summarizes the different RSZ configuration possibilities as a function of the input data format.
Table 179. ISS ISP RSZ Data Flow vs. Input Data Format Constraints
372
VP 1
Data Format
VP 2
Data Format
RSZ-A
Configuration
RSZ-B
Configuration
RAW
N/A
Disabled
Disabled
Comments
RSZ module in pass-though
mode
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 179. ISS ISP RSZ Data Flow vs. Input Data Format Constraints (continued)
3.3.4.5
VP 1
Data Format
VP 2
Data Format
RSZ-A
Configuration
RSZ-B
Configuration
N/A
RAW
Disabled
Disabled
RSZ module in pass-though
mode
YUV4:2:2
N/A
Disabled
Disabled
RSZ module in pass-though
mode or bypass mode
YUV4:2:2
N/A
Enabled
Disabled
One output image
YUV4:2:2
N/A
Disabled
Enabled
One output image
YUV4:2:2
N/A
Enabled
Enabled
Two output images
N/A
YUV4:2:2
Disabled
Disabled
RSZ module in pass-though
mode or bypass mode
N/A
YUV4:2:2
Enabled
Disabled
One output image
N/A
YUV4:2:2
Disabled
Enabled
One output image
N/A
YUV4:2:2
Enabled
Enabled
Two output images
Comments
ISS ISP RSZ Functional Description
To start up, the RSZ configuration can be set from the RSZ_SYSCONFIG register, which provides
enabling the RSZ-A and RSZ-B clocks. The RSZ module does not have standalone reset and status
check. Software reset must be done at the ISP level. Moreover, when enabled, the RSZ module can
control the input data buffer, and when the rsz_stall_input signals are set from the RSZ_IN_FIFO_CTRL
register (see Section 3.3.4.5.3.2.5), the RSZ module generates a stall signal that can be used by the
master module sending data to the RSZ module when the data threshold is too high.
The RSZ_SRC_EN[0] EN bit starts the resizer processing. If the processing mode is set to one shot (one
run and then turn off) from the RSZ_SRC_MODE[0] OST bit, the EN bit is cleared to 0.
The resizer can be configured to be bypassed in certain cases (see Figure 194 for the module constraints)
from the RSZ_SRC_FMT0[1] BYPASS bit. The data can be sent directly from here to the output interface
(bypass mode) or imported to the module buffer, but not manipulated and sent to the output interface
(pass-through mode). The master device sending data to the resizer can be switched between IPIPEIF
and IPIPE using the RSZ_SRC_FMT0[0] SEL bit. The resizer understanding of the data input is set from
the RSZ_SRC_FMT1 register (for more information, see Table 181). The RSZ_SEQ.VRVX and
RSZ_SEQ.HRVX registers can be set to flip the image horizontally or vertically, respectively (see
Figure 193).
Depending on the mode to which the resizer is set, the core clock can be enabled from the
RSZ_GCK_SDR register. Table 180 summarizes the behavior of the module for the different settings.
Table 180. ISS ISP RSZ Module Modes: Register Settings
Configu
ration
Number
0
RSZ_SR RZA_EN RZA_CL RZB_EN
C_ EN
K_ EN
0
X
X
X
RZB_
CLK_
EN
X
RSZ_GC RSZ_SR Comments
K_SDR. C_FMT0
CORE
.BYPAS
S
X
X
Data cannot go through the RSZ module.
Interrupts are not issued.
1
1
0
X
0
X
1
0
Resizer A is disabled.
Resizer B is disabled.
It is best to have RZA_EN = RZB_EN = 0
to save power, but RZA_EN = RZB_EN = 1
is also supported.
This configuration is supported but does
not make sense because data cannot go
through the module.
2
1
1
1
0
X
1
0
Resizer A is enabled.
Resizer B is disabled.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
373
ISS ISP
www.ti.com
Table 180. ISS ISP RSZ Module Modes: Register Settings (continued)
It is best to have RZB_EN = 0 to save
power, but RZB_EN=1 is supported as
well.
3
1
0
X
1
1
1
0
Resizer A is disabled.
Resizer B is enabled.
It is best to have RZA_EN = 0 to save
power, but RZA_EN = 1 is also supported.
4
1
1
1
1
1
1
0
Resizer A is enabled.
Resizer B is enabled.
5
1
X
X
X
X
0
0
6
1
X
X
X
X
0
1
Bypass mode is enabled.
Resizer core functional clock is disabled.
Pass-through mode enabled.
Resizer core functional clock is disabled.
7
1
X
X
X
X
1
1
Pass-through mode is enabled.
Resizer core functional clock is enabled.
Not a preferred configuration. Configuration
(6) saves power.
Table 181. ISS ISP RSZ Module Input Control: Register Settings
RSZ_SRC_FMT1.IN420
RSZ_SRC_FMT1.COL
0
X
Comments
YUV4:2:2 input. Chrominance is cosited.
1
0
YUV4:2:0 input. Valid data is Y, C is dummy. On the VP,
YUV4:2:2 data is always assumed.
1
1
YUV4:2:0 input. Valid data is C, Y is dummy. On the VP,
YUV4:2:2 data is always assumed.
The RSZ_YUV_PHS[0] POS bit sets the chrominance output. The RSZ module does not change the
relative position of the chroma samples versus the luma samples between the input and output, and the
chroma position at the output of the IPIPE module and at the output of the RSZ module must be identical.
In other words, RSZ_YUV_PHS.POS = IPIPE_YUV_PHS.POS.
Settings are common for both resizer engines inside the RSZ module. Each engine (RZA or RZB) can be
enabled from the RZx_EN register: select the mode from RZx_MODE, and select the input and output in
the YUV color scheme from the RZx_420 register (valid only if YUV 4:2:2 is the input set from
RSZ_SRC_FMT1.IN420). Table 182 summarizes the combination of settings available in the RZx_420
register.
Table 182. ISS ISP RSZ-A/RSZ-B Output Format Selection
3.3.4.5.1
RZx_420.YEN
RZx_420.CEN
Comments
0
0
Input is YUV4:2:2. Output is YUV4:2:2 if RZX_RGB_EN = 0 and RGB if
RZB_RGB_EN = 1.
0
1
Input is YUV4:2:2. Output is the chroma of YUV4:2:0. RZX_RGB_EN is
ignored. Must be used to rescale YUV4:2:0 data: 1st/2nd pass
1
0
Input is YUV4:2:2 .Output is the luma of YUV4:2:0. RZX_RGB_EN is ignored.
Must be used to rescale YUV4:2:0 data: 2nd/1st pass
1
1
Input is YUV4:2:2 .Output is YUV4:2:0. RZX_RGB_EN is ignored.
ISS ISP RSZ Operating Modes
The RSZ module offers two basic rescaling modes. These modes are not built-in but are particular
configurations, which means that other hybrid modes can be programmed. The normal mode provides
more flexibility (the rescale ratio granularity is smaller) than downscale mode, but downscale mode
produces better image quality (averager performs anti-aliasing):
374
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
•
•
Normal mode: The scaling process is carried out using interpolation with a 4-tap filter. The interpolation
method is a 4-tap cubic convolution or a 3-tap linear filter + 2-tap linear interpolation. The user controls
the type of interpolation that is used. The possible rescale ratios range from 1/16x to 20x.
Downscale mode: The scaling process is the same as for normal mode, but an averaging function is
placed before. It enables reaching much higher reduction factors while avoiding anti-aliasing artifacts.
The interpolation method is a 4-tap cubic convolution or a 3-tap linear filter + 2-tap linear interpolation.
The possible rescale ratios range from 1/4096x to 1x.
NOTE: The selection of the mode is independent for each resizer engine. One resizer engine can be
configured in normal mode, while another is configured in downscale mode.
The RSZ module can produce two output images simultaneously, because there are two independent
resizer engines. The input data used by the two resizer engines is the same. The RSZ output image sizes
are limited to RSZ_GNC[0:12] RSZA_MEM_LINE_SIZE pixels/line for RSZ-A (5376 pixels/line) and
RSZB_MEM_LINE_SIZE[16:28] for RSZ-B (2336 pixels/line).
Figure 195 shows the RSZ operating modes. Nothing prevents the use of linear interpolation in normal
mode or bicubic interpolation in downscale mode; similarly, it is possible to mix the interpolation modes for
horizontal and vertical filtering. This is fully programmable.
Figure 195. ISS ISP RSZ Operating Modes
Normal mode:
4-tap
interpolation(H)
Input
image
4-tap
interpolation(V)
Resize ratio = 256 /nH
with (16 = nH < 4096 )
Resize ratio = 256/n
with (16 = nV < 4096 )
Output
image
Downscale mode:
Input
image
Linear
filter
(H)
Averaging
(H/V)
1 /2n
with (0 < n < 8)
Linear
interpolation
(H)
256 /m H
with (256 < mH < 4096 )
Linear
filter
(V)
Linear
interpolation
(V)
Output
image
256 /m V
with (256 < mV < 4096 )
camss-401
3.3.4.5.1.1 ISS ISP RSZ Operating Modes and Maximum Input Clock
The maximum output pixel clock on both resizers is 200 MHz (100 percent optimal power performance
[OPP]); that is, a pixel throughput of 200 MPix/s. Moreover, hardware takes care of the following
constraints:
• When both resizer engines are configured to perform downscaling, there is no particular constraint on
the VP pixel clock. The VP pixel clock can be as high as 200 MHz.
• When one resizer engine is configured to perform upscaling and the second resizer engine is
configured to perform downscaling, the VP pixel clock must be limited. The VP must be lower than:
clk_pix = (200 MHz/(Vertical Upscale Ratio * Horizontal Upscale Ratio))
(4)
For example, if a 4x upscale ratio happens horizontally and vertically, then the input pixel clock must
be lower than 200/(4*4) = 12.5 MHz.
It is the reason why it is not possible to perform digital zoom upscaling on the fly. It is necessary to
acquire the pixels to memory first and to read them back at a pace that does not exceed the previously
discussed constraints. At the ISS level, data can be read back from memory from the SC or ISIF
module.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
375
ISS ISP
www.ti.com
•
When the two resizer engines are configured to perform upscaling, the VP pixel clock must be limited.
In that case, the VP frequency is limited by the resizer engine having the larger rescale ratios.
3.3.4.5.2
ISS ISP RSZ Input Data Cropper
The data coming from the VPs into the RSZ module can be cropped: this applies to RAW and YUV4:2:2
data. It is mandatory to crop the data as early as possible in the RSZ processing pipeline to reduce power
consumption. It is mandatory to crop the data before storing it in the input data buffer. Figure 196 is the
block diagram of the RSZ input data cropper.
Figure 196. ISS ISP RSZ Input Data Cropper Block Diagram
IPIPEIF
Video
port 1
Video
port 2
Crop
Input data cropper
Input buffer
Passthrough mode:
RAW 16 bits and YUV 16 bits
IPIPE
Output
interface
BL
RSZ
camss-708
The input data are in YUV4:2:2 interleaved format or RAW format.
For YUV4:2:2 format, the data come as Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc. Y denotes the luma
component value and Cb/Cr denotes the chroma component values. There are as many Y components as
Cb/Cr components per line.
Figure 197 shows input data cropping. Only the cropped data is stored in the input data buffer. The names
used in the figure correspond to the register names. If no cropping is desired, the RSZ_SRC_HPS and
RSZ_SRC_VPS registers, which set the horizontal and vertical positions, must be set to 0; the start size
from the RSZ_SRC_HSZ register must be set to the input image width minus 1, and the RSZ_SRC_VSZ
register must be set to the input image height minus 1. These are typical settings for both resize engines
inside the RESIZER. After setting, more flexibility is present through RZx_i_VPS and RZx_i_HPS for
vertical and horizontal positioning, respectively, of the input/output (where x = A or B, i = I or O).
Depending on the input data format, different constraints apply to the registers that set the cropping
parameters:
• For YUV4:2:2 format, the vertical start positions of the cropped frame can be even or odd. However,
the horizontal start position must be even: the reason is to always start with the same pattern: Cb2n,
Y2n, Cr2n, Y2n+1,.. For the same reason, the horizontal size of the cropped frame (RSZ_SRC_HSZ + 1)
must be an even number. Finally, the vertical size of the cropped frame can be odd or even.
• For RAW format, the vertical start position of the cropped frame can be even or odd. The vertical size
can be even or odd. The horizontal resolution must be even.
These features and constraints are common for both resizer engines inside the resizer module. Figure 197
shows the input data cropping.
376
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 197. ISS ISP RSZ Input Data Cropping
RSZ_SRC_HPS
RSZ_SRC_HSZ + 1
pixels
HS = Horizontal Synchro
RSZ_SRC_VPS
RSZ_SRC_VSZ + 1
lines
VS = Vertical Synchro
Cropped frame
Input frame
camss-403
3.3.4.5.3
ISS ISP RSZ Input Data Buffer
3.3.4.5.3.1 ISS ISP RSZ Input Data Buffer Overview
The input data buffering is used to store pixel data received from the cropping submodule as well as
changing clock domains.
• The data is written into the buffer at the pixel clock frequency: maximum frequency is 200 MHz
(remainder 100 percent OPP).
• The data is read from the buffer at the functional clock frequency: maximum frequency of 200 MHz
(remainder 100 percent OPP).
The data write period into the buffer is not constant. The period follows a typical image sensor frame
structure with intervals of data transmission and horizontal and vertical blanking periods (no data
transmission). Blanking periods must be used by the resizer engines to keep emptying the buffer if there is
data to process.
The data read period from the buffer is not constant because the resizer engines have to generate more
lines or less lines during the vertical processing of the image. This is to compensate for the fact that the
vertical resize ratio is set up by a fractional number. For every input line, the vertical resize process
outputs N or N + 1 lines, as described in the following sections.
3.3.4.5.3.2 ISS ISP RSZ Input Data Buffer Vertical Resize Examples
The following two examples show the number of output lines that the vertical resize process must
generate: in the first example N = 1, and in the second example N = 2.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
377
ISS ISP
www.ti.com
3.3.4.5.3.2.1 ISS ISP RSZ Input Data Buffer Vertical Resize Example 1
The horizontal rescale ratio is set to 1.0x, and the vertical upscale ratio is set to 1.1x (fractional number).
The resizer engine cannot output 1.1 lines; instead, at every 10 input lines, 11 output lines are generated.
The VP pixel clock must be limited to 200/1.1 = 181 MHz.
Table 183 summarizes the number of lines that the resizer must generate. The number of lines that must
be generated is not constant (1 or 2 lanes are output).
Table 183. ISS ISP RZA Input Data Buffering: Vertical Upscale Ratio = x1.1
Old Vertical Ratio
New Vertical Ratio
Vertical Resizer
(Cumulated)
Output lines
0
1.1
1
1.1
2.2
1
2.2
3.3
1
3.3
4.4
1
4.4
5.5
1
5.5
6.6
1
6.6
7.7
1
7.7
8.8
1
8.8
9.9
1
9.9
11
2
11
12.1
1
12.1
13.2
1
13.2
14.3
1
[ ... ]
[ ... ]
[ ... ]
Comments
floor(1.1) – floor(0.0) = 1
floor(11.0) – floor(9.9) = 2
3.3.4.5.3.2.2 ISS ISP RSZ Input Data Buffer Vertical Resize Example 2
The horizontal rescale ratio is set to 1.0x, and the vertical upscale ratio is set to 2.7x (fractional number).
The resizer engine cannot output 2.7 lines; instead, at every 10 input lines, 27 output lines are generated.
The VP pixel clock must be limited to 200/2.7 = 74 MHz.
Table 184 summarizes the number of lines that the resizer will have to generate. The number of lines that
must be generated is not constant (2 or 3 lanes are output).
Table 184. ISS ISP RZA Input Data Buffering: Vertical Upscale Ratio = x2.7
Old Vertical Ratio
378
New Vertical Ratio
Vertical Resizer
Comments
(Cumulated)
Output lines
0
2.7
2
floor(2.7) – floor(0.0) = 2
2.7
5.4
3
floor(5.4) – floor(2.7) = 3
5.4
8.1
3
floor(8.1) – floor(5.4) = 3
8.1
10.8
2
floor(10.8) – floor(8.1) = 2
10.8
13.5
3
13.5
16.2
3
16.2
18.9
2
18.9
21.6
3
21.6
24.3
3
24.3
27
3
27
29.7
2
29.7
32.4
3
32.4
35.1
3
[ ... ]
[ ... ]
[ ... ]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.4.5.3.2.3 ISS ISP RSZ Input Data Circular Buffer
Table 183 and Table 184 show that the output data rate varies within a frame. However, the input pixel
clock is always constant (except during blanking periods). Thus, a simple double-buffering scheme is not
sufficient because overflow would occur. Instead, the input data buffering block uses a triple buffer
mounted as a circular buffer.
Figure 198. ISS ISP RSZ-A/RSZ-B Input Data Buffering
HS
Signal
B0
5
1
6
B1
7
2
8
B2
3
WR
RD
0
1
0
2
4
0
1
2
1
2
2
0
0
1
2
1
2
2
0
1
camss-681
The size of the buffer line is the maximum of the RSZ_GNC[12:0] RSZA_MEM_LINE_SIZE and
RSZ_GNC[28:16] RSZB_MEM_LINE_SIZE bit fields.
3.3.4.5.3.2.4 ISS ISP RSZ Overflow Detection
Overflow can happen when a new line is to be written into the circular buffer but the destination is not
empty (all data has not been read out). This event can be also triggered in the same scenario but at the
RSZ master output interface FIFO. In this case the RSZ output data stall signal is asserted.
The RSZ_FIFO_OVF event is triggered in case of overflow.
3.3.4.5.3.2.5 ISS ISP RSZ Input Data Stalling
The input data buffering module generates a stall signal to prevent input FIFO overflow.
• The rsz_stall_input signal is asserted when the sum of the data in the input buffer FIFOs is greater
than or equal to a programmable FIFO threshold.
– The threshold is set up by the RSZ_IN_FIFO_CTRL[12:0] THRLD_HIGH bit field.
• The rsz_stall_input signal stays high as long as the sum of the data in the input buffer FIFOs is greater
than or equal to another programmable FIFO threshold.
– The threshold is set up by the RSZ_IN_FIFO_CTRL[28:16] THRLD_LOW bit field.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
379
ISS ISP
www.ti.com
The assertion of the rsz_stall_input signal does not ensure that no more data will be sent.
3.3.4.5.4
ISS ISP RSZ Data Requestor Module
The data requestor module reads the data from the circular buffer, synchronizes the resizer engines,
controls the vertical buffer switch, and updates the circular buffer counters.
Reads are asynchronous from writes. The data requestor module must be able to request pixels at a data
rate of 200 MPix/s with pixels coded on 16 bits.
The two resizer engines are synchronized on input lines boundaries, regardless of their setting
(downscale/downscale, upscale/upscale, or upscale/downscale). It means that the slowest resizer engine
determines the performance of the second resizer. The synchronization boundaries are highlighted in
Figure 199 (vertical lines).
• The data can be read and forwarded by the data requestor module to both resizers. That is typically
the case when the resizers are configured in downscale/downscale mode.
• The data can be read and forwarded by the data request module to one resizer only. In this case the
second resizer is stalled. That is typically the case when the resizers are configured in upscale/upscale
or upscale/downscale modes.
The data requestor must decrease the input buffer counters only when a given line is no longer needed.
For example, if a line needs to be used M times, the counter decrements the line counter only the last
time the line is needed. For every input line the vertical resizers send the data requestor the number of
output lines that will be output for the current line.
Figure 199 shows the data requestor behavior. Resizer A requests 2, 2, and 3 lines, and resizer B
requests 1, 1, and 2 lines. Obviously, resizer A stalls resizer B.
Figure 199. ISS ISP RSZ Data Requestor Module Behavior Example
Resizer engine
Sync boundary
Resizer A: data
Resizer A: switch control
Resizer B: data
Resizer B: switch control
Resizer engine
Sync boundary
Resizer engine
Sync boundary
Resizer engine
Sync boundary
Line 0
Line 0
Line 1
Line 1
Line 2
Line 2
Line 2
Switch A
opened
Switch A
closed
Switch A
opened
Switch A
closed
Switch A
opened
Switch A
opened
Switch A
closed
Line 0
No data
Line 1
No data
Line 2
Line 2
No data
Switch B
closed
Switch B
closed
Switch B
opened
Switch B
closed
Switch B
opened
Switch B
closed
Switch B
closed
Counter 0 level
Input
buffer
counters
Counter 1 level
Counter 2 level
camss-406
380
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.4.5.5
ISS ISP RSZ Averager
3.3.4.5.5.1 ISS ISP RSZ Use Cases
The two RSZ engines can have independent averager settings:
• Both resizers can use it.
• One resizer can bypass it and the other can use it.
• Both resizers can bypass it.
3.3.4.5.5.2 ISS ISP RSZ Memory Utilization
Vertical averaging requires memory to perform pixel data accumulation. It shares the vertical memory lines
that are used for vertical filtering: this is the reason why the vertical memory lines are organized as two
banks of half lines.
• The averagers output lines that are at most half the size of the input image in one memory bank.
• The horizontal resizers write their output data in the second memory banks.
Figure 200 shows the use of memory when the averager is enabled or disabled.
Figure 200. ISS ISP RSZ Averager Memory Utilization
Averager is enabled
½ BANK
INPUT
N pixels/line
½ BANK
AVG
MEM
H RSZ
MEM
Minimum
downscale
factor is 2x
Maximum line
size is N/2
Maximum line
size is N/2
1 line
required
3 lines
required
V RSZ
OUTPUT
Averager is disabled
2 x ½ BANK
INPUT
N pixels/line
H RSZ
MEM
V RSZ
OUTPUT
Maximum line
size is N
3 lines
required
camss-407
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
381
ISS ISP
www.ti.com
3.3.4.5.5.3 ISS ISP RSZ Border Conditions
Figure 201 shows the averager behavior for border conditions. If the input image is not big enough, border
duplication must occur.
Figure 201. ISS ISP RSZ Averager Border Conditions
Image horizontal size before downscaler
Downscaler window
Height
Downscaler window
Image vertical size before downscaler
Width
camss-408
Downscaling is enabled from the RZi_DWN_EN register. Moreover, the vertical averaging size is set by
the RZA_DWN_AV[3:5] V bit field. The actual downscale ratio is given by 1/2 (RZA_DWN_AV[3:5] V +1). The range
is from 1/2 to 1/256 in power of 2. The horizontal averaging size is set by the RZA_DWN_AV[0:2] H bit
field. The actual downscale ratio is given by 1/2 (RZA_DWN_AV[3:5] H +1) . The equations are the same for RSZ-B.
The range goes from 1/2 to 1/256 in power of 2.
3.3.4.5.6
ISS ISP RSZ Interpolation
Figure 202 shows the basic interpolation method used in the RESIZER module. The following
assumptions are made:
• The distance between each input pixel is 1.
• The magnification ration is given by 256/N and p/256 is the initial phase of the output data.
The output pixels are also evenly spaced. The distance between each output pixel is given by N/256. In
the example in Figure 202, N is greater than 256. The position of the nth output pixel is given by (n x N +
p) / 256.
382
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 202. ISS ISP RSZ Basic Interpolation Method
1
1
1
1
1
Input pixels
i0
i1
[…]
in–1
in
in +1
Output pixels
o0
p/256
o1
on–1
o2
N/256
on
N/256
N/256
x n = (n x N + p) / 256
camss-682
Assuming the intensity of input pixels is i0, i1, i2, etc. and the resized (output) pixels are o0, o1, o2, etc., the
nth output pixel (on) is determined using the nearest 4 input pixels as follows:
on = h(1+d) x i1 + h(d) x im + h(d-1) x im+1 + h(d-2) x im+2
In the previous equation h(x) is the interpolation main function. The RESIZER module supports linear and
bicubic convolution interpolation functions.
Figure 203 shows the interpolation principle at the nth output pixel (on) at position xn. Furthermore, the m
and d parameters are as follows:
m = floor((n x N + p) / 256) and d = ((n x N + p) / 256) – m
Figure 203. ISS ISP RSZ Interpolation Filtering
1
1
Om–1
1
Om
On–1
Om +1
On
Om +2
On +1
d
Xn= (n x N + p) / 256
camss-683
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
383
ISS ISP
www.ti.com
For each resizer (RSZ-A or RSZ-B), and for chrominance and luminance, the interpolation method for
vertical interpolation can be a 2-tap linear interpolation or a 4-tap cubic convolution (default) method. The
choice is made in RZi_V_TYP[0] Y for luminance and RZi_V_TYP[1] C for chrominance, where i = A or B
and is the resizer number. It is similar for horizontal interpolation from RZi_H_TYP[0] Y for luminance and
RZi_H_TYP[1] C for chrominance, where i = A or B and is the resizer number.
3.3.4.5.6.1 ISS ISP RSZ Liner Interpolation Input Data
Before data interpolation, a low pass filtering (LPF) operation is required on the input data. The following
equation gives the LPF function. The equation is evaluated at pixel position di but neighbor pixels di-1 and
di+1 are required. The gain value g is set up by the register RZi_V_LPF and RZi_H_LPF. Different gains
are possible horizontally and vertically as well as for Luma and Chroma.
LPFg (di-1, di, di+1) = di + g x (di-1 - 2di+1 + di+2)/128
3.3.4.5.6.1.1 ISS ISP RSZ Cubic Convolution Mode
The input data is not modified in bicubic mode. Basically, the input is equal to the output.
3.3.4.5.6.1.2 ISS ISP RSZ Phase Settings
The initial value for the phase value for vertical resizing is set by the RZi_V_PHS_Y for luminance and
RZi_V_PHS_C for chrominance. These values are in the U14Q8 fractional format (values in the range [0 –
63.996]). When YUV4:2:2 data are output, the phase value for Luma and Chroma must be aligned; that is,
RZi_V_PHS_Y = RZi_V_PHS_C.
The following constraint equation applies: | RZi_V_PHS_Y - RZx_V_PHS_C | = RZi_V_DIF. This
constraint means that at most the distance between the initial phases for luminance and chrominance is
not expected to exceed the distance between two Luma pixels. The absolute value is used; therefore, the
initial Luma phase can be greater than the initial Chroma phase or vice versa. As a reminder, the distance
between two output pixels for Luma is given by RZi_V_DIF.
The initial value for the phase value for horizontal resizing is set by the RZi_H_PHS bit field. The
RZi_H_PHS_ADJ register enables adjusting the horizontal phase for the Luma component when
averaging is enabled (the averager disrupts the relative sampling point between luminance and
chrominance when YUV4:2:2 cosited data is input). The relative phase between Luma and Chroma is
different before and after the horizontal averager. The vertical phase is not affected by the averager.
Figure 204 shows the effect of the averager on the phases. RZi_H_PHS_ADJ is expected to be equal to
zero if the averager is disabled.
384
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 204. ISS ISP RSZ-A/RSZ-B Phase Averager Effect
Input Chroma is co-sited: relative input I/O phases btw Y and UV are different, correction is needed.
Input Luma and Chroma before averager
Output Luma and Chroma after averager
Input Chroma is centered: relative input I/O phases btw Y and UV are identical, no correction is needed.
Input Luma and Chroma before averager
Output Luma and Chroma after averager
camss-685
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
385
ISS ISP
www.ti.com
3.3.4.5.7
ISS ISP RSZ Data Saturator
After vertical rescaling and before color conversion, the output data is saturated (clipped) to programmable
values that are given by the following registers:
• RSZ_YUV_Y_MIN
• RSZ_YUV_Y_MAX
• RSZ_YUV_C_MIN
• RSZ_YUV_C_MAX
The maximum Y value is set up with the RSZ_YUV_Y_MAX register. If the Input Y value is greater than
the MAX value, it is clipped to MAX.
The minimum Y value is set up with the RSZ_YUV_Y_MIN register. If the Input Y value is smaller than the
MIN value, it is clipped to MIN.
The maximum Cb/Cr value is set up with the RSZ_YUV_C_MAX register. If the Input Cb/Cr value is
greater than the MAX value, it is clipped to MAX.
The minimum Cb/Cr value is set up with the RSZ_YUV_C_MIN register . If the Input Cb/Cr value is
smaller than the MIN value, it is clipped to MIN.
3.3.4.5.8
ISS ISP RSZ Color Convertor
As mentioned previously, the resizer can support RAW, YUV4:2:0, and YUV4:2:2 formats. The resizer
engines can also support RGB output: RGB5:6:5 and ARGB32.
The RGB5:6:5 data is 16 bits wide and consists of 5 bits for red, 6 bits for green, and 5 bits for blue.
The following table shows the way RGB5:6:5 is stored to memory. This data format is compatible with the
display controller. Only the little-endian memory representation is supported.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R1
G1
B1
9
8
R0
7
6
5
4
3
G0
2
1
0
B0
The ARGB32 data is 32 bits wide and consists of 8 bits for alpha, 8 bits for red, 8 bits for green, and 8 bits
for blue. The alpha value is global and is set for the entire frame; registers control the alpha value: the
RZx_RGB_BLD register controls the alpha values of resizer A and resizer B.
The following table shows the way ARGB32 is stored to memory. This data format is compatible with the
display controller. This representation is endiannism invariant: it is the same for little endian and big
endian.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A
R
9
8
G
7
6
5
4
3
2
1
0
B
The RGB output is enabled by setting the RZx_RGB_EN[0] RGB_EN bit to 1.
The RGB format is set by the RZx_RGB_TYP[0] TYP bit (0 for ARGB32 format and 1 for RGB5:6:5).
To handle the horizontal border conditions, the leftmost Chroma sample or the right-most Chroma sample
is duplicated on the left or the right.
Software must make it possible to remove 2 pixels on the left and/or right to take care of the issues that
Chroma duplication introduces on the borders. The RZx_RGB_TYP[1] MSK0 and RZx_RGB_TYP[2]
MSK1 bits control this feature.
386
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 205. ISS ISP RSZ Chroma Position and Upsampling
Co-sited chroma position:
Luma: Y
even
odd
even
odd
even
odd
even
odd
even
odd
even
odd
Chroma: Cr/Cb
Centered chroma position:
Luma
Chroma: Cb/Cr
camss-409
3.3.4.5.9
ISS ISP RSZ Output Interface
The output interface receives the data generated by the two resizer engines and generates the addresses
and the port requests to the BL module.
• The port 1 interface is dedicated to the RSZ-A module. If the RSZ module is set up in pass-through
mode, then the data is output on the port 1 interface. This interface can transfer RAW, YUV4:2:2,
YUV4:2:0 and RGB data
• The port 2 interface is dedicated to the RSZ-B module. This interface can transfer RAW, YUV4:2:2,
YUV4:2:0 and RGB data.
The YUV4:2:0 data format is handled differently from the other formats because the output data are
written at two different memory locations: luminance in one buffer and chrominance in a second buffer.
For all other formats the data are written in the same buffer.
Each data format must be stored in memory in a dedicated manner, which is summarized in Table 185.
Table 185. ISS ISP RSZ Output Interface: Data Formats
Output Format
Bytes per Pixel
Output Buffers per Image
RAW
2
1
MTC port 1
YUV4:2:2
2 average
1
MTC port 1 port 2
YUV4:2:0
1.5 average
2
MTC port 1 port 2
RGB16
2
1
MTC port 1 port 2
ARGB32
4
1
MTC port 1 port 2
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Interface Supporting the Data Format
387
ISS ISP
www.ti.com
3.3.4.5.9.1 ISS ISP RSZ Circular Buffer
Figure 206 shows the parameters that are required to set up the circular buffers. As mentioned previously,
there can be up to four circular buffers in case the two resizer engines are outputting YUV4:2:0 data.
The circular buffer management requires the following parameters (REZ-A or RSZ-B A or B ,chrominance
or luminance Y or C, low or high part of the address, L or H. Sets the base address of the circular buffer):
• Baseline address (BAD, in registers, where x is the resizer A or B, and i is Y or C)
• Start address (SAD, in RZx_SDR_i_SAD_j registers)
• Start pointer (PTR_S, in RZx_SDR_i_PTR_S registers)
• End pointer (PTR_E, in RZx_SDR_i_PTR_E registers)
• Line offset (OFT, in RZx_SDR_i_OFT registers)
Circular Buffer Parameter
Baseline address
Register (for RSZ-A and RSZ-B)
RZA_SDR_Y_BAD_H
Description
Sets the base address of the circular buffer
RZA_SDR_Y_BAD_L
RZA_SDR_C_BAD_H
RZA_SDR_C_BAD_L
RZB_SDR_Y_BAD_H
RZB_SDR_Y_BAD_L
RZB_SDR_C_BAD_H
RZB_SDR_C_BAD_L
Start address
RZA_SDR_Y_SAD_H
RZA_SDR_Y_SAD_L
RZA_SDR_C_SAD_H
RZA_SDR_C_SAD_L
Sets the start address of the circular buffer. The
first data output is written to this address. If the first
line of a frame must be written at the beginning of
the circular buffer memory, then SAD = BAD and
PTR_S = 0.
RZB_SDR_Y_SAD_H
RZB_SDR_Y_SAD_L
RZB_SDR_C_SAD_H
RZB_SDR_C_SAD_L
Start pointer
RZA_SDR_Y_PTR_S
RZA_SDR_C_PTR_S
RZB_SDR_Y_PTR_S
Sets the initial value of the circular buffer internal
counter. It must be set up as PTR_S = (SAD BAD)/OFT. PTR_S is expressed in the number of
lines.
RZB_SDR_C_PTR_S
End pointer
RZA_SDR_Y_PTR_E
RZA_SDR_C_PTR_E
Sets the size of the circular buffer. PTR_E is
expressed in the number of lines. The circular
buffer can contain up to PTR_E lines.
RZB_SDR_Y_PTR_E
RZB_SDR_C_PTR_E
Line offset
RZA_SDR_Y_OFT
RZA_SDR_C_OFT
RZB_SDR_Y_OFT
RZB_SDR_C_OFT
This is the offset expressed in bytes between two
lines in the circular buffer. Here: Line 0 = SAD,
Line 1 = SAD + 1 x OFT, Line 2 = SAD + 2 x OFT,
etc. OFT does not necessarily correspond to the
size of a line in a frame; it can be bigger.
More generally, the following equations hold:
• SAD = BAD + (PTR_S x OFT) and PTR_S PTR_E
Interrupts can be triggered every time a certain number of lines are written to the circular buffer. There are
independent settings for each resizer and for each possible output of each resizer.
388
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 206. ISS ISP RSZ and Circular Buffer Settings
OFT
System memory
(DRAM or RAM)
Baseline address
BAD
Circular buffer
memory
SAD
Start address
PTR_S
PTR_E
End address
camss-410
Figure 207 shows how the data are stored in the circular buffer over time when vertical flip is disabled. In
this example, PTR_S = 5 and PTR_E = 7. There can be up to PTR_E = 7 lines in the circular buffer.
Figure 207. ISS ISP RSZ and Circular Buffer Settings – Example 1
OFT
OFT
PTR_S = 5
BAD
SAD
LINE 4
LINE 5
SAD
LINE 0
LINE 2
LINE 3
LINE 1
LINE 6
PTR_E = 7
BAD
LINE 7
LINE 8
Vertical flip enabled:
1. Start from SAD.
2. Output PTR_E – PTR_S lines.
3. Wrap to BAD.
4. Output PTR_E lines and continue wrapping to BAD.
camss-412
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
389
ISS ISP
www.ti.com
Figure 208 shows how the data are stored in the circular buffer over time when vertical flip is enabled. In
this example, PTR_S = 5 and PTR_E = 7. There can be up to PTR_E = 7 lines in the circular buffer.
Figure 208. ISS ISP RSZ and Circular Buffer Settings – Example 2
OFT
OFT
LINE 1
LINE 0
LINE 10
LINE 9
LINE 8
LINE 7
SAD
BAD
PTR_E = 7
LINE 3
LINE 2
SAD
LINE 11
PTR_S = 5
LINE 4
LINE 6
LINE 5
BAD
Vertical flip enabled:
1. Start from SAD.
2. Output PTR_E – PTR_S lines.
3. Wrap to BAD.
4. Output PTR_E lines and continue wrapping to BAD.
camss-413
390
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.5
ISS ISP H3A Functional Description
3.3.5.1
ISS ISP H3A Overview
The H3A module supports the control loops for autofocus, auto white balance, and auto exposure by
collecting metrics about the imaging/video data. The metrics are used to adjust parameters for processing
the imaging/video data. There are two main blocks in the H3A module:
• Autofocus (AF) engine:
The AF submodule extracts and filters the red, green, and blue data from input image data and
provides the accumulation or peaks of the data in a specified region. The specified region is a 2D block
of data referred to as a paxel. The AF engine supports the following features:
– Peak mode in a paxel
• Accumulation of the maximum focus value (FV) of each line in a paxel
– Accumulation mode in a paxel
– Accumulation of horizontal and vertical focus value in a paxel
– Up to 12 paxels in the horizontal direction and up to 12 paxels in the vertical direction with vertical
focus
– Up to 36 paxels in the horizontal direction and up to 128 paxels in the vertical direction with
horizontal focus only
– Programmable width and height for the paxel/window
– Programmable red, green, and blue position within a 2 × 2 matrix
– Separate horizontal start for paxel and filtering
– Programmable vertical and horizontal line increments within a paxel
– Horizontal FV uses parallel infinite impulse response (IIR) filters configured in a dual-biquad
configuration with individual coefficients (two filters with 11 coefficients each). The filters are
intended to compute the sharpness/peaks in the frame to focus on.
– Vertical FV uses a 5-tap FIR filter with 8-bit coefficients. With horizontal steps each paxel has up to
32 columns to be maintained for vertical FV calculation.
• Auto exposure and auto white balance (AE/AWB) engine:
The AE/AWB engine accumulates values and checks for saturated values in a subsampling of the
video data. In the case of the AE/AWB, the 2D block of data is referred to as a window. Thus, other
than having different names, paxels and windows are essentially the same. However, the numbers,
dimensions, and starting positions of AF paxels and AE/AWB windows are programmable separately.
AE/AWB supports the following features:
– Accumulate clipped pixels along with all nonsaturated pixels in each window per color
– Accumulate the sum of squared pixels in each window per color
– Minimum and maximum pixel values in each window per color
– Supports for up to 36 horizontal windows with sum + { sum_sq or min+max} output
– Support for up to 56 horizontal windows with sum output
– Support for up to 128 vertical windows
– Programmable width and height for the windows. All windows in the frame are the same size.
– Separate vertical start coordinate and height for a black row of paxels that is different than the
remaining color paxels
– Programmable horizontal sampling points in a window
– Programmable vertical sampling points in a window
• Maximum pixel throughput of 200 MPix/s
• Double-buffer for paxel/window accumulation
• H3A data path is 10 bits.
• Maximum input size is 3008 pixels.
Figure 209 shows the H3A module connections to other submodules of the ISP.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
391
ISS ISP
www.ti.com
Figure 209. ISS ISP H3A High-Level Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
camss-003b
3.3.5.2
ISS ISP H3A Top-Level Block Diagram
The block diagram in Figure 210 shows the process of the AF and AE/AWB data paths through the H3A
module.
The data flow before H3A is:
1. Data comes from the VP (VP) or BL.
2. The data is processed by the ISIF.
3. The data is processed by the IPIPEIF.
4. The data is 10 bits from the IPIPEIF at H3A input.
Figure 210. ISS ISP H3A Top-Level Block Diagram
AF
Preprocessing
IIR
Median
filter
A-Law
Local
memory
Horizontal Fv
RGB
pixel
extraction
Vertical Fv
FIR
IPIPEIF
HFV
accumulator
Thresh
VFV
accumulator
Thresh
A-Law
10 bits
Local
memory
control
Buffer
logic
10 bits
AE/AWB
Median
filter
A-Law
Down
sampling
Saturation
check
Paxel
accumulator
camss-067
392
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.5.3
ISS ISP H3A Line Framing Logic
In certain cases the number of clock cycles between HD pulses is greater than the line buffer included in
the H3A. To solve this problem a framing module was added before the line buffer. The framing module
uses the H3A_LINE_START register to find the position of the first pixel to place into the line buffer. All
other registers reference this point as the 0 pixel for their start positions. The line size is 3008 pixels. After
3008 clock cycles the framing logic disables the line buffer and waits until the next HD. If the next HD
comes before 3008 clock cycles, then the active region ends immediately and the counter waits for the
H3A_LINE_START register count to be reached again. For the vertical position the
H3A_LINE_START[31:16] SLV bit field can be used to determine where the start point of the frame is
relative to the rising edge of VD. This logic allows for an active frame to cross VD boundaries and remain
in the same frame.
Figure 211. ISS ISP H3A Frame Format Settings
HDW
HD
Frame width on VP
VD
VDW
H3A_LINE_START[31:16] SLV
H3A_LINE_START[15:0] LINE_START
Frame
height
on VP
Input frame on H3A
Global
frame
camss-073
NOTE: (Frame width on VP) - (H3A_LINE_START[15:0] LINE_START) must be less than or equal
to 3008, because the H3A memory lines are limited to 3008 pixels.
3.3.5.4
ISS ISP H3A Optional Preprocessing
The input to the H3A module is 10-bit RAW data from the IPIPEIF. A 10-bit to 8-bit A-Law compression
step can be enabled and disabled separately for the AF engine (the H3A_PCR[1] AF_ALAW_EN bit) and
the AE/AWB engine (the H3A_PCR[17] AEW_ALAW_EN bit). A-Law compression offers added protection
against overflowing the accumulators.
If the A-Law table is enabled, the output is 10 bits, with the upper two bits filled with 0.
For the AF process, a horizontal median filter can be enabled and disabled (the H3A_PCR[2]
AF_MED_EN bit) before A-Law compression. This filter is useful for reducing temperature-induced noise.
The horizontal median filter calculates the absolute difference between the current pixel (i) and pixel (i –
2), and between the current pixel (i) and pixel (i + 2). If the absolute difference exceeds a threshold, and
the sign of the differences is the same, the average of pixel (i – 2) and pixel (i + 2) replaces pixel (i). The
threshold of the horizontal median filter can be set in the H3A_PCR[10:3] MED_TH bit field.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
393
ISS ISP
3.3.5.5
www.ti.com
ISS ISP H3A Autofocus Engine
The AF engine works by extracting each green (Gr or Gb) pixel from the video stream and subtracts a
fixed offset of 128 or 512 (depending of whether A-Law is enabled or disabled) from the pixel value. The
offset value is then passed through an IIR filter and the absolute value of the filter output is the focus
value (FV). Both FV and FV2 are produced. The FV and FV2 values can be accumulated or the maximum
for each line/column can be accumulated. The following sections describe this process in more detail.
3.3.5.5.1
ISS ISP H3A Paxel Extraction
From the paxel starting coordinate (the H3A_AFPAXSTART[27:16] PAXSH and H3A_AFPAXSTART[11:0]
PAXSV bit fields) specifies the starting point of the paxel grid, with respect to first pixel of th input image
frame.
The paxel starting coordinate also indicates which color pixels are extracted if VF is enabled (that is, if
H3A_PCR[20] AF_VF_EN = 1). Normally, either Gr or Gb is used for AF, but it is not important to the
hardware whether it is red, green, or blue. If VF is not enabled, then the red, green, and blue pixel
extraction is controlled by the H3A_PCR [13:11] RGBPOS bit field to extract the correct colors from the
input stream. Figure 213 shows the available options for this bit field. The red and blue pixel positions are
interchangeable. For each 2 × 2 grid, the green pixels are summed to create a single value. Because of
this, the amplitude of the green output contains 2 pixels, while the red and blue outputs each contain 1
pixel.
Figure 212. ISS ISP H3A Red, Green, and Blue Pixel Extraction Examples
Input
Output
green
Output
red
Output
blue
G
R
G
G
B
G
R
G
G
B
G
G
R
G
B
G
G
R
G
G
B
G
G
G
G
R
B
R
B
R
B
R
B
G
G
R
B
G
G
G
RGBPOS=0x0
R
B
RGBPOS=0x1
R
B
RGBPOS=0x2
R
B
RGBPOS=0x3
G
RGBPOS=0x4
G
RGBPOS=0x5
camss-068
394
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Each paxel is H3A_AFPAX1[23:16] PAXW × H3A_AFPAX1[7:0] PAXH (width × height) pixels. Inside each
paxel, horizontal FV can skip lines, operating on one every H3A_AFPAX2[16:13] AFINCV lines. Vertical
FV can skip columns, operating on one every H3A_AFPAX2[20:17] AFINCH columns. Up to 32 columns
are supported for each paxel. If floor (PAXW/AFINCH) = 32, only the first 32 designated columns are
operated on. Because PAXW, PAXH, AFINCV, and AFINCH are all even numbers, AF always operates
on the same green color, Gr or Gb. IIR filters for the horizontal FVs start operation at column
H3A_AFIIRSH[11:0] IIRSH.
Figure 213. ISS ISP H3A Horizontal/Vertical FV Paxel Configuration
PAXHC
PAXSV
PAXW
PAXSH
PAXH
AFINCH
PAXVC
IIRSH
AFINCV
Input frame on H3A
camss-071
NOTE: (H3A_AFPAXSTART [27:16] PAXSH) + (H3A_AFPAX2 [5:0] PAXHC) ×
(H3A_AFPAX1[23:16] PAXW) = [(Frame width on VP) – (H3A_LINE_START[15:0]
LINE_START)] = 3008
Table 186 lists the register fields that configure the size and number of paxels.
Table 186. ISS ISP H3A Paxel Register Field Descriptions
Register Field
Bit Width
Description
H3A_AFPAX1[23:16] PAXW
8
Paxel width (in pixels)
H3A_AFPAX1[7:0] PAXH
8
Paxel height (in lines)
H3A_AFPAX2[5:0] PAXHC
6
Paxel count for horizontal direction
H3A_AFPAX2[12:6] PAXVC
7
Paxel count for vertical direction
H3A_AFPAX2[16:13] AFINCV
4
Line increments in a paxel
H3A_AFPAX2[20:17] AFINCH
4
Column increments in a paxel
H3A_AFPAXSTART[27:16] PAXSH
12
Paxel start position H
H3A_AFPAXSTART[11:0] PAXSV
12
Paxel start position V
H3A_AFIIRSH[11:0] IIRSH
12
IIR filter start position
The H3A AF engine also has an option for an advanced or normal stats collection mode. When 0xCA00 is
written to the H3A_ADVANCED[31:15] ID bit field, then H3A_ADVANCED[0] AF_MODE can be used to
toggle between normal and advanced AF stats collection mode. When the advanced AF stats collection
mode is enabled, the ZEROS section of the AF paxel packet is filled with the sum of the maximum FVs,
regardless of the color, from HFV_1 and HFV_2.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
395
ISS ISP
www.ti.com
3.3.5.5.2
ISS ISP H3A Horizontal FV Calculator
The FV calculator takes the unsigned red/green/blue extracted data and subtracts 128 or 512 (depending
on whether A-Law is enabled) to place the data in the range [–128:127] or [–512:511].
After removing the offset, the data is sent through two parallel IIR filters configured in a dual-biquad
configuration. Each filter uses a unique set of 11 programmable coefficients. Each coefficient is 12-bitswide with 6 bits of decimal, S12Q6 (H3A_AFCOEF010 to H3A_AFCOEF0010 for SET0, and
H3A_AFCOEF110 to H3A_AFCOEF1010 for SET1). The filter-shift registers are cleared on each
horizontal line at the position set by the register IIR horizontal start register (the H3A_AFIIRSH [11:0]
IIRSH bit field). The absolute values of the output (16-bits-wide with 4 bits of decimal, U16Q4) of both
filters are then sent to the AF accumulator module. Signed clipping is performed during the FV calculation.
If the input value is m bits (signed) and the required output value is n bits, clipping transforms the input to
between –21 and 21. Values lower than –21 are set to –21, and values higher than 21 are set to 21.
Figure 214 shows the IIR filter model.
Figure 214. ISS ISP H3A IIR Filter Model
Filter Out
IIROUT_1
Filter In
Coeff 0
Coeff 8
Coeff 3
Clip
Clip
Clip
Clip
Filter Out
IIROUT_2
S17Q0
Coeff 1
Coeff 2
Z
–1
Coeff 4
Z
Coeff 6
Z
–1
–1
Coeff 5
Coeff 9
Z
–1
Coeff 10
Coeff 7
camss-069
3.3.5.5.3
ISS ISP H3A HFV Accumulator
The horizontal focus value (HFV) accumulator takes the output of the horizontal IIR filter and accumulates
values for each paxel. The size and number of paxels is configurable by registers.
Table 186 lists the register fields that configure the size and number of paxels:
• In peak mode (H3A_PCR[14] FVMODE = 0x1), the maximum value is accumulated.
• In sum mode (H3A_PCR[14] FVMODE = 0x0), all HFV_n are accumulated in a paxel.
The following equations detail the calculation for:
• Sum of pixel values used in HFV: The pixel values that are used for filtering and accumulation of HFV
are also accumulated in this sum of pixel values.
• HFV_n (HFV_n_peak for peak mode or HFV_n_sum for sum mode)
• HFV_count_n
• HFV_sq_n (HFV_sq_n_peak for peak mode or HFV_sq_n_sum for sum mode)
n = 1 or 2 for IIR1 and IIR2, respectively.
For each paxel, these six values are available for each R, G, and B component.
for
(k=0; k<PAXH; k++) // Loop on paxel rows
{
rowpeak_n = 0;
for (l=0; l<PAXW; l++) // Loop on values within a row
{
396
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
aIIRout_n = ABS(IIRout_n);
if (aIIRout_n >= threshold_n)
{
hfval = aIIRout_n - threshold_n;
HFV_count_n++;
}
else hfval = 0;
if (hfval > rowpeak_n)
{
rowpeak_n = hfval;
}
HFV_n_sum += hfval;
HFV_sq_n_sum += (hfval* hfval + RNDADD)>> RNDSHIFT;
} // Finished looping on values in a row
HFV_n_peak += rowpeak_n;
HFV_sq_n_peak += (rowpeak_n * rowpeak_n + RNDADD)>> RNDSHIFT;
}
•
•
•
•
•
•
•
3.3.5.5.4
threshold_n is H3A_HVF_THR[15:0] HTHR1and H3A_HVF_THR[31:16] HTHR2, respectively.
IIRout_n is the IIRout_1 and IIRout_2 outputs, respectively.
HFV_count_n and HFV_sq_n are not sent to the DMA interface if VF is disabled.
RNDADD and RNDSHIFT depend on whether input pixels are 8-bit or 10-bit, and achieves rounding.
This is automatically performed by the module.
If VF is enabled, only the green color channel values are output to the DMA interface.
In sum mode:
– HFV_n = HFV_n_sum
– HFV_sq_n = HFV_sq_n_sum
In peak mode:
– HFV_n = HFV_n_peak
– HFV_sq_n = HFV_sq_n_peak
ISS ISP H3A VFV Calculator
The VFV calculator takes the unsigned extracted data through two FIR filters, each with a set of five
coefficients (VCOEF1_x, where x = 0..4, in the H3A_VFV_CFG1 and H3A_VFV_CFG2 registers for FIR 1,
and VCOEF2_x, where x = 0..4, in H3A_VFV_CFG3 and H3A_VFV_CFG4 registers). Each coefficient is 8
bits wide with 4 bits of decimal (S8Q4). The filter outcome is downshifted by 4 bits and taken absolute
value to produce a 16-bit unsigned value. This is then sent to threshold H3A_VFV_CFG2[31:16] VTHR1
for FIR 1, and H3A_VFV_CFG4[31:16] VTHR2 for FIR 2, and square logic to produce VFV_n and
VFV_sq_n.
3.3.5.5.5
ISS ISP H3A VFV Accumulator
The VFV accumulator takes the output of the vertical FIR filters and accumulates values for each paxel.
The size and number of paxels is configurable by registers.
Table 186 lists the register fields that configure the size and number of paxels.
The following equations detail the calculation for:
• VFV_n
• VFV_count_n
• VFV_sq_n
n = 1 or 2 for FIR1 and FIR2, respectively.
For each paxel, these six values are available for each R, G, and B component.
FIR_coef_n = [VCOEFn_0, VCOEFn_1, VCOEFn_2, VCOEFn_3, VCOEFn_4]; /* coefficient values in S8.4
format */
aFIRout_n = (ABS(inner_product(extracted_G, FIR_coef_n)) + 8) >> 4;
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
397
ISS ISP
www.ti.com
if (aFIRout_n ≥ threshold_n)
{
VFV_n = aFIRout_n - threshold_n
VFV_count_n++;
}
else VFV_n = 0;
VFV_sq_n = (VFV_n * VFV_n + RNDADD) >> RNDSHIFT;
•
•
•
3.3.5.6
threshold_n is H3A_VFV_CFG2[31:16] VTHR1 and H3A_VFV_CFG4[31:16] VTHR2, respectively.
FIRout_n is the FIRout_1 and FIRout_2 outputs, respectively.
RNDADD and RNDSHIFT depend on whether the input pixels are 8-bit or 10-bit, and achieves
rounding. This is automatically performed by the module.
ISS ISP H3A AE/AWB Engine
The AE/AWB engine starts by dividing the frames into windows, and then subsamples each window into 2
× 2 blocks. For each subsampled 2 × 2 block, each pixel is accumulated. Also, each pixel is compared to
a limit set in a register. If any pixels in a 2 × 2 block are greater than or equal to the limit, the block is not
counted in the unsaturated block counter. Pixels greater than the limit are replaced by the limit, and the
value of the pixel is accumulated.
The AE/AWB module has three output format modes, which are set through the H3A_AEWCFG[9:8]
AEFMT bit field:
• Sum of square mode: H3A_AEWCFG[9:8] AEFMT = 0x0
• Min/max mode: H3A_AEWCFG[9:8] AEFMT = 0x1
• Sum-only mode: H3A_AEWCFG[9:8] AEFMT = 0x2
3.3.5.6.1
ISS ISP H3A Subsampler
The subsampler partitions the frame into windows using the size, count, and starting location parameters
shown on the left in Figure 211. Each window is further sampled down to a set of 2 × 2 blocks. The
horizontal and vertical distances between the start of blocks within a window is programmable using the
parameters shown on the right in Figure 211.
Figure 215. ISS ISP H3A AE/AWB Window Configurations
HD
WINSV
WINH
VD
AEWINCH
WINSH
AEWINCV
WINVC
WINH
WINW
WINW
WINHC
Input frame
camss-072
Table 187 lists the register fields that configure the window and block sizes, counts, and starting positions.
398
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 187. ISS ISP H3A AE/AWB Window Register Field Descriptions
Register Field
Bit Width
Description
H3A_AEWWIN1[20:13] WINW
7
Window width (in pixels)
H3A_AEWWIN1[31:24] WINH
7
Window height (in lines)
H3A_AEWWIN1[5:0] WINHC
6
Window count for horizontal direction
H3A_AEWWIN1[12:6] WINVC
7
Window count for vertical direction
H3A_AEWINSTART[11:0] WINSH
12
Window start position H
H3A_AEWINSTART[27:16] WINSV
12
Window start position V
H3A_AEWSUBWIN[3:0] AEWINCH
4
Horizontal distance between subsamples
H3A_AEWSUBWIN[11:8] AEWINCV
4
Vertical distance between subsamples
3.3.5.6.2
ISS ISP H3A Additional Black Row of AE/AWB Windows
In addition to the 128 rows of windows, the AE/AWB module provides support for an additional row of
windows for black data. This data may be useful in determining the DC offset noise of the rest of the data.
The black row of windows can be before or after the regular rows of windows. The vertical start line for the
black row of windows is specified in the H3A_AEWINBLK[27:16] WINSV bit field, and the height is
specified in the H3A_AEWINBLK[6:0] WINH bit field. The horizontal starting pixel and horizontal width of
the black row of windows are the same as for the regular rows of windows.
Figure 216 shows a black row of windows before rows of windows.
Figure 216. ISS ISP H3A Black Row of Windows Before Regular Rows of Windows
HD
H3A_AEWINBLK[27:16] WINSV
WINSV
H3A_AEWINBLK[6:0] WINH
VD
WINH
WINSH
AEWINCH
AEWINCV
WINVC
WINH
WINW
WINW
WINHC
Input frame
camss-075
Table 188. ISS ISP H3A AE/AWB Window with Additional Black Row Register Field Descriptions
Register Field
Bit Width
Description
H3A_AEWWIN1[20:13] WINW
7
Window width (in pixels)
H3A_AEWWIN1[31:24] WINH
7
Window height (in lines)
H3A_AEWWIN1[5:0] WINHC
6
Window count for horizontal direction
H3A_AEWWIN1[12:6] WINVC
7
Window count for vertical direction
H3A_AEWINSTART[11:0] WINSH
12
Window start position H
H3A_AEWINSTART[27:16] WINSV
12
Window start position V
H3A_AEWSUBWIN[3:0] AEWINCH
4
Horizontal distance between subsamples
H3A_AEWSUBWIN[11:8] AEWINCV
4
Vertical distance between subsamples
H3A_AEWINBLK[27:16] WINSV
12
Window start position H for single black line
H3A_AEWINBLK[6:0] WINH
7
Window height (in lines) for single black line
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
399
ISS ISP
3.3.5.6.3
www.ti.com
ISS ISP H3A Saturation Check
The saturation check module compares the data from the subsampler to the value programmed in the
H3A_PCR [31:22] AVE2LMT bit field. This value is the maximum clipping value. If all 4 pixels in the 2 × 2
block are less than the AVE2LMT value, the value of the unsaturated block counter is incremented. There
is one unsaturated block counter per window. The unsaturated block counters are later written to memory.
3.3.5.6.4
ISS ISP H3A AE/AWB Accumulators
The output from the saturation check module and the subsampler module are separately accumulated for
each pixel in every 2 × 2 pixel block for each window. Therefore, there are eight accumulators per window
(one accumulator for each pixel in a 2 × 2 pixel block, times two sets of accumulators: clipped/saturated
data and presaturated data). Each of the 4 pixels in the 2 × 2 pixel grid is associated with a color (R, Gr,
B, Gb); however, the output of these accumulators is referenced by position in the grid, not color.
The accumulators are 16 bits wide, and the accumulated data is 10 bits wide. Therefore, when a window
contains more than 64 pixels of the same color, an overflow risk exists. This risk can be reduced by
enabling the A-Law conversion in the preprocessing stage. See Section 3.3.5.4 for details.
The AE/AWB module has a shift value for the accumulation of pixel values that is set in the
H3A_AEWCFG[3:0] SUMSHFT bit field.
3.3.5.7
ISS ISP H3A DMA Interface
The DMA interface module takes the data from the AF engine and AE/AWB engine and builds packets to
be sent out to the memory through the BL module.
The data interface has separate start pointers for the AF and AE/AWB engines.
• The starting address for the AF engine is the H3A_AFBUFST[31:5] AFBUFST bit field.
• The starting address for the AE/AWB engine is the H3A_AEWBUFST[31:5] AEWBUFST bit field.
The DMA interface module continuously loops through this data as it builds the packets. To optimize the
transfer sizes, the DMA interface sends out an AF or AE transfer for each row of paxels or windows. This
requires that each horizontal row of paxels or windows starts and ends on a 32-byte boundary. If a
horizontal row of paxels or windows ends on a non-32 byte boundary, the hardware packs zeroes. The
counts for the AEW that occur every eight windows is sent in the row with the 8th consecutive window.
Table 189 lists the packet formats for AF with vertical AF disabled.
Table 189. ISS ISP H3A AF Packet Format With Vertical AF Disabled
Buffer Start 31
16 15
Address (Byte
Address)
H3A_AFBUFST
Sum of pixel values used in HFV
HFV_1 (peak or sum)
HFV_2 (peak or sum)
ZEROES
Sum of pixel values used in HFV
HFV_1 (peak or sum)
HFV_2 (peak or sum)
ZEROES
Sum of pixel values used in HFV
HFV_1 (peak or sum)
HFV_2 (peak or sum)
ZEROES
Sum of pixel values used in HFV
HFV_1 (peak or sum)
HFV_2 (peak or sum)
ZEROES
400
0
(Paxel 0:G)
(Paxel 0:G)
(Paxel 0:G)
(Paxel 0:G)
(Paxel 0:R)
(Paxel 0:R)
(Paxel 0:R)
(Paxel 0:R)
(Paxel 0:B)
(Paxel 0:B)
(Paxel 0:B)
(Paxel 0:B)
(Paxel 1)
(Paxel 1)
(Paxel 1)
(Paxel 1)
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 189. ISS ISP H3A AF Packet Format With Vertical AF Disabled (continued)
Buffer Start 31
Address (Byte
Address)
H3A_AFBUFST
...
16 15
0
Table 190 shows the packet formats for AF with vertical AF enabled.
Table 190. ISS ISP H3A AF Packet Format With Vertical AF Enabled
Buffer Start 31
16 15
Address (Byte
Address)
H3A_AFBUFST
Sum of pixel values used in HFV
HFV_1 (peak or sum)
HFV_sq_1 (peak or sum)
HFV_count_1
HFV_2 (peak or sum)
HFV_sq_2 (peak or sum)
HFV_count_2
ZEROES
VFV_1
VFV_sq_1
VFV_count_1
ZEROES
VFV_2
VFV_sq_2
VFV_count_2
ZEROES
Sum of pixel values used in HFV
HFV_1 (peak or sum)
HFV_sq_1 (peak or sum)
HFV_count_1
...
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
0
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 0)
(Paxel 1)
(Paxel 1)
(Paxel 1)
(Paxel 1)
401
ISS ISP
www.ti.com
Figure 217 shows the windows and subsample definition used in tables.
Figure 217. ISS ISP H3A AE/AWB Window and Subsample Definition
Window 0 Window 1
...
subsample [0]
subsample [2]
subsample [1]
subsample [3]
AEWINCH
0
1
0
1
0
1
2
3
2
3
2
3
AEWINCV
0
1
0
1
0
1
2
3
2
3
2
3
0
1
0
1
0
1
2
3
2
3
2
3
WINH
WINW
camss-624
Table 191 lists the packet formats for AE/AWB for sum of square mode (H3A_AEWCFG[9:8] AEFMT =
0x0) .
Table 191. ISS ISP H3A AE/AWB Packet Format for Sum of Square Mode
31
Buffer address
(byte address)
H3A_AEWBUF
ST
H3A_AEWBUF
ST +
32 bytes
16 15
Subsample Accum[1]
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Subsample Accum[1]
0
Subsample Accum[0]
Window 0 data
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
Subsample Accum[0]
Window 1 data
Subsample Accum[3]
Subsample Accum[2]
Saturator Accum[1]
Saturator Accum[0]
Saturator Accum [3]
Saturator Accum[2]
Sum of squares[0]
402
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 191. ISS ISP H3A AE/AWB Packet Format for Sum of Square
Mode (continued)
31
H3A_AEWBUF
ST +
64 bytes
H3A_AEWBUF
ST +
96 bytes
H3A_AEWBUF
ST +
128 bytes
H3A_AEWBUF
ST +
160 bytes
H3A_AEWBUF
ST +
192 bytes
16 15
Sum of squares[1]
Sum of squares[2]
Sum of squares[3]
Subsample Accum[1]
Subsample Accum[0]
0
Window 2 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
Subsample Accum[0]
Window 3 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
Subsample Accum[0]
Window 4 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
Subsample Accum[0]
Window 5 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
Subsample Accum[0]
Window 6 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
403
ISS ISP
www.ti.com
Table 191. ISS ISP H3A AE/AWB Packet Format for Sum of Square
Mode (continued)
31
H3A_AEWBUF
ST +
224 bytes
16 15
Subsample Accum[1]
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Sum
Sum
Sum
Sum
Unsaturated count, win 1
H3A_AEWBUF
ST +
256 bytes
0
Subsample Accum[0]
Window 7 data
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
of squares[0]
of squares[1]
of squares[2]
of squares[3]
Unsaturated count, win 0
Unsaturated
block count for
the above 8
windows
Unsaturated count, win 3
Unsaturated count, win 2
Unsaturated count, win 5
Unsaturated count, win 4
Unsaturated count, win 7
Unsaturated count, win 6
Data for next eight windows, and so on.
If the total number of windows is not a multiple of 8, the unsaturated
counters are written immediately following the last window data.
For example, if the total number of windows (including the black row)
are 43, the first 40 windows are written out as per the 272-byte
boundary above. Then the remaining three windows are written at +0,
+32, and +64 bytes. The counts are written out at +96 instead of
+256-byte boundary.
Table 192 lists the packet formats for AE/AWB in minimum-maximum mode (H3A_AEWCFG[9:8] AEFMT
= 0x1).
Table 192. ISS ISP H3A AE/AWB Packet Format for Minimum-Maximum Mode
31
Buffer address
(byte address)
H3A_AEWBUF
ST
H3A_AEWBUF
ST +
32 bytes
H3A_AEWBUF
ST +
64 bytes
404
16 15
0
Subsample Accum[1]
Subsample Accum[0]
Window 0 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 1 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 2 data
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 192. ISS ISP H3A AE/AWB Packet Format for Minimum-Maximum
Mode (continued)
31
H3A_AEWBUF
ST +
96 bytes
H3A_AEWBUF
ST +
128 bytes
H3A_AEWBUF
ST +
160 bytes
H3A_AEWBUF
ST +
192 bytes
H3A_AEWBUF
ST +
224 bytes
16 15
0
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 3 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 4 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 5 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 6 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Minimum[3]
Maximum[1]
Maximum[3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
Minimum[2]
Maximum[0]
Maximum[2]
Subsample Accum[0]
Window 7 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Minimum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Minimum[0]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
405
ISS ISP
www.ti.com
Table 192. ISS ISP H3A AE/AWB Packet Format for Minimum-Maximum
Mode (continued)
31
16 15
Minimum[3]
Maximum[1]
Maximum[3]
Unsaturated count, win 1
H3A_AEWBUF
ST +
256 bytes
0
Minimum[2]
Maximum[0]
Maximum[2]
Unsaturated count, win 0
Unsaturated
block count for
the above 8
windows
Unsaturated count, win 3
Unsaturated count, win 2
Unsaturated count, win 5
Unsaturated count, win 4
Unsaturated count, win 7
Unsaturated count, win 6
Data for next eight windows, and so on.
If the total number of windows is not a multiple of 8, the unsaturated
counters are written immediately following the last window data.
For example, if the total number of windows (including the black row)
are 43, the first 40 windows are written out as per the 272-byte
boundary above. Then the remaining three windows are written at +0,
+32, and +64 bytes. The counts are written out at +96 instead of
+256-byte boundary.
Table 193 lists the packet formats for AE/AWB in sum-only mode (H3A_AEWCFG[9:8] AEFMT = 0x2).
Table 193. ISS ISP H3A AE/AWB Packet Format for Sum-Only Mode
31
Buffer address
(byte address)
H3A_AEWBUF
ST
H3A_AEWBUF
ST +
32 bytes
H3A_AEWBUF
ST +
64 bytes
H3A_AEWBUF
ST +
96 bytes
H3A_AEWBUF
ST +
128 bytes
406
16 15
0
Subsample Accum[1]
Subsample Accum[0]
Window 0 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Subsample Accum[0]
Window 1 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Subsample Accum[0]
Window 2 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Subsample Accum[0]
Window 3 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Subsample Accum[0]
Window 4 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 193. ISS ISP H3A AE/AWB Packet Format for Sum-Only Mode (continued)
31
H3A_AEWBUF
ST +
160 bytes
H3A_AEWBUF
ST +
192 bytes
H3A_AEWBUF
ST +
224 bytes
H3A_AEWBUF
ST +
256 bytes
16 15
0
Subsample Accum[1]
Subsample Accum[0]
Window 5 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Subsample Accum[0]
Window 6 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Subsample Accum[1]
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Subsample Accum[0]
Window 7 data
Subsample Accum[3]
Saturator Accum[1]
Saturator Accum [3]
Unsaturated count, win 1
Subsample Accum[2]
Saturator Accum[0]
Saturator Accum[2]
Unsaturated count, win 0
Unsaturated
block count for
the above 8
windows
Unsaturated count, win 3
Unsaturated count, win 2
Unsaturated count, win 5
Unsaturated count, win 4
Unsaturated count, win 7
Unsaturated count, win 6
Data for next eight windows, and so on.
If the total number of windows is not a multiple of 8, the unsaturated
counters are written immediately following the last window data.
For example, if the total number of windows (including black row) are
43, the first 40 windows are written out as per the 272-byte boundary
above. Then the remaining three windows are written at +0, +32, and
+64 bytes. The counts are written out at +96 instead of +256-byte
boundary.
3.3.5.8
ISS ISP H3A Events and Status Checking
The AF and AEW engines generate an interrupt event at the end of processing each frame. However,
these two interrupts are internally tied together so that only one H3A interrupt signal is generated. If the
AF engine and AEW engine do not process the same frame concurrently, this should not be an issue.
However, if they do run concurrently, one of two outcomes may occur:
• The H3A interrupt may seem to trigger only once for each frame. This can happen when the
processing for the AF and AEW engines finishes at or near the same time. The interrupt service
routine does not have enough time to clear the interrupt flag for the first interrupt before the second
interrupt occurs.
• The H3A interrupt may trigger twice for each frame. This can happen when the AF engine or the AEW
engine finishes processing the frame much earlier than the other engine. In this case, the interrupt
service routine does have enough time to clear the interrupt flag for the first interrupt by the time the
second interrupt occurs.
The outcome depends on the difference in location of the last paxel/window in the frame (determines
when processing is finished), the frequency of the relative clocks in the system, the occurrence and
triggering of other interrupts in the system, and the latencies of the context switching and interrupt service
routine execution.
The H3A_PCR[15] BUSYAF and/or H3A_PCR[18] BUSYAEAWB status bits are set when the start of
frame occurs (if the H3A_PCR[0] AF_EN and/or H3A_PCR[16] AEW_EN bits are 1 at that time). They are
automatically reset to 0 at the end of processing a frame. The H3A_PCR[15] BUSYAF and/or
H3A_PCR[18] BUSYAEAWB status bits may be polled to determine the end of frame status.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
407
ISS ISP
3.3.6
www.ti.com
ISS ISP ISIF Functional Description
3.3.6.1
ISS ISP ISIF Overview
The image sensor interface (ISIF) module receives RAW or YUV4:2:2 data from the IPIPEIF module. The
module outputs data back to the IPIPEIF module and can also output data to memory though the BL
module. The ISIF module can process the incoming data and supports the following functions:
• Maximum supported image size is 32,768 × 32,768
• Supports up to 16-bit analog front end
• Sensor data linearization
• Supports Bayer and Foveon® input data format (RGB and CMYG color support)
• Supports VGA read out mode
• Supports various image data format
• Color space conversion
• Digital clamp with horizontal/vertical offset drift compensation
• Vertical line defect correction
• Programmable 2D-matrix LSC
• Gain and offset control
• Programmable horizontal/vertical culling pattern
• Maximum pixel rate clock of 200 MPix/s on the VP interface.
• 10-to-8-bit A-Law compression table inside
• 12-bit pack supported when written to memory
Figure 218 show the ISIF module connections to other submodules of the ISP.
Figure 218. ISS ISP ISIF High-Level Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
camss-003e
408
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.6.2
ISS ISP ISIF Top-Level Block Diagram
Figure 219 shows the different blocks of the ISIF module.
Figure 219. ISS ISP ISIF Top-Level Block Diagram
ISIF module
Timing generator
Interface
YIN[7:0] and CIN[7:0]
U16
0
IPIPEIF
Sensor linearization
ISIF_MODESET[6]
DPOL
ISIF_CCDCFG[4]
YCINSWP
U16
U16
ISIF_LINCFG0[0]
LINEN
U16
0
16-to-16-bit
selection
1
U12
16-to-12
bit
1
U12
1
Linearization
ISIF_CSCCTL[0]
CSCEN
ISIF_FMTCFG[0]
FMTEN
U12
A
U16 data[15:4]
CIN[7:0] and YIN[7:0]
0
A
U12
0
Black clamp
VDFC
U12
0
0
S13
S13
S13
0
B
S13
Input data
formatter
1
1
1
Clamp value
(horizontal)
Color space
converter
Clamp value
(vertical)
2D-LSC
1
VDFC
S13
U12
DFCCTL[4]
S13
ISIF_CLAMPCFG[0]
CLEN
ISIF_CLDCOFST[12:0]
CLDC
White balance
ISIF_2DLSCCFG[0]
ENABLE
U13
0
B
ISIF_CGMMAWD[8]
OFSTEN0
ISIF_CGMMAWD[12]
WBEN0
U12
S13
CLIP
2D LSC
1
GAIN
C
S13
S13
OFFSET
ISIF_CGAMMAWD[13]
WBEN1
ISIF_CGAMMAWD[9]
OFSTEN1
CLIP
S13
U12
IPIPEIF
(IPIPE datapath)
S13
GAIN
OFFSET
ISIF_CGAMMAWD[14] ISIF_CGAMMAWD[10]
WBEN2
OFSTEN2
CLIP
S13
U12
12-to-10
bits
S13
GAIN
OFFSET
ISIF_CRGAIN[11:0] CGR for R/Ye
ISIF_CGRGAIN[11:0] CGGR for Gr/Cy
ISIF_CGBGAIN[11:0] CGGB for Gb/Cy
ISIF_CBGAIN[11:0] CGB for B/Mg
OFFSET: ISIF_COFSTA[11:0] COFT
U10
IPIPEIF
(H3A datapath)
U12 data[11:2]
GAIN:
LPF
A-Law compression
ISIF_MODESET[14]
HLPF
ISIF_CGAMMAWD[0]
CCDTBL
U12
C
LPF
1
U12
U12
0
0
DPCM
D
H and V
culling
D
A-Law
U12
12-to-10
8-to-12
compression
1
bits U10
bits
10-to-8 U8
U12 data[11:2]
LSB-align
0000 and U8
Storage formatter
ISIF_MISC[12]
DPCMEN
U12
U12
0
DPCM U8
encoder
12-to-8
8-to-12
bits
U12
Data
shift
U12
Output
formatter
U32
Buffer logic (BL)
1
ISIF_MISC[13] LSB-align
0000 and U8
DPCMPRE
camss-074
The following sections describe the blocks in the ISIF module.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
409
ISS ISP
3.3.6.3
www.ti.com
ISS ISP ISIF Input Interface
The input interface is a video interface. It comprises the horizontal (HD) and vertical (VD) synchronization
signal, pixel clock (PCLK), and data (DATA). Table 194 gives more information about these different
signals. The ISIF uses the HD and VD signals provided by the sensor through the VP and IPIPEIF. The
pixel clock clocks data into the ISIF at a maximum rate of 200 MHz.
Table 194. ISS ISP ISIF Input Interface Signals
3.3.6.4
Name
I/O
VD
I
Function
Vertical sync signal
HD
I
Horizontal sync signal
PCLK
I
Pixel clock.
This signal is the pixel clock used to load
image data into the ISIF. The clock
controller can configure to trigger on the
rising or falling edge of the PCLK signal.
DATA
I
Data.
The data interface is a 16-bit interface.
When the ISIF is configured to write data
to SDRAM, the write enable signal allows
an external device to control which data is
to be written to SDRAM. The data input
can be configured from the
ISIF_MODESET.INPMOD register where
it can be set to RAW, YCbCr (16 bits and
8 bits). The polarity of the data can be
changed from the ISIF_MODESET.DPOL
as shown in Figure 220.
ISS ISP ISIF Interface
Figure 220. ISS ISP ISIF Interface Block Diagram
Interface
ISIF_CCDCFG[4]
YCINSWP
U16
YIN[7:0] and CIN[7:0]
0
CIN[7:0] and YIN[7:0]
1
ISIF_MODESET[6]
DPOL
U16
U16
16- to 16-bit
selection
U16
0
1
camss-626
The ISIF supports 8- to 16-bit-wide RAW data signals and 8-/16-bit YCbCr signals, as described in
Table 195. The interface can be set in the three different modes from the ISIF_MODESET[13:12]
INPMOD bit field. The ISIF_CCDCFG[11] Y8POS bit selects the y signal positioning whenever YUV4:2:2
is input. Moreover, if CCIR656 input is used the width of selected bit can be set through the
ISIF_CCDCFG[5] BT656 bit.
Table 195. ISS ISP ISIF Data Input Formats
410
ISIF Input Port Name
RAW Data
16-bit YCbCr
YI7
C_DATA15
Y7
YI6
C_DATA14
Y6
YI5
C_DATA13
Y5
YI4
C_DATA12
Y4
YI3
C_DATA11
Y3
YI2
C_DATA10
Y2
YI1
C_DATA9
Y1
8-bit YCbCr
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 195. ISS ISP ISIF Data Input Formats (continued)
ISIF Input Port Name
RAW Data
16-bit YCbCr
YI0
C_DATA8
Y0
8-bit YCbCr
CI7
C_DATA7
Cb7,Cr7
Y7,Cb7,Cr7
CI6
C_DATA6
Cb6,Cr6
Y6,Cb6,Cr6
CI5
C_DATA5
Cb5,Cr5
Y5,Cb5,Cr5
CI4
C_DATA4
Cb4,Cr4
Y4,Cb4,Cr4
CI3
C_DATA3
Cb3,Cr3
Y3,Cb3,Cr3
CI2
C_DATA2
Cb2,Cr2
Y2,Cb2,Cr2
CI1
C_DATA1
Cb1,Cr1
Y1,Cb1,Cr1
CI0
C_DATA0
Cb0,Cr0
Y0,Cb0,Cr0
Y and C input signals can be swapped through the ISIF_CCDCFG[4] YCINSWP bit.
In case of RAW data at ISIF input, a 16- to-16-bit selection can be done: when the number of RAW data
lines is less than 16, data can be connected to the upper or lower lines of C_DATA[15:0]. Lines not
connected must be tied low. As shown in Table 196, the ISIF_CGAMMAWD[4:1] GWDI bit field must be
configured correctly so that the MSB of the input is connected to the MSB of the 16-bit data bus in ISIF.
Table 196. ISS ISP ISIF Raw Data Connection: Selects MSB Position of Input Data
ISIF_CGAMMAWD[4:1] GWDI
16-to-16-bit Selection
0
C_DATA [15:0] = C_DATA[15:0]
1
C_DATA [15:0] = C_DATA[14:0] 0
2
C_DATA [15:0] = C_DATA[13:0] 00
3
C_DATA [15:0] = C_DATA[12:0] 000
4
C_DATA [15:0] = C_DATA[11:0] 0000
5
C_DATA [15:0] = C_DATA[10:0] 00000
6
C_DATA [15:0] = C_DATA[9:0] 000000
7
C_DATA [15:0] = C_DATA[8:0] 0000000
8
C_DATA [15:0] = C_DATA[7:0] 00000000
The polarity of the input image data can be switched through the ISIF_MODESET[6] DPOL bit.
3.3.6.5
ISS ISP ISIF Sensor Linearization
NOTE: For the memory access locations of the sensor linearization table, see Section 3.3.8.
Figure 221. ISS ISP ISIF Sensor Linearization Block Diagram
Sensor linearization
ISIF_LINCFG0[0] LINEN
U16
16- to
12-bit
U12
U12
0
U16 data[15:4]
U12
Linearization
1
camss-627
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
411
ISS ISP
www.ti.com
The sensor linearization module can correct for the non-linear response of image sensors. A LUT is
programmed with an offset value to add to the original pixel value based on the original pixel value.
The LUT is a sampling of the linearization correction curve based on calibration of the image sensor.
Intermediate values between sampling points are computed using linear interpolation. The entire
correction curve is divided into seven regions, as shown in Table 197. The regions for the darkest part and
the brightest part of the response curve have dense sampling. The linearization mode can be a uniform or
a non-uniform sampling and can be set through the ISIF_LINCFG0[1] LINMD bit.
Table 197. ISS ISP ISIF Linearization LUT
Region
Number of Sample Points
LUT Address
table_in[15:11] == 00000
32
table_in[10:6]
table_in[15:11] == 00001
4
table_in[10:9] + 32
table_in[15:12] == 0001
4
table_in[11:10] + 36
table_in[15:13] == 001
4
table_in[12:11] + 40
table_in[15:14] == 01
4
table_in[13:12] + 44
table_in[15:14] == 10
16
table_in[13:10] + 48
table_in[15:14] == 01
128
table_in[13:7] + 64
The LUT has 192 entries and is split into two 96 × 10-bit memories, as shown in Figure 222. The table is
mapped in the memory map. The LUT entries are interleaved between memory 0 and memory 1.
Figure 222. ISS ISP ISIF Linearization LUT Memories
9
0
Address = 0
Entry 0
1
Entry 1
2
Entry 2
3
Memory-0
9
Entry 3
:
:
190
Entry 190
191
Entry 191
LUT
Memory-1
9
0
0
Address = 0
Entry 0
Address = 0
Entry 1
1
Entry 2
1
Entry 3
:
:
94
95
:
:
Entry 188
94
Entry 189
Entry 190
95
Entry 191
camss-613
Table 198. ISS ISP ISIF LUT Memory Region
412
Memory Region
Address Range
Description
Memory 0
0xC000 – 0xC17F
ISIF linearity compensation LUT 0
Memory 1
0xC400 – C57F
ISIF linearity compensation LUT 1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
A scale factor is applied to the input before lookup through the ISIF_LINCFG1[10:0] LUTSCL bit field. The
LUT entries are signed 10-bit data (u16). After linear interpolation, the correction value is left-shifted by a
programmable amount (the ISIF_LINCFG0[6:4] CORRSFT bit field), and then added to the input. This is
then converted to unsigned 12-bit by right shift, followed by clipping.
Figure 223. ISS ISP ISIF Linearization Block Diagram
Linearization_out (U12)
Linearization_in (u16)
Clip
>>4
U12
8 (rounding)
>>10
LUT
Clip
with liear
U16 interpolation
<<CORRSFT
correction_value
512 (rounding)
LUTSCL
(U11Q10)
camss-625
To enable the linearization module, set the ISIF_LINCFG0[0] LINEN bit to 1.
If the linearization module is disabled (ISIF_LINCFG0[0] LINEN = 0x0), a 16- to-12-bit transformation is
done, and the upper 12-bits of U16 input are sent to the next block.
3.3.6.6
ISS ISP ISIF Input Data Formatter
Figure 224. ISS ISP ISIF Input Data Formatter Block Diagram
ISIF_CSCCTL[0] CSCEN
ISIF_FMTCFG[0] FMTEN
U12
Input data
formatter
0
0
1
1
Color space
converter
camss-628
There are two functional blocks: input data formatter and color space converter, which use two 5376 × 12bit memories (corresponds to one line of maximum 5376 pixels with each pixel equal to 12 bits). Only one
of the function blocks can be enabled.
The input data formatter block allows the ISIF to handle a wide variety of current and future readout
schemes other than Bayer format. Two line memories and a programmable address generator are used to
translate those patterns into a standard Bayer pattern (or any other pattern). This allows the back-end
processing (noise filters, interpolation, histogram, 3A statistics) to remain unchanged.
The input data formatter block also supports divided input lines. In case an input line is divided into
multiple lines and fed to the ISIF, the formatter gathers the divided lines and organizes a single line. Up to
four divided lines can be supported.
The input data formatter is enabled through the ISIF_FMTCFG[0] FMTEN bit.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
413
ISS ISP
www.ti.com
The input data formatter can split an input line into 1, 2, 3, or 4 output lines, or can combine the divided 1,
2, 3, or 4 input lines into a single line.
• Set the ISIF_FMTCFG[1] FMTCBL bit to 0 for split mode.
• Set the ISIF_FMTCFG[1] FMTCBL bit to 1 for combine mode.
• Select the number of lines in the ISIF_FMTCFG[5:4] LNUM bit field.
The Input data formatter can work in normal or line alternative mode. The choice is done through the
ISIF_FMTCFG[2] LNALT bit.
Figure 225 shows an example of generating three output lines from an input line with a new, internally
generated HD signal.
Figure 225. ISS ISP ISIF Splits an Input Line Into Three Output Lines
Line memory
Output
Input
Line memory
HD in
Timing generator
HD out
Ex: Three lines in a line
camss-126
This HD signal then gates the downstream processing rather than the original sensor HD signal.
Descriptions of how to configure the formatter are provided in the following sections.
Because the size of the line memories is 5376 × 12 bits, the following restrictions apply for the data
formatter:
• Split mode:
– The maximum number of pixels that can be supported in an output line if the input line is
transformed into 1 output line is 5376.
– The maximum number of pixels that can be supported in an output line if the input line is
transformed into 2 output lines is 2688.
– The maximum number of pixels that can be supported in an output line if the input line is
transformed into 3 output lines is 1792.
– The maximum number of pixels that can be supported in an output line if the input line is
transformed into 4 output lines is 1344.
• Combine mode:
– The maximum number of pixels that can be supported in an input line if 1 input line is transformed
into an output line is 5376.
– The maximum number of pixels that can be supported in an input line if 2 input lines are
transformed into an output line is 2368.
– The maximum number of pixels that can be supported in an input line if 3 input lines are
transformed into an output line is 1792.
– The maximum number of pixels that can be supported in an input line if 4 input lines are
transformed into an output line is 1344.
414
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.6.6.1
As
•
•
•
•
ISS ISP ISIF Formatter Area Settings
shown in Figure 226, the following registers are used to set the formatter area:
ISIF_FMTSPH
ISIF_FMTLNH
ISIF_FMTLSV
ISIF_FMTLNV
Table 199 describes these registers. The input line is input to the formatter, and the output line is output
from the formatter.
Figure 226. ISS ISP ISIF Input Data Formatter Area Settings
HD
ISIF_FMTSPH
ISIF_FMTLNH
ISIF_FMTLSV
Valid data region
ISIF_FMTLNV
VD
Global input frame
camss-112
Table 199. ISS ISP ISIF Input Data Formatter Area Setting Registers
Register
Description
ISIF_FMTSPH
The first valid pixel of an input line
ISIF_FMTLNH
Valid length of a input line = FMTLNH + 1
ISIF_FMTLSV
The first valid input line
ISIF_FMTLNV
The number of the valid input lines = FMTLNV + 1
Table 200. ISS ISP ISIF Output Data Formatter Area Setting Registers
Register
Description
ISIF_FMTRLEN
The length of an output line
ISIF_FMTHCNT
HD interval for output lines
ISIF_SPH
The first pixel in an output line to be stored to SDRAM
ISIF_LNH
Number of pixels in an output line to be stored to SDRAM = LNH
+1
ISIF_LNV
The number of the output lines to be stored to SDRAM = LNV +
1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
415
ISS ISP
www.ti.com
The number of pixels in an output line must be set to the ISIF_FMTRLEN register, and the HD output
interval must be set to the ISIF_FMTHCNT register. It is not necessary to set the ISIF_FMTHCNT register
if multiple input lines are combined into a single line.
Figure 227 shows an example of splitting an input line into two or three output lines.
Figure 227. ISS ISP ISIF Data Formatter Output Control Example
Line memory 1
Line memory 2
1 –>2 lines
FMTRLEN
1st line
1 –> 3 lines
2nd line
FMTRLEN
1st line
2nd line
3rd line
HD (input)
FMTHCNT
1 –>2 lines HD (output)
FMTRLEN
Data (output)
1 –> 3 lines HD (output)
FMTHCNT
FMTRLEN
Data (output)
camss-127
3.3.6.6.2
ISS ISP ISIF Formatter Programming
The data formatter derives its flexibility by supporting up to 16 different addresses and a program that can
contain up to 32 entries.
Address pointer
There are 16 address pointer registers (ISIF_FMTAPTR0 to ISIF_FMTAPTR15), which contain:
•
•
The ISIF_FMTAPTRx[14:13] LINE bit field: 2-bit line number to specify the output line to which it
belongs: 0, 1, 2, or 3. It is valid only for the line splitting.
The ISIF_FMTAPTRx[12:0] INIT bit field: 13-bit initial address for pointer x (where x = 0 to 15)
Each of the address values is auto-incremented or auto-decremented by a programmable value (the
ISIF_FMTCFG[11:8] FMTAINC bit field).
Program
There are 32 program entry registers, which contain:
• In the ISIF_FMTPGMVF0 and ISIF_FMTPGMVF1 registers: The PGMxxEN fields (where xx = 00 to
31) set the program entry valid flag.
• In the ISIF_FMTPGMAPS0 to ISIF_FMTPGMAPS7 registers: The PGMxxAPTR fields specify the
program xx address pointer (where xx = 00 to 31).
• In the ISIF_FMTPGMAPU0 and ISIF_FMTPGMAPU1 registers: The PGMxxUPDT fields (where xx =
00 to 31) set the program xx address update (increment or decrement).
416
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Because each of the program entries has a valid flag, the formatter can also support images larger than
the memory limit (length: 4480) by not choosing some of the entries.
The total program memory of 32 entries is divided into two or four SETs:
• Program memory of 16 entries each for odd and even lines to split the line:
– SET0 for even input line: Program entry 015
– SET1 for odd input line: Program entry 1631
• Program memory of eight entries for up to four input lines to combine the lines:
– SET0 for first input line: Program entry 07
– SET1 for second input line: Program entry 815
– SET2 for third input line: Program entry 1623
– SET3 for fourth input line: Program entry 2431
The number of program entries per SET must be specified by the ISIF_FMTPLEN register as follows:
• Number of program entries for SET0: ISIF_FMTPLEN[3:0] FMTPLEN0
• Number of program entries for SET1: ISIF_FMTPLEN[7:4] FMTPLEN1
• Number of program entries for SET2: ISIF_FMTPLEN[10:8] FMTPLEN2
• Number of program entries for SET3: ISIF_FMTPLEN[14:12] FMTPLEN3
The program entry must be set from the lower registers within a SET. For instance, start from program
entry 16 for odd input lines.
The following examples show the programmability of the data formatter:
• Register settings:
– ISIF_FMTCFG[0] FMTEN = 0x1
– ISIF_FMTCFG[1] FMTCBL = 0x0
– ISIF_FMTCFG[11:8] FMTAINC = 0x0 (add or subtract 1)
• 1 input line - 1 output line
NOTE: ADDR0 is set to an example value. Addresses with no value in the following example are
marked with X.
Figure 228. ISS ISP ISIF Conventional Read-Out Pattern
Line no.
Init value
ADDR0
0
0
ADDR1
X
X
ADDR2
X
X
ADDR3
X
X
ADDR4
X
X
ADDR5
X
X
ADDR6
X
X
ADDR7
X
X
Address pointers
ADDR0 +1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SET0/1
length = 1
SET0–
even line
SET1–
odd line
ADDR0 +1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
camss-128
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
417
ISS ISP
www.ti.com
The following examples show the programmability of the data formatter with a 2-tap analog front end
(AFE):
• Register settings:
– ISIF_FMTCFG[0] FMTEN = 0x1
– ISIF_FMTCFG[1] FMTCBL = 0x0
– ISIF_FMTCFG[11:8] FMTAINC = 0x0 (add or subtract 1)
– ISIF_FMTCFG[5:4] LNUM = 0x0
• One input line (4096) - one output line with left and right read-out
• Input - First pixel, last pixel, first pixel + 1, last pixel – 1, and so on
• Input - 0, 4095, 1, 4094, 2, 4093, 3, 4092, ..., 2047 and 2048
• Output - 0, 1, 2, 3, ..., 4094 and 4095
Figure 229. ISS ISP ISIF Conventional Read-Out Pattern With 2-tap AFE
Line no.
Init value
ADDR0
0
0
ADDR1
0
4095
ADDR2
X
X
ADDR3
X
X
ADDR4
X
X
ADDR5
X
X
ADDR6
X
X
ADDR7
X
X
Address pointers
ADDR0 +1
ADDR1 –1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SET0/1
length = 2
SET0 –
even line
SET 1–
odd line
ADDR0 +1
ADDR1 –1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
camss-129
3.3.6.6.3
ISS ISP ISIF Combine the Divided Input Lines
The formatter can gather the divided input lines and organize a single line. Figure 230 shows an example
generating a single output line from three input lines and masking two out of three HD input pulses.
Figure 230. ISS ISP ISIF Combine Three Input Lines Into Single Line
Line memory
Output
Input
Line memory
HD in
Timing generator
HD out
Ex: An input line is divided into three lines.
camss-130
418
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 231 is an example that shows the register setting.
• Multiple input lines combined into one output line (use three input lines to one output line in this
example)
• Input - 4, 5, 10, 11, ..., 2, 3, 8, 9, ..., 0, 1, 6, 7, ... (three lines read from sensor)
• Output - 0, 1, 2, 3, ... (1 line output)
• Register settings:
– ISIF_FMTCFG[0] FMTEN = 0x1
– ISIF_FMTCFG[1] FMTCBL = 0x1
– ISIF_FMTCFG[11:8] FMTAINC = 0x5 (add or subtract 6)
– ISIF_FMTCFG[5:4] LNUM = 0x2
– SETs recycled based on LNUM
Figure 231. ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line
First line
20
787
Input
lines
B
Gb
B
Gb - - - Gb
Line
memory
B
Gb
B
Gb
0
B
Gb
20
B
B
787
Gb
Gb
B
B
Line no.
Init value
ADDR0
X
0
ADDR1
X
1
X
2
ADDR3
X
3
ADDR4
X
4
ADDR5
X
5
ADDR6
X
X
ADDR7
X
X
Address pointers
20
Gb - - - Gb
Gb
4
ADDR2
Third line
Second line
B
Gb
787
B
B
Gb
Gb
B
Gb - - - Gb
--------
10
ADDR4 +6
ADDR5 +6
X
X
X
X
X
X
SET0 –
th
0 line
B
Gb
2303
SET2 –
2
nd
line
ADDR0 +6
ADDR1 +6
X
X
X
X
X
X
SET0/1/2
ADDR2 +6
length = 1
ADDR3 +6
X
X
X
SET1 –
X
st
X
1 line
X
X
X
X
X
X
X
X
X
SET3 –
rd
3 line –
do not use
based on
LNUM
camss-131
Table 201. ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line: Register
Setting Example
Step
Configuration Required
Size
Formatter enable
ISIF_FMTCFG[0] FMTEN
1
Combine input lines.
ISIF_FMTCFG[1] FMTCBL
1
Address increment = FMTAINC + 1 = 6
ISIF_FMTCFG[11:8] FMTAINC
5
The first valid pixel of a divided line
ISIF_FMTSPH[12:0] FMTSPH
20
Valid length of a divided line = FMTLNH + 1 = 768
ISIF_FMTLNH[12:0] FMTLNH
767
The first valid divided line
ISIF_FMTLSV[12:0] FMTSLV
16
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
419
ISS ISP
www.ti.com
Table 201. ISS ISP ISIF Example of Combining Three Input Lines Into a Single Line: Register
Setting Example (continued)
Step
Configuration Required
Size
The number of the valid divided lines = FMTLNV + 1 = 4590
ISIF_FMTLNV[14:0] FMTLNV
4589
The length of an organized line = (FMTLNH + 1) x (LNUM + 1) = ISIF_FMTRLEN[12:0]
2304
FMTRLEN
420
2304
Split/combine line number = LNUM + 1 = 3.
ISIF_FMTCFG[5:4] LNUM
2
Number of PGM entries for SET0 = FMTPLEN0 + 1 = 2
ISIF_FMTPLEN[3:0]
FMTPLEN0
1
Number of PGM entries for SET1 = FMTPLEN1 + 1 = 2
ISIF_FMTPLEN[7:4]
FMTPLEN1
1
Number of PGM entries for SET2 = FMTPLEN2 + 1 = 2
ISIF_FMTPLEN[10:8]
FMTPLEN2
1
Address Pointer 0, INIT = 0
ISIF_FMTAPTR0[12:0] INIT
0
Address Pointer 1, INIT = 1
ISIF_FMTAPTR1[12:0] INIT
1
Address Pointer 2, INIT = 2
ISIF_FMTAPTR2[12:0] INIT
2
Address Pointer 3, INIT = 3
ISIF_FMTAPTR3[12:0] INIT
3
Address Pointer 4, INIT = 4
ISIF_FMTAPTR4[12:0] INIT
4
Address Pointer 5, INIT = 5
ISIF_FMTAPTR5[12:0] INIT
5
Program 0 Valid flag
ISIF_FMTPGMVF0[0]
PGM00EN
1
Program 1 Valid flag
ISIF_FMTPGMVF0[1]
PGM01EN
1
Program 8 Valid flag
ISIF_FMTPGMVF0[8]
PGM08EN
1
Program 9 Valid flag
ISIF_FMTPGMVF0[9]
PGM09EN
1
Program 16 Valid flag
ISIF_FMTPGMVF1[0]
PGM16EN
1
Program 17 Valid flag
ISIF_FMTPGMVF1[1]
PGM17EN
1
Increment Address pointer = 0x0
Program 0 Address pointer = ADDR4 + 6
ISIF_FMTPGMAPU0[0]
PGM0UPDT
ISIF_FMTPGMAPS0[3:0]
PGM0APTR
4
Increment Address pointer = 0x0
Program 1 Address pointer = ADDR5 + 6
ISIF_FMTPGMAPU0[1]
PGM1UPDT
ISIF_FMTPGMAPS0[7:4]
PGM1APTR
5
Increment Address pointer = 0x0
Program 8 Address pointer = ADDR2 + 6
ISIF_FMTPGMAPU0[8]
PGM8UPDT
ISIF_FMTPGMAPS2[3:0]
PGM8APTR
2
Increment Address pointer = 0x0
Program 9 Address pointer = ADDR3 + 6
ISIF_FMTPGMAPU0[9]
PGM9UPDT
ISIF_FMTPGMAPS2[7:4]
PGM9APTR
3
Increment Address pointer = 0x0
Program 16 Address pointer = ADDR0 + 6
ISIF_FMTPGMAPU1[1]
PGM17UPDT
ISIF_FMTPGMAPS4[3:0]
PGM16APTR
0
Increment Address pointer = 0x0
Program 17 Address pointer = ADDR1 + 6
ISIF_FMTPGMAPU1[0]
PGM16UPDT
ISIF_FMTPGMAPS4[7:4]
PGM17APTR
1
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.6.7
ISS ISP ISIF Color Space Converter
Figure 232. ISS ISP ISIF Color Space Converter Block Diagram
ISIF_CSCCTL[0] CSCEN
ISIF_FMTCFG[0] FMTEN
U12
Input data
formatter
0
0
1
1
Color space
converter
camss-629
The color space converter (CSC) includes four 8-bit × 12-bit multipliers and one adder for the color space
conversion. These multiplier/adder units are used for the operation described in Figure 233. Data are
taken from two input lines during the operation.
Coefficients are signed 8-bit (decimal is 5 bits). Coefficients are set through the following registers:
• Coefficient M00: ISIF_CSCM0[7:0] CSCM00
• Coefficient M01: ISIF_CSCM0[15:8] CSCM01
• Coefficient M02: ISIF_CSCM1[7:0] CSCM02
• Coefficient M03: ISIF_CSCM1[15:8] CSCM03
• Coefficient M10: ISIF_CSCM2[7:0] CSCM10
• Coefficient M11: ISIF_CSCM2[15:8] CSCM11
• Coefficient M12: ISIF_CSCM3[7:0] CSCM12
• Coefficient M13: ISIF_CSCM3[15:8] CSCM13
• Coefficient M20: ISIF_CSCM4[7:0] CSCM20
• Coefficient M21: ISIF_CSCM4[15:8] CSCM21
• Coefficient M22: ISIF_CSCM5[7:0] CSCM22
• Coefficient M23: ISIF_CSCM5[15:8] CSCM23
• Coefficient M30: ISIF_CSCM6[7:0] CSCM30
• Coefficient M31: ISIF_CSCM6[15:8] CSCM31
• Coefficient M32: ISIF_CSCM7[7:0] CSCM32
• Coefficient M33: ISIF_CSCM7[15:8] CSCM33
Figure 233. ISS ISP ISIF Color Space Converter Operation
In1
In2
Out1 Out2
In4
In3
Out3 Out4
æ Out1 ö æ M00 M01 M02 M03 ö æ In1 ö
ç
÷ ç
֍
÷
ç Out2 ÷ = ç M10 M11 M12 M13 ÷ ç In2 ÷
ç Out3 ÷ ç M20 M21 M22 M23 ÷ ç In3 ÷
çç
÷÷ çç
÷÷ çç
÷÷
è Out4 ø è M30 M31 M32 M33 ø è In4 ø
M00–M33: Signed 8-bit data with 5-bit decimal
the value range –4=< Mxx<4
camss-618
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
421
ISS ISP
www.ti.com
The CSC can convert CMYG filtered CCD data to Bayer matrix (RGBG) data, as shown in Figure 234.
Figure 234. ISS ISP ISIF Color Space Converter Operation: CMYG to RGBG
Y
C
Y
C
G
R
G
R
M
G
M
G
B
G
B
G
Y
C
Y
C
G
R
G
R
M
G
M
G
B
G
B
G
0.5
0.5
–0.5
0
Y
0.5
–0.5
0.5
0
C
B
–0.5
0.5
0.5
0
M
G
0
0
0
1
G
G
R
=
camss-113
Figure 235 through Figure 237 show which input pixels are used for the operation. There is one-line
latency between the input and the output.
Figure 235. ISS ISP ISIF Color Space Conversion Example
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-114
Figure 236. ISS ISP ISIF 1st Pixel/1st Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-115
422
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 237. ISS ISP ISIF 2nd Pixel/1st Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-116
As shown in Figure 238 through Figure 241, the operation for the last pixel and the second last pixel uses
the same input data.
Figure 238. ISS ISP ISIF 2nd Last Pixel/1st Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-117
Figure 239. ISS ISP ISIF Last Pixel/1st Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-118
Figure 240. ISS ISP ISIF 1st Pixel/Last Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-119
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
423
ISS ISP
www.ti.com
Figure 241. ISS ISP ISIF 2nd Pixel/Last Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-120
Also, the operation for the last line and the second last line uses the same input data (see Figure 242 and
Figure 243).
Figure 242. ISS ISP ISIF 2nd Last Pixel/Last Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-121
Figure 243. ISS ISP ISIF Last Pixel/Last Line Generation
Y
C
Y
C
Y
C
Y
C
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
Y
C
Y
C
Y
C
Y
C
B
G
B
G
B
G
B
G
M
G
M
G
M
G
M
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
camss-122
In addition to the registers specific to the color space converter, some of the registers are shared with the
input data formatter to configure the valid area:
• ISIF_FMTSPH
• ISIF_FMTLNH
• ISIF_FMTLSV
• ISIF_FMTLNV
There must be at least 1 invalid pixel at the end of the line and one invalid line at the end of the frame.
To enable the color space conversion, set the ISIF_CSCCTL[0] CSCEN bit to 1.
424
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.6.8
ISS ISP ISIF Black Clamp
NOTE: For the memory access locations of the ISIF clamp, see Section 3.3.8.
Figure 244. ISS ISP ISIF Black Clamp Block Diagram
Black clamp
U12
0
S13
S13
1
Clamp value
(horizontal)
Clamp value
(vertical)
S13
S13 ISIF_CLAMPCFG[0]
CLEN
U12
ISIF_CLDCOFST[12:0]
CLDC
camss-630
The clamp value is calculated based on the pixel value of the OB region of the sensor. The clamp value is
calculated separately for horizontal and vertical directions to compensate the offset drift in both horizontal
and vertical directions. The sum of the horizontal and vertical clamp values is subtracted from the image
data, and then the additional DC offset is added (the ISIF_CLDCOFST[12:0] CLDC bit field, an S13Q0
value). This value is added whether the black clamp module is enabled or not.
The horizontal clamp is disabled through the ISIF_CLAMPCFG[2:1] CLHMD bit field.
To enable the black clamp module, set the ISIF_CLAMPCFG[0] CLEN bit to 1. The ISIF_PPLN[15:0]
PPLN bit field sets the pixel per line, and the number of pixel clock periods in one line HD period equals
PPLN + 1 pixel clock. The ISIF_PPLN[15:0] bit field is not used when the input is are already HD/VD.
3.3.6.8.1
ISS ISP ISIF Clamp Value for Horizontal Direction
The clamp value for horizontal direction is calculated using the pixel values at the upper OB region.
The maximum pixel value to be used for the clamp value calculation can be limited to 1023 if the pixel
value limitation is enabled (ISIF_CLHWIN0[6] CLHLMT = 1).
Clamp value calculation for horizontal direction can be disabled in case there is no upper OB region. The
operating modes are:
• Horizontal clamp value calculation is enabled. The calculated horizontal clamp value is subtracted from
the image data along with the vertical clamp value (ISIF_CLAMPCFG[2:1] CLHMD = 0x1).
• Horizontal clamp value is not updated. The horizontal clamp value used for the previous image is
subtracted from the image data along with the vertical clamp value (ISIF_CLAMPCFG[2:1] CLHMD =
0x2).
• Horizontal clamp value is not updated. Only the vertical clamp value is subtracted from the image data
(ISIF_CLAMPCFG[2:1] CLHMD = 0x0).
The number of windows in a row is set with the ISIF_CLHWIN0[4:0] CLHWC bit field.
Up to 32 windows in a row can be set for clamp value calculation. All the windows have the same size in a
format [2(ISIF_CLHWIN0[9:8] CLHWM+5)] pixels by [2(ISIF_CLHWIN0[13:12] CLHWN+1)] lines.
The ISIF_CLHWIN2[12:0] CLHSV and ISIF_CLHWIN1[12:0] CLHSH bit fields enable setting the position
of the first optical black clamp window in the frame. The pixel and line offset are in a range [0:8191]. The
ISIF_HDW register sets the width of the HD.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
425
ISS ISP
www.ti.com
Figure 245. ISS ISP ISIF Clamp Value for Horizontal Direction
HD
2(ISIF_CLHWIN0[9:8] CLHWM+5)
ISIF_CLHWIN2[12:0]
CLHSV
win0
VD
win1
winN
ISIF_CLHWIN1[12:0]
CLHSH
2(ISIF_CLHWIN0[13:12] CLHWN+1)
Linear
interpolation
Optical
black
region
Valid data region
Average
Windows settings details
win0
win1
x
(A)
winN
CLHWM-x
(B)
(C)
camss-132
The clamp value for horizontal direction calculation steps is:
1. Calculate the average of the pixel value in each window (ave_win0 to ave_winN).
Calculation Steps
win0
win1
win2
Average of the pixel
value
ave_win0
ave_win1
ave_win2
...
wini
wini + 1
ave_wini
ave_wini + 1
...
winN
ave_winN
2. Set the average of the left-most window or the right-most window as the base value B_V:
• B_V = ave_win0 (if ISIF_CLHWIN0[5] CLHWBS = 0x0, case 1)
• B_V = ave_winN (if ISIF_CLHWIN0[5] CLHWBS = 0x1, case 2)
3. Subtract the base value from the average of each window. Use this value as a clamp value for each
window.
Calculation Steps
win0
Clamp value for each window
clamp_win0 =
ave_win0- B_V
...
wini
wini+1
clamp_wini =
ave_wini-B_V
clamp_wini + 1
= ave_wini + 1B_V
...
winN
clamp_winN =
ave_winN-B_V
4. Acquire the horizontal distance (X and CLHWM – X) from the valid pixel to be processed to the center
of the closest two windows.
426
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
5. Calculate the clamp value of the valid pixel by linear interpolation, using the clamp value of the closest
two windows (i and i + 1).
• Case 1: interpolated_clamp_winX = (clamp_wini + 1 – clamp_wini) * X / CLHWM
• Case 2: interpolated_clamp_winX = (clamp_wini – clamp_winN) * (CLHWM - X) / CLHWM +
(clamp_wini + 1 – clamp_winN) * X / CLHWM
6. If the valid pixel is on the left of the center of the left-most window, the clamp value of the left-most
window is applied. If the valid pixel is on the right of the center of the right-most window, the clamp
value of the right-most window is applied.
The clamp values calculated (A), (B) and (C) are:
• Case1: Base is win0 (Left-most window: ISIF_CLHWIN0[5] CLHWBS = 0x0)
– (A): zero
– (B): (clamp_wini + 1 – clamp_wini) * X / CLHWM
– (C): (clamp_winN – clamp_win0)
• Case2: Base is winN (Right-most window: ISIF_CLHWIN0[5] CLHWBS = 0x1)
– (A): (clamp_win0 – clamp_winN)
– (B): (clamp_wini – clamp_winN) * (CLHWM – X) / CLHWM + (clamp_wini + 1 – clamp_winN) * X /
CLHWM
– (C): zero
Each interpolated value interpolated_clamp_winX is then subtracted to the associated column.
3.3.6.8.2
ISS ISP ISIF Clamp Value for Vertical Direction
The clamp value for vertical direction is calculated using the pixel values at the left or right OB region. Line
average is calculated for the OB H valid period (2(ISIF_CLVWIN0[2:0] CLVOBH + 1)). The averages for the previous
lines are also added back to reduce the difference between the lines, as shown in Figure 246.
Figure 246. ISS ISP ISIF Clamp Value for Vertical Direction Calculation
U12
Input data
U12
Line
average
k
Valid during
OB H valid period
1–k
Z–1
Clamp value
(vertical direction)
@ the end of OB H valid period
Reset at the beginning of OB V valid
camss-619
•
•
Clamp Value (Vn) = Line Average (Vn) * k + Clamp Value (V1) * (1-k)
k = ISIF_CLVWIN0[15:8] CLVCOEF
The position of the first vertical black clamp window is set with the ISIF_CLVWIN2[12:0] CLVSV and
ISIF_CLVWIN1[12:0] CLVSH bit fields. The number of vertical windows is set with the
ISIF_CLVWIN3[12:0] CLVOBV bit field. ISIF_VDW sets the width of the VD.
The accumulator, which holds the vertical clamp value for the previous line, is reset at the beginning of the
OB V valid. The reset value can be selected through the ISIF_CLVWIN0[5:4] CLVRVSL bit field:
• ISIF_CLVWIN0[5:4] CLVRVSL = 0x0: The base value is calculated for horizontal direction (left-most
window win0 or right-most winn set with ISIF_CLHWIN0[5] CLHWBS).
• ISIF_CLVWIN0[5:4] CLVRVSL = 0x1: The base value is set through the configuration register
(ISIF_CLVRV[11:0] CLVRV).
• ISIF_CLVWIN0[5:4] CLVRVSL = 0x2: No update (same as the previous image)
The following figures show the OB valid settings and associated vertical clamp value calculation when OB
region is at the left (see Figure 247) and when OB region is at the right (see Figure 248). Each line
average value is subtracted from the associated line valid region data.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
427
ISS ISP
www.ti.com
Figure 247. ISS ISP ISIF Clamp Value for Vertical Direction With OB Region at the Left
HD
Optical black region
ISIF_CLVWIN2[12:0]
CLVSV
VD
OB H valid
2(ISIF_CLVWIN0[2:0] CLVOBH+1)
Filter reset timing
ISIF_CLVWIN1[12:0]
CLVSH
OB V valid
ISIF_CLVWIN3[12:0]
CLVOBV
Valid data region
Average
Filter
camss-133
Figure 248. ISS ISP ISIF Clamp Value for Vertical Direction With OB Region at the Right
HD
Optical black region
VD
ISIF_CLVWIN2[12:0]
CLVSV
OB H valid
2(ISIF_CLVWIN0[2:0] CLVOBH+1)
Filter reset timing
ISIF_CLVWIN1[12:0] CLVSH
OB V valid
ISIF_CLVWIN3[12:0] CLVOBV
Valid data region
Average
Filter
428
camss-620
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.6.9
ISS ISP ISIF Vertical Line Defect Correction (VDFC)
Figure 249 shows the block diagram of the vertical line defect (VDFC) correction.
Figure 249. ISS ISP ISIF Vertical Line Defect Correction Block Diagram
VDFC
S13
0
VDFC
S13
1
DFCCTL[4]
camss-631
The VDFC block can correct up to eight vertical line defects (see Figure 250).
Figure 250. ISS ISP ISIF Vertical Line Defects
Defect 1(H1, V1)
Defect 2(H2, V2)
camss-134
The correction method is common to all the defects and can be selected through the ISIF_DFCCTL[6:5]
VDFCSL bit field.
There are two different methods to correct vertical line defects (ISIF_DFCCTL[6:5] VDFCSL):
• Method 1: Data is replaced by an average (ISIF_DFCCTL[6:5] VDFCSL = 0x2):
– The defect is replaced by the average of pixel (i – 2) and pixel (i + 2)
• Method 2: Data is subtracted by a defect level (ISIF_DFCCTL[6:5] VDFCSL = 0x0 or 0x1):
– A saturation level is defined in the ISIF_VDFSATLV[11:0] VDFSLV bit field.
– The coordinates of the defect:
• Are defined in the ISIF_DFCMEM0[12:0] DFCMEM0 and ISIF_DFCMEM1[12:0] DFCMEM1 bit
fields
• Are 13 bits wide for horizontal and vertical direction, so an image size up to 8192 × 8192 is
supported
– If the data is not saturated (data VDFSLV):
• The defect is corrected by subtracting the defect level. A different defect level is defined for:
• The point of the defect (V = Vdefect): SUB1 defect level is defined in the
ISIF_DFCMEM2[7:0] DFCMEM2 bit field.
• The pixels lower than the defect (V Vdefect): SUB2 defect level is defined in the
ISIF_DFCMEM3[7:0] DFCMEM3 bit field.
• The pixels upper than the defect (V Vdefect): Defect level is defined in the
ISIF_DFCMEM4[7:0] DFCMEM4 bit field.
• Each defect level (value to be subtracted from the data) described previously can be up-shifted
through the ISIF_DFCCTL[10:8] VDFLSFT bit field.
• Vertical line defect correction for upper pixels can be disabled through the ISIF_DFCCTL[7]
VDFCUDA bit.
– If the data is saturated (VDFSLV), there are two possibilities:
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
429
ISS ISP
www.ti.com
•
•
ISIF_DFCCTL[6:5] VDFCSL = 0x0: Data is simply fed through (not subtracted).
ISIF_DFCCTL[6:5] VDFCSL = 0x1: Horizontal interpolation ((i 2) + (i + 2))/2 (data is replaced by
interpolation or data is subtracted with interpolation)
The ISIF_LPFR register sets the number of half lines per frame or field: VD period = (L PFR+ 1)/2 lines.
LPFR is not used when HD and VD are inputs.
The following paragraphs concern only method 2 correction.
The coordinates of the defects and the defect levels to be subtracted from the data must be set to the
processing shown in Table 202.
Table 202. ISS ISP ISIF Vertical Line Defect Table in Memory
Bit
Defect Information
12:0
Vertical position of the defects
25:13
Horizontal position of the defects
33:26
Defect level of the vertical line defect position (V = Vdefect)
41:34
Defect level of the pixels upper than the vertical line defect (V
Vdefect)
49:42
Defect level of the pixels lower than the vertical line defect (V
Vdefect)
The defect must be set from left to right, as shown in Figure 251.
Figure 251. ISS ISP ISIF Vertical Line Defects
Defect 3
Order to be set in a memory:
Defect 1
1. Defect 1
2. Defect 2
3. Defect 3
Defect 2
:
:
camss-135
Vertical line defect correction is enable by setting the ISIF_DFCCTL[4] VDFCEN bit to 1, but the
procedure explained in Section 3.3.6.9.1, ISS ISP ISIF Vertical Line Defect Table Update Procedure, must
be respected.
3.3.6.9.1
ISS ISP ISIF Vertical Line Defect Table Update Procedure
The following procedure must be respected to write the vertical line defect table in memory.
1. ISIF_DFCMEMCTL[4] DFCMCLR = 0x1
2. Ensure that ISIF_DFCCTL[4] VDFCEN is disabled (0x0).
3. Write the V coordinate of the first defect to the ISIF_DFCMEM0[12:0] DFCMEM0 bit field.
4. Write the H coordinate of the first defect to the ISIF_DFCMEM1[12:0] DFCMEM1 bit field.
5. Set the defect level to:
• ISIF_DFCMEM2[7:0] DFCMEM2
• ISIF_DFCMEM3[7:0] DFCMEM3
• ISIF_DFCMEM4[7:0] DFCMEM4
430
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
6. Set the ISIF_DFCMEMCTL[0] DFCMWR bit to 1 with the ISIF_DFCMEMCTL[2] DFCMARST bit set to
1.
7. Wait until the ISIF_DFCMEMCTL[0] DFCMWR bit is cleared.
8. Write the next data to:
• ISIF_DFCMEM0[12:0] DFCMEM0
• ISIF_DFCMEM1[12:0] DFCMEM1
• ISIF_DFCMEM2[7:0] DFCMEM2
• ISIF_DFCMEM3[7:0] DFCMEM3
• ISIF_DFCMEM4[7:0] DFCMEM4
9. Set the ISIF_DFCMEMCTL[0] DFCMWR bit to 1 with the ISIF_DFCMEMCTL[2] DFCMARST bit
cleared.
10. Repeat 4~5 times until all entries (up to 8) are written to the vertical line defect table.
11. In case the defect entry is less than 8, an extra write cycle is required to fill the next table location with
a certain value.
12. Clear the ISIF_DFCMEM0[12:0] DFCMEM0 bit field to all 0, set the ISIF_DFCMEM1[12:0] DFCMEM1
to all 1, and set the ISIF_DFCMEMCTL[0] DFCMWR bit to 1 with the ISIF_DFCMEMCTL[2]
DFCMARST bit cleared.
13. Enable VDFC by setting the ISIF_DFCCTL[1] VDFCEN bit.
3.3.6.10
ISS ISP ISIF Lens Shading Correction (2D-LSC)
NOTE: For the memory access locations of the 2D-LSC table, see Section 3.3.8.
Figure 252. ISS ISP ISIF 2D-LSC Block Diagram
2D-LSC
ISIF_2DLSCCFG[0]
ENABLE
U13
0
2D LSC
S13
1
camss-632
LSC is useful for correcting optical artifacts that cause image brightness to decrease starting from the
center of the image and going out to the edges.
The LSC module implements a per pixel offset and gain adjustment in the RAW Bayer domain (2 × 2 color
pattern). The offset is applied before gain multiplication.
The offset and gains are stored in a LUT, which is stored in SDRAM and is loaded in real time. The
submodule prefetches the data from SDRAM such that no underflow occurs. Underflow occurs when the
offset and gain data required for the current pixel are not available.
The data stored in the LUT is downsampled; that is, there is no gain or offset per pixel. The downsampling
factor is programmable. High downsampling ratios lead to a smaller LUT, lower accuracy, and lower
memory bandwidth. A low downsampling ratio leads to a bigger LUT, higher accuracy, and higher memory
bandwidth.
When the offset and gain values are loaded, they are upscaled to the incoming image resolution. The
missing table values are computed through bilinear interpolation.
To enable the 2D-LSC module, set the ISIF_2DLSCCFG[0] ENABLE bit to 1.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
431
ISS ISP
www.ti.com
3.3.6.10.1 ISS ISP ISIF 2D-LSC Active Region Settings
The gain and offset maps are internally up-sampled to full resolution before being applied to the image. In
order to account for all the possible cropping schemes and zoom ratios, the 2D-LSC can be configured
such that a single gain map can be stored in memory that maps to sensor lens. The 2D-LSC active region
is defined by Figure 253.
Figure 253. ISS ISP ISIF 2D-LSC Active Region for ISIF Input Frame
HD
ISIF_PPLN[15:0] PPLN + 1
VD
(ISIF_LPFR[15:0] LPFR+1)/2
ISIF_LSCVOFST[13:0] VOFST
ISIF_LSCHOFST[13:0]
HOFST
H
=
ISIF_LSCVVAL[13:0]
VVAL + 1
W = ISIF_LSCHVAL[13:0] HVAL + 1
LSC
active region
Global frame
camss-621
3.3.6.10.1.1 ISS ISP ISIF 2D-LSC Gain and Offset Tables
The gain and offset map are MxN downsampled:
• M is the horizontal sampling factor.
• N is the vertical sampling factor.
• M and N are {8, 16, 32, 64, 128} independently.
• N = M. M is set in the ISIF_2DLSCCFG[14:12] GAIN_MODE_M bit field.
• N is set in the ISIF_2DLSCCFG[10:8] GAIN_MODE_N bit field.
The starting point of the preconfigured lens shading map can be modified in software to align with the ISIF
input image frame. The location of the gain and offset mask data in memory is specified by :
• For gain map:
– Table base address: ISIF_2DLSCGRBU[15:0] BASE31_16 and ISIF_2DLSCGRBL[15:0]
BASE15_0
• For offset map:
– Table base address: ISIF_2DLSCORBU[15:0] BASE and ISIF_2DLSCORBL[15:0] BASE
The input address must be aligned to a 4-byte boundary.
In the full resolution case, the address is set to the beginning of the map. When the LSC active region is
defined over a cropped region of the full image, the SDRAM input address can be set to the upper-left
corner of the grid closest to the beginning of the active region, and the ISIF_2DLSCINI[6:0] X and
ISIF_2DLSCINI[14:8] Y bit fields mark the offset into the upsampled gain and offset map where the active
region begins. Figure 254 shows the LSC active region with respect to the gain and offset map grid.
Because (X, Y) deals with the pixel phase inside a gain and offset map grid, X and Y must each be less
than M and N, respectively.
432
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Before applying the gain or offset table, the table is internally upsampled and interpolated back to full
resolution via bilinear interpolation.
Figure 254. ISS ISP ISIF Gain and Offset Mask Upsampling via Bilinear Interpolation
M
=
Table base address
2(ISIF_2DLSCCFG[14:12] GAIN_MODE_M)
Y = ISIF_2DLSCINI[14:8] Y
X = ISIF_2DLSCINI[6:0] X
N
=
2(ISIF_2DLSCCFG[10:8] GAIN_MODE_N)
Y
X
LSC active region
Interpolate
camss-123
The gain table format is set in the ISIF_2DLSCCFG[3:1] GAIN_FORMAT bit field. 8-bit entries are
supported in the gain map (in U8Q8, U8Q7, U8Q6, and U8Q5 format with optional base of 1.0 to shift the
range up).
8-bit entries are supported in the offset map (in S8Q0 format). An optional shifting up for offsets is
possible. The shift up value is selected through the ISIF_2DLSCOFST[6:4] OFSTSFT bit field. A scaling
factor for offsets is defined in the ISIF_2DLSCOFST[15:8] OFSTSF bit field.
The offset control in the 2D-LSC module can be enabled or disabled through the ISIF_2DLSCOFST[0]
OFSTEN bit.
For an LSC active region size of W × H (the output and input are the same size), and the gain and offset
maps are MxN downsampled, a table with the following values is needed:
• (ceil[(X + W) / M] + 1) x (ceil[(Y + H) / N] + 1) × 4 bytes data in external memory organized as:
– (ceil[(InitX + W) / M] +1) lines of data
– Each line having at least (ceil[(InitY + H) / N] + 1) × 4 data points
Extra data at end of each line can be skipped by the line offset register parameter:
– For gain map:
• Line offset: ISIF_2DLSCGROF[15:0] OFFSET
– For offset map:
• Line offset: ISIF_2DLSCOROF[15:0] OFFSET
– Each line offset must start at a 32-bit aligned boundary.
3.3.6.10.1.2 ISS ISP ISIF 2D-LSC Gain and Offset Table Upsampling
Upsampling of the pixel-by-pixel gains is performed by locating the four same-color anchors for each
destination gain value and applying bilinear interpolation.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
433
ISS ISP
www.ti.com
The gain and offset mask function is neutral to color pattern. The starting color of the gain and offset mask
must be consistent with the starting color of the image, and can be any color. To align starting colors, the
X and Y values must be even. The 2D-LSC engine upsamples each phase of the mask data as a separate
plane and applies the upsampled mask to the image with the same color phasing. In other words, the red
gains are interpolated with red gains, and applied to the red input pixels. The same is done for each of the
other three colors in the color pattern. The 2D-LSC module is designed to work with Bayer CFA data,
having the R/Gr/Gb/B color pattern. For the purpose of functional description, assume red is the starting
color, but any other starting color or other 2 × 2 pattern can be used by placing color gains in the
appropriate order.
3.3.6.10.1.3 ISS ISP ISIF Application of Gain and Offset to Image Pixels
The gain value interpolated for each pixel is multiplied with a corresponding input pixel. An offset is
applied before the gain. The product is rounded to the nearest integer and then clipped or saturated to the
valid range of 13 bits.
The following equation describes the operation of the LSC in terms of offset and gain:
out[x,y] = (in[x,y] + a*(ofst[x,y] T)) * gain[x,y]
•
•
•
•
•
•
(5)
in[x, y] are the input pixels, 13 bits signed.
ofst[x, y] are the upsampled offset points.
T is the upshift value applied to the result of the offset interpolation points (0 – 5) set through the
ISIF_2DLSCOFST[6:4] OFSTSFT bit field.
a is the offset gain value in U8Q7 format set through the ISIF_2DLSCOFST[15:8] OFSTSF bit field.
gain[x, y] are the upsampled gain points.
out[x, y] are the resulting output pixels, 13 bits signed.
3.3.6.10.1.4 ISS ISP ISIF Enabling/ Disabling the 2D-LSC Module
LSC operates on a single frame or continuously, depending on the firmware programming.
Upon power-on reset (POR), the 2D-LSC module is disabled and input pixels are copied to the output,
bypassing any shading operation.
When enabling or disabling the 2D-LSC, caution must be taken on the timing of register modifications. To
avoid causing a prefetch error or other unexpected behavior, the following safeguards must be
implemented:
1. While configuring the 2D-LSC registers, the input clock into the ISIF should be toggling.
2. All of the 2D-LSC registers must be configured appropriately before enabling the ISIF_2DLSCCFG[0]
ENABLE bit.
3. After setting the ENABLE bit to 1, the hardware immediately begins fetching the first two rows of gain
and offset data entries from external memory. When this is complete, the ISIF_2DLSCIRQST[2]
PREFETCH_COMPETED status flag is set.
NOTE: If the ENABLE bit is disabled before the ISIF_2DLSCIRQST[3] SOF status flag is set, the
ISIF_2DLSCIRQST[1] PREFETCH_ERROR flag is set and the state of the 2D-LSC
submodule may lead to unexpected errors. Therefore, the ENABLE bit must not be disabled
until after the ISIF_2DLSCIRQST[3] SOF status flag is set.
4. Appropriate gains and offsets are applied to the image pixels. Pixels outside the LSC active region are
passed through unaltered. When the 2D-LSC operation on the active region completes, the
ISIF_2DLSCIRQST[0] DONE status flag is set.
5. At this point:
• If the ENABLE bit is still set to 1, the hardware immediately begins to prefetch the gain and offset
data entries for the next frame and waits for the active region of the next frame to arrive.
• If the ENABLE bit is set to 0, it stops LSC operation once the active region is passed, and goes
into idle until the ENABLE bit is written to 1 again.
434
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
NOTE: To provide a mechanism for firmware to recover from the LSC module waiting indefinitely for
the input image, if LSC_ENABLE is written to 0 after it has started gain/offset map
prefetching, but before the LSC gets to the next active region, the LSC operation is aborted
and turned idle, and any prefetched gain/offset entries are discarded. This can happen
before or after the next start-of-frame.
NOTE: Therefore, because of the constraints set in point 3, the ENABLE register bit must be
disabled only after the ISIF_2DLSCIRQST[3] SOF status flag is set and before the
ISIF_2DLSCIRQST[0] DONE status flag is set for that same frame.
It is suggested that when the 2D-LSC or the whole ISIF needs to be disabled for switching
modes, the ISIF_2DLSCIRQST[3] SOF interrupt be enabled so that software knows when it
is safe to disable the 2D-LSC. Then the ISIF can be disabled after the ISIF_2DLSCIRQST[0]
DONE status signal is set for that frame.
NOTE: The LSC_ENABLE bit, once written to 1, must not be cleared until at least one vpi_clk clock
cycle after start-of-frame, to ensure correct processing.
3.3.6.10.1.5 ISS ISP ISIF 2D-LSC Events and Status Checking
The 2D-LSC submodule can generate events on a single interrupt line. These events are further
remapped at the ISP level in ISP5_IRQENABLE_SET__0.ISIF_INT_3 ISP5_IRQENABLE_SET__3.ISIF_INT3.
Four 2D-LSC events can be generated:
• DONE: LSC done. This event triggers when the LSC submodules transition from ACTIVE state to IDLE
state.
• PREFETCH_ERROR: Gain table prefetch error. This event triggers when the tables stored in SDRAM
are read too slowly. After this event is asserted, the LSC disables the LSC computation until the
beginning of the next frame.
• PREFETCH_COMPLETE: Gain table prefetch complete. This event triggers when data prefetching
from SDRAM completes. Data prefetching must complete by the time the first pixel of a frame comes.
The event triggers when the buffer contains three full rows of data.
• SOF: This event signals the start of the LSC valid region. The LSC configuration registers for the next
frame can be updated after the LSC SOF triggers.
The ISIF_2DLSCIRQEN register can be configured to select which events are masked and which are
propagated to the LSC interrupt signal. The ISIF_2DLSCIRQST register can be read and cleared to
identify which events have occurred.
In addition, the 2D-LSC module provides the following status bit:
• BUSY: This indicates that LSC has entered the active region vertically. This bit remains on during
horizontal blanking, and turns off only after the entire active region of the current frame is processed.
3.3.6.10.1.6 ISS ISP ISIF Supported On-the-Fly 2D-LSC Configurations
The 2D-LSC prefetch memory is equal to 2 × 1536 × 32 bits. This memory is sized to fetch three lines of
8-bit gain and 8-bit offset × four color components per paxel. Given an image sensor of horizontal
resolution H, there are floor [(H / ISIF_2DLSCCFG[14:12] GAIN_MODE_M) + 1] paxels per line, where M
is the horizontal LSC paxel size.
Table 203 shows the LSC horizontal paxel size, which can be supported for different image sensor
resolutions. When M = 8, some resolutions cannot be supported on the fly (orange-shaded cells in the
table); the way to process such large images is to use vertical frame division.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
435
ISS ISP
www.ti.com
Table 203. ISS ISP ISIF Supported On-the-Fly LSC Configurations
MPix
Aspect Ratio
Horizontal LSC Paxel Size: M = 2[ISIF_2DLSCCFG[14:12] GAIN_MODE_M]
Line Size
8
16
32
64
128
Maximum
–
–
5376
2019
1011
507
255
129
16
16
9
5333
2003
1003
503
253
128
16
4
3
4619
1735
869
436
220
111
16
3
2
4899
1840
922
462
233
118
12
16
9
4619
1735
869
436
220
111
12
4
3
4000
1503
753
378
191
97
12
3
2
4243
1594
798
401
202
102
10
16
9
4216
1584
794
398
201
102
10
4
3
3651
1372
688
345
174
89
10
3
2
3873
1455
729
366
185
94
8
16
9
3771
1417
710
357
180
91
8
4
3
3266
1228
615
309
156
80
8
3
2
3464
1302
653
328
165
84
3.3.6.10.1.7 ISS ISP ISIF Bandwidth Requirements on BL Read Port
See Section 3.3.6.18.2 for details.
3.3.6.11
ISS ISP ISIF White Balance
Figure 255 shows the white balance block diagram.
Figure 255. ISS ISP ISIF White Balance Block Diagram
White balance
ISIF_CGMMAWD[12] ISIF_CGMMAWD[8]
WBEN0
OFSTEN0
U12
S13
Clip
GAIN
C
S13
S13
OFFSET
ISIF_CGAMMAWD[13] ISIF_CGAMMAWD[9]
WBEN1
OFSTEN1
U12
IPIPEIF
(IPIPE datapath)
Clip
S13
S13
GAIN
OFFSET
ISIF_CGAMMAWD[14] ISIF_CGAMMAWD[10]
WBEN2
OFSTEN2
U12
Clip
S13
S13
GAIN
OFFSET
U10
12- to
10-bit
IPIPEIF
(H3A datapath)
U12 data[11:2]
GAIN:
ISIF_CRGAIN[11:0] CGR for R/Ye
ISIF_CGRGAIN[11:0] CGGR for Gr/Cy
ISIF_CGBGAIN[11:0] CGGB for Gb/Cy
ISIF_CBGAIN[11:0] CGB for B/Mg
OFFSET: ISIF_COFSTA[11:0] COFT
camss-633
Color pattern settings are set through the ISIF_CCOLP register. Moreover, through this register the pixel
position from 0 to 3 can be set to the needed Bayer universal camera filter color pattern (RGB/CYGM).
The CFA pattern can be in two modes, stripe or mosaic, and is set through the ISIF_CGAMMAWD[5]
CFAP bit.
436
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
There are color-dependent gain controls for the three outputs: BL output, IPIPEIF (IPIPE path) output, and
IPIPEIF (H3A path) output. Gain applied to each data is selected according to the pixel position and the
color pattern settings. Gain factors are common for the three data paths. Gain is in U11Q9 format, which
ranges from 0 to 3 + 511/512.
The gain factor is set through the following registers:
• R/Ye gain: ISIF_CRGAIN[11:0] CGR
• Gr/Cy gain: ISIF_CGRGAIN[11:0] CGGR
• Gb/Cy gain: ISIF_CGBGAIN[11:0] CGGB
• B/Mg gain: ISIF_CBGAIN[11:0] CGB
Gain control can be enabled or disabled individually for each path.
• Enable or disable gain for the BL path: ISIF_CGAMMAWD[12] WBEN0.
• Enable or disable gain for the IPIPEIF (IPIPE) path: ISIF_CGAMMAWD[13] WBEN1.
• Enable or disable gain for the IPIPEIF (H3A) path: ISIF_CGAMMAWD[14] WBEN2.
After the gain control, a single offset value can be added to each path individually. This offset is common
for the three paths and is set through the ISIF_COFSTA[11:0] COFT bit field. The offset value is U12,
which ranges from 0 to 4095. Data (S13) are then truncated to U12.
• Enable or disable offset for the BL path: ISIF_CGAMMAWD[8] OFSTEN0.
• Enable or disable offset for the IPIPEIF (IPIPE) path: ISIF_CGAMMAWD[9] OFSTEN1.
• Enable or disable offset for the IPIPEIF (H3A) path: ISIF_CGAMMAWD[10] OFSTEN2.
3.3.6.12
ISS ISP ISIF Low-Pass Filter (LPF)
Figure 256 shows the low-pass filter block diagram.
Figure 256. ISS ISP ISIF Low-Pass Filter Block Diagram
LPF
ISIF_MODESET[14]
HLPF
U12
C
LPF
1
U12
0
camss-634
An optional horizontal low-pass anti-aliasing filter (LPF) can be applied (the ISIF_MODESET[14] HLPF bit)
after reframing. The low-pass filter consists of a simple 3-tap (1/4, 1/2, and 1/4) filter. Two pixels on the
left and two pixels on the right of each line are cropped if the filter is enabled. Use of the LPF is intended
for bandwidth reduction if culling is enabled.
NOTE: For YUV data, the LPF must be disabled (ISIF_MODESET[14] HLPF = 0x0).
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
437
ISS ISP
3.3.6.13
www.ti.com
ISS ISP ISIF A-Law Compression
Figure 257shows the A-Law compression block diagram.
Figure 257. ISS ISP ISIF A-Law Compression Block Diagram
A-Law compression
ISIF_CGAMMAWD[0] CCDTBL
U12
U12
D
0
12- to
10-bit
U10
U12 data[11:2]
A-Law
compression
10-to-8
U8
8- to
12-bit
U12
1
LSB-align
0000 and U8
camss-635
An optional 10-to-8-bit A-Law compression using a fixed A-Law table can be applied
(ISIF_CGAMMAWD[0] CCDTBL) as the final processing stage. Using this compression causes the data
width to be reduced to 8 bits and allows packing to 8 bits/pixel when saving to memory. Because data
resolution can be greater than 10 bits at this stage, the 10 bits for input to the A-Law operation must be
selected (ISIF_CGAMMAWD[4:1] GWDI).
The IPIPEIF module has an inverse A-Law table (A-Law decompression) option so that this nonlinear
operation can be reversed if this saved data is to be read back in for further processing.
NOTE: Do not use A-Law compression (ISIF_CGAMMAWD[0] CCDTBL = 0) with YUV data.
Figure 258 shows the A-Law table diagram, and Figure 259 shows the A-Law table values.
Figure 258. ISS ISP ISIF A-Law Table Diagram
256
192
128
64
0
0
256
512
768
1024
camss-264
438
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 259. ISS ISP ISIF A-Law Table Values
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
78
79
80
81
82
83
84
84
85
86
87
88
88
89
90
91
91
92
93
93
94
95
96
96
97
98
98
99
100
100
101
102
102
103
103
104
105
105
106
106
107
108
108
109
109
110
110
111
112
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
112
113
113
114
114
115
115
116
116
117
117
118
118
119
119
120
120
121
121
122
122
123
123
124
124
125
125
125
126
126
127
127
128
128
129
129
129
130
130
131
131
132
132
132
133
133
134
134
134
135
135
136
136
136
137
137
137
138
138
139
139
139
140
140
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
140
141
141
142
142
142
143
143
143
144
144
144
145
145
145
146
146
146
147
147
147
148
148
148
149
149
149
150
150
150
151
151
151
152
152
152
152
153
153
153
154
154
154
155
155
155
155
156
156
156
157
157
157
157
158
158
158
159
159
159
159
160
160
160
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
161
161
161
161
162
162
162
162
163
163
163
163
164
164
164
164
165
165
165
166
166
166
166
167
167
167
167
168
168
168
168
168
169
169
169
169
170
170
170
170
171
171
171
171
172
172
172
172
173
173
173
173
173
174
174
174
174
175
175
175
175
175
176
176
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
176
176
177
177
177
177
177
178
178
178
178
178
179
179
179
179
179
180
180
180
180
181
181
181
181
181
182
182
182
182
182
183
183
183
183
183
184
184
184
184
184
185
185
185
185
185
185
186
186
186
186
186
187
187
187
187
187
188
188
188
188
188
188
189
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
189
189
189
189
190
190
190
190
190
190
191
191
191
191
191
191
192
192
192
192
192
193
193
193
193
193
193
194
194
194
194
194
194
195
195
195
195
195
195
196
196
196
196
196
196
197
197
197
197
197
197
198
198
198
198
198
198
198
199
199
199
199
199
199
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
200
200
200
200
200
200
201
201
201
201
201
201
201
202
202
202
202
202
202
202
203
203
203
203
203
203
204
204
204
204
204
204
204
205
205
205
205
205
205
205
206
206
206
206
206
206
206
207
207
207
207
207
207
207
208
208
208
208
208
208
208
208
209
209
camss-262
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
439
ISS ISP
www.ti.com
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
Input
A-Law
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
209
209
209
209
209
210
210
210
210
210
210
210
211
211
211
211
211
211
211
211
212
212
212
212
212
212
212
212
213
213
213
213
213
213
213
214
214
214
214
214
214
214
214
215
215
215
215
215
215
215
215
216
216
216
216
216
216
216
216
217
217
217
217
217
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
217
217
217
217
218
218
218
218
218
218
218
218
219
219
219
219
219
219
219
219
220
220
220
220
220
220
220
220
220
221
221
221
221
221
221
221
221
221
222
222
222
222
222
222
222
222
222
223
223
223
223
223
223
223
223
223
224
224
224
224
224
224
224
224
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
224
225
225
225
225
225
225
225
225
225
226
226
226
226
226
226
226
226
226
227
227
227
227
227
227
227
227
227
227
228
228
228
228
228
228
228
228
228
229
229
229
229
229
229
229
229
229
229
230
230
230
230
230
230
230
230
230
230
231
231
231
231
231
231
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
231
231
231
231
232
232
232
232
232
232
232
232
232
232
233
233
233
233
233
233
233
233
233
233
233
234
234
234
234
234
234
234
234
234
234
235
235
235
235
235
235
235
235
235
235
235
236
236
236
236
236
236
236
236
236
236
236
237
237
237
237
237
237
237
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
237
237
237
237
238
238
238
238
238
238
238
238
238
238
238
239
239
239
239
239
239
239
239
239
239
239
240
240
240
240
240
240
240
240
240
240
240
240
241
241
241
241
241
241
241
241
241
241
241
242
242
242
242
242
242
242
242
242
242
242
242
243
243
243
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
243
243
243
243
243
243
243
243
243
244
244
244
244
244
244
244
244
244
244
244
244
245
245
245
245
245
245
245
245
245
245
245
245
246
246
246
246
246
246
246
246
246
246
246
246
246
247
247
247
247
247
247
247
247
247
247
247
247
247
248
248
248
248
248
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
248
248
248
248
248
248
248
249
249
249
249
249
249
249
249
249
249
249
249
249
250
250
250
250
250
250
250
250
250
250
250
250
250
250
251
251
251
251
251
251
251
251
251
251
251
251
251
252
252
252
252
252
252
252
252
252
252
252
252
252
252
253
253
253
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
253
253
253
253
253
253
253
253
253
253
254
254
254
254
254
254
254
254
254
254
254
254
254
254
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
camss-263
440
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.6.14
ISS ISP ISIF Culling
Figure 260 shows the culling block diagram.
Figure 260. ISS ISP ISIF Culling Block Diagram
H,V and YUV4:2:2
culling
D
U12
camss-636
The culling block performs a programmable decimation function for horizontal, vertical, and YUV4:2:2 data
directions. The horizontal and vertical decimation of image data can be controlled by two registers.
The horizontal culling operation allows selected pixel data to be culled (deleted) from a line. The
ISIF_CULH register specifies the horizontal culling pattern for even and odd lines:
• Even lines: ISIF_CULH[15:8] CLHE
• Odd lines: ISIF_CULH[16:0] CLHO
The vertical culling operation allows selected lines to be culled from a frame. The ISIF_CULV register
specifies the pattern for the vertical direction. The LSBs of CULV represent the top line of the CCD; the
MSB is the seventh line.
Figure 261 is an example of how register values apply the decimation pattern to the data. The red pixels
are saved to memory and the white pixels are discarded. In this example, CULH = 0x59C4 and CULV =
0x0066.
NOTE: Culling can be used with YUV data, but care must be taken to preserve the YUV4:2:2 output
format.
Figure 261. ISS ISP ISIF Example for Decimation Pattern
LSB
MSB
ISIF_CULH[7:0] CLHE
0
0
1
0
0
0
1
1
ISIF_CULH[15:8] CLHO
1
0
0
1
1
0
1
0
th
0 line
st
1 line
2
nd
0
1
line
1
3 line
0
rd
th
4 line
th
5 line
th
6 line
th
7 line
0
1
1
0
ISIF_CULV[7:0]
CULV
camss-265
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
441
ISS ISP
3.3.6.15
www.ti.com
ISS ISP ISIF 12-to-8 bit DCPM Compression Block
In ISIF, there is a DPCM compression block, which is between the culling module and the storage
formatter module. This block can compress 12-bit image data to 8 bits for bandwidth reduction in
transmission between the ISIF and SDRAM. An 8- to-12-bit DPCM decoder at the IPIPEIF decompresses
data for IPIPE processing.
Two different predictors are used for the compression system. The first predictor is simple (simple
predictor), and the second predictor is slightly more complex (advanced predictor). Because the advanced
predictor gives a slightly better prediction for the pixel value, the image quality can be improved using it.
Because the simple predictor is very simple, the processing power and memory requirements are reduced
using it, when the image quality is already sufficiently high.
• Advanced predictor: This predictor uses only the previous same color component value as a prediction
value. Therefore, only 2-pixel memory is required.
• This predictor uses four previous pixel values when the prediction value is evaluated. This means that
the other color component values are also used when the prediction value has been defined.
The function is controlled from the ISIF_MISC[12] DPCMEN and ISIF_MISC[13] DPCMPRE bits.
3.3.6.16
ISP ISIF Storage Formatter
Figure 262 shows the storage formatter block diagram.
Figure 262. ISS ISP ISIF Storage Formatter Block Diagram
Storage formatter
U12
U12
Data
shift
Output
formatter
U32
Buffer logic (BL)
camss-638
Data are stored to the lower bits of a 16-bit SDRAM word, or can be 8- or 12-bit packed. The
ISIF_HSIZE[11:0] HSIZE bit field can specify the memory address offsets between lines of memory (offset
in 32-byte units). If set, the ISIF_HSIZE[12] ADCR bit can decrement the memory address line and the
line can be horizontally flipped in memory.
In case of RAW data, a data shift module is used: data to be stored can be right-shifted according to the
value set at the ISIF_MODESET[10:8] CCDW bit field, as described in Table 204.
442
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 204. ISS ISP ISIF RAW Data Shifting
ISIF_MODESET[10:8] CCDW
Output Format
MSB
LSB
000
0000 U12 data[11:0]
001
00000 U12 data[11:1]
010
000000 U12 data[11:2]
011
0000000 U12 data[11:3]
100
00000000 U12 data[11:4]
Table 205 shows the format where data are stored to the lower bits of a 16-bit word and the format where data are packed to 8 bits. The unused
bits are filled with zeros.
Table 205. ISS ISP ISIF SDRAM Data Format
Upper Word
Lower Word
MSB(31)
LSB(16)
Pixel 1
MSB(15)
0
LSB(0)
12 bit
0
11 bit
0
10 bit
0
9 bit
0
8 bit
0
Pixel 1
0
Pixel 0
8-bit packed
Pixel 3
Pixel 2
Pixel 1
Pixel 0
Pixel 1
Pixel 0
0
Pixel 1
Pixel 0
0
Pixel 1
Pixel 0
0
Pixel 0
Table 206 shows the format where data are packed to 12 bits.
Table 206. ISS ISP ISIF SDRAM Data Format for 12-bit Packed
Upper Word
Lower Word
MSB(31)
LSB(16)
Pixel2[7:0]
12 bit
Pixel5[3:0]
MSB(15)
Pixel1
Pixel4
Pixel7
LSB(0)
Pixel 0
Pixel3
Pixel6
Pixel2[11:8]
Pixel5[11:4]
443
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
In case of YUV, YUV data is stored in memory in packed YUV4:2:2 mode, using 2 pixels per 32 bits, as
shown in Table 207.
The output formatter can configure to any image format by using the SDRAM line offset register and offset
control registers. Figure 263 shows how to construct a frame format in SDRAM. The ISIF_CADU[10:0]
CADU bit field specifies the memory destination (upper 11 bits) to SDRAM (the address is the value of the
set bit multiplied by 32 bytes). On the other hand, the ISIF_CADL[15:0] CADL bit field sets the memory
destination to SDRAM (lower 16 bits) (the address is the value of the set bit multiplied by 32 bytes).
• ISIF_SPH
• ISIF_LNH
• ISIF_SLV0
• ISIF_SLV1
• ISIF_LNV
Figure 263. ISS ISP ISIF Frame Image Format Conversion
Start line
Even
Odd
Even
Odd
Input image
Output image
LINE1
LINE2
LINE3
LINE4
LINE2
LINE1
LINE4
LINE3
Even line
offset
•
•
•
•
Odd line
offset
•
•
•
•
camss-125
3.3.6.17
ISS ISP ISIF YCbCr signal Processing
The ISIF accepts 4:2:2 sampled YCbCr input data . The luminance and color difference signals are 8 bits
each, scaled 0 to 255. The color difference signals are multiplexed into one 8-bit bus beginning with a Cb
sample. The Y and CbCr buses can be input parallel (16-bit mode) or be time-multiplexed and input as a
single bus (8-bit mode).
The 16- or 8-bit YCbCr data is stored in SDRAM as 4:2:2 format. Table 207 lists the data format in
SDRAM. Y data typically has a range of 16 to 235; however, it is possible to subtract a DC value from the
Y signal.
Table 207. ISS ISP ISIF Memory Output Format for YUV Data
Memory Address
3.3.6.18
Upper Word
Lower Word
MSB(31)
LSB(16)
MSB(15)
LSB(0)
N
Y1
Cr0
Y0
Cb0
N+1
Y3
Cr1
Y2
Cb1
N+2
Y5
Cr2
Y4
Cb2
ISS ISP ISIF Expected Bandwidth on BL Ports
The ISIF module has a write port and a read port connected to the BL. This section summarizes the
expected bandwidth on these ports.
3.3.6.18.1 ISS ISP ISIF Write Port
The write port is used to write pixels to memory after the data have passed through the storage formatter.
Data storage to SDRAM is controlled by the ISIF_SYNCEN[1] DWEN bit. The module allows writing the
data as 16, 12, and 8 bits per pixel. The bit width is controlled by the ISIF_CCDCFG[1:0] SDRPACK bit
field.
444
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
The write port generates a burst of 32 bytes on the MTC interface. The delay between consecutive bursts
is proportional to the input pixel clock. Hence, the write port does not request peak bandwidth traffic.
Table 208 lists the estimated delay between 32-byte MTC requests for different pixel clock frequencies
and assumes the L3 clock is 200 MHz.
Table 208. ISP ISIF ISIF Module: Write Port Bandwidth
Pixel Clock
Maximum Bandwidth
2 bytes/s pixel
MB/s
Expected Delay Between MTC
Requests
200
400
16 cycles = 80 ns
100
200
32 cycles = 160 ns
10
20
320 cycles = 1600 ns
3.3.6.18.2 ISS ISP ISIF Read Port
The read port is used to read gain and offset data from SDRAM required for the LSC computation. When
LSC is enabled, 8-bit gain values are read and 8-bit offset values can optionally also be read. The LSC
gain computation can be enabled or disabled by setting the ISIF_2DLSCCFG[0] ENABLE bit. The LSC
offset computation can be enabled by setting the ISIF_2DLSCOFST[0] OFSTEN bit.
The LSC submodule fetches four 8-bit gain values per paxel and optionally four 8-bit offset values per
paxel. This is a maximum 8 bytes per paxel.
The bandwidth that is generated by the LSC module is also proportional to the paxel size. The paxel size
is set up by the ISIF_2DLSCCFG[14:12] GAIN_MODE_M and ISIF_2DLSCCFG[10:8] GAIN_MODE_N bit
fields. The possible values are 8, 16, 32, 64 and 128. Smaller values lead to higher memory bandwidth
requirements. Hence, the worst case is achieved by setting an 8 × 8 paxel size.
When the LSC submodule is enabled it automatically prefetches two lines of gain values and two lines of
offset values (if this is enabled). When the first VD comes, it again requests one line of gain values and
one line of offset values (if this is enabled). Then, it again fetches one line of gain values and one line of
offset values (if this is enabled) after ISIF_2DLSCCFG[10:8] GAIN_MODE_N lines. It continues to do so
until the last row of paxels. For the last row of paxels, it fetch two lines of gain values and two lines of
offset values (if this is enabled), which are used for the following frame.
By default, the LSC submodule creates peak bandwidth requirements. To avoid this, the MTC bandwidth
limiter must be used to space the request over time.
The MTC bandwidth limiter must be used to smooth the bandwidth requirements of the LSC module. The
MTC bandwidth limiter can be set with the ISP5_BL_MTC_1.ISIF_R register.
The principle is that instead of reading the gain and offset data as fast as possible, use the time that it
takes for ISIF_2DLSCCFG[10:8] GAIN_MODE_N lines to pass through the ISP to read the data.
Table 209 gives the estimated delay between 32-byte MTC requests for different pixel clock frequencies
and assumes the L3 clock at 200 MHz.
Table 209. ISS ISP ISIF Read Port Bandwidth
Pixel Clock
Max Bandwidth
MB/s
Expected Delay Between MTC Requests
200
25.07
255 cycles = 1275 ns
100
12.5
510 cycles = 2550 ns
10
1.25
5103 cycles = 2515 ns
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
445
ISS ISP
www.ti.com
When the bandwidth limiter is used, ensure that there is enough time for the data prefetching.
• The LSC submodule must be enabled at least 2 × ISIF_2DLSCCFG[10:8] GAIN_MODE_N lines before
the first VD.
• There must be at least ISIF_2DLSCCFG[10:8] GAIN_MODE_N lines of blanking. If there is not enough
blanking, multiply the bandwidth requirement by 2 (that is, ensure two lines of gain and offset data can
be fetched within the time of ISIF_2DLSCCFG[10:8] GAIN_MODE_N lines.
3.3.6.19
ISS ISP ISIF Events and Status Checking
The ISIF module can generate four different interrupts: VDINT0, VDINT1, VDINT2, and 2DLSCINT. The
ISIF_SYNCEN[0] SYEN bit must be enabled to receive any of the ISIF interrupts.
3.3.6.19.1 ISS ISP ISIF VDINT0, VDINT1, and VDINT2 Interrupts
As shown in Figure 264, the VDINT0, VDINT1, and VDINT2 interrupts occur relative to the VD pulse. The
trigger timing is selected by using the ISIF_MODESET[2] VDPOL bit setting. VDINT0, VDINT1, and
VDINT2 occur after receiving the number of horizontal lines (HD pulse signals) set in the
ISIF_VDINT0[14:0] CDV0, ISIF_VDINT1[14:0] CDV1, and ISIF_VDINT2[14:0] CDV2 register fields,
respectively.
NOTE: In the case of BT.656 input mode, there is a VD at the beginning of each field. Therefore,
there are two interrupts for each frame (that is, one for each field).
If the ISIF_MODESET[2] VDPOL bit is set to 0, the VDINT0, VDINT1, and VDINT2 HD counters begin
counting HD pulses from the rising edge of the external VD.
Figure 264. ISS ISP ISIF VDINT0/VDINT1/VDINT2 Interrupt Behavior When VDPOL = 0
External VD:
Relocatable
VDINT0, VDINT1:
camss-611
If the ISIF_MODESET[2] VDPOL bit is set to 1, the VDINT0, VDINT1, and VDINT2 HD counters begin
counting HD pulses from the falling edge of the external VD.
Figure 265. ISS ISP ISIF VDINT0/VDINT1/VDINT2 Interrupt Behavior When VDPOL = 1
External VD:
Relocatable
VDINT0, VDINT1:
camss-612
3.3.6.19.2 ISS ISP ISIF 2DLSCINT Interrupt
See Section 3.3.6.10.1.5 for more information.
3.3.6.19.3 ISS ISP ISIF Status Checking
The ISIF_MODESET[15] MDFS bit is set when the field status is on an even field, and it is cleared when
the field status is on an odd field.
The 2D-LSC has a register that monitors the status of the LSC. See Section 3.3.6.10.1.5 for more
information.
446
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.7
ISS ISP BL Functional Description
3.3.7.1
ISS ISP BL Overview
The BL module arbitrates and merges the memory requests of the ISP master module. The BL module
also generates interrupts upon frame completion for the following modules. The interrupt generation is
delayed until the transfer completes (ack is returned). The following interrupts are delayed by the BL
module:
• RSZ module RSZ-A EOF
• RSZ module resizer RSZ-B EOF
• H3A module EOF
• IPIPE module EOF
The BL uses two different types of interfaces:
• MTC protocol is used between the ISP modules and the BL.
• VBUSM is use on the BL master port interface.
Figure 266 show the BL module connections to other submodules of the ISP.
Figure 266. ISS ISP BL High-Level Diagram
Image
subsystem
(ISS)
Video port
ISP
CLK SYNC
IPIPEIF
IPIPE
H3A
RSZ
RSZ
ISIF
Buffer logic
ISP registers
Bridge
ISS interconnect
camss-003f
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
447
ISS ISP
3.3.7.2
www.ti.com
ISS ISP BL Functional Description
The BL merges the memory requests of the ISP master module to memory (read/write). The BL interfaces
with all the ISP modules through a 32-bit-wide bus following.
The ISP modules make memory requests of 32 bytes. Additional signals, SOF for read and EOF for write,
are included to deal with boundary conditions in frame transitions.
The BL arbitration is divided into two parts: a bus hog and a fixed priority arbitration. Bus hog refers to the
property of the buffer logic that gives higher priority to the module that last sent or received data.
RESIZER module MTC write port 0 and RESIZER module MTC write port 1 are excluded from the bus
hog.
The buffer logic is to be programmed to maximize the memory bandwidth: it makes maximum burst
requests of 128 bytes (8 × 128 bits) for reads and writes. The BL can generate burst sizes of 2 × 128, 4 ×
128, 6 × 128, and 8 × 128 bits.
NOTE: The ISP interface supports burst sizes of only 1, 2, 4, and 8 × 128 bits. If the BL generates a
6 × 128-bit request, it is broken into a 4 × 128-bit request, followed by another 2 × 128-bit
request.
To use the memory bandwidth efficiently, the BL interfaces with the memory through a high-bandwidth bus
(128 bits wide).
The BL handles memory requests for the following modules:
• IPIPEIF module read port
• ISIF-LSC module read port
• ISIF module write port
• IPIPE-BOXCAR module write port
• H3A module write port
• RESIZER module write port 0
• RESIZER module write port 1
From a use case point of view, the following sharing and priority arrangement is used. All reads have
higher priority than writes; for reads: IPIPEIF ISIF-LSC, and for writes: ISIF IPIPE-BOXCAR RESIZER 0
RESIZER 1 H3A.
NOTE: BL can generate a static or a dynamic MFlag signal. The MFlag signal is used by the ISS
arbitration to consider the urgency of the requests coming from the ISP. The dynamic MFlag
feature is enabled from the ISP5_CTRL[21] MFLAG bit.
Figure 267 shows the BL top-level block diagram. The figure highlights the two clock domains that are
used.
448
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
IPIPEIF
32b
RBL
CMD FIFO
Arbitration
CMD ARB
DATA FIFO
RD mux
MEM
128b
WR mux
ISS Interconnect
Figure 267. ISS ISP BL Block Diagram
RBL
CMD FIFO
LSC
32b
DATA FIFO
MEM
ISIF
Mflag
WBL
CMD FIFO
Dynamic Mflag signla
generation. Level depens
upon BL internal FIFO
levels
32b
DATA FIFO
MEM
H3A
WBL
CMD FIFO
32b
DATA FIFO
MEM
IPIPE_INT_DMA
IPIPE
WBL
CMD FIFO
RSZ_INT_DMA
Delayed by data
transfer completion
32b
DATA FIFO
MEM
WBL
CMD FIFO
32b
DATA FIFO
MEM
Resizer
MTC
32b
WBL
CMD FIFO
DATA FIFO
MEM
BL
camss-080u
NOTE: The BL module has no registers. The configurations come from the top level of the ISP. See
Table 260 for register details.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
449
ISS ISP
www.ti.com
3.3.7.3
ISS ISP BL Address Alignment
The BL module ensures maximum memory efficiency by realigning data to a 128-byte address boundary.
In all cases, the BL accesses are 32-byte-aligned: address [4:0] is always 0.
This is required when the input address is a multiple of 32 bytes, not 128 bytes. The BL issues a nonaligned burst until it reaches a 128-byte boundary, and then keeps making a 128-byte request until the
end of the line. Eventually, although the last burst in a line may not be a multiple of 128 bytes, it will
always be a multiple of 32 bytes, as shown in Figure 268.
Figure 268. ISS ISP BL Address Alignment
Last request
may not be
a multiple of
128 bytes.
32 bytes aligned
Next 128 byte aligned address
Last 128 byte aligned address
camss-687
3.3.7.4
ISS ISP BL Out-of-Order Responses
BL supports out-of-order responses. The out-of-order response is handled by having up to 16 outstanding
CIDs (reads + writes). The maximum number of outstanding CIDs is set up by the ISP5_CTRL[7:4]
VBUSM_CIDS bit field. There is one outstanding request per CID.
If any of the CIDs are not outstanding, a command is accepted from the highest prioritized buffer with a
request. The CID availability is cleared when status complete is received. The outstanding commands can
be all reads or all writes or any combination. The CID that is allocated is the lowest number of the 16 that
are available when the command is accepted. As soon as a CID is released it is used if a command is
available.
The VBUSM2OCP module transforms the VBUMS CIDs into OCP MFlag signals. Note that there can be
only one outstanding per tag. It is not authorized to make a new request on a tag which is already waiting
for a response.
3.3.7.5
ISS ISP BL Stalling
The BL can stall the requests from the initiator modules for reads and writes
3.3.7.5.1
ISS ISP BL Stalling Write Requests
One reason for the BL to stall write requests is that there is usually back pressure on the system memory
and requests cannot be issued as fast as required. In that case the BL must stall requests from the
initiator modules. The BL module cannot know whether stalling the request will lead to an initiator overflow
or not. The RESIZER module can support back pressure from the BL module when it is configured in
bypass mode. The input buffer memory can be used to store data from the IPIPE and IPIPEIF modules . If
the RESIZER input buffer overflows, an interrupt is issued.
3.3.7.5.2
ISS ISP BL Stalling Read Requests
The BL may also stall read requests from the ISIF-LSC and IPIPEIF modules. When data comes from an
image sensor there is no way to stop the sensor. If the read request is stalled too long, the LSC module
may eventually underflow. When the IPIPEIF module reads all its data from memory, the IPIPEIF stalls
transfers to successive modules by masking the clock.
450
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.3.7.6
ISS ISP BL Dynamic and Static MFlag Generation
NOTE: The following applies when ISP5_CTRL[21] MFLAG = 1. The MFlag value is static.
The BL outputs cpriority[2:0] and cepriority[2:0] signals on its VBUS master port interface. On the VBUSM
side, these signals are aligned with the request (creq). Both values are actually repeating register input
signals. The lower value (0) corresponds to the higher priority.
The MFlag signal does not need to be aligned with the request. The signal can change value anytime.
In the ISP VBUSM2 interface bridge, the cepriority signal is ignored and only the cpriority signal is used.
Because the priority value is set up by a register setting, the value is not going to be dynamically modified
obviously. Table 210 shows how the cpriority values are mapped to the interface MFlag signal, which is
present on the ISP master interface and set in the ISP5_CTRL[3:1] VBUSM_CPRIORITY bit field.
Table 210. ISS ISP BL cpriority to MFlag With ISP5_CTRL[21] MFLAG = 1
MFlag[1:0]
Description
00
Normal priority cpriority[2:0] = 4, 5, 6, 7
01
Medium priority cpriority[2:0] = 2, 3
10
Reserved
11
High priority cpriority[2:0] = 0, 1
NOTE: The following applies when the ISP5_CTRL[21] MFLAG = 0. The MFlag value is dynamic.
This feature is enabled at reset. The general idea for dynamic MFlag generation is to monitor the FIFO
levels. Thresholds are used to increase or decrease the MFlag values. There are different
implementations for read and write requestors.
An individual MFlag value is generated for each FIFO and then ORed altogether and exported at the BL
boundary. The MFlag signal generation does not affect the BL arbitration scheme.
• Writes: To prevent overflows in the BL, dynamic MFlag signal generation gives higher priority to FIFOs
that are almost full:
– Low FIFO level = 50 percent
– High FIFO level = 75 percent
– FIFOs with more than 75 percent fill level have high priority: MFlag = 11
– FIFOs between 50 and 75 percent fill level have medium priority: MFlag = 01
– FIFOs below 50 percent fill level have normal priority: MFlag = 00
Table 211 gives the low- and high-level priority thresholds for write initiators.
Table 211. ISS ISP BL MFlag Write Low- and High-Level Priority Thresholds
ISIF
H3A
IPIPE
RSZ
Access type
Write
Write
Write
Write
Buffer size
64 × 128
64 × 128
48 × 128
64 × 136
50% low level
32 × 128
32 × 128
24 × 128
32 × 136
75% high level
48 × 128
48 × 128
36 × 128
48 × 128
•
Reads: The dynamic MFlag signal generation depends on the reserved data units in the initiator data
FIFO. The reserved data units correspond to read commands waiting to be sent on the interface bus,
plus the read commands that have been sent on the interface bus and for which data responses have
not yet arrived.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
451
ISS ISP
www.ti.com
•
The total FIFO size in bytes can be expressed as reserved data units (bytes) + data bytes stored
(bytes) + empty space (bytes). By definition, empty space is lower than a burst size (128 bytes).
– Low FIFO level = 25 percent
– High FIFO level = 50 percent
– Data bytes stored + empty space (bytes) = 50 percent of FIFO size: MFlag = 00
– Data bytes stored + empty space (bytes) 50 percent of FIFO size: MFlag = 01
– Data bytes stored + empty space (bytes) 25 percent of FIFO size: MFlag = 11
Table 212 gives the low- and high-level priority thresholds for read initiators.
Table 212. ISS ISP BL MFlag Read Low- and High-Level Priority Thresholds
3.3.7.7
IPIPEIF
ISIF-LSC
Access type
Read
Read
Buffer size
64 × 128
32 × 128
25% buffer size
16 × 128
8 × 128
50% buffer size
32 × 128
16 × 128
ISS ISP BL VBUSM2OCP Last Beat Command Delay
The VBUSM2OCP module bridge implements the following function to work around a limitation of the BL
module, which does not send back-to-back requests to the ISS, thereby leading to possible situations
where the ISP loses arbitration at the ISS level.
To fully benefit from dynamic MFlag generation (see Section 3.3.7.6), the following function is present in
the VBUSM2OCP module bridge:
• The delay occurs only if BL MFflag = ISP5_BL_VBUSM[5] MFLAG_THRES.
• The MFlag value used is whatever is available when the last beat comes on the interface bus.
• The last beat of the interface request (read or write) is held until one cycle before a new command
(read or write). This is achieved by masking the last beat of the interface command at the ISP
interface.
The last beat is unmasked on the first event of one cycle before a new interface command, or the
delay counter that uses the ISP5_BL_VBUSM[4:0] LASTCMD_DLY value counter expires (has
decremented to zero). The ISP5_BL_VBUSM[4:0] LASTCMD_DLY bit field must be set before the
request on the BL starts. If the value of the ISP5_BL_VBUSM[4:0] LASTCMD_DLY bit field is changed
during the pending requests, the delay counter is not updated.
3.3.7.8
ISS ISP BL Peak Memory Bandwidth Reduction
To limit the peak memory bandwidth generated by the IPIPEIF (read port), ISIF (read port), and H3A (write
port) modules, a bandwidth limiter is placed between the modules and the BL. The resizer module has this
function built in and therefore does not need a bandwidth limiter.
The bandwidth limiter enables control of the minimum interval between two consecutive memory requests.
This function is controlled by the ISP5_BL_MTC_1 and ISP5_BL_MTC_2 registers. When the registers
are set to 0, the function is not modified (that is, the bandwidth limiter is disabled). For the resizer module,
it is controlled by the following registers: RSZ_DMA_RZA and RSZ_DMA_RZB.
3.3.8
ISS ISP Memory Mapping
A total of 64KB is reserved for the ISP registers and memories. Table 213 and Table 214 describe the
memory map.
452
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 213. ISS ISP Memory Mapping for Cortex-M3 Private Access
Memory Mapping
Start
End
Size
Comments
ISS ISP5 SYS1
0x5505 0000
0x5505 009F
160
ISP5 configuration
registers (set 1)
ISS ISP5 SYS2
0x5505 00A0
0x5505 03FF
864
ISP5 configuration
registers (set 2)
ISS RESIZER registers
0x5505 0400
0x5505 07FF
1024
RESIZER configuration
registers
ISS IPIPE registers
0x5505 0800
0x5505 0FFF
2048
IPIPE configuration
registers
ISS ISIF registers
0x5505 1000
0x5505 11FF
512
ISIF configuration
registers
ISS IPIPEIF registers
0x5505 1200
0x5505 13FF
512
IPIPEIF configuration
registers
ISS H3A registers
0x5505 1400
0x5505 15FF
512
H3A configuration
registers
Reserved
0x5505 1600
0x5505 17FF
512
Reserved
Reserved
0x5505 1800
0x5505 1BFF
1024
Reserved
Reserved
0x5505 1C00
0x5505 1DFF
512
Reserved
Reserved
0x5505 1E00
0x5505 1FFF
512
Reserved
HST memory 0
0x5505 2000
0x5505 27FF
2048
IPIPE histogram
HST memory 1
0x5505 2800
0x5505 2FFF
2048
IPIPE histogram
HST memory 2
0x5505 3000
0x5505 37FF
2048
IPIPE histogram
HST memory 3
0x5505 3800
0x5505 3FFF
2048
IPIPE histogram
BSC memory 1
0x5505 6000
0x5505 6EFF
8192
IPIPE Boundary Signal
Calc column sum
DPC table 0
0x5505 8000
0x5505 81FF
1024
IPIPE Defect(Fault) Pixel
Correction address table
DPC table 1
0x5505 8400
0x5505 85FF
1024
IPIPE Defect(Fault) Pixel
Correction address table
YEE table
0x5505 8800
0x5505 8FFF
2048
IPIPE Y-data Edge
Enhance table
GBC table
0x5505 9000
0x5505 97FF
2048
IPIPE GBCE LUT
3DLUT table0
0x5505 9800
0x5505 9AFF
1024
IPIPE 3D LUT
3DLUT table1
0x5505 9C00
0x5505 9EFF
1024
IPIPE 3D LUT
3DLUT table2
0x5505 A000
0x5505 A2FF
1024
IPIPE 3D LUT
3DLUT table3
0x5505 A400
0x5505 A6FF
1024
IPIPE 3D LUT
GAMR table
0x5505 A800
0x5505 AFFF
2048
IPIPE Gamma correction
table (R)
GAMG table
0x5505 B000
0x5505 B7FF
2048
IPIPE Gamma correction
table (G)
GAMB table
0x5505 B800
0x5505 BFFF
2048
IPIPE Gamma correction
table (B)
LIN table0
0x5505 C000
0x5505 C17F
1024
ISIF Linearization table
LIN table1
0x5505 C400
0x5505 C57F
1024
ISIF Linearization table
DCCLAMP
0x5505 C800
0x5505 C9FF
2048
ISIF Digital Clamp
LSC table0
0x5505 D000
0x5505 E7FF
6144
ISIF Lens Shading gain
table
LSC table1
0x5505 E800
0x5505 FFFF
6144
ISIF Lens Shading gain
table
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
453
ISS ISP
www.ti.com
Table 214. ISS ISP Memory Mapping for L3 Interconnect Access
Memory Mapping
Start
End
Size
Comments
ISS ISP5 SYS1
0x5C01 0000
0x5C01 009F
160
ISP5 configuration
registers (set 1)
ISS ISP5 SYS2
0x5C01 00A0
0x5C01 03FF
864
ISP5 configuration
registers (set 2)
ISS RESIZER registers
0x5C01 0400
0x5C01 07FF
1024
RESIZER configuration
registers
ISS IPIPE registers
0x5C01 0800
0x5C01 0FFF
2048
IPIPE configuration
registers
ISS ISIF registers
0x5C01 1000
0x5C01 11FF
512
ISIF configuration
registers
ISS IPIPEIF registers
0x5C01 1200
0x5C01 13FF
512
IPIPEIF configuration
registers
ISS H3A registers
0x5C01 1400
0x5C01 15FF
512
H3A configuration
registers
Reserved
0x5C01 1600
0x5C01 17FF
512
Reserved
Reserved
0x5C01 1800
0x5C01 1BFF
1024
Reserved
Reserved
0x5C01 1C00
0x5C01 1DFF
512
Reserved
Reserved
0x5C01 1E00
0x5C01 1FFF
512
Reserved
HST memory 0
0x5C01 2000
0x5C01 27FF
2048
IPIPE histogram
HST memory 1
0x5C01 2800
0x5C01 2FFF
2048
IPIPE histogram
HST memory 2
0x5C01 3000
0x5C01 37FF
2048
IPIPE histogram
HST memory 3
0x5C01 3800
0x5C01 3FFF
2048
IPIPE histogram
BSC memory 1
0x5C01 6000
0x5C01 6EFF
8192
IPIPE Boundary Signal
Calc column sum
DPC table 0
0x5C01 8000
0x5C01 81FF
1024
IPIPE Defect(Fault) Pixel
Correction address table
DPC table 1
0x5C01 8400
0x5C01 85FF
1024
IPIPE Defect(Fault) Pixel
Correction address table
YEE table
0x5C01 8800
0x5C01 8FFF
2048
IPIPE Y-data Edge
Enhance table
454
GBC table
0x5C01 9000
0x5C01 97FF
2048
IPIPE GBCE LUT
3DLUT table0
0x5C01 9800
0x5C01 9AFF
1024
IPIPE 3D LUT
3DLUT table1
0x5C01 9C00
0x5C01 9EFF
1024
IPIPE 3D LUT
3DLUT table2
0x5C01 A000
0x5C01 A2FF
1024
IPIPE 3D LUT
3DLUT table3
0x5C01 A400
0x5C01 A6FF
1024
IPIPE 3D LUT
GAMR table
0x5C01 A800
0x5C01 AFFF
2048
IPIPE Gamma correction
table (R)
GAMG table
0x5C01 B000
0x5C01 B7FF
2048
IPIPE Gamma correction
table (G)
GAMB table
0x5C01 B800
0x5C01 BFFF
2048
IPIPE Gamma correction
table (B)
LIN table0
0x5C01 C000
0x5C01 C17F
1024
ISIF Linearization table
LIN table1
0x5C01 C400
0x5C01 C57F
1024
ISIF Linearization table
DCCLAMP
0x5C01 C800
0x5C01 C9FF
2048
ISIF Digital Clamp
LSC table0
0x5C01 D000
0x5C01 E7FF
6144
ISIF Lens Shading gain
table
LSC table1
0x5C01 E800
0x5C01 FFFF
6144
ISIF Lens Shading gain
table
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
3.4
ISS ISP Programming Model
NOTE: The preferred way to perform memory-to-memory processing with ISP is to use the Stall
Controller (SC) module at the ISS level (see , ISS Interfaces.). It is possible to use the
IPIPEIF read port for memory-to-memory processing, but it is not the preferred way because
it does not provide enough granularity on the fractional clock divider for up to 20x digital
zoom.
3.4.1
ISS ISP ISIF Programming Model
This section discusses issues related to the software control of the ISIF. It lists the registers that are
required to be programmed in different modes, describes how to enable and disable the ISIF and how to
check the status of the ISIF, discusses the different register access types, and enumerates several
programming constraints.
3.4.1.1
ISS ISP ISIF Hardware Setup/Initialization
This section discusses the configuration of the ISIF required before image processing can begin.
3.4.1.1.1
ISS ISP ISIF Reset Behavior
Upon hardware reset of the ISP, all of the registers in the ISIF, except the defect table registers, are reset
to their reset values. Because the defect table registers are stored in internal RAM, they do not have reset
values. If the reset is a chip-level POR (reset after power is applied), the values of the defect table register
are unknown. If the reset is an ISP module reset (when power remains active), the contents of this
memory remain the same as before the reset.
3.4.1.1.2
ISS ISP ISIF Register Setup
Before enabling the ISIF, the hardware must be properly configured through register writes. Figure 269
and Figure 270 show the sequence to be used for RAW and YUV data before enabling the ISIF. The
register settings for each process in the following sequence are described in Table 215.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
455
ISS ISP
www.ti.com
Figure 269. ISS ISP ISIF Initialization Flow Chart – Part One
From IPIPEIF
General settings
HD&VD settings
Interlaced fields
settings
RAW data
YUV data
ISIF_MODESET
[13:12]
INPMOD?
Input mode REC656
settings
RAW data input mode
settings
Input mode YUV8
settings
Linearization settings
Disable all RAW
functionalities
Color space converter
settings
Input data formatter
settings
Black clamp settings
VDFC settings
2D LSC settings
White Balance general
settings
White balance for H3A
settings
White balance for BL
settings
White balance for IPIPE
settings
to IPIPEIF
LPF settings
to IPIPEIF
A-Law settings
RAW data
ISIF_MODESET
[13:12]
INPMOD?
YUV data
A
camss-600
456
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Figure 270. ISS ISP ISIF Initialization Flow Chart – Part Two
A
Culling settings
External WEN settings
RAW data
ISIF_MODESET
[13:12]
INPMOD?
YUV data
Disable DPCM
and data shift
DPCM settings
Data shift settings
External trigger settings
Output formatter settings
for YUV and RAW data
RAW data
ISIF_MODESET
[13:12]
INPMOD?
YUV data
Output formatter settings
for RAW data
to BL
camss-601
Table 215. ISS ISP ISIF Required Configuration Parameters
Step
Configuration Required
Value
General settings
Set the Field Indicator signal direction.
ISIF_MODESET[1] FIDD
Set the VD signal polarity.
ISIF_MODESET[2] VDPOL
Set the HD signal polarity.
ISIF_MODESET[3] HDPOL
Set the Field Indicator signal polarity.
ISIF_MODESET[4] FIPOL
HD and VD settings
Set the HD and VD signal directions.
ISIF_MODESET[0] HDVDD
If: HD and VD are set as output (HDVDD = 0x1):
Set the HD width.
ISIF_HDW[11:0] HDW
Set the VD width.
ISIF_VDW[11:0] VDW
Set the HD period.
ISIF_PPLN[15:0] PPLN
Set the VD period.
ISIF_LPFR[15:0] LPFR
End
Interlaced fields settings
Select the type of image sensor
(progressive or interlaced)
ISIF_MODESET[7] CCDMD
Input mode settings
Set the data input mode.
ISIF_MODESET[13:12] INPMOD
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
457
ISS ISP
www.ti.com
Table 215. ISS ISP ISIF Required Configuration Parameters (continued)
Step
Configuration Required
Value
Input mode settings for REC656 data
Select CCIR Rec.656 interface or not.
ISIF_REC656IF[1] R656ON
If: input is REC656 (R656ON = 0x1)
Set error correction of FVH code.
ISIF_REC656IF[0] ECCFVH
Selects bit width of CCIR656.
ISIF_CCDCFG[5] BT656
End
Input mode settings for YCC 8 bit data (if INPMOD = 0x2)
Selects Y position signal
ISIF_CCDCFG[11] Y8POS
RAW data processing: input settings
Enable or disable MSB inverse of CIN port ISIF_CCDCFG[13] MSBINVI
(YUV format).
Select Y and C swapping.
ISIF_CCDCFG[4] YCINSWP
Selects MSB position of input data (16
bits-to-16 bits)
ISIF_CGAMMAWD[4:1] GWDI
Set the image sensor data polarity.
ISIF_MODESET[6] DPOL
Select the CFA pattern mode.
ISIF_CGAMMAWD[5] CFAP
Specifies the color pattern
ISIF_CCOLP[7:6] CP0_F0
ISIF_CCOLP[5:4] CP1_F0
ISIF_CCOLP[3:2] CP2_F0
ISIF_CCOLP[1:0] CP3_F0
Linearization settings
Enable linearization or not.
ISIF_LINCFG0[0] LINEN
If: Linearization enabled (LINEN = 0x1)
Select linearization mode.
ISIF_LINCFG0[1] LINMD
Select the shift value.
ISIF_LINCFG0[6:4] CORRSFT
Set the scale factor for LUT.
ISIF_LINCFG1[10:0] LUTSCL
Set up linearization LUT.
End
Input data formatter settings
Enable data formatter or not.
ISIF_FMTCFG[0] FMTEN
If: Data formatter is enabled (FMTEN =
0x1)
Select the combine input lines.
ISIF_FMTCFG[1] FMTCBL
Select the mode normal or alternative.
ISIF_FMTCFG[2] LNALT
Select the split/combine number of lines.
ISIF_FMTCFG[5:4] LNUM
Set the address increment.
ISIF_FMTCFG[11:8] FMTAINC
Set the number of program entries per
SET.
ISIF_FMTPLEN[3:0] FMTPLEN0
ISIF_FMTPLEN[7:4] FMTPLEN1
ISIF_FMTPLEN[10:8] FMTPLEN2
ISIF_FMTPLEN[14:12] FMTPLEN3
Set the first pixel in a line.
ISIF_FMTSPH[12:0] FMTSPH
Set the number of pixels in a line.
ISIF_FMTLNH[12:0] FMTLNH
Set the start line vertical.
ISIF_FMTLSV[12:0] FMTSLV
Set the number of lines in a vertical.
ISIF_FMTLNV[14:0] FMTLNV
Set the number of pixels in an output line.
ISIF_FMTRLEN[12:0] FMTRLEN
Set the HD interval for output lines.
ISIF_FMTHCNT[12:0] FMTHCNT
Set up to 16 address pointers.
ISIF_FMTAPTRx[14:13] LINE (x = 0 to 15)
ISIF_FMTAPTRx[12:0] INIT (x = 0 to 15)
458
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 215. ISS ISP ISIF Required Configuration Parameters (continued)
Step
Configuration Required
Set the 32 possible program entry valid
flag.
ISIF_FMTPGMVF0
Set the 32 possible address pointers.
ISIF_FMTPGMAPS0
Value
ISIF_FMTPGMVF1
ISIF_FMTPGMAPS1
ISIF_FMTPGMAPS2
ISIF_FMTPGMAPS3
ISIF_FMTPGMAPS4
ISIF_FMTPGMAPS5
ISIF_FMTPGMAPS6
ISIF_FMTPGMAPS7
Set the 32 possible address update
(increment or decrement).
ISIF_FMTPGMAPU0
ISIF_FMTPGMAPU1
End
Color space converter settings
Enable or disable color space converter.
ISIF_CSCCTL[0] CSCEN
If: Color space converter is enabled (CSCEN = 0x1)
Set the color space converter coefficients.
ISIF_CSCM0
ISIF_CSCM1
ISIF_CSCM2
ISIF_CSCM3
ISIF_CSCM4
ISIF_CSCM5
ISIF_CSCM6
ISIF_CSCM7
End
Black Clamp settings
Enable or disable black clamp.
ISIF_CLAMPCFG[0] CLEN
If: Black clamp is enabled (CLEN = 0x1)
Set the DC offset for black clamp.
ISIF_CLDCOFST[12:0] CLDC
[Horizontal Black Clamp]
Set the horizontal clamp mode.
ISIF_CLAMPCFG[2:1] CLHMD
Set the vertical dimension of a window.
ISIF_CLHWIN0[13:12] CLHWN
Set the horizontal dimension of a window.
ISIF_CLHWIN0[9:8] CLHWM
Enable or disable limitation for horizontal.
ISIF_CLHWIN0[6] CLHLMT
Select base window.
ISIF_CLHWIN0[5] CLHWBS
Set the window count per color.
ISIF_CLHWIN0[4:0] CLHWC
Set window start position (H).
ISIF_CLHWIN1[12:0] CLHSH
Set the window start position (V).
ISIF_CLHWIN2[12:0] CLHSV
[Vertical Black Clamp]
Set the black clamp start position.
ISIF_CLSV[12:0] CLSV
Set the vertical black clamp reset value.
ISIF_CLVRV[11:0] CLVRV
Set the line average coefficient.
ISIF_CLVWIN0[15:8] CLVCOEF
Select the reset value for the clamp value
of the previous line.
ISIF_CLVWIN0[5:4] CLVRVSL
Select the optical black H valid.
ISIF_CLVWIN0[2:0] CLVOBH
Set the window start position (H).
ISIF_CLVWIN1[12:0] CLVSH
Set the window start position (V).
ISIF_CLVWIN2[12:0] CLVSV
Select the optical black V valid.
ISIF_CLVWIN3[12:0] CLVOBV
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
459
ISS ISP
www.ti.com
Table 215. ISS ISP ISIF Required Configuration Parameters (continued)
Step
Configuration Required
Value
End
Set the DC offset for black clamp (RAW
data only).
ISIF_CLDCOFST[12:0] CLDC
DC offset available for YUV
Vertical line defect correction (VDFC) settings
Disable vertical line defect correction.
ISIF_DFCCTL[4] VDFCEN
0x0
If: Vertical line defect correction will be enabled (VDFCEN = 0x1)
Select the mode.
ISIF_DFCCTL[6:5] VDFCSL
Select upper pixels correction enable or
disable.
ISIF_DFCCTL[7] VDFCUDA
Set the shift value.
ISIF_DFCCTL[10:8] VDFLSFT
Set the saturation level.
ISIF_VDFSATLV[11:0] VDFSLV
Clear memories.
ISIF_DFCMEMCTL[4] DFCMCLR
Vertical line defect table update
procedure.
See Section 3.3.6.9.1 for details.
0x1
Use the following registers:
ISIF_DFCMEMCTL[2] DFCMARST
ISIF_DFCMEMCTL[0] DFCMWR
ISIF_DFCMEM0
ISIF_DFCMEM1
ISIF_DFCMEM2
ISIF_DFCMEM3
ISIF_DFCMEM4
End
Enable vertical line defect correction.
ISIF_DFCCTL[4] VDFCEN
0x1
2D Lens Shading Compensation (LSC) settings
Disable lens shading compensation.
ISIF_2DLSCCFG[0] ENABLE
0x0
If: 2D-LSC will be enabled (ENABLE = 0x1)
Set the H direction data offset.
ISIF_LSCHOFST[13:0] HOFST
Set the V direction data offset.
ISIF_LSCVOFST[13:0] VOFST
Set the number of valid pixels in H
direction.
ISIF_LSCHVAL[13:0] HVAL
Set the number of valid lines in V
direction.
ISIF_LSCVVAL[13:0] VVAL
Define the horizontal dimension of a
paxel.
ISIF_2DLSCCFG[14:12] GAIN_MODE_M
Define the vertical dimension of a paxel.
ISIF_2DLSCCFG[10:8] GAIN_MODE_N
Set gain format table.
ISIF_2DLSCCFG[3:1] GAIN_FORMAT
Enable or disable offset control.
ISIF_2DLSCOFST[0] OFSTEN
Select shift up value for offsets.
ISIF_2DLSCOFST[6:4] OFSTSFT
Set scaling factor for offset.
ISIF_2DLSCOFST[15:8] OFSTSF
Set the initial Y position.
ISIF_2DLSCINI[14:8] Y
Set the initial X position.
ISIF_2DLSCINI[6:0] X
Set the gain table base address.
ISIF_2DLSCGRBU[15:0] BASE31_16
ISIF_2DLSCGRBL[15:0] BASE15_0
Set the gain table offset (length of one
row).
ISIF_2DLSCGROF[15:0] OFFSET
Set the offset table base address.
ISIF_2DLSCORBU[15:0] BASE
ISIF_2DLSCORBL[15:0] BASE
Set the offset table offset (length of one
row).
460
ISIF_2DLSCOROF
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 215. ISS ISP ISIF Required Configuration Parameters (continued)
Step
Configuration Required
Enable useful interrupts
ISIF_2DLSCIRQEN[3] SOF
Value
ISIF_2DLSCIRQEN[2]
PREFETCH_COMPLETED
ISIF_2DLSCIRQEN[1]
PREFETCH_ERROR
ISIF_2DLSCIRQEN[0] DONE
Set up LSC gain table and offset table in SDRAM. See Figure 256 for details.
Wait seven clock periods before enabling LSC.
Enable lens shading compensation.
ISIF_2DLSCCFG[0] ENABLE
0x1
End
White balance color settings
Set R/Ye gain.
ISIF_CRGAIN[11:0] CGR
Set Gr/Cy gain.
ISIF_CGRGAIN[11:0] CGGR
Set Gr/Cy gain.
ISIF_CGBGAIN[11:0] CGGB
Set B/Mg gain.
ISIF_CBGAIN[11:0] CGB
Set offset.
ISIF_COFSTA[11:0] COFT
[For BL output]
Enable or disable white balance for BL
path.
ISIF_CGAMMAWD[12] WBNEN0
Enable or disable offset control for BL
path.
ISIF_CGAMMAWD[8] OFSTEN0
[For IPIPE (through IPIPEIF) output]
Enable or disable white balance for IPIPE
path.
ISIF_CGAMMAWD[13] WBEN1
Enable or disable offset control for IPIPE
path.
ISIF_CGAMMAWD[9] OFSTEN1
[For H3A (through IPIPEIF) output]
Enable or disable white balance for H3A
path.
ISIF_CGAMMAWD[14] WBEN2
Enable or disable offset control for H3A
path.
ISIF_CGAMMAWD[10] OFSTEN2
LPF settings (for BL output only) (RAW data only)
Enable or disable low pass filter.
ISIF_MODESET[14] HLPF
A-Law compression settings (for BL output only) (RAW data only)
Enable or disable A-Law compression.
ISIF_CGAMMAWD[0] CCDTBL
Culling settings (for BL output only) (RAW or YUV data)
Set the culling pattern in odd lines.
ISIF_CULH[15:8] CLHO
Set the culling pattern in even lines.
ISIF_CULH[7:0] CLHE
Set the culling pattern in vertical lines.
ISIF_CULV[7:0] CULV
External WEN settings (for BL output only)
Select external WEN use or not.
ISIF_MODESET[5] SWEN
If: External WEN is used (SWEN = 0x1):
Specifies the CCD valid area
ISIF_CCDCFG[8] WENLOG
End
DPCM settings (for BL output only) RAW data only
Select the predictor for DPCM encoder.
ISIF_MISC[13] DPCMPRE
Enable or disable DPCM encoding.
ISIF_MISC[12] DPCMEN
Data shift settings (for BL output only) (RAW data only)
Select the data shift value when image is
written to memory
ISIF_MODESET[10:8] CCDW
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
461
ISS ISP
www.ti.com
Table 215. ISS ISP ISIF Required Configuration Parameters (continued)
Step
Configuration Required
Value
External trigger settings (for BL output
only)
If: External trigger is selected (EXTRG = 0x1):
Select the trigger source signal.
ISIF_CCDCFG[9] TRGSEL
End
Output formatter (for BL output only) RAW
and YUV
Set the memory address decrement.
ISIF_HSIZE[12] ADCR
Set the memory address offset between
lines.
ISIF_HSIZE[11:0] HSIZE
Set the first pixel in a line to be stored in
memory.
ISIF_SPH[14:0] SPH
Set the number of pixels in a line to be
stored in memory.
ISIF_LNH[14:0] LNH
Set the start line vertical for field 0.
ISIF_SLV0[14:0] SLV0
Set the start line vertical for field 1.
ISIF_SLV1[14:0] SLV1
Set the number of lines to be stored in
memory.
ISIF_LNV[14:0] LNV
Enable or disable the storage of image in
memory.
ISIF_SYNCEN[1] DWEN
Set the memory destination address.
ISIF_CADU[10:0] CADU
ISIF_CADL[10:0] CADL
3.4.1.2
Enable or disable MSB inverse of COUT
port.
ISIF_CCDCFG[14] MSBINVO
Enable or disable byte swap when
SDRAM capturing.
ISIF_CCDCFG[12] BSWD
Select Y and C swapping.
ISIF_CCDCFG[2] YCOUNTSWP
Select SDRAM pack mode.
ISIF_CCDCFG[1:0] SDRPACK
Enable or disable VD/HD output.
ISIF_SYNCEN[0] SYEN
ISS ISP ISIF Enable/Disable Hardware
The ISIF is enabled by setting the ISIF_SYNCEN[0] SYEN bit. This is done after all the required registers
discussed in the previous section are programmed.
With respect to the write enable bit and output address, the following procedure must be followed:
1. Set the data output address (ISIF_CADU and ISIF_CADL).
2. Enable HD/VD and WEN at the same time (ISIF_MODESET[1] DWEN and ISIF_SYNCEN[0] SYEN).
If the ISIF_SYNCEN[0] SYEN bit is written before the output address and the SDRAM write enable bit (not
recommended but may be required for a particular mode), data begins to be written to the old address
value and not the one recently programmed. The desired response can be achieved if the following
procedure is followed:
1. Enable HD/VD (ISIF_SYNCEN[0] SYEN).
2. Set the output address (ISIF_CADU and ISIF_CADL).
3. Wait for the next VD.
4. Enable WEN (ISIF_MODESET[1] DWEN).
The ISIF always operates in continuous mode. In other words, after enabling the ISIF, it continues to
process sequential frames until the ISIF_SYNCEN[0] SYEN bit is cleared by software. When this happens,
the frame being processed is disabled immediately and does not continue to process the current frame.
462
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
When the HD/VD signals are set to outputs ( ISIF_MODESET[0] HDVDD = 0x1), fetching and processing
of the frame begin immediately upon setting the ISIF_SYNCEN[0] SYEN bit.
When the HD/VD signals are set to inputs ( ISIF_MODESET[0] HDVDD = 0x0), processing of the frame is
dependent on the input timing of the external sensor/decoder. To ensure that data from the external
device is not missed, the ISIF must be enabled before data transmission from the external device. In this
way, the ISIF waits for data from the external device.
3.4.1.3
ISS ISP ISIF Register Accessibility During Frame Processing
There are two types of register access in the ISIF:
• Shadowed registers (event latched registers)
Shadowed registers are those that can be read and written at any time, but the written values take
effect (are latched) only at certain times based on some event. Reads still return the most recent write
even though the settings are not used until the specific event occurs.
• Busy-writable registers
These registers/fields can be read or written even if the module is busy. Changes to the underlying
settings takes place instantly.
The following registers/fields can be set as shadow registers, or optionally set as busy-writable registers.
When the ISIF_CCDCFG[15] VDLC bit is set to 0, these registers are shadowed; when the
ISIF_CCDCFG[15] VDLC bit is set to 1, these registers are busy-writable. All other ISIF registers not
included in this list are always busy-writable.
3.4.1.4
ISIF_SYNCEN[1] DWEN
ISIF_MODESET[14] HLPF
ISIF_HDW
ISIF_VDW
ISIF_PPLN
ISIF_SLV1
ISIF_CULH
ISIF_CULV
ISIF_HSIZE
ISIF_SDOFST
ISIF_LPFR
ISIF_SPH
ISIF_LNH
ISIF_SLV0
ISIF_CADU
ISIF_CADL
ISIF_CCOLP
ISIF_CRGAIN
ISIF_CGRGAIN
ISIF_CGBGAIN
ISIF_CBGAIN
ISIF_COFSTA
ISIF_CLAMPCFG[0]
CLEN
ISIF_MISC
ISIF_CGAMMAWD
ISIF_FMTSPH
ISIF_FMTLNH
ISIF_FMTLSV
ISIF_FMTLNV
ISIF_LSCHOFST
ISIF_LSCVOFST
ISIF_DFCCTL
ISIF_VDFSATLV
ISS ISP ISIF Interframe Operations
Between frames, it may be necessary to enable or disable functions or to modify the memory pointers.
Because the ISIF_SYNCEN[1] DWEN bit and the memory pointer registers are shadowed, these
modifications can occur any time before the end of the frame and the data will be latched in for the next
frame. Likewise, the 2D-LSC registers can be changed after receiving the LSC SOF interrupt but before it
starts to prefetch the gain values for the next frame (the end of the LSC active region is reached). The
host controller can perform these changes upon receiving an interrupt.
3.4.1.5
ISS ISP ISIF Summary of Constraints
The following is a list of register configuration constraints to adhere to when programming the ISIF. It can
be used as a quick checklist. More detailed register setting constraints can be found in the individual
register descriptions.
• PCLK cannot be higher than 200 MHz.
• If SDRAM output port is enabled:
– The memory output line offset and address must be on 32-byte boundaries.
– ISIF_LNH[14:0] LNH –1 must be a multiple of 32 bytes.
– ISIF_SPH, ISIF_LNH, ISIF_SLV0, ISIF_SLV1, and ISIF_LNV must be cleared to 0 within the same
VD period that the ISIF_SYNCEN[1] DWEN bit is cleared to 0.
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
463
ISS ISP
www.ti.com
•
•
•
– ISIF_SPH, ISIF_LNH, ISIF_SLV0, ISIF_SLV1, and ISIF_LNV must be set from 0 to the appropriate
values within the same VD period that the ISIF_SYNCEN[1] DWEN bit is set to 1.
In RAW input mode:
– ISIF_CCDCFG[4] YCINSWP must be set to 0.
If DPCM compression is enabled:
– Horizontal culling must not be used. Use the input formatter instead.
For 2D-LSC:
– N=M (where M = horizontal downsampling factor, N = vertical downsampling factor)
– The ISIF_2DLSCINI register values must be even numbers.
– Maximum widths with respect to selected M value (see Table 216)
Table 216. ISS ISP ISIF Maximum Line Width Versus M Value
3.4.2
M
Maximum Line Width
8
2040
16
4080
32
8160
64
16,320
128
16,384
ISS ISP IPIPEIF Programming Model
This section discusses issues related to the software control of the IPIPEIF module. It lists the registers
that are required to be programmed in different modes, describes how to enable and disable the IPIPEIF
module and how to check the status of the IPIPEIF module, discusses the different register access types,
and enumerates several programming constraints.
3.4.2.1
ISS ISP IPIPEIF Hardware Setup/Initialization
This section discusses the configuration of the IPIPEIF module required before image processing can
begin.
3.4.2.1.1
ISS ISP IPIPEIF Reset Behavior
Upon hardware reset of the ISP (ISP5_SYSCONFIG[1] SOFTRESET = 0x1), all the registers in the
IPIPEIF are reset to their reset values.
3.4.2.1.2
ISS ISP IPIPEIF Register Setup
Before enabling the IPIPEIF, the hardware must be properly configured through register writes. Table 217
identifies the register parameters that must be programmed before enabling the IPIPEIF module
(depending on the functions needed).
Table 217. ISS ISP IPIPEIF Required Configuration Parameters
Step
Configuration Required
Value
General settings
Select the input sources for IPIPEIF.
IPIPEIF_CFG1[15:14] INPSRC1
IPIPEIF_CFG1[3:2] INPSRC2
464
Select VD sync polarity.
IPIPEIF_CFG2[2] VDPOL
Select HD sync polarity.
IPIPEIF_CFG2[1] HDPOL
Select the interrupt source.
IPIPEIF_CFG2[0] INTSW
Select the input clock source.
IPIPEIF_CFG1[10] CLKSEL
Set the clock divider value.
IPIPEIF_CLKDIV[15:0] CLKDIV
Set the data type: YUV or RAW.
IPIPEIF_CFG2[3] YUV16
SPRUHL6A – January 2013 – Revised June 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
ISS ISP
www.ti.com
Table 217. ISS ISP IPIPEIF Required Configuration Parameters (continued)
Step
Configuration Required
Value
Settings to perform if data is from BL
Set HD setting.
IPIPEIF_PPLN[12:0] PPLN
Set VD setting.
IPIPEIF_LPFR[12:0] LPFR
Set the number of valid pixels in a line.
IPIPEIF_HNUM[12:0] HNUM
Set the number of valid lines.
IPIPEIF_VNUM[12:0] VNUM
Set memory address information.
IPIPEIF_ADDRU[10:0] ADDRU
IPIPEIF_ADDRL[15:0] ADDRL
IPIPEIF_ADOFS[11:0] ADOFS
Set one-shot mode, if needed.
IPIPEIF_CFG1[0] ONESHOT
Use SYNCOFF function only for doublebuffering.
See Section 3.3.2.3.2.1 for details.
IPIPEIF_ENABLE[1] SYNCOFF
Settings to perform for RAW data from
ISIF or BL
Select the unpack function.
IPIPEIF_CFG1[9:8] UNPACK
Settings to perform for YUV for data from
ISIF
Set the data type to YUV.
IPIPEIF_CFG2[3] YUV16
If YUV16 = 0x1, enables or not the
conversion from 8 bits to 16 bits
IPIPEIF_CFG2[6] YUV8
If YUV16 = 0x1, set the way the data is
unpacked.
IPIPEIF_CFG2[7] YUV8P
DCPM function
RAW data from Buffer Logic (BL)
Enable or disable DPCM decompression.
IPIPEIF_DPCM[0] ENA
Select DPCM prediction mode.
IPIPEIF_DPCM[1] PRED
Select DPCM bit mode.
IPIPEIF_DPCM[2] BITS
Select inverse A-Law function.
IPIPEIF_CFG1[9:8] UNPACK
Select SDRAM read data shift.
- For RAW data
- DPCM enabled and A- Law disabled
- or DPCM disabled
IPIPEIF_CFG1[13:11] DATASFT
Dark frame subtraction (DFS) function
RAW data from VP (video port), BL(buffer
logic, SDRAM) or ISIF
Set defect pixel correction (DPC1) for VP
or ISIF inputs.
IPIPEIF_DPC1[12] ENA
Set the associated threshold for DPC1.
IPIPEIF_DPC1[11:0] TH
Set defect pixel correction (DPC2) for BL
inputs.
IPIPEIF_DPC2[12] ENA
Set the associate