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Texas Instruments DRA75x and DRA74x EVM CPU Board User guides
DRA7x EVM CPU Board
User's Guide
Literature Number: SPRUI50
February 2016
Contents
1
2
3
Introduction ......................................................................................................................... 5
Overview ............................................................................................................................. 5
2.1
EVM System Configurations ............................................................................................ 6
2.2
CPU Board Feature List ................................................................................................. 8
Hardware ........................................................................................................................... 10
3.1
Hardware Architecture ................................................................................................. 10
3.2
Reset Structure ......................................................................................................... 10
3.3
Boot Modes .............................................................................................................. 12
3.4
Signal Multiplex Logic .................................................................................................. 15
3.5
I2C Interface............................................................................................................. 22
7
................................................................................................................
3.7
TAG and Emulator ......................................................................................................
Power Supply.....................................................................................................................
4.1
Power Monitoring .......................................................................................................
CPU Board With Components Identification ..........................................................................
USB3 Supported Configurations ..........................................................................................
6.1
Option 1 ..................................................................................................................
6.2
Option 2 ..................................................................................................................
6.3
Option 3 ..................................................................................................................
References ........................................................................................................................
2
Table of Contents
3.6
4
5
6
GPIO List
27
28
28
29
31
31
32
33
34
34
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List of Figures
1
CPU Board.................................................................................................................... 6
2
CPU Board Block Diagram ................................................................................................ 10
3
Reset Structure ............................................................................................................. 11
4
CPU Board Switch and Button Locations (Rev E and earlier)
14
5
CPU Board Switch and Button Locations (Rev G and later)
15
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
.......................................................
.........................................................
NOR/NAND Booting vs FPD-Link Video Multiplexing .................................................................
QSPI vs Full Address NOR Flash Multiplexing .........................................................................
GPMC and MMC2 Multiplexing...........................................................................................
VIN1A and LI Camera Multiplexing ......................................................................................
VIN2A and RGMII1 Multiplexing..........................................................................................
VIN5A and MLB Multiplexing .............................................................................................
VIN4B and RGMII0 Multiplexing..........................................................................................
VIN6A and McASP1, 2, 3 and 7 Multiplexing...........................................................................
UART3 and SPI[2] Multiplexing ..........................................................................................
UART1 vs UART3 Multiplexing ...........................................................................................
I2C2 Vs HDMI Multiplexing ...............................................................................................
I2C3 vs DCAN2 Multiplexing..............................................................................................
Power Blocks ...............................................................................................................
Power Monitoring Block Diagram ........................................................................................
CPU Board ..................................................................................................................
3023009-01M USB 3.0 Micro-AB TO Standard-B 1m (3.28’) ........................................................
Qualtek SIIG JU-H40312-S14Pport USB3.0 Super Speed USB Hub ...............................................
Qualtek 3023007-01M USB3.0 Micro-AB to Micro-B 1m (3.28') ....................................................
IOGEAR GUH374 4-Port USB3.0 Hub ..................................................................................
Qualtek 3023005-01M USB3.0 Standard-A to Micro-B 1m (3.28') ..................................................
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List of Figures
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16
17
17
18
18
19
19
20
20
21
21
22
29
30
31
32
32
33
33
34
3
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List of Tables
EVM Wake-Up Board and Kits (Obsolete)
2
Production Boards (Obsolete) .............................................................................................. 7
3
Production Kits (Obsolete) .................................................................................................. 7
4
Production Boards ........................................................................................................... 7
5
Production Kits ............................................................................................................... 7
6
EVM Kit Truth Table ......................................................................................................... 8
7
12 V, 5A, 65W Compatible Wall Supplies ................................................................................ 8
8
Reset signals structure .................................................................................................... 11
9
SYS_Boot Switch Settings ................................................................................................ 12
10
Board Controls for Booting Options ...................................................................................... 13
11
Board Controls for Signaling and Operational Modes ................................................................. 13
12
NOR/NAND Booting vs FPD-Link Video Mux Control ................................................................. 16
13
QSPI vs Full Address NOR Flash Booting Mux Control
14
GPMC and MMC2 Selection Table ...................................................................................... 17
15
VIN1A Selection Table..................................................................................................... 18
16
VIN2A and RGMII1 Selection Table ..................................................................................... 19
17
VIN5A and MLB Selection Table ......................................................................................... 19
18
VIN4B and RGMII0 Selection Table ..................................................................................... 20
19
VIN6A and McASP1, 2, 3 and 7 Selection Table ...................................................................... 20
20
UART3 and SPI[2] Selection Table ...................................................................................... 21
21
UART1 vs UART3 Selection Table ...................................................................................... 21
22
I2C2 vs HDMI Selection Table
23
24
25
26
27
4
...............................................................................
1
..............................................................
...........................................................................................
I2C3 vs DCAN2 Selection Table .........................................................................................
I2C Device Address Chart ................................................................................................
GPIO Expander IO Chart ..................................................................................................
Configuration EEPROM Definition Table ................................................................................
GPIO List ...................................................................................................................
List of Tables
6
17
22
22
22
23
26
27
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User's Guide
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DRA7x EVM CPU Board
This user's guide is intended for software and hardware engineers developing applications for the Jacinto
6 high performance, multimedia application processor based on enhanced OMAP™ architecture
implemented with 28-nm technology. It describes the EVM CPU board’s hardware, firmware and software
functions supplied by Texas Instruments Inc.
The schematics mentioned in this document can be downloaded from the CPU EVM Schematic Rev H
(SPRR210).
1
Introduction
To allow scalability and re-use across DRA74x and DRA75x “Jacinto” Infotaiment System-on-Chips
(SoCs), it is based on “Jacinto 6 Ex” DRA75x SoC that incorporates a heterogeneous, scalable
architecture that includes a mix of two ARM® Cortex®-A15 Microprocessor Units, two ARM Cortex-M4
Processing Subsystems, each with two ARM Cortex-Microprocessors, two Digital Signal Processors (DSP
C66x), a Vision AccelerationPac including two Embedded Vision Engines (EVEs), 2D and 3D-Graphic
Processing Units including Imagination Technologies POWERVR® SGX544 dual-core and High-Definition
Image and Video Accelerator. Also it integrates a host of peripherals including multi-camera interfaces
(both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.
The main CPU board integrates these key peripherals such as Ethernet or HDMI, while the infotainment
application daughter board (JAMR3) and LCD/TS daughter board will complement the CPU board to
deliver complete system to jump start your evaluation and application development.
2
Overview
An EVM system is comprised of a CPU board with one or more application board(s). The CPU board
(shown in Figure 1) can be used standalone for software debug and development. Each EVM system has
been designed to enable customers to evaluate the Processor performance and flexibility in the following
targeted markets:
• Automotive Infotainment applications
• Automotive Vision applications
• Emerging End Equipment applications
The CPU board contains the (Jacinto 6/TDA2x) applications processor, a companion Power Management
IC (TPS659039), Audio Codec (TLV320AIC3106), DDR3 DRAM, four different Flash memories (QSPI,
eMMC, NAND and NOR), a multitude of interface ports and expansion connectors. The board provides
additional support components that provide software debugging, signal routing and configuration controls
that would not be needed in a final product. Different version CPU boards will be built to support the
development process that include:
• Socketed processor used for wakeup, early software development, quick and easy chip revision
evaluation
• Soldered-down processor used for high performance Use Cases and evaluations
All other components on-board are soldered-down.
OMAP is a trademark of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
POWERVR is a registered trademark of Imagination Technologies Limited.
All other trademarks are the property of their respective owners.
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Figure 1. CPU Board
2.1
EVM System Configurations
2.1.1
Revisions
• ES1.0 is on CPU Board through Rev E (obsolete), ES1.1 is on CPU Board Rev G (obsolete), and
ES2.0 is on CPU Board Rev H+
• Table 1 through Table 5 indicates the obsolete and valid production versions.
Table 1. EVM Wake-Up Board and Kits (Obsolete)
6
Wake-Up Platforms
Description
Model Number
ES1.0 CPU Bd
Socketed CPU Board, Power Supply and Limited
Accessory Cables.
EVM5777BX-01-00-00
ES1.0 EVM Kit
Socketed CPU Board, LCD/TS Daughter Bd, Power
Supply and Limited Accessory Cables.
EVM5777X-01-00-00
ES1.0 EVM Infotainment Kit
Socketed CPU Board, JAMR3 Apps Bd, LCD/TS
Daughter Bd, Power Supply and Limited Accessory
Cables.
EVM5777X-01-20-00
ES1.0 EVM Vision Kit
Socketed CPU Board, Vision Apps Bd, LCD/TS
Daughter Bd, Power Supply and Limited Accessory
Cables.
EVM5777X-01-40-00
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Table 2. Production Boards (Obsolete)
Production Boards
Description
Model Number
CPU Bd ES1.1 GP
CPU Board, Power Supply and Limited Accessory
Cables
EVM5777BG-02-00-00
CPU Bd ES1.1 HS
CPU Board, Power Supply and Limited Accessory
Cables
EVM5777BH-02-00-00
CPU Bd ES1.0 GP
CPU Board, Power Supply and Limited Accessory
Cables
EVM5777BG-01-00-00
CPU Bd ES1.0 HS
CPU Board, Power Supply and Limited Accessory
Cables
EVM5777BH-01-00-00
LCD/TS Daughter Board
7-inch WVGA LCD (24-bit color) with projective /
capacitive touch-screen and bezel / frame
EVM5777LCDTS-V1-0
10.1” LCD/TS Daughter
Board
10.1-inch 1280X800 LCD (24-bit color) with projective /
capacitive touch-screen and bezel / frame
EVM5777LCDTS-V2-0
Vision Application Board
Support for multiple camera inputs for surround view,
stereo vision, and proprietary camera board interfaces
EVM5777VISION-V1-0
Table 3. Production Kits (Obsolete)
Production Kits
Description
Model Number
ES1.1 GP EVM Kit
CPU Board, 10.1” LCD/TS Daughter Bd, Power Supply
and Limited Accessory Cables.
EVM5777G-02-01-00
ES1.1 GP EVM
Infotainment Kit
CPU Board, JAMR3 Apps Bd, 10.1” LCD/TS Daughter
Bd, Power Supply and Limited Accessory Cables.
EVM5777G-02-21-00
ES1.1 GP EVM Vision Kit
CPU Board, Vision Apps Bd, 10.1” LCD/TS Daughter Bd, EVM5777G-02-40-00
Power Supply and Limited Accessory Cables.
ES1.0 GP EVM Kit
CPU Board, LCD/TS Daughter Bd, Power Supply and
Limited Accessory Cables.
EVM5777G-01-00-00
ES1.0 GP EVM
Infotainment Kit
CPU Board, JAMR3 Apps Bd, LCD/TS Daughter Bd,
Power Supply and Limited Accessory Cables.
EVM5777G-01-20-00
ES1.0 GP EVM Vision Kit
CPU Board, Vision Apps Bd, LCD/TS Daughter Bd,
Power Supply and Limited Accessory Cables.
EVM5777G-01-40-00
Table 4. Production Boards
Production Boards
Description
Model Number
CPU Bd 2.0 GP
CPU Board and Limited Accessory Cables.
EVM5777BG-03-00-00
PU Bd ES2.0 HS
CPU Board and Limited Accessory Cables.
EVM5777BH-03-00-00
10.1” LCD/TS Daughter
Board
10.1-inch 1920X1200 LCD (24-bit color) capacitive touchscreen and bezel / frame
EVM5777LCDTS-V3-0
JAMR3 Application Board
Head-unit DIN form-factor Application Board with radio
tuners, multiple audio I/O’s, and video input extendibility
EVM5777JAMR3-V1-0
Vision Application Board
Support for multiple camera inputs for surround view,
stereo vision, and proprietary camera board interfaces,
AD7611 HDMI receiver
EVM5777VISION-V2-0
Table 5. Production Kits
Production Kits
Description
Model Number
ES2.0 GP EVM Kit
CPU Board, 10.1” LCD/TS Daughter Bd and Limited
Accessory Cables.
EVM5777G-03-00-00
ES2.0 GP EVM
Infotainment Kit
CPU Board, JAMR3 Apps Bd, 10.1” LCD/TS Daughter Bd EVM5777G-03-20-00
and Limited Accessory Cables.
ES2.0 GP EVM Vision Kit
CPU Board, Vision Apps Bd, 10.1” LCD/TS Daughter Bd
and Limited Accessory Cables.
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Table 6. EVM Kit Truth Table
Kit Name
CPU Bd
GP EVM
X
GP EVM Infotainment
X
GP EVM Vision
X
JAMR3 App Bd
LCD/TS Daughter
Bd
X
X
2.1mm to 2.5mm
Power Supply
Adapter
Vision App Bd
X
X
X
X
Wall Power Supply not included. Table 7 that lists the recommended and tested supplies.
Table 7. 12 V, 5A, 65W Compatible Wall Supplies
Manufacturer Part
Number
Manufacturer
102-3417-ND
SDI65-12-U-P5
CUI Inc.
62-1221-ND
KTPS65-1250DT-3PVI-C-P1
102-3419-ND
SDI65-12-UD-P5
CUI Inc.
Barrel Plug, 2.1mm I.D. x 5.5mm
O.D. x 9.5mm
SDI65-12-U-P6
CUI Inc.
Barrel Plug, 2.5mm I.D. x 5.5mm
O.D. x 9.5mm
SDI65-12-UD-P6
CUI Inc.
Barrel Plug, 2.5mm I.D. x 5.5mm
O.D. x 9.5mm
Digi-Key Part Number
SDI65-12-U-P6-ND
SDI65-12-UD-P6-ND
2.2
Notes
Barrel Plug, 2.1mm I.D. x 5.5mm
O.D. x 9.5mm
Required adapter,
provided in the EVM Kits
Volgen America/
Barrel Plug, 2.1mm I.D. x 5.5mm
Kaga Electronics USA O.D. x 9.5mm
Required adapter,
provided in the EVM Kits
Required adapter,
provided in the EVM Kits
CPU Board Feature List
•
•
•
•
•
•
8
Output Connector
Processor:
– SoC (23mm x 23mm package, 0.8mm pitch with 28x28 via-channel array)
– Support for corresponding socket
Memory:
– EMIF1 - DDR3L-1066 (with ECC): two 8Gbit (16bit data/ea) and one 4Gbit (8bit data, for ECC)
memory devices
– EMIF2 - DDR3L-1066: four 4Gbit (8bit data/ea) memory devices
– QSPI (Quad SPI)
– eMMC
– NAND flash memory 16 bit
– NOR flash memory
– I2C EEPROM
Boot mode selection DIP switch
On-Board Temperature Sensor
– TMP102
JTAG/Emulator:
– 60-pin MIPI Connector
– 20-pin-CTI adapter: 10 x 2, 1.27mm pitch
– 14-pin adapter: 7 x 2, 2.54mm pitch
Audio input and output:
– AIC3106 codec: Headphone OUT, Line OUT, Line IN, Microphone IN
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•
•
•
Connectors and Transceivers:
– CAN Interface - 2-wire PHY on DCAN1
– Two USB Host receptacles:
• USB3.0 (micro-USB)
• USB2.0 (mini-USB)
– PCIe x 1
– Video - one HDMI Out, one FPD-Link III, one LCD
– MLB and MLBP on Mictor connector
– RS232 via USB FTDI converter (mini-A/B USB)
– COM8 connector
– Gigabit Ethernet PHY (RJ45) x 2
– MicroSD socket
– SATA
– I2C Expander
– LCD Daughter Board connector
Power supply:
– 12 V DC input (Wall supply not supplied with Kit)
– Optimized Power Management IC (PMIC) Solution
– Support sleep mode with wake-up capability
PCB:
– Dimension (W x D): 170mm x 170mm
– Expansion Connectors to support application boards
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3
Hardware
3.1
Hardware Architecture
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Figure 2 shows the CPU Board’s Functional Block Diagram.
Figure 2. CPU Board Block Diagram
3.2
Reset Structure
The CPU board has two push buttons for reset:
• Power ON reset (PORz) (or cold reset for complete system reset)
• Warm reset (RESETn)
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EMU_ RSTn
RESETN
( Warm Reset)
CPU_ RESETn
CPU_ POR_ RESETn
PCI_ PORz
PMIC_ RESET_IN
PMIC
SOC
PORz
( Cold Reset)
PMIC_ RESET_ OUT
PMIC_ RESWARMN
RTC_ PORZ
RTC_ PORZ
RSTOUT
System
RSTOUTn
Figure 3. Reset Structure
Table 8 summarizes the reset signals.
Table 8. Reset signals structure
Reset Type
Reset Signal Sources
Comments
Power-On Reset Input
(as whole system reset)
CPU_POR_RESETn
PORn push button reset
PCI_PORz
PCIe inbound reset
PMIC_RESET_OUT
Power on reset from PMIC
CPU_RESETn
Warm push button reset
EMU_RSTn
Reset from Emulator
PMIC Power-On Reset Input
PMIC_RESET_IN
PMIC Power on reset input
RTC Power-On Reset Input
RTC_PORZ
RTC block power on reset
Reset Output
RSTOUTn
Reset output from processor to system
APP_BD_PORz
Reset to expansion connector
PMIC_NRESWARM
Warm Reset input to PMIC
Warm Reset Input
3.2.1
Wakeup Signals
Wakeup0 is connected to on-board CAN transceiver, and is used for multi-function. Under normal
operating modes, the pin can be configured/used as DCAN receive input. When placed in RTC sleep
mode, the pin can be configured as to trigger wakeup events from CAN bus.
Wakeup 1 is connected to PMIC, and is used for multi-function. Under normal operating modes, the pin
can be configured as input to receive interrupt events from PMIC. When placed in RTC sleep mode, the
pin can be configured as to trigger wakeup events from PMIC.
Wakeup 2 is connected to both LCD and expansion connectors. Under normal operation modes, the pin is
configured as input to receive interrupts from LCD touch panel controller.
Wakeup 3 is connected to expansion connector, and can be used as either wakeup event or general
purpose input.
NOTE: ES1.0 Rev E system and older supported an on-board pushbutton to generate wakeup
event. Depending on revision, the button was connected to either Wakeup1 or Wakeup2.
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3.3
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Boot Modes
Multiple boot modes are supported as determined by the 16-bit “system boot” setting present on the
shared specific I/O balls during power-on sequence. For more information, see the device-specific
technical reference manual (TRM). These shared I/O resources can be “redeployed” to support alternate
interfaces after boot-up by changing of the on-die mux mode settings per I/O and configuring CPU board’s
on-board bus logic switches. Boot mode selection is accomplished by the setting of DIP switches SW2
and SW3 as shown in Table 9.
Table 9. SYS_Boot Switch Settings
Interface
(Internal System Boot Input)
CPU Bd Net
DIP Switch Ref Des
Position No Connections
Factory Settings
GPMC_AD0
(sysboot0)
GPMC_D00
SW2.P1
ON
GPMC_AD1
(sysboot1)
GPMC_D01
SW2.P2
OFF
GPMC_AD2
(sysboot2)
GPMC_D02
SW2.P3
ON
GPMC_AD3
(sysboot3)
GPMC_D03
SW2.P4
OFF
GPMC_AD4
(sysboot4)
GPMC_D04
SW2.P5
ON
GPMC_AD5
(sysboot5)
GPMC_D05
SW2.P6
OFF
GPMC_AD6
(sysboot6)
GPMC_D06
SW2.P7
OFF
GPMC_AD7
(sysboot7)
GPMC_D07
SW2.P8
OFF
GPMC_AD8
(sysboot8)
GPMC_D08
SW3.P1
OFF
GPMC_AD9
(sysboot9)
GPMC_D09
SW3.P2
OFF
GPMC_AD10
(sysboot10)
GPMC_D10
SW3.P3
OFF
GPMC_AD11
(sysboot11)
GPMC_D11
SW3.P4
OFF
GPMC_AD12
(sysboot12)
GPMC_D12
SW3.P5
OFF
GPMC_AD13
(sysboot13)
GPMC_D13
SW3.P6
OFF
GPMC_AD14
(sysboot14)
GPMC_D14
SW3.P7
OFF
GPMC_AD15
(sysboot15)
GPMC_D15
SW3.P8
OFF
3.3.1
On-Board Boot Routing Control
CPU board has external, on-board multiplexing bus logic switches to enhance the flexibility of the EVM.
Multiplexing options on-board should be selected accordingly to the desired boot mode to enable interface
paths required to access desired boot devices or port. DIP Switch SW5 has 10 individual SPST positions.
Positions 1-5 have been used to control board signal routing for booting. Positions 6-10 have been used to
control other CPU board signaling paths and modes of operation.
SW5 DIP switches connect nets to strong (1k) pull-down resistors to ground when a switch is set to the
“ON” position, corresponding to a “Low” logic level signal. Alternatively, when switch is in the “OFF”
position, a 10k pull-up connects it to 3.3 V rail, corresponding to a “High” logic level signal.
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Table 10. Board Controls for Booting Options
DIP Switch
Factory Settings
I2C1 GPIO
Expander
Low = Enable GPMC_nCS0 for NAND flash
boot
SW5.1
OFF
U57.P10
NOR_BOOTn (2)
Low = Enable GPMC_nCS0 for NOR flash boot
SW5.2
OFF
U57.P11
MMC2_BOOT
Low = Enable MMC2 Interface for eMMC flash
boot
SW5.3
OFF
U57.P12
QSPI_BOOT
Low = Enable QSPI1 Interface for QSPI flash
boot
SW5.4
OFF
U57.P13
UART_SEL1_3
High = UART3 Interface for UART boot is
enabled
SW5.5
ON
U57.P14
Signals
Description
NAND_BOOTn
(1)
(1) Routing control for GPMC_nCS0 is “shared” between NOR & NAND Flash memories. Ensure that only one DIP switch, SW5.P1
or SW5.P2, is ever set to “ON” state at any one time so that GMPC_nCS0 is only connected to one memory. Failure to adhere
to this requirement causes NOR & NAND memory data bus contention.
(2) GPIO Expander (U57) connections to “Board Signal” nets are intended to provide a “read-only” feature to determine boot image
source (NOR or NAND). Boot image selection must be set before power on sequence by setting DIP Switches SW2 and SW3
along with SW5.P1 and .P2 appropriately, as shown above.
Table 11. Board Controls for Signaling and Operational Modes
DIP Switch
Factory
Settings
I2C1 GPIO
Expander
Low = Enable COMx signal paths
SW5.6
OFF
U57.P15
FORCE_EMU
Always set low
SW5.7
OFF
U57.P17
PCI_RESET_SEL
High = PCIe device may reset
Low = May reset the PCIe device
SW5.8
OFF
NA
GPMC_WPN
Low = Enable write protection of NAND Flash
SW5.9
OFF
NA
I2C_EEPROM_WP
High = Enable write protection of Board identification
EEPROM
SW5.10
OFF
NA
PMIC_BOOT1
Low = Always, pull-down resistor
NA
NA
NA
PMIC_BOOT0
(Rev E and older only)
ON = High = Double Reset Pulse Mode
OFF = Low = Power-up seq and voltages (Single reset
pulse)
SW8.1
ON
NA
PMIC_BOOT0
(Rev G+ Board only)
ON = Low = Power-up seq and voltages (Single reset
pulse)
OFF = High = Double Reset Pulse Mode
SW8.1
ON
NA
GPIO_PWR_MUX
(Rev E and older only)
ON = High = Connect PMIC GPIOs as follows:
• GPIO_4 = EVM_3V3_SW power load switch
enable
• GPIO_6 = 1V35_DDR power converter enable
OFF = Low = Connect PMIC GPIOs as follows:
• GPIO_4 = 1V35_DDR power converter enable
• GPIO_6 = EVM_3V3_SW power load switch
enable
SW8.2
OFF
NA
AIC _I2C_ ADDR_CTL
(SW8.2 reused in Rev G+,
boards for AIC I2C address
selection)
ON = High = i2C – 0X19 (for AIC operation with 10.1”
display support)
OFF = Low = I2C=0X18 (for AIC operation with 7”
display support)
SW8.2
ON
NA
Signals
Description
MCASP1_ENn
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Figure 4. CPU Board Switch and Button Locations (Rev E and earlier)
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Figure 5. CPU Board Switch and Button Locations (Rev G and later)
3.4
Signal Multiplex Logic
A high level of internal I/O signal multiplexing is supported to maximize silicon functionality available at
package balls. Likewise, the CPU board design uses a combination of FET switch and passive resistor
multiplexers to route the signals to different functional blocks or peripheral components to maximize
development platform system functionality. The following sections and diagrams will illustrate the flexibility
of the on-die and CPU’s on-board signal multiplexing options.
3.4.1
NOR/NAND Booting vs FPD-Link Video
A high level of internal I/O signal multiplexing is supported to maximize silicon functionality available at the
package balls. Likewise, the CPU board design uses a combination of FET switch and passive resistor
multiplexers to route the signals to different functional blocks or peripheral components to maximize
development platform system functionality. The following sections and diagrams illustrate the flexibility of
the on-die and CPU’s on-board signal multiplexing options.
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Figure 6. NOR/NAND Booting vs FPD-Link Video Multiplexing
Table 12. NOR/NAND Booting vs FPD-Link Video Mux Control
Interface
NOR_BOOTn (1), (2)
NAND_BOOTn (1), (2)
GPMC_AD and
GPMC_nCS0
Low (SW5.P2 = ON)
High (SW5.P1 = OFF)
High (SW5.P2 = OFF)
Low (SW5.P1 = ON)
VOUT3B
NA
NA
SEL_GPMC_AD_VID_S0
(3), (4), (5)
Device
High
NOR Flash
NAND Flash
Low
FPD-Link
(1) Routing control for GPMC_nCS0 is “shared” between NOR and NAND Flash memories. Ensure that only one DIP switch,
SW5.P1 or SW5.P2, is ever set to “ON” state at any one time so that GMPC_nCS0 is only connected to one memory. Failure to
adhere to this requirement will cause NOR & NAND memory data bus contention.
(2) GPIO Expander (U57) connections to “Board Signal” nets are intended to provide a “read-only” feature to determine boot image
source NOR or NAND). Boot image selection must be set before power on sequence by setting DIP Switches SW2 and SW3
along with SW5.P1 and .P2 appropriately, as shown above.
(3) Bus Logic Switch select input S1 is the inversion of select input S0 connected to SEL_GPMC_AD_VID_S0 net controlled via
GPIO Expander U57.P0.
(4) Bus Logic Switches (RU33, 88 and 94) power-up with S0 = High via pull-up resistor resulting in GPMC_AD bus routed to
memories (S1, S0 = 0, 1).
(5) GPIO Expander (U57) is accessible via I2C1, address 0x21.
3.4.2
QSPI vs NOR Flash Booting
The CPU can be booted from either a QSPI or NOR Flash memory component. The memory interface
signals are routed through a “Resistor Bypass Path” for optimal QSPI signal integrity (SI) or “Bus Logic
Switch Path” for flexible boot image selection. The source and load “muxing resistors” that enable the
“Resistor Bypass Path” have been installed on CPU boards as the default configuration for QSPI booting
with optimal SI. As a consequence, six of the upper GMPC address signals (A13 – A18) are not
connected to the NOR Flash memory due to source muxing resistors being “No-Mount” on the “Bus Logic
Switch Path”. This limits the addressable NOR memory to an 8KByte range (A0-A12) due to default mux
resistor mounting. The “resistor muxing” option would need to change to route the GPMC signals via “Bus
Logic Switch Path” to the NOR Flash memory in order to access the full addressable range of the NOR
memory.
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Figure 7. QSPI vs Full Address NOR Flash Multiplexing
Table 13. QSPI vs Full Address NOR Flash Booting Mux Control
Muxing Resistors
Mounted
Muxing Resistors
“Not-Mounted”
Signal Path
QSPI_BOOT (3), (4)
Device
QSPI
R735, R737, R739,
R741,R743, R745,
R747
R736, R738, R740,
R742, R744, R746,
R748
Resistor Bypass (1)
NA
QSPI Flash
GPMC
R736, R738, R740,
R742, R744, R746,
R748
R735, R737, R739,
R741, R743, R745,
R747
Bus Switch (2)
Low
(SW5.P4 = ON)
QSPI Flash
High
(SW5.P4 = OFF)
NOR Flash
Interface
QSPI
(1) Best PCB Signal Integrity (SI) routing is default configuration via Resistor Bypass Path for QSPI signaling.
(2) Most flexible routing is optional configuration via Bus Logic Switch pending SI validation for QSPI signaling.
(3) GPIO Expander (U57) connection to “nQSPI_BOOT” net is intended as a “read-only” feature to determine boot image source
(QSPI or NOR). Boot image selection must be set before power on sequence.
(4) GPIO Expander (U57) is accessible via I2C1, address 0x21.
3.4.3
GPMC Vs MMC2
Multiplex control logic for GPMC and MMC2 is shown in Figure 8.
Figure 8. GPMC and MMC2 Multiplexing
The default interface are the GPMC signals; the selection table is shown in Table 14.
Table 14. GPMC and MMC2 Selection Table
GPMC vs MMC2
GPMC/MMC2
MMC2_BOOT
Interface
Device
1
GPMC
NOR Flash
0
MMC2
eMMC
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Use Bit “P12” in the I2C IO Expander (U57) with slave address 0x0100 0010(Write) to control, signal
"MMC2_BOOT". A DIP switch is also available to control the MMC2_BOOT signal for boot mode
configuration.
3.4.4
VIN1A Vs LI Camera
VIN1A signal group can be switch between on-board LI Imager and expansion connector as shown in
Figure 9.
Figure 9. VIN1A and LI Camera Multiplexing
The default interface is VIN1A interface to expansion connectors and the selection table is shown in
Table 15.
Table 15. VIN1A Selection Table
VIN1A vs LI Camera
VIN1A
CAM_FPD_MUX_S0
Interface
Device
1
VIN1A
Expansion Connector
0
VIN1A
LI-CAMERA
Use Bit “P3” in the I2C IO Expander(U119) with slave address 0x0100 0100(Write) to control, signal
"CAM_FPD_MUX_S0".
3.4.5
VIN2A Vs RGMII1
Multiplex control logic for VIN2A and RGMII1 is shown in Figure 10.
Figure 10. VIN2A and RGMII1 Multiplexing
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The default interface is RGMII1 and the selection table is shown in Table 16.
Table 16. VIN2A and RGMII1 Selection Table
VIN2A vs RGMII1
VIN2_S0
Interface
Device
1
RGMII1
Gbit Ethernet PHY
0
VIN2A
Expansion Connector
VIN2A/RGMII1
Use bit “P2” in I2C IO Expander (U119) with slave address 0x0100 0100(Write) to control, signal
"VIN2_S0".
3.4.6
VIN5A Vs MLB
VIN5A or MLB can be selected through the resistor mounting options available on board as shown in
Figure 11.
Figure 11. VIN5A and MLB Multiplexing
The default interface is VIN5A to the expansion connector. The selection table is shown in Table 17.
Table 17. VIN5A and MLB Selection Table
VIN5A vs MLB
Mount
No Mount
Interface
Device
VIN5A and MLB
R538, R526, R525
R541, R527, R177
VIN5A
Expansion Connector
R541, R527, R177
0R538, R526, R525
MLB Interface
MLB Conn
3.4.7
VIN4B vs RGMII0
Multiplex control logic for VIN4B and RGMII0.
Figure 12. VIN4B and RGMII0 Multiplexing
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Table 18. VIN4B and RGMII0 Selection Table
VIN4B vs RGMII0
SEL_ENET_MUX_S0
Interface
Device
VIN4B and RGMII0
1
RGMII0
Gbit Ethernet PHY
0
VIN4B/GPIO's
Expansion Connector
Use Bit “P4” in I2C IO Expander (U57) with slave address 0x0100 0010(Write) to control, signal
"SEL_ENET_MUX_S0".
3.4.8
VIN6A Vs McASP1, 2, 3 and 7
Multiplex control logic for VIN6A and McASP1, 2, 3 and 7.
Figure 13. VIN6A and McASP1, 2, 3 and 7 Multiplexing
The default interface is VIN6A to the expansion connector and the selection table is shown in Table 19.
Table 19. VIN6A and McASP1, 2, 3 and 7 Selection Table
VIN6A vs McASP1,2,3 and 7
VIN6A/McASP1,2,3 and 7
VIN6_SEL_S0
Interface
Device
1
VIN6A
Expansion Connector
0
McASP1,2,3 and 7
TLV320AIC3106, COM8 Conn,
Exp.Conn.
Use Bit “P1” in I2C IO Expander (U119) with slave address 0x0100 0100(Write) to control, signal
"VIN6_SEL_S0".
3.4.9
UART3 Vs SPI[2]
Multiplex control logic for UART3 and SPI[2].
Figure 14. UART3 and SPI[2] Multiplexing
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The default interface is UART3 and the selection table is shown in Table 20.
Table 20. UART3 and SPI[2] Selection Table
UART3 vs SPI[2]
CAM_FPD_MUX_S0
Interface
Device
UART3 and SPI[2]
1
SPI[2]
Expansion Connector
0
UART3
FTDI UART and COM8 Conn
Use Bit “P16” in I2C IO Expander (U57) with slave address 0x0100 0010(Write) to control, signal
"SEL_UART3_SPI2".
3.4.10
UART1 vs UART3
Upon selection of UART3, it has been multiplexed with UART1 and then connected to FT232RQ UART to
the USB converter for the USB console. GPIO expander selection can be override by available manual
switch on board. The corresponding image is shown in Figure 15 and the UART1 vs UART3 selection
table is shown in Table 21.
Figure 15. UART1 vs UART3 Multiplexing
Table 21. UART1 vs UART3 Selection Table
UART1 vs UART3
UART_SEL1_3
Interface
Device
UART3 and SPI[2]
1
UART3
FT232RQ
0
UART1
Use bit “P14” in I2C IO Expander (U57) with slave address 0x0100 0010(Write) to control, signal
"UART_SEL1_3". A DIP switch is also available to control the UART_SEL1_3 signal for boot mode
configuration.
3.4.11
I2C2 Vs HDMI
Multiplex control logic for I2C2 and HDMI.
Figure 16. I2C2 Vs HDMI Multiplexing
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The default interface is I2C2 interface and the I2C2 Vs HDMI selection table is shown in Table 22.
Table 22. I2C2 vs HDMI Selection Table
I2C2 vs HDMI
SEL_HDMI_I2C2
Interface
Device
I2C2and HDMI
1
HDMI
HDMI DDC and Signals
0
I2C2
GPIO Expander, FPD-Link, LI
Camera, Exp. Conn.
Use McASP2_ACLKR (ball E15) to control signal “SEL_HDMI_I2C2”.
3.4.12
I2C3 vs DCAN2
Multiplex control logic for I2C3 and DCAN.
Figure 17. I2C3 vs DCAN2 Multiplexing
The default interface is I2C3 interface and the I2C3 vs DCAN2 selection table is shown in Table 23.
Table 23. I2C3 vs DCAN2 Selection Table
I2C3 vs DCAN2
SEL_I2C3_CAN2
Interface
Device
I2C3 and DCAN2
1
DCAN2
Header
0
I2C3
Expansion Connector
Use bit “P3” in I2C IO Expander (U57) with slave address 0x0100 0010(Write) to control, signal
"SEL_I2C3_CAN2".
3.5
I2C Interface
Table 24 shows the list of I2C interface available with the list of devices connected in each I2C interface
and its corresponding device address.
Table 24. I2C Device Address Chart
CPU Board
Part No
EEPROM
I2C1
24WC256
U105
X
Digital Temperature Sensor
TMP102AIDRLT
U117
X
0x48
Digital Temperature Sensor
TMP102AIDRLT
U109
X
Either U117 or
U109 will be
mounted on
board
GPIO Expander
PCF8575
U58
X
0x20
GPIO Expander
PCF8575
U57
X
0x21
MLB Connector
Connector
P8
X
NA
LCD Interface
Connector
J15
X
NA
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I2C2
I2C3
Device
Address(7b)
Ref. Des
0x50
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Table 24. I2C Device Address Chart (continued)
CPU Board
Part No
COM8 Connector
Connector
Audio Codec
TLV320AIC3106
Expansion Connector
Connector
PMIC
TPS659039 - DVS
Ref. Des
I2C1
I2C2
I2C3
Device
Address(7b)
P9
X
NA
U59
X
0x18 or 0X19 (1)
EXP_P2
X
NA
U45
X
0x12
TPS659039 - Power
U45
X
0x58
TPS659039 - Interfaces
U45
X
0x59
TPS659039 - Trimming
U45
X
0x5A
X
TPS659039 - OTP
U45
GPIO Expander
PCF8575
U119
X
0x5B
0x26
FPD Link
DS90UH925Q
U3
X
0x1B
LI Camera
Connector
J5
X
NA
Expansion Connector
Connector
EXP_P3
X
NA
HDMI DDC
Connector
P4
X
Expansion Connector
Connector
EXP_P1
NA
X
NA
1. 0X18 on Rev E boards and older. On Rev G boards and later, I2C address is switchable (SW8.P2).
Need 0X18 on AIC when using 7” display and 0X19 when using 10.1” display.
3.5.1
I2C GPIO Expander IO List
Table 25. GPIO Expander IO Chart
Ref. Des
U58
Slave
Address
0b0010 000
(0x20)
I2C I/F
Expander IO
I2C1
INT#
Netname
Description
PCF8575_INT
Interrupt output
P0
TS_LCD_GPIO1
Press Button Switch 1
P1
TS_LCD_GPIO2
Press Button Switch 2
P2
TS_LCD_GPIO3
Press Button Switch 3
P3
TS_LCD_GPIO4
Press Button Switch 4
P4
USER_LED1
User LED 1
P5
USER_LED2
User LED 2
P6
USER_LED3
User LED 3
P7
USER_LED4
User LED 4
P10
EXP_ETH0_RSTn
RGMII0 Reset
P11
EXP_ETH1_RSTn
RGMII1 Reset
P12
USB1-VBUS_OCN
USB1 Over Current Indication
P13
USB2-VBUS_OCN
USB2 Over Current Indication
P14
PCI_SW_RESETn
PCI Interface SW Reset
P15
CON_LCD_PWR_DN
LCD Board Master power enable
P16
NC
No Connection
P17
TMP102_ALERT
Digital Temp. sensor Altert signal
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Table 25. GPIO Expander IO Chart (continued)
Ref. Des
U57
(0x21)
24
Slave
Address
0b0010 001
I2C I/F
Expander IO
Netname
Description
I2C1
INT#
NC
No Connection (Rev D and earlier)
INT#
PCF8575_INT
Interrupt output (Rev E and later
only)
P0
SEL_GPMC_AD_VID_S0
MUX out control signal for GPMC
Vs VOUT3B
P1
USB1_ID
USB1 ID PIN
P2
USB2_ID
USB2 ID PIN
P3
SEL_I2C3_CAN2
MUX out control signal for I2C3 Vs
DCAN2
P4
SEL_ENET_MUX_S0
MUX out control signal for RGMII0
Vs VIN4B
P5
MMC_PWR_ON
Power on MMC
P6
NC
No Connection
P7
NC
No Connection
P10
NAND_BOOTn
NAND boot Chip select enable
signal
P11
NOR_BOOTn
NOR boot Chip select enable
signal
P12
MMC2_BOOT
MUX out control signal for GPMC
Vs MMC2
P13
QSPI_BOOT
MUX out control signal for GPMC
Vs QSPI1
P14
UART_SEL1_3
MUX out control signal for UART1
Vs UART3
P15
MCASP1_ENn
COM8 interface level shifter
enable signal
P16
SEL_UART3_SPI2
MUX out control signal for UART3
Vs SPI2
P17
FORCE_EMU
MUX out control signal for EMU
signals
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Table 25. GPIO Expander IO Chart (continued)
Ref. Des
U119
(0x26)
Slave
Address
0b0010 010
I2C I/F
Expander IO
I2C2
P0
Netname
Description
Cannot revert back to I2C2 after
selecting HDMI
(***DO NOT USE)
***DO NOT USE.
McASP2_ACLKR replaces this
signal. Drive McASP2_ACLKR (in
McASP GPIO mode) as the
SEL_HDMI_I2C2 signal.
P1
VIN6_SEL_S0
MUX out control signal for VIN6A
and McASPx
P2
VIN2_S0
MUX out control signal for EMAC1
and VIN2A Signals
P3
CAM_FPD_MUX_S0
MUX out control signal for VIN1A
& LI Camera Signals
P4
HDMI_CT_HPD
HDMI Hot Plug Detect
P5
HDMI_LS_OE
HDMI Level Shifter Enable
P6
NC
No Connection
P7
NC
No Connection
P10
NC
No Connection
P11
NC
No Connection
P12
NC
No Connection
P13
NC
No Connection
P14
NC
No Connection(Rev E and earlier)
P15
NC
No Connection(Rev E and earlier)
P16
NC
No Connection(Rev E and earlier)
P17
NC
No Connection(Rev E and earlier)
P14
MMC2_BOOT_OVR_OEN
MMC2 DIP Switch Override
Enable(Rev G)
P15
MMC2_BOOT_OVR
MMC2 DIP Switch Override (Rev
G)
P16
NOR_BOOT_OVR_OEN
NOR BOOT DIP Switch Override
Enable (Rev G)
P17
NOR_BOOT_OVR
NOR BOOT DIP Switch Override
(Rev G)
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User Interface LED’s
The board has four user interface LEDs for debug, status indication and so on. Details about the user
interface LED and its GPIO assignment is shown in Table 25.
3.5.3
Configuration EEPROM
The CPU board contains an EEPROM memory device for storing and retrieving configuration information.
The EEPROM provides 256Kb (or 32KBytes) of storage space, and is accessible via I2. Device location
information is located in Table 24. The configuration ID information is programmed by the factory at time
of manufacturing, and should not be altered. Table 26 shows the configuration data format within the
EEPROM.
Table 26. Configuration EEPROM Definition Table
Byte
Location
Value
(Rev H CPU board
example)
ID.HEADER
[3:0]
0xAA5533EE
ID.BOARD_NAME
[19:4]
‘5777xCPU-DDR3’
(ascii)
ID.VERSION_MAJOR
[21:20]
0x7
A=0x1
B=0x2
C=0x3
D=0x4
E=0x5
F Skipped
G=0x6
H=0x7
ID.VERSION_MINOR
[23:22]
0x0
0x0 for major revision
0x1-0x15 for others
ID.CONFIG_OPTION
[27:24]
0x3E
EEPROM Field
Description
Fixed value at start of header ID.
Fixed value of ‘5777xCPU’ or ‘5777xCPU-DDR3’
Bit 6: 1 – EMIF2 ECC Supported, 0 - No
Bit 5: 1 – EMIF2 Supported, 0 – No
Bit 4: 1 – EMIF1 ECC Supported, 0 – No
Bit
Bit
Bit
Bit
3: 1 – EMIF1 Supported, 0 – No
2: 1 – Extended Memory EEPROM Cfg Support, 0 – No (1)
1: 1 – MAC addr in EEPROM (default)
0: 0 - QSPI (default), 1 - NOR
EMIF1_SIZE_BYTES
[31:28]
0x8000 0000
Memory size for EMIF1 in bytes (unsigned long) (2)
EMIF2_SIZE_BYTES
[35:32]
0x8000 0000
Memory size for EMIF2 in bytes (unsigned long) (2)
RESERVED
[55:36]
0x0
MAC_ADDR
0x7F00
00.0E.99.zz.yy.xx
Reserved (2)
Optional MAC address
(1) If Bit 2 is set to 0, all EEPROM data beyond that is set to 0 (Not defined or Used). If set to 1, the mapping is per the table.
(2) Prior to Rev H, Bytes [55:28] were reserved and set to 0x0.
For reference, a C-style coded structure is provided:
Struct EEPROM_ID_T
{
Unsigned long header;
Char board_name[16];
Unsigned short version_major;
Unsigned short version_minor;
Unsigned long config_option;
Unsigned long emif1_size_bytes;
Unsigned long emif2_size_bytes;
Char reserved[28];
} eeprom_id;
4
16
2
2
4
4
4
20
56 Bytes
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3.6
GPIO List
Table 27 shows the GPIO lists.
Table 27. GPIO List (1)
CPU Bd Net
(I/F Component Des.Pin)
GPIO / Sym
Ball Name (ball no.)
Function
Peripheral Device
Intermediate Net
Application Board
Expansion Connector
GP5[0]
(EXP_P2.34)
NA
GPIO5_0
MCASP1_ACLKR
(B14)
Application Board
Expansion Connector
GP5[1]
(EXP_P2.36)
NA
GPIO5_1
MCASP1_FSR
(J14)
Connectivity on Module
COM8 Connector
GP5[4]
(P9.89)
BT_EN
GPIO5_4
MCASP1_AXR2
(G13)
Connectivity on Module
COM8 Connector
GP5[5]
(P9.50)
GPS_PPS_OUT
GPIO5_5
MCASP1_AXR3
(J11)
Connectivity on Module
COM8 Connector
GP5[6]
(P9.48)
GPS_TIME_STAMP
GPIO5_6
MCASP1_AXR4
(E12)
Connectivity on Module
COM8 Connector
GP5[7]
(P9.34)
WLAN_IRQ
GPIO5_7
MCASP1_AXR5
(F13)
Connectivity on Module
COM8 Connector
GP5[8]
(P9.4)
WL_EN
GPIO5_8
MCASP1_AXR6
(C12)
Media Local Bus(MLB)
MLB Connector
GP5[9]
(P8.34)
NA
GPIO5_9
MCASP1_AXR7
(D12)
I2C GPIO Expander
PCF8575
PCF8575_INT
(U58.1) Rev D and earlier
(U57.1 and U58.1) Rev E
and later
NA
GPIO6_11
(AB4)
I2C2/HDMI
I2C2 bus, HDMI
HPD/CEC
SEL_HDMI_I2C2
NA
MCASP2_ACLK
(use as McASP GPIO)
Interrupt
Ethernet PHY
ENET_INTSn
(U15.4)
NA
GPIO6_16
(F21)
Media Local Bus(MLB)
MLB Connector
GP6_[28]
(P8.24)
NA
GPIO6_28
MMC1_SDWP
(Y9)
Application Board
Expansion Connector
GP5[17]
(EXP_P2.32)
NA
RMII_MHZ_50_CLK
GPIO5_17
(U3)
Application Board
Expansion Connector
GP5[31]
(EXP_P1.38)
C_EMAC[0]_RXD0
RGMII0_RXD0
GPIO5_31
(W2)
Application Board
Expansion Connector
GP5[30]
(EXP_P1.36)
C_EMAC[0]_RXD1
RGMII0_RXD1
GPIO5_30
(Y2)
Application Board
Expansion Connector
GP5[29]
(EXP_P1.34)
C_EMAC[0]_RXD2
RGMII0_RXD2
GPIO5_29
(V3)
Application Board
Expansion Connector
GP5[25]
(EXP_P1.35)
C_EMAC[0]_TXD0
RGMII0_TXD0
GPIO5_25
(U6)
Application Board
Expansion Connector
GP5[22]
(EXP_P1.33)
C_EMAC[0]_TXD3
RGMII0_TXD3
GPIO5_22
(V7)
Application Board
Expansion Connector
GP2[27]
(EXP_P2.108)
NA
GPMC_BEN1
GPIO2_27
(M4)
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Table 27. GPIO List (1) (continued)
CPU Bd Net
(I/F Component Des.Pin)
GPIO / Sym
Ball Name (ball no.)
Function
Peripheral Device
Intermediate Net
Application Board
Expansion Connector
GP6[17]
(EXP_P1.15)
NA
XREF_CLK0
GPIO6_17
(D18)
Application Board
Expansion Connector
GP6[20]
(EXP_P3.13)
NA
XREF_CLK3
GPIO6_20
(C23)
Interrupt
PMIC
PMIC_INT
(U45.PK1)
NA
WAKEUP1
GPIO1_1
(AC17)
Display Interface
Display Connector
GP1[2]
(EXP_P1.13)
GP1[2] - (TS_IRQ)
WAKEUP2
GPIO1_2
(AB16)
Application Board
Expansion Connector
GP1[3]
(EXP_P1.14)
NA
WAKEUP3
GPIO1_3
(AC16)
1. Functional signals of pin mux are not considered for this table. For more information, see CPU EVM
Schematic Rev H (SPRR210).
3.7
TAG and Emulator
The CPU Board has support of the following JTAG emulation headers support:
• 60-Pin MIPI Connector
• Standard 14-pin to 60-pin MIPI adapter
• 20-pin CTI to 60-pin MIPI adapter
4
Power Supply
The companion power management IC (PMIC) for the SOC is TPS659039EP-Q1. A step-down 12 V to
3.3 V and 5 V converters are available in order to provide a 3.3V and 5 V DC input to the PMIC as well as
3.3 V and 5 V power rails at the board level.
Figure 18 shows the complete power supply section of the CPU board. For power on/off sequence, see
TPS65903x-Q1 Automotive Power Management Unit (PMU) for Processor Data Sheet (SWCS095).
28
DRA7x EVM CPU Board
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Copyright © 2016, Texas Instruments Incorporated
Power Supply
www.ti.com
Figure 18. Power Blocks
4.1
Power Monitoring
The CPU Board has provisions for power monitoring using INA226. The measurement system is
consisting of the TI INA226 I2C current shunt/power monitors. The INA226 device provides both power
supply voltage and shunt current measurements, as well as calculated power via an I2C bus. This allows
the device to be placed close to the shunt.
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Copyright © 2016, Texas Instruments Incorporated
29
Power Supply
www.ti.com
Figure 19 shows a block diagram of the current monitoring system. INA226 are located at the appropriate
shunts for various supplies are listed below. These INA226s would be controlled by an off-board MSP430
(or similar device) via a dedicated I2C bus mastered by the off-board device.
Figure 19. Power Monitoring Block Diagram
Power supply pin groups that are monitored are as follows:
• VDD_MPU
• VDD_GPU
• VDD_DSPEVE
• CORE_VDD
• VDD_IVA
• CPU_VDD_DDR
• VDD_DDR
• VDDS18V
• VDDA_1V8_PLL
• VDDA_1V8_PHY
• VUSB_3V3
• VDDSHV
30
DRA7x EVM CPU Board
SPRUI50 – February 2016
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CPU Board With Components Identification
www.ti.com
5
CPU Board With Components Identification
Figure 20. CPU Board
6
USB3 Supported Configurations
The following USB3.x combinations are supportable:
• Micro-A plug to Standard-B plug
– Connect to hub or external drive/device that has a std B receptacle
• Micro-A plug to Micro-B plug
– EVM connects to hub or external drive/device that has a micro B receptacle
– Host connects to the EVM acting as a device
• Standard-A plug to Micro-B plug
– Host connects to the EVM acting as a device
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31
USB3 Supported Configurations
6.1
www.ti.com
Option 1
Use a USB3.0 micro-A to standard-B and USB3.0 Hub like the SIIG shown in Figure 21 and Figure 22.
uEVM5432 Side
HUB Side
Figure 21. 3023009-01M USB 3.0 Micro-AB TO Standard-B 1m (3.28’)
Figure 22. Qualtek SIIG JU-H40312-S14Pport USB3.0 Super Speed USB Hub
32
DRA7x EVM CPU Board
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USB3 Supported Configurations
www.ti.com
6.2
Option 2
Use a USB3.0 micro-A to micro-B and USB3.0 Hub like the IOGEAR as shown in Figure 23 and
Figure 24.
uEVM5432 Side
USB3.0 HUB Side
Figure 23. Qualtek 3023007-01M USB3.0 Micro-AB to Micro-B 1m (3.28')
Figure 24. IOGEAR GUH374 4-Port USB3.0 Hub
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33
USB3 Supported Configurations
6.3
www.ti.com
Option 3
Use a USB3.0 micro-B to standard-A. Host PC connects to the EVM acting as a device as shown in
Figure 25.
Host PC Side
uEVM5432 Side
Figure 25. Qualtek 3023005-01M USB3.0 Standard-A to Micro-B 1m (3.28')
7
References
•
•
•
•
•
34
CPU
CPU
CPU
CPU
CPU
EVM
EVM
EVM
EVM
EVM
PCB Rev H (SPRR209)
Schematic Rev H (SPRR210)
BOM Rev H (SPRR211)
Assembly Drawing Rev H (SPRR212)
PCB Drawing Rev H (SPRR213)
DRA7x EVM CPU Board
SPRUI50 – February 2016
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Copyright © 2016, Texas Instruments Incorporated
STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
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Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
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Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
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www.dlp.com
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www.ti.com/consumer-apps
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dsp.ti.com
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www.ti.com/industrial
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interface.ti.com
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www.ti.com/medical
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logic.ti.com
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www.ti.com/space-avionics-defense
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