Texas Instruments | AM35x ARM Microprocessor (Rev. C) | User Guides | Texas Instruments AM35x ARM Microprocessor (Rev. C) User guides

Texas Instruments AM35x ARM Microprocessor (Rev. C) User guides
AM35x ARM Microprocessor
Technical Reference Manual
Literature Number: SPRUGR0C
October 2009 – Revised November 2013
Contents
....................................................................................................................................
Introduction ....................................................................................................................
1.1
Overview ..................................................................................................................
1.2
Environment ..............................................................................................................
1.3
Description ................................................................................................................
1.3.1 MPU Subsystem ................................................................................................
1.3.2 On-Chip Memory ................................................................................................
1.3.3 External Memory Interfaces ...................................................................................
1.3.4 DMA Controllers .................................................................................................
1.3.5 Multimedia Accelerators ........................................................................................
1.3.6 Security (HS Devices Only) ....................................................................................
1.3.7 Comprehensive Power Management .........................................................................
1.3.8 Peripherals .......................................................................................................
1.4
Device Family ............................................................................................................
1.4.1 Device Features .................................................................................................
1.4.2 Device Identification ............................................................................................
1.4.3 General Recommendations Relative to Unavailable Features/Modules .................................
Memory Mapping .............................................................................................................
2.1
Introduction ...............................................................................................................
2.2
Global Memory Space Mapping .......................................................................................
2.3
L3 and L4 Memory Space Mapping ...................................................................................
2.3.1 L3 Memory Space Mapping ...................................................................................
2.3.2 L4 Memory Space Mapping ...................................................................................
2.3.2.1
L4-Core Memory Space Mapping ......................................................................
2.3.2.2
L4-Wakeup Memory Space Mapping ..................................................................
2.3.2.3
L4-Peripheral Memory Space Mapping ................................................................
2.3.2.4
L4-Emulation Memory Space Mapping ................................................................
2.3.3 Register Access Restrictions ..................................................................................
2.4
IPSS Memory Space Mapping .........................................................................................
2.4.1 L3 Interconnect View of the IPSS Memory Space ..........................................................
MPU Subsystem ..............................................................................................................
3.1
MPU Subsystem Overview .............................................................................................
3.1.1 Introduction ......................................................................................................
3.1.2 Features ..........................................................................................................
3.2
MPU Subsystem Integration ............................................................................................
3.2.1 MPU Subsystem Clock and Reset Distribution .............................................................
3.2.1.1
Clock Distribution .........................................................................................
3.2.1.2
Reset Distribution .........................................................................................
3.2.2 ARM Subchip ....................................................................................................
3.2.2.1
ARM Overview ............................................................................................
3.2.2.2
ARM Description ..........................................................................................
3.2.2.2.1 Public ARM Cortex-A8 Instruction, Data, and Private Peripheral Port ........................
3.2.2.2.2 MPU Subsystem Features ..........................................................................
3.2.2.3
Clock, Reset, and Power Management ................................................................
3.2.2.3.1 Clocks ..................................................................................................
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3.3
3.4
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3.2.2.3.2 Reset ...................................................................................................
3.2.2.3.3 Power Management .................................................................................
3.2.3 AXI2OCP and I2Async Bridges ...............................................................................
3.2.3.1
Bridges Overview .........................................................................................
3.2.3.2
AXI2OCP Description ....................................................................................
3.2.3.3
Clocks, Reset, and Power Management ..............................................................
3.2.3.3.1 Clocks ..................................................................................................
3.2.3.3.2 Reset ...................................................................................................
3.2.3.3.3 Power Management .................................................................................
3.2.4 Interrupt Controller ..............................................................................................
3.2.4.1
Clocks ......................................................................................................
3.2.4.2
Reset .......................................................................................................
3.2.4.3
Power Management ......................................................................................
MPU Subsystem Functional Description ..............................................................................
3.3.1 Interrupts .........................................................................................................
3.3.2 Power Management ............................................................................................
3.3.2.1
Power Domains ...........................................................................................
3.3.2.2
Power States ..............................................................................................
3.3.2.3
Power Modes ..............................................................................................
3.3.2.4
Transitions .................................................................................................
MPU Subsystem Basic Programming Model .........................................................................
3.4.1 Clock Control ....................................................................................................
3.4.2 MPU Power Mode Transitions ................................................................................
3.4.2.1
Basic Power-On Reset ...................................................................................
3.4.2.2
MPU to Standby Mode ...................................................................................
3.4.2.3
MPU Out of Standby Mode ..............................................................................
3.4.2.4
MPU Power-On from a Powered-Off State ............................................................
3.4.3 Neon Power Mode Transition .................................................................................
3.4.4 ARM Programming Model .....................................................................................
Power, Reset, and Clock Management
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4.2
4.3
4.4
4.5
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PRCM Introduction to Power Management ...........................................................................
4.1.1 Goal of Power Management ...................................................................................
4.1.2 Architectural Blocks for Power Management ................................................................
4.1.2.1
Clock Domain .............................................................................................
4.1.2.2
Power Domain ............................................................................................
4.1.2.3
Voltage Domain ...........................................................................................
4.1.3 Device Power-Management Architecture ....................................................................
4.1.3.1
Module Interface and Functional Clocks ...............................................................
4.1.3.2
Autoidle Clock Control ...................................................................................
PRCM Overview .........................................................................................................
4.2.1 Introduction ......................................................................................................
4.2.2 PRCM Features .................................................................................................
PRCM Environment ......................................................................................................
4.3.1 External Clock Signals .........................................................................................
4.3.2 External Reset Signals .........................................................................................
PRCM Integration ........................................................................................................
4.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................
4.4.1.1
Resets ......................................................................................................
4.4.1.2
Interrupt Requests ........................................................................................
PRCM Reset Manager Functional Description .......................................................................
4.5.1 Overview .........................................................................................................
4.5.2 General Characteristics of Reset Signals ....................................................................
4.5.2.1
Scope .......................................................................................................
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4.6
4.7
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4.5.2.2
Occurrence ................................................................................................
4.5.2.3
Source Type ...............................................................................................
4.5.3 Reset Sources ...................................................................................................
4.5.3.1
Global Reset Sources ....................................................................................
4.5.3.2
Local Reset Sources .....................................................................................
4.5.4 Reset Distribution ...............................................................................................
4.5.5 Domain Reset Descriptions ....................................................................................
4.5.5.1
MPU Domain ..............................................................................................
4.5.5.2
NEON Domain ............................................................................................
4.5.5.3
CORE Domain ............................................................................................
4.5.5.4
DSS Domain ...............................................................................................
4.5.5.5
USBHOST Domain .......................................................................................
4.5.5.6
SGX Domain ..............................................................................................
4.5.5.7
WKUP Domain ............................................................................................
4.5.5.8
PER Domain ...............................................................................................
4.5.5.9
DPLL Domains ............................................................................................
4.5.5.10 EFUSE Domain ...........................................................................................
4.5.5.11 BANDGAP Logic ..........................................................................................
4.5.5.12 Other Module Resets .....................................................................................
4.5.5.13 External Warm Reset Assertion ........................................................................
4.5.6 Reset Logging ...................................................................................................
4.5.6.1
PRCM Reset Logging Mechanism .....................................................................
4.5.6.2
SCM Reset Logging ......................................................................................
4.5.7 Reset Management Overview .................................................................................
4.5.8 Reset Summary .................................................................................................
4.5.9 Reset Sequences ...............................................................................................
4.5.9.1
Power-Up Sequence .....................................................................................
4.5.9.2
CPEFUSE Reset Sequence .............................................................................
PRCM Power Manager Functional Description ......................................................................
4.6.1 Overview .........................................................................................................
4.6.1.1
Device Partitioning ........................................................................................
4.6.1.2
Domain State Transitions ................................................................................
4.6.1.3
Device Power Modes .....................................................................................
4.6.2 Domain Implementation ........................................................................................
4.6.2.1
Domain Dependencies ...................................................................................
4.6.2.2
Domain Software Controls ...............................................................................
PRCM Clock Manager Functional Description .......................................................................
4.7.1 Overview .........................................................................................................
4.7.1.1
Interface and Functional Clocks ........................................................................
4.7.2 External Clock I/Os .............................................................................................
4.7.2.1
External Clock Inputs .....................................................................................
4.7.2.1.1 32-kHz Always-On Clock ............................................................................
4.7.2.1.2 High-Frequency System Clock .....................................................................
4.7.2.1.3 Alternate Clock .......................................................................................
4.7.2.2
External Clock Outputs ..................................................................................
4.7.2.3
Summary ...................................................................................................
4.7.3 Internal Clock Generation ......................................................................................
4.7.3.1
PRM ........................................................................................................
4.7.3.2
CM ..........................................................................................................
4.7.3.3
DPLLs ......................................................................................................
4.7.3.3.1 DPLL1 (MPU) .........................................................................................
4.7.3.3.2 DPLL3 (CORE) .......................................................................................
4.7.3.3.3 DPLL4 (Peripherals) .................................................................................
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4.8
4.7.3.3.4 DPLL5 (Peripherals) .................................................................................
4.7.3.3.5 DPLL Clock Summary ...............................................................................
4.7.3.4
32-kHz Oscillator ..........................................................................................
4.7.3.5
Summary ...................................................................................................
4.7.4 Clock Distribution ...............................................................................................
4.7.4.1
Domain Clock Distribution ...............................................................................
4.7.4.1.1 MPU Domain ..........................................................................................
4.7.4.1.2 SGX Domain ..........................................................................................
4.7.4.1.3 CORE Domain ........................................................................................
4.7.4.1.4 IPSS Domain .........................................................................................
4.7.4.1.5 EFUSE Domain .......................................................................................
4.7.4.1.6 DSS Domain ..........................................................................................
4.7.4.1.7 USBHOST Domain ...................................................................................
4.7.4.1.8 WKUP Domain .......................................................................................
4.7.4.1.9 PER Domain ..........................................................................................
4.7.4.1.10 DPLL Domains .......................................................................................
4.7.4.2
Clock Distribution Summary .............................................................................
4.7.4.2.1 Domain Source Clocks ..............................................................................
4.7.4.2.2 Peripheral Module Clocks ...........................................................................
4.7.5 External Clock Controls ........................................................................................
4.7.5.1
Clock Request (sys_clkreq) Control ....................................................................
4.7.5.2
System Clock Oscillator Control ........................................................................
4.7.5.3
External Output Clock1 (sys_clkout1) Control ........................................................
4.7.5.4
External Output Clock2 (sys_clkout2) Control ........................................................
4.7.6 DPLL Control ....................................................................................................
4.7.6.1
DPLL Multiplier and Divider Factors ....................................................................
4.7.6.2
DPLL Jitter Correction ....................................................................................
4.7.6.3
DPLL Frequency Ramp-Up Delay ......................................................................
4.7.6.4
DPLL Modes ...............................................................................................
4.7.6.5
DPLL Low-Power Mode ..................................................................................
4.7.6.6
DPLL Clock Path Power Down .........................................................................
4.7.6.7
Latencies ...................................................................................................
4.7.6.8
Recalibration ..............................................................................................
4.7.6.9
DPLL Programming Sequence .........................................................................
4.7.7 Internal Clock Controls .........................................................................................
4.7.7.1
PRM Source-Clock Controls ............................................................................
4.7.7.2
CM Source-Clock Controls ..............................................................................
4.7.7.3
Common Interface Clock Controls ......................................................................
4.7.7.4
DPLL Source-Clock Controls ............................................................................
4.7.7.5
SGX Domain Clock Controls ............................................................................
4.7.7.6
CORE Domain Clock Controls ..........................................................................
4.7.7.7
EFUSE Domain Clock Controls .........................................................................
4.7.7.8
DSS Domain Clock Controls ............................................................................
4.7.7.9
USBHOST Domain Clock Controls .....................................................................
4.7.7.10 WKUP Domain Clock Controls ..........................................................................
4.7.7.11 PER Domain Clock Controls ............................................................................
4.7.7.12 Other Modules Clocks ....................................................................................
4.7.8 Clock Configurations ............................................................................................
4.7.8.1
Processor Clock Configurations ........................................................................
4.7.8.2
Interface and Peripheral Functional Clock Configurations ..........................................
PRCM Idle and Wake-Up Management ..............................................................................
4.8.1 Overview .........................................................................................................
4.8.2 Sleep Transition .................................................................................................
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4.9
4.10
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4.8.3 Wakeup ...........................................................................................................
4.8.4 Device Wake-Up Events .......................................................................................
4.8.5 Sleep and Wake-Up Dependencies ..........................................................................
4.8.5.1
Sleep Dependencies .....................................................................................
4.8.5.2
Wake-Up Dependencies .................................................................................
4.8.6 Other Modules Idle/Wakeup Management ..................................................................
PRCM Interrupts .........................................................................................................
PRCM Voltage Management Functional Description ...............................................................
PRCM Basic Programming Model .....................................................................................
4.11.1 Global Registers ...............................................................................................
4.11.1.1 Revision Information Registers .........................................................................
4.11.1.2 PRCM Configuration Registers .........................................................................
4.11.1.3 Interrupt Configuration Registers .......................................................................
4.11.1.3.1 MPU Interrupt Event Sources ......................................................................
4.11.1.3.2 MPU Interrupt Registers ............................................................................
4.11.1.4 Event Generator Control Registers .....................................................................
4.11.1.5 Output Signal Polarity Control Registers ..............................................................
4.11.1.5.1 CM_POLCTRL (CM Polarity Control Register) ..................................................
4.11.1.5.2 PRM_POLCTRL (PRM Polarity Control Register) ...............................................
4.11.2 Clock Management Registers ................................................................................
4.11.2.1 System Clock Control Registers ........................................................................
4.11.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register) .......................................
4.11.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register) ..............................................
4.11.2.1.3 PRM_CLKSEL (Source-Clock Selection Register) ..............................................
4.11.2.2 External Clock Output Control Registers ..............................................................
4.11.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) ............................................
4.11.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register) .............................................
4.11.2.3 DPLL Clock Control Registers ..........................................................................
4.11.2.3.1 CM_CLKSELn_PLL_<processor_name> (Processor DPLL Clock Selection Register) ....
4.11.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register) ..........................................
4.11.2.3.3 CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register) ..........
4.11.2.3.4 CM_CLKEN_PLL (DPLL Enable Register) .......................................................
4.11.2.3.5 CM_AUTOIDLE_PLL_<processor_name> (Processor DPLL Autoidle Register) ............
4.11.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register) .................................................
4.11.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register) ..............................................
4.11.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register) ....................................
4.11.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register) .........................
4.11.2.3.10 CM_IDLEST_PLL_<processor_name> (Processor DPLL Idle-Status Register) ...........
4.11.2.4 Power-Domain Clock Control Registers ...............................................................
4.11.2.4.1 CM_CLKSEL_<domain_name> (Clock Select Register) .......................................
4.11.2.4.2 CM_FCLKEN_<domain_name> (Functional Clock Enable Register) .........................
4.11.2.4.3 CM_ICLKEN_<domain_name> (Interface Clock Enable Register) ............................
4.11.2.4.4 CM_AUTOIDLE_<domain_name> (Autoidle Register) .........................................
4.11.2.4.5 CM_IDLEST_<domain_name> (Idle-Status Register) ..........................................
4.11.2.4.6 CM_CLKSTCTRL_<domain_name>(Clock State Control Register) ..........................
4.11.2.4.7 CM_CLKSTST_<domain_name> (Clock State Status Register) ..............................
4.11.2.4.8 CM_SLEEPDEP_<domain_name> (Sleep Dependency Control Register) ..................
4.11.2.5 Domain Wake-Up Control Registers ...................................................................
4.11.2.5.1 PM_WKEN_<domain_name> (Wake-Up Enable Register) ....................................
4.11.2.5.2 PM_WKST_<domain_name> (Wake-Up Status Register) .....................................
4.11.2.5.3 PM_WKDEP_<domain_name> (Wake-Up Dependency Register) ............................
4.11.2.5.4 PM_<processor_name>GRPSEL_<domain_name> (Processor Group Selection Register)
..........................................................................................................
................................................................................
4.11.3 Reset Management Registers
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4.12
4.11.3.1 Reset Control ..............................................................................................
4.11.3.1.1 PRM_RSTTIME (Reset Time Register) ...........................................................
4.11.3.1.2 RM_RSTCTRL_<domain_name> (Reset Control Register) ....................................
4.11.3.1.3 RM_RSTST_<domain_name> (Reset Status Register) ........................................
4.11.4 Power Management Registers ...............................................................................
4.11.4.1 PM_PWSTST_<domain_name> (Power State Status Register) ...................................
4.11.5 Generic Programming Examples ............................................................................
4.11.5.1 Clock Control ..............................................................................................
4.11.5.1.1 Enabling and Disabling the Functional Clocks ...................................................
4.11.5.1.2 Enabling and Disabling the Interface Clocks .....................................................
4.11.5.1.3 Enabling and Disabling the INACTIVE State .....................................................
4.11.5.1.4 Processor Clock Control ............................................................................
4.11.5.2 Reset Management .......................................................................................
4.11.5.3 Wake-Up Control .........................................................................................
4.11.5.4 Event Generator Programming Examples .............................................................
PRCM Registers .........................................................................................................
4.12.1 CM Module Registers .........................................................................................
4.12.1.1 CM Module Registers Mapping Summary .............................................................
4.12.1.2 OCP_System_Reg_CM Register Descriptions .......................................................
4.12.1.2.1 CM_REVISION .......................................................................................
4.12.1.2.2 CM_SYSCONFIG ....................................................................................
4.12.1.3 MPU_CM Register Descriptions ........................................................................
4.12.1.3.1 CM_CLKEN_PLL_MPU .............................................................................
4.12.1.3.2 CM_IDLEST_MPU ...................................................................................
4.12.1.3.3 CM_IDLEST_PLL_MPU .............................................................................
4.12.1.3.4 CM_AUTOIDLE_PLL_MPU .........................................................................
4.12.1.3.5 CM_CLKSEL1_PLL_MPU ..........................................................................
4.12.1.3.6 CM_CLKSEL2_PLL_MPU ..........................................................................
4.12.1.3.7 CM_CLKSTCTRL_MPU .............................................................................
4.12.1.3.8 CM_CLKSTST_MPU ................................................................................
4.12.1.4 CORE_CM Register Descriptions ......................................................................
4.12.1.4.1 CM_FCLKEN1_CORE ..............................................................................
4.12.1.4.2 CM_FCLKEN3_CORE ..............................................................................
4.12.1.4.3 CM_ICLKEN1_CORE ...............................................................................
4.12.1.4.4 CM_ICLKEN2_CORE ...............................................................................
4.12.1.4.5 CM_ICLKEN3_CORE ...............................................................................
4.12.1.4.6 CM_IDLEST1_CORE ................................................................................
4.12.1.4.7 CM_IDLEST2_CORE ................................................................................
4.12.1.4.8 CM_IDLEST3_CORE ................................................................................
4.12.1.4.9 CM_AUTOIDLE1_CORE ............................................................................
4.12.1.4.10 CM_AUTOIDLE2_CORE ..........................................................................
4.12.1.4.11 CM_AUTOIDLE3_CORE ..........................................................................
4.12.1.4.12 CM_CLKSEL_CORE ...............................................................................
4.12.1.4.13 CM_CLKSTCTRL_CORE .........................................................................
4.12.1.4.14 CM_CLKSTST_CORE .............................................................................
4.12.1.5 SGX_CM Register Descriptions ........................................................................
4.12.1.5.1 CM_FCLKEN_SGX ..................................................................................
4.12.1.5.2 CM_ICLKEN_SGX ...................................................................................
4.12.1.5.3 CM_IDLEST_SGX ...................................................................................
4.12.1.5.4 CM_CLKSEL_SGX ..................................................................................
4.12.1.5.5 CM_SLEEPDEP_SGX ..............................................................................
4.12.1.5.6 CM_CLKSTCTRL_SGX .............................................................................
4.12.1.5.7 CM_CLKSTST_SGX ................................................................................
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4.12.1.6 WKUP_CM Register Descriptions ......................................................................
4.12.1.6.1 CM_FCLKEN_WKUP ................................................................................
4.12.1.6.2 CM_ICLKEN_WKUP ................................................................................
4.12.1.6.3 CM_IDLEST_WKUP .................................................................................
4.12.1.6.4 CM_AUTOIDLE_WKUP .............................................................................
4.12.1.6.5 CM_CLKSEL_WKUP ................................................................................
4.12.1.7 Clock_Control_Reg_CM Register Descriptions .......................................................
4.12.1.7.1 CM_CLKEN_PLL ....................................................................................
4.12.1.7.2 CM_CLKEN2_PLL ...................................................................................
4.12.1.7.3 CM_IDLEST_CKGEN ...............................................................................
4.12.1.7.4 CM_IDLEST2_CKGEN ..............................................................................
4.12.1.7.5 CM_AUTOIDLE_PLL ................................................................................
4.12.1.7.6 CM_AUTOIDLE2_PLL ...............................................................................
4.12.1.7.7 CM_CLKSEL1_PLL ..................................................................................
4.12.1.7.8 CM_CLKSEL2_PLL ..................................................................................
4.12.1.7.9 CM_CLKSEL3_PLL ..................................................................................
4.12.1.7.10 CM_CLKSEL4_PLL ................................................................................
4.12.1.7.11 CM_CLKSEL5_PLL ................................................................................
4.12.1.7.12 CM_CLKOUT_CTRL ...............................................................................
4.12.1.8 DSS_CM Register Descriptions ........................................................................
4.12.1.8.1 CM_FCLKEN_DSS ..................................................................................
4.12.1.8.2 CM_ICLKEN_DSS ...................................................................................
4.12.1.8.3 CM_IDLEST_DSS ...................................................................................
4.12.1.8.4 CM_AUTOIDLE_DSS ...............................................................................
4.12.1.8.5 CM_CLKSEL_DSS ..................................................................................
4.12.1.8.6 CM_SLEEPDEP_DSS ...............................................................................
4.12.1.8.7 CM_CLKSTCTRL_DSS .............................................................................
4.12.1.8.8 CM_CLKSTST_DSS .................................................................................
4.12.1.9 PER_CM Register Descriptions ........................................................................
4.12.1.9.1 CM_FCLKEN_PER ..................................................................................
4.12.1.9.2 CM_ICLKEN_PER ...................................................................................
4.12.1.9.3 CM_IDLEST_PER ...................................................................................
4.12.1.9.4 CM_AUTOIDLE_PER ...............................................................................
4.12.1.9.5 CM_CLKSEL_PER ..................................................................................
4.12.1.9.6 CM_SLEEPDEP_PER ...............................................................................
4.12.1.9.7 CM_CLKSTCTRL_PER .............................................................................
4.12.1.9.8 CM_CLKSTST_PER .................................................................................
4.12.1.10 EMU_CM Register Descriptions .......................................................................
4.12.1.10.1 CM_CLKSEL1_EMU ...............................................................................
4.12.1.10.2 CM_CLKSTCTRL_EMU ...........................................................................
4.12.1.10.3 CM_CLKSTST_EMU ...............................................................................
4.12.1.10.4 CM_CLKSEL2_EMU ...............................................................................
4.12.1.10.5 CM_CLKSEL3_EMU ...............................................................................
4.12.1.11 Global_Reg_CM Register Descriptions ..............................................................
4.12.1.11.1 CM_POLCTRL ......................................................................................
4.12.1.12 NEON_CM Register Descriptions .....................................................................
4.12.1.12.1 CM_IDLEST_NEON ................................................................................
4.12.1.12.2 CM_CLKSTCTRL_NEON .........................................................................
4.12.1.13 USBHOST_CM Register Descriptions ................................................................
4.12.1.13.1 CM_FCLKEN_USBHOST .........................................................................
4.12.1.13.2 CM_ICLKEN_USBHOST ..........................................................................
4.12.1.13.3 CM_IDLEST_USBHOST ..........................................................................
4.12.1.13.4 CM_AUTOIDLE_USBHOST ......................................................................
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4.12.1.13.5 CM_SLEEPDEP_USBHOST ......................................................................
4.12.1.13.6 CM_CLKSTCTRL_USBHOST ....................................................................
4.12.1.13.7 CM_CLKSTST_USBHOST ........................................................................
4.12.2 PRM Module Registers ........................................................................................
4.12.2.1 PRM Module Registers Mapping Summary ...........................................................
4.12.2.2 OCP_System_Reg_PRM Register Descriptions .....................................................
4.12.2.2.1 PRM_REVISION .....................................................................................
4.12.2.2.2 PRM_SYSCONFIG ..................................................................................
4.12.2.2.3 PRM_IRQSTATUS_MPU ...........................................................................
4.12.2.2.4 PRM_IRQENABLE_MPU ...........................................................................
4.12.2.3 MPU_PRM Register Descriptions ......................................................................
4.12.2.3.1 RM_RSTST_MPU ...................................................................................
4.12.2.3.2 PM_WKDEP_MPU ...................................................................................
4.12.2.3.3 PM_EVGENCTRL_MPU ............................................................................
4.12.2.3.4 PM_EVGENONTIM_MPU ..........................................................................
4.12.2.3.5 PM_EVGENOFFTIM_MPU .........................................................................
4.12.2.3.6 PM_PWSTCTRL_MPU ..............................................................................
4.12.2.3.7 PM_PWSTST_MPU .................................................................................
4.12.2.3.8 PM_PREPWSTST_MPU ............................................................................
4.12.2.4 CORE_PRM Register Descriptions ....................................................................
4.12.2.4.1 RM_RSTST_CORE ..................................................................................
4.12.2.4.2 PM_WKEN1_CORE .................................................................................
4.12.2.4.3 PM_MPUGRPSEL1_CORE ........................................................................
4.12.2.4.4 PM_WKST1_CORE .................................................................................
4.12.2.4.5 PM_WKST3_CORE .................................................................................
4.12.2.4.6 PM_PWSTCTRL_CORE ............................................................................
4.12.2.4.7 PM_PWSTST_CORE ...............................................................................
4.12.2.4.8 PM_PREPWSTST_CORE ..........................................................................
4.12.2.4.9 PM_WKEN3_CORE .................................................................................
4.12.2.4.10 PM_MPUGRPSEL3_CORE .......................................................................
4.12.2.5 SGX_PRM Register Descriptions ......................................................................
4.12.2.5.1 RM_RSTST_SGX ....................................................................................
4.12.2.5.2 PM_WKDEP_SGX ...................................................................................
4.12.2.5.3 PM_PWSTCTRL_SGX ..............................................................................
4.12.2.5.4 PM_PWSTST_SGX ..................................................................................
4.12.2.5.5 PM_PREPWSTCTRL_SGX ........................................................................
4.12.2.6 WKUP_PRM Register Descriptions ....................................................................
4.12.2.6.1 PM_WKEN_WKUP ..................................................................................
4.12.2.6.2 PM_MPUGRPSEL_WKUP .........................................................................
4.12.2.6.3 PM_WKST_WKUP ...................................................................................
4.12.2.7 Clock_Control_Reg_PRM Register Descriptions .....................................................
4.12.2.7.1 PRM_CLKSEL ........................................................................................
4.12.2.7.2 PRM_CLKOUT_CTRL ...............................................................................
4.12.2.8 DSS_PRM Register Descriptions .......................................................................
4.12.2.8.1 RM_RSTST_DSS ....................................................................................
4.12.2.8.2 PM_WKEN_DSS .....................................................................................
4.12.2.8.3 PM_WKDEP_DSS ...................................................................................
4.12.2.8.4 PM_PWSTCTRL_DSS ..............................................................................
4.12.2.8.5 PM_PWSTST_DSS ..................................................................................
4.12.2.8.6 PM_PREPWSTST_DSS ............................................................................
4.12.2.9 PER_PRM Register Descriptions .......................................................................
4.12.2.9.1 RM_RSTST_PER ....................................................................................
4.12.2.9.2 PM_WKEN_PER .....................................................................................
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Interconnect
5.1
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5.3
5.4
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4.12.2.9.3 PM_MPUGRPSEL_PER ............................................................................
4.12.2.9.4 PM_WKST_PER .....................................................................................
4.12.2.9.5 PM_WKDEP_PER ...................................................................................
4.12.2.9.6 PM_PWSTCTRL_PER ..............................................................................
4.12.2.9.7 PM_PWSTST_PER ..................................................................................
4.12.2.9.8 PM_PREPWSTST_PER ............................................................................
4.12.2.10 EMU_PRM Register Descriptions .....................................................................
4.12.2.10.1 RM_RSTST_EMU ..................................................................................
4.12.2.11 Global_Reg_PRM Register Descriptions .............................................................
4.12.2.11.1 PRM_RSTCTRL ....................................................................................
4.12.2.11.2 PRM_RSTTIME .....................................................................................
4.12.2.11.3 PRM_RSTST ........................................................................................
4.12.2.11.4 PRM_CLKSRC_CTRL .............................................................................
4.12.2.11.5 PRM_OBS ...........................................................................................
4.12.2.11.6 PRM_CLKSETUP ..................................................................................
4.12.2.11.7 PRM_POLCTRL ....................................................................................
4.12.2.12 NEON_PRM Register Descriptions ...................................................................
4.12.2.12.1 RM_RSTST_NEON ................................................................................
4.12.2.12.2 PM_WKDEP_NEON ...............................................................................
4.12.2.12.3 PM_PWSTCTRL_NEON ..........................................................................
4.12.2.12.4 PM_PWSTST_NEON ..............................................................................
4.12.2.12.5 PM_PREPWSTST_NEON ........................................................................
4.12.2.13 USBHOST_PRM Register Descriptions ..............................................................
4.12.2.13.1 RM_RSTST_USBHOST ...........................................................................
4.12.2.13.2 PM_WKEN_USBHOST ............................................................................
4.12.2.13.3 PM_MPUGRPSEL_USBHOST ...................................................................
4.12.2.13.4 PM_WKST_USBHOST ............................................................................
4.12.2.13.5 PM_WKDEP_USBHOST ..........................................................................
4.12.2.13.6 PM_PWSTCTRL_USBHOST .....................................................................
4.12.2.13.7 PM_PWSTST_USBHOST .........................................................................
4.12.2.13.8 PM_PREPWSTST_USBHOST ...................................................................
Revision History ..........................................................................................................
.................................................................................................................... 489
Interconnect Overview ...................................................................................................
5.1.1 Terminology ......................................................................................................
5.1.2 Architecture Overview ..........................................................................................
5.1.3 Module Distribution .............................................................................................
5.1.3.1
L3 Interconnect Agents ..................................................................................
5.1.3.2
L4-Core Agents ...........................................................................................
5.1.3.3
L4-Per Agents .............................................................................................
5.1.3.4
L4-Emu Agents ............................................................................................
5.1.3.5
L4-Wakeup Agents .......................................................................................
5.1.4 Connectivity Matrix ..............................................................................................
L3 Interconnect ...........................................................................................................
5.2.1 Overview .........................................................................................................
L3 Interconnect Integration .............................................................................................
5.3.1 Clocking, Reset, and Power-Management Scheme ........................................................
5.3.1.1
Clocks ......................................................................................................
5.3.1.2
Resets ......................................................................................................
5.3.1.3
Power Management ......................................................................................
5.3.2 Hardware Requests .............................................................................................
5.3.2.1
Interrupt Requests ........................................................................................
L3 Interconnect Functional Description ...............................................................................
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5.5
5.6
5.4.1 Initiator Identification ............................................................................................
5.4.2 Register Target ..................................................................................................
5.4.3 L3 Security and Firewalls ......................................................................................
5.4.3.1
Protection Region .........................................................................................
5.4.3.1.1 Default Region/Region0 .............................................................................
5.4.3.1.2 Normal Regions ......................................................................................
5.4.3.2
Priority Level Overview ..................................................................................
5.4.3.3
Read and Write Permission .............................................................................
5.4.3.4
REQ_INFO_PERMISSION Configuration .............................................................
5.4.3.5
L3 Firewall Registers Overview .........................................................................
5.4.3.6
L3 Firewall Error-Logging Registers ....................................................................
5.4.3.7
L3 Firewall and System Control Module ...............................................................
5.4.4 Error Handling ...................................................................................................
5.4.4.1
Error Detection and Logging ............................................................................
5.4.4.2
Time-Out ...................................................................................................
5.4.4.3
Error Steering .............................................................................................
5.4.4.4
Global Error Reporting ...................................................................................
L3 Interconnect Basic Programming Model ..........................................................................
5.5.1 General Recommendation .....................................................................................
5.5.2 Initialization ......................................................................................................
5.5.3 Error Analysis ....................................................................................................
5.5.3.1
Time-out Handling ........................................................................................
5.5.3.2
Acknowledging Errors ....................................................................................
L3 Interconnect Registers ...............................................................................................
5.6.1 L3 Initiator Agent (L3 IA) Register Mapping Summary .....................................................
5.6.2 L3 Initiator Agent (L3 IA) Register Descriptions ............................................................
5.6.2.1
L3_IA_AGENT_CONTROL ..............................................................................
5.6.2.2
L3_IA_AGENT_STATUS ................................................................................
5.6.2.3
L3_IA_ERROR_LOG .....................................................................................
5.6.2.4
L3_IA_ERROR_LOG_ADDR ............................................................................
5.6.3 L3 Target Agent (L3 TA) Register Mapping Summary .....................................................
5.6.4 L3 Target Agent (L3 TA) Register Descriptions .............................................................
5.6.4.1
L3_TA_AGENT_CONTROL .............................................................................
5.6.4.2
L3_TA_AGENT_STATUS ...............................................................................
5.6.4.3
L3_TA_ERROR_LOG ....................................................................................
5.6.4.4
L3_TA_ERROR_LOG_ADDR ...........................................................................
5.6.5 Register Target (RT) Register Mapping Summary .........................................................
5.6.6 Register Target (RT) Register Descriptions .................................................................
5.6.6.1
L3_RT_NETWORK .......................................................................................
5.6.6.2
L3_RT_INITID_READBACK ............................................................................
5.6.6.3
L3_RT_NETWORK_CONTROL ........................................................................
5.6.7 Protection Mechanism (PM) Register Mapping Summary .................................................
5.6.8 Protection Mechanism (PM) Register Descriptions .........................................................
5.6.8.1
L3_PM_ERROR_LOG ...................................................................................
5.6.8.2
L3_PM_CONTROL .......................................................................................
5.6.8.3
L3_PM_ERROR_CLEAR_SINGLE ....................................................................
5.6.8.4
L3_PM_ERROR_CLEAR_MULTI ......................................................................
5.6.8.5
L3_PM_REQ_INFO_PERMISSION_i ..................................................................
5.6.8.6
L3_PM_READ_PERMISSION_i ........................................................................
5.6.8.7
L3_PM_WRITE_PERMISSION_i .......................................................................
5.6.8.8
Bit Availability and Initialization Values for L3_PM_READ_PERMISSION_i and
L3_PM_WRITE_PERMISSION_i .......................................................................
5.6.8.9
L3_PM_ADDR_MATCH_k ...............................................................................
5.6.9 Sideband Interconnect (SI) Register Mapping Summary ..................................................
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5.8
5.9
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5.6.10 Sideband Interconnect (SI) Register Descriptions .........................................................
5.6.10.1 L3_SI_CONTROL ........................................................................................
5.6.10.2 L3_SI_FLAG_STATUS_0 ...............................................................................
5.6.10.3 L3_SI_FLAG_STATUS_1 ...............................................................................
L4 Interconnects .........................................................................................................
5.7.1 Overview .........................................................................................................
5.7.1.1
L4-Core Interconnect .....................................................................................
5.7.1.2
L4-Per Interconnect ......................................................................................
5.7.1.3
L4-Emu Interconnect .....................................................................................
5.7.1.4
L4-Wakeup Interconnect .................................................................................
L4 Interconnects Integration ............................................................................................
5.8.1 Clocking, Reset, and Power-Management Scheme ........................................................
5.8.1.1
Clocks ......................................................................................................
5.8.1.2
Resets ......................................................................................................
5.8.1.2.1 Hardware Reset ......................................................................................
5.8.1.2.2 Software Reset .......................................................................................
5.8.1.3
Power Domain ............................................................................................
5.8.1.4
Power Management ......................................................................................
5.8.1.4.1 Module Power-Saving ...............................................................................
5.8.1.4.2 System Power Management and Wakeup ........................................................
L4 Interconnects Functional Description ..............................................................................
5.9.1 L4-Interconnects Initiator Identification .......................................................................
5.9.2 Endianness Management ......................................................................................
5.9.3 L4 Security and Firewalls ......................................................................................
5.9.3.1
Protection Mechanism ...................................................................................
5.9.3.2
Protection Group ..........................................................................................
5.9.3.3
Segments and Regions ..................................................................................
5.9.3.4
L4 Firewall Address and Protection Registers Setting ...............................................
5.9.4 Error Handling ...................................................................................................
5.9.4.1
Overview ...................................................................................................
5.9.4.2
Error Logging ..............................................................................................
5.9.4.2.1 No Target Core Found/Address Hole ..............................................................
5.9.4.2.2 Protection Violation ..................................................................................
5.9.4.2.3 Time-Out ..............................................................................................
5.9.4.3
TA Software Reset .......................................................................................
5.9.4.4
Error Reporting ............................................................................................
L4 Interconnects Registers .............................................................................................
5.10.1 L4 Initiator Agent (L4 IA) Register Mapping Summary ....................................................
5.10.2 L4 Initiator Agent (L4 IA) Register Descriptions ...........................................................
5.10.2.1 L4_IA_AGENT_CONTROL_L ...........................................................................
5.10.2.2 L4_IA_AGENT_STATUS_L .............................................................................
5.10.2.3 L4_IA_ERROR_LOG_L ..................................................................................
5.10.3 L4 Target Agent (L4 TA) Register Mapping Summary ....................................................
5.10.4 L4 Target Agent (L4 TA) Register Descriptions ............................................................
5.10.4.1 L4_TA_AGENT_CONTROL_L ..........................................................................
5.10.4.2 L4_TA_AGENT_CONTROL_H .........................................................................
5.10.4.3 L4_TA_AGENT_STATUS_L ............................................................................
5.10.5 L4 Link Register Agent (LA) Register Mapping Summary ................................................
5.10.6 L4 Link Register Agent (LA) Register Descriptions ........................................................
5.10.6.1 L4_LA_NETWORK_H ....................................................................................
5.10.6.2 L4_LA_INITIATOR_INFO_L .............................................................................
5.10.6.3 L4_LA_INITIATOR_INFO_H ............................................................................
5.10.6.4 L4_LA_NETWORK_CONTROL_L .....................................................................
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5.10.6.5
5.10.7 L4
5.10.7.1
5.10.8 L4
5.10.8.1
5.10.8.2
5.10.8.3
5.10.8.4
5.10.8.5
5.10.8.6
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L4_LA_NETWORK_CONTROL_H .....................................................................
Address Protection (AP) Register Mapping Summary ................................................
Reset Values ..............................................................................................
Address Protection (AP) Register Descriptions ........................................................
L4_AP_SEGMENT_i_L ..................................................................................
L4_AP_SEGMENT_i_H ..................................................................................
L4_AP_PROT_GROUP_MEMBERS_k_L .............................................................
L4_AP_PROT_GROUP_ROLES_k_L .................................................................
L4_AP_REGION_l_L .....................................................................................
L4_AP_REGION_l_H ....................................................................................
System Control Module
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6.4
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System Control Module Overview .....................................................................................
System Control Module Environment .................................................................................
6.2.1 Functional Interfaces ...........................................................................................
6.2.1.1
Basic System Control Module Pins .....................................................................
6.2.1.2
System Control Module Interface Description ........................................................
System Control Module Integration ....................................................................................
6.3.1 Clocking, Reset, and Power-Management Scheme ........................................................
6.3.1.1
Clock .......................................................................................................
6.3.1.2
Resets ......................................................................................................
6.3.1.3
Power Management ......................................................................................
6.3.1.3.1 System Power Management ........................................................................
6.3.1.3.2 Module Power Saving ...............................................................................
6.3.2 Hardware Requests .............................................................................................
System Control Module Functional Description ......................................................................
6.4.1 Block Diagram ...................................................................................................
6.4.2 System Control Module Initialization .........................................................................
6.4.3 Wake-Up Control Module ......................................................................................
6.4.4 Pad Functional Multiplexing and Configuration .............................................................
6.4.4.1
Mode Selection ............................................................................................
6.4.4.2
Pull Selection ..............................................................................................
6.4.4.3
Pad Multiplexing Register Fields .......................................................................
6.4.5 Functional Register Description ...............................................................................
6.4.5.1
Static Device Configuration Registers .................................................................
6.4.5.2
MPU MSuspend Configuration Registers .............................................................
6.4.5.3
Device Status Registers .................................................................................
6.4.6 Debug and Observability .......................................................................................
6.4.6.1
Description .................................................................................................
6.4.6.2
Observability Tables ......................................................................................
6.4.7 Electromagnetic Interference Reduction for Clocking Generation (Spreading) .........................
6.4.7.1
Overview ...................................................................................................
6.4.7.2
Integration .................................................................................................
6.4.7.2.1 Clocking, Reset, and Power Management Scheme .............................................
6.4.7.3
Functional Description ...................................................................................
6.4.7.3.1 Spreading Generation Block ........................................................................
6.4.7.3.2 Spread Spectrum Clocking (SSC) .................................................................
6.4.7.3.3 Frequency Limitations ...............................................................................
6.4.7.4
Basic Programming Model ..............................................................................
6.4.7.4.1 Spread Spectrum Clocking Configuration .........................................................
System Control Module Programming Model ........................................................................
6.5.1 Feature Settings .................................................................................................
6.5.1.1
Video Driver ...............................................................................................
6.5.1.2
McBSP1 Internal Clock ..................................................................................
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14
6.5.1.3
McBSP2 Internal Clock ..................................................................................
6.5.1.4
McBSP3 Internal Clock ..................................................................................
6.5.1.5
McBSP4 Internal Clock ..................................................................................
6.5.1.6
McBSP5 Internal Clock ..................................................................................
6.5.1.7
MMC/SD/SDIO2 Module Input Clock Selection ......................................................
6.5.1.8
Setting Sensitivity on SYS_NDMAREQ[3:0] Input Pins .............................................
6.5.1.9
Force MPU Writes to Be Nonposted ...................................................................
6.5.2 Pad Configuration Programming Points ......................................................................
6.5.3 I/O Power Optimization Guidelines ...........................................................................
System Control Module Registers .....................................................................................
6.6.1 System Control Module Register Mapping Summary ......................................................
6.6.2 INTERFACE Register Descriptions ...........................................................................
6.6.2.1
CONTROL_REVISION ...................................................................................
6.6.2.2
Control System Configuration Register (CONTROL_SYSCONFIG) ...............................
6.6.3 PADCONFS Register Description ............................................................................
6.6.4 GENERAL Register Descriptions .............................................................................
6.6.4.1
CONTROL_PADCONF_OFF ...........................................................................
6.6.4.2
CONTROL_DEVCONF0 .................................................................................
6.6.4.3
CONTROL_MEM_DFTRW0 ............................................................................
6.6.4.4
CONTROL_MEM_DFTRW1 ............................................................................
6.6.4.5
CONTROL_MSUSPENDMUX_0 .......................................................................
6.6.4.6
CONTROL_MSUSPENDMUX_1 .......................................................................
6.6.4.7
CONTROL_MSUSPENDMUX_2 .......................................................................
6.6.4.8
CONTROL_MSUSPENDMUX_4 .......................................................................
6.6.4.9
CONTROL_MSUSPENDMUX_5 .......................................................................
6.6.4.10 CONTROL_MSUSPENDMUX_6 .......................................................................
6.6.4.11 CONTROL_DEVCONF1 .................................................................................
6.6.4.12 CONTROL_SEC_STATUS ..............................................................................
6.6.4.13 CONTROL_SEC_ERR_STATUS .......................................................................
6.6.4.14 CONTROL_SEC_ERR_STATUS_DEBUG ...........................................................
6.6.4.15 CONTROL_STATUS .....................................................................................
6.6.4.16 CONTROL_RPUB_KEY_H_0 ...........................................................................
6.6.4.17 CONTROL_RPUB_KEY_H_1 ...........................................................................
6.6.4.18 CONTROL_RPUB_KEY_H_2 ...........................................................................
6.6.4.19 CONTROL_RPUB_KEY_H_3 ...........................................................................
6.6.4.20 CONTROL_RPUB_KEY_H_4 ...........................................................................
6.6.4.21 CONTROL_USB_CONF_0 ..............................................................................
6.6.4.22 CONTROL_USB_CONF_1 ..............................................................................
6.6.4.23 CONTROL_FUSE_EMAC_LSB ........................................................................
6.6.4.24 CONTROL_FUSE_EMAC_MSB ........................................................................
6.6.4.25 CONTROL_FUSE_SR ...................................................................................
6.6.4.26 CONTROL_CEK_0 .......................................................................................
6.6.4.27 CONTROL_CEK_1 .......................................................................................
6.6.4.28 CONTROL_CEK_2 .......................................................................................
6.6.4.29 CONTROL_CEK_3 .......................................................................................
6.6.4.30 CONTROL_MSV_0 .......................................................................................
6.6.4.31 CONTROL_CEK_BCH_0 ................................................................................
6.6.4.32 CONTROL_CEK_BCH_1 ................................................................................
6.6.4.33 CONTROL_CEK_BCH_2 ................................................................................
6.6.4.34 CONTROL_CEK_BCH_3 ................................................................................
6.6.4.35 CONTROL_CEK_BCH_4 ................................................................................
6.6.4.36 CONTROL_MSV_BCH_0 ...............................................................................
6.6.4.37 CONTROL_MSV_BCH_1 ...............................................................................
Contents
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SPRUGR0C – October 2009 – Revised November 2013
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6.7
7
DMA
7.1
7.2
7.3
6.6.4.38 CONTROL_SWRV_0 ....................................................................................
6.6.4.39 CONTROL_SWRV_1 ....................................................................................
6.6.4.40 CONTROL_SWRV_2 ....................................................................................
6.6.4.41 CONTROL_SWRV_3 ....................................................................................
6.6.4.42 CONTROL_SWRV_4 ....................................................................................
6.6.4.43 CONTROL_DEBOBS_0 .................................................................................
6.6.4.44 CONTROL_DEBOBS_1 .................................................................................
6.6.4.45 CONTROL_DEBOBS_2 .................................................................................
6.6.4.46 CONTROL_DEBOBS_3 .................................................................................
6.6.4.47 CONTROL_DEBOBS_4 .................................................................................
6.6.4.48 CONTROL_DEBOBS_5 .................................................................................
6.6.4.49 CONTROL_DEBOBS_6 .................................................................................
6.6.4.50 CONTROL_DEBOBS_7 .................................................................................
6.6.4.51 CONTROL_DEBOBS_8 .................................................................................
6.6.4.52 CONTROL_WKUP_CTRL ...............................................................................
6.6.4.53 CONTROL_DSS_DPLL_SPREADING ................................................................
6.6.4.54 CONTROL_CORE_DPLL_SPREADING ..............................................................
6.6.4.55 CONTROL_PER_DPLL_SPREADING ................................................................
6.6.4.56 CONTROL_USBHOST_DPLL_SPREADING .........................................................
6.6.4.57 CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH .................................................
6.6.4.58 CONTROL_DPF_OCM_RAM_FW_REQINFO .......................................................
6.6.4.59 CONTROL_DPF_OCM_RAM_FW_WR ...............................................................
6.6.4.60 CONTROL_DPF_REGION4_GPMC_FW_ADDR_MATCH .........................................
6.6.4.61 CONTROL_DPF_REGION4_GPMC_FW_REQINFO ...............................................
6.6.4.62 CONTROL_DPF_REGION4_GPMC_FW_WR .......................................................
6.6.4.63 CONTROL_APE_FW_DEFAULT_SECURE_LOCK .................................................
6.6.4.64 CONTROL_OCMROM_SECURE_DEBUG ...........................................................
6.6.4.65 CONTROL_EXT_SEC_CONTROL ....................................................................
6.6.4.66 CONTROL_DEVCONF2 .................................................................................
6.6.4.67 CONTROL_DEVCONF3 .................................................................................
6.6.4.68 CONTROL_CBA_PRIORITY ............................................................................
6.6.4.69 CONTROL_LVL_INTR_CLEAR ........................................................................
6.6.4.70 CONTROL_IP_SW_RESET .............................................................................
6.6.4.71 CONTROL_IPSS_CLK_CTRL ..........................................................................
6.6.4.72 CONTROL_IDCODE .....................................................................................
6.6.5 MEM_WKUP Register Descriptions ..........................................................................
6.6.6 PADCONFS_WKUP Register Description ...................................................................
6.6.7 GENERAL_WKUP Register Descriptions ...................................................................
6.6.7.1
CONTROL_SEC_TAP ...................................................................................
6.6.7.2
CONTROL_SEC_EMU ..................................................................................
6.6.7.3
CONTROL_WKUP_DEBOBS_0 ........................................................................
6.6.7.4
CONTROL_WKUP_DEBOBS_1 ........................................................................
6.6.7.5
CONTROL_WKUP_DEBOBS_2 ........................................................................
6.6.7.6
CONTROL_WKUP_DEBOBS_3 ........................................................................
6.6.7.7
CONTROL_WKUP_DEBOBS_4 ........................................................................
6.6.7.8
CONTROL_SEC_DAP ...................................................................................
Revision History ..........................................................................................................
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............................................................................................................................... 792
SDMA Module Overview ................................................................................................ 793
SDMA Controller Environment ......................................................................................... 795
7.2.1 Environment Overview ......................................................................................... 795
7.2.2 SDMA Request Scheme ....................................................................................... 795
SDMA Module Integration .............................................................................................. 796
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Contents
15
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7.4
7.5
7.6
16
7.3.1 External SDMA Request Interface Description .............................................................
7.3.2 Clocking, Reset, and Power-Management Scheme ........................................................
7.3.2.1
Clocking ....................................................................................................
7.3.2.2
Resets ......................................................................................................
7.3.2.2.1 Asynchronous Hardware Reset ....................................................................
7.3.2.2.2 Software Reset Through the Configuration Port .................................................
7.3.2.3
Power Domain ............................................................................................
7.3.3 Hardware Requests .............................................................................................
7.3.3.1
Interrupts to the MPU Subsystem ......................................................................
7.3.3.2
DMA Requests to the SDMA Controller ...............................................................
SDMA Functional Description ..........................................................................................
7.4.1 Logical Channel Transfer Overview ..........................................................................
7.4.2 FIFO Queue Memory Pool .....................................................................................
7.4.3 Addressing Modes ..............................................................................................
7.4.4 Packed Accesses ...............................................................................................
7.4.5 Burst Transactions ..............................................................................................
7.4.6 Endianism Conversion .........................................................................................
7.4.7 Transfer Synchronization ......................................................................................
7.4.7.1
Software Synchronization ................................................................................
7.4.7.2
Hardware Synchronization ..............................................................................
7.4.8 Thread Budget Allocation ......................................................................................
7.4.9 FIFO Budget Allocation ........................................................................................
7.4.10 Chained Logical Channel Transfers .........................................................................
7.4.11 Reprogramming an Active Channel .........................................................................
7.4.12 Interrupt Generation ...........................................................................................
7.4.13 Packet Synchronization .......................................................................................
7.4.14 Graphics Acceleration Support ...............................................................................
7.4.15 Supervisor Modes ..............................................................................................
7.4.16 Posted and Nonposted Writes ...............................................................................
7.4.17 Disabling a Channel During Transfer ........................................................................
7.4.18 FIFO Draining Mechanism ....................................................................................
7.4.19 Reset ............................................................................................................
7.4.20 Power Management ...........................................................................................
7.4.20.1 Interconnect Clock Auto-Idle ............................................................................
7.4.20.2 Automatic Standby Mode ................................................................................
SDMA Basic Programming Model .....................................................................................
7.5.1 Setup Configuration .............................................................................................
7.5.2 Software-Triggered (Nonsynchronized) Transfer ...........................................................
7.5.3 Hardware-Synchronized Transfer .............................................................................
7.5.4 Synchronized Transfer Monitoring Using CDAC ............................................................
7.5.5 Concurrent Software and Hardware Synchronization ......................................................
7.5.6 Chained Transfer ................................................................................................
7.5.7 90-Degree Clockwise Image Rotation ........................................................................
7.5.8 Graphic Operations .............................................................................................
SDMA Use Cases and Tips ............................................................................................
7.6.1 Camcorder Use Case: How to Configure SDMA to Handle Transfers With McBSP2 and MMC to
External DRAM ..................................................................................................
7.6.1.1
Introduction ................................................................................................
7.6.1.2
SDMA Configuration to Transfer Data Between the McBSP and External DRAM ...............
7.6.1.2.1 Overview ..............................................................................................
7.6.1.2.2 Environment ...........................................................................................
7.6.1.2.3 Data Path ..............................................................................................
7.6.1.2.4 Programming Flow ...................................................................................
7.6.1.3
SDMA Configuration to Transfer Data Between MMC and External DRAM ......................
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SPRUGR0C – October 2009 – Revised November 2013
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7.7
8
7.6.1.3.1 Overview ..............................................................................................
7.6.1.3.2 Programming Flow ...................................................................................
SDMA Registers Manual ................................................................................................
7.7.1 SDMA Instance Summary .....................................................................................
7.7.2 SDMA Register Summary .....................................................................................
7.7.3 SDMA Register Description ....................................................................................
Interrupt Controller (INTC)
8.1
8.2
8.3
8.4
8.5
8.6
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829
832
832
832
833
................................................................................................ 858
Interrupt Controller Overview ...........................................................................................
Interrupt Controller Environment .......................................................................................
MPU Subsystem INTCPS Integration .................................................................................
8.3.1 Clocking, Reset, and Power Management Scheme ........................................................
8.3.1.1
MPU Subsystem INTC Clocks ..........................................................................
8.3.1.2
Hardware and Software Reset ..........................................................................
8.3.1.3
Power Management ......................................................................................
8.3.2 Interrupt Request Lines ........................................................................................
Interrupt Controller Functional Description ...........................................................................
8.4.1 Interrupt Processing ............................................................................................
8.4.1.1
Input Selection ............................................................................................
8.4.1.2
Masking ....................................................................................................
8.4.1.2.1 Individual Masking ...................................................................................
8.4.1.2.2 Global Masking (HS Devices Only) ................................................................
8.4.1.2.3 Priority Masking ......................................................................................
8.4.1.3
Priority Sorting ............................................................................................
8.4.2 Secure Interrupts (HS Devices Only) .........................................................................
8.4.3 Register Protection .............................................................................................
8.4.4 Module Power Saving ..........................................................................................
8.4.5 Interrupt Latency ................................................................................................
Interrupt Basic Programming Model ...................................................................................
8.5.1 Initialization Sequence .........................................................................................
8.5.2 MPU INTC Processing Sequence ............................................................................
8.5.3 MPU INTC Preemptive Processing Sequence ..............................................................
8.5.4 MPU INTC Spurious Interrupt Handling ......................................................................
Interrupt Controller Registers ...........................................................................................
8.6.1 Register Mapping Summary ...................................................................................
8.6.2 MPU INTC Register Descriptions .............................................................................
8.6.2.1
INTCPS_SYSCONFIG ...................................................................................
8.6.2.2
INTCPS_SYSSTATUS ...................................................................................
8.6.2.3
INTCPS_SIR_IRQ ........................................................................................
8.6.2.4
INTCPS_SIR_FIQ ........................................................................................
8.6.2.5
INTCPS_CONTROL ......................................................................................
8.6.2.6
INTCPS_PROTECTION .................................................................................
8.6.2.7
INTCPS_IDLE .............................................................................................
8.6.2.8
INTCPS_IRQ_PRIORITY ................................................................................
8.6.2.9
INTCPS_FIQ_PRIORITY ................................................................................
8.6.2.10 INTCPS_THRESHOLD ..................................................................................
8.6.2.11 INTCPS_ITRn .............................................................................................
8.6.2.12 INTCPS_MIRn ............................................................................................
8.6.2.13 INTCPS_MIR_CLEARn ..................................................................................
8.6.2.14 INTCPS_MIR_SETn ......................................................................................
8.6.2.15 INTCPS_ISR_SETn ......................................................................................
8.6.2.16 INTCPS_ISR_CLEARn ..................................................................................
8.6.2.17 INTCPS_PENDING_IRQn ...............................................................................
8.6.2.18 INTCPS_PENDING_FIQn ...............................................................................
SPRUGR0C – October 2009 – Revised November 2013
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8.6.2.19 INTCPS_ILRm ............................................................................................
8.6.3 Device INTC Initialization Register Descriptions ............................................................
8.6.3.1
INTC_INIT_REGISTER1 ................................................................................
8.6.3.2
INTC_INIT_REGISTER2 ................................................................................
9
887
888
888
888
......................................................................................................... 889
General-Purpose Memory Controller (GPMC) ....................................................................... 890
9.1.1 General-Purpose Memory Controller Overview ............................................................. 890
9.1.1.1
GPMC Features ........................................................................................... 891
9.1.2 GPMC Environment ............................................................................................ 892
9.1.3 GPMC Integration ............................................................................................... 895
9.1.3.1
Description ................................................................................................. 895
9.1.3.2
Clocking, Reset, and Power Management Scheme ................................................. 896
9.1.3.2.1 Clocking ............................................................................................... 896
9.1.3.2.2 Hardware Reset ...................................................................................... 896
9.1.3.2.3 Software Reset ....................................................................................... 896
9.1.3.2.4 Power Domain, Power Saving, and Reset Management ....................................... 896
9.1.3.2.5 Hardware Requests .................................................................................. 896
9.1.3.3
GPMC Address and Data Bus .......................................................................... 897
9.1.3.3.1 GPMC I/O Configuration Setting (In Default Pinout Mode 0) ................................... 897
9.1.3.3.2 GPMC CS0 Default Configuration at IC Reset ................................................... 898
9.1.4 GPMC Functional Description ................................................................................. 899
9.1.4.1
Description ................................................................................................. 899
9.1.4.2
L3 Interconnect Interface ................................................................................ 900
9.1.4.3
Address Decoder, GPMC Configuration, and Chip-Select Configuration Register File ......... 900
9.1.4.4
Error Correction Code Engine (ECC) .................................................................. 901
9.1.4.5
Prefetch and Write-Posting Engine ..................................................................... 901
9.1.4.6
External Device/Memory Port Interface ................................................................ 901
9.1.5 GPMC Basic Programming Model ............................................................................ 902
9.1.5.1
Chip-Select Base Address and Region Size Configuration ......................................... 902
9.1.5.2
Access Protocol Configuration .......................................................................... 903
9.1.5.2.1 Supported Devices ................................................................................... 903
9.1.5.2.2 Access Size Adaptation and Device Width ....................................................... 904
9.1.5.2.3 Address/Data-Multiplexing Interface ............................................................... 904
9.1.5.2.4 Address and Data Bus ............................................................................... 904
9.1.5.2.5 Asynchronous and Synchronous Access ......................................................... 904
9.1.5.2.6 Page and Burst Support ............................................................................. 905
9.1.5.2.7 System Burst Versus External Device Burst Support ........................................... 905
9.1.5.3
Timing Setting ............................................................................................. 906
9.1.5.3.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME) .............. 907
Memory Subsystem
9.1
9.1.5.3.2
nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME /
CSWROFFTIME / CSEXTRADELAY) ............................................................. 907
9.1.5.3.3 nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY) .............. 908
9.1.5.3.4 nOE/nRE: Output Enable / Read Enable Signal Control Assertion / Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY) ............................................... 908
9.1.5.3.5 nWE: Write Enable Signal Control Assertion / Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY) ................................................................................... 908
9.1.5.3.6 GPMC_CLK ........................................................................................... 909
9.1.5.3.7 GPMC_CLK and Control Signals Setup and Hold ............................................... 909
9.1.5.3.8 Access Time (RDACCESSTIME / WRACCESSTIME) .......................................... 910
9.1.5.3.9 Page Burst Access Time (PAGEBURSTACCESSTIME) ....................................... 910
9.1.5.3.10 Bus Keeping Support ................................................................................ 911
9.1.5.4
WAIT Pin Monitoring Control ............................................................................ 911
9.1.5.4.1 Wait Monitoring During an Asynchronous Read Access ........................................ 912
18
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9.1.5.4.2 Wait Monitoring During an Asynchronous Write Access ........................................
9.1.5.4.3 Wait Monitoring During a Synchronous Read Access ..........................................
9.1.5.4.4 Wait Monitoring During a Synchronous Write Access ...........................................
9.1.5.4.5 WAIT with NAND Device ............................................................................
9.1.5.4.6 Idle Cycle Control between Successive Accesses ..............................................
9.1.5.4.7 Slow Device Support (TIMEPARAGRANULARITY Parameter) ................................
9.1.5.5
gpmc_io_dir Pin ...........................................................................................
9.1.5.6
Reset .......................................................................................................
9.1.5.7
Write Protect (nWP) ......................................................................................
9.1.5.8
Byte Enable (nBE1/nBE0) ...............................................................................
9.1.5.9
Asynchronous Access Description .....................................................................
9.1.5.9.1 Asynchronous Single Read .........................................................................
9.1.5.9.2 Asynchronous Single Write .........................................................................
9.1.5.9.3 Asynchronous Multiple (Page Mode) Read .......................................................
9.1.5.10 Synchronous Access .....................................................................................
9.1.5.10.1 Synchronous Single Read ..........................................................................
9.1.5.10.2 Synchronous Single Write ..........................................................................
9.1.5.10.3 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst with Wraparound Capability)
..........................................................................................................
9.1.5.10.4 Synchronous Multiple (Burst) Write ................................................................
9.1.5.11 pSRAM Basic Programming Model ....................................................................
9.1.5.12 Error Handling .............................................................................................
9.1.5.13 Boot Configuration ........................................................................................
9.1.5.14 NAND Device Basic Programming Model .............................................................
9.1.5.14.1 NAND Memory Device in Byte or Word16 Stream Mode .......................................
9.1.5.14.2 NAND Device-Ready Pin ...........................................................................
9.1.5.14.3 ECC Calculator .......................................................................................
9.1.5.14.4 Prefetch and Write-Posting Engine ................................................................
9.1.6 GPMC Use Cases and Tips ...................................................................................
9.1.6.1
How to Set GPMC Timing Parameters for Typical Accesses .......................................
9.1.6.1.1 External Memory Attached to the GPMC Module ................................................
9.1.6.1.2 Typical GPMC Setup ................................................................................
9.1.6.2
How to Choose a Suitable Memory to use with the GPMC .........................................
9.1.6.2.1 Supported Memories or Devices ...................................................................
9.1.6.2.2 GPMC Features and Settings ......................................................................
9.1.7 GPMC Registers ................................................................................................
9.1.7.1
GPMC Register Mapping Summary ....................................................................
9.1.7.2
GPMC Register Descriptions ............................................................................
9.1.7.2.1 GPMC_SYSCONFIG ................................................................................
9.1.7.2.2 GPMC_SYSSTATUS ................................................................................
9.1.7.2.3 GPMC_IRQSTATUS .................................................................................
9.1.7.2.4 GPMC_IRQENABLE .................................................................................
9.1.7.2.5 GPMC_TIMEOUT_CONTROL .....................................................................
9.1.7.2.6 GPMC_ERR_ADDRESS ............................................................................
9.1.7.2.7 GPMC_ERR_TYPE ..................................................................................
9.1.7.2.8 GPMC_CONFIG ......................................................................................
9.1.7.2.9 GPMC_STATUS .....................................................................................
9.1.7.2.10 GPMC_CONFIG1_i ..................................................................................
9.1.7.2.11 GPMC_CONFIG2_i ..................................................................................
9.1.7.2.12 GPMC_CONFIG3_i ..................................................................................
9.1.7.2.13 GPMC_CONFIG4_i ..................................................................................
9.1.7.2.14 GPMC_CONFIG5_i ..................................................................................
9.1.7.2.15 GPMC_CONFIG6_i ..................................................................................
9.1.7.2.16 GPMC_CONFIG7_i ..................................................................................
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9.2
20
9.1.7.2.17 GPMC_NAND_COMMAND_i ...................................................................... 996
9.1.7.2.18 GPMC_NAND_ADDRESS_i ........................................................................ 997
9.1.7.2.19 GPMC_NAND_DATA_i ............................................................................. 997
9.1.7.2.20 GPMC_PREFETCH_CONFIG1 .................................................................... 998
9.1.7.2.21 GPMC_PREFETCH_CONFIG2 .................................................................. 1000
9.1.7.2.22 GPMC_PREFETCH_CONTROL ................................................................. 1000
9.1.7.2.23 GPMC_PREFETCH_STATUS .................................................................... 1001
9.1.7.2.24 GPMC_ECC_CONFIG ............................................................................. 1002
9.1.7.2.25 GPMC_ECC_CONTROL .......................................................................... 1003
9.1.7.2.26 GPMC_ECC_SIZE_CONFIG ..................................................................... 1004
9.1.7.2.27 GPMC_ECCj_RESULT ............................................................................ 1006
9.1.7.2.28 GPMC_BCH_RESULT0_i ......................................................................... 1007
9.1.7.2.29 GPMC_BCH_RESULT1_i ......................................................................... 1007
9.1.7.2.30 GPMC_BCH_RESULT2_i ......................................................................... 1007
9.1.7.2.31 GPMC_BCH_RESULT3_i ......................................................................... 1008
9.1.7.2.32 GPMC_BCH_SWDATA ............................................................................ 1008
SDRAM Controller (SDRC) Subsystem ............................................................................. 1009
9.2.1 SDRC Subsystem Overview ................................................................................. 1009
9.2.1.1
Features .................................................................................................. 1010
9.2.2 SDRC Subsystem Integration ................................................................................ 1011
9.2.2.1
Clocking, Reset, and Power Management Scheme ................................................ 1012
9.2.2.1.1 Clocking .............................................................................................. 1012
9.2.2.1.2 Hardware Reset ..................................................................................... 1012
9.2.2.1.3 Software Reset ...................................................................................... 1012
9.2.3 SDRC Subsystem Functional Description .................................................................. 1013
9.2.3.1
SDRAM Memory Scheduler ........................................................................... 1013
9.2.3.1.1 Memory Access Scheduling ....................................................................... 1014
9.2.3.1.2 Arbitration Policy .................................................................................... 1014
9.2.3.1.3 Internal Class Arbitration ........................................................................... 1016
9.2.3.1.4 Security Firewall .................................................................................... 1017
9.2.3.1.5 Rotation Engine ..................................................................................... 1020
9.2.3.1.6 Register Security .................................................................................... 1021
9.2.3.1.7 Security Violation Reporting ....................................................................... 1022
9.2.3.2
Module Power Saving .................................................................................. 1022
9.2.3.3
System Power Management ........................................................................... 1022
9.2.3.4
External Memory Interface Module (EMIF) .......................................................... 1023
9.2.3.4.1 EMIF Overview ...................................................................................... 1023
9.2.3.4.2 Functional Description ............................................................................. 1025
9.2.3.4.3 EMIF Registers ...................................................................................... 1040
9.2.3.4.4 Interrupt Conditions ................................................................................. 1069
9.2.3.4.5 Power Management ................................................................................ 1069
9.2.3.4.6 Programming/Usage Guide ....................................................................... 1075
9.2.4 SMS Basic Programming Model ............................................................................. 1075
9.2.4.1
SMS Firewall Usage .................................................................................... 1075
9.2.4.2
VRFB Context Configuration ........................................................................... 1076
9.2.4.3
Memory-Access Scheduler Configuration ............................................................ 1078
9.2.4.4
Error Logging ............................................................................................ 1078
9.2.5 SDRC Use Cases and Tips .................................................................................. 1079
9.2.5.1
How to Program the VRFB ............................................................................ 1079
9.2.5.1.1 VRFB Rotation Mechanism ........................................................................ 1079
9.2.5.1.2 Setting a VRFB Context ........................................................................... 1081
9.2.5.1.3 Applicative Use Case and Tips ................................................................... 1084
9.2.5.2
SMS Mode of Operation ................................................................................ 1087
Contents
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9.3
9.4
10
9.2.5.2.1 The SDRAM Memory Scheduler and Arbitration Policy .......................................
9.2.5.2.2 The Arbitration Decision ...........................................................................
9.2.5.2.3 Arbitration Granularity ..............................................................................
9.2.5.2.4 How these Mechanisms Interact ..................................................................
9.2.5.3
Camcorder Use Case: How to Configure the VRFB ................................................
9.2.5.3.1 Overview .............................................................................................
9.2.5.3.2 Data Path ............................................................................................
9.2.5.3.3 Programming Flow .................................................................................
9.2.5.4
Understanding SDRAM Subsystem Address Spaces ..............................................
9.2.5.4.1 Physical vs Virtual Address Spaces ..............................................................
9.2.6 SDRAM Memory Scheduler (SMS) Registers .............................................................
9.2.6.1
SMS Register Mapping Summary ....................................................................
9.2.6.2
SMS Register Descriptions ............................................................................
9.2.6.2.1 SMS_SYSCONFIG .................................................................................
9.2.6.2.2 SMS_SYSSTATUS .................................................................................
9.2.6.2.3 SMS_RG_ATTi ......................................................................................
9.2.6.2.4 SMS_RG_RDPERMi ...............................................................................
9.2.6.2.5 SMS_RG_WRPERMi ..............................................................................
9.2.6.2.6 SMS_RG_STARTj ..................................................................................
9.2.6.2.7 SMS_RG_ENDj .....................................................................................
9.2.6.2.8 SMS_SECURITY_CONTROL ....................................................................
9.2.6.2.9 SMS_CLASS_ARBITER0 .........................................................................
9.2.6.2.10 SMS_CLASS_ARBITER1 .........................................................................
9.2.6.2.11 SMS_CLASS_ARBITER2 .........................................................................
9.2.6.2.12 SMS_INTERCLASS_ARBITER ...................................................................
9.2.6.2.13 SMS_CLASS_ROTATIONm ......................................................................
9.2.6.2.14 SMS_ERR_ADDR ..................................................................................
9.2.6.2.15 SMS_ERR_TYPE ..................................................................................
9.2.6.2.16 SMS_POW_CTRL ..................................................................................
9.2.6.2.17 SMS_ROT_CONTROLn ...........................................................................
9.2.6.2.18 SMS_ROT_SIZEn ..................................................................................
9.2.6.2.19 SMS_ROT_PHYSICAL_BAn ......................................................................
On-Chip Memory (OCM) Subsystem ................................................................................
9.3.1 OCM Subsystem Overview ..................................................................................
9.3.2 OCM Subsystem Integration .................................................................................
9.3.2.1
Description ...............................................................................................
9.3.2.2
Clocking, Reset, and Power-Management Scheme ................................................
9.3.2.2.1 Clocking ..............................................................................................
9.3.2.2.2 Hardware Reset .....................................................................................
9.3.2.2.3 Power Domain ......................................................................................
9.3.3 OCM Subsystem Functional Description ...................................................................
9.3.3.1
OCM_ROM ...............................................................................................
9.3.3.2
OCM_RAM ...............................................................................................
Revision History ........................................................................................................
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Overview ................................................................................................................. 1123
10.1.1 Features ....................................................................................................... 1124
VPFE Controller - The System View ................................................................................. 1124
10.2.1 Clocks .......................................................................................................... 1124
10.2.2 Reset ........................................................................................................... 1125
10.2.3 Interrupts ...................................................................................................... 1125
Functional Description ................................................................................................. 1125
10.3.1 External IO Interface ......................................................................................... 1125
Video Processing Front End (VPFE)
10.1
10.2
10.3
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............................................................................................ 1173
SGX Overview .......................................................................................................... 1174
11.1.1 POWERVR SGX Main Features ........................................................................... 1174
11.1.2 SGX 3D Features ............................................................................................ 1175
11.1.3 Universal Scalable Shader Engine (USSE) – Key Features ............................................ 1176
SGX Integration ......................................................................................................... 1177
11.2.1 Clocking, Reset, and Power-Management Scheme ..................................................... 1177
11.2.1.1 Clocks ..................................................................................................... 1177
11.2.1.2 Resets .................................................................................................... 1178
2D/3D Graphics Accelerator
11.1
11.2
22
10.3.1.1 Raw Data Mode .........................................................................................
10.3.1.1.1 Mode Information – Always Required ...........................................................
10.3.1.1.2 Timing Information – Optional, Depending on Control Signals and Sensor Mode .........
10.3.1.2 ITU-R BT.656 Interface .................................................................................
10.3.1.3 Digital YCbCr Interface .................................................................................
10.3.2 VPFE Data / Image Processing ............................................................................
10.3.2.1 Raw Data Mode .........................................................................................
10.3.2.1.1 Input Sampling and Formatting ...................................................................
10.3.2.1.2 Optical Black Clamping ............................................................................
10.3.2.1.3 Black Level Compensation ........................................................................
10.3.2.1.4 Output Formatter ...................................................................................
10.3.2.2 YCbCr and BT656 Modes ..............................................................................
10.3.2.2.1 Input Sampling and Formatting ...................................................................
10.3.2.2.2 Black Clamping .....................................................................................
10.3.2.2.3 Output Formatter ...................................................................................
Programming Model ....................................................................................................
10.4.1 Enabling and Disabling the VPFE Controller .............................................................
10.4.2 Configuring VPFE Registers ................................................................................
10.4.2.1 General Register Setup ................................................................................
10.4.2.2 Interrupts .................................................................................................
10.4.2.3 Status .....................................................................................................
10.4.2.4 VDIN_VD latched Registers ...........................................................................
10.4.2.5 Inter-frame Operations .................................................................................
10.4.3 VPFE Limitations .............................................................................................
Video Processing Front End (VPFE) Registers ....................................................................
10.5.1 Peripheral Revision and Class Information Register (PID) .............................................
10.5.2 VPFE_Peripheral Control Register (VPFE_PCR) ........................................................
10.5.3 SYN_MODE Format and Description Register (SYN_MODE) .........................................
10.5.4 Horizontal Pixel Information Register (HORZ_INFO) ....................................................
10.5.5 Vertical Line - Settings for the Starting Pixel Register (VERT_START) ..............................
10.5.6 Number of Vertical Lines Register (VERT_LINES) .....................................................
10.5.7 Culling Information in Horizontal and Vertical Directions Register (CULLING) ......................
10.5.8 Horizontal Size (HSIZE_OFF) ..............................................................................
10.5.9 External Memory Line Offset Register (SDOFST) .......................................................
10.5.10 external memory Address Register (SDR_ADDR) .....................................................
10.5.11 Optical Black Clamping Settings Register (CLAMP) ...................................................
10.5.12 DC Clamp Register (DCSUB) .............................................................................
10.5.13 CCD Color Pattern Register (COLPTN) .................................................................
10.5.14 Black Compensation Register (BLKCMP) ...............................................................
10.5.15 VPFE Interrupt Control Register (VDINT) ...............................................................
10.5.16 ALAW Configuration Register (ALAW) ...................................................................
10.5.17 REC656IF Configuration Register (REC656IF) .........................................................
10.5.18 CCD Configuration Register (CCDCFG) .................................................................
10.5.19 DMA Control Register (DMA_CNTL) .....................................................................
Contents
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11.3
11.4
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11.2.1.3 Power Management ....................................................................................
11.2.2 Hardware Requests ..........................................................................................
11.2.2.1 Interrupt Request ........................................................................................
SGX Functional Description ...........................................................................................
11.3.1 SGX Block Diagram ..........................................................................................
11.3.2 SGX Elements Description ..................................................................................
SGX Register Mapping ................................................................................................
Display Subsystem
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12.3
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Display Subsystem Overview .........................................................................................
Display Subsystem Environment .....................................................................................
12.2.1 LCD Support ..................................................................................................
12.2.1.1 Parallel Interface ........................................................................................
12.2.1.1.1 Parallel Interface in RFBI Mode (MIPI DBI Protocol) ..........................................
12.2.1.1.2 Parallel Interface in Bypass Mode (MIPI DPI Protocol) .......................................
12.2.1.1.3 LCD Output and Data Format for the Parallel Interface .......................................
12.2.1.1.4 Transaction Timing Diagrams .....................................................................
12.2.1.2 SDI Serial Interface .....................................................................................
12.2.1.3 DSI Serial Interface .....................................................................................
12.2.2 LCD Support With MIPI DSI 1.0 Protocol and Data Format ............................................
12.2.2.1 Physical Layer ...........................................................................................
12.2.2.1.1 Data/Clock Configuration ..........................................................................
12.2.2.1.2 ULPS .................................................................................................
12.2.2.2 Video Port (VP) Interface ...............................................................................
12.2.2.2.1 Video Port Used for Video Mode .................................................................
12.2.2.2.2 Video Port Used on Command Mode ............................................................
12.2.2.2.3 Burst Mode ..........................................................................................
12.2.2.3 Multilane Layer ..........................................................................................
12.2.2.3.1 SoT and EoT in Multilane Configurations .......................................................
12.2.2.3.2 Lane Splitter .........................................................................................
12.2.2.4 Protocol Layer ...........................................................................................
12.2.2.4.1 Short Packet ........................................................................................
12.2.2.4.2 Long Packet .........................................................................................
12.2.2.4.3 Data Identifier .......................................................................................
12.2.2.4.4 Virtual Channel ID - VC Field, DI[7:6] ............................................................
12.2.2.4.5 Data Type Field DT[5:0] ...........................................................................
12.2.2.4.6 Pixel Data Formats in Video Mode ...............................................................
12.2.2.4.7 Synchronization Codes ............................................................................
12.2.2.4.8 Blanking ..............................................................................................
12.2.2.4.9 Frame Structures ...................................................................................
12.2.2.4.10 Virtual Channels ...................................................................................
12.2.2.5 Pixel Data Formats ......................................................................................
12.2.2.5.1 24 Bits per Pixel - RGB Color Format, Long Packet ...........................................
12.2.2.5.2 18 Bits per Pixel (Loosely Packed) - RGB Color Format, Long Packet .....................
12.2.2.5.3 18 Bits per Pixel (Packed) - RGB Color Format, Long Packet ...............................
12.2.2.5.4 16 Bits per Pixel - RGB Color Format, Long Packet ...........................................
12.2.3 LCD Output With TI FlatLink3G Data Format for the SDI Module .....................................
12.2.4 TV Display Support ...........................................................................................
12.2.4.1 TV Output and Data Format ...........................................................................
12.2.4.2 Digital-to-Analog Converter ............................................................................
Display Subsystem Integration .......................................................................................
12.3.1 Clocking, Reset, and Power-Management Scheme .....................................................
12.3.1.1 Clocks .....................................................................................................
12.3.1.2 Resets ....................................................................................................
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12.3.1.2.1 Hardware Reset ....................................................................................
12.3.1.2.2 Software Reset .....................................................................................
12.3.1.3 Power Domain ...........................................................................................
12.3.1.4 Power Management ....................................................................................
12.3.1.4.1 Clock Activity Mode ................................................................................
12.3.1.4.2 Autoidle Mode .......................................................................................
12.3.1.4.3 Idle Mode ............................................................................................
12.3.1.4.4 SDI Idle Mode .......................................................................................
12.3.1.4.5 Wake-Up Mode .....................................................................................
12.3.1.4.6 Standby Mode .......................................................................................
12.3.2 Hardware Requests ..........................................................................................
12.3.2.1 DMA Requests ..........................................................................................
12.3.2.1.1 Display Controller DMA Request (Line Trigger) ................................................
12.3.2.1.2 DSI Protocol Engine DMA Request ..............................................................
12.3.2.1.3 RFBI DMA Request ................................................................................
12.3.2.2 Interrupt Requests ......................................................................................
12.3.2.2.1 DISPC Interrupt Request ..........................................................................
12.3.2.2.2 DSI Interrupt Request ..............................................................................
Display Subsystem Functional Description .........................................................................
12.4.1 Block Diagram ................................................................................................
12.4.2 Display Controller Functionalities ..........................................................................
12.4.2.1 Display Modes ...........................................................................................
12.4.2.1.1 LCD Output ..........................................................................................
12.4.2.1.2 Digital Output ........................................................................................
12.4.2.2 Graphics Pipeline .......................................................................................
12.4.2.2.1 Graphics Memory Format .........................................................................
12.4.2.2.2 Color Look-Up Table/Gamma Table .............................................................
12.4.2.3 Video Pipeline ...........................................................................................
12.4.2.3.1 Video Memory Formats ............................................................................
12.4.2.3.2 Color Space Conversion ...........................................................................
12.4.2.3.3 Hardware Cursor ...................................................................................
12.4.2.3.4 Up-/Down-Sampling ................................................................................
12.4.2.4 Overlay Support .........................................................................................
12.4.2.4.1 Priority Rule .........................................................................................
12.4.2.4.2 Transparency Color Keys .........................................................................
12.4.2.4.3 Overlay Optimization (Only Available in Normal Mode) .......................................
12.4.2.5 Active/Passive Matrix Display Data Path ............................................................
12.4.2.5.1 Color Phase Rotation ..............................................................................
12.4.2.5.2 Passive Matrix Display Dithering Logic ..........................................................
12.4.2.5.3 Passive Matrix Display Output FIFO .............................................................
12.4.2.5.4 Multiple Cycle Output Format .....................................................................
12.4.2.6 Video Line Buffer ........................................................................................
12.4.2.7 Synchronized Buffer Update ...........................................................................
12.4.2.8 Rotation ...................................................................................................
12.4.2.9 Multiple Buffer Support .................................................................................
12.4.3 DSI Protocol Engine Functionalities .......................................................................
12.4.3.1 DSI Protocol Architecture ..............................................................................
12.4.3.2 Clock Requirements ....................................................................................
12.4.3.2.1 Timing Parameters for an LP to HS Transaction ...............................................
12.4.3.2.2 Timing Parameters for an HS to LP Transaction ...............................................
12.4.3.2.3 Extra LP Transitions ................................................................................
12.4.3.3 DSI Transfer Modes ....................................................................................
12.4.3.3.1 Video Mode ..........................................................................................
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12.4.3.3.2 Command Mode ....................................................................................
12.4.3.3.3 Video + Command Modes .........................................................................
12.4.3.3.4 Burst Modes .........................................................................................
12.4.3.3.5 Interleaving Mode ..................................................................................
12.4.3.4 Power Management ....................................................................................
12.4.3.5 Serial Configuration Port (SCP) Interface ............................................................
12.4.3.5.1 Shadowing Register ................................................................................
12.4.3.5.2 Busy Signal ..........................................................................................
12.4.3.6 Power Control ............................................................................................
12.4.3.6.1 Complex I/O Power Control Commands ........................................................
12.4.3.6.2 DSI PLL Power Control Commands .............................................................
12.4.3.7 Timers ....................................................................................................
12.4.3.7.1 Twakeup Timer .....................................................................................
12.4.3.7.2 ForceTxStopMode FSM ...........................................................................
12.4.3.7.3 TurnRequest FSM ..................................................................................
12.4.3.7.4 Peripheral Reset Timer ............................................................................
12.4.3.7.5 HS TX Timer ........................................................................................
12.4.3.7.6 LP RX Timer ........................................................................................
12.4.3.8 Bus Turnaround .........................................................................................
12.4.3.9 PHY Triggers ............................................................................................
12.4.3.9.1 Reset .................................................................................................
12.4.3.9.2 Tearing Effect .......................................................................................
12.4.3.9.3 Acknowledge ........................................................................................
12.4.3.10 ECC Generation ........................................................................................
12.4.3.11 Checksum Generation for Long Packet Payloads .................................................
12.4.3.12 End of Transfer Packet ................................................................................
12.4.4 DSI PLL Controller Functionalities .........................................................................
12.4.4.1 DSI PLL Controller Overview ..........................................................................
12.4.4.2 DSI PLL Controller Architecture .......................................................................
12.4.4.3 DSI PLL Operations .....................................................................................
12.4.4.4 DSI PLL Controller Shadowing Mechanism .........................................................
12.4.4.5 Error Handling ...........................................................................................
12.4.5 DSI Complex I/O Functionalities ...........................................................................
12.4.5.1 DSI Complex I/O Overview ............................................................................
12.4.5.2 DSI Complex I/O Architecture .........................................................................
12.4.6 RFBI Functionalities ..........................................................................................
12.4.6.1 RFBI FIFO ................................................................................................
12.4.6.2 RFBI Interconnect FIFO ................................................................................
12.4.6.3 Input Pixel Formats .....................................................................................
12.4.6.4 Output Parallel Modes ..................................................................................
12.4.6.5 Unmodified Bits ..........................................................................................
12.4.6.6 Bypass Mode ............................................................................................
12.4.6.7 Send Commands ........................................................................................
12.4.6.8 Read/Write ...............................................................................................
12.4.7 Video Encoder Functionalities ..............................................................................
12.4.7.1 Test Pattern Generation ................................................................................
12.4.7.2 Luma Stage ..............................................................................................
12.4.7.3 Chroma Stage ...........................................................................................
12.4.7.4 Subcarrier and Burst Generation ......................................................................
12.4.7.5 Closed Caption Encoding ..............................................................................
12.4.7.6 Wide-Screen Signaling (WSS) Encoding ............................................................
12.4.7.7 Video DAC Architecture ................................................................................
12.4.7.8 Video DC/AC Coupled TV Load .......................................................................
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12.4.7.9 TV Detection/Disconnection Pulse Generation and Usage ........................................
12.4.7.9.1 TV Detection/Disconnection Pulse Generation .................................................
12.4.7.9.2 TV Detection Procedure ...........................................................................
12.4.7.9.3 TV Disconnection Procedure ......................................................................
12.4.7.9.4 Recommended TV Detection/Disconnection Pulse Waveform ...............................
12.4.7.9.5 TV Detection/Disconnection Usage ..............................................................
12.4.7.10 Video DAC Bypass Mode .............................................................................
12.4.7.11 Video Dual-DAC Test Mode ..........................................................................
12.4.8 SDI Functionalities ...........................................................................................
Display Subsystem Basic Programming Model ....................................................................
12.5.1 Display Subsystem Reset ...................................................................................
12.5.2 Display Subsystem Configuration Phase ..................................................................
12.5.3 Display Controller Basic Programming Model ............................................................
12.5.3.1 Display Controller Configuration ......................................................................
12.5.3.2 Graphics Layer Configuration .........................................................................
12.5.3.2.1 Graphics DMA Registers ..........................................................................
12.5.3.2.2 Graphics Layer Configuration Registers .........................................................
12.5.3.2.3 Graphics Window Attributes .......................................................................
12.5.3.3 Video Layer Configuration .............................................................................
12.5.3.3.1 Video DMA Registers ..............................................................................
12.5.3.3.2 Video Configuration Register .....................................................................
12.5.3.3.3 Video Window Attributes ..........................................................................
12.5.3.3.4 Video Up-/Down-Sampling Configuration .......................................................
12.5.3.3.5 Video Color Space Conversion Configuration ..................................................
12.5.3.4 Rotation/Mirroring Display Subsystem Settings .....................................................
12.5.3.4.1 Image Data Formats ...............................................................................
12.5.3.4.2 Image Data from On-Chip SRAM ................................................................
12.5.3.4.3 Image Data from External SRAM ................................................................
12.5.3.4.4 Additional configuration when using YUV format ...............................................
12.5.3.5 LCD-Specific Control Registers .......................................................................
12.5.3.5.1 LCD Attributes ......................................................................................
12.5.3.5.2 LCD Timings ........................................................................................
12.5.3.5.3 LCD Overlay ........................................................................................
12.5.3.5.4 LCD TDM ............................................................................................
12.5.3.5.5 LCD Spatial/Temporal Dithering ..................................................................
12.5.3.5.6 LCD Color Phase Rotation ........................................................................
12.5.3.6 TV Set-Specific Control Registers ....................................................................
12.5.3.6.1 Digital Timings ......................................................................................
12.5.3.6.2 Digital Frame/Field Size ...........................................................................
12.5.3.6.3 Digital Overlay ......................................................................................
12.5.4 DSI Protocol Engine Basic Programming Model .........................................................
12.5.4.1 Software Reset ..........................................................................................
12.5.4.2 Power Management ....................................................................................
12.5.4.3 Interrupts .................................................................................................
12.5.4.4 Global Register Controls ...............................................................................
12.5.4.5 Virtual Channels .........................................................................................
12.5.4.6 Packets ...................................................................................................
12.5.4.7 DSI Complex I/O ........................................................................................
12.5.4.8 Video Mode ..............................................................................................
12.5.4.9 Video Port Data Bus ....................................................................................
12.5.4.10 Command Mode .......................................................................................
12.5.4.10.1 Command Mode TX FIFO .......................................................................
12.5.4.10.2 Command Mode RX FIFO .......................................................................
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SPRUGR0C – October 2009 – Revised November 2013
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12.5.4.10.3 Command Mode DMA Requests ...............................................................
12.5.4.11 Ultra-Low Power State ................................................................................
12.5.4.11.1 Entering ULPS .....................................................................................
12.5.4.11.2 Exiting ULPS .......................................................................................
12.5.4.12 DSI Programming Sequence Example ..............................................................
12.5.4.12.1 Video Mode Transfer .............................................................................
12.5.4.12.2 Command Mode Transfer Example 1 ..........................................................
12.5.4.12.3 Command Mode Transfer Example 2 ..........................................................
12.5.5 DSI PLL Controller Basic Programming Model ...........................................................
12.5.5.1 Software Reset ..........................................................................................
12.5.5.2 DSI PLL Programming Blocks .........................................................................
12.5.5.3 DSI PLL Go Sequence .................................................................................
12.5.5.4 DSI PLL Clock Gating Sequence .....................................................................
12.5.5.5 DSI PLL Lock Sequence ...............................................................................
12.5.5.6 DSI PLL Error Handling ................................................................................
12.5.5.7 DSI PLL Recommended Values ......................................................................
12.5.6 DSI Complex I/O Basic Programming Model .............................................................
12.5.6.1 Software Reset ..........................................................................................
12.5.6.2 Reset-Done Bits .........................................................................................
12.5.6.3 Pad Configuration .......................................................................................
12.5.6.4 Display Timing Configuration ..........................................................................
12.5.6.4.1 High-Speed Clock Transmission .................................................................
12.5.6.4.2 High-Speed Data Transmission ..................................................................
12.5.6.4.3 Turn-Around Request in Transmit Mode ........................................................
12.5.6.4.4 Turn-Around Request in Receive Mode .........................................................
12.5.6.4.5 Other DSI_PHY Transmission and Reception ..................................................
12.5.6.5 Error Handling ...........................................................................................
12.5.7 RFBI Basic Programming Model ...........................................................................
12.5.7.1 DISPC Control Registers ...............................................................................
12.5.7.2 RFBI Control Registers .................................................................................
12.5.7.2.1 High Threshold ......................................................................................
12.5.7.2.2 Bypass Mode ........................................................................................
12.5.7.2.3 Enable ................................................................................................
12.5.7.2.4 Configuration Selection ............................................................................
12.5.7.2.5 ITE Bit ................................................................................................
12.5.7.2.6 Number of Pixels to Transfer .....................................................................
12.5.7.2.7 Programmable Line Number ......................................................................
12.5.7.3 RFBI Configuration ......................................................................................
12.5.7.3.1 Parallel Mode .......................................................................................
12.5.7.3.2 Trigger Mode ........................................................................................
12.5.7.3.3 VSYNC Pulse Width (Minimum Value) ..........................................................
12.5.7.3.4 HSYNC Pulse Width (Minimum Value) ..........................................................
12.5.7.3.5 Cycle Format ........................................................................................
12.5.7.3.6 Unused Bits .........................................................................................
12.5.7.3.7 RFBI Timings ........................................................................................
12.5.7.3.8 RFBI State-Machine ................................................................................
12.5.7.3.9 RFBI Configuration Flow Charts ..................................................................
12.5.8 Video Encoder Basic Programming Model ................................................................
12.5.8.1 Video Encoder Software Reset ........................................................................
12.5.8.2 Video DAC Settings .....................................................................................
12.5.8.3 Video Encoder Programming Sequence .............................................................
12.5.8.4 Video Encoder Register Settings ......................................................................
12.5.9 SDI Basic Programming Model .............................................................................
SPRUGR0C – October 2009 – Revised November 2013
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12.5.9.1 SDI Configuration .......................................................................................
12.5.9.1.1 SDI PLL Configuration .............................................................................
12.5.9.1.2 Signal Features Configuration ....................................................................
12.5.9.1.3 Number of Data Pairs ..............................................................................
12.5.9.2 SDI Power-Management Programming Sequence .................................................
12.5.9.2.1 SDI Reset State .....................................................................................
12.5.9.2.2 SDI Power_On Sequence .........................................................................
12.5.9.2.3 SDI Power-Down Sequence ......................................................................
12.5.9.3 SDI Start Sequence .....................................................................................
12.5.9.4 SDI Stop Sequence .....................................................................................
12.5.9.5 Clock Source/Frequency Change Sequence ........................................................
12.5.9.5.1 Complete Sequence ...............................................................................
12.5.9.5.2 Simplified Sequence When LCD and PCD Are Swapped ....................................
12.5.9.6 SDI Error Management .................................................................................
Display Subsystem Use Cases and Tips ............................................................................
12.6.1 How to Configure the Scaling Unit in the DISPC Module ...............................................
12.6.1.1 Filtering ...................................................................................................
12.6.1.1.1 Vertical Filtering .....................................................................................
12.6.1.1.2 Horizontal Filtering .................................................................................
12.6.1.2 Scaling Algorithms ......................................................................................
12.6.1.3 Scaling Settings .........................................................................................
12.6.1.3.1 Register List .........................................................................................
12.6.1.3.2 Enabling .............................................................................................
12.6.1.3.3 Factor ................................................................................................
12.6.1.3.4 Initial Phase .........................................................................................
12.6.1.3.5 Coefficients ..........................................................................................
12.6.2 Display Low-Power Refresh Settings ......................................................................
12.6.2.1 Display Low-Power Refresh Overview ...............................................................
12.6.2.2 Display Subsystem Clock ..............................................................................
12.6.2.2.1 Display Subsystem Clock Configuration .........................................................
12.6.2.2.2 Display Subsystem Clock Enable ................................................................
12.6.2.3 DPLL4 in Low-Power Mode ............................................................................
12.6.2.4 Autoidle and Smart Idle ................................................................................
12.6.2.4.1 Autoidle ..............................................................................................
12.6.2.4.2 Smart-Idle ............................................................................................
12.6.2.5 FIFO Thresholds ........................................................................................
12.6.2.5.1 FIFO Threshold Settings to Reduce Power Consumption ....................................
12.6.2.6 Vertical and Horizontal Timings .......................................................................
12.6.2.6.1 Horizontal and Vertical Timing Settings to Reduce Power Consumption ...................
12.6.3 How to Configure the Serial Display Interface Module With FlatLink3G Protocol ...................
12.6.3.1 SDI PLL Architecture ...................................................................................
12.6.3.2 SDI PLL Configuration ..................................................................................
12.6.3.3 Application Example: HVGA Display .................................................................
12.6.3.3.1 HVGA Display .......................................................................................
12.6.3.3.2 SDI PLL Settings for 1-Channel Mode: ..........................................................
12.6.3.3.3 SDI PLL Settings for 2-Channel Mode: ..........................................................
12.6.4 How to Interface OMAP Device With SN65LVDS302 Receiver for an XGA Display Application ..
12.6.4.1 Hardware Connections .................................................................................
12.6.4.2 SN65LVDS302 Receiver Description .................................................................
12.6.4.3 SDI Software Settings ..................................................................................
12.6.4.3.1 SDI Configuration ...................................................................................
12.6.4.3.2 Signal Features Configuration ....................................................................
12.6.4.3.3 SDI PLL Configuration .............................................................................
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12.7
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12.6.4.4 SN65LVDS302 Receiver Settings ....................................................................
12.6.4.4.1 Receiver Power-Up .................................................................................
12.6.4.4.2 Receiver Modes and Transitions .................................................................
12.6.4.4.3 Parity Error Detection and Handling .............................................................
12.6.5 Camcorder Use Case: How to Configure the Display Subsystem When Connected With a QVGA
LCD Panel ......................................................................................................
12.6.5.1 Overview .................................................................................................
12.6.5.2 Environment ..............................................................................................
12.6.5.2.1 LCD panel Features ................................................................................
12.6.5.3 Data Path .................................................................................................
12.6.5.4 Programming Flow ......................................................................................
12.6.5.4.1 Pads Multiplexing Configuration ..................................................................
12.6.5.4.2 Display Subsystem Initialization ..................................................................
12.6.5.4.3 Video1 Channel Configuration ....................................................................
12.6.5.4.4 Interrupts Enable ...................................................................................
12.6.5.4.5 Display Panel Configuration .......................................................................
12.6.5.4.6 LCD Enable .........................................................................................
12.6.6 How to Configure the DSI PLL in Video Mode ...........................................................
12.6.7 DSI Video Mode Using the DISPC Video Port ...........................................................
12.6.7.1 Display Subsystem Clock Configuration .............................................................
12.6.7.2 Configure DSI, DSI PLL and Complex I/O ...........................................................
12.6.7.2.1 Reset DSI Modules .................................................................................
12.6.7.2.2 Set Up DSI DPLL ...................................................................................
12.6.7.2.3 Switch to DSI PLL Clock Source .................................................................
12.6.7.2.4 Set Up DSI Protocol Engine ......................................................................
12.6.7.2.5 Configure DSI_PHY ................................................................................
12.6.7.2.6 Drive Stop State ....................................................................................
12.6.7.3 Initialization of the External MIPI Display Controller ................................................
12.6.7.4 Configure the DISPC ...................................................................................
12.6.7.4.1 Reset DISPC ........................................................................................
12.6.7.4.2 Configure DISPC Timing, Window, and Color ..................................................
12.6.7.5 Enable Video Mode Using the DISPC Video Port ..................................................
12.6.8 DSI Command Mode Using the DISPC Video Port ......................................................
12.6.8.1 Display Subsystem Use Cases and Tips ............................................................
12.6.8.1.1 Configure DSS Clocks at the PRCM Module ...................................................
12.6.8.1.2 Configure DSI Protocol Engine, DSI PLL, and Complex I/O .................................
12.6.8.1.3 Initialization of the External MIPI LCD Controller ...............................................
12.6.8.1.4 Configure the DISPC ...............................................................................
12.6.8.1.5 Enable Command Mode Using DISPC Video Port .............................................
12.6.8.1.6 Send Frame Data to LCD Panel Using Automatic TE .........................................
Display Subsystem Register Manual ................................................................................
12.7.1 Display Subsystem Register Mapping Summary .........................................................
12.7.2 Register Descriptions ........................................................................................
12.7.2.1 Display Subsystem and SDI Registers ...............................................................
12.7.2.2 Display Controller Registers ...........................................................................
12.7.2.3 RFBI Registers ..........................................................................................
12.7.2.4 Video Encoder Registers ...............................................................................
12.7.2.5 DSI Protocol Engine Registers ........................................................................
12.7.2.6 DSI complex I/O Registers .............................................................................
12.7.2.7 DSI PLL Control Module Registers ...................................................................
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Timers Overview ........................................................................................................ 1622
General-Purpose Timers .............................................................................................. 1623
Timers
13.1
13.2
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Contents
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13.3
13.4
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13.2.1 GP Timers Overview .........................................................................................
13.2.1.1 GP Timers Features ....................................................................................
13.2.2 GP Timers Environment .....................................................................................
13.2.2.1 GP Timers External System Interface ................................................................
13.2.3 GP Timers Integration .......................................................................................
13.2.3.1 Clocking, Reset, and Power-Management Scheme ................................................
13.2.3.1.1 Clock Management .................................................................................
13.2.3.1.2 Wake-Up Capability ................................................................................
13.2.3.1.3 Reset and Power Management ...................................................................
13.2.3.2 Software Reset ..........................................................................................
13.2.3.3 GP Timer Interrupts .....................................................................................
13.2.4 GP Timers Functional Description .........................................................................
13.2.4.1 GP Timers Block Diagram .............................................................................
13.2.4.2 Timer Mode Functionality ..............................................................................
13.2.4.2.1 1-ms Tick Generation (Only GPTIMER1, GPTIMER2, and GPTIMER10) ..................
13.2.4.3 Capture Mode Functionality ............................................................................
13.2.4.4 Compare Mode Functionality ..........................................................................
13.2.4.5 Prescaler Functionality .................................................................................
13.2.4.6 Pulse-Width Modulation ................................................................................
13.2.4.7 Timer Counting Rate ....................................................................................
13.2.5 Timer Under Emulation ......................................................................................
13.2.6 Accessing GP Timer Registers .............................................................................
13.2.6.1 Writing to Timer Registers .............................................................................
13.2.6.1.1 Write Posting Synchronization Mode ............................................................
13.2.6.1.2 Write Nonposting Synchronization Mode ........................................................
13.2.6.2 Reading From Timer Counter Registers .............................................................
General-Purpose Timers Register Manual ..........................................................................
13.3.1 GP Timer Register Map .....................................................................................
13.3.1.1 Instance Summary ......................................................................................
13.3.2 GP Timer Register Mapping Summary ....................................................................
13.3.3 GP Timer Register Descriptions ............................................................................
Watchdog Timers .......................................................................................................
13.4.1 WDTs Overview ..............................................................................................
13.4.1.1 WDT Features ...........................................................................................
13.4.2 WDT Integration ..............................................................................................
13.4.2.1 Clocking, Reset, and Power-Management Scheme ................................................
13.4.2.1.1 Clock Management .................................................................................
13.4.2.1.2 Reset and Power Management ...................................................................
13.4.2.2 Interrupts .................................................................................................
13.4.3 WDTs Functional Description ...............................................................................
13.4.3.1 General WDT Operation ...............................................................................
13.4.3.2 Reset Context ............................................................................................
13.4.3.3 Overflow/Reset Generation ............................................................................
13.4.3.4 Prescaler Value/Timer Reset Frequency .............................................................
13.4.3.5 Triggering a Timer Reload .............................................................................
13.4.3.6 Start/Stop Sequence for WDTs (Using WDTi.WSPR Register) ...................................
13.4.3.7 Modifying Timer Count/Load Values and Prescaler Setting .......................................
13.4.3.8 Watchdog Counter Register Access Restriction (WDTi.WCRR Register) .......................
13.4.3.9 WDT Interrupt Generation ..............................................................................
13.4.3.10 WDT Under Emulation ................................................................................
13.4.3.11 Accessing Watchdog Timer Registers ..............................................................
Watchdog Timer Register Manual ....................................................................................
13.5.1 Instance Summary ...........................................................................................
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13.6
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13.5.2 WDT Register Mapping Summary .........................................................................
13.5.3 WDT Register Descriptions .................................................................................
32-kHz Synchronized Timer ...........................................................................................
13.6.1 32-kHz Sync Timer Functional Description ...............................................................
13.6.1.1 Reading the 32-kHz Sync Timer ......................................................................
13.6.1.2 32-kHz Sync Timer Features ..........................................................................
13.6.2 32-kHz Sync Timer Environment ...........................................................................
13.6.3 32-kHz Sync Timer Integration .............................................................................
13.6.3.1 Clocking, Reset, and Power-Management Scheme ................................................
13.6.3.2 Interrupts .................................................................................................
13.6.3.3 Sync Timer 32k and MSuspend Signal ..............................................................
32-kHz Sync Timer Register Manual ................................................................................
13.7.1 32-kHz Sync Timer Instance Summary ...................................................................
13.7.2 32-kHz Sync Timer Register Mapping Summary ........................................................
13.7.3 32-kHz Sync Timer Register Descriptions ................................................................
UART/IrDA/CIR Module
14.1
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14.3
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UART/IrDA/CIR Overview .............................................................................................
14.1.1 UART Features ...............................................................................................
14.1.2 IrDA Features .................................................................................................
14.1.3 CIR Features ..................................................................................................
UART/IrDA/CIR Environment .........................................................................................
14.2.1 System Using UART Communication with Hardware Handshake .....................................
14.2.2 System using IrDA Communication Protocol .............................................................
14.2.3 System using CIR Communication Protocol with Remote Control .....................................
14.2.4 UART Interface Description .................................................................................
14.2.4.1 UART Interface Description ............................................................................
14.2.4.2 UART Protocol and Data Format .....................................................................
14.2.5 IrDA Functional Interfaces ...................................................................................
14.2.5.1 UART3 Interface Description ..........................................................................
14.2.5.2 IrDA Protocol and Data Format .......................................................................
14.2.5.2.1 SIR Mode ............................................................................................
14.2.5.2.2 SIR Free Format Mode ............................................................................
14.2.5.2.3 MIR Mode ...........................................................................................
14.2.5.2.4 FIR Mode ............................................................................................
14.2.6 CIR Functional Interfaces ...................................................................................
14.2.6.1 CIR Interface Description ..............................................................................
14.2.6.2 CIR Protocol and Data Format ........................................................................
14.2.6.2.1 Carrier Modulation ..................................................................................
14.2.6.2.2 Pulse Duty Cycle ...................................................................................
14.2.6.2.3 Consumer IR Encoding/Decoding ................................................................
UART/IrDA/CIR Integration ............................................................................................
14.3.1 Clocking, Reset, and Power-Management Scheme .....................................................
14.3.1.1 Clocking ..................................................................................................
14.3.1.2 Hardware Reset .........................................................................................
14.3.1.3 Software Reset ..........................................................................................
14.3.2 Hardware Requests ..........................................................................................
14.3.2.1 Interrupts .................................................................................................
14.3.2.2 DMA Requests ..........................................................................................
14.3.2.3 Wake-up Request .......................................................................................
UART/IrDA/CIR Functional Description ..............................................................................
14.4.1 UART/IrDA/CIR Block Description .........................................................................
14.4.2 FIFO Management ...........................................................................................
14.4.2.1 FIFO Trigger .............................................................................................
SPRUGR0C – October 2009 – Revised November 2013
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14.4.2.1.1 Transmit FIFO Trigger .............................................................................
14.4.2.1.2 Receive FIFO Trigger ..............................................................................
14.4.2.2 FIFO Interrupt Mode ....................................................................................
14.4.2.3 FIFO Polled Mode Operation ..........................................................................
14.4.2.4 FIFO DMA Mode Operation ............................................................................
14.4.2.4.1 DMA Transfers (DMA Mode 1, 2, or 3) ..........................................................
14.4.2.4.2 DMA Transmission .................................................................................
14.4.2.4.3 DMA Reception .....................................................................................
14.4.3 Mode Selection ...............................................................................................
14.4.3.1 Register Access Modes ................................................................................
14.4.3.1.1 Operational Mode and Configuration Modes ...................................................
14.4.3.1.2 Register Access Submode ........................................................................
14.4.3.1.3 Registers Available for the Register Access Modes ...........................................
14.4.3.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection ...................................................
14.4.3.2.1 Registers Available for the UART Function .....................................................
14.4.3.2.2 Registers Available for the IrDA Function (UART3 Only) .....................................
14.4.3.2.3 Registers Available for the CIR Function (UART3 Only) ......................................
14.4.4 Protocol Formatting ..........................................................................................
14.4.4.1 UART Mode ..............................................................................................
14.4.4.1.1 UART Clock Generation: Baud Rate Generation ..............................................
14.4.4.1.2 Choosing the Appropriate Divisor Value .........................................................
14.4.4.1.3 UART Data Formatting ............................................................................
14.4.4.1.4 UART Mode Interrupt Management ..............................................................
14.4.4.2 IrDA Mode (UART3 Only) ..............................................................................
14.4.4.2.1 IrDA Clock Generation: Baud Generator ........................................................
14.4.4.2.2 Choosing the Appropriate Divisor Value .........................................................
14.4.4.2.3 IrDA Data Formatting ..............................................................................
14.4.4.2.4 SIR Mode DATA Formatting ......................................................................
14.4.4.2.5 MIR and FIR Mode Data Formatting .............................................................
14.4.4.2.6 IrDA Mode Interrupt Management ................................................................
14.4.4.3 CIR Mode (UART3 Only) ...............................................................................
14.4.4.3.1 CIR Mode Clock Generation ......................................................................
14.4.4.3.2 CIR Data Formatting ...............................................................................
14.4.4.3.3 CIR Mode Interrupt Management ................................................................
14.4.5 Power Management ..........................................................................................
14.4.5.1 UART Mode Power Management .....................................................................
14.4.5.1.1 Module Power Saving ..............................................................................
14.4.5.1.2 System Power Saving .............................................................................
14.4.5.2 IrDA Mode Power Management (UART3 Only) .....................................................
14.4.5.2.1 Module Power Saving ..............................................................................
14.4.5.2.2 System Power Saving .............................................................................
14.4.5.3 CIR Mode Power Management (UART3 Only) ......................................................
14.4.5.3.1 Module Power Saving ..............................................................................
14.4.5.3.2 System Power Saving .............................................................................
UART/IrDA/CIR Basic Programming Model .........................................................................
14.5.1 UART Programming Model .................................................................................
14.5.1.1 Quick Start ...............................................................................................
14.5.1.1.1 Software Reset .....................................................................................
14.5.1.1.2 FIFOs and DMA Settings ..........................................................................
14.5.1.1.3 Protocol, Baud Rate, and Interrupt Settings ....................................................
14.5.1.2 Hardware and Software Flow Control Configuration ...............................................
14.5.1.2.1 Hardware Flow Control Configuration ...........................................................
14.5.1.2.2 Software Flow Control Configuration ............................................................
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1717
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1717
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1719
1720
1721
1722
1722
1722
1722
1723
1727
1728
1728
1729
1729
1731
1732
1732
1733
1733
1734
1735
1735
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SPRUGR0C – October 2009 – Revised November 2013
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14.6
14.5.2 IrDA Programming Model (UART3 Only) ..................................................................
14.5.2.1 SIR Mode .................................................................................................
14.5.2.1.1 Receive ..............................................................................................
14.5.2.1.2 Transmit .............................................................................................
14.5.2.2 MIR Mode ................................................................................................
14.5.2.2.1 Receive ..............................................................................................
14.5.2.2.2 Transmit .............................................................................................
14.5.2.3 FIR Mode .................................................................................................
14.5.2.3.1 Receive ..............................................................................................
14.5.2.3.2 Transmit .............................................................................................
UART/IrDA/CIR Registers .............................................................................................
14.6.1 UART/IrDA/CIR Register Mapping Summary .............................................................
14.6.2 UART/IrDA/CIR Register Descriptions ....................................................................
14.6.2.1 DLL_REG ................................................................................................
14.6.2.2 RHR_REG ...............................................................................................
14.6.2.3 THR_REG ................................................................................................
14.6.2.4 IER_REG .................................................................................................
14.6.2.4.1 UART Bitfield Details ...............................................................................
14.6.2.4.2 IrDA Bitfield Details .................................................................................
14.6.2.4.3 CIR Bitfield Details .................................................................................
14.6.2.5 DLH_REG ................................................................................................
14.6.2.6 FCR_REG ................................................................................................
14.6.2.7 IIR_REG ..................................................................................................
14.6.2.7.1 UART Bitfield Details ...............................................................................
14.6.2.7.2 IrDA Bitfield Details .................................................................................
14.6.2.7.3 CIR Bitfield Details .................................................................................
14.6.2.8 EFR_REG ................................................................................................
14.6.2.9 LCR_REG ................................................................................................
14.6.2.10 MCR_REG ..............................................................................................
14.6.2.11 XON1_ADDR1_REG ..................................................................................
14.6.2.12 LSR_REG ...............................................................................................
14.6.2.12.1 UART Bitfield Details .............................................................................
14.6.2.12.2 IrDA Bitfield Details ...............................................................................
14.6.2.12.3 CIR Bitfield Details ................................................................................
14.6.2.13 XON2_ADDR2_REG ..................................................................................
14.6.2.14 XOFF1_REG ...........................................................................................
14.6.2.15 TCR_REG ...............................................................................................
14.6.2.16 MSR_REG ..............................................................................................
14.6.2.17 SPR_REG ...............................................................................................
14.6.2.18 XOFF2_REG ...........................................................................................
14.6.2.19 TLR_REG ...............................................................................................
14.6.2.20 MDR1_REG ............................................................................................
14.6.2.21 MDR2_REG ............................................................................................
14.6.2.22 TXFLL_REG ............................................................................................
14.6.2.23 SFLSR_REG ...........................................................................................
14.6.2.24 RESUME_REG .........................................................................................
14.6.2.25 TXFLH_REG ............................................................................................
14.6.2.26 RXFLL_REG ............................................................................................
14.6.2.27 SFREGL_REG .........................................................................................
14.6.2.28 SFREGH_REG .........................................................................................
14.6.2.29 RXFLH_REG ...........................................................................................
14.6.2.30 BLR_REG ...............................................................................................
14.6.2.31 UASR_REG .............................................................................................
SPRUGR0C – October 2009 – Revised November 2013
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Contents
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1758
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1763
1764
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1771
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14.6.2.32
14.6.2.33
14.6.2.34
14.6.2.35
14.6.2.36
14.6.2.37
14.6.2.38
14.6.2.39
15
ACREG_REG ..........................................................................................
SCR_REG ..............................................................................................
SSR_REG ...............................................................................................
EBLR_REG .............................................................................................
SYSC_REG .............................................................................................
SYSS_REG .............................................................................................
WER_REG ..............................................................................................
CFPS_REG .............................................................................................
1788
1790
1791
1792
1793
1794
1795
1796
................................................................................................................................ 1797
High-Speed I2C Controller Overview ................................................................................. 1798
High-Speed I2C Controller Environment ............................................................................. 1800
15.2.1 Multimaster HS I2C Controllers in I2C Mode .............................................................. 1800
15.2.1.1 Multimaster HS I2C Controller Pins for Typical Connections in I2C Mode ....................... 1800
15.2.1.2 I2C Interface Typical Connections ..................................................................... 1800
15.2.1.3 I2C Typical Connection Protocol and Data Format ................................................. 1801
15.2.1.3.1 Serial Data Format ................................................................................. 1801
15.2.1.3.2 Data Validity ......................................................................................... 1801
15.2.1.3.3 Start and Stop Conditions ......................................................................... 1801
15.2.1.3.4 Addressing .......................................................................................... 1802
15.2.1.3.5 Master Transmitter ................................................................................. 1803
15.2.1.3.6 Master Receiver .................................................................................... 1803
15.2.1.3.7 Slave Transmitter ................................................................................... 1803
15.2.1.3.8 Slave Receiver ...................................................................................... 1803
15.2.1.3.9 Bus Arbitration ...................................................................................... 1804
15.2.1.3.10 I2C Clock Generation and Synchronization .................................................... 1804
15.2.2 Multimaster High-Speed I2C Controllers in SCCB Mode ................................................ 1805
15.2.2.1 Multimaster HS I2C Controller Pins for Typical Connections in SCCB Mode ................... 1806
15.2.2.2 SCCB Interface Typical Connections ................................................................. 1807
15.2.2.3 SCCB Typical Connection Protocol and Data Format ............................................. 1808
15.2.2.3.1 Serial Transmission Timing Diagram ............................................................ 1808
15.2.2.3.2 SCCB Transmission Data Formats .............................................................. 1808
15.2.3 High-Speed I2C Controller for Communication With Power Chip(s) ................................... 1809
15.2.3.1 HS I2C Controller I2C4 Pins for Typical Connections .............................................. 1810
15.2.3.2 HS I2C Controller I2C4 Interface Typical Connections ............................................. 1810
15.2.3.3 I2C Typical Connections Protocol and Data Format for I2C4 ...................................... 1812
15.2.3.3.1 Serial Data Format ................................................................................. 1812
15.2.3.3.2 Data Validity ......................................................................................... 1812
15.2.3.3.3 S and P Conditions ................................................................................. 1812
15.2.3.3.4 Addressing .......................................................................................... 1812
15.3 High-Speed I2C Controller Integration ............................................................................... 1813
15.3.1 Clocking, Reset, and Power-Management Scheme ..................................................... 1814
15.3.1.1 Clocks ..................................................................................................... 1814
15.3.1.1.1 Module Clocks ...................................................................................... 1814
15.3.1.2 Power Management .................................................................................... 1815
15.3.1.2.1 Module Power Saving .............................................................................. 1815
15.3.1.2.2 System Power Management ...................................................................... 1815
15.3.1.2.3 Wake-Up Capability ................................................................................ 1816
15.3.1.3 Resets .................................................................................................... 1818
15.3.1.3.1 Hardware Reset .................................................................................... 1818
15.3.1.3.2 Software Reset ..................................................................................... 1818
15.3.1.4 Power Domain ........................................................................................... 1819
15.3.2 Hardware Requests .......................................................................................... 1819
15.3.2.1 DMA Requests .......................................................................................... 1819
I2C
15.1
15.2
34
Contents
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15.4
15.5
15.6
16
15.3.2.2 Interrupt Requests ......................................................................................
High-Speed I2C Controller Functional Description .................................................................
15.4.1 Block Diagram ................................................................................................
15.4.2 Transmit Mode in I2C Mode .................................................................................
15.4.3 Receive Mode in I2C Mode ..................................................................................
15.4.4 FIFO Management ...........................................................................................
15.4.4.1 FIFO Interrupt Mode Operation .......................................................................
15.4.4.2 FIFO Polling Mode Operation .........................................................................
15.4.4.3 FIFO DMA Mode Operation (I2C Mode Only) .......................................................
15.4.4.4 Draining Feature (I2C Mode Only) ....................................................................
15.4.5 Programmable Multislave Channel Feature (I2C Mode Only) ..........................................
15.4.6 Automatic Blocking of the I2C Clock Feature (I2C Mode Only) .........................................
15.4.7 Clocking ........................................................................................................
15.4.8 Noise Filter ....................................................................................................
15.4.9 System Test Mode ...........................................................................................
15.4.10 Write and Read Operations in SCCB Mode .............................................................
15.4.11 Power Chip Communication Operations .................................................................
High-Speed I2C Controller Basic Programming Model ............................................................
15.5.1 Multimaster HS I2C Controller Basic Programming Model in I2C Mode ...............................
15.5.1.1 Main Program ............................................................................................
15.5.1.1.1 Configure the Module Before Enabling the I2C Controller .....................................
15.5.1.1.2 Initialize the I2C Controller .........................................................................
15.5.1.1.3 Configure Slave Address and the Data Control Register .....................................
15.5.1.1.4 Initiate a Transfer ...................................................................................
15.5.1.1.5 Receive Data ........................................................................................
15.5.1.1.6 Transmit Data .......................................................................................
15.5.1.2 Interrupt Subroutine Sequence ........................................................................
15.5.1.3 Programming Flow Diagrams ..........................................................................
15.5.2 High-Speed I2C Controller Basic Programming Model in SCCB Mode ...............................
15.5.2.1 Main Program ............................................................................................
15.5.2.1.1 Configure the Module Before Enabling the I2C Controller .....................................
15.5.2.1.2 Initialize the I2C Controller .........................................................................
15.5.2.1.3 Initiate a Transfer ...................................................................................
15.5.2.1.4 Receive Data ........................................................................................
15.5.2.1.5 Transmit Data .......................................................................................
15.5.2.2 Interrupt Subroutine Sequence ........................................................................
15.5.2.3 Programming Flow Diagrams ..........................................................................
15.5.3 Master Transmitter HS I2C Controller I2C4 Basic Programming Model for Communication With
Power Chips ....................................................................................................
15.5.3.1 Configure the Voltage Controller Registers ..........................................................
15.5.3.2 Configure the Master Transmitter HS I2C Controller I2C4 .........................................
15.5.3.3 Configure the External Power Chip(s) ................................................................
High-Speed I2C Controllers Register Manual .......................................................................
15.6.1 Multimaster HS I2C Controller Register Mapping Summary ............................................
15.6.2 Register Description ..........................................................................................
Multichannel SPI
16.1
16.2
16.3
McSPI
McSPI
16.2.1
16.2.2
McSPI
16.3.1
16.3.2
1819
1822
1822
1822
1823
1823
1823
1825
1825
1827
1827
1827
1828
1829
1829
1830
1830
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1831
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1842
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1849
1849
1849
1849
1850
1850
1851
............................................................................................................ 1871
Overview ........................................................................................................
Environment ....................................................................................................
SPI Interface in Master Mode ...............................................................................
SPI Interface in Slave Mode ................................................................................
Functional Interface ...........................................................................................
Basic McSPI Pins for Master Mode ........................................................................
Basic McSPI Pins for Slave Mode .........................................................................
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Contents
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16.4
16.5
36
16.3.3 Multichannel SPI Protocol and Data Format ..............................................................
16.3.3.1 Transfer Format .........................................................................................
McSPI Integration ......................................................................................................
16.4.1 McSPI Description ............................................................................................
16.4.2 Clocking, Reset, and Power-Management Scheme .....................................................
16.4.2.1 Clocking ..................................................................................................
16.4.2.2 Power Domain ...........................................................................................
16.4.2.3 Hardware Reset .........................................................................................
16.4.2.4 Software Reset ..........................................................................................
16.4.3 Hardware Requests ..........................................................................................
16.4.3.1 DMA Requests ..........................................................................................
16.4.3.2 Interrupt Requests ......................................................................................
16.4.3.3 Wake-Up Requests .....................................................................................
McSPI Functional Description ........................................................................................
16.5.1 McSPI Block Diagram ........................................................................................
16.5.2 Master Mode ..................................................................................................
16.5.2.1 Master Mode Features .................................................................................
16.5.2.2 Master Transmit-and-Receive Mode (Full Duplex) .................................................
16.5.2.3 Master Transmit-Only Mode (Half Duplex) ...........................................................
16.5.2.4 Master Receive-Only Mode (Half Duplex) ...........................................................
16.5.2.5 Single-Channel Master Mode ..........................................................................
16.5.2.5.1 Programming Tips When Switching to Another Channel ......................................
16.5.2.5.2 Force spim_csx Mode .............................................................................
16.5.2.5.3 Turbo Mode .........................................................................................
16.5.2.6 Start Bit Mode ...........................................................................................
16.5.2.7 Chip-Select Timing Control ............................................................................
16.5.2.8 Programmable SPI Clock (spim_clk) .................................................................
16.5.2.8.1 Clock Ratio Granularity ............................................................................
16.5.3 Slave Mode ....................................................................................................
16.5.3.1 Dedicated Resources ...................................................................................
16.5.3.2 Slave Transmit-and-Receive Mode ...................................................................
16.5.3.3 Slave Transmit-Only Mode .............................................................................
16.5.3.4 Slave Receive-Only Mode .............................................................................
16.5.4 FIFO Buffer Management ...................................................................................
16.5.4.1 Buffer Almost Full .......................................................................................
16.5.4.2 Buffer Almost Empty ....................................................................................
16.5.4.3 End of Transfer Management .........................................................................
16.5.5 Interrupts ......................................................................................................
16.5.5.1 Interrupt Events in Master Mode ......................................................................
16.5.5.1.1 TXx_EMPTY ........................................................................................
16.5.5.1.2 TXx_UNDERFLOW ................................................................................
16.5.5.1.3 RXx_ FULL ..........................................................................................
16.5.5.1.4 End Of Word Count ................................................................................
16.5.5.2 Interrupt Events in Slave Mode ........................................................................
16.5.5.2.1 TXx_EMPTY ........................................................................................
16.5.5.2.2 TXx_UNDERFLOW ................................................................................
16.5.5.2.3 RXx_FULL ...........................................................................................
16.5.5.2.4 RX0_OVERFLOW ..................................................................................
16.5.5.2.5 End Of Word Count ................................................................................
16.5.5.3 Interrupt-Driven Operation .............................................................................
16.5.5.4 Polling .....................................................................................................
16.5.6 DMA Requests ................................................................................................
16.5.7 Power Saving Management .................................................................................
Contents
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1904
1905
1905
1905
1905
1906
SPRUGR0C – October 2009 – Revised November 2013
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16.6
16.7
16.8
17
16.5.7.1 Normal Mode ............................................................................................
16.5.7.2 Idle Mode .................................................................................................
16.5.7.2.1 Wake-Up Event in Smart-Idle Mode .............................................................
16.5.7.2.2 Transitions From Smart-Idle Mode to Normal Mode ...........................................
16.5.7.2.3 Force-Idle Mode ....................................................................................
McSPI Basic Programming Model ...................................................................................
16.6.1 Initialization of Modules ......................................................................................
16.6.2 Transfer Procedures without FIFO .........................................................................
16.6.2.1 Common Transfer Procedure ..........................................................................
16.6.2.2 End-of-Transfer Procedure .............................................................................
16.6.2.3 Transmit and Receive Procedure .....................................................................
16.6.2.4 Transmit-Only Procedure ..............................................................................
16.6.2.4.1 Based on Interrupt Requests .....................................................................
16.6.2.4.2 Transmit-Only Based on DMA Write Requests .................................................
16.6.2.5 Receive-Only Procedure ...............................................................................
16.6.2.5.1 Master Normal Receive-Only Procedure ........................................................
16.6.2.5.2 Master Turbo Receive-Only Procedure ..........................................................
16.6.2.5.3 Slave Receive-Only Procedure ...................................................................
16.6.2.6 McSPI Configuration and Operations Example .....................................................
16.6.2.6.1 McSPI Initialization Sequence ....................................................................
16.6.2.6.2 Operations for the First Slave (On Channel 0) .................................................
16.6.2.6.3 Programming in Interrupt Mode ..................................................................
16.6.2.6.4 Operations for the Second Slave (on Channel 1) in Polling Mode ...........................
16.6.3 Transfer Procedures with FIFO .............................................................................
16.6.3.1 Common Transfer Procedure ..........................................................................
16.6.3.2 Transmit-Receive Procedure With Word Count (WCNT≠0) .......................................
16.6.3.3 Transmit-Receive Procedure Without Word Count (WCNT=0) ...................................
16.6.3.4 Transmit-Only Procedure ..............................................................................
16.6.3.5 Receive-Only Procedure With Word Count (WCNT≠0) ............................................
16.6.3.6 Receive-Only Procedure Without Word Count (WCNT=0) ........................................
McSPI Use Cases and Tips ...........................................................................................
16.7.1 How to Configure the McSPI Interface When Connected with an EPSON VGA FlatLink™ 3G
Device ...........................................................................................................
16.7.1.1 Overview .................................................................................................
16.7.1.2 Environment ..............................................................................................
16.7.1.3 Data Path .................................................................................................
16.7.1.4 Programming Flow ......................................................................................
16.7.1.4.1 McSPI Module Configuration ......................................................................
16.7.1.4.2 'SOFT RESET', 'SLEEP OUT' and 'DISPLAY ON' Commands ..............................
16.7.1.4.3 'READ DISPLAY STATUS' Command ...........................................................
McSPI Register Manual ................................................................................................
16.8.1 McSPI Instance Summary ...................................................................................
16.8.2 McSPI Register Summary ...................................................................................
16.8.3 McSPI Register Description .................................................................................
HDQ/1-Wire
17.1
17.2
17.3
1906
1906
1907
1908
1908
1909
1909
1909
1910
1910
1912
1913
1913
1913
1914
1914
1916
1918
1920
1920
1920
1921
1921
1922
1922
1924
1925
1926
1927
1928
1930
1930
1930
1930
1931
1932
1933
1934
1934
1936
1936
1936
1937
.................................................................................................................... 1957
HDQ/1-Wire Overview .................................................................................................
HDQ/1-Wire Environment .............................................................................................
17.2.1 HDQ/1-Wire Functional Interface ...........................................................................
17.2.2 HDQ and 1-Wire (SDQ) Protocols .........................................................................
17.2.2.1 HDQ Protocol Initialization (Default) ..................................................................
17.2.2.2 1-Wire (SDQ) Protocol Initialization ...................................................................
17.2.2.3 Communication Sequence (HDQ and 1-Wire Protocols) ..........................................
HDQ/1-Wire Integration ................................................................................................
SPRUGR0C – October 2009 – Revised November 2013
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Contents
1958
1959
1959
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17.4
17.5
17.6
17.7
18
Multichannel Buffered Serial Port
18.1
18.2
38
17.3.1 Clocking, Reset, and Power Management Scheme .....................................................
17.3.1.1 HDQ/1-Wire Clocks .....................................................................................
17.3.1.2 HDQ/1-Wire Reset Scheme ...........................................................................
17.3.1.3 HDQ/1-Wire Power Domain ...........................................................................
17.3.2 Hardware Requests ..........................................................................................
HDQ/1-Wire Functional Description ..................................................................................
17.4.1 HDQ/1-Wire Block Diagram .................................................................................
17.4.2 HDQ Mode (Default) .........................................................................................
17.4.2.1 HDQ Mode Features ....................................................................................
17.4.2.2 Description ...............................................................................................
17.4.2.3 Single-Bit Mode ..........................................................................................
17.4.2.4 Interrupt Conditions .....................................................................................
17.4.3 1-Wire Mode ..................................................................................................
17.4.3.1 1-Wire Mode Features ..................................................................................
17.4.3.2 Description ...............................................................................................
17.4.3.3 1-Wire Single-Bit Mode Operation ....................................................................
17.4.3.4 Interrupt Conditions .....................................................................................
17.4.3.5 Status Flags ..............................................................................................
17.4.4 Module Power Saving ........................................................................................
17.4.4.1 Autoidle Mode ...........................................................................................
17.4.4.2 Power-Down Mode ......................................................................................
17.4.5 System Power Management and Wakeup ................................................................
HDQ/1-Wire Basic Programming Model .............................................................................
17.5.1 Module Initialization Sequence .............................................................................
17.5.1.1 Mode Selection ..........................................................................................
17.5.1.2 Reset/Initialization .......................................................................................
17.5.2 HDQ Protocol Basic Programming Model .................................................................
17.5.2.1 Write Operation ..........................................................................................
17.5.2.2 Read Operation ..........................................................................................
17.5.3 1-Wire Mode (SDQ) Basic Programming Model .........................................................
17.5.3.1 Write Operation ..........................................................................................
17.5.3.2 Read Operation ..........................................................................................
17.5.3.3 1-Wire Bit Mode Operation .............................................................................
17.5.4 Power Management ..........................................................................................
17.5.4.1 Module Power-Down Mode ............................................................................
17.5.4.2 System Idle Mode .......................................................................................
HDQ/1-Wire Use Cases and Tips ....................................................................................
17.6.1 How to Configure the HDQ/1-Wire when Connected with a BQ27000 Gauge .......................
17.6.1.1 Environment ..............................................................................................
17.6.1.2 Programming Flow ......................................................................................
17.6.1.3 Pad Configuration and HDQ/1-Wire Clock and Power Management ............................
17.6.1.4 HDQ/1-Wire Software Reset ...........................................................................
17.6.1.5 Interrupts Enable ........................................................................................
17.6.1.6 Read and Write Operations ............................................................................
HDQ/1-Wire Register Manual .........................................................................................
17.7.1 HDQ/1-Wire Instance Summary ............................................................................
17.7.2 HDQ/1-Wire Register Mapping Summary .................................................................
17.7.3 HDQ/1-Wire Register Description ..........................................................................
McBSP
18.1.1
18.1.2
McBSP
Contents
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..................................................................................... 1983
Overview .......................................................................................................
McBSP Features .............................................................................................
SIDETONE Core .............................................................................................
Environment ...................................................................................................
1984
1984
1985
1987
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18.3
18.4
18.2.1 McBSP Functions ............................................................................................
18.2.2 McBSP Signals Descriptions ................................................................................
18.2.3 McBSP Functions Description ..............................................................................
18.2.3.1 McBSP Modes ...........................................................................................
18.2.3.2 McBSP Functions .......................................................................................
18.2.3.2.1 McBSP Function 1: Control and Data ...........................................................
18.2.3.2.2 McBSP Function 2: Audio Data ...................................................................
18.2.3.2.3 McBSP Function 3: Voice Data ...................................................................
18.2.4 McBSP Protocols and Data Formats ......................................................................
18.2.4.1 Words, Frames, and Phases Definitions .............................................................
18.2.4.1.1 Words or Channels .................................................................................
18.2.4.1.2 Frames ...............................................................................................
18.2.4.1.3 Phases ...............................................................................................
18.2.4.2 Serial Protocol and Data Formats .....................................................................
18.2.4.2.1 Protocol ..............................................................................................
18.2.4.2.2 Data Format .........................................................................................
18.2.4.3 Audio Protocol and Data Formats .....................................................................
18.2.4.3.1 Protocol ..............................................................................................
18.2.4.3.2 Data Formats ........................................................................................
18.2.4.4 Voice Protocol and Data Formats .....................................................................
18.2.4.4.1 Protocol ..............................................................................................
18.2.4.4.2 Data Formats ........................................................................................
McBSP Integration .....................................................................................................
18.3.1 Signal Source Control ........................................................................................
18.3.1.1 McBSP1 Module (6 Pins Configuration) ..............................................................
18.3.1.2 McBSP2, 3, 4, and 5 modules (4 pins configuration) ...............................................
18.3.2 Clocking, Reset, and Power Management Scheme .....................................................
18.3.2.1 Power Domain ...........................................................................................
18.3.2.2 Clocks .....................................................................................................
18.3.2.2.1 McBSP1 Clocks .....................................................................................
18.3.2.2.2 McBSP2 Clocks .....................................................................................
18.3.2.2.3 McBSP3 Clocks .....................................................................................
18.3.2.2.4 McBSP4 Clocks .....................................................................................
18.3.2.2.5 McBSP5 Clocks .....................................................................................
18.3.2.2.6 SIDETONE Clock ...................................................................................
18.3.2.3 Hardware and Software Reset ........................................................................
18.3.2.4 Power Management ....................................................................................
18.3.2.4.1 McBSP Operating States ..........................................................................
18.3.2.4.2 McBSP Acknowledgment Modes .................................................................
18.3.2.4.3 Wake-Up Capability ................................................................................
18.3.2.4.4 Analysis of the Receiver Smart Idle Behavior ..................................................
18.3.3 Hardware Requests ..........................................................................................
18.3.3.1 DMA Requests ..........................................................................................
18.3.3.2 Interrupt Requests ......................................................................................
18.3.3.2.1 McBSP Interrupt Requests ........................................................................
18.3.3.2.2 SIDETONE_McBSP Interrupt Requests .........................................................
McBSP Functional Description .......................................................................................
18.4.1 Block Diagram ................................................................................................
18.4.2 McBSP Data Transfer Process .............................................................................
18.4.2.1 Data Transfer Process for 8- / 12- / 16- / 20- / 24- / 32-bits Long Words .......................
18.4.2.2 Bit Reordering (Option to Transfer LSB First) .......................................................
18.4.2.3 Clocking and Framing Data ............................................................................
18.4.2.3.1 Clocking ..............................................................................................
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18.4.2.3.2 Serial Words ........................................................................................
18.4.2.3.3 Frames and Frame Synchronization .............................................................
18.4.2.3.4 Detecting Frame-Synchronization Pulses, Even in Reset State .............................
18.4.2.3.5 Ignoring Frame-Synchronization Pulses .........................................................
18.4.2.3.6 Frame Frequency ...................................................................................
18.4.2.3.7 Maximum Frame Frequency ......................................................................
18.4.2.4 Frame Phases (Dual-Phase Frame I2S Support) ...................................................
18.4.2.4.1 Number of Phases, Words, and Bits per Frame ...............................................
18.4.2.4.2 Single-Phase Frame Example ....................................................................
18.4.2.4.3 Dual-Phase Frame Example ......................................................................
18.4.2.5 McBSP Reception .......................................................................................
18.4.2.6 McBSP Transmission ...................................................................................
18.4.2.7 Enable/Disable the Transmit and Receive Processes .............................................
18.4.2.8 MCBSP Data Transfer Mode ..........................................................................
18.4.2.8.1 Transmit Full Cycle Mode .........................................................................
18.4.2.8.2 Transmit Half Cycle Mode .........................................................................
18.4.2.8.3 Receive Full Cycle Mode ..........................................................................
18.4.2.8.4 Receive Half Cycle Mode ..........................................................................
18.4.3 McBSP SRG ..................................................................................................
18.4.3.1 Clock Generation in the SRG ..........................................................................
18.4.3.2 Frame Sync Generation in the SRG ..................................................................
18.4.3.2.1 Choosing the Width of the Frame-sync Pulse ..................................................
18.4.3.2.2 Controlling the Period Between the Starting Edges of Frame Sync Pulses ................
18.4.3.2.3 Keeping FSG Synchronized to an External Clock .............................................
18.4.3.3 Synchronizing SRG Outputs to an External Clock ..................................................
18.4.3.3.1 Operating the Transmitter Synchronously with the Receiver .................................
18.4.3.3.2 Synchronization Examples ........................................................................
18.4.4 McBSP Exception/Error Conditions ........................................................................
18.4.4.1 Introduction ...............................................................................................
18.4.4.2 Overrun in the Receiver ................................................................................
18.4.4.3 Unexpected Receive Frame-sync Pulse .............................................................
18.4.4.3.1 Possible Responses to Receive Frame-sync Pulses ..........................................
18.4.4.3.2 Example of an Unexpected Receive Frame-sync Pulse ......................................
18.4.4.3.3 Preventing Unexpected Receive Frame-sync Pulses .........................................
18.4.4.4 Underflow in the Receiver ..............................................................................
18.4.4.5 Underflow in the Transmitter ...........................................................................
18.4.4.6 Unexpected Transmit Frame-sync Pulse ............................................................
18.4.4.6.1 Possible Responses to Transmit Frame-sync Pulses .........................................
18.4.4.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse ............................
18.4.4.6.3 Preventing Unexpected Transmit Frame-sync Pulses .........................................
18.4.4.7 Overflow in the Transmitter ............................................................................
18.4.5 McBSP DMA Configuration .................................................................................
18.4.6 Multichannel Selection Modes ..............................................................................
18.4.6.1 Channels, Blocks, and Partitions ......................................................................
18.4.6.2 Multichannel Selection ..................................................................................
18.4.6.3 Configuring a Frame for Multichannel Selection ....................................................
18.4.6.4 Using Eight Partitions ...................................................................................
18.4.6.5 Receive Multichannel Selection Mode ................................................................
18.4.6.6 Using Two Partitions (Legacy Only) ..................................................................
18.4.6.7 Transmit Multichannel Selection Modes .............................................................
18.4.6.7.1 Disabling/Enabling Versus Masking/Unmasking ...............................................
18.4.6.7.2 Activity on McBSP Pins for Different Values of XMCM ........................................
18.4.7 SIDETONE Mode (ALP) .....................................................................................
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SPRUGR0C – October 2009 – Revised November 2013
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18.5
18.6
19
18.4.7.1 Introduction ...............................................................................................
18.4.7.2 SIDETONE Interface ....................................................................................
18.4.7.3 Data Processing Path ..................................................................................
18.4.7.4 Data Processing .........................................................................................
18.4.7.4.1 Filtering ..............................................................................................
18.4.7.4.2 Applying Gain .......................................................................................
18.4.7.4.3 Enabling SIDETONE ...............................................................................
18.4.7.4.4 FIR Accuracy ........................................................................................
18.4.7.5 Interrupt Operation ......................................................................................
McBSP Basic Programming Model ..................................................................................
18.5.1 McBSP Core ..................................................................................................
18.5.1.1 McBSP Initialization Procedure ........................................................................
18.5.1.2 Reset and Initialization Procedure for the Sample Rate Generator ..............................
18.5.1.3 Data Transfer DMA Request Configuration ..........................................................
18.5.1.4 Interrupt Configuration ..................................................................................
18.5.1.4.1 L4-Compliant Interrupt Line .......................................................................
18.5.1.4.2 Legacy Interrupt Line ...............................................................................
18.5.1.5 Receiver Configuration .................................................................................
18.5.1.5.1 Resetting (Step 1) and Enabling (Step 3) the Receiver .......................................
18.5.1.5.2 Programming the McBSP Registers for the Desired Receiver Configuration (Step 2) ....
18.5.1.6 Transmitter Configuration ..............................................................................
18.5.1.6.1 Resetting (Step 1) and Enabling (Step 3) the Transmitter ....................................
18.5.1.6.2 Programming the McBSP Registers for the Desired Transmitter Operation (Step 2) .....
18.5.1.7 General-Purpose I/O on the McBSP Pins (Legacy Only) ..........................................
18.5.1.8 Data Packing Examples ................................................................................
18.5.1.8.1 Data Packing Using Frame Length and Word Length .........................................
18.5.1.8.2 Data Packing Using Word Length and the Frame-Sync Ignore Function ...................
18.5.2 SIDETONE Feature ..........................................................................................
18.5.2.1 SIDETONE Activation Procedure .....................................................................
18.5.2.2 SIDETONE Initialization Procedure ...................................................................
18.5.2.3 SIDETONE FIR Coefficients Writing ..................................................................
18.5.2.4 SIDETONE FIR Coefficients Reading ................................................................
McBSP Register Manual ..............................................................................................
18.6.1 McBSP Register Mapping Summary .......................................................................
18.6.2 SIDETONE Register Mapping Summary ..................................................................
18.6.3 McBSP Register Description ................................................................................
18.6.4 SIDETONE Register Description ...........................................................................
MMC/SD/SDIO Card Interface
19.1
19.2
19.3
2048
2048
2050
2051
2051
2052
2052
2052
2052
2053
2053
2053
2056
2059
2059
2059
2060
2061
2061
2062
2070
2070
2071
2077
2078
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2079
2080
2080
2081
2081
2081
2082
2082
2087
2088
2135
........................................................................................... 2141
MMC/SD/SDIO Overview ..............................................................................................
19.1.1 MMC/SD/SDIO Features ....................................................................................
MMC/SD/SDIO Environment ..........................................................................................
19.2.1 MMC/SD/SDIO Connected to an MMC, an SD, or an SDIO Card .....................................
19.2.2 MMC/SD/SDIO Connected to an MMC, an SD, or an SDIO Card Through an External
Transceiver Device ............................................................................................
19.2.3 MMC/SD/SDIO Functional Interfaces ......................................................................
19.2.3.1 Basic MMC/SD/SDIOi Pins Without External Transceiver .........................................
19.2.3.2 Basic MMC/SD/SDIO2 Pins with External Transceiver ............................................
19.2.3.3 MMC/SD/SDIO Protocol and Data Format ...........................................................
19.2.3.3.1 Protocol ..............................................................................................
19.2.3.3.2 Data Format .........................................................................................
MMC/SD/SDIO Integration ............................................................................................
19.3.1 Clocking, Reset, and Power-Management Scheme .....................................................
19.3.1.1 Clocks .....................................................................................................
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19.4
19.5
19.6
42
19.3.1.1.1 Module Clocks ......................................................................................
19.3.1.1.2 Power Management ................................................................................
19.3.1.2 Resets ....................................................................................................
19.3.1.2.1 Hardware Reset ....................................................................................
19.3.1.2.2 Software Reset .....................................................................................
19.3.1.3 Power Domain ...........................................................................................
19.3.2 Hardware Requests ..........................................................................................
19.3.2.1 DMA Requests ..........................................................................................
19.3.2.1.1 DMA Receive Mode ................................................................................
19.3.2.1.2 DMA Transmit Mode ...............................................................................
19.3.2.2 Interrupt Requests ......................................................................................
19.3.2.2.1 Interrupt-Driven Operation .........................................................................
19.3.2.2.2 Polling ................................................................................................
MMC/SD/SDIO Functional Description ..............................................................................
19.4.1 Description ....................................................................................................
19.4.2 Mode Selection ...............................................................................................
19.4.3 Buffer Management ..........................................................................................
19.4.3.1 Data Buffer ...............................................................................................
19.4.3.1.1 Data Buffer Status ..................................................................................
19.4.4 Transfer Process .............................................................................................
19.4.4.1 Different Types of Commands .........................................................................
19.4.4.2 Different Types of Responses .........................................................................
19.4.5 Transfer or Command Status and Errors Reporting .....................................................
19.4.6 Transfer Stop .................................................................................................
19.4.7 MMC CE-ATA Command Completion Disable Management ...........................................
MMC/SD/SDIO Basic Programming Model .........................................................................
19.5.1 MMC/SD/SDIO Host Controller Initialization Flow .......................................................
19.5.1.1 Enable Interface and Functional clock for MMC Controller ........................................
19.5.1.2 MMCHS Soft Reset Flow ...............................................................................
19.5.1.3 Set MMCHS Default Capabilities ......................................................................
19.5.1.4 Wake-Up Configuration .................................................................................
19.5.1.5 MMC Host and Bus Configuration ....................................................................
19.5.2 Basic Operations for MMC/SD/SDIO Host Controller ...................................................
19.5.2.1 Card Detection, Identification, and Selection ........................................................
19.5.2.2 Read/Write Transfer Flow in DMA Mode with Interrupt ............................................
19.5.2.3 Read/Write Transfer Flow in DMA Mode with Polling ..............................................
19.5.2.4 Read/Write Transfer Flow without DMA with Polling ...............................................
19.5.2.5 Read/Write Transfer Flow in CE-ATA Mode .........................................................
19.5.2.6 Suspend-Resume Flow .................................................................................
19.5.2.6.1 Suspend Flow .......................................................................................
19.5.2.6.2 Resume Flow .......................................................................................
19.5.2.7 Basic Operations - Steps Detailed ....................................................................
19.5.2.7.1 Command Transfer Flow ..........................................................................
19.5.2.7.2 MMCHS Clock Frequency Change ..............................................................
19.5.3 MMC/SD/SDIO1 Bus Voltage Selection ...................................................................
MMC/SD/SDIO Use Cases and Tips ................................................................................
19.6.1 MMCHS Controller Usage ...................................................................................
19.6.1.1 Overview .................................................................................................
19.6.1.2 Environment ..............................................................................................
19.6.1.2.1 Command and Data Transfer Formats ..........................................................
19.6.1.3 Programming Flow ......................................................................................
19.6.1.3.1 Initial Configuration .................................................................................
19.6.1.3.2 MMC Card Identification ...........................................................................
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SPRUGR0C – October 2009 – Revised November 2013
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19.7
20
19.6.1.3.3 MMC Bus Setting Change After Card Identification ............................................
19.6.1.3.4 Reading the CSD Register of a MMC Card .....................................................
19.6.1.3.5 MMC Write Transfer ................................................................................
19.6.1.3.6 MMC Read Transfer ...............................................................................
19.6.1.3.7 Dealing with High Capacity Cards ................................................................
MMC/SD/SDIO Register Manual .....................................................................................
19.7.1 MMC/SD/SDIO Instance Summary ........................................................................
19.7.2 MMC/SD/SDIO Registers Mapping Summary ............................................................
Universal Serial Bus (USB)
20.1
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.............................................................................................. 2236
High-Speed USB OTG Controller ....................................................................................
20.1.1 Introduction ....................................................................................................
20.1.1.1 Purpose of the Peripheral ..............................................................................
20.1.2 Features Supported ..........................................................................................
20.1.2.1 Features Not Supported ................................................................................
20.1.3 Functional Description .......................................................................................
20.1.3.1 Compliance to Standards ..............................................................................
20.1.3.2 Functional Operation ....................................................................................
20.1.3.2.1 Overview .............................................................................................
20.1.3.2.2 Mentor Core .........................................................................................
20.1.3.2.3 USB OTG PHY .....................................................................................
20.1.3.2.4 CPPI 4.1 DMA Controller ..........................................................................
20.1.3.2.5 CPPI DMA Scheduler ..............................................................................
20.1.3.2.6 CP_INTD ............................................................................................
20.1.3.2.7 CPPI Queue Manager .............................................................................
20.1.3.2.8 USB20OTG_F Packet Processing Unit ..........................................................
20.1.3.2.9 USB20OTG_F VBUSP to AHB (V2A) ...........................................................
20.1.3.2.10 USB20OTG_F Transfer (XFER) DMA .........................................................
20.1.3.2.11 PDR Interrupts .....................................................................................
20.1.3.2.12 VBUSP Retiming ..................................................................................
20.1.3.2.13 PDR Clocking and IP Generics .................................................................
20.1.3.2.14 Switched Central Resource (SCR) .............................................................
20.1.4 Interrupt Conditions ..........................................................................................
20.1.4.1 CPU Interrupts ...........................................................................................
20.1.4.2 Interrupt Description ....................................................................................
20.1.4.2.1 USB Core PDR Interrupts .........................................................................
20.1.4.2.2 USB Core Non-PDR Interrupts ...................................................................
20.1.4.2.3 Completion Queue Interrupts .....................................................................
20.1.4.3 Interrupt Condition Control .............................................................................
20.1.4.3.1 USB Core Interrupts ................................................................................
20.1.4.4 Interrupt Handling .......................................................................................
20.1.4.4.1 USB Core Interrupts ................................................................................
20.1.5 I/O Description ................................................................................................
20.1.5.1 Module I/O ...............................................................................................
20.1.5.1.1 Reset Interface ......................................................................................
20.1.5.1.2 Queue Manager Event Interface .................................................................
20.1.5.1.3 USB Interface .......................................................................................
20.1.5.1.4 Interrupt Interface ...................................................................................
20.1.5.2 External Pins .............................................................................................
20.1.5.2.1 External Pin Table ..................................................................................
20.1.6 Teardown Procedure .........................................................................................
20.1.6.1 Transmit Teardown .....................................................................................
20.1.6.2 Receive Teardown ......................................................................................
20.1.7 USB Bus Reset Handling ....................................................................................
SPRUGR0C – October 2009 – Revised November 2013
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20.1.8 VBUSP Slave Port Bursting .................................................................................
20.1.9 Core Register Type Mixing ..................................................................................
20.1.10 Zero Byte Packet Parameters .............................................................................
20.1.11 Interrupt Usage ..............................................................................................
20.1.12 Powerdown Handling .......................................................................................
20.1.13 Clock Stop and Emulation Suspend ......................................................................
20.1.14 Registers .....................................................................................................
20.1.14.1 USB Control Register (Base Address + 0x0004) ..................................................
20.1.14.2 USB Status Register (Base Address + 0x0008) ...................................................
20.1.14.3 USB Auto Req Register (Base Address + 0x0014) ...............................................
20.1.14.4 USB Teardown Register (Base Address + 0x001C) ..............................................
20.1.14.5 USB Endpoint Interrupt Source Register (Base Address + 0x0020) ............................
20.1.14.6 USB Endpoint Interrupt Source Set Register (Base Address + 0x0024) .......................
20.1.14.7 USB Endpoint Interrupt Source Clear Register (Base Address + 0x0028) .....................
20.1.14.8 USB Endpoint Interrupt Mask Register (Base Address + 0x002C) ..............................
20.1.14.9 USB Endpoint Interrupt Mask Set Register (Base Address + 0x0030) .........................
20.1.14.10 USB Endpoint Interrupt Mask Clear Register (Base Address + 0x0034) .....................
20.1.14.11 USB Endpoint Interrupt Source Masked Register (Base Address + 0x0038) ................
20.1.14.12 USB Core Interrupt Source Register (Base Address + 0x0040) ...............................
20.1.14.13 USB Core Interrupt Source Set Register (Base Address + 0x0044) ..........................
20.1.14.14 USB Core Interrupt Source Clear Register (Base Address + 0x0048) ........................
20.1.14.15 USB Core Interrupt Mask Register (Base Address + 0x004C) .................................
20.1.14.16 USB Core Interrupt Mask Set Register (Base Address + 0x0050) ............................
20.1.14.17 USB Core Interrupt Mask Clear Register (Base Address + 0x0054) ..........................
20.1.14.18 USB Core Interrupt Source Masked Register (Base Address + 0x0058) .....................
20.1.14.19 USB End of Interrupt Register (Base Address + 0x0060) .......................................
20.1.14.20 USB MOP/SOP Interrupt Enable Register (Base Address + 0x0064) .........................
20.1.14.21 USB Tx Mode Register (Base Address + 0x0070) ...............................................
20.1.14.22 USB Rx Mode Register (Base Address + 0x0074) ..............................................
20.1.14.23 USB EP Count Mode Register (Base Address + 0x0078) ......................................
20.1.14.24 USB Generic RNDIS EP N Size Register (Base Address + 0x0080) .........................
20.1.14.25 USB Queue Interrupt Threshold Enable Register (Base Address + 0x00C0) ................
20.1.14.26 USB Queue Threshold Register 0 (Base Address + 0x00C4) ..................................
20.1.14.27 USB Interrupt Clear Register 0 (Base Address + 0x00C8) .....................................
20.1.14.28 USB Queue Threshold Register 1 (Base Address + 0x00D4) ..................................
20.1.14.29 USB Interrupt Clear Register 1 (Base Address + 0x00D8) .....................................
20.1.14.30 USB Mentor Core Registers/FIFOs (Base Address + 0x400 – 0x59C) .......................
20.1.14.30.1 CDMA Tx Channel N Global Configuration Register (Base Address + 0x0800 + 32*N)
.........................................................................................................
2251
2251
2251
2252
2252
2252
2253
2256
2257
2258
2261
2262
2262
2263
2263
2264
2264
2265
2265
2266
2266
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2267
2268
2268
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2269
2270
2272
2274
2276
2276
2277
2277
2278
2278
2279
2279
20.1.14.30.2 CDMA Rx Channel N Global Configuration Register (Base Address + 0x0808 + 32*N)
......................................................................................................... 2280
20.1.14.30.3 CDMA Rx Channel N Host Packet Configuration Register A (Base Address + 0x080C +
32*N) ................................................................................................. 2282
20.1.14.30.4 CDMA Rx Channel N Host Packet Configuration Register B (Base Address + 0x0810 +
32*N) ................................................................................................. 2283
20.1.14.30.5 CDMA Scheduler Control Register (Base Address + 0x0C00) ............................ 2284
20.1.14.30.6 CDMA Scheduler Table Word N Registers (Base Address + 0x0D00:0DC00 + 4*N) .. 2285
20.1.14.31 INTD Revision Register (Base Address + 0x3000) .............................................. 2287
20.1.14.32 INTD EOI Register (Base Address + 0x3010) .................................................... 2288
20.1.14.33 INTD EOI Interrupt Vector Register (Base Address + 0x3014) ................................ 2289
20.1.14.34 INTD Status Register 0 (Base Address + 0x3200) ............................................... 2290
20.1.14.35 INTD Status Register 1 (Base Address + 0x3204) ............................................... 2291
20.1.14.36 INTD Status Register 2 (Base Address + 0x3208) ............................................... 2292
20.1.14.37 INTD Status Register 3 (Base Address + 0x320C) .............................................. 2295
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20.2
20.1.14.38 INTD Status Clear Register 0 (Base Address + 0x280) .........................................
20.1.14.39 Queue Manager Revision Register (0x4000) .....................................................
20.1.14.40 Queue Manager Queue Diversion Register (0x4008) ...........................................
20.1.14.41 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (0x4020) .............
20.1.14.42 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (0x4024) .............
20.1.14.43 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (0x4028) .............
20.1.14.44 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (0x402c) ..............
20.1.14.45 Queue Manager Free Descriptor/Buffer Starvation Count Register 4 (0x4030) .............
20.1.14.46 Queue Manager Free Descriptor/Buffer Starvation Count Register 5 (0x4034) .............
20.1.14.47 Queue Manager Free Descriptor/Buffer Starvation Count Register 6 (0x4038) .............
20.1.14.48 Queue Manager Free Descriptor/Buffer Starvation Count Register 7 (0x403C) .............
20.1.14.49 Queue Manager Linking RAM Region 0 Base Address Register (0x4080) ...................
20.1.14.50 Queue Manager Linking RAM Region 0 Size Register (0x4084) ..............................
20.1.14.51 Queue Manager Linking RAM Region 1 Base Address Register (0x4088) ...................
20.1.14.52 Queue Manager Queue Pending Register 0 (0x4090) ..........................................
20.1.14.53 Queue Manager Queue Pending Register 1 (0x4094) ..........................................
20.1.14.54 Queue Manager Queue Pending Register 2 (0x4098) ..........................................
20.1.14.55 Queue Manager Memory Region R Base Address Register (0x5000 + 16xR) ..............
20.1.14.56 Queue Manager Memory Region R Control Register (0x5000 + 16xR + 4) ..................
20.1.14.57 Queue Manager Queue N Register A (0x6000 + 16xN) ........................................
20.1.14.58 Queue Manager Queue N Register B (0x6000 + 16xN + 4) ....................................
20.1.14.59 Queue Manager Queue N Register C (0x6000 + 16xN + 8) ...................................
20.1.14.60 Queue Manager Queue N Register D (0x6000 + 16xN + C) ...................................
20.1.14.61 Queue Manager Queue N Status Register A (0x6800 + 16xN) ................................
20.1.14.62 Queue Manager Queue N Status Register B (0x6800 + 16xN + 4) ...........................
20.1.14.63 Queue Manager Queue N Status Register C (0x6800 + 16xN + 8) ...........................
High-Speed USB Host Subsystem ...................................................................................
20.2.1 High-Speed USB Host Subsystem Overview .............................................................
20.2.1.1 Main Features ...........................................................................................
20.2.2 High-Speed USB Host Subsystem Environment .........................................................
20.2.2.1 Standard USB Implementation: Transceiver Connection ..........................................
20.2.2.2 TLL Connection ..........................................................................................
20.2.2.3 ULPI Interfaces ..........................................................................................
20.2.2.3.1 Transceiver Interface Configurations ............................................................
20.2.2.3.2 TLL Configurations .................................................................................
20.2.2.3.3 High-Speed USB Host Subsystem Functional Interfaces .....................................
20.2.2.4 Serial Interfaces .........................................................................................
20.2.2.4.1 Encoding in Serial Mode ...........................................................................
20.2.2.4.2 Sideband Signals for Serial Modes ..............................................................
20.2.2.4.3 Transceiver Interface Configurations ............................................................
20.2.2.4.4 TLL Configurations .................................................................................
20.2.2.4.5 High-Speed USB Host Subsystem Interface Description .....................................
20.2.3 High-Speed USB Host Subsystem Integration ...........................................................
20.2.3.1 Reset, Clocking, and Power-Management Scheme ................................................
20.2.3.1.1 High-Speed USB Host Subsystem Resets ......................................................
20.2.3.1.2 High-Speed USB Host Subsystem Clocks ......................................................
20.2.3.1.3 Power-Management Scheme .....................................................................
20.2.3.2 Hardware Requests .....................................................................................
20.2.3.2.1 Interrupt Requests ..................................................................................
20.2.3.2.2 IDLE Handshake Protocol .........................................................................
20.2.3.2.3 MSTANDBY Handshake Protocol ................................................................
20.2.3.2.4 Wake-Up Request ..................................................................................
20.2.4 High-Speed USB Host Subsystem Functional Description .............................................
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20.2.4.1 High-Speed USB Host Controller Functionality .....................................................
20.2.4.1.1 High-Speed USB Host Controller Architecture .................................................
20.2.4.1.2 OHCI Implementation Specifications .............................................................
20.2.4.1.3 UTMI Ports ..........................................................................................
20.2.4.1.4 ULPI Ports ...........................................................................................
20.2.4.1.5 Port Status ...........................................................................................
20.2.4.1.6 Save and Restore ..................................................................................
20.2.4.1.7 Burst Control ........................................................................................
20.2.4.2 USBTLL Module Functionality .........................................................................
20.2.4.2.1 Channels and Ports ................................................................................
20.2.4.2.2 Channel Architecture ...............................................................................
20.2.4.2.3 Channel Configuration .............................................................................
20.2.4.2.4 VBUS Management and Emulations .............................................................
20.2.4.2.5 Multimode Serial Port ..............................................................................
20.2.4.2.6 Attach/Connect Emulation for Serial TLL Modes ...............................................
20.2.4.2.7 Save and Restore ..................................................................................
20.2.5 High-Speed USB Host Subsystem Basic Programming Model ........................................
20.2.5.1 Selecting and Configuring USB Connectivity ........................................................
20.2.5.1.1 ULPI Interface Selection ...........................................................................
20.2.5.1.2 Serial Interface Selection ..........................................................................
20.2.5.2 USBTLL Registers ......................................................................................
20.2.5.2.1 TLL Control and Status Registers ................................................................
20.2.5.2.2 ULPI PHY-Side Registers .........................................................................
20.2.6 High-Speed USB Host Subsystem Registers .............................................................
20.2.6.1 USBTLL ULPI PHY-Side Register Space ............................................................
20.2.6.2 L4-Core Interconnect Register Space ................................................................
20.2.6.3 High-Speed USB Host Subsystem Register Mapping Summary .................................
20.2.6.4 USBTLL Register Descriptions ........................................................................
20.2.6.4.1 USBTLL_REVISION ...............................................................................
20.2.6.4.2 USBTLL_SYSCONFIG ............................................................................
20.2.6.4.3 USBTLL_SYSSTATUS ............................................................................
20.2.6.4.4 USBTLL_IRQSTATUS .............................................................................
20.2.6.4.5 USBTLL_IRQENABLE .............................................................................
20.2.6.4.6 TLL_SHARED_CONF .............................................................................
20.2.6.4.7 TLL_CHANNEL_CONF_i ..........................................................................
20.2.6.4.8 ULPI_VENDOR_ID_LO_i ..........................................................................
20.2.6.4.9 ULPI_VENDOR_ID_HI_i ..........................................................................
20.2.6.4.10 ULPI_PRODUCT_ID_LO_i ......................................................................
20.2.6.4.11 ULPI_PRODUCT_ID_HI_i .......................................................................
20.2.6.4.12 ULPI_FUNCTION_CTRL_i ......................................................................
20.2.6.4.13 ULPI_FUNCTION_CTRL_SET_i ................................................................
20.2.6.4.14 ULPI_FUNCTION_CTRL_CLR_i ................................................................
20.2.6.4.15 ULPI_INTERFACE_CTRL_i .....................................................................
20.2.6.4.16 ULPI_INTERFACE_CTRL_SET_i ..............................................................
20.2.6.4.17 ULPI_INTERFACE_CTRL_CLR_i ..............................................................
20.2.6.4.18 ULPI_OTG_CTRL_i ...............................................................................
20.2.6.4.19 ULPI_OTG_CTRL_SET_i ........................................................................
20.2.6.4.20 ULPI_OTG_CTRL_CLR_i ........................................................................
20.2.6.4.21 ULPI_USB_INT_EN_RISE_i ....................................................................
20.2.6.4.22 ULPI_USB_INT_EN_RISE_SET_i ..............................................................
20.2.6.4.23 ULPI_USB_INT_EN_RISE_CLR_i ..............................................................
20.2.6.4.24 ULPI_USB_INT_EN_FALL_i ....................................................................
20.2.6.4.25 ULPI_USB_INT_EN_FALL_SET_i ..............................................................
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20.2.6.4.26 ULPI_USB_INT_EN_FALL_CLR_i .............................................................
20.2.6.4.27 ULPI_USB_INT_STATUS_i .....................................................................
20.2.6.4.28 ULPI_USB_INT_LATCH_i .......................................................................
20.2.6.4.29 ULPI_DEBUG_i ...................................................................................
20.2.6.4.30 ULPI_SCRATCH_REGISTER_i .................................................................
20.2.6.4.31 ULPI_SCRATCH_REGISTER_SET_i ..........................................................
20.2.6.4.32 ULPI_SCRATCH_REGISTER_CLR_i ..........................................................
20.2.6.4.33 ULPI_EXTENDED_SET_ACCESS_i ...........................................................
20.2.6.4.34 ULPI_UTMI_VCONTROL_EN_i .................................................................
20.2.6.4.35 ULPI_UTMI_VCONTROL_EN_SET_i ..........................................................
20.2.6.4.36 ULPI_UTMI_VCONTROL_EN_CLR_i ..........................................................
20.2.6.4.37 ULPI_UTMI_VCONTROL_STATUS_i ..........................................................
20.2.6.4.38 ULPI_UTMI_VCONTROL_LATCH_i ...........................................................
20.2.6.4.39 ULPI_UTMI_VSTATUS_i ........................................................................
20.2.6.4.40 ULPI_UTMI_VSTATUS_SET_i ..................................................................
20.2.6.4.41 ULPI_UTMI_VSTATUS_CLR_i .................................................................
20.2.6.4.42 ULPI_USB_INT_LATCH_NOCLR_i ............................................................
20.2.6.4.43 ULPI_VENDOR_INT_EN_i ......................................................................
20.2.6.4.44 ULPI_VENDOR_INT_EN_SET_i ................................................................
20.2.6.4.45 ULPI_VENDOR_INT_EN_CLR_i ...............................................................
20.2.6.4.46 ULPI_VENDOR_INT_STATUS_i ...............................................................
20.2.6.4.47 ULPI_VENDOR_INT_LATCH_i .................................................................
20.2.6.5 UHH_CONFIG Register Descriptions ................................................................
20.2.6.5.1 UHH_REVISION ....................................................................................
20.2.6.5.2 UHH_SYSCONFIG .................................................................................
20.2.6.5.3 UHH_SYSSTATUS .................................................................................
20.2.6.5.4 UHH_HOSTCONFIG ...............................................................................
20.2.6.5.5 UHH_DEBUG_CSR ................................................................................
20.2.6.6 OHCI Register Descriptions ...........................................................................
20.2.6.6.1 HCREVISION .......................................................................................
20.2.6.6.2 HCCONTROL .......................................................................................
20.2.6.6.3 HCCOMMANDSTATUS ...........................................................................
20.2.6.6.4 HCINTERRUPTSTATUS ..........................................................................
20.2.6.6.5 HCINTERRUPTENABLE ..........................................................................
20.2.6.6.6 HCINTERRUPTDISABLE .........................................................................
20.2.6.6.7 HCHCCA ............................................................................................
20.2.6.6.8 HCPERIODCURRENTED .........................................................................
20.2.6.6.9 HCCONTROLHEADED ............................................................................
20.2.6.6.10 HCCONTROLCURRENTED ....................................................................
20.2.6.6.11 HCBULKHEADED ................................................................................
20.2.6.6.12 HCBULKCURRENTED ...........................................................................
20.2.6.6.13 HCDONEHEAD ...................................................................................
20.2.6.6.14 HCFMINTERVAL ..................................................................................
20.2.6.6.15 HCFMREMAINING ...............................................................................
20.2.6.6.16 HCFMNUMBER ...................................................................................
20.2.6.6.17 HCPERIODICSTART .............................................................................
20.2.6.6.18 HCLSTHRESHOLD ...............................................................................
20.2.6.6.19 HCRHDESCRIPTORA ...........................................................................
20.2.6.6.20 HCRHDESCRIPTORB ...........................................................................
20.2.6.6.21 HCRHSTATUS ....................................................................................
20.2.6.6.22 HCRHPORTSTATUS_1 ..........................................................................
20.2.6.6.23 HCRHPORTSTATUS_2 ..........................................................................
20.2.6.6.24 HCRHPORTSTATUS_3 ..........................................................................
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20.2.6.7 EHCI Register Descriptions ............................................................................
20.2.6.7.1 HCCAPBASE .......................................................................................
20.2.6.7.2 HCSPARAMS .......................................................................................
20.2.6.7.3 HCCPARAMS .......................................................................................
20.2.6.7.4 USBCMD ............................................................................................
20.2.6.7.5 USBSTS .............................................................................................
20.2.6.7.6 USBINTR ............................................................................................
20.2.6.7.7 FRINDEX ............................................................................................
20.2.6.7.8 CTRLDSSEGMENT ................................................................................
20.2.6.7.9 PERIODICLISTBASE ..............................................................................
20.2.6.7.10 ASYNCLISTADDR ................................................................................
20.2.6.7.11 CONFIGFLAG .....................................................................................
20.2.6.7.12 PORTSC_i .........................................................................................
20.2.6.7.13 INSNREG00 .......................................................................................
20.2.6.7.14 INSNREG01 .......................................................................................
20.2.6.7.15 INSNREG02 .......................................................................................
20.2.6.7.16 INSNREG03 .......................................................................................
20.2.6.7.17 INSNREG04 .......................................................................................
20.2.6.7.18 INSNREG05_UTMI ...............................................................................
20.2.6.7.19 INSNREG05_ULPI ................................................................................
21
General-Purpose Interface
21.1
21.2
21.3
21.4
21.5
48
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General-Purpose Interface Overview ................................................................................
21.1.1 Global Features ...............................................................................................
General-Purpose Interface Environment ............................................................................
21.2.1 GPIO as a Keyboard Interface ..............................................................................
21.2.2 General-Purpose Interface Functional Interfaces ........................................................
21.2.2.1 General-Purpose Interface Pins .......................................................................
General-Purpose Interface Integration ...............................................................................
21.3.1 Description ....................................................................................................
21.3.1.1 Clocking, Reset, and Power-Management Scheme ................................................
21.3.1.1.1 Clocking ..............................................................................................
21.3.1.1.2 Reset .................................................................................................
21.3.1.1.3 Power Domain ......................................................................................
21.3.1.1.4 Power Management ................................................................................
21.3.1.2 Hardware Requests .....................................................................................
21.3.1.2.1 Interrupt Requests ..................................................................................
General-Purpose Interface Functional Description .................................................................
21.4.1 Interrupt and Wake-Up Features ...........................................................................
21.4.1.1 Synchronous Path: Interrupt Request Generation ..................................................
21.4.1.2 Asynchronous Path: Wake-Up Request Generation ...............................................
21.4.1.3 Interrupt (or Wake-Up) Line Release .................................................................
General-Purpose Interface Basic Programming Model ............................................................
21.5.1 Power Saving by Grouping the Edge/Level Detection ...................................................
21.5.2 Set-and-Clear Instructions ..................................................................................
21.5.2.1 Description ...............................................................................................
21.5.2.2 Clear Instruction .........................................................................................
21.5.2.2.1 Clear Registers Addresses ........................................................................
21.5.2.2.2 Clear Instruction Example .........................................................................
21.5.2.3 Set Instruction ...........................................................................................
21.5.2.3.1 Set Registers Addresses ..........................................................................
21.5.2.3.2 Set Instruction Example ...........................................................................
21.5.3 Interrupt and Wakeup ........................................................................................
21.5.3.1 Involved Configuration Registers ......................................................................
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21.6
22
21.5.3.2 Description ...............................................................................................
21.5.4 Data Input (Capture)/Output (Drive) .......................................................................
21.5.5 Debouncing Time .............................................................................................
General-Purpose Interface Register Manual ........................................................................
21.6.1 General-Purpose Interface Register Mapping Summary ................................................
21.6.2 Register Descriptions ........................................................................................
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module
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Introduction ..............................................................................................................
22.1.1 Purpose of the Peripheral ...................................................................................
22.1.2 Features .......................................................................................................
22.1.3 Functional Block Diagram ...................................................................................
22.1.4 Industry Standard(s) Compliance Statement .............................................................
Architecture ..............................................................................................................
22.2.1 Clock Control ..................................................................................................
22.2.2 Memory Map ..................................................................................................
22.2.2.1 CPPI Descriptors ........................................................................................
22.2.2.2 EMAC Subsystem Module .............................................................................
22.2.2.3 EMAC Module ...........................................................................................
22.2.2.4 MDIO Module ............................................................................................
22.2.3 Signal Descriptions ...........................................................................................
22.2.3.1 RMII Receive (RX) ......................................................................................
22.2.3.2 RMII Transmit (TX) ......................................................................................
22.2.3.3 Reduced Media Independent Interface (RMII) Connections ......................................
22.2.4 Ethernet Protocol Overview .................................................................................
22.2.4.1 Ethernet Frame Format .................................................................................
22.2.4.2 Ethernet’s Multiple Access Protocol ..................................................................
22.2.5 Programming Interface of Packet Descriptors ............................................................
22.2.5.1 CPPI Packet Buffer Descriptors .......................................................................
22.2.5.2 Transmit and Receive Descriptor Queues ...........................................................
22.2.5.3 Transmit and Receive EMAC Interrupts ..............................................................
22.2.5.4 CPPI Transmit Buffer Descriptor Format .............................................................
22.2.5.4.1 Next Descriptor Pointer ............................................................................
22.2.5.4.2 Buffer Pointer .......................................................................................
22.2.5.4.3 Buffer Offset .........................................................................................
22.2.5.4.4 Buffer Length ........................................................................................
22.2.5.4.5 Packet Length .......................................................................................
22.2.5.4.6 Start of Packet (SOP) Flag ........................................................................
22.2.5.4.7 End of Packet (EOP) Flag .........................................................................
22.2.5.4.8 Ownership (OWNER) Flag ........................................................................
22.2.5.4.9 End of Queue (EOQ) Flag .........................................................................
22.2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag ..................................................
22.2.5.4.11 Pass CRC (PASSCRC) Flag ....................................................................
22.2.5.5 CPPI Receive Buffer Descriptor Format .............................................................
22.2.5.5.1 Next Descriptor Pointer ............................................................................
22.2.5.5.2 Buffer Pointer .......................................................................................
22.2.5.5.3 Buffer Offset .........................................................................................
22.2.5.5.4 Buffer Length ........................................................................................
22.2.5.5.5 Packet Length .......................................................................................
22.2.5.5.6 Start of Packet (SOP) Flag ........................................................................
22.2.5.5.7 End of Packet (EOP) Flag .........................................................................
22.2.5.5.8 Ownership (OWNER) Flag ........................................................................
22.2.5.5.9 End of Queue (EOQ) Flag .........................................................................
22.2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag ..................................................
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22.2.5.5.11 Pass CRC (PASSCRC) Flag ....................................................................
22.2.5.5.12 Jabber Flag ........................................................................................
22.2.5.5.13 Oversize Flag ......................................................................................
22.2.5.5.14 Fragment Flag .....................................................................................
22.2.5.5.15 Undersized Flag ...................................................................................
22.2.5.5.16 Control Flag ........................................................................................
22.2.5.5.17 Overrun Flag .......................................................................................
22.2.5.5.18 Code Error (CODEERROR) Flag ..............................................................
22.2.5.5.19 Alignment Error (ALIGNERROR) Flag ........................................................
22.2.5.5.20 CRC Error (CRCERROR) Flag .................................................................
22.2.5.5.21 No Match (NOMATCH) Flag ....................................................................
22.2.6 MDIO Module .................................................................................................
22.2.6.1 MDIO Module Components ............................................................................
22.2.6.1.1 MDIO Regs ..........................................................................................
22.2.6.1.2 Control and Schedule ..............................................................................
22.2.6.1.3 MDIO Interface ......................................................................................
22.2.6.2 MDIO Module Operational Overview .................................................................
22.2.6.2.1 Initializing the MDIO Module ......................................................................
22.2.6.2.2 Writing Data To a PHY Register ..................................................................
22.2.6.2.3 Reading Data From a PHY Register .............................................................
22.2.6.2.4 Example of MDIO Register Access Code .......................................................
22.2.7 EMAC Module ................................................................................................
22.2.7.1 EMAC Module Components ...........................................................................
22.2.7.2 EMAC Module Operational Overview ................................................................
22.2.8 MAC Interface .................................................................................................
22.2.8.1 Data Reception ..........................................................................................
22.2.8.1.1 Receive Control .....................................................................................
22.2.8.1.2 Receive Inter-Frame Interval ......................................................................
22.2.8.1.3 Receive Flow Control ..............................................................................
22.2.8.2 Data Transmission ......................................................................................
22.2.8.2.1 Transmit Control ....................................................................................
22.2.8.2.2 CRC Insertion .......................................................................................
22.2.8.2.3 Adaptive Performance Optimization (APO) .....................................................
22.2.8.2.4 Interpacket-Gap (IPG) Enforcement .............................................................
22.2.8.2.5 Back Off ..............................................................................................
22.2.8.2.6 Transmit Flow Control .............................................................................
22.2.8.2.7 Speed, Duplex, and Pause Frame Support .....................................................
22.2.9 Packet Receive Operation ..................................................................................
22.2.9.1 Receive DMA Host Configuration .....................................................................
22.2.9.2 Receive Channel Enabling .............................................................................
22.2.9.3 Receive Address Matching ............................................................................
22.2.9.4 VBUSP Latency .........................................................................................
22.2.9.5 Hardware Receive QOS Support .....................................................................
22.2.9.6 Host Free Buffer Tracking ..............................................................................
22.2.9.7 Receive Channel Teardown ...........................................................................
22.2.9.8 Receive Frame Classification ..........................................................................
22.2.9.9 Promiscuous Receive Mode ...........................................................................
22.2.9.10 Big Endian Mode .......................................................................................
22.2.9.11 Receive Overrun .......................................................................................
22.2.10 Packet Transmit Operation ................................................................................
22.2.10.1 Transmit DMA Host Configuration ...................................................................
22.2.10.2 Transmit Channel Teardown .........................................................................
22.2.11 Receive and Transmit Latency ............................................................................
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SPRUGR0C – October 2009 – Revised November 2013
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22.3
22.4
22.2.12 Transfer Node Priority ......................................................................................
22.2.13 Clock Stop ...................................................................................................
22.2.14 Software Reset ..............................................................................................
22.2.14.1 Soft Reset of EMAC Submodule .....................................................................
22.2.15 Initialization ..................................................................................................
22.2.15.1 Enabling the EMAC/MDIO Peripheral ...............................................................
22.2.15.2 EMAC Subsystem Module Initialization .............................................................
22.2.15.3 MDIO Module Initialization ............................................................................
22.2.15.4 EMAC Module Initialization ...........................................................................
22.2.16 Interrupt Support ............................................................................................
22.2.16.1 EMAC Module Interrupt Events and Requests .....................................................
22.2.16.1.1 Transmit Packet Completion Interrupts ........................................................
22.2.16.1.2 Receive Packet Completion Interrupts .........................................................
22.2.16.1.3 Statistics Interrupt .................................................................................
22.2.16.1.4 Host Error Interrupt ...............................................................................
22.2.16.1.5 Receive Threshold Interrupts ....................................................................
22.2.16.1.6 Pulse Interrupts ....................................................................................
22.2.16.2 Proper Interrupt Processing ..........................................................................
22.2.16.3 Interrupt Multiplexing ..................................................................................
22.2.16.4 Pulse Interrupts in EMAC SubSystem ..............................................................
22.2.16.4.1 C(0/1/2) RXTHRESHPULSE Interrupt Description ...........................................
22.2.16.4.2 2 C(0/1/2) RXPULSE Interrupt Description ....................................................
22.2.16.4.3 C(0/1/2) TXPULSE Interrupt Description ......................................................
22.2.16.4.4 C(0/1/2) MISCPULSE Interrupt Description ...................................................
22.2.16.5 Interrupt Pacing ........................................................................................
22.2.16.6 MDIO Module Interrupt Events and Requests .....................................................
22.2.16.6.1 Link Change Interrupt ............................................................................
22.2.16.6.2 User Access Completion Interrupt ..............................................................
22.2.17 Power Management ........................................................................................
22.2.18 Emulation Considerations ..................................................................................
22.2.18.1 EMAC Subsystem .....................................................................................
22.2.18.2 EMAC Submodule .....................................................................................
EMAC Subsystem Registers ..........................................................................................
22.3.1 Revision ID Register (REVID) ..............................................................................
22.3.2 Software Reset Register (SOFTRESET) ..................................................................
22.3.3 Interrupt Control Register (INTCONTROL) ...............................................................
22.3.4 Interrupt Core Receive Threshold Interrupt Enable Registers (C0RXTHRESHENC2RXTHRESHEN) ............................................................................................
22.3.5 Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN) .............................
22.3.6 Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN) .............................
22.3.7 Interrupt Core Miscellaneous Interrupt Enable Registers (C0MISCEN-C2MISCEN) ................
22.3.8 Interrupt Core Receive Threshold Interrupt Status Registers (C0RXTHRESHSTATC2RXTHRESHSTAT) .........................................................................................
22.3.9 Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT) .......................
22.3.10 Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT) ......................
22.3.11 Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT) .........
22.3.12 Interrupt Core Receive Interrupts Per Millisecond Registers (C0RXIMAX-C2RXIMAX) ..........
22.3.13 Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) ..........
MDIO Registers .........................................................................................................
22.4.1 MDIO Revision ID Register (REVID) ......................................................................
22.4.2 MDIO Control Register (CONTROL) .......................................................................
22.4.3 PHY Acknowledge Status Register (ALIVE) ..............................................................
22.4.4 PHY Link Status Register (LINK) ...........................................................................
22.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ..........................
SPRUGR0C – October 2009 – Revised November 2013
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Contents
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22.5
22.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ........................
22.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) .................
22.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ...............
22.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ..............
22.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ......
22.4.11 MDIO User Access Register 0 (USERACCESS0) .....................................................
22.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) .................................................
22.4.13 MDIO User Access Register 1 (USERACCESS1) .....................................................
22.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................
EMAC Module Registers ..............................................................................................
22.5.1 Transmit Revision ID Register (TXREVID) ................................................................
22.5.2 Transmit Control Register (TXCONTROL) ................................................................
22.5.3 Transmit Teardown Register (TXTEARDOWN) ..........................................................
22.5.4 Receive Revision ID Register (RXREVID) ................................................................
22.5.5 Receive Control Register (RXCONTROL) ................................................................
22.5.6 Receive Teardown Register (RXTEARDOWN) ..........................................................
22.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ..................................
22.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................
22.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ..............................................
22.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................
22.5.11 MAC Input Vector Register (MACINVECTOR) ..........................................................
22.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) ..........................................
22.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) .................................
22.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ...............................
22.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) .............................................
22.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .......................................
22.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ...................................
22.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .................................
22.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ...............................................
22.5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) .........................................
22.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ........
22.5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................
22.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ................................................
22.5.24 Receive Maximum Length Register (RXMAXLEN) .....................................................
22.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) ................................................
22.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ................
22.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH)
22.5.28
22.5.29
22.5.30
22.5.31
22.5.32
22.5.33
22.5.34
22.5.35
22.5.36
22.5.37
22.5.38
22.5.39
22.5.40
22.5.41
22.5.42
22.5.43
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....................................................................................................................
Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) .......
MAC Control Register (MACCONTROL) ................................................................
MAC Status Register (MACSTATUS) ....................................................................
Emulation Control Register (EMCONTROL) ............................................................
FIFO Control Register (FIFOCONTROL) ................................................................
MAC Configuration Register (MACCONFIG) ............................................................
Soft Reset Register (SOFTRESET) ......................................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) .....................................
MAC Source Address High Bytes Register (MACSRCADDRHI) .....................................
MAC Hash Address Register 1 (MACHASH1) ..........................................................
MAC Hash Address Register 2 (MACHASH2) ..........................................................
Back Off Test Register (BOFFTEST) ....................................................................
Transmit Pacing Algorithm Test Register (TPACETEST) .............................................
Receive Pause Timer Register (RXPAUSE) ............................................................
Transmit Pause Timer Register (TXPAUSE) ............................................................
MAC Address Low Bytes Register (MACADDRLO) ....................................................
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SPRUGR0C – October 2009 – Revised November 2013
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22.6
23
22.5.44 MAC Address High Bytes Register (MACADDRHI) ....................................................
22.5.45 MAC Index Register (MACINDEX) .......................................................................
22.5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) ..................
22.5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) ..................
22.5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) ..................................
22.5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP) ..................................
22.5.50 Network Statistics Registers ...............................................................................
22.5.50.1 Good Receive Frames Register (RXGOODFRAMES) ............................................
22.5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) .....................................
22.5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) ......................................
22.5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) ..........................................
22.5.50.5 Receive CRC Errors Register (RXCRCERRORS) ................................................
22.5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS) .........................
22.5.50.7 Receive Oversized Frames Register (RXOVERSIZED) ..........................................
22.5.50.8 Receive Jabber Frames Register (RXJABBER) ...................................................
22.5.50.9 Receive Undersized Frames Register (RXUNDERSIZED) .......................................
22.5.50.10 Receive Frame Fragments Register (RXFRAGMENTS) ........................................
22.5.50.11 Filtered Receive Frames Register (RXFILTERED) ..............................................
22.5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) .................................
22.5.50.13 Receive Octet Frames Register (RXOCTETS) ...................................................
22.5.50.14 Good Transmit Frames Register (TXGOODFRAMES) ..........................................
22.5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) ...................................
22.5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) ....................................
22.5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) ........................................
22.5.50.18 Deferred Transmit Frames Register (TXDEFERRED) ..........................................
22.5.50.19 Transmit Collision Frames Register (TXCOLLISION) ...........................................
22.5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) ................................
22.5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) ................................
22.5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) ......................
22.5.50.23 Transmit Late Collision Frames Register (TXLATECOLL) ......................................
22.5.50.24 Transmit Underrun Error Register (TXUNDERRUN) ............................................
22.5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) ................................
22.5.50.26 Transmit Octet Frames Register (TXOCTETS) ..................................................
22.5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) .................................
22.5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) ..................
22.5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255) ...............
22.5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) ...............
22.5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) ............
22.5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) ...
22.5.50.33 Network Octet Frames Register (NETOCTETS) .................................................
22.5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) ...........
22.5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) ........
22.5.50.36 Receive DMA Overruns Register (RXDMAOVERRUNS) .......................................
EMAC/MDIO Glossary .................................................................................................
High-End CAN Controller (HECC)
23.1
23.2
23.3
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CAN Overview ..........................................................................................................
23.1.1 CAN Protocol Processor Features .........................................................................
23.1.2 Standard CAN Controller (SCC) Features ................................................................
23.1.3 High-End CAN Controller (HECC) Features ..............................................................
CAN Network and Module Overview .................................................................................
23.2.1 CAN Protocol Overview .....................................................................................
23.2.2 CAN Controller Overview ....................................................................................
Standard CAN Controller (SCC) Overview ..........................................................................
SPRUGR0C – October 2009 – Revised November 2013
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23.3.1 SCC Memory Map ............................................................................................
High-End CAN Controller (HECC) Overview .......................................................................
23.4.1 SCC-Compatible Mode ......................................................................................
23.4.2 HECC Memory Map ..........................................................................................
23.5 Message Objects .......................................................................................................
23.5.1 SCC Message Objects ......................................................................................
23.5.2 HECC Message Objects .....................................................................................
23.5.3 CAN Message Mailbox ......................................................................................
23.5.3.1 Transmit Mailbox ........................................................................................
23.5.3.2 Receive Mailbox .........................................................................................
23.5.3.3 Handling of Remote Frames ...........................................................................
23.5.3.4 CPU Message Mailbox Access ........................................................................
23.5.4 CAN Acceptance Filter ......................................................................................
23.5.4.1 SCC Acceptance Filtering ..............................................................................
23.5.4.2 HECC Acceptance Filtering ............................................................................
23.6 CAN Module Initialization ..............................................................................................
23.6.1 CAN Bit-Timing Configuration ..............................................................................
23.6.2 CAN Bit Rate Calculation ....................................................................................
23.7 CAN Interrupts ..........................................................................................................
23.7.1 Interrupts Scheme ............................................................................................
23.7.2 Message Object Interrupt ...................................................................................
23.8 CAN Power-Down Mode ..............................................................................................
23.8.1 Local Power Down ...........................................................................................
23.8.2 Global Power Down ..........................................................................................
23.9 Timer Management Unit ...............................................................................................
23.9.1 Time-Stamp Functions .......................................................................................
23.9.2 Time-Out Functions ..........................................................................................
23.9.3 Behavior/Usage of MAIF0/1 Bit in User Applications ....................................................
23.10 Registers ................................................................................................................
23.10.1 SCC/HECC control registers ..............................................................................
23.10.1.1 Mailbox Enable Register (CANME) ..................................................................
23.10.1.2 Mailbox Direction Register (CANMD) ...............................................................
23.10.1.3 Transmission Request Set Register (CANTRS) ...................................................
23.10.1.4 Transmission Request Reset Register (CANTRR) ................................................
23.10.1.5 Transmission Acknowledge Register (CANTA) ....................................................
23.10.1.6 Abort Acknowledge Register (CANAA) .............................................................
23.10.1.7 Receive Message Pending Register (CANRMP) ..................................................
23.10.1.8 Receive Message Lost Register (CANRML) .......................................................
23.10.1.9 Remote Frame Pending Register (CANRFP) ......................................................
23.10.1.10 Global Acceptance Mask Register (CANGAM) ...................................................
23.10.1.11 Master Control Register (CANMC) .................................................................
23.10.1.12 Bit-Timing Configuration Register (CANBTC) ....................................................
23.10.1.13 Error and Status Register (CANES) ...............................................................
23.10.1.14 Transmit Error Counter Register (CANTEC) ......................................................
23.10.1.15 Receive Error Counter Register (CANREC) ......................................................
23.10.1.16 Global Interrupt Flag Registers (CANGIF0, CANGIF1) .........................................
23.10.1.17 Global Interrupt Mask Register (CANGIM) ........................................................
23.10.1.18 Mailbox Interrupt Mask Register (CANMIM) ......................................................
23.10.1.19 Mailbox Interrupt Level Register (CANMIL) .......................................................
23.10.1.20 Overwrite Protection Control Register (CANOPC) ...............................................
23.10.1.21 Transmit I/O Control Register (CANTIOC) ........................................................
23.10.1.22 Receive I/O Control Registers (CANRIOC) .......................................................
23.10.2 Time Stamp Registers ......................................................................................
23.4
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23.10.2.1 Local Network Time Register (CANLNT) ...........................................................
23.10.2.2 Message Object Time Stamp Registers (CANMOTS) ............................................
23.10.3 Time-Out Registers .........................................................................................
23.10.3.1 Message Object Time-Out Registers (CANMOTO) ...............................................
23.10.3.2 Time-Out Control Register (CANTOC) ..............................................................
23.10.3.3 Time-Out Status Register (CANTOS) ...............................................................
23.10.4 Message Mailbox Registers ...............................................................................
23.10.4.1 Message Identifier Register (CANMID) .............................................................
23.10.4.2 Message Control Field Register (CANMCF) .......................................................
23.10.4.3 Message Data Registers (CANMDL, CANMDH) ..................................................
23.10.4.4 Local Acceptance Mask Register (CANLAM) ......................................................
24
Applications Processor Initialization
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24.4
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Initialization Overview ..................................................................................................
24.1.1 Terminology ...................................................................................................
24.1.2 Initialization Process .........................................................................................
Preinitialization ..........................................................................................................
24.2.1 Power Connections ..........................................................................................
24.2.2 Clock and Reset ..............................................................................................
24.2.2.1 Clock and Reset Overview .............................................................................
24.2.2.2 Clock Configuration .....................................................................................
24.2.2.2.1 Required System Input Clocks ....................................................................
24.2.2.2.2 Optional System Input Clock: SYS_ALTCLK ...................................................
24.2.2.2.3 Optional System Output Clock: SYS_CLKOUT1 and SYS_CLKOUT2 .....................
24.2.2.3 Reset Configuration .....................................................................................
24.2.3 Boot Configuration ...........................................................................................
Power, Clocks, and Reset Power-Up Sequence ...................................................................
Device Initialization by ROM Code ...................................................................................
24.4.1 Booting Overview .............................................................................................
24.4.1.1 Booting Types ...........................................................................................
24.4.1.2 Main Features ...........................................................................................
24.4.2 Memory Map ..................................................................................................
24.4.2.1 ROM Memory Map ......................................................................................
24.4.2.2 RAM Memory Map ......................................................................................
24.4.3 Overall Booting Sequence ..................................................................................
24.4.4 Start-Up and Configuration ..................................................................................
24.4.4.1 Start-Up ...................................................................................................
24.4.4.2 Clocking Configuration .................................................................................
24.4.4.3 Booting Device List Set-Up ............................................................................
24.4.5 Peripheral Booting ............................................................................................
24.4.5.1 Overview .................................................................................................
24.4.5.2 UART .....................................................................................................
24.4.5.3 USB .......................................................................................................
24.4.5.3.1 USB Driver Descriptors ............................................................................
24.4.5.3.2 USB Customized Descriptors .....................................................................
24.4.5.3.3 USB Driver Functionality ..........................................................................
24.4.5.4 EMAC .....................................................................................................
24.4.5.4.1 Boot Host Servers ..................................................................................
24.4.5.4.2 EMAC Boot UseCase ..............................................................................
24.4.6 Fast External Booting ........................................................................................
24.4.6.1 Overview .................................................................................................
24.4.6.2 External Booting .........................................................................................
24.4.7 Memory Booting ..............................................................................................
24.4.7.1 Overview .................................................................................................
SPRUGR0C – October 2009 – Revised November 2013
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Contents
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24.5
24.6
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24.4.7.2 Non-XIP Memory ........................................................................................
24.4.7.3 XIP Memory ..............................................................................................
24.4.7.3.1 GPMC Initialization .................................................................................
24.4.7.4 NAND .....................................................................................................
24.4.7.4.1 Initialization and NAND Detection ................................................................
24.4.7.4.2 Read Sector Procedure ............................................................................
24.4.7.5 OneNAND ................................................................................................
24.4.7.5.1 Initialization and OneNAND Detection ...........................................................
24.4.7.5.2 OneNAND Read Sector Procedure ..............................................................
24.4.7.6 MMC/SD Cards ..........................................................................................
24.4.7.6.1 Initialization and MMC/SD Card Detection ......................................................
24.4.7.6.2 Read Sector Procedure ............................................................................
24.4.7.6.3 File System Handling ..............................................................................
24.4.7.7 DiskOnChip™ ............................................................................................
24.4.7.8 SPI Flash .................................................................................................
24.4.8 Image Format .................................................................................................
24.4.8.1 Overview .................................................................................................
24.4.8.2 Image Header ............................................................................................
24.4.8.3 Image Format for GP Devices .........................................................................
24.4.8.4 Image Execution .........................................................................................
24.4.9 Tracing .........................................................................................................
Debug Configuration ...................................................................................................
24.5.1 Overview .......................................................................................................
24.5.2 JTAG Port Signal Description ...............................................................................
24.5.3 Initial Scan Chain Configuration ............................................................................
24.5.4 Debugger Address Space ...................................................................................
Revision History ........................................................................................................
Contents
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2734
2735
2735
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SPRUGR0C – October 2009 – Revised November 2013
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List of Figures
1-1.
Environment Using TPS65023 .........................................................................................
137
1-2.
Block Diagram ............................................................................................................
138
2-1.
Interconnect Overview...................................................................................................
148
3-1.
MPU Subsystem Overview .............................................................................................
164
3-2.
MPU Subsystem Integration Overview ................................................................................
167
3-3.
MPU Subsystem Clocking Scheme
...................................................................................
168
3-4.
MPU Subsystem Reset Scheme .......................................................................................
169
3-5.
Bridges Overview ........................................................................................................
172
3-6.
MPU Subsystem Power Domain Overview ...........................................................................
174
4-1.
Generic Clock Domain
..................................................................................................
Functional and Interface Clocks .......................................................................................
PRCM Overview .........................................................................................................
PRCM Functional External Interface (Detailed View) ...............................................................
External Clock Interface .................................................................................................
PRCM External Clock Sources.........................................................................................
External Reset Signals ..................................................................................................
PRCM Integration ........................................................................................................
PRCM Reset Signals ....................................................................................................
Reset Manager Interface ................................................................................................
Reset Sources Overview ................................................................................................
Reset Destinations Overview ...........................................................................................
Other Module Reset Distributions Overview .........................................................................
EMIF4 Reset Distributions Overview ..................................................................................
External Warm Reset Interface ........................................................................................
Device Reset Manager Overview ......................................................................................
Domain Reset Management: Part 1 ...................................................................................
Domain Reset Management: Part 2 ...................................................................................
Domain Reset Management: Part 3 ...................................................................................
PRCM Clock Manager Overview ......................................................................................
External Clock I/O ........................................................................................................
Internal Clock Sources ..................................................................................................
PRM Clock Generator ...................................................................................................
CM Clock Generator Functional Overview ...........................................................................
CM Emulation Clock Generator Functional Overview ...............................................................
Generic DPLL Functional Diagram ....................................................................................
DPLL3 Clocks ............................................................................................................
DPLL4 Clocks ............................................................................................................
DPLL5 Clocks ............................................................................................................
MPU Domain Clocking Scheme .......................................................................................
SGX Domain Clocking Scheme ........................................................................................
CORE Clock Signals: Part 1 ............................................................................................
CORE Clock Signals: Part 2 ............................................................................................
CORE Clock Signals: Part 3 ............................................................................................
IPSS Domain .............................................................................................................
EFUSE Clock Signals ...................................................................................................
DSS Clock Signals .......................................................................................................
USBHOST Clock Signals ...............................................................................................
183
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
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4-9.
4-10.
4-11.
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4-13.
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4-19.
4-20.
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4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
SPRUGR0C – October 2009 – Revised November 2013
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List of Figures
184
188
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4-39.
WKUP Clock Signals ....................................................................................................
241
4-40.
PER Clock Signals .......................................................................................................
242
4-41.
DPLL Clock Signals
4-42.
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
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4-54.
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4-57.
4-58.
4-59.
4-60.
4-61.
4-62.
4-63.
4-64.
4-65.
4-66.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
6-1.
6-2.
6-3.
6-4.
6-5.
58
.....................................................................................................
System Clock Oscillator Controls ......................................................................................
Common PRM Source-Clock Controls ................................................................................
Common CM Source-Clock Controls ..................................................................................
Common Interface Clock Controls .....................................................................................
DPLL Domain Clock Controls ..........................................................................................
SGX Domain Clock Controls ...........................................................................................
CORE Domain Clock Controls: Part 1 ................................................................................
CORE Domain Clock Controls: Part 2 ................................................................................
CORE Domain Clock Controls: Part 3 ................................................................................
EFUSE Domain Clock Controls ........................................................................................
DSS Domain Clock Controls ...........................................................................................
USBHOST Domain Clock Controls ....................................................................................
WKUP Domain Clock Controls .........................................................................................
PER Domain Clock Controls: Part 1...................................................................................
PER Domain Clock Controls: Part 2...................................................................................
Clock Sources for Other Modules .....................................................................................
Domain Sleep/Wake-Up Transition ....................................................................................
Device Power Reset and Clock Controllers ..........................................................................
sys_clkout2 Gating Polarity Control ...................................................................................
Functional Clock Basic Programming Model .........................................................................
Functional Clock Switching .............................................................................................
Interface Clock Basic Programming Model ...........................................................................
Domain INACTIVE STATE Basic Programming Model .............................................................
Processor Clock Basic Programming Model .........................................................................
Wake-Up Basic Programming Model ..................................................................................
Interconnect Architecture Overview ...................................................................................
L3 Port Initiators ..........................................................................................................
L3 Interconnect Overview ...............................................................................................
Flowchart of the Protection Mechanism...............................................................................
L3 Firewall Implementation .............................................................................................
L3 Region Overlay and Priority Level Overview .....................................................................
Example of REQ_INFO_PERMISSION Register ....................................................................
L3 Error Reporting Structure ...........................................................................................
Global Error Routing .....................................................................................................
L3 Error Routing..........................................................................................................
Typical Error Analysis Sequence ......................................................................................
L4 Interconnect Overview ...............................................................................................
L4 Initiator-Target Connectivity for L4-Core and L4-Per ............................................................
Example of CONNID_BIT_VECTOR ..................................................................................
L4 Firewall Overview ....................................................................................................
L4 Error Reporting .......................................................................................................
System Control Module Overview .....................................................................................
System Control Module Environment Overview .....................................................................
System Control Module Interface Signals ............................................................................
System Control Module Integration ....................................................................................
Internal Clock Implementation ..........................................................................................
List of Figures
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614
SPRUGR0C – October 2009 – Revised November 2013
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6-6.
System Control Module Block Diagram ...............................................................................
615
6-7.
Pad Configuration Register Functionality .............................................................................
616
6-8.
Pad Configuration Diagram .............................................................................................
618
6-9.
Overview of the Debug and Observability Register Functionality .................................................
630
6-10.
DPLL with EMI Reduction Feature
....................................................................................
669
6-11.
DPLL-D Integration ......................................................................................................
670
6-12.
Spreading Generation Block Diagram .................................................................................
671
6-13.
Modulation Profiles
......................................................................................................
Effect of the SSC in Frequency ........................................................................................
Effect of the SSC in the Time Domain ................................................................................
Peaks Reduction Due to Spreading ...................................................................................
Supported Spreading Frequency and Deviation .....................................................................
Supported Safe Operating Regions and Jitter Impact ..............................................................
I/O Power Optimization Flowchart .....................................................................................
SDMA Overview ..........................................................................................................
Edge-Sensitive DMA Request Scheme ...............................................................................
Transition-Sensitive DMA Request Scheme .........................................................................
SDMA Controller Integration ............................................................................................
Example of External DMA Requests Use to the SDMA Controller ................................................
SDMA Controller Top-Level Block Diagram ..........................................................................
Example Showing Double-Index Addressing, Elements, Frames, and Strides ..................................
Addressing Mode Example (a) .........................................................................................
Addressing Mode Example (b) .........................................................................................
Addressing Mode Example (c) .........................................................................................
Example of a 90° Clockwise Image Rotation .........................................................................
2-D Graphic Transparent Color Block Diagram ......................................................................
Overview ..................................................................................................................
Environment ..............................................................................................................
Data Flow .................................................................................................................
Overview ..................................................................................................................
Interrupt Controller Highlight ............................................................................................
Interrupts from External Devices .......................................................................................
MPU Subsystem INTCPS Integration .................................................................................
Top-Level Block Diagram ...............................................................................................
IRQ/FIQ Processing Sequence ........................................................................................
Nested IRQ/FIQ Sequence .............................................................................................
GPMC Environment .....................................................................................................
GPMC to 16-Bit Address/Data-Multiplexed Memory ................................................................
GPMC to 16-Bit NAND Device .........................................................................................
GPMC Integration in the Processor ...................................................................................
GPMC Functional Diagram .............................................................................................
Chip-Select Address Mapping and Decoding Mask .................................................................
Asynchronous Single Read on a Nonmultiplexed Address/Data Device .........................................
Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ......................
Wait Behavior During a Synchronous Read Burst Access .........................................................
Asynchronous Single Read on an Address/Data-Nonmultiplexed Device .......................................
Asynchronous Single Read on an Address/Data-Multiplexed Device ............................................
Asynchronous Single Write on an Address/Data-Nonmultiplexed Device ........................................
Asynchronous Single Write on an Address/Data-Multiplexed Device.............................................
673
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
SPRUGR0C – October 2009 – Revised November 2013
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List of Figures
674
674
675
676
676
681
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795
795
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816
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826
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913
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9-14.
Asynchronous Multiple (Page Mode) Read...........................................................................
924
9-15.
Synchronous Single Read (GPMCFCLKDIVIDER = 0) .............................................................
926
9-16.
Synchronous Single Read (GPMCFCLKDIVIDER = 1) .............................................................
927
9-17.
Synchronous Single Write on an Address/Data-Multiplexed Device ..............................................
928
9-18.
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0) ..................................................
929
9-19.
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1) ..................................................
930
9-20.
Synchronous Multiple (Burst) Write ....................................................................................
931
9-21.
Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode
..................................
NAND Command Latch Cycle ..........................................................................................
NAND Address Latch Cycle ............................................................................................
NAND Data Read Cycle ................................................................................................
NAND Data Write Cycle .................................................................................................
Hamming Code Accumulation Algorithm (½) .........................................................................
Hamming Code Accumulation Algorithm (2/2) .......................................................................
ECC Computation for a 256-Byte Data Stream (Read or Write) ..................................................
ECC Computation for a 512-Byte Data Stream (Read or Write) ..................................................
128 Word 16 ECC Computation .......................................................................................
256 Word 16 ECC Computation .......................................................................................
Manual Mode Sequence and Mapping ................................................................................
NAND Page Mapping and ECC: Per-Sector Schemes .............................................................
NAND Page Mapping and ECC: Pooled Spare Schemes ..........................................................
NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC .....................................
NAND Read Cycle Optimization Timing Description ................................................................
GPMC Connection to External NOR Flash Memory ................................................................
Synchronous Burst Read Access (Timing Parameters in Clock Cycles) .........................................
Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ......................................
Asynchronous Single Write Access (Timing Parameters in Clock Cycles) .......................................
SDRC Subsystem Environment ......................................................................................
SDRC Integration to the Processor ..................................................................................
SMS Top-Level Diagram ..............................................................................................
Security Region Organization .........................................................................................
EMIF4 Top Level Block Diagram .....................................................................................
EMIF4 Block Diagram ..................................................................................................
64-Byte Linear Read Starting at Address 0x0 ......................................................................
64-Byte Linear Read Starting at Address 0x8 (LPDDR1) .........................................................
64-Byte Linear Read Starting at Address 0x8 ......................................................................
64-Byte Linear Read Starting at Address 0x10.....................................................................
64-Byte Linear Read Starting at Address 0x18.....................................................................
Data Bus Obfuscation ..................................................................................................
EMIF Module ID and Revision Register (EMIF_MOD_ID_REV) .................................................
SDRAM Status Register (STATUS) ..................................................................................
SDRAM Configuration Register (SDRAM_CONFIG) ..............................................................
SDRAM Refresh Control Register (SDRAM_REF_CTRL) ........................................................
SDRAM Refresh Control Shadow Register (SDRAM_REF_CTRL_SHDW)....................................
SDRAM Timing 1 Register (SDRAM_TIM_1) .......................................................................
SDRAM Timing 1 Shadow Register (SDRAM_TIM_1_SHDW) ..................................................
SDRAM Timing 2 Register (SDRAM_TIM_2) .......................................................................
SDRAM Timing 2 Shadow Register (SDRAM_TIM_2_SHDW) ..................................................
SDRAM Timing 3 Register (SDRAM_TIM_3) .......................................................................
933
9-22.
9-23.
9-24.
9-25.
9-26.
9-27.
9-28.
9-29.
9-30.
9-31.
9-32.
9-33.
9-34.
9-35.
9-36.
9-37.
9-38.
9-39.
9-40.
9-41.
9-42.
9-43.
9-44.
9-45.
9-46.
9-47.
9-48.
9-49.
9-50.
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
60
List of Figures
937
938
939
940
944
945
945
946
947
947
952
956
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958
964
967
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971
1009
1011
1013
1019
1025
1026
1032
1032
1032
1032
1032
1038
1042
1043
1044
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1047
1048
1049
1050
1051
1052
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
9-72.
9-73.
9-74.
9-75.
9-76.
9-77.
9-78.
9-79.
9-80.
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9-83.
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9-87.
9-88.
9-89.
9-90.
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9-92.
9-93.
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9-99.
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9-101.
9-102.
9-103.
9-104.
9-105.
9-106.
9-107.
9-108.
9-109.
9-110.
10-1.
..................................................
Power Management Control Register (PWR_MGMT_CTRL) ....................................................
Power Management Control Shadow Register (PWR_MGMT_CTRL_SHDW) ................................
OCP Configuration Register (OCP_CONFIG) ......................................................................
OCP Configuration Value 1 Register (OCP_CFG_VAL_1) .......................................................
OCP Configuration Value 2 Register (OCP_CFG_VAL_2) .......................................................
IODFT Test Logic Global Control Register (IODFT_TLGC) ......................................................
IODFT Test Logic Control MISR Result Register (IODFT_CTRL_MISR_RSLT) ..............................
IODFT Test Logic Address MISR Result Register (IODFT_ADDR_MISR_RSLT) ............................
IODFT Test Logic Data MISR Result 1 Register (IODFT_DATA_MISR_RSLT_1) ............................
IODFT Test Logic Data MISR Result 2 Register (IODFT_DATA_MISR_RSLT_2) ............................
IODFT Test Logic Data MISR Result 3 Register (IODFT_DATA_MISR_RSLT_3) ............................
Performance Counter 1 Register (PERF_CNT_1) .................................................................
Performance Counter 2 Register (PERF_CNT_2) .................................................................
Performance Counter Configuration Register (PERF_CNT_CFG) ..............................................
Performance Counter Master Region Select Register (PERF_CNT_SEL) .....................................
Performance Counter Time Register (PERF_CNT_TIM) .........................................................
End of Interrupt Register (IRQ_EOI) .................................................................................
System OCP Interrupt Raw Status Register (IRQSTATUS_RAW_SYS) .......................................
System OCP Interrupt Status Register (IRQSTATUS_SYS) .....................................................
System OCP Interrupt Enable Set Register (IRQENABLE_SET_SYS) .........................................
System OCP Interrupt Enable Clear Register (IRQENABLE_CLR_SYS) ......................................
OCP Error Log Register (OCP_ERR_LOG) ........................................................................
DDR PHY Control 1 Register (DDR_PHY_CTRL_1) ..............................................................
DDR PHY Control 1 Shadow Register (DDR_PHY_CTRL_1_SHDW) ..........................................
DDR PHY Control 2 Register (DDR_PHY_CTRL_2) ..............................................................
Connecting Two DDR2 on One Chip Select ........................................................................
Connecting Two DDR2 on Two Chip Selects.......................................................................
Natural Scan Order .....................................................................................................
SDRC Subsystem Overview ..........................................................................................
YUV Format: Pixel Representation...................................................................................
VRFB Context Configuration ..........................................................................................
Example of VRFB Context 1 Configuration .........................................................................
Display a Rotated QVGA Image ......................................................................................
Arbitration Granularity Versus Arbitration Decision ................................................................
BURST-COMPLETE on Class 2-Group 3 ...........................................................................
Priority Between Classes ..............................................................................................
Idle Cycle Mechanism within a Burst ................................................................................
Example of EXTENDEDGRANT Mechanism .......................................................................
Arbitration Between Classes ..........................................................................................
Arbitration within a Class ..............................................................................................
Generic Arbitration Decision ..........................................................................................
Arbitration Granularity ..................................................................................................
SDRC Camcorder Use Case Overview .............................................................................
VRFB Actual Image Size vs Programmed Image Size ............................................................
SDRC Address Space in MPU Global Address Space ............................................................
OCM Subsystem Overview ...........................................................................................
OCM Subsystem Integration to the Device .........................................................................
VPSS Module, Memory, and the CPU ...............................................................................
SDRAM Timing 3 Shadow Register (SDRAM_TIM_3_SHDW)
SPRUGR0C – October 2009 – Revised November 2013
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List of Figures
1053
1054
1055
1055
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1056
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1058
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10-2.
Clock Sources...........................................................................................................
1124
10-3.
CCD Controller Frame and Control Signal Definitions
............................................................
1126
10-4.
BT.656 Signal Interface ................................................................................................
1127
10-5.
Data Processing in Raw Data Mode .................................................................................
1130
10-6.
Color Patterns ...........................................................................................................
1130
10-7.
Input Formatter
.........................................................................................................
Optical Black Averaging & Application...............................................................................
Black Clamping and Black Level Compensation ...................................................................
Output Formatter .......................................................................................................
A-Law Table .............................................................................................................
Image De-interfacing ...................................................................................................
Non-inversed vs Inversed Format ....................................................................................
Data Processing in YUV/BT656 Modes .............................................................................
CCD Controller ..........................................................................................................
Black Clamping and Block Level Compensation ...................................................................
Output Formatter .......................................................................................................
VDPOL is 0 ..............................................................................................................
VDPOL is 1 ..............................................................................................................
CCDC_VD2_INT Interrupt .............................................................................................
Peripheral Revision and Class Information Register (PID) .......................................................
VPFE_Peripheral Control Register (VPFE_PCR) ..................................................................
Sync and Mode Set Register (SYN_MODE) ........................................................................
Horizontal Pixel Information Register (HORZ_INFO) ..............................................................
Vertical Line - Settings for the Starting Pixel Register (VERT_START).........................................
Number of Vertical Lines Register (VERT_LINES) ................................................................
Culling Information in Horizontal and Vertical Directions Register (CULLING) ................................
Horizontal Size Register (HSIZE_OFF) .............................................................................
External Memory Line Offset Register (SDOFST) .................................................................
external memory Address Register (SDR_ADDR) .................................................................
Optical Black Clamping Settings Register (CLAMP) ...............................................................
DC Clamp Register (DCSUB).........................................................................................
CCD Color Pattern Register (COLPTN) .............................................................................
Black Compensation Register (BLKCMP) ...........................................................................
VPFE Interrupt Control (VDINT) Register ..........................................................................
ALAW Configuration (ALAW) Register ..............................................................................
REC656IF Configuration Register (REC656IF) ....................................................................
CCD Configuration Register (CCDCFG) ............................................................................
DMA Control (DMA_CNTL) Register ................................................................................
Graphics Accelerator Highlight .......................................................................................
SGX Subsystem Integration...........................................................................................
SGX Block Diagram ....................................................................................................
Display Subsystem Highlight ..........................................................................................
LCD Support Parallel Interface (RFBI Mode) .......................................................................
1131
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
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10-27.
10-28.
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10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
11-1.
11-2.
11-3.
12-1.
12-2.
62
1132
1133
1134
1135
1139
1140
1142
1143
1143
1144
1147
1147
1147
1150
1150
1151
1153
1154
1155
1156
1157
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1160
1161
1163
1164
1166
1167
1168
1169
1170
1172
1174
1177
1179
1183
1188
12-3.
External Generation of TE Signal Based on Logical OR Operation Between HSYNC and VSYNC (ActiveHigh)...................................................................................................................... 1189
12-4.
LCD Support Parallel Interface (Bypass Mode) ....................................................................
1190
12-5.
LCD Pixel Data Monochrome4 Passive Matrix .....................................................................
1191
12-6.
LCD Pixel Data Monochrome8 Passive Matrix .....................................................................
1192
12-7.
LCD Pixel Data Color Passive Matrix ................................................................................
1192
List of Figures
SPRUGR0C – October 2009 – Revised November 2013
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12-8.
LCD Pixel Data Color12 Active Matrix ...............................................................................
1193
12-9.
LCD Pixel Data Color16 Active Matrix ...............................................................................
1194
12-10. LCD Pixel Data Color18 Active Matrix ...............................................................................
1194
12-11. LCD Pixel Data Color24 Active Matrix ...............................................................................
1195
12-12. RFBI Data Stall Signal Diagram ......................................................................................
1195
.................................................................
Command Data Write ..................................................................................................
Display Data Read .....................................................................................................
Read to Write and Write to Read .....................................................................................
Active Matrix Timing Diagram of Configuration 1 (Start of Frame) ..............................................
Active Matrix Timing Diagram of Configuration 1 (Between Lines) ..............................................
Active Matrix Timing Diagram of Configuration 1 (Between Frames) ...........................................
Active Matrix Timing Diagram of Configuration 1 (End of Frame) ...............................................
Active Matrix Timing Diagram of Configuration 2 (Start of Frame) ..............................................
Active Matrix Timing Diagram of Configuration 2 (Between Lines) ..............................................
Active Matrix Timing Diagram of Configuration 2 (Between Frames) ...........................................
Active Matrix Timing Diagram of Configuration 2 (End of Frame) ...............................................
Active Matrix Timing Diagram of Configuration 3 (Start of Frame) ..............................................
Active Matrix Timing Diagram of Configuration 3 (Between Lines) ..............................................
Active Matrix Timing Diagram of Configuration 3 (Between Frames) ...........................................
Active Matrix Timing Diagram of Configuration 3 (End of Frame) ...............................................
Passive Matrix Timing Diagram (Start of Frame) ..................................................................
Passive Matrix Timing Diagram (Between Lines) ..................................................................
Passive Matrix Timing Diagram (Between Frames) ...............................................................
Passive Matrix Timing Diagram (End of Frame) ...................................................................
Typical SDI Connection ................................................................................................
Typical DSI Connection ................................................................................................
DSI Video Mode Without Burst (No-Line Buffer) ...................................................................
DSI Video Mode Without Burst (One-Line Buffer) .................................................................
DSI Video Mode With Burst (Two-Line Buffers) ....................................................................
Stall Timing With Pixel on Rising Edge ..............................................................................
Stall Timing With Pixel on Falling Edge .............................................................................
Data Flow in Command Mode Using the Video Port ..............................................................
Two Data Lane Configuration .........................................................................................
One Data Lane Configuration .........................................................................................
Two Packets Using Two-Data Lane Configuration (Example) ...................................................
Protocol Layer With Short and Long Packets.......................................................................
Short Packet Structure .................................................................................................
Long Packet Structure .................................................................................................
Data Identifier Structure ...............................................................................................
Virtual Channel Controller .............................................................................................
DSI Video Mode: Nonburst Transfer With VE and HE ............................................................
DSI Video Mode: Nonburst Transfer Without VE and HE .........................................................
DSI Video Mode: Burst Transfer Without VE and HE .............................................................
DSI General Frame Structure .........................................................................................
DSI General Frame Structure Using Burst Mode ..................................................................
DSi General Frame Structure Using Burst Mode and Interleaving ..............................................
24 Bits per Pixel RGB Color Format, Long Packet ................................................................
18 Bits per Pixel (Loosely Packed) RGB Color Format, Long Packet ...........................................
1196
12-13. RFBI Data Stall Signal Diagram With Handcheck
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
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12-27.
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12-47.
12-48.
12-49.
12-50.
12-51.
12-52.
12-53.
12-54.
12-55.
12-56.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Figures
1196
1197
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12-57. 18 Bits per Pixel (Packed) RGB Color Format, Long Packet .....................................................
................................................................
1231
12-59. 24 Bits Per Pixel With One Data Channel...........................................................................
1232
12-60. 24 Bits Per Pixel With Two Data Channels .........................................................................
1232
12-61. 24 Bits Per Pixel With Three Data Channels .......................................................................
1232
12-62. TV Display Interface (s-video mode) .................................................................................
1233
............................................................................
.......................................................................................
12-65. Display Subsystem Clock Tree .......................................................................................
12-66. Display Subsystem DMA Tree ........................................................................................
12-67. DSI Interrupt Tree ......................................................................................................
12-68. DISPC and DSS Interrupts Tree .....................................................................................
12-69. Display Subsystem Full Schematic ..................................................................................
12-70. Display Controller Architecture Overview ...........................................................................
12-71. Palette/Gamma Correction Architecture .............................................................................
12-72. YCbCr 4:2:2 to YCbCr 4:4:4 (0- or 180-Degree Rotation) ........................................................
12-73. YCbCr 4:2:2 to YCbCr 4:4:4 (90- or 270-Degree Rotation) .......................................................
12-74. Interpolation of the Missing Chrominance Component ............................................................
12-75. YCbCr to RGB Registers (VIDFULLRANGE=0)....................................................................
12-76. YCbCr to RGB Registers (VIDFULLRANGE=1)....................................................................
12-77. Color Space Conversion Macro-Architecture .......................................................................
12-78. Video Upsampling ......................................................................................................
12-79. Resampling Macro-Architecture (3-Coefficient Processing) ......................................................
12-80. Overlay Manager in Normal Mode ..................................................................................
12-81. Display Attributes in Normal Mode ..................................................................................
12-82. Overlay Manager in Alpha Mode ....................................................................................
12-83. Display Attributes in Alpha Mode .....................................................................................
12-84. Alpha Blending Macro Architecture ..................................................................................
12-85. Video Source Transparency Example ...............................................................................
12-86. Graphics Destination Transparency Example ......................................................................
12-87. Color Phase Rotation Matrix ..........................................................................................
12-88. Color Phase Rotation Macro Architecture ...........................................................................
12-89. DSI Protocol Engine....................................................................................................
12-90. DSI Transmitter/Receiver Data Flow .................................................................................
12-91. LP to HS Timing ........................................................................................................
12-92. HS to LP Timing ........................................................................................................
12-93. HS Command Mode Interleaving .....................................................................................
12-94. LP Command Mode Interleaving .....................................................................................
12-95. Complex I/O Power FSM ..............................................................................................
12-96. DSI PLL Power FSM ...................................................................................................
12-97. DSI PLL HS Clock FSM ...............................................................................................
12-98. ForceTxStopMode FSM ...............................................................................................
12-99. TurnRequest FSM ......................................................................................................
12-100. High-Speed TX Timer FSM ..........................................................................................
12-101. Low-Power RX Timer FSM ..........................................................................................
12-102. 64-Bit ECC Generation on TX Side .................................................................................
12-103. Checksum Transmission .............................................................................................
12-104. 16 Bit CRC Generation Using a Shift Register ....................................................................
12-105. DSI PLL Controller Overview ........................................................................................
1233
12-58. 16 Bits per Pixel RGB Color Format, Long Packet
12-63. TV Display Interface (Composite Mode)
12-64. Display Subsystem Integration
64
1230
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SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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12-106. DSI PLL Reference Diagram ........................................................................................
1304
12-107. DSI Complex I/O Architecture .......................................................................................
1306
12-108. RFBI Architecture Overview .........................................................................................
1307
12-109. Video Encoder Architecture Overview..............................................................................
1309
12-110. Closed Captioning Timing............................................................................................
1313
12-111. WSS Timing............................................................................................................
1315
12-112. Dual 10-Bit Video DAC Architecture ................................................................................
1316
12-113. DC-Coupling TV Detect Waveforms for TV Connected and Disconnected ...................................
1319
12-114. AC-Coupling TV Detect Waveforms for TV Connected and Disconnected
1319
12-115.
...................................
GPIO Signal Waveform Proposal for TV Detection/Disconnection in DC-Coupling Mode ..................
GPIO Signal Waveform Proposal for TV Detection/Disconnection in AC-Coupling Mode ..................
DAC Test Mode in Composite Video Mode .......................................................................
DAC Test Mode in Separate video Mode ..........................................................................
SDI Architecture Overview ...........................................................................................
Overlay Optimization: Case 1 .......................................................................................
Overlay Optimization: Case 2 .......................................................................................
Overlay Optimization: Case 3 .......................................................................................
Overlay Optimization: Case 4 .......................................................................................
90° DMA Rotation Example..........................................................................................
Rotation/Mirroring Settings...........................................................................................
90° Rotation With Mirroring ..........................................................................................
Offset for VRFB Rotation.............................................................................................
Offset for VRFB Rotation With Mirroring ...........................................................................
Timing Values Description (Active Matrix Display) ...............................................................
PCDmin Formulas (V Down-Sampling Only) ......................................................................
Color Phase Rotation Matrix .........................................................................................
Color Phase Rotation Matrix (R Component Only) ...............................................................
Color Phase Rotation Matrix (G Component Only) ...............................................................
Color Phase Rotation Matrix (B Component Only) ...............................................................
Diagonal Matrix Configuration .......................................................................................
Example - Diagonal Matrix Configuration ..........................................................................
Image With and Without CPR (Diagonal Matrix) ..................................................................
Example - Image With and Without CPR (Standard Matrix) ....................................................
DSI PLL Programming Blocks .......................................................................................
DSI PLL Go Sequence (Manual Mode) ............................................................................
DSI PLL Go Sequence (Automatic Mode) .........................................................................
Gated Mode Sequence ...............................................................................................
DSI PLL Programming Sequence...................................................................................
High-Speed Clock Transmission ....................................................................................
High-Speed Data Transmission .....................................................................................
Turn-Around Request in Transmit Mode ...........................................................................
Turn-Around Request in Receive Mode............................................................................
How to Use RFBI......................................................................................................
RFBI Initial Configuration ............................................................................................
RFBI Output Enable ..................................................................................................
SDI Start Sequence ...................................................................................................
SDI Stop Sequence ...................................................................................................
SDI Clock Source/Frequency Change Sequence Part A ........................................................
SDI Clock Source/Frequency Change Sequence Part B ........................................................
1320
12-116.
12-117.
12-118.
12-119.
12-120.
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12-149.
12-150.
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12-152.
12-153.
12-154.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Figures
1320
1321
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12-155. Vertical Filtering Macro Architecture (Three Taps) ...............................................................
1404
12-156. Vertical Filtering Macro Architecture (Five Taps) .................................................................
1405
12-157. Horizontal Filtering Macro Architecture (Five Taps) ..............................................................
1406
............................................................................
12-159. Horizontal Up-/Down-Sampling Algorithm .........................................................................
12-160. QVGA LCD Timings ..................................................................................................
12-161. SDI PLL Architecture .................................................................................................
12-162. Main Flowchart ........................................................................................................
12-163. Flowchart SDI 1-Data Pair ...........................................................................................
12-164. Flowchart SDI 2-Data Pairs ..........................................................................................
12-165. Flowchart SDI 3-Data Pairs ..........................................................................................
12-166. HVGA Display .........................................................................................................
12-167. Hardware Connections for FlatLink3G Application ...............................................................
12-168. SN65LVDS302 Receiver Modes and Transitions .................................................................
12-169. Overview ...............................................................................................................
12-170. Environment ...........................................................................................................
12-171. Display Subsystem Data Flow.......................................................................................
12-172. Display Controller Data Flow ........................................................................................
12-173. Display Panel Configuration for the Camcorder Use Case ......................................................
12-174. Display Subsystem Configuration for Camcorder Use Case ....................................................
12-175. Display Subsystem Initialization .....................................................................................
12-176. Software Reset Flowchart............................................................................................
12-177. Display Panel Configuration Flowchart .............................................................................
12-178. QVGA LCD Panel Timings ...........................................................................................
12-179. DSI Clock Tree in Video Mode ......................................................................................
12-180. Overview ...............................................................................................................
12-181. Overview ...............................................................................................................
13-1. Timers ....................................................................................................................
13-2. GP Timers Overview ...................................................................................................
13-3. GP Timers External System Interface ...............................................................................
13-4. GP Timer Integration ...................................................................................................
13-5. Wake-Up Request Generation ........................................................................................
13-6. Block Diagram of GPTIMER3 through GPTIMER9 and GPTIMER11 ...........................................
13-7. Block Diagram of GPTIMER1, GPTIMER2, and GPTIMER10 ...................................................
13-8. GPTi.TCRR Timing Value .............................................................................................
13-9. Block Diagram of the 1-ms Tick Module.............................................................................
13-10. Capture Wave Example for GPTi.TCLR[13] CAPT_MODE = 0 ..................................................
13-11. Capture Wave Example for GPTi.TCLR[13] CAPT_MODE = 1 ..................................................
13-12. Timing Diagram of PWM With GPTi.TCLR[7] SCPWM Bit = 0 ...................................................
13-13. Timing Diagram of PWM With GPTi.TCLR[7] SCPWM Bit = 1 ...................................................
13-14. WDTs Block Diagram ..................................................................................................
13-15. WDT Integration ........................................................................................................
13-16. 32-Bit WDT Functional Block Diagram ..............................................................................
13-17. WDT General Functional View .......................................................................................
13-18. 32-kHz Sync Timer Block Diagram ..................................................................................
14-1. UART Module ...........................................................................................................
14-2. UART Mode Bus System Overview ..................................................................................
14-3. IrDA System Overview .................................................................................................
14-4. CIR System Overview .................................................................................................
1407
12-158. Vertical Up-/Down-Sampling Algorithm
66
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SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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14-5.
UART Frame Data Format ............................................................................................
1694
14-6.
IrDA SIR Frame Format ...............................................................................................
1695
14-7.
IrDA SIR Encoding Mechanism .......................................................................................
1696
14-8.
IrDA SIR Decoding Mechanism
......................................................................................
SIR Free Format Mode ................................................................................................
MIR Transmit Frame Format ..........................................................................................
MIR Baud Rate Adjustment Mechanism ............................................................................
SIP ........................................................................................................................
CIR Pulse Modulation ..................................................................................................
CIR Modulation Duty Cycle ...........................................................................................
RC-5 Bit Encoding ......................................................................................................
SIRC Bit Encoding .....................................................................................................
RC-5 Standard Packet Format .......................................................................................
SIRC Packet Format ...................................................................................................
SIRC Bit Transmission Example .....................................................................................
UART Functional Integration ..........................................................................................
UART/IrDA/CIR Block Diagram .......................................................................................
FIFO Management Registers .........................................................................................
Receive FIFO Interrupt Request Generation .......................................................................
Transmit FIFO Interrupt Request Generation .......................................................................
Receive FIFO DMA Request Generation (32 Characters) ........................................................
Transmit FIFO DMA Request Generation (56 Spaces) ...........................................................
Transmit FIFO DMA Request Generation (8 Spaces) .............................................................
Transmit FIFO DMA Request Generation (1 Space) ..............................................................
Transmission Process .................................................................................................
Reception Process .....................................................................................................
Baud Rate Generation .................................................................................................
Baud Rate Generator ..................................................................................................
CIR Mode Block Components ........................................................................................
HS I2C Controllers ......................................................................................................
Multimaster HS I2C Controllers and Typical Connections to I2C Devices .......................................
Multimaster HS I2C Controller Interface Signals in I2C Mode .....................................................
I2C Data Transfer .......................................................................................................
Bit Transfer on the I2C Bus ............................................................................................
S and P Condition Events .............................................................................................
I2C Data Transfer Formats in F/S Mode .............................................................................
I2C Data Transfers in HS Mode .......................................................................................
Arbitration Between Master Transmitters............................................................................
Synchronization of I2C Clock Generators............................................................................
Multimaster HS I2C Controllers and Typical Connections to SCCB Devices ...................................
Multimaster HS I2C Controller Interface Signals in SCCB Mode .................................................
3-wire SCCB Transmission Timing Diagram........................................................................
SCCB Transmission Data Formats ..................................................................................
Typical Connection Between the HS I2C Controller and Power Chip(s) ........................................
HS I2C Controller I2C4 Interface Signals ............................................................................
I2C Data Transfer Format in F/S Mode for the I2C4 Module......................................................
I2C Data Transfer Format in HS Mode for the I2C4 Module ......................................................
HS I2C Controller Integration ..........................................................................................
Wake-up Generation Flow.............................................................................................
1697
14-9.
14-10.
14-11.
14-12.
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15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Figures
1698
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15-21. Multimaster HS I C Controller Block Diagram ......................................................................
2
.......................................................................
1824
15-23. Transmit FIFO Interrupt Request Generation .......................................................................
1824
15-24. Receive FIFO DMA Request Generation
1825
15-25.
...........................................................................
Transmit FIFO Request Generation (High Threshold).............................................................
Transmit FIFO Request Generation (Low Threshold) .............................................................
I2C Clock Generation ...................................................................................................
I2C Setup Procedure ...................................................................................................
I2C Master Transmitter Mode, Polling Method, in F/S and HS Modes ..........................................
I2C Master Receiver Mode, Polling Method, in F/S and HS Modes .............................................
I2C Master Transmitter Mode, Interrupt Method, in F/S and HS Modes.........................................
I2C Master Receiver Mode, Interrupt Method, in F/S and HS Modes............................................
I2C Master Transmitter Mode, DMA Method in F/S and HS Modes .............................................
I2C Master Receiver Mode, DMA Method in F/S and HS Modes ................................................
I2C Slave Transmitter/Receiver Mode, Polling ......................................................................
I2C Slave Transmitter/Receiver Mode, Interrupt ....................................................................
SCCB Setup Procedure ...............................................................................................
SCCB Master Transmitter Mode, Polling ............................................................................
SCCB Master Receiver Mode, Polling ...............................................................................
SCCB Master Transmitter Mode, Interrupt ..........................................................................
SCCB Master Receiver Mode, Interrupt .............................................................................
Multichannel Modules SPI1, SPI2, SPI3, and SPI4 ................................................................
Typical Application Using the McSPI ................................................................................
McSPI Master Mode (Full-Duplex) ...................................................................................
McSPI Master Single Mode (Receive-Only) ........................................................................
McSPI Slave Mode (Full Duplex) .....................................................................................
McSPI Slave Single Mode (Transmit Only) .........................................................................
McSPI Interface Signals in Master Mode............................................................................
McSPI Interface Signals in Slave Mode .............................................................................
Phase and Polarity Combinations ....................................................................................
Full-Duplex Transfer Format With PHA = 0 .........................................................................
Extended SPI Transfer With a Start-Bit (SBE = 1) .................................................................
McSPI Integration ......................................................................................................
McSPI Block Diagram ..................................................................................................
SPI Full-Duplex Transmission (Example) ...........................................................................
Continuous Transfers With spim_csx Maintained Active (Single-Data-Pin Interface Mode) .................
Continuous Transfers With spim_csx Maintained Active (Dual-Data-Pin Interface Mode) ...................
Chip-Select SPIEN Timing Controls .................................................................................
Example of McSPI Slave With One Master and Multiple Slave Devices on Channel 0.......................
SPI Half-Duplex Transmission (Transmit-Only Slave) .............................................................
SPI Half-Duplex Transmission (Receive-Only Slave)..............................................................
Buffer Use in Transmit Direction Only ...............................................................................
Buffer Use in Receive Direction Only ................................................................................
Buffer Used For Both Transmit/Receive Directions ................................................................
Buffer Almost Full Level (AFL) ........................................................................................
Buffer Almost Empty Level (AEL) ....................................................................................
Module Initialization Flow ..............................................................................................
Common Transfer Sequence: Main Process .......................................................................
Transmit and Receive (Master and Slave) ..........................................................................
1826
15-22. Receive FIFO Interrupt Request Generation
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
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15-37.
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15-41.
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16-2.
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16-28.
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SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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16-29. Transmit-Only With Interrupts (Master and Slave) .................................................................
1913
16-30. Transmit-Only With DMA (Master and Slave) ......................................................................
1914
......................................................................
Receive-Only With DMA (Master Normal) ..........................................................................
Receive-Only With Interrupt (Master Turbo) ........................................................................
Receive-Only With DMA (Master Turbo) ............................................................................
Receive Only (Slave)...................................................................................................
Two SPI Transfers With PHA = 0 (Flexibility of McSPI) ...........................................................
Common Transfer Sequence/Main Process ........................................................................
Transmit-Receive With Word Count .................................................................................
Transmit-Receive Without Word Count ..............................................................................
Transmit-Only ...........................................................................................................
Receive-Only With Word Count ......................................................................................
Receive-Only Without Word Count...................................................................................
Overview .................................................................................................................
Environment .............................................................................................................
McSPI Data Flow .......................................................................................................
HDQ/1-Wire Highlight ..................................................................................................
HDQ/1-Wire Typical Application System Overview ................................................................
HDQ Break-Pulse Timing Diagram...................................................................................
1-Wire (SDQ) Reset Timing Diagram ................................................................................
HDQ/1-Wire Transmitted Bit Timing .................................................................................
HDQ/1-Wire Communication Sequence .............................................................................
HDQ/1-Wire Integration ................................................................................................
HDQ/1-Wire Block Diagram ...........................................................................................
Protocol Registers Description........................................................................................
Environment .............................................................................................................
HDQ/1-Wire Configuration in HDQ Mode ...........................................................................
Software Reset Flowchart .............................................................................................
McBSP Highlight ........................................................................................................
SIDETONE Core Architecture ........................................................................................
Mode Overview of McBSP1 Module .................................................................................
Mode Overview of McBSPi Module ..................................................................................
DBB Data Application ..................................................................................................
Audio Data Application.................................................................................................
Voice Data Application .................................................................................................
McBSP Reception/Transmission Signal Activity....................................................................
Serial Data Formats ....................................................................................................
TDM Data Format; Word Width: 32 Bits; Data Length: 24 Bits ..................................................
I2S Data Format; Word Width: 32 Bits; Data Length: 24 Bits ....................................................
Left Justified Data Format; Word Width: 32 Bits; Data Length: 24 Bits .........................................
Right Justified Data Format; Word Width: 32 Bits; Data Length: 24 Bits .......................................
PCM Protocol - Mode 1 Data Format ................................................................................
PCM Protocol - Mode 2 Data Format ................................................................................
McBSP1 Integration ....................................................................................................
McBSP2 Integration ....................................................................................................
McBSP3 Integration ....................................................................................................
McBSP4 Integration ....................................................................................................
McBSP5 Integration ....................................................................................................
16-31. Receive Only With Interrupt (Master Normal)
1915
16-32.
1916
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
SPRUGR0C – October 2009 – Revised November 2013
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List of Figures
1917
1918
1919
1920
1923
1925
1926
1927
1928
1929
1930
1931
1932
1958
1959
1960
1960
1961
1961
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1965
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1990
1990
1991
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1994
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1994
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18-21. McBSP1, McBSP4 and McBSP5 Block Diagrams .................................................................
2017
18-22. McBSP2 Block Diagram ...............................................................................................
2018
18-23. McBSP3 Block Diagram ...............................................................................................
2019
18-24. McBSP Data Transfer Paths ..........................................................................................
2020
........................................................................................
2020
18-25. McBSP2 Data Transfer Paths
18-26. Conceptual Block Diagram for Clock and Frame Generation When MCBSPLP_SPCR1_REG[15] ALB =
0 and CONTROL_DEVCONF0[3] MCBSP1_CLKR = 0 ...........................................................
2021
18-27. Clock Signal Control of Bit Transfer Timing .........................................................................
2023
18-28. McBSP Operating at Maximum Packet Frequency ................................................................
2025
18-29. Single-Phase Frame for a McBSP Data Transfer ..................................................................
2027
18-30. Dual-Phase Frame for a McBSP Data Transfer ....................................................................
2027
18-31. McBSP Reception Physical Data Path ..............................................................................
2028
18-32. McBSP Reception Signal Activity
2028
18-33.
....................................................................................
McBSP Transmission Physical Data Path ..........................................................................
McBSP Transmission Signal Activity ................................................................................
Transmit Full Cycle Timing Diagram .................................................................................
Transmit Half Cycle Timing Diagram ................................................................................
Receive Full Cycle Timing Diagram ..................................................................................
Receive Half Cycle Timing Diagram .................................................................................
Conceptual Block Diagram of the Sample Rate Generator .......................................................
CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 0x1) .............................
CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 0x3) .............................
Overrun in the McBSP Receiver .....................................................................................
Unexpected Frame-sync Pulse During a McBSP Reception .....................................................
Proper Positioning of Receive Frame-sync Pulses ................................................................
Unexpected Frame-sync Pulse During a McBSP Transmission .................................................
Proper Positioning of Transmit Frame-sync Pulses................................................................
McBSP Data Transfer in 8-Partition Mode ..........................................................................
Alternating Between Partitions A and B Channels .................................................................
Activity on McBSP Pins When XMCM=0b00 .......................................................................
Activity on McBSP Pins When XMCM=0b01 .......................................................................
Activity on McBSP Pins When XMCM=0b10 .......................................................................
Activity on McBSP Pins When XMCM=0b11 .......................................................................
SIDETONE Data Path .................................................................................................
McBSP to SIDETONE Data Exchange ..............................................................................
SIDETONE to McBSP Data Exchange ..............................................................................
SIDETONE Processed Data Interfaces .............................................................................
Flow Diagram of McBSP Initialization Procedure for Master Mode ..............................................
Flow Diagram of McBSP Initialization Procedure for Slave Mode ...............................................
Flow Diagram for the SRG Registers Programmation .............................................................
Important Tasks to Configure the McBSP Receiver (Part 1) .....................................................
Important Tasks to Configure the McBSP Receiver (Part 2) .....................................................
Range of Programmable Data Delay ................................................................................
2-Bit Data Delay Used to Skip a Framing Bit .......................................................................
Data Externally Clocked on a Rising Edge and Sampled on a Falling Edge ...................................
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ......................................
Important Tasks to Configure the McBSP Transmitter (Part 1) ..................................................
Important Tasks to Configure the McBSP Transmitter (Part 2) ..................................................
Range of Programmable Data Delay ................................................................................
2029
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
18-63.
18-64.
18-65.
18-66.
18-67.
18-68.
70
List of Figures
2029
2030
2031
2031
2031
2032
2036
2036
2038
2038
2039
2040
2041
2044
2045
2047
2047
2047
2048
2049
2050
2050
2051
2054
2055
2058
2062
2063
2065
2066
2068
2069
2071
2072
2074
SPRUGR0C – October 2009 – Revised November 2013
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18-69. 2-Bit Data Delay Used to Skip a Framing Bit .......................................................................
2074
18-70. Four 8-bit Data Words Transferred To/From McBSP Module ....................................................
2079
18-71. One 32-bit Data Word Transferred To/From McBSP Module ....................................................
2079
18-72. 8-bit Data Words Transferred at Maximum Packet Frequency ...................................................
2080
18-73. Configuring the Data Stream as a Continuous 32-bit Word
......................................................
....................................................................................
MMC/SD/SDIO2 Overview ............................................................................................
MMC/SD/SDIO Connected to an MMC, an SD, or an SDIO Card Without External Transceiver ...........
MMC/SD/SDIO2 Connected to an MMC, an SD, or an SDIO Card with External Transceiver ..............
MMC/SD/SDIOi Interface Signals ....................................................................................
MMC/SD/SDIO2 Interface Signals ...................................................................................
Sequential Read Operation (MMC Cards Only) ....................................................................
Sequential Write Operation (MMC Cards Only) ....................................................................
Multiple Block Read Operation .......................................................................................
Multiple Block Write Operation with Card Busy Signal ............................................................
Command Token Format ..............................................................................................
Response Token Format (R1, R3, R4, R5, R6) ....................................................................
Response Token Format (R2) ........................................................................................
Data Token Format for 1-Bit Transfers ..............................................................................
Data Token Format for 4-Bit Transfers ..............................................................................
Data Token Format for 8-Bit Transfers ..............................................................................
MMC/SD/SDIO1 Integration ...........................................................................................
DMA Receive Mode ....................................................................................................
DMA Transmit Mode ...................................................................................................
MMC/SD/SDIO Diagram ...............................................................................................
Buffer Management for a Write .......................................................................................
Buffer Management for a Read .......................................................................................
MMC/SD/SDIO Controller Meta Initialization Steps ................................................................
MMC/SD/SDIO Controller Software Reset Flow ...................................................................
MMC/SD/SDIO Controller Wake-Up Configuration ................................................................
MMC/SD/SDIO Controller Bus Configuration .......................................................................
MMC/SD/SDIO Controller Card Identification and Selection - Part 1............................................
MMC/SD/SDIO Controller Card Identification and Selection - Part 2............................................
MMC/SD/SDIO Controller Read/Write Transfer Flow in DMA Mode with Interrupt ............................
MMC/SD/SDIO Controller Read/Write Transfer Flow in DMA Mode with Polling ..............................
MMC/SD/SDIO Controller Read/Write Transfer Flow without DMA with Polling ...............................
MMC/SD/SDIO Controller Read/Write in CE-ATA Mode ..........................................................
MMC/SD/SDIO Controller Suspend Flow ...........................................................................
MMC/SD/SDIO Controller Resume Flow ............................................................................
MMC/SD/SDIO Controller Command Transfer Flow with Polling ................................................
MMC/SD/SDIO Controller Command Transfer Flow with Interrupts .............................................
MMC/SD/SDIO Controller Clock Frequency Change Flow .......................................................
Overview .................................................................................................................
Environment .............................................................................................................
Command Transfer .....................................................................................................
Data Read Transfer ....................................................................................................
Data Write Transfer ....................................................................................................
USB Modules Overview ...............................................................................................
USB Subsystem Block Diagram ......................................................................................
2080
19-1.
2142
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
20-1.
20-2.
MMC/SD/SDIO1 and 3 Overview
SPRUGR0C – October 2009 – Revised November 2013
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List of Figures
2143
2145
2146
2146
2147
2148
2148
2149
2149
2150
2150
2150
2151
2151
2152
2153
2158
2159
2162
2165
2166
2170
2171
2172
2173
2174
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2178
2179
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2182
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2184
2185
2186
2186
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2187
2236
2239
71
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20-3.
USB20OTG_F Block Diagram ........................................................................................
20-4.
USB Control Register ..................................................................................................
2256
20-5.
USB Status Register ...................................................................................................
2257
20-6.
USB Auto Req Register
...............................................................................................
USB Teardown Register ...............................................................................................
USB Endpoint Interrupt Source Register ............................................................................
USB Endpoint Interrupt Source Set Register .......................................................................
USB Endpoint Interrupt Source Clear Register .....................................................................
USB Endpoint Interrupt Mask Register ..............................................................................
USB Endpoint Interrupt Mask Set Register .........................................................................
USB Endpoint Interrupt Mask Clear Register .......................................................................
USB Endpoint Interrupt Source Masked Register ..................................................................
USB Core Interrupt Source Register .................................................................................
USB Core Interrupt Source Set Register ............................................................................
USB Core Interrupt Source Clear Register .........................................................................
USB Core Interrupt Mask Register ...................................................................................
USB Core Interrupt Mask Set Register ..............................................................................
USB Core Interrupt Mask Clear Register............................................................................
USB Core Interrupt Source Masked Register ......................................................................
USB End of Interrupt Register ........................................................................................
USB MOP/SOP Interrupt Enable Register ..........................................................................
USB Tx Mode Register ................................................................................................
USB Rx Mode Register ................................................................................................
USB EP Count Mode Register........................................................................................
USB Generic RNDIS EP N Size Register ..........................................................................
USB Queue Interrupt Threshold Enable Register ..................................................................
USB Queue Threshold Register 0 ...................................................................................
USB Interrupt Clear Register 0 .......................................................................................
USB Queue Threshold Register 1 ...................................................................................
USB Interrupt Clear Register 1 .......................................................................................
CDMA Tx Channel N Global Configuration Register ..............................................................
CDMA Rx Channel N Global Configuration Register ..............................................................
CDMA Rx Channel N Host Packet Configuration Register A.....................................................
CDMA Rx Channel N Host Packet Configuration Register B.....................................................
CDMA Scheduler Control Register ..................................................................................
CDMA Scheduler Table Word N Registers .........................................................................
INTD Revision Register ................................................................................................
INTD EOI Register .....................................................................................................
INTD EOI Interrupt Vector Register ..................................................................................
INTD Status Register 0 ................................................................................................
INTD Status Register 1 ................................................................................................
INTD Status Register 2 ................................................................................................
INTD Status Register 3 ................................................................................................
INTD Status Clear Register 0 .........................................................................................
Queue Manager Revision Register ..................................................................................
Queue Manager Queue Diversion Register.........................................................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 ...........................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 ...........................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 ...........................................
2258
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
72
List of Figures
2239
2261
2262
2262
2263
2263
2264
2264
2265
2265
2266
2266
2267
2267
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2269
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2277
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2288
2289
2290
2291
2292
2295
2296
2297
2298
2299
2300
2301
SPRUGR0C – October 2009 – Revised November 2013
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20-52. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 ...........................................
2302
20-53. Queue Manager Free Descriptor/Buffer Starvation Count Register 4 ...........................................
2303
20-54. Queue Manager Free Descriptor/Buffer Starvation Count Register 5 ...........................................
2304
20-55. Queue Manager Free Descriptor/Buffer Starvation Count Register 6 ...........................................
2305
20-56. Queue Manager Free Descriptor/Buffer Starvation Count Register 7 ...........................................
2306
20-57. Queue Manager Linking RAM Region 0 Base Address Register ................................................
2307
...........................................................
2308
20-59. Queue Manager Linking RAM Region 1 Base Address Register ................................................
2308
20-60. Queue Manager Queue Pending Register 0
2309
20-61.
.......................................................................
Queue Manager Queue Pending Register 1 .......................................................................
Queue Manager Queue Pending Register 2 .......................................................................
Queue Manager Memory Region R Base Address Register .....................................................
Queue Manager Memory Region R Control Register .............................................................
Queue Manager Queue N Register A ...............................................................................
Queue Manager Queue N Register B ...............................................................................
Queue Manager Queue N Register C ...............................................................................
Queue Manager Queue N Register D ...............................................................................
Queue Manager Queue N Status Register A .......................................................................
Queue Manager Queue N Status Register B .......................................................................
Queue Manager Queue N Status Register C .......................................................................
High-Speed USB Host Subsystem Highlight........................................................................
USB Connection ........................................................................................................
High-Speed USB Host Controller Connection—With and Without TLL .........................................
High-Speed USB Host Controller Typical Application System – ULPI Interfaces..............................
High-Speed USB Host Subsystem Typical Application System - ULPI TLL Interfaces .......................
ULPI Interfaces – 12-Pin/8-Bit Data SDR Version .................................................................
ULPI TLL Interfaces –12-Pin/8-Bit Data SDR Version ............................................................
ULPI TLL Interfaces – 8-Pin/4-Bit Data DDR Version .............................................................
High-Speed USB Host Subsystem Functional Interface Signals .................................................
High-Speed USB Host Subsystem Typical Application System ..................................................
Serial Interface Sideband Integration - Transceiver Configuration...............................................
Serial Interface Sideband Integration - TLL Configuration ........................................................
6-Pin Unidirectional Using DAT/SE0 Signaling .....................................................................
6-Pin Unidirectional Using DP/DM Signaling .......................................................................
3-Pin Bidirectional Using DAT/SE0 Signaling ......................................................................
4-Pin Bidirectional Using DP/DM Signaling .........................................................................
6-Pin Unidirectional TLL Using DAT/SE0 Signaling ...............................................................
6-Pin Unidirectional TLL Using DP/DM Signaling ..................................................................
3-Pin Bidirectional TLL Using DAT/SE0 Signaling .................................................................
4-Pin Bidirectional TLL Using DP/DM Signaling....................................................................
2-Pin Bidirectional TLL Using DP/DM Encoding, With 4-Pin Bidirectional USB Device ......................
2-Pin Bidirectional TLL Using DAT/SE0 Encoding, With 3-Pin Bidirectional USB Device ....................
High-Speed USB Subsystem Integration ............................................................................
High-Speed USB Host Controller Architecture .....................................................................
USBTLL Channel .......................................................................................................
Per-Configuration Datapath Through USBTLL .....................................................................
Selecting and Configuring High-Speed USB Host Subsystem Connectivity....................................
General-Purpose Interface Overview ................................................................................
General-Purpose Interface Typical Application System Overview ...............................................
2309
20-58. Queue Manager Linking RAM Region 0 Size Register
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
20-82.
20-83.
20-84.
20-85.
20-86.
20-87.
20-88.
20-89.
20-90.
20-91.
20-92.
20-93.
20-94.
20-95.
20-96.
20-97.
20-98.
21-1.
21-2.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Figures
2310
2310
2311
2312
2313
2313
2314
2314
2315
2315
2317
2319
2320
2321
2322
2323
2324
2325
2326
2329
2333
2333
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2334
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2337
2337
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2338
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2343
2352
2355
2358
2364
2454
2455
73
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21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
74
.......................................................
General-Purpose Interface Integration Overview ..................................................................
General-Purpose Interface Description ..............................................................................
Synchronous Path ......................................................................................................
Asynchronous Path.....................................................................................................
Interrupt Request Generation .........................................................................................
Wake-Up Request Generation ........................................................................................
Write @GPIO_CLEARDATAOUT Register Example ..............................................................
Write @GPIO_SETIRQENABLEx Register Example ..............................................................
EMAC and MDIO Block Diagram .....................................................................................
Ethernet Configuration—RMII Connections .........................................................................
Ethernet Frame Format ................................................................................................
Basic Descriptor Format ...............................................................................................
Typical Descriptor Linked List.........................................................................................
Transmit Buffer Descriptor Format ...................................................................................
Receive Buffer Descriptor Format ....................................................................................
VBUS MII Management Interface Module...........................................................................
EMAC Module Block Diagram ........................................................................................
Revision ID Register (REVID) ........................................................................................
Software Reset Register (SOFTRESET) ............................................................................
Interrupt Control Register (INTCONTROL) .........................................................................
Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (CnRXTHRESHEN) ........................
Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN)................................................
Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...............................................
Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) .....................................
Interrupt Core 0-2 Receive Threshold Interrupt Status Register (CnRXTHRESHSTAT) .....................
Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .............................................
Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) .............................................
Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT) ...................................
Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) .................................
Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .................................
MDIO Revision ID Register (REVID).................................................................................
MDIO Control Register (CONTROL) .................................................................................
PHY Acknowledge Status Register (ALIVE) ........................................................................
PHY Link Status Register (LINK) .....................................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ....................................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ..................................
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ...........................
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) .........................
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ........................
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .................
MDIO User Access Register 0 (USERACCESS0) .................................................................
MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................
MDIO User Access Register 1 (USERACCESS1) .................................................................
MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................
Transmit Revision ID Register (TXREVID) ..........................................................................
Transmit Control Register (TXCONTROL) ..........................................................................
Transmit Teardown Register (TXTEARDOWN) ....................................................................
Receive Revision ID Register (RXREVID) ..........................................................................
General-Purpose Interface Used as a Keyboard Interface
List of Figures
2456
2458
2465
2465
2466
2467
2468
2470
2471
2495
2497
2498
2500
2501
2504
2509
2513
2517
2543
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2557
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2559
2560
2561
2562
2563
2564
2565
2566
2567
2572
2572
2573
2574
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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..........................................................................
Receive Teardown Register (RXTEARDOWN) ....................................................................
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ............................................
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)...........................................
Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................
MAC Input Vector Register (MACINVECTOR) .....................................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) ......................................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) .............................................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ...........................................
Receive Interrupt Mask Set Register (RXINTMASKSET) .........................................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..............................................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED).............................................
MAC Interrupt Mask Set Register (MACINTMASKSET) ..........................................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ....................................................
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ....................
Receive Unicast Enable Set Register (RXUNICASTSET) ........................................................
Receive Unicast Clear Register (RXUNICASTCLEAR) ...........................................................
Receive Maximum Length Register (RXMAXLEN) ................................................................
Receive Buffer Offset Register (RXBUFFEROFFSET)............................................................
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ...........................
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) ...................................
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ..........................................
MAC Control Register (MACCONTROL) ............................................................................
MAC Status Register (MACSTATUS) ...............................................................................
Emulation Control Register (EMCONTROL) ........................................................................
FIFO Control Register (FIFOCONTROL)............................................................................
MAC Configuration Register (MACCONFIG) .......................................................................
Soft Reset Register (SOFTRESET) ..................................................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) ................................................
MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................
MAC Hash Address Register 1 (MACHASH1) .....................................................................
MAC Hash Address Register 2 (MACHASH2) .....................................................................
Back Off Random Number Generator Test Register (BOFFTEST)..............................................
Transmit Pacing Algorithm Test Register (TPACETEST) .........................................................
Receive Pause Timer Register (RXPAUSE) ........................................................................
Transmit Pause Timer Register (TXPAUSE) .......................................................................
MAC Address Low Bytes Register (MACADDRLO) ...............................................................
MAC Address High Bytes Register (MACADDRHI)................................................................
MAC Index Register (MACINDEX) ...................................................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) ........................................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) ........................................
Transmit Channel n Completion Pointer Register (TXnCP) ......................................................
Receive Channel n Completion Pointer Register (RXnCP) .......................................................
Statistics Register ......................................................................................................
CAN Data Frame .......................................................................................................
Architecture of the SCC and HECC CAN Controllers .............................................................
SCC Functional Block Diagram .......................................................................................
22-41. Receive Control Register (RXCONTROL)
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
22-51.
22-52.
22-53.
22-54.
22-55.
22-56.
22-57.
22-58.
22-59.
22-60.
22-61.
22-62.
22-63.
22-64.
22-65.
22-66.
22-67.
22-68.
22-69.
22-70.
22-71.
22-72.
22-73.
22-74.
22-75.
22-76.
22-77.
22-78.
22-79.
22-80.
22-81.
22-82.
22-83.
22-84.
22-85.
22-86.
23-1.
23-2.
23-3.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Figures
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2587
2587
2588
2588
2589
2592
2593
2594
2594
2595
2595
2596
2597
2599
2601
2602
2603
2604
2605
2605
2606
2607
2608
2609
2610
2610
2611
2612
2612
2613
2613
2614
2614
2615
2629
2630
2631
75
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23-4.
SCC Memory Map ......................................................................................................
2633
23-5.
HECC Functional Block Diagram .....................................................................................
2634
23-6.
HECC Memory Map ....................................................................................................
2636
23-7.
Configuration Sequence ...............................................................................................
2642
23-8.
Partition of the Bit Time ................................................................................................
2643
23-9.
SCC Interrupts Scheme Block Diagram .............................................................................
2645
23-10. HECC Interrupts Scheme Diagram
2653
23-12.
..................................................................................
...........................................................................
Mailbox Direction Register (CANMD) [04h] .........................................................................
Transmission Request Set Register (CANTRS) [08h] .............................................................
Transmission Request Reset Register (CANTRR) [0Ch] .........................................................
Transmission Acknowledge Register (CANTA) [10h] ..............................................................
Abort Acknowledge Register (CANAA) [14h] .......................................................................
Receive Message Pending Register (CANRMP) [18h] ............................................................
Receive Message Lost Register (CANRML) [1Ch] ................................................................
Remote Frame Pending Register (CANRFP) [20h] ................................................................
Global Acceptance Mask Register (CANGAM) [24h] ..............................................................
Master Control Register (CANMC) [28h] ............................................................................
Bit-Timing Configuration Register (CANBTC) [2Ch] ...............................................................
Error and Status Register (CANES) [30h] ...........................................................................
Transmit Error Counter Register (CANTEC) [34h] .................................................................
Receive Error Counter Register (CANREC) [38h] .................................................................
Global Interrupt Flag 0 Register (CANGIF0) [3Ch].................................................................
Global Interrupt Flag 1 Register (CANGIF1) [44h] .................................................................
Global Interrupt Mask Register (CANGIM) [40h] ...................................................................
Mailbox Interrupt Mask Register (CANMIM) [48h] .................................................................
Mailbox Interrupt Level Register (CANMIL) [4Ch] ..................................................................
Overwrite Protection Control Register (CANOPC) [50h] ..........................................................
Transmit I/O Control Register (CANTIOC) [54h] ...................................................................
Receive I/O Control Register (CANRIOC) [58h]....................................................................
Local Network Time Register (CANLNT) ............................................................................
Message Object Time Stamp Register (CANMOTS) [100h] ......................................................
Message Object Time-Out Registers (CANMOTO) [180h] .......................................................
Time-Out Control Register (CANTOC) [60h]........................................................................
Time-Out Status Register (CANTOS) [64h] .........................................................................
Message Identifier Register (CANMID) [00h] .......................................................................
Message Control Field Register (CANMCF) [04h] .................................................................
Message Data Low Register with DBO = 0 (CANMDL) [08h] ....................................................
Message Data High Register with DBO = 0 (CANMDH) [0Ch] ...................................................
Message Data Low Register with DBO = 1 (CANMDL) [08h] ....................................................
Message Data High Register with DBO = 1 (CANMDH) [0Ch] ...................................................
Local Acceptance Mask Register (CANLAM) [3000h] .............................................................
Initialization Process ...................................................................................................
Power Connections.....................................................................................................
Clock and Reset Environment ........................................................................................
Clock Interface ..........................................................................................................
ROM Code Architecture ...............................................................................................
32KB ROM Memory Map ..............................................................................................
64KB RAM Memory Map of GP Devices ............................................................................
2646
23-11. Mailbox Enable Register (CANME) [00h]
2654
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
23-45.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
76
List of Figures
2655
2656
2657
2658
2659
2660
2661
2662
2663
2666
2668
2670
2671
2672
2672
2674
2676
2677
2678
2679
2680
2681
2681
2682
2682
2683
2684
2685
2686
2686
2686
2686
2687
2690
2691
2693
2694
2703
2704
2706
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
............................................................................................
Device List Set-Up .....................................................................................................
Common Peripheral Booting Protocol ...............................................................................
Peripheral Booting Procedure ........................................................................................
Customer USB Descriptor Selection .................................................................................
Dumb Servers Boot Response .......................................................................................
EMAC Boot Packet Sequences ......................................................................................
Fast External Boot ......................................................................................................
Memory Booting ........................................................................................................
Detailed Memory Booting for Non-XIP Devices ....................................................................
NAND Device Detection ...............................................................................................
NAND ID2 Detection ...................................................................................................
NAND Invalid Block Detection ........................................................................................
OneNAND Read Sector ...............................................................................................
MMC/SD Booting .......................................................................................................
MMC/SD Detection Procedure........................................................................................
SD/MMC Booting .......................................................................................................
MBR Detection Procedure.............................................................................................
Get MBR Partition ......................................................................................................
Image Format ...........................................................................................................
Image Header Format .................................................................................................
Overall Booting Sequence
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Figures
2708
2710
2711
2713
2718
2720
2722
2724
2725
2726
2731
2732
2734
2736
2738
2739
2741
2745
2746
2747
2748
77
www.ti.com
List of Tables
1-1.
Device Peripherals .......................................................................................................
142
1-2.
Subsystem, Co-Processor, and Peripheral Support Matrixon the (ZCN Package)
.............................
Device Identification Registers .........................................................................................
Chip Identification ........................................................................................................
CONTROL_IDCODE Register Definition .............................................................................
Revision Number Value .................................................................................................
Hawkeye Number Value ................................................................................................
CONTROL_DIE_ID ......................................................................................................
Global Memory Space Mapping .......................................................................................
L3 Control Register Mapping ...........................................................................................
L4-Core Memory Space Mapping .....................................................................................
L4-Wakeup Memory Space Mapping .................................................................................
L4-Peripheral Memory Space Mapping ...............................................................................
L4-Emulation Memory Space Mapping ...............................................................................
Register Access Restrictions ...........................................................................................
L3 Interconnect View of the IPSS Memory Space...................................................................
MPU Clock Generator Clock Signals ..................................................................................
MPU Subsystem Reset Signals ........................................................................................
ARM Core Key Features ................................................................................................
MPU Subsystem Clock Signal .........................................................................................
ARM Reset Signals ......................................................................................................
Bridge Clock Signals ....................................................................................................
MPU Subsystem Reset Signal .........................................................................................
Bridge Clock Signals ....................................................................................................
MPU Subsystem Reset Signal .........................................................................................
Overview of the MPU Subsystem Power Domain ...................................................................
MPU Power States.......................................................................................................
MPU DPLL Power Modes...............................................................................................
MPU Retention Modes ..................................................................................................
MPU Subsystem Operation Power Modes ...........................................................................
Power Mode Allowable Transitions ....................................................................................
States of a Clock Domain ...............................................................................................
External Clock Signal Descriptions ....................................................................................
External Reset Signals Description ....................................................................................
PRCM Reset Signals ....................................................................................................
Global Reset Sources ...................................................................................................
Local Reset Sources ....................................................................................................
MPU Domain Reset Signals ............................................................................................
NEON Domain Reset Signal ...........................................................................................
CORE Domain Reset Signals ..........................................................................................
DSS Domain Reset Signal ..............................................................................................
USBHOST Domain Reset Signal ......................................................................................
SGX Domain Reset Signal .............................................................................................
WKUP Domain Reset Signals ..........................................................................................
PER Domain Reset Signal ..............................................................................................
DPLL Domain Reset Signals ...........................................................................................
EFUSE Domain Reset Signal ..........................................................................................
143
1-3.
1-4.
1-5.
1-6.
1-7.
1-8.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
78
List of Tables
144
144
144
145
145
145
150
152
154
156
157
159
160
162
169
169
170
171
171
173
173
173
173
174
175
175
176
176
179
184
191
193
195
199
200
202
202
202
203
203
203
203
204
204
204
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
4-17.
BANDGAP Logic Reset Signal .........................................................................................
204
4-18.
Global Reset Summary
.................................................................................................
..................................................................................................
Domain Modules .........................................................................................................
System Clock Input Configurations ....................................................................................
External Clock I/Os ......................................................................................................
DPLL Output Clocks .....................................................................................................
Source-Clock Summary .................................................................................................
Clock Distribution ........................................................................................................
Peripheral Module Functional Clock Frequencies ...................................................................
sys_clkreq Pad Direction Control ......................................................................................
System Clock Operation Modes .......................................................................................
Oscillator Controls .......................................................................................................
DPLL Multiplier and Divider Factors ...................................................................................
Internal Clock Frequency ...............................................................................................
DPLL Power Modes .....................................................................................................
DPLL Power Modes Support ...........................................................................................
DPLL Power Mode Control .............................................................................................
LP Mode Control .........................................................................................................
Clock Path Power-Down Control .......................................................................................
DPLL Operating Mode and Latency ...................................................................................
Time Required to Switch Clocks .......................................................................................
DPLL Recalibration Controls ...........................................................................................
Common PRM Source-Clock Gating Controls .......................................................................
Common CM Source-Clock Gating Controls .........................................................................
Common Interface Clock-Gating Controls ............................................................................
DPLL Domain Clock-Gating Controls .................................................................................
SGX Domain Clock-Gating Controls ..................................................................................
CORE Domain Clock-Gating Controls ................................................................................
EFUSE Domain Clock-Gating Control ................................................................................
DSS Domain Clock-Gating Controls...................................................................................
USBHOST Domain Clock-Gating Controls ...........................................................................
WKUP Domain Clock-Gating Controls ................................................................................
PER Domain Clock-Gating Controls...................................................................................
Processor Clock Configuration Controls ..............................................................................
Processor Clock Configurations........................................................................................
Interface Clock Configuration Controls ................................................................................
Functional Clock Configuration Controls ..............................................................................
MPU Domain Wake-Up Events ........................................................................................
NEON Domain Wake-Up Events ......................................................................................
SGX Domain Wake-Up Events.........................................................................................
CORE Domain Wake-Up Events ......................................................................................
DSS Domain Wake-Up Events .........................................................................................
USBHOST Domain Wake-Up Events .................................................................................
PER Domain Wake-Up Events .........................................................................................
EMU Domain Wake-Up Events ........................................................................................
WKUP Domain Wake-Up Events ......................................................................................
Clock Domain Mute Conditions ........................................................................................
Sleep Dependencies.....................................................................................................
213
4-19.
Local Reset Summary
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
4-39.
4-40.
4-41.
4-42.
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
4-59.
4-60.
4-61.
4-62.
4-63.
4-64.
4-65.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
214
215
220
220
232
232
244
245
247
248
249
250
250
251
252
252
253
253
254
254
255
257
259
259
260
261
264
265
265
266
267
270
271
271
272
272
276
276
276
277
277
278
278
279
279
279
281
79
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4-66.
Wake-Up Dependencies ................................................................................................
4-67.
Interrupt Descriptions ....................................................................................................
285
4-68.
MPU Interrupt Event Descriptions .....................................................................................
285
4-69.
SGX Functional Clock Ratio Settings .................................................................................
295
4-70.
Interface Clock Autoidle Settings ......................................................................................
296
4-71.
Clock State Transition Settings
........................................................................................
Sleep Dependency Settings ............................................................................................
CM Instance Summary ..................................................................................................
OCP_System_Reg_CM Register Mapping Summary ...............................................................
MPU_CM Register Mapping Summary ...............................................................................
CORE_CM Register Mapping Summary ..............................................................................
SGX_CM Register Mapping Summary ................................................................................
WKUP_CM Register Mapping Summary .............................................................................
Clock_Control_Reg_CM Register Mapping Summary ..............................................................
DSS_CM Register Mapping Summary ................................................................................
PER_CM Register Mapping Summary ................................................................................
EMU_CM Register Mapping Summary ...............................................................................
Global_Reg_CM Register Mapping Summary .......................................................................
NEON_CM Register Mapping Summary ..............................................................................
USBHOST_CM Register Mapping Summary ........................................................................
CM_REVISION ...........................................................................................................
CM_SYSCONFIG ........................................................................................................
CM_CLKEN_PLL_MPU .................................................................................................
CM_IDLEST_MPU .......................................................................................................
CM_IDLEST_PLL_MPU.................................................................................................
CM_AUTOIDLE_PLL_MPU ............................................................................................
CM_CLKSEL1_PLL_MPU ..............................................................................................
CM_CLKSEL2_PLL_MPU ..............................................................................................
CM_CLKSTCTRL_MPU.................................................................................................
CM_CLKSTST_MPU ....................................................................................................
CM_FCLKEN1_CORE ..................................................................................................
CM_FCLKEN3_CORE ..................................................................................................
CM_ICLKEN1_CORE ...................................................................................................
CM_ICLKEN2_CORE ...................................................................................................
CM_ICLKEN3_CORE ...................................................................................................
CM_IDLEST1_CORE....................................................................................................
CM_IDLEST2_CORE....................................................................................................
CM_IDLEST3_CORE....................................................................................................
CM_AUTOIDLE1_CORE ...............................................................................................
CM_AUTOIDLE2_CORE ...............................................................................................
CM_AUTOIDLE3_CORE ...............................................................................................
CM_CLKSEL_CORE ....................................................................................................
CM_CLKSTCTRL_CORE ...............................................................................................
CM_CLKSTST_CORE ..................................................................................................
CM_FCLKEN_SGX ......................................................................................................
CM_ICLKEN_SGX .......................................................................................................
CM_IDLEST_SGX .......................................................................................................
CM_CLKSEL_SGX ......................................................................................................
CM_SLEEPDEP_SGX ..................................................................................................
297
4-72.
4-73.
4-74.
4-75.
4-76.
4-77.
4-78.
4-79.
4-80.
4-81.
4-82.
4-83.
4-84.
4-85.
4-86.
4-87.
4-88.
4-89.
4-90.
4-91.
4-92.
4-93.
4-94.
4-95.
4-96.
4-97.
4-98.
4-99.
4-100.
4-101.
4-102.
4-103.
4-104.
4-105.
4-106.
4-107.
4-108.
4-109.
4-110.
4-111.
4-112.
4-113.
4-114.
80
List of Tables
282
298
313
313
313
314
314
314
314
315
315
315
316
316
316
317
317
318
320
320
321
322
323
324
325
326
328
329
331
332
333
336
337
338
340
341
342
343
344
345
345
346
346
347
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
4-115. CM_CLKSTCTRL_SGX .................................................................................................
348
....................................................................................................
349
4-117. CM_FCLKEN_WKUP....................................................................................................
350
....................................................................................................
CM_IDLEST_WKUP .....................................................................................................
CM_AUTOIDLE_WKUP .................................................................................................
CM_CLKSEL_WKUP ....................................................................................................
CM_CLKEN_PLL ........................................................................................................
CM_CLKEN2_PLL .......................................................................................................
CM_IDLEST_CKGEN ...................................................................................................
CM_IDLEST2_CKGEN ..................................................................................................
CM_AUTOIDLE_PLL ....................................................................................................
CM_AUTOIDLE2_PLL ..................................................................................................
CM_CLKSEL1_PLL ......................................................................................................
CM_CLKSEL2_PLL ......................................................................................................
CM_CLKSEL3_PLL ......................................................................................................
CM_CLKSEL4_PLL ......................................................................................................
CM_CLKSEL5_PLL ......................................................................................................
CM_CLKOUT_CTRL ....................................................................................................
CM_FCLKEN_DSS ......................................................................................................
CM_ICLKEN_DSS .......................................................................................................
CM_IDLEST_DSS .......................................................................................................
CM_AUTOIDLE_DSS ...................................................................................................
CM_CLKSEL_DSS ......................................................................................................
CM_SLEEPDEP_DSS ..................................................................................................
CM_CLKSTCTRL_DSS .................................................................................................
CM_CLKSTST_DSS.....................................................................................................
CM_FCLKEN_PER ......................................................................................................
CM_ICLKEN_PER .......................................................................................................
CM_IDLEST_PER .......................................................................................................
CM_AUTOIDLE_PER ...................................................................................................
CM_CLKSEL_PER ......................................................................................................
CM_SLEEPDEP_PER ..................................................................................................
CM_CLKSTCTRL_PER .................................................................................................
CM_CLKSTST_PER.....................................................................................................
CM_CLKSEL1_EMU ....................................................................................................
CM_CLKSTCTRL_EMU.................................................................................................
CM_CLKSTST_EMU ....................................................................................................
CM_CLKSEL2_EMU ....................................................................................................
CM_CLKSEL3_EMU ....................................................................................................
CM_POLCTRL ...........................................................................................................
CM_IDLEST_NEON .....................................................................................................
CM_CLKSTCTRL_NEON ...............................................................................................
CM_FCLKEN_USBHOST...............................................................................................
CM_ICLKEN_USBHOST ...............................................................................................
CM_IDLEST_USBHOST ................................................................................................
CM_AUTOIDLE_USBHOST ............................................................................................
CM_SLEEPDEP_USBHOST ...........................................................................................
CM_CLKSTCTRL_USBHOST .........................................................................................
351
4-116. CM_CLKSTST_SGX
4-118. CM_ICLKEN_WKUP
4-119.
4-120.
4-121.
4-122.
4-123.
4-124.
4-125.
4-126.
4-127.
4-128.
4-129.
4-130.
4-131.
4-132.
4-133.
4-134.
4-135.
4-136.
4-137.
4-138.
4-139.
4-140.
4-141.
4-142.
4-143.
4-144.
4-145.
4-146.
4-147.
4-148.
4-149.
4-150.
4-151.
4-152.
4-153.
4-154.
4-155.
4-156.
4-157.
4-158.
4-159.
4-160.
4-161.
4-162.
4-163.
SPRUGR0C – October 2009 – Revised November 2013
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List of Tables
352
353
354
355
358
360
362
363
364
365
367
368
369
370
371
372
373
374
375
376
378
379
380
381
383
385
387
389
390
391
392
393
395
396
397
398
399
400
401
402
403
404
405
406
407
81
www.ti.com
4-164. CM_CLKSTST_USBHOST .............................................................................................
4-165. PRM Instance Summary ................................................................................................
409
4-166. OCP_System_Reg_PRM Register Mapping Summary .............................................................
409
4-167. MPU_PRM Register Mapping Summary ..............................................................................
409
4-168. CORE_PRM Register Mapping Summary ............................................................................
410
4-169. SGX_PRM Register Mapping Summary ..............................................................................
410
4-170. WKUP_PRM Register Mapping Summary............................................................................
410
4-171. Clock_Control_Reg_PRM Registers Mapping Summary ...........................................................
410
4-172. DSS_PRM Registers Mapping Summary .............................................................................
410
4-173. PER_PRM Registers Mapping Summary .............................................................................
411
4-174. EMU_PRM Registers Mapping Summary ............................................................................
411
4-175. Global_Reg_PRM Registers Mapping Summary ....................................................................
411
4-176. NEON_PRM Registers Mapping Summary
412
4-177.
..........................................................................
USBHOST_PRM Registers Mapping Summary .....................................................................
PRM_REVISION .........................................................................................................
PRM_SYSCONFIG ......................................................................................................
PRM_IRQSTATUS_MPU ...............................................................................................
PRM_IRQENABLE_MPU ...............................................................................................
RM_RSTST_MPU .......................................................................................................
PM_WKDEP_MPU.......................................................................................................
PM_EVGENCTRL_MPU ................................................................................................
PM_EVGENONTIM_MPU ..............................................................................................
PM_EVGENOFFTIM_MPU .............................................................................................
PM_PWSTCTRL_MPU..................................................................................................
PM_PWSTST_MPU .....................................................................................................
PM_PREPWSTST_MPU ................................................................................................
RM_RSTST_CORE ......................................................................................................
PM_WKEN1_CORE .....................................................................................................
PM_MPUGRPSEL1_CORE ............................................................................................
PM_WKST1_CORE .....................................................................................................
PM_WKST3_CORE .....................................................................................................
PM_PWSTCTRL_CORE ................................................................................................
PM_PWSTST_CORE ...................................................................................................
PM_PREPWSTST_CORE ..............................................................................................
PM_WKEN3_CORE .....................................................................................................
PM_MPUGRPSEL3_CORE ............................................................................................
RM_RSTST_SGX ........................................................................................................
PM_WKDEP_SGX .......................................................................................................
PM_PWSTCTRL_SGX ..................................................................................................
PM_PWSTST_SGX .....................................................................................................
RM_RSTST_SGX ........................................................................................................
PM_WKEN_WKUP ......................................................................................................
PM_MPUGRPSEL_WKUP .............................................................................................
PM_WKST_WKUP.......................................................................................................
PRM_CLKSEL ............................................................................................................
PRM_CLKOUT_CTRL ..................................................................................................
RM_RSTST_DSS ........................................................................................................
PM_WKEN_DSS .........................................................................................................
PM_WKDEP_DSS .......................................................................................................
412
4-178.
4-179.
4-180.
4-181.
4-182.
4-183.
4-184.
4-185.
4-186.
4-187.
4-188.
4-189.
4-190.
4-191.
4-192.
4-193.
4-194.
4-195.
4-196.
4-197.
4-198.
4-199.
4-200.
4-201.
4-202.
4-203.
4-204.
4-205.
4-206.
4-207.
4-208.
4-209.
4-210.
4-211.
4-212.
82
408
List of Tables
413
413
414
416
418
419
420
421
421
422
423
424
425
426
428
430
433
434
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
4-213. PM_PWSTCTRL_DSS ..................................................................................................
453
4-214. PM_PWSTST_DSS ......................................................................................................
454
4-215. PM_PREPWSTST_DSS ................................................................................................
455
4-216. RM_RSTST_PER ........................................................................................................
456
4-217. PM_WKEN_PER .........................................................................................................
457
4-218. PM_MPUGRPSEL_PER ................................................................................................
459
4-219. PM_WKST_PER .........................................................................................................
461
4-220. PM_WKDEP_PER .......................................................................................................
464
4-221. PM_PWSTCTRL_PER ..................................................................................................
465
4-222. PM_PWSTST_PER ......................................................................................................
466
4-223. PM_PREPWSTST_PER ................................................................................................
467
.......................................................................................................
468
4-224. RM_RSTST_EMU
4-225. PRM_RSTCTRL..........................................................................................................
469
4-226. PRM_RSTTIME ..........................................................................................................
470
4-227. PRM_RSTST .............................................................................................................
471
4-228. PRM_CLKSRC_CTRL
473
4-229.
..................................................................................................
PRM_OBS ................................................................................................................
PRM_CLKSETUP ........................................................................................................
PRM_POLCTRL..........................................................................................................
RM_RSTST_NEON ......................................................................................................
PM_WKDEP_NEON .....................................................................................................
PM_PWSTCTRL_NEON ................................................................................................
PM_PWSTST_NEON ...................................................................................................
PM_PREPWSTST_NEON ..............................................................................................
RM_RSTST_USBHOST ................................................................................................
PM_WKEN_USBHOST .................................................................................................
PM_MPUGRPSEL_USBHOST ........................................................................................
PM_WKST_USBHOST..................................................................................................
PM_WKDEP_USBHOST ...............................................................................................
PM_PWSTCTRL_USBHOST...........................................................................................
PM_PWSTST_USBHOST ..............................................................................................
PM_PREPWSTST_USBHOST.........................................................................................
Document Revision History .............................................................................................
MCmd Qualifier Description ............................................................................................
MReqInfo Qualifier Description .........................................................................................
SResp Qualifier Description ............................................................................................
L3 Initiator Agents ........................................................................................................
L3 Target Agents .........................................................................................................
L4-Core Initiator Agent ..................................................................................................
L4-Core Target Agents ..................................................................................................
L4-Per Initiator Agent ....................................................................................................
L4-Per Target Agents....................................................................................................
L4-Emu Initiator Agents .................................................................................................
L4-Emu Target Agents ..................................................................................................
L4-Wakeup Initiator Agent ..............................................................................................
L4-Wakeup Target Agents ..............................................................................................
Connectivity Matrix .......................................................................................................
L3 Interconnect Clocks ..................................................................................................
L3 Interconnect Reset ...................................................................................................
474
4-230.
4-231.
4-232.
4-233.
4-234.
4-235.
4-236.
4-237.
4-238.
4-239.
4-240.
4-241.
4-242.
4-243.
4-244.
4-245.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
474
475
476
477
478
479
480
481
482
482
483
484
485
486
487
488
491
491
491
494
494
495
495
496
496
497
497
497
497
498
500
500
83
www.ti.com
5-17.
L3 Interconnect Hardware Requests ..................................................................................
501
5-18.
InitiatorID Definition ......................................................................................................
502
5-19.
Target Firewall and Region Configuration ............................................................................
502
5-20.
L3 Firewall Size Parameter Definition .................................................................................
505
5-21.
MReqInfo Parameter Combinations ...................................................................................
508
5-22.
L3 Firewall Permission-Setting Registers .............................................................................
509
5-23.
L3 Firewall Error Logging Registers ...................................................................................
511
5-24.
Error Types ...............................................................................................................
515
5-25.
CODE Field Definition ...................................................................................................
515
5-26.
L3 Timeout Register Target and Agent Programming ..............................................................
516
5-27.
L3 External Input Flags..................................................................................................
518
5-28.
L3_SI_FLAG_STATUS_0 for Application Error ......................................................................
519
5-29.
L3_SI_FLAG_STATUS_1 for Debug Error ...........................................................................
520
5-30.
Error Clearing .............................................................................................................
524
5-31.
Instance Summary .......................................................................................................
525
5-32.
Initiator Agent Common Register Mapping Summary ...............................................................
526
5-33.
Initiator Agent Common Register Mapping Summary ...............................................................
526
5-34.
Initiator Agent Common Register Mapping Summary ...............................................................
526
5-35.
Initiator Agent Common Register Mapping Summary ...............................................................
526
5-36.
L3_IA_AGENT_CONTROL .............................................................................................
527
5-37.
L3_IA_AGENT_STATUS
...............................................................................................
L3_IA_ERROR_LOG ....................................................................................................
L3_IA_ERROR_LOG_ADDR ...........................................................................................
Target Agent Common Register Mapping Summary ................................................................
Target Agent Common Register Mapping Summary ................................................................
Target Agent Common Register Mapping Summary ................................................................
Target Agent Common Register Mapping Summary ................................................................
L3_TA_AGENT_CONTROL ............................................................................................
L3_TA_AGENT_STATUS...............................................................................................
L3_TA_ERROR_LOG ...................................................................................................
L3_TA_ERROR_LOG_ADDR ..........................................................................................
RT Register Mapping Summary .......................................................................................
L3_RT_NETWORK ......................................................................................................
L3_RT_INITID_READBACK ............................................................................................
L3_RT_NETWORK_CONTROL .......................................................................................
Protection Mechanism Common Register Mapping Summary .....................................................
Protection Mechanism Common Register Mapping Summary .....................................................
Protection Mechanism Common Register Mapping Summary .....................................................
L3_PM_ERROR_LOG ..................................................................................................
L3_PM_CONTROL ......................................................................................................
L3_PM_ERROR_CLEAR_SINGLE ....................................................................................
L3_PM_ERROR_CLEAR_MULTI......................................................................................
L3_PM_REQ_INFO_PERMISSION_i .................................................................................
Reset Value for REQ_INFO_PERMISSION ..........................................................................
L3_PM_READ_PERMISSION_i .......................................................................................
L3_PM_WRITE_PERMISSION_i ......................................................................................
529
550
Bit Availability and Initialization Values for L3_PM_READ_PERMISSION_i and
L3_PM_WRITE_PERMISSION_i .....................................................................................
552
L3_PM_ADDR_MATCH_k ..............................................................................................
553
5-38.
5-39.
5-40.
5-41.
5-42.
5-43.
5-44.
5-45.
5-46.
5-47.
5-48.
5-49.
5-50.
5-51.
5-52.
5-53.
5-54.
5-55.
5-56.
5-57.
5-58.
5-59.
5-60.
5-61.
5-62.
5-63.
5-64.
84
List of Tables
531
532
533
533
533
533
535
536
537
538
539
540
540
541
542
542
542
544
545
546
546
547
547
548
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
5-65.
5-66.
5-67.
5-68.
5-69.
5-70.
5-71.
5-72.
5-73.
5-74.
5-75.
5-76.
5-77.
5-78.
5-79.
5-80.
5-81.
5-82.
5-83.
5-84.
5-85.
5-86.
5-87.
5-88.
5-89.
5-90.
5-91.
5-92.
5-93.
5-94.
5-95.
5-96.
5-97.
5-98.
5-99.
5-100.
5-101.
5-102.
5-103.
5-104.
5-105.
5-106.
5-107.
5-108.
5-109.
5-110.
5-111.
5-112.
5-113.
.........................................................................
SI Register Mapping Summary.........................................................................................
L3_SI_CONTROL ........................................................................................................
L3_SI_FLAG_STATUS_0 ...............................................................................................
L3_SI_FLAG_STATUS_1 ...............................................................................................
L4-Core Target Agents ..................................................................................................
L4-Per Target Agents....................................................................................................
L4-Emu Target Agents ..................................................................................................
L4-Emu Initiator Agents .................................................................................................
L4-Wakeup Target Agents ..............................................................................................
L4-Wakeup Initiator Agents .............................................................................................
L4 Interconnect Clocks ..................................................................................................
L4 Interconnect Hardware Reset ......................................................................................
L4 Interconnect Power Domains .......................................................................................
Region Allocation for L4-Core Interconnect ..........................................................................
Region Allocation for L4-Per Interconnect ............................................................................
Region Allocation for L4-Emu Interconnect...........................................................................
L4 Firewall Register Description Overview ...........................................................................
L4 Time-Out Link and TA Programming ..............................................................................
L4 Time-Out TA Programming .........................................................................................
L4- Core Instance Summary............................................................................................
L4-Per Instance Summary ..............................................................................................
L4-Emu Instance Summary .............................................................................................
L4-WKUP Instance Summary ..........................................................................................
L4 IA Register Mapping Summary (1) .................................................................................
L4 IA Register Mapping Summary (2) .................................................................................
L4_IA_AGENT_CONTROL_L ..........................................................................................
L4_IA_AGENT_STATUS_L ............................................................................................
L4_IA_ERROR_LOG_L .................................................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
CORE_TA Common Register Mapping Summary ...................................................................
PER_TA Common Register Mapping Summary .....................................................................
PER_TA Common Register Mapping Summary .....................................................................
Reset Value for L3_PM_ADDR_MATCH_k
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
553
555
556
557
557
560
561
561
561
562
562
562
563
563
567
569
570
572
573
574
576
577
577
577
579
579
580
581
581
582
582
582
582
583
583
583
583
583
583
584
584
584
584
584
585
585
585
585
585
85
www.ti.com
5-114. PER_TA Common Register Mapping Summary .....................................................................
585
5-115. PER_TA Common Register Mapping Summary .....................................................................
586
5-116. PER_TA Common Register Mapping Summary .....................................................................
586
5-117. PER_TA Common Register Mapping Summary .....................................................................
586
5-118. PER_TA Common Register Mapping Summary .....................................................................
586
....................................................................
EMU_TA Common Register Mapping Summary ....................................................................
WKUP_TA Common Register Mapping Summary ..................................................................
WKUP_TA Common Register Mapping Summary ..................................................................
WKUP_TA Common Register Mapping Summary ..................................................................
L4_TA_AGENT_CONTROL_L .........................................................................................
L4_TA_AGENT_CONTROL_H.........................................................................................
L4_TA_AGENT_STATUS_L............................................................................................
L4 LA Register Mapping Summary ....................................................................................
L4_LA_NETWORK_H ...................................................................................................
L4_LA_INITIATOR_INFO_L ............................................................................................
Reset value for L4_LA_INITIATOR_INFO_L .........................................................................
L4_LA_INITIATOR_INFO_H ...........................................................................................
Reset value for L4_LA_INITIATOR_INFO_H ........................................................................
L4_LA_NETWORK_CONTROL_L .....................................................................................
L4_LA_NETWORK_CONTROL_H ....................................................................................
L4 AP Register Mapping Summary ....................................................................................
L4 AP Register Mapping Summary ....................................................................................
Reset Values for CORE_AP L4_AP_REGION_l_L and L4_AP_REGION_l_H ..................................
Reset Values for PER_AP L4_AP_REGION_l_L and L4_AP_REGION_l_H ....................................
Reset Values for EMU_AP L4_AP_REGION_l_L and L4_AP_REGION_l_H ...................................
Reset Values for WKPUP_AP L4_AP_REGION_l_L and L4_AP_REGION_l_H................................
L4_AP_SEGMENT_i_L .................................................................................................
Reset Values for L4_AP_SEGMENT_i_L.............................................................................
L4_AP_SEGMENT_i_H .................................................................................................
Reset Values for L4_AP_SEGMENT_i_H ............................................................................
L4_AP_PROT_GROUP_MEMBERS_k_L ............................................................................
L4_AP_PROT_GROUP_ROLES_k_L ................................................................................
L4_AP_REGION_l_L ....................................................................................................
L4_AP_REGION_l_H ....................................................................................................
SCM I/O Description .....................................................................................................
Bit Directions for CONTROL_PADCONF_x Registers ..............................................................
Mode Selection ...........................................................................................................
Pull Selection .............................................................................................................
Core and Wakeup Control Module Pad Configuration Registers ..................................................
Static Device Configuration Registers .................................................................................
MSuspendMux Control Registers ......................................................................................
Device Status Registers.................................................................................................
Observability Registers ..................................................................................................
Internal Signals Multiplexed on OBSMUX0...........................................................................
Internal Signals Multiplexed on OBSMUX1...........................................................................
Internal Signals Multiplexed on OBSMUX2...........................................................................
Internal Signals Multiplexed on OBSMUX3...........................................................................
Internal Signals Multiplexed on OBSMUX4...........................................................................
586
5-119. EMU_TA Common Register Mapping Summary
5-120.
5-121.
5-122.
5-123.
5-124.
5-125.
5-126.
5-127.
5-128.
5-129.
5-130.
5-131.
5-132.
5-133.
5-134.
5-135.
5-136.
5-137.
5-138.
5-139.
5-140.
5-141.
5-142.
5-143.
5-144.
5-145.
5-146.
5-147.
5-148.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
86
List of Tables
587
587
588
588
589
590
590
591
592
593
593
594
594
595
596
597
597
598
600
601
602
603
603
604
604
604
605
605
606
610
617
618
619
620
629
629
629
631
632
633
634
635
636
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
6-15.
Internal Signals Multiplexed on OBSMUX5...........................................................................
637
6-16.
Internal Signals Multiplexed on OBSMUX6...........................................................................
638
6-17.
Internal Signals Multiplexed on OBSMUX7...........................................................................
640
6-18.
Internal Signals Multiplexed on OBSMUX8...........................................................................
641
6-19.
Internal Signals Multiplexed on OBSMUX9...........................................................................
642
6-20.
Internal Signals Multiplexed on OBSMUX10 .........................................................................
643
6-21.
Internal Signals Multiplexed on OBSMUX11 .........................................................................
644
6-22.
Internal Signals Multiplexed on OBSMUX12 .........................................................................
645
6-23.
Internal Signals Multiplexed on OBSMUX13 .........................................................................
646
6-24.
Internal Signals Multiplexed on OBSMUX14 .........................................................................
647
6-25.
Internal Signals Multiplexed on OBSMUX15 .........................................................................
648
6-26.
Internal Signals Multiplexed on OBSMUX16 .........................................................................
649
6-27.
Internal Signals Multiplexed on OBSMUX17 .........................................................................
650
6-28.
Internal Signals Multiplexed on WKUPOBSMUX0
..................................................................
Internal Signals Multiplexed on WKUPOBSMUX1 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX2 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX3 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX4 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX5 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX6 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX7 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX8 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX9 ..................................................................
Internal Signals Multiplexed on WKUPOBSMUX10 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX11 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX12 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX13 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX14 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX15 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX16 .................................................................
Internal Signals Multiplexed on WKUPOBSMUX17 .................................................................
Existing Pin Types .......................................................................................................
Instance Summary .......................................................................................................
INTERFACE Registers Mapping Summary ..........................................................................
PADCONFS Registers Mapping Summary ...........................................................................
GENERAL Registers Mapping Summary .............................................................................
MEM_WKUP Register Mapping Summary ...........................................................................
PADCONFS_WKUP Registers Mapping Summary .................................................................
GENERAL_WKUP Registers Mapping Summary ...................................................................
CONTROL_REVISION ..................................................................................................
Control System Configuration Register (CONTROL_SYSCONFIG) ..............................................
CONTROL_PADCONF_X ..............................................................................................
CONTROL_PADCONF_CAPABILITIES ..............................................................................
CONTROL_PADCONF_OFF ...........................................................................................
CONTROL_DEVCONF0 ................................................................................................
CONTROL_MEM_DFTRW0 ............................................................................................
Type Value For CONTROL_MEM_DFTRW0 Register..............................................................
CONTROL_MEM_DFTRW1 ............................................................................................
Type Value For CONTROL_MEM_DFTRW1 Register..............................................................
651
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
6-41.
6-42.
6-43.
6-44.
6-45.
6-46.
6-47.
6-48.
6-49.
6-50.
6-51.
6-52.
6-53.
6-54.
6-55.
6-56.
6-57.
6-58.
6-59.
6-60.
6-61.
6-62.
6-63.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
681
683
683
684
686
688
688
688
690
691
692
694
702
703
704
704
705
706
87
www.ti.com
6-64.
6-65.
6-66.
6-67.
6-68.
6-69.
6-70.
6-71.
6-72.
6-73.
6-74.
6-75.
6-76.
6-77.
6-78.
6-79.
6-80.
6-81.
6-82.
6-83.
6-84.
6-85.
6-86.
6-87.
6-88.
6-89.
6-90.
6-91.
6-92.
6-93.
6-94.
6-95.
6-96.
6-97.
6-98.
6-99.
6-100.
6-101.
6-102.
6-103.
6-104.
6-105.
6-106.
6-107.
6-108.
6-109.
6-110.
6-111.
6-112.
88
......................................................................................
CONTROL_MSUSPENDMUX_1 ......................................................................................
CONTROL_MSUSPENDMUX_2 ......................................................................................
CONTROL_MSUSPENDMUX_4 ......................................................................................
CONTROL_MSUSPENDMUX_5 ......................................................................................
CONTROL_MSUSPENDMUX_6 ......................................................................................
CONTROL_DEVCONF1 ................................................................................................
CONTROL_SEC_STATUS .............................................................................................
Type Value For CONTROL_SEC_STATUS Register ...............................................................
CONTROL_SEC_ERR_STATUS ......................................................................................
Type Value For CONTROL_SEC_ERR_STATUS Register ........................................................
CONTROL_SEC_ERR_STATUS_DEBUG ...........................................................................
Type Value For CONTROL_SEC_ERR_STATUS_DEBUG Register.............................................
CONTROL_STATUS ....................................................................................................
CONTROL_RPUB_KEY_H_0 ..........................................................................................
CONTROL_RPUB_KEY_H_1 ..........................................................................................
CONTROL_RPUB_KEY_H_2 ..........................................................................................
CONTROL_RPUB_KEY_H_3 ..........................................................................................
CONTROL_RPUB_KEY_H_4 ..........................................................................................
CONTROL_USB_CONF_0 .............................................................................................
CONTROL_USB_CONF_1 .............................................................................................
CONTROL_FUSE_EMAC_LSB .......................................................................................
CONTROL_FUSE_EMAC_MSB ......................................................................................
CONTROL_FUSE_SR ..................................................................................................
CONTROL_CEK_0 ......................................................................................................
Type Value For CONTROL_CEK_0 Register ........................................................................
CONTROL_CEK_1 ......................................................................................................
Type Value For CONTROL_CEK_1 Register ........................................................................
CONTROL_CEK_2 ......................................................................................................
Type Value For CONTROL_CEK_2 Register ........................................................................
CONTROL_CEK_3 ......................................................................................................
Type Value For CONTROL_CEK_3 Register ........................................................................
CONTROL_MSV_0 ......................................................................................................
Type Value For CONTROL_MSV_0 Register ........................................................................
CONTROL_CEK_BCH_0 ...............................................................................................
CONTROL_CEK_BCH_1 ...............................................................................................
CONTROL_CEK_BCH_2 ...............................................................................................
CONTROL_CEK_BCH_3 ...............................................................................................
CONTROL_CEK_BCH_4 ...............................................................................................
CONTROL_MSV_BCH_0 ...............................................................................................
CONTROL_MSV_BCH_1 ...............................................................................................
CONTROL_SWRV_0 ....................................................................................................
CONTROL_SWRV_1 ....................................................................................................
CONTROL_SWRV_2 ....................................................................................................
CONTROL_SWRV_3 ....................................................................................................
CONTROL_SWRV_4 ....................................................................................................
CONTROL_DEBOBS_0.................................................................................................
CONTROL_DEBOBS_1.................................................................................................
CONTROL_DEBOBS_2.................................................................................................
CONTROL_MSUSPENDMUX_0
List of Tables
707
709
711
714
715
717
719
721
723
724
725
726
727
728
729
729
730
730
731
731
732
732
732
733
733
733
734
734
734
734
735
735
735
735
736
736
737
737
738
738
739
739
740
740
741
741
742
743
744
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
6-113. CONTROL_DEBOBS_3.................................................................................................
745
6-114. CONTROL_DEBOBS_4.................................................................................................
746
6-115. CONTROL_DEBOBS_5.................................................................................................
747
6-116. CONTROL_DEBOBS_6.................................................................................................
748
6-117. CONTROL_DEBOBS_7.................................................................................................
749
6-118. CONTROL_DEBOBS_8.................................................................................................
750
6-119. CONTROL_WKUP_CTRL ..............................................................................................
751
6-120. CONTROL_DSS_DPLL_SPREADING................................................................................
752
.............................................................................
CONTROL_PER_DPLL_SPREADING................................................................................
CONTROL_USBHOST_DPLL_SPREADING ........................................................................
CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH ................................................................
Type Value For CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH Register ..................................
CONTROL_DPF_OCM_RAM_FW_REQINFO .......................................................................
Type Value For CONTROL_DPF_OCM_RAM_FW_REQINFO Register ........................................
CONTROL_DPF_OCM_RAM_FW_WR ..............................................................................
Type Value For CONTROL_DPF_OCM_RAM_FW_WR Register ................................................
CONTROL_DPF_REGION4_GPMC_FW_ADDR_MATCH ........................................................
Type Value For CONTROL_DPF_REGION4_GPMC_FW_ADDR_MATCH Register ..........................
CONTROL_DPF_REGION4_GPMC_FW_REQINFO ...............................................................
Type Value For CONTROL_DPF_REGION4_GPMC_FW_REQINFO Register ................................
CONTROL_DPF_REGION4_GPMC_FW_WR ......................................................................
Type Value For CONTROL_DPF_REGION4_GPMC_FW_WR Register ........................................
CONTROL_APE_FW_DEFAULT_SECURE_LOCK ................................................................
Type Value For CONTROL_APE_FW_DEFAULT_SECURE_LOCK Register ..................................
Reset Value For CONTROL_APE_FW_DEFAULT_SECURE_LOCK Register .................................
CONTROL_OCMROM_SECURE_DEBUG ..........................................................................
Type Value For CONTROL_OCMROM_SECURE_DEBUG Register ............................................
Reset Value For CONTROL_OCMROM_SECURE_DEBUG Register ...........................................
CONTROL_EXT_SEC_CONTROL ....................................................................................
Type Value For CONTROL_EXT_SEC_CONTROL Register......................................................
Reset Value For CONTROL_EXT_SEC_CONTROL Register.....................................................
CONTROL_DEVCONF2 ................................................................................................
CONTROL_DEVCONF3 ................................................................................................
CONTROL_CBA_PRIORITY ...........................................................................................
CONTROL_LVL_INTR_CLEAR ........................................................................................
CONTROL_IP_SW_RESET ............................................................................................
CONTROL_IPSS_CLK_CTRL .........................................................................................
CONTROL_IDCODE ....................................................................................................
CONTROL_PADCONF_WKUP_CAPABILITIES ....................................................................
CONTROL_SEC_TAP ..................................................................................................
Type Value For CONTROL_SEC_TAP Register ....................................................................
Reset Value For CONTROL_SEC_TAP Register ...................................................................
CONTROL_SEC_EMU ..................................................................................................
Type Value For CONTROL_SEC_EMU Register....................................................................
Reset Value For CONTROL_SEC_EMU Register ..................................................................
CONTROL_WKUP_DEBOBS_0 .......................................................................................
Type Value For CONTROL_WKUP_DEBOBS_0 Register .........................................................
CONTROL_WKUP_DEBOBS_1 .......................................................................................
753
6-121. CONTROL_CORE_DPLL_SPREADING
6-122.
6-123.
6-124.
6-125.
6-126.
6-127.
6-128.
6-129.
6-130.
6-131.
6-132.
6-133.
6-134.
6-135.
6-136.
6-137.
6-138.
6-139.
6-140.
6-141.
6-142.
6-143.
6-144.
6-145.
6-146.
6-147.
6-148.
6-149.
6-150.
6-151.
6-152.
6-153.
6-154.
6-155.
6-156.
6-157.
6-158.
6-159.
6-160.
6-161.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
754
755
756
756
757
757
758
758
759
759
760
760
761
761
762
763
763
765
765
765
766
766
766
767
770
772
773
774
775
777
779
780
781
781
782
782
783
784
784
785
89
www.ti.com
6-162. Type Value For CONTROL_WKUP_DEBOBS_1 Register .........................................................
6-163. CONTROL_WKUP_DEBOBS_2 .......................................................................................
786
6-164. Type Value For CONTROL_WKUP_DEBOBS_2 Register .........................................................
786
6-165. CONTROL_WKUP_DEBOBS_3 .......................................................................................
787
6-166. Type Value For CONTROL_WKUP_DEBOBS_3 Register .........................................................
787
6-167. CONTROL_WKUP_DEBOBS_4 .......................................................................................
788
6-168. Type Value For CONTROL_WKUP_DEBOBS_4 Register .........................................................
788
6-169. CONTROL_SEC_DAP ..................................................................................................
789
6-170. Type Value For CONTROL_SEC_DAP Register ....................................................................
789
6-171. Document Revision History .............................................................................................
790
7-1.
Description External DMA Request Pin ...............................................................................
796
7-2.
SDMA Interrupt Mapping to the MPU Subsystem ...................................................................
799
7-3.
SDMA Request Mapping ................................................................................................
799
7-4.
Parameter Values for Addressing Mode Examples (a), (b), and (c)
..............................................
Equations for Rotation ...................................................................................................
Example Parameter Values for a 90° Clockwise Image Rotation .................................................
Buffering Disable .........................................................................................................
Logical DMA Channel Events ..........................................................................................
Registers Print ............................................................................................................
Registers Print ............................................................................................................
SDMA Instances Summary .............................................................................................
SDMA Register Summary ..............................................................................................
DMA4_REVISION........................................................................................................
Register Call Summary for Register DMA4_REVISION ............................................................
DMA4_IRQSTATUS_Lj .................................................................................................
Register Call Summary for Register DMA4_IRQSTATUS_Lj ......................................................
DMA4_IRQENABLE_Lj .................................................................................................
Register Call Summary for Register DMA4_IRQENABLE_Lj ......................................................
DMA4_SYSSTATUS ....................................................................................................
Register Call Summary for Register DMA4_SYSSTATUS .........................................................
DMA4_OCP_SYSCONFIG .............................................................................................
Register Call Summary for Register DMA4_OCP_SYSCONFIG ..................................................
DMA4_CAPS_0 ..........................................................................................................
Register Call Summary for Register DMA4_CAPS_0 ...............................................................
DMA4_CAPS_2 ..........................................................................................................
Register Call Summary for Register DMA4_CAPS_2 ...............................................................
DMA4_CAPS_3 ..........................................................................................................
Register Call Summary for Register DMA4_CAPS_3 ...............................................................
DMA4_CAPS_4 ..........................................................................................................
Register Call Summary for Register DMA4_CAPS_4 ...............................................................
DMA4_GCR ..............................................................................................................
Register Call Summary for Register DMA4_GCR ...................................................................
DMA4_CCRi ..............................................................................................................
Register Call Summary for Register DMA4_CCRi...................................................................
DMA4_CLNK_CTRLi ....................................................................................................
Register Call Summary for Register DMA4_CLNK_CTRLi .........................................................
DMA4_CICRi .............................................................................................................
Register Call Summary for Register DMA4_CICRi ..................................................................
DMA4_CSRi ..............................................................................................................
807
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
90
785
List of Tables
807
808
811
814
828
831
832
832
833
833
833
834
834
834
834
835
835
836
836
837
837
838
838
839
839
841
841
842
842
845
845
846
846
847
847
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
7-40.
Register Call Summary for Register DMA4_CSRi ...................................................................
849
7-41.
DMA4_CSDPi
............................................................................................................
849
7-42.
Register Call Summary for Register DMA4_CSDPi .................................................................
850
7-43.
DMA4_CENi ..............................................................................................................
851
7-44.
Register Call Summary for Register DMA4_CENi ...................................................................
851
7-45.
DMA4_CFNi ..............................................................................................................
851
7-46.
Register Call Summary for Register DMA4_CFNi ...................................................................
852
7-47.
DMA4_CSSAi.............................................................................................................
852
7-48.
Register Call Summary for Register DMA4_CSSAi .................................................................
852
7-49.
DMA4_CDSAi
............................................................................................................
852
7-50.
Register Call Summary for Register DMA4_CDSAi .................................................................
853
7-51.
DMA4_CSEIi..............................................................................................................
853
7-52.
Register Call Summary for Register DMA4_CSEIi ..................................................................
853
7-53.
DMA4_CSFIi ..............................................................................................................
853
7-54.
Register Call Summary for Register DMA4_CSFIi ..................................................................
854
7-55.
DMA4_CDEIi
.............................................................................................................
Register Call Summary for Register DMA4_CDEIi ..................................................................
DMA4_CDFIi..............................................................................................................
Register Call Summary for Register DMA4_CDFIi ..................................................................
DMA4_CSACi ............................................................................................................
Register Call Summary for Register DMA4_CSACi .................................................................
DMA4_CDACi ............................................................................................................
Register Call Summary for Register DMA4_CDACi .................................................................
DMA4_CCENi ............................................................................................................
Register Call Summary for Register DMA4_CCENi .................................................................
DMA4_CCFNi ............................................................................................................
Register Call Summary for Register DMA4_CCFNi .................................................................
DMA4_COLORi ..........................................................................................................
Register Call Summary for Register DMA4_COLORi ...............................................................
MPU Subsystem INTC Clock Rates ...................................................................................
Hardware and Software Reset .........................................................................................
Interrupt Lines Incoming and Outgoing ...............................................................................
Interrupt Mapping to the MPU Subsystem ...........................................................................
INTC Instance Summary ................................................................................................
MPU INTC Register Summary .........................................................................................
Device INTC Initialization Register Summary ........................................................................
INTCPS_SYSCONFIG ..................................................................................................
INTCPS_SYSSTATUS ..................................................................................................
INTCPS_SIR_IRQ .......................................................................................................
INTCPS_SIR_FIQ........................................................................................................
INTCPS_CONTROL .....................................................................................................
INTCPS_PROTECTION ................................................................................................
INTCPS_IDLE ............................................................................................................
INTCPS_IRQ_PRIORITY ...............................................................................................
INTCPS_FIQ_PRIORITY ...............................................................................................
INTCPS_THRESHOLD .................................................................................................
INTCPS_ITRn ............................................................................................................
INTCPS_MIRn ............................................................................................................
INTCPS_MIR_CLEARn .................................................................................................
854
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
854
854
854
855
855
855
855
855
856
856
856
856
857
861
862
862
862
877
877
878
879
879
880
880
881
881
882
882
883
883
883
884
884
91
www.ti.com
8-21.
INTCPS_MIR_SETn .....................................................................................................
885
8-22.
INTCPS_ISR_SETn .....................................................................................................
885
8-23.
INTCPS_ISR_CLEARn..................................................................................................
886
8-24.
INTCPS_PENDING_IRQn ..............................................................................................
886
8-25.
INTCPS_PENDING_FIQn ..............................................................................................
887
8-26.
INTCPS_ILRm ............................................................................................................
887
8-27.
INTC_INIT_REGISTER1 ................................................................................................
888
8-28.
INTC_INIT_REGISTER2 ................................................................................................
888
9-1.
GPMC I/O Description ...................................................................................................
893
9-2.
GPMC Pin Multiplexing Options
.......................................................................................
894
9-3.
Idle Cycle Insertion Configuration......................................................................................
917
9-4.
Chip-Select Configuration for NAND Interfacing .....................................................................
935
9-5.
ECC Enable Settings ....................................................................................................
943
9-6.
Flattened BCH Codeword Mapping (512 Bytes + 104 Bits) ........................................................
948
9-7.
Aligned Message Byte Mapping in 8-bit NAND ......................................................................
949
9-8.
Aligned Message Byte Mapping in 16-bit NAND
....................................................................
Aligned Nibble Mapping of Message in 8-bit NAND .................................................................
Misaligned Nibble Mapping of Message in 8-bit NAND .............................................................
Aligned Nibble Mapping of Message in 16-bit NAND ...............................................................
Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble).....................................
Misaligned Nibble Mapping of Message in 16-bit NAND (2 Unused Nibbles) ...................................
Misaligned Nibble Mapping of Message in 16-bit NAND (3 Unused Nibbles) ...................................
Prefetch Mode Configuration ...........................................................................................
Write-Posting Mode Configuration .....................................................................................
GPMC Signals ............................................................................................................
Useful Timing Parameters on the Memory Side .....................................................................
Calculating GPMC Timing Parameters................................................................................
AC Characteristics for Asynchronous Read Access ................................................................
GPMC Timing Parameters for Asynchronous Read Access .......................................................
AC Characteristics for Asynchronous Single Write ( Memory Side) ..............................................
GPMC Timing Parameters for Asynchronous Single Write ........................................................
Supported Memories Interfaces ........................................................................................
NAND Interface Bus Operations Summary ...........................................................................
NOR Interface Bus Operations Summary ............................................................................
Instance Summary .......................................................................................................
GPMC Register Mapping Summary ...................................................................................
GPMC_SYSCONFIG ....................................................................................................
GPMC_SYSSTATUS ....................................................................................................
GPMC_IRQSTATUS ....................................................................................................
GPMC_IRQENABLE ....................................................................................................
GPMC_TIMEOUT_CONTROL .........................................................................................
GPMC_ERR_ADDRESS ................................................................................................
GPMC_ERR_TYPE ......................................................................................................
GPMC_CONFIG .........................................................................................................
GPMC_STATUS .........................................................................................................
GPMC_CONFIG1_i ......................................................................................................
GPMC_CONFIG2_i ......................................................................................................
GPMC_CONFIG3_i ......................................................................................................
GPMC_CONFIG4_i ......................................................................................................
949
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
9-25.
9-26.
9-27.
9-28.
9-29.
9-30.
9-31.
9-32.
9-33.
9-34.
9-35.
9-36.
9-37.
9-38.
9-39.
9-40.
9-41.
92
List of Tables
949
950
950
950
950
950
960
962
966
967
968
969
970
971
971
972
973
974
975
975
977
978
979
981
982
983
984
985
986
987
990
991
992
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
9-42.
GPMC_CONFIG5_i ......................................................................................................
993
9-43.
GPMC_CONFIG6_i ......................................................................................................
994
9-44.
GPMC_CONFIG7_i ......................................................................................................
995
9-45.
GPMC_NAND_COMMAND_i
..........................................................................................
GPMC_NAND_ADDRESS_i............................................................................................
GPMC_NAND_DATA_i .................................................................................................
GPMC_PREFETCH_CONFIG1 ........................................................................................
GPMC_PREFETCH_CONFIG2 ......................................................................................
GPMC_PREFETCH_CONTROL .....................................................................................
GPMC_PREFETCH_STATUS ........................................................................................
GPMC_ECC_CONFIG .................................................................................................
GPMC_ECC_CONTROL ..............................................................................................
GPMC_ECC_SIZE_CONFIG .........................................................................................
GPMC_ECCj_RESULT ................................................................................................
GPMC_BCH_RESULT0_i .............................................................................................
GPMC_BCH_RESULT1_i .............................................................................................
GPMC_BCH_RESULT2_i .............................................................................................
GPMC_BCH_RESULT3_i .............................................................................................
GPMC_BCH_SWDATA ................................................................................................
Arbitration Class Allocation ............................................................................................
Security ReqInfo Parameters Ordering ..............................................................................
VRFB Contexts Virtual Address Spaces vs Rotation Angle ......................................................
EMIF4A Configuration .................................................................................................
MAddrSpace Mapping to Chip Selects ..............................................................................
Turn Around Time ......................................................................................................
Address to SDRAM Address Mapping for 16-Bit SDRAM (reg_ibank_pos=0) .................................
OCP Address to SDRAM Address Mapping for 32-Bit SDRAM (reg_ibank_pos=0) ..........................
OCP Address to SDRAM Address Mapping for reg_ibank_pos=1 ..............................................
OCP Address to SDRAM Address Mapping for reg_ibank_pos=2 ..............................................
OCP Address to SDRAM Address Mapping for ibank_pos=3 ....................................................
64-bit OCP Data Width ................................................................................................
EMIF Register Mapping Summary ...................................................................................
EMIF Module ID and Revision Register (EMIF_MOD_ID_REV) Field Descriptions ...........................
SDRAM Status Register (STATUS) Field Descriptions ...........................................................
SDRAM Configuration Register (SDRAM_CONFIG) Field Descriptions ........................................
SDRAM Refresh Control Register (SDRAM_REF_CTRL) Field Descriptions..................................
SDRAM Refresh Control Shadow Register (SDRAM_REF_CTRL_SHDW) Field Descriptions .............
SDRAM Timing 1 Register (SDRAM_TIM_1) Field Descriptions ................................................
SDRAM Timing 1 Shadow Register (SDRAM_TIM_1_SHDW) Field Descriptions ............................
SDRAM Timing 2 Register (SDRAM_TIM_2) Field Descriptions ................................................
SDRAM Timing 2 Shadow Register (SDRAM_TIM_2_SHDW) Field Descriptions ............................
SDRAM Timing 3 Register (SDRAM_TIM_3) Field Descriptions ................................................
‘‘‘‘‘‘‘‘‘‘‘‘‘‘‘‘‘‘ .................................................................................................................
Power Management Control Register (PWR_MGMT_CTRL) Field Descriptions ..............................
Power Management Control Shadow Register (PWR_MGMT_CTRL_SHDW) Field Descriptions ..........
OCP Configuration Register (OCP_CONFIG) Field Descriptions ................................................
OCP Configuration Value 1 Register (OCP_CFG_VAL_1) Field Descriptions .................................
OCP Configuration Value 2 Register (OCP_CFG_VAL_2) Field Descriptions .................................
IODFT Test Logic Global Control Register (IODFT_TLGC) Field Descriptions ................................
996
9-46.
9-47.
9-48.
9-49.
9-50.
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
9-72.
9-73.
9-74.
9-75.
9-76.
9-77.
9-78.
9-79.
9-80.
9-81.
9-82.
9-83.
9-84.
9-85.
9-86.
9-87.
9-88.
9-89.
9-90.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
997
997
998
1000
1000
1001
1002
1003
1004
1006
1007
1007
1007
1008
1008
1014
1017
1020
1025
1027
1032
1034
1035
1036
1036
1037
1040
1040
1042
1043
1044
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1055
1056
1056
1057
93
www.ti.com
9-91.
IODFT Test Logic Control MISR Result Register (IODFT_CTRL_MISR_RSLT) Field Descriptions ........ 1058
9-92.
IODFT Test Logic Address MISR Result Register (IODFT_ADDR_MISR_RSLT) Field Descriptions ...... 1058
9-93.
IODFT Test Logic Data MISR Result 1 Register (IODFT_DATA_MISR_RSLT_1) Field Descriptions...... 1059
9-94.
IODFT Test Logic Data MISR Result 2 Register (IODFT_DATA_MISR_RSLT_2) Field Descriptions...... 1059
9-95.
IODFT Test Logic Data MISR Result 3 Register (IODFT_DATA_MISR_RSLT_3) Field Descriptions...... 1059
9-96.
Performance Counter 1 Register (PERF_CNT_1) Field Descriptions ...........................................
1060
9-97.
Performance Counter 2 Register (PERF_CNT_2) Field Descriptions ...........................................
1060
9-98.
Performance Counter Configuration Register (PERF_CNT_CFG) Field Descriptions ........................
1061
9-99.
Performance Counter Filter Configuration
..........................................................................
Performance Counter Master Region Select Register (PERF_CNT_SEL) Field Descriptions ...............
Performance Counter Time Register (PERF_CNT_TIM) Field Descriptions ...................................
End of Interrupt Register (IRQ_EOI) Field Descriptions...........................................................
System OCP Interrupt Raw Status Register (IRQSTATUS_RAW_SYS) Field Descriptions .................
System OCP Interrupt Status Register (IRQSTATUS_SYS) Field Descriptions ...............................
System OCP Interrupt Enable Set Register (IRQENABLE_SET_SYS) Field Descriptions...................
System OCP Interrupt Enable Clear Register (IRQENABLE_CLR_SYS) Field Descriptions ................
OCP Error Log Register (OCP_ERR_LOG) Field Descriptions ..................................................
DDR PHY Control 1 Register (DDR_PHY_CTRL_1) Field Descriptions ........................................
DDR PHY Control 1 Shadow Register (DDR_PHY_CTRL_1_SHDW) Field Descriptions ...................
DDR PHY Control 2 Register (DDR_PHY_CTRL_2) Field Descriptions ........................................
Calculating Image Size ...............................................................................................
VRFB Use Case Summarizing Register Print ......................................................................
EMIF and SMS Configuration Registers Space ....................................................................
VRFB Contexts vs Rotation Angle ...................................................................................
SMS Instance Summary ...............................................................................................
SMS Register Mapping Summary ....................................................................................
SMS_SYSCONFIG .....................................................................................................
SMS_SYSSTATUS.....................................................................................................
SMS_RG_ATTi .........................................................................................................
SMS_RG_RDPERMi ...................................................................................................
SMS_RG_WRPERMi ..................................................................................................
SMS_RG_STARTj ......................................................................................................
SMS_RG_ENDj .........................................................................................................
SMS_SECURITY_CONTROL ........................................................................................
SMS_CLASS_ARBITER0 .............................................................................................
SMS_CLASS_ARBITER1 .............................................................................................
SMS_CLASS_ARBITER2 .............................................................................................
SMS_INTERCLASS_ARBITER ......................................................................................
SMS_CLASS_ROTATIONm ..........................................................................................
SMS_ERR_ADDR ......................................................................................................
SMS_ERR_TYPE ......................................................................................................
SMS_POW_CTRL ......................................................................................................
SMS_ROT_CONTROLn ...............................................................................................
SMS_ROT_SIZEn ......................................................................................................
SMS_ROT_PHYSICAL_BAn .........................................................................................
Document Revision History ...........................................................................................
ARM Interrupts - VPFE ................................................................................................
CCD Interface Signals .................................................................................................
ITU-R BT.656 Interface Signals ......................................................................................
1061
9-100.
9-101.
9-102.
9-103.
9-104.
9-105.
9-106.
9-107.
9-108.
9-109.
9-110.
9-111.
9-112.
9-113.
9-114.
9-115.
9-116.
9-117.
9-118.
9-119.
9-120.
9-121.
9-122.
9-123.
9-124.
9-125.
9-126.
9-127.
9-128.
9-129.
9-130.
9-131.
9-132.
9-133.
9-134.
9-135.
9-136.
10-1.
10-2.
10-3.
94
List of Tables
1062
1063
1063
1064
1064
1065
1065
1066
1067
1068
1068
1084
1099
1100
1101
1102
1102
1103
1104
1104
1105
1105
1106
1106
1107
1109
1110
1111
1112
1112
1113
1113
1115
1115
1116
1116
1122
1125
1125
1127
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
10-4.
Video Timing Reference Codes for SAV and EAV .................................................................
1128
10-5.
F, V, H Signal Descriptions
...........................................................................................
1128
10-6.
F, H, V Protection (error correction) Bits ............................................................................
1128
10-7.
CCD Interface Signals .................................................................................................
1129
10-8.
Example for Decimation Pattern ......................................................................................
1134
10-9.
A-Law Table – Part 1
..................................................................................................
A-Law Table – Part 2 ..................................................................................................
Storage Format in external memory for Raw Data Mode .........................................................
Storage Format in external memory for BT.656/YCbCr Modes ..................................................
Basic Configuration of VPFE Registers .............................................................................
Conditional Configuration of VPFE Registers ......................................................................
CCD Controller (CCDC) Register Map .............................................................................
Peripheral Revision and Class Information Register (PID) Field Descriptions .................................
VPFE_Peripheral Control Register (VPFE_PCR) Field Descriptions ............................................
Sync and Mode Set Register (SYN_MODE) Field Descriptions .................................................
Horizontal Pixel Information Register (HORZ_INFO) Field Descriptions .......................................
Vertical Line - Settings for the Starting Pixel Register (VERT_START) Field Descriptions ..................
Number of Vertical Lines Register (VERT_LINES) Field Descriptions ..........................................
Culling Information in Horizontal and Vertical Directions Register (CULLING) Field Descriptions ..........
Horizontal Size Register (HSIZE_OFF) Field Descriptions .......................................................
External Memory Line Offset Register (SDOFST) Field Descriptions ...........................................
External Memory Address Register (SDR_ADDR) Field Descriptions ..........................................
Optical Black Clamping Settings Register (CLAMP) Field Descriptions ........................................
DC Clamp Register (DCSUB) Field Descriptions ..................................................................
CCD Color Pattern Register (COLPTN) Field Descriptions .......................................................
Black Compensation Register (BLKCMP) Field Descriptions ....................................................
VPFE Interrupt Control (VDINT) Register Field Descriptions .....................................................
ALAW Configuration (ALAW) Register Field Descriptions ........................................................
REC656IF Configuration Register (REC656IF) Field Descriptions ..............................................
CCD Configuration Register (CCDCFG) Field Descriptions ......................................................
DMA Control (DMA_CNTL) Field Descriptions .....................................................................
Clock Descriptions......................................................................................................
Instance Summary .....................................................................................................
I/O Pad Mode Selection ...............................................................................................
LCD Interface Signals (RFBI Mode) .................................................................................
LCD Interface Signals (Bypass Mode)...............................................................................
Number of Displayed Pixels per Pixel Clock Cycle Based on Display Type ...................................
Programmable Timing Fields in RFBI Mode ........................................................................
Programmable Fields in Bypass Mode ..............................................................................
Interface Signals Between the SDI Module and LCD Panel ......................................................
I/O Description for DSI Serial Interface ..............................................................................
DSI Lane Configuration ................................................................................................
Video Interface for DSI Protocol Engine.............................................................................
Video Interface in the Context of Video Mode ......................................................................
Video Interface in the Context of Command Mode ................................................................
Pixel Data Format in Video Mode ....................................................................................
Synchronization Codes ................................................................................................
Sync Short Packet Values.............................................................................................
Virtual Channel Values ................................................................................................
1135
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
11-1.
11-2.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1136
1141
1144
1145
1146
1149
1150
1150
1151
1153
1154
1155
1156
1157
1158
1160
1161
1163
1164
1166
1167
1168
1169
1170
1172
1177
1180
1187
1188
1190
1191
1196
1198
1204
1205
1205
1206
1207
1212
1218
1219
1220
1227
95
www.ti.com
.............................................................................................
Display Subsystem Clocks ............................................................................................
Possible Digital Clock Division for the Video Encoder.............................................................
SDI PLL Operation Modes ............................................................................................
DSS DMA Requests Description .....................................................................................
Display Subsystem Interrupts .........................................................................................
DSI Global Interrupts ...................................................................................................
DSI Complex I/O Interrupts ...........................................................................................
DSI Virtual Channel Interrupts ........................................................................................
Functional Clock Frequency Requirement in RGB16 & YUV422—Active Matrix Display ....................
Functional Clock Frequency Requirement in RGB24—Active Matrix Display ..................................
Alpha Blending 4-Bit Values ..........................................................................................
8-Bit Interface Configuration/24-Bit Mode ...........................................................................
Maximum Width Allowed ..............................................................................................
LP to HS Timing Parameters .........................................................................................
HS to LP Timing Parameters .........................................................................................
Extra NULL Packet Header ...........................................................................................
Extra NULL Packet Payload ..........................................................................................
DSI PLL Operation Modes When Not Locked ......................................................................
16-Bit Interface Configuration/24-Bit Mode .........................................................................
Read/Write Function Description .....................................................................................
Minimum Cycle Time for CSx/WE Always Asserted ...............................................................
100/100 Color Bar Table ..............................................................................................
VENC_S_CARR Register Recommended Values .................................................................
Closed-Caption Data Format..........................................................................................
Closed-Caption Run Clock Frequency Settings ....................................................................
Closed-Caption Standard Timing Values ............................................................................
Wide-Screen Signaling Run Clock Frequency Settings ...........................................................
Shadow Registers ......................................................................................................
Vertical/Horizontal Accumulator Phase ..............................................................................
Color Space Conversion Register Values ...........................................................................
90-degree DMA Rotation Example Description ....................................................................
DMA Rotation Register Settings ......................................................................................
Video Rotation Register Settings (With RGB24 Packet Format) .................................................
Register Settings for DMA Rotation With Mirroring ................................................................
VRFB Rotation - DMA Settings .......................................................................................
VRFB Rotation With Mirroring - DMA Settings .....................................................................
Video Rotation Register Settings (YUV Only) ......................................................................
Video Rotation With Mirroring Register Settings (YUV only) .....................................................
Programming Rules ....................................................................................................
Pixel Clock Frequency Limitations - RGB16 and YUV422 Active Matrix Display ..............................
Pixel Clock Frequency Limitations - RGB16 and YUV422 Passive Matrix Display - Mono4 .................
Pixel Clock Frequency Limitations - RGB16 and YUV422 Passive Matrix Display - Mono8 .................
Pixel Clock Frequency Limitations - RGB16 and YUV422 Passive Matrix Display - Color ...................
Register Access Width Limitations ...................................................................................
Virtual Channel TX FIFO Size Values ...............................................................................
Virtual Channel TX FIFO Start Address .............................................................................
Virtual Channel RX FIFO Size Values ...............................................................................
Virtual Channel RX FIFO Start Address .............................................................................
12-17. TV Display Interface Pins
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
12-42.
12-43.
12-44.
12-45.
12-46.
12-47.
12-48.
12-49.
12-50.
12-51.
12-52.
12-53.
12-54.
12-55.
12-56.
12-57.
12-58.
12-59.
12-60.
12-61.
12-62.
12-63.
12-64.
12-65.
96
List of Tables
1233
1238
1240
1243
1246
1248
1249
1250
1251
1265
1265
1271
1276
1276
1279
1281
1281
1282
1304
1308
1309
1309
1310
1311
1311
1312
1313
1314
1325
1335
1336
1338
1340
1341
1342
1342
1344
1345
1346
1347
1348
1348
1348
1349
1356
1361
1361
1362
1362
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
12-66. Recommended Programming Values ................................................................................
1376
..........................................................................................................
1385
12-68. RFBI Timings Configuration ...........................................................................................
1388
12-69. Video Encoder Register Programming Values .....................................................................
1394
12-67. RFBI Behavior
12-70. PLL Divisor Example Values for TI FlatLink3G .....................................................................
1396
12-71. SDI Pixel Data Format .................................................................................................
1397
12-72. Vertical FIR Coefficients Corresponding Table (3-Tap Configuration) ..........................................
1408
12-73. Vertical FIR Coefficients Corresponding Table (5-Tap Configuration) ..........................................
1409
12-74. Horizontal FIR Coefficients Corresponding Table (5-Tap Configuration) .......................................
1409
12-75. Vertical/Horizontal Accumulator Phase ..............................................................................
1411
............................................................
12-77. Up-Sampling Vertical Filter Coefficients (Five Taps) ..............................................................
12-78. Up-Sampling Horizontal Filter Coefficients (Five Taps) ...........................................................
12-79. Down-Sampling Vertical Filter Coefficients (Three Taps) .........................................................
12-80. Down-Sampling Vertical Filter Coefficients (Five Taps) ...........................................................
12-81. Down-Sampling Horizontal Filter Coefficients (Five Taps) ........................................................
12-82. SN65LVDS302 Receiver Mode Transitions .........................................................................
12-83. Registers Print for QVGA LCD panel Pads Multiplexing Configuration .........................................
12-84. Registers Print for Display Subsytem Clock Management ........................................................
12-85. Registers Print for Display Subsystem Power Management .....................................................
12-86. Registers Print for Display Subsystem Software Reset ...........................................................
12-87. VRFB Rotation Configuration .........................................................................................
12-88. VRFB Rotation Configuration for a VGA Display (UYVY format) ................................................
12-89. Video Rotation Register Settings (UYVY Only) ....................................................................
12-90. Registers Print for Video1 Channel Configuration .................................................................
12-91. Registers Print for Interrupts Enable .................................................................................
12-92. Registers Print for Display Panel Configuration ....................................................................
12-93. Registers Print for LCD Enable .......................................................................................
12-94. Ratio R ...................................................................................................................
12-95. Main Steps ..............................................................................................................
12-96. PRCM Registers ........................................................................................................
12-97. Resets....................................................................................................................
12-98. DSI PLL Configuration Registers .....................................................................................
12-99. DSI Control Registers ..................................................................................................
12-100. DSI Complex I/O Registers ..........................................................................................
12-101. DSI Timing Registers .................................................................................................
12-102. Calculate DSI_PHY Timing ..........................................................................................
12-103. Drive Stop State .......................................................................................................
12-104. Reset DISPC ..........................................................................................................
12-105. Configure DISPC Registers ..........................................................................................
12-106. Configure Color Space Coefficient Registers .....................................................................
12-107. Configure DISPC_CONTROL .......................................................................................
12-108. Configure DISPC_VID1_ATTRIBUTES ............................................................................
12-109. Enable DISPC .........................................................................................................
12-110. Main Sequence ........................................................................................................
12-111. Configure DSS Clocks at the PRCM Module ......................................................................
12-112. Configure DSI Protocol Engine, DSI PLL, and Complex I/O ....................................................
12-113. Reset DSI Modules ...................................................................................................
12-114. Configure DSI PLL ....................................................................................................
1412
12-76. Up-Sampling Vertical Filter Coefficients (Three Taps)
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1412
1412
1413
1414
1414
1431
1436
1438
1438
1439
1440
1440
1441
1441
1443
1445
1445
1446
1450
1451
1451
1451
1452
1453
1453
1454
1454
1455
1455
1455
1456
1456
1456
1458
1459
1459
1459
1460
97
www.ti.com
12-115. Switch to DSI PLL Clock Source ....................................................................................
1461
................................................................................................
1461
12-116. DSI Control Registers
12-117. DSI Complex I/O Registers ..........................................................................................
1461
12-118. DSI Timing Registers .................................................................................................
1462
12-119. Configure DSI_PHY Timing ..........................................................................................
1463
12-120. Drive Stop State .......................................................................................................
1464
12-121. Initialization of the External MIPI LCD Controller .................................................................
1464
12-122. Reset DISPC
1464
12-123.
..........................................................................................................
Configure DISPC Registers ..........................................................................................
Configure DISPC_CONTROL .......................................................................................
Enable Command Mode and Automatic TE .......................................................................
Send Frame Data to LCD Panel Using Automatic TE ...........................................................
Instance Summary ....................................................................................................
Display Subsystem Register Mapping Summary .................................................................
Display Controller Register Mapping Summary ...................................................................
Display Controller VID1 Register Summary .......................................................................
Display Controller VID2 Register Summary .......................................................................
RFBI Register Mapping Summary ..................................................................................
Video Encoder Register Mapping Summary ......................................................................
DSI Protocol Engine Register Mapping Summary ................................................................
DSI_PHY Register Mapping Summary .............................................................................
DSI PLL Controller Register Mapping Summary ..................................................................
DSS_REVISIONNUMBER ...........................................................................................
Register Call Summary for Register DSS_REVISIONNUMBER ...............................................
DSS_SYSCONFIG ....................................................................................................
Register Call Summary for Register DSS_SYSCONFIG ........................................................
DSS_SYSSTATUS ...................................................................................................
Register Call Summary for Register DSS_SYSSTATUS ........................................................
DSS_IRQSTATUS ....................................................................................................
Register Call Summary for Register DSS_IRQSTATUS .........................................................
DSS_CONTROL ......................................................................................................
Register Call Summary for Register DSS_CONTROL ...........................................................
DSS_SDI_CONTROL ................................................................................................
Register Call Summary for Register DSS_SDI_CONTROL .....................................................
DSS_PLL_CONTROL ................................................................................................
Register Call Summary for Register DSS_PLL_CONTROL.....................................................
DSS_SDI_STATUS ...................................................................................................
Register Call Summary for Register DSS_SDI_STATUS .......................................................
DISPC_REVISION ....................................................................................................
Register Call Summary for Register DISPC_REVISION ........................................................
DISPC_SYSCONFIG .................................................................................................
Register Call Summary for Register DISPC_SYSCONFIG .....................................................
DISPC_SYSSTATUS .................................................................................................
Register Call Summary for Register DISPC_SYSSTATUS .....................................................
DISPC_IRQSTATUS .................................................................................................
Register Call Summary for Register DISPC_IRQSTATUS ......................................................
DISPC_IRQENABLE .................................................................................................
Register Call Summary for Register DISPC_IRQENABLE ......................................................
DISPC_CONTROL ....................................................................................................
1464
12-124.
12-125.
12-126.
12-127.
12-128.
12-129.
12-130.
12-131.
12-132.
12-133.
12-134.
12-135.
12-136.
12-137.
12-138.
12-139.
12-140.
12-141.
12-142.
12-143.
12-144.
12-145.
12-146.
12-147.
12-148.
12-149.
12-150.
12-151.
12-152.
12-153.
12-154.
12-155.
12-156.
12-157.
12-158.
12-159.
12-160.
12-161.
12-162.
12-163.
98
List of Tables
1465
1465
1466
1467
1467
1468
1468
1469
1470
1470
1471
1472
1473
1473
1473
1473
1474
1474
1474
1475
1475
1475
1476
1476
1477
1477
1479
1479
1480
1480
1481
1481
1482
1482
1483
1483
1485
1485
1487
1487
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
12-164. Register Call Summary for Register DISPC_CONTROL ........................................................
1490
......................................................................................................
1491
12-165. DISPC_CONFIG
12-166. Register Call Summary for Register DISPC_CONFIG ...........................................................
1494
12-167. DISPC_DEFAULT_COLOR_m ......................................................................................
1494
12-168. Register Call Summary for Register DISPC_DEFAULT_COLOR_m ..........................................
1495
12-169. DISPC_TRANS_COLOR_m .........................................................................................
1495
.............................................
1495
12-171. DISPC_LINE_STATUS ...............................................................................................
1495
12-172. Register Call Summary for Register DISPC_LINE_STATUS ...................................................
1496
12-173. DISPC_LINE_NUMBER ..............................................................................................
1496
12-174. Register Call Summary for Register DISPC_LINE_NUMBER ..................................................
1496
12-175. DISPC_TIMING_H ....................................................................................................
1496
12-176. Register Call Summary for Register DISPC_TIMING_H
1497
12-177.
........................................................
DISPC_TIMING_V ....................................................................................................
Register Call Summary for Register DISPC_TIMING_V .........................................................
DISPC_POL_FREQ ..................................................................................................
Register Call Summary for Register DISPC_POL_FREQ .......................................................
DISPC_DIVISOR ......................................................................................................
Register Call Summary for Register DISPC_DIVISOR ..........................................................
DISPC_GLOBAL_ALPHA ............................................................................................
Register Call Summary for Register DISPC_GLOBAL_ALPHA ................................................
DISPC_SIZE_DIG.....................................................................................................
Register Call Summary for Register DISPC_SIZE_DIG .........................................................
DISPC_SIZE_LCD ....................................................................................................
Register Call Summary for Register DISPC_SIZE_LCD ........................................................
DISPC_GFX_BAj......................................................................................................
Register Call Summary for Register DISPC_GFX_BAj ..........................................................
DISPC_GFX_POSITION .............................................................................................
Register Call Summary for Register DISPC_GFX_POSITION .................................................
DISPC_GFX_SIZE ....................................................................................................
Register Call Summary for Register DISPC_GFX_SIZE ........................................................
DISPC_GFX_ATTRIBUTES .........................................................................................
Register Call Summary for Register DISPC_GFX_ATTRIBUTES..............................................
DISPC_GFX_FIFO_THRESHOLD..................................................................................
Register Call Summary for Register DISPC_GFX_FIFO_THRESHOLD ......................................
DISPC_GFX_FIFO_SIZE_STATUS ................................................................................
Register Call Summary for Register DISPC_GFX_FIFO_SIZE_STATUS.....................................
DISPC_GFX_ROW_INC .............................................................................................
Register Call Summary for Register DISPC_GFX_ROW_INC..................................................
DISPC_GFX_PIXEL_INC ............................................................................................
Register Call Summary for Register DISPC_GFX_PIXEL_INC.................................................
DISPC_GFX_WINDOW_SKIP ......................................................................................
Register Call Summary for Register DISPC_GFX_WINDOW_SKIP ...........................................
DISPC_GFX_TABLE_BA ............................................................................................
Register Call Summary for Register DISPC_GFX_TABLE_BA .................................................
DISPC_VIDn_BAj .....................................................................................................
Register Call Summary for Register DISPC_VIDn_BAj ..........................................................
DISPC_VIDn_POSITION ............................................................................................
Register Call Summary for Register DISPC_VIDn_POSITION .................................................
1497
12-170. Register Call Summary for Register DISPC_TRANS_COLOR_m
12-178.
12-179.
12-180.
12-181.
12-182.
12-183.
12-184.
12-185.
12-186.
12-187.
12-188.
12-189.
12-190.
12-191.
12-192.
12-193.
12-194.
12-195.
12-196.
12-197.
12-198.
12-199.
12-200.
12-201.
12-202.
12-203.
12-204.
12-205.
12-206.
12-207.
12-208.
12-209.
12-210.
12-211.
12-212.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1498
1498
1499
1499
1499
1500
1500
1500
1501
1501
1502
1502
1502
1502
1503
1503
1503
1504
1505
1505
1506
1506
1506
1506
1507
1507
1507
1507
1508
1508
1508
1508
1509
1509
1509
99
www.ti.com
1510
12-214.
1510
12-215.
12-216.
12-217.
12-218.
12-219.
12-220.
12-221.
12-222.
12-223.
12-224.
12-225.
12-226.
12-227.
12-228.
12-229.
12-230.
12-231.
12-232.
12-233.
12-234.
12-235.
12-236.
12-237.
12-238.
12-239.
12-240.
12-241.
12-242.
12-243.
12-244.
12-245.
12-246.
12-247.
12-248.
12-249.
12-250.
12-251.
12-252.
12-253.
12-254.
12-255.
12-256.
12-257.
12-258.
12-259.
12-260.
12-261.
100
...................................................................................................
Register Call Summary for Register DISPC_VIDn_SIZE ........................................................
DISPC_VIDn_ATTRIBUTES.........................................................................................
Register Call Summary for Register DISPC_VIDn_ATTRIBUTES .............................................
DISPC_VIDn_FIFO_THRESHOLD .................................................................................
Register Call Summary for Register DISPC_VIDn_FIFO_THRESHOLD......................................
DISPC_VIDn_FIFO_SIZE_STATUS................................................................................
Register Call Summary for Register DISPC_VIDn_FIFO_SIZE_STATUS ....................................
DISPC_VIDn_ROW_INC .............................................................................................
Register Call Summary for Register DISPC_VIDn_ROW_INC .................................................
DISPC_VIDn_PIXEL_INC............................................................................................
Register Call Summary for Register DISPC_VIDn_PIXEL_INC ................................................
DISPC_VIDn_FIR .....................................................................................................
Register Call Summary for Register DISPC_VIDn_FIR..........................................................
DISPC_VIDn_PICTURE_SIZE ......................................................................................
Register Call Summary for Register DISPC_VIDn_PICTURE_SIZE...........................................
DISPC_VIDn_ACCUl .................................................................................................
Register Call Summary for Register DISPC_VIDn_ACCUl ......................................................
DISPC_VIDn_FIR_COEF_Hi ........................................................................................
Register Call Summary for Register DISPC_VIDn_FIR_COEF_Hi ............................................
DISPC_VIDn_FIR_COEF_HVi ......................................................................................
Register Call Summary for Register DISPC_VIDn_FIR_COEF_HVi ...........................................
DISPC_VIDn_CONV_COEF0 .......................................................................................
Register Call Summary for Register DISPC_VIDn_CONV_COEF0............................................
DISPC_VIDn_CONV_COEF1 .......................................................................................
Register Call Summary for Register DISPC_VIDn_CONV_COEF1............................................
DISPC_VIDn_CONV_COEF2 .......................................................................................
Register Call Summary for Register DISPC_VIDn_CONV_COEF2............................................
DISPC_VIDn_CONV_COEF3 .......................................................................................
Register Call Summary for Register DISPC_VIDn_CONV_COEF3............................................
DISPC_VIDn_CONV_COEF4 .......................................................................................
Register Call Summary for Register DISPC_VIDn_CONV_COEF4............................................
DISPC_DATA_CYCLEk ..............................................................................................
Register Call Summary for Register DISPC_DATA_CYCLEk ..................................................
DISPC_VIDn_FIR_COEF_Vi ........................................................................................
Register Call Summary for Register DISPC_VIDn_FIR_COEF_Vi .............................................
DISPC_CPR_COEF_R ...............................................................................................
Register Call Summary for Register DISPC_CPR_COEF_R ...................................................
DISPC_CPR_COEF_G...............................................................................................
Register Call Summary for Register DISPC_CPR_COEF_G ...................................................
DISPC_CPR_COEF_B ...............................................................................................
Register Call Summary for Register DISPC_CPR_COEF_B ...................................................
DISPC_GFX_PRELOAD .............................................................................................
Register Call Summary for Register DISPC_GFX_PRELOAD .................................................
DISPC_VIDn_PRELOAD ............................................................................................
Register Call Summary for Register DISPC_VIDn_PRELOAD .................................................
RFBI_REVISION ......................................................................................................
Register Call Summary for Register RFBI_REVISION...........................................................
RFBI_SYSCONFIG ...................................................................................................
12-213. DISPC_VIDn_SIZE
List of Tables
1510
1513
1513
1513
1514
1514
1514
1514
1515
1515
1515
1516
1516
1516
1517
1517
1517
1518
1518
1518
1518
1519
1519
1519
1519
1520
1520
1520
1520
1521
1521
1522
1522
1522
1522
1523
1523
1523
1524
1524
1524
1524
1525
1525
1525
1525
1525
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
12-262. Register Call Summary for Register RFBI_SYSCONFIG........................................................
1526
12-263. RFBI_SYSSTATUS ...................................................................................................
1526
12-264. Register Call Summary for Register RFBI_SYSSTATUS
1527
12-265.
.......................................................
RFBI_CONTROL ......................................................................................................
Register Call Summary for Register RFBI_CONTROL ..........................................................
RFBI_PIXEL_CNT ....................................................................................................
Register Call Summary for Register RFBI_PIXEL_CNT .........................................................
RFBI_LINE_NUMBER ................................................................................................
Register Call Summary for Register RFBI_LINE_NUMBER ....................................................
RFBI_CMD .............................................................................................................
Register Call Summary for Register RFBI_CMD .................................................................
RFBI_PARAM .........................................................................................................
Register Call Summary for Register RFBI_PARAM ..............................................................
RFBI_DATA ............................................................................................................
Register Call Summary for Register RFBI_DATA ................................................................
RFBI_READ ...........................................................................................................
Register Call Summary for Register RFBI_READ ................................................................
RFBI_STATUS ........................................................................................................
Register Call Summary for Register RFBI_STATUS .............................................................
RFBI_CONFIGi ........................................................................................................
Register Call Summary for Register RFBI_CONFIGi ............................................................
RFBI_ONOFF_TIMEi .................................................................................................
Register Call Summary for Register RFBI_ONOFF_TIMEi .....................................................
RFBI_CYCLE_TIMEi .................................................................................................
Register Call Summary for Register RFBI_CYCLE_TIMEi ......................................................
RFBI_DATA_CYCLE1_i ..............................................................................................
Register Call Summary for Register RFBI_DATA_CYCLE1_i ..................................................
RFBI_DATA_CYCLE2_i ..............................................................................................
Register Call Summary for Register RFBI_DATA_CYCLE2_i ..................................................
RFBI_DATA_CYCLE3_i ..............................................................................................
Register Call Summary for Register RFBI_DATA_CYCLE3_i ..................................................
RFBI_VSYNC_WIDTH ...............................................................................................
Register Call Summary for Register RFBI_VSYNC_WIDTH ....................................................
RFBI_HSYNC_WIDTH ...............................................................................................
Register Call Summary for Register RFBI_HSYNC_WIDTH ....................................................
VENC_REV_ID ........................................................................................................
Register Call Summary for Register VENC_REV_ID ............................................................
VENC_STATUS .......................................................................................................
Register Call Summary for Register VENC_STATUS ...........................................................
VENC_F_CONTROL .................................................................................................
Register Call Summary for Register VENC_F_CONTROL ......................................................
VENC_VIDOUT_CTRL ...............................................................................................
Register Call Summary for Register VENC_VIDOUT_CTRL ...................................................
VENC_SYNC_CTRL..................................................................................................
Register Call Summary for Register VENC_SYNC_CTRL ......................................................
VENC_LLEN ...........................................................................................................
Register Call Summary for Register VENC_LLEN ...............................................................
VENC_FLENS .........................................................................................................
Register Call Summary for Register VENC_FLENS .............................................................
1527
12-266.
12-267.
12-268.
12-269.
12-270.
12-271.
12-272.
12-273.
12-274.
12-275.
12-276.
12-277.
12-278.
12-279.
12-280.
12-281.
12-282.
12-283.
12-284.
12-285.
12-286.
12-287.
12-288.
12-289.
12-290.
12-291.
12-292.
12-293.
12-294.
12-295.
12-296.
12-297.
12-298.
12-299.
12-300.
12-301.
12-302.
12-303.
12-304.
12-305.
12-306.
12-307.
12-308.
12-309.
12-310.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1528
1528
1529
1529
1529
1529
1530
1530
1530
1530
1531
1531
1531
1532
1532
1532
1533
1534
1534
1535
1535
1535
1536
1536
1537
1537
1538
1538
1538
1538
1539
1539
1539
1539
1540
1540
1541
1541
1541
1542
1543
1543
1543
1543
1544
101
www.ti.com
1544
12-312.
1544
12-313.
12-314.
12-315.
12-316.
12-317.
12-318.
12-319.
12-320.
12-321.
12-322.
12-323.
12-324.
12-325.
12-326.
12-327.
12-328.
12-329.
12-330.
12-331.
12-332.
12-333.
12-334.
12-335.
12-336.
12-337.
12-338.
12-339.
12-340.
12-341.
12-342.
12-343.
12-344.
12-345.
12-346.
12-347.
12-348.
12-349.
12-350.
12-351.
12-352.
12-353.
12-354.
12-355.
12-356.
12-357.
12-358.
12-359.
102
................................................................................................
Register Call Summary for Register VENC_HFLTR_CTRL .....................................................
VENC_CC_CARR_WSS_CARR ....................................................................................
Register Call Summary for Register VENC_CC_CARR_WSS_CARR ........................................
VENC_C_PHASE .....................................................................................................
Register Call Summary for Register VENC_C_PHASE..........................................................
VENC_GAIN_U........................................................................................................
Register Call Summary for Register VENC_GAIN_U ............................................................
VENC_GAIN_V ........................................................................................................
Register Call Summary for Register VENC_GAIN_V ............................................................
VENC_GAIN_Y ........................................................................................................
Register Call Summary for Register VENC_GAIN_Y ............................................................
VENC_BLACK_LEVEL ...............................................................................................
Register Call Summary for Register VENC_BLACK_LEVEL ...................................................
VENC_BLANK_LEVEL ...............................................................................................
Register Call Summary for Register VENC_BLANK_LEVEL ...................................................
VENC_X_COLOR .....................................................................................................
Register Call Summary for Register VENC_X_COLOR .........................................................
VENC_M_CONTROL .................................................................................................
Register Call Summary for Register VENC_M_CONTROL .....................................................
VENC_BSTAMP_WSS_DATA ......................................................................................
Register Call Summary for Register VENC_BSTAMP_WSS_DATA ...........................................
VENC_S_CARR .......................................................................................................
Register Call Summary for Register VENC_S_CARR ...........................................................
VENC_LINE21.........................................................................................................
Register Call Summary for Register VENC_LINE21 .............................................................
VENC_LN_SEL........................................................................................................
Register Call Summary for Register VENC_LN_SEL ............................................................
VENC_L21_WC_CTL ................................................................................................
Register Call Summary for Register VENC_L21_WC_CTL .....................................................
VENC_HTRIGGER_VTRIGGER ....................................................................................
Register Call Summary for Register VENC_HTRIGGER_VTRIGGER ........................................
VENC_SAVID_EAVID ................................................................................................
Register Call Summary for Register VENC_SAVID_EAVID ....................................................
VENC_FLEN_FAL ....................................................................................................
Register Call Summary for Register VENC_FLEN_FAL .........................................................
VENC_LAL_PHASE_RESET ........................................................................................
Register Call Summary for Register VENC_LAL_PHASE_RESET ............................................
VENC_HS_INT_START_STOP_X .................................................................................
Register Call Summary for Register VENC_HS_INT_START_STOP_X ......................................
VENC_HS_EXT_START_STOP_X .................................................................................
Register Call Summary for Register VENC_HS_EXT_START_STOP_X .....................................
VENC_VS_INT_START_X ..........................................................................................
Register Call Summary for Register VENC_VS_INT_START_X ...............................................
VENC_VS_INT_STOP_X_VS_INT_START_Y ...................................................................
Register Call Summary for Register VENC_VS_INT_STOP_X_VS_INT_START_Y ........................
VENC_VS_INT_STOP_Y_VS_EXT_START_X...................................................................
Register Call Summary for Register VENC_VS_INT_STOP_Y_VS_EXT_START_X .......................
VENC_VS_EXT_STOP_X_VS_EXT_START_Y ..................................................................
12-311. VENC_HFLTR_CTRL
List of Tables
1544
1545
1545
1545
1545
1546
1546
1546
1546
1547
1547
1547
1547
1548
1548
1549
1549
1550
1550
1550
1551
1551
1551
1552
1552
1552
1552
1553
1553
1554
1554
1554
1554
1555
1555
1555
1556
1556
1556
1556
1557
1557
1557
1557
1558
1558
1558
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
12-360. Register Call Summary for Register VENC_VS_EXT_STOP_X_VS_EXT_START_Y ......................
1558
12-361. VENC_VS_EXT_STOP_Y ...........................................................................................
1559
12-362. Register Call Summary for Register VENC_VS_EXT_STOP_Y ................................................
1559
12-363. VENC_AVID_START_STOP_X .....................................................................................
1559
12-364. Register Call Summary for Register VENC_AVID_START_STOP_X .........................................
1559
12-365. VENC_AVID_START_STOP_Y .....................................................................................
1559
12-366. Register Call Summary for Register VENC_AVID_START_STOP_Y .........................................
1560
................................................................
Register Call Summary for Register VENC_FID_INT_START_X_FID_INT_START_Y .....................
VENC_FID_INT_OFFSET_Y_FID_EXT_START_X ..............................................................
Register Call Summary for Register VENC_FID_INT_OFFSET_Y_FID_EXT_START_X ..................
VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y .............................................................
Register Call Summary for Register VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y .................
VENC_TVDETGP_INT_START_STOP_X.........................................................................
Register Call Summary for Register VENC_TVDETGP_INT_START_STOP_X .............................
VENC_TVDETGP_INT_START_STOP_Y.........................................................................
Register Call Summary for Register VENC_TVDETGP_INT_START_STOP_Y .............................
VENC_GEN_CTRL ...................................................................................................
Register Call Summary for Register VENC_GEN_CTRL ........................................................
VENC_OUTPUT_CONTROL ........................................................................................
Register Call Summary for Register VENC_OUTPUT_CONTROL ............................................
VENC_OUTPUT_TEST ..............................................................................................
Register Call Summary for Register VENC_OUTPUT_TEST ...................................................
DSI_REVISION ........................................................................................................
Register Call Summary for Register DSI_REVISION ............................................................
DSI_SYSCONFIG .....................................................................................................
Register Call Summary for Register DSI_SYSCONFIG .........................................................
DSI_SYSSTATUS.....................................................................................................
Register Call Summary for Register DSI_SYSSTATUS .........................................................
DSI_IRQSTATUS .....................................................................................................
Register Call Summary for Register DSI_IRQSTATUS ..........................................................
DSI_IRQENABLE .....................................................................................................
Register Call Summary for Register DSI_IRQENABLE ..........................................................
DSI_CTRL..............................................................................................................
Register Call Summary for Register DSI_CTRL ..................................................................
DSI_COMPLEXIO_CFG1 ............................................................................................
Register Call Summary for Register DSI_COMPLEXIO_CFG1 ................................................
DSI_COMPLEXIO_IRQSTATUS ....................................................................................
Register Call Summary for Register DSI_COMPLEXIO_IRQSTATUS ........................................
DSI_COMPLEXIO_IRQENABLE ....................................................................................
Register Call Summary for Register DSI_COMPLEXIO_IRQENABLE ........................................
DSI_CLK_CTRL .......................................................................................................
Register Call Summary for Register DSI_CLK_CTRL ...........................................................
DSI_TIMING1 ..........................................................................................................
Register Call Summary for Register DSI_TIMING1 ..............................................................
DSI_TIMING2 ..........................................................................................................
Register Call Summary for Register DSI_TIMING2 ..............................................................
DSI_VM_TIMING1 ....................................................................................................
Register Call Summary for Register DSI_VM_TIMING1 .........................................................
12-367. VENC_FID_INT_START_X_FID_INT_START_Y
1560
12-368.
1560
12-369.
12-370.
12-371.
12-372.
12-373.
12-374.
12-375.
12-376.
12-377.
12-378.
12-379.
12-380.
12-381.
12-382.
12-383.
12-384.
12-385.
12-386.
12-387.
12-388.
12-389.
12-390.
12-391.
12-392.
12-393.
12-394.
12-395.
12-396.
12-397.
12-398.
12-399.
12-400.
12-401.
12-402.
12-403.
12-404.
12-405.
12-406.
12-407.
12-408.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1560
1561
1561
1561
1561
1562
1562
1562
1562
1563
1564
1565
1565
1565
1565
1566
1566
1567
1567
1568
1568
1570
1571
1572
1572
1575
1576
1578
1578
1581
1581
1584
1584
1585
1586
1587
1587
1588
1588
1589
103
www.ti.com
12-409. DSI_VM_TIMING2 ....................................................................................................
1589
12-410. Register Call Summary for Register DSI_VM_TIMING2 .........................................................
1590
12-411. DSI_VM_TIMING3 ....................................................................................................
1590
12-412. Register Call Summary for Register DSI_VM_TIMING3 .........................................................
1590
....................................................................................................
1590
12-414. Register Call Summary for Register DSI_CLK_TIMING .........................................................
1591
12-413. DSI_CLK_TIMING
12-415. DSI_TX_FIFO_VC_SIZE .............................................................................................
1591
12-416. Register Call Summary for Register DSI_TX_FIFO_VC_SIZE .................................................
1592
12-417. DSI_RX_FIFO_VC_SIZE
1592
12-418.
............................................................................................
Register Call Summary for Register DSI_RX_FIFO_VC_SIZE .................................................
DSI_COMPLEXIO_CFG2 ............................................................................................
Register Call Summary for Register DSI_COMPLEXIO_CFG2 ................................................
DSI_RX_FIFO_VC_FULLNESS ....................................................................................
Register Call Summary for Register DSI_RX_FIFO_VC_FULLNESS .........................................
DSI_VM_TIMING4 ....................................................................................................
Register Call Summary for Register DSI_VM_TIMING4 .........................................................
DSI_TX_FIFO_VC_EMPTINESS ...................................................................................
Register Call Summary for Register DSI_TX_FIFO_VC_EMPTINESS ........................................
DSI_VM_TIMING5 ....................................................................................................
Register Call Summary for Register DSI_VM_TIMING5 .........................................................
DSI_VM_TIMING6 ....................................................................................................
Register Call Summary for Register DSI_VM_TIMING6 .........................................................
DSI_VM_TIMING7 ....................................................................................................
Register Call Summary for Register DSI_VM_TIMING7 .........................................................
DSI_STOPCLK_TIMING .............................................................................................
Register Call Summary for Register DSI_STOPCLK_TIMING..................................................
DSI_VCn_CTRL .......................................................................................................
Register Call Summary for Register DSI_VCn_CTRL ...........................................................
DSI_VCn_TE ..........................................................................................................
Register Call Summary for Register DSI_VCn_TE ...............................................................
DSI_VCn_LONG_PACKET_HEADER .............................................................................
Register Call Summary for Register DSI_VCn_LONG_PACKET_HEADER ..................................
DSI_VCn_LONG_PACKET_PAYLOAD ............................................................................
Register Call Summary for Register DSI_VCn_LONG_PACKET_PAYLOAD ................................
DSI_VCn_SHORT_PACKET_HEADER ...........................................................................
Register Call Summary for Register DSI_VCn_SHORT_PACKET_HEADER ................................
DSI_VCn_IRQSTATUS ..............................................................................................
Register Call Summary for Register DSI_VCn_IRQSTATUS ...................................................
DSI_VCn_IRQENABLE ..............................................................................................
Register Call Summary for Register DSI_VCn_IRQENABLE ...................................................
DSI_PHY_CFG0 ......................................................................................................
Register Call Summary for Register DSI_PHY_CFG0 ...........................................................
DSI_PHY_CFG1 ......................................................................................................
Register Call Summary for Register DSI_PHY_CFG1 ...........................................................
DSI_PHY_CFG2 ......................................................................................................
Register Call Summary for Register DSI_PHY_CFG2 ...........................................................
DSI_PHY_CFG3 ......................................................................................................
Register Call Summary for Register DSI_PHY_CFG3 ...........................................................
DSI_PHY_CFG4 ......................................................................................................
1593
12-419.
12-420.
12-421.
12-422.
12-423.
12-424.
12-425.
12-426.
12-427.
12-428.
12-429.
12-430.
12-431.
12-432.
12-433.
12-434.
12-435.
12-436.
12-437.
12-438.
12-439.
12-440.
12-441.
12-442.
12-443.
12-444.
12-445.
12-446.
12-447.
12-448.
12-449.
12-450.
12-451.
12-452.
12-453.
12-454.
12-455.
12-456.
12-457.
104
List of Tables
1593
1595
1595
1596
1596
1596
1596
1597
1597
1597
1598
1598
1598
1599
1599
1599
1599
1602
1603
1603
1604
1604
1604
1605
1605
1605
1606
1607
1607
1609
1609
1609
1610
1611
1611
1611
1612
1612
1612
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
12-458. Register Call Summary for Register DSI_PHY_CFG4 ...........................................................
1612
12-459. DSI_PHY_CFG5 ......................................................................................................
1613
12-460. Register Call Summary for Register DSI_PHY_CFG5 ...........................................................
1613
12-461. DSI_PLL_CONTROL .................................................................................................
1614
12-462. Register Call Summary for Register DSI_PLL_CONTROL ......................................................
1614
12-463. DSI_PLL_STATUS ....................................................................................................
1615
12-464. Register Call Summary for Register DSI_PLL_STATUS ........................................................
1616
12-465. DSI_PLL_GO ..........................................................................................................
1616
12-466. Register Call Summary for Register DSI_PLL_GO ...............................................................
1617
12-467. DSI_PLL_CONFIGURATION1 ......................................................................................
1617
12-468. Register Call Summary for Register DSI_PLL_CONFIGURATION1 ...........................................
1617
12-469. DSI_PLL_CONFIGURATION2 ......................................................................................
1618
12-470. Register Call Summary for Register DSI_PLL_CONFIGURATION2 ...........................................
1619
13-1.
Input/Output Description ...............................................................................................
1624
13-2.
Clock, Power, and Reset Domains for GP Timers .................................................................
1626
13-3.
GP Timer PRCM Clock Selection Bits ...............................................................................
1626
13-4.
GP Timer PRCM Clock Control Bits .................................................................................
1626
13-5.
IDLEMODE Settings ...................................................................................................
1627
13-6.
CLOCKACTIVITY Settings ............................................................................................
1628
13-7.
Timer Interrupt Names and Processor IRQ Mapping ..............................................................
1630
13-8.
Value Loaded in GPTi.TCRR to Generate 1-ms Tick
.............................................................
Prescaler/Timer Reload Values Versus Contexts ..................................................................
Prescaler Clock Ratio Values .........................................................................................
Value and Corresponding Interrupt Period ..........................................................................
GP Timer Instance Summary .........................................................................................
GPTIMER1 to GPTIMER4 Register Summary .....................................................................
GPTIMER5 to GPTIMER8 Register Summary .....................................................................
GPTIMER9 to GPTIMER11 Register Summary ....................................................................
TIDR ......................................................................................................................
Register Call Summary for Register TIDR ..........................................................................
TIOCP_CFG.............................................................................................................
Register Call Summary for Register TIOCP_CFG .................................................................
TISTAT ...................................................................................................................
Register Call Summary for Register TISTAT .......................................................................
TISR ......................................................................................................................
Register Call Summary for Register TISR ..........................................................................
TIER ......................................................................................................................
Register Call Summary for Register TIER ..........................................................................
TWER ....................................................................................................................
Register Call Summary for Register TWER.........................................................................
TCLR .....................................................................................................................
Register Call Summary for Register TCLR .........................................................................
TCRR ....................................................................................................................
Register Call Summary for Register TCRR .........................................................................
TLDR .....................................................................................................................
Register Call Summary for Register TLDR .........................................................................
TTGR .....................................................................................................................
Register Call Summary for Register TTGR .........................................................................
TWPS ....................................................................................................................
1635
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1638
1639
1640
1643
1644
1645
1646
1646
1647
1647
1648
1649
1649
1650
1651
1651
1652
1652
1653
1653
1655
1655
1656
1656
1657
1657
1657
1658
105
www.ti.com
13-37. Register Call Summary for Register TWPS .........................................................................
1659
....................................................................................................................
1660
13-39. Register Call Summary for Register TMAR .........................................................................
1660
13-40. TCAR1 ...................................................................................................................
1661
13-41. Register Call Summary for Register TCAR1 ........................................................................
1661
13-42. TSICR ....................................................................................................................
1662
........................................................................
1662
13-38. TMAR
13-43. Register Call Summary for Register TSICR
13-44. TCAR2 ...................................................................................................................
1663
13-45. Register Call Summary for Register TCAR2 ........................................................................
1663
13-46. TPIR ......................................................................................................................
1663
13-47. Register Call Summary for Register TPIR
1664
13-48.
..........................................................................
TNIR ......................................................................................................................
Register Call Summary for Register TNIR ..........................................................................
TCVR .....................................................................................................................
Register Call Summary for Register TCVR .........................................................................
TOCR ....................................................................................................................
Register Call Summary for Register TOCR .........................................................................
TOWR ....................................................................................................................
Register Call Summary for Register TOWR ........................................................................
WD Timers Default State for GP and EMU devices ...............................................................
Clock, Power, and Reset Domains for WDTs ......................................................................
WDT PRCM Clock Control Bits .......................................................................................
IDLEMODE Settings ...................................................................................................
CLOCKACTIVITY Settings ............................................................................................
WDT Interrupt Names and Processor IRQ Mapping...............................................................
Count and Prescaler Default Reset Values .........................................................................
Prescaler Clock Ratios.................................................................................................
Reset Period Examples ................................................................................................
Default WDT Time Periods ............................................................................................
WDT Instance Summary ..............................................................................................
WDTIMER2 Register Summary ......................................................................................
WDTIMER3 Register Summary ......................................................................................
WIDR .....................................................................................................................
Register Call Summary for Register WIDR .........................................................................
WD_SYSCONFIG ......................................................................................................
Register Call Summary for Register WD_SYSCONFIG ...........................................................
WD_SYSSTATUS ......................................................................................................
Register Call Summary for Register WD_SYSSTATUS ..........................................................
WISR .....................................................................................................................
Register Call Summary for Register WISR .........................................................................
WIER .....................................................................................................................
Register Call Summary for Register WIER .........................................................................
WCLR ....................................................................................................................
Register Call Summary for Register WCLR.........................................................................
WCRR....................................................................................................................
Register Call Summary for Register WCRR ........................................................................
WLDR ....................................................................................................................
Register Call Summary for Register WLDR.........................................................................
WTGR ....................................................................................................................
1664
13-49.
13-50.
13-51.
13-52.
13-53.
13-54.
13-55.
13-56.
13-57.
13-58.
13-59.
13-60.
13-61.
13-62.
13-63.
13-64.
13-65.
13-66.
13-67.
13-68.
13-69.
13-70.
13-71.
13-72.
13-73.
13-74.
13-75.
13-76.
13-77.
13-78.
13-79.
13-80.
13-81.
13-82.
13-83.
13-84.
13-85.
106
List of Tables
1664
1665
1665
1665
1665
1666
1666
1667
1669
1669
1669
1670
1671
1672
1672
1673
1673
1676
1676
1676
1677
1677
1677
1678
1678
1679
1679
1679
1679
1680
1680
1680
1681
1681
1681
1682
1682
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
13-86. Register Call Summary for Register WTGR ........................................................................
1682
13-87. WWPS ...................................................................................................................
1682
13-88. Register Call Summary for Register WWPS ........................................................................
1683
13-89. WSPR ....................................................................................................................
1683
........................................................................
1683
13-91. Clock, Power, and Reset Domains for 32-kHz Sync Timer .......................................................
1685
13-92. 32-kHz Sync Timer Instance Summary..............................................................................
1686
13-90. Register Call Summary for Register WSPR
13-93. 32-kHz Sync Timer Register Summary ..............................................................................
1686
13-94. REG_32KSYNCNT_REV ..............................................................................................
1686
13-95. Register Call Summary for Register REG_32KSYNCNT_REV ..................................................
1687
13-96. REG_32KSYNCNT_SYSCONFIG ...................................................................................
1687
13-97. Register Call Summary for Register REG_32KSYNCNT_SYSCONFIG ........................................
1687
13-98. REG_32KSYNCNT_CR ...............................................................................................
1687
13-99. Register Call Summary for Register REG_32KSYNCNT_CR ....................................................
1687
14-1.
UART Mode Baud Rates, Divisor Values, and Error Rates.......................................................
1690
14-2.
UART IrDA Mode Baud Rates, Divisor Values, and Error Rates ................................................
1691
14-3.
UART I/O Pin Description .............................................................................................
1693
14-4.
UART3 I/O Description
................................................................................................
EFR_REG[0-1] IR Address Checking Options .....................................................................
FIR Transmit Frame Format ..........................................................................................
4-PPM Format ..........................................................................................................
FIR Preamble, Start Flag, and Stop Flag ...........................................................................
FIR Data Byte Transmission Order Example .......................................................................
CIR I/O Description .....................................................................................................
UART Clocks ............................................................................................................
Reset Domain ...........................................................................................................
Interrupt Mapping to MPU Subsystem ...............................................................................
UART DMA Requests to System DMA ..............................................................................
Wake-Up Requests from PRCM......................................................................................
TX FIFO Trigger Level Setting Summary ...........................................................................
RX FIFO Trigger Level Setting Summary ...........................................................................
UART/IrDA/CIR Register Access Mode Programming (Using LCR_REG) .....................................
Sub-Configuration_Mode_A Mode Summary .......................................................................
Sub-Configuration_Mode_B Mode Summary .......................................................................
Sub-Operational_Mode Mode Summary ............................................................................
UART/IrDA/CIR Register Access Mode Overview .................................................................
UART Mode Selection .................................................................................................
UART Mode Register Overview .....................................................................................
IrDA Mode Register Overview .......................................................................................
CIR Mode Register Overview ........................................................................................
UART Baud Rate Settings (48-MHz Clock) .........................................................................
UART Parity Bit Encoding .............................................................................................
EFR_REG[0-3] Software Flow Control Options ....................................................................
UART Mode Interrupts .................................................................................................
IrDA Baud Rates Settings .............................................................................................
IrDA Mode Interrupts ...................................................................................................
Duty Cycle ...............................................................................................................
CIR Mode Interrupts....................................................................................................
Instance Summary .....................................................................................................
1694
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1697
1700
1700
1700
1700
1701
1706
1707
1707
1707
1708
1711
1711
1717
1717
1717
1717
1718
1719
1719
1720
1721
1722
1723
1724
1727
1729
1732
1734
1735
1746
107
www.ti.com
14-36. UART Mode Overview .................................................................................................
1746
........................................................................................
1747
14-38. UART1/2/3/4 Register Summary for Configuration_Mode_A Mode Active .....................................
1747
14-39. UART1/2/3/4 Subconfiguration_Mode_A Mode Summary ........................................................
1747
14-37. UART1/2/3/4 Mode Summary
14-40. UART1/2/3/4 Register Summary for Sub-Configuration_Mode_A Mode: MSR_SPR Mode Active ......... 1748
14-41. UART1/2/3/4 Register Summary for Sub-Configuration_Mode_A Mode: TCR_TLR Mode Active .......... 1748
14-42. UART1/2/3/4 Register Summary for Configuration_Mode_B Mode Active .....................................
1748
1749
14-44.
1749
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
14-81.
14-82.
14-83.
14-84.
108
......................................................
UART1/2/3/4 Register Summary for Sub-Configuration_Mode_B Mode: TCR_TLR Mode Active ..........
UART1/2/3/4 Register Summary for Sub-Configuration_Mode_B Mode: XOFF Mode Active ...............
UART1/2/3/4 Register Summary for Operational_Mode Mode Active ..........................................
UART1/2/3/4 Sub-Operational_Mode Mode Summary ............................................................
UART1/2/3/4 Register Summary for Sub-Operational_Mode Mode: MSR_SPR Mode Active ...............
UART1/2/3/4 Register Summary for Suboperational_Mode Mode: TCR_TLR Mode Active .................
DLL_REG ................................................................................................................
RHR_REG ...............................................................................................................
THR_REG ...............................................................................................................
IER_REG ................................................................................................................
DLH_REG ...............................................................................................................
FCR_REG ...............................................................................................................
IIR_REG .................................................................................................................
EFR_REG ...............................................................................................................
LCR_REG ...............................................................................................................
MCR_REG ..............................................................................................................
XON1_ADDR1_REG ...................................................................................................
LSR_REG ...............................................................................................................
XON2_ADDR2_REG ...................................................................................................
XOFF1_REG ............................................................................................................
TCR_REG ...............................................................................................................
MSR_REG ...............................................................................................................
SPR_REG ...............................................................................................................
XOFF2_REG ............................................................................................................
TLR_REG................................................................................................................
MDR1_REG .............................................................................................................
MDR2_REG .............................................................................................................
TXFLL_REG.............................................................................................................
SFLSR_REG ............................................................................................................
RESUME_REG .........................................................................................................
TXFLH_REG ............................................................................................................
RXFLL_REG ............................................................................................................
SFREGL_REG ..........................................................................................................
SFREGH_REG .........................................................................................................
RXFLH_REG ............................................................................................................
BLR_REG ...............................................................................................................
UASR_REG .............................................................................................................
ACREG_REG ...........................................................................................................
SCR_REG ...............................................................................................................
SSR_REG ...............................................................................................................
EBLR_REG..............................................................................................................
14-43. UART1/2/3/4 Sub-Configuration_Mode_B Mode Summary
List of Tables
1749
1749
1750
1750
1750
1751
1752
1753
1754
1757
1758
1760
1763
1764
1766
1767
1768
1771
1771
1772
1773
1774
1774
1775
1776
1778
1779
1780
1781
1781
1782
1783
1784
1785
1786
1787
1788
1790
1791
1792
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
14-85. SYSC_REG .............................................................................................................
1793
14-86. SYSS_REG
1795
14-88.
.............................................................................................................
..............................................................................................................
CFPS_REG .............................................................................................................
Input/Output .............................................................................................................
Input/Output .............................................................................................................
Input/Output Description ...............................................................................................
Multimaster HS I2C Controller Power Management Modes .......................................................
State of the Interface and Functional Clocks When the Module is in Idle Mode ...............................
Wake-up Events ........................................................................................................
Multimaster HS I2C Controller DMA Requests ......................................................................
Multimaster HS I2C Controller Interrupt Requests..................................................................
Multimaster HS I2C Controller Interrupt Events .....................................................................
Operation Mode Selection .............................................................................................
RX and TX FIFO Depths ..............................................................................................
HS I2C tLOW and tHIGHValues of the I2C Clock.........................................................................
List of tests for the Multimaster HS I2C Controllers ................................................................
Instance Summary .....................................................................................................
Register Summary......................................................................................................
I2C_REV .................................................................................................................
Register Call Summary for Register I2C_REV .....................................................................
I2C_IE ....................................................................................................................
Register Call Summary for Register I2C_IE ........................................................................
I2C_STAT ...............................................................................................................
Register Call Summary for Register I2C_STAT ....................................................................
I2C_WE ..................................................................................................................
Register Call Summary for Register I2C_WE ......................................................................
I2C_SYSS ...............................................................................................................
Register Call Summary for Register I2C_SYSS....................................................................
I2C_BUF .................................................................................................................
Register Call Summary for Register I2C_BUF .....................................................................
I2C_CNT .................................................................................................................
Register Call Summary for Register I2C_CNT .....................................................................
I2C_DATA ...............................................................................................................
Register Call Summary for Register I2C_DATA ....................................................................
I2C_SYSC ...............................................................................................................
Register Call Summary for Register I2C_SYSC ...................................................................
I2C_CON ................................................................................................................
Register Call Summary for Register I2C_CON .....................................................................
I2C_OA0 .................................................................................................................
Register Call Summary for Register I2C_OA0 .....................................................................
I2C_SA ...................................................................................................................
Register Call Summary for Register I2C_SA .......................................................................
I2C_PSC .................................................................................................................
Register Call Summary for Register I2C_PSC .....................................................................
I2C_SCLL................................................................................................................
Register Call Summary for Register I2C_SCLL ....................................................................
I2C_SCLH ...............................................................................................................
Register Call Summary for Register I2C_SCLH ....................................................................
1794
14-87. WER_REG
1796
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
15-44.
15-45.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1801
1807
1811
1816
1816
1817
1819
1819
1819
1822
1823
1828
1829
1850
1850
1851
1851
1851
1852
1853
1855
1855
1856
1857
1857
1857
1858
1858
1859
1859
1859
1860
1860
1861
1862
1862
1863
1863
1863
1864
1864
1864
1865
1865
1865
109
www.ti.com
15-46. I2C_SYSTEST ..........................................................................................................
1865
..............................................................
1866
15-47. Register Call Summary for Register I2C_SYSTEST
15-48. I2C_BUFSTAT ..........................................................................................................
1866
15-49. Register Call Summary for Register I2C_BUFSTAT
1867
15-50.
..............................................................
I2C_OA1 .................................................................................................................
Register Call Summary for Register I2C_OA1 .....................................................................
I2C_OA2 .................................................................................................................
Register Call Summary for Register I2C_OA2 .....................................................................
I2C_OA3 .................................................................................................................
Register Call Summary for Register I2C_OA3 .....................................................................
I2C_ACTOA .............................................................................................................
Register Call Summary for Register I2C_ACTOA .................................................................
I2C_SBLOCK ...........................................................................................................
Register Call Summary for Register I2C_SBLOCK ................................................................
McSPI I/O Description (Master Mode) ...............................................................................
McSPI I/O Description (Slave Mode) ................................................................................
SPI Master Clock Rates ...............................................................................................
Phase and Polarity Combinations ....................................................................................
McSPI Clocks ...........................................................................................................
Power Domain ..........................................................................................................
McSPI Hardware Reset ................................................................................................
DMA Requests ..........................................................................................................
Interrupt Requests ......................................................................................................
Wake-Up Requests.....................................................................................................
SPI Master Clock Rates ...............................................................................................
CLKSPIO High/Low Time Computation .............................................................................
Clock Granularity Examples...........................................................................................
FIFO Writes, Word Length Relationship .............................................................................
Smart-Idle Mode and Wake-Up Capabilities ........................................................................
End-of-Transfer Sequences ...........................................................................................
End-of-Transfer Types .................................................................................................
EPSON VGA Configuration Commands.............................................................................
McSPI Configuration Registers Print .................................................................................
Display Configuration Registers Print ................................................................................
Display Status Check Registers Print ................................................................................
McSPI Instance Summary .............................................................................................
McSPI Register Summary .............................................................................................
MCSPI_REVISION .....................................................................................................
Register Call Summary for Register MCSPI_REVISION..........................................................
MCSPI_SYSCONFIG ..................................................................................................
Register Call Summary for Register MCSPI_SYSCONFIG.......................................................
MCSPI_SYSSTATUS ..................................................................................................
Register Call Summary for Register MCSPI_SYSSTATUS ......................................................
MCSPI_IRQSTATUS ..................................................................................................
Register Call Summary for Register MCSPI_IRQSTATUS .......................................................
MCSPI_IRQENABLE ..................................................................................................
Register Call Summary for Register MCSPI_IRQENABLE .......................................................
MCSPI_WAKEUPENABLE............................................................................................
Register Call Summary for Register MCSPI_WAKEUPENABLE ................................................
1867
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
110
List of Tables
1867
1868
1868
1868
1868
1868
1869
1869
1870
1878
1879
1879
1880
1884
1885
1885
1886
1887
1887
1894
1894
1895
1900
1907
1911
1924
1933
1933
1934
1935
1936
1936
1937
1937
1937
1938
1939
1939
1939
1942
1942
1944
1944
1944
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
16-36. MCSPI_SYST ...........................................................................................................
1945
...............................................................
1946
16-38. MCSPI_MODULCTRL .................................................................................................
1946
16-39. Register Call Summary for Register MCSPI_MODULCTRL ......................................................
1947
16-37. Register Call Summary for Register MCSPI_SYST
16-40. MCSPI_CHxCONF .....................................................................................................
1947
16-41. Register Call Summary for Register MCSPI_CHxCONF..........................................................
1950
16-42. MCSPI_CHxSTAT ......................................................................................................
1951
16-43. Register Call Summary for Register MCSPI_CHxSTAT ..........................................................
1952
16-44. MCSPI_CHxCTRL ......................................................................................................
1952
16-45. Register Call Summary for Register MCSPI_CHxCTRL ..........................................................
1953
16-46. MCSPI_TXx .............................................................................................................
1953
16-47. Register Call Summary for Register MCSPI_TXx ..................................................................
1954
16-48. MCSPI_RXx .............................................................................................................
1954
.................................................................
MCSPI_XFERLEVEL ..................................................................................................
I/O Description ..........................................................................................................
HDQ/1-Wire Command Byte ..........................................................................................
Registers Print for HDQ/1-Wire Configuration ......................................................................
Registers Print for HDQ/1-Wire Software Reset ...................................................................
Registers Print for HDQ/1-Wire Interrupts Enable .................................................................
Instance Summary .....................................................................................................
HDQ/1-Wire Register Summary ......................................................................................
HDQ_REVISION........................................................................................................
Register Call Summary for Register HDQ_REVISION ............................................................
HDQ_TX_DATA ........................................................................................................
Register Call Summary for Register HDQ_TX_DATA .............................................................
HDQ_RX_DATA ........................................................................................................
Register Call Summary for Register HDQ_RX_DATA.............................................................
HDQ_CTRL_STATUS .................................................................................................
Register Call Summary for Register HDQ_CTRL_STATUS ......................................................
HDQ_INT_STATUS ....................................................................................................
Register Call Summary for Register HDQ_INT_STATUS.........................................................
HDQ_SYSCONFIG.....................................................................................................
Register Call Summary for Register HDQ_SYSCONFIG .........................................................
HDQ_SYSSTATUS ....................................................................................................
Register Call Summary for Register HDQ_SYSSTATUS .........................................................
Functions Description ..................................................................................................
Input/Output Description ...............................................................................................
Clocking Signals Input to McBSP Module ...........................................................................
Software Reset Signals to All McBSP Modules ....................................................................
State of Clocks When the Module is in Idle State ..................................................................
McBSP Smart Idle Mode Configuration Behavior ..................................................................
McBSP DMA Requests ................................................................................................
McBSP Common Interrupt Requests ................................................................................
McBSP Transmit Interrupt Requests .................................................................................
McBSP Receive Interrupt Requests .................................................................................
McBSP Transmit Interrupt Events ....................................................................................
McBSP Receive Interrupt Events ....................................................................................
SIDETONE_McBSP Interrupt Requests .............................................................................
1955
16-49. Register Call Summary for Register MCSPI_RXx
16-50.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
1955
1959
1961
1974
1975
1976
1977
1977
1978
1978
1978
1978
1979
1979
1979
1980
1980
1981
1981
1982
1982
1982
1987
1988
2001
2007
2008
2011
2013
2013
2014
2014
2014
2015
2015
111
www.ti.com
18-14. SIDETONE_McBSP Interrupt Events ................................................................................
18-15. Receiver Clock Mode ..................................................................................................
2022
18-16. Phases, Words and Bits per Frame Control Bit ....................................................................
2026
18-17. Assumptions for the Single-Phase Frame Example ...............................................................
2026
18-18. Assumptions for the Dual-Phase Frame Example .................................................................
2027
18-19. Effects of DLB and ALB Bits on Clock Modes ......................................................................
2033
....................................................
2043
18-21. Eight Partitions – Transmit Channel Assignment and Control....................................................
2043
.................................
McBSP Channel Control Options ....................................................................................
McBSP Configuration in Function of the SRG Clock Source Selected..........................................
Input Clock Selection for Sample Rate Generator .................................................................
How to Calculate the Length of the Receive Frame ...............................................................
Example: Use of RJUST Bit Field With 12-bit Data Value 0xABC ...............................................
Example: Use of RJUST Bit Field With 20-bit Data Value 0xABCDE ...........................................
FSRM and GSYNC Effects on Frame-Sync Signal and mcbsp_fsr Pin .........................................
CLKRM Effect on Receive Clock Signal and mcbsp_clkr Pin ....................................................
How to Calculate the Length of the Transmit Frame ..............................................................
How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses ...................................
CLKXM Bit Effect on Transmit Clock and MCBSPLP.CLKX Pin .................................................
Using McBSP Pins for General-Purpose I/O .......................................................................
Selection of the SIDETONE Input and Output Channels .........................................................
Device Instance Summary ............................................................................................
McBSP1 Registers Mapping Summary ..............................................................................
McBSP5 Registers Mapping Summary ..............................................................................
McBSP2 Registers Mapping Summary ..............................................................................
McBSP3 Registers Mapping Summary ..............................................................................
McBSP4 Registers Mapping Summary ..............................................................................
SIDETONE_McBSP2 Registers Mapping Summary ..............................................................
SIDETONE_McBSP3 Registers Mapping Summary ..............................................................
MCBSPLP_DRR_REG ................................................................................................
Register Call Summary for Register MCBSPLP_DRR_REG .....................................................
MCBSPLP_DXR_REG.................................................................................................
Register Call Summary for Register MCBSPLP_DXR_REG .....................................................
MCBSPLP_SPCR2_REG .............................................................................................
Register Call Summary for Register MCBSPLP_SPCR2_REG ..................................................
MCBSPLP_SPCR1_REG .............................................................................................
Register Call Summary for Register MCBSPLP_SPCR1_REG ..................................................
MCBSPLP_RCR2_REG ...............................................................................................
Register Call Summary for Register MCBSPLP_RCR2_REG ...................................................
MCBSPLP_RCR1_REG ...............................................................................................
Register Call Summary for Register MCBSPLP_RCR1_REG ...................................................
MCBSPLP_XCR2_REG ...............................................................................................
Register Call Summary for Register MCBSPLP_XCR2_REG....................................................
MCBSPLP_XCR1_REG ...............................................................................................
Register Call Summary for Register MCBSPLP_XCR1_REG....................................................
MCBSPLP_SRGR2_REG .............................................................................................
Register Call Summary for Register MCBSPLP_SRGR2_REG .................................................
MCBSPLP_SRGR1_REG .............................................................................................
2045
18-20. Eight Partitions – Receive Channel Assignment and Control
18-22. Selecting a Transmit Multichannel Selection Mode With the XMCM Bit Field
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
112
2016
List of Tables
2046
2056
2059
2065
2066
2066
2067
2069
2073
2075
2076
2078
2081
2082
2082
2083
2084
2085
2086
2087
2088
2088
2088
2089
2089
2089
2091
2091
2092
2093
2094
2094
2095
2096
2097
2097
2098
2098
2099
2100
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
.................................................
18-64. MCBSPLP_MCR2_REG...............................................................................................
18-65. Register Call Summary for Register MCBSPLP_MCR2_REG ...................................................
18-66. MCBSPLP_MCR1_REG...............................................................................................
18-67. Register Call Summary for Register MCBSPLP_MCR1_REG ...................................................
18-68. MCBSPLP_RCERA_REG .............................................................................................
18-69. Register Call Summary for Register MCBSPLP_RCERA_REG .................................................
18-70. MCBSPLP_RCERB_REG .............................................................................................
18-71. Register Call Summary for Register MCBSPLP_RCERB_REG .................................................
18-72. MCBSPLP_XCERA_REG .............................................................................................
18-73. Register Call Summary for Register MCBSPLP_XCERA_REG .................................................
18-74. MCBSPLP_XCERB_REG .............................................................................................
18-75. Register Call Summary for Register MCBSPLP_XCERB_REG .................................................
18-76. MCBSPLP_PCR_REG.................................................................................................
18-77. Register Call Summary for Register MCBSPLP_PCR_REG .....................................................
18-78. MCBSPLP_RCERC_REG .............................................................................................
18-79. Register Call Summary for Register MCBSPLP_RCERC_REG .................................................
18-80. MCBSPLP_RCERD_REG .............................................................................................
18-81. Register Call Summary for Register MCBSPLP_RCERD_REG .................................................
18-82. MCBSPLP_XCERC_REG .............................................................................................
18-83. Register Call Summary for Register MCBSPLP_XCERC_REG .................................................
18-84. MCBSPLP_XCERD_REG .............................................................................................
18-85. Register Call Summary for Register MCBSPLP_XCERD_REG .................................................
18-86. MCBSPLP_RCERE_REG .............................................................................................
18-87. Register Call Summary for Register MCBSPLP_RCERE_REG .................................................
18-88. MCBSPLP_RCERF_REG .............................................................................................
18-89. Register Call Summary for Register MCBSPLP_RCERF_REG .................................................
18-90. MCBSPLP_XCERE_REG .............................................................................................
18-91. Register Call Summary for Register MCBSPLP_XCERE_REG .................................................
18-92. MCBSPLP_XCERF_REG .............................................................................................
18-93. Register Call Summary for Register MCBSPLP_XCERF_REG ..................................................
18-94. MCBSPLP_RCERG_REG ............................................................................................
18-95. Register Call Summary for Register MCBSPLP_RCERG_REG .................................................
18-96. MCBSPLP_RCERH_REG .............................................................................................
18-97. Register Call Summary for Register MCBSPLP_RCERH_REG .................................................
18-98. MCBSPLP_XCERG_REG .............................................................................................
18-99. Register Call Summary for Register MCBSPLP_XCERG_REG .................................................
18-100. MCBSPLP_XCERH_REG ...........................................................................................
18-101. Register Call Summary for Register MCBSPLP_XCERH_REG ................................................
18-102. MCBSPLP_REV_REG ...............................................................................................
18-103. Register Call Summary for Register MCBSPLP_REV_REG ....................................................
18-104. MCBSPLP_RINTCLR_REG .........................................................................................
18-105. Register Call Summary for Register MCBSPLP_RINTCLR_REG ..............................................
18-106. MCBSPLP_XINTCLR_REG .........................................................................................
18-107. Register Call Summary for Register MCBSPLP_XINTCLR_REG ..............................................
18-108. MCBSPLP_ROVFLCLR_REG ......................................................................................
18-109. Register Call Summary for Register MCBSPLP_ROVFLCLR_REG ...........................................
18-110. MCBSPLP_SYSCONFIG_REG .....................................................................................
18-111. Register Call Summary for Register MCBSPLP_SYSCONFIG_REG .........................................
18-63. Register Call Summary for Register MCBSPLP_SRGR1_REG
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
2100
2101
2102
2103
2104
2104
2105
2105
2105
2106
2106
2106
2107
2107
2109
2110
2110
2111
2111
2111
2112
2112
2112
2113
2113
2113
2114
2114
2114
2115
2115
2115
2116
2116
2116
2117
2117
2117
2118
2118
2118
2119
2119
2119
2120
2120
2120
2121
2122
113
www.ti.com
18-112. MCBSPLP_THRSH2_REG ..........................................................................................
2122
18-113. Register Call Summary for Register MCBSPLP_THRSH2_REG...............................................
2122
18-114. MCBSPLP_THRSH1_REG ..........................................................................................
2123
18-115. Register Call Summary for Register MCBSPLP_THRSH1_REG...............................................
2123
.....................................................................................
2123
18-117. Register Call Summary for Register MCBSPLP_IRQSTATUS_REG ..........................................
2125
.....................................................................................
2126
18-116. MCBSPLP_IRQSTATUS_REG
18-118. MCBSPLP_IRQENABLE_REG
18-119. Register Call Summary for Register MCBSPLP_IRQENABLE_REG ..........................................
2127
.....................................................................................
18-121. Register Call Summary for Register MCBSPLP_WAKEUPEN_REG ..........................................
18-122. MCBSPLP_XCCR_REG .............................................................................................
18-123. Register Call Summary for Register MCBSPLP_XCCR_REG ..................................................
18-124. MCBSPLP_RCCR_REG .............................................................................................
18-125. Register Call Summary for Register MCBSPLP_RCCR_REG..................................................
18-126. MCBSPLP_XBUFFSTAT_REG .....................................................................................
18-127. Register Call Summary for Register MCBSPLP_XBUFFSTAT_REG ..........................................
18-128. MCBSPLP_RBUFFSTAT_REG .....................................................................................
18-129. Register Call Summary for Register MCBSPLP_RBUFFSTAT_REG .........................................
18-130. MCBSPLP_SSELCR_REG ..........................................................................................
18-131. Register Call Summary for Register MCBSPLP_SSELCR_REG...............................................
18-132. MCBSPLP_STATUS_REG ..........................................................................................
18-133. Register Call Summary for Register MCBSPLP_STATUS_REG ...............................................
18-134. ST_REV_REG .........................................................................................................
18-135. Register Call Summary for Register ST_REV_REG .............................................................
18-136. ST_SYSCONFIG_REG ..............................................................................................
18-137. Register Call Summary for Register ST_SYSCONFIG_REG ...................................................
18-138. ST_IRQSTATUS_REG ...............................................................................................
18-139. Register Call Summary for Register ST_IRQSTATUS_REG ...................................................
18-140. ST_IRQENABLE_REG ...............................................................................................
18-141. Register Call Summary for Register ST_IRQENABLE_REG ...................................................
18-142. ST_SGAINCR_REG ..................................................................................................
18-143. Register Call Summary for Register ST_SGAINCR_REG.......................................................
18-144. ST_SFIRCR_REG ....................................................................................................
18-145. Register Call Summary for Register ST_SFIRCR_REG .........................................................
18-146. ST_SSELCR_REG ...................................................................................................
18-147. Register Call Summary for Register ST_SSELCR_REG ........................................................
19-1. MMC/SD/SDIOi I/O Description ......................................................................................
19-2. MMC/SD/SDIO2 I/O Description .....................................................................................
19-3. Relation Between Configuration and Name of Response Type .................................................
19-4. Smart Idle Mode and Wake-Up Capabilities ........................................................................
19-5. MMC, SD, SDIO responses in the MMCHS_RSPxx registers ...................................................
19-6. CC and TC Values Upon Error Detected ............................................................................
19-7. MMC/SD/SDIOi Controller Transfer Stop Command Summary ..................................................
19-8. Register Print for the MMCHS1 controller's clocks Initialization..................................................
19-9. MMCHS Controller Voltage Capabilities Initialization ..............................................................
19-10. MMC Controller Default Initialization Values ........................................................................
19-11. MMCHS Controller INIT Procedure Start ............................................................................
19-12. MMCHS Controller Pre-Card Identification Configuration .........................................................
19-13. Sending CMD0 ..........................................................................................................
2128
18-120. MCBSPLP_WAKEUPEN_REG
114
List of Tables
2129
2129
2131
2131
2132
2132
2133
2133
2133
2134
2134
2135
2135
2136
2136
2136
2136
2137
2137
2137
2138
2138
2138
2138
2139
2139
2140
2146
2147
2151
2155
2167
2167
2168
2187
2188
2188
2189
2189
2189
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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19-14. Sending CMD5 ..........................................................................................................
2190
19-15. Sending CMD8 ..........................................................................................................
2190
19-16. Sending CMD55 ........................................................................................................
2190
19-17. Sending CMD1 ..........................................................................................................
2191
19-18. Sending CMD2 ..........................................................................................................
2191
19-19. Sending CMD3 ..........................................................................................................
2191
19-20. MMC Bus Setting Change Table .....................................................................................
2192
19-21. Sending CMD9 ..........................................................................................................
2192
19-22. MMCHS_SYSCTL Value ..............................................................................................
2193
19-23. Sending CMD7 ..........................................................................................................
2193
19-24. Setting Data Bus Width with CMD6 ..................................................................................
2194
19-25. MMCHS_CON Value...................................................................................................
2194
....................................................................................
MMCHS_SYSCTL Value ..............................................................................................
Setting Block Length ...................................................................................................
Setting Number of Blocks .............................................................................................
CMD25 Issuing .........................................................................................................
CMD18 Issuing .........................................................................................................
Instance Summary .....................................................................................................
MMC/SD/SDIO1 Register Summary .................................................................................
MMCHS_SYSCONFIG ................................................................................................
Register Call Summary for Register MMCHS_SYSCONFIG .....................................................
MMCHS_SYSSTATUS ................................................................................................
Register Call Summary for Register MMCHS_SYSSTATUS .....................................................
MMCHS_CSRE .........................................................................................................
Register Call Summary for Register MMCHS_CSRE .............................................................
MMCHS_SYSTEST ....................................................................................................
Register Call Summary for Register MMCHS_SYSTEST.........................................................
MMCHS_CON ..........................................................................................................
Register Call Summary for Register MMCHS_CON ...............................................................
MMCHS_PWCNT ......................................................................................................
Register Call Summary for Register MMCHS_PWCNT ...........................................................
MMCHS_BLK ...........................................................................................................
Register Call Summary for Register MMCHS_BLK ................................................................
MMCHS_ARG ..........................................................................................................
Register Call Summary for Register MMCHS_ARG ...............................................................
MMCHS_CMD ..........................................................................................................
Register Call Summary for Register MMCHS_CMD ...............................................................
MMCHS_RSP10 ........................................................................................................
Register Call Summary for Register MMCHS_RSP10 ............................................................
MMCHS_RSP32 ........................................................................................................
Register Call Summary for Register MMCHS_RSP32 ............................................................
MMCHS_RSP54 ........................................................................................................
Register Call Summary for Register MMCHS_RSP54 ............................................................
MMCHS_RSP76 ........................................................................................................
Register Call Summary for Register MMCHS_RSP76 ............................................................
MMCHS_DATA .........................................................................................................
Register Call Summary for Register MMCHS_DATA ..............................................................
MMCHS_PSTATE ......................................................................................................
19-26. Enabling High Speed with CMD6
2194
19-27.
2195
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
2195
2195
2196
2197
2198
2198
2199
2200
2200
2200
2201
2201
2201
2205
2205
2208
2209
2209
2209
2210
2211
2211
2211
2213
2213
2214
2214
2214
2214
2215
2215
2215
2216
2216
2216
115
www.ti.com
19-63. Register Call Summary for Register MMCHS_PSTATE ..........................................................
2218
19-64. MMCHS_HCTL .........................................................................................................
2218
19-65. Register Call Summary for Register MMCHS_HCTL ..............................................................
2220
19-66. MMCHS_SYSCTL ......................................................................................................
2221
19-67. Register Call Summary for Register MMCHS_SYSCTL ..........................................................
2222
.........................................................................................................
Register Call Summary for Register MMCHS_STAT ..............................................................
MMCHS_IE ..............................................................................................................
Register Call Summary for Register MMCHS_IE ..................................................................
MMCHS_ISE ............................................................................................................
Register Call Summary for Register MMCHS_ISE ................................................................
MMCHS_AC12..........................................................................................................
Register Call Summary for Register MMCHS_AC12 ..............................................................
MMCHS_CAPA .........................................................................................................
Register Call Summary for Register MMCHS_CAPA .............................................................
MMCHS_CUR_CAPA..................................................................................................
Register Call Summary for Register MMCHS_CUR_CAPA ......................................................
MMCHS_REV ...........................................................................................................
Register Call Summary for Register MMCHS_REV ...............................................................
TX Channel Allocation .................................................................................................
RX Channel Allocation .................................................................................................
Queue Allocation .......................................................................................................
CPU Interrupts ..........................................................................................................
TX Endpoint Interrupts .................................................................................................
RX Endpoint Interrupts.................................................................................................
USB Interrupts ..........................................................................................................
External Pin Information ...............................................................................................
Universal Serial Bus (USB) Registers ...............................................................................
USB Control Register Field Descriptions ............................................................................
USB Status Register Field Descriptions .............................................................................
USB Auto Req Register Field Descriptions .........................................................................
USB Teardown Register Field Descriptions ........................................................................
USB Endpoint Interrupt Source Register Field Descriptions......................................................
USB Endpoint Interrupt Source Set Register Field Descriptions .................................................
USB Endpoint Interrupt Source Clear Register Field Descriptions ..............................................
USB Endpoint Interrupt Mask Register Field Descriptions ........................................................
USB Endpoint Interrupt Mask Set Register Field Descriptions ...................................................
USB Endpoint Interrupt Mask Clear Register Field Descriptions ................................................
USB Endpoint Interrupt Source Masked Register Field Descriptions ...........................................
USB Core Interrupt Source Register Field Descriptions ..........................................................
USB Core Interrupt Source Set Register Field Descriptions......................................................
USB Core Interrupt Source Clear Register Field Descriptions ...................................................
USB Core Interrupt Mask Register Field Descriptions ............................................................
USB Core Interrupt Mask Set Register Field Descriptions ........................................................
USB Core Interrupt Mask Clear Register Field Descriptions .....................................................
USB Core Interrupt Source Masked Register Field Descriptions ................................................
USB End of Interrupt Register Field Descriptions ..................................................................
USB MOP/SOP Interrupt Enable Register Field Descriptions ....................................................
USB Tx Mode Register Field Descriptions ..........................................................................
2223
19-68. MMCHS_STAT
19-69.
19-70.
19-71.
19-72.
19-73.
19-74.
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
116
List of Tables
2226
2227
2228
2229
2230
2231
2231
2232
2233
2234
2234
2235
2235
2240
2241
2243
2247
2247
2248
2248
2250
2253
2256
2257
2258
2261
2262
2262
2263
2263
2264
2264
2265
2265
2266
2266
2267
2267
2268
2268
2269
2269
2270
SPRUGR0C – October 2009 – Revised November 2013
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www.ti.com
20-31. USB Rx Mode Register Field Descriptions..........................................................................
2272
20-32. USB EP Count Mode Register Field Descriptions .................................................................
2274
20-33. USB Generic RNDIS EP N Size Register Field Descriptions.....................................................
2276
20-34. USB Queue Interrupt Threshold Enable Register Field Descriptions
2276
20-35.
...........................................
USB Queue Threshold Register 0 Field Descriptions .............................................................
USB Interrupt Clear Register 0 Field Descriptions .................................................................
USB Queue Threshold Register 1 Field Descriptions .............................................................
USB Interrupt Clear Register 1 Field Descriptions .................................................................
CDMA Tx Channel N Global Configuration Register Field Descriptions ........................................
CDMA Rx Channel N Global Configuration Register Field Descriptions ........................................
CDMA Rx Channel N Host Packet Configuration Register A Field Descriptions ..............................
CDMA Rx Channel N Host Packet Configuration Register B Field Descriptions ..............................
CDMA Scheduler Control Register Field Descriptions ............................................................
CDMA Scheduler Table Word N Registers Field Descriptions ...................................................
INTD Revision Register Field Descriptions .........................................................................
INTD EOI Register Field Descriptions ...............................................................................
INTD EOI Interrupt Vector Register ..................................................................................
INTD Status Register 0 Field Descriptions ..........................................................................
INTD Status Register 1 Field Descriptions ..........................................................................
INTD Status Register 2 Field Descriptions ..........................................................................
INTD Status Register 3 Field Descriptions ..........................................................................
INTD Status Clear Register 0 Field Descriptions ..................................................................
Queue Manager Revision Register ..................................................................................
Queue Manager Queue Diversion Register Field Descriptions ..................................................
Queue Manager Free Descriptor/Buffer Starvation Count Register 0 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 1 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 2 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 3 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 4 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 5 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 6 Field Descriptions.....................
Queue Manager Free Descriptor/Buffer Starvation Count Register 7 Field Descriptions.....................
Queue Manager Linking RAM Region 0 Base Address Register Field Descriptions ..........................
Queue Manager Linking RAM Region 0 Size Register Field Descriptions .....................................
Queue Manager Linking RAM Region 1 Base Address Register Field Descriptions ..........................
Queue Manager Queue Pending Register 0 Field Descriptions .................................................
Queue Manager Queue Pending Register 1 Field Descriptions .................................................
Queue Manager Queue Pending Register 2 Field Descriptions .................................................
Queue Manager Memory Region R Base Address Register Field Descriptions ...............................
Queue Manager Memory Region R Control Register Field Descriptions .......................................
Queue Manager Queue N Register A Field Descriptions .........................................................
Queue Manager Queue N Register B Field Descriptions .........................................................
Queue Manager Queue N Register C Field Descriptions .........................................................
Queue Manager Queue N Register D Field Descriptions .........................................................
Queue Manager Queue N Status Register A Field Descriptions.................................................
Queue Manager Queue N Status Register B Field Descriptions.................................................
Queue Manager Queue N Status Register C Field Descriptions ................................................
USB Connectivity Modes ..............................................................................................
I/O Description ..........................................................................................................
2277
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
2277
2278
2278
2279
2280
2282
2283
2284
2285
2287
2288
2289
2290
2291
2292
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2308
2309
2309
2310
2310
2311
2312
2313
2313
2314
2314
2315
2315
2319
2327
117
www.ti.com
20-80. Signaling Between High-Speed USB Host Subsystem and 6-Pin Unidirectional USB Transceiver
(DAT/SE0 Signaling) ...................................................................................................
2330
20-81. Signaling Between High-Speed USB Host Subsystem and 6-Pin Unidirectional USB Transceiver (DP/DM
Signaling) ................................................................................................................ 2330
20-82. Signaling Between High-Speed USB Host Subsystem and 3-Pin Bidirectional USB Transceiver Using
DAT/SE0 Signaling .....................................................................................................
2331
20-83. Signaling Between High-Speed USB Host Subsystem and 4-Pin Bidirectional USB Transceiver Using
DP/DM Signaling .......................................................................................................
2332
..............................................................
2339
20-85. Pullup/Pulldown Configuration for DAT/SE0 Encoding ............................................................
2340
20-84. Pullup/Pulldown Configuration for DP/DM Encoding
20-86. I/O Description ..........................................................................................................
2340
20-87. High-Speed USB Host Subsystem Reset Description .............................................................
2344
20-88. High-Speed USB Host Subsystem Clocks ..........................................................................
2345
20-89. High-Speed USB Controller L3 Master Interface Clock ...........................................................
2346
20-90. USBTLL Module Interface Clock .....................................................................................
2346
.....................................................
2347
20-92. High-Speed USB Host Controller MIDLEMODE Settings .........................................................
2348
20-93. High-Speed USB Host Controller SIDLEMODE Settings .........................................................
2348
20-94. High-Speed USB Host Controller CLOCKACTIVITY Settings ....................................................
2349
20-95. USBTLL Module PRCM Clock Control Bits .........................................................................
2349
20-96. USBTLL Module SIDLEMODE Settings .............................................................................
2350
20-97. USBTLL Module CLOCKACTIVITY Settings .......................................................................
2350
20-98. High-Speed USB Host Subsystem Interrupts .......................................................................
2351
20-91. High-Speed USB Host Controller PRCM Clock Control Bits
.........................................................................................
2355
20-100. USBTLL Channel Configuration .....................................................................................
2357
20-101. VBUS Level Software Reporting for Serial Transceiver Configuration .........................................
2359
20-99. USBTLL Channel USB Ports
2360
20-103.
2361
20-104.
20-105.
20-106.
20-107.
20-108.
20-109.
20-110.
20-111.
20-112.
20-113.
20-114.
20-115.
20-116.
20-117.
20-118.
20-119.
20-120.
20-121.
20-122.
20-123.
20-124.
20-125.
118
........................................................
Serial Mode Description, Signal Functionality .....................................................................
Pullup Enable Emulation in Serial TLL Modes ....................................................................
USBTLL Registers Impacted by the SAR Context ................................................................
USB Connectivity Mode Description ................................................................................
ULPI Register Mapping Summary (For a Single ULPI Port) ....................................................
Instance Summary ....................................................................................................
USBTLL Register Mapping Summary (L4-Core Interconnect Register Space) ...............................
UHH_CONFIG Register Mapping Summary ......................................................................
OHCI Register Mapping Summary .................................................................................
EHCI Register Mapping Summary ..................................................................................
USBTLL_REVISION ..................................................................................................
USBTLL_SYSCONFIG ...............................................................................................
USBTLL_SYSSTATUS ...............................................................................................
USBTLL_IRQSTATUS ...............................................................................................
USBTLL_IRQENABLE ...............................................................................................
TLL_SHARED_CONF ................................................................................................
TLL_CHANNEL_CONF_i ............................................................................................
ULPI_VENDOR_ID_LO_i ............................................................................................
ULPI_VENDOR_ID_HI_i .............................................................................................
ULPI_PRODUCT_ID_LO_i ..........................................................................................
ULPI_PRODUCT_ID_HI_i ...........................................................................................
ULPI_FUNCTION_CTRL_i ..........................................................................................
ULPI_FUNCTION_CTRL_SET_i ....................................................................................
20-102. Emulation of VBUS Levels for UTMI-to-ULPI TLL Mode
List of Tables
2362
2363
2366
2367
2368
2369
2371
2371
2372
2373
2374
2375
2376
2377
2378
2379
2382
2382
2383
2383
2384
2385
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
20-126. ULPI_FUNCTION_CTRL_CLR_i ....................................................................................
2385
20-127. ULPI_INTERFACE_CTRL_i .........................................................................................
2386
20-128. ULPI_INTERFACE_CTRL_SET_i
2387
20-129.
..................................................................................
ULPI_INTERFACE_CTRL_CLR_i ..................................................................................
ULPI_OTG_CTRL_i ...................................................................................................
ULPI_OTG_CTRL_SET_i ............................................................................................
ULPI_OTG_CTRL_CLR_i ............................................................................................
ULPI_USB_INT_EN_RISE_i.........................................................................................
ULPI_USB_INT_EN_RISE_SET_i ..................................................................................
ULPI_USB_INT_EN_RISE_CLR_i ..................................................................................
ULPI_USB_INT_EN_FALL_i ........................................................................................
ULPI_USB_INT_EN_FALL_SET_i ..................................................................................
ULPI_USB_INT_EN_FALL_CLR_i .................................................................................
ULPI_USB_INT_STATUS_i .........................................................................................
ULPI_USB_INT_LATCH_i ...........................................................................................
ULPI_DEBUG_i .......................................................................................................
ULPI_SCRATCH_REGISTER_i .....................................................................................
ULPI_SCRATCH_REGISTER_SET_i ..............................................................................
ULPI_SCRATCH_REGISTER_CLR_i ..............................................................................
ULPI_EXTENDED_SET_ACCESS_i ...............................................................................
ULPI_UTMI_VCONTROL_EN_i .....................................................................................
ULPI_UTMI_VCONTROL_EN_SET_i ..............................................................................
ULPI_UTMI_VCONTROL_EN_CLR_i ..............................................................................
ULPI_UTMI_VCONTROL_STATUS_i ..............................................................................
ULPI_UTMI_VCONTROL_LATCH_i................................................................................
ULPI_UTMI_VSTATUS_i ............................................................................................
ULPI_UTMI_VSTATUS_SET_i ......................................................................................
ULPI_UTMI_VSTATUS_CLR_i......................................................................................
ULPI_USB_INT_LATCH_NOCLR_i ................................................................................
ULPI_VENDOR_INT_EN_i ..........................................................................................
ULPI_VENDOR_INT_EN_SET_i ....................................................................................
ULPI_VENDOR_INT_EN_CLR_i ...................................................................................
ULPI_VENDOR_INT_STATUS_i ...................................................................................
ULPI_VENDOR_INT_LATCH_i .....................................................................................
UHH_REVISION ......................................................................................................
UHH_SYSCONFIG ...................................................................................................
UHH_SYSSTATUS ...................................................................................................
UHH_HOSTCONFIG .................................................................................................
UHH_DEBUG_CSR ..................................................................................................
HCREVISION ..........................................................................................................
HCCONTROL .........................................................................................................
HCCOMMANDSTATUS ..............................................................................................
HCINTERRUPTSTATUS .............................................................................................
HCINTERRUPTENABLE .............................................................................................
HCINTERRUPTDISABLE ............................................................................................
HCHCCA ...............................................................................................................
HCPERIODCURRENTED ...........................................................................................
HCCONTROLHEADED ..............................................................................................
HCCONTROLCURRENTED.........................................................................................
2387
20-130.
20-131.
20-132.
20-133.
20-134.
20-135.
20-136.
20-137.
20-138.
20-139.
20-140.
20-141.
20-142.
20-143.
20-144.
20-145.
20-146.
20-147.
20-148.
20-149.
20-150.
20-151.
20-152.
20-153.
20-154.
20-155.
20-156.
20-157.
20-158.
20-159.
20-160.
20-161.
20-162.
20-163.
20-164.
20-165.
20-166.
20-167.
20-168.
20-169.
20-170.
20-171.
20-172.
20-173.
20-174.
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
2388
2389
2389
2390
2391
2391
2392
2393
2393
2394
2395
2396
2396
2397
2397
2397
2398
2398
2399
2399
2400
2400
2401
2401
2402
2402
2403
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2417
2418
2418
2419
2419
119
www.ti.com
....................................................................................................
20-176. HCBULKCURRENTED ...............................................................................................
20-177. HCDONEHEAD .......................................................................................................
20-178. HCFMINTERVAL ......................................................................................................
20-179. HCFMREMAINING ...................................................................................................
20-180. HCFMNUMBER .......................................................................................................
20-181. HCPERIODICSTART .................................................................................................
20-182. HCLSTHRESHOLD ...................................................................................................
20-183. HCRHDESCRIPTORA ...............................................................................................
20-184. HCRHDESCRIPTORB ...............................................................................................
20-185. HCRHSTATUS ........................................................................................................
20-186. HCRHPORTSTATUS_1 ..............................................................................................
20-187. HCRHPORTSTATUS_2 ..............................................................................................
20-188. HCRHPORTSTATUS_3 ..............................................................................................
20-189. HCCAPBASE ..........................................................................................................
20-190. HCSPARAMS .........................................................................................................
20-191. HCCPARAMS .........................................................................................................
20-192. USBCMD ...............................................................................................................
20-193. USBSTS ................................................................................................................
20-194. USBINTR ...............................................................................................................
20-195. FRINDEX ...............................................................................................................
20-196. CTRLDSSEGMENT ..................................................................................................
20-197. PERIODICLISTBASE .................................................................................................
20-198. ASYNCLISTADDR ....................................................................................................
20-199. CONFIGFLAG .........................................................................................................
20-200. PORTSC_i .............................................................................................................
20-201. INSNREG00 ...........................................................................................................
20-202. INSNREG01 ...........................................................................................................
20-203. INSNREG02 ...........................................................................................................
20-204. INSNREG03 ...........................................................................................................
20-205. INSNREG04 ...........................................................................................................
20-206. INSNREG05_UTMI ...................................................................................................
20-207. INSNREG05_ULPI ....................................................................................................
21-1. I/O Pin Description .....................................................................................................
21-2. Clocks ....................................................................................................................
21-3. Interrupts.................................................................................................................
21-4. Wake-Up Signals .......................................................................................................
21-5. GPIO Channel Description ............................................................................................
21-6. Instance Summary .....................................................................................................
21-7. GPIO1 to GPIO3 Register Summary ................................................................................
21-8. GPIO4 to GPIO6 Register Summary ................................................................................
21-9. GPIO_REVISION .......................................................................................................
21-10. Register Call Summary for Register GPIO_REVISION ...........................................................
21-11. GPIO_SYSCONFIG ....................................................................................................
21-12. Register Call Summary for Register GPIO_SYSCONFIG ........................................................
21-13. GPIO_SYSSTATUS ....................................................................................................
21-14. Register Call Summary for Register GPIO_SYSSTATUS ........................................................
21-15. GPIO_IRQSTATUS1 ...................................................................................................
21-16. Register Call Summary for Register GPIO_IRQSTATUS1 .......................................................
20-175. HCBULKHEADED
120
List of Tables
2420
2420
2421
2421
2422
2422
2423
2423
2424
2425
2426
2427
2429
2431
2433
2434
2435
2436
2438
2440
2441
2441
2442
2442
2443
2444
2447
2447
2448
2448
2449
2450
2451
2457
2459
2462
2463
2463
2475
2475
2476
2477
2477
2477
2478
2478
2479
2479
2479
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
www.ti.com
21-17. GPIO_IRQENABLE1 ...................................................................................................
2480
21-18. Register Call Summary for Register GPIO_IRQENABLE1 .......................................................
2480
21-19. GPIO_WAKEUPENABLE
2480
21-20.
.............................................................................................
Register Call Summary for Register GPIO_WAKEUPENABLE ..................................................
GPIO_IRQSTATUS2 ...................................................................................................
Register Call Summary for Register GPIO_IRQSTATUS2 .......................................................
GPIO_IRQENABLE2 ...................................................................................................
Register Call Summary for Register GPIO_IRQENABLE2 .......................................................
GPIO_CTRL .............................................................................................................
Register Call Summary for Register GPIO_CTRL .................................................................
GPIO_OE ................................................................................................................
Register Call Summary for Register GPIO_OE ....................................................................
GPIO_DATAIN ..........................................................................................................
Register Call Summary for Register GPIO_DATAIN ..............................................................
GPIO_DATAOUT .......................................................................................................
Register Call Summary for Register GPIO_DATAOUT ...........................................................
GPIO_LEVELDETECT0 ...............................................................................................
Register Call Summary for Register GPIO_LEVELDETECT0....................................................
GPIO_LEVELDETECT1 ...............................................................................................
Register Call Summary for Register GPIO_LEVELDETECT1....................................................
GPIO_RISINGDETECT ................................................................................................
Register Call Summary for Register GPIO_RISINGDETECT ....................................................
GPIO_FALLINGDETECT ..............................................................................................
Register Call Summary for Register GPIO_FALLINGDETECT ..................................................
GPIO_DEBOUNCENABLE............................................................................................
Register Call Summary for Register GPIO_DEBOUNCENABLE ................................................
GPIO_DEBOUNCINGTIME ...........................................................................................
Register Call Summary for Register GPIO_DEBOUNCINGTIME................................................
GPIO_CLEARIRQENABLE1 ..........................................................................................
Register Call Summary for Register GPIO_CLEARIRQENABLE1 ..............................................
GPIO_SETIRQENABLE1..............................................................................................
Register Call Summary for Register GPIO_SETIRQENABLE1 ..................................................
GPIO_CLEARIRQENABLE2 ..........................................................................................
Register Call Summary for Register GPIO_CLEARIRQENABLE2 ..............................................
GPIO_SETIRQENABLE2..............................................................................................
Register Call Summary for Register GPIO_SETIRQENABLE2 ..................................................
GPIO_CLEARWKUENA ...............................................................................................
Register Call Summary for Register GPIO_CLEARWKUENA ...................................................
GPIO_SETWKUENA ...................................................................................................
Register Call Summary for Register GPIO_SETWKUENA .......................................................
GPIO_CLEARDATAOUT ..............................................................................................
Register Call Summary for Register GPIO_CLEARDATAOUT ..................................................
GPIO_SETDATAOUT..................................................................................................
Register Call Summary for Register GPIO_SETDATAOUT ......................................................
EMAC and MDIO Signals for RMII Interface........................................................................
Ethernet Frame Description ...........................................................................................
Basic Descriptor Description ..........................................................................................
Tx Buffer Descriptor Word 0 ..........................................................................................
Tx Buffer Descriptor Word 1 ..........................................................................................
2481
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
22-1.
22-2.
22-3.
22-4.
22-5.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
2481
2481
2482
2482
2483
2483
2483
2484
2484
2484
2485
2485
2485
2486
2486
2486
2486
2487
2487
2487
2487
2488
2488
2488
2489
2489
2489
2490
2490
2490
2490
2491
2491
2491
2491
2492
2492
2492
2493
2493
2497
2498
2501
2506
2506
121
www.ti.com
22-6.
Tx Buffer Descriptor Word 2 ..........................................................................................
2507
22-7.
Tx Buffer Descriptor Word 3 ..........................................................................................
2507
22-8.
Rx Buffer Descriptor Word 0 ..........................................................................................
2508
22-9.
Rx Buffer Descriptor Word 1 ..........................................................................................
2508
22-10. Rx Buffer Descriptor Word 2 ..........................................................................................
2508
22-11. Rx Buffer Descriptor Word 3 ..........................................................................................
2508
22-12. Receive Frame Treatment Summary ................................................................................
2526
22-13. Little Endian .............................................................................................................
2527
22-14. Big Endian ...............................................................................................................
2527
22-15. Middle of Frame Overrun Treatment .................................................................................
2527
22-16. Emulation Control
2540
22-17.
......................................................................................................
Emulation Control ......................................................................................................
EMAC Subsystem Registers ..........................................................................................
Revision ID Register (REVID) Field Descriptions ..................................................................
Software Reset Register (SOFTRESET) ............................................................................
Interrupt Control Register (INTCONTROL) .........................................................................
Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (CnRXTHRESHEN) ........................
Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN)................................................
Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...............................................
Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) .....................................
Interrupt Core 0-2 Receive Threshold Interrupt Status Register (CnRXTHRESHSTAT) .....................
Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .............................................
Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) .............................................
Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT) ...................................
Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) .................................
Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .................................
Management Data Input/Output (MDIO) Registers ................................................................
MDIO Revision ID Register (REVID) Field Descriptions ..........................................................
MDIO Control Register (CONTROL) Field Descriptions ..........................................................
PHY Acknowledge Status Register (ALIVE) Field Descriptions ..................................................
PHY Link Status Register (LINK) Field Descriptions ..............................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ..............
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ............
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions.....
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ...
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .
2541
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions .............................................................................................................
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2555
2556
2557
2557
2558
2559
2560
2561
2562
2563
22-43. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ...........................................
2564
22-44. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ......................................
2565
22-45. MDIO User Access Register 1 (USERACCESS1) Field Descriptions ...........................................
2566
22-46. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ......................................
2567
22-47. Ethernet Media Access Controller (EMAC) Registers .............................................................
2568
...................................................
2572
22-49. Transmit Control Register (TXCONTROL) Field Descriptions....................................................
2572
22-50. Transmit Teardown Register (TXTEARDOWN) Field Descriptions ..............................................
2573
22-51. Receive Revision ID Register (RXREVID) Field Descriptions ....................................................
2574
22-52. Receive Control Register (RXCONTROL) Field Descriptions ....................................................
2574
22-53. Receive Teardown Register (RXTEARDOWN) Field Descriptions ..............................................
2575
22-48. Transmit Revision ID Register (TXREVID) Field Descriptions
122
2542
2543
List of Tables
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22-54. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ......................
2576
22-55. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ....................
2577
22-56. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................
2578
22-57. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................
2579
22-58. MAC Input Vector Register (MACINVECTOR) Field Descriptions ...............................................
2580
22-59. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions................................
2581
......................
2582
22-61. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions .....................
2583
..................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ........................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ......................
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ....................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ..............................
2584
22-60. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
22-62. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
22-63.
22-64.
22-65.
22-66.
22-67.
22-68. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions .............................................................................................................
2585
2587
2587
2588
2588
2589
22-69. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ..................................
2592
22-70. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions .....................................
2593
22-71. Receive Maximum Length Register (RXMAXLEN) Field Descriptions ..........................................
2594
22-72. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions .....................................
2594
22-73. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ..... 2595
22-74. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............ 2595
22-75. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ....................
2596
22-76. MAC Control Register (MACCONTROL) Field Descriptions......................................................
2597
22-77. MAC Status Register (MACSTATUS) Field Descriptions .........................................................
2599
.................................................
FIFO Control Register (FIFOCONTROL) Field Descriptions .....................................................
MAC Configuration Register (MACCONFIG) Field Descriptions .................................................
Soft Reset Register (SOFTRESET) Field Descriptions ...........................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ..........................
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ..........................
MAC Hash Address Register 1 (MACHASH1) Field Descriptions ...............................................
MAC Hash Address Register 2 (MACHASH2) Field Descriptions ...............................................
Back Off Test Register (BOFFTEST) Field Descriptions ..........................................................
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................
Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................
Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................................
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions .........................................
MAC Address High Bytes Register (MACADDRHI) Field Descriptions .........................................
MAC Index Register (MACINDEX) Field Descriptions.............................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions .................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ..................
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions ................................
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ................................
Physical Layer Definitions .............................................................................................
SCC and HECC Features Overview ................................................................................
SCC Message Object Description ....................................................................................
HECC Message Object Description ..................................................................................
Message Object Types ................................................................................................
2601
22-78. Emulation Control Register (EMCONTROL) Field Descriptions
22-79.
22-80.
22-81.
22-82.
22-83.
22-84.
22-85.
22-86.
22-87.
22-88.
22-89.
22-90.
22-91.
22-92.
22-93.
22-94.
22-95.
22-96.
22-97.
23-1.
23-2.
23-3.
23-4.
SPRUGR0C – October 2009 – Revised November 2013
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List of Tables
2602
2603
2604
2605
2605
2606
2607
2608
2609
2610
2610
2611
2612
2612
2613
2613
2614
2614
2625
2626
2637
2638
2639
123
www.ti.com
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
124
.................................................................................................
Mailbox Enable Register (CANME) Field Descriptions ............................................................
Mailbox Direction Register (CANMD) Field Descriptions..........................................................
Transmission Request Set Register (CANTRS) Field Descriptions .............................................
Transmission Request Reset Register (CANTRR) Field Descriptions ..........................................
Transmission Acknowledge Register (CANTA) Field Descriptions ..............................................
Abort Acknowledge Register (CANAA) Field Descriptions ........................................................
Receive Message Pending Register (CANRMP) Field Descriptions ............................................
Receive Message Lost Register (CANRML) Field Descriptions .................................................
Remote Frame Pending Register (CANRFP) Field Descriptions ................................................
Global Acceptance Mask Register (CANGAM) Field Descriptions ..............................................
Master Control Register (CANMC) Field Descriptions ............................................................
Bits Not Changed After Software Reset .............................................................................
Bit-Timing Configuration Register (CANBTC) Field Descriptions ...............................................
Error and Status Register (CANES) Field Descriptions ..........................................................
Global Interrupt Flag Registers (CANGIF) Field Descriptions ...................................................
Global Interrupt Mask Register (CANGIM) Field Descriptions ...................................................
Mailbox Interrupt Mask Register (CANMIM) Field Descriptions ..................................................
Mailbox Interrupt Level Register (CANMIL) Field Descriptions ...................................................
Overwrite Protection Control Register (CANOPC) Field Descriptions ...........................................
Transmit I/O Control Register (CANTIOC) Field Descriptions ....................................................
Receive I/O Control Register (CANRIOC) Field Descriptions ....................................................
Local Network Time Register (CANLNT) Field Descriptions .....................................................
Message Object Time Stamp Register (CANMOTS) Field Descriptions ........................................
Message Object Time-Out Registers (CANMOTO) Field Descriptions .........................................
Time-Out Control Register (CANTOC) Field Descriptions ........................................................
Time-Out Status Register (CANTOS) Field Descriptions .........................................................
Message Identifier Register (CANMID) Field Descriptions .......................................................
Message Control Field Register (CANMCF) Field Descriptions..................................................
Local Acceptance Mask Register (CANLAM) Field Descriptions ................................................
Power Pin Descriptions ...............................................................................................
Mapping for Input Sources ............................................................................................
Memory Booting Configuration Pins after POR ....................................................................
Peripheral Booting Configuration Pins after POR ..................................................................
Booting Configuration Pins after a Warm Reset....................................................................
Pin Multiplexing According to Boot Peripheral ......................................................................
ROM Exception Vectors ...............................................................................................
Dead Loops .............................................................................................................
Tracing Data ............................................................................................................
RAM Exception Vectors ...............................................................................................
ROM Code Default Clock Settings ...................................................................................
ASIC ID Structure ......................................................................................................
Boot Messages .........................................................................................................
Device Descriptor .......................................................................................................
Device-Qualifier Descriptor ............................................................................................
Configuration Descriptor ...............................................................................................
Other Speed Configuration Descriptor ...............................................................................
Interface Descriptor ....................................................................................................
BULK IN Endpoint Descriptor .........................................................................................
SCC/HECC Registers
List of Tables
2651
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2666
2668
2672
2674
2676
2677
2678
2679
2680
2681
2681
2682
2682
2683
2684
2685
2687
2692
2695
2697
2699
2700
2702
2704
2705
2706
2706
2709
2711
2712
2714
2715
2715
2715
2716
2716
SPRUGR0C – October 2009 – Revised November 2013
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Copyright © 2009–2013, Texas Instruments Incorporated
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24-20. BULK OUT Endpoint Descriptor ......................................................................................
2716
.......................................................................................
2717
24-21. Language ID String Descriptor
24-22. Manufacturer ID String Descriptor ....................................................................................
2717
24-23. Product ID String Descriptor ..........................................................................................
2717
24-24. Configuration String Descriptor .......................................................................................
2717
24-25. Interface String Descriptor.............................................................................................
2717
24-26. Customized Descriptor Parameters ..................................................................................
2718
..............................................................................
Boot Announce Frame .................................................................................................
Frame transmitted by the Boot Server ...............................................................................
ACK frame sent by the Device to the Boot Server .................................................................
Blocks and Sectors Searched on Non-XIP Memories .............................................................
XIP Timing Parameters ................................................................................................
NAND Timing Parameters .............................................................................................
Supported NAND Devices .............................................................................................
Fourth NAND ID Data Byte ...........................................................................................
ID2 Byte Description ...................................................................................................
Bad Block Marks Locations in NAND Spare Areas ................................................................
Master Boot Record Structure ........................................................................................
Partition Table Entry ...................................................................................................
FAT Directory Entry ....................................................................................................
FAT Entry Description .................................................................................................
TOC Item ................................................................................................................
GP Device SW Image..................................................................................................
Booting Parameters Structure ........................................................................................
Tracing Vector ..........................................................................................................
Debug POR Signals ....................................................................................................
Debugger Address Space .............................................................................................
Document Revision History ...........................................................................................
24-27. Standard Device Requests Supported
2719
24-28.
2720
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
SPRUGR0C – October 2009 – Revised November 2013
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
List of Tables
2722
2723
2726
2727
2728
2729
2730
2733
2734
2742
2742
2743
2744
2748
2748
2749
2750
2751
2752
2753
125
Preface
SPRUGR0C – October 2009 – Revised November 2013
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Community Resources
The following link connects to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki — Texas Instruments Embedded Processors Wiki
Established to assist developers using the many Embedded Processors from Texas Instruments to
get started, help each other innovate, and foster the growth of general knowledge about the
hardware and software surrounding these devices.
126
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If You Need Assistance. . .
If you want to . . .
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Call the CRC (1) hotline:
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Or write to:
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Call the CRC (1) hotline:
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127
About This Manual
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About This Manual
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required
to take whatever measures may be required to correct this interference.
Information About Cautions and Warnings
This book may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your
software or equipment.
WARNING
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and
warning carefully.
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Register, Field, and Bit Calls
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Register, Field, and Bit Calls
The naming convention applied for a call consists of:
• For a register call: <Module name>.<Register name>; for example: UART.UASR
• For a bit field call:
– <Module name>.<Register name>[End:Start] <Field name> field; for example, UART.UASR[4:0]
SPEED bit field
– <Field name> field <Module name>.<Register name>[End:Start]; for example, SPEED bit field
UART.UASR[4:0]
• For a bit call:
– <Module name>.<Register name>[pos] <Bit name> bit; for example, UART.UASR[5]
BIT_BY_CHAR bit
– <Bit name> bit <Module name>.<Register name>[pos]; for example, BIT_BY_CHAR bit
UART.UASR[5]
To help the reader navigate the document, each register call is hyperlinked to its register description in the
register manual section. After each register description, a table summarizes all hyperlinked register calls.
To navigate in the PDF documents, see Acrobat Reader Tips.
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Coding Rules
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Coding Rules
The programming models or code listings follow the rules:
Type
Definition
Example
File
Starts with the module name
PRCM_test1.c
MCBSP1_init.h
Variable
Global variables are prefixed by "g_"
Pointers are prefixed by "p"
Global pointers are prefixed by "g_p"
g_SDMA_LogicalChan
pAddrCounter
g_pSDMA_LogicalChan
Function
Starts with the module name
PRCM_SetupClocks()
ArmIntC_MaskInterrupts()
Typedef
Ends with "_t"
PRCM_Struct_t
Definition
Starts with the module name and is followed by the
register name
#define SMS_ERR_TYPE *((volatileUint32*)0x680080F4)
#define MCBSP2_RCR1_REG *((volatile Uint32*)0x4807401C)
Enumeration
Starts with the module name
Typedef enum DMA_Mode_Label
{
INPUT_MODE
OUTPUT_MODE
} DMA_Mode_t;
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Flow Chart Rules
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Flow Chart Rules
Flow charts follow the following rules:
Shape
Start/Stop
The height of the text box
and its associated line
increases or decreases as
you add text. To change the
width of the comment, drag
the side handle.
Name
Definition
Process
Any computational steps or processing function of a program; defined
operation(s) causing change in value, form, or location of information
Decision
A decision or switching-type operation that determines which of a number
of alternate paths is followed
Predefined process or subprocess
One or more named operations or program steps specified in a
subroutine or another set of flow charts
Data or I/O
General I/O function; information available for processing (input) or
recording of processed information (output)
Terminator
Terminal point in a flow chart: start, stop, halt, delay, or interrupt; may
show exit from a closed subroutine
Annotation
Additional descriptive clarification, comment
On page connector (reference)
Exit to, or entry from, another part of chart in the same page
Off page connector (reference)
The flow continues on a different page.
Summing Junction
Logical AND
Or
Logical OR
Parallel mode (ISO)
Beginning or end of two or more simultaneous operations
Flow Line
Lines indicate the sequence of steps and the direction of flow.
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Acrobat Reader Tips
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Acrobat Reader Tips
Acrobat includes two methods to search for words in a PDF:
• The Find toolbar provides a basic set of options to locate a word in the current PDF.
• The Search window lista words or partial words that match your text in the current PDF.
These guidelines apply to Acrobat Reader 5.x, 6.0, and 7.0.
For more information on Acrobat Reader search features, see the Adobe Reader Help.
To search for words in a document using the Find dialog box:
1. Open the document.
2. To display the Find toolbar, right-click in the toolbar area and select Find.
3. In the Find box, type the word, words, or partial words for which you want to search.
4. From the Find Options menu, select options as desired.
5. To view each search result, click the Find toolbar, the Find Previous button, or the Find Next button to
go backward or forward through the document.
To search for words in a document using the Search PDF window:
1. Open the document.
2. Click the Search button on the File toolbar or right-click on your document and select Search.
3. Type the word, words, or part of a word for which you want to search.
4. Click Search.
5. The results appear in page order and, if applicable, show a few words of context. Each result displays
an icon to identify the type of occurrence. All other searchable areas display the Search Result icon.
6. To display the page that contains a search result, click an item in the Results list. The occurrence is
highlighted.
7. To navigate to the next result, choose Edit > Search Results > Next Result (or Ctrl+G).
8. To navigate to the previous result, choose Edit > Search Results > Previous Result (or Shift+Ctrl+G).
Navigate through your previous view
To retrace your path within an Adobe PDF document:
• For the previous view: Choose View > Go To > Previous View or Alt+Left Arrow.
• For the next view: Choose View > Go To > Next View or Alt+Right Arrow. The Next View command is
available only if you have chosen Previous View.
If you view the PDF document in a browser, use options on the Navigation toolbar to move between
views.
• Right-click the toolbar area, and then choose Navigation.
• Click the Go To Previous View button or the Go To Next View button.
NOTE: This navigation tip is useful to return to your previous view after clicking on a register call
hyperlink.
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OMAP3 Disclaimer
www.ti.com
OMAP3 Disclaimer
All programming models and use cases presented in this manual are provided for educative purposes only
and may differ from or be optimized for your applications.
All OMAP peripheral devices presented in this manual are provided for illustration purposes and may be
different from those in your system.
Trademarks
TMS320DMC64x, C64x, M-Shield and FlatLink3G are trademarks of Texas Instruments Incorporated.
ARM, JAZELLE, and THUMB are registered trademarks of ARM Limited.
ETM, ETB, ARM9, CoreSight, Cortex and Neon are trademarks of ARM Limited.
Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is licensed to Texas Instruments.
Memory Stick is a registered trademark of Sony Corporation, and Memory Stick PRO is a trademark of
Sony Corporation.
HDQ is a trademark of Benchmarq.
1-Wire is a registered trademark of Dallas Semiconductor.
Windows is a registered trademark of Microsoft Corporation in the United States and other countries.
USSE and POWERVR are trademarks or registered trademarks of Imagination Technologies Ltd.
Mentor Graphics is a registered trademark of Mentor Graphics Corporation or its affiliated companies in
the United States and other countries.
SonicsMX, Sonics3220 are trademarks or registered trademarks of Sonics, Inc.
Foveon X3 is a registered trademarks of Foveon, Inc.
Super CCD Honeycom is a registered trademark of Fuji Photo Film Co., Ltd.
Linux is a registered trademark of Linus Torvalds.
Symbian and all Symbian based trademarks and logos are trademarks of Symbian Software Limited.
Synopsys is a registered trademark of Synopsys, Inc.
MIPI is a registered trademark of the Mobile Industry Processor Interface (MIPI) Alliance.
OneNAND is a trademark of SAMSUNG.
All other trademarks are the property of their respective owners.
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History
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History
The following table summarizes the AM35x TRM versions.
(1)
(2)
(3)
(4)
134
Version
Literature Number
Date
Notes
*
SPRUGR0
October 2009
See
(1)
A
SPRUGR0
June 2010
See
(2)
B
SPRUGR0
July 2010
See
(3)
C
SPRUGR0
November 2013
See
(4)
AM35x ARM Microprocessor Technical Reference Manual - * version (SPRUGR0) initial release.
AM35x ARM Microprocessor Technical Reference Manual - version A (SPRUGR0).
•
Chapter 7: DMA
•
Chapter 12: Display Subsystem
•
Chapter 14: UART/IrDA/CIR
•
Chapter 16: Multichannel SPI
•
Chapter 17: Multichannel Buffered Serial Port
AM35x ARM Microprocessor Technical Reference Manual - version B (SPRUGR0B).
•
Chapter 8: Interrupt Controller
•
Chapter 14: UART/IrDA/CIR
AM35x ARM Microprocessor Technical Reference Manual - version C (SPRUGR0C).
•
Chapter 1: Introduction
•
Chapter 4: Power, Reset, and Clock Management
•
Chapter 18: Multichannel Buffered Serial Port
•
Chapter 20: Universal Serial Bus (USB)
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Chapter 1
SPRUGR0C – October 2009 – Revised November 2013
Introduction
This chapter introduces the features, supporting subsystems, and architecture of the AM35x ARM
Microprocessors.
Topic
...........................................................................................................................
1.1
1.2
1.3
1.4
Overview ........................................................................................................
Environment ...................................................................................................
Description .....................................................................................................
Device Family ..................................................................................................
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Introduction
Page
136
137
138
143
135
Overview
1.1
www.ti.com
Overview
The AM35x ARM Microprocessors are integrated on TI's advanced 65-nm process technology.
NOTE: This technical reference manual describes all available features. Some features may not be
available or supported on your particular device. For more information, see your devicespecific data manual and Section 1.4, Device Family.
These devices are designed to provide maximum flexibility for ARM based applications including, but not
limited to, Industrial Automation/Control, Single Board Computers, and Human Machine Interface.
These devices also feature M-Shield™ mobile security technology to enable secure e-commerce
applications and the replay of copyright-protected digital media content.
Security features integrated on these devices support applications designed for:
• Protection against malicious attacks
• M-commerce
• Content protection for recordable media (CPRM)
• Digital rights management (DRM)
High-security (HS) devices rely on a security scheme based on hardware mechanisms and secure readonly memory (ROM) code, ensuring that only trusted code can access secure resources. These resources
are in specific regions of memory as well as in peripherals, hardware cryptographic accelerators, and
eFuse keys.
NOTE:
To determine if a high-security (HS) version of your device is available and for more
information on HS devices, see your device-specific data manual and Section 1.4, Device
Family.
The device supports high-level operating systems such as:
• Windows CE
• Linux
Multiple RTOS are also supported.
These devices also include state-of-the-art power-management techniques required for high-performance
mobile products.
The following subsystems are part of the device:
• Microprocessor unit (MPU) subsystem based on the ARM® Cortex™-A8 microprocessor
• SGX subsystem for 3D graphics acceleration to support display and gaming effects
NOTE: SGX is not available on all devices. For more information see your device-specific data
manual and Section 1.4, Device Family.
•
•
•
Camera image signal processor (VPFE) that supports multiple formats and interfacing options
connected to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a
programmable interface supporting a wide variety of displays. The display subsystem also supports
NTSC/PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple
initiators to the internal and external memory controllers and to on-chip peripherals
These devices also offer a comprehensive power and clock-management scheme that enables highperformance and low-power operation.
136
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Environment
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1.2
Environment
This section provides an overview of the device when integrated with the TPS65023 power integrated
circuit (IC). For more information on the TPS65023 device, contact your TI representative.
Figure 1-1 provides an overview of a nonexhaustive environment for the high-tier device.
Figure 1-1. Environment Using TPS65023
PO
W
Amplified
Headset
Main/Sub
audio out audio in/out
Micro
H Bridge
Ear
Charger
interface
Gas Gauge
ty
ER
Headset
Handset
microphones Headset ear
speaker
BT+FM
TPS65023
AUDIO IC
N
Co etw
nn ork
ec
tiv
i
Hand free
speaker
AU
DI
O
Vibrator
Audio Aux
Keyboard
Power
OneNAND
BQ27000
I2C_CNTL
HDQ
I2C1
1
4
7
*
3
6
9
#
GPIO
USB
Mini-AB
BRF6350
TDM/I2S
USB OTG
External
PHY
McBSP3
McBSP2
UART2
EMAC
O
GPMC
M
EM
I2C2
WLAN
RI
E
S
Main
battery
2
5
8
0
KFM1G16Q2A
TNETW1253
MMC2
DDR2
UWB
SDRC
tm
uwb
MT46H32M32LF
UWB9100
3G/GGE Modem
McBSP1
Microprocessor
McBSP4
A SULTMED
SO
C I AIA CA
T I ORD
N
aGPS
24 mm
M
24 mm
32 mm
Generic
32 mm
MMC1 8bits
MMC1 4bits
I2C3
M
A SULTMED
SO
C I AIA CA
T I ORD
N
MMC/SD Card
MMC/SD
Card
8 bits
4 bits
GPS5300
HDD CE-ATA
IrDA
MMC3
UART3
HMS361008M5C
A00
TVOUT
McSPI2
Touch
screen
SUB LCD
Svideo
DTV
TSC2005
QVGA 64KCol
2MJ-0102A120
DTV1000
I2C2
Sub camera
Im
ag
TBD
AT77C105A
HSDL-3021
in
g
Fingerprint
IN U
T E SE
R R
(U FA
I) C
E
McSPI3
McSPI1
CAM
8 bit/16 bit//
FCM-1F108S
108-001
NOTE: Some features are not available on all devices. For more information. see your devicespecific data manual and Section 1.4, Device Family.
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Introduction
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Description
1.3
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Description
These devices are offered in the following package:
• ZCN package: 491-pin BGA (17x17, 0.65mm pitch)
• ZER package: 484-pin PBGA (23x23, 1mm pitch)
Figure 1-2 shows the block diagram.
Figure 1-2. Block Diagram
LCD Panel
MPU
Subsystem
ARM CortexA8TM Core
16K/16K L1$
L2$
256K
64
64
HECC
32
32
32
Channel
System
DMA
32
64
HS/FS/
LS
USB
Host
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV → QCIF Support
32
USB PHY
USB OTG
Controller
32
Async
EMAC
USB transceivers /
device ports [3]
Analog
DAC
Parallel
POWERVR
TM
SGX
Graphics
Accelerator
(AM3517 only)
CVBS
or
S-Video
32
VPFE
64
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
32
64K
On-Chip
RAM
64
132K
On-Chip
BOOT
ROM
SMS:
SDRAM
Memory
Scheduler/
Rotation
EMIF
Controller
DDR PHY
External
DDR2/
mDDR
32
32
32
L4 Interconnect
GPMC:
General
Purpose
Memory
Controller
NAND/NOR/
FLASH,
SRAM
Peripherals:
4xUART, 3xHigh-Speed I2C,
5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 186xGPIO,
3xHigh-Speed MMC/SDIO,
HDQ/1 Wire,
12xGPTimers, 1xWDT,
32K Sync Timer
System
Controls
PRCM
External
Peripherals
Interfaces
Emulation
Debug: ETM, JTAG
SPRS550-006
NOTE: Some features are not available on all devices. For more information, see your devicespecific data manual and Section 1.4, Device Family.
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Description
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1.3.1 MPU Subsystem
The MPU subsystem integrates the following modules
• ARM subchip
– ARM® Cortex™-A8 core
– ARM Version 7™ ISA: Standard ARM instruction set + Thumb®-2, Jazelle® RCT Java accelerator,
and media extensions
– NEON™ SIMD coprocessor (VFP lite + media streaming instructions)
– Cache memories
• Level 1: 16KB instruction and 16KB data—4-way set associative cache, 64 bytes/line
• Level 2: see Section 1.4, Device Family
• Interrupt controller (MPU INTC) of 96 synchronous interrupt lines
• Asynchronous interface with core logic
• Debug, trace, and emulation features: ICE-Crusher, ETM, ETB modules
1.3.2 On-Chip Memory
On-chip memory configuration offers memory resources for program and data storage:
• 112KB ROM
• 64KB single-access static random access memory (SRAM)
1.3.3 External Memory Interfaces
The device includes two external memory interfaces:
• General-purpose memory controller (GPMC)
– NOR flash, NAND flash (with ECC Hamming code calculation), SRAM and Pseudo-SRAM
asynchronous and synchronous protocols
– Flexible asynchronous protocol control for external ASIC or peripheral interfacing
– 16-bit data, up to 8 chip-selects (CSs)
– 128M-byte addressable per chip-select, 1G-byte total address space
– Nonmultiplexed device with limited address (2K bytes)
• SDRAM Controller (SDRC)
– Double data rate (DDR2 and LPDDR) SDRAM
– 16-bit or 32-bit data, 2 chip-selects, configurations for a maximum of 1 G-byte address space per
chip-select
– Work in conjunction with the SDRAM memory scheduler (SMS) companion module
1.3.4 DMA Controllers
The device embeds one generic DMA controller, the system DMA (sDMA) controller, used for memory-tomemory, memory-to-peripheral, and peripheral-to-memory transfers:
• One read port, one write port
• 32 prioritizable logical channels
• 96 hardware requests
• 256 x 32-bit FIFO dynamically allocable between active channels
The device also embeds two dedicated DMA controllers: display DMA and USB HS DMA.
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Description
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1.3.5 Multimedia Accelerators
The device uses the following multimedia accelerators for display and gaming effects as well as high-end
imaging and video applications:
• 3D graphics accelerator (SGX)
– 3D graphics and video codecs supported on common hardware
– Tile-based architecture
– Universal scalable shader engine (USSE™) multithreaded engine incorporating pixel and vertex
shader functionality reducing die area
– Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
– Industry standard API supports OGL-ES 1.1 and 2.0, OpenVG 1.0, and OpenMax
– Fine-grained task switching, load balancing, and power management
– Programmable high-quality image anti-aliasing
– Advanced geometry DMA driven operation for minimum CPU interaction
– Fully virtualized memory addressing for OS operation in a unified memory architecture
– Advanced and standard 2D operations (that is, vector graphics, BLTs, ROPs, etc.)
• Video Processing Front End (VPFE)
– Supports most of the raw and smart image sensors available in the market
– 16-bit parallel interface supported
– Pixel clock up to 75 MHz
CAUTION
Clock configurations depend on the core voltage and maximum clock
frequencies. Values in this document might not apply to production devices.
Refer to your device-specific data manual for supported values for
production devices.
•
140
Display interface
– Display controller
– Color and monochrome displays up to 2048 x 2048 x 24-bpp resolution
– 256 x 24-bit entries palette in red, green, blue (RGB)
– 3,375 colors, 15 grayscales
– Picture-in-picture (overlay), color-space conversion, rotation, color-phase rotation, and resizing
support
– Remote frame buffer interface
– Liquid-crystal display (LCD) pixel interfaces (MIPI DPI 1.0) and LCD bus interfaces (MIPI DBI 1.0)
supported
– NTSC/PAL video encoder outputs with integrated digital-to-analog converters (DACs) output are
supported on CVBS and S-video TV analog output signals
– Embedded DMA controller
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Description
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1.3.6 Security (HS Devices Only)
The secure firmware resides in a secure version of the ROM and includes hardware security features that
enable HS devices and encryption/decryption accelerators. The following encryption/decryption
accelerators are only available in HS devices:
• RNG
• 2 x DES/3DES
• SHA1/MD5
• SHA2/MD5
• 2 x AES with counter mode
• Fast PKA
The customer programmable fuse ROM (CPFROM) module is only available on high-security (HS)
devices.
NOTE:
To determine if a high-security (HS) version of your device is available and for more
information on HS devices, see your device-specific data manual and Section 1.4, Device
Family.
1.3.7 Comprehensive Power Management
The device includes the following power management features:
• Clock and reset generation and distribution
• Auto clock gating to save active power by gating clock when peripheral is not active
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Description
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1.3.8 Peripherals
The device supports a comprehensive set of peripherals to provide flexible and high-speed interfacing and
on-chip programming resources. Table 1-1 provides a list and description of the peripherals that are
available.
Table 1-1. Device Peripherals
Type
Serial Communication
Removable Media
Miscellaneous
Security Modules (Highsecurity Devices Only)
142
Introduction
Name
Number
Description
Multi-channel Buffered
Serial Ports (McBSPs)
5
The McBSPs provide a full-duplex direct serial interface between
the device and other devices in a system such as audio and
voice codecs and other application chips.
McBSP1, McBSP2, and McBSP3 serve as general purpose
serial ports while McBSP2 and McBSP3 include additional
audio-loopback capability.
Multi-channel Serial Port
Interface (McSPI)
4
The McSPIs provide a master/slave interface to SPI devices.
High-speed Multi-port
USB Host Controller
1
High-speed USB2.0 host controller with three host ports each
offering high-speed data transactions (up to 480 Mbps) or fullspeed/low-speed data transactions (12 and 1.5 Mbps,
respectively).
In high-speed mode, the USB host controller ports interface to
external USB PHYs using a 12-pin or 8-pin UTMI low pin
interface (ULPI). In full-speed and low-speed mode, the ports
interface to external USB PHYs using a 6-/4-/3-pin serial
interface.
High-speed USB OTG
Controller
1
High-speed USB2.0 OTG controller that offers high-speed data
transactions (up to 480 Mbps) on a USB port with embedded
DMA controller.
The high speed USB OTG controller includes integrated PHY,
thus eliminating need of external PHY.
HDQ/1-Wire®
1
The HDQ/1-Wire interface supports the Benchmark HDQ
protocol and the Dallas Semiconductor 1-Wire protocol.
Universal Asynchronous
Receiver/Transmitter
(UART)
4
Serial communication interfaces compatible to the industry
standard TL16C550 asynchronous communications element.
UART1 and UART 2 are general serial communication
interfaces. UART3 provides additional support for infrared data
association (IrDA) and consumer infrared (CIR) communications.
High-speed (HS) Interintegrated Circuit (I2C)
Controllers
3
Master/slave I2C high-speed standard interfaces with support for
standard mode (up to 100K bits/s), fast mode (up to 400K
bits/s), and high-speed mode (up to 3.4M bits/s).
HECC
1
Interface used to connect to vehicle bus in automotive.
Multimedia Card/Secure
Digital/Secure Digital I/O
(MMC/SDIO) Card
Interface
3
MMC memory card, SD memory card, or SDIO cards interface.
GP timers
12
Twelve general-purpose timers
Watchdog timers
(WDTs)
1
Three watchdog timers
32-kHz synchronization
timer
1
32-kHz clock timer
General-purpose
input/output (GPIO)
Packagespecific
General-purpose input/output pins controlled by six GPIO
controllers.
EMAC
1
10/100 Mbit Ethernet MAC operation with CPPI4.0 compliant &
RMII interface. Interface used to connect to vehicle
Control module
1
I/O multiplexing and chip-configuration control.
RNG, Fast PKA, 2xDES/3DES, SHA1/MD5, SHA2/MD5, 2xAES,
and Secure Watchdog Timer.
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Device Family
www.ti.com
1.4
Device Family
1.4.1 Device Features
Devices are configured with different sets of features on different devices. This technical reference manual
details all available features. Some features may not be available or supported in your particular device.
Features supported across different devices are shown in Table 1-2 (ZCN package). For more information
on the ZCN package, refer to your device-specific data manual.
Table 1-2. Subsystem, Co-Processor, and Peripheral Support Matrixon the (ZCN Package)
Subsystem/Co-Processor/Peripheral
Chapter
AM3517
POWERVR SGX™ 3D Graphics Accelerator
11
x
Cortex-A8 Neon Co-Processor
3
x
x
SDRAM Controller
9
x
x
General-Purpose Memory Controller
9
x
x
VPFE
10
x
x
Display Subsystem
12
x
x
x
x
LCD DPI, LCD RFBI and TV Output Interface
AM3505
LCD DSI and LCD SDI
McBSP1/2/3/4/5
17
x
x
McSPI1/2/3/4
16
x
x
High-Speed USB OTG Controller
20
x
x
High-Speed USB Host Controller
20
x
x
HDQ/1-Wire
18
x
x
UART1/2
14
x
x
UART3/IrDA/CIR
14
x
x
I2C1/2/3
15
x
x
EMAC
22
x
x
HECC
23
x
x
MMC/SD/SDIO1/2/3
19
x
x
GP Timer (x12)
13
x
x
Watchdog Timer
13
x
x
32-kHz Sync Timer
13
x
x
GPIO
21
x
x
Secure ROM
1
RNG
1
DES/3DES
1
SHA1/MD5
1
SHA2/MD5
1
AES
1
Fast PKA
1
Secure Watchdog Timer
1
High-security Device
1
General-purpose Device
1
x
x
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Introduction
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Device Family
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1.4.2 Device Identification
The identification registers include the CONTROL_IDCODE and CONTROL_DIE_ID data registers. These
registers are accessible through the L4 interconnect port starting at physical address 0x4830 A204 and
0x4830 A218, respectively. See the Memory Mapping chapter for more information about the L4 memory
space mapping. Table 1-3 describes the identification registers.
The silicon type can be read in the HAWKEYE bit field value of the CONTROL.CONTROL_IDCODE
register. The silicon revision can be read in the VERSION bit field value of the
CONTROL.CONTROL_IDCODE register.
Table 1-3. Device Identification Registers
Register Name
Address
Size
CONTROL.CONTROL_IDCODE[31:0]
0x4830 A204
32
CONTROL.CONTROL_DIE_ID[127:0]
0x4830 A218
128
To retrieve chip identification, see Table 1-4. This register helps software identify the chip derivative.
Table 1-4. Chip Identification
Scalable
Resource
Name
SGX
SGX_scalable_control
Reserved
Reserved
MPU L2 Cache
Size
MPU_L2_cache_size
MPU Frequency
ARM_MHz
Reserved
Reserved
NEON & VFP
NEON_VFPLite
Reserved
Reserved
MMC1 Width
4_8_bit_mmc
TV Out
Bit
Value
14:13
00
Full use.
01
Core clock restricted in HW to /6 from L3.
10
HW not present.
11
Reserved.
12
0
Reserved. Not available for use.
11:10
00
0 KB.
01
64 KB.
10
128 KB.
11
00
01
400 MHz.
10
266 MHz.
11
Reserved.
7:5
1
4
0
1
Not available for use.
3:2
1
1
0
1
Restricted use (4-bit width at 3.0v IO)
0
Full use.
1
Not available for use.
9:8
TO_OUT
0
Description
AM3517
AM3505
00
10
0
0
Full use (256 KB).
11
11
500 MHz.
00
00
Reserved. Not available for use.
0
0
Full use.
0
0
Reserved. Not available for use.
0
0
Full use (8-bit width at 3.0v IO)
0
0
0
0
0x0C00
0x4C00
Control Device Status Register 15:0 (Address 0x4800 244C)
Table 1-5. CONTROL_IDCODE Register Definition
Field
Bits
Value
Comment
CONTROL.CONTROL_IDCODE [31:28]
VERSION
See Table 1-6
Revision number
CONTROL.CONTROL_IDCODE [27:12]
HAWKEYE
See Table 1-7
Hawkeye number
CONTROL.CONTROL_IDCODE [11:1]
TI_IDM
0x13
Manufacturer identity (TI)
CONTROL.CONTROL_IDCODE [0]
--
0x1
Always set to 1.
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The Hawkeye number is hardcoded in the design. Table 1-7 lists the Hawkeye number values, and
Table 1-6 lists the silicon revision values.
Table 1-6. Revision Number Value
Silicon Type
Field
Value
ES1.0
CONTROL.CONTROL_IDCODE[31:28]
0000
ES1.1
CONTROL.CONTROL_IDCODE[31:28]
0001
Table 1-7. Hawkeye Number Value
Silicon Type
Field
Value
ES1.0
CONTROL.CONTROL_IDCODE[27:12]
0xB868
ES1.1
CONTROL.CONTROL_IDCODE[27:12]
0xB868
•
The CONTROL.CONTROL_DIE_ID register is the 128 bits single identifier of the device.
Table 1-8. CONTROL_DIE_ID
Field
DIE_ID[127:0]
Bits
Value
RESERVED
Single identifier
1.4.3 General Recommendations Relative to Unavailable Features/Modules
As explained in the previous section, some features are not available in all devices. For unavailable
features, use the following recommendations:
• Memory mapping: Memory area of unavailable modules and features are RESERVED, read is
undefined, and write can lead to unpredictable behavior.
• Interrupt controllers: Ensure that interrupts of unavailable modules and features are masked in the
MPU subsystem.
• DMA: Ensure that DMA requests of unavailable modules and features are masked in DMA
subsystems.
• System Control Module (SCM): Unavailable modules and feature pins are not functional and should
not be used.
• Power, Reset, and Clock Management Module (PRCM): For power management and power-saving
consideration, ensure that power domains of unavailable features/modules are switched off and clocks
are cut off.
• Interconnect: To flag potential interconnect outstanding commands, the time-out of target agents
attached to unavailable modules can be enabled with the lowest setting.
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Memory Mapping
This chapter describes memory mapping.
NOTE: This chapter gives information about all modules and features in the high-tier device. To
check availability of modules and features, see Chapter 1, Device Family. The memory area
of unavailable modules and features is RESERVED, read is undefined, and write can lead to
unpredictable behavior.
146
Topic
...........................................................................................................................
2.1
2.2
2.3
2.4
Introduction ....................................................................................................
Global Memory Space Mapping .........................................................................
L3 and L4 Memory Space Mapping ....................................................................
IPSS Memory Space Mapping ...........................................................................
Memory Mapping
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147
149
152
162
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Introduction
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2.1
Introduction
The microprocessor unit (MPU) has a 32-bit address port, allowing it to handle a 4Gbytes space divided
into several regions, depending on the target type.
The memory map is composed of a memory space (general-purpose memory controller [GPMC], external
memory interface [EMIF4], etc.), register space (L3 and L4 interconnects), and dedicated spaces (SGX,
etc.), all of which are shared among the initiators (for example, the MPU subsystem or the display
subsystem).
The GPMC and EMIF4 are dedicated to memory connection. The GPMC is used for NOR/NAND flash and
PSRAM memories. The EMIF4 is used for DDR2. For more information, see the Memory Subsystem
chapter.
The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip
memories, between all the initiators of the platform. The L4 interconnects control access to the
peripherals.
Transfers between initiators and targets across the platform are physically conditioned by the chip
interconnect and can be logically conditioned by firewalls. For more information about the
intercommunication (L3 and L4 interconnects) and protection mechanisms implemented in the device, see
the Interconnect.
NOTE: Some features may not be available or supported in your particular device. For more
information, see Chapter 1, Device Family, and your device-specific data manual.
Figure 2-1 shows the interconnect of the device and the main modules and subsystems in the platform.
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148
Memory Mapping
OCMC
RAM
Firewall
OCMC
ROM
MPU
subsystem
GPMC
External memory
EMIF
SMS
SDRAM
Controller
SGX
L3 interconnect
L4
Display
subsystem
L4
3x McBSP, UART-IRDA,
8xGPTimer, 5xGPIO, WDTimer
L4 interconnect (peripheral)
SDMA
HS USB
HOST
HECC
(CAN)
L4 interconnect (core)
IP-Subsystem
EMAC
(RMII)
CameraVPFE
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External peripherals ports
PRM, 2xGPT, 2xWDT,
GPIO, Timer32K
DAP
TPIU, SDTI,
ETB, Test TAP
L4 interconnect
(emulation)
L4 interconnect (wake-up)
3xI2C, 2xMcBSP, 2xGPT, 4xMcSPI,
3xUART, 3xMMC, SDMA, CM,
Control Module, MPU-INTC, HDQ/Wire
L4
USB
OTG
External peripherals ports
100-022
L4
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Figure 2-1. Interconnect Overview
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2.2
Global Memory Space Mapping
This section provides a global view of the memory mapping and details the boot, GPMC, EMIF4, and
virtual rotated frame buffer (VRFB) memory spaces.
The system memory mapping is flexible, with two levels of granularity for target address space allocation:
• Level 1: Four quarters are labeled Q0, Q1, Q2, and Q3. Each quarter corresponds to a 1Gbyte
address space (total address space is 4Gbytes).
• Level 2: Each quarter is divided into eight blocks of 128Mbytes, with target spaces mapped inside the
blocks.
This organization allows all target spaces to be decoded based on the five most significant bits (MSBs) of
the 32-bit address ([31:27]).
• Boot space
The system has a 1Mbyte boot space either in the on-chip boot ROM or on the GPMC memory space.
When booting from the on-chip ROM with the appropriate external sys_boot5 pin configuration, the
1Mbyte memory space is redirected to the on-chip boot ROM memory address space [0x4000 0000 –
0x400F FFFF].
When booting from the GPMC with the appropriate external sys_boot5 pin configuration, the memory
space is part of the GPMC memory space.
For more information on sys_boot5 pin configuration, see the Memory Subsystem and Initialization
chapters.
• GPMC space
Eight independent GPMC chip-selects (gpmc_ncs0 to gpmc_ncs7) are available in the first quarter
(Q0) of the addressing space to access NOR/NAND flash and PSRAM memories. The chip-selects
have a programmable start address and programmable size (16Mbytes, 32Mbytes, 64Mbytes, or
128Mbytes) in a total memory space of 1Gbyte.
• EMIF4 space
Two EMIF4 chip-selects (emif4_ncs0 and emif4_ncs1) are available on the third quarter (Q2) of the
addressing space to access SDRAM memories. The base address of EMIF4 space starts at 0x8000
0000. For more information on EMIF please refer to MemorySubsystem Chapter.
• VRFB space
The EMIF4-SMS virtual memory space is a different memory space used to access a subset of the
EMIF4 memory space through the rotation engine. The virtual address space size is 768Mbytes split
into two parts: The first 256M-byte part is in the second quarter (Q1) of the memory; the second
512Mbytes part is in the fourth quarter (Q3) of the memory.
For more information on GPMC, EMIF4, and VRFB, see the Memory Subsystem chapter.
This section gives information about all modules and features in the high-tier device. To check availability
of modules and features, see Chapter 1, Device Family. The memory area of unavailable modules and
features is RESERVED, read is undefined, and write can lead to unpredictable behavior.
Table 2-1 describes the global memory space mapping.
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Table 2-1. Global Memory Space Mapping
QUARTER
Device Name
Q0
(1GB)
Boot space (1)
GPMC
GPMC
Q1
(1GB)
Start Address
(HEX)
End Address
(HEX)
0x0000 0000
0x3FFF FFFF
On-Chip
Memory
ROM/SRAM address space
0x4001 3FFF
80KB
32-bit Ex (2)/R – Secure
0x4001 4000
0x4001 BFFF
32KB
32-bit Ex (2)/R – Public
Reserved
0x4001 C000
0x400F FFFF
912KB
Reserved
Reserved
0x4010 0000
0x401F FFFF
1MB
Reserved
SRAM internal
0x4020 0000
0x4020 FFFF
64KB
32-bit Ex (2)/R/W –
Secure/public (3)
Reserved
0x4021 0000
0x4024 FFFF
256KB
Reserved
Reserved
0x4025 0000
0x47FF FFFF
128,704KB
Reserved
(4)
128MB
All system peripherals
See Table 2-3.
0x4800 0000
0x48FF FFFF
16MB
(0x4830 0000)
(0x4833 FFFF)
(256KB)
L4-Per
0x4900 0000
0x490F FFFF
1MB
Reserved
0x4910 0000
0x4FFF FFFF
111MB
Reserved
64MB
Graphic accelerator slave
port
Graphic accelerator slave
port
SGX
(See Table 2-4.)
See Table 2-5.
SGX
0x5000 0000
0x5000 FFFF
64KB
Reserved
0x5001 0000
0x53FF FFFF
65,472KB
Reserved
64MB
Emulation
L4 Emulation
L4-Emu
0x5400 0000
0x547F FFFF
Reserved
0x5480 0000
0x57FF FFFF
Reserved
Reserved
8MB
See Table 2-6.
56MB
Reserved
64MB
Reserved
64MB
Reserved
0x5800 0000
0x5BFF 0FFF
64MB
IPSS
IPSS
0x5C00 0000
0x5EFF FFFF
48MB
IPSS. See Table 2-8.
Reserved
0x5F00 0000
0x5FFF FFFF
16MB
Reserved
128MB
Reserved
IPSS
Reserved
Reserved
0x6000 0000
0x67FF FFFF
128MB
Reserved
128MB
Control Registers
0x68FF FFFF
16MB
See Table 2-2.
L3 Interconnect
L3 Control
Registers
(4)
8/16 Ex (2)/R/W
0x4000 0000
(L4-Wakeup)
(3)
Description
Boot ROM
internal (1)
L4-Core
(2)
1GB
128MB
L4
interconnects
(1)
Size
1MB
1GB
or 1GB-1MB
0x6800 0000
Reserved
0x6900 0000
0x6BFF FFFF
48MB
Reserved
SMS registers
0x6C00 0000
0x6CFF FFFF
16MB
Configuration registers SMS
address space 2
EMIF4 registers
0x6D00 0000
0x6DFF FFFF
16MB
Configuration registers SMS
address space 3
GPMC registers
0x6E00 0000
0x6EFF FFFF
16MB
Configuration registers
GPMC address space 1
Reserved
0x6F00 0000
0x6FFF FFFF
16MB
Reserved
Boot space location depends on the external sys_boot5 pin configuration.
Executable
Default public/secure settings after reset only
Peripherals connected to the L4-Wakeup interconnect are accessed through the L4-Core interconnect.
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Table 2-1. Global Memory Space Mapping (continued)
QUARTER
Device Name
Start Address
(HEX)
End Address
(HEX)
0x7000 0000
0x7FFF FFFF
EMIF4/SMS
EMIF4/SMS
virtual
Address space 0
Q2
(1GB)
EMIF4/SMS
SDRAM
Q3
(1GB)
0x8000 0000
0xBFFF FFFF
Reserved
Reserved
0xC000 0000
0xDFFF FFFF
EMIF4/SMS
EMIF4/SMS
virtual
Address space 1
0xE000 0000
0xFFFF FFFF
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Size
Description
256MB
EMIF4/SMS
256MB
EMIF4-SMS virtual address
space 0
1GB
SDRAM main address
space (SMS)
1GB
EMIF4/SMS
512MB
Reserved
512MB
Reserved for future use.
512MB
EMIF4/SMS
512MB
EMIF4-SMS virtual address
space 1
Memory Mapping
151
L3 and L4 Memory Space Mapping
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L3 and L4 Memory Space Mapping
The memory space system is defined from a hierarchical view: L1, L2, L3, and L4.
L1 memory includes the MPU subsystem.
The chip-level interconnect, which is made of one L3 and four L4s, enables communication between all
modules and subsystems.
L3 handles many types of data transfers and, in particular, the data exchange with system onchip/external memories.
The four L4s that handle transfers with peripherals are: the L4-Core, L4-Wakeup, L4-Per, and L4-Emu
interconnects.
For more information about the interconnect, see the Interconnect chapter.
The following sections describe the register mapping of the L3 and L4 interconnects. The software
configures these registers.
2.3.1 L3 Memory Space Mapping
The L3 interconnect control registers are mapped in a 16Mbytes space and allow the configuration of the
L3 interconnect parameters.
The L3 default settings are fully functional and enable all possible functional data paths. However, the
interconnect parameters can be changed to accommodate expectations.
Accesses to the L3 interconnect can be configured on a per-module basis using the internal L3 registers,
which are grouped into five register block types:
• IA: initiator agent configuration registers
• TA: target agent configuration registers
• RT: register target (global configuration registers)
• PM: protection mechanism (firewalls) configuration registers
• SI: global sideband signal configuration registers
For more information, see the Interconnect chapter.
This section gives information about all modules and features in the high-tier device. to check availability
of modules and features, see Chapter 1, Device Family. The memory area of unavailable modules and
features is RESERVED, read is undefined, and write can lead to unpredictable behavior.
Table 2-2 describes the mapping of the L3 interconnect control registers.
Table 2-2. L3 Control Register Mapping
Start Address
(HEX)
End Address
(HEX)
Size
Description
L3 RT
0x6800 0000
0x6800 03FF
1KB
L3 configuration registers
L3 SI
0x6800 0400
0x6800 07FF
1KB
Sideband signals configuration
Reserved
0x6800 0800
0x6800 13FF
3KB
Reserved
MPU SS IA
0x6800 1400
0x6800 17FF
1KB
MPU subsystem instruction port agent
configuration
Unused
0x6800 1800
0x6800 1BFF
1KB
Unused
SGX SS IA
0x6800 1C00
0x6800 1FFF
1KB
SGX subsystem initiator port agent
configuration
SMS TA
0x6800 2000
0x6800 23FF
1KB
SMS target port agent configuration
GPMC TA
0x6800 2400
0x6800 27FF
1KB
GPMC target port agent configuration
OCM RAM TA
0x6800 2800
0x6800 2BFF
1KB
OCM RAM target port agent
configuration
OCM ROM TA
0x6800 2C00
0x6800 2FFF
1KB
OCM ROM target port agent
configuration
Reserved
0x6800 3000
0x6800 3FFF
4KB
Reserved
Device Name
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Table 2-2. L3 Control Register Mapping (continued)
Start Address
(HEX)
End Address
(HEX)
Size
Description
HS USB HOST IA
0x6800 4000
0x6800 43FF
1KB
HS USB HOST initiator port agent
configuration
IPSS IA
0x6800 4400
0x6800 47FF
1KB
IPSS
Reserved
0x6800 4800
0x6800 4BFF
1KB
Reserved
sDMA RD IA
0x6800 4C00
0x6800 4FFF
1KB
sDMA RD initiator port agent
configuration
sDMA WR IA
0x6800 5000
0x6800 53FF
1KB
sDMA WR initiator port agent
configuration
Display SS IA
0x6800 5400
0x6800 57FF
1KB
Display subsystem initiator port agent
configuration
Unused
0x6800 5800
0x6800 5BFF
1KB
Unused
DAP IA
0x6800 5C00
0x6800 5FFF
1KB
Debug access port initiator port agent
configuration
IPSS TA
0x6800 6000
0x6800 63FF
1KB
IPSS Target Port agent configuration
SGX SS TA
0x6800 6400
0x6800 67FF
1KB
SGX subsystem target port agent
configuration
L4-Core TA
0x6800 6800
0x6800 6BFF
1KB
L4-Core target port agent
configuration
L4-Per TA
0x6800 6C00
0x6800 6FFF
1KB
L4-Per target port agent configuration
Reserved
0x6800 7000
0x6800 FFFF
36KB
Reserved
RT PM
0x6801 0000
0x6801 03FF
1KB
Register target port protection
Reserved
0x6801 0400
0x6801 23FF
8KB
Reserved
GPMC PM
0x6801 2400
0x6801 27FF
1KB
GPMC target port protection
OCM RAM PM
0x6801 2800
0x6801 2BFF
1KB
OCM RAM target port protection
OCM ROM PM
0x6801 2C00
0x6801 2FFF
1KB
OCM ROM target port protection
Reserved
0x6801 3000
0x6801 3FFF
4KB
Reserved
IPSS PM
0x6801 4000
0x6801 43FF
1KB
IPSS
Reserved
0x6801 4400
0x68FF FFFF
16,303KB
Device Name
Reserved
2.3.2 L4 Memory Space Mapping
The device contains four L4 interconnects: the L4-Core, L4-Wakeup, L4-Per, and L4-Emu interconnects.
As with the L3 interconnect, the L4 interconnects can be configured to tune the access depending on the
characteristics of each module.
For more information on the L4 interconnect, see the Interconnect chapter.
2.3.2.1
L4-Core Memory Space Mapping
The L4-Core interconnect is a 16Mbytes space composed of the L4-Core interconnect configuration
registers and the module registers.
Table 2-3 describes the mapping of the registers for the L4-Core interconnect.
NOTE: All memory spaces described as modules provide direct access to module registers outside
the L4-Core interconnect. All other accesses are internal to the L4-Core interconnect.
This section gives information about all modules and features in the high-tier device. To check availability
of modules and features, see Chapter 1, Device Family. The memory area of unavailable modules and
features is RESERVED, read is undefined, and write can lead to unpredictable behavior.
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Table 2-3. L4-Core Memory Space Mapping
(1)
Start Address
(HEX)
End Address
(HEX)
Size
L4-Core
0x4800 0000
0x48FF FFFF
16MB
Reserved
0x4800 0000
0x4800 1FFF
8KB
Reserved
System control module
0x4800 2000
0x4800 2FFF
4KB
Module
0x4800 3000
0x4800 3FFF
4KB
L4 interconnect
0x4800 4000
0x4800 5FFF
8KB
Module region A
0x4800 6000
0x4800 67FF
2KB
Module region B
0x4800 6800
0x4800 6FFF
2KB
Reserved
0x4800 7000
0x4800 7FFF
4KB
L4 interconnect
Reserved
0x4800 8000
0x4802 3FFF
112KB
Reserved
Reserved
0x4802 4000
0x4802 4FFF
4KB
Reserved
0x4802 5000
0x4802 5FFF
4KB
Reserved
Reserved
0x4802 6000
0x4803 FFFF
104KB
Reserved
L4-Core configuration
0x4804 0000
0x4804 07FF
2KB
Address/protection (AP)
0x4804 0800
0x4804 0FFF
2KB
Initiator port (IP)
0x4804 1000
0x4804 1FFF
4KB
Link agent (LA)
Reserved
0x4804 2000
0x4804 FBFF
55KB
Reserved
Reserved
0x4804 FC00
0x4804 FFFF
1KB
Reserved
Display subsystem
• Display subsystem top
• Display controller
• RFBI
• Video encoder
0x4805 0000
0x4805 03FF
1KB
Display subsystem top
0x4805 0400
0x4805 07FF
1KB
Display controller
Device Name
Clock manager
• DPLL
• Clock manager
Description
0x4805 0800
0x4805 0BFF
1KB
RFBI
0x4805 0C00
0x4805 0FFF
1KB
Video encoder
0x4805 1000
0x4805 1FFF
4KB
L4 interconnect
Reserved
0x4805 2000
0x4805 5FFF
16KB
Reserved
sDMA
0x4805 6000
0x4805 6FFF
4KB
Module
0x4805 7000
0x4805 7FFF
4KB
L4 interconnect
Reserved
0x4805 8000
0x4805 FFFF
32KB
Reserved
I2C3
0x4806 0000
0x4806 0FFF
4KB
Module
0x4806 1000
0x4806 1FFF
4KB
L4 interconnect
0x4806 2000
0x4806 2FFF
4KB
Module
0x4806 3000
0x4806 3FFF
4KB
L4 interconnect
0x4806 4000
0x4806 4FFF
4KB
Module
0x4806 5000
0x4806 5FFF
4KB
L4 interconnect
USBTLL module
HS USB HOST
Reserved
0x4806 6000
0x4806 9FFF
16KB
Reserved
UART1
0x4806 A000
0x4806 AFFF
4KB
Module
0x4806 B000
0x4806 BFFF
4KB
L4 interconnect
0x4806 C000
0x4806 CFFF
4KB
Module
UART2
0x4806 D000
0x4806 DFFF
4KB
L4 interconnect
Reserved
0x4806 E000
0x4806 FFFF
8KB
Reserved
I2C1
0x4807 0000
0x4807 0FFF
4KB
Module
0x4807 1000
0x4807 1FFF
4KB
L4 interconnect
0x4807 2000
0x4807 2FFF
4KB
Module
0x4807 3000
0x4807 3FFF
4KB
L4 interconnect
McBSP1
(Digital baseband data)
0x4807 4000
0x4807 4FFF
4KB
Module
0x4807 5000
0x4807 5FFF
4KB
L4 interconnect
Reserved
0x4807 6000
0x4808 5FFF
64KB
Reserved
I2C2
(1)
The registers mapped in this range are shadow registers of the first 2Kbytes region A [0x4800 4000 - 0x4800 47FF]. Region A
and region B share the same port.
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Table 2-3. L4-Core Memory Space Mapping
(2)
(continued)
Device Name
Start Address
(HEX)
End Address
(HEX)
Size
Description
GPTIMER10
0x4808 6000
0x4808 6FFF
4KB
Module
0x4808 7000
0x4808 7FFF
4KB
L4 interconnect
0x4808 8000
0x4808 8FFF
4KB
Module
0x4808 9000
0x4808 9FFF
4KB
L4 interconnect
Reserved
0x4808 A000
0x4809 3FFF
40KB
Reserved
Unused
0x4809 4000
0x4809 5FFF
8KB
Unused
McBSP5
(MIDI data)
0x4809 6000
0x4809 6FFF
4KB
Module
0x4809 7000
0x4809 7FFF
4KB
L4 interconnect
McSPI1
0x4809 8000
0x4809 8FFF
4KB
Module
0x4809 9000
0x4809 9FFF
4KB
L4 interconnect
0x4809 A000
0x4809 AFFF
4KB
Module
0x4809 B000
0x4809 BFFF
4KB
L4 interconnect
0x4809 C000
0x4809 CFFF
4KB
Module
0x4809 D000
0x4809 DFFF
4KB
L4 interconnect
0x4809 E000
0x4809 EFFF
4KB
Module
0x4809 F000
0x4809 FFFF
4KB
L4 interconnect
0x480A 0000
0x480A FFFF
4KB
Module
0x480A 1000
0x480A 1FFF
4KB
L4 interconnect
0x480A 2000
0x480A 2FFF
4KB
Module
0x480A 3000
0x480A 3FFF
4KB
L4 interconnect
0x480A 4000
0x480A 4FFF
4KB
Module
0x480A 5000
0x480A 5FFF
4KB
L4 interconnect
0x480A 6000
0x480A 6FFF
4KB
Module
0x480A 7000
0x480A 7FFF
4KB
L4 interconnect
0x480A 8000
0x480A 8FFF
4KB
Module
0x480A 9000
0x480A 9FFF
4KB
L4 interconnect
0x480A B000
0x480A BFFF
4KB
Module
0x480A C000
0x480A CFFF
4KB
L4 interconnect
0x480A D000
0x480A DFFF
4KB
Module
0x480A E000
0x480A EFFF
4KB
L4 interconnect
Reserved
0x480A F000
0x480A FFFF
4KB
Reserved
Reserved
0x480B 0000
0x480B 0FFF
4KB
Module
0x480B 1000
0x480B 1FFF
4KB
Reserved
0x480B 2000
0x480B 2FFF
4KB
Reserved
0x480B 3000
0x480B 3FFF
4KB
L4 interconnect
0x480B 4000
0x480B 4FFF
4KB
Module
0x480B 5000
0x480B 5FFF
4KB
L4 interconnect
Unused
0x480B 6000
0x480B 7FFF
8KB
Unused
McSPI3
0x480B 8000
0x480B 8FFF
4KB
Module
0x480B 9000
0x480B 9FFF
4KB
L4 interconnect
0x480B A000
0x480B AFFF
4KB
Module
0x480B B000
0x480B BFFF
4KB
L4 interconnect
Unused
0x480B C000
0x480C 0FFF
20KB
Unused
DES3DES2
0x480C 1000
0x480C 1FFF
4KB
Module
0x480C 2000
0x480C 2FFF
4KB
L4 interconnect
0x480C 3000
0x480C 3FFF
4KB
Module
0x480C 4000
0x480C 4FFF
4KB
L4 interconnect
GPTIMER11
McSPI2
MMC/SD/SDIO1
UART4
RNG
DES3DES1
SHA2MD5
AES1
Fast PKA
USB High Speed 2.0
MMC/SD/SDIO3
HDQ/1-wire
MMC/SD/SDIO2
McSPI4
SHA1MD5 2
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Table 2-3. L4-Core Memory Space Mapping
(2)
(continued)
Start Address
(HEX)
End Address
(HEX)
Size
Description
0x480C 5000
0x480C 5FFF
4KB
Module
0x480C 6000
0x480C 6FFF
4KB
L4 interconnect
Unused
0x480C 7000
0x480C AFFF
16KB
Unused
SR2
0x480C B000
0x480C BFFF
4KB
Module
Device Name
AES2
0x480C C000
0x480C CFFF
4KB
L4 interconnect
Unused
0x480C D000
0x480C EFFF
8KB
Unused
CPFROM
0x480CF000
0x480C FFFF
4KB
Module
L4 interconnect
0x480D 0000
0x480D 0FFF
4KB
Reserved
0x480D 1000
0x481F FFFF
1212KB
Interrupt controller 1
0x4820 0000
0x4820 0FFF
4KB
Non-shared device
mapping
Reserved
0x4201 0000
0x482F FFFF
508KB
Non-shared device
mapping
S.M.
0x4828 0000
0x4828 0FFF
4KB
Non-shared device
mapping
Reserved
0x4828 1000
0x482F FFFF
506KB
Non-shared device
mapping
L4-Wakeup interconnect (region A)
0x4830 0000
0x4830 9FFF
40KB
Non-shared device
mapping
Control module ID code
0x4830 A000
0x4830 AFFF
4KB
See Table 2-4
0x4830 B000
0x4830 BFFF
4KB
L4 interconnect
0x4830 C000
0x4833 FFFF
208KB
See Table 2-4
0x4834 0000
0x4834 0FFF
4KB
L4 interconnect
0x4834 1000
0x48FF EFFF
13,052KB
L4-Wakeup interconnect (Region B)
Reserved
2.3.2.2
Reserved
Reserved
L4-Wakeup Memory Space Mapping
The L4-Wakeup interconnect is a 256Kbytes space composed of the L4-Wakeup interconnect
configuration registers and the module registers.
Table 2-4 describes the mapping of the registers for the L4-Wakeup interconnect.
NOTE: All memory spaces described as modules provide direct access to module registers outside
the L4-Wakeup interconnect. All other accesses are internal to the L4-Wakeup interconnect.
Table 2-4. L4-Wakeup Memory Space Mapping
Start Address
(HEX)
End Address
(HEX)
Size
L4-Wakeup
0x4830 0000
0x4833 FFFF
256KB
Reserved
0x4830 0000
0x4830 3FFF
16KB
Reserved
GPTIMER12
0x4830 4000
0x4830 4FFF
4KB
Module
Device Name
Description
0x4830 5000
0x4830 5FFF
4KB
L4 interconnect
Power and reset manager
• Power manager
• Reset manager
0x4830 6000
0x4830 7FFF
8KB
Module region A
0x4830 8000
0x4830 87FF
2KB
Module region B (1)
0x4830 8800
0x4830 8FFF
2KB
Reserved
0x4830 9000
0x4830 9FFF
4KB
L4 interconnect
Reserved
0x4830 A000
0x4830 BFFF
8KB
Reserved
(1)
The registers mapped in this range are shadow registers of the first 2Kbytes region A [0x4830 6000 - 0x4830 67FF]. Region A
and region B share the same port.
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Table 2-4. L4-Wakeup Memory Space Mapping (continued)
Start Address
(HEX)
End Address
(HEX)
Size
Description
0x4830 C000
0x4830 CFFF
4KB
Module
0x4830 D000
0x4830 DFFF
4KB
L4 interconnect
0x4831 0000
0x4831 0FFF
4KB
Module
0x4831 1000
0x4831 1FFF
4KB
L4 interconnect
Reserved
0x4831 2000
0x4831 3FFF
8KB
Reserved
WDTIMER2
0x4831 4000
0x4831 4FFF
4KB
Module
0x4831 5000
0x4831 5FFF
4KB
L4 interconnect
Reserved
0x4831 6000
0x4831 7FFF
8KB
Reserved
GPTIMER1
0x4831 8000
0x4831 8FFF
4KB
Module
0x4831 9000
0x4831 9FFF
4KB
L4 interconnect
Reserved
0x4831 A000
0x4831 FFFF
24KB
Reserved
32KTIMER
0x4832 0000
0x4832 0FFF
4KB
Module
0x4832 1000
0x4832 1FFF
4KB
L4 interconnect
Reserved
0x4832 2000
0x4832 7FFF
24KB
Reserved
L4-Wakeup configuration
0x4832 8000
0x4832 87FF
2KB
Address/protection (AP)
0x4832 8800
0x4832 8FFF
2KB
Initiator port (IP) L4Core
Device Name
WDTIMER1
GPIO1
Reserved
2.3.2.3
0x4832 9000
0x4832 9FFF
4KB
Link agent (LA)
0x4832 A000
0x4832 A7FF
2KB
Initiator port (IP) L4-Emu
0x4832 A800
0x4833 FFFF
86KB
Reserved
L4-Peripheral Memory Space Mapping
The L4-Per interconnect is a 1Mbyte space composed of the L4-Per interconnect configuration registers
and the module registers.
Table 2-5 describes the mapping of the registers for the L4-Per interconnect.
NOTE: All memory spaces described as modules provide direct access to the module registers
outside the L4-Per interconnect. All other accesses are internal to the L4-Per interconnect.
Table 2-5. L4-Peripheral Memory Space Mapping
Start Address
(HEX)
End Address
(HEX)
Size
L4-Per
0x4900 0000
0x490F FFFF
1MB
L4-Per configuration
0x4900 0000
0x4900 07FF
2KB
Address/protection (AP)
0x4900 0800
0x4900 0FFF
2KB
Initiator port (IP)
0x4900 1000
0x4900 1FFF
4KB
Link agent (LA)
Reserved
0x4900 2000
0x4901 FFFF
120KB
UART3
(Infrared)
0x4902 0000
0x4902 0FFF
4KB
Module
0x4902 1000
0x4902 1FFF
4KB
L4 interconnect
McBSP2
(Audio for codec)
0x4902 2000
0x4902 2FFF
4KB
Module
0x4902 3000
0x4902 3FFF
4KB
L4 interconnect
McBSP3
(Bluetooth voice data)
0x4902 4000
0x4902 4FFF
4KB
Module
0x4902 5000
0x4902 5FFF
4KB
L4 interconnect
McBSP4
(Digital baseband voice data)
0x4902 6000
0x4902 6FFF
4KB
Module
0x4902 7000
0x4902 7FFF
4KB
L4 interconnect
Device Name
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Description
Reserved
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Table 2-5. L4-Peripheral Memory Space Mapping (continued)
Start Address
(HEX)
End Address
(HEX)
Size
Description
0x4902 8000
0x4902 8FFF
4KB
Module
0x4902 9000
0x4902 9FFF
4KB
L4 interconnect
0x4902 A000
0x4902 AFFF
4KB
Module
0x4902 B000
0x4902 BFFF
4KB
L4 interconnect
Reserved
0x4902 C000
0x4902 FFFF
16KB
Reserved
WDTIMER3
0x4903 0000
0x4903 0FFF
4KB
Module
0x4903 1000
0x4903 1FFF
4KB
L4 interconnect
0x4903 2000
0x4903 2FFF
4KB
Module
0x4903 3000
0x4903 3FFF
4KB
L4 interconnect
0x4903 4000
0x4903 4FFF
4KB
Module
0x4903 5000
0x4903 5FFF
4KB
L4 interconnect
0x4903 6000
0x4903 6FFF
4KB
Module
0x4903 7000
0x4903 7FFF
4KB
L4 interconnect
GPTIMER5
0x4903 8000
0x4903 8FFF
4KB
Module
0x4903 9000
0x4903 9FFF
4KB
L4 interconnect
GPTIMER6
0x4903 A000
0x4903 AFFF
4KB
Module
0x4903 B000
0x4903 BFFF
4KB
L4 interconnect
0x4903 C000
0x4903 CFFF
4KB
Module
0x4903 D000
0x4903 DFFF
4KB
L4 interconnect
0x4903 E000
0x4903 EFFF
4KB
Module
0x4903 F000
0x4903 FFFF
4KB
L4 interconnect
0x4904 0000
0x4904 0FFF
4KB
Module
0x4904 1000
0x4904 1FFF
4KB
L4 interconnect
Reserved
0x4904 2000
0x4904 FFFF
56KB
Reserved
GPIO2
0x4905 0000
0x4905 0FFF
4KB
Module
0x4905 1000
0x4905 1FFF
4KB
L4 interconnect
0x4905 2000
0x4905 2FFF
4KB
Module
0x4905 3000
0x4905 3FFF
4KB
L4 interconnect
0x4905 4000
0x4905 4FFF
4KB
Module
0x4905 5000
0x4905 5FFF
4KB
L4 interconnect
0x4905 6000
0x4905 6FFF
4KB
Module
0x4905 7000
0x4905 7FFF
4KB
L4 interconnect
0x4905 8000
0x4905 8FFF
4KB
Module
0x4905 9000
0x4905 9FFF
4KB
L4 interconnect
0x4905 A000
0x490F FFFF
664KB
Device Name
McBSP2 (Sidetone)
McBSP3 (Sidetone)
GPTIMER2
GPTIMER3
GPTIMER4
GPTIMER7
GPTIMER8
GPTIMER9
GPIO3
GPIO4
GPIO5
GPIO6
Reserved
2.3.2.4
Reserved
L4-Emulation Memory Space Mapping
The L4-Emu interconnect is an 8Mbytes space composed of the L4-Emu interconnect configuration
registers and module registers.
Table 2-6 describes the mapping of the registers for the L4-Emu interconnect.
NOTE: All memory spaces described as modules provide direct access to the module registers
outside the L4-Emu interconnect. All other accesses are internal to the L4-Emu interconnect
158
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Table 2-6. L4-Emulation Memory Space Mapping
Start Address
(HEX)
End Address
(HEX)
Size
L4-Emu
0x5400 0000
0x547F FFFF
8MB
Reserved
0x5400 0000
0x5400 3FFF
16KB
Reserved
TEST chip-level TAP
0x5400 4000
0x5400 4FFF
4KB
Module
0x5400 5000
0x5400 5FFF
4KB
L4 interconnect
0x5400 6000
0x5400 67FF
2KB
Address/protection (AP)
0x5400 6800
0x5400 6FFF
2KB
Initiator port (IP) L4-Core
0x5400 7000
0x5400 7FFF
4KB
Link agent (LA)
0x5400 8000
0x5400 87FF
2KB
Initiator port (IP) DAP
Reserved
0x5400 8800
0x5400 FFFF
30KB
Reserved
MPU emulation
0x5401 0000
0x5401 7FFF
16KB
Module
0x5401 8000
0x5401 7FFF
4KB
L4 interconnect
0x5401 9000
0x5401 9FFF
4KB
Module
0x5401 A000
0x5401 AFFF
4KB
L4 interconnect
0x5401 B000
0x5401 BFFF
4KB
Module
0x5401 C000
0x5401 CFFF
4KB
L4 interconnect
0x5401 D000
0x5401 DFFF
4KB
Module
0x5401 E000
0x5401 EFFF
4KB
L4 interconnect
0x5401 F000
0x5401 FFFF
4KB
L4 interconnect
0x5402 0000
0x544F FFFF
4992KB
0x5450 0000
0x5450 FFFF
4KB
0x5451 0000
0x545F FFFF
1984KB
0x5460 0000
0x546F FFFF
1MB
SDTI module (window)
Reserved
0x5470 0000
0x5470 3FFF
16KB
Reserved
GPTIMER12
0x5470 4000
0x5470 4FFF
4KB
Module
0x5470 5000
0x5470 5FFF
4KB
L4 interconnect
Power and reset manager
• Power manager
• Reset manager
(WAKEUP domain (1))
0x5470 6000
0x5470 7FFF
8KB
Module region A
0x5470 8000
0x5470 87FF
2KB
Module region B (2)
0x5470 8800
0x5470 8FFF
2KB
Reserved
0x5470 9000
0x5470 9FFF
4KB
L4 interconnect
Reserved
0x5470 A000
0x5470 BFFF
8KB
Reserved
WDTIMER1
0x5470 C000
0x5470 CFFF
4KB
Module
0x5470 D000
0x5470 DFFF
4KB
L4 interconnect
Reserved
0x5470 E000
0x5470 FFFF
8KB
Reserved
GPIO1
(WAKEUP domain (1))
0x5471 0000
0x5471 0FFF
4KB
Module
0x5471 1000
0x5471 1FFF
4KB
L4 interconnect
Reserved
0x5471 2000
0x5471 3FFF
8KB
Reserved
WDTIMER2
(WAKEUP domain (1))
0x5471 4000
0x5471 4FFF
4KB
Module
0x5471 5000
0x5471 5FFF
4KB
L4 interconnect
Reserved
0x5471 6000
0x5471 7FFF
8KB
Reserved
GPTIMER1
(WAKEUP domain (1))
0x5471 8000
0x5471 8FFF
4KB
Module
0x5471 9000
0x5471 9FFF
4KB
L4 interconnect
Reserved
0x5471 A000
0x5471 FFFF
24KB
Reserved
32KTIMER
(WAKEUP domain (1))
0x5472 0000
0x5472 0FFF
4KB
Module
0x5472 1000
0x5472 1FFF
4KB
L4 interconnect
Device Name
L4-Emu configuration
TPIU
ETB
DAPCTL
SDTI
(1)
(2)
Description
Reserved
SDTI module
(configuration)
Reserved
These modules are accessed through the L4-Wakeup interconnect (for emulation purpose only).
The registers mapped in this range are shadow registers of the first 2Kbytes region A [0x5470 6000 - 0x5470 67FF]. Region A
and region B share the same port.
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Table 2-6. L4-Emulation Memory Space Mapping (continued)
Start Address
(HEX)
End Address
(HEX)
Size
Description
Reserved
0x5472 2000
0x5472 7FFF
24KB
Reserved
L4-Wakeup configuration
(WAKEUP domain (1))
0x5472 8000
0x5472 87FF
2KB
Address/protection (AP)
0x5472 8800
0x5472 8FFF
2KB
Initiator port (IP) L4-Core
0x5472 9000
0x5472 9FFF
4KB
Link agent (LA)
Device Name
0x5472 A000
0x5472 A7FF
2KB
Initiator port (IP) L4-Emu
Reserved
0x5472 A800
0x5472 FFFF
22KB
Reserved
L4 WKUP
0x5473 0000
0x5473 0FFF
4KB
Module
Reserved
0x5473 1000
0x547F FFFF
828KB
Reserved
2.3.3 Register Access Restrictions
This section gives information about all modules and features in the high-tier device. To check availability
of modules and features, see Chapter 1, Device Family. The memory area of unavailable modules and
features is RESERVED, read is undefined, and write can lead to unpredictable behavior.
Table 2-7 gives the supported data access widths per module.
Table 2-7. Register Access Restrictions
Module
Allowed Access
MPU subsystem
8-bit/16-bit/32-bit
IPSS
32-bit
SGX
32-bit
Display subsystem
32-bit
GPMC
8-bit/16-bit/32-bit
SMS
8-bit/16-bit/32-bit
EMIF4
8-bit/16-bit/32-bit
sDMA
8-bit/16-bit/32-bit
HS USB HOST
32-bit
USBTLL
32-bit
USB - ULPI and UTMI registers
8-bit/16-bit/32-bit
L4-Wakeup interconnect
8-bit/16-bit/32-bit
L4-Core interconnect
8-bit/16-bit/32-bit
Clock manager
32-bit
Power and reset manager
32-bit
System control module
32KTIMER
GPIO
8-bit/16-bit/32-bit
16-bit/32-bit
8-bit/16-bit/32-bit
GPTIMER
16-bit/32-bit
WDTIMER
16-bit/32-bit
I2C
8-bit/16-bit
HDQ/1-wire
McBSP
32-bit
32-bit
Sidetone
8-bit/16-bit/32-bit
McSPI
8-bit/16-bit/32-bit
UART
8-bit/16-bit/32-bit
MMC/SD/SDIO
MPU INTC
160
8-bit
L3 interconnect
Memory Mapping
32-bit
16-bit/32-bit
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Table 2-7. Register Access Restrictions (continued)
Module
Allowed Access
SR
8-bit/16-bit/32-bit
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IPSS Memory Space Mapping
2.4.1 L3 Interconnect View of the IPSS Memory Space
Table 2-8 lists the IPSS memory space mapping from the perspective of the MPU subsystem through the
L3 interconnect.
Table 2-8. L3 Interconnect View of the IPSS Memory Space
162
Region Name
Start Address
(HEX)
End Address
(HEX)
Size
CPGMAC-TOP
0x5C00 0000
0x5C00 00FF
256B
Reserved
0x5C00 0100
0x5C00 FFFF
63.75KB
CPGMAC-CPGMAC
0x5C01 0000
0x5C01 07FF
2KB
Reserved
0x5C01 0800
0x5C01 FFFF
62KB
CPGMAC-CPPI
0x5C02 0000
0x5C02 1FFF
8KB
Reserved
0x5C02 2000
0x5C02 FFFF
56KB
CPGMAC-MDIO
0x5C03 0000
0x5C03 00FF
256B
Reserved
0x5C03 0100
0x5C03 FFFF
63.75KB
USBOTGSS
0x5C04 0000
0x5C04 7FFF
32KB
Reserved
0x5C04 8000
0x5C04 FFFF
32KB
HECC
0x5c05 0000
0x5C05 3FFF
16KB
Reserved
0x5C05 4000
0x5C05 FFFF
48KB
VPFE
0x5c06 0000
0x5C06 FFFF
64KB
Reserved (valid)
0x5C07 0000
0x5EFF FFFF
47.56MB
Memory Mapping
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved. Null response
is provided by SCR
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Chapter 3
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MPU Subsystem
This chapter describes the microprocessor unit (MPU) subsystem.
Topic
3.1
3.2
3.3
3.4
...........................................................................................................................
MPU
MPU
MPU
MPU
Subsystem
Subsystem
Subsystem
Subsystem
Overview ................................................................................
Integration ..............................................................................
Functional Description .............................................................
Basic Programming Model .......................................................
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Page
164
166
174
180
163
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3.1
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MPU Subsystem Overview
3.1.1 Introduction
The MPU subsystem of the device handles transactions among the ARM core, the L3 interconnect, and
the interrupt controller (INTC).
The MPU subsystem is a hard macro that integrates the ARM subchip with additional logic for protocol
conversion, emulation, interrupt handling, and debug enhancements. Figure 3-1 is a high-level block
diagram of the MPU subsystem.
Figure 3-1. MPU Subsystem Overview
MPUSS
ARM Cortex-A8
NEON
MPU_INTC_FIQ
AXI
MPU_INTC_IRQ
Trace/debug
AXI
Interrupts
INTC
MOCP
(P)
AX2OCPI
MOCP
(L3)
MPU
clock
generator
PRCM
Emulation/
(ICE-Crusher)
To L3
I2Async
mpuss-001
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3.1.2 Features
The MPU subsystem integrates the following:
• ARM subchip
– Public ARM Cortex™-A8 core
– ARM version 7 ISA: Standard ARM instruction set + Thumb-2™, Jazelle® RCT Java accelerator,
and media extensions
– Neon single instruction, multiple data (SIMD) coprocessor (VFP light + media streaming
instructions)
– Cache memories
• Level 1: 16-KB instruction and 16-KB data caches – 4-way associative, 64 bytes/line
• Level 2: See Section 1.4, .
– Emulation/debug
• INTC of 96 synchronous level-sensitive interrupt lines (For details, see Chapter 8, Interrupt Controller.)
• AXI2OCP bridge between ARM AXI bus, L3 master open-core protocol (OCP) bus, and INTC master
OCP bus
• MPU clock generator: Clock generation module that generate clocks, power modes, and idle and
active acknowledge signals
• Debug, trace, and emulation features: ICECrusher™, embedded trace macrocell (ETM), advanced
peripheral bus (APB) modules. Cortex-A8 MPU implements an APB slave interface that allows access
to ETM, ICECrusher, and debug registers.
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MPU Subsystem Integration
The MPU subsystem integrates the following group of submodules:
• Public ARM Cortex-A8 MPU: Provides a high processing capability, including the Neon technology for
mobile multimedia acceleration. The ARM communicates through an AXI bus with the AXI2OCP bridge
and receives interrupts from the MPU INTC.
• INTC: Handles module interrupts (for details, see Chapter 8, Interrupt Controller).
• AXI2OCP bridge: Allows communication among the ARM (AXI), the INTC (OCP), and the modules
(OCP L3).
• I2Async bridge: An asynchronous bridge interface providing an asynchronous OCP-to-OCP interface.
This interface is between the AXI2OCP bridge in the MPU subsystem and the T2Async bridge external
to the MPU subsystem. The T2Async bridge connects to OCP L3.
• MPU clock generator: Provides clocks to internal modules of the MPU subsystem; fed by the MPU
digital phase-locked loop (DPLL) of the power, reset, and clock management (PRCM) module of the
device. The MPU DPLL generates the clock for the ARM Cortex-A8 CPU and the Cortex-A8 MPU
subsystem logic. The power, reset, and MPU DPLL source clock are generated from the device PRCM
module.
Figure 3-2 shows the signals that interface with the external modules.
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Figure 3-2. MPU Subsystem Integration Overview
Device
MPU subsystem
NEON_RST
ARM Cortex-8
MPU_INTC_FIQ
MPU_INTC_IRQ
AXI
MPU_MSTANDBY
NEON
Device
modules
Interrupts
sys_nirq
PRCM
INTC
AXI
CORE_RST
MOCP
(P)
AXI2OCP
MOCP
(P)
MPU
clock
generator
MPU_CLK
L3_ICLK
MPU_RST
I2Async
Non-OCP
Level T2Async
shift
L3
mpuss-002
NOTE: Some debug, trace, and emulation features are implemented in the MPU subsystem. This
chapter includes only clock/reset inputs and power-management aspects for these features.
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3.2.1 MPU Subsystem Clock and Reset Distribution
3.2.1.1
Clock Distribution
The MPU subsystem includes a clock generator block that supplies clocks for the modules in the MPU
subsystem. It is fed by the MPU_CLK clock from the PRCM module.
All major modules in the MPU subsystem are clocked at half the frequency of the ARM core. The divider
of the output clock can be programmed with the PRCM.CM_CLKSEL2_PLL_MPU[4:0]
MPU_DPLL_CLKOUT_DIV bit field; the frequency is relative to the ARM core. For details see , Power,
Reset, and Clock Management (PRCM) module . The clock generator generates the following functional
clocks:
• ARM (ARM_FCLK): This is the core clock. It is the base fast clock that is routed internally to the ARM
logic and internal RAMs, including Neon, L2 cache, the ETM core (emulation), and the ARM core. It
runs at one half the frequency of the MPU_CLK when DPLL1 is locked, and runs at the same
frequency as the MPU_CLK when DPLL1 is bypassed.
• AXI2OCP clock (AXI_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). The
OCP interface thus performs at one half the frequency of ARM.
• INTC functional clock (MPU_INTC_FCLK): This clock, which is part of the INTC module, is half the
frequency of the ARM clock (ARM_FCLK).
• ICE-Crusher functional clock (ICECRUSHER_FCLK): ICECrusher clocking operates on the APB
interface, using the ARM core clocking.
• I2Async clock (I2ASYNC_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). It
matches the OCP interface of the AXI2OCP bridge.
NOTE: The second half of the asynchronous bridge (T2ASYNC) is clocked directly by the PRCM
module with the core clock. T2ASYNC is not part of the MPU subsystem.
Emulation clocking: Except for the ICECrusher functional clock, which is provided by the MPU DLL, the
emulation modules in the MPU subsystem are not generated by the MPU subsystem DPLL, but by an
EMU DPLL. These clocks (EMU_CLOCKS) are distributed by the PRCM module, are asynchronous with
the ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock.
Figure 3-3 shows the MPU subsystem clocking scheme.
Figure 3-3. MPU Subsystem Clocking Scheme
MPU SS
INTC_FCLK (ARM_FCLK/2)
INTC
AXI2OCP_FCLK (ARM_FCLK/2)
AXI2OCP
MPU_CLK
PRCM
MPU
Clock
Generator
I2ASYNC_FCLK (ARM_FCLK/2)
ICECRUSHER_FCLK (ARM_FCLK/2)
I2Async
IceCrusher
ARM_FCLK
ARM Cortex-A8
EMU
DPLL
EMU_CLOCKS
Emulation/
trace/debug
mpuss-003
Table 3-1 lists the clocks generated in the MPU subsystem by the MPU clock generator.
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Table 3-1. MPU Clock Generator Clock Signals
Signal Name
3.2.1.2
I/O
Interface
Comments
MPU_CLK
I
PRCM
MPU DPLL clock out
ARM_FCLK
O
ARM
ARM functional clock
MPU_INTC_FCLK
O
MPU INTC
MPU INTC functional clock
I2ASYNC_FCLK
O
I2Async
I2Async functional clock
AXI_FCLK
O
AXI2OCP
AXI2OCP functional clock
ICECRUSHER_FCLK
O
ICE-Crusher
ICECrusher functional clock
Reset Distribution
Resets to the MPU subsystem are provided by the PRCM module and controlled by the clock generator
module. There are as many reset signals as power domains. For details about power domains, see
Section 3.3.2.1. Figure 3-4 shows the reset scheme of the MPU subsystem.
Figure 3-4. MPU Subsystem Reset Scheme
MPU Subsystem
CORE_RST
INTC
MPU_RST
AXI2OCP
I2Async
PRCM
ARM Cortex-A8
NEON_RST
NEON
EMU_RST
EMU
EMU_RSTPWRON
MPU_RSTPWRON
IceCrusher
108-004
Table 3-2. MPU Subsystem Reset Signals
Signal Name
I/O
Interface
Comments
MPU_RST
I
PRCM
MPU power domain reset
Neon_RST
I
PRCM
Neon power domain reset
CORE_RST
I
PRCM
CORE power domain reset
MPU_RSTPWRON
I
PRCM
ICECrusher reset. It is active only on cold reset.
EMU_RST
I
PRCM
Emulation interconnect reset
EMU_RSTPWRON
I
PRCM
Emulation modules reset
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For details about clocks, resets, and power domains, see , Power, Reset, and Clock Management.
3.2.2 ARM Subchip
3.2.2.1
ARM Overview
The public ARM Cortex-A8 processor incorporates the technologies available in the ARM7 architecture.
These technologies include Neon for media and signal processing and Jazelle RCT for acceleration of
realtime compilers, Thumb-2 technology for code density and the VFPv3 floating-point architecture.
For details, see the public ARM Cortex-A8 Technical Reference Manual.
3.2.2.2
ARM Description
3.2.2.2.1 Public ARM Cortex-A8 Instruction, Data, and Private Peripheral Port
The AXI bus interface is the main interface to the ARM system bus. It performs L2 cache fills and
noncacheable accesses for instructions and data. The AXI interface supports 64-bit wide input and output
data buses. It supports multiple outstanding requests on the AXI bus and a wide range of bus clock-tocore clock ratios. The bus clock is synchronous with the core clock.
See the public ARM Cortex-A8 Technical Reference Manual for a complete programming model of the
transaction rules (ordering, posting, and pipeline synchronization) that are applied depending on the
memory region attribute associated with the transaction destination address.
3.2.2.2.2 MPU Subsystem Features
Table 3-3 is a list of main functionalities of the ARM core supported in the MPU subsystem for the device.
The MPU subsystem implements the ARM7™ instruction set architecture.
Table 3-3. ARM Core Key Features
Feature
Comment
ARM version 7 ISA
Standard ARM instruction set + Thumb-2, Jazelle RCT Java accelerator, and media
extensions. Backward-compatible with previous ARM ISA versions.
L1 Icache and Dcache
16KB, 4-way, 64-byte cache line, and 128-bit interface. Note: L1 memories cannot be put in
retention mode.
L2 Cache
The L2 cache and cache controller are embedded in the ARM core. For size, see
Section 1.4, .
TLB
Fully associative and separate ITLB with 32 entries and DTLB with 32 entries
CoreSight ETM
The CoreSight ETM is embedded in the ARM core. The 4KB buffer (ETB) exists at the
device level.
Branch target address cache
512 entries
Enhanced Memory Management Unit
Mapping sizes are 4KB, 64KB, 1MB, and 16MB. ARM MMU adds extended physical
address ranges.
Neon
Enhances throughput for media workloads and VFP-Lite support
Tightly coupled memory
Not present
AXI Bus
Separate 64-bit input and 64-bit output data buses. The public ARM Cortex-A8 has a single
AXI bus interface. The AXI interface is shared by instruction fetches, data accesses,
peripheral accesses and PLE (on-chip preload engine, previously known as DMA)
accesses. DMA is available.
Low interrupt latency
Interrupt request (IRQ) and fast interrupt request (FIQ) are directly connected to ARM and
INTC is before L3.
Vectored Interrupt Controller Port
Not used
JTAG based debug
Supported through debug access port (DAP)
Trace support
Supported through trace port interface unit (TPIU)
External coprocessor
Not supported
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For more information, see the public ARM Cortex-A8 Technical Reference Manual.
3.2.2.3
Clock, Reset, and Power Management
3.2.2.3.1 Clocks
Table 3-4 shows the ARM functional clock. For configuration, see , Power, Reset, and Clock
Management.
Table 3-4. MPU Subsystem Clock Signal
Signal Name
ARM_FCLK
I/O
Interface
I
MPU Clock Generator
Comments
Functional clock
3.2.2.3.2 Reset
Table 3-5 lists the resets for the ARM. They include the power domain reset, Neon_RST, which resets the
Neon module of the ARM subchip only, and MPU_RST, which resets the rest of the ARM subchip and the
AXI2OCP and I2Async bridges.
Table 3-5. ARM Reset Signals
Signal Name
I/O
Interface
MPU_RST
I
PRCM
Comments
MPU power domain reset
Neon_RST
I
PRCM
Reset Neon only
EMU_RST
I
PRCM
Emulation interconnect reset
EMU_RSTPWRON
I
PRCM
Emulation modules reset
3.2.2.3.3 Power Management
For details, see Section 3.3.2.
3.2.3 AXI2OCP and I2Async Bridges
3.2.3.1
Bridges Overview
The AXI2OCP bridge connects the AXI bus on the ARM MPU to the OCP native L3 interconnect and
INTC. It converts between AXI and OCP protocols and maintains a mapping of AXI tags to the OCP
thread ID. This bridge is responsible for some minimal address decoding to determine where to forward
requests between L3 and INTC.
Bridging to the L3 is accomplished through an asynchronous interface involving the I2Async and T2Async
modules. The I2Async module in the MPU subsystem has an OCP port that is asynchronously transferred
to the T2Async module and routed to the L3. T2Async is outside the MPU subsystem.
NOTE: The interface between I2Async and T2Async is not an OCP protocol.
Figure 3-5 is an overview of the AXI2OCP and the L3 bridges.
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Figure 3-5. Bridges Overview
MPUSS
To ARM
AXI (64 bit)
AXI slave
AXI2OCP_FCLK
OCP
Master(INTC)
OCP2.0 (32 bit)
To INTC
AXI2OCP
MPU_RST
OCP Master
(L3)
OCP2.0 (64 bit)
I2ASYNC_CLK
I2Async
No OCP
Levelshift
T2Async
L3
mpuss-006
3.2.3.2
AXI2OCP Description
The AXI2OCP bridge key features are:
• Connection to the L3 interconnect through a 64-bit OCP port. Address bus is 32-bit.
• Connection to the INTC through a 32-bit OCP port (only single transactions are supported)
• Support of single-request-multiple-data (data handshaking) burst mode to pipeline requests to L3.
Bursts with width less than 64 bits are converted as single requests on L3. This can affect system
performance. The INTC does not support burst transfers
• Support of multiple outstanding requests
• Remapping of the AXI tags to five OCP threads:
– Instruction fetch (Thread_IR)
– Cacheable data read (Thread_CR)
– Cacheable data write (Thread_CW)
– Noncacheable data read (Thread_DR)
– Noncacheable data write (Thread_DW)
• Interface to the L3 through the asynchronous bridge (I2Async)
• Emulation and support of boot-mode translation
• Translation of exclusive accesses to nonexclusive read/write in the bridge
• Boot mode address translation
• Force write nonposted support
• Debug related: Ready fail, force ready
• Interconnect attach neutralizer
• Narrow burst support
• Time-out counter for nonresponsive slaves on OCP
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3.2.3.3
Clocks, Reset, and Power Management
3.2.3.3.1 Clocks
Table 3-6 lists the bridge functional clocks.
Table 3-6. Bridge Clock Signals
Signal Name
I/O
Interface
AXI2OCP_FCLK
I
MPU Clock Generator
Comments
AXI2OCP functional clock
I2ASYNC_FCLK
I
MPU Clock Generator
I2Async functional clock
3.2.3.3.2 Reset
Table 3-7 lists the bridge reset. It is a power domain reset that also resets the ARM.
Table 3-7. MPU Subsystem Reset Signal
Signal Name
MPU_RST
I/O
Interface
I
PRCM
Comments
MPU power domain reset
3.2.3.3.3 Power Management
For details, see Section 3.3.2.
3.2.4 Interrupt Controller
For information, see Chapter 8, Interrupt Controllers.
3.2.4.1
Clocks
Table 3-8 lists the INTC clocks.
Table 3-8. Bridge Clock Signals
Signal Name
3.2.4.2
I/O
Interface
MPU_INTC_FCLK
I
MPU Clock Generator
Comments
INTC functional clock
MPU_INTC_ICLK
I
OCP Clock
INTC interface clock
Reset
Table 3-9 lists the reset of the INTC. It is a power domain reset that resets the entire CORE power
domain. For details, see Chapter 8, Interrupt Controller and , Power, Reset, and Clock Management.
Table 3-9. MPU Subsystem Reset Signal
3.2.4.3
Signal Name
I/O
Interface
CORE_RST
I
PRCM
Comments
CORE power domain reset
Power Management
See Chapter 8, Interrupt Controller, and , Power, Reset, and Clock Management.
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MPU Subsystem Functional Description
3.3.1 Interrupts
The MPU INTC is connected to the MPU through the AXI2OCP bridge. It runs at half-processor speed.
The INTC prioritizes all service requests from the system peripherals and generates an IRQ or an FIQ to
the MPU, depending on the INTC programming. The INTC handles only interrupts directed to the MPU
subsystem. A maximum of 96 requests can be steered/prioritized as MPU FIQ or IRQ interrupt requests.
For details, see Chapter 8, Interrupt Controller.
3.3.2 Power Management
3.3.2.1
Power Domains
The MPU subsystem is divided into five power domains controlled by the PRCM module, as shown in
Figure 3-6. The EMU and CORE power domains are not fully embedded in the MPU subsystem.
Figure 3-6. MPU Subsystem Power Domain Overview
MPU subsystem
MPU_RST
MPU domain
ARM Cortex™-A8
I2Async
AXI2OCP
SRAM L1
SRAM L2
MPU_RSTPWRON
IceCrusher
EMU_RSTPWRON
Emulation domain
EMU_RST
NEON_RST
NEON domain
INTC
CORE_RST
Core domain
mpuss-007
Power-management requirements at the device level govern power domains for the MPU subsystem.
The device-level power domains are directly aligned with voltage domains and thus can be represented as
a cross reference to the different voltage domains. Table 3-10 shows the power domains of the MPU
subsystem and the modules inside it.
Table 3-10. Overview of the MPU Subsystem Power Domain
Functional Power Domain
Physical Power Domain per System/Module
MPU subsystem domain
ARM, AXI2OCP, I2Asynch Bridge, ARM L1 and L2 periphery logic and array, ICECrusher, ETM,
APB modules
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Table 3-10. Overview of the MPU Subsystem Power Domain (continued)
Functional Power Domain
Physical Power Domain per System/Module
MPU Neon domain
ARM Neon accelerator
CORE domain
MPU INTC
EMU domain
EMU (ETB, DAP)
NOTE: L1 and L2 array memories have separate control signals to the MPU subsystem; thus are
directly controlled by the PRCM module.
For information about the physical power domains and the voltage domains, see , Power, Reset, and
Clock Management.
3.3.2.2
Power States
Each power domain can be driven by the PRCM module in four power states, depending on the functional
mode required by the user.
Table 3-11. MPU Power States
Power State
Logic Power
Memory Power
Clocks
Memory State Retention
ACTIVE
On
On or Off
On (at least one clock)
All
INACTIVE
On
On or Off
Off
All
RETENTION
On or Off
On or Off
Off (all clocks)
All or part
OFF
Off
Off
Off (all clocks)
None
For each power domain, the PRCM module manages all transitions by controlling domain clocks, domain
resets, domain logic power switches, memory power switches, and memory retention. The MPU DPLL
internally synchronizes the internal clocks, resets, and switches.
3.3.2.3
Power Modes
MPU DPLL power modes:
The PRCM.CM_AUTOIDLE_PLL_MPU[2:0] AUTO_MPU_DPLL bit field lets the MPU DPLL be put in an
auto-idle mode when set to 0x1. In this mode, the MPU DPLL is automatically put in low power stop mode
when the MPU clock is not required. It is also restarted automatically. Table 3-12 describes the power
modes of the MPU DPLL in auto-idle or manual mode. The manual modes (locked and low-power bypass)
can be configured by the PRCM.CM_CLKEN_PLL_MPU[2:0] EN_MPU_DPLL bit field. The status of the
MPU DPLL clock activity can be checked with the PRCM.CM_IDLEST_PLL_MPU[0] ST_MPU_CLK bit.
Table 3-12. MPU DPLL Power Modes
Mode
System
Input Clock
Clock
Output
DPLL
Power
State
Condition
Locked
ON
ON
ON
Software request
(manual) or MPU
wakes up (auto)
Lowpower
bypass
ON
ON
ON
Software request
(manual) or on global
reset release (auto)
Stop low
power
OFF
OFF
ON
MPU is RET or OFF
(auto).
OFF
OFF
OFF
OFF
Device is OFF (auto).
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The MPU DPLL power domain is switched off automatically by the PRCM module only when the device
enters OFF mode.
MPU subsytem power modes:
The major part of the MPU subsystem belongs to the MPU power domain. Modules in this power domain
can be off when the ARM processor is in OFF or standby mode. IDLE/WAKEUP control is managed by
the clock generator block, but initiated by the PRCM module. The MPU standby status can be checked
with the PRCM.CM_IDLEST_MPU[0] ST_MPU bit.
For the MPU to be on, the core (referred to here as the device core) power must be on.
Device power management does not allow INTC to go to OFF state when the MPU domain is on (active or
one of the retention modes).
The Neon core is in independent power off mode when not in use. Enabling and disabling of Neon can be
controlled by software.
The MPU retention modes are described in Table 3-13.
Table 3-13. MPU Retention Modes
Name
ARM Logic
L1
L2
Dormant
OFF
OFF
RET
RET
RET
RET
RET
Table 3-14 lists the supported operational power modes. All other combinations are illegal. The ARM L2,
Neon, and ETM/debug can be powered up/down independently. The APB/ATB ETM/Debug column refers
to all three features: ARM emulation, trace, and debug.
Table 3-14. MPU Subsystem Operation Power Modes
(1)
176
Mode
MPU and ARM
Core Logic
ARM L2 RAM
Neon
OMAP Core
INTC
APB/ATB
ETM/Debug
Comments
1
Active
Active
Active
Active
Disabled or enabled Functional active
run mode (ETM
enabled mode when
emulation/debug
required. Production
devices should have
ETM disabled).
2
Active
Active
OFF
Active
Disabled or enabled Functional active
run mode. Neon
disabled through
software; Neon is
internally clockgated.
3
Active
RET
Active
Active
Disabled or enabled Do not use; see
(1)
.
4
Active
RET
OFF
Active
Disabled or enabled Do not use; see
(1)
.
5
Active
OFF
Active
Active
Disabled or enabled Active mode; L2 is
off. Controlled
through software to
the PRCM module.
L2 context save and
restore required or
L2 flush.
6
Active
OFF
OFF
Active
Disabled or enabled Active mode; L2 is
off. Controlled
through software to
the PRCM module.
L2 context save and
restore required or
L2 flush.
The L2 can be put in retention mode regardless of other voltage domain states. The combination of Cortex Logic active and L2 in
retention mode (modes 3 and 4) is legal, but results in incorrect execution of instructions with referencing data from L2. This combination
must not be used.
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Table 3-14. MPU Subsystem Operation Power Modes (continued)
Mode
MPU and ARM
Core Logic
ARM L2 RAM
Neon
OMAP Core
INTC
APB/ATB
ETM/Debug
Comments
7
OFF
RET
OFF
OFF
Disabled or enabled Lowest power sleep
mode (dormant
mode); L2 is in
retention. Controlled
through software to
the PRCM module.
ARM core and L1
context save and
restore required or
L1 flush.
8
Standby
Active
Standby
Active
Disabled or enabled Standby mode.
StandbyWFI (wait
for interrupt)
controlled to put into
standby and
wakeup through
interrupt.
9
Standby
Active
OFF
Active
Disabled or enabled Standby mode.
StandbyWFI
controlled to put into
standby and
wakeup through
interrupt when Neon
is off.
10
Standby
RET
Standby
Active
Disabled or enabled Standby mode
(retention mode).
StandbyWFI
controlled to put into
standby and
wakeup through
interrupt when L2 is
in retention.
11
Standby
RET
OFF
Active
Disabled or enabled Standby mode
(retention mode).
StandbyWFI
controlled to put into
standby and
wakeup through
interrupt when L2 is
in retention and
Neon is off.
12
Standby
OFF
Standby
Active
Disabled or enabled Standby mode.
StandbyWFI
controlled to put into
standby and
wakeup through
interrupt when L2 is
off.
13
Standby
OFF
OFF
Active
Disabled or enabled Standby mode.
StandbyWFI
controlled to put into
standby and
wakeup through
interrupt when L2
and Neon are off.
14
OFF
OFF
OFF
OFF
Disabled or enabled Power-down mode
In any mode where the MPU or Neon power domains are active, the MPU DPLL clocks must be active
(modes 1, 3, and 5 require active clocks from the DPLL, while modes 7 and 8 do not).
Thus, the MPU DPLL must be in one of the following states:
• Locked
• Low-power bypass: inclk = on, clkout = on, power = on
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When the MPU DPLL is not providing clocks, the MPU subsystem must be in a power mode where the
MPU power domain, Neon power domain, debug power domain, and INTC power domain are in standby,
RETENTION, or OFF state. The states of the MPU DPLL can be:
• Locked
• STOP low power
• OFF
CAUTION
The L2 can be put into retention mode regardless of other voltage domain
states. The combination of ARM Logic active and L2 in retention mode (modes
3 and 4) is legal, but results in incorrect execution of instructions with
referencing data from L2. This combination must not be used.
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3.3.2.4
Transitions
Table 3-15 describes allowable transitions from power modes described in Table 3-14. For example, a
transition from mode 13 to mode 4 is allowed, but the reverse is not true, because the L2 RET to OFF is
illegal.
Any mode change that requires state saving or flush must be serialized. For example, L2 RET does not
require state saving, so it can happen at the same time as power-down Neon. L2 off and Neon off cannot
happen at the same time, because L2 flush and Neon state saving must be serialized. Standby mode can
enter from active mode only by executing the WFI instruction.
Table 3-15. Power Mode Allowable Transitions
To Power Mode
From
1
2
3
4
5
1
Y
Y
Y
Y
Y
2
Y
Y
Y
Y
3
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
5
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
6
6
7
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
Y
Y
Y
Y
Y
Y
14
Y
Y
Y
Y
Y
Y
Y
Y
11
12
13
14
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
10
Y
Y
Y
9
Y
Y
Y
8
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
For more information about clocks, reset, power management, and wake-up events for the MPU
subsystem, see , Power, Reset, and Clock Management.
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MPU Subsystem Basic Programming Model
For detailed descriptions of registers used for MPU configuration, see , Power, Reset, and Clock
Management, and Chapter 8, Interrupt Controller.
3.4.1 Clock Control
For clock configuration settings, see , Power, Reset, and Clock Management.
3.4.2 MPU Power Mode Transitions
The following subsections describe transitions of different power modes for the MPU power domain:
• Basic power on reset
• MPU to standby mode
• MPU out of standby mode
• MPU power on from a powered-off state
3.4.2.1
Basic Power-On Reset
The following power-on reset (POR) sequence applies to initial power-up and wakeup from device off
mode:
1. Reset DPLL, supply reference clock, program the MPU DPLL in applicable DPLL mode to generate
clocks for MPU subsystem modules. This is controlled solely by the PRCM module.
2. Reset the INTC (CORE_RST) and the MPU subsystem modules (MPU_RST). The clocks must be
active during MPU reset and CORE reset.
3.4.2.2
MPU to Standby Mode
The following MPU to standby mode sequence applies to initial power-up and wakeup from device off
mode:
1. The ARM core initiates entering standby through software only (CP15 - WFI).
2. MPU modules requested internally by MPU subsystem to enter idle, after ARM core standby detected.
3. MPU is in standby output asserted for the PRCM module (all outputs ensured to be at reset values).
4. The PRCM module requests the INTC to enter idle mode. Acknowledge from INTC goes to the PRCM
module.
5. The PRCM module starts to shut down clocks through DPLL programming.
NOTE: The INTC SWAKEUP output is a pure hardware signal to the PRCM module for the status of
its IDLE request and IDLE acknowledge handshake.
NOTE: In debug mode, ICECrusher can prevent the MPU subsystem from entering IDLE mode.
3.4.2.3
MPU Out of Standby Mode
The following MPU out of standby mode sequence of operation applies to initial power-up and wakeup
from device off mode:
1. PRCM must start clocks through DPLL programming.
2. Detect active clocking through status output of DPLL.
3. Initiate an interrupt through the INTC to wake up the ARM core from STANDBYWFI mode.
3.4.2.4 MPU Power-On from a Powered-Off State
1. To minimize the peaking of current during power up, DPLL power on, MPU power on, Neon power on,
and Core power on (INTC) should follow the ordered sequence per power switch daisy chain.
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NOTE: Before the MPU can be reset, the CORE power domain must be on, and reset, with the
DPLL clocks on.
2. Follow the reset sequence as described in Section 3.4.2.1, Basic Power-On Reset.
3.4.3 Neon Power Mode Transition
Because of the hardware sleep dependency between Neon and the MPU domain, when the Neon power
domain transition is configured to automatic hardware-supervised mode (the CM_CLKSTCTRL_Neon[1:0]
CLKTRCTRL_Neon bit field is set to 0x3), it cannot transition to idle mode unless the MPU goes to
standby mode. The MPU domain must also be configured in automatic hardware-supervised mode (the
CM_CLKSTCTRL_MPU[1:0] CLKTRCTRL_MPU bit field must be set to 0x3) for the Neon power domain
transition to occur.
3.4.4 ARM Programming Model
For the complete programming model, see the public ARM Cortex-A8 Technical Reference Manual.
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Power, Reset, and Clock Management
This chapter describes power, reset, and clock management.
Topic
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
182
...........................................................................................................................
PRCM Introduction to Power Management ..........................................................
PRCM Overview ...............................................................................................
PRCM Environment ..........................................................................................
PRCM Integration ............................................................................................
PRCM Reset Manager Functional Description .....................................................
PRCM Power Manager Functional Description ....................................................
PRCM Clock Manager Functional Description .....................................................
PRCM Idle and Wake-Up Management ................................................................
PRCM Interrupts ..............................................................................................
PRCM Voltage Management Functional Description ............................................
PRCM Basic Programming Model ......................................................................
PRCM Registers ..............................................................................................
Revision History ..............................................................................................
Power, Reset, and Clock Management
Page
183
187
190
193
197
215
218
273
284
285
286
313
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4.1
PRCM Introduction to Power Management
This introduction contains the following information:
• Requirement and goal of power management in mobile devices
• State-of-the-art power-management techniques for maximizing battery life for mobile devices
• Essential architectural building blocks for power management
• Overview of the device power-management architecture
NOTE: Some features may not be available or supported in your particular device. For more
information, see Chapter 1, the Device Family section, and your device-specific data manual.
4.1.1 Goal of Power Management
Power management (efficient use of the available limited battery resources of a mobile device) is one of
the most important design aspects of any mobile system. It imposes strong control over limited available
power resources to ensure they function for the longest possible amount of time.
The device architecture ensures maximum performance for user satisfaction (audio/video support) while
offering versatile power-management techniques for maximum design flexibility, depending on application
requirements.
4.1.2 Architectural Blocks for Power Management
The processor does not support Voltage and Power domains. As a result, there is one voltage supply to
the device processors and peripherals. There is also no support for switching power on or off to individual
power domains. Although the power domain terminology is retained, the state of power to all domains is
either ON when the device is supplied with external power, or OFF when the external power source to the
device is off.
The device does support dynamic clock gating for power management through clock domains. A clock
domain is a group of modules or subsections of the device that share a common clock.
4.1.2.1
Clock Domain
A clock domain is a group of modules fed with the same gated clock signal (see Figure 4-1). By gating the
clock to each domain, it is possible to cut a clock to a group of inactive modules to lower their active
power consumption. Thus, a clock domain allows control of dynamic power consumption by the device.
Figure 4-1. Generic Clock Domain
CLK
Ctrl
Ctrl
CLK2
CLK1
Subsystem A
Subsystem B
Clock domain CLK1
Subsystem C
Clock domain CLK2
prcm-005
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Table 4-1 lists the two possible states of the clock domain.
Table 4-1. States of a Clock Domain
State
Active
Idle
4.1.2.2
Description
The domain clock is running.
The domain clock is stopped or gated.
Power Domain
Some members of the device family support independent control of power to subsections of the device
(called Power Domains) via independent power switches. While retaining some of the Power Domain
terminology, this device does not support independent Power Domain control. The state of all Power
Domains in the device is either ON when the device is externally supplied with power or OFF when the
device is completely powered down. In effect, the entire device is a single power domain.
4.1.2.3
Voltage Domain
Whereas some members of the device family have subsystems grouped into voltage domains that can be
supplied by independently scalable voltage regulators, the device has its core subsystems all in a single
voltage domain. Therefore, the voltage domain concept does not apply to this device.
4.1.3 Device Power-Management Architecture
The device supports a clock distribution and control architecture, which is described in the following
sections.
4.1.3.1
Module Interface and Functional Clocks
The clocks delivered to the modules in the device are divided into two categories: interface clocks and
functional clocks (see Figure 4-2).
Figure 4-2. Functional and Interface Clocks
Interconnect
Interface
clocks
Clock
generator
X_ICLK
Y_ICLK
Module X
Functional
clocks
{
Module Y
Y_FCLK
X_FCLK
prcm-009
Interface clocks have the following characteristics:
• They ensure proper communication between any module/subsystem and the interconnect.
• In most cases, they supply the module interface and registers.
• A typical module has one interface clock, but it can have several.
• They are synchronous across the entire device, because the interconnect fabric is itself fully
synchronous.
• Interface clock management is done at the device level.
• From the standpoint of the power, reset, and clock management (PRCM) module, an interface clock is
distributed through the device interconnect and is identified with an _ICLK suffix.
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Functional clocks have the following characteristics:
• They supply the functional part of a module or a subsystem.
• Each module can have several functional clocks, or none at all. A module may or may not require its
functional clocks to be active (nonidle).
• Several modules can share the same functional clock signals, but the branches of the clock tree are
not balanced between the modules.
• From the PRCM standpoint, a functional clock is directly distributed to the related modules through a
dedicated clock tree. It is identified with an _FCLK suffix.
NOTE: At the module level, the interface clocks are always fed by the interface clock outputs of the
PRCM. The functional clocks are fed either by a PRCM functional clock output or a PRCM
interface clock output. In the latter case, the functional and interface clocks of the module
inherit capabilities (autoidle features) from the PRCM interface clock (see Section 4.7, Clock
Manager Functional Description).
4.1.3.2
Autoidle Clock Control
The device supports an autoidle clock control scheme for the module interface clocks. With this control
scheme, PRCM can automatically activate and deactivate the interface clock of any device module,
depending on its operating mode. This scheme executes under hardware control and is transparent to the
software. This scheme identifies two module types in the device: the target and the initiator modules, or
subsystems.
NOTE: The functional clocks do not have the autoidle clock scheme, and the software must gate the
functional clock of each module when it is not needed.
Initiator
An initiator can generate bus transactions (read, write, etc.) toward targets. It is considered to be active
when it generates transactions. If it enters standby mode, it stops generating transactions. Because most
initiators also support a target port for configuration purposes, they are both targets and initiators. Some
examples of initiators are processors, direct memory access (DMA), and memory management unit
(MMU).
Target
A target is a passive module that can process bus transactions (that is, it reads/writes to memory-mapped
registers). It is considered to be active when its interface clocks and some or all of its functional clocks are
available so it can accept incoming transactions. A target can be put in idle mode by the PRCM, and in
this mode its interface clock can be gated at any time. An idle module can still receive its functional clocks
and generate interrupts and DMA requests. It can also generate asynchronous wake-up requests, if it is
wakeup-capable.
Active, Idle, and Standby Modes
The PRCM module handles automatic clock control differently for initiator and target modules.
For the initiator module, the following hardware handshake scheme is employed:
1. The initiator, when switching from active to idle mode, signals its status to the PRCM.
2. The PRCM cuts off the interface clock to the initiator module.
3. When the initiator module must reactivate, it signals the PRCM, which reactivates its functional and
interface clocks.
For the target module, the following hardware handshake scheme is employed:
1. When the PRCM confirms that the target module satisfies the idle conditions, it signals the target
module.
2. The target module acknowledges the idle request of the PRCM, depending on its idle mode internal
settings (for details about idle mode settings, see the chapter in the technical reference manual for the
corresponding device module):
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•
3.
4.
5.
6.
If the module is set to smart-idle mode, it terminates its current operations, and then acknowledges
the idle request to the PRCM.
• If the module is set to force-idle mode, it acknowledges immediately, regardless of its current state.
Because pending transfers, interrupts, and DMA requests can potentially be lost, special software
care must be taken.
• If the module is set to no-idle mode, it does not acknowledge the idle request. This forces the
PRCM to maintain the clock active.
The PRCM cuts off the module clocks.
The target module can be wakened by the PRCM when its wake-up conditions are satisfied (wake-up
event). It activates the module clocks, and then signals the wakeup.
The target module acknowledges the wake-up request.
Some target modules can support wake-up capability. They can explicitly request the PRCM to activate
their clock.
This automatic clock control ensures reduced dynamic power consumption of the device without any
associated software overhead.
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4.2
PRCM Overview
This section gives information about all modules and features in the high-tier device. See Chapter 1,
Device Family section, to check availability of modules and features. For power saving considerations,
ensure that clocks for unavailable or unused modules are gated.
4.2.1 Introduction
The power-management framework of the device significantly reduces dynamic power consumption to
extend the life of the battery in the end-product. This framework incorporates support for state-of-the-art
power-management techniques. It ensures optimal device operation with significantly reduced power
consumption. The PRCM module, which is the enhanced power-management subsystem of the device, is
the central control module for the clock, reset, and power-management signals in the device.
The device has the following features to support the different power-management techniques:
• Clock tree with selective clock-gating conditions
• Hardware-controlled reset sequencing management
• Support for hardware-controlled autogating of module clocks
• Support for low-power device standby mode
The PRCM module is the centralized management module for the power, reset, and clock control signals.
It interfaces with all the components on the device for power, clock, and reset management through
power-control signals. It integrates enhanced features to allow the device to adapt energy consumption
dynamically according to changing application and performance requirements.
The PRCM module is composed of two main entities:
• Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock
source control (oscillator)
• Clock manager (CM): Handles the clock generation, distribution, and management
The PRCM is fully configurable through its L4 interface port.
Figure 4-3 is an overview of the PRCM module and its internal connections with a generic power domain
(a group of modules with related functionality).
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Figure 4-3. PRCM Overview
WKUP domain
Device
sys_nreswarm
PRCM
sys_nrespwron
L4
interconnect
Configuration registers
sys_32k
sys_xtalout
Device Core
sys_xtalin
Idle, wakeup
control
Subsystem
or Module
Power, reset
manager
(PRM)
sys_altclk
Memory
Reset Ctrl
sys_boot6
sys_clkreq
Clock Ctrl
sys_clkout1
Clock manager
(CM)
sys_clkout2
CORE domain
prcm-010
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4.2.2 PRCM Features
The PRCM module includes the following features:
• Handling proper idle/wake-up procedures
• Allowing both software and partial hardware control
• Monitoring and handling wake-up events
• Controlling system clock/reset input sources
• Managing and distributing clocks and resets with high granularity
• Handling power-up sequences
• Debug and emulation features
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PRCM Environment
The PRCM module receives the external reset, clock, and power signals. Figure 4-4 shows the interface
of the PRCM with external reset, clock, and power sources.
Figure 4-4. PRCM Functional External Interface (Detailed View)
1.8 V
Device
To peripherals
Power IC
Pullup
PRCM
sys_nreswarm
Reset button
sys_nrespwron
sys_32k
sys_xtalout
sys_xtalin
sys_altclk
Alternate
clock source
sys_boot6
sys_clkreq
sys_clkout1
sys_clkout2
Ctrl
VDD3
Domains voltages
To peripherals
vdd_core
vdds_wkup_bg
LDO
vdds_sram
LDO
prcm-011
NOTE: In the remainder of this chapter, the term "power IC" refers to a peripheral power source IC
that is interfaced with the device.
The following sections describe the interfaces for the external clock, reset, and power sources.
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4.3.1 External Clock Signals
The device has three external clock inputs: low frequency (sys_32k), high frequency (sys_xtalin), and an
optional clock (sys_altclk). The device has two configurable clock outputs: sys_clkout1 and sys_clkout2.
Figure 4-5 shows the external clock signals of the PRCM module. Table 4-2 lists the external clock
signals, I/Os, and module reset values.
Figure 4-5. External Clock Interface
Device
PRCM
sys_boot6
sys_32k
sys_xtalout
PRM
sys_xtalin
sys_clkreq
sys_clkout1
sys_altclk
CM
sys_clkout2
prcm-013
Table 4-2. External Clock Signal Descriptions
Signal Name
I/O (1)
Description
Module Reset Value
sys_boot6
I
Boot oscillator mode control
Unknown
sys_32k
I
32-kHz clock input
Unknown
sys_xtalout
O
Output of oscillator
0
sys_xtalin
I
Main input clock. Crystal oscillator clock (only at 26 MHz) or CMOS
digital clock (at 26 MHz).
sys_clkreq
I/O
Clock request to/ from device for system clock
sys_clkout1
O
Configurable output clock 1
sys_altclk
I
Alternate clock source selectable for USB (48 MHz) or NTSC/PAL (54
MHz)
sys_clkout2
O
Configurable output clock 2
(1)
Unknown
1
0
Unknown
0
I = Input, O = Output
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Figure 4-6 shows the PRCM external clock sources.
Figure 4-6. PRCM External Clock Sources
Solution 2: Use of an external square clock source
1.8 V
Device
Solution 1: Use of an external quartz
Device
PRCM
Internal
oscillator
Pull-down
sys_boot6
PRCM
sys_xtalout
sys_xtalout
sys_xtalin
sys_xtalin
sys_clkreq
Pull-up
sys_boot6
Unused
sys_clkreq
Can be used as
GPIO (input only)
Square
clock
source
prcm-012
The system clock source can be either of the following:
• Internal oscillator with crystal connected between sys_xtalin and sys_xtalout
• A CMOS digital clock that arrives at the sys_xtalin pin
In the first option, the sys_clkreq signal is used in input mode to control sys_clkout1 and the internal clock
oscillator. In the second option, the signal is used in output mode to request the external system clock.
An external pulldown or pullup tied on sys_boot6 determines whether the internal oscillator is used or an
external clock source is supplied, respectively.
CAUTION
Only one clock source option can be used at a time.
An alternate clock input (sys_altclk) provides a precise clock source for 54 MHz, 48 MHz, or other
frequencies (for example, 59 MHz or 49.04 MHz for VDAC).
For more information about external clock signals, see Section 4.7.5 , External Clock Controls.
4.3.2 External Reset Signals
The device supports two reset signals: power-on (sys_nrespwron) and warm reset (sys_nreswarm).
sys_nrespwron is asserted at power up to reset the full logic in the device. sys_nreswarm can be activated
at any time by an external device or an external reset push-button action (see Figure 4-4) to cause a
global warm reset event.
Because sys_nreswarm is bidirectional, it can also be used to drive a reset of external devices. Any global
warm reset source (for example, a push-button) causes sys_nreswarm to be driven out and maintained for
a limited length of time at the boundary of the device. In this way, the device and its related peripherals
are properly reset together.
The sys_nrespwron assertion also causes the sys_nreswarm assertion.
Figure 4-7 shows the external reset signals. Table 4-3 lists the external reset signals, I/Os, and module
reset values.
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Figure 4-7. External Reset Signals
Device
PRCM
sys_nreswarm
PRM
sys_nrespwron
prcm-014
Table 4-3. External Reset Signals Description
(1)
Signal Name
I/O (1)
Description
Module Reset Value
sys_nreswarm
I/O
Warm-boot reset
1
sys_nrespwron
I
Power-on reset
Unknown
I = Input, O = Output
4.4 PRCM Integration
The PRCM internal registers can be accessed for configuration and controlled through the WKUP L4
interconnect. In addition to the L4 interconnect, the PRCM internal module interface contains the following:
• A set of signals for idle/wake-up control for each module
• Clocks and reset signals
• Interrupt to the MPU subsystem interrupt controller (INTC)
• Digital phase-locked loop (DPLL) control commands for recalibration and bypass
• System clock oscillator control for device-level sleep/wake-up transitions
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Figure 4-8. PRCM Integration
Device
WKUP domain
PRCM_MPU_IRQ
MPU_INTC
PRCM
L4
interconnect
Configuration registers
PRM
System clock
oscillator
Oscillator control
Idle, wakeup control
Logic
Wake-up management
Low frequency clock
Reset control
Reset manager
Memory
Voltage control
Generic domain
CM
Clock control
Clock control signals
High frequency clock
DPLL (x5)
DPLLs control
vdd_core
vdds_wkup_bg
LDO
vdds_sram
LDO
prcm-016
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4.4.1 Power-Management Scheme, Reset, and Interrupt Requests
4.4.1.1
Resets
The PRM and CM modules are reset by independent reset signals (see Table 4-4).
Table 4-4. PRCM Reset Signals
PRCM Subsystem
Reset Signal
PRM
PRM_RSTPWRON
CM
CM_RSTPWRON_RET
The PRM module is reset by the cold reset signal PRM_RSTPWRON. The CM module is reset by
assertion of the CM_RSTPWRON_RET signal.
The CM logic is reset on:
• Any global cold reset
The PRM logic is reset on:
• Any global cold reset
CM and PRM registers that are sensitive to a warm reset are also reset when a global warm reset occurs.
However, the CM and PRM logic is not reset.
NOTE: At global cold reset:
•
Only the device finite state-machine (FSM) in the PRM is operating on the 32-kHz clock,
and it is released from reset on the release of the global reset.
•
PRM logic operates on the system clock and is released from reset on release of the
reset PRM_RSTPWRON.
Figure 4-9 shows the PRCM reset signals.
Figure 4-9. PRCM Reset Signals
PRM_RSTPWRON
Device
PRCM
PRM
CM_RSTPWRON_RET
Reset manager
CM
prcm-018
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Interrupt Requests
The PRCM module can generate an interrupt to the MPU interrupt controller module:
• PRCM_MPU_IRQ: Mapped to the MPU INTC module (M_IRQ_11 interrupt line)
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4.5
PRCM Reset Manager Functional Description
4.5.1 Overview
The PRCM manages the reset of all the modules in the device, including DPLLs.
Several reset domains are defined. A reset domain is defined by a unique reset signal that originates from
the reset manager and is connected to one or multiple modules of the device. All the connected modules
of the reset domain are reset simultaneously when the reset signal is asserted.
Figure 4-10 is an overview of the reset manager interface with a generic domain in the device.
Figure 4-10. Reset Manager Interface
Device
PRCM
PRM
Reset domain 1
reset 1
reset 2
Reset manager
reset n
Reset domain 2
Reset domain n
prcm-019
Resets can be generated either by hardware sources or software control. For modules that can be reset
by software control, a software-reset bit is implemented in their <module name>_SYSCONFIG
configuration register. Software reset has the same effect on the module logic as a hardware reset.
Special reset control is available when the device operates under emulation control to reset specific reset
domains.
NOTE: All reset assertion is asynchronous, and all reset signals are active low, except for the DPLL
reset signals.
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4.5.2 General Characteristics of Reset Signals
Reset signals can be categorized based on three criteria:
• Scope
• Occurrence
• Source type
4.5.2.1
Scope
A reset signal can be categorized according to its scope (the area of the device affected by that reset):
• Global reset: Affects the entire device; all modules are reset. Generally, when the device powers up or
an abnormal operation is detected (secure watchdog timer overflows, the eFuse bad device is
detected, etc.).
• Local reset: Affects one reset domain. When a software-reset control bit for a domain is set, only the
group of modules within that domain is affected.
4.5.2.2
Occurrence
A reset signal can also be categorized depending on when the reset occurs:
• Cold reset: Occurs only on device power up or in certain emulation modes. The cold reset is a global
reset that affects every module on the device. It usually corresponds to the initial power-on reset.
• Warm reset: Occurs when the device is in normal operating state. The warm reset is also a global
reset, but it does not affect all the modules on the device. Usually, the device does not require a
complete reboot on a warm reset. Several reset sources are types of warm resets, such as the global
software reset and the watchdog reset.
Modules that behave differently in cold reset and warm reset have two reset signals: RST and
PWRON_RST. These reset signals reconstruct warm reset and cold reset in modules that require them.
For a global warm reset, the PRCM performs the following sequence:
1. It applies a warm reset on all the modules.
2. It drives the sys_nreswarm reset output low and holds it for a specified length of time (programmed in
the PRCM.PRM_RSTTIME[7:0] RSTTIME1 bit field).
A
•
•
•
•
•
•
•
global warm reset does not apply to the following modules of the device:
SDRC
System control module (SCM) (I/O control)
Part of PRM and CM registers (see note below)
32-kHz synchronization timer
DPLL3 (refer to )
Emulation modules
eFuse farm
NOTE: For information on the PRCM registers affected by the global warm reset see the Registers
Mapping Summary tables in Section 4.12, PRCM Register Manual.
4.5.2.3
Source Type
A reset can also be categorized depending on whether it is software-controlled or hardware-triggered:
• Software reset: Triggered by setting a bit in a configuration register of the PRCM module
• Hardware reset: Triggered by a signal from a hardware module inside or outside the PRCM module
4.5.3 Reset Sources
Figure 4-11 is an overview of the reset sources.
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Figure 4-11. Reset Sources Overview
Device
PRCM
Reset sources
Reset sources
ICE Crusher
ICE PICK
module
ICECRUSHER_RST
MPU watchdog
(WDTIMER2)
MPU_WD_RST
sys_nrespwron
ICEPICK_RST
sys_nreswarm
MPU_DOM_RST
NEON_DOM_RST
SGX_DOM_RST
BAD_DEVICE_RST
PRCM
registers
DPLL3_SW_RST
(software sources)
GLOBAL_SW_RST
PRM
reset manager
Efuse
device type
decoder
CORE_DOM_RST
CORE_DOM_RET_RST
PER_DOM_RST
PER_DOM_RET_RST
DSS_DOM_RST
Domain
manager FSMs
EMU_DOM_RST
USBHOST_DOM_RST
DPLL1_DOM_RST
DPLL3_DOM_RST
DPLL4_DOM_RST
DPLL5_DOM_RST
*The green region in the figure represents the boundary of the PRCM.
4.5.3.1
prcm-020
Global Reset Sources
Table 4-5 lists the global reset sources of the device. The global reset source signals received by the
reset manager trigger the reset of all the device modules. For all hardware reset signals, the source of the
reset is identified; for the software reset signals, the reset triggering bit is identified.
Table 4-5. Global Reset Sources
Type
(1)
(1)
Name
Source/Control
Description
H/C
sys_nrespwron
Input pin
The entire device is reset on power up.
H/C
BAD_DEVICE_RST
PRCM
Asserted when during the power-up
sequence the device is identified as bad,
after reading eFuses.
H/W
sys_nreswarm
Bidirectional pin
External hardware warm reset
H = Hardware reset, S = Software reset, C = Cold reset, W = Warm reset
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Table 4-5. Global Reset Sources (continued)
Type
4.5.3.2
(1)
Name
Source/Control
Description
H/W
SECURE_WD_RST
WDTIMER1
Security watchdog timer overflow reset
H/W
MPU_WD_RST
WDTIMER2
MPU watchdog timer overflow reset
H/W
MPU_SEC_VIOL_RST
Processor security FSM
Security violation reset request by the
processor security FSM
S/W
GLOBAL_SW_RST
PRCM.PRM_RSTCTRL[1] RST_GS
Global software reset
S/W
DPLL3_SW_RST
PRCM.PRM_RSTCTRL[2]
RST_DPLL3
Local cold reset for DPLL3 and a global
cold reset to the device.
H/W
ICEPICK_RST
ICEPick module
Global warm reset from ICEPick emulation
module.
Local Reset Sources
Table 4-6 lists the local reset sources of the device. A local reset source signal received by the reset
manager resets only some of the device modules.
Table 4-6. Local Reset Sources
Type
(1)
(1)
Source/Control
Description
H/C
CORE_DOM_RET_RST
Name
PRCM
H/C
USB_DOM_RET_RST
PRCM
H/C
PER_DOM_RET_RST
PRCM
Asserted only for a domain
transition from OFF to ACTIVE
state as in the case of the device
power-up. See note below for
further clarification.
H/C
MPU_DOM_RST
PRCM
H/C
NEON_DOM_RST
PRCM
H/C
SGX_DOM_RST
PRCM
H/C
CORE_DOM_RST
PRCM
H/C
PER_DOM_RST
PRCM
H/C
DSS_DOM_RST
PRCM
H/C
DPLL1_DOM_RST
PRCM
H/C
DPLL3_DOM_RST
PRCM
H/C
DPLL4_DOM_RST
PRCM
H/C
DPLL5_DOM_RST
PRCM
Asserted only for a domain
transition from OFF to ACTIVE
state as in the case of the device
power-up. See note below for
further clarification.
H = Hardware reset, S = Software reset, C = Cold reset, W = Warm reset
NOTE: For domains with <domain name>_DOM_RST and <domain name>_DOM_RET_RST, the
reset sources are asserted together when the device transitions from OFF to ON power
state, whereas only <domain name>_DOM_RET_RST is asserted on a global or local warm
reset.
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4.5.4 Reset Distribution
Each domain can contain one power-on reset (RSTPWRON) and one or more reset (RST) signals. These
signals behave as follows:
• On any global or local cold reset, both RST and RSTPWRON are asserted.
• On any global or local warm reset, only RST is asserted.
The CORE domain receives two additional legacy reset signals: retention reset (RST_RET) and power-on
retention reset (RSTPWRON_RET). These signals behave as follows:
• On any global cold reset, both RST_RET and RSTPWRON_RET are asserted.
• On any global warm reset, only RST_RET is asserted.
Figure 4-12 shows the reset distribution among the domains.
Figure 4-12. Reset Destinations Overview
Device
PRCM
Reset
destinations
Reset
destinations
sys_nreswarm
DPLL1_RST
DPLL3_RST
WKUP_RST
WKUP
WKUP_RSTPWRON
SYNCT_RST
MPU
PRM
reset manager
DPLL4_RST
DPLL5_RST
PER_RST
PER_RST_RET
DPLL3
DPLL4
DPLL5
PER
MPU_RST
DSS_RST
NEON_RST
USBTLL_RST
CORE_RST
CORE
DPLL1
SGX_RST
EFUSE_RSTPWRON
CM_RSTPWRON_RET
NEON
SGX
EFUSE
EMU_RST
CORE_RST_RET
CORE_RSTPWRON_RET
DSS
EMU_RSTPWRON
BANDGAP_RSTPWRON
USBHOST_RST
EMU
Bandgap
USBHOST
* The green region in the figure represents the boundary of the PRCM
prcm-021
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4.5.5 Domain Reset Descriptions
4.5.5.1
MPU Domain
The MPU domain has one input and one output reset signal (see Table 4-7).
Table 4-7. MPU Domain Reset Signals
Name
I/O
(1)
Source/Destination (2)
Reset Domain
MPU_RST
I
PRM
Resets the MPU processor core and the
asynchronous bridge in the MPU domain.
MPU_SEC_VIOL_RST
O
PRM
Global cold reset source to reset manager.
Generated by the security FSM in the MPU
subsystem.
(1)
(2)
I = Input, O = Output
Source for an input signal and destination for an output signal.
NOTE: The MPU_CLK is divided by 2 inside the MPU subsystem to generate the ARM_FCLK This
divider is only active when the DPLL is locked. (Refer to MPU Subsystem for information on
ARM_FCLK).
4.5.5.2
NEON Domain
The NEON domain has one reset input signal (see Table 4-8).
Table 4-8. NEON Domain Reset Signal
(1)
4.5.5.3
Name
I/O (1)
Source
Reset Domain
NEON_RST
I
PRM
Resets the NEON coprocessor
I = Input, O = Output
CORE Domain
The CORE domain has eight input reset signals. (See Table 4-9).
Table 4-9. CORE Domain Reset Signals
I/O (1)
Source/Destination (2)
Reset Domain
CORE_RST
I
PRM
Resets parts of the three asynchronous bridges, MPU
INTC, interconnects, GPMC, OCM, UART[1,2], HDQ
and HS USB, I2C[1..3], McBSP 1 and 5, McSPI [1..3],
MMC[1..3], GPTIMER[10,11], D3D[1,2], SHAM1, RNG,
AES[1..2], PKA, and SHAM2
CORE_RST_RET
I
PRM
Resets part of the SDRC, SDMA, SMS, and MPU INTC
CORE_RSTPWRON_RE
T
I
PRM
Resets part of the SDRC and SCM
CM_RSTPWRON_RET
I
PRM
Resets the clock manager
CPEFUSE_RST
I
PRM
Reset the Customer Programmable EFUSE controller.
Asserted under the same condition as that of
CORE_RST. The CPEFUSE functional clock must be
active to release the reset. This clock is enabled by
default following a power-on reset. (For the reset
sequence, see Section 4.5.9.2.)
USBTLL_RST
I
PRM
Resets the USB TLL asynchronously
Name
(1)
(2)
I = Input, O = Output
Source for an input signal and destination for an output signal
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The CM logic is reset on:
• Any global cold reset
Because the CM logic is not reset in this case, the CM registers that are sensitive to a warm reset must
also be reset synchronously with the L4 clock when a global warm reset occurs.
4.5.5.4
DSS Domain
The DSS domain has one reset input signal (see Table 4-10).
Table 4-10. DSS Domain Reset Signal
Name
DSS_RST
(1)
4.5.5.5
I/O (1)
Source
I
PRM
Reset Domain
Resets the entire display subsystem
I = Input, O = Output
USBHOST Domain
The USBHOST domain has one reset input signal (see Table 4-11).
Table 4-11. USBHOST Domain Reset Signal
Name
USBHOST_RST
(1)
4.5.5.6
I/O (1)
Source
I
PRM
Reset Domain
Resets the entire HS USB Host
subsystem
I = Input, O = Output
SGX Domain
The SGX domain has one reset input signal (see Table 4-12).
Table 4-12. SGX Domain Reset Signal
Name
SGX_RST
(1)
4.5.5.7
I/O (1)
Source
I
PRM
Reset Domain
Resets the entire SGX subsystem
I = Input, O = Output
WKUP Domain
The WKUP domain has three reset input signals and two reset output signals (see Table 4-13).
Table 4-13. WKUP Domain Reset Signals
I/O (1)
Source/Destination (2)
WKUP_RST
I
PRM
Resets the GPTIMER[1,12], WDTIMER2, GPIO 1 and
USIMOCP
WKUP_RSTPWRON
I
PRM
Reset the wake-up control module and WDTIMER1
SYNCT_RST
I
PRM
Resets the 32-kHz sync timer. This reset is directly
connected to the sys_nrespwron global reset source.
SECURE_WD_RST
O
PRM
Global warm reset for PRM. Generated by WDTIMER1.
MPU_WD_RST
O
PRM
Global warm reset for PRM. Generated by WDTIMER2.
Name
(1)
(2)
Reset Domain
I = Input, O = Output
Source for an input signal and destination for an output signal
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The PRM logic is reset on any global cold reset. Because the PRM logic is not reset in this case, the PRM
registers that are sensitive to a warm reset must also be reset synchronously with the system clock when
a global warm reset occurs.
4.5.5.8
PER Domain
The PER domain has two reset input signals (see Table 4-14).
Table 4-14. PER Domain Reset Signal
I/O (1)
Source
PER_RST
I
PRCM
Resets the UART3, McBSP[2,3,4],
GPTIMER[2,..,9], WDTIMER3 modules
PER_RST_RET
I
PRCM
Resets the GPIO [2,..,6] modules
Name
(1)
4.5.5.9
Reset Domain
I = Input, O = Output
DPLL Domains
The DPLL domains for DPLL1, DPLL3, DPLL4 and DPLL5 each have one reset input signal.
Table 4-15. DPLL Domain Reset Signals
I/O (1)
Source
DPLL1_RSTPWRON
I
PRCM
Resets the DPLL1 module
DPLL3_RSTPWRON
I
PRCM
Resets the DPLL3 module
DPLL4_RSTPWRON
I
PRCM
Resets the DPLL4 module
DPLL5_RSTPWRON
I
PRCM
Resets the DPLL5 module
Name
(1)
Reset Domain
I = Input, O = Output
They are asserted for any type of global cold reset.
4.5.5.10 EFUSE Domain
The EFUSE domain has one reset input signal (see Table 4-16).
Table 4-16. EFUSE Domain Reset Signal
Name
EFUSE_RSTPWRON
(1)
I/O (1)
Source
I
PRCM
Reset Domain
Resets the eFuse controller
I = Input, O = Output
This signal is asserted for any type of global cold reset.
4.5.5.11 BANDGAP Logic
The BANDGAP logic has one reset input signal (see Table 4-17).
Table 4-17. BANDGAP Logic Reset Signal
Name
BANDGAP_RSTPWRON
(1)
204
I/O (1)
Source
I
PRCM
Reset Domain
Resets the BANDGAP logic
I = Input, O = Output
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This signal is asserted for any type of global cold reset.
4.5.5.12 Other Module Resets
Both Figure 4-13 and Figure 4-14 show the reset connectivity of the remaining modules. The CBASS,
USBOTG subsystem, CPGMAC subsystem, VPFE, HECC, EMIF subsystem, and VBUS-to-OCP bridges
are connected to the Warm Reset output of the PRM as shown in the Figure 4-13.
Additionally, a software reset register is present the system control module to allow software to reset these
modules. Note that SW Reset is not self clearing. Software needs to write ‘1’ to put these modules in reset
and write ‘0’ to bring it out of reset. Please refer to the System Control Module chapter for more details on
the software reset register.
Figure 4-13. Other Module Reset Distributions Overview
UART4
CBASS
Prm_coreRst_n
L3_ick
Sw_reset[1]
OR
OR
cpgmac_vbus_rst_n
CPGMAC
bridges_vbus_rst_n
OCP2VBUSP and
VBUSP20CP
BRIDGES
usb20otg_vbus_rst_n
OR
Sw_reset[0]
OR
Sw_reset[2]
USB20OTG
dma_rst_n
mmr_rs_n
VPFE
ccdc_rst_n
pclk
Sw_reset[4]
OR
sws_clk
Sw_reset[3]
OR
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Figure 4-14. EMIF4 Reset Distributions Overview
Emif4_ss
OCP Clock Domain
MCLK Clock Domain
Efmif4d_sms_wrap
gs60phy_32bit
Divider Reset
OCP L3 Interface
DATA0
SMS
Core Warm Reset
Clock Reset
CMD
Main_arst_n
PowerOnReset
Phy_rst_n
EMIF4
por_rst_n
DATA1
Divider Reset
4.5.5.13 External Warm Reset Assertion
Figure 4-15 shows the external warm reset interface.
Figure 4-15. External Warm Reset Interface
Device
1.8 V
PRCM
Pull-up
sys_nreswarm_out
PRM
sys_nreswarm
Reset to
peripherals
sys_nreswarm_in
Global reset source
Reset
button
prcm-022
Any global reset source (internal or external) causes sys_nreswarm_out to be driven and maintained at
the boundary of the device for at least the amount of time configured in the PRCM.PRM_RSTTIME[7:0]
RSTTIME1 bit field. This ensures that the device and its related peripherals are properly reset together.
NOTE: Because the system warm-reset output is implemented on a bidirectional pad, any input
pulse on sys_nreswarm causes a global warm reset.
4.5.6 Reset Logging
The reset in the device is logged in two ways. First, dedicated registers in the PRCM (that is, the
RM_RSTST_power domain> and PRM_RSTST registers) log the reset source. Second, the SCM also
logs the device reset activity in dedicated registers, for security purposes.
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4.5.6.1
PRCM Reset Logging Mechanism
The reset status registers (RM_RSTST_power domain> and PRM_RSTST) are reset asynchronously on
assertion of a global cold reset. However, a reset status bit is always logged when the reset is released to
the domain.
For this reason, after the assertion of a global cold reset, the reset status register is cleared to 0. When
the domain reset is released, the register bit to log the global cold reset (that is, the RM_RSTST_<power
domain> [0] GLOBALCOLD_RST bit) is updated to 1. For the same reason, the reset status register of
domains released from reset by software is updated only when software releases the domain reset.
The assertion of a global cold reset prevents logging any other source of reset until after the release of the
domain reset. This is valid in the following situations:
• A source of reset other than global cold reset is asserted before, during, or after the active period of a
global cold source of reset and before the release of the domain reset signal.
• A source of reset other than global cold reset was asserted and then released, but a global cold reset
source was asserted before the release of the domain reset signal.
4.5.6.2
SCM Reset Logging
The PRM exports reset the activity status signals to the SCM. For security purposes, the SCM uses these
signals to log a reset status in the SCM.CONTROL_SEC_STATUS register. The reset activity status
signal is asserted high when any source of reset to the domain is active.
It
•
•
•
•
also provides reset status for the following global reset signals:
Global cold reset
Global warm reset
Global warm secure watchdog reset (SECURE_WD_RST)
Global warm security violation reset (MPU_SEC_VIOL_RST)
There is one reset activity status signal for each of the following domains:
• CORE
• DSS
• EMU
• SGX
• MPU
• NEON
• PER
• USBHOST
These signals are asserted high on assertion of any source of reset on the domain and logged. For
information about the SCM, see the System Control Module chapter.
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4.5.7 Reset Management Overview
The reset management structure in the device can be considered as a 2-layered structure composed of
multiple instances of the reset manager. In the first layer, a top-level reset manager, called the device
reset manager, handles all the sources of global reset (cold and warm). It provides reset managers for the
second layer, called local reset managers, and the global reset and global power-on reset signals.
Each domain has a minimum of one local reset manager. The local reset manager also receives resets,
such as the software reset and domain power transition reset, from the local reset source for the domain.
Figure 4-16 through Figure 4-19 provide an overview of reset management in the device. They do not
provide reset sequencing between the reset managers.
NOTE: The domain must be ready (that is, the domain clocks must be active) before its reset is
released.
Figure 4-16. Device Reset Manager Overview
GLOBAL_SW_RST
DPLL3_SW_RST
Global warm reset
MPU_WD_RST
Device reset
Global power on reset
manager
Registers warm reset
sys_nrespwron
ICEPICK_RST
External warm
sys_nreswarm_in
reset assertion
logic
sys_nreswarm_out
prcm-023
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Figure 4-17. Domain Reset Management: Part 1
ICECRUSHER_RST
MPU_RST
MPU_DOM_RST
MPU domain
reset manager
MPU_RSTPWRON
CORE_DOM_RET_RST
NEON_DOM_RST
NEON domain
reset manager
NEON_RST
SGX domain
reset manager
SGX_RST
CORE_DOM_RET_RST
SGX__DOM_RST
CORE_DOM_RET_RST
CORE_DOM_RET_RST
CORE domain
reset manager 1
CORE_RST
CORE_RST_RET
CORE_DOM_RET_RST
CORE_DOM_RST
CORE domain
reset manager 2
CORE_RSTPWRON_RET
CORE domain
reset manager 4
USBTLL_RST
prcm-024
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Figure 4-18. Domain Reset Management: Part 2
Global power on reset
CM reset
CORE_DOM_RET_RST
CM_RSTPWRON_RET
manager
Global warm reset
DSS_DOM_RST
CORE_DOM_RET_RST
DSS domain
reset manager
DSS_RST
PER domain
PER_RST
BAD_DEVICE_RESET
PER_DOM_RST
CORE_DOM_RET_RST
reset manager 1
PER_DOM_RET _RST
CORE_DOM_RET_RST
reset manager 2
PER domain
USB_DOM_RST
CORE_DOM_RET_RST
USBHOST domain
reset manager
PER_RST_RET
USBHOST_RST
prcm-025
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Figure 4-19. Domain Reset Management: Part 3
WKUP_RST
WKUP domain
reset manager
PRM reset
manager
Global power on reset
WKUP_RSTPWRON
PRM_RSTPWRON
SYNCT_RST
sys_nrespwron
EFUSE_DOM_RST
EFUSE domain
reset manager
EFUSE_RSTPWRON
EMU_RST
EMU_DOM_RST
EMU_DOM_RST
BAD_DEVICE_RST
DPLL1_DOM_RST
EMU domain
reset manager 1
EMU domain
reset manager 2
EMU_RSTPWRON
ICEPICK_RSTPWRON
DPLL1 domain
reset manager
DPLL1_RSTPWRON
DPLL3 domain
reset manager
DPLL3_RSTPWRON
DPLL4 domain
reset manager
DPLL4_RSTPWRON
DPLL5 domain
reset manager
DPLL5_RSTPWRON
Global warm reset
DPLL3_SW_RST
DPLL3_DOM_RST
DPLL4_DOM_RST
DPLL5_DOM_RST
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4.5.8 Reset Summary
Table 4-18 and Table 4-19 summarize the different sources of global and local resets and their actions on
the reset signals.
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Table 4-18. Global Reset Summary
(1)
Domain Resets
Power Domain
Reset Sources
Signal
Cold Reset
sys_nres
pweron
MPU
MPU_RST
NEON
NEON_RST
SGX
SGX_RST
CORE
CORE_RST
Warm Reset
DPLL3_
SW_RST
sys_nres
warm_in
MPU_WD_
RST
GLOBAL_
SW_RST
CORE_RSTPWRON
CORE_RST_RET
CORE_RSTPWRON_RET
CM_RSTPWRON_RET
USBTLL_RST
WKUP
WKUP_RST
SYNCT_RST
PER
PER_RST
PER_RST_RET
DSS
DSS_RST
USBHOST
USBHOST_RST
EMU
EMU_RST
EMU_RSTPWRON
ICEPICK_RSTPWRON
DPLL1
DPLL1_RSTPWRON
DPLL3
DPLL3_RSTPWRON
DPLL4
DPLL4_RSTPWRON
DPLL5
DPLL5_RSTPWRON
SR
SR_RST
EFUSE
EFUSE_RSTPWRON
BANDGAP
BANDGAP_RSTPWRON
Device pad (output)
SYS_NRESWARM_OUT
(1)
The shaded blocks identify the domain reset signals triggered as a result of the reset source signal (at the head of the column).
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Table 4-19. Local Reset Summary
Domain Resets
Power Domain
Reset Sources
Signal
Cold Reset
CORE_DO
M_
RET_RST
MPU
MPU_RST
NEON
NEON_RST
SGX
SGX_RST
CORE
CORE_RST
(1)
PER_DOM_
RET_RST
DPLL3_
SW_RST
Warm Reset
BAD_
DEVICE_
RESET
ICECRUSHER
_
RST
CORE_RST_RET
CORE_RSTPWRON_RET
CM_RSTPWRON_RET
USBTLL_RST
WKUP
WKUP_RST
SYNCT_RST
PER
PER_RST
PER_RST_RET
DSS
DSS_RST
USBHOST
USBHOST_RST
EMU
EMU_RST
EMU_RSTPWRON
ICEPICK_RSTPWRON
DPLL1
DPLL1_RSTPWRON
DPLL3
DPLL3_RSTPWRON
DPLL4
DPLL4_RSTPWRON
DPLL5
DPLL5_RSTPWRON
SR
SR_RST
EFUSE
EFUSE_RSTPWRON
BANDGAP
BANDGAP_RSTPWRON
Device pad (output)
sys_nreswarm_out
(1)
The shaded blocks identify the domain reset signals triggered as a result of the reset source signal (at the head of the column).
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4.5.9 Reset Sequences
4.5.9.1
Power-Up Sequence
NOTE: Please reference the device-specific data manual for power-up sequencing.
4.5.9.2
CPEFUSE Reset Sequence
In the CPEFUSE reset sequence, Customer Programmable EFUSE is coupled with the SCM. Whenever
the SCM is reset, the CPEFUSE cells are sensed. This sequence is initiated by the PRCM module and
the SCM (hardware-controlled) after a device cold reset. Under these conditions, the CM part of the
PRCM is released from reset, and, according to the configuration of the PRCM.CM_FCLKEN3_CORE[0]
EN_CPEFUSE bit, the CPEFUSE functional clock is automatically restarted and the CPEFUSE_RST reset
is released (de-asserted). The SCM completes the autoload sequence of the CPEFUSE. Software must
poll the autoload completion status bit in the SCM before switching off the CPEFUSE functional clock.
Whenever the software must blow a CPEFUSE, it must ensure that the functional clock is enabled; it
starts the autoload sequence by programming the SCM.
For information about the SCM, see the System Control Module chapter.
4.6
PRCM Power Manager Functional Description
4.6.1 Overview
4.6.1.1
Device Partitioning
Table 4-20 lists the device modules split over the domains.
Table 4-20. Domain Modules
Power Domain
Modules
MPU
MPU core
ICE-crusher CS
MPU async bridge (master)
SSM
NEON
NEON coprocessor
SGX
SGX subsystem
CORE
GPMC
GPTIMER[10, 11]
HDQ/1-Wire
HS USB
I2C[1, 2, 3]
McBSP[1, 5]
McSPI[1, 2, 3, 4]
MMC/SD/SDIO[1, 2, 3]
MPU async bridge (slave)
MPU INTC
OCM_RAM
OCM_ROM
SCM
SDRC
SHAM[1, 2]
SMS
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Table 4-20. Domain Modules (continued)
Power Domain
Modules
L3 Interconnect
UART[1, 2]
SDMA
Temperature sensor (x2)]
CPEfuse farm
L4_Core interconnect
DSS
Display subsystem
Video DAC
PER
UART3
WDTIMER3
McBSP[2..4]
GPIO[2..6]
GPTIMER[2..9]
L4_Per interconnect
WKUP
GPIO1
GPTIMER[1, 2]
WDTIMER[1, 2]
32-kHz sync timer
L4_Wakeup interconnect
EMU
CWT
DAP-APB
ETB
ICEPICK
SDTI
TRACEPORT
L4_EMU interconnect
4.6.1.2
EFUSE
eFuse farm
DPLL1
MPU DPLL
DPLL3
CORE DPLL
DPLL4
Peripherals DPLL
DPLL5
Peripherals DPLL2
Domain State Transitions
For each domain, the PRM manages state transitions, controlling domain clocks and resets.
Two types of power state transitions are possible:
• Sleep: Moving from a higher consumption power state (ACTIVE) to a lower consumption power state
(INACTIVE).
• Wake-up: Moving directly from a lower consumption power state (INACTIVE) to the ACTIVE power
state.
4.6.1.3
Device Power Modes
A device power mode is a specific functional combination of the states of all the domains of the device.
Unlike domain states, device power modes are not hardware-defined; they are defined by software as
relevant combinations of the domain states.
There are two types of device power modes:
• Active: Any valid combination of domain states in which one or several domains are still active,
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•
regardless of whether any software is running.
Standby: Any valid combination of domain states in which all the domains are in INACTIVE state.
4.6.2 Domain Implementation
4.6.2.1
Domain Dependencies
Besides the inner conditions to operate a state transition on a single domain, the device offers hardwired
and software-programmable dependencies between the domains.
Two kinds of dependencies exist:
• Sleep dependencies: Used to start a sleep transition on a domain only if the related domains are in
mute mode (not requesting any service from the linked domain)
• Wake-up dependencies: Used to initiate a wake-up transition on a domain as a consequence of a
linked domain wake-up transition
Two dedicated sets of registers (PRCM.CM_SLEEPDEP_<domain> and PRCM.PM_WKDEP_<domain>)
allow the setting of programmable dependencies.
Section 4.8.5, Sleep and Wake-Up Dependencies, summarizes the possible dependency combinations
between domains.
4.6.2.2
Domain Software Controls
If all conditions are met to initiate a domain state transition (that is, all the modules are idle/standby and
the related clocks are shut down), the PRCM automatically manages the transition according to the
following settings:
• Dependencies setting: The PRCM.CM_SLEEPDEP_<domain> registers and
PRCM.PM_WKDEP_<domain> registers are used to set/clear programmable dependencies between
domains.
Not all dependencies are programmable by software; some are hardwired and thus do not allow any
control. For more information about the dependencies between domains, see Section 4.8, Idle and
Wake-Up Management, and Section 4.11, Basic Programming Model.
• Event generator: Three registers (PRCM.PM_EVGENCTRL_MPU, PRCM.PM_EVGENONTIM_MPU,
and PRCM.PM_EVGENOFFTIM_MPU) allow the MPU domain to be switched between on inactive
mode. The PRCM.PM_EVGENONTIM_MPU and PRCM.PM_EVGENOFFTIM_MPU registers are used
to set the durations of the on and inactive modes, respectively.
For details, see Section 4.11, Basic Programming Model, and Section 4.12,PRCM Registers Manual.
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PRCM Clock Manager Functional Description
This section gives information about all modules and features in the high-tier device. See Chapter 1,
Device Family section, to check availability of modules and features. For power saving considerations,
ensure that clocks to unused domains and modules are properly gated.
4.7.1 Overview
The PRCM module provides control for clock generation, division, distribution, synchronization, and gating.
It distributes the clock sources to all the modules in the device.
The device-level clock generation is handled by internal oscillators (the system clock oscillator and the 32kHz oscillator for secure clock) and DPLLs; clock division and gating are handled by the PRM and the CM
sections of the PRCM. Figure 4-20 shows the high-level clock-management scheme in the device.
Figure 4-20. PRCM Clock Manager Overview
Device
PRCM
Oscillator
PRM
PRM generated clocks
DPLLs
Reference Clock
sys_xtalout
sys_xtalin
sys_boot6
Clock
division
and
gating
control
sys_boot7
sys_32k
sys_clkout1
Device subsystems
sys_clkreq
Clock and
control signals
CM
CM generated
clocks
DPLL1
(MPU)
MPU
clock
sys_altclk
Clock
division
and
gating
control
DPLL3
(CORE)
DPLL3
clocks
sys_clkout2
DPLL4
(PER)
DPLL4
clocks
DPLL5
(PER2)
DPLL5
clocks
prcm-034
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4.7.1.1
Interface and Functional Clocks
The PRCM propagates two kinds of clocks:
• Interface clock: Ensures proper communication between any module and the system interconnects (L3
or L4). In most cases, the interface clock supplies the interface and registers of the module. For some
modules, the interface clock is also used as the functional clock.
• Functional clock: Supplies the functional part of a module or subsystem. In some cases, a module or
subsystem may require several functional clocks.
To be operational, a module requires functional clock(s); to communicate with other modules, it requires
an interface clock. For example, the functional clock of a general-purpose timer (GPTIMER) must be
active for it to run, but its interface clock can be turned off.
A module can use one or more optional functional clocks. Because an optional functional clock is used
only for specific features of the module, it can be shut down without stopping the module activity (for
example, 54 MHz for the DSS domain).
4.7.2 External Clock I/Os
Figure 4-21 shows the external clock I/Os of the device.
Figure 4-21. External Clock I/O
sys_boot7
sys_32k
Fixed
Divider
PRM
sys_xtalin
Oscillator
sys_xtalout
sys_clk_out1
sys_atlclk
CM
4.7.2.1
sys_clkout2
External Clock Inputs
4.7.2.1.1 32-kHz Always-On Clock
The 32-kHz clock is used for low-frequency operation (timers, denouncing, etc.). It also supplies the
WKUP domain for operation in the lowest power standby mode. The device supports an external 32kHz
clock signal or an internal 32kHz clock divided down from the external 26MHz high-frequency clock. The
selection between external and internal 32kHz clock is done by sys_boot7 pin. The sys_32k input pin
supplies the 32-kHz always-on clock (32K_FCLK clock) when the sys_boot7 pin is configured for external
32-kHz clock.
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4.7.2.1.2 High-Frequency System Clock
The high-frequency system clock (SYS_CLK) is either supplied to the device from an external clock
source through the sys_xtalin input pin or is generated internally by a local system clock crystal oscillator.
In the latter case, a crystal is connected between the sys_xtalout and sys_xtalin device pins. The
sys_boot[6] pin is used to set the oscillator operating mode (see Figure 4-6).
The source system clock can be 26 MHz and is internally divided by 2 to provide the standard frequencies
(26 MHz becomes 13 MHz). It supplies the reference to the DPLLs and is also used by several modules.
The system clock is activated in the device after the device power-on reset is released by the reset
manager in the PRCM module.
The source-clock selection register (PRCM.PRM_CKSEL [2:0] SYS_CLKIN_SEL bit field) is set by the
software to identify the input frequency of the system clock.
Table 4-21 provides the system clock input configurations.
Table 4-21. System Clock Input Configurations
Input Source
Device Pin Mapping
Description
Quartz
sys_xtalin and sys_xtalout
Internal oscillator is enabled.
Square clock (1.8-V CMOS signal)
sys_xtalin (sys_xtalout is not connected)
Internal oscillator is bypassed.
NOTE: An external pullup or pulldown tied on the sys_boot6 input pin of the device determines
whether the internal oscillator is used (oscillator mode) or an external clock source is
supplied to the sys_xtalin input pin (bypass mode).
4.7.2.1.3 Alternate Clock
The sys_altclk pin can be used to provide an alternate 54-MHz, 48-MHz, or any other frequency clock.
4.7.2.2
External Clock Outputs
The device can output two clocks externally:
• sys_clkout1 can output an oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. The output
oscillator clock can be controlled either by software or externally using sys_clkreq control.
• sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (CORE DPLL output), or
96-MHz or 54-MHz clocks. It can be divided by 2, 4, 8, or 16. This output is active only when the
CORE domain is ACTIVE. Also, the selected source clock must be enabled by software. Enabling
sys_clkout2 does not automatically request the required source clock.
4.7.2.3
Summary
Table 4-22 summarizes the external clock I/O.
Table 4-22. External Clock I/Os
Name
(1)
I/O
(1)
Source/Destination
Description
sys_xtalin
I
Oscillator
Main input clock. Crystal oscillator clock (only at 26 MHz) or CMOS
digital clock (at 26 MHz).
sys_xtalout
O
Oscillator
Output of oscillator
sys_clkout1
O
PRCM
Configurable output clock 1
sys_clkout2
O
PRCM
Configurable output clock 2
sys_32k
I
PRCM
32-kHz clock input
sys_altclk
I
PRCM
Alternate selectable clock source for UARTs or NTSC/PAL. It can be 54
MHz, 48 MHz, or any frequency.
I = Input, O = Output
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4.7.3 Internal Clock Generation
The device generates internal clocks from four sources:
• PRM
• CM
• DPLLs
• 32-kHz oscillator
Figure 4-22 shows the internal clock generation scheme of the device.
generator
32K_FCLK
clock
SYS_CLK
PRM
MPU_CLK
DPLL1
(MPU)
Figure 4-22. Internal Clock Sources
L4_ICLK
L3_ICLK
12M_FCLK
CM
48M_FCLK
DSS_TV_CLK
clock generator
96M_FCLK
DPLL3
(CORE)
CORE_CLK
COREX2_CLK
EMU_CORE_ALWON_CLK
DPLL4 (PER)
EMU_PER_ALWON_CLK
DSS1_ALWON_FCLK
DPLL5 (PER2)
96M_ALWON_FCLK
120M_FCLK
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PRM
The PRM resides in the WKUP domain. It handles the generation of the 32-kHz low-frequency clocks and
the high-frequency system clocks from the SYS_CLK. It also manages the clock oscillator and the external
clock output sys_clkout1.
SYS_CLK is generated by the internal oscillator or supplied as the external clock signal on the sys_xtalin
pin. It supplies most of the clocks in the device. SYS_CLK is also the source of the WKUP domain
interface clocks.
It also handles the gating and distribution of the 96-MHz clock from DPLL4 to the CM and the PER
domain modules.
Figure 4-23 is the functional overview of the PRM. The other clocks in the figure are explained in the
following sections.
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DPLL4_ALWON_FCLK
SYS_CLK
PRM control
sys_boot6
CM_SYS_CLK
DPLL5_ALWON_FCLK
SYS_CLK
Divider
[1, 2]
OSC_SYS_CLK
Osc_ctrl
sys_xtalin
Oscillator
sys_xtalout
DPLL3_ALWON_FCLK
PRM control
SR_ALWON_FCLK
EFUSE_ALWON_FCLK
Gating/state
control
pad
sys_clkreq
/800
USBHOST_SAR_FCLK
USBTLL_SAR_FCLK
PRM
clock generator
Clkout1_pol
Clkout1_fcgc
sys_clkout1
96M_ALWON_FCLK
PRM_96M_ALWON_CLK
DPLL4
CM_96M_FCLK
32K_FCLK
sys_boot7
CM_32K_CLK
sys_32k
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PRCM Clock Manager Functional Description
Figure 4-23. PRM Clock Generator
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PRCM Clock Manager Functional Description
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CM
The CM clock generator generates interface clocks and peripheral functional clocks for most of the
modules. It also controls DPLL3, DPLL4, and the external peripheral clock output sys_clkout2 (see
Figure 4-24).
The CM is in the CORE domain.
DPLL3 receives SYS_CLK from the PRM and generates CORE_CLK through the CM. CORE_CLK is the
source for the interface clocks (L3 and L4) and the functional clock . The L3 and L4 interface clocks
supply the device interconnects and all module interface clocks. The L4 clock is divided to supply the reset
managers (PRM) in the WKUP domain. The clocks derived from CORE_CLK are fully balanced over the
device.
The 96M_FCLK, 48M_FCLK, and 12M_FCLK clocks are functional unbalanced clocks for a number of
modules in the CORE and PER domains.
The functional 96-MHz clock path can be bypassed with SYS_CLK to allow a peripheral such as I2C to be
functional while the DPLL4 is not yet enabled. The default configuration after initial power-on is bypassed
with the system clock. Software must switch to the DPLL-generated clock after programming the proper
system settings.
The 96-MHz clock input from PRM to the CM (that is, CM_96M_FCLK) is internally gated by the CM.
Figure 4-24 shows the functional overview of the CM.
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Ctrl
Figure 4-24. CM Clock Generator Functional Overview
Divider
[4]
mux
Divider
[2]
DPLL4
DPLL4_M3X2_CLK
DSS_TV_FCLK
54 MHz
mux
sys_altclk
12M_FCLK
48M_FCLK
mux
DPLL4_M2X2_CLK
96M_FCLK
COREX2_CLK
Divider
[1, 2]
CM
Clock generator
DPLL3
PRM_96M_ALWON_CLK
DPLL3_M2X2_CLK
DPLL1_FCLK
Divider
[1, 2]
CM_SYS_CLK
CORE_CLK
96 MHz
54 MHz
L3_ICLK
L4_ICLK
mux
PRM
Divider
[1, 2]
CORE_CLK
DPLL3_M2_CLK
CM_96M_FCLK
Divider
[1, 2]
Divider
[1, 2, 4, 8, 16]
DPLL5
CLKOUT2_EN
sys_clkout2
RM_ICLK
(to PRM)
CLKOUT2_POL
Gating/state
control
CM_SYS_CLK
120M_FCLK
DPLL5_M2_CLK
prcm-038
Figure 4-25 shows the functional overview of the CM for emulation clocks.
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Figure 4-25. CM Emulation Clock Generator Functional Overview
Divider
[1, 2, 4]
Divider
[1, 2]
EMU_PER_ALWON_CLK
EMU_TRACE_CLK
EMU_AT_CLK
Divider
[2, 3, 4, 6]
DPLL3
Trace
Mux
DPLL4_M6X2_CLK
EMU_CLK
Divider
[1, 2, 3]
Ctrl
EMU_CORE_ALWON_CLK
Ctrl
DPLL4
sys_altclk
EMUX2_CLK
MPU_CLK
Divider
[ 3]
MPU
EMU
Mux
DPLL3_M3X2_CLK
EMU_MPU_ALWON_CLK
prcm-100
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4.7.3.3
DPLLs
To generate high-frequency clocks, the device supports five on-chip DPLLs controlled directly by the
PRCM:
• DPLL1 (MPU)
• DPLL3 (CORE)
• DPLL4 (PER)
• DPLL5 (PER2)
NOTE: This chapter discusses only DPLL1 to DPLL5, because they are directly controlled by the
PRCM module. The Display Interface Subsystem chapter discusses the DPLLs in the DSS.
Figure 4-26 shows the functional architecture of a generic DPLL.
Figure 4-26. Generic DPLL Functional Diagram
High frequency
bypass clock
DPLL<n>_FCLK
Low frequency
bypass clock
DPLL<n>_ALWON_FCLK
Fref
Multiplier and divider
(M,N)
DPLL
Bypass clock
Dividers
Divider CLKOUT M2
1/2
CLKOUTX2
PRCM
DPLL Power Mode
Control Bitfield
Hardware control
Bypass select
CLKOUT_M2
M2
CLKOUT_M2X2
M3
CLKOUT_M3X2
M4
CLKOUT_M4X2
M5
CLKOUT_M5X2
M6
CLKOUT_M6X2
Gating control
prcm-039
Depending on its hardware configuration, the DPLL may receive one or two clock inputs.
When the DPLL has two clock inputs, it uses one as the reference clock (Fref ) to generate the highfrequency clock; the second one serves as the bypass clock when the DPLL is in bypass mode (that is,
not locked and generating the high-frequency clock). For example, DPLL1 receives the high-frequency
bypass clock from the DPLL3 output, and the reference clock from the PRM.
When the DPLL has only one clock input, it uses that clock input as the reference clock and bypass clock.
For example, DPLL3, DPLL4, and DPLL5 receive only one input clock from PRM, and it is used as both
the reference and the bypass clock.
It internally generates two main clocks according to the following equations:
• CLKOUTX2 = (Fref x 2 x M) / (N+1)
• CLKOUT = CLKOUTX2/2
where M is an 11-bit multiplier and N is a 7-bit divider.
NOTE: When M is set to 0 or 1, the DPLL is forced into bypass mode.
The internal clocks (CLKOUT and CLKOUTX2) of the DPLL may then be used to generate six
independent output clocks:
• CLKOUT_M2 = CLKOUT / M2
• CLKOUT_M2X2 = CLKOUTX2 / M2
• CLKOUT_M3X2 = CLKOUTX2 / M3
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•
•
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CLKOUT_M4X2 = CLKOUTX2 / M4
CLKOUT_M5X2 = CLKOUTX2 / M5
CLKOUT_M6X2 = CLKOUTX2 / M6
where M2, M3, M4, M5, and M6 are additional dividers for the DPLL-synthesized clock.
The output clock frequencies defined by these equations are generated by the DPLL only when it is
locked. When the DPLL is in bypass mode, however, all clock outputs run at the bypass clock frequency.
The bypass clock can either be a high-frequency bypass clock (only for DPLL1) or the low-frequency
reference clock.
The DPLL also provides an independent clock-gating signal for each of the six output clocks. The PRCM
provides the DPLL with a clock-gating control signal, and the DPLL returns a clock activity status signal
indicating whether the output clock is effectively gated or running.
For an explanation of the DPLL multiplier, divider settings, and gating controls, see Section 4.7.6, DPLL
Control.
Each clock-generating DPLL of the device has the following features:
• Independent domain
• Control by the CM
• Fed by always-on SYS_CLK with independent gating control for the SYS_CLK
• Analog part supplied by a dedicated power supply and an embedded LDO to eliminate 1-MHz noise
• Up to six independent output dividers for simultaneous generation of multiple output clocks with
different frequencies
4.7.3.3.1 DPLL1 (MPU)
DPLL1 is in the MPU subsystem. It supplies clocks to this subsystem that are used as the source clocks
for internally generating all subsystem clocks.
DPLL1 uses a reference clock to produce its synthesized clock. It receives the reference clock
(DPLL1_ALWON_FCLK) from the PRM and its high-frequency bypass clock (DPLL1_FCLK) from the CM.
The reference clock is SYS_CLK and the high-frequency bypass clock is CORE_CLK.
To save on DPLL power consumption by the processor, the high-frequency bypass input clock from
DPLL3 (CORE) is used when the DPLL is set to bypass mode (either statically, or dynamically during
relock time) or when the processor is not required to run faster than at L3 clock speed. This use of the
high-frequency bypass input clock also optimizes the performance of the DPLLs during frequency scaling.
4.7.3.3.2 DPLL3 (CORE)
Figure 4-27 is the block diagram of DPLL3.
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Figure 4-27. DPLL3 Clocks
WKUP domain
CORE
domain
PRM
DPLL3_ALWON_FCLK
Crontrol
CM
DPLL3 domain
DPLL3
M2
M2 (X2)
M3
DPLL3_M2_CLK
DPLL3_M2X2_CLK
EMU_CORE_
ALWON_CLK
prcm-040
DPLL3 receives its reference clock (DPLL3_ALWON_FCLK), which is the SYS_CLK, from the PRM.
DPLL3 does not receive a high-frequency bypass clock, and it uses the reference clock as the lowfrequency bypass clock. DPLL3 supplies the source clock for all interfaces and a few functional clocks for
the device modules. It also serves as the source of the emulation trace clock. While the CORE domain is
on, the output of DPLL3 can be used as HS bypass clock input to DPLL1.
4.7.3.3.3 DPLL4 (Peripherals)
Figure 4-28 is the block diagram of DPLL4.
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Figure 4-28. DPLL4 Clocks
WKUP domain
CORE domain
PRM
DPLL4_ALWON_FCLK
Ctrl
CM
DPLL4 domain
DPLL4
M3
M2(X2)
M6
M4
EMU_PER_ALWON_CLK
DPLL4_M3X2_CLK
PRM_96M_ALWON_CLK
DSS1_ALWON_FCLK
prcm-041
DPLL4 receives its reference clock (DPLL4_ALWON_FCLK), which is the SYS_CLK, from the PRM.
DPLL4 does not receive a high-frequency bypass clock, and it uses the reference clock as the lowfrequency bypass clock. DPLL4 generates clocks for the peripherals, supplying five clock sources:
• 96-MHz always-on source clock for the PRM
• 54-MHz to TV DAC
• Display functional clock
• Emulation trace clock
The clock outputs to the DSS, PER, and EMU domains are always on.
4.7.3.3.4 DPLL5 (Peripherals)
Figure 4-29 is the block diagram of DPLL5.
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Figure 4-29. DPLL5 Clocks
WKUP domain
CORE domian
PRM
CM
Ctrl
DPLL5_ALWON_FCLK
DPLL5 domain
DPLL5
M2
120M_FCLK
prcm-089
DPLL5 receives its reference clock (DPLL5_ALWON_FCLK), which is the SYS_CLK, from the PRM.
DPLL5 does not receive a high-frequency bypass clock, and it uses the reference clock as the lowfrequency bypass clock. DPLL5 generates clocks for the peripherals, supplying five clock sources:
• 120-MHz functional clock to the peripheral domain modules.
• USIM source clock for the functional clock of the USIM open-core protocol (OCP) in the WKUP
domain.
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4.7.3.3.5 DPLL Clock Summary
Table 4-23 summarizes the use of the divided output clocks of the five DPLLs in the device.
Table 4-23. DPLL Output Clocks
CLKOUT_M2
CLKOUT_M2X2
DPLL1
DPLL3
X
X
DPLL4
DPLL5
(1)
4.7.3.4
CLKOUT_M3X2
CLKOUT_M4X2
CLKOUT_M5X2
CLKOUT_M6X2
X
X
X
(1)
X
X
X
X
X
X represents the DPLL clock output used.
32-kHz Oscillator
An internal 32-kHz always-on oscillator feeds the secure watchdog timer (WDTIMER1) and the secure
timer (GPTIMER12). It is not software-controllable. The oscillator ensures protection for these timers
against clock stoppage caused by an external attack.
4.7.3.5
Summary
Table 4-24 summarizes the source clocks in the device.
Table 4-24. Source-Clock Summary
Clock Name
External/Internal Source
Clock Generator
32K_FCLK
sys_32k (input pin)
PRM
SYS_CLK
Oscillator
PRM
System clock. Serves as primary
source clock of the device. Also used
as functional and interface clock for
PRM.
DSS_TV_CLK
DPLL4/sys_altclk (input pin)
CM
DSS TV clock
120M_FCLK
DPLL5
CM
96M_FCLK
DPLL4
CM
48M_FCLK
DPLL4/sys_altclk (input pin)
CM
12M_FCLK
DPLL4/sys_altclk (input pin)
CM
96M_ALWON_CLK
232
Description
DPLL4
Direct from DPLL4
CORE_CLK
DPLL3
CM
DPLL3 clock output frequency
COREX2_CLK
DPLL3
CM
DPLL3 clock output frequency x 2
L3_ICLK
DPLL3
CM
L3 interconnect interface clock
L4_ICLK
DPLL3
CM
L4 interconnect interface clock
MPU_CLK
DPLL1
MPU subsystem source clock
SECURE_32K_FCLK
32-kHz oscillator
Generated internally by an RC
oscillator. It is always active.
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4.7.4 Clock Distribution
4.7.4.1
Domain Clock Distribution
This section describes the PRCM clock distribution over device domains:
4.7.4.1.1 MPU Domain
The PRCM does not directly provide any clock to the MPU domain. It feeds only DPLL1, which generates
MPU_CLK. All clocks are then locally generated by the clock generator in the MPU subsystem.
Figure 4-30 shows the clocking scheme in the MPU domain.
Figure 4-30. MPU Domain Clocking Scheme
CORE domain
WKUP domain
PRM
CM
DPLL1_ALWON_FCLK
DPLL1_FCLK
L3_ICLK
DPLL1 domain
DPLL1
MPU domain
MPU_CLK
MPU core
Clock generator
Asynchronous
bridge - slave
Asynchronous
bridge - master
MPU INTC
CORE domain
MPU subsystem
prcm-042
4.7.4.1.2 SGX Domain
This section gives information about all modules and features in the high-tier device. See Chapter 1,
Device Family section, to check availability of modules and features. For power savings considerations,
ensure that clocks to unused modules are properly cut off.
The SGX subsystem interface clock is sourced by the L3 clock, whereas the functional clock source can
be selected between CORE_CLK and CM_96M_FCLK. When the functional clock source is CORE_CLK,
its frequency can be divided (by 3, 4, or 6).
Figure 4-31 shows the clocking scheme in the SGX domain.
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Figure 4-31. SGX Domain Clocking Scheme
CORE domain
CM
L3_ICLK
CORE_CLK CM_96M_FCLK
Divider
[3, 4, 6]
mux
SGX_L3_ICLK
SGX_FCLK
SGX subsystem
SGX domain
prcm-044
4.7.4.1.3 CORE Domain
The CORE domain has both L3- and L4-derived clock domains.
The CORE domain receives several functional clocks (12-, 48-, 96-MHz, system, and 32-kHz) that feed its
peripherals and modules, with an exception:
• The McBSP 1 and McBSP 5 modules can be clocked either by CORE_96M_FCLK from the CM or
from an external clock, MCBSP_CLKS. The SCM manages the selection between the two sources. For
more information about the SCM, see System Control Module chapter.
Figure 4-32 through Figure 4-34 show the clock signals and their relationships in the CORE domain.
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Figure 4-32. CORE Clock Signals: Part 1
CORE domain
CM
L3_ICLK
CORE_L4_ICLK
CORE_L3_ICLK
L4_ICLK
L3 interconnect
SMS
HS USB
MPU
Async - slave
SDMA
OCM
ROM
GPMC
OCM
RAM
SDRC
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Figure 4-33. CORE Clock Signals: Part 2
Wake-up domain
PRM
CM_SYS_CLK
USBTLL_SAR_FCLK
CM_32K_CLK
CORE domain
MMC[1, 2, 3]
UART[1, 2]
HDQ/1-wire
I2C[1, 2, 3]
McSPI[1–4]
EMU async
bridge
MUX
MUX
CORE_32K_FCLK
L4_ICLK 12M_FCLK
CORE_12M_FCLK
CORE_120M_FCLK
From system
control module
48M_FCLK
CORE_48M_FCLK
120M_FCLK
CORE_L4_ICLK
CM
96M_FCLK
CORE_96M_FCLK
MCBSP_CLKS
MUX
Temp. sensor (x2)
GPTIMER
[10, 11]
GPT11_FCLK
GPT10_FCLK
McBSP[1, 5]
USB TLL
prcm-046
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Figure 4-34. CORE Clock Signals: Part 3
CORE domain
CM
CORE_L4_ICLK
L4_ICLK
CORE L4
interconnect
System
control
prcm-047
4.7.4.1.4 IPSS Domain
The IPSS domain receives following clocks from the system:
• L3_ICLK: interface clock that feeds VBUS, VBUS2OCP and OCP2VBUS architecture of IPSS. This
clock is used as interface clock for all the IPSS modules.
• SYS_CLK: used as functional clock for HECC module and as source clock for USBOTG SS.
External clocks include:
• rmii_50mhz_clk: This clock feeds EMAC module for RMII functionality. (Refer to the EMAC chapter for
more information on EMAC and RMII clocks.)
• rmii_mdio_clk: This is the output clock coming from EMAC which is used for external PHY.
• ccdc_pclk: This is the VPFE pixel clock input from the external sensor. (Refer to the VPFE chapter for
more information on ccdc_pclk.)
The CONTROL_IPSS_CLK_CTRL register controls the clocking for IPSS. The field ipss_vbusp_clk_en
has the gating control for interface clock and ipss_func_clk_en field will switch ON the functional clock for
the IPSS modules (VPFE, USBOTG, HECC and EMAC). Few of the modules use their interface clock as
functional clock, for more details refer to corresponding modules chapter.
Software can program ipss_vbusp_clk_en register bits to put corresponding modules in IDLE mode. It
needs to read ipss_vbusp_clk_en_ack bits to make sure that these module clocks are gated. (Refer to the
System Control Module chapter for more details.)
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Figure 4-35. IPSS Domain
System Control
ipss_vbusp_clk_en[3:0]
PRM
CM
ipss_func_clk_en[3:0]
ipss_vbusp_clk_en_ack[3:0]
SYS_CLK
L3_iCLK
ccdc_pclk
rmii_50Mhz_clk
IPSS SUBSYSTEM
rmii_mdio_clk
prcm-015
4.7.4.1.5 EFUSE Domain
Figure 4-36 shows the clock signals and their relationships in the EFUSE domain.
Figure 4-36. EFUSE Clock Signals
WKUP domain
PRM
SYS_CLK
EFUSE_ALWON_FCLK
Efuse FARM
EFUSE domain
prcm-048
The EFUSE sense procedure is performed at device power up. During this procedure, the PRM enables
the EFUSE_ALWON_FCLK clock.
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4.7.4.1.6 DSS Domain
This section gives information about all modules and features in the high-tier device. See Chapter 1,
Device Family section, to check availability of modules and features. For power savings considerations,
ensure that clocks to unused modules are properly cut off.
Figure 4-37 shows the clock signals and their relationships in the DSS domain.
Figure 4-37. DSS Clock Signals
DPLL4 domain
WKUP domain
CORE domain
CM
96M_FCLK
PRM
DSS_TV_FCLK
L3_ICLK
L4_ICLK
SYS_CLK
DSS2_ALWON_FCLK
DSS_L4_ICLK
DSS_L3_ICLK
DSS_96M_FCLK
DSS1_ALWON_FCLK
DPLL4
VDAC
Display subsystem
DSS domain
prcm-049
The DSS subsystem interface is clocked with the L3 and L4 clocks. It receives four functional clocks:
• DSS1_ALWON_FCLK: Issued from DPLL4. Its frequency can be a division by 1 to 16 of the frequency
of the DPLL4 synthesized clock.
• DSS2_ALWON_FCLK: The gated SYS_CLK. Used mainly for display in low-power refresh modes.
• DSS_96M_FCLK: Required when TV output is activated
• DSS_TV_FCLK: Required when TV output is activated
4.7.4.1.7 USBHOST Domain
Figure 4-38 shows the clock signals and their relationships in the USBHOST domain.
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Figure 4-38. USBHOST Clock Signals
WKUP domain
CORE domain
PRM
OSC_SYS_CLK
USBHOST_SAR_FCLK
USBHOST_120M_FCLK
48M_FCLK 120M_FCLK
USBHOST_48M_FCLK
L4_ICLK
USBHOST_L4_ICLK
USBHOST_L3_ICLK
CM
L3_ICLK
USBHOST subsystem
USBHOST domain
prcm-090
The HS USB Host subsystem interface is clocked with the L3 and L4 clocks (USBHOST_L3_ICLK and
USBHOST_L4_ICLK, respectively).
The HS USB Host subsystem requires two functional clocks (USBHOST_120M_FCLK and
USBHOST_48M_FCLK) that may or may not be requested simultaneously. Therefore, they are gated
independently based on the configuration of the CM_FCLKEN_USBHOST[0] EN_USBHOST1 and
CM_FCLKEN_USBHOST[1] EN_USBHOST2 bits.
The HS USB Host subsystem gets an additional functional clock from the PRM (USBHOST_SAR_FCLK).
It is dedicated to the save-and-restore mechanism and is automatically gated/enabled by the PRM, based
on the HS USB Host save-and-restore bit configuration (that is, the PM_PWSTCTRL_USBHOST[4]
SAVEANDRESTORE bit) and on the USBHOST domain state transitions.
4.7.4.1.8 WKUP Domain
Figure 4-39 shows the clock signals and their relationships in the WKUP domain.
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Figure 4-39. WKUP Clock Signals
WKUP domain
PRM
SYS_CLK
32K_FCLK
MUX
WKUP_32K_FCLK
GPT1_FCLK
WKUP L4
interconnect
GPTIMER1
32-kHz
Sync Timer
WDTIMER2
GPIO1
WKUP_L4_ICLK
prcm-051
All clocks in the WKUP domain are generated by the PRM, except for the functional clock for the secure
timers (WDTIMER1 and GPTIMER12). This clock is supplied directly by the internal 32-kHz oscillator
(SECURE_32K_FCLK). The functional clock GPT1_FCLK of GPTIMER1 can be selected as either
SYS_CLK or 32K_FCLK. The 32-kHz sync timer, WDTIMER2, and GPIO1 receive 32K_FCLK as their
functional clock. This is the low-frequency always-on clock.
The PRM receives SYS_CLK as the L4 interface clock. For all other modules of the WKUP domain, the L4
interface clock WKUP_L4_ICLK is derived from SYS_CLK. Communication between the WKUP domain
and CORE L4 interconnects is asynchronous.
The USIM OCP module receives the functional clocks (USIM_FCLK and 32K_FCLK) and the L4 interface
clock (WKUP_L4_ICLK) from the PRM.
4.7.4.1.9 PER Domain
Figure 4-40 shows the clock signals and their relationships in the PER domain.
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Figure 4-40. PER Clock Signals
WKUP domain
CORE domain
CM
48M_FCLK
PRM
L4_ICLK
32K_FCLK
SYS_CLK
PER_32K_ALWON_FCLK
96M_ALWON_FCLK
PER_L4_ICLK
PER_48M_FCLK
MCBSP_CLKS
MUX
´8
GPT9_ALWON_FCLK
GPT8_ALWON_FCLK
GPT7_ALWON_FCLK
GPT6_ALWON_FCLK
GPT5_ALWON_FCLK
GPIO6
GPIO5
GPIO4
GPIO3
GPIO[2–6]
GPT3_ALWON_FCLK
PER L4
interconnect
WDTIMER3
GPT4_ALWON_FCLK
UART3
GPT2_ALWON_FCLK
PER domain
MUX
GPT9
GPT8
GPT7
GPT6
GPT5
GPT4
GPTIMER
GPT3
[2..9]
McBSP[2–4]
prcm-052
The PER domain receives several functional clocks (48M_FCLK, 96M_ALWON_FCLK, SYS_CLK, and
32K_FCLK) that feed its peripherals and modules. All the functional clocks (except 48M_FCLK) are
permanently supplied so that the peripherals can be used during low-power scenarios. Figure 4-40 shows
the clock distribution scheme in the PER domain.
The McBSP 2, 3, and 4 modules can be clocked either by a clock from PRM (PER_96M_FCLK) or from
an external clock (MCBSP_CLKS). This clock must be permanently buffered from the pad to the PER
domain. The device SCM manages the selection between the two (see System Control Module chapter).
4.7.4.1.10 DPLL Domains
The PRCM provides clock sources for the DPLLs, as shown in Figure 4-41
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DPLL5_ALWON_FCLK
DPLL5 domain
DPLL5_M2X2_CLK
DPLL5 (PER2)
Figure 4-41. DPLL Clock Signals
DPLL4_M3X2_CLK
DPLL4_ALWON_FCLK
DPLL4_M4X2_CLK
DPLL4 domain
DPLL4_M5X2_CLK
DPLL4 (PER)
DPLL4_M6X2_CLK
DPLL3_ALWON_FCLK
DPLL1_ALWON_FCLK
PRM
Wake-up domain
MPU
DPLL3 domain
DPLL1_FCLK
DPLL1_M2X2_CLK
CM
CORE domain
MPU domain
DPLL3_M2X2_CLK
DPLL1 domain
DPLL3_M2_CLK
DPLL3 (CORE)
DPLL3_M3X2_CLK
DPLL1 (MPU)
DPLL4_M2X2_CLK
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The PRCM also manages clock-gating control for these DPLL outputs.
The MPU uses clock outputs locally in the subsystem. The CM uses the DPLL3 clock outputs to generate
all interface clocks and some functional clocks. The CM uses two of the five clocks generated by DPLL4
and one clock output of DPLL5 to generate functional clocks for the peripheral domain modules. The
remaining three clocks of DPLL4 are propagated to their corresponding modules.
4.7.4.2
Clock Distribution Summary
4.7.4.2.1 Domain Source Clocks
Table 4-25 summarizes clock distribution for each domain.
Table 4-25. Clock Distribution
Power Domain
MPU
Clock
MPU_CLK
Generator
DPLL1
NEON
SGX
CORE
DSS
NEON
SGX_FCLK
CM
SGX_L3_ICLK
CM
CORE_ 120M_FCLK
CM
USB TLL
CORE_ 96M_FCLK
CM
McBSP[1,5], MMC[1,2,3], I2C[1,2,3]
CORE_48M_FCLK
CM
UART[1,2], McSPI[1..4]
CORE_12M_FCLK
CM
HDQ
GPT10_FCLK
CM
GPTIMER10
GPT11_FCLK
CM
GPTIMER11
CPEFUSE_FCLK
CM
SGX subsystem
CPEFUSE
USBTLL_SAR_FCLK
PRM
USB TLL
CM_32K_CLK
PRM
Temperature sensor (x2), MMC[1,2,3]
CORE_L3_ICLK
CM
L3 interconnect, SDMA, MPU Async
Bridge(Slave), USB20OTGSS, SMS, GPMC,
OCM ROM, SDRC, OCM RAM, CORE L3
interconnect
CORE_L4_ICLK
CM
L3 interconnect, SDMA, McBSP[1,5], MMC[1,2],
I2C[1..3], GPTIMER [10,11], UART[1,2],
McSPI[1..4], HDQ, CORE L4 interconnect,
SCM
DSS_TV_FCLK
CM
DSS, VDAC
DSS_96M_FCLK
CM
VDAC
DSS1_ALWON_FCLK
DPLL4
DSS2_ALWON_FCLK
PRM
DSS_L3_ICLK
DSS_L4_ICLK
PER
Destination
MPU subsystem
96M_ALWON_FCLK
PER_48M_FCLK
PER_32K_ALWON_FCLK
DSS
CM
CM
PRM
McBSP[2..4]
CM
UART3
CM
WDTIMER3, GPIO[2..6],
GPT2_ALWON_FCLK
PRM
GPTIMER2
GPT3_ALWON_FCLK
PRM
GPTIMER3
GPT4_ALWON_FCLK
PRM
GPTIMER4
GPT5_ALWON_FCLK
PRM
GPTIMER5
GPT6_ALWON_FCLK
PRM
GPTIMER6
GPT7_ALWON_FCLK
PRM
GPTIMER7
GPT8_ALWON_FCLK
PRM
GPTIMER8
GPT9_ALWON_FCLK
PRM
GPTIMER9
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Table 4-25. Clock Distribution (continued)
Power Domain
Clock
PER_L4_ICLK
WKUP
WKUP_32K_FCLK
SECURE_32K_FCLK
Generator
CM
PRM
32-kHz oscillator
Destination
UART3, PER L4 interconnect, WDTIMER3,
GPIO[2..6], GPTIMER[2..9], McBSP[2..4]
WDTIMER2, GPIO1
WDTIMER1, GPTIMER12
32K_FCLK
PRM
32-kHz sync timer, USIM OCP
GPT1_FCLK
PRM
GPTIMER1
USIM_FCLK
CM
USIM OCP
WKUP_L4_ICLK
PRM
WKUP L4 interconnect, GPTIMER[1,12], 32kHz sync timer, GPIO1, WDTIMER[1,2], USIM
OCP
EFUSE
EFUSE_ALWON_FCLK
PRM
eFuse farm
DPLL1
DPLL1_ALWON_FCLK
PRM
DPLL1
DPLL1_FCLK
CM
DPLL3
DPLL3_ALWON_FCLK
PRM
DPLL3
DPLL4
DPLL4_ALWON_FCLK
PRM
DPLL4
DPLL5
DPLL5_ALWON_FCLK
PRM
DPLL5
NOTE:
•
Modules supplied by the L3 interface clock only:
•
– MPU asynchronous bridge
– All memory controllers (OCM ROM, OCM RAM, SDRC, SMS, and GPMC)
Modules that require both L3 and L4 clocks:
•
– SDMA
– HS USB
– All security modules (FPKA, AES, RNG, SHAM, and D3D)
Modules fed by the L4 clock:
–
–
SCM
All peripherals (McBSP1, McBSP5, MMC1, MMC2, I2C1, I2C2, I2C3, McSPI1,
McSPI2, McSPI3, McSPI4, UART1, UART2, HDQ, GPTIMER10, and GPTIMER11)
4.7.4.2.2 Peripheral Module Clocks
Table 4-26 lists the peripherals and DSS functional clock frequency requirements.
Table 4-26. Peripheral Module Functional Clock Frequencies
Module
Functional Clock
Frequency
MMC-SDIO[1,2,3]
96M_FCLK
96 MHz
McBSP[1, 5]
96M_FCLK
96 MHz
McSPI[1..4]
CORE_48M_FCLK
48 MHz
DSS1_ALWON_FCLK
Up to 173 MHz
DSS2_ALWON_FCLK
System clock
DSS_96M_FCLK
96 MHz
UART[1..3]
Display subsystem
DSS_TV_FCLK
54 MHz
I2C[1..3]
CORE_96M_FCLK
96 MHz
HDQ
CORE_12M_FCLK
12 MHz
GPT1_FCLK
32-kHz (p) or system clock
GPTn_ALWON_FCLK
32-kHz (p) or system clock
GPTIMER1
GPTIMER[2..9]
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Table 4-26. Peripheral Module Functional Clock Frequencies (continued)
Module
Functional Clock
Frequency
GPTn_FCLK
32-kHz or system clock
GPTIMER12
SECURE_32K_FCLK
32 kHz (p) (s)
FPKA1
SECURITY_L3_ICLK
L3_ICLK
AES 1
SECURITY_L4_ICLK2
L4_ICLK
CORE_L4_ICLK
L4_ICLK
SECURE_32K_FCLK
32 kHz (p) (s)
WDTIMER2
WKUP_32K_FCLK
32 kHz
WDTIMER3
PER_32K_ALWON_FCLK
32 kHz
WKUP_32K_FCLK
32 kHz
PER_32K_ALWON_FCLK
32 kHz
32-kHz sync timer
32K_FCLK
32 kHz (p)
Bandgap/temp sensor
32K_FCLK
32 kHz (p)
CORE_L4_ICLK
L4_ICLK
GPTIMER[10, 11]
D3D 1
SHAM 1
RNG1
AES 2
SHAM 2
D3D 2
WDTIMER1
GPIO1
GPIO[2-6]
System control
4.7.5 External Clock Controls
Because the use of sys_32k and sys_altclk was discussed previously (see Section 4.7.3.1, PRM, and
Section 4.7.3.2, CM), these clock signals are not discussed here. This section discusses the remaining
external clock signals.
4.7.5.1
Clock Request (sys_clkreq) Control
The system clock request signal sys_clkreq is bidirectional. In bypass mode in the system clock oscillator
(see Section 4.7.5.2), it is an output signal driven by the device to request an external clock. In this case,
the output buffer is driven as long as the system clock is requested by the device; otherwise, it remains in
high impedance. In this way, other external peripherals can share the same clock request signal with the
device.
If PRM_POLCTRL.CLKREQ_POL = 1, the software must configure the SCM to select the internal
pulldown on the sys_clkreq pad, or an external pulldown is connected to the pad. If
PRM_POLCTRL.CLKREQ_POL = 0, the internal pull-up on the sys_clkreq pad, or an external pull-up is
connected to the pad.
In master mode in the system clock oscillator (see Section 4.7.5.2), sys_clkreq is an input. If
PRM_POLCTRL.CLKREQ_POL = 1, the software must configure the SCM to select the internal pulldown
on the sys_clkreq pad, or an external pulldown is connected to the pad. If PRM_POLCTRL.CLKREQ_POL
= 0, the internal pull-up on the sys_clkreq pad, or an external pull-up is connected to the pad.
The PRCM.PRM_POLCTRL[1] CLKREQ_POL bit allows software control over the polarity of sys_clkreq.
This software setting takes effect when the clock is requested by the device and also when the clock
request is driven externally. The output buffer is directly driven by this register when the clock request
comes from the device.
Table 4-27 shows the bidirectional control of the sys_clkreq Pad:
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Table 4-27. sys_clkreq Pad Direction Control
Description
Oscillator
Mode
Master
Mode
Bypass
Mode
(1)
(2)
4.7.5.2
Sys_boot6
Internal Clock
request (always
active high)
External Clock
Sys_clkreq Direction
request (Note:
polarity depends
on
CLKREQ_POL)
0
0
0 (1)
Input (Output buffer in Hi-Z)
Note: (Input is not driven from
outside of the device in that
case)
The clock is neither requested
internally nor externally
(external device/peripheral)
0
0
1 (1)
Input (Output buffer in Hi-Z)
The clock is requested
externally
0
1
0 (1)
Output
The clock is requested
internally
0
1
1 (1)
Output Note: (The pad is driven The clock is requested both
both by the device and from
internally and externally
outside of the device in taht
case.)
1
0
0 (1)
Input (Output buffer in Hi-Z)
Note: (Input is not driven from
outside of the device in that
case.)
The clock is neither requested
internally nor externally
1
0
1 (2)
Input (output buffer in Hi-Z)
The clock is requested
externally
1
1
0 (2)
Output
The clock is requested
internally
1
1
1 (2)
Output Note: (Input is not
driven from outside of the
device in that case.)
The clock is requested both
internally and externally
Case when PRM_POLCTRL.CLKREQ_POL = 1 (sys_clkreq active high). These values would be inverted in the table above, in
case PRM_POLCTRL.CLKREQ_POL = 0 (sys_clkreq active low).
Case when PRM_POLCTRL.CLKREQ_POL = 1 (sys_clkreq active high). These values would be inverted in the table above, in
case PRM_POLCTRL.CLKREQ_POL = 0 (sys_clkreq active low).
System Clock Oscillator Control
Depending on the hardware configuration, the device can receive the system clock from an external
source or generate it locally using the internal system clock crystal oscillator. Thus, the device oscillator
has two possible operating modes:
• Master (oscillator enable) mode: The oscillator is enabled and connected to an external quartz. It
provides the system clock to the device. The oscillator is activated on a device wake-up or on an
external clock request.
• Bypass (oscillator inactive) mode: The system clock is supplied by an external device and the oscillator
is always set in bypass mode. The oscillator is insensitive to the external system clock request on the
sys_clkreq pin.
NOTE: An external pullup or pulldown tied on the sys_boot6 input pin of the device determines
whether the oscillator is in master or bypass mode. See Section 4.3.1, External Clock
Signals.
When operating in master mode, the device receives an external clock request (sys_clkreq) and provides
the system clock to external peripherals through the sys_clkout1 pin; in bypass mode, the device
generates a clock request to the external clock source to request the system clock.
The selected mode of the oscillator can be read from the PRCM.PRM_CLKSRC_CTRL[1:0] SYSCLKSEL
bit field.
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Whatever the oscillator mode, the oscillator can be powered down when the device enters inactive mode,
unless an external system clock request is active (from the sys_clkreq pin). Note that this option can only
be used if the 32kHz clock is not derived from the high frequency sysclk, as the 32kHz clock is required
for autonomous wakeup capability. This setting is configured in the PRCM.PRM_CLKSRC_CTRL[4:3]
AUTOEXTCLKMODE bit field. Table 4-29 lists the four possible operation modes of the system clock.
Table 4-28. System Clock Operation Modes
AUTOEXTCLKMODE
System Clock Mode
Oscillator Mode
0x0
Always-active mode
Master
The oscillator is kept active even when the
clock is neither requested by the device
internally (all device clocks are inactive) nor
externally (that is, the sysclkreq input signal is
not asserted).
Bypass
The sys_clkreq output signal is permanently
asserted by the device, regardless of its
internal clocks state (active or inactive).
Master
The oscillator is switched off when the device
is in INACTIVE mode and the sys_clkreq input
signal is not asserted.
Bypass
The sys_clkreq output signal is de-asserted
when the device is in idle mode.
0x1
Off when device in
INACTIVE state
Description
To exit power-down mode, the oscillator requires a device wakeup or an external clock request.
The device allows configuring of the system clock stabilization time to ensure a stable system clock in the
device. This delay is configured in the PRCM.PRM_CLKSETUP[15:0] SETUP_TIME bit field.
Figure 4-42 shows the system clock oscillator controls in the device.
Figure 4-42. System Clock Oscillator Controls
PRCM
sys_xtalout
OSC_SYS_CLK
PRM
Oscillator
sys_xtalin
sys_clkreq
Internal clock request
Device
power FSM
Control
logic
sys_boot6
prcm-055
Table 4-29 lists the oscillator controls.
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Table 4-29. Oscillator Controls
Oscillator
Mode
Internal
Clock
Request (1)
External
Clock
Request (1)
Oscillator
State
sys_clkreq
Pad Direction
sys_clkreq (1)
Description
Master
Not asserted
Not asserted
Off
Both input and output
Not asserted
System clock not requested
internally (within the device)
and externally (by an
external device or
peripheral).
Not asserted
Asserted
Active
Input
Asserted
System clock is requested
externally only.
Asserted
Not asserted
Active
Output
Asserted
System clock is requested
internally only.
Asserted
Asserted
Active
Both input and output
(that is, driven
internally by device
and externally by
peripheral)
Asserted
System clock is requested
internally and externally.
Not asserted
x (2)
Bypass
Both input and output
(when external
request is not
asserted) or input
(when external
request is asserted)
Asserted
x (2)
Bypass
Output (when only
internal request is
asserted) or both
input and output
(when external and
internal request are
asserted)
Bypass
External clock System clock is not
request state requested internally
(sys_clkreq input has no
effect).
Asserted
System clock is requested
internally (sys_clkreq input
has no effect).
(1)
(2)
4.7.5.3
•
If the PRCM.PRM_POLCTRL[1] CLKREQ_POL is set to active high (that is, 0x1), Asserted = 1, and Not asserted = 0.
•
If the PRCM.PRM_POLCTRL[1] CLKREQ_POL is set to active low (that is, 0x0), Asserted = 0, and Not asserted = 1.
x indicates that the signal may be asserted or not asserted.
External Output Clock1 (sys_clkout1) Control
The sys_clkout1 clock is active if the oscillator clock (OSC_SYS_CLK) is active (stable) and an external
system clock request is active. It can be gated by programming the PRCM.PRM_CLKOUT_CTRL[7]
CLKOUT_EN bit. The polarity of the sys_clkout1 signal, when the clock is gated, is controllable by
programming the PRCM.PRM_POLCTRL[2] CLKOUT_POL bit.
When the device is in standby mode, both SYS_CLK and sys_clkout1 are disabled. In that case,
reactivation of sys_clkout1 depends on the oscillator mode:
• Oscillator in active mode (sys_boot6 is 0): The sys_clkout1 clock can be reactivated (after oscillator
stabilization), provided its gating was previously enabled by programming the
PRCM.PRM_CLKOUT_CTRL[7] CLKOUT_EN bit and asserting an external clock request. This
activation does not generate a device wake-up event; an external clock request activates only the
internal SYS_CLK oscillator and sys_clkout1.
• Oscillator in bypass mode (sys_boot6 is 1): The sys_clkout1 clock can be reactivated only after the
device wakes up (on any wake-up event) and SYS_CLK is active. When the device is active,
SYS_CLK is running and sys_clkout1 is enabled as soon as requested by software.
4.7.5.4
External Output Clock2 (sys_clkout2) Control
A second output clock, sys_clkout2, is generated with a frequency that can be the source-clock frequency
divided by 1, 2, 4, 8, or 16. Its source clock can be CORE_CLK, CM_SYS_CLK, 96 MHz, or 54 MHz. The
selected source clock must be enabled by software. Enabling sys_clkout2 does not automatically request
the required source clock. The polarity of the sys_clkout2 signal, when the clock is gated, is controllable
by programming the PRCM.CM_POLCTRL[0] CLKOUT2_POL bit.
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4.7.6 DPLL Control
The PRCM allows the configuration of the output clock frequencies of the DPLLs by setting their
respective multipliers and dividers. It also allows control of the operating mode of the DPLLs and
automatic recalibration mode.
4.7.6.1
DPLL Multiplier and Divider Factors
DPLL clock outputs are set by programming the corresponding multiplier and divider factors M, N, M2, M3,
M4, M5, and M6. Table 4-30 lists the register bit fields for configuration of the multiplier and divider factors
for the DPLLs.
Table 4-30. DPLL Multiplier and Divider Factors
4.7.6.2
DPLL1
DPLL3
DPLL4
DPLL5
M
PRCM.CM_CLKSEL1_
PLL_MPU[18:8] MPU_
DPLL_MULT
PRCM.CM_CLKSEL1_
PLL[26:16] CORE_DPLL_MULT
PRCM.CM_CLKSEL2_
PLL[18:8] PERIPH_
DPLL_MULT
PRCM.CM_CLKSEL4_
PLL[18:8] PERIPH2_
DPLL_MULT
N
PRCM.CM_CLKSEL1_
PLL_MPU[6:0] MPU_
DPLL_DIV
PRCM.CM_CLKSEL1_
PLL[14:8] CORE_DPLL_DIV
PRCM.CM_CLKSEL2_
PLL[6:0] PERIPH_
DPLL_DIV
PRCM.CM_CLKSEL4_
PLL[6:0] PERIPH2_
DPLL_DIV
M2
PRCM.CM_CLKSEL2_
PLL_MPU[4:0] MPU_
DPLL_CLKOUT_DIV
PRCM.CM_CLKSEL1_
PLL[31:27] CORE_DPLL_
CLKOUT_DIV
PRCM.CM_CLKSEL3_
PLL[4:0] DIV_96M
PRCM.CM_CLKSEL5_
PLL[4:0] DIV_120M
M3
Not used
PRCM.CM_CLKSEL1_
EMU[20:16] DIV_DPLL3
PRCM.CM_CLKSEL_
DSS[12:8] CLKSEL_TV
Not used
M4
Not used
Not used
PRCM.CM_CLKSEL_
DSS[4:0] CLKSEL_DSS1
Not used
M5
Not used
Not used
PRCM.CM_CLKSEL_
Not used
M6
Not used
Not used
PRCM.CM_CLKSEL1_
EMU[28:24] DIV_DPLL4
Not used
DPLL Jitter Correction
To satisfy the jitter specification of the DPLL at a specific internal clock frequency, set the corresponding
CM_CLKEN_PLL_processor_name>[7:4]processor_name>_DPLL_FREQSEL, CM_CLKEN_PLL[23:20]
PERIPH_DPLL_FREQSEL, CM_CLKEN_PLL[7:4] CORE_DPLL_FREQSEL, CM_CLKEN2_PLL[7:4]
PERIPH2_DPLL_FREQSEL bit field. Table 4-31 lists the possible values for the bit field and the
corresponding internal clock frequency ranges.
NOTE: The internal clock frequency is the frequency of the internal interface clock Fint, with Fint=
(CLKINP/(N + 1).
Table 4-31. Internal Clock Frequency
Bit Field Values
Clock Frequency Ranges
0x3
0.75 MHz—1.0 MHz
0x4
1.0 MHz—1.25 MHz
0x5
1.25 MHz—1.5 MHz
0x6
1.5 MHz—1.75 MHz
0x7
1.75 MHz—2.1 MHz
0xB
7.5 MHz—10 MHz
0xC
10 MHz—12.5 MHz
0xD
12.5 MHz—15 MHz
0xE
15 MHz—17.5 MHz
0xF
17.5 MHz—21 MHz
Other cases are reserved.
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NOTE: In the DPLL programming sequence, the DPLL_FREQSEL must be programmed before the
new Multiplier factor M and the Divider factor N are programmed so that the new value is
taken into account during current DPLL relock.
4.7.6.3
DPLL Frequency Ramp-Up Delay
When the DPLL switches from bypass mode to lock mode, the clock output frequency changes from
bypass clock frequency to normal operating frequency. The frequency ramp-up feature allows the DPLL
output frequency to switch gradually (in steps) from the bypass to locked frequency. Before reaching the
locked frequency, the DPLL output switches to four intermediate frequencies:
1. Fout/8
2. Fout/4
3. Fout/2
4. Fout
The time delay in passing from the bypass clock frequency to normal frequency is the ramp-up delay. The
ramp-up delay is configured by setting the
CM_CLKEN_PLL_processor_name>[9:8]processor_name>_DPLL_RAMPTIME, CM_CLKEN_PLL[25:24]
PERIPH_DPLL_RAMPTIME, CM_CLKEN_PLL[9:8] CORE_DPLL_RAMPTIME, CM_CLKEN2_PLL[9:8]
PERIPH2_DPLL_RAMPTIME bit field.
There are three possible values for the bit field and the corresponding ramp-up delays:
• 0x0: Disables the frequency ramping feature.
• 0x1: Ramp step size range is 2–40 Fint cycles.
• 0x2: Ramp step size range is 4–80 Fint cycles.
• 0x3: Ramp step size range is 12–240 Fint cycles.
NOTE: If the ramp-up time configured for the DPLL is less than the DPLL lock time, the last
frequency step, Fout/2 to Fout, gets stretched to the DPLL lock time.
4.7.6.4
DPLL Modes
DPLL supports several power modes (see Table 4-32). Each mode results in a tradeoff between power
savings and relock time.
Table 4-32. DPLL Power Modes
Mode
Clock Input
Clock Output
DPLL Power State
Power
Consumption
Latency
Locked
On
Lock frequency
ON
Maximum
N/A
Low-power bypass
On
Bypass frequency
ON
Less than locked
Same as low-power
stop
Fast-relock bypass
On
Bypass frequency
ON
Less than locked
Less than lowpower bypass
Low-power stop
On
Bypass frequency
ON
Less than locked
Same as low-power
bypass
MN bypass
On
Bypass frequency
ON
Less than locked
Maximum
Off
Off
Off
OFF
Minimum
Maximum
A DPLL power mode can be achieved on a software request (manual) and/or automatically (automatic),
depending on the specific hardware conditions. After a device power-on reset, the DPLL can be kept in
either low-power stop mode (DPLL4 and DPLL5) or MN bypass mode (DPLL1 and DPLL3).
A DPLL can switch from one mode to the other as a result of the following:
• Software-programmed transition only (manual): The software configures a dedicated register for the
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next desired DPLL mode. It must ensure that the transition can be performed based on the activity on
the device.
Combined software-programmed and hardware-conditions-based transition (automatic): The PRCM
triggers the transition when the software requests it (by configuring the registers) and the hardware
conditions are satisfied. When the hardware conditions are no longer met, the PRCM triggers the
return transition.
For automatic transition, automatic mode must be enabled by programming the
PRCM.CM_AUTOIDLE_PLL or the PRCM.CM_AUTOIDLE_PLLprocessor_name> registers.
Table 4-33 describes the manual and automatic control of the DPLL power modes by the PRCM.
Table 4-33. DPLL Power Modes Support
DPLL4
DPLL5
Locked
Mode
Software request
(manual) or MPU wakes
up (automatic).
DPLL1
Software request
(manual) or CORE
wakes up (automatic).
DPLL3
Software request
(manual) or at least one
peripheral clock is used
(automatic).
Software request
(manual) or at least one
peripheral clock is used
(automatic).
Low-power bypass
Software request
(manual)
Software request
(manual) or all interface
clocks are gated
(automatic).
N/A
N/A
Fast-relock bypass
N/A
Software request
(manual).
N/A
N/A
Low-power stop
MPU is idle (automatic).
Device is idle
(automatic).
(Default state) Software
request (manual) or all
functional clocks from
DPLL are unused or on
global reset release
(automatic).
(Default state) Software
request (manual) or all
functional clocks from
DPLL (120-MHz clock)
are unused or on global
reset release
(automatic).
MN bypass
Global reset (automatic)
Global reset (automatic). N/A
N/A
Off
Device off (automatic)
Device off (automatic).
Device off (automatic)
Device off (automatic)
NOTE: DPLL1 and DPLL3 cannot be manually forced to switch to Low-Power Stop mode from any
other power mode. They must be in Locked state with automatic transition to Low-Power
Stop mode configured and the hardware condition for the transition (identified in Table 4-33)
must be satisfied, in order to switch to the Low-Power Stop mode.
Table 4-34 lists the bit fields that must be programmed for manual and automatic mode control of the four
DPLLs.
Table 4-34. DPLL Power Mode Control
252
Mode
Manual Control
Auto Control
DPLL1
PRCM.CM_CLKEN_PLL_MPU[2:0]
EN_MPU_DPLL
PRCM.CM_AUTOIDLE_PLL_MPU[2:0] AUTO_MPU_DPLL
DPLL3
PRCM.CM_CLKEN_PLL[2:0]
EN_CORE_DPLL
PRCM.CM_AUTOIDLE_PLL[2:0] AUTO_CORE_DPLL
DPLL4
PRCM.CM_CLKEN_PLL[18:16]
EN_PERIPH_DPLL
PRCM.CM_AUTOIDLE_PLL[5:3] AUTO_PERIPH_DPLL
DPLL5
PRCM.CM_CLKEN2_PLL[2:0]
EN_PERIPH2_DPLL
PRCM.CM_AUTOIDLE2_PLL[2:0] AUTO_PERIPH2_DPLL
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NOTE: The DPLL automatically enters locked mode on a domain wakeup only if the DPLL is locked
before the sleep transition and one of the automatic modes is enabled.
4.7.6.5
DPLL Low-Power Mode
The DPLL can operate in a low-power mode by reducing the operating frequency range. This in turn
reduces the power consumption of the DPLL. In this mode, however, there is a period and phase jitter
effect.
The DPLL can enter this mode only if the targeted lock frequency of the DPLL is less than 600 MHz. This
implies locking or relocking the DPLL to a new targeted locked-frequency when entering or exiting lowpower mode. Software must ensure that the DPLL lock-frequency does not exceed 600 MHz in low-power
mode.
Software can enable/disable automatic switching of the DPLL between normal mode and low-power
mode. The new mode is effective only after the DPLL is relocked. Low-power mode control is considered
only during the following transitions:
• From bypass mode to lock
• From stop mode to lock
• From lock to relock
Table 4-35 lists the bit fields that must be programmed for manual control of the four DPLLs.
Table 4-35. LP Mode Control
4.7.6.6
Mode
Manual Control
DPLL1
PRCM.CM_CLKEN_PLL_MPU[10] EN_MPU_DPLL_LPMODE
DPLL3
PRCM.CM_CLKEN_PLL[10] EN_CORE_DPLL_LPMODE
DPLL4
PRCM.CM_CLKEN_PLL[26] EN_PERIPH_DPLL_LPMODE
DPLL5
PRCM.CM_CLKEN2_PLL[10] EN_PERIPH2_DPLL_LPMODE
DPLL Clock Path Power Down
DPLL3 and DPLL4 can power down the CLKOUTX2 path. A small section of logic is powered down as the
M2 post divider is also shared with the CLKOUT path, which remains functional.
The HSDIVIDER can power down each CLKOUTn path (with n in the range of 3 to 6) independently,
therefore allowing further power savings. The clock output path is also powered down when the DPLL is in
stop mode, regardless of the software setting.
Software must ensure the proper sequencing of the control. To avoid a glitch at the output, activate this
control when the clock is no longer required, and when the output clock is gated. Conversely, ensure a
delay between deactivation and reactivation of the clock by using the power-down control.
Table 4-36 lists the bit fields and the corresponding clock outputs of the DPLLs.
Table 4-36. Clock Path Power-Down Control
DPLL
Control Bit Field
Clock Path
DPLL4
PRCM.CM_CLKEN_PLL[27] PWRDN_96M
96-MHz clock output (DPLL4 output M2X2)
PRCM.CM_CLKEN_PLL[28] PWRDN_TV
DSS TV clock output (DPLL4 output M3X2)
PRCM.CM_CLKEN_PLL[29] PWRDN_DSS1
DSS1 clock output (DPLL4 output M4X2)
PRCM.CM_CLKEN_PLL[31] PWRDN_EMU_PERIPH
EMU_PERIPH clock output (DPLL4 output M6X2)
PRCM.CM_CLKEN_PLL[12] PWRDN_EMU_CORE
EMU_CORE clock output (DPLL3 output M3X2)
DPLL3
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Latencies
Lock mode for the DPLL is frequency lock.
Lock latencies depend on the internal reference frequency (FINT) of the DPLL, calculated as:
FINT = Fref / (N+1)
where Fref is the reference clock input to DPLL.
Table 4-37 lists the operating modes of the DPLL and the output clock frequency and associated lock
latency.
FREQSEL[3] = 0 refers to the following bits:
• CM_CLKEN_PLL_MPU[7]
• CM_CLKEN_PLL[7]
• CM_CLKEN_PLL[23]
• CM_CLKEN2_PLL[7]
Table 4-37. DPLL Operating Mode and Latency
Mode
CLKOUTX2
Lock Time in FINT cycles
(FREQSEL[3] = 0)
Lock Time in Fint Cycles
(FREQSEL[3]= 1)
OFF
Off
150
780
M, N reprogramming
bypass clock
150
780
Low-power stop mode Off
40
400
Low-power bypass
bypass clock
40
400
Fast-relock bypass
bypass clock
10
100
Active (locked)
CLKINP x M/(N+1)/M2 x 2
N/A
N/A
The post-divider M2 supports change on the fly. The time required to switch from the clock with the old
period to the clock with the new period depends on the old value of M2 (see Table 4-38).
Table 4-38. Time Required to Switch Clocks
4.7.6.8
Old Value of M2
Time for Switching
1
4 REFCLKs + 8 CLKOUTX2s
Even
4 REFCLKs + 2 CLKOUTX2s
Odd & > 1
4 REFCLKs + 4 CLKOUTX2s
Recalibration
A lock sequence occurs during an initial lock or during a relock following a new multiplier or divider value.
Each time the DPLL is reset or performs a lock sequence, it performs a recalibration of the output
frequency, based on the voltage and temperature conditions. By compensating for voltage and
temperature changes within a certain range, the calibration allows the lock frequency to remain steady. If
the voltage or temperature drifts outside the acceptable range, the DPLL asserts a recalibration flag.
For example, a large temperature drift can cause the DPLL to lose its lock and require recalibration. When
the DPLL locks at a temperature within the 080 degrees Celsius range, the maximum temperature drift is
approximately 55 degrees Celsius. When DPLL starts at a negative temperature, the maximum
temperature drift is higher.
If the DPLL locks at 30 degrees Celsius, the temperature can change by 60 degrees Celsius (from 30 to
+90 degrees Celsius) and the DPLL will not lose the lock. However, for temperatures above the 60
degrees Celsius range, the DPLL may need to be relocked. A new relock sequence reinitializes the
starting temperature.
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This compensation mechanism is active only while the DPLL is locked. When the DPLL is in off or bypass
mode (low-power or fast-relock), it does not assert the recalibration flag. If the voltage or temperature
exceeds the drift limits while the DPLL is not locked, and then the DPLL tries to relock, the DPLL fails to
lock within the normal delay and recalibrates automatically before eventually locking. The only difference
from a standard relock is the delay.
The DPLL can automatically start recalibration when the recalibration flag is asserted, or recalibration can
be managed by the software. The mode of operation is selected by configuring the corresponding
registers in the PRCM (see Table 4-39). The software or manual control mode is selected by default.
NOTE: Automatic recalibration of the DPLL can start at any time. While relocking, the DPLL
switches to bypass mode. For modules that are sensitive to frequency change while
operating, this can introduce operational instability. For example, the SDRC is sensitive to a
frequency change on DPLL3 because its embedded DLL relocks on a frequency change.
Any access during this DLL relock period can be corrupted. It is important, therefore, to stall
SDRC access during DPLL recalibration.
To allow the software to recalibrate the DPLL at the correct time depending on the device activity, the
PRCM can generate a wake-up event on the MPU domain, followed by an interrupt on the MPU when the
DPLL recalibration flag is asserted.
Table 4-39 summarizes the software programming control over the DPLL recalibration feature.
Table 4-39. DPLL Recalibration Controls
DPLL
Software Control
Description
DPLL1 (MPU) PRCM.CM_CLKEN_PLL_MPU[3]
MPU_DPLL_DRIFTGUARD
DPLL3
(CORE)
DPLL4 (PER)
DPLL5
(PER2)
Enable/disable the MPU DPLL automatic recalibration
feature.
PRCM.PRM_IRQENABLE_MPU[7]
MPU_DPLL_RECAL_EN
Enable/disable the MPU DPLL recalibration interrupt
to MPU.
PRCM.PRM_IRQSTATUS_MPU[7] MPU_DPLL_ST
Status of the MPU DPLL recalibration interrupt
PRCM.CM_CLKEN_PLL[3]
EN_CORE_DPLL_DRIFTGUARD
Enable/disable the CORE DPLL automatic
recalibration feature.
PRCM.PRM_IRQENABLE_MPU[5] CORE_DPLL_RECAL
Enable/disable the CORE DPLL recalibration interrupt
to MPU.
PRCM.PRM_IRQSTATUS_MPU[5] CORE_DPLL_ST
Status of the CORE DPLL recalibration interrupt
PRCM.CM_CLKEN_PLL[19]
EN_PERIPH_DPLL_DRIFTGUARD
Enable/disable the PER DPLL automatic recalibration
feature.
PRCM.PRM_IRQENABLE_MPU[6]
PERIPH_DPLL_RECAL
Enable/disable the PER DPLL recalibration interrupt
to MPU.
PRCM.PRM_IRQSTATUS_MPU[6] PERIPH_DPLL_ST
Status of the PER DPLL recalibration interrupt
PRCM.CM_CLKEN2_PLL[3]
EN_PERIPH2_DPLL_DRIFTGUARD
Enable/disable the PER DPLL2 automatic
recalibration feature.
PRCM.PRM_IRQENABLE_MPU[25]
SND_PERIPH_DPLL_RECAL_EN
Enable/disable the PER DPLL2 recalibration interrupt
to MPU.
PRCM.PRM_IRQSTATUS_MPU[25]
SND_PERIPH_DPLL_ST
Status of the PER DPLL2 recalibration interrupt
NOTE: DPLL recalibration is not necessary in real use (specified operating voltage and temperature
range).
4.7.6.9
DPLL Programming Sequence
The DPLL programming sequence follows:
1. Set the multiplier (M) and divider (N) values for the desired CLKOUT frequency (see Section 4.7.6.1).
2. Set the corresponding output dividers (M2, M3, M4, M5, and M6) (see Section 4.7.6.1).
3. Set the corresponding FREQSEL bit field to satisfy the jitter specification (see Section 4.7.6.2).
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4.
5.
6.
7.
8.
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Set the corresponding ramp-up delay (see Section 4.7.6.3).
Enable/disable the auto-recalibration feature (see Section 4.7.6.8).
Enable/disable the autoidle feature (see Section 4.7.6.4).
Mask/unmask the interrupt to the MPU (see Section 4.7.6.8).
Enable the DPLL lock mode (see Section 4.7.6.4).
4.7.7 Internal Clock Controls
This section describes the software and hardware controls of the internal source clocks. Figure 4-43
through list the clock controls. The Source selection/division column lists the PRCM register bits used to
select or divide the clocks. The Software control column lists the PRCM register bits used to
enable/disable the clocks. The Hardware control column lists the hardware conditions required to
effectively gate the clocks.
In the Hardware control column, the boxes labeled CL, GS, GC, and HC indicate specific information
about the hardware clock controls:
• CL (combinational logic): The functional or interface clock is required by more than one module across
more than one domain. The gating control is the OR combination of all the domain clock requests. If
any module of this clock domain requests the clock, the clock is not gated.
• GS (gating selection): The clock is selectable among several possible source clocks for a module. The
gating control depends on the software programming of the CM_CLKSEL_<domain_name> type of
register. The clock request of the module or domain must be set by the CM_CLKSEL bit.
• GC (gating control): The functional/interface clock is required by a single module across the domain.
The gating control depends only on the software programming of the FCLKEN/ICLKEN bit. For the
interface clock, the enable bit is effective only if autoidle mode is not used. If autoidle mode is used,
the gating control also depends on the state of the domain.
• HC (hardware control): A specific rule not covered by CL, GS, or GC.
NOTE: Because the PRCM must receive hardware acknowledgement from the different modules
before it can gate the clock, the clock is not gated immediately after the software requests
clock-gating conditions.
4.7.7.1
PRM Source-Clock Controls
Figure 4-43 shows the common source-clock controls for the PRM.
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Figure 4-43. Common PRM Source-Clock Controls
Source selection/division
Hardware control
Software control
sys_xtalout
PRCM.PRM_CLKSRC_CTRL[4:3]
AUTOEXTCLKMODE
sys_xtalin
OSC_SYS_CLK
sys_boot6
HC
sys_clkreq
PRCM.PRM_POLCTRL[1]
CLKREQ_POL
HC
PRCM.PRM_CLKSETUP[15:0]
SETUP_TIME
PRCM.PRM_CLKOUT_CTRL[7]
CLKOUT_EN
sys_clkout1
HC
PRCM.PRM_POLCTRL[2]
CLKOUT_POL
SYS_CLK
PRCM.PRM_CLKSRC_CTRL[7:6]
SYSCLKDIV
GS CL
sys_32k
CM_SYS_CLK
32K_FCLK
GS CL
CM_32K_CLK
96M_ALWON_FCLK
PRM_96M_ALWON_CLK
GS CL
GS CL
CM_96M_FCLK
prcm-056
Table 4-40 shows the common source-clock gating controls for the PRM.
Table 4-40. Common PRM Source-Clock Gating Controls
Clock Name
Reset
Clock-Gating Control
Gating Description
OSC_SYS_CLK
Running
PRCM.PRM_CLKSRC_CTRL[4:3]
AUTOEXTCLKMODE and device power state and
sys_clkreq
Gated when the oscillator is programmed
to power down with the device
sleep/retention/off transition.
sys_clkout1
Running
PRCM.PRM_CLKOUT_CTRL[7] CLKOUT_EN and Active when OSC_SYS_CLK is active,
PRCM.PRM_POLCTRL[2] CLKOUT_POL and
sys_clkout1 is enabled, and sys_clkreq is
sys_clkreq
asserted.
SYS_CLK
Running
Activated after clksetup_count_overflow
Active when OSC_SYS_CLK is active and
the SYS_CLK setup time is up.
CM_SYS_CLK
Running
PRCM.CM_CLKSEL_CORE[6] CLKSEL_GPT10,
PRCM.CM_CLKSEL_CORE[7] CLKSEL_GPT11,
and depends on the clock-gating conditions of
GPT10_FCLK and GPT11_FCLK
Active if it is the source clock of the
GPT10_FCLK or GPT11_FCLK and the
functional clock is active.
32K_FCLK
Running
None
Always-active clock from sys_32k input pin
CM_32K_CLK
Running
PRCM.CM_CLKSEL_CORE[6] CLKSEL_GPT10,
PRCM.CM_CLKSEL_CORE[7] CLKSEL_GPT11,
and depends on the clock-gating conditions of
GPT10_FCLK and GPT11_FCLK
Active if it is the source clock of the
GPT10_FCLK or GPT11_FCLK and the
functional clock is active.
CM_96M_FCLK
Gated
CM_CLKSEL1_PLL[3] SOURCE_48M bit cleared,
and depends on the clock-gating condition of
96M_FCLK, 48M_FCLK, and 12M_FCLK
Active if the derived clocks (96M_FCLK,
48M_FCLK, and 12M_FCLK) are active.
96M_ALWON_FCLK
Gated
CM_FCLKEN_PER[0] EN_MCBSP2,
CM_FCLKEN_PER[1] EN_MCBSP3, and
CM_FCLKEN_PER[2] EN_MCBSP4
Gated when none of the three McBSPs
[2..4] have their functional clock enable
requested.
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The oscillator output clock (OSC_SYS_CLK) is gated whenever the PRCM.PRM_CLKSRC_CTRL[4:3]
AUTOEXTCLKMODE bit field is programmed to power down the oscillator when the device enters
retention. In this condition, all the clock trees in the device must be gated, and the four DPLLs (DPLL1,
DPLL3, and DPLL4) must enter stop mode before this transition can occur.
SYS_CLK is gated under the same conditions as the oscillator output clock, but it is enabled only after the
oscillator stabilizes. Oscillator stabilization is determined by a counter overflow configured in the
PRCM.PRM_CLKSETUP[15:0] SETUP_TIME bit field.
The sys_clkreq active condition is described in Section 4.7.5, External Clock Control.
4.7.7.2
CM Source-Clock Controls
Figure 4-44 shows the common so