Texas Instruments | TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller (Rev. E) | User Guides | Texas Instruments TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller (Rev. E) User guides

Texas Instruments TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller (Rev. E) User guides
TMS320C6472/TMS320TCI648x DSP
Enhanced DMA (EDMA3) Controller
User's Guide
Literature Number: SPRU727E
December 2005 – Revised July 2011
2
SPRU727E – December 2005 – Revised July 2011
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Contents
...................................................................................................................................... 13
Introduction ...................................................................................................................... 15
1.1
Overview .................................................................................................................... 16
1.2
Features .................................................................................................................... 16
1.3
Terminology Used in This Document ................................................................................... 17
EDMA3 Architecture .......................................................................................................... 19
2.1
Functional Overview ...................................................................................................... 20
2.1.1 EDMA3 Controller Block Diagram .............................................................................. 20
2.1.2 EDMA3 Channel Controller (EDMA3CC) ...................................................................... 21
2.1.3 EDMA3 Transfer Controller (EDMA3TC) ...................................................................... 25
2.2
Types of EDMA3 Transfers .............................................................................................. 26
2.2.1 A-Synchronized Transfers ....................................................................................... 27
2.2.2 AB-Synchronized Transfers ..................................................................................... 28
2.3
Parameter RAM (PaRAM) ................................................................................................ 29
2.3.1 PaRAM ............................................................................................................. 30
2.3.2 EDMA3 Channel PaRAM Set Entry Fields .................................................................... 32
2.3.3 Null PaRAM Set .................................................................................................. 35
2.3.4 Dummy PaRAM Set .............................................................................................. 35
2.3.5 Dummy Versus Null Transfer Comparison .................................................................... 35
2.3.6 Parameter Set Updates .......................................................................................... 36
2.3.7 Linking Transfers ................................................................................................. 38
2.3.8 Constant Addressing Mode Transfers/Alignment Issues .................................................... 41
2.3.9 Element Size ...................................................................................................... 41
2.4
Initiating a DMA Transfer ................................................................................................. 42
2.4.1 DMA Channel ..................................................................................................... 42
2.4.2 QDMA Channels .................................................................................................. 45
2.4.3 Comparison Between DMA and QDMA Channels ........................................................... 45
2.5
Completion of a DMA Transfer .......................................................................................... 46
2.5.1 Normal Completion ............................................................................................... 47
2.5.2 Early Completion ................................................................................................. 47
2.5.3 Dummy or Null Completion ...................................................................................... 47
2.6
Event, Channel, and PaRAM Mapping ................................................................................. 47
2.6.1 DMA Channel to PaRAM Mapping ............................................................................. 47
2.6.2 QDMA Channel to PaRAM Mapping ........................................................................... 47
2.7
EDMA3 Channel Controller Regions .................................................................................... 49
2.7.1 Region Overview ................................................................................................. 49
2.7.2 Channel Controller Regions ..................................................................................... 50
2.7.3 Region Interrupts ................................................................................................. 51
2.8
Chaining EDMA3 Channels .............................................................................................. 52
2.9
EDMA3 Interrupts ......................................................................................................... 53
2.9.1 Transfer Completion Interrupts ................................................................................. 54
2.9.2 EDMA3 Interrupt Servicing ...................................................................................... 57
2.9.3 Interrupt Evaluation Operations ................................................................................. 58
2.9.4 Error Interrupts .................................................................................................... 59
2.10 Memory Protection ........................................................................................................ 60
Preface
1
2
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2.11
2.12
2.13
2.14
2.15
2.16
3
EDMA3 Transfer Examples
3.1
3.2
3.3
3.4
4
4.3
Tips
A.1
A.2
4
60
63
65
66
66
66
67
67
67
69
69
70
70
72
72
72
73
73
73
73
73
................................................................................................. 77
Block Move Example ......................................................................................................
Subframe Extraction Example ...........................................................................................
Data Sorting Example .....................................................................................................
Peripheral Servicing Example ...........................................................................................
3.4.1 Nonbursting Peripherals .........................................................................................
3.4.2 Bursting Peripherals ..............................................................................................
3.4.3 Continuous Operation ............................................................................................
3.4.4 Ping-Pong Buffering ..............................................................................................
3.4.5 Transfer Chaining Examples ....................................................................................
Registers
4.1
4.2
A
2.10.1 Active Memory Protection ......................................................................................
2.10.2 Proxy Memory Protection ......................................................................................
Event Queue(s) ............................................................................................................
2.11.1 DMA/QDMA Channel to Event Queue Mapping ............................................................
2.11.2 Queue RAM Debug Visibility ...................................................................................
2.11.3 Queue Resource Tracking .....................................................................................
2.11.4 Performance Considerations ...................................................................................
EDMA3 Transfer Controller (EDMA3TC) ...............................................................................
2.12.1 Architecture Details .............................................................................................
2.12.2 Memory Protection ..............................................................................................
2.12.3 Error Generation .................................................................................................
2.12.4 Debug Features .................................................................................................
2.12.5 EDMA3TC Configuration .......................................................................................
Event Dataflow .............................................................................................................
EDMA3 Prioritization ......................................................................................................
2.14.1 Channel Priority ..................................................................................................
2.14.2 Trigger Source Priority ..........................................................................................
2.14.3 Dequeue Priority .................................................................................................
2.14.4 System (Transfer Controller) Priority .........................................................................
Reset Considerations .....................................................................................................
Emulation Considerations ................................................................................................
78
80
82
84
84
86
88
91
96
.......................................................................................................................... 99
Register Memory Maps .................................................................................................
EDMA3 Channel Controller Control Registers .......................................................................
4.2.1 Global Registers ................................................................................................
4.2.2 Error Registers ..................................................................................................
4.2.3 Region Access Enable Registers .............................................................................
4.2.4 Status/Debug Visibility Registers .............................................................................
4.2.5 Memory Protection Address Space ...........................................................................
4.2.6 DMA Channel Registers .......................................................................................
4.2.7 Interrupt Registers ..............................................................................................
4.2.8 QDMA Registers ................................................................................................
EDMA3 Transfer Controller Control Registers .......................................................................
4.3.1 Peripheral Identification Register (PID) ......................................................................
4.3.2 EDMA3TC Configuration Register (TCCFG) ................................................................
4.3.3 EDMA3TC Channel Status Register (TCSTAT) ............................................................
4.3.4 Error Registers ..................................................................................................
4.3.5 Read Rate Register (RDRATE) ...............................................................................
4.3.6 EDMA3TC Channel Registers .................................................................................
100
100
103
112
121
123
129
133
145
151
158
159
160
161
163
168
169
................................................................................................................................ 183
Debug Checklist .......................................................................................................... 183
Miscellaneous Programming/Debug Tips ............................................................................. 184
Contents
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B
C
....................................................................................................... 185
Revision History .............................................................................................................. 187
Setting Up a Transfer
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List of Figures
2-1.
EDMA3 Controller Block Diagram for TCI6482/86/C6472 Devices ................................................. 20
2-2.
EDMA3 Controller Block Diagram for TCI6487/88 Devices
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
2-15.
2-16.
2-17.
2-18.
2-19.
2-20.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
6
......................................................... 20
EDMA3 Channel Controller (EDMA3CC) Block Diagram for TCI6482/86/C6472 Devices ...................... 22
EDMA3 Channel Controller (EDMA3CC) Block Diagram for TCI6487/88 Devices ............................... 23
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................ 25
Definition of ACNT, BCNT, and CCNT ................................................................................ 26
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................... 27
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................... 28
PaRAM Set ................................................................................................................. 30
Channel Options Parameter (OPT) ..................................................................................... 32
Linked Transfer ............................................................................................................ 39
Link-to-Self Transfer ...................................................................................................... 40
DMA/QDMA Channel to PaRAM Mapping ............................................................................. 48
Shadow Region Registers ................................................................................................ 50
Interrupt Diagram .......................................................................................................... 56
Error Interrupt Operation ................................................................................................. 59
PaRAM Set Content for Proxied Memory Protection Example ...................................................... 64
Proxied Memory Protection Example ................................................................................... 65
EDMA3 Prioritization for TCI6482/86/C6472 Devices ................................................................ 74
EDMA3 Prioritization for TCI6487/88 Devices ......................................................................... 75
Block Move Example ...................................................................................................... 78
Block Move Example PaRAM Configuration ........................................................................... 79
Subframe Extraction Example ........................................................................................... 80
Subframe Extraction Example PaRAM Configuration ................................................................ 81
Data Sorting Example ..................................................................................................... 82
Data Sorting Example PaRAM Configuration .......................................................................... 83
Servicing Incoming McBSP Data Example ............................................................................ 84
Servicing Incoming McBSP Data Example PaRAM Configuration.................................................. 85
Servicing Peripheral Burst Example .................................................................................... 86
Servicing Peripheral Burst Example PaRAM Configuration ......................................................... 87
Servicing Continuous McBSP Data Example .......................................................................... 88
Servicing Continuous McBSP Data Example PaRAM Configuration ............................................... 89
Servicing Continuous McBSP Data Example Reload PaRAM Configuration ..................................... 89
Ping-Pong Buffering for McBSP Data Example ...................................................................... 92
Ping-Pong Buffering for McBSP Example PaRAM Configuration ................................................... 93
Ping-Pong Buffering for McBSP Example Pong PaRAM Configuration ............................................ 93
Ping-Pong Buffering for McBSP Example Ping PaRAM Configuration............................................. 95
Intermediate Transfer Completion Chaining Example ................................................................ 97
Single Large Block Transfer Example .................................................................................. 98
Smaller Packet Data Transfers Example ............................................................................... 98
Peripheral ID Register (PID) ............................................................................................ 103
EDMA3CC Configuration Register (CCCFG) ........................................................................ 104
DMA Channel Map n Registers (DCHMAPn) ........................................................................ 106
QDMA Channel Map n Registers (QCHMAPn) ...................................................................... 107
DMA Channel Queue n Number Registers (DMAQNUMn) ........................................................ 108
QDMA Channel Queue Number Register (QDMAQNUM) for TCI6482/86/C6472 Devices ................... 109
QDMA Channel Queue Number Register (QDMAQNUM) for TCI6487/88 Devices ............................ 109
List of Figures
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4-8.
Queue-to-TC Mapping Register (QUETCMAP) for TCI6482/86/C6472 Devices ................................ 110
4-9.
Queue-to-TC Mapping Register (QUETCMAP) for TCI6487/88 Devices......................................... 110
4-10.
Queue Priority Register (QUEPRI) for TCI6482/86/C6472 Devices
4-11.
Queue Priority Register (QUEPRI) for TCI6487/88 Devices ....................................................... 111
4-12.
Event Missed Register (EMR) .......................................................................................... 112
4-13.
Event Missed Register High (EMRH)
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
4-39.
4-40.
4-41.
4-42.
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
..............................................
.................................................................................
Event Missed Clear Register (EMCR).................................................................................
Event Missed Clear Register High (EMCRH) ........................................................................
QDMA Event Missed Register (QEMR) for TCI6482/86/C6472 Devices .........................................
QDMA Event Missed Register (QEMR) for TCI6487/88 Devices .................................................
QDMA Event Missed Clear Register (QEMCR) for TCI6482/86/C6472 Devices................................
QDMA Event Missed Clear Register (QEMCR) for TCI6487/88 Devices ........................................
EDMA3CC Error Register (CCERR) for TCI6482/86/C6472 Devices ............................................
EDMA3CC Error Register (CCERR) for TCI6487/88 Devices .....................................................
EDMA3CC Error Clear Register (CCERRCLR) for TCI6482/86/C6472 Devices ................................
EDMA3CC Error Clear Register (CCERRCLR) for TCI6487/88 Devices ........................................
Error Evaluation Register (EEVAL) ....................................................................................
DMA Region Access Enable Register for Region m (DRAEm) ....................................................
DMA Region Access Enable High Register for Region m (DRAEHm)............................................
QDMA Region Access Enable for Region m (QRAEm) for TCI6482/86/C6472 Devices ......................
QDMA Region Access Enable for Region m (QRAEm) for TCI6487/88 Devices ...............................
Event Queue Entry Registers (QxEy) .................................................................................
Queue Status Register n (QSTATn) ...................................................................................
Queue Watermark Threshold A Register (QWMTHRA) ............................................................
Queue Watermark Threshold B Register (QWMTHRB) for TCI6487/88 Devices ...............................
EDMA3CC Status Register (CCSTAT) for TCI6482/86/C6472 Devices ..........................................
EDMA3CC Status Register (CCSTAT) for TCI6487/88 Devices ..................................................
Memory Protection Fault Address Register (MPFAR) ..............................................................
Memory Protection Fault Status Register (MPFSR) .................................................................
Memory Protection Fault Command Register (MPFCR) ............................................................
Memory Protection Page Attribute Register (MPPAG/MPPAn) ....................................................
Event Register (ER) .....................................................................................................
Event Register High (ERH) .............................................................................................
Event Clear Register (ECR) ............................................................................................
Event Clear Register High (ECRH) ....................................................................................
Event Set Register (ESR) ...............................................................................................
Event Set Register High (ESRH) ......................................................................................
Chained Event Register (CER).........................................................................................
Chained Event Register High (CERH) ................................................................................
Event Enable Register (EER) ..........................................................................................
Event Enable Register High (EERH) ..................................................................................
Event Enable Clear Register (EECR) .................................................................................
Event Enable Clear Register High (EECRH) .........................................................................
Event Enable Set Register (EESR) ....................................................................................
Event Enable Set Register High (EESRH) ...........................................................................
Secondary Event Register (SER) ......................................................................................
Secondary Event Register High (SERH)..............................................................................
Secondary Event Clear Register (SECR) .............................................................................
Secondary Event Clear Register High (SECRH) ....................................................................
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List of Figures
111
112
113
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4-57.
Interrupt Enable Register (IER) ........................................................................................ 145
4-58.
Interrupt Enable Register High (IERH) ................................................................................ 145
4-59.
Interrupt Enable Clear Register (IECR) ............................................................................... 146
4-60.
Interrupt Enable Clear Register High (IECRH) ....................................................................... 146
4-61.
Interrupt Enable Set Register (IESR).................................................................................. 147
4-62.
Interrupt Enable Set Register High (IESRH) ......................................................................... 147
4-63.
Interrupt Pending Register (IPR) ....................................................................................... 148
4-64.
Interrupt Pending Register High (IPRH)
4-65.
Interrupt Clear Register (ICR) .......................................................................................... 149
4-66.
Interrupt Clear Register High (ICRH) .................................................................................. 149
4-67.
Interrupt Evaluate Register (IEVAL) ................................................................................... 150
4-68.
QDMA Event Register (QER) for TCI6482/86/C6472 Devices
4-69.
QDMA Event Register (QER) for TCI6487/88 Devices ............................................................. 151
4-70.
QDMA Event Enable Register (QEER) for TCI6482/86/C6472 Devices
4-71.
4-72.
4-73.
4-74.
4-75.
4-76.
4-77.
4-78.
4-79.
4-80.
4-81.
4-82.
4-83.
4-84.
4-85.
4-86.
4-87.
4-88.
4-89.
4-90.
4-91.
4-92.
4-93.
4-94.
4-95.
4-96.
4-97.
4-98.
4-99.
4-100.
4-101.
4-102.
4-103.
4-104.
4-105.
8
..............................................................................
....................................................
.........................................
QDMA Event Enable Register (QEER) for TCI6487/88 Devices ..................................................
QDMA Event Enable Clear Register (QEECR) for TCI6482/86/C6472 Devices ................................
QDMA Event Enable Clear Register (QEECR) for TCI6487/88 Devices .........................................
QDMA Event Enable Set Register (QEESR) for TCI6482/86/C6472 Devices ...................................
QDMA Event Enable Set Register (QEESR) for TCI6487/88 Devices ...........................................
QDMA Secondary Event Register (QSER) for TCI6482/86/C6472 Devices .....................................
QDMA Secondary Event Register (QSER) for TCI6487/88 Devices..............................................
QDMA Secondary Event Clear Register (QSECR) for TCI6482/86/C6472 Devices ............................
QDMA Secondary Event Clear Register (QSECR) for TCI6487/88 Devices ....................................
Peripheral ID Register (PID) ............................................................................................
EDMA3TC Configuration Register (TCCFG) .........................................................................
EDMA3TC Channel Status Register (TCSTAT) .....................................................................
Error Register (ERRSTAT) .............................................................................................
Error Enable Register (ERREN) .......................................................................................
Error Clear Register (ERRCLR) ........................................................................................
Error Details Register (ERRDET) ......................................................................................
Error Interrupt Command Register (ERRCMD) ......................................................................
Read Rate Register (RDRATE) ........................................................................................
Source Active Options Register (SAOPT) ............................................................................
Source Active Source Address Register (SASRC) ..................................................................
Source Active Count Register (SACNT) ..............................................................................
Source Active Destination Address Register (SADST) .............................................................
Source Active Source B-Dimension Index Register (SABIDX) ....................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) .................................................
Source Active Count Reload Register (SACNTRLD) ...............................................................
Source Active Source Address B-Reference Register (SASRCBREF) ...........................................
Source Active Destination Address B-Reference Register (SADSTBREF) ......................................
Destination FIFO Options Register (DFOPTn) .......................................................................
Destination FIFO Source Address Register (DFSRCn) .............................................................
Destination FIFO Count Register (DFCNTn) .........................................................................
Destination FIFO Destination Address Register (DFDSTn) ........................................................
Destination FIFO B-Index Register (DFBIDXn) ......................................................................
Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) ............................................
Destination FIFO Count Reload Register (DFCNTRLDn) ..........................................................
Destination FIFO Source Address B-Reference Register (DFSRCBREFn)......................................
List of Figures
148
151
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181
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4-106. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) ................................. 181
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List of Figures
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List of Tables
2-1.
EDMA3 Parameter RAM Contents ...................................................................................... 29
2-2.
EDMA3 Channel Parameter Description ............................................................................... 31
2-3.
Channel Options Parameters (OPT) Field Descriptions .............................................................. 32
2-4.
Dummy and Null Transfer Request ..................................................................................... 36
2-5.
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ...................................... 37
2-6.
EDMA3 Channel Synchronization Events .............................................................................. 43
2-7.
Expected Number of Transfers for Non-Null Transfer ................................................................ 46
2-8.
Shadow Region Registers ................................................................................................ 50
2-9.
Chain Event Triggers
2-10.
EDMA3 Transfer Completion Interrupts for TCI6482/86/C6472 Devices .......................................... 53
2-11.
EDMA3 Transfer Completion Interrupts for TCI6487/88 Devices ................................................... 53
2-12.
EDMA3 Error Interrupts for TCI6482/86/C6472 Devices ............................................................. 53
2-13.
EDMA3 Error Interrupts for TCI6487/88 Devices
2-14.
Number of Interrupts ...................................................................................................... 54
2-15.
Allowed Accesses ......................................................................................................... 60
2-16.
MPPA Registers to Region Assignment ................................................................................ 61
2-17.
Example Access Denied .................................................................................................. 61
2-18.
Example Access Allowed ................................................................................................. 62
2-19.
Read/Write Command Optimization Rules ............................................................................. 68
2-20.
EDMA3 Transfer Controller Configurations for TCI6482/86/C6472 Devices ...................................... 70
2-21.
EDMA3 Transfer Controller Configurations for TCI6487/88 Devices ............................................... 70
4-1.
EDMA3CC Registers .................................................................................................... 100
4-2.
Peripheral ID Register (PID) Field Descriptions
4-3.
EDMA3CC Configuration Register (CCCFG) Field Descriptions .................................................. 104
4-4.
DMA Channel Map n Registers (DCHMAPn) Field Descriptions .................................................. 106
4-5.
QDMA Channel Map n Registers (QCHMAPn) Field Descriptions ................................................ 107
4-6.
DMA Channel Queue n Number Registers (DMAQNUMn) Field Descriptions .................................. 108
4-7.
Bits in DMAQNUMn
4-8.
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ................................... 109
4-9.
Queue-to-TC Mapping Register (QUETCMAP) Field Descriptions................................................ 110
4-10.
Queue Priority Register (QUEPRI) Field Descriptions .............................................................. 111
4-11.
Event Missed Register (EMR) Field Descriptions
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
10
.....................................................................................................
.....................................................................
.....................................................................
.....................................................................................................
...................................................................
Event Missed Register High (EMRH) Field Descriptions ...........................................................
Event Missed Clear Register (EMCR) Field Descriptions ..........................................................
Event Missed Clear Register High (EMCRH) Field Descriptions ..................................................
QDMA Event Missed Register (QEMR) Field Descriptions ........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ...............................................
EDMA3CC Error Register (CCERR) Field Descriptions ............................................................
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ...............................................
Error Evaluation Register (EEVAL) Field Descriptions ..............................................................
DMA Region Access Enable Registers for Region M (DRAEm/DRAEHm) Field Descriptions ................
QDMA Region Access Enable for Region M (QRAEm) Field Descriptions ......................................
Event Queue Entry Registers (QxEy) Field Descriptions ...........................................................
Queue Status Register n (QSTATn) Field Descriptions ............................................................
Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ......................................
Queue Watermark Threshold B Register (QWMTHRB) Field Descriptions for TCI6487/88 Devices .........
EDMA3CC Status Register (CCSTAT) Field Descriptions .........................................................
List of Tables
52
54
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108
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4-27.
Memory Protection Fault Address Register (MPFAR) Field Descriptions ........................................ 129
4-28.
Memory Protection Fault Status Register (MPFSR) Field Descriptions .......................................... 130
4-29.
Memory Protection Fault Command Register (MPFCR) Field Descriptions
131
4-30.
Memory Protection Page Attribute Register (MPPAG/MPPAn) Field Descriptions
132
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
4-39.
4-40.
4-41.
4-42.
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
4-59.
4-60.
4-61.
4-62.
4-63.
4-64.
4-65.
4-66.
4-67.
4-68.
4-69.
4-70.
4-71.
4-72.
4-73.
4-74.
4-75.
.....................................
.............................
Event Register (ER) Field Descriptions ...............................................................................
Event Register High (ERH) Field Descriptions .......................................................................
Event Clear Register (ECR) Field Descriptions ......................................................................
Event Clear Register High (ECRH) Field Descriptions..............................................................
Event Set Register (ESR) Field Descriptions ........................................................................
Event Set Register High (ESRH) Field Descriptions ................................................................
Chained Event Register (CER) Field Descriptions ..................................................................
Chained Event Register High (CERH) Field Descriptions ..........................................................
Event Enable Register (EER) Field Descriptions ....................................................................
Event Enable Register High (EERH) Field Descriptions ............................................................
Event Enable Clear Register (EECR) Field Descriptions ...........................................................
Event Enable Clear Register High (EECRH) Field Descriptions...................................................
Event Enable Set Register (EESR) Field Descriptions .............................................................
Event Enable Set Register High (EESRH) Field Descriptions .....................................................
Secondary Event Register (SER) Field Descriptions................................................................
Secondary Event Register High (SERH) Field Descriptions .......................................................
Secondary Event Clear Register (SECR) Field Descriptions ......................................................
Secondary Event Clear Register High (SECRH) Field Descriptions ..............................................
Interrupt Enable Register (IER) Field Descriptions ..................................................................
Interrupt Enable Register High (IERH) Field Descriptions ..........................................................
Interrupt Enable Clear Register (IECR) Field Descriptions .........................................................
Interrupt Enable Clear Register High (IECRH) Field Descriptions ................................................
Interrupt Enable Set Register (IESR) Field Descriptions ...........................................................
Interrupt Enable Set Register High (IESRH) Field Descriptions ...................................................
Interrupt Pending Register (IPR) Field Descriptions ................................................................
Interrupt Pending Register High (IPRH) Field Descriptions ........................................................
Interrupt Clear Register (ICR) Field Descriptions ....................................................................
Interrupt Clear Register High (ICRH) Field Descriptions ...........................................................
Interrupt Evaluate Register (IEVAL) Field Descriptions .............................................................
QDMA Event Register (QER) Field Descriptions ....................................................................
QDMA Event Enable Register (QEER) Field Descriptions .........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions ................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ..................................................
QDMA Secondary Event Register (QSER) Field Descriptions.....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ...........................................
EDMA3 Transfer Controller Registers .................................................................................
Peripheral ID Register (PID) Field Descriptions .....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ...............................................
Error Register (ERRSTAT) Field Descriptions .......................................................................
Error Enable Register (ERREN) Field Descriptions .................................................................
Error Clear Register (ERRCLR) Field Descriptions .................................................................
Error Details Register (ERRDET) Field Descriptions................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions ................................................
Read Rate Register (RDRATE) Field Descriptions ..................................................................
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List of Tables
134
134
135
135
136
137
138
139
140
140
141
141
142
142
143
143
144
144
145
145
146
146
147
147
148
148
149
149
150
151
153
154
155
156
157
158
159
160
161
163
164
165
166
167
168
11
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4-76.
Source Active Options Register (SAOPT) Field Descriptions ...................................................... 169
4-77.
Source Active Source Address Register (SASRC) Field Descriptions ............................................ 171
4-78.
Source Active Count Register (SACNT) Field Descriptions ........................................................ 171
4-79.
Source Active Destination Address Register (SADST) Field Descriptions ....................................... 172
4-80.
Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions .............................. 172
4-81.
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ........................... 173
4-82.
Source Active Count Reload Register (SACNTRLD) Field Descriptions ......................................... 174
4-83.
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
4-84.
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ................ 175
4-85.
................................................
......................................
Destination FIFO Count Register (DFCNTn) Field Descriptions ...................................................
Destination FIFO Destination Address Register (DFDSTn) Field Descriptions ..................................
Destination FIFO B-Index Register (DFBIDXn) Field Descriptions ................................................
Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field Descriptions......................
Destination FIFO Count Reload Register (DFCNTRLDn) Field Descriptions ....................................
Destination FIFO Source Address B-Reference Register (DFSRCBREFn) Field Descriptions ...............
Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) Field Descriptions ...........
Debug List.................................................................................................................
EDMA3 Revision History ................................................................................................
4-86.
4-87.
4-88.
4-89.
4-90.
4-91.
4-92.
4-93.
A-1.
C-1.
12
....................
174
Destination FIFO Options Register (DFOPTn) Field Descriptions
177
Destination FIFO Source Address Register (DFSRCn) Field Descriptions
178
List of Tables
178
179
179
180
180
181
181
183
187
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Preface
SPRU727E – December 2005 – Revised July 2011
Read This First
About This Manual
This document describes the features and operations of the enhanced direct memory access (EDMA3)
controller in the TMS320C6472/TMS320TCI648x digital signal processor (DSP). The EDMA3 is a
high-performance, multichannel, multithreaded DMA controller that allows you to program a wide variety of
transfer geometries and transfer sequences.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet. Tip: Enter the literature number in the search box provided at
www.ti.com.
SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors
(DSPs).
SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you
to program custom plug-ins for Code Composer.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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13
14
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Chapter 1
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Introduction
This chapter provides an overview of features and terminology.
Topic
1.1
1.2
1.3
...........................................................................................................................
Page
Overview .......................................................................................................... 16
Features ........................................................................................................... 16
Terminology Used in This Document ................................................................... 17
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Overview
1.1
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Overview
The enhanced direct memory access (EDMA3) controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.
Typical usage includes, but is not limited to the following:
• Servicing software-driven paging transfers (e.g., transfers from external memory, such as SDRAM to
internal device memory, such as DSP L2 SRAM)
• Servicing event-driven peripherals, such as a serial port and UTOPIA
• Performing sorting or sub-frame extraction of various data structures
• Offloading data transfers from the main device CPU(s)
• See the device-specific data manual for specific peripherals that are accessible via the EDMA3
controller
The EDMA3 controller has a different architecture from the previous EDMA2 controller on the
TMS320C64x DSPs. [For more information on new/advanced features, see the EDMA v3.0 (EDMA3)
Migration Guide for TMS320TCI648x DSP (SPRAAC1).]
The EDMA3 controller consists of two principle blocks:
• EDMA3 channel controller (EDMA3CC)
• EDMA3 transfer controller(s) (EDMA3TC)
The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CC
includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The
EDMA3CC serves to prioritize incoming software requests or events from peripherals and submits transfer
requests (TRs) to the transfer controller.
The EDMA3 transfer controllers are responsible for data movement and issue read/write commands to the
source and destination addresses that are programmed for a given transfer in the EDMA3CC. The
operation is transparent to you.
1.2
Features
The EDMA3 channel controller has following features:
• Fully orthogonal transfer description
– Three transfer dimensions
– A-synchronized transfers: one-dimension serviced per event
– AB-synchronized transfers: two-dimensions serviced per event
– Independent indexes on source and destination
– Chaining feature allows a 3-D transfer based on a single event
• Flexible transfer definition
– Increment or constant addressing modes
– Linking mechanism allows automatic PaRAM set update
– Chaining allows multiple transfers to execute with one event
• Interrupt generation for the following:
– Transfer completion
– Error conditions
• Debug visibility
– Queue water marking/threshold
– Error and status recording to facilitate debug
• 64 DMA channels
– Event synchronization
– Manual synchronization (CPU(s) write to event set register)
– Chain synchronization (completion of one transfer triggers another transfer)
• Four QDMA channels for the TCI6482/86/C6472 devices
Eight QDMA channels for the TCI6487/88 devices
16
Introduction
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Terminology Used in This Document
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•
•
•
•
– QDMA channels trigger automatically when you write to a PaRAM set entry
– Support for programmable DMA channel and QDMA channel to PaRAM mapping
256 PaRAM sets
– Each PaRAM set can be used for a DMA channel, QDMA channel, or link set
Four transfer controllers/event queues for the TCI6482/86/C6472 devices
Six transfer controllers/event queues for the TCI6487/88 devices. The system-level priority of these
queues is user programmable. (For the possible system priorities, see the device-specific data manual)
16 event entries per event queue
Memory protection support
– Proxied memory protection for TR submission
– Active memory protection for accesses to PaRAM and registers
The EDMA3 transfer controller has the following features:
• Four transfer controllers (TC) for the TCI6482/86/C6472 devices
Six transfer controllers (TC) for the TCI6487/88 devices
• 128-bit wide read and write ports per TC for the TCI6482/86/C6472 devices
• Three transfer controllers with 128-bit wide read-write ports for the TCI6487/88 devices
• Three transfer controllers with 64-bit wide read-write ports for the TCI6487/88 devices
• Up to four in-flight transfer requests (TRs)
• Programmable priority level
• Supports two-dimensional transfers with independent indexes on source and destination (EDMA3CC
manages the 3rd dimension)
• Support for increment or constant addressing mode transfers
• Interrupt and error support
• Little-endian or big-endian operation
• Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR regardless of endianness
1.3
Terminology Used in This Document
The following is a brief explanation of some terms that are used in this document:
Term
A-synchronized transfer
AB-synchronized
transfer
Chaining
Meaning
A transfer type where one dimension is serviced per synchronization event.
A transfer type where two dimensions are serviced per synchronization event.
A trigger mechanism in which a transfer can be initiated at the completion of another transfer or
sub-transfer.
CPU(s)
The main processing engine or engines on a device. The CPU is typically a DSP or general-purpose
processor(see the device-specific data manual to learn more about the CPU on your system.)
Device
Digital signal processor (DSP)
DMA channel
One of the 64 channels that external, manual, or chained events can trigger. All DMA channels exist in
the EDMA3CC.
Dummy set or dummy
A PaRAM set for which at least one of the count fields is equal to 0 and at least one of the count fields is
PaRAM set
nonzero. All of the count fields are cleared in a null PaRAM set.
Dummy transfer
A dummy set results in the EDMA3CC performing a dummy transfer. This is not an error condition. A
null set results in an error condition.
EDMA3 channel
The EDMA3CC is the portion of the EDMA3 that you program. The EDMA3CC contains the parameter
controller (EDMA3CC)
RAM (PaRAM), event processing logic, DMA/QDMA channels, and event queues. The EDMA3CC
service events (external, manual, chained, and QDMA) and is responsible for submitting transfer
requests to the transfer controllers (EDMA3TC) that perform the actual transfer.
EDMA3 programmer
Any entity on the chip that has read/write access to the EDMA3 registers and can program an EDMA3
transfer.
EDMA3 transfer
Transfer controllers are the transfer engines for the EDMA3 controller. They perform the read/writes, as
controller(s) (EDMA3TC) dictated by the EDMA3CC's transfer requests.
Enhanced direct
EDMA3 consists of the EDMA3 channel controller (EDMA3CC) and the EDMA3 transfer controller(s)
memory access
(EDMA3TC), referred to as EDMA3 in this document.
(EDMA3) controller
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Introduction
17
Terminology Used in This Document
Term
Link parameter set
Linking
Memory-mapped slave
Master peripherals
Null set or null PaRAM
set
Null transfer
Parameter RAM
(PaRAM)
Parameter RAM
(PaRAM) set
Parameter RAM
(PaRAM) set entry
QDMA channel
Slave end points
Transfer request (TR)
Trigger event
Trigger word
TR synchronization
(sync) event
18
Introduction
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Meaning
A PaRAM set that is used for linking.
The mechanism of reloading a PaRAM set with new transfer characteristics on completion of the current
transfer.
All on-chip memories, off-chip memories, and slave peripherals. These typically rely on the EDMA3 (or
other master peripheral) to perform transfers to and from them.
All peripherals that are capable of initiating read and write transfers to the system that may not solely
rely on the EDMA3 for their data transfers.
A PaRAM set that has all count fields cleared (except for the link field). A dummy PaRAM set has at
least one of the count fields nonzero.
A trigger event for a null PaRAM set results in the EDMA3CC performing a null transfer. This is an error
condition. A dummy transfer is not an error condition.
Programmable RAM that stores PaRAM sets that DMA channels, QDMA channels, and linking uses.
The PaRAM set is a 32-byte EDMA3 channel transfer definition. Each parameter set consists of eight
words (that are four bytes each) that store the context for a DMA/QDMA/link transfer. A PaRAM set
includes source address, destination address, counts, indexes, and options.
A PaRAM set entry occurs when one of the eight four-byte components of the parameter set.
A QDMA channel is one of the four (TCI6482/86/C6472) or eight (TCI6487/88) channels that you can
trigger when writing to the trigger word (TRWORD) of a PaRAM set. All QDMA channels exist in the
EDMA3CC.
Slave end points are all on-chip memories, off-chip memories, and slave peripherals. Slave end points
may rely on the EDMA3 to perform transfers to and from them.
A command for data movement that is issued from the EDMA3CC to the EDMA3TC. A TR includes
source and destination addresses, counts, indexes, and options.
A trigger event is an action that causes the EDMA3CC to service the channel and to submit a transfer
request to the EDMA3TC. Trigger events for the DMA channels include events that are triggered
manually, externally, and by chain. Trigger events for QDMA channels include events that are triggered
automatically and by link.
For QDMA channels, the trigger word specifies the PaRAM set entry that results in a QDMA trigger
event when it is written. The trigger word is programmed via the QDMA channel map register
(QCHMAP) and can point to any of the PaRAM set entries.
See Trigger event.
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Chapter 2
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EDMA3 Architecture
This chapter provides the architecture details and common operations of the EDMA3 channel controller
(EDMA3CC) and the EDMA3 transfer controller (EDMA3TC).
Topic
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
...........................................................................................................................
Functional Overview ..........................................................................................
Types of EDMA3 Transfers .................................................................................
Parameter RAM (PaRAM) ....................................................................................
Initiating a DMA Transfer ....................................................................................
Completion of a DMA Transfer ............................................................................
Event, Channel, and PaRAM Mapping ..................................................................
EDMA3 Channel Controller Regions ....................................................................
Chaining EDMA3 Channels .................................................................................
EDMA3 Interrupts ..............................................................................................
Memory Protection ............................................................................................
Event Queue(s) .................................................................................................
EDMA3 Transfer Controller (EDMA3TC) ...............................................................
Event Dataflow ..................................................................................................
EDMA3 Prioritization ..........................................................................................
Reset Considerations ........................................................................................
Emulation Considerations ..................................................................................
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EDMA3 Architecture
Page
20
26
29
42
46
47
49
52
53
60
65
67
72
72
73
73
19
Functional Overview
2.1
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Functional Overview
2.1.1 EDMA3 Controller Block Diagram
Figure 2-1 and Figure 2-2 show a block diagram for the EDMA3 controller.
Figure 2-1. EDMA3 Controller Block Diagram for TCI6482/86/C6472 Devices
Transfer
controllers
MMR
access
Channel controller
DMA/QDMA
channel
logic
To/from
EDMA3
programmer
Event
queues
PaRAM
Transfer
request
submission
TC0
Read/write
commands
and data
TC3
Read/write
commands
and data
EDMA3TC0_
ERRINT0
MMR
access
EDMA3CC_ERRINT
Completion
and error
interrupt
logic
EDMA3CC_INT[7:0]
EDMA3CC_MPINT
Completion
detection
EDMA3TC3_
ERRINT
EDMA3CC_GINT
Figure 2-2. EDMA3 Controller Block Diagram for TCI6487/88 Devices
Transfer
controllers
MMR
access
Channel controller
To/from
EDMA3
programmer
DMA/QDMA
channel
logic
Event
queues
PaRAM
Transfer
request
submission
TC0
Read/write
commands
and data
TC5
Read/write
commands
and data
EDMA3TC0_
ERRINT0
MMR
access
EDMA3CC_ERRINT
EDMA3CC_INT[7:0]
EDMA3CC_MPINT
Completion
and error
interrupt
logic
Completion
detection
EDMA3TC5_
ERRINT
EDMA3CC_GINT
20
EDMA3 Architecture
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2.1.2 EDMA3 Channel Controller (EDMA3CC)
Figure 2-3 shows a functional block diagram of the EDMA3 channel controller (EDMA3CC).
The main blocks of the EDMA3CC are as follows:
• Parameter RAM (PaRAM): The PaRAM maintains parameter sets for channel and reload parameter
sets. You must write the PaRAM with the transfer context for the desired channels and link parameter
sets. EDMA3CC processes sets based on a trigger event and submits a transfer request (TR) to the
transfer controller.
• EDMA3 event and interrupt processing registers: Allows mapping of events to parameter sets,
enable/disable events, enable/disable interrupt conditions, and clearing interrupts.
• Completion detection: The completion detect block detects completion of transfers by the EDMA3TC
and/or slave peripherals. You can optionally use completion of transfers to chain trigger new transfers
or to assert interrupts.
• Event queues: Event queues form the interface between the event detection logic and the transfer
request submission logic.
• Memory protection registers: Memory protection registers define the accesses (privilege level and
requestor(s)) that are allowed to access the DMA channel shadow region view(s) and regions of
PaRAM.
Other functions include the following:
• Region registers: Region registers allow DMA resources (DMA channels and interrupts) to be assigned
to unique regions that different EDMA3 programmers or different application threads can own.
• Debug registers: Debug registers allow debug visibility by providing registers to read the queue status,
controller status, and missed event status.
The EDMA3CC includes two channel types: DMA channels (64 channels) and QDMA channels (4
(TCI6482/86/C6472) or 8 (TCI6487/88) channels).
Each channel is associated with a given event queue/transfer controller and with a given PaRAM set. The
main thing that differentiates a DMA channel from a QDMA channel is the method that the system uses to
trigger transfers; see Section 2.4 and Figure 2-4.
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Figure 2-3. EDMA3 Channel Controller (EDMA3CC) Block Diagram for TCI6482/86/C6472 Devices
From peripherals/external events
E63
E1 E0
Event queues
15
0
Queue 2
Chained
event
register
(CER/CERH)
15
4
Parameter
set 254
Queue 3
Queue bypass
Completion
interface
To chained event register (CER/CERH)
EDMA3CC_
MPINT
22
Read/
write to/
from CPU
EDMA3 Architecture
To
TC(S)
Parameter
set 255
0
QDMA trigger
Memory
protection
T ransfer request process submit
64:1 priority encoder
Queue 1
Event
64
set
register
(ESR/ESRH)
64
QDMA
event
register
(QER)
0
15
Early completion
Chain
trigger
Parameter
set 1
Channel mapping
Manual
trigger
Event
64
enable
register
(EER/EERH)
Parameter
set 0
Queue 0
4:1 priority encoder
Event
trigger
Event
register
(ER/ERH)
PaRAM
0
15
Error
detection
EDMA3CC_
ERRINT
From
EDMA3TC0
Completion
detection
From
EDMA3TC3
Completion
interrupt
EDMA3
channel
controller
EDMA3CC_INT[7:0]
EDMA3CC_GINT
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Figure 2-4. EDMA3 Channel Controller (EDMA3CC) Block Diagram for TCI6487/88 Devices
From peripherals/external events
E63
E1 E0
Event queues
15
15
0
Parameter
set 254
Queue 3
15
Chained
event
register
(CER/CERH)
QDMA
event
register
(QER)
0
Queue 2
Event
64
set
register
(ESR/ESRH)
64
8
0
0
Queue 5
Queue bypass
Completion
interface
QDMA trigger
To chained event register (CER/CERH)
Memory
protection
EDMA3CC_
MPINT
Read/
write to/
from CPU
To
TC(S)
Parameter
set 255
Queue 4
15
T ransfer request process submit
64:1 priority encoder
Queue 1
Early completion
Chain
trigger
Parameter
set 1
0
15
Channel mapping
Manual
trigger
Event
64
enable
register
(EER/EERH)
Parameter
set 0
Queue 0
8:1 priority encoder
Event
trigger
Event
register
(ER/ERH)
PaRAM
0
15
Error
detection
EDMA3CC_
ERRINT
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From
EDMA3TC0
Completion
detection
From
EDMA3TC5
Completion
interrupt
EDMA3CC_INT[7:0]
EDMA3CC_GINT
EDMA3
channel
controller
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EDMA3 Architecture
23
Functional Overview
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A trigger event is necessary to initiate a transfer. A trigger event may be due to an external event, manual
write to the event set register, or chained event for DMA channels. QDMA channels auto-trigger when a
write to the trigger word that you program occurs on the associated PaRAM set. All such trigger events
are logged into appropriate registers upon recognition. See Section 4.2.1.3.
Once a trigger event is recognized, the appropriate EDMA3CC event queue ques the event / channel. The
assignment of each DMA/QDMA channel to an event queue is programmable. Each queue is 16 events
deep; therefore, you can queue up to 16 events (on a single queue) in the EDMA3CC at a time. Additional
pending events that are mapped to a full queue are queued when the event queue space becomes
available. See Section 2.11.
If events on different channels are detected simultaneously, the events are queued based on a fixed
priority arbitration scheme with the DMA channels being higher priority events than the QDMA channels.
Among the two groups of channels, the lowest-numbered channel is the highest priority.
Each event in the event queue is processed in FIFO order. When the head of the queue is reached, the
PaRAM associated with that channel is read to determine the transfer details. The TR submission logic
evaluates the validity of the TR and is responsible for submitting a valid transfer request (TR) to the
appropriate EDMA3TC (based on the event queue to the EDMA3TC association for TCI6482/86/C6472
devices, Q0 goes to TC0, Q1 goes to TC1, Q2 goes to TC2, and Q3 goes to TC3; for TCI6487/88
devices, Q0 goes to TC0, Q1 goes to TC1, Q2 goes to TC2, Q3 goes to TC3, Q4 goes to TC4, and Q5
goes to TC5). For more information, see Section 2.3.
The EDMA3TC receives the request and is responsible for data movement, as specified in the transfer
request packet (TRP), other necessary tasks like buffering, and ensuring transfers are carried out in an
optimal fashion wherever possible. For more information on EDMA3TC, see Section 2.1.3.
If you have decided to receive an interrupt or to chain to another channel on completion of the current
transfer, the EDMA3TC signals completion to the EDMA3CC completion detection logic when the transfer
is complete. You can alternately choose to trigger completion when a TR leaves the EDMA3CC boundary,
rather than wait for all of the data transfers to complete. Based on the setting of the EDMA3CC interrupt
registers, the completion interrupt generation logic is responsible for generating EDMA3CC completion
interrupts to the CPU. For more information, see Section 2.5.
Additionally, the EDMA3CC also has an error detection logic that causes an error interrupt generation on
various error conditions (like missed events, exceeding event queue thresholds, etc.). For more
information on error interrupts, see Section 2.9.4.
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2.1.3 EDMA3 Transfer Controller (EDMA3TC)
Figure 2-5 shows a functional block diagram of the EDMA3 transfer controller (EDMA3TC).
Figure 2-5. EDMA3 Transfer Controller (EDMA3TC) Block Diagram
To completion
detection logic
in EDMA3CC
EDMA3TCn_ERRINT
SRC
Write
controller
Transfer request
submission
Program
register set
SRC active
register set
Read
controller
EDMA3TCn
Destination FIFO
register set
Read
command
Read data
Write
command
Write data
The main blocks of the EDMA3TC are:
• DMA program register set: The DMA program register set stores the transfer requests received from
the EDMA3 channel controller (EDMA3CC).
• DMA source active register set: The DMA source active register set stores the context for the DMA
transfer request currently in progress in the read controller.
• Read controller: The read controller issues read commands to the source address.
• Destination FIFO register set: The destination (DST) FIFO register set stores the context for the DMA
transfer request(s) currently in progress in the write controller.
• Write controller: The write controller issues write commands/write data to the destination slave.
• Data FIFO: The data FIFO exists for holding temporary in-flight data.
• Completion interface: The completion interface sends completion codes to the EDMA3CC when a
transfer completes, and generates interrupts and chained events (also, see Section 2.1.2 for more
information on transfer completion reporting).
When the EDMA3TC is idle and receives its first TR, DMA program register set receives the TR, where it
transitions to the DMA source active set and the destination FIFO register set immediately. The second
TR (if pending from EDMA3CC) is loaded into the DMA program set, ensuring it can start as soon as
possible when the active transfer completes. As soon as the current active set is exhausted, the TR is
loaded from the DMA program register set into the DMA source active register set as well as to the
appropriate entry in the destination FIFO register set.
The read controller issues read commands governed by the rules of command fragmentation and
optimization. These are issued only when the data FIFO has space available for the data read. When
sufficient data is in the data FIFO, the write controller starts issuing a write command again following the
rules for command fragmentation and optimization. For more information on command fragmentation and
optimization, see Section 2.12.1.1.
Depending on the number of entries, the read controller can process up to two or four transfer requests
ahead of the destination subject to the amount of free data FIFO.
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Types of EDMA3 Transfers
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Types of EDMA3 Transfers
An EDMA3 transfer is always defined in terms of three dimensions. Figure 2-6 shows the three
dimensions used by EDMA3 transfers. These three dimensions are defined as:
• 1st Dimension or Array (A): The 1st dimension in a transfer consists of ACNT contiguous bytes.
• 2nd Dimension or Frame (B): The 2nd dimension in a transfer consists of BCNT arrays of ACNT bytes.
Each array transfer in the 2nd dimension is separated from each other by an index programmed using
SRCBIDX or DSTBIDX.
• 3rd Dimension or Block (C): The 3rd dimension in a transfer consists of CCNT frames of BCNT arrays
of ACNT bytes. Each transfer in the 3rd dimension is separated from the previous by an index
programmed using SRCCIDX or DSTCIDX.
Note that the reference point for the index depends on the synchronization type. The amount of data
transferred upon receipt of a trigger/synchronization event is controlled by the synchronization types
(SYNCDIM bit in OPT). Of the three dimensions, only two synchronization types are supported:
A-synchronized transfers and AB-synchronized transfers.
Figure 2-6. Definition of ACNT, BCNT, and CCNT
ACNT bytes in
Array/1st dimension
Frame 0
Array 1
Array 2
Array BCNT
Frame 1
Array 1
Array 2
Array BCNT
Frame CCNT
Array 1
Array 2
Array BCNT
CCNT frames in
Block/3rd dimmension
BCNT arrays in Frame/2nd dimmension
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2.2.1 A-Synchronized Transfers
In an A-synchronized transfer, each EDMA3 sync event initiates the transfer of the 1st dimension of ACNT
bytes, or one array of ACNT bytes. In other words, each event/TR packet conveys the transfer information
for one array only. Thus, BCNT × CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by SRCBIDX and DSTBIDX, as shown in Figure 2-7, where the start address
of Array N is equal to the start address of Array N – 1 plus source (SRC) or destination (DST) BIDX.
Frames are always separated by SRCCIDX and DSTCIDX. For A-synchronized transfers, after the frame
is exhausted, the address is updated by adding SRCCIDX/DSTCIDX to the beginning address of the last
array in the frame. As in Figure 2-7, SRCCIDX/DSTCIDX is the difference between the start of Frame 0
Array 3 to the start of Frame 1 Array 0.
Figure 2-7 shows an A-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes.
In this example, a total of 12 sync events (BCNT × CCNT) exhaust a PaRAM set. See Section 2.3.6 for
details on parameter set updates.
Figure 2-7. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
Frame 0
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Array 0
Array 1
Array 2
Each array submit
as one TR
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 1
Array 0
(SRC|DST)
(SRC|DST)
BIDX
BIDX
Array 1
Array 2
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 2
Array 0
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BIDX
Array 1
(SRC|DST)
BIDX
Array 2
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2.2.2 AB-Synchronized Transfers
In a AB-synchronized transfer, each EDMA3 sync event initiates the transfer of 2 dimensions or one
frame. In other words, each event/TR packet conveys information for one entire frame of BCNT arrays of
ACNT bytes. Thus, CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 2-8. Frames are always
separated by SRCCIDX and DSTCIDX.
Note that for AB-synchronized transfers, after a TR for the frame is submitted, the address update is to
add SRCCIDX/DSTCIDX to the beginning address of the beginning array in the frame. This is different
from A-synchronized transfers where the address is updated by adding SRCCIDX/DSTCIDX to the start
address of the last array in the frame. See Section 2.3.6 for details on parameter set updates.
Figure 2-8 shows an AB-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes.
In this example, a total of 3 sync events (CCNT) exhaust a PaRAM set; that is, a total of 3 transfers of
4 arrays each completes the transfer.
Figure 2-8. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
AB_Sync transfer
(SRC|DST)
BIDX
Frame 0
Array 0
(SRC|DST)
BIDX
(SRC|DST)
Each array submit
as one TR
BIDX
Array 1
Array 2
(SRC|DST)
(SRC|DST)
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 1
Array 0
BIDX
BIDX
Array 1
Array 2
(SRC|DST)
(SRC|DST)
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 2
Array 0
BIDX
Array 1
BIDX
Array 2
Array 3
NOTE: ABC-synchronized transfers are not directly supported. But can be logically achieved by
chaining between multiple AB-synchronized transfers.
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2.3
Parameter RAM (PaRAM)
The EDMA3 controller is a RAM-based architecture. The transfer context (source/destination addresses,
count, indexes, etc.) for DMA or QDMA channels is programmed in a parameter RAM table within
EDMA3CC, referred to as PaRAM. The PaRAM table is segmented into multiple PaRAM sets. Each
PaRAM set includes eight 4-byte PaRAM set entries (32 bytes total per PaRAM set), which includes
typical DMA transfer parameters such as source address, destination address, transfer counts, indexes,
options, etc.
The PaRAM structure supports flexible ping-pong, circular buffering, channel chaining, and auto-reloading
(linking).
The contents of the PaRAM include the following:
• 256 PaRAM sets
• Any PaRAM entry can be used for DMA, QDMA, or link sets
• By default, all channels map to PaRAM set 0. These should be re-mapped before use. See
Section 4.2.1.3 (DCHMAP registers) and Section 4.2.1.4 (QCHMAP registers) for more information.
Table 2-1. EDMA3 Parameter RAM Contents
(1)
PaRAM Set Number
Address
Parameters
0
02A0 4000h to 02A0 401Fh
PaRAM set 0
1
02A0 4020h to 02A0 403Fh
PaRAM set 1
2
02A0 4040h to 02A0 405Fh
PaRAM set 2
3
02A0 4060h to 02A0 407Fh
PaRAM set 3
4
02A0 4080h to 02A0 409Fh
PaRAM set 4
5
02A0 40A0h to 02A0 40BFh
PaRAM set 5
6
02A0 40C0h to 02A0 40DFh
PaRAM set 6
7
02A0 40E0h to 02A0 40FFh
PaRAM set 7
8
02A0 4100h to 02A0 411Fh
PaRAM set 8
9
02A0 4120h to 02A0 413Fh
PaRAM set 9
...
...
...
63
02A0 47E0h to 02A0 47FFh
PaRAM set 63
64
02A0 4800h to 02A0 481Fh
PaRAM set 64
65
02A0 4820h to 02A0 483Fh
PaRAM set 65
...
...
...
254
02A0 5FC0h to 02A0 5FDFh
PaRAM set 254
255
02A0 5FE0h to 02A0 5FFFh
PaRAM set 255
(1)
A PaRAM set can be configured for use with either DMA channel, QDMA channel, or as a reload link
set.
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2.3.1 PaRAM
Each parameter set of PaRAM is organized into eight 32-bit words or 32 bytes, as shown in Figure 2-9
and described in Table 2-2. Each PaRAM set consists of 16-bit and 32-bit parameters.
Figure 2-9. PaRAM Set
Byte
address
Set
#
PaRAM
PaRAM set
02A0 4000h 0
Parameter set 0
OPT
02A0 4020h 1
Parameter set 1
02A0 4040h 2
Parameter set 2
02A0 4060h 3
Parameter set 3
30
Parameter set 254
02A0 5FE0 255
Parameter set 255
EDMA3 Architecture
+0h
+4h
SRC
ACNT
+8h
SRCBIDX
+10h
BCNTRLD
LINK
+14h
DSTCIDX
SRCCIDX
+18h
Rsvd
CCNT
+1Ch
BCNT
+Ch
DST
DSTBIDX
02A0 5FC0 254
Byte address
offset
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Table 2-2. EDMA3 Channel Parameter Description
Offset Address
(bytes)
Acronym
Parameter
Description
0h
OPT
Channel Options
Transfer configuration options
4h
SRC
Channel Source Address
The byte address from which data is transferred
ACNT
Count for 1st Dimension
Unsigned value specifying the number of contiguous
bytes within an array (first dimension of the transfer).
Valid values range from 1 to 65 535.
BCNT
Count for 2nd Dimension
Unsigned value specifying the number of arrays in a
frame, where an array is ACNT bytes. Valid values
range from 1 to 65 535.
DST
Channel Destination Address
The byte address to which data is transferred
SRCBIDX
Source BCNT Index
Signed value specifying the byte address offset between
source arrays within a frame (2nd dimension). Valid
values range from –32 768 and 32 767.
DSTBIDX
Destination BCNT Index
Signed value specifying the byte address offset between
destination arrays within a frame (2nd dimension). Valid
values range from –32 768 and 32 767.
LINK
Link Address
The PaRAM address containing the PaRAM set to be
linked (copied from) when the current PaRAM set is
exhausted. A value of FFFFh specifies a null link.
BCNTRLD
BCNT Reload
The count value used to reload BCNT when BCNT
decrements to 0 (TR is submitted for the last array in
2nd dimension). Only relevant in A-synchronized
transfers.
SRCCIDX
Source CCNT Index
Signed value specifying the byte address offset between
frames within a block (3rd dimension). Valid values
range from –32 768 and 32 767.
8h
(1)
Ch
10h (1)
14h (1)
18h (1)
A-synchronized transfers: The byte address offset from
the beginning of the last source array in a frame to the
beginning of the first source array in the next frame.
AB-synchronized transfers: The byte address offset from
the beginning of the first source array in a frame to the
beginning of the first source array in the next frame.
DSTCIDX
Destination CCNT index
Signed value specifying the byte address offset between
frames within a block (3rd dimension). Valid values
range from –32 768 and 32 767.
A-synchronized transfers: The byte address offset from
the beginning of the last destination array in a frame to
the beginning of the first destination array in the next
frame.
AB-synchronized transfers: The byte address offset from
the beginning of the first destination array in a frame to
the beginning of the first destination array in the next
frame.
1Ch
(1)
CCNT
Count for 3rd Dimension
Unsigned value specifying the number of frames in a
block, where a frame is BCNT arrays of ACNT bytes.
Valid values range from 1 to 65 535.
RSVD
Reserved
Reserved
It is recommended to access the parameter set sets as 32-bit words whenever possible.
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2.3.2 EDMA3 Channel PaRAM Set Entry Fields
2.3.2.1
Channel Options Parameter (OPT)
The channel options parameter (OPT) is shown in Figure 2-10 and described in Table 2-3.
Figure 2-10. Channel Options Parameter (OPT)
31
30
28
23
22
21
20
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 2-3. Channel Options Parameters (OPT) Field Descriptions
Bit
Field
31
PRIV
30-28
Reserved
27-24
PRIVID
23
Value
Description
Privilege level (supervisor versus user) for the host/CPU/DMA that programmed this PaRAM set. This
value is set with the EDMA3 master’s privilege value when any part of the PaRAM set is written.
0
User level privilege
1
Supervisor level privilege
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0-Fh
Privilege identification for the external host/CPU/DMA that programmed this PaRAM set. This value is
set with the EDMA3 master’s privilege identification value when any part of the PaRAM set is written.
ITCCHEN
Intermediate transfer completion chaining enable.
0
Intermediate transfer complete chaining is disabled
1
Intermediate transfer complete chaining is enabled
When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer
completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the
PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.
22
TCCHEN
Transfer complete chaining enable.
0
Transfer complete chaining is disabled
1
Transfer complete chaining is enabled
When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion
(upon completion of the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC
value specified.
21
ITCINTEN
Intermediate transfer completion interrupt enable.
0
Intermediate transfer complete interrupt is disabled
1
Intermediate transfer complete interrupt is enabled
When enabled, the interrupt pending register (IPR / IPRH) bit is set on every intermediate transfer
completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the
PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. To generate a completion
interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set.
20
TCINTEN
Transfer complete interrupt enable.
0
Transfer complete interrupt is disabled
1
Transfer complete interrupt is enabled
When enabled, the interrupt pending register (IPR / IPRH) bit is set on transfer completion (upon
completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value
specified. To generate a completion interrupt to the CPU, the corresponding IER[TCC] / IERH [TCC] bit
must be set.
19-18
Reserved
17-12
TCC
32
0
0-3Fh
EDMA3 Architecture
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
Transfer complete code. This 6-bit code sets the relevant bit in the chaining enable register (CER [TCC]
/CERH [TCC]) for chaining or in the interrupt pending register (IPR [TCC] / IPRH [TCC]) for interrupts.
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Table 2-3. Channel Options Parameters (OPT) Field Descriptions (continued)
Bit
Field
11
TCCMODE
10-8
FWID
Value
Transfer complete code mode. Indicates the point at which a transfer is considered completed for
chaining and interrupt generation.
0
Normal completion: A transfer is considered completed after the data has been transferred.
1
Early completion: A transfer is considered completed after the EDMA3CC submits a TR to the
EDMA3TC. TC may still be transferring data when the interrupt/chain is triggered.
0-7h
Reserved
3
FIFO width is 8-bit
1h
FIFO width is 16-bit
2h
FIFO width is 32-bit
3h
FIFO width is 64-bit
4h
FIFO width is 128-bit
5h
FIFO width is 256-bit
0
STATIC
2
Set is not static. The PaRAM set is updated or linked after a TR is submitted. A value of 0 should be
used for DMA channels and for non-final transfers in a linked list of QDMA transfers.
1
Set is static. The PaRAM set is not updated or linked after a TR is submitted. A value of 1 should be
used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.
Transfer synchronization dimension.
0
A-synchronized. Each event triggers the transfer of a single array of ACNT bytes.
1
AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.
Destination address mode.
0
Increment (INCR) mode. Destination addressing within an array increments. Destination is not a FIFO.
1
Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
SAM
2.3.2.2
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
Static set.
DAM
0
Reserved
0
SYNCDIM
1
FIFO Width. Applies if either SAM or DAM is set to constant addressing mode.
0
6h-7h
7-4
Description
Source address mode.
0
Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
1
Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
Channel Source Address (SRC)
The 32-bit source address parameter specifies the starting byte address of the source. For SAM in
increment mode, there are no alignment restrictions imposed by EDMA3. For SAM in constant addressing
mode, you must program the source address to be aligned to a 256-bit aligned address (5 LSBs of
address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 2.12.3 for
additional details.
2.3.2.3
Channel Destination Address (DST)
The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM
in increment mode, there are no alignment restrictions imposed by EDMA3. For DAM in constant
addressing mode, you must program the destination address to be aligned to a 256-bit aligned address (5
LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 2.12.3
for additional details.
2.3.2.4
Count for 1st Dimension (ACNT)
ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned
value with valid values between 0 and 65 535. Therefore, the maximum number of bytes in an array is
65 535 bytes (64K – 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to
EDMA3TC. A transfer with ACNT equal to 0 is considered either a null or dummy transfer.
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See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions.
2.3.2.5
Count for 2nd Dimension (BCNT)
BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal
operation, valid values for BCNT are between 1 and 65 535. Therefore, the maximum number of arrays in
a frame is 65 535 (64K – 1 arrays). A transfer with BCNT equal to 0 is considered either a null or dummy
transfer.
See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions.
2.3.2.6
Count for 3rd Dimension (CCNT)
CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are
between 1 and 65 535. Therefore, the maximum number of frames in a block is 65 535 (64K – 1 frames).
A transfer with CCNT equal to 0 is considered either a null or dummy transfer.
See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions.
2.3.2.7
BCNT Reload (BCNTRLD)
BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the
2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the
EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT reaches 0, the
EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value.
For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC
decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.
2.3.2.8
Source B Index (SRCBIDX)
SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each
array in the 2nd dimension. Valid values for SRCBIDX are between –32 768 and 32 767. It provides a
byte address offset from the beginning of the source array to the beginning of the next source array. It
applies to both A-synchronized and AB-synchronized transfers. Some examples:
• SRCBIDX = 0000h (0): no address offset from the beginning of an array to the beginning of the next
array. All arrays are fixed to the same beginning address.
• SRCBIDX = 0003h (+3): the address offset from the beginning of an array to the beginning of the next
array in a frame is 3 bytes. For example, if the current array begins at address 1000h, the next array
begins at 1003h.
• SRCBIDX = FFFFh (–1): the address offset from the beginning of an array to the beginning of the next
array in a frame is –1 byte. For example, if the current array begins at address 5054h, the next array
begins at 5053h.
2.3.2.9
Destination B Index (DSTBIDX)
DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between
each array in the 2nd dimension. Valid values for DSTBIDX are between –32 768 and 32 767. It provides
a byte address offset from the beginning of the destination array to the beginning of the next destination
array within the current frame. It applies to both A-synchronized and AB-synchronized transfers. See
SRCBIDX for examples.
2.3.2.10 Source C Index (SRCCIDX)
SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the
3rd dimension. Valid values for SRCCIDX are between –32 768 and 32 767. It provides a byte address
offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first
source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that
when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame
(Figure 2-7), while the current array in an AB-synchronized transfer is the first array in the frame
(Figure 2-8).
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2.3.2.11 Destination C Index (DSTCIDX)
DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the
3rd dimension. Valid values are between –32 768 and 32 767. It provides a byte address offset from the
beginning of the current array (pointed to by DST address) to the beginning of the first destination array
TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when
DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame
(Figure 2-7), while the current array in a AB-synchronized transfer is the first array in the frame
(Figure 2-8).
2.3.2.12 Link Address (LINK)
The EDMA3CC provides a mechanism, called linking, to reload the current PaRAM set upon its natural
termination (that is, after the count fields are decremented to 0) with a new PaRAM set. The 16-bit
parameter LINK specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads
the next PaRAM set during linking.
You must program the link address to point to a valid aligned 32-byte PaRAM set. The 5 LSBs of the LINK
field should be cleared to 0.
The EDMA3CC ignores the upper 2 bits of the LINK entry, allowing the programmer the flexibility of
programming the link address as either an absolute/literal byte address or use the PaRAM-base-relative
offset address. Therefore, if you make use of the literal address with a range from 4000h to 7FFFh, it will
be treated as a PaRAM-base-relative value of 0000h to 3FFFh.
You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM
address that falls in the range of the available PaRAM addresses on the device.
A LINK value of FFFFh is referred to as a NULL link that should cause the EDMA3CC to perform an
internal write of 0 to all entries of the current PaRAM set, except for the LINK field that is set to FFFFh.
Also, see Section 2.5 for details on terminating a transfer.
2.3.3 Null PaRAM Set
A null PaRAM set is defined as a PaRAM set where all count fields (ACNT, BCNT, and CCNT) are
cleared to 0. If a PaRAM set associated with a channel is a NULL set, then when serviced by the
EDMA3CC, the bit corresponding to the channel is set in the associated event missed register (EMR,
EMRH, or QEMR). This bit remains set in the associated secondary event register (SER, SERH, or
QSER). This implies that any future events on the same channel are ignored by the EDMA3CC and you
are required to clear the bit in SER, SERH, or QSER for the channel. This is considered an error
condition, since events are not expected on a channel that is configured as a null transfer. See
Section 4.2.6.8 and Section 4.2.2.1 for more information on the SER and EMR registers, respectively.
2.3.4 Dummy PaRAM Set
A dummy PaRAM set is defined as a PaRAM set where at least one of the count fields (ACNT, BCNT, or
CCNT) is cleared to 0 and at least one of the count fields is nonzero.
If a PaRAM set associated with a channel is a dummy set, then when serviced by the EDMA3CC, it will
not set the bit corresponding to the channel (DMA/QDMA) in the event missed register (EMR, EMRH, or
QEMR) and the secondary event register (SER, SERH, or QSER) bit gets cleared similar to a normal
transfer. Future events on that channel are serviced. A dummy transfer is a legal transfer of 0 bytes. See
Section 4.2.6.8 and Section 4.2.2.1 for more information on the SER and EMR registers, respectively.
2.3.5 Dummy Versus Null Transfer Comparison
There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request.
A null transfer request is an error condition, but a dummy transfer is a legal transfer of 0 bytes. A null
transfer causes an error bit (En) in EMR to get set and the En bit in SER remains set, essentially
preventing any further transfers on that channel without clearing the associated error registers.
Table 2-4 summarizes the conditions and effects of null and dummy transfer requests.
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Table 2-4. Dummy and Null Transfer Request
Feature
Null TR
Dummy TR
EMR/EMRH/QEMR is set
Yes
No
SER/SERH/QSER remains set
Yes
No
Link update (STATIC = 0 in OPT)
Yes
Yes
QER is set
Yes
Yes
IPR/IPRH CER/CERH is set using early completion
Yes
Yes
2.3.6 Parameter Set Updates
When a TR is submitted for a given DMA/QDMA channel and its corresponding PaRAM set, the
EDMA3CC is responsible for updating the PaRAM set in anticipation of the next trigger event. For events
that are not final, this includes address and count updates; for final events, this includes the link update.
The specific PaRAM set entries that are updated depend on the channel’s synchronization type
(A-synchronized or B-synchronized) and the current state of the PaRAM set. A B-update refers to the
decrementing of BCNT in the case of A-synchronized transfers after the submission of successive TRs. A
C-update refers to the decrementing of CCNT in the case of A-synchronized transfers after BCNT TRs for
ACNT byte transfers have submitted. For AB-synchronized transfers, a C-update refers to the
decrementing of CCNT after submission of every transfer request.
See Table 2-5 for details and conditions on the parameter updates. A link update occurs when the PaRAM
set is exhausted, as described in Section 2.3.7.
After the TR is read from the PaRAM (and is in process of being submitted to EDMA3TC), the following
fields are updated if needed:
• A-synchronized: BCNT, CCNT, SRC, DST
• AB-synchronized: CCNT, SRC, DST
The following fields are not updated (except for during linking, where all fields are overwritten by the link
PaRAM set):
• A-synchronized: ACNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK
• AB-synchronized: ACNT, BCNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK
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Note that PaRAM updates only pertain to the information that is needed to properly submit the next
transfer request to the EDMA3TC. Updates that occur while data is moved within a transfer request are
tracked within the transfer controller, and is detailed in Section 2.12. For A-synchronized transfers, the
EDMA3CC always submits a TRP for ACNT bytes (BCNT = 1 and CCNT = 1). For AB-synchronized
transfers, the EDMA3CC always submits a TRP for ACNT bytes of BCNT arrays (CCNT = 1). The
EDMA3TC is responsible for updating source and destination addresses within the array based on ACNT
and FWID (in OPT). For AB-synchronized transfers, the EDMA3TC is also responsible to update source
and destination addresses between arrays based on SRCBIDX and DSTBIDX.
Table 2-5 shows the details of parameter updates that occur within EDMA3CC for A-synchronized and
AB-synchronized transfers.
Table 2-5. Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set)
A-Synchronized Transfer
AB-Synchronized Transfer
B-Update
C-Update
Link Update
B-Update
C-Update
Link Update
BCNT > 1
BCNT == 1 &&
CCNT > 1
BCNT == 1 &&
CCNT == 1
N/A
CCNT > 1
CCNT == 1
SRC
+= SRCBIDX
+= SRCCIDX
= Link.SRC
in EDMA3TC
+= SRCCIDX
= Link.SRC
DST
+= DSTBIDX
+= DSTCIDX
= Link.DST
in EDMA3TC
+= DSTCIDX
= Link.DST
ACNT
None
None
= Link.ACNT
None
None
= Link.ACNT
BCNT
–= 1
= BCNTRLD
= Link.BCNT
in EDMA3TC
N/A
= Link.BCNT
CCNT
None
–= 1
= Link.CCNT
in EDMA3TC
–=1
= Link.CCNT
SRCBIDX
None
None
= Link.SRCBIDX
in EDMA3TC
None
= Link.SRCBIDX
DSTBIDX
None
None
= Link.DSTBIDX
None
None
= Link.DSTBIDX
SRCCIDX
None
None
= Link.SRCBIDX
in EDMA3TC
None
= Link.SRCBIDX
DSTCIDX
None
None
= Link.DSTBIDX
None
None
= Link.DSTBIDX
LINK
None
None
= Link.LINK
None
None
= Link.LINK
BCNTRLD
None
None
= Link.BCNTRLD
None
None
= Link.BCNTRLD
OPT (1)
None
None
= LINK.OPT
None
None
= LINK.OPT
Condition:
(1)
In all cases, no updates occur if OPT.STATIC == 1 for the current PaRAM set.
NOTE: The EDMA3CC includes no special hardware to detect when an indexed address update
calculation overflows/underflows. The address update will wrap across boundaries as
programmed by the user. You should ensure that no transfer is allowed to cross internal port
boundaries between peripherals. A single TR must target a single source/destination slave
endpoint.
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2.3.7 Linking Transfers
The EDMA3CC provides a mechanism known as linking, which allows the entire PaRAM set to be
reloaded from a location within the PaRAM memory map (for both DMA and QDMA channels). Linking is
especially useful for maintaining ping-pong buffers, circular buffering, and repetitive/continuous transfers
with no CPU intervention. Upon completion of a transfer, the current transfer parameters are reloaded with
the parameter set pointed that the 16-bit link address field of the current parameter set points to. Linking
only occurs when the STATIC bit in OPT clears.
NOTE: You should always link a transfer (EDMA3 or QDMA) to another useful transfer. If you must
terminate a transfer, then you should link the transfer to a NULL parameter set. See
Section 2.3.3.
The link update occurs after the current PaRAM set event parameters have been exhausted. An event's
parameters are exhausted when the EDMA3 channel controller has submitted all of the transfers that are
associated with the PaRAM set.
A link update occurs for null and dummy transfers depending on the state of the STATIC bit in OPT and
the LINK field. In both cases (null or dummy), if the value of LINK is FFFFh, then a null PaRAM set (with
all 0s and LINK set to FFFFh) is written to the current PaRAM set. Similarly, if LINK is set to a value other
than FFFFh, then the appropriate PaRAM location that LINK points to is copied to the current PaRAM set.
Once the channel completion conditions are met for an event, the transfer parameters that are located at
the link address are loaded into the current DMA or QDMA channel’s associated parameter set. This
indicates that the EDMA3CC reads the entire set (eight words) from the PaRAM set specified by LINK and
writes all eight words to the PaRAM set that is associated with the current channel. Figure 2-11 shows an
example of a linked transfer.
You can use any PaRAM set in the PaRAM as a link/reload parameter set.
If a PaRAM set location is defined as a QDMA channel PaRAM set (by QCHMAPn), then copying the link
PaRAM set into the current QDMA channel PaRAM set is recognized as a trigger event. It is latched in
QER because a write to the trigger word was performed. You can use this feature to create a linked list of
transfers using a single QDMA channel and multiple PaRAM sets. See Section 2.4.2.
Linking to itself replicates the behavior of auto-initialization, thus facilitating the use of circular buffering
and repetitive transfers. After an EDMA3 channel exhausts its current PaRAM set, it reloads all of the
parameter set entries from another PaRAM set, which is initialized with values that are identical to the
original PaRAM set. Figure 2-12 shows an example of a linked to self transfer. Here, the PaRAM set 255
has the link field pointing to the address of parameter set 255 (linked to self).
NOTE: If the STATIC bit in OPT is set for a PaRAM set, then link updates are not performed.
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Figure 2-11. Linked Transfer
(a) At initialization
PaRAM set 3
Byte
address
Set
#
PaRAM
02A0 4000h
02A0 4020h
02A0 4040h
02A0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
BCNTRLD X Link X=5FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 255
02A0 5FC0h
02A0 5FE0h
254
255
Parameter set 254
Parameter set 255
(b) After completion of PaRAM set 3
(link update)
OPT Y
SRC Y
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
PaRAM set 255
Byte
address
Set
#
PaRAM
02A0 4000h
02A0 4020h
02A0 4040h
02A0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT Y
SRC Y
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
Link
update
PaRAM set 255
02A0 5FC0h
02A0 5FE0h
254
255
OPT Y
SRC Y
Parameter set 254
Parameter set 255
BCNT Y
(c) After completion of PaRAM set 255
(link to null set)
Byte
address
Set
#
PaRAM
02A0 4000h
02A0 4020h
02A0 4040h
02A0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
PaRAM set 3 (Null PaRAM set)
0h
0h
0h
0h
0h
02A0 5FC0h
02A0 5FE0h
254
255
Parameter set 254
Parameter set 255
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0h
0h
0h
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0h
Link=FFFFh
0h
0h
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Figure 2-12. Link-to-Self Transfer
(a) At initialization
PaRAM set 3
Byte
address
Set
#
PaRAM
02A0 4000h
02A0 4020h
02A0 4040h
02A0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
BCNTRLD X
Link=5FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 255
02A0 5FC0h
02A0 5FE0h
254
255
Parameter set 254
Parameter set 255
(b) After completion of PaRAM set 3
(link update)
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link =5FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 3
Byte
address
Set
#
PaRAM
02A0 4000h
02A0 4020h
02A0 4040h
02A0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link =5FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 255
02A0 5FC0h
02A0 5FE0h
254
255
OPT X
SRC X
Parameter set 254
Parameter set 255
Link
update
BCNT X
(c) After completion of PaRAM set 255
(link to self)
Byte
address
Set
#
PaRAM
02A0 4000h
02A0 4020h
02A0 4040h
02A0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link =5FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 3
OPT X
SRC X
BCNT X
02A0 5FC0h
02A0 5FE0h
40
EDMA3 Architecture
254
255
Parameter set 254
Parameter set 255
ACNT X
DST X
SRCBIDX X
DSTBIDX X
Link=5FE0h
BCNTRLD X
SRCCIDX X
DSTCIDX X
CCNT X
Rsvd
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2.3.8 Constant Addressing Mode Transfers/Alignment Issues
If either SAM or DAM is set (constant addressing mode), then the source or destination address must be
aligned to a 256-bit aligned address, respectively, and the corresponding BIDX should be an even multiple
of 32 bytes (256 bits). The EDMA3CC does not recognize errors here, but the EDMA3TC asserts an error
if this is not true. See Section 2.12.3.
NOTE: Constant (CONST) addressing mode has limited applicability. The EDMA3 should be
configured for CONST mode (SAM/DAM = 1) only if the transfer source or destination
(on-chip memory, off-chip memory controllers, slave peripherals) support constant
addressing mode.
See the device-specific data manual and/or peripheral user's guide to verify if constant
addressing mode is supported. If constant addressing mode is not supported, the similar
logical transfer can be achieved using INCR mode (SAM/DAM = 0) by appropriately
programming the count and indices values.
2.3.9 Element Size
The EDMA3 controller does not use element-size and element-indexing. Instead, all transfers are defined
in terms of all three dimensions: ACNT, BCNT, and CCNT. An element-indexed transfer is logically
achieved by programming ACNT to the size of the element and BCNT to the number of elements that
need to be transferred. For example, if you have 16-bit audio data and 256 audio samples that must be
transferred to a serial port, you can only do this by programming the ACNT = 2 (2 bytes) and BCNT = 256.
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Initiating a DMA Transfer
There are multiple ways to initiate a programmed data transfer using the EDMA3 channel controller.
Transfers on DMA channels are initiated by three sources.
They are listed as follows:
• Event-triggered transfer request (this is the more typical usage of EDMA3): A peripheral, system, or
externally-generated event triggers a transfer request.
• Manually-triggered transfer request:The CPU to manually triggers a transfer by writing a 1 to the
corresponding bit in the event set register (ESR/ESRH).
• Chain-triggered transfer request: A transfer is triggered on the completion of another transfer or
sub-transfer.
Transfers on QDMA channels are initiated by two sources. They are as follows:
• Auto-triggered transfer request: Writing to the programmed trigger word triggers a transfer.
• Link-triggered transfer requests: Writing to the trigger word triggers the transfer when linking occurs.
2.4.1 DMA Channel
2.4.1.1
Event-Triggered Transfer Request
When an event is asserted from a peripheral or device pins, it gets latched in the corresponding bit of the
event register (ER.En = 1). For peripheral event-to-DMA event mapping, see Table 2-6. If the
corresponding event in the event enable register (EER) is enabled (EER.En = 1), then the EDMA3CC
prioritizes and queues the event in the appropriate event queue. When the event reaches the head of the
queue, it is evaluated for submission as a transfer request to the transfer controller.
If the PaRAM set is valid (not a NULL set), then a transfer request packet (TRP) is submitted to the
EDMA3TC and the En bit in ER is cleared. At this point, a new event can be safely received by the
EDMA3CC.
If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request
(TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding
channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to
a null TR being serviced. Good programming practices should include cleaning the event missed error
before re-triggering the DMA channel.
When an event is received, the corresponding event bit in the event register is set (ER.En = 1), regardless
of the state of EER.En. If the event is disabled when an external event is received (ER.En = 1 and
EER.En = 0), the ER.En bit remains set. If the event is subsequently enabled (EER.En = 1), then the
pending event is processed by the EDMA3CC and the TR is processed/submitted, after which the ER.En
bit is cleared.
If an event is being processed (prioritized or is in the event queue) and another sync event is received for
the same channel prior to the original being cleared (ER.En != 0), then the second event is registered as a
missed event in the corresponding bit of the event missed register (EMR.En = 1).
Table 2-6 gives an example of the synchronization events associated with each of the programmable
DMA channels in the device. To determine the event-to-channel mapping, see the device-specific data
manual.
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Table 2-6. EDMA3 Channel Synchronization Events
(1)
(2)
EDMA3 Channel
Event Name
0 (2)
DSP_EVT
HPI/PCI-to-DSP Event
1
TEVTLO0
Timer 0 Lower Counter Event
Timer 0 Higher Counter Event
(1)
Event Description
2
TEVTHI0
3-8
-
9
ETBHFULLINT
10
ETBFULLINT
Embedded Trace Buffer (ETB) is Full
11
ETBACQINT
Embedded Trace Buffer (ETB) Acquisition is
Complete
12
XEVT0
MCBSP0 Transmit Event
13
REVT0
MCBSP0 Receive Event
14
XEVT1
MCBSP1 Transmit Event
15
REVT1
MCBSP1 Receive Event
16
TINT1L
Timer1 Lower Counter Event
17
TINT1H
Timer1 Higher Counter Event
18
-
19
INTDST0
RapidIO Interrupt 0
20
INTDST1
RapidIO Interrupt 1
21
INTDST2
RapidIO Interrupt 2
22
INTDST3
RapidIO Interrupt 3
23
INTDST4
RapidIO Interrupt 4
24
INTDST5
RapidIO Interrupt 5
25
INTDST6
RapidIO Interrupt 6
None
Embedded Trace Buffer (ETB) is Half Full
None
26-27
-
28
VCP2REVT
VCP2 Receive Event
29
VCP2XEVT
VCP2 Transmit Event
30
TCP2AREVT
TCP2_A Receive Event
31
TCP2AXEVT
TCP2_A Transmit Event
32
UREVT
UTOPIA Receive Event
33
TCP2BREVT
TCP2_B Receive Event
TCP2_B Transmit Event
34
TCP2BXEVT
35-39
-
40
UXEVT
None
None
UTOPIA Transmit Event
41-43
-
44
ICREVT
None
I2C Receive Event
45
ICXEVT
I2C Transmit Event
46-47
-
48
GPINT0
None
GPIO Event 0
49
GPINT1
GPIO Event 1
50
GPINT2
GPIO Event 2
51
GPINT3
GPIO Event 3
52
GPINT4
GPIO Event 4
53
GPINT5
GPIO Event 5
54
GPINT6
GPIO Event 6
55
GPINT7
GPIO Event 7
56
GPINT8
GPIO Event 8
To determine the event-to-channel mapping for your device, see the device-specific data manual.
HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the
EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
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Table 2-6. EDMA3 Channel Synchronization Events (1) (continued)
2.4.1.2
EDMA3 Channel
Event Name
57
GPINT9
Event Description
GPIO Event 9
58
GPINT10
GPIO Event 10
59
GPINT11
GPIO Event 11
60
GPINT12
GPIO Event 12
61
GPINT13
GPIO Event 13
62
GPINT14
GPIO Event 14
63
GPINT15
GPIO Event 15
Manually-Triggered Transfer Request
The CPU or any EDMA programmer initiates a DMA transfer by writing to the event set register (ESR).
Writing a 1 to an event bit in the ESR results in the event being prioritized/queued in the appropriate event
queue, regardless of the state of the EER.En bit. When the event reaches the head of the queue, it is
evaluated for submission as a transfer request to the transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request
(TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding
channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to
a null TR being serviced. Good programming practices should include clearing the event missed error
before re-triggering the DMA channel.
If an event is being processed (prioritized or is in the event queue) and the same channel is manually set
by a write to the corresponding channel bit of the event set register (ESR.En = 1) prior to the original
being cleared (ESR.En = 0), then the second event is registered as a missed event in the corresponding
bit of the event missed register (EMR.En = 1).
2.4.1.3
Chain-Triggered Transfer Request
Chaining is a mechanism by which the completion of one transfer automatically sets the event for another
channel. When a chained completion code is detected, the value of which is dictated by the transfer
completion code (TCC[5:0] in OPT of the PaRAM set associated with the channel), it results in the
corresponding bit in the chained event register (CER) to be set (CER.E[TCC] = 1).
Once a bit is set in CER, the EDMA3CC prioritizes and queues the event in the appropriate event queue.
When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request
(TR) is submitted and the corresponding En bit in CER is cleared and simultaneously the corresponding
channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to
a null TR being serviced. In this case, the error condition must be cleared by you before the DMA channel
can be re-triggered. Good programming practices might include clearing the event missed error before
re-triggering the DMA channel.
If a chaining event is being processed (prioritized or queued) and another chained event is received for
the same channel prior to the original being cleared (CER.En != 0), then the second chained event is
registered as a missed event in the corresponding channel bit of the event missed register (EMR.En = 1).
NOTE: Chained event registers, event registers, and event set registers operate independently. An
event (En) can be triggered by any of the trigger sources (event-triggered,
manually-triggered, or chain-triggered).
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2.4.2 QDMA Channels
2.4.2.1
Auto-triggered and Link-Triggered Transfer Request
QDMA-based transfer requests are issued when a QDMA event gets latched in the QDMA event register
(QER.En = 1). A bit corresponding to a QDMA channel is set in the QDMA event register (QER) when the
following occurs:
• A CPU (or any EDMA3 programmer) write occurs to a PaRAM address that is defined as a QDMA
channel trigger word (programmed in the QDMA channel mapping register (QCHMAPn)) for the
particular QDMA channel and the QDMA channel is enabled via the QDMA event enable register
(QEER.En = 1).
• EDMA3CC performs a link update on a PaRAM set address that is configured as a QDMA channel
(matches QCHMAPn settings) and the corresponding channel is enabled via the QDMA event enable
register (QEER.En = 1).
Once a bit is set in QER, the EDMA3CC prioritizes and queues the event in the appropriate event queue.
When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If a bit is already set in QER (QER.En = 1) and a second QDMA event for the same QDMA channel
occurs prior to the original being cleared, the second QDMA event gets captured in the QDMA event miss
register (QEMR.En = 1).
2.4.3 Comparison Between DMA and QDMA Channels
The primary difference between DMA and QDMA channels is the event/channel synchronization. QDMA
events are either auto-triggered or link triggered. auto-triggering allows QDMA channels to be triggered by
CPU(s) with a minimum number of linear writes to PaRAM. Link triggering allows a linked list of transfers
to be executed, using a single QDMA PaRAM set and multiple link PaRAM sets.
A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the
QDMA channel parameter set (auto-triggered) or when the EDMA3CC performs a link update on a
PaRAM set that has been mapped to a QDMA channel (link triggered). Note that for CPU triggered
(manually triggered) DMA channels, in addition to writing to the PaRAM set, it is required to write to the
event set register (ESR) to kick-off the transfer.
QDMA channels are typically for cases where a single event will accomplish a complete transfer since the
CPU (or EDMA3 programmer) must reprogram some portion of the QDMA PaRAM set in order to
re-trigger the channel. In other words, QDMA transfers are programmed with BCNT = CCNT = 1 for
A-synchronized transfers, and CCNT = 1 for AB-synchronized transfers.
Additionally, since linking is also supported (if STATIC = 0 in OPT) for QDMA transfers, it allows you to
initiate a linked list of QDMAs, so when EDMA3CC copies over a link PaRAM set (including the write to
the trigger word), the current PaRAM set mapped to the QDMA channel will automatically be recognized
as a valid QDMA event and initiate another set of transfers as specified by the linked set.
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Completion of a DMA Transfer
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Completion of a DMA Transfer
A parameter set for a given channel is complete when the required number of transfer requests is
submitted (based on receiving the number of synchronization events). The expected number of TRs for a
non-null/non-dummy transfer is shown in Table 2-7 for both synchronization types along with state of the
PaRAM set prior to the final TR being submitted. When the counts (BCNT and/or CCNT) are this value,
the next TR results in a:
• Final chaining or interrupt codes to be sent by the transfer controllers (instead of intermediate).
• Link updates (linking to either null or another valid link set).
Table 2-7. Expected Number of Transfers for Non-Null Transfer
Sync Mode
Counts at Time 0
Total # Transfers
Counts Prior to Final TR
A-synchronized
ACNT
BCNT
CCNT
(BCNT × CCNT ) TRs of ACNT bytes each
BCNT == 1 && CCNT == 1
AB-synchronized
ACNT
BCNT
CCNT
CCNT TRs for ACNT × BCNT bytes each
CCNT == 1
You must program the PaRAM OPT field with a specific transfer completion code (TCC) along with the
other OPT fields (TCCHEN, TCINTEN, ITCCHEN, and ITCINTEN bits) to indicate whether the completion
code is to be used for generating a chained event or/and for generating an interrupt upon completion of a
transfer.
The specific TCC value (6-bit binary value) programmed dictates which of the 64-bits in the chain event
register (CER[TCC]) and/or interrupt pending register (IPR[TCC]) is set.
See Section 2.9 for details on interrupts and Section 2.8 for details on chaining.
You can also selectively program whether the transfer controller sends back completion codes on
completion of the final transfer request (TR) of a parameter set (TCCHEN or TCINTEN), for all but the
final transfer request (TR) of a parameter set (ITCCHEN or ITCINTEN), or for all TRs of a parameter set
(both). See Section 2.8 for details on chaining (intermediate/final chaining) and Section 2.9 for details on
intermediate/final interrupt completion.
A completion detection interface exists between the EDMA3 channel controller and transfer controller(s).
This interface sends back information from the transfer controller to the channel controller to indicate that
a specific transfer is completed.
All DMA/QDMA PaRAM sets must also specify a link address value. For repetitive transfers such as
ping-pong buffers, the link address value should point to another predefined PaRAM set. Alternatively, a
non-repetitive transfer should set the link address value to the null link value. The null link value is defined
as FFFFh. See Section 2.3.7 for more details.
NOTE: Any incoming events that are mapped to a null PaRAM set results in an error condition. The
error condition should be cleared before the corresponding channel is used again. See
Section 2.3.5.
There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal
completion, early completion, and dummy/null completion. This applies to both chained events and
completion interrupt generation.
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2.5.1 Normal Completion
In normal completion mode (TCCMODE = 0 in OPT), the transfer or sub-transfer is considered to be
complete when the EDMA3 channel controller receives the completion codes from the EDMA3 transfer
controller. In this mode, the completion code to the channel controller is posted by the transfer controller
after it receives a signal from the destination peripheral. Normal completion is typically used to generate
an interrupt to inform the CPU that a set of data is ready for processing.
2.5.2 Early Completion
In early completion mode (TCCMODE = 1 in OPT), the transfer is considered to be complete when the
EDMA3 channel controller submits the transfer request (TR) to the EDMA3 transfer controller. In this
mode, the channel controller generates the completion code internally. Early completion is typically useful
for chaining, as it allows subsequent transfers to be chained-triggered while the previous transfer is still in
progress within the transfer controller, maximizing the overall throughput of the set of the transfers.
2.5.3 Dummy or Null Completion
This is a variation of early completion. Dummy or null completion is associated with a dummy set
(Section 2.3.4) or null set (Section 2.3.3). In both cases, the EDMA3 channel controller does not submit
the associated transfer request to the EDMA3 transfer controller(s). However, if the set (dummy/null) has
the OPT field programmed to return completion code (intermediate/final interrupt/chaining completion),
then it will set the appropriate bits in the interrupt pending registers (IPR/IPRH) or chained event register
(CER/CERH). The internal early completion path is used by the channel controller to return the completion
codes internally (that is, EDMA3CC generates the completion code).
2.6
Event, Channel, and PaRAM Mapping
Several of the 64 DMA channels are tied to a specific hardware event, thus allowing events from device
peripherals or external hardware to trigger transfers. A DMA channel typically requests a data transfer
when it receives its event (apart from manually-triggered, chain-triggered, and other transfers). The
amount of data transferred per synchronization event depends on the channel’s configuration (ACNT,
BCNT, CCNT, etc.) and the synchronization type (A-synchronized or AB-synchronized).
The association of an event to a channel is fixed, each DMA channel has one specific event associated
with it. Table 2-6 provides the synchronization events that are associated with each of the programmable
DMA channels.
In an application, if a channel does not use the associated synchronization event or if it does not have an
associated synchronization event (unused), that channel can be used for manually-triggered or
chained-triggered transfers, for linking/reloading, or as a QDMA channel.
2.6.1 DMA Channel to PaRAM Mapping
The mapping between the DMA channel numbers and the PaRAM sets is programmable. The DMA
channel mapping registers (DCHMAPn) in the EDMA3CC provide programmability that allows you to map
the DMA channels to any of the PaRAM sets in the PaRAM memory map. Figure 2-13 illustrates the use
of DCHMAP. There is one DCHMAP register per channel.
2.6.2 QDMA Channel to PaRAM Mapping
The mapping between the QDMA channels and the PaRAM sets is programmable. The QDMA channel
mapping register (QCHMAP) in the EDMA3CC allows you to map the QDMA channels to any of the
PaRAM sets in the PaRAM memory map. Figure 2-13 illustrates the use of QCHMAP.
Additionally, QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel. A
trigger word is one of the eight words in the PaRAM set. For a QDMA transfer to occur, a valid TR
synchronization event for EDMA3CC is a write to the trigger word in the PaRAM set pointed to by
QCHMAP for a particular QDMA channel. By default, QDMA channels are mapped to PaRAM set 0. You
must appropriately re-map PaRAM set 0 before you use it.
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QDMA channel to PaRAM mapping is shown in Figure 2-13.
Figure 2-13. DMA/QDMA Channel to PaRAM Mapping
DCHMAPn
31
QCHMAPn
14 13
0000 0000 0000 0000 00
5
PAENTRY
4
0
00000
31
14 13
5 4
0000 0000 0000 0000 00
PAENTRY
Byte
address
Set
#
PaRAM
02A0 4000h
0
Parameter set 0
OPT
02A0 4020h
1
Parameter set 1
SRC
02A0 4040h
2
Parameter set 2
02A0 4060h
3
Parameter set 3
PaRAM set
BCNT
2 1 0
TR WORD 00
Byte
address
offset
+0h
+4h
ACNT
+8h
+Ch
DST
DSTBIDX
SRCBIDX
+10h
BCNTRLD
LINK
+14h
DSTCIDX
SRCCIDX
+18h
Rsvd
CCNT
+1Ch
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EDMA3 Architecture
02A0 5FC0h
254
Parameter set 254
02A0 5FE0h
255
Parameter set 255
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2.7
EDMA3 Channel Controller Regions
The EDMA3 channel controller divides its address space into eight regions. Individual channel resources
are assigned to a specific region, where each region is typically assigned to a specific EDMA programmer.
You can design the application software to use regions or to ignore them altogether. You can use active
memory protection in conjunction with regions so that only a specific EDMA programmer (for example,
privilege identification) or privilege level (for example, user vs. supervisor) is allowed access to a given
region, and thus to a given DMA or QDMA channel. This allows robust system-level DMA code where
each EDMA programmer only modifies the state of the assigned resources. Memory protection is
described in Section 2.10.
2.7.1 Region Overview
The EDMA3 channel controller memory-mapped registers are divided in three main categories:
1. Global registers
2. Global region channel registers
3. Shadow region channel registers
The global registers are located at a single/fixed location in the EDMA3CC memory map. These registers
control EDMA3 resource mapping and provide debug visibility and error tracking information. See the
device-specific data manual for the EDMA3CC memory map.
The channel registers (including DMA, QDMA, and interrupt registers) are accessible via the global
channel region address range, or in the shadow n channel region address range(s). For example, the
event enable register (EER) is visible at the global address of 02A0 1020h or region addresses of
02A0 2020h for region 0, 02A0 2220h for region 1, … 02A0 2E20h for region 7.
The DMA region access enable registers (DRAEm) and the QDMA region access enable registers
(QRAEn) control the underlying control register bits that are accessible via the shadow region address
space (except for IEVALn). Table 2-8 lists the registers in the shadow region memory map. See the
EDMA3CC memory map (Table 4-1) for the complete global and shadow region memory maps.
Figure 2-14 illustrates the conceptual view of the regions.
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Table 2-8. Shadow Region Registers
DRAEm
DRAEHm
ER
ERH
QRAEn
QER
ECR
ECRH
QEER
ESR
ESRH
QEECR
CER
CERH
QEESR
EER
EERH
EECR
EECRH
EESR
EESRH
SER
SERH
SECR
SECRH
IER
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
Register not affected by DRAE/DRAEH
IEVAL
Figure 2-14. Shadow Region Registers
Shadow region 0
Access address
02A0 2000h
02A0 2094h
except IEVAL
ER, ERH
QSECR
DRAE0/
DRAE0H
QRAE0
IEVAL
Shadow region 0
registers
Physical register
ER, ERH
ECR, ECRH
ESR, ESRH
CER, CERH
EER, EERH
EECR, EECRH
EESR, EESRH
SER, SERH
SECR, SECRH
02A0 1000h
IER, IERH
IECR,
IESR,
IPR,
ICR,
IEVAL,
ER, ERH
Access address
02A0 2E00h
02A0 2E94h
QSECR
DRAE7/
DRAE7H
QRAE7
IEVAL
QER
QEER
QEECR
QEESR
QSER
QSECR
02A0 1094h
Shadow region 7
registers
2.7.2 Channel Controller Regions
There are eight EDMA3 shadow regions (and associated memory maps). Associated with each shadow
region are a set of registers defining which channels and interrupt completion codes belong to that region.
These registers are user-programmed per region to assign ownership of the DMA/QDMA channels to a
region.
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•
•
•
DRAEm and DRAEHm: One register pair exists for each of the shadow regions. The number of bits in
each register pair matches the number of DMA channels (64 DMA channels). These registers need to
be programmed to assign ownership of DMA channels and interrupt (or TCC codes) to the respective
region. Accesses to DMA and interrupt registers via the shadow region address view are filtered
through the DRAE/DRAEH pair. A value of 1 in the corresponding DRAE(H) bit implies that the
corresponding DMA/interrupt channel is accessible; a value of 0 in the corresponding DRAE(H) bit
forces writes to be discarded and returns a value of 0 for reads.
QRAEn: One register exists for every region. The number of bits in each register matches the number
of QDMA channels (4 (TCI6482/86/C6472) or 8 (TCI6487/88) QDMA channels). These registers must
be programmed to assign ownership of QDMA channels to the respective region. To enable a channel
in a shadow region using shadow region 0 QEER, the respective bit in QRAE must be set or writing
into QEESR will not have the desired effect.
MPPAn and MPPAG: One register exists for every region. This register defines the privilege level,
requestor, and types of accesses allowed to a region's memory-mapped registers.
It is typical for an application to have a unique assignment of DMA/QDMA channels (and, therefore, a
given bit position) to a given region.
The use of shadow regions allows for restricted access to EDMA3 resources (DMA channels, QDMA
channels, TCC, interrupts) by tasks in a system by setting or clearing bits in the DRAE/QRAE registers. If
exclusive access to any given channel/TCC code is required for a region, then only that region's
DRAE/QRAE should have the associated bit set.
Example 2-1. Resource Pool Division Across Two Regions
This example illustrates a judicious resource pool division across two regions, assuming region 0 must be
allocated 16 DMA channels (0-15) and 1 QDMA channel (0) and 32 TCC codes (0-15 and 48-63). Region 1
needs to be allocated 16 DMA channels (16-32) and the remaining 3 QDMA channels (1-3) and TCC codes
(16-47). DRAE should be equal to the OR of the bits that are required for the DMA channels and the TCC
codes:
Region 0:
DRAEH, DRAE = FFFF 0000h, 0000 FFFFh
QRAE = 000 0001h
Region 1:
DRAEH, DRAE = 0000 FFFFh, FFFF 0000h
QRAE = 000 000Eh
2.7.3 Region Interrupts
In addition to the EDMA3CC global completion interrupt, there is an additional completion interrupt line
that is associated with every shadow region. Along with the interrupt enable register (IER), DRAE acts as
a secondary interrupt enable for the respective shadow region interrupts. See Section 2.9 for more
information.
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Chaining EDMA3 Channels
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Chaining EDMA3 Channels
The channel chaining capability for the EDMA3 allows the completion of an EDMA3 channel transfer to
trigger another EDMA3 channel transfer. The purpose is to allow you the ability to chain several events
through one event occurrence.
Chaining is different from linking (Section 2.3.7). The EDMA3 link feature reloads the current channel
parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any
channel parameter set; it provides a synchronization event to the chained channel (see Section 2.4.1.3 for
chain-triggered transfer requests).
Chaining is achieved at either final transfer completion or intermediate transfer completion, or both, of the
current channel. Consider a channel m (DMA/QDMA) required to chain to channel n. Channel number n
(0-63) needs to be programmed into the TCC bit of channel m channel options parameter (OPT) set.
• If final transfer completion chaining (TCCHEN = 1 in OPT) is enabled, the chain-triggered event occurs
after the submission of the last transfer request of channel m is either submitted or completed
(depending on early or normal completion).
• If intermediate transfer completion chaining (ITCCHEN = 1 in OPT) is enabled, the chain-triggered
event occurs after every transfer request, except the last of channel m is either submitted or completed
(depending on early or normal completion).
• If both final and intermediate transfer completion chaining (TCCHEN = 1 and ITCCHEN = 1 in OPT)
are enabled, then the chain-trigger event occurs after every transfer request is submitted or completed
(depending on early or normal completion).
Table 2-9 illustrates the number of chain event triggers occurring in different synchronized scenarios.
Consider channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 2-9. Chain Event Triggers
(Number of chained event triggers on channel 30)
52
Options
A-Synchronized
AB-Synchronized
TCCHEN = 1, ITCCHEN = 0
1 (Owing to the last TR)
1 (Owing to the last TR)
TCCHEN = 0, ITCCHEN = 1
19 (Owing to all but the last TR)
4 (Owing to all but the last TR)
TCCHEN = 1, ITCCHEN = 1
20 (Owing to a total of 60 TRs)
5 (Owing to a total of 5 TRs)
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2.9
EDMA3 Interrupts
The EDMA3 interrupts are divided into 2 categories: transfer completion interrupts and error interrupts.
There are nine region interrupts, eight shadow regions and one global region. The transfer completion
interrupts are listed in Table 2-10 and Table 2-11 and the error interrupts are listed in Table 2-12 and
Table 2-13. The transfer completion interrupts and the error interrupts from the transfer controllers are all
routed to the DSP interrupt controller.
Table 2-10. EDMA3 Transfer Completion Interrupts for TCI6482/86/C6472 Devices
DSP Interrupt
Number
Name
Description
EDMA3CC_GINT
EDMA3CC Global Transfer Completion Interrupt
24
EDMA3CC_INT0
EDMA3CC Transfer Completion Interrupt Shadow Region 0
71
EDMA3CC_INT1
EDMA3CC Transfer Completion Interrupt Shadow Region 1
72
EDMA3CC_INT2
EDMA3CC Transfer Completion Interrupt Shadow Region 2
73
EDMA3CC_INT3
EDMA3CC Transfer Completion Interrupt Shadow Region 3
74
EDMA3CC_INT4
EDMA3CC Transfer Completion Interrupt Shadow Region 4
75
EDMA3CC_INT5
EDMA3CC Transfer Completion Interrupt Shadow Region 5
76
EDMA3CC_INT6
EDMA3CC Transfer Completion Interrupt Shadow Region 6
77
EDMA3CC_INT7
EDMA3CC Transfer Completion Interrupt Shadow Region 7
78
EDMA3CC_AET
EDMA3CC Advanced Event Triggering Event
85
Table 2-11. EDMA3 Transfer Completion Interrupts for TCI6487/88 Devices
DSP Interrupt
Number
Name
Description
EDMA3CC_GINT
EDMA3CC Global Transfer Completion Interrupt
61
EDMA3CC_INT0
EDMA3CC Transfer Completion Interrupt Shadow Region 0
62
EDMA3CC_INT1
EDMA3CC Transfer Completion Interrupt Shadow Region 1
63
EDMA3CC_INT2
EDMA3CC Transfer Completion Interrupt Shadow Region 2
64
EDMA3CC_INT3
EDMA3CC Transfer Completion Interrupt Shadow Region 3
65
EDMA3CC_INT4
EDMA3CC Transfer Completion Interrupt Shadow Region 4
66
EDMA3CC_INT5
EDMA3CC Transfer Completion Interrupt Shadow Region 5
67
EDMA3CC_INT6
EDMA3CC Transfer Completion Interrupt Shadow Region 6
68
EDMA3CC_INT7
EDMA3CC Transfer Completion Interrupt Shadow Region 7
69
EDMA3CC_AET
EDMA3CC Advanced Event Triggering Event
44
Table 2-12. EDMA3 Error Interrupts for TCI6482/86/C6472 Devices
DSP Interrupt
Number
Name
Description
EDMA3CC_ERRINT
EDMA3CC Error Interrupt
79
EDMA3CC_MPINT
EDMA3CC Memory Protection Interrupt
80
EDMA3TC0_ERRINT
TC0 Error Interrupt
81
EDMA3TC1_ERRINT
TC1 Error Interrupt
82
EDMA3TC2_ERRINT
TC2 Error Interrupt
83
EDMA3TC3_ERRINT
TC3 Error Interrupt
84
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Table 2-13. EDMA3 Error Interrupts for TCI6487/88 Devices
(1)
CIC[2:0] Event
Number
Name
Description
EDMA3CC_ERRINT
EDMA3CC Error Interrupt
36
EDMA3CC_MPINT
EDMA3CC Memory Protection Interrupt
37
EDMA3TC0_ERRINT
TC0 Error Interrupt
38
EDMA3TC1_ERRINT
TC1 Error Interrupt
39
EDMA3TC2_ERRINT
TC2 Error Interrupt
40
EDMA3TC3_ERRINT
TC3 Error Interrupt
41
EDMA3TC4_ERRINT
TC4 Error Interrupt
42
EDMA3TC5_ERRINT
TC5 Error Interrupt
43
(1)
Different error interrupts are routed to DSP cores according to the Chip Interrupt Controller (CIC) logic. This is programmable to
the user. For more details, see the TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor data manual
(SPRS358).
2.9.1 Transfer Completion Interrupts
The EDMA3CC is responsible for generating transfer completion interrupts to the CPU. The EDMA3
generates a single completion interrupt per shadow region, as well as one for the global region on behalf
of all 64 channels. The various control registers and bit fields facilitate EDMA3 interrupt generation.
For a given DMA/QDMA channel, the software architecture should either use the global interrupt or the
shadow interrupts, but not both.
The transfer completion code (TCC) value is directly mapped to the bits of the interrupt pending register
(IPR/IPRH). For example, if TCC = 10 0001b, IPRH[1] is set after transfer completion, and results in
interrupt generation to the CPU(s) if the completion interrupt is enabled for the CPU. See Section 2.9.1.1
for details on enabling EDMA3 transfer completion interrupts.
When a completion code is returned (as a result of early or normal completions), the corresponding bit in
IPR/IPRH is set if transfer completion interrupt (final/intermediate) is enabled in the channel options
parameter (OPT) for a PaRAM set associated with the transfer.
You can program the transfer completion code (TCC) to any value for a DMA/QDMA channel. A direct
relation between the channel number and the transfer completion code value does not need to exist. This
allows multiple channels having the same transfer completion code value to cause a CPU to execute the
same interrupt service routine (ISR) for different channels.
If the channel is used in the context of a shadow region and you intend for the shadow region interrupt to
be asserted, then ensure that the bit corresponding to the TCC code is enabled in IER/IERH and in the
corresponding shadow region's DMA region access registers (DRAE/DRAEH).
You can enable Interrupt generation at either final transfer completion or intermediate transfer completion,
or both. Consider channel m as an example.
• If the final transfer interrupt (TCCINT = 1 in OPT) is enabled, the interrupt occurs after the last transfer
request of channel m is either submitted or completed (depending on early or normal completion).
• If the intermediate transfer interrupt (ITCCINT = 1 in OPT) is enabled, the interrupt occurs after every
transfer request, except the last TR of channel m is either submitted or completed (depending on early
or normal completion).
• If both final and intermediate transfer completion interrupts (TCCINT = 1, and ITCCINT = 1 in OPT) are
enabled, then the interrupt occurs after every transfer request is submitted or completed (depending on
early or normal completion).
Table 2-14 shows the number of interrupts that occur in different synchronized scenarios. Consider
channel 31, programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 2-14. Number of Interrupts
54
Options
A-Synchronized
AB-Synchronized
TCINTEN = 1, ITCINTEN = 0
1 (Last TR)
1 (Last TR)
TCINTEN = 0, ITCINTEN = 1
19 (All but the last TR)
4 (All but the last TR)
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Table 2-14. Number of Interrupts (continued)
2.9.1.1
Options
A-Synchronized
AB-Synchronized
TCINTEN = 1, ITCINTEN = 1
20 (All TRs)
5 (All TRs)
Enabling Transfer Completion Interrupts
For the EDMA3 channel controller to assert a transfer completion to the external environment, the
interrupts must be enabled in the EDMA3CC. This is in addition to setting up the TCINTEN and ITCINTEN
bits in OPT of the associated PaRAM set.
The EDMA3 channel controller has interrupt enable registers (IER/IERH) and each bit location in
IER/IERH serves as a primary enable for the corresponding interrupt pending registers (IPR/IPRH).
All of the interrupt registers (IER, IESR, IECR, and IPR) are either manipulated from the global DMA
channel region, or by the DMA channel shadow regions. The shadow regions provide a view to the same
set of physical registers that are in the global region.
The EDMA3 channel controller has a hierarchical completion interrupt scheme that uses a single set of
interrupt pending registers (IPR/IPRH) and single set of interrupt enable registers (IER/IERH). The
programmable DMA region access enable registers (DRAE/DRAEH) provides a second level of interrupt
masking. The global region interrupt output is gated based on the enable mask that is provided by IER.
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The region interrupt outputs are gated by IER and the specific DRAE/DRAEH associated with the region.
See Figure 2-15.
Figure 2-15. Interrupt Diagram
Interrupt pending
register (IPR)
X
1
0
Interrupt
enable
register
(IER)
X
DMA region
access enable 0
(DRAE0)
1
IEVAL.EVAL
0
X
1
IEVAL0.EVAL
DMA region
access enable 7
(DRAE7)
0
X
1
0
IEVAL7.EVAL
Eval
pulse
Eval
pulse
Eval
pulse
EDMA3CC_GINT
EDMA3CC_INT0
EDMA3CC_INT7
For the EDMA3CC to generate the transfer completion interrupts that are associated with each shadow
region, the following conditions must be true:
• EDMA3CC_INT0: (IPR.E0 & IER.E0 & DRAE0.E0) | (IPR.E1 & IER.E1 & DRAE0.E1) | …|(IPRH.E63 &
IERH.E63 & DRAHE0.E63)
• EDMA3CC_INT1: (IPR.E0 & IER.E0 & DRAE1.E0) | (IPR.E1 & IER.E1 & DRAE1.E1) | …| (IPRH.E63
& IERH.E63 & DRAHE1.E63)
• EDMA3CC_INT2 : (IPR.E0 & IER.E0 & DRAE2.E0) | (IPR.E1 & IER.E1 & DRAE2.E1) | …|(IPRH.E63
& IERH.E63 & DRAHE2.E63)....
• Up to EDMA3CC_INT7 : (IPR.E0 & IER.E0 & DRAE7.E0) | (IPR.E1 & IER.E1 & DRAE7.E1) |
…|(IPRH.E63 & IERH.E63 & DRAEH7.E63)
NOTE: The DRAE/DRAEH for all regions are expected to be set up at system initialization and to
remain static for an extended period of time. The interrupt enable registers should be used
for dynamic enable/disable of individual interrupts.
Because there is no relation between the TCC value and the DMA/QDMA channel, it is
possible, for example, for DMA channel 0 to have the OPT.TCC = 63 in its associated
PaRAM set. This would mean that if a transfer completion interrupt is enabled
(OPT.TCINTEN or OPT.ITCINTEN is set), then based on the TCC value, IPRH.E63 is set up
on completion. For proper channel operations and interrupt generation using the shadow
region map, you must program the DRAE/DRAEH that is associated with the shadow region
to have read/write access to both bit 0 (corresponding to channel 0) and bit 63
(corresponding to IPRH bit that is set upon completion).
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2.9.1.2
Clearing Transfer Completion Interrupts
Transfer completion interrupts that are latched to the interrupt pending registers (IPR/IPRH) are cleared by
writing a 1 to the corresponding bit in the interrupt pending clear register (ICR/ICRH). For example, a write
of 1 to ICR.E0 clears a pending interrupt in IPR.E0.
If an incoming transfer completion code (TCC) gets latched to a bit in IPR/IPRH, then additional bits that
get set due to a subsequent transfer completion will not result in asserting the EDMA3CC completion
interrupt. In order for the completion interrupt to be pulsed, the required transition is from a state where no
enabled interrupts are set to a state where at least one enabled interrupt is set.
2.9.2 EDMA3 Interrupt Servicing
Upon completion of a transfer (early or normal completion), the EDMA3 channel controller sets the
appropriate bit in the interrupt pending registers (IPR/IPRH), as the transfer completion codes specify. If
the completion interrupts are appropriately enabled, then the CPU enters the interrupt service routine
(ISR) when the completion interrupt is asserted.
After servicing the interrupt, the ISR should clear the corresponding bit in IPR/IPRH, thereby enabling
recognition of future interrupts. The EDMA3CC will only assert additional completion interrupts when all
IPR/IPRH bits clear.
When one interrupt is serviced many other transfer completions may result in additional bits being set in
IPR/IPRH, thereby resulting in additional interrupts. Each of the bits in IPR/IPRH may need different types
of service; therefore, the ISR may check all pending interrupts and continue until all of the posted
interrupts are serviced appropriately.
Examples of pseudo code for a CPU interrupt service routine for an EDMA3CC completion interrupt are
shown in Example 2-2 and Example 2-3.
The ISR routine in Example 2-2 is more exhaustive and incurs a higher latency.
Example 2-2. Interrupt Servicing
The pseudo code:
1. Reads the interrupt pending register (IPR/IPRH).
2. Performs the operations needed.
3. Writes to the interrupt pending clear register (ICR/ICRH) to clear the corresponding IPR/IPRH bit(s).
4. Reads IPR/IPRH again:
(a) If IPR/IPRH is not equal to 0, repeat from step 2 (implies occurrence of new event between step 2 to
step 4).
(b) If IPR/IPRH is equal to 0, this should assure you that all of the enabled interrupts are inactive.
NOTE: An event may occur during step 4 while the IPR/IPRH bits are read as 0 and the application is
still in the interrupt service routine. If this happens, a new interrupt is recorded in the device
interrupt controller and a new interrupt generates as soon as the application exits in the interrupt
service routine.
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Example 2-3 is less rigorous, with less burden on the software in polling for set interrupt bits, but can
occasionally cause a race condition as mentioned above.
Example 2-3. Interrupt Servicing
If you want to leave any enabled and pending (possibly lower priority) interrupts; you must force the interrupt
logic to reassert the interrupt pulse by setting the EVAL bit in the interrupt evaluation register (IEVAL).
The pseudo code is as follows:
1. Enters ISR. (The corresponding bit (EDMA3CC_INT bit) in the DSP IFR is cleared).
2. Reads IPR/IPRH.
3. For the condition that is set in IPR/IPRH that you want to service, do the following:
(a) Service interrupt as the application requires.
(b) Clear the bit for serviced conditions (others may still be set, and other transfers may have resulted in
returning the TCC to EDMA3CC after step 2).
4. Reads IPR/IPRH prior to exiting the ISR:
(a) If IPR/IPRH is equal to 0, then exit the ISR.
(b) If IPR/IPRH is not equal to 0, then set IEVAL so that upon exit of ISR, a new interrupt triggers if any
enabled interrupts are still pending.
2.9.3 Interrupt Evaluation Operations
The EDMA3CC has interrupt evaluate registers (IEVAL) that exist in the global region and in each shadow
region. The registers in the shadow region are the only registers in the DMA channel shadow region
memory map that are not affected by the settings for the DMA region access enable registers
(DRAE/DRAEH). Writing a 1 to the EVAL bit in the registers that are associated with a particular shadow
region results in pulsing the associated region interrupt (global or shadow), if any enabled interrupt (via
IER/IERH) is still pending (IPR/IPRH). This register assures that the CPU does not miss the interrupts (or
the EDMA3 master associated with the shadow region) if the software architecture chooses not to use all
interrupts. See Example 2-3 for the use of IEVAL in the EDMA3 interrupt service routine (ISR).
Similarly an error evaluation register (EEVAL) exists in the global region. Writing a 1 to the EVAL bit in
EEVAL causes the pulsing of the error interrupt if any pending errors are in EMR/EMRH, QEMR, or
CCERR. See Section 2.9.4 for additional information regarding error interrupts.
NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the
IEVAL operated upon is from that particular shadow region memory map.
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2.9.4 Error Interrupts
The EDMA3CC error registers provide the capability to differentiate error conditions (event missed,
threshold exceed, etc.). Additionally, setting the error bits in these registers results in asserting the
EDMA3CC error interrupt. If the EDMA3CC error interrupt is enabled in the device interrupt controller(s),
then it allows the CPU(s) to handle the error conditions.
The EDMA3CC has a single error interrupt (EDMA3CC_ERRINT) that is asserted for all EDMA3CC error
conditions. There are four conditions that cause the error interrupt to pulse:
• DMA missed events: for all 64 DMA channels. DMA missed events are latched in the event missed
registers (EMR/EMRH).
• QDMA missed events: for all QDMA channels. QDMA missed events are latched in the QDMA event
missed register (QEMR).
• Threshold exceed: for all event queues. These are latched in EDMA3CC error register (CCERR).
• TCC error: for outstanding transfer requests that are expected to return completion code (TCCHEN or
TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This is also latched in the
EDMA3CC error register (CCERR).
Figure 2-16 illustrates the EDMA3CC error interrupt generation operation.
If any of the bits are set in the error registers due to any error condition, the EDMA3CC_ERRINT is always
asserted, as there are no enables for masking these error events. Similar to transfer completion interrupts
(EDMA3CC_INT), the error interrupt also only pulses when the error interrupt condition transitions from no
errors being set to at least one error being set. If additional error events are latched prior to the original
error bits clearing, the EDMA3CC does not generate additional interrupt pulses.
To reduce the burden on the software, there is an error evaluate register (EEVAL) that allows
re-evaluation of pending set error events/bits, similar to the interrupt evaluate register (IEVAL). You can
use this so that the CPU(s) does not miss any error events.
NOTE: It is good practice to enable the error interrupt in the device interrupt controller and to
associate an interrupt service routine with it to address the various error conditions
appropriately. Doing so puts less burden on the software (polling for error status);
additionally, it provides a good debug mechanism for unexpected error conditions.
Figure 2-16. Error Interrupt Operation
EMR/EMRH
63
QEMR
1
0
3
2
1
CCERR
0
16
3
2
1
0
EEVAL.EVAL
Eval/
pulse
EDMACC_ERRINT
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2.10 Memory Protection
The EDMA3 channel controller supports two kinds of memory protection: active and proxy.
2.10.1 Active Memory Protection
Active memory protection is a feature that allows or prevents read and write accesses (by any EDMA3
programmer) to the EDMA3CC registers (based on permission characteristics that you program). Active
memory protection is achieved by a set of memory protection permissions attribute (MPPA) registers.
The EMA3CC register map is divided into three categories:
• a global region
• a global channel region
• eight shadow regions
Each shadow region consists of the respective shadow region registers and the associated PaRAM. For
more detailed information regarding the contents of a shadow region, see Table 2-8.
Each of the eight shadow regions has an associated MPPA register (MPPAn) that defines the specific
requestor(s) and types of requests that are allowed to the regions resources.
The global channel region is also protected with a memory-mapped register (MPPAG). The MPPAG
applies to the global region and to the global channel region, except the other MPPA registers themselves.
For more detailed information on the list of the registers in each region, see Table 2-16.
See Section 4.2.5.4 for the bit field descriptions of MPPAn. The MPPAn have a certain set of access
rules.
Table 2-15 shows the accesses that are allowed or not allowed to the MPPAG and MPPAn.
Table 2-15. Allowed Accesses
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Access
Supervisor
User
Read
Yes
Yes
Write
Yes
No
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Table 2-16 describes the MPPA register mapping for the shadow regions (which includes shadow region
registers and PaRAM addresses).
The region-based MPPA registers are used to protect accesses to the DMA shadow regions and the
associated region PaRAM. Because there are eight regions, there are eight MPPA region registers
(MPPA[0-7]).
Table 2-16. MPPA Registers to Region Assignment
Register
Registers Protect
Address Range
PaRAM Protect
Address Range
MPPAG
Global Range
0000h-1FFCh
N/A
N/A
MPPA0
DMA Shadow 0
2000h-21FCh
1st octant
4000h-43FCh
MPPA1
DMA Shadow 1
2200h-23FCh
2nd octant
4400h-47FCh
MPPA2
DMA Shadow 2
2400h-25FCh
3rd octant
4800h-4BFCh
MPPA3
DMA Shadow 3
2600h-27FCh
4th octant
4C00h-4FFCh
MPPA4
DMA Shadow 4
2800h-29FCh
5th octant
5000h-53FCh
MPPA5
DMA Shadow 5
2A00h-2BFCh
6th octant
5400h-57FCh
MPPA6
DMA Shadow 6
2C00h-2DFCh
7th octant
5800h-5BFCh
MPPA7
DMA Shadow 7
2E00h-2FFCh
8th octant
5C00h-5FFCh
The following is an example of access denied to an EDMA3CC register.
Write access to shadow region 7's event enable set register (EESR)
1. The original value of the event enable register (EER) at address 02A0 1020h is 0.
2. The MPPA[7] is set to prevent user level accesses (UW = 0, UR = 0), but it allows supervisor level
accesses (SW = 1, SR = 1) with a privilege ID of 0. (AID0 = 1).
3. An EDMA3 programmer with a privilege ID of 0 attempts to perform a user-level write access of a
value of FF00 FF00h to shadow region 7's event enable set register (EESR) at address 02A0 2E30h.
Note that the EER is a read-only register and the only way that you can write to it is by writing to the
EESR. Also remember that there is only one physical register for EER, EESR, etc. and that the
shadow regions only provide to the same physical set.
4. Since the MPPA[7] has UW = 0, though the privilege ID of the write access is set to 0, the access is
not allowed and the EER is not written to.
Table 2-17 illustrates the example above.
Table 2-17. Example Access Denied
Register
Value
Description
EER
(02A0 1020h)
0000 0000h
Initial value in EER.
EESR
(02A0 2E30h)
FF00 FF00h
↓
Value attempted to be written to shadow region 7's EESR.
This is done by an EDMA3 programmer with a privilege level of User and Privilege
ID of 0.
MPPA[7]
(02A0 082Ch)
0000 04B0h
Memory Protection Filter AID0 = 1, UW = 0, UR = 0, SW = 1, SR = 1.
EER
(02A0 1020h)
0000 0000h
X
Access Denied
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The following is an example of access allowed to an EDMA3CC register.
Write access to shadow region 7's event enable set register (EESR)
1. The original value of the event enable register (EER) at address 02A0 1020h is 0
2. The MPPA[7] is set to allow user-level accesses (UW = 1, UR = 1) and supervisor-level accesses (SW
= 1, SR = 1) with a privilege ID of 0. (AID0 = 1)
3. An EDMA3 programmer with a privilege ID of 0, attempts to perform a user-level write of a value of
ABCD 0123h to shadow region 7's event enable set register (EESR) at address 02A0 2E30h. Note that
the EER is a read-only register and the only way that you can write to it is by writing to the EESR. Also
remember that there is only one physical register for EER, EESR, etc. and that the shadow regions
only provide to the same physical set.
4. Since the MPPA[7] has UW = 1 and AID0 = 1, the user-level write access is allowed.
5. Remember that accesses to shadow region registers are masked by their respective DRAE register. In
this example, the DRAE[7] is set of 9F00 0F00h.
6. The value finally written to EER is 9F00 0F00h.
Table 2-18 illustrates the example above.
Table 2-18. Example Access Allowed
Register
Value
0000 0000h
Initial value in EER.
EESR
(02A0 2E30h)
FF00 FF00h
Value attempted to be written to shadow region 7's EESR. This is done by an
EDMA3 programmer with a privilege level of User and Privilege ID of 0.
MPPA[7]
(02A0 082Ch)
0000 04B3h
Memory Protection Filter AID0 = 1, UW = 1, UR = 1, SW = 1, SR = 1.
✓
↓
62
Description
EER
(02A0 1020h)
Access allowed.
DRAE[7]
(02A0 0378h)
9FF0 0FC2h
↓
DMA Region Access Enable Filter
EESR
(02A 02A0 2E30h)
9F00 0F00h
↓
Value written to shadow region 7's EESR. This is done by an EDMA3 programmer
with a privilege level of User and a Privilege ID of 0.
EER
(02A0 1020h)
↓
9F00 0F00h
Final value of EER.
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2.10.2 Proxy Memory Protection
Proxy memory protection allows an EDMA3 transfer programmed by a given EDMA3 programmer to have
its permissions travel with the transfer through the EDMA3TC. The permissions travel along with the read
transactions to the source and the write transactions to the destination endpoints. The PRIV bit and
PRIVID bit in the channel options parameter (OPT) is set with the EDMA3 programmer's PRIV value and
PRIVID values, respectively, when any part of the PaRAM set is written.
The PRIV is the privilege level (i.e., user vs. supervisor). The PRIVID refers to a privilege ID with a
number that is associated with an EDMA3 programmer.
See the data manual for the PRIVIDs that are associated with potential EDMA3 programmers.
These options are part of the TR that are submitted to the transfer controller. The transfer controller uses
the above values on their respective read and write command bus so that the target endpoints can
perform memory protection checks based on these values.
For example, consider a parameter set that is programmed by a CPU in user privilege level for a simple
transfer with the source buffer on an L2 page and the destination buffer on an L1D page. The PRIV is 0
for user-level and the CPU has a PRIVID of 0.
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The PaRAM set is shown in Figure 2-17.
Figure 2-17. PaRAM Set Content for Proxied Memory Protection Example
(a) EDMA3 Parameters
Parameter Contents
0010 0007h
009F 0000h
0001h
0004h
00F0 7800h
0001h
0001h
0000h
0001h
FFFFh
1000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
30
0
0
29
PRIV Rsvd
28
27
24
00
0000
Rsvd
PRIVID
15
12
11
23
22
21
20
0
0
0
1
19
ITCCHEN TCCHEN ITCINTEN TCINTEN
10
8
7
4
0000
0
000
0000
TCC
TCCMOD
FWID
Reserved
18
17
16
00
00
Reserved
TCC
3
2
1
0
0
1
1
1
STATIC SYNCDIM DAM SAM
The PRIV and PRIVID information travels along with the read and write requests that are issued to the
source and destination memories.
For example, if the access attributes that are associated with the L2 page with the source buffer only allow
supervisor read, write accesses (SR, SW), the user-level read request above is refused. Similarly, if the
access attributes that are associated with the L1D page with the destination buffer only allow supervisor
read and write accesses (SR, SW), the user-level write request above is refused. For the transfer to
succeed, the source and destination pages should have user-read and user-write permissions,
respectively, along with allowing accesses with a PRIVID 0. For more information regarding how to set
memory protection attributes for pages of memory in L2/L1D, see the TMS320C64x/C64x+ DSP CPU and
Instruction Set Reference Guide (SPRU732).
Because the programmers privilege level and privilege identification travel with the read and write
requests, EDMA3 acts as a proxy.
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Figure 2-18 illustrates the propagation of PRIV and PRIVID at the boundaries of all the interacting entities
(CPU, EDMA3CC, EDMA3TC, and slave memories).
Figure 2-18. Proxied Memory Protection Example
Memory
Protection
Attribute
Read req
PRIVID=0,
PRIV=0
EDMA3CC
PaRAM
EDMA3TC0
AID0=1
UR=1
L2 Page
9F 0000h
Src Buffer
PRIVID=0
User write
CPU
from user
Privilege level
PaRAM
entry 5
PRIVID=0,
PRIV=0
TR
Read
Access allowed
Submission
Write
PRIVID = 0,
PRIV = 0
Access
allowed
L1D Page
F0 7800h
AID0=1
UW=1
Dst Buffer
Memory
Protection
Attribute
2.11 Event Queue(s)
Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the
event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC.
Each queue is 16 entries deep; thus, each event queue can queue a maximum of 16 events. If there are
more than 16 events, then the events that cannot find a place in the event queue remain set in the
associated event register and the CPU does not stall.
There are four event queues (Queue0, Queue1, Queue2, and Queue3) for TCI6482/86/C6472 devices.
Events in Queue0 result in submission of its associated transfer requests (TRs) to TC0. Similarly, transfer
requests that are associated with events in Queue3 are submitted to TC3.There are six event queues
(Queue0, Queue1, Queue2, Queue3, Queue 4 and Queue5) for TMS320TCI6487/8 devices. Events in
Queue0 result in submission of its associated transfer requests (TRs) to TC0. Similarly, transfer requests
associated with events in Queue5 are submitted to TC5.
An event that wins prioritization against other DMA and/or QDMA pending events is placed at the tail of
the appropriate event queue. Each event queue is serviced in FIFO order. Once the event reaches the
head of its queue and the corresponding transfer controller is ready to receive another TR, the event is
de-queued and the PaRAM set corresponding to the de-queued event is processed and submitted as a
transfer request packet (TRP) to the associated EDMA3 transfer controller.
Queue0 has highest priority and Queue3 has the lowest priority, if Queue0 and Queue1 both have at least
one event entry and if both TC0 and TC1 can accept transfer requests, then the event in Queue0 is
de-queued first and its associated PaRAM set is processed and submitted as a transfer request (TR) to
TC0.
See Section 2.11.4 for system-level performance considerations. All of the event entries in all of the event
queues are software readable (not writeable) by accessing the event entry registers (Q0E0,
Q0E1,…Q1E15, etc.). Each event entry register characterizes the queued event in terms of the type of
event (manual, event, chained or auto-triggered) and the event number. See Section 4.2.4.1 for a
description of the bit fields in the queue event entry registers.
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2.11.1 DMA/QDMA Channel to Event Queue Mapping
Each of the 64 DMA channels and four QDMA channels are programmed independently to map to a
specific queue, using the DMA queue number register (DMAQNUM) and the QDMA queue number
register (QDMANUM). The mapping of DMA/QDMA channels is critical to achieving the desired
performance level for the EDMA and most importantly, in meeting real-time deadlines. See Section 2.11.4.
NOTE: If an event is ready to be queued and both the event queue and the EDMA3 transfer
controller that is associated to the event queue are empty, then the event bypasses the
event queue, and moves the PaRAM processing logic, and eventually to the transfer request
submission logic for submission to the EDMA3TC. In this case, the event is not logged in the
event queue status registers.
2.11.2 Queue RAM Debug Visibility
There are four event queues and each queue has 16 entries. These 16 entries are managed in a circular
FIFO manner. There is a queue status register (QSTAT) associated with each queue. These along with all
of the 16 entries per queue can be read via registers QSTATn and QxEy, respectively.
These registers provide user visibility and may be helpful while debugging real-time issues (typically
post-mortem), involving multiple events and event sources.
Each of the 16 entries in the event queue are read using the EDMA3CC memory-mapped register. By
reading the event queue, you see the history of the last 16 TRs that have been processed by the EDMA3
on a given queue. This provides user/software visibility and is helpful for debugging real-time issues
(typically post-mortem), involving multiple events and event sources.
The event queue entry register (QxEx) uniquely identifies the specific event type (event-triggered,
manually-triggered, chain-triggered, and QDMA events) along with the event number (for all DMA/QDMA
event channels) that are in the queue or have been de-queued (passed through the queue).
The queue status register (QSTATn) includes fields for the start pointer (STRTPTR) which provides the
offset to the head entry of an event. It also includes a field called NUMVAL that provides the total number
of valid entries residing in the event queue at a given instance of time. The STRTPTR may be used to
index appropriately into the 16 event entries. NUMVAL number of entries starting from STRTPTR are
indicative of events still queued in the respective queue. The remaining entry may be read to determine
what's already de-queued and submitted to the associated transfer controller.
2.11.3 Queue Resource Tracking
The EDMA3CC event queue includes watermarking/threshold logic that allows you to keep track of
maximum usage of all event queues. This is useful for debugging real-time deadline violations that may
result from head-of-line blocking on a given EDMA3 event queue.
You can program the maximum number of events that can queue up in an event queue by programming
the threshold value (between 0 to 15) in the queue watermark threshold A register (QWMTHRA). The
maximum queue usage is recorded actively in the watermark (WM) field of the queue status register
(QSTATn) that keeps getting updated based on a comparison of number of valid entries, which is also
visible in the NUMVAL bit in QSTATn and the maximum number of entries (WM bit in QSTATn).
If the queue usage is exceeded, this status is visible in the EDMA3CC registers: the QTHRXCDn bit in the
channel controller error register (CCERR) and the THRXCD bit in QSTATn, where n stands for the event
queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt.
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2.11.4 Performance Considerations
The main switched central resource (SCR) (see the device-specific data manual) arbitrates bus requests
from all of the masters (CPU, EMAC, RapidIO, UHPI, and RAC) to the shared slave resources
(peripherals and memories).
The priorities of transfer requests (read and write commands) from the EDMA3 transfer controllers with
respect to other masters within the system crossbar are programmed using the queue priority register
(QUEPRI). QUEPRI programs the priority of the event queues (or indirectly, TC0-TC3 for
TCI6482/86/C6472; TC0-TC5 for TCI6487/88, because QueueN transfer requests are submitted to TCN).
Therefore, the priority of unloading queues has a secondary affect compared to the priority of the transfers
as they are executed by the EDMA3TC (dictated by the priority set using QUEPRI).
2.12 EDMA3 Transfer Controller (EDMA3TC)
The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller
(EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR)
to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR; thus, the EDMA3TC
is a slave to the EDMA3CC.
2.12.1 Architecture Details
2.12.1.1 Command Fragmentation
The TC read and write controllers in conjunction with the source and destination register sets are
responsible for issuing optimally-sized reads and writes to the slave endpoints. An optimally-sized
command is defined by the transfer controller default burst size (DBS). See Section 2.12.5 for DBS value
of each EDMA3TC.
The EDMA3TC attempts to issue the largest possible command size as limited by the DBS value or the
ACNT/BCNT value of the TR. EDMA3TC obeys the following rules:
• The read/write controllers always issue commands less than or equal to the DBS tie-off value.
• The first command of a 1D transfer command always aligns to the DBS tie-off value for subsequent
commands.
Example 2-4 shows command fragmentation for DBS of 64 bytes. In summary, if the ACNT value is larger
than the DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the
source/destination addresses. Each BCNT number of arrays are then serviced in succession.
For BCNT arrays of ACNT bytes (that is, a 2D transfer), if the ACNT value is less than or equal to the
DBS value, then the TR may be optimized into a 1D-transfer in order to maximize efficiency. The
optimization takes place if the EDMA3TC recognizes that the 2D-transfer is organized as a single
dimension (ACNT == BIDX) and the ACNT value is a power of 2. Table 2-19 summarizes conditions in
which the optimizations are performed.
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Example 2-4. Command Fragmentation (DBS = 64)
The pseudo code:
1. ACNT = 8, BCNT = 8, SRCBIDX = 8, DSTBIDX = 10, SRCADDR = 64, DSTADDR = 191
Read Controller: This is optimized from a 2D-transfer to a 1D-transfer such that the read side is equivalent
to ACNT = 64, BCNT = 1.
Cmd0 = 64 byte
Write Controller: Because DSTBIDX != ACNT, it is not optimized.
Cmd0 = 8 byte, Cmd1 = 8 byte, Cmd2 = 8 byte, Cmd3 = 8 byte, Cmd4 = 8 byte, Cmd5 = 8 byte, Cmd6 = 8
byte, Cmd7 = 8 byte.
2. ACNT=128, BCNT = 1,SRCADDR = 63, DSTADDR = 513
Read Controller: Read address is not aligned.
Cmd0 = 1 byte, (now the SRCADDR is aligned to 64 for the next command)
Cmd1 = 64 bytes
Cmd2 = 63 bytes
Write Controller: The write address is also not aligned.
Cmd0 = 63 bytes, (now the DSTADDR is aligned to 64 for the next command)
Cmd1 = 64 bytes
Cmd2 = 1 byte
Table 2-19. Read/Write Command Optimization Rules
ACNT ≤ DBS
ACNT is power of 2
BIDX = ACNT
BCNT ≤ 1023
SAM/DAM =
Increment
Yes
Yes
Yes
Yes
Yes
No
x
x
x
x
Not Optimized
x
No
x
x
x
Not Optimized
x
x
No
x
x
Not Optimized
x
x
x
No
x
Not Optimized
x
x
x
x
No
Not Optimized
Description
Optimized
2.12.1.2 TR Pipelining
TR pipelining refers to the ability of the source active set to proceed ahead of the destination active set.
Essentially, the reads for a given TR may already be in progress while the writes of a previous TR may
not have completed.
The number of outstanding TRs is limited by the number of destination FIFO register entries.
TR pipelining is useful for maintaining throughput on back-to-back small TRs. It minimizes the startup
overhead because reads start in the background of a previous TR writes.
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2.12.1.3 Performance Tuning
By default, reads are as issued as fast as possible. In some cases, the reads issued by the EDMA3TC
could fill the available command buffering for a slave, delaying other (potentially higher priority) masters
from successfully submitting commands to that slave. The rate at which read commands are issued by the
EDMA3TC is controlled by the RDRATE register. The RDRATE register defines the number of cycles that
the EDMA3TC read controller waits before issuing subsequent commands for a given TR, thus minimizing
the chance of the EDMA3TC consuming all available slave resources. The RDRATE value should be set
to a relatively small value if the transfer controller is targeted for high priority transfers and to a higher
value if the transfer controller is targeted for low priority transfers.
In contrast, the Write Interface does not have any performance turning knobs because writes always have
an interval between commands as write commands are submitted along with the associated write data.
2.12.2 Memory Protection
The transfer controller plays an important role in handling proxy memory protection. There are two access
properties associated with a transfer: for instance, the privilege id (system-wide identification assigned to a
master) of the master initiating the transfer, and the privilege level (user versus supervisor) used to
program the transfer. This information is maintained in the PaRAM set when it is programmed in the
channel controller. When a TR is submitted to the transfer controller, this information is made available to
the EDMA3TC and used by the EDMA3TC while issuing read and write commands. The read or write
commands have the same privilege identification, and privilege level as that programmed in the EDMA3
transfer in the channel controller.
2.12.3 Error Generation
Errors are generated if enabled under three conditions:
• EDMA3TC detection of an error signaled by the source or destination address.
• Attempt to read or write to an invalid address in the configuration memory map.
• Detection of a constant addressing mode TR violating the constant addressing mode transfer rules (the
source/destination addresses and source/destination indexes must be aligned to 32 bytes).
Either or all error types may be disabled. If an error bit is set and enabled, the error interrupt for the
concerned transfer controller is pulsed.
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2.12.4 Debug Features
The DMA program register set, DMA source active register set, and the destination FIFO register set are
used to derive a brief history of TRs serviced through the transfer controller.
Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing
activity within different parts of the transfer controller:
• The SRCACTV bit indicates whether the source active set is active.
• The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given
instance.
• The PROGBUSY bit indicates whether a valid TR is present in the DMA program set.
If the TRs are in progression, caution must be used and you must realize that there is a chance that the
values read from the EDMA3TC status registers will be inconsistent since the EDMA3TC may change the
values of these registers due to ongoing activities.
It is recommended that you ensure no additional submission of TRs to the EDMA3TC in order to facilitate
ease of debug.
2.12.4.1 Destination FIFO Register Pointer
The destination FIFO register pointer is implemented as a circular buffer with the start pointer being
DFSTRTPTR and a buffer depth of usually 2 or 4. The EDMA3TC maintains two important status details in
TCSTAT that may be used during advanced debugging, if necessary. The DFSTRTPTR is a start pointer,
that is, the index to the head of the destination FIFO register. The DSTACTV is a counter for the number
of valid (occupied) entries. These registers may be used to get a brief history of transfers.
Examples of some register field values and their interpretation:
• DFSTRTPTR = 0 and DSTACTV = 0 implies that no TRs are stored in the destination FIFO register.
• DFSTRTPTR = 1 and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 1 and the second pending TR is read from the destination
FIFO register entry 2.
• DFSTRTPTR = 3h and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 3 and the second pending TR is read from the destination
FIFO register entry 0.
2.12.5 EDMA3TC Configuration
Table 2-20and Table 2-21 provides the configuration of the individual EDMA3 transfer controllers present
on the device.
Table 2-20. EDMA3 Transfer Controller Configurations for TCI6482/86/C6472 Devices
Name
TC0
TC1
TC2
TC3
FIFOSIZE
128 bytes
128 bytes
256 bytes
256 bytes
BUSWIDTH
16 bytes
16 bytes
16 bytes
16 bytes
DSTREGDEPTH
2 entries
4 entries
4 entries
4 entries
DBS
64 bytes
64 bytes
64 bytes
64 bytes
Table 2-21. EDMA3 Transfer Controller Configurations for TCI6487/88 Devices
Name
70
TC0
TC1
TC2
TC3
TC4
TC5
FIFOSIZE
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
BUSWIDTH
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
DSTREGDEPTH
4 entries
4 entries
4 entries
4 entries
4 entries
4 entries
DBS
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
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2.13 Event Dataflow
This section summarizes the data flow of a single event, from the time the event is latched to the channel
controller to the time the transfer completion code is returned. The following steps list the sequence of
EDMA3CC activity:
1. Event is asserted from an external source (peripheral or external interrupt). This also is similar for a
manually-triggered, chained-triggered, or QDMA-triggered event. The event is latched into the
ER.En/ERH.En (or CER.En/CERH.En, ESR.En /ESRH.En, QER.En) bit.
2. Once an event is prioritized and queued into the appropriate event queue, the SER.En/SERH.En (or
QSER.En) bit is set to inform the event prioritization/processing logic to disregard this event since it is
already in the queue. Alternatively, if the transfer controller and the event queue are empty, then the
event bypasses the queue.
3. The EDMA3CC processing and the submission logic evaluates the appropriate PaRAM set and
determines whether it is a non-null and non-dummy transfer request (TR).
4. The EDMA3CC clears the ER.En/ERH.En (or CER.En/CERH.En, ESR.En/ESRH.En, QER.En) bit and
the SER.En/SERH.En bit as soon as it determines the TR is non-null. In the case of a null set, the
SER.En/SERH.En bit remains set. It submits the non-null/non-dummy TR to the associated transfer
controller. If the TR was programmed for early completion, the EDMA3CC immediately sets the
interrupt pending register (IPR.I[TCC]/IPRH.I[TCC]-32).
5. If the TR was programmed for normal completion, the EDMA3CC sets the interrupt pending register
(IPR.I[TCC]/IPRH.I[TCC]) when the EDMA3TC informs the EDMA3CC about completion of the transfer
(returns transfer completion codes).
6. The EDMA3CC programs the associated EDMA3TCn's Program Register Set with the TR.
7. The TR is then passed to the Source Active set and the Dst FIFO Register Set, if both the register sets
are available.
8. The Read Controller processes the TR by issuing read commands to the source slave endpoint. The
Read Data lands in the Data FIFO of the EDMA3TCn.
9. As soon as sufficient data is available, the Write Controller begins processing the TR by issuing write
commands to the destination slave endpoint.
10. This continues until the TR completes and the EDMA3TCn then signals completion status to the
EDMA3CC.
2.14 EDMA3 Prioritization
The EDMA3 controller has many implementation rules to deal with concurrent events/channels, transfers,
etc. The following subsections detail various arbitration details whenever there might be occurrence of
concurrent activity. Figure 2-19 shows the different places EDMA3 priorities come into play.
2.14.1 Channel Priority
The DMA event registers (ER and ERH) capture up to 64 events; likewise, the QDMA event register
(QER) captures QDMA events for all QDMA channels; therefore, it is possible for events to occur
simultaneously on the DMA/QDMA event inputs. For events arriving simultaneously, the event associated
with the lowest channel number is prioritized for submission to the event queues (for DMA events, channel
0 has the highest priority and channel 63 has the lowest priority; similarly, for QDMA events, channel 0
has the highest priority and channel 3 (TCI6482/86/C6472) or 7 (TCI6487/88) has the lowest priority). This
mechanism only sorts simultaneous events for submission to the event queues.
If a DMA and QDMA event occurs simultaneously, the DMA event always has prioritization against the
QDMA event for submission to the event queues.
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2.14.2 Trigger Source Priority
If a DMA channel is associated with more than one trigger source (event trigger, manual trigger, and chain
trigger), and if multiple events are set simultaneously for the same channel (ER.En = 1, ESR.En = 1 ,
CER.En = 1) , then the EDMA3CC always services these events in the following priority order: event
trigger (via ER) is higher priority than chain trigger (via CER) and chain trigger is higher priority than
manual trigger (via ESR).
This implies that if for channel 0, both ER.E0 = 1 and CER.E0 = 1 at the same time, then the ER.E0 event
is always queued before the CER.E0 event.
2.14.3 Dequeue Priority
The priority of the associated transfer request (TR) is further mitigated by which event queue is being used
for event submission (dictated by DMAQNUM and QDMAQNUM). For submission of a TR to the transfer
request, events need to be de-queued from the event queues. Queue 0 has the highest dequeue priority
and queue 3 the lowest.
2.14.4
System (Transfer Controller) Priority
Every transfer controller has a programmed system priority (programmed via QUEPRI) that is
implemented when multiple masters in the system are vying for the same endpoint. The priority of the
associated transfer request (TR) is further mitigated by the system priority setting of the transfer controller.
This priority comes into play at the SCR when several masters are submitting requests to the main SCR.
The default priority for all TCs is the same (0 or highest priority to other masters). If an application requires
the EDMA3 to service both real-time (urgent) and non-real-time transfers, it is recommended that this
priority be changed.
2.15 Reset Considerations
A hardware reset resets the EDMA3 (EDMA3CC and EDMA3TC) and the EDMA3 configuration registers.
The PaRAM memory contents are undefined after device reset and you should not rely on parameters to
be reset to a known state. The PaRAM entry must be initialized to a desired value before it is used.
2.16 Emulation Considerations
During debug when using the emulator, the CPU(s) may be halted on an execute packet boundary for
single-stepping, benchmarking, profiling, or other debug purposes. During an emulation halt, the EDMA3
channel controller and transfer controller operations continue. Events continue to be latched and
processed and transfer requests continue to be submitted and serviced.
Since EDMA3 is involved in servicing multiple master and slave peripherals, it is not feasible to have an
independent behavior of the EDMA3 for emulation halts. EDMA3 functionality would be coupled with the
peripherals it is servicing, which might have different behavior during emulation halts. For example, if a
McBSP is halted during an emulation access (FREE = 0 and SOFT = 0 or 1 in McBSP registers), the
McBSP stops generating the McBSP receive or transmit events (REVT or XEVT) to the EDMA. From the
point of view of the McBSP, the EDMA3 is suspended, but other peripherals (for example, a timer) still
assert events and will be serviced by the EDMA.
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Figure 2-19. EDMA3 Prioritization for TCI6482/86/C6472 Devices
Trigger source priority
64
15
Q0
0
TC0
15
15
Q2
0
15
64
Parameter
entry 254
Q3
TC3
Parameter
entry 255
QDMA
event
register
(QER)
4
Queue bypass
EDMA3
channel
controller
QDMA trigger
To chained event register (CER/CERH)
Completion
detection
Early completion
Chained
event
register
(CER/CERH)
4:1 priority encoder
Chain
trigger
Event
64
set
register
(ESR/ESRH)
Parameter
entry 0
Parameter
entry 1
Q1
0
Manual
trigger
PaRAM
Dequeue
priority
SCR
Event
enable
register
(EER/EERH)
0
64:1 priority encoder
Event
trigger
Event
register
(ER/ERH)
Event queues
Transfer request process submit
Channel
priority
Channel mapping
From peripherals/external events
E63
E1 E0
System
priority
From
EDMA3TC0
Completion
interface
Memory
protection
EDMA3CC_
MPINT
74
Read/
write to/
from EDMA3
programmer
EDMA3 Architecture
Error
detection
EDMA3CC_
ERRINT
Completion
interrupt
From
EDMA3TC3
EDMA3CC_INT[0:7]
EDMA3CC_GINT
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Figure 2-20. EDMA3 Prioritization for TCI6487/88 Devices
8
SRC
Transfer request process submit
Channel mapping
Parameter
entry 254
15
0
TC5
Parameter
entry 255
15
0
EDMA3
channel
controller
QDMA trigger
15
Early completion
64
Chained
event
register
(CER/CERH)
QDMA
event
register
(QER)
Queue 0
Queue 1
Event
64
set
register
(ESR/ESRH)
15
0
TC0
Queue 2
Chain
trigger
64
PaRAM
Parameter
entry 0
Parameter
entry 1
Queue 3
Manual
trigger
Event
enable
register
(EER/EERH)
Channel priority
Channel Event queues
priority
0
Dequeue
priority
8:1 priority encoder
Event
trigger
Event
register
(ER/ERH)
Trigger source priority
64:1 priority encoder
From peripherals/external events
E63 E1 E0
System
priority
Queue 4
0
Queue 5
15
0
15
Queue bypass
To chained event register (CER/CERH)
From
EDMA3TC0
Completion
detection
Completion
interface
Memory
protection
EDMA3CC_
MPINT
Read/
write to/
from EDMA3
programmer
Error
detection
EDMA3CC_
ERRINT
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Completion
interrupt
From
EDMA3TC5
EDMA3CC_INT[0:7]
EDMA3CC_INTG
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Chapter 3
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EDMA3 Transfer Examples
This chapter contains examples and common usage scenarios.
Topic
3.1
3.2
3.3
3.4
...........................................................................................................................
Block Move Example .........................................................................................
Subframe Extraction Example .............................................................................
Data Sorting Example ........................................................................................
Peripheral Servicing Example .............................................................................
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80
82
84
77
Block Move Example
3.1
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Block Move Example
The most basic transfer performed by the EDMA3 is a block move. During device operation it is often
necessary to transfer a block of data from one location to another, usually between on-chip and off-chip
memory.
In this example, a section of data is to be copied from external memory to internal L2 SRAM. A data block
of 256 words residing at address 8000 0000h (external memory ) needs to be transferred to internal
address 0080 0000h (L2), as shown in Figure 3-1. Figure 3-2 shows the parameters for this transfer.
The source address for the transfer is set to the start of the data block in external memory, and the
destination address is set to the start of the data block in L2. If the data block is less than 64K bytes, the
PaRAM configuration shown in Figure 3-2 holds true with the synchronization type set to A-synchronized
and indexes cleared to 0. If the amount of data is greater than 64K bytes, BCNT and the B-indexes need
to be set appropriately with the synchronization type set to AB-synchronized. The STATIC bit in OPT is set
to prevent linking.
This transfer example may also be set up using QDMA. For successive transfer submissions, of a similar
nature, the number of cycles used to submit the transfer are fewer depending on the number of changing
transfer parameters. You may program the QDMA trigger word to be the highest numbered offset in the
PaRAM set that undergoes change.
Figure 3-1. Block Move Example
8000 0000h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
...
...
...
... 244 245 246 247 248
249 250 251 252 253 254 255 256
78
EDMA3 Transfer Examples
0080 0000h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
...
...
...
... 244 245 246 247 248
249 250 251 252 253 254 255 256
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Figure 3-2. Block Move Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
0010 0008h
8000 0000h
0001h
0100h
0080 0000h
0000h
0000h
0000h
0000h
FFFFh
0000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
0000
1
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Subframe Extraction Example
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Subframe Extraction Example
The EDMA3 can efficiently extract a small frame of data from a larger frame of data. By performing a
2D-to-1D transfer, the EDMA3 retrieves a portion of data for the CPU to process. In this example, a
640 × 480-pixel frame of video data is stored in external memory, CE2. Each pixel is represented by a
16-bit halfword. The CPU extracts a 16 × 12-pixel subframe of the image for processing. To facilitate more
efficient processing time by the CPU, the EDMA3 places the subframe in internal L2 SRAM. Figure 3-3
shows the transfer of a subframe from external memory to L2. Figure 3-4 shows the parameters for this
transfer.
The same PaRAM entry options are used for QDMA channels, as well as DMA channels. The STATIC bit
in OPT is set to prevent linking. For successive transfers, only changed parameters need to be
programmed before triggering the channel.
Figure 3-3. Subframe Extraction Example
A000 0000h
0
80 0000h
A000 0788h
0_1 0_2 0_3 0_4 0_5 0_6 0_7 0_8 0_9 0_A 0_B 0_C 0_D 0_E 0_F 0_10
1_1 1_2 1_3 1_4 1_5 1_6 1_7 1_8 1_9 1_A 1_B 1_C 1_D 1_E 1_F 1_10
2_1 2_2 2_3 2_4 2_5 2_6 2_7 2_8 2_9 2_A 2_B 2_C 2_D 2_E 2_F 2_10
3_1 3_2 3_3 3_4 3_5 3_6 3_7 3_8 3_9 3_A 3_B 3_C 3_D 3_E 3_F 3_10
4_1 4_2 4_3 4_4 4_5 4_6 4_7 4_8 4_9 4_A 4_B 4_C 4_D 4_E 4_F 4_10
5_1 5_2 5_3 5_4 5_5 5_6 5_7 5_8 5_9 5_A 5_B 5_C 5_D 5_E 5_F 5_10
6_1 6_2 6_3 6_4 6_5 6_6 6_7 6_8 6_9 6_A 6_B 6_C 6_D 6_E 6_F 6_10
7_1 7_2 7_3 7_4 7_5 7_6 7_7 7_8 7_9 7_A 7_B 7_C 7_D 7_E 7_F 7_10
8_1 8_2 8_3 8_4 8_5 8_6 8_7 8_8 8_9 8_A 8_B 8_C 8_D 8_E 8_F 8_10
9_1 9_2 9_3 9_4 9_5 9_6 9_7 9_8 9_9 9_A 9_B 9_C 9_D 9_E 9_F 9_10
A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_A A_B A_C A_D A_E A_F A_10
B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_A B_B B_C B_D B_E B_F B_10
A002 5580h
479
0
80
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Figure 3-4. Subframe Extraction Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
0010 000Ch
A000 0788h
000Ch
0020h
0080 0000h
0020h
0500h
0000h
0000h
FFFFh
0000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
0000
1
1
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Data Sorting Example
Many applications require the use of multiple data arrays; it is often desirable to have the arrays arranged
such that the first elements of each array are adjacent, the second elements are adjacent, and so on.
Often this is not how the data is presented to the device. Either data is transferred via a peripheral with
the data arrays arriving one after the other or the arrays are located in memory with each array occupying
a portion of contiguous memory spaces. For these instances, the EDMA3 can reorganize the data into the
desired format. Figure 3-5 shows the data sorting.
To
•
•
•
•
•
•
•
determine the parameter set values, the following need to be considered:
ACNT - Program this to be the size in bytes of an element.
BCNT - Program this to be the number of elements in a frame.
CCNT - Program this to be the number of frames.
SRCBIDX - Program this to be the size of the element or ACNT.
DSTBIDX - CCNT × ACNT
SRCCDX - ACNT × BCNT
DSTCIDX - ACNT
The synchronization type needs to be AB-synchronized and the STATIC bit is 0 to allow updates to the
parameter set. It is advised to use normal EDMA3 channels for sorting.
It is not possible to sort this with a single trigger event. Instead, the channel can be programmed to be
chained to itself. After BCNT elements get sorted, intermediate chaining could be used to trigger the
channel again causing the transfer of the next BCNT elements and so on. Figure 3-6 shows the parameter
set programming for this transfer, assuming channel 0 and an element size of 4 bytes.
Figure 3-5. Data Sorting Example
A000 0000h
A_1
A_2
A_3
...
...
A_1022 A_1023 A_1024
A_1
B_1
C_1
D_1
B_1
B_2
B_3
...
...
B_1022 B_1023 B_1024
A_2
B_2
C_2
D_2
C_1
C_2
C_3
...
...
C_1022 C_1023 C_1024
A_3
B_3
C_3
D_3
D_1
D_2
D_3
...
...
D_1022 D_1023 D_1024
...
...
...
...
...
...
...
...
80 0000h
A_1022 B_1022 C_1022 D_1022
A_1023 B_1023 C_1023 D_1023
A_1024 B_1024 C_1024 D_1024
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Figure 3-6. Data Sorting Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
0090 0004h
A000 0000h
0400h
0004h
0080 0000h
0010h
0001h
0000h
0001h
FFFFh
1000h
0000h
0004h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
1
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
0000
0
1
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Peripheral Servicing Example
The EDMA3 channel controller also services peripherals in the background of CPU operation, without
requiring any CPU intervention. Through proper initialization of the EDMA3 channels, they can be
configured to continuously service on-chip and off-chip peripherals throughout the device operation. Each
event available to the EDMA3 has its own dedicated channel, and all channels operate simultaneously.
The only requirements are to use the proper channel for a particular transfer and to enable the channel
event in the event enable register (EER). When programming an EDMA3 channel to service a peripheral,
it is necessary to know how data is to be presented to the DSP. Data is always provided with some kind of
synchronization event as either one element per event (non-bursting) or multiple elements per event
(bursting).
3.4.1 Nonbursting Peripherals
Nonbursting peripherals include the on-chip multichannel buffered serial port (McBSP) and many external
devices, such as codecs. Regardless of the peripheral, the EDMA3 channel configuration is the same.
The on-chip McBSP is the most-commonly used peripheral in a C6000 DSP system.
The McBSP transmit and receive data streams are treated independently by the EDMA3. The transmit
and receive data streams can have completely different counts, data sizes, and formats. Figure 3-7 shows
servicing incoming McBSP data.
To transfer the incoming data stream to its proper location in L2 memory, the EDMA3 channel must be set
up for a 1D-to-1D transfer with A-synchronization. Because an event (REVT0) is generated for every word
as it arrives, it is necessary to have the EDMA3 issue the transfer request for each element individually.
Figure 3-8 shows the parameters for this transfer. The source address of the EDMA3 channel is set to the
data receive register (DRR) address for McBSP0, and the destination address is set to the start of the
data block in L2. Because the address of DRR is fixed, the source B index is cleared to 0 (no modification)
and the destination B index is set to 01b (increment).
Based on the premise that serial data is typically a high priority, the EDMA3 channel should be
programmed to be on queue 0.
Figure 3-7. Servicing Incoming McBSP Data Example
:
3
:
2
:
1
80 0000h
REVT0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
...
...
...
...
244
245
246
247
248
250
251
252
253
254
255
256
3000 0000h
RSR
RBR
DRR
249
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Figure 3-8. Servicing Incoming McBSP Data Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
0010 0000h
3000 0000h
0100h
0001h
0080 0000h
0001h
0000h
0000h
0000h
FFFFh
0000h
0000h
0004h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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3.4.2 Bursting Peripherals
Higher bandwidth applications require that multiple data elements be presented to the DSP for every
synchronization event. This frame of data can either be from multiple sources that are working
simultaneously or from a single high-throughput peripheral that streams data to/from the DSP.
In this example, a port is receiving a video frame from a camera and presenting it to the DSP one array at
a time. The video image is 640 × 480 pixels, with each pixel represented by a 16-bit element. The image
is to be stored in external memory. Figure 3-9 shows this example.
To transfer data from an external peripheral to an external buffer one array at a time based on EVTn ,
channel n must be configured. Due to the nature of the data (a video frame made up of arrays of pixels)
the destination is essentially a 2D entity. Figure 3-10 shows the parameters to service the incoming data
with a 1D-to-2D transfer using AB-synchronization. The source address is set to the location of the video
framer peripheral, and the destination address is set to the start of the data buffer. Because the input
address is static, the SRCBIDX is 0 (no modification to the source address). The destination is made up of
arrays of contiguous, linear elements; therefore, the DSTBIDX is set to pixel size, 2 bytes. ANCT is equal
to the pixel size, 2 bytes. BCNT is set to the number of pixels in an array, 640. CCNT is equal to the total
number of arrays in the block, 480. SRCCIDX is 0 because the source address undergoes no increment.
The DSTCIDX is equal to the difference between the starting addresses of each array. Because a pixel is
16 bits (2 bytes), DSTCIDX is equal to 640 × 2.
Figure 3-9. Servicing Peripheral Burst Example
EVTx
...1_2..1_1..0_2..0_1
86
External
peripheral
EDMA3 Transfer Examples
A000 0000h
0_1
0_2
0_3
A000 0500h
1_1
1_2
...
A000 0A00h
2_1
...
...
...
...
...
A009 5100h
477_1
...
A009 5600h
478_1
478_2
...
A009 5B00h
479_1
479_2
479_3
...
...
0_638
0_639
0_640
...
1_639
1_640
...
2_640
...
...
...
...
...
...
477_640
478_639 478_640
479_638 479_639 479_640
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Figure 3-10. Servicing Peripheral Burst Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
0010 0004h
Channel Source Address
0280h
0002h
E000 0000h
0002h
0000h
0000h
0500h
FFFFh
0000h
0000h
01E0h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
0000
0
1
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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3.4.3 Continuous Operation
Configuring an EDMA3 channel to receive a single frame of data is useful, and is applicable to some
systems. A majority of the time, however, data is going to be continuously transmitted and received
throughout the entire operation of the DSP. In this case, it is necessary to implement some form of linking
such that the EDMA3 channels continuously reload the necessary parameter sets. In this example,
McBSP0 is configured to transmit and receive data on a T1 array. To simplify the example, only two
channels are active for both transmit and receive data streams. Each channel receives packets of
128 elements. The packets are transferred from the serial port to L2 memory and from L2 memory to the
serial port, as shown Figure 3-11.
The McBSP generates REVT0 for every element received and generates XEVT0 for every element
transmitted. To service the data streams, EDMA3 channels 12 and 13 must be set up for 1D-to-1D
transfers with A-synchronization.
Figure 3-12 shows the parameter entries for the channel for these transfers. To service the McBSP
continuously throughout DSP operation, the channels must be linked to a duplicate PaRAM set in the
PaRAM. After all frames have been transferred, the EDMA3 channels reload and continue. Figure 3-13
shows the reload parameters for the channel.
3.4.3.1
Receive Channel
EDMA3 channel 13 services the incoming data stream of McBSP0. The source address is set to that of
the data receiver register (DRR), and the destination address is set to the first element of the data block.
Because there are two data channels being serviced, A and B, they are to be located separately within the
L2 SRAM.
To facilitate continuous operation, a copy of the PaRAM set for the channel is placed in PaRAM set 64.
The LINK option is set and the link address is provided in the PaRAM set. Upon exhausting the channel
13 parameter set, the parameters located at the link address are loaded into the channel 13 parameter set
and operation continues. This function continues throughout device operation until halted by the CPU.
3.4.3.2
Transmit Channel
EDMA3 channel 12 services the outgoing data stream of McBSP0. In this case the destination address
needs no update, hence, the parameter set changes accordingly. Linking is also used to allow continuous
operation by the EDMA3 channel, with duplicate PaRAM set entries at PaRAM set 65.
Figure 3-11. Servicing Continuous McBSP Data Example
80 0000h
REVT0
..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1
RSR
RBR
3000 0000h
A2i
A4i
A9i
A10i A11i A12i A13i
B1i
B2i
B9i
B10i B11i B12i B13i
XEVT0
80 1000h
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5
3000 0004h
B3i
B4i
B5i
...
...
B6i
B7i
...
...
A8i
B8i
...
...
DXR
B1o B2o B3o B4o B5o B6o B7o B8o
B9o B10o B11o B12o B13o
EDMA3 Transfer Examples
A7i
A1o A2o A3o A4o A5o A6o A7o A8o
A9o A10o A11o A12o A13o
80 1080h
88
A6i
DRR
80 0080h
XSR
A3i
A5i
A1i
...
...
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Figure 3-12. Servicing Continuous McBSP Data Example PaRAM Configuration
(a) EDMA Parameters for Receive Channel (PaRAM Set 13) being Linked to PaRAM Set 64
Parameter Contents
0010 0000h
3000 0000h
0080h
0001h
0080 0000h
0001h
0000h
0080h
0000h
4800h
0000h
0000h
FFFFh
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content for Receive Channel (PaRAM Set 13)
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
7
0000
4
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
(c) EDMA Parameters for Transmit Channel (PaRAM Set 12) being Linked to PaRAM Set 65
Parameter Contents
0010 1000h
0080 1000h
0080h
0001h
3000 0004h
0000h
0001h
0080h
0000h
4820h
0000h
0000h
FFFFh
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 12)
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
0001
0
000
0000
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
Figure 3-13. Servicing Continuous McBSP Data Example Reload PaRAM Configuration
(a) EDMA Reload Parameters (PaRAM Set 64) for Receive Channel
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Parameter Contents
0010 0000h
3000 0000h
0080h
0001h
0080 0000h
0001h
0000h
0080h
0000h
4800h
0000h
0000h
FFFFh
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content for Receive Channel (PaRAM Set 64)
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
0000
12
11
0
10
000
8
7
0000
4
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
(c) EDMA Reload Parameters (PaRAM Set 65) for Transmit Channel
Parameter Contents
0010 1000h
0080 1000h
0080h
0001h
3000 0004h
0000h
0001h
0080h
0000h
4820h
0000h
0000h
FFFFh
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65)
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
90
12
27
24
11
10
7
4
18
17
16
3
2
1
0001
0
000
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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3.4.4 Ping-Pong Buffering
Although the previous configuration allows the EDMA3 to service a peripheral continuously, it presents a
number of restrictions to the CPU. Because the input and output buffers are continuously being
filled/emptied, the CPU must match the pace of the EDMA3 very closely to process the data. The EDMA3
receive data must always be placed in memory before the CPU accesses it, and the CPU must provide
the output data before the EDMA3 transfers it. Though not impossible, this is an unnecessary challenge. It
is particularly difficult in a 2-level cache scheme.
Ping-pong buffering is a simple technique that allows the CPU activity to be distanced from the EDMA3
activity. This means that there are multiple (usually two) sets of data buffers for all incoming and outgoing
data streams. While the EDMA3 transfers the data into and out of the ping buffers, the CPU manipulates
the data in the pong buffers. When both CPU and EDMA3 activity completes, they switch. The EDMA3
then writes over the old input data and transfers the new output data. Figure 3-14 shows the ping-pong
scheme for this example.
To change the continuous operation example, such that a ping-pong buffering scheme is used, the
EDMA3 channels need only a moderate change. Instead of one parameter set, there are two; one for
transferring data to/from the ping buffers and one for transferring data to/from the pong buffers. As soon
as one transfer completes, the channel loads the PaRAM set for the other and the data transfers continue.
Figure 3-15 shows the EDMA3 channel configuration required.
Each channel has two parameter sets, ping and pong. The EDMA3 channel is initially loaded with the ping
parameters (Figure 3-15). The link address for the ping set is set to the PaRAM offset of the pong
parameter set (Figure 3-16). The link address for the pong set is set to the PaRAM offset of the ping
parameter set (Figure 3-17). The channel options, count values, and index values are all identical between
the ping and pong parameters for each channel. The only differences are the link address provided and
the address of the data buffer.
3.4.4.1
Synchronization with the CPU
To utilize the ping-pong buffering technique, the system must signal the CPU when to begin to access the
new data set. After the CPU finishes processing an input buffer (ping), it waits for the EDMA3 to complete
before switching to the alternate (pong) buffer. In this example, both channels provide their channel
numbers as their report word and set the TCINTEN bit to generate an interrupt after completion. When
channel 13 fills an input buffer, the E13 bit in the interrupt pending register (IPR) is set; when channel 12
empties an output buffer, the E12 bit in IPR is set. The CPU must manually clear these bits. With the
channel parameters set, the CPU polls IPR to determine when to switch. The EDMA3 and CPU could
alternatively be configured such that the channel completion interrupts the CPU. By doing this, the CPU
could service a background task while waiting for the EDMA3 to complete.
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Figure 3-14. Ping-Pong Buffering for McBSP Data Example
..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1
RSR
Pong
Ping
80 0000h
A1i
A2i
A3i
A4i
A5i
A6i
A7i
A9i
A10i A11i A12i A13i
...
...
RBR
A8i
80 0800h
A1i
A2i
A3i
A4i
A5i
A9i
A10i A11i A12i A13i
B1i
B2i
B9i
B10i B11i B12i B13i
A1o
A2o
A6i
A7i
...
...
B6i
B7i
...
...
A6o
A7o
...
...
B6o
B7o
...
...
A8i
DRR
80 0080h
80 1000h
B1i
B2i
B3i
B4i
B5i
B9i
B10i B11i B12i B13i
A1o
A2o
A3o
A4o
A5o
A9o A10o A11o A12o A13o
B6i
B7i
...
...
A6o
A7o
...
...
3000 0000h
B8i
80 0880h
REVT0
A8o
80 1800h
XEVT0
B3i
A3o
B4i
A4o
B5i
A5o
A9o A10o A11o A12o A13o
B8i
A8o
DXR
80 1080h
B1o
B2o
B3o
B4o
B5o
B9o B10o B11o B12o B13o
B6o
B7o
...
...
B8o
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5
80 1880h
B1o
B2o
B3o
B4o
B5o
B9o B10o B11o B12o B13o
B8o
XSR
3000 0004h
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Figure 3-15. Ping-Pong Buffering for McBSP Example PaRAM Configuration
(a) EDMA Parameters for Channel 13 (Using PaRAM Set 13 Linked to Pong Set 64)
Parameter Contents
0010 D000h
3000 0000h
0080h
0001h
0080 0000h
0001h
0000h
0080h
0000h
4800h
0000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content for Channel 13
31
30
28
27
24
23
22
21
20
19
18
17
16
0
000
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
3
2
1
1101
12
11
0
10
000
8
7
0000
4
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
(c) EDMA Parameters for Channel 12 (Using PaRAM Set 12 Linked to Pong Set 65)
Parameter Contents
0010 C000h
0080 1000h
0080h
0001h
3000 0004h
0000h
0001h
0080h
0000h
4840h
0000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(d) Channel Options Parameter (OPT) Content for Channel 12
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
1100
0
000
0000
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
Figure 3-16. Ping-Pong Buffering for McBSP Example Pong PaRAM Configuration
(a) EDMA Pong Parameters for Channel 13 at Set 64 Linked to Set 65
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Parameter Contents
0010 D000h
3000 0000h
0080h
0001h
0080 0800h
0001h
0000h
0080h
0000h
4820h
0000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) EDMA Pong Parameters for Channel 12 at Set 66 Linked to Set 67
Parameter Contents
0010 C000h
0080 1800h
0080h
0001h
3000 0004h
0000h
0001h
94
0080h
0000h
4860h
0000h
0000h
0001h
EDMA3 Transfer Examples
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
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Figure 3-17. Ping-Pong Buffering for McBSP Example Ping PaRAM Configuration
(a) EDMA Ping Parameters for Channel 13 at Set 65 Linked to Set 64
Parameter Contents
0010 D000h
3000 0000h
0080h
0001h
0080 0000h
0001h
0000h
0080h
0000h
4800h
0000h
0000h
0001h
Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
(b) EDMA Ping Parameters for Channel 12 at Set 67 Linked to Set 66
Parameter Contents
0010 C000h
0080 1000h
0080h
0001h
3000 0004h
0000h
0001h
0080h
0000h
4840h
0000h
0000h
0001h
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Parameter
Channel Options Parameter (OPT)
Channel Source Address (SRC)
Count for 2nd Dimension (BCNT)
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
Destination BCNT Index
Source BCNT Index (SRCBIDX)
(DSTBIDX)
BCNT Reload (BCNTRLD)
Link Address (LINK)
Destination CCNT Index
Source CCNT Index (SRCCIDX)
(DSTCIDX)
Reserved
Count for 3rd Dimension (CCNT)
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3.4.5 Transfer Chaining Examples
The following examples explain the intermediate transfer complete chaining function.
3.4.5.1
Servicing Input/Output FIFOs with a Single Event
Many systems require the use of a pair of external FIFOs that must be serviced at the same rate. One
FIFO buffers data input, and the other buffers data output. The EDMA3 channels that service these FIFOs
can be set up for AB-synchronized transfers. While each FIFO is serviced with a different set of
parameters, both can be signaled from a single event. For example, an external interrupt pin can be tied
to the status flags of one of the FIFOs. When this event arrives, the EDMA3 needs to perform servicing for
both the input and output streams. Without the intermediate transfer complete chaining feature this would
require two events, and thus two external interrupt pins. The intermediate transfer complete chaining
feature allows the use of a single external event (for example, a GPIO event). Figure 3-18 shows the
EDMA3 setup and illustration for this example.
A GPIO event (in this case, GPINT0) triggers an array transfer. Upon completion of each intermediate
array transfer of channel 48, intermediate transfer complete chaining sets the E8 bit (specified by TCC of
8) in the chained event register (CER) and provides a synchronization event to channel 8. Upon
completion of the last array transfer of channel 48, transfer complete chaining—not intermediate transfer
complete chaining—sets the E8 bit in CER (specified by TCCMODE:TCC) and provides a synchronization
event to channel 8. The completion of channel 8 sets the I8 bit (specified by TCCMODE:TCC) in the
interrupt pending register (IPR), which can generate an interrupt to the CPU, if the I8 bit in the interrupt
enable register (IER) is set.
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Figure 3-18. Intermediate Transfer Completion Chaining Example
Hardwired event
(tied to GPINT0, event 48)
Chained event
(event 8)
Event 48
Intermediate
transfer complete(A)
Channel 48, array 0
Channel 8, array 0
Event 48
Intermediate
transfer complete(A)
Channel 48, array 1
Channel 8, array 1
Event 48
Intermediate
transfer complete(A)
Channel 8, array 2
Channel 48, array 2
Event 48
Channel 48, array 3
(last array)
Notes:
Channel 8, array 3
Transfer complete sets
IPR.I8 = 1
If IPR.I8 = 1, interrupt
EDMACC_INT* sent
to CPU
(A) Intermediate transfer complete chaining synchronizes event 8
ITCCHEN = 1, TCC = 01000b, and sets CER.E8 = 1
(B) Transfer complete chaining synchronizes event 8
TCCHEN =1, TCC = 01000b and sets CER.E8 = 1
Setup
Channel 48 parameters
for chaining
3.4.5.2
Transfer complete(B)
Channel 8 parameters
for chaining
Enable transfer
complete chaining:
OPT.TCCHEN = 1
OPT.TCC = 01000b
Enable transfer
complete chaining:
OPT.TCINTEN = 1
OPT.TCC = 01000b
Enable intermediate transfer
complete chaining:
OPT.ITCCHEN = 1
OPT.TCC = 01000b
Disable intermediate transfer
complete chaining:
OPT.ITCCHEN = 0
Event enable register (EER)
Enable channel 48
EER.E48 = 1
Breaking Up Large Transfers with Intermediate Chaining
Another feature of intermediate transfer chaining (ITCCHEN) is for breaking up large transfers. A large
transfer may lock out other transfers of the same priority level for the duration of the transfer. For example,
a large transfer on queue 0 from the internal memory to the external memory using the EMIF may starve
other EDMA3 transfers on the same queue. In addition, this large high-priority transfer may prevent the
EMIF for a long duration to service other lower priority transfers. When a large transfer is considered to be
high priority, it should be split into multiple smaller transfers. Figure 3-19 shows the EDMA3 setup and
illustration of an example single large block transfer.
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Figure 3-19. Single Large Block Transfer Example
Event 25 (CPU writes 1 to ESR.E25)
EDMA3 channel 25 setup
ACNT = 16384
BCNT = 1
CCNT = 1
OPT.ITCINTEN = 0
OPT.TCC = Don’t care
1D transfer of 16 KByte elements
16 KBytes data transfer
The intermediate transfer chaining enable (ITCCHEN) provides a method to break up a large transfer into
smaller transfers. For example, to move a single large block of memory (16K bytes), the EDMA3 performs
an A-synchronized transfer. The element count is set to a reasonable value, where reasonable derives
from the amount of time it would take to move this smaller amount of data. Assume 1 Kbyte is a
reasonable small transfer in this example. The EDMA3 is set up to transfer 16 arrays of 1 Kbyte elements,
for a total of 16K byte elements. The TCC field in the channel options parameter (OPT) is set to the same
value as the channel number and ITCCHEN are set. In this example, EDMA3 channel 25 is used and
TCC is also set to 25. The TCINTEN may also be set to trigger interrupt 25 when the last 1 Kbyte array is
transferred. The CPU starts the EDMA3 transfer by writing to the appropriate bit of the event set register
(ESR.E25). The EDMA3 transfers the first 1 Kbyte array. Upon completion of the first array, intermediate
transfer complete code chaining generates a synchronization event to channel 25, a value specified by the
TCC field. This intermediate transfer completion chaining event causes EDMA3 channel 25 to transfer the
next 1 Kbyte array. This process continues until the transfer parameters are exhausted, at which point the
EDMA3 has completed the 16K byte transfer. This method breaks up a large transfer into smaller packets,
thus providing natural time slices in the transfer such that other events may be processed. Figure 3-20
shows the EDMA3 setup and illustration of the broken up smaller packet transfers.
Figure 3-20. Smaller Packet Data Transfers Example
Event 25 (CPU writes 1 to ESR.E25)
ITCCHEN=1, TCC=25 causes
channel 25 to be synchronized again
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
Time gaps allow other transfers on the same priority level
to be performed
EDMA3 channel 25 setup
ACNT = 1024
BCNT = 16
CCNT = 1
OPT.SYNCDIM = A SYNC
OPT.ITCCHEN = 1
OPT.TCINTEN = 1
OPT.TCC = 25
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Chapter 4
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Registers
This chapter describes the memory-mapped registers associated with the EDMA3 controller.
Topic
4.1
4.2
4.3
...........................................................................................................................
Page
Register Memory Maps ..................................................................................... 100
EDMA3 Channel Controller Control Registers ..................................................... 100
EDMA3 Transfer Controller Control Registers ..................................................... 158
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Registers
99
Register Memory Maps
4.1
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Register Memory Maps
For the register memory maps, see the device-specific data manual.
4.2
EDMA3 Channel Controller Control Registers
Table 4-1 lists the memory-mapped registers for the EDMA3 channel controller (EDMA3CC). For the
memory address of these registers and for the shadow region addresses, see the device-specific data
manual. All other register offset addresses not listed in Table 4-1 should be considered as reserved
locations and the register contents should not be modified.
Table 4-1. EDMA3CC Registers
Offset
Acronym
Register Description
00h
PID
Peripheral Identification Register
Section 4.2.1.1
04h
CCCFG
EDMA3CC Configuration Register
Section 4.2.1.2
0100h-01FCh
See
DCHMAP0-63
DMA Channel 0-63 Mapping Registers
Section 4.2.1.3
0200h
QCHMAP0
QDMA Channel 0 Mapping Register
Section 4.2.1.4
0204h
QCHMAP1
QDMA Channel 1 Mapping Register
Section 4.2.1.4
0208h
QCHMAP2
QDMA Channel 2 Mapping Register
Section 4.2.1.4
020Ch
QCHMAP3
QDMA Channel 3 Mapping Register
Section 4.2.1.4
0210h
QCHMAP4
QDMA Channel 4 Mapping Register (TCI6487/88 only)
Section 4.2.1.4
0214h
QCHMAP5
QDMA Channel 5 Mapping Register (TCI6487/88 only)
Section 4.2.1.4
0218h
QCHMAP6
QDMA Channel 6 Mapping Register (TCI6487/88 only)
Section 4.2.1.4
021Ch
QCHMAP7
QDMA Channel 7 Mapping Register (TCI6487/88 only)
Section 4.2.1.4
0240h
DMAQNUM0
DMA Queue Number Register 0
Section 4.2.1.5
0244h
DMAQNUM1
DMA Queue Number Register 1
Section 4.2.1.5
0248h
DMAQNUM2
DMA Queue Number Register 2
Section 4.2.1.5
024Ch
DMAQNUM3
DMA Queue Number Register 3
Section 4.2.1.5
0250h
DMAQNUM4
DMA Queue Number Register 4
Section 4.2.1.5
0254h
DMAQNUM5
DMA Queue Number Register 5
Section 4.2.1.5
0258h
DMAQNUM6
DMA Queue Number Register 6
Section 4.2.1.5
025Ch
DMAQNUM7
DMA Queue Number Register 7
Section 4.2.1.5
0260h
QDMAQNUM
QDMA Queue Number Register
Section 4.2.1.6
0280h
QUETCMAP
Queue-to-TC Mapping Register
Section 4.2.1.7
0284h
QUEPRI
Queue Priority Register
Section 4.2.1.8
0300h
EMR
Event Missed Register
Section 4.2.2.1
0304h
EMRH
Event Missed Register High
Section 4.2.2.1
0308h
EMCR
Event Missed Clear Register
Section 4.2.2.2
030Ch
EMCRH
Event Missed Clear Register High
Section 4.2.2.2
0310h
QEMR
QDMA Event Missed Register
Section 4.2.2.3
0314h
QEMCR
QDMA Event Missed Clear Register
Section 4.2.2.4
0318h
CCERR
EDMA3CC Error Register
Section 4.2.2.5
031Ch
CCERRCLR
EDMA3CC Error Clear Register
Section 4.2.2.6
0320h
EEVAL
Error Evaluate Register
Section 4.2.2.7
0340h
DRAE0
DMA Region Access Enable Register for Region 0
Section 4.2.3.1
0344h
DRAEH0
DMA Region Access Enable Register High for Region 0
Section 4.2.3.1
0348h
DRAE1
DMA Region Access Enable Register for Region 1
Section 4.2.3.1
034Ch
DRAEH1
DMA Region Access Enable Register High for Region 1
Section 4.2.3.1
0350h
DRAE2
DMA Region Access Enable Register for Region 2
Section 4.2.3.1
0354h
DRAEH2
DMA Region Access Enable Register High for Region 2
Section 4.2.3.1
0358h
DRAE3
DMA Region Access Enable Register for Region 3
Section 4.2.3.1
035Ch
DRAEH3
DMA Region Access Enable Register High for Region 3
Section 4.2.3.1
100 Registers
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Table 4-1. EDMA3CC Registers (continued)
Offset
Acronym
Register Description
0360h
DRAE4
DMA Region Access Enable Register for Region 4
Section 4.2.3.1
See
0364h
DRAEH4
DMA Region Access Enable Register High for Region 4
Section 4.2.3.1
0368h
DRAE5
DMA Region Access Enable Register for Region 5
Section 4.2.3.1
036Ch
DRAEH5
DMA Region Access Enable Register High for Region 5
Section 4.2.3.1
0370h
DRAE6
DMA Region Access Enable Register for Region 6
Section 4.2.3.1
0374h
DRAEH6
DMA Region Access Enable Register High for Region 6
Section 4.2.3.1
0378h
DRAE7
DMA Region Access Enable Register for Region 7
Section 4.2.3.1
037Ch
DRAEH7
DMA Region Access Enable Register High for Region 7
Section 4.2.3.1
0380h-039Ch
QRAE0-7
QDMA Region Access Enable Registers for Region 0-7
Section 4.2.3.2
0400h-04FCh
Q0E0-Q3E15
Event Queue Entry Registers Q0E0-Q3E15
Section 4.2.4.1
0600h-060Ch
QSTAT0-3
Queue Status Registers 0-3
Section 4.2.4.2
0620h
QWMTHRA
Queue Watermark Threshold A Register
Section 4.2.4.3
0624h
QWMTHRB
Queue Watermark Threshold B Register for TCI6487/88 Devices
Section 4.2.4.4
0640h
CCSTAT
EDMA3CC Status Register
Section 4.2.4.5
0800h
MPFAR
Memory Protection Fault Address Register
Section 4.2.5.1
0804h
MPFSR
Memory Protection Fault Status Register
Section 4.2.5.2
0808h
MPFCR
Memory Protection Fault Command Register
Section 4.2.5.3
080 Ch
MPPAG
Memory Protection Page Attribute Global Register
Section 4.2.5.4
0810h-082Ch
MPPA0-7
Memory Protection Page Attribute Registers 0-7
Section 4.2.5.4
1000h
ER
Event Register
Section 4.2.6.1
1004h
ERH
Event Register High
Section 4.2.6.1
1008h
ECR
Event Clear Register
Section 4.2.6.2
100Ch
ECRH
Event Clear Register High
Section 4.2.6.2
1010h
ESR
Event Set Register
Section 4.2.6.3
1014h
ESRH
Event Set Register High
Section 4.2.6.3
1018h
CER
Chained Event Register
Section 4.2.6.4
101Ch
CERH
Chained Event Register High
Section 4.2.6.4
1020h
EER
Event Enable Register
Section 4.2.6.5
1024h
EERH
Event Enable Register High
Section 4.2.6.5
1028h
EECR
Event Enable Clear Register
Section 4.2.6.6
102Ch
EECRH
Event Enable Clear Register High
Section 4.2.6.6
1030h
EESR
Event Enable Set Register
Section 4.2.6.7
1034h
EESRH
Event Enable Set Register High
Section 4.2.6.7
1038h
SER
Secondary Event Register
Section 4.2.6.8
103Ch
SERH
Secondary Event Register High
Section 4.2.6.8
1040h
SECR
Secondary Event Clear Register
Section 4.2.6.9
1044h
SECRH
Secondary Event Clear Register High
Section 4.2.6.9
1050h
IER
Interrupt Enable Register
Section 4.2.7.1
1054h
IERH
Interrupt Enable Register High
Section 4.2.7.1
1058h
IECR
Interrupt Enable Clear Register
Section 4.2.7.2
105Ch
IECRH
Interrupt Enable Clear Register High
Section 4.2.7.2
1060h
IESR
Interrupt Enable Set Register
Section 4.2.7.3
1064h
IESRH
Interrupt Enable Set Register High
Section 4.2.7.3
1068h
IPR
Interrupt Pending Register
Section 4.2.7.4
106Ch
IPRH
Interrupt Pending Register High
Section 4.2.7.4
1070h
ICR
Interrupt Clear Register
Section 4.2.7.5
1074h
ICRH
Interrupt Clear Register High
Section 4.2.7.5
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Table 4-1. EDMA3CC Registers (continued)
Offset
Acronym
Register Description
1078h
IEVAL
Interrupt Evaluate Register
Section 4.2.7.6
See
1080h
QER
QDMA Event Register
Section 4.2.8.1
1084h
QEER
QDMA Event Enable Register
Section 4.2.8.2
1088h
QEECR
QDMA Event Enable Clear Register
Section 4.2.8.3
108Ch
QEESR
QDMA Event Enable Set Register
Section 4.2.8.4
1090h
QSER
QDMA Secondary Event Register
Section 4.2.8.5
1094h
QSECR
QDMA Secondary Event Clear Register
Section 4.2.8.6
Shadow Region 0 Channel Registers
2000h
ER
Event Register
2004h
ERH
Event Register High
2008h
ECR
Event Clear Register
200Ch
ECRH
Event Clear Register High
2010h
ESR
Event Set Register
2014h
ESRH
Event Set Register High
2018h
CER
Chained Event Register
201Ch
CERH
Chained Event Register High
2020h
EER
Event Enable Register
2024h
EERH
Event Enable Register High
2028h
EECR
Event Enable Clear Register
202Ch
EECRH
Event Enable Clear Register High
2030h
EESR
Event Enable Set Register
2034h
EESRH
Event Enable Set Register High
2038h
SER
Secondary Event Register
203Ch
SERH
Secondary Event Register High
2040h
SECR
Secondary Event Clear Register
2044h
SECRH
Secondary Event Clear Register High
2050h
IER
Interrupt Enable Register
2054h
IERH
Interrupt Enable Register High
2058h
IECR
Interrupt Enable Clear Register
205Ch
IECRH
Interrupt Enable Clear Register High
2060h
IESR
Interrupt Enable Set Register
2064h
IESRH
Interrupt Enable Set Register High
2068h
IPR
Interrupt Pending Register
206Ch
IPRH
Interrupt Pending Register High
2070h
ICR
Interrupt Clear Register
2074h
ICRH
Interrupt Clear Register High
2078h
IEVAL
Interrupt Evaluate Register
2080h
QER
QDMA Event Register
2084h
QEER
QDMA Event Enable Register
2088h
QEECR
QDMA Event Enable Clear Register
208Ch
QEESR
QDMA Event Enable Set Register
2090h
QSER
QDMA Secondary Event Register
2094h
QSECR
QDMA Secondary Event Clear Register
2200h-2294h
-
Shadow Region 1 Channel Registers
2400h-2494h
-
Shadow Region 2 Channel Registers
...
2E00h-2E94h
102 Registers
...
-
Shadow Channel Registers for MP Space 7
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4.2.1 Global Registers
4.2.1.1
Peripheral Identification Register (PID)
The peripheral identification register (PID) uniquely identifies the EDMA3CC and the specific revision of
the EDMA3CC.
The PID is shown in Figure 4-1 and described in Table 4-2.
Figure 4-1. Peripheral ID Register (PID)
31
16
PID
R-4001h
15
0
PID
(A)
LEGEND: R = Read only; -n = value after reset
A. R-1B00h for TCI6482/86/C6472 devices; R-5300h for TCI6487/88 devices
Table 4-2. Peripheral ID Register (PID) Field Descriptions
Bit
31-0
Field
PID
Value
0-FFFF FFFFh
Description
Peripheral identifier uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC.
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EDMA3CC Configuration Register (CCCFG)
The EDMA3CC configuration register (CCCFG) provides the features/resources for the EDMA3CC in a
particular device.
The CCCFG is shown in Figure 4-2 and described in Table 4-3.
Figure 4-2. EDMA3CC Configuration Register (CCCFG)
31
26
23
22
25
24
Reserved
MP_EXIST
CHMAP_EXIST
R-x
R-1
R-1
21
20
19
18
16
Reserved
NUM_REGN
Reserved
NUM_EVQUE
R-0
R-3h
R-x
R-3h
15
14
12
11
10
8
Reserved
NUM_PAENTRY
Reserved
NUM_INTCH
R-x
R-4h
R-x
R-4h
7
6
4
3
2
0
Reserved
NUM_QDMACH
Reserved
NUM_DMACH
R-x
R-2h
R-x
R-5h
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 4-3. EDMA3CC Configuration Register (CCCFG) Field Descriptions
Bit
31-26
25
24
Field
Reserved
21-20
NUM_REGN
Reserved
NUM_EVQUE
104
Reserved
Registers
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
Memory protection existence.
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
1
Memory protection logic included
Channel mapping existence.
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
1
Channel mapping logic included
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0-3h
Number of MP and shadow regions.
0-2h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
3h
8 regions
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0-7h
Number of queues/number of TCs.
0-2h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
3h
15
Description
0
CHMAP_EXIST
Reserved
18-16
0
MP_EXIST
23-22
19
Value
4 EDMA3TCs/Event Queues
4h-7h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
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Table 4-3. EDMA3CC Configuration Register (CCCFG) Field Descriptions (continued)
Bit
14-12
Field
NUM_PAENTRY
Value
Number of PaRAM sets.
0-3h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
4h
11
10-8
Reserved
NUM_INTCH
6-4
3
2-0
Reserved
NUM_QDMACH
Reserved
NUM_DMACH
256 PaRAM sets
5h-7h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0-7h
Number of interrupt channels.
0-3h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
4h
7
Description
0-7h
64 interrupt channels
5h-7h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior.
0-7h
Number of QDMA channels.
0-1h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior (for TCI6482/86/C6472 devices).
0-3h
Reserved (for TCI6487/88 devices).
2h
4 QDMA channels (for TCI6482/86/C6472 devices).
4h
8 QDMA channels (for TCI6487/88 devices).
3h-7h
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so
may result in undefined behavior (for TCI6482/86/C6472 devices).
5h-7h
Reserved (for TCI6487/88 devices).
0
Reserved
0-7h
Number of DMA channels.
0-4h
Reserved
5h
6h-7h
64 DMA channels
Reserved
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DMA Channel Map n Registers (DCHMAPn)
The DMA channel map n register (DCHMAPn) is shown in Figure 4-3 and described in Table 4-4.
Figure 4-3. DMA Channel Map n Registers (DCHMAPn)
31
16
Reserved
R-0
15
14
13
5
4
0
Reserved
PAENTRY
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-4. DMA Channel Map n Registers (DCHMAPn) Field Descriptions
Bit
Field
Value
31-14
Reserved
0
13-5
PAENTRY
0-1FFh
4-0
Reserved
0
106
Registers
Description
Reserved
Points to the PaRAM set number for DMA channel n.
Reserved
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4.2.1.4
QDMA Channel Map n Registers (QCHMAPn)
Each QDMA channel in EDMA3CC can be associated with any PaRAM set available on the device.
Furthermore, the specific trigger word (0-7) of the PaRAM set can be programmed. The PaRAM set
association and trigger word for every QDMA channel register is configurable using the QDMA channel
map n register (QCHMAPn).
The QCHMAPn is shown in Figure 4-4 and described in Table 4-5.
NOTE: At reset the QDMA channel map registers for all QDMA channels point to PaRAM set 0. If
an application makes use of both a DMA channel that points to PaRAM set 0 and any QDMA
channels, ensure that QCHMAPn is programmed appropriately to point to a different PaRAM
entry.
Figure 4-4. QDMA Channel Map n Registers (QCHMAPn)
31
16
Reserved
R-0
15
14
13
5
4
2
1
0
Reserved
PAENTRY
TRWORD
Reserved
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-5. QDMA Channel Map n Registers (QCHMAPn) Field Descriptions
Bit
Field
Value
Description
31-14
Reserved
0
13-5
PAENTRY
0-1FFh
PAENTRY points to the PaRAM set number for QDMA channel n.
0-FFh
Parameter entry 0 through 255
100h-1FFh
4-2
TRWORD
0-7h
1-0
Reserved
0
Reserved
Reserved
Points to the specific trigger word of the PaRAM set defined by PAENTRY. A write to the trigger
word results in a QDMA event being recognized.
Reserved
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DMA Channel Queue n Number Registers (DMAQNUMn)
The DMA channel queue number register (DMAQNUMn) allows programmability of each of the 64 DMA
channels in the EDMA3CC to submit its associated synchronization event to any event queue in the
EDMA3CC. At reset, all channels point to event queue 0.
The DMAQNUMn is shown in Figure 4-5 and described in Table 4-6. Table 4-7 shows the channels and
their corresponding bits in DMAQNUMn.
Figure 4-5. DMA Channel Queue n Number Registers (DMAQNUMn)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
En
Rsvd
En
Rsvd
En
Rsvd
En
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
En
Rsvd
En
Rsvd
En
Rsvd
En
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-6. DMA Channel Queue n Number Registers (DMAQNUMn) Field Descriptions
Bit
31-0
Field
Value
En
0-7h
Description
DMA queue number. Contains the event queue number to be used for the corresponding DMA channel.
Programming DMAQNUMn for an event queue number to a value more then the number of queues
available in the EDMA3CC results in undefined behavior.
0
Event n is queued on Q0.
1h
Event n is queued on Q1.
2h
Event n is queued on Q2.
3h
Event n is queued on Q3.
4h
Event n is queued on Q4 (for TCI6487/88 devices).
5h
Event n is queued on Q5 (for TCI6487/88 devices).
4h-7h
Reserved (for TCI6482/86/C6472 devices)
6h-7h
Reserved (for TCI6487/88 devices)
Table 4-7. Bits in DMAQNUMn
Channel Number (DMAQNUMn)
108
En bit
0
1
2
3
4
5
6
7
0-2
E0
E8
E16
E24
E32
E40
E48
E56
4-6
E1
E9
E17
E25
E33
E41
E49
E57
8-10
E2
E10
E18
E26
E34
E42
E50
E58
12-14
E3
E11
E19
E27
E35
E43
E51
E59
16-18
E4
E12
E20
E28
E36
E44
E52
E60
20-22
E5
E13
E21
E29
E37
E45
E53
E61
24-26
E6
E14
E22
E30
E38
E46
E54
E62
28-30
E7
E15
E23
E31
E39
E47
E55
E63
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4.2.1.6
QDMA Channel Queue Number Register (QDMAQNUM)
The QDMA channel queue number register (QDMAQNUM) is used to program all the QDMA channels in
the EDMA3CC to submit the associated QDMA event to any of the event queues in the EDMA3CC.
The QDMAQNUM is shown in Figure 4-6 and Figure 4-7 and described in Table 4-8.
Figure 4-6. QDMA Channel Queue Number Register (QDMAQNUM) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
E3
Rsvd
E2
Rsvd
E1
Rsvd
E0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-7. QDMA Channel Queue Number Register (QDMAQNUM) for TCI6487/88 Devices
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
E7
Rsvd
E6
Rsvd
E5
Rsvd
E4
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
E3
Rsvd
E2
Rsvd
E1
Rsvd
E0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-8. QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
Bit
Field
31-15
Reserved
14-0
En
Value
0
0-7h
Description
Reserved
QDMA queue number. Contains the event queue number to be used for the corresponding QDMA
channel.
0
Event n is queued on Q0.
1h
Event n is queued on Q1.
2h
Event n is queued on Q2.
3h
Event n is queued on Q3.
4h
Event n is queued on Q4 (for TCI6487/88 devices).
5h
Event n is queued on Q5 (for TCI6487/88 devices).
4h-7h
Reserved (for TCI6482/86/C6472 devices)
6h-7h
Reserved (for TCI6487/88 devices)
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Queue-to-TC Mapping Register (QUETCMAP)
The Queue-to-TC Mapping Register (QUETCMAP) is shown in Figure 4-8and Figure 4-9 and described in
Table 4-9.
Figure 4-8. Queue-to-TC Mapping Register (QUETCMAP) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
TCNUMQ3
Rsvd
TCNUMQ2
Rsvd
TCNUMQ1
Rsvd
TCNUMQ0
R-0
R/W-3
R-0
R/W-2
R-0
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-9. Queue-to-TC Mapping Register (QUETCMAP) for TCI6487/88 Devices
31
15
23
14
22
20
19
18
16
Reserved
TCNUMQ5
Rsvd
TCNUMQ4
R-0
R/W-5
R-0
R/W-4
12
11
10
8
7
6
4
3
2
0
Rsvd
TCNUMQ3
Rsvd
TCNUMQ2
Rsvd
TCNUMQ1
Rsvd
TCNUMQ0
R-0
R/W-3
R-0
R/W-2
R-0
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-9. Queue-to-TC Mapping Register (QUETCMAP) Field Descriptions
Bit
Field
Value
Description
31-15, Reserved
11, 7, 3
Reserved for TCI6482/86/C6472 Devices
31-23, Reserved
19, 15,
11, 7, 3
Reserved for TCI6487/88 Devices
14-12, TCNUMQn
10-8,
6-4, 2-0
TC number for queue n for TCI6482/86/C6472 Devices. Defines the TC number to which Event
Queue n TRs are written via the TR bus interface. Only used if TCs are not identical (e.g., TC0
FIFO is 32 bytes while TC1 FIFO is 64 bytes). Note that the same TC cannot be assigned to
multiple queues (i.e., TCNUMQn ≠ TCNUMQm).
22-20, TCNUMQn
18-16,
14-12,
10-8,
6-4, 2-0
TC number for queue n for TCI6487/88 Devices. Defines the TC number to which Event Queue n
TRs are written via the TR bus interface. Only used if TCs are not identical (e.g., TC0 FIFO is 32
bytes while TC1 FIFO is 64 bytes). Note that the same TC cannot be assigned to multiple queues
(i.e., TCNUMQn ≠ TCNUMQm).
110
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4.2.1.8
Queue Priority Register (QUEPRI)
The queue priority register (QUEPRI) allows you to change the priority of the individual queues and the
priority of the transfer request (TR) associated with the events queued in the queue. The queue-to-TC
mapping programmable feature programs QUEPRI, essentially governing the priority of the associated
transfer controller(s) read/write commands with respect to the other bus masters in the device. You can
modify the EDMA3TC priority to obtain the desired system performance.
The QUEPRI is shown in Figure 4-10 and Figure 4-11 and described in Table 4-10.
Figure 4-10. Queue Priority Register (QUEPRI) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
14
12
11
10
8
Rsvd
PRIQ3
Rsvd
PRIQ2
R-0
R/W-0
R-0
R/W-0
7
6
Rsvd
4
3
2
0
PRIQ1
Rsvd
PRIQ0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-11. Queue Priority Register (QUEPRI) for TCI6487/88 Devices
31
15
23
14
12
22
20
19
18
16
Reserved
PRIQ5
Rsvd
PRIQ4
R-0
R/W-0
R-0
R/W-0
11
10
8
Rsvd
PRIQ3
Rsvd
PRIQ2
R-0
R/W-0
R-0
R/W-0
7
Rsvd
6
4
3
2
0
PRIQ1
Rsvd
PRIQ0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-10. Queue Priority Register (QUEPRI) Field Descriptions
Bit
Field
Value
Description
31-15
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-23
Reserved
0
Reserved for TCI6487/88 devices.
22-20
PRIQ5
19
18-16
15
14-12
11
10-8
7
6-4
3
2-0
Reserved
PRIQ4
Reserved
PRIQ3
Reserved
PRIQ2
Reserved
PRIQ1
Reserved
PRIQ0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
Priority level for queue 5. Dictates the priority level used by TC5 relative to other masters in the device.
A value of 0 means highest priority and a value of 7 means lowest priority for TCI6487/88 devices.
Reserved for TCI6487/88 devices.
Priority level for queue 4. Dictates the priority level used by TC4 relative to other masters in the device.
A value of 0 means highest priority and a value of 7 means lowest priority for TCI6487/88 devices.
Reserved for TCI6487/88 devices.
Priority level for queue 3. Dictates the priority level used by TC3 relative to other masters in the device.
A value of 0 means highest priority and a value of 7 means lowest priority.
Reserved
Priority level for queue 2. Dictates the priority level used by TC2 relative to other masters in the device.
A value of 0 means highest priority and a value of 7 means lowest priority.
Reserved
Priority level for queue 1. Dictates the priority level used by TC1 relative to other masters in the device.
A value of 0 means highest priority and a value of 7 means lowest priority.
Reserved
Priority level for queue 0. Dictates the priority level used by TC0 relative to other masters in the device.
A value of 0 means highest priority and a value of 7 means lowest priority.
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4.2.2 Error Registers
The EDMA3CC contains a set of registers that provide information on missed DMA and/or QDMA events,
and instances when event queue thresholds are exceeded. If any of the bits in these registers is set, it
results in the EDMA3CC generating an error interrupt.
4.2.2.1
Event Missed Registers (EMR/EMRH)
For a particular DMA channel, if a second event is received prior to the first event getting cleared/serviced,
the bit corresponding to that channel is set/asserted in the event missed registers (EMR/EMRH). All
trigger types are treated individually, that is, manual triggered (ESR/ESRH), chain triggered (CER/CERH),
and event triggered (ER/ERH) are all treated separately. The EMR/EMRH bits for a channel are also set if
an event on that channel encounters a NULL entry (or a NULL TR is serviced). If any EMR/EMRH bit is
set (and all errors, including bits in other error registers (QEMR, CCERR) were previously cleared), the
EDMA3CC generates an error interrupt. See Section 2.9.4 for details on EDMA3CC error interrupt
generation.
The EMR is shown in Figure 4-12 and described in Table 4-11. The EMRH is shown in Figure 4-13 and
described in Table 4-12.
Figure 4-12. Event Missed Register (EMR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-11. Event Missed Register (EMR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear
register (EMCR).
0
No missed event.
1
Missed event occurred.
Figure 4-13. Event Missed Register High (EMRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-12. Event Missed Register High (EMRH) Field Descriptions
Bit
31-0
112
Field
Value
En
Registers
Description
Channel 32–63 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed
clear register high (EMCRH).
0
No missed event.
1
Missed event occurred.
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4.2.2.2
Event Missed Clear Registers (EMCR/EMCRH)
Once a missed event is posted in the event missed registers (EMR/EMRH), the bit remains set and you
need to clear the set bit(s). This is done by way of CPU writes to the event missed clear registers
(EMCR/EMCRH). Writing a 1 to any of the bits clears the corresponding missed event (bit) in EMR/EMRH;
writing a 0 has no effect.
The EMCR is shown in Figure 4-14 and described in Table 4-13. The EMCRH is shown in Figure 4-15
and described in Table 4-14.
Figure 4-14. Event Missed Clear Register (EMCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-13. Event Missed Clear Register (EMCR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event missed 0-31 clear. All error bits must be cleared before additional error interrupts will be asserted
by the EDMA3CC.
0
No effect.
1
Corresponding missed event bit in the event missed register (EMR) is cleared (En = 0).
Figure 4-15. Event Missed Clear Register High (EMCRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-14. Event Missed Clear Register High (EMCRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event missed 32–63 clear. All error bits must be cleared before additional error interrupts will be asserted
by the EDMA3CC.
0
No effect.
1
Corresponding missed event bit in the event missed register high (EMRH) is cleared (En = 0).
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QDMA Event Missed Register (QEMR)
For a particular QDMA channel, if two QDMA events are detected without the first event getting
cleared/serviced, the bit corresponding to that channel is set/asserted in the QDMA event missed register
(QEMR). The QEMR bits for a channel are also set if a QDMA event on the channel encounters a NULL
entry (or a NULL TR is serviced). If any QEMR bit is set (and all errors, including bits in other error
registers (EMR/EMRH, CCERR) were previously cleared), the EDMA3CC generates an error interrupt.
See Section 2.9.4 for details on EDMA3CC error interrupt generation.
The QEMR is shown in Figure 4-16 and Figure 4-17 and described in Table 4-15.
Figure 4-16. QDMA Event Missed Register (QEMR) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 4-17. QDMA Event Missed Register (QEMR) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-15. QDMA Event Missed Register (QEMR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
114
Channel 0-7 QDMA event missed for TCI6487/88 devices.
0
No missed event.
1
Missed event occurred.
En
Registers
Channel 0-3 QDMA event missed for TCI6482/86/C6472 devices.
0
No missed event.
1
Missed event occurred.
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4.2.2.4
QDMA Event Missed Clear Register (QEMCR)
Once a missed event is posted in the QDMA event missed registers (QEMR), the bit remains set and you
need to clear the set bit(s). This is done by way of CPU writes to the QDMA event missed clear registers
(QEMCR). Writing a 1 to any of the bits clears the corresponding missed event (bit) in QEMR; writing a 0
has no effect.
The QEMCR is shown in Figure 4-18 and Figure 4-19 and described in Table 4-16.
Figure 4-18. QDMA Event Missed Clear Register (QEMCR) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Figure 4-19. QDMA Event Missed Clear Register (QEMCR) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-16. QDMA Event Missed Clear Register (QEMCR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
QDMA event missed clear. All error bits must be cleared before additional error interrupts will be
asserted by the EDMA3CC for TCI6487/88 devices.
0
No effect.
1
Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0).
En
QDMA event missed clear. All error bits must be cleared before additional error interrupts will be
asserted by the EDMA3CC for TCI6482/86/C6472 devices.
0
No effect.
1
Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0).
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EDMA3CC Error Register (CCERR)
The EDMA3CC error register (CCERR) indicates whether or not at any instant of time the number of
events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set
in the queue watermark threshold register (QWMTHRA). Additionally, CCERR also indicates if when the
number of outstanding TRs that have been programmed to return transfer completion code (TRs which
have the TCINTEN or TCCHEN bit in OPT set) to the EDMA3CC has exceeded the maximum allowed
value of 63. If any bit in CCERR is set (and all errors, including bits in other error registers (EMR/EMRH,
QEMR) were previously cleared), the EDMA3CC generates an error interrupt. See Section 2.9.4 for details
on EDMA3CC error interrupt generation. Once the error bits are set in CCERR, they can only be cleared
by writing to the corresponding bits in the EDMA3CC error clear register (CCERRCLR).
The CCERR is shown in Figure 4-20 and Figure 4-21 and described in Table 4-17.
Figure 4-20. EDMA3CC Error Register (CCERR) for TCI6482/86/C6472 Devices
31
17
16
Reserved
TCCERR
R-0
R-0
15
3
2
1
0
Reserved
4
QTHRXCD3
QTHRXCD2
QTHRXCD1
QTHRXCD0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 4-21. EDMA3CC Error Register (CCERR) for TCI6487/88 Devices
31
17
15
6
16
Reserved
TCCERR
R-0
R-0
5
4
3
2
1
0
Reserved
QTHRXCD5
QTHRXCD4
QTHRXCD3
QTHRXCD2
QTHRXCD1
QTHRXCD0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-17. EDMA3CC Error Register (CCERR) Field Descriptions
Bit
Field
31-17
Reserved
16
TCCERR
Value
0
Description
Reserved
Transfer completion code error. TCCERR is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Total number of allowed TCCs outstanding has not been reached.
1
Total number of allowed TCCs has been reached.
15-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
15-6
Reserved
0
Reserved for TCI6487/88 devices.
5
4
3
116
QTHRXCD5
Queue threshold error for queue 5. QTHRXCD5 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR) for TCI6487/88 devices.
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD4
Queue threshold error for queue 4. QTHRXCD4 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR) for TCI6487/88 devices.
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD3
Registers
Queue threshold error for queue 3. QTHRXCD3 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
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Table 4-17. EDMA3CC Error Register (CCERR) Field Descriptions (continued)
Bit
2
1
0
Field
Value
QTHRXCD2
Description
Queue threshold error for queue 2. QTHRXCD2 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD1
Queue threshold error for queue 1. QTHRXCD1 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD0
Queue threshold error for queue 0. QTHRXCD0 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
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EDMA3CC Error Clear Register (CCERRCLR)
The EDMA3CC error clear register (CCERRCLR) is used to clear any error bits that are set in the
EDMA3CC error register (CCERR). In addition, CCERRCLR also clears the values of some bit fields in
the queue status registers (QSTATn) associated with a particular event queue. Writing a 1 to any of the
bits clears the corresponding bit in CCERR; writing a 0 has no effect.
The CCERRCLR is shown in Figure 4-22 and Figure 4-23 and described in Table 4-18.
Figure 4-22. EDMA3CC Error Clear Register (CCERRCLR) for TCI6482/86/C6472 Devices
31
17
16
Reserved
TCCERR
W-0
W-0
15
3
2
1
0
Reserved
4
QTHRXCD3
QTHRXCD2
QTHRXCD1
QTHRXCD0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Figure 4-23. EDMA3CC Error Clear Register (CCERRCLR) for TCI6487/88 Devices
31
17
15
6
16
Reserved
TCCERR
W-0
W-0
5
4
3
2
1
0
Reserved
QTHRXCD5
QTHRXCD4
QTHRXCD3
QTHRXCD2
QTHRXCD1
QTHRXCD0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-18. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
Bit
Field
31-17
Reserved
16
TCCERR
Value
0
Description
Reserved
Transfer completion code error clear
0
No effect.
1
Clears the TCCERR bit in the EDMA3CC error register (CCERR).
15-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
15-6
Reserved
0
Reserved for TCI6487/88 devices.
5
4
3
2
118
QTHRXCD5
Queue threshold error clear for queue 5 for TCI6487/88 devices.
0
No effect.
1
Clears the QTHRXCD5 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 5 (QSTAT5).
QTHRXCD4
Queue threshold error clear for queue 4 for TCI6487/88 devices.
0
No effect.
1
Clears the QTHRXCD4 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 4 (QSTAT4).
QTHRXCD3
Queue threshold error clear for queue 3.
0
No effect.
1
Clears the QTHRXCD3 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 3 (QSTAT3).
QTHRXCD2
Registers
Queue threshold error clear for queue 2.
0
No effect.
1
Clears the QTHRXCD2 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 2 (QSTAT2).
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Table 4-18. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions (continued)
Bit
1
0
Field
Value
QTHRXCD1
Description
Queue threshold error clear for queue 1.
0
No effect.
1
Clears the QTHRXCD1 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 1 (QSTAT1).
QTHRXCD0
Queue threshold error clear for queue 0.
0
No effect.
1
Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue status register 0 (QSTAT0).
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Error Evaluation Register (EEVAL)
The EDMA3CC error interrupt is asserted whenever an error bit is set in any of the error registers
(EMR/EMRH, QEMR, and CCERR). For subsequent error bits that get set, the EDMA3CC error interrupt
is reasserted only when transitioning from an “all the error bits cleared” to “at least one error bit is set”.
Alternatively, a CPU write of 1 to the EVAL bit in the error evaluation register (EEVAL) results in
reasserting the EDMA3CC error interrupt, if there are any outstanding error bits set due to subsequent
error conditions. Writes of 0 have no effect.
The EEVAL is shown in Figure 4-24 and described in Table 4-19.
Figure 4-24. Error Evaluation Register (EEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
2
Rsvd
EVAL
R-0
R/W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 4-19. Error Evaluation Register (EEVAL) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
Reserved
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0
EVAL
120
Registers
Error interrupt evaluate.
0
No effect.
1
EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers
(EMR/EMRH, QEMR, or CCERR).
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4.2.3 Region Access Enable Registers
The region access enable register group consists of the DMA access enable registers (DRAEm and
DRAEHm) and the QDMA access enable registers (QRAEm). Where m is the number of shadow regions
in the EDMA3CC memory map for a device. You can configure these registers to assign ownership of
DMA/QDMA channels to a particular shadow region.
4.2.3.1
DMA Region Access Enable for Region m (DRAEm)
The DMA region access enable register for shadow region m (DRAEm/DRAEHm) is programmed to allow
or disallow read/write accesses on a bit-by-bit bases for all DMA registers in the shadow region m view of
the DMA channel registers. See the EDMA3CC register memory map (Table 4-1) for a list of all the DMA
channel and interrupt registers mapped in the shadow region view. Additionally, the DRAEm/DRAEHm
configuration determines completion of which DMA channels will result in assertion of the shadow
region m DMA completion interrupt (see Section 2.9).
The DRAEm is shown in Figure 4-25 and described in Table 4-20. The DRAEHm is shown in Figure 4-26
and described in Table 4-20.
Figure 4-25. DMA Region Access Enable Register for Region m (DRAEm)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 4-26. DMA Region Access Enable High Register for Region m (DRAEHm)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 4-20. DMA Region Access Enable Registers for Region M (DRAEm/DRAEHm)
Field Descriptions
Bit
31-0
Field
Value
En
Description
DMA region access enable for bit n/channel n in region m.
0
Accesses via region m address space to bit n in any DMA channel register are not allowed. Reads return
0 on bit n and writes do not modify the state of bit n. Enabled interrupt bits for bit n do not contribute to the
generation of a transfer completion interrupt for shadow region m.
1
Accesses via region m address space to bit n in any DMA channel register are allowed. Reads return the
value from bit n and writes modify the state of bit n. Enabled interrupt bits for bit n contribute to the
generation of a transfer completion interrupt for shadow region m.
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QDMA Region Access Enable Registers (QRAEm)
The QDMA region access enable register for shadow region m (QRAEm) is programmed to allow or
disallow read/write accesses on a bit-by-bit bases for all QDMA registers in the shadow region m view of
the QDMA registers. This includes all 4-bit QDMA registers.
The QRAEm is shown in Figure 4-27 and Figure 4-28 and described in Table 4-21.
Figure 4-27. QDMA Region Access Enable for Region m (QRAEm) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-28. QDMA Region Access Enable for Region m (QRAEm) for TCI6487/88 Devices
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Reserved
E7
E6
E5
E4
E3
E2
E1
E0
R-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-21. QDMA Region Access Enable for Region M (QRAEm) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
122
QDMA region access enable for bit n/QDMA channel n in region m for TCI6487/88 devices.
0
Accesses via region m address space to bit n in any QDMA channel register are not allowed. Reads
return 0 on bit n and writes do not modify the state of bit n.
1
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return
the value from bit n and writes modify the state of bit n.
En
Registers
QDMA region access enable for bit n/QDMA channel n in region m for TCI6482/86/C6472 devices.
0
Accesses via region m address space to bit n in any QDMA channel register are not allowed. Reads
return 0 on bit n and writes do not modify the state of bit n.
1
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return
the value from bit n and writes modify the state of bit n.
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4.2.4 Status/Debug Visibility Registers
The following set of registers provide visibility into the event queues and a TR life cycle. These are useful
for system debug as they provide in-depth visibility for the events queued up in the event queue and also
provide information on what parts of the EDMA3CC logic are active once the event has been received by
the EDMA3CC.
4.2.4.1
Event Queue Entry Registers (QxEy)
The event queue entry registers (QxEy) exist for all 16 queue entries (the maximum allowed queue
entries) for all event queues in the EDMA3CC.
There are Q0E0 to Q0E15, Q1E0 to Q1E15, Q2E0 to Q2E15, and Q3E0 to Q3E15. Each register details
the event number (ENUM) and the event type (ETYPE). For example, if the value in Q1E4 is read as 000
004Fh, this means the 4th entry in queue 1 is a manually-triggered event on DMA channel 15.
The QxEy is shown in Figure 4-29 and described in Table 4-22.
Figure 4-29. Event Queue Entry Registers (QxEy)
31
16
Reserved
R-0
15
8
7
6
5
0
Reserved
ETYPE
ENUM
R-0
R-x
R-x
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 4-22. Event Queue Entry Registers (QxEy) Field Descriptions
Bit
Field
31-8
Reserved
7-6
ETYPE
5-0
ENUM
Value
0
0-3h
ENUM
Reserved
Event entry y in queue x. Specifies the specific event type for the given entry in the event queue.
0
Event triggered via ER.
1h
Manual triggered via ESR.
2h
Chain triggered via CER.
3h
Auto-triggered via QER.
0-3Fh
0-3h
5-0
Description
Event entry y in queue x. Event number:
QDMA channel number (0 to 3 for TCI6482/86/C6472 devices).
0-3Fh
DMA channel/event number (0 to 63).
0-3Fh
Event entry y in queue x. Event number:
0-7h
0-3Fh
QDMA channel number (0 to 7 for TCI6487/88 devices).
DMA channel/event number (0 to 63).
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Queue Status Registers (QSTATn)
The queue status registers (QSTATn) is shown in Figure 4-30 and described in Table 4-23.
Figure 4-30. Queue Status Register n (QSTATn)
31
25
15
13
24
23
21
20
16
Reserved
THRXCD
Reserved
WM
R-0
R-0
R-0
R-0
12
8
7
4
3
0
Reserved
NUMVAL
Reserved
STRTPTR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-23. Queue Status Register n (QSTATn) Field Descriptions
Bit
Field
31-25
Reserved
24
THRXCD
23-21
Reserved
20-16
WM
Value
0
Description
Reserved
Threshold exceeded. THRXCD is cleared by writing a 1 to the corresponding QTHRXCDn bit in
the EDMA3CC error clear register (CCERRCLR).
0
Threshold specified by the Qn bit in the queue watermark threshold register
(QWMTHRA/QWMTHRB) has not been exceeded.
1
Threshold specified by the Qn bit in the queue watermark threshold register
(QWMTHRA/QWMTHRB) has been exceeded.
0
Reserved
0-10h
Watermark for maximum queue usage. Watermark tracks the most entries that have been in
queue n since reset or since the last time that the watermark (WM) bit was cleared. WM is cleared
by writing a 1 to the corresponding QTHRXCDn bit in the EDMA3CC error clear register
(CCERRCLR).
0-10h
Legal values are 0 (empty) to 10h (full).
11h-1Fh
Reserved
15-13
Reserved
0
Reserved
12-8
NUMVAL
0-10h
Number of valid entries in queue n. The total number of entries residing in the queue manager
FIFO at a given instant. Always enabled.
0-10h
Legal values are 0 (empty) to 10h (full).
11h-1Fh
Reserved
Reserved
7-4
Reserved
0
3-0
STRTPTR
0-Fh
124
Registers
Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal
values are 0 (0th entry) to Fh (15th entry).
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4.2.4.3
Queue Watermark Threshold A Register (QWMTHRA)
The queue watermark threshold A register (QWMTHRA) is shown in Figure 4-31 and described in
Table 4-24.
Figure 4-31. Queue Watermark Threshold A Register (QWMTHRA)
31
29
28
24
23
21
20
16
Reserved
Q3
Reserved
Q2
R-0
R/W-10
R-0
R/W-10
15
13
12
8
7
5
4
0
Reserved
Q1
Reserved
Q0
R-0
R/W-10h
R-0
R/W-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-24. Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions
Bit
Field
31-29
Reserved
28-24
Q3
Value
0
Reserved
20-16
Q2
Queue threshold for queue 3 value. The QTHRXCD3 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 3 (QSTAT3) are set when the number of events
in queue 3 at an instant in time (visible via the NUMVAL bit in QSTAT3) equals or exceeds the
value specified by Q3.
0-10h
The default is 16 (maximum allowed).
Reserved
12-8
Q1
Reserved
0
Reserved
0-1Fh
Queue threshold for queue 2 value. The QTHRXCD2 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 2 (QSTAT2) are set when the number of events
in queue 2 at an instant in time (visible via the NUMVAL bit in QSTAT2) equals or exceeds the
value specified by Q2.
0-10h
The default is 16 (maximum allowed).
Reserved
0
Reserved
Queue threshold for queue 1 value. The QTHRXCD1 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 1 (QSTAT1) are set when the number of events
in queue 1 at an instant in time (visible via the NUMVAL bit in QSTAT1) equals or exceeds the
value specified by Q1.
11h
Reserved
4-0
Q0
Disables the threshold errors.
12h-1Fh
0-10h
7-5
Disables the threshold errors.
12h-1Fh
11h
15-13
Reserved
0-1Fh
11h
23-21
Description
The default is 16 (maximum allowed).
Disables the threshold errors.
12h-1Fh
Reserved
0
Reserved
Queue threshold for queue 0 value. The QTHRXCD0 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 0 (QSTAT0) are set when the number of events
in queue 0 at an instant in time (visible via the NUMVAL bit in QSTAT0) equals or exceeds the
value specified by Q0.
0-10h
11h
12h-1Fh
The default is 16 (maximum allowed).
Disables the threshold errors.
Reserved
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Queue Watermark Threshold B Register (QWMTHRB) for TCI6487/88 Devices
The queue watermark threshold B register (QWMTHRB) is shown in Figure 4-32 and described in
Table 4-25.
Figure 4-32. Queue Watermark Threshold B Register (QWMTHRB)
for TCI6487/88 Devices
31
16
Reserved
R-0
15
13
12
8
7
5
4
0
Reserved
Q5
Reserved
Q4
R-0
R/W-10h
R-0
R/W-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-25. Queue Watermark Threshold B Register (QWMTHRB) Field Descriptions for TCI6487/88
Devices
Bit
Field
31-13
Reserved
12-8
Q5
Value
0
11h
Reserved
4-0
Q4
Disables the threshold errors.
Reserved
0
Reserved
Queue threshold for queue 4 value. The QTHRXCD0 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 4 (QSTAT4) are set when the number of events
in queue 4 at an instant in time (visible via the NUMVAL bit in QSTAT4) equals or exceeds the
value specified by Q4.
11h
12h-1Fh
Registers
The default is 16 (maximum allowed).
12h-1Fh
0-10h
126
Reserved
Queue threshold for queue 5 value. The QTHRXCD1 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 5 (QSTAT5) are set when the number of events
in queue 5 at an instant in time (visible via the NUMVAL bit in QSTAT5) equals or exceeds the
value specified by Q5.
0-10h
7-5
Description
The default is 16 (maximum allowed).
Disables the threshold errors.
Reserved
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4.2.4.5
EDMA3CC Status Register (CCSTAT)
The EDMA3CC status register (CCSTAT) has a number of status bits that reflect which parts of the
EDMA3CC logic is active at any given instant of time. The CCSTAT is shown in Figure 4-33 and
Figure 4-34 and described in Table 4-26.
Figure 4-33. EDMA3CC Status Register (CCSTAT) for TCI6482/86/C6472 Devices
31
24
Reserved
R-0
23
20
15
19
18
17
16
Reserved
QUEACTV3
QUEACTV2
QUEACTV1
QUEACTV0
R-0
R-0
R-0
R-0
R-0
14
13
8
Reserved
COMPACTV
R-0
R-0
7
4
3
2
1
0
Reserved
5
ACTV
WSTATACTV
TRACTV
QEVTACTV
EVTACTV
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 4-34. EDMA3CC Status Register (CCSTAT) for TCI6487/88 Devices
31
24
Reserved
R-0
23
21
20
19
18
17
16
Reserved
22
QUEACTV5
QUEACTV4
QUEACTV3
QUEACTV2
QUEACTV1
QUEACTV0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
8
Reserved
COMPACTV
R-0
R-0
7
4
3
2
1
0
Reserved
5
ACTV
WSTATACTV
TRACTV
QEVTACTV
EVTACTV
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-26. EDMA3CC Status Register (CCSTAT) Field Descriptions
Bit
Field
Value
Description
31-20
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-22
Reserved
0
Reserved for TCI6487/88 devices.
21
20
19
QUEACTV5
Queue 5 active for TCI6487/88 devices.
0
No events are queued in queue 5.
1
At least one TR is queued in queue 5.
QUEACTV4
Queue 4 active for TCI6487/88 devices.
0
No events are queued in queue 4.
1
At least one TR is queued in queue 4.
QUEACTV3
Queue 3 active.
0
No events are queued in queue 3.
1
At least one TR is queued in queue 3.
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Table 4-26. EDMA3CC Status Register (CCSTAT) Field Descriptions (continued)
Bit
Field
18
QUEACTV2
17
16
Value
Queue 2 active.
0
No events are queued in queue 2.
1
At least one TR is queued in queue 2.
QUEACTV1
Queue 1 active.
0
No events are queued in queue 1.
1
At least one TR is queued in queue 1.
QUEACTV0
15-14
Reserved
13-8
COMPACTV
Queue 0 active.
0
No events are queued in queue 0.
1
At least one TR is queued in queue 0.
0
Reserved
0-3Fh
0
1h-3Fh
7-5
4
3
2
1
0
128
Reserved
0
ACTV
Completion request active. The COMPACTV field reflects the count for the number of completion
requests submitted to the transfer controllers. This count increments every time a TR is submitted
and is programmed to report completion (the TCINTEN or TCCCHEN bits in OPT in the parameter
entry associated with the TR are set). The counter decrements for every valid TCC received back
from the transfer controllers. If at any time the count reaches a value of 63, the EDMA3CC will not
service any new TRs until the count is less then 63 (or return a transfer completion code from a
transfer controller, which would decrement the count).
No completion requests outstanding.
Total of 1 completion request to 63 completion requests are outstanding.
Reserved
Channel controller active. Channel controller active is a logical-OR of each of the *ACTV bits. The
ACTV bit remains high through the life of a TR.
0
Channel is idle.
1
Channel is busy.
WSTATACTV
Write status interface active.
0
Write status req is idle and write status FIFO is idle.
1
Either the write status request is active or additional write status responses are pending in the write
status FIFO.
TRACTV
Transfer request active.
0
Transfer request processing/submission logic is inactive.
1
Transfer request processing/submission logic is active.
QEVTACTV
QDMA event active.
0
No enabled QDMA events are active within the EDMA3CC.
1
At least one enabled QDMA event (QER) is active within the EDMA3CC.
EVTACTV
Registers
Description
DMA event active.
0
No enabled DMA events are active within the EDMA3CC.
1
At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC.
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4.2.5 Memory Protection Address Space
4.2.5.1
Memory Protection Fault Address Register (MPFAR)
The memory protection fault address register (MPFAR) is shown in Figure 4-35 and described in
Table 4-27. A CPU write of 1 to the MPFCLR bit in the memory protection fault command register
(MPFCR) causes any error conditions stored in MPFAR to be cleared.
Figure 4-35. Memory Protection Fault Address Register (MPFAR)
31
16
FADDR
R-0
15
0
FADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-27. Memory Protection Fault Address Register (MPFAR) Field Descriptions
Bit
31-0
Field
FADDR
Value
0-FFFF FFFFh
Description
Fault address. This 32-bit read-only status register contains the fault address when a memory
protection violation is detected. This register can only be cleared via the memory protection fault
command register (MPFCR).
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Memory Protection Fault Status Register (MPFSR)
The memory protection fault status register (MPFSR) is shown in Figure 4-36 and described in Table 4-28.
A CPU write of 1 to the MPFCLR bit in the memory protection fault command register (MPFCR) causes
any error conditions stored in MPFSR to be cleared.
Figure 4-36. Memory Protection Fault Status Register (MPFSR)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
13
12
FID
9
8
Reserved
6
SRE
SWE
SXE
URE
UWE
UXE
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-28. Memory Protection Fault Status Register (MPFSR) Field Descriptions
Bit
Field
31-13
Reserved
12-9
FID
8-6
Reserved
5
4
3
2
1
0
130
Value
0
0-Fh
0
SRE
Reserved
Faulted identification. FID contains valid information if any of the MP error bits (UXE, UWE, URE, SXE,
SWE, SRE) are nonzero (that is, if an error has been detected.) The FID field contains the privilege ID
for the specific request/requestor that resulted in an MP error.
Reserved
Supervisor read error.
0
No error detected.
1
Supervisor level task attempted to read from a MP page without SR permissions.
SWE
Supervisor write error.
0
No error detected.
1
Supervisor level task attempted to write to a MP page without SW permissions.
SXE
Supervisor execute error.
0
No error detected.
1
Supervisor level task attempted to execute from a MP page without SX permissions.
URE
User read error.
0
No error detected.
1
User level task attempted to read from a MP page without UR permissions.
UWE
User write error.
0
No error detected.
1
User level task attempted to write to a MP page without UW permissions.
UXE
Registers
Description
User execute error.
0
No error detected.
1
User level task attempted to execute from a MP page without UX permissions.
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4.2.5.3
Memory Protection Fault Command Register (MPFCR)
The memory protection fault command register (MPFCR) is shown in Figure 4-37 and described in
Table 4-29.
Figure 4-37. Memory Protection Fault Command Register (MPFCR)
31
16
Reserved
R-0
15
1
0
Reserved
MPFCLR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-29. Memory Protection Fault Command Register (MPFCR) Field Descriptions
Bit
Field
31-1
Reserved
0
MPFCLR
Value
0
Description
Reserved
Fault clear register.
0
CPU write of 0 has no effect.
1
CPU write of 1 to the MPFCLR bit causes any error conditions stored in the memory protection fault
address register (MPFAR) and the memory protection fault status register (MPFSR) to be cleared.
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Memory Protection Page Attribute Register (MPPAG/MPPAn)
The memory protection page attribute register (MPPAn) is shown in Figure 4-38 and described in
Table 4-30.
Figure 4-38. Memory Protection Page Attribute Register (MPPAG/MPPAn)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
EXT
Rsvd
7
Reserved
6
SR
SW
SX
UR
UW
UX
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
RW-1
R-0
RW-1
RW-1
RW-1
RW-0
RW-1
RW-1
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-30. Memory Protection Page Attribute Register (MPPAG/MPPAn) Field Descriptions
Bit
Field
31-16
Reserved
15-10
AIDm
9
Value
0
Description
Reserved
Allowed ID n
0
Requests with Privilege ID == n are not allowed to region m, regardless of permission settings (UW,
UR, SW, SR).
1
Requests with Privilege ID == n are permitted, if access type is allowed as defined by permission
settings (UW, UR, SW, SR).
EXT
External Allowed ID.
0
Requests with Privilege ID >= 6 are not allowed to region m, regardless of permission settings (UW,
UR, SW, SR).
1
Requests with Privilege ID >= 6 are permitted, if access type is allowed as defined by permission
settings (UW, UR, SW, SR).
8
Reserved
0
Reserved
7-6
Reserved
1
Reserved. Always write 1 to this bit.
5
4
3
2
1
0
132
SR
Supervisor read permission
0
Supervisor read accesses are not allowed from region m.
1
Supervisor write accesses are allowed from region m addresses.
SW
Supervisor write permission.
0
Supervisor write accesses are not allowed to region m.
1
Supervisor write accesses are allowed to region n addresses.
SX
Supervisor execute permission.
0
Supervisor execute accesses are not allowed from region m.
1
Supervisor execute accesses are allowed from region m addresses.
UR
User read permission.
0
User read accesses are not allowed from region m.
1
User read accesses are allowed from region n addresses.
UW
User write permission.
0
User write accesses are not allowed to region m.
1
User write accesses are allowed to region m addresses.
UX
Registers
User execute permission.
0
User execute accesses are not allowed from region m.
1
User execute accesses are allowed from region m addresses.
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4.2.6 DMA Channel Registers
The following sets of registers pertain to the 64 DMA channels. The 64 DMA channels consist of a set of
registers (with exception of DMAQNUMn) that each have 64 bits and the bit position of each register
matches the DMA channel number. Each register is named with the format reg_name that corresponds to
DMA channels 0 through 31 and reg_name_High that corresponds to DMA channels 32 through 64.
For example, the event register (ER) corresponds to DMA channel 0 through 31 and the event register
high register (ERH) corresponds to DMA channel 32 through 63. The register is typically called the event
register.
The DMA channel registers are accessible via read/writes to the global address range. They are also
accessible via read/writes to the shadow address range. The read/write ability to the registers in the
shadow region are controlled by the DMA region access registers (DRAEm/DRAEHm). The registers are
described in Section 4.2.3.1 and the details for shadow region/global region usage is explained in
Section 2.7.
4.2.6.1
Event Registers (ER, ERH)
All external events are captured in the event register (ER/ERH). The events are latched even when the
events are not enabled. If the event bit corresponding to the latched event is enabled
(EER.En/EERH.En = 1), then the event is evaluated by the EDMA3CC logic for an associated transfer
request submission to the transfer controllers. The event register bits are automatically cleared
(ER.En/ERH.En = 0) once the corresponding events are prioritized and serviced. If ER.En/ERH.En are
already set and another event is received on the same channel/event, then the corresponding event is
latched in the event miss register (EMR.En/EMRH.En), provided that the event was enabled
(EER.En/EERH.En = 1).
Event n can be cleared by the CPU writing a 1 to corresponding event bit in the event clear register
(ECR/ECRH). The setting of an event is a higher priority relative to clear operations (via hardware or
software). If set and clear conditions occur concurrently, the set condition wins. If the event was previously
set, then EMR/EMRH would be set because an event is lost. If the event was previously clear, then the
event remains set and is prioritized for submission to the event queues.
Table A-1 provides the type of synchronization events and the EDMA3CC channels associated to each of
these external events.
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The ER is shown in Figure 4-39 and described in Table 4-31. The ERH is shown in Figure 4-40 and
described in Table 4-32.
Figure 4-39. Event Register (ER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-31. Event Register (ER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event 0-31. Events 0-31 are captured by the EDMA3CC and are latched into ER. The events are set
(En = 1) even when events are disabled (En = 0 in the event enable register, EER).
0
EDMA3CC event is not asserted.
1
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA
events for submission to the EDMA3TC.
Figure 4-40. Event Register High (ERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-32. Event Register High (ERH) Field Descriptions
Bit
31-0
134
Field
Value
En
Registers
Description
Event 32-63. Events 32-63 are captured by the EDMA3CC and are latched into ERH. The events are set
(En = 1) even when events are disabled (En = 0 in the event enable register high, EERH).
0
EDMA3CC event is not asserted.
1
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA
events for submission to the EDMA3TC.
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4.2.6.2
Event Clear Registers (ECR, ECRH)
Once an event has been posted in the event registers (ER/ERH), the event is cleared in two ways. If the
event is enabled in the event enable register (EER/EERH) and the EDMA3CC submits a transfer request
for the event to the EDMA3TC, it clears the corresponding event bit in the event register. If the event is
disabled in the event enable register (EER/EERH), the CPU can clear the event by way of the event clear
registers (ECR/ECRH).
Writing a 1 to any of the bits clears the corresponding event; writing a 0 has no effect. Once an event bit is
set in the event register, it remains set until EDMA3CC submits a transfer request for that event or the
CPU clears the event by setting the corresponding bit in ECR/ECRH.
The ECR is shown in Figure 4-41 and described in Table 4-33. The ECRH is shown in Figure 4-42 and
described in Table 4-34.
Figure 4-41. Event Clear Register (ECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-33. Event Clear Register (ECR) Field Descriptions
Bit
31-0
Field
Value
Description
En
Event clear for event 0-31. Any of the event bits in ECR is set to clear the event (En) in the event register
(ER). A write of 0 has no effect.
0
No effect.
1
EDMA3CC event is cleared in the event register (ER).
Figure 4-42. Event Clear Register High (ECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-34. Event Clear Register High (ECRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event clear for event 32-63. Any of the event bits in ECRH are set to clear the event (En) in the event
register high (ERH). A write of 0 has no effect.
0
No effect.
1
EDMA3CC event is cleared in the event register high (ERH).
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Event Set Registers (ESR, ESRH)
The event set registers (ESR/ESRH) allow the CPU (EDMA3 programmers) to manually set events to
initiate DMA transfer requests. CPU writes of 1 to any event set register (En) bits set the corresponding
bits in the registers. The set event is evaluated by the EDMA3CC logic for an associated transfer request
submission to the transfer controllers. Writing a 0 has no effect.
The event set registers operate independent of the event registers (ER/ERH), and a write of 1 is always
considered a valid event regardless of whether the event is enabled (the corresponding event bits are set
or cleared in EER.En/EERH.En).
Once the event is set in the event set registers, it cannot be cleared by CPU writes, in other words, the
event clear registers (ECR/ECRH) have no effect on the state of ESR/ESRH. The bits will only be cleared
once the transfer request corresponding to the event has been submitted to the transfer controller. The
setting of an event is a higher priority relative to clear operations (via hardware). If set and clear conditions
occur concurrently, the set condition wins. If the event was previously set, then EMR/EMRH would be set
because an event is lost. If the event was previously clear, then the event remains set and is prioritized for
submission to the event queues.
Manually-triggered transfers via writes to ESR/ESRH allow the CPU to submit DMA requests in the
system, these are relevant for memory-to-memory transfer scenarios. If the ESR.En/ESRH.En bit is
already set and another CPU write of 1 is attempted to the same bit, then the corresponding event is
latched in the event missed registers (EMR.En/EMRH.En = 1).
The ESR is shown in Figure 4-43 and described in Table 4-35. The ESRH is shown in Figure 4-44 and
described in Table 4-36.
Figure 4-43. Event Set Register (ESR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 4-35. Event Set Register (ESR) Field Descriptions
Bit
31-0
136
Field
Value
En
Registers
Description
Event set for event 0-31.
0
No effect.
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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Figure 4-44. Event Set Register High (ESRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 4-36. Event Set Register High (ESRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event set for event 32-63.
0
No effect .
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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Chained Event Registers (CER, CERH)
When the OPTIONS parameter for a PaRAM entry is programmed to returned a chained completion code
(ITCCHEN = 1 and/or TCCHEN = 1), then the value dictated by the TCC[5:0] (also programmed in OPT)
forces the corresponding event bit to be set in the chained event registers (CER/CERH). The set chained
event is evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer
controllers. This results in a chained-triggered transfer.
The chained event registers do not have any enables. The generation of a chained event is essentially
enabled by the PaRAM entry that has been configured for intermediate and/or final chaining on transfer
completion. The En bit is set (regardless of the state of EER.En/EERH.En) when a chained completion
code is returned from one of the transfer controllers or is generated by the EDMA3CC via the early
completion path. The bits in the chained event register are cleared when the corresponding events are
prioritized and serviced.
If the En bit is already set and another chaining completion code is return for the same event, then the
corresponding event is latched in the event missed registers (EMR.En/EMRH.En = 1). The setting of an
event is a higher priority relative to clear operations (via hardware). If set and clear conditions occur
concurrently, the set condition wins. If the event was previously set, then EMR/EMRH would be set
because an event is lost. If the event was previously clear, then the event remains set and is prioritized for
submission to the event queues.
The CER is shown in Figure 4-45 and described in Table 4-37. The CERH is shown in Figure 4-46 and
described in Table 4-38.
Figure 4-45. Chained Event Register (CER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-37. Chained Event Register (CER) Field Descriptions
Bit
31-0
138
Field
Value
En
Registers
Description
Chained event for event 0-31.
0
No effect.
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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Figure 4-46. Chained Event Register High (CERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-38. Chained Event Register High (CERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Chained event set for event 32-63.
0
No effect.
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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Event Enable Registers (EER, EERH)
The EDMA3CC provides the option of selectively enabling/disabling each event in the event registers
(ER/ERH) by using the event enable registers (EER/EERH). If an event bit in EER/EERH is set (using the
event enable set registers, EESR/EESRH), it will enable that corresponding event. Alternatively, if an
event bit in EER/EERH is cleared (using the event enable clear registers, EECR/EECRH), it will disable
the corresponding event.
The event registers latch all events that are captured by EDMA3CC, even if the events are disabled
(although EDMA3CC does not process it). Enabling an event with a pending event already set in the event
registers enables the EDMA3CC to process the already set event like any other new event. The
EER/EERH settings do not have any effect on chained events (CER.En/CERH.En = 1) and manually set
events (ESR.En/ESRH.En = 1).
The EER is shown in Figure 4-47 and described in Table 4-39. Th EERH is shown in Figure 4-48 and
described in Table 4-40.
Figure 4-47. Event Enable Register (EER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-39. Event Enable Register (EER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable for events 0-31.
0
Event is not enabled. An external event latched in the event register (ER) is not evaluated by the
EDMA3CC.
1
Event is enabled. An external event latched in the event register (ER) is evaluated by the EDMA3CC.
Figure 4-48. Event Enable Register High (EERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-40. Event Enable Register High (EERH) Field Descriptions
Bit
31-0
140
Field
Value
En
Registers
Description
Event enable for events 32-63.
0
Event is not enabled. An external event latched in the event register high (ERH) is not evaluated by the
EDMA3CC.
1
Event is enabled. An external event latched in the event register high (ERH) is evaluated by the
EDMA3CC.
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4.2.6.6
Event Enable Clear Register (EECR, EECRH)
The event enable registers (EER/EERH) cannot be modified by directly writing to them. The intent is to
ease the software burden for the case where multiple tasks are attempting to simultaneously modify these
registers. The event enable clear registers (EECR/EECRH) are used to disable events. Writes of 1 to the
bits in EECR/EECRH clear the corresponding event bits in EER/EERH; writes of 0 have no effect.
The EECR is shown in Figure 4-49 and described in Table 4-41. The EECRH is shown in Figure 4-50 and
described in Table 4-42.
Figure 4-49. Event Enable Clear Register (EECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-41. Event Enable Clear Register (EECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable clear for events 0-31.
0
No effect.
1
Event is disabled. Corresponding bit in the event enable register (EER) is cleared (En = 0).
Figure 4-50. Event Enable Clear Register High (EECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-42. Event Enable Clear Register High (EECRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable clear for events 32-63.
0
No effect.
1
Event is disabled. Corresponding bit in the event enable register high (EERH) is cleared (En = 0).
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Event Enable Set Registers (EESR, EESRH)
The event enable registers (EER/EERH) cannot be modified by directly writing to them. The intent is to
ease the software burden for the case where multiple tasks are attempting to simultaneously modify these
registers. The event enable set registers (EESR/EESRH) are used to enable events. Writes of 1 to the bits
in EESR/EESRH set the corresponding event bits in EER/EERH; writes of 0 have no effect.
The EESR is shown in Figure 4-51 and described in Table 4-43. The EESRH is shown in Figure 4-52 and
described in Table 4-44.
Figure 4-51. Event Enable Set Register (EESR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-43. Event Enable Set Register (EESR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable set for events 0-31.
0
No effect.
1
Event is enabled. Corresponding bit in the event enable register (EER) is set (En = 1).
Figure 4-52. Event Enable Set Register High (EESRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-44. Event Enable Set Register High (EESRH) Field Descriptions
Bit
31-0
142
Field
Value
En
Registers
Description
Event enable set for events 32-63.
0
No effect.
1
Event is enabled. Corresponding bit in the event enable register high (EERH) is set (En = 1).
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4.2.6.8
Secondary Event Registers (SER, SERH)
The secondary event registers (SER/SERH) provide information on the state of a DMA channel or event
(0 through 63). If the EDMA3CC receives a TR synchronization due to a manual-trigger, event-trigger, or
chained-trigger source (ESR.En/ESRH.En = 1, ER.En/ERH.En = 1, or CER.En/CERH.En = 1), which
results in the setting of a corresponding event bit in SER/SERH (SER.En/SERH.En = 1), it implies that the
corresponding DMA event is in the queue.
Once a bit corresponding to an event is set in SER/SERH, the EDMA3CC does not prioritize additional
events on the same DMA channel. Depending on the condition that lead to the setting of the SER bits,
either the EDMA3CC hardware or the software (using SECR/SECRH) needs to clear the SER/SERH bits
for the EDMA3CC to evaluate subsequent events (subsequent transfers) on the same channel. See
Section 1.1 for additional conditions that can cause the secondary event registers to be set.
The SER is shown in Figure 4-53 and described in Table 4-45. The SERH is shown in Figure 4-54 and
described in Table 4-46.
Figure 4-53. Secondary Event Register (SER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-45. Secondary Event Register (SER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Secondary event register. The secondary event register is used along with the event register (ER) to
provide information on the state of an event.
0
Event is not currently stored in the event queue.
1
Event is currently stored in the event queue. Event arbiter will not prioritize additional events.
Figure 4-54. Secondary Event Register High (SERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-46. Secondary Event Register High (SERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Secondary event register. The secondary event register is used along with the event register high (ERH)
to provide information on the state of an event.
0
Event is not currently stored in the event queue.
1
Event is currently stored in the event queue. Event submission/prioritization logic will not prioritize
additional events.
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Secondary Event Clear Registers (SECR, SECRH)
The secondary event clear registers (SECR/SECRH) clear the status of the secondary event registers
(SER/SERH). CPU writes of 1 clear the corresponding set bits in SER/SERH. Writes of 0 have no effect.
The SECR is shown in Figure 4-55 and described in Table 4-47. The SECRH is shown in Figure 4-56 and
described in Table 4-48.
Figure 4-55. Secondary Event Clear Register (SECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-47. Secondary Event Clear Register (SECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Secondary event clear register
0
No effect.
1
Corresponding bit in the secondary event register (SER) is cleared (En = 0).
Figure 4-56. Secondary Event Clear Register High (SECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-48. Secondary Event Clear Register High (SECRH) Field Descriptions
Bit
31-0
144
Field
Value
En
Registers
Description
Secondary event clear register.
0
No effect.
1
Corresponding bit in the secondary event registers high (SERH) is cleared (En = 0).
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4.2.7 Interrupt Registers
All DMA/QDMA channels can be set to assert an EDMA3CC completion interrupt to the CPU on transfer
completion, by appropriately configuring the PaRAM entry associated with the channels. The following set
of registers is used for the transfer completion interrupt reporting/generating by the EDMA3CC. See
Section 2.9 for more details on EDMA3CC completion interrupt generation.
4.2.7.1
Interrupt Enable Registers (IER, IERH)
Interrupt enable registers (IER/IERH) are used to enable/disable the transfer completion interrupt
generation by the EDMA3CC for all DMA/QDMA channels. The IER/IERH cannot be written to directly. To
set any interrupt bit in IER/IERH, a 1 must be written to the corresponding interrupt bit in the interrupt
enable set registers (IESR/IESRH). Similarly, to clear any interrupt bit in IER/IERH, a 1 must be written to
the corresponding interrupt bit in the interrupt enable clear registers (IECR/IECRH).
The IER is shown in Figure 4-57 and described in Table 4-49. The IERH is shown in Figure 4-58 and
described in Table 4-50.
Figure 4-57. Interrupt Enable Register (IER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27I
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-49. Interrupt Enable Register (IER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable for channels 0-31.
0
Interrupt is not enabled.
1
Interrupt is enabled.
Figure 4-58. Interrupt Enable Register High (IERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-50. Interrupt Enable Register High (IERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable for channels 32-63.
0
Interrupt is not enabled.
1
Interrupt is enabled.
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Interrupt Enable Clear Register (IECR, IECRH)
The interrupt enable clear registers (IECR/IECRH) are used to clear interrupts. Writes of 1 to the bits in
IECR/IECRH clear the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0
have no effect.
The IECR is shown in Figure 4-59 and described in Table 4-51. The IECRH is shown in Figure 4-60 and
described in Table 4-52.
Figure 4-59. Interrupt Enable Clear Register (IECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
16
16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-51. Interrupt Enable Clear Register (IECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable clear for channels 0-31.
0
No effect
1
Corresponding bit in the interrupt enable register (IER) is cleared (In = 0).
Figure 4-60. Interrupt Enable Clear Register High (IECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-52. Interrupt Enable Clear Register High (IECRH) Field Descriptions
Bit
31-0
146
Field
Value
En
Registers
Description
Interrupt enable clear for channels 32-63.
0
No effect.
1
Corresponding bit in the interrupt enable register high (IERH) is cleared (In = 0).
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4.2.7.3
Interrupt Enable Set Registers (IESR, IESRH)
The interrupt enable set registers (IESR/IESRH) are used to enable interrupts. Writes of 1 to the bits in
IESR/IESRH set the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0
have no effect.
The IESR is shown in Figure 4-61 and described in Table 4-53. The IESRH is shown in Figure 4-62 and
described in Table 4-54.
Figure 4-61. Interrupt Enable Set Register (IESR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
II8
I17
I16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-53. Interrupt Enable Set Register (IESR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable set for channels 0-31.
0
No effect.
1
Corresponding bit in the interrupt enable register (IER) is set (In = 1).
Figure 4-62. Interrupt Enable Set Register High (IESRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-54. Interrupt Enable Set Register High (IESRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable clear for channels 32-63.
0
No effect.
1
Corresponding bit in the interrupt enable register high (IERH) is set (In = 1).
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Interrupt Pending Register (IPR, IPRH)
If the TCINTEN and/or ITCINTEN bit in the channel option parameter (OPT) is set in the PaRAM entry
associated with the channel (DMA or QDMA), then the EDMA3TC (for normal completion) or the
EDMA3CC (for early completion) returns a completion code on transfer or intermediate transfer
completion. The value of the returned completion code is equal to the TCC bit in OPT for the PaRAM
entry associated with the channel.
When an interrupt transfer completion code with TCC = n is detected by the EDMA3CC, then the
corresponding bit is set in the interrupt pending register (IPR.In, if n = 0 to 31; IPRH.In, if n = 32 to 63).
Note that once a bit is set in the interrupt pending registers, it remains set; it is your responsibility to clear
these bits. The bits set in IPR/IPRH are cleared by writing a 1 to the corresponding bits in the interrupt
clear registers (ICR/ICRH).
The IPR is shown in Figure 4-63 and described in Table 4-55. The IPRH is shown in Figure 4-64 and
described in Table 4-56.
Figure 4-63. Interrupt Pending Register (IPR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-55. Interrupt Pending Register (IPR) Field Descriptions
Bit
31-0
Field
Value
In
Description
Interrupt pending for TCC = 0-31.
0
Interrupt transfer completion code is not detected or was cleared.
1
Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
Figure 4-64. Interrupt Pending Register High (IPRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-56. Interrupt Pending Register High (IPRH) Field Descriptions
Bit
31-0
148
Field
Value
In
Registers
Description
Interrupt pending for TCC = 32-63.
0
Interrupt transfer completion code is not detected or was cleared.
1
Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
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4.2.7.5
Interrupt Clear Registers (ICR, ICRH)
The bits in the interrupt pending registers (IPR/IPRH) are cleared by writing a 1 to the corresponding bits
in the interrupt clear registers(ICR/ICRH). Writes of 0 have no effect. All set bits in IPR/IPRH must be
cleared to allow EDMA3CC to assert additional transfer completion interrupts.
The ICR is shown in Figure 4-65 and described in Table 4-57. The ICRH is shown in Figure 4-66 and
described in Table 4-58.
Figure 4-65. Interrupt Clear Register (ICR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-57. Interrupt Clear Register (ICR) Field Descriptions
Bit
31-0
Field
Value
In
Description
Interrupt clear register for TCC = 0-31.
0
No effect.
1
Corresponding bit in the interrupt pending register (IPR) is cleared (In = 0).
Figure 4-66. Interrupt Clear Register High (ICRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 4-58. Interrupt Clear Register High (ICRH) Field Descriptions
Bit
31-0
Field
Value
In
Description
Interrupt clear register for TCC = 32-63.
0
No effect.
1
Corresponding bit in the interrupt pending register high (IPRH) is cleared (In = 0).
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Interrupt Evaluate Register (IEVAL)
The interrupt evaluate register (IEVAL) is the only register that physically exists in both the global region
and the shadow regions. In other words, the read/write accessibility for the shadow region IEVAL is not
affected by the DMA/QDMA region access registers (DRAEm/DRAEHm, QRAEn/QRAEHn). IEVAL is
needed for robust ISR operations to ensure that interrupts are not missed by the CPU.
The IEVAL is shown in Figure 4-67 and described in Table 4-59.
Figure 4-67. Interrupt Evaluate Register (IEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
2
Rsvd
EVAL
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-59. Interrupt Evaluate Register (IEVAL) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
Reserved
0
Reserved. Always write 0. Writes of 1 to this bit are not supported and attempts to do so may result in
undefined behavior.
0
EVAL
Interrupt evaluate
0
No effect.
1
Causes EDMA3CC completion interrupt to be pulsed, if any enabled (IERn/IERHn = 1) interrupts are
still pending (IPRn/IPRHn = 1).
The EDMA3CC completion interrupt that is pulsed depends on which IEVAL is being exercised. For
example, writing to the EVAL bit in IEVAL pulses the global completion interrupt, but writing to the EVAL
bit in IEVAL0 pulses the region 0 completion interrupt.
150
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4.2.8 QDMA Registers
The following sets of registers control the QDMA channels in the EDMA3CC. The QDMA channels (with
the exception of the QDMA queue number register) consist of a set of registers, each of which have a bit
location. Each bit position corresponds to a QDMA channel number. The QDMA channel registers are
accessible via read/writes to the global address range. They are also accessible via read/writes to the
shadow address range. The read/write accessibility in the shadow region address region is controlled by
the QDMA region access registers (QRAEn/QRAEHn). Section 2.7 details shadow region/global region
usage.
4.2.8.1
QDMA Event Register (QER)
The QDMA event register (QER) channel n bit is set (En = 1) when the CPU or any EDMA3 programmer
(including EDMA3) performs a write to the trigger word (using the QDMA channel mapping register
(QCHMAPn)) in the PaRAM entry associated with QDMA channel n (which is also programmed using
QCHMAPn). The En bit is also set when the EDMA3CC performs a link update on a PaRAM address that
matches the QCHMAPn settings. The QDMA event is latched only if the QDMA event enable register
(QEER) channel n bit is also enabled (QEER.En = 1). Once a bit is set in QER, then the corresponding
QDMA event (auto-trigger) is evaluated by the EDMA3CC logic for an associated transfer request
submission to the transfer controllers. See Section 1.1 for additional conditions that can lead to the setting
of QER bits.
The setting of an event is a higher priority relative to clear operations (via hardware). If set and clear
conditions occur concurrently, the set condition wins. If the event was previously set, then the QDMA
event missed register (QEMR) would be set because an event is lost. If the event was previously clear,
then the event remains set and is prioritized for submission to the event queues.
The set bits in QER are only cleared when the transfer request associated with the corresponding
channels has been processed by the EDMA3CC and submitted to the transfer controller. If the En bit is
already set and a QDMA event for the same QDMA channel occurs prior to the original being cleared,
then the second missed event is latched in QEMR (En = 1).
The QER is shown in Figure 4-68 and Figure 4-69 and described in Table 4-60.
Figure 4-68. QDMA Event Register (QER) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 4-69. QDMA Event Register (QER) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-60. QDMA Event Register (QER) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
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Table 4-60. QDMA Event Register (QER) Field Descriptions (continued)
Bit
Field
7-0
En
3-0
152
Value
QDMA event for channels 0-7 for TCI6487/88 devices.
0
No effect.
1
Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to
the EDMA3TC.
En
Registers
Description
QDMA event for channels 0-3 for TCI6482/86/C6472 devices.
0
No effect.
1
Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to
the EDMA3TC.
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4.2.8.2
QDMA Event Enable Register (QEER)
The EDMA3CC provides the option of selectively enabling/disabling each channel in the QDMA event
register (QER) by using the QDMA event enable register (QEER). If any of the event bits in QEER is set
(using the QDMA event enable set register, QEESR), it will enable that corresponding event. Alternatively,
if any event bit in QEER is cleared (using the QDMA event enable clear register, QEECR), it will disable
the corresponding QDMA channel. The QDMA event register will not latch any event for a QDMA channel,
if it is not enabled via QEER.
The QEER is shown in Figure 4-70 and Figure 4-71 and described in Table 4-61.
Figure 4-70. QDMA Event Enable Register (QEER) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 4-71. QDMA Event Enable Register (QEER) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-61. QDMA Event Enable Register (QEER) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
QDMA event enable for channels 0-7 for TCI6487/88 devices.
0
QDMA channel n is not enabled. QDMA event is not recognized and is not latched in the QDMA event
register (QER).
1
QDMA channel n is enabled. QDMA events are recognized and are latched in the QDMA event register
(QER).
En
QDMA event enable for channels 0-3 for TCI6482/86/C6472 devices.
0
QDMA channel n is not enabled. QDMA event is not recognized and is not latched in the QDMA event
register (QER).
1
QDMA channel n is enabled. QDMA events are recognized and are latched in the QDMA event register
(QER).
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QDMA Event Enable Clear Register (QEECR)
The QDMA event enable register (QEER) cannot be modified by directly writing to the register, to ease the
software burden when multiple tasks are attempting to simultaneously modify these registers. The QDMA
event enable clear register (QEECR) is used to disable events. Writes of 1 to the bits in QEECR clear the
corresponding QDMA channel bits in QEER; writes of 0 have no effect.
The QEECR is shown in Figure 4-72 and Figure 4-73 and described in Table 4-62.
Figure 4-72. QDMA Event Enable Clear Register (QEECR) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Figure 4-73. QDMA Event Enable Clear Register (QEECR) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-62. QDMA Event Enable Clear Register (QEECR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
154
QDMA event enable clear for channels 0-7 for TCI6487/88 devices.
0
No effect.
1
QDMA event is disabled. Corresponding bit in the QDMA event enable register (QEER) is cleared (En =
0).
En
Registers
QDMA event enable clear for channels 0-3 for TCI6482/86/C6472 devices.
0
No effect.
1
QDMA event is disabled. Corresponding bit in the QDMA event enable register (QEER) is cleared (En =
0).
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4.2.8.4
QDMA Event Enable Set Register (QEESR)
The QDMA event enable register (QEER) cannot be modified by directly writing to the register, to ease the
software burden when multiple tasks are attempting to simultaneously modify these registers. The QDMA
event enable set register (QEESR) is used to enable events. Writes of 1 to the bits in QEESR set the
corresponding QDMA channel bits in QEER; writes of 0 have no effect.
The QEESR is shown in Figure 4-74 and Figure 4-75 and described in Table 4-63.
Figure 4-74. QDMA Event Enable Set Register (QEESR) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Figure 4-75. QDMA Event Enable Set Register (QEESR) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-63. QDMA Event Enable Set Register (QEESR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
QDMA event enable set for channels 0-7 for TCI6487/88 devices.
0
No effect.
1
QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1).
En
QDMA event enable set for channels 0-3 for TCI6482/86/C6472 devices.
0
No effect.
1
QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1).
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QDMA Secondary Event Register (QSER)
The QDMA secondary event register (QSER) provides information on the state of a QDMA event. If at any
time a bit corresponding to a QDMA channel is set in QSER, that implies that the corresponding QDMA
event is in the queue. Once a bit corresponding to a QDMA channel is set in QSER, the EDMA3CC does
not prioritize additional events on the same QDMA channel. Depending on the condition that lead to the
setting of the QSER bits, either the EDMA3CC hardware or the software (using QSECR) needs to clear
the QSER bits for the EDMA3CC to evaluate subsequent QDMA events on the channel. Based on
whether the associated TR request is valid, or it is a null or dummy TR, the implications on the state of
QSER and the required user actions to submit another QDMA transfer might be different. See Section 1.1
for additional conditions that can cause the secondary event registers (QSER/SER) to be set.
The QSER is shown in Figure 4-76 and Figure 4-77 and described in Table 4-64.
Figure 4-76. QDMA Secondary Event Register (QSER) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 4-77. QDMA Secondary Event Register (QSER) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-64. QDMA Secondary Event Register (QSER) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
156
QDMA secondary event register for channels 0-7 for TCI6487/88 devices.
0
QDMA event is not currently stored in the event queue.
1
QDMA event is currently stored in the event queue. EDMA3CC does not prioritize additional events.
En
Registers
QDMA secondary event register for channels 0-3 for TCI6482/86/C6472 devices.
0
QDMA event is not currently stored in the event queue.
1
QDMA event is currently stored in the event queue. EDMA3CC does not prioritize additional events.
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4.2.8.6
QDMA Secondary Event Clear Register (QSECR)
The QDMA secondary event clear register (QSECR) clears the status of the QDMA secondary event
register (QSER) and the QDMA event register (QER). CPU writes of 1 clear the corresponding set bits in
QSER and QER. Writes of 0 have no effect. Note that this differs from the secondary event clear register
(SECR) operation, which only clears the secondary event register (SER) bits and does not affect the event
registers.
The QSECR is shown in Figure 4-78 and Figure 4-79 and described in Table 4-65.
Figure 4-78. QDMA Secondary Event Clear Register (QSECR) for TCI6482/86/C6472 Devices
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Figure 4-79. QDMA Secondary Event Clear Register (QSECR) for TCI6487/88 Devices
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-65. QDMA Secondary Event Clear Register (QSECR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved for TCI6482/86/C6472 devices.
31-8
Reserved
0
Reserved for TCI6487/88 devices.
7-0
En
3-0
QDMA secondary event clear for channels 0-7 for TCI6487/88 devices.
0
No effect.
1
Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER)
is cleared (En = 0).
En
QDMA secondary event clear for channels 0-3 for TCI6482/86/C6472 devices.
0
No effect.
1
Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER)
is cleared (En = 0).
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EDMA3 Transfer Controller Control Registers
Table 4-66 lists the memory-mapped registers for the EDMA3 transfer controller (EDMA3TC). See the
device-specific data manual for the memory address of these registers.
Table 4-66. EDMA3 Transfer Controller Registers
Offset
Acronym
Register Description
See
00h
PID
Peripheral Identification Register
Section 4.3.1
04h
TCCFG
EDMA3TC Configuration Register
Section 4.3.2
0100h
TCSTAT
EDMA3TC Channel Status Register
Section 4.3.3
0120h
ERRSTAT
Error Register
Section 4.3.4.1
0124h
ERREN
Error Enable Register
Section 4.3.4.2
0128h
ERRCLR
Error Clear Register
Section 4.3.4.3
012Ch
ERRDET
Error Details Register
Section 4.3.4.4
0130h
ERRCMD
Error Interrupt Command Register
Section 4.3.4.5
0140h
RDRATE
Read Rate Register
0240h
SAOPT
Source Active Options Register
Section 4.3.6.1
0244h
SASRC
Source Active Source Address Register
Section 4.3.6.2
0248h
SACNT
Source Active Count Register
Section 4.3.6.3
024Ch
SADST
Source Active Destination Address Register
Section 4.3.6.4
0250h
SABIDX
Source Active Source B-Index Register
Section 4.3.6.5
0254h
SAMPPRXY
Source Active Memory Protection Proxy Register
Section 4.3.6.6
0258h
SACNTRLD
Source Active Count Reload Register
Section 4.3.6.7
025Ch
SASRCBREF
Source Active Source Address B-Reference Register
Section 4.3.6.8
0260h
SADSTBREF
Source Active Destination Address B-Reference Register
Section 4.3.6.9
0280h
DFCNTRLD
Destination FIFO Set Count Reload
Section 4.3.6.16
0284h
DFSRCBREF
Destination FIFO Set Destination Address B Reference Register
Section 4.3.6.17
0288h
DFDSTBREF
Destination FIFO Set Destination Address B Reference Register
Section 4.3.6.18
0300h
DFOPT0
Destination FIFO Options Register 0
Section 4.3.6.10
0304h
DFSRC0
Destination FIFO Source Address Register 0
Section 4.3.6.11
Section 4.3.5
0308h
DFCNT0
Destination FIFO Count Register 0
Section 4.3.6.12
030Ch
DFDST0
Destination FIFO Destination Address Register 0
Section 4.3.6.13
0310h
DFBIDX0
Destination FIFO BIDX Register 0
Section 4.3.6.14
0314h
DFMPPRXY0
Destination FIFO Memory Protection Proxy Register 0
Section 4.3.6.15
0340h
DFOPT1
Destination FIFO Options Register 1
Section 4.3.6.10
0344h
DFSRC1
Destination FIFO Source Address Register 1
Section 4.3.6.11
0348h
DFCNT1
Destination FIFO Count Register 1
Section 4.3.6.12
034Ch
DFDST1
Destination FIFO Destination Address Register 1
Section 4.3.6.13
0350h
DFBIDX1
Destination FIFO BIDX Register 1
Section 4.3.6.14
0354h
DFMPPRXY1
Destination FIFO Memory Protection Proxy Register 1
Section 4.3.6.15
0380h
DFOPT2
Destination FIFO Options Register 2
Section 4.3.6.10
0384h
DFSRC2
Destination FIFO Source Address Register 2
Section 4.3.6.11
0388h
DFCNT2
Destination FIFO Count Register 2
Section 4.3.6.12
038Ch
DFDST2
Destination FIFO Destination Address Register 2
Section 4.3.6.13
0390h
DFBIDX2
Destination FIFO BIDX Register 2
Section 4.3.6.14
0394h
DFMPPRXY2
Destination FIFO Memory Protection Proxy Register 2
Section 4.3.6.15
03C0h
DFOPT3
Destination FIFO Options Register 3
Section 4.3.6.10
03C4h
DFSRC3
Destination FIFO Source Address Register 3
Section 4.3.6.11
03C8h
DFCNT3
Destination FIFO Count Register 3
Section 4.3.6.12
03CCh
DFDST3
Destination FIFO Destination Address Register 3
Section 4.3.6.13
03D0h
DFBIDX3
Destination FIFO BIDX Register 3
Section 4.3.6.14
158 Registers
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Table 4-66. EDMA3 Transfer Controller Registers (continued)
Offset
Acronym
Register Description
03D4h
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
See
Section 4.3.6.15
4.3.1 Peripheral Identification Register (PID)
The peripheral identification register (PID) is a constant register that uniquely identifies the EDMA3TC and
specific revision of the EDMA3TC. The PID is shown in Figure 4-80 and described in Table 4-67.
Figure 4-80. Peripheral ID Register (PID)
31
16
PID
(A)
15
0
PID
(B)
LEGEND: R = Read only; -n = value after reset
A. R-0333h for TCI6482/86/C6472 devices; R-4000h for TCI6487/88 devices
B. R-4425h for TCI6482/86/C6472 devices; R-3300h for TCI6487/88 devices
Table 4-67. Peripheral ID Register (PID) Field Descriptions
Bit
31-0
Field
PID
Value
0-FFFF FFFFh
Description
Peripheral identifier.
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4.3.2 EDMA3TC Configuration Register (TCCFG)
The EDMA3TC configuration register (TCCFG) is shown in Figure 4-81 and described in Table 4-68.
Figure 4-81. EDMA3TC Configuration Register (TCCFG)
31
16
Reserved
R-0
15
10
9
8
7
6
5
4
3
2
0
Reserved
DREGDEPTH
Reserved
BUSWIDTH
Rsvd
FIFOSIZE
R-0
R-x
R-0
R-0x00000223
R-0
R-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 4-68. EDMA3TC Configuration Register (TCCFG) Field Descriptions
Bit
31-10
9-8
Field
Reserved
DREGDEPTH
7-6
Reserved
5-4
BUSWIDTH
Value
0
0-3h
Description
Reserved
Destination register FIFO depth parameterization.
0
Reserved
1h
2 entry (for TC0) for TCI6482/86/C6472 devices;
Reserved for TCI6487/88 devices
2h
4 entry (for TC0, TC1, and TC3) for TCI6482/86/C6472 devices;
4 entry (for TC0-TC5) for TCI6487/88 devices
3h
Reserved
0
Reserved
0-3h
Bus width parameterization.
0
Reserved
1h
Reserved for TCI6482/86/C6472 devices;
64-bit (for TC0, TC1, and TC2) for TCI6487/88 devices
2h
128-bit (for TC0-TC3) for TCI6482/86/C6472 devices;
128-bit (for TC3, TC4, and TC5) for TCI6487/88 devices
3h
Reserved
3
Reserved
0
Reserved
2-0
FIFOSIZE
0-7h
FIFO size.
0-1h
Reserved
2h
128-byte FIFO (for TC0, TC1, and TC2) for TCI6482/86/C6472 devices;
Reserved for TCI6487/88 devices
3h
256-byte FIFO (for TC3) for TCI6482/86/C6472 devices;
256-byte FIFO (for TC0-TC5) for TCI6487/88 devices
4h-7h
160
Registers
Reserved
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4.3.3 EDMA3TC Channel Status Register (TCSTAT)
The EDMA3TC channel status register (TCSTAT) is shown in Figure 4-82 and described in Table 4-69.
Figure 4-82. EDMA3TC Channel Status Register (TCSTAT)
31
16
Reserved
R-0
15
14
13
12
11
9
8
Reserved
DFSTRTPTR
Reserved
Reserved
R-0
R-0
R-0
R-1
3
2
1
0
Reserved
7
6
DSTACTV
4
Reserved
WSACTV
SRCACTV
PROGBUSY
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-69. EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
Bit
Field
31-14
Reserved
13-12
DFSTRTPTR
Value
0
Description
Reserved
0-3h
Destination FIFO start pointer. Represents the offset to the head entry of the destination register FIFO,
in units of entries.
0
TCI6482/86/C6472: For TC1,TC2 ,TC3: if the destination register FIFO depth parameterization is 4. For
TC0: if the destination register FIFO depth parameterization is 2.
TCI6487/88: For TC0-TC5: if the destination register FIFO depth parameterization is 4.
1h
TCI6482/86/C6472: For TC1,TC2 ,TC3: if the destination register FIFO depth parameterization is 4. For
TC0: if the destination register FIFO depth parameterization is 2.
TCI6487/88: For TC0-TC5: if the destination register FIFO depth parameterization is 4.
2h
TCI6482/86/C6472: For TC1,TC2 ,TC3: if the destination register FIFO depth parameterization is 4.
TCI6487/88: For TC0-TC5: if the destination register FIFO depth parameterization is 4.
3h
TCI6482/86/C6472: For TC1,TC2 ,TC3: if the destination register FIFO depth parameterization is 4.
TCI6487/88: For TC0-TC5: if the destination register FIFO depth parameterization is 4.
11-9
Reserved
0
Reserved
8
Reserved
1
Reserved. Always read as 1.
7
Reserved
0
Reserved
6-4
DSTACTV
0-7h
Destination active state. Specifies the number of transfer requests (TRs) that are resident in the
destination register FIFO at a given instant. This bit field can be primarily used for advanced debugging.
Legal values are constrained by the destination register FIFO depth parameterization (DSTREGDEPTH)
parameter.
0
Destination FIFO is empty.
1h
Destination FIFO contains 1 TR.
2h
Destination FIFO contains 2 TRs. (Full if DSTREGDEPTH == 2)
3h
Destination FIFO contains 3 TRs.
4h
Destination FIFO contains 4 TRs. (Full if DSTREGDEPTH==4)
If the destination register FIFO is empty, then any TR written to Prog Set immediately transitions to the
destination register FIFO. If the destination register FIFO is not empty and not full, then any TR written
to Prog Set immediately transitions to the destination register FIFO set if the source active state
(SRCACTV) bit is set to idle.
If the destination register FIFO is full, then TRs cannot transition to the destination register FIFO. The
destination register FIFO becomes not full when the TR at the head of the destination register FIFO is
completed.
3
Reserved
2
WSACTV
5h-7h
Reserved
0
Reserved
Write status active.
0
Write status is not pending. Write status has been received for all previously issued write commands.
1
Write status is pending. Write status has not been received for all previously issued write commands.
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Table 4-69. EDMA3TC Channel Status Register (TCSTAT) Field Descriptions (continued)
Bit
1
0
162
Field
Value
SRCACTV
Source active state.
0
Source controller is idle. Source active register set contains a previously processed transfer request.
1
Source controller is busy servicing a transfer request.
PROGBUSY
Registers
Description
Program register set busy.
0
Program set idle and is available for programming by the EDMA3CC.
1
Program set busy.
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4.3.4 Error Registers
4.3.4.1
Error Register (ERRSTAT)
The error status register (ERRSTAT) is shown in Figure 4-83 and described in Table 4-70.
Figure 4-83. Error Register (ERRSTAT)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
MMRAERR
TRERR
Reserved
BUSERR
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-70. Error Register (ERRSTAT) Field Descriptions
Bit
31-4
3
2
Field
Reserved
Value
0
MMRAERR
Reserved
0
BUSERR
Reserved
MMR address error.
0
Condition is not detected
1
User attempted to read or write to an invalid address in configuration memory map.
TRERR
1
Description
Transfer request (TR) error event.
0
Condition is not detected.
1
TR detected that violates constant addressing mode transfer (SAM or DAM is set) alignment rules or
has ACNT or BCNT == 0.
0
Reserved
Bus error event.
0
Condition is not detected.
1
EDMA3TC has detected an error at source or destination address. Error information can be read from
the error details register (ERRDET).
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Error Enable Register (ERREN)
The error enable register (ERREN) is shown in Figure 4-84 and described in Table 4-71.
When any of the enable bits are set, a bit set in the corresponding ERRSTAT causes an assertion of the
EDMA3TC interrupt.
Figure 4-84. Error Enable Register (ERREN)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
MMRAERR
TRERR
Reserved
BUSERR
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-71. Error Enable Register (ERREN) Field Descriptions
Bit
31-4
3
2
164
Field
Reserved
Value
0
MMRAERR
Reserved
0
BUSERR
Registers
Reserved
Interrupt enable for MMR address error (MMRAERR).
0
MMRAERR is disabled.
1
MMRAERR is enabled and contributes to the state of EDMA3TC error interrupt generation
TRERR
1
Description
Interrupt enable for transfer request error (TRERR).
0
TRERR is disabled.
1
TRERR is enabled and contributes to the state of EDMA3TC error interrupt generation.
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
Interrupt enable for bus error (BUSERR).
0
BUSERR is disabled.
1
BUSERR is enabled and contributes to the state of EDMA3TC error interrupt generation.
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4.3.4.3
Error Clear Register (ERRCLR)
The error clear register (ERRCLR) is shown in Figure 4-85 and described in Table 4-72.
Figure 4-85. Error Clear Register (ERRCLR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
MMRAERR
TRERR
Reserved
BUSERR
R-0
W-0
W-0
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-72. Error Clear Register (ERRCLR) Field Descriptions
Bit
31-4
3
2
Field
Reserved
Value
0
MMRAERR
Reserved
0
BUSERR
Reserved
Interrupt enable clear for the MMRAERR bit in the error status register (ERRSTAT).
0
No effect.
1
Clears the MMRAERR bit in ERRSTAT but does not clear the error details register (ERRDET).
TRERR
1
Description
Interrupt enable clear for the TRERR bit in the error status register (ERRSTAT).
0
No effect.
1
Clears the TRERR bit in ERRSTAT but does not clear the error details register (ERRDET).
0
Reserved
Interrupt clear for the BUSERR bit in the error status register (ERRSTAT).
0
No effect.
1
Clears the BUSERR bit in ERRSTAT and clears the error details register (ERRDET).
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Error Details Register (ERRDET)
The error details register (ERRDET) is shown in Figure 4-86 and described in Table 4-73.
Figure 4-86. Error Details Register (ERRDET)
31
18
17
Reserved
TCCHEN
R-0
15
14
13
16
TCINTEN
R-0
8
7
4
R-0
3
0
Reserved
TCC
Reserved
STAT
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-73. Error Details Register (ERRDET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
17
TCCHEN
0-1
Transfer completion chaining enable. Contains the TCCHEN value in the channel options parameter
(OPT) programmed by the channel controller for the read or write transaction that resulted in an error.
16
TCINTEN
0-1
Transfer completion interrupt enable. Contains the TCINTEN value in the channel options parameter
(OPT) programmed by the channel controller for the read or write transaction that resulted in an error.
15-14
Reserved
0
13 - 8
TCC
7-4
Reserved
3-0
STAT
0-3Fh
0
0-Fh
0
166
Registers
Reserved
Reserved
Transfer complete code. Contains the TCC value in the channel options parameter (OPT) programmed
by the channel controller for the read or write transaction that resulted in an error.
Reserved
Transaction status. Stores the nonzero status/error code that was detected on the read status or write
status bus. If read status and write status are returned on the same cycle, then the EDMA3TC chooses
nonzero version. If both are nonzero, then the write status is treated as higher priority.
No error
1h-7h
Read error
8h-Fh
Write error
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4.3.4.5
Error Interrupt Command Register (ERRCMD)
The error command register (ERRCMD) is shown in Figure 4-87 and described in Table 4-74.
Figure 4-87. Error Interrupt Command Register (ERRCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
Rsvd
EVAL
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 4-74. Error Interrupt Command Register (ERRCMD) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
Reserved
0
Reserved. Writes of 1 to this bit are not supported. Attempts to do so may result in undefined behavior.
0
EVAL
Error evaluate.
0
No effect.
1
EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set.
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4.3.5 Read Rate Register (RDRATE)
The EDMA3 transfer controller issues read commands at a rate controlled by the read rate register
(RDRATE). The RDRATE defines the number of idle cycles that the read controller must wait before
issuing subsequent commands. This applies both to commands within a transfer request packet (TRP)
and for commands that are issued for different transfer requests (TRs). For instance, if RDRATE is set to
4 cycles between reads, there are 3 inactive cycles between reads.
RDRATE allows flexibility in transfer controller access requests to an endpoint. For an application,
RDRATE can be manipulated to slow down the access rate, so that the endpoint may service requests
from other masters during the inactive EDMA3TC cycles.
The RDRATE is shown in Figure 4-88 and described in Table 4-75.
NOTE: It is expected that the RDRATE value for a transfer controller is static, as it is decided based
on the application requirement. It is not recommended to change this setting on the fly.
Figure 4-88. Read Rate Register (RDRATE)
31
16
Reserved
R-0
15
3
2
0
Reserved
RDRATE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-75. Read Rate Register (RDRATE) Field Descriptions
Bit
Field
Value
31-3
Reserved
0
2-0
RDRATE
0-7h
Registers
Reserved
Read rate. Controls the number of cycles between read commands. This is a global setting that applies
to all TRs for this EDMA3TC.
0
Reads issued as fast as possible.
1h
4 cycles between reads.
2h
8 cycles between reads.
3h
16 cycles between reads.
4h
32 cycles between reads.
5h-7h
168
Description
Reserved
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4.3.6 EDMA3TC Channel Registers
The EDMA3TC channel registers are split into three parts: the programming registers, the source active
registers, and the destination FIFO register. This section describes the registers and their functions. The
program register set is programmed by the channel controller, and is for internal use. The other two sets
are read-only and provided to facilitate advanced debug capabilities. The number of destination FIFO
register sets depends on the destination FIFO depth.
For the TCI6482/86/C6472 devices, TC0 has a FIFO depth of 2, so there are two sets of destination FIFO
registers associated with TC0. TC1, TC2, and TC3 have a destination FIFO depth of 4, so there are four
sets of destination FIFO registers for each of these transfer controllers.
For the TCI6487/88 devices, TC0, TC1, TC2, TC3, TC4 and TC5 all have a destination FIFO depth of 4,
so there are four sets of destination FIFO registers for each of these transfer controllers.
4.3.6.1
Source Active Options Register (SAOPT)
The source active options register (SAOPT) is shown in Figure 4-89 and described in Table 4-76.
Figure 4-89. Source Active Options Register (SAOPT)
31
23
15
22
21
20
Reserved
TCCHEN
Rsvd
TCINTEN
Reserved
TCC
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
12
11
10
8
7
6
4
19
18
3
2
TCC
Rsvd
FWID
Rsvd
PRI
Reserved
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
17
16
1
0
DAM
SAM
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-76. Source Active Options Register (SAOPT) Field Descriptions
Bit
Field
31-23
Reserved
22
TCCHEN
21
Reserved
20
TCINTEN
19-18
Reserved
17-12
TCC
11
10-8
7
Reserved
FWID
Reserved
Value
0
Description
Reserved
Transfer complete chaining enable.
0
Transfer complete chaining is disabled.
1
Transfer complete chaining is enabled.
0
Reserved
Transfer complete interrupt enable.
0
Transfer complete interrupt is disabled.
1
Transfer complete interrupt is enabled.
0
Reserved
0-3Fh
0
0-7h
Transfer complete code. This 6-bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC
module.
Reserved
FIFO width. Applies if either SAM or DAM is set to constant addressing mode.
0
FIFO width is 8-bit.
1h
FIFO width is 16-bit.
2h
FIFO width is 32-bit.
3h
FIFO width is 64-bit.
4h
FIFO width is 128-bit.
5h
FIFO width is 256-bit.
6h-7h
Reserved
0
Reserved
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Table 4-76. Source Active Options Register (SAOPT) Field Descriptions (continued)
Bit
Field
6-4
PRI
Value
0-7h
0
1h-6h
3-2
1
0
170
Reserved
Transfer priority. Reflects the values programmed in the QUEPRI register in the EDMACC.
Priority 0 - Highest priority
Priority 1 to priority 6
7h
Priority 7 - Lowest priority
0
Reserved
DAM
Destination address mode within an array.
0
Increment (INCR) mode. Destination addressing within an array increments.
1
Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
SAM
Registers
Description
Source address mode within an array.
0
Increment (INCR) mode. Source addressing within an array increments.
1
Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
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4.3.6.2
Source Active Source Address Register (SASRC)
The source active source address register (SASRC) is shown in Figure 4-90 and described in Table 4-77.
Figure 4-90. Source Active Source Address Register (SASRC)
31
16
SADDR
R-0
15
0
SADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-77. Source Active Source Address Register (SASRC) Field Descriptions
Bit
Field
31-0
SADDR
4.3.6.3
Value
Description
0-FFFF FFFFh
Source address for program register set. EDMA3TC updates value according to source
addressing mode (SAM bit in the source active options register, SAOPT) .
Source Active Count Register (SACNT)
The source active count register (SACNT) is shown in Figure 4-91 and described in Table 4-78.
Figure 4-91. Source Active Count Register (SACNT)
31
16
BCNT
R-0
15
0
ACNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-78. Source Active Count Register (SACNT) Field Descriptions
Bit
Field
31-16
BCNT
0-FFFFh B dimension count. Number of arrays to be transferred, where each array is ACNT in length. It is
decremented after each read command appropriately. Represents the amount of data remaining to be
read. It should be 0 when transfer request (TR) is complete.
Value
Description
15-0
ACNT
0-FFFFh A dimension count. Number of bytes to be transferred in first dimension. It is decremented after each read
command appropriately. Represents the amount of data remaining to be read. It should be 0 when
transfer request (TR) is complete.
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Source Active Destination Address Register (SADST)
The source active destination address register (SADST) is shown in Figure 4-92 and described in
Table 4-79.
Figure 4-92. Source Active Destination Address Register (SADST)
31
16
DADDR
R-0
15
0
DADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-79. Source Active Destination Address Register (SADST) Field Descriptions
Bit
Field
31-0
DADDR
4.3.6.5
Value
Description
0
Always reads as 0
Source Active Source B-Dimension Index Register (SABIDX)
The source active set B-dimension index register (SABIDX) is shown in Figure 4-93 and described in
Table 4-80.
Figure 4-93. Source Active Source B-Dimension Index Register (SABIDX)
31
16
DSTBIDX
R-0
15
0
SRCBIDX
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-80. Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions
Bit
Field
Value
31-16
DSTBIDX
0
15-0
SRCBIDX
0-FFFFh
172
Registers
Description
B-Index offset between destination arrays. Represents the offset in bytes between the starting
address of each destination. Always reads as 0.
B-Index offset between source arrays. Represents the offset in bytes between the starting address
of each source array.
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4.3.6.6
Source Active Memory Protection Proxy Register (SAMPPRXY)
The source active memory protection proxy register (SAMPPRXY) is shown in Figure 4-94 and described
in Table 4-81.
Figure 4-94. Source Active Memory Protection Proxy Register (SAMPPRXY)
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
PRIV
Reserved
PRIVID
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-81. Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions
Bit
31-9
8
Field
Reserved
Value
0
PRIV
Description
Reserved
Privilege level. The privilege level used by the host to set up the parameter entry in the channel
controller. This field is set up when the associated TR is submitted to the EDMA3TC.
The privilege ID is used while issuing read and write command to the target endpoints so that the target
endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA
transaction.
7-4
Reserved
3-0
PRIVID
0
User-level privilege
1
Supervisor-level privilege
0
Reserved
0-Fh
Privilege ID. This contains the privilege ID of the host that set up the parameter entry in the channel
controller. This field is set up when the associated TR is submitted to the EDMA3TC.
This PRIVID value is used while issuing read and write commands to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIVID of the host that set up
the DMA transaction.
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Source Active Count Reload Register (SACNTRLD)
The source active count reload register (SACNTRLD) is shown in Figure 4-95 and described in
Table 4-82.
Figure 4-95. Source Active Count Reload Register (SACNTRLD)
31
16
Reserved
R-0
15
0
ACNTRLD
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-82. Source Active Count Reload Register (SACNTRLD) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-0
ACNTRLD
0-FFFFh
4.3.6.8
Description
Reserved
A-count reload value. Represents the originally programmed value of ACNT. The reload value is
used to reinitialize ACNT after each array is serviced.
Source Active Source Address B-Reference Register (SASRCBREF)
The source active source address B-reference register (SASRCBREF) is shown in Figure 4-96 and
described in Table 4-83.
Figure 4-96. Source Active Source Address B-Reference Register (SASRCBREF)
31
16
SADDRBREF
R-0
15
0
SADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-83. Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
Bit
31-0
174
Field
SADDRBREF
Registers
Value
0-FFFF FFFFh
Description
Source address B-reference. Represents the starting address for the array currently being
read.
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4.3.6.9
Source Active Destination Address B-Reference Register (SADSTBREF)
The source active destination address B-reference register (SADSTBREF) is shown in Figure 4-97 and
described in Table 4-84.
Figure 4-97. Source Active Destination Address B-Reference Register (SADSTBREF)
31
16
DADDRBREF
R-0
15
0
DADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-84. Source Active Destination Address B-Reference Register (SADSTBREF) Field
Descriptions
Bit
31-0
Field
DADDRBREF
Value
0
Description
Always reads as 0
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4.3.6.10 Destination FIFO Options Register (DFOPTn)
The destination FIFO options register (DFOPTn) is shown in Figure 4-98 and described in Table 4-85.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 4-98. Destination FIFO Options Register (DFOPTn)
31
23
15
12
22
21
20
Reserved
TCCHEN
Rsvd
TCINTEN
Reserved
TCC
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
11
10
8
7
6
4
19
18
3
2
TCC
Rsvd
FWID
Rsvd
PRI
Reserved
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
17
16
1
0
DAM
SAM
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
176
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Table 4-85. Destination FIFO Options Register (DFOPTn) Field Descriptions
Bit
Field
31-23
Reserved
22
TCCHEN
21
Reserved
20
TCINTEN
19-18
Reserved
17-12
TCC
11
10-8
7
6-4
Reserved
FWID
Reserved
PRI
Value
0
0
Transfer complete chaining is disabled.
1
Transfer complete chaining is enabled.
0
Reserved
Transfer complete interrupt enable.
0
Transfer complete interrupt is disabled.
1
Transfer complete interrupt is enabled.
0
Reserved
0-3Fh
0
0-7h
0
Reserved
Transfer complete code. This 6-bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC
module.
Reserved
FIFO width. Applies if either SAM or DAM is set to constant addressing mode.
0
FIFO width is 8-bit.
1h
FIFO width is 16-bit.
2h
FIFO width is 32-bit.
3h
FIFO width is 64-bit.
4h
FIFO width is 128-bit.
5h
FIFO width is 256-bit.
6h-7h
Reserved
0
Reserved
0-7h
0
1
Reserved
Transfer complete chaining enable.
1h-6h
3-2
Description
Transfer priority.
Priority 0 - Highest priority
Priority 1 to priority 6
7h
Priority 7 - Lowest priority
0
Reserved
DAM
Destination address mode within an array.
0
Increment (INCR) mode. Destination addressing within an array increments.
1
Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
SAM
Source address mode within an array.
0
Increment (INCR) mode. Source addressing within an array increments.
1
Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
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4.3.6.11 Destination FIFO Source Address Register (DFSRCn)
The destination FIFO source address register (DFSRCn) is shown in Figure 4-99 and described in
Table 4-86.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 4-99. Destination FIFO Source Address Register (DFSRCn)
31
16
SADDR
R-0
15
0
SADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-86. Destination FIFO Source Address Register (DFSRCn) Field Descriptions
Bit
Field
31-0
SADDR
Value
0
Description
Always read as 0.
4.3.6.12 Destination FIFO Count Register (DFCNTn)
The destination FIFO count register (DFCNTn) is shown in Figure 4-100 and described in Table 4-87.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 4-100. Destination FIFO Count Register (DFCNTn)
31
16
BCNT
R-0
15
0
ACNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-87. Destination FIFO Count Register (DFCNTn) Field Descriptions
Bit
Field
31-16
BCNT
0-FFFFh B-dimension count. Number of arrays to be transferred, where each array is ACNT in length. Count/count
remaining for destination register set. Represents the amount of data remaining to be written.
15-0
ACNT
0-FFFFh A-dimension count. Number of bytes to be transferred in first dimension count/count remaining for
destination register set. Represents the amount of data remaining to be written.
178
Registers
Value
Description
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4.3.6.13 Destination FIFO Destination Address Register (DFDSTn)
The destination FIFO destination address register (DFDSTn) is shown in Figure 4-101 and described in
Table 4-88.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 4-101. Destination FIFO Destination Address Register (DFDSTn)
31
16
DADDR
R-0
15
0
DADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-88. Destination FIFO Destination Address Register (DFDSTn) Field Descriptions
Bit
31-0
Field
DADDR
Value
Description
0
Destination address for the destination FIFO register set. When a transfer request (TR) is complete, the
final value should be the address of the last write command issued.
4.3.6.14 Destination FIFO B-Index Register (DFBIDXn)
The destination FIFO B-index register (DFBIDXn) is shown in Figure 4-102 and described in Table 4-89.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 4-102. Destination FIFO B-Index Register (DFBIDXn)
31
16
DSTBIDX
R-0
15
0
SRCBIDX
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-89. Destination FIFO B-Index Register (DFBIDXn) Field Descriptions
Bit
Field
Value
31-16
DSTBIDX
0-FFFFh
15-0
SRCBIDX
0
Description
B-Index offset between destination arrays. Represents the offset in bytes between the starting
address of each destination.
Always read as 0.
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4.3.6.15 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
The destination FIFO memory protection proxy register (DFMPPRXYn) is shown in Figure 4-103 and
described in Table 4-81.
Figure 4-103. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
PRIV
Reserved
PRIVID
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-90. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field Descriptions
Bit
31-9
8
Field
Value
Reserved
0
Description
Reserved
PRIV
Privilege level. This contains the Privilege level used by the EDMA3 programmer to set up the
parameter entry in the channel controller. This field is set up when the associated TR is submitted to the
EDMA3TC.
The privilege ID is used while issuing read and write command to the target endpoints so that the target
endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA
transaction.
7-4
Reserved
3-0
PRIVID
0
User-level privilege
1
Supervisor-level privilege
0
Reserved
0-Fh
Privilege ID. This contains the Privilege ID of the EDMA3 programmer that set up the parameter entry in
the channel controller. This field is set up when the associated TR is submitted to the EDMA3TC.
This PRIVID value is used while issuing read and write commands to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIVID of the host that set up
the DMA transaction.
4.3.6.16 Destination FIFO Count Reload Register (DFCNTRLDn)
The destination FIFO count reload register (DFCNTRLDn) is shown in Figure 4-104 and described in
Table 4-91.
Figure 4-104. Destination FIFO Count Reload Register (DFCNTRLDn)
31
16
Reserved
R-0
15
0
ACNTRLD
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-91. Destination FIFO Count Reload Register (DFCNTRLDn) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-0
ACNTRLD
0-FFFFh
180
Registers
Description
Reserved
A-count reload value. Represents the originally programmed value of ACNT. The reload value is
used to reinitialize ACNT after each array is serviced.
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4.3.6.17 Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
The destination FIFO source address B-reference register (DFSRCBREFn) is shown in Figure 4-105 and
described in Table 4-92.
Figure 4-105. Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
31
16
SADDRBREF
R-0
15
0
SADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-92. Destination FIFO Source Address B-Reference Register (DFSRCBREFn) Field
Descriptions
Bit
31-0
Field
SADDRBREF
Value
0
Description
Not Applicable. Always read as 0.
4.3.6.18 Destination FIFO Destination Address B-Reference (DFDSTBREFn)
The destination FIFO destination address B-reference register (DFDSTBREFn) is shown in Figure 4-106
and described in Table 4-93.
Figure 4-106. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn)
31
16
DADDRBREF
R-0
15
0
DADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 4-93. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) Field
Descriptions
Bit
31-0
Field
DADDRBREF
Value
0-FFFF FFFFh
Description
Destination address reference for the destination FIFO register set. Represents the starting
address for the array currently being written.
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Appendix A
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Tips
A.1
Debug Checklist
This section lists some tips to keep in mind while debugging applications using the EDMA3.
The following table provides some common issues and their probable causes and resolutions.
Table A-1. Debug List
Issue
Description/Solution
The transfer associated with the channel
does not happen. The channel does not
get serviced.
The EDMA3CC may not service a transfer request, even though the associated
PaRAM set is programmed appropriately. Check for the following:
1) Verify that events are enabled, i.e., if an external/peripheral event is latched in Event
Registers (ER/ERH), make sure that the event is enabled in the Event Enable
Registers (EER/EERH). Similarly, for QDMA channels, make sure that QDMA events
are appropriately enabled in the QDMA Event Enable Register (QEER).
2) Verify that the DMA or QDMA Secondary Event Register (SER/SERH/QSERH) bits
corresponding to the particular event or channel are not set.
The Secondary Event Registers bits are
set, not allowing additional transfers to
occur on a channel.
It is possible that a trigger event was received when the parameter set associated with
the channel/event was a NULL set for a previous transfer on the channel. This is
typical in two cases:
1) QDMA channels: Typically if the parameter set is non-static and expected to be
terminated by a NULL set (i.e., OPT.STATIC = 0, LINK = FFFFh), the parameter set is
updated with a NULL set after submission of the last TR. Because QDMA channels are
auto-triggered, this update caused the generation of an event. An event generated for a
NULL set causes an error condition and results in setting the bits corresponding to the
QDMA channel in the QEMR and QSER. This will disable further prioritization of the
channel.
2) DMA channels used in a continuous mode: The peripheral may be set up to
continuously generate infinite events (for instance, in case of McBSP, every time the
data shifts out from the DXR register, it generates an XEVT). The parameter set may
be programmed to expect only a finite number of events and to be terminated by a
NULL link. After the expected number of events, the parameter set is reloaded with a
NULL parameter set. Because the peripheral will generate additional events, an error
condition is set in the SER.Ex and EMR.Ex set, preventing further event prioritization.
You must ensure that the number of events received is limited to the expected number
of events for which the parameter set is programmed, or you must ensure that bits
corresponding to particular channel or event are not set in the Secondary event
registers (SER/SERH/QSER) and Event Missed Registers (EMR/EMRH/QEMR) before
trying to perform subsequent transfers for the event/channel.
Completion interrupts are not asserted, or You must ensure the following:
no further interrupts are received after the 1) The interrupt generation is enabled in the OPT of the associated PaRAM set
first completion interrupt.
(TCINTEN = 1 and/or ITCINTEN = 1).
2) The interrupts are enabled in the EDMA3 Channel Controller, via the Interrupt
Enable Registers (IER/IERH).
3) The corresponding interrupts are enabled in the device interrupt controller.
4) The set interrupts are cleared in the interrupt pending registers (IPR/IPRH) before
exiting the transfer completion interrupt service routine (ISR). For details on writing
EDMA3 ISRs, see Section 2.9.1.2.
5) If working with shadow region interrupts, make sure that the DMA Region Access
registers (DRAE/DRAEH) are set up properly, because the DRAE/DRAEH registers act
as secondary enables for shadow region completion interrupts, along with the
IER/IERH registers.
If working with shadow region interrupts, make sure that the bits corresponding to the
transfer completion code (TCC) value are also enabled in the DRAE/DRAEH registers.
For instance, if the PaRAM set associated with Channel 0 returns a completion code of
63 (OPT.TCC=63), ensure that DRAEH.E63 is also set for a shadow region completion
interrupt because the interrupt pending register bit set will be IPRH.I63 (not IPR.I0).
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Tips 183
Miscellaneous Programming/Debug Tips
A.2
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Miscellaneous Programming/Debug Tips
1. For several registers, the setting and clearing of bits needs to be done via separate dedicated
registers. For example, the Event Register (ER/ERH) can only be cleared by writing a 1 to the
corresponding bits in the Event Clear Registers (ECR/ECRH). Similarly, the Event Enable Register
(EER/EERH) bits can only be set with writes of 1 to the Event Enable Set Registers (EESR/EESRH)
and cleared with writes of 1 to the corresponding bits in the Event Enable Clear Register
(EECR/EECRH).
2. Writes to the shadow region memory maps are governed by region access registers
(DRAE/DRAEH/QRAE). If the appropriate channels are not enabled in these registers, read/write
access to the shadow region memory map is not enabled.
3. When working with shadow region completion interrupts, ensure that the DMA Region Access
Registers (DRAE/DRAEH) for every region are set in a mutually exclusive way (unless it is a
requirement for an application). If there is an overlap in the allocated channels and transfer completion
codes (setting of Interrupt Pending Register bits) in the region resource allocation, it results in multiple
shadow region completion interrupts. For example, if DRAE0.E0 and DRAE1.E0 are both set, then on
completion of a transfer that returns a TCC=0, they will generate both shadow region 0 and 1
completion interrupts.
4. While programming a non-dummy parameter set, ensure the CCNT is not left to zero.
5. Enable the EDMA3CC error interrupt in the device controller and attach an interrupt service routine
(ISR) to ensure that error conditions are not missed in an application and are appropriately addressed
with the ISR.
6. Depending on the application, you may want to break large transfers into smaller transfers and use
self-chaining to prevent starvation of other events in an event queue.
7. In applications where a large transfer is broken into sets of small transfers using chaining or other
methods, you might choose to use the early chaining option to reduce the time between the sets of
transfers and increase the throughput. However, keep in mind that with early completion, all data might
have not been received at the end point when completion is reported because the EDMA3CC internally
signals completion when the TR is submitted to the EDMA3TC, potentially before any data has been
transferred.
8. The event queue entries can be observed to determine the last few events if there is a system failure
(provided the entries were not bypassed).
184
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Appendix B
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Setting Up a Transfer
The following list provides a quick guide for the typical steps involved in setting up a transfer.
1. Initiating a DMA/QDMA channel
(a) Determine the type of channel (QDMA or DMA) to be used.
(b) Channel mapping
(i) If using a QDMA Channel, program the QCHMAP with the parameter set number to which the
channel maps and the trigger word.
(ii) If using a DMA channel, program the DCHMAP with the parameter set number to which the
channel maps.
(c) If the channel is being used in the context of a shadow region, ensure the DRAE/DRAEH for the
region is properly set up to allow read write accesses to bits in the event registers and interrupt
registers in the Shadow region memory map. The subsequent steps in this process should be done
using the respective shadow region registers. (Shadow region descriptions and usage are provided
in Section 2.7.1.)
(d) Determine the type of triggering used.
(i) If external events are used for triggering (DMA channels), enable the respective event in
EER/EERH by writing into EESR/EESRH.
(ii) If QDMA Channel is used, enable the channel in QEER by writing into QEESR.
(e) Queue setup
(i) If a QDMA channel is used, set up the QDMAQNUM to map the channel to the respective
event queue.
(ii) If a DMA channel is used, set up the DMAQNUM to map the event to the respective event
queue.
2. Parameter set setup
(a) Program the PaRAM set number associated with the channel. Note that if it is a QDMA channel,
the PaRAM entry that is configured as trigger word is written to last. Alternatively, enable the
QDMA channel (step 1-b-ii above) just before the write to the trigger word.
See Chapter 3 for parameter set field setups for different types of transfers. See the sections on
chaining (Section 2.8) and interrupt completion (Section 2.9) on how to set up final/intermediate
completion chaining and/or interrupts.
3. Interrupt setup
(a) Enable the interrupt in the IER/IERH by writing into IESR/IESRH.
(b) Ensure the EDMA3CC completion interrupt (this refers to either the Global interrupt or the shadow
region interrupt) is enabled properly in the device interrupt controller.
(c) Set up the interrupt controller properly to receive the expected EDMA3 interrupt.
4. Initiate transfer
(a) This step is highly dependent on the event trigger source:
(i) If the source is an external event coming from a peripheral, the peripheral will be enabled to
start generating relevant EDMA3 events that can be latched to the ER transfer.
(ii) For QDMA events, writes to the trigger word (step 2-a above) will initiate the transfer.
(iii) Manually triggered transfers will be initiated by writes to the Event Set Registers (ESR/ESRH).
(iv) Chained-trigger events initiate when a previous transfer returns a transfer completion code
equal to the chained channel number.
5. Wait for completion
(a) If the interrupts are enabled as mentioned in step 3 above, then the EDMA3CC will generate a
completion interrupt to the CPU whenever transfer completion results in setting the corresponding
bits in the interrupt pending register (IPR/IPRH). The set bits must be cleared in the IPR/IPRH by
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Setting Up a Transfer
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writing to corresponding bit in ICR/ICRH.
(b) If polling for completion (interrupts not enabled in the device controller), then the application code
can wait on the expected bits to be set in the IPR/IPRH. Again, the set bits in the IPR/IPRH must
be manually cleared via ICR/ICRH before the next set of transfers is performed for the same
transfer completion code values.
186
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Appendix C
SPRU727E – December 2005 – Revised July 2011
Revision History
This revision history highlights the technical changes made to the document in this revision.
Table C-1. EDMA3 Revision History
See
Additions/Modifications/Deletions
Section 4.2.1.5 Deleted Note
Section 4.2.1.7 Added new section: Queue-to-TC Mapping Register (QUETCMAP)
SPRU727E – December 2005 – Revised July 2011
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Revision History
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