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Texas Instruments TMS320C6474 DSP DDR2 Memory Controller (Rev. D) User guides
TMS320C6474 DSP
DDR2 Memory Controller
User's Guide
Literature Number: SPRUG19D
October 2008 – Revised June 2011
2
SPRUG19D – October 2008 – Revised June 2011
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Contents
Preface ....................................................................................................................................... 7
1
Introduction ........................................................................................................................ 9
.............................................................................................. 9
.................................................................................................................. 9
1.3
Functional Block Diagram .............................................................................................. 9
1.4
Industry Standard(s) Compliance Statement ....................................................................... 10
2
Peripheral Architecture ...................................................................................................... 11
2.1
Clock Control ........................................................................................................... 11
2.2
Memory Map ............................................................................................................ 11
2.3
Signal Descriptions .................................................................................................... 11
2.4
Protocol Description(s) ................................................................................................ 13
2.5
Memory Width, Byte Alignment, and Endianness ................................................................. 20
2.6
Address Mapping ...................................................................................................... 21
2.7
DDR2 Memory Controller Interface .................................................................................. 24
2.8
Refresh Scheduling .................................................................................................... 27
2.9
Self-Refresh Mode ..................................................................................................... 28
2.10 Reset Considerations .................................................................................................. 28
2.11 DDR2 SDRAM Memory Initialization ................................................................................ 28
2.12 Interrupt Support ....................................................................................................... 30
2.13 EDMA Event Support .................................................................................................. 30
2.14 Emulation Considerations ............................................................................................. 30
3
Using the DDR2 Memory Controller ..................................................................................... 31
3.1
Connecting the DDR2 Memory Controller to DDR2 SDRAM .................................................... 31
3.2
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications .................... 35
4
DDR2 Memory Controller Registers ..................................................................................... 38
4.1
Module ID and Revision Register (MIDR) .......................................................................... 39
4.2
DDR2 Memory Controller Status Register (DMCSTAT) .......................................................... 40
4.3
SDRAM Configuration Register (SDCFG) .......................................................................... 41
4.4
SDRAM Refresh Control Register (SDRFC) ....................................................................... 43
4.5
SDRAM Timing 1 Register (SDTIM1) ............................................................................... 44
4.6
SDRAM Timing 2 Register (SDTIM2) ............................................................................... 46
4.7
Burst Priority Register (BPRIO) ...................................................................................... 47
4.8
DDR2 Memory Controller Control Register (DMCCTL) ........................................................... 48
Revision History ......................................................................................................................... 49
1.1
Purpose of the Peripheral
1.2
Features
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Table of Contents
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List of Figures
4
1
Device Block Diagram .................................................................................................... 10
2
DDR2 Memory Controller Signals ....................................................................................... 12
3
DDR2 MRS and EMRS Command ...................................................................................... 14
4
Refresh Command ........................................................................................................ 15
5
ACTV Command........................................................................................................... 16
6
DCAB Command .......................................................................................................... 17
7
DEAC Command .......................................................................................................... 18
8
DDR2 READ Command .................................................................................................. 19
9
DDR2 WRT Command
10
Byte Alignment ............................................................................................................. 21
11
Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ............................................... 22
12
Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM ............................................... 22
13
Logical Address-to-DDR2 SDRAM Address Map ..................................................................... 23
14
DDR2 SDRAM Column, Row, and Bank Access
15
DDR2 Memory Controller FIFO Block Diagram ....................................................................... 25
16
Connecting to Two 16-Bit DDR2 SDRAM Device ..................................................................... 32
17
Connecting to a Single 16-Bit DDR2 SDRAM Device ................................................................ 33
18
Connecting to Two 8-Bit DDR2 SDRAM Devices ..................................................................... 34
19
Module ID and Revision Register (MIDR) .............................................................................. 39
20
DDR2 Memory Controller Status Register (DMCSTAT) .............................................................. 40
21
SDRAM Configuration Register (SDCFG)
22
SDRAM Refresh Control Register (SDRFC) ........................................................................... 43
23
SDRAM Timing 1 Register (SDTIM1) ................................................................................... 44
24
SDRAM Timing 2 Register (SDTIM2) ................................................................................... 46
25
Burst Priority Register (BPRIO) .......................................................................................... 47
26
DDR2 Memory Controller Control Register (DMCCTL)
List of Figures
...................................................................................................
.....................................................................
.............................................................................
..............................................................
20
24
41
48
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List of Tables
1
DDR2 Memory Controller Signal Descriptions ......................................................................... 12
2
DDR2 SDRAM Commands
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
..............................................................................................
Truth Table for DDR2 SDRAM Commands ............................................................................
Addressable Memory Ranges ...........................................................................................
Bank Configuration Register Fields for Address Mapping ...........................................................
DDR2 Memory Controller FIFO Description ...........................................................................
Refresh Urgency Levels ..................................................................................................
Device and DDR2 Memory Controller Reset Relationship ...........................................................
DDR2 SDRAM Mode Register Configuration ..........................................................................
DDR2 SDRAM Extended Mode Register 1 Configuration ...........................................................
SDCFG Configuration .....................................................................................................
DDR2 Memory Refresh Specification ..................................................................................
SDRFC Configuration .....................................................................................................
SDTIM1 Configuration ....................................................................................................
SDTIM2 Configuration ....................................................................................................
DMCCTL Configuration ...................................................................................................
DDR2 Memory Controller Registers ....................................................................................
Module ID and Revision Register (MIDR) Field Descriptions .......................................................
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions .......................................
SDRAM Configuration Register (SDCFG) Field Descriptions .......................................................
SDRAM Refresh Control Register (SDRFC) Field Descriptions ....................................................
SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................
SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................
Burst Priority Register (BPRIO) Field Descriptions ...................................................................
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions ........................................
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List of Tables
13
13
20
21
24
27
28
29
29
35
36
36
36
37
37
38
39
40
41
43
44
46
47
48
5
6
List of Tables
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Preface
SPRUG19D – October 2008 – Revised June 2011
Read This First
About This Manual
This document describes the DDR2 memory controller in the TMS320C6474 digital signal processors
(DSPs).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet. Tip: Enter the literature number in the search box provided at
www.ti.com.
SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors
(DSPs).
SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you
to program custom plug-ins for Code Composer.
SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal
processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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Preface
7
8
Read This First
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User's Guide
SPRUG19D – October 2008 – Revised June 2011
C6474 DDR2 Memory Controller
1
Introduction
1.1
Purpose of the Peripheral
The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAM
devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories
are not supported. The DDR2 memory controller SDRAM can be used for program and data storage.
1.2
Features
The DDR2 memory controller supports the following features:
• JESD79-2B standard compliant DDR2 SDRAM
• 512M byte memory space
• Data bus width of 32 or 16 bits
• CAS latencies: 2, 3, 4, and 5
• Internal banks: 1, 2, 4, and 8
• Burst length: 8
• Burst type: sequential
• 1 CE signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM autoinitialization
• Self-refresh mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little endian and big endian transfers
1.3
Functional Block Diagram
The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1). Master
peripherals, such as the EDMA controller and the CPU can access the DDR2 memory controller through
the switched central resource (SCR). The DDR2 memory controller performs all memory-related
background tasks such as opening and closing banks, refreshes, and command arbitration.
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Introduction
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Figure 1. Device Block Diagram
DDR2 SDRAM
DSP Subsystem 2
DSP Subsystem 1
32
DDR2 Memory
Controller
DSP Subsystem 0
32K Bytes
L1P SRAM/Cache
Direct-Mapped
L2/Cache
0.5 - 1.5 M
PLL2
C64x+ Megamodule
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
Serial RapidIO
(2x)
McBSP0
McBSP1
EMAC
10/100/1000
SGMII
Switched Central Resource (SCR)
VCP2
SPLOOP Buffer
Instruction Decode
In-Circuit Emulation
.L1
A Register File
B Register File
A31 - A16
B31 - B16
A15 - A0
B15 - B0
.S1
.M1
xx
xx
.D1
.D2
.M2
xx
xx
.S2
L2 Memory Controller
(Memory Protect/
Bandwidth Mgmt)
16-/32-bit
Instruction Dispatch
Internal DMA
(DMA)
Control Registers
Power Control
Instruction Fetch
TCP2
Interrupt Exception Controller
C64x+ DSP Core
System
2
.L2
MDIO
I2C
L1 Data Memory Controller (Memory Protect/Bandwidth Mgmt)
16
GPIO16
32K Bytes Total
L1D SRAM/Cache 2-Way
Set Associative
FSYNC
Semaphore
Antenna
Interface
EDMA 3.0
PLL1 and
PLL1 Controller
Timer [0-5]
Power-Down and Device
Configuration Logic
L3 ROM
Boot Configuration
1.4
Industry Standard(s) Compliance Statement
The DDR2 memory controller is compliant with the JESD79-2B DDR2 SDRAM.
10
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2
Peripheral Architecture
The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and
supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility
through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing
parameters.
The following sections describe the architecture of the DDR2 memory controller as well as how to
interface and configure it to perform read and write operations to DDR2 SDRAM devices. Also, Section 3
provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM
device.
2.1
Clock Control
The PLL2 multiplies its input clock by 10. This clock serves as input to DDR2 PHY. The frequency of
DDR2CLKOUT can be determined by using the following formula:
DDR2CLKOUT frequency = (PLL2 input clock frequency × 10)/2
2.2
Memory Map
For information describing the device memory map, see the TMS320C6474 Multicore Digital Signal
Processor data manual (SPRS552).
2.3
Signal Descriptions
The DDR2 memory controller signals are shown in Figure 2 and described in Table 1. The following
features are included:
•
•
•
•
•
•
•
The maximum width for the data bus (DED[31:0]) is 32-bits.
The address bus (DEA[13:0]) is 14-bits wide with an additional 3 bank address pins (DBA[2:0]).
Two differential output clocks (DDR2CLKOUT and DDR2CLKOUT) driven by internal clock sources.
Command signals: Row and column address strobe (DSDRAS and DSDCAS), write enable strobe
(DSDWE), data strobe (DSDDQS[3:0] and DSDDQS[3:0]), and data mask (DSDDQM[3:0]).
One chip select signal (DCE0).
One clock enable signal (DSDCKE).
One on-die termination output signal (DDRODT).
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Figure 2. DDR2 Memory Controller Signals
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DCE0
DSDWE
DSDRAS
DSDCAS
DDR2
Memory
Controller
DSDDQM[3:0]
DSDDQS[3:0]
DSDDQS[3:0]
DBA[2:0]
DEA[13:0]
DED[31:0]
DDRODT
DSDDQGATE[3:0]
VREFSSTL
DDRSLRATE
Table 1. DDR2 Memory Controller Signal Descriptions
12
Pin
Description
DED[31:0]
Bidirectional data bus. Input for data reads and output for data writes.
DEA[13:0]
External address output.
DCE0
Active-low chip enable for memory space CE0. DCE0 is used to enable the DDR2 SDRAM memory
device during external memory accesses.
DSDDQM[3:0]
Active-low output data mask.
DDR2CLKOUT
DDR2CLKOUT
Differential clock outputs.
DSDCKE
Clock enable (used for self-refresh mode).
DSDCAS
Active-low column address strobe.
DSDRAS
Active-low row address strobe.
DSDWE
Active-low write enable.
DSDDQS[3:0]/
DSDDQS[3:0]
Differential data strobe bidirectional signals.
DDRODT
On-die termination signals to external DDR2 SDRAM.
DBA[2:0]
Bank-address control outputs.
DSDDQGATE[3:0]
Data strobe gate pins. These pins are used as a timing reference during memory reads. The
DSDDQGATE0 and DSDDQGATE2 pins should be routed out and connected to the DSDDQGATE1
and DSDDQGATE3 pins, respectively. For more routing requirements on these pins, see the
TMS320C6474 Multicore Digital Signal Processor data manual (SPRS552).
VREFSSTL
DDR2 Memory Controller reference voltage. This voltage must be supplied externally. For more details,
see the TMS320C6474 Multicore Digital Signal Processor data manual (SPRS552).
DDRSLRATE
Pulling the DDRSLRATE input pin low selects the normal slew rate. If pulled high, the slew rate is
reduced by 33%. For normal full-speed operation, the DDRSLRATE should be pulled low.This pin
needs to be pulled low or high at all times (it is not latched).
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2.4
Protocol Description(s)
The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the
signal truth table for the DDR2 SDRAM commands.
Table 2. DDR2 SDRAM Commands
Command
Function
ACTV
Activates the selected bank and row.
DCAB
Precharge all command. Deactivates (precharges) all banks.
DEAC
Precharge single command. Deactivates (precharges) a single bank.
DESEL
Device Deselect.
EMRS
Extended Mode Register set. Allows altering the contents of the mode register.
MRS
Mode register set. Allows altering the contents of the mode register.
NOP
No operation.
Power Down
Power down mode.
READ
Inputs the starting column address and begins the read operation.
REFR
Autorefresh cycle.
SLFREFR
Self-refresh mode.
WRT
Inputs the starting column address and begins the write operation.
Table 3. Truth Table for DDR2 SDRAM Commands
DDR2 SDRAM
Signals
CKE
CS
RAS
CAS
WE
BA[2:0]
A[13:11, 9:0]
A10
DEA[13:11, 9:0]
DEA[10]
DSDCKE
DDR2 Memory
Controller Signals
Previous
Cycles
Current Cycle
DCE0
DSDRAS
DSDCAS
DSDWE
DBA[2:0]
ACTV
H (1)
H
L
L
H
H
Bank
DCAB
H
H
L
L
H
L
X
X
DEAC
H
H
L
L
H
L
Bank
X
MRS
H
H
L
L
L
L
BA (2)
EMRS
H
H
L
L
L
L
BA
READ
H
H
L
H
L
H
BA
Column Address
WRT
H
H
L
H
L
L
BA
Column Address
L
REFR
H
H
L
L
L
H
X
X
X
SLFREFR
entry
H
L
L
L
L
H
X
X
X
SLFREFR
exit
L
H
H
X
X
X
X
X
X
L
H
H
H
X
X
X
NOP
H
X
L
H
H
H
X
X
X
DESEL
H
X
H
X
X
X
X
X
X
Power-down
entry
H
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
Power-down
exit
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
(1)
(2)
H
Row Address
H
L
OP Code
OP Code
L
LEGEND: H = logic high; L = logic low; X = don't care (either H or L).
BA refers to the bank address pins (BA[2:0]).
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Mode Register Set (MRS and EMRS)
DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for
operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended
strobe, etc.
The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by
issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on
DBA[1:0] selects the mode register to be written and the data on DEA[12:0] is loaded into the register.
Figure 3 shows the timing for an MRS and EMRS command.
The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller
initialization sequence. For more information, see Section 2.11.
Figure 3. DDR2 MRS and EMRS Command
DDR2CLKOUT
DDR2CLKOUT
MRS/EMRS
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
14
DEA[13:0]
COL
DBA[2:0]
BANK
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2.4.2
Refresh Mode
The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4). REFR is
automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks
selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a
rate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC).
Page information is always invalid before and after a REFR command; thus, a refresh cycle always forces
a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands may not be
disabled within the DDR2 memory controller. See Section 2.8 for more details on REFR command
scheduling.
Figure 4. Refresh Command
REFR
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:0]
DBA[2:0]
DSDDQM[3:0]
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Activation (ACTV)
The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to
a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or
writes) with minimum latency. The value of DBA[2:0] selects the bank and the value of A[12:0] selects the
row. When the DDR2 memory controller issues an ACTV command, a delay of tRCD is incurred before a
read or write command is issued. Figure 5 shows an example of an ACTV command. Reads or writes to
the currently active row and bank of memory can achieve much higher throughput than reads or writes to
random areas because every time a new row is accessed, the ACTV command must be issued and a
delay of tRCD incurred.
Figure 5. ACTV Command
DDR2CLKOUT
DDR2CLKOUT
ACTV
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:0]
ROW
DBA[2:0]
BANK
DSDDQM[3:0]
16
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2.4.4
Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or
following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and
mode set register commands (MRS and EMRS). During a DCAB command, DEA10 is driven high to
ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command.
Figure 6. DCAB Command
DCAB
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:11, 9:0]
DEA[10]
DBA[2:0]
DSDDQM[3:0]
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The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows
the timings diagram for a DEAC command.
Figure 7. DEAC Command
DDR2CLKOUT
DDR2CLKOUT
DEAC
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:11, 9:0]
DEA[10]
DBA[2:0]
DSDDQM[3:0]
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2.4.5
READ Command
Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ
command initiates a burst read operation to an active row. During the READ command, DSDCAS drives
low, DSDWE and DSDRAS remain high, the column address is driven on DEA[12:0], and the bank
address is driven on DBA[2:0].
The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or
5. The CAS latency is three cycles in Figure 8. Read latency is equal to CAS latency plus additive latency.
The DDR2 memory controller always configures the memory to have an additive latency of 0, so read
latency equals CAS latency. Since the default burst size is 8, the DDR2 memory controller returns 8
pieces of data for every read command. If additional accesses are not pending to the DDR2 memory
controller, the read burst completes and the unneeded data is disregarded. If additional accesses are
pending, depending on the scheduling result, the DDR2 memory controller can terminate the read burst
and start a new read burst. Furthermore, the DDR2 memory controller does not issue a DCAB/DEAC
command until page information becomes invalid.
Figure 8. DDR2 READ Command
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:0]
DBA[2:0]
COL
BANK
DEA[10]
DSDDQM[3:0]
CAS Latency
DED[31:0]
D0
D1
D2
D3
D4
D5
D6
D7
DSDDQS[3:0]
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Write (WRT) Command
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the
WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have
a burst length of 8. The use of the DSDDQM outputs allows byte and halfword writes to be executed.
Figure 9 shows the timing for a write on the DDR2 memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pending
commands, the DDR2 memory controller can:
• Mask out the additional data using DSDDQM outputs
• Terminate the write burst and start a new write burst
The DDR2 memory controller does not perform the DEAC command until page information becomes
invalid.
Figure 9. DDR2 WRT Command
DDR2CLKOUT
DDR2CLKOUT
Sample
Write Latency
DSDCKE
DCE0
DSDRAS
DSDCAS
DSDWE
DEA[13:0]
DBA[2:0]
COL
BANK
DEA[10]
DSDDQM[3:0]
DED[31:0]
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
D0
D1
D2
D3
D4
D5
D6
D7
DSDDQS[3:0]
2.5
Memory Width, Byte Alignment, and Endianness
The DDR2 memory controller supports memory widths of 16 bits and 32 bits. Table 4 summarizes the
addressable memory ranges on the DDR2 memory controller.
Table 4. Addressable Memory Ranges
20
Memory Width
Maximum Addressable Bytes
×16
256M bytes
Halfword address
×32
512M bytes
Word address
C6474 DDR2 Memory Controller
Address Type Generated by DDR2
Memory Controller
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Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always
right aligned on the data bus.
Figure 10. Byte Alignment
DDR2 memory controller data bus
DED[31:24]
(Byte Lane 3)
DED[23:16]
(Byte Lane 2)
DED[15:8]
(Byte Lane 1)
DED[7:0]
(Byte Lane 0)
32-bit memory device
16-bit memory device
The DDR2 memory controller supports both little endian and big endian formats. The endianness mode
determines whether byte lane 0 (DED[7:0]) is accessed as byte address 0 (little endian) or as byte
address N (big endian), where 2n is the memory width in bytes. Similarly, byte lane N is addresses as
either byte address 0 (big endian) or as byte address N (little endian).
The DDR2 memory controller uses the endianness mode being used by the rest of the DSP. The
endianness mode of the DSP is set during device reset (for more details, see the TMS320C6474 Multicore
Digital Signal Processor data manual (SPRS552). The endianness mode of the DDR2 memory controller
is shown on the BE bit of the DDR2 memory controller status register (DMCSTAT); BE = 1 indicates big
endian mode and BE = 0 indicates little endian mode.
2.6
Address Mapping
The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This
statement is true regardless of the number of memory devices located on the chip select space. The
DDR2 memory controller receives DDR2 memory access requests along with a 32-bit logical address from
the rest of the system. In turn, DDR2 memory controller uses the logical address to generate a row/page,
column, bank address, and chip selects for the DDR2 SDRAM. The number of column and bank address
bits used is determined by the IBANK and PAGESIZE fields. The chip selection pins used are determined
by the DCE0 field (see Table 5). The DDR2 memory controller uses up to 14 bits for the row/page
address.
Table 5. Bank Configuration Register Fields for Address Mapping
Bit Field
Bit Value Bit Description
IBANK
Defines the number of internal banks on the external DDR2 memory.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
PAGESIZE
Defines the page size of each page of the external DDR2 memory.
0
256 words (requires 8 column address bits)
1h
512 words (requires 9 column address bits)
2h
1024 words (requires 10 column address bits)
3h
2048 words (requires 11 column address bits)
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Figure 11 and Figure 12 show how the logical address bits map to the row, column, bank, and chip select
bits all combinations of IBANK and PAGESIZE values. Note that the upper three bits of the logical address
cannot be used for memory addressing, as the DDR2 memory controller has a maximum addressable
memory range of 512M bytes.
The DDR2 memory controller address pins provide the row and column address to the DDR2 SDRAM,
thus the DDR2 memory controller appropriately shifts the logical address during row and column address
selection. The bank address is driven to the DDR2 SDRAM using the bank address pins. The two lower
bits of the logical address decode the value of the byte enable pins (only used for accesses less than the
width of the DDR2 memory controller data bus).
Figure 11. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM
SDCFG Bit
Logical Address
IBANK
PAGESIZE
31:29
28
27
26
25
24
0
0
X
X
X
X
X
X
1
0
X
X
X
X
X
2
0
X
X
X
X
3
0
X
X
X
0
1
X
X
X
X
1
1
X
X
X
X
2
1
X
X
X
3
1
X
X
0
2
X
X
X
1
2
X
X
X
2
2
X
X
3
2
X
0
3
X
X
1
3
X
X
2
3
X
3
3
X
23
22:17
16
15
14
13
12
11
10
9:2
nrb=14
ncb=8
nrb=14
nbb=1
nrb=14
nrb=14
ncb=8
nbb=3
X
ncb=8
nrb=14
ncb=9
nrb=14
nbb=1
nrb=14
ncb=9
nbb=2
nrb=14
ncb=9
nbb=3
X
ncb=9
nrb=14
ncb=10
nrb=14
nbb=1
nrb=14
ncb=10
nbb=2
nrb=14
ncb=10
nbb=3
X
ncb=8
nbb=2
ncb=10
nrb=14
ncb=11
nrb=14
nbb=1
nrb=14
ncb=11
nbb=2
nrb=13
ncb=11
nbb=3
ncb=11
LEGEND: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits.
Figure 12. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM
SDCFG Bit
Logical Address
IBANK
PAGESIZE
31:29
28
27
26
25
24
23
0
0
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
2
0
X
X
X
X
X
3
0
X
X
X
X
0
1
X
X
X
X
X
1
1
X
X
X
X
X
2
1
X
X
X
X
3
1
X
X
X
0
2
X
X
X
X
1
2
X
X
X
X
2
2
X
X
X
3
2
X
X
0
3
X
X
X
1
3
X
X
X
2
3
X
X
3
3
X
22
21:16
15
14
13
12
11
10
9
8:1
nrb=14
ncb=8
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=8
nrb=14
ncb=9
nrb=14
nbb=1
nrb=14
ncb=9
nbb=3
nrb=14
ncb=9
ncb=10
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
nbb=3
X
ncb=9
nbb=2
nrb=14
X
ncb=8
nbb=3
X
ncb=8
nrb=14
ncb=10
ncb=10
ncb=10
ncb=11
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
nbb=3
ncb=11
ncb=11
ncb=11
LEGEND: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits.
Figure 11 shows how the DSP memory map is partitioned into columns, rows, and banks. Note that during
a linear access, the DDR2 memory controller increments the column address as the logical address
increments. When the DDR2 memory controller reaches a page/row boundary, it moves onto the same
page/row in the next bank. This movement continues until the same page has been accessed in all banks.
To the DDR2 SDRAM, this process looks as shown on Figure 14.
By traversing across banks while remaining on the same row/page, the DDR2 memory controller
maximizes the number of activated banks for a linear access. This results in the maximum number of
open pages when performing a linear access being equal to the number of banks. Note that the DDR2
memory controller never opens more than one page per bank.
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Ending the current access is not a condition that forces the active DDR2 SDRAM row/page to be closed.
The DDR2 memory controller leaves the active row open until it becomes necessary to close it. This
decreases the deactivate-reactivate overhead.
Figure 13. Logical Address-to-DDR2 SDRAM Address Map
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 0
Row 1, bank 1
Row 1, bank 2
Row 1, bank P
Row N, bank 0
Row N, bank 1
Row N, bank 2
Row N, bank P
A
M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK)
minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
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Figure 14. DDR2 SDRAM Column, Row, and Bank Access
Bank 0
C C C
o o o
l l l
0 1 2 3
Row 0
Row 1
Row 2
C
o
l
M
Bank 1
C C C
o o o
l l l
0 1 2 3
Row 0
Row 1
Row 2
C
o
l
M
Bank 2
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Bank P
Row 0
Row 1
Row N
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 2
Row N
Row N
Row N
A
2.7
M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK)
minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
DDR2 Memory Controller Interface
To move data efficiently from on-chip resources to external DDR2 SDRAM device, the DDR2 memory
controller makes use of a command FIFO, a write FIFO, a read FIFO, and command and data schedulers.
Table 6 describes the purpose of each FIFO.
Figure 15 shows the block diagram of the DDR2 memory controller FIFOs. Commands, write data, and
read data arrive at the DDR2 memory controller parallel to each other. The same peripheral bus is used to
write and read data from external memory as well as internal memory-mapped registers.
Table 6. DDR2 Memory Controller FIFO Description
24
Depth (64-Bit
Doublewords)
FIFO
Description
Command
Stores all commands coming from on-chip requestors
7
Write
Stores write data coming from on-chip requestors to
memory
11
Read
Stores read data coming from memory to on-chip
requestors
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Figure 15. DDR2 Memory Controller FIFO Block Diagram
Command FIFO
Command/Data
Scheduler
Command
to Memory
EDMA BUS
Write FIFO
Write Data
to Memory
Read FIFO
Read Data
from
Memory
Registers
Command
Data
2.7.1
Command Ordering and Scheduling, Advanced Concept
The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve
efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address,
and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows. Command
re-ordering takes place within the command FIFO.
The DDR2 memory controller examines all the commands stored in the command FIFO to schedule
commands to the external memory. For each master, the DDR2 memory controller reorders the
commands based on the following rules:
• Selects the oldest command
• A read command is advanced before an older write command if the read is to a different block address
(2048 bytes) and the read priority is equal to or greater than the write priority.
NOTE: Most masters issue commands on a single priority level. Also, the EDMA transfer controller
read and write ports are considered different masters, and thus, the above rule does not
apply.
The second bullet above may be viewed as an exception to the first bullet. This means that for an
individual master, all of its commands will complete from oldest to newest, with the exception that a read
may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master
may have one command ready for execution.
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Next, the DDR2 memory controller examines each of the commands selected by the individual masters
and performs the following reordering:
• Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes
to rows already open.
• Selects the highest priority command from pending reads and writes to open rows. If multiple
commands have the highest priority, then the DDR2 memory controller selects the oldest command.
The DDR2 memory controller may now have a final read and write command. If the Read FIFO is not full,
then the read command will be performed before the write command, otherwise the write command will be
performed first.
Besides commands received from on-chip resources, the DDR2 memory controller also issues refresh
commands. The DDR2 memory controller attempts to delay refresh commands as long as possible to
maximize performance while meeting the SDRAM refresh requirements. As the DDR2 memory controller
issues read, write, and refresh commands to DDR2 SDRAM device, it follows the following priority
scheme:
1. (Highest) Refresh request resulting from the Refresh Must level of urgency (see Section 2.8) being
reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency (see Section 2.8) being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency (see Section 2.8) being reached
6. (Lowest) Request to enter self-refresh mode
The following results from the above scheduling algorithm:
• All writes from a single master will complete in order
• All reads from a single master will complete in order
• From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
2.7.2
Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2 memory controller. Command
starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2 SDRAM commands to a row in an open bank can block commands to
the closed row in the same bank.
To avoid these conditions, the DDR2 memory controller can momentarily raise the priority of the oldest
command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE field
in the Burst Priority Register (BPRIO) sets the number of the transfers that must be made before the
DDR2 memory controller will raise the priority of the oldest command.
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2.7.3
Possible Race Condition
A race condition may exist when certain masters write data to the DDR2 memory controller. For example,
if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that
the write completes, when master B attempts to read the software message it may read stale data and
therefore receive an incorrect message. In order to confirm that a write from master A has landed before a
read from master B is performed, master A must wait for the write completion status from the DDR2
memory controller before indicating to master B that the data is ready to be read. If master A does not
wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2 memory controller module ID and revision register.
3. Perform a dummy read to the DDR2 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
For a list of the master peripherals that need this workaround, see the TMS320C6474 Multicore Digital
Signal Processor data manual (SPRS552).
2.8
Refresh Scheduling
The DDR2 memory controller issues autorefresh (REFR) commands to DDR2 SDRAM devices at a rate
defined in the refresh rate (REFRESH_RATE) bit field in the SDRAM refresh control register (SDRFC). A
refresh interval counter is loaded with the value of the REFRESH_RATE bit field and decrements by 1
each cycle until it reaches zero. Once the interval counter reaches zero, it reloads with the value of the
REFRESH_RATE bit. Each time the interval counter expires, a refresh backlog counter increments by 1.
Conversely, each time the DDR2 memory controller performs a REFR command, the backlog counter
decrements by 1. This means the refresh backlog counter records the number of REFR commands the
DDR2 memory controller currently has outstanding.
The DDR2 memory controller issues REFR commands based on the level of urgency. The level of
urgency is defined in Table 7. Whenever the refresh level of urgency is reached, the DDR2 memory
controller issues a REFR command before servicing any new memory access requests. Following a REFR
command, the DDR2 memory controller waits T_RFC cycles, defined in the SDRAM timing 1 register
(SDTIM1), before rechecking the refresh urgency level.
In addition to the refresh counter previously mentioned, a separate backlog counter ensures the interval
between two REFR commands does not exceed 8× the refresh rate. This backlog counter increments by 1
each time the interval counter expires and resets to zero when the DDR2 memory controller issues a
REFR command. When this backlog counter is greater than 7, the DDR2 memory controller issues four
REFR commands before servicing any new memory requests.
The refresh counters do not operate when the DDR2 memory is in self-refresh mode.
Table 7. Refresh Urgency Levels
Urgency Level
Description
Refresh May
Backlog count is greater than 0. Indicates there is a backlog of REFR commands, when the DDR2 memory
controller is not busy it will issue the REFR command.
Refresh Release
Backlog count is greater than 3. Indicates the level at which enough REFR commands have been performed
and the DDR2 memory controller may service new memory access requests.
Refresh Need
Backlog count is greater than 7. Indicates the DDR2 memory controller should raise the priority level of a
REFR command above servicing a new memory access.
Refresh Must
Backlog count is greater than 11. Indicates the level at which the DDR2 memory controller should perform a
REFR command before servicing new memory access requests.
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Self-Refresh Mode
Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2
memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the
DDR2 SDRAM maintains valid data while consuming a minimal amount of power. When the SR bit is
asserted, the DDR2 memory controller continues normal operation until all outstanding memory access
requests have been serviced and the refresh backlog has been cleared. At this point, all open pages of
DDR2 SDRAM are closed and a self-refresh (SLFRFR) command (an autorefresh command with
DSDCKE low) is issued.
The DDR2 memory controller exits the self-refresh state when a memory access is received or when the
SR bit in SDRFC is cleared. While in the self-refresh state, if a request for a memory access is received,
the DDR2 memory controller services the memory access request, returning to the self-refresh state upon
completion.
The DDR2 memory controller will not exit the self-refresh state (whether from a memory access request or
from clearing the SR bit) until T_CKE + 1 cycles have expired since the self-refresh command was issued.
The value of T_CKE is defined in the SDRAM timing 2 register (SDTIM2).
After exiting from the self-refresh state, the DDR2 memory controller will not immediately start using
commands. Instead, it will wait T_XSNR+1 clock cycles before issuing non-read commands and
T_XSRD+1 clock cycles before issuing read commands. The SDRAM timing 2 register (SDTIM2)
programs the values of T_XSNR+1 and T_XSRD+1.
2.10 Reset Considerations
The DDR2 memory controller can be reset through a hard reset or a soft reset. A hard reset resets the
state machine, the FIFOs, and the internal registers. A soft reset only resets the state machine and the
FIFOs. A soft reset does not reset the internal registers except for the interrupt registers. Register
accesses cannot be performed while either reset is asserted.
The DDR2 memory controller hard and soft reset are derived from device-level resets. C6474 devices
have several types of device-level resets: power-on reset, warm reset, max reset, system reset, and CPU
reset. Table 8 shows the relationship between the device-level resets and the DDR2 memory controller
resets.
Table 8. Device and DDR2 Memory Controller Reset Relationship
DDR2 Memory
Controller Reset
Effect
Initiated by:
Hard reset
Resets control logic and all DDR2 memory
controller registers
Power on reset
Warm reset
Max reset
Soft reset
Resets control logic and interrupt registers
System reset
CPU reset
In case of a warm reset on the DSP, the DDR2 SDRAM memory content can be retained if the user
places the DDR2 SDRAM in self-refresh mode before invoking the warm reset. However, the DDR2
memory controller registers will be reset and need to be reprogrammed to the required values after the
warm reset. For more information on the device-level resets, see the TMS320C6474 Multicore Digital
Signal Processor data manual (SPRS552).
2.11 DDR2 SDRAM Memory Initialization
DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation
for the device. These registers control parameters such as burst type, burst length, and CAS latency. The
DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by
issuing MRS and EMRS commands during the initialization sequence described in Section 2.11.2 and
Section 2.11.3. The initialization sequence performed by the DDR2 memory controller is compliant with
the JESDEC79-2A specification.
The DDR2 memory controller performs the initialization sequence under the following conditions:
• Automatically following a hard or soft reset, see Section 2.11.2.
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•
Following a write to the two least-significant bytes in the SDRAM configuration register (SDCFG); see
Section 2.11.3.
At the end of the initialization sequence, the DDR2 memory controller performs an auto-refresh cycle,
leaving the DDR2 memory controller in an idle state with all banks deactivated.
When the initialization section is started automatically after a hard or soft reset, commands and data
stored in the DDR2 memory controller FIFOs are lost. However, when the initialization sequence is
initiated by a write to the two least-significant bytes in SDCFG, data and commands stored in the DDR2
memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands
are completed before starting the initialization sequence.
2.11.1
DDR2 SDRAM Device Mode Register Configuration Values
The DDR2 memory controller initializes the mode register and extended mode register 1 of the memory
device with the values shown on Table 9 and Table 10. The DDR2 SDRAM extended mode registers 2
and 3 are configured with a value of 0h.
Table 9. DDR2 SDRAM Mode Register Configuration
Mode
Register Bit Mode Register Field
12
11-9
Init Value
Power-down Mode
Write Recovery
Description
0
Active power-down exit time bit. Configured for Fast exit.
SDTIM1.T_WR
Write recovery bits for auto-precharge. Initialized using
the T_WR bits of the SDRAM timing 1 register (SDTIM1).
8
DLL Reset
0
DLL reset bits. DLL is not in reset.
7
Mode
0
Operating mode bit. Normal operating mode is always
selected.
6-4
3
2-0
CAS Latency
SDCFG.CL
CAS latency bits. Initialized using the CL bits of the
SDRAM configuration register (SDCFG).
Burst Type
0
Burst type bits. Sequential burst mode is always used.
Burst Length
3h
Bust length bits. A burst length of 8 is always used.
Table 10. DDR2 SDRAM Extended Mode Register 1 Configuration
Mode
Register Bit Mode Register Field
Init Value
Description
12
Output Buffer Enable
0
Output buffer enable bits. Output buffer is always
enabled.
11
RDQS Enable
0
RDQS enable bits. Always initialized to 0 (RDQS signals
disabled.)
10
DQS enable
0
DQS enable bit. Always initialized to 0 (DQS signals
enabled.)
9-7
OCD Operation
0h
Off-chip driver impedance calibration bits. This bit is
always initialized to 0h.
6
ODT Value (Rtt)
0
On-die termination effective resistance (Rtt) bit. Together
with bit 2, this bit selects the value for Rtt as 75 Ω. (This
bit is available only on TCI6484/TCI6487/TCI6488
devices.)
5-3
Additive Latency
0h
Additive latency bits. Always initialized to 0h (no additive
latency).
2
ODT Value (Rtt)
1
On-die termination effective resistance (Rtt) bit. Together
with bit 2, this bit selects the value for Rtt as 75 Ω. (This
bit is available only on TCI6484/TCI6487/TCI6488
devices.)
1
Output Driver Impedance
SDCFG.DDR_DRIVE
Output driver impedance control bits. Initialized using the
DDR_DRIVE bit of the SDRAM configuration register
(SDCFG).
0
DLL Enable
0
DLL enable/disable bits. DLL is always enabled.
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DDR2 SDRAM Initialization After Reset
After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence.
The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and
the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device(s). Note
that since a soft reset does not reset the DDR2 memory controller registers, an initialization sequence
started by a soft reset would use the register values from a previous configuration.
2.11.3
DDR2 SDRAM Initialization After Register Configuration
The initialization sequence can also be initiated by performing a write to the two least-significant bytes in
the SDRAM configuration register (SDCFG). Using this approach, data and commands stored in the
DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write
commands are completed before starting the initialization sequence.
Perform the following steps to start the initialization sequence:
1. Set the BOOT_UNLOCK bit and the TIMUNLOCK bit in the SDRAM configuration register (SDCFG).
2. Program the SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) with the
value needed to meet the DDR2 SDRAM device timings.
3. Program the read latency (RL) bit in the DDR2 memory controller control register (DMCCTL) to the
desired value. Ensure that the reserved fields are not changed.
4. Program the REFRESH_RATE bits in the SDRAM refresh control register (SDRFC) to a value that
meets the refresh requirements of the DDR2 SDRAM device.
5. Program SDCFG with the desired value leaving the TIMUNLOCK bit set and the BOOT_UNLOCK bit
cleared. Ensure that the reserved fields are not changed.
6. Clear the TIMUNLOCK bit.
2.12 Interrupt Support
The DDR2 memory controller does not generate any interrupts.
2.13 EDMA Event Support
The DDR2 memory controller is a DMA slave peripheral and therefore does not generate EDMA events.
Data read and write requests may be made directly by masters including the EDMA controller.
2.14 Emulation Considerations
The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access
to external memory.
30
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3
Using the DDR2 Memory Controller
The following sections show various ways to connect the DDR2 memory controller to DDR2 memory
devices. The steps required to configure the DDR2 memory controller for external memory access are
also described.
3.1
Connecting the DDR2 Memory Controller to DDR2 SDRAM
Figure 16, Figure 17, and Figure 18 show a high-level view of the three memory topologies
• A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices
• A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device
• A 16-bit wide configuration interfacing to two 8-bit wide DDR2 SDRAM devices
All DDR2 SDRAM devices must be complaint to the JESD79-2B standard.
Not all of the memory topologies shown may be supported by your device. For more information, see the
TMS320C6474 Multicore Digital Signal Processor data manual (SPRS552).
Printed circuit board (PCB) layout rules and connection requirements between the DSP and the memory
device exist and are described in a separate document. For more information, see the TMS320C6474
Multicore Digital Signal Processor data manual (SPRS552).
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Figure 16. Connecting to Two 16-Bit DDR2 SDRAM Device
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DDR2
DCE0
Memory
DSDWE
Controller
DSDRAS
DSDCAS
DSDDQM0
DSDDQM1
DSDDQS0
DSDDQS0
DSDDQS1
DSDDQS1
DBA[2:0]
DEA[13:0]
DED[15:0]
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
LDQS
UDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
VREF
DSDDQM2
DSDDQM3
ODT
VREF
DSDDQS2
DSDDQS2
DSDDQS3
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
LDQS
UDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DSDDQS3
DED[31:16]
DDRODT
DDRSLRATE
DDR2
Memory
x16-bit
VDD
(A)
DSDDQGATE0
(A)
DSDDQGATE1
(A)
DSDDQGATE2
(A)
DSDDQGATE3
DDR2
Memory
x16-bit
ODT
VREF
A
32
These pins are used as a timing reference during memory reads. For routing rules, see the TMS320C6474 Multicore
Digital Signal Processor data manual (SPRS552).
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Figure 17. Connecting to a Single 16-Bit DDR2 SDRAM Device
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DDR2
DCE0
Memory
DSDWE
Controller
DSDRAS
DSDCAS
DSDDQM0
DSDDQM1
DSDDQS0
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
LDQS
DSDDQS0
DSDDQS1
DSDDQS1
DBA[2:0]
DEA[13:0]
DED[15:0]
DDRODT
VREFSSTL
DDRSLRATE
VREF
DDR2
Memory
x16-bit
UDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
ODT
VREF
VDD
(A)
DSDDQGATE0
(A)
DSDDQGATE1
(A)
DSDDQGATE2
(A)
DSDDQGATE3
A
These pins are used as a timing reference during memory reads. For routing rules, see the TMS320C6474 Multicore
Digital Signal Processor data manual (SPRS552).
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Figure 18. Connecting to Two 8-Bit DDR2 SDRAM Devices
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
DDR2
DCE0
Memory
DSDWE
Controller
DSDRAS
DSDCAS
DSDDQM0
DSDDQS0
DSDDQS0
CK
CK
CKE
CS
WE
RAS
CAS
DM
DQS
DQS
RDQS
RDQS
BA[2:0]
A[13:0]
DQ[7:0]
VREF
DBA[2:0]
DEA[13:0]
DED[7:0]
DSDDQM1
DSDDQS1
DSDDQS1
DED[15:8]
DDRODT
VREFSSTL
DDRSLRATE
DDR2
Memory
x8-bit
ODT
VREF
CK
CK
CKE
CS
WE
RAS
CAS
DM
DQS
DQS
RDQS
RDQS
BA[2:0]
A[13:0]
DQ[7:0]
VDD
(A)
DSDDQGATE0
(A)
DSDDQGATE1
(A)
DSDDQGATE2
(A)
DSDDQGATE3
DDR2
Memory
x8-bit
ODT
VREF
A
34
These pins are used as a timing reference during memory reads. For routing rules, see the TMS320C6474 Multicore
Digital Signal Processor data manual (SPRS552).
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3.2
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. This
provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By
programming the SDRAM Configuration Register (SDCFG), SDRAM Refresh Control Register (SDRFC),
SDRAM Timing 1 Register (SDTIM1), and SDRAM Timing 2 Register (SDTIM2), the DDR2 memory
controller can be configured to meet the data sheet specification for JESD79-2B compliant DDR2 SDRAM
devices.
As an example, the following sections describe how to configure each of these registers for access to two
1Gb, 16-bit wide DDR2 SDRAM devices connected as shown on , where each device has the following
configuration:
•
•
•
•
Maximum data rate: 533MHz
Number of banks: 8
Page size: 1024 words
CAS latency: 4
It is assumed that the frequency of the DDR2 memory controller clock (DDR2CLKOUT) is set to 250MHz.
3.2.1
Programming the SDRAM Configuration Register (SDCFG)
The SDRAM configuration register (SDCFG) contains register fields that configure the DDR2 memory
controller to match the data bus width, CAS latency, number of banks, and page size of the attached
DDR2 memory.
Table 11 shows the resulting SDCFG configuration. Note that the value of the TIMUNLOCK field is
dependent on whether or not it is desirable to unlock SDTIM1 and SDTIM2. The TIMUNLOCK bit should
only be set to 1 when the SDTIM1 and SDTIM2 needs to be updated.
Table 11. SDCFG Configuration
Field
TIMUNLOCK
3.2.2
Value
x
Function Selection
Set to 1 to unlock the SDRAM timing and timing 2 registers. Cleared to 0 to lock the SDRAM
timing and timing 2 registers.
NM
0h
To configure the DDR2 memory controller for a 32-bit data bus width.
CL
4h
To select a CAS latency of 4.
IBANK
3h
To select 8 internal DDR2 banks.
PAGESIZE
2h
To select 1024-word page size.
Programming the SDRAM Refresh Control Register (SDRFC)
The SDRAM refresh control register (SDRFC) configures the DDR2 memory controller to meet the refresh
requirements of the attached DDR2 device. SDRFC also allows the DDR2 memory controller to enter and
exit self refresh. In this example, we assume that the DDR2 memory controller is not is in self-refresh
mode.
The REFRESH_RATE field in SDRFC is defined as the rate at which the attached DDR2 device is
refreshed in DDR2 cycles. The value of this field may be calculated using the following equation:
REFRESH_RATE = DDR2CLKOUT frequency × memory refresh period
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Table 12 displays the DDR2-533 refresh rate specification.
Table 12. DDR2 Memory Refresh Specification
Symbol
Description
Value
tREF
Average Periodic Refresh Interval
7.8 μs
Therefore, the value for the REFRESH-RATE can be calculated as follows:
REFRESH_RATE = 250 MHz × 7.8 μs = 1950 = 79Eh
Table 13 shows the resulting SDRFC configuration.
Table 13. SDRFC Configuration
Field
Value
SR
0
REFRESH_RATE
3.2.3
Function Selection
DDR2 memory controller is not in self-refresh mode.
79Eh
Set to 79Eh DDR2 clock cycles to meet the DDR2 memory refresh rate
requirement.
Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)
The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2
memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in
SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 14
and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along
with the data sheet value. These tables also provide a formula to calculate the register field value and
displays the resulting calculation. Each of the equations include a minus 1 because the register fields are
defined in terms of DDR2 clock cycles minus 1. See Section 4.5 and Section 4.6 for more information.
Table 14. SDTIM1 Configuration
36
Register Field
Name
DDR2 SDRAM
Data Sheet
Parameter Name
Description
T_RFC
tRFC
Refresh cycle time
T_RP
tRP
T_RCD
Data Sheet
Value (ns)
Formula (Register Field Must
Be ≥)
Field
Value
127.5
(tRFC × fDDR2_CLK) - 1
31
Precharge command to
refresh or activate
command
15
(tRP × fDDR2_CLK) - 1
3
tRCD
Activate command to
read/write command
15
(tRCD × fDDR2_CLK) - 1
3
T_WR
tWR
Write recovery time
15
(tWR × fDDR2_CLK) - 1
3
T_RAS
tRAS
Active to precharge
command
45
(tRAC × fDDR2_CLK) - 1
11
T_RC
tRC
Activate to Activate
command in the same
bank
60
(tRC × fDDR2_CLK) - 1
14
T_RRD
tRRD
Activate to Activate
command in a different
bank
10
( (4*trrd + 2*tck) / (4*tck) ) - 1
2
T_WTR
tWTR
Write to read command
delay
7.5
(tWTR × fDDR2_CLK) - 1
1
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Table 15. SDTIM2 Configuration
3.2.4
Register Field
Name
DDR2 SDRAM Data
Sheet Parameter
Name
Description
Data Sheet
Value
Formula (Register
Field Must Be ≥)
Field
Value
T_ODT
tAOND
tAOND specifies the ODT turn-on
delay
2 (tCK cycles)
tAOND
2
T_XSNR
tXSNR
Exit self refresh to a non-read
command
137.5 ns
(tXSNR × fDDR2_CLK) - 1
34
T_XSRD
tXSRD
Exit self refresh to a read
command
200 (tCK cycles)
(tXSRD) - 1
199
T_RTP
tRTP
Read to precharge command
delay
7.5 ns
(tRTP × fDDR2_CLK) - 1
1
T_CKE
tCKE
CKE minimum pulse width
3 (tCK cycles)
(tCKE) - 1
2
Configuring the DDR2 Memory Controller Control Register (DMCCTL)
The DDR2 memory controller control register (DMCCTL) contains a read latency (RL) field that helps the
DDR2 memory controller determine when to sample read data. The RL field should be programmed to a
value equal to CAS latency + 1. For example, if a CAS latency of 4 is used, then RL should be
programmed to 5.
Table 16. DMCCTL Configuration
Register
Value
Register Field Name
Description
IFRESET
Programmed to be out of reset.
0
RL
Read latency is equal to CAS latency + 1.
5
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DDR2 Memory Controller Registers
Table 17 lists the memory-mapped registers for the DDR2 memory controller. For the memory address of
these registers, see the TMS320C6474 Multicore Digital Signal Processor data manual (SPRS552).
Table 17. DDR2 Memory Controller Registers
Offset
38
Acronym
00h
MIDR
04h
DMCSTAT
08h
Register Description
Section
Module ID and Revision Register
Section 4.1
DDR2 Memory Controller Status Register
Section 4.2
SDCFG
SDRAM Configuration Register
Section 4.3
0Ch
SDRFC
SDRAM Refresh Control Register
Section 4.4
10h
SDTIM1
SDRAM Timing 1 Register
Section 4.5
14h
SDTIM2
SDRAM Timing 2 Register
Section 4.6
20h
BPRIO
Burst Priority Register
Section 4.7
E4h
DMCCTL
DDR2 Memory Controller Control Register
Section 4.8
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4.1
Module ID and Revision Register (MIDR)
The Module ID and Revision register (MIDR) is shown in Figure 19 and described in Table 18.
Figure 19. Module ID and Revision Register (MIDR)
31
30
28
27
16
Reserved
MOD_ID
R-0x4
R-0x034
15
8
7
6
5
0
MJ_REV
Reserved
MN_REV
R-0x0B
R-0x0
R-0x1F
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Module ID and Revision Register (MIDR) Field Descriptions
Bit
Field
Value
Description
31-28
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
27-16
MOD_ID
Module ID bits.
15-8
MJ_REV
Major revision.
7-6
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
5-0
MN_REV
Minor revision.
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DDR2 Memory Controller Status Register (DMCSTAT)
The DDR2 memory controller status register (DMCSTAT) is shown in Figure 20
Figure 20. DDR2 Memory Controller Status Register (DMCSTAT)
31
30
29
16
BE
DUAL
_CLK_
MODE
Reserved
R-0x0
R-0x1
R-0x0
15
3
2
1
0
Reserved
IFRDY
Reserved
R-0x0
R-0x0
R-0x0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
Bit
Field
31
BE
Big endian. Reflects the value on the BIG_ENDIAN port that defines whether the EMIF is in
big- or little-endian mode.
30
DUAL_CLK_MODE
Dual clock mode. Reflects the value on the DUAL_CLK_MODE port that defines whether the
VCLK and MCLK inputs are asynchronous.
29-3
2
1-0
40
Reserved
Value
0
IFRDY
Reserved
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
DDR2 memory controller interface logic ready bit. The interface logic controls the signals used
to communicate with DDR2 SDRAM devices. This bit displays the status of the interface logic.
0
Interface logic is not ready; either powered down, not ready, or not locked.
1
Interface logic is powered up, locked, and ready for operation.
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
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4.3
SDRAM Configuration Register (SDCFG)
The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to
meet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to match
the data bus width, CAS latency, number of internal banks, and page size of the external DDR2 memory.
Bits 0-14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 (unlocked). for
more information on initializing the configuration registers of the DDR2 memory controller, see
Section 2.11.1. The SDCFG register is shown in Figure 21 and described in Table 20.
Figure 21. SDRAM Configuration Register (SDCFG)
31
28
23
27
26
24
Reserved
DDR2_
TERM[1]
Reserved
R-0x0
R/W-0x0
R-0x0
22
21
20
19
18
17
16
BOOT_
UNLOCK
DDR2_DDQS
DDR2_
TERM[0]
DDR2_
ENABLE
DDR_DISABLE
_DLL
SDRAM_
DRIVE[0]
DDR_ENABLE
SDRAM_
ENABLE
R/W-0x0
R/W-0x0
R/W-0x1
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
15
14
13
12
11
9
8
TIMUNLOCK
NM
Reserved
CL
Reserved
R-0x0
R-0x0
R-0x0
R-0x2
R-0x0
7
6
4
3
2
0
Reserved
IBANK
Reserved
PAGESIZE
R-0x0
R-0x2
R-0x0
R-0x0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions
Bit
31-28
27
26-24
23
22
21
20
Field
Value
Description
Reserved
Reserved. Writes to this register must keep these bits at their default values.
DDR2_TERM[1]
In combination with DDR2_TERM[0], defines termination resistor value Rtt in the extended
mode register of the SDRAM device. This bit is writeable only when the BOOT_UNLOCK bit is
unlocked (set to 1).
0
Disables termination.
1
75 Ω.
2
150 Ω.
3
50 Ω.
Reserved
Reserved. Writes to this register must keep these bits at their default values.
BOOT_UNLOCK
Boot unlock bit. Controls write access to bits 16-22 and 27 of this register.
0
Writes to bits 27, 22:16 of this register are not permitted.
1
Writes to bits 27, 22:16 of this register are allowed.
DDR2_DDQS
DDR2 SDRAM differential DQS enable. This bit is writeable only when the BOOT_UNLOCK
bit is unlocked (set to 1).
0
Single-ended DQS (not supported).
1
Differential DQS.
DDR2_TERM[0]
DDR2_ENABLE
In combination with DDR2_TERM[1], defines termination resistor value. This bit is writeable
only when the BOOT_UNLOCK bit is unlocked (set to 1).
0
Disables termination.
1
75 Ω.
2
150 Ω.
3
50 Ω.
DDR2 enable. This bit is only valid when the SDRAM_ENABLE and DDR_ENABLE bits are
set to 1. This bit is writeable only when the BOOT_UNLOCK bit is unlocked (set to 1).
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Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued)
Bit
Field
19
DDR_DISABLE_DLL
18
SDRAM_DRIVE[0]
Value
Description
Disable DLL select for DDR SDRAM. This bit is writeable only when the BOOT_UNLOCK bit
is unlocked.
1
Disables DLL inside DDR SDRAM.
DDR2 SDRAM drive strength. This bit is used to select the drive strength used by the DDR2
SDRAM. This bit is writeable only when BOOT_UNLOCK is unlocked (set to 1).
0
Normal drive strength.
1
Weak (60%) drive strength.
17
DDR_ENABLE
DDR enable. This bit is writeable only when the BOOT_UNLOCK bit is unlocked (set to 1).
This bit is only valid when SDRAM_ENABLE is set to 1.
16
SDRAM_ENABLE
SDRAM enable. This bit is writeable only when the BOOT_UNLOCK bit is unlocked (set to 1).
15
TIMUNLOCK
Timing unlock bit.Controls write access for the SDRAM Timing Register (SDTIM1) and
SDRAM Timing Register 2 (SDTIM2). A write to this bit causes the DDR2 Memory Controller
to start the SDRAM initialization sequence.
14
0
Register fields in the SDTIM1 and SDTIM2 registers may not be changed.
1
Register fields in the SDTIM1 and SDTIM2 registers may be changed.
NM
DDR2 data bus width. A write to this bit will cause the DDR2 Memory Controller to start the
SDRAM initialization sequence.
0
32-bit bus width.
1
16-bit bus width
13-12
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
11-9
CL
CAS latency. The value of this field defines the CAS latency, to be used when accessing
connected SDRAM devices. A write to this field will cause the DDR2 Memory Controller to
start the SDRAM initialization sequence. This field is writeable only when the TIMUNLOCK bit
is unlocked. Values 0, 1, 6, and 7 are reserved for this field.
CAS latency of 2.
3
CAS latency of 3.
4
CAS latency of 4.
5
CAS latency of 5.
8-7
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
6-4
IBANK
Internal SDRAM bank setup bits. Defines number of banks inside connected SDRAM devices.
A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization
sequence. Values 4-7 are reserved for this field.
3
2-0
42
2
0
One bank SDRAM devices.
1
Two banks SDRAM devices.
2
Four banks SDRAM devices.
3
Eight banks SDRAM devices.
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
PAGESIZE
Page size bits. Defines the internal page size of the external DDR2 memory. A write to this bit
will cause the DDR2 Memory Controller to start the SDRAM initialization sequence. Values 4-7
are reserved for this field.
0
256-word page requiring 8 column address bits.
1
512-word page requiring 9 column address bits.
2
1024-word page requiring 10 column address bits.
3
2048-word page requiring 11 column address bits.
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4.4
SDRAM Refresh Control Register (SDRFC)
The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to:
• Enter and Exit the self-refresh state.
• Meet the refresh requirement of the attached DDR2 device by programming the rate at which the
DDR2 memory controller issues autorefresh commands.
The SDRFC is shown in Figure 22 and described in Table 21.
Figure 22. SDRAM Refresh Control Register (SDRFC)
31
30
SR
Rsvd
29
16
Reserved
15
0
REFRESH_RATE
R/W-0x1388
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. SDRAM Refresh Control Register (SDRFC) Field Descriptions
Bit
Field
31
SR
Value
Description
Self-refresh bit. Writing a 1 to this bit will cause connected SDRAM devices to be place into Self
Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state.
0
Exit self-refresh mode.
1
Enter self-refresh mode.
30-16
Reserved
Reserved. Writes to this register must keep this field at its default value.
15-0
REFRESH_RATE
Refresh rate bits. The value in this field is used to define the rate at which connected SDRAM
devices will be refreshed as follows:
SDRAM refresh rate = DDR2CLKOUT clock rate / REFRESH_RATE
Writing a value less than 0x0100 to this field will cause it to be loaded with 2 * T_RFC value from
the SDRAM Timing 1 Register.
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4.5
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SDRAM Timing 1 Register (SDTIM1)
The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC
timing specification of the DDR2 memory. Note that DDR2CLKOUT is equal to the period of the
DDR2CLKOUT signal. For information on the appropriate values to program each field, see the DDR2
memory section of the TMS320C6474 Multicore Digital Signal Processor data manual (SPRS552). The bit
fields in the SDTIM1 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration
register (SDCFG) is unlocked. The SDTIM1 is shown in Figure 23 and described in Table 22.
Figure 23. SDRAM Timing 1 Register (SDTIM1)
31
25
24
22
21
19
18
16
T_RFC
T_RP
T_RCD
T_WR
R/W-0x2A
R/W-0x4
R/W-0x4
R/W-0x4
15
11
10
6
5
3
2
1
0
T_RAS
T_RC
T_RRD
Rsvd
T_WTR
R/W-0xE
R/W-0xB
R/W-0x3
R-0x0
R/W-0x2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions
Bit
Field
31-25
T_RFC
24-22
T_RP
21-19
T_RCD
Value
Description
These bits specify the minimum number of DDR2CLKOUT cycles from a refresh or load mode
command to a refresh or activate command, minus one. The value for these bits can be derived
from the trfc AC timing parameter in the DDR2 memory section of the TMS320C6474 Multicore
Digital Signal Processor data manual (SPRS552). Calculate using this formula:
T_RFC = (trfc/DDR2CLKOUT) - 1
These bits specify the minimum number of DDR2CLKOUT cycles from a precharge command to a
refresh or activate command, minus 1. The value for these bits can be derived from the trp AC
timing parameter in the DDR2 memory section of the TMS320C6474 Multicore Digital Signal
Processor data manual (SPRS552). Calculate using the formula:
T_RP = (trp/DDR2CLKOUT) - 1
These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a
read or write command, minus 1. The value for these bits can be derived from the trcd AC timing
parameter in the DDR2 memory section of the TMS320C6474 Multicore Digital Signal Processor
data manual (SPRS552). Calculate using the formula:
T_RCD = (trcd/DDR2CLKOUT) - 1
18-16
T_WR
These bits specify the minimum number of DDR2CLKOUT cycles from the last write transfer to a
precharge command, minus 1. The value for these bits can be derived from the twr AC timing
parameter in the DDR2 memory section of the TMS320C6474 Multicore Digital Signal Processor
data manual (SPRS552). Calculate using the formula:
T_WR = (twr/DDR2CLKOUT) - 1
The SDRAM initialization sequence will be started when the value of this field is changed from the
previous value and the DDR2_ENABLE in SDCFG is equal to 1.
15-11
T_RAS
These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a
precharge command, minus 1. The value for these bits can be derived from the tras AC timing
parameter in the DDR2 memory section of the TMS320C6474 Multicore Digital Signal Processor
data manual (SPRS552). Calculate using this formula:
T_RAS = (tras/DDR2CLKOUT) - 1
T_RAS must be greater than or equal to T_RCD.
10-6
T_RC
These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an
activate command, minus 1. The value for these bits can be derived from the trc AC timing
parameter in the DDR2 memory section of the TMS320C6474 Multicore Digital Signal Processor
data manual (SPRS552). Calculate using this formula:
T_RC = (trc/DDR2CLKOUT) - 1
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Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)
Bit
Field
5-3
T_RRD
Value
Description
These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an
activate command in a different bank, minus 1. The value for these bits can be derived from the trrd
AC timing parameter in the DDR2 memory section of the TMS320C6474 Multicore Digital Signal
Processor data manual (SPRS552). Calculate using this formula:
T_RRD = (trrd/DDR2CLKOUT) - 1
When connecting to an 8-bank DDR2 SDRAM, this field must be equal to:
T_RRD = ((4*trrd + 2*tck) / (4*tck)) - 1
2
1-0
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
T_WTR
These bits specify the minimum number of DDR2CLKOUT cycles from the last write to a read
command, minus 1. The value for these bits can be derived from the twtr AC timing parameter in the
DDR2 memory section of the TMS320C6474 Multicore Digital Signal Processor data manual
(SPRS552). Calculate using this formula:
T_WTR = (twtr/DDR2CLKOUT) - 1
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SDRAM Timing 2 Register (SDTIM2)
Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the
DDR2 memory controller to meet the AC timing specification of the DDR2 memory. For information on the
appropriate values to program each field, see the DDR2 memory section of the TMS320C6474 Multicore
Digital Signal Processor data manual (SPRS552). The bit fields in the SDTIM2 register are only writeable
when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked. SDTIM2 is shown
in Figure 24 and described in Table 23.
Figure 24. SDRAM Timing 2 Register (SDTIM2)
31
25
24
23
22
16
Reserved
T_ODT
T_XSNR
R-0x1E
R/W-0x1
R/W-0x2D
15
8
7
5
4
0
T_XSRD
T_RTP
T_CKE
R/W-0xC7
R/W-0x2
R/W-0x2
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 23. SDRAM Timing 2 Register (SDTIM2) Field Descriptions
Bit
Field
Value
Description
31-25
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
24-23
T_ODT
Minimum number of DDR clock cycles from ODT enable to write data driven for DDR2
SDRAM. T_ODT must be equal to tAOND.
22-16
T_XSNR
0-7Fh
15-8
T_XSRD
0-FFh
T_ODT = tAOND
These bits specify the minimum number of DDR2CLKOUT cycles from a self_refresh exit to
any other command except a read command, minus 1. The value for these bits can be derived
from the tXSNR AC timing parameter in the DDR2 section of the TMS320C6474 Multicore Digital
Signal Processor data manual (SPRS552). Calculate using this formula:
T_XSNR = tXSNR - 1
These bits specify the minimum number of DDR2CLKOUT cycles from a self_refresh exit to a
read command, minus 1. The value for these bits can be derived from the tXSRD AC timing
parameter in the DDR2 section of the TMS320C6474 Multicore Digital Signal Processor data
manual (SPRS552). Calculate using this formula:
T_XSRD = tXSRD - 1
7-5
T_RTP
0-7h
4-0
T_CKE
0-1Fh
These bits specify the minimum number of DDR2CLKOUT cycles from a last read command
to a precharge command, minus 1. The value for these bits can be derived from the trtp AC
timing parameter in the DDR2 section of the TMS320C6474 Multicore Digital Signal Processor
data manual (SPRS552). Calculate using this formula:
T_RTP = (trtp/DDR2CLKOUT) - 1
These bits specify the minimum number of DDR2CLKOUT cycles between transitions on the
DSDCKE pin, minus 1. The value for these bits can be derived from the tcke AC timing
parameter in the DDR2 section of the TMS320C6474 Multicore Digital Signal Processor data
manual (SPRS552). Calculate using this formula:
T_CKE = tcke - 1
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4.7
Burst Priority Register (BPRIO)
The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory
controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of
the oldest command in the command FIFO after a set number of transfers have been made. The
PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller
raises the priority of the oldest command. The BPRIO is shown in Figure 25 and described in Table 24.
For more details on command starvation, see Section 2.7.2.
Figure 25. Burst Priority Register (BPRIO)
31
16
Reserved
R-0x000000FF
15
8
7
0
Reserved
PRIO_RAISE
R-0x000000FF
R/W-0xFF
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Burst Priority Register (BPRIO) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
000h
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0
PRIO_RAISE
0h
1 memory transfer.
1h
2 memory transfers.
...
FEh
255 memory transfers.
FFh
EMIF reorders commands based on its arbitration.
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DDR2 Memory Controller Control Register (DMCCTL)
The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory
controller. The DMCCTL is shown in Figure 26 and described in Table 25.
Figure 26. DDR2 Memory Controller Control Register (DMCCTL)
31
3
2
0
Reserved
RL
R-0x000000FF
R/W-0x4
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
Bit
48
Field
Value
Description
31-3
Reserved
Reserved. Writes to this register must keep this field at its default value.
2-0
RL
Read latency bits. These bits must be set equal to the CAS latency + 1.
C6474 DDR2 Memory Controller
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Revision History
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Revision History
This revision history highlights the technical changes made to the document in this revision.
See
Table 1
Additions/Modifications/Deletions
Modified Description for DDRODT Pins
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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Revision History
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