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Texas Instruments TMS320DM646x DMSoC Enhanced Direct Memory Access Controller (EDMA) (Rev. B) User guides
TMS320DM646x DMSoC
Enhanced Direct Memory Access (EDMA3)
Controller
User's Guide
Literature Number: SPRUEQ5B
January 2011
2
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Preface ...................................................................................................................................... 10
1
Introduction ...................................................................................................................... 11
................................................................................................................ 11
................................................................................................................. 12
1.3
Functional Block Diagram ............................................................................................. 13
1.4
Terminology Used in This Document ............................................................................... 13
2
Architecture ...................................................................................................................... 15
2.1
Functional Overview ................................................................................................... 15
2.2
Types of EDMA3 Transfers ........................................................................................... 18
2.3
Parameter RAM (PaRAM) ............................................................................................ 21
2.4
Initiating a DMA Transfer ............................................................................................. 32
2.5
Completion of a DMA Transfer ....................................................................................... 36
2.6
Event, Channel, and PaRAM Mapping .............................................................................. 37
2.7
EDMA3 Channel Controller Regions ................................................................................ 40
2.8
Chaining EDMA3 Channels .......................................................................................... 43
2.9
EDMA3 Interrupts ...................................................................................................... 44
2.10 Event Queue(s) ........................................................................................................ 50
2.11 EDMA3 Transfer Controller (EDMA3TC) ........................................................................... 52
2.12 Event Dataflow ......................................................................................................... 55
2.13 EDMA3 Prioritization .................................................................................................. 56
2.14 EDMA3 Operating Frequency (Clock Control) ..................................................................... 57
2.15 Reset Considerations .................................................................................................. 57
2.16 Power Management ................................................................................................... 58
2.17 Emulation Considerations ............................................................................................. 58
3
EDMA3 Transfer Examples ................................................................................................. 59
3.1
Block Move Example .................................................................................................. 59
3.2
Subframe Extraction Example ........................................................................................ 61
3.3
Data Sorting Example ................................................................................................. 62
3.4
Peripheral Servicing Example ........................................................................................ 64
4
Registers .......................................................................................................................... 76
4.1
Register Memory Maps ............................................................................................... 76
4.2
Parameter RAM (PaRAM) Entries ................................................................................... 76
4.3
EDMA3 Channel Controller Control Registers ..................................................................... 82
4.4
EDMA3 Transfer Controller Control Registers .................................................................... 127
Appendix A Tips ...................................................................................................................... 150
A.1
Debug Checklist ..................................................................................................... 150
A.2
Miscellaneous Programming/Debug Tips ........................................................................ 151
Appendix B Setting Up a Transfer .............................................................................................. 152
Appendix C Revision History ..................................................................................................... 153
1.1
Overview
1.2
Features
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Table of Contents
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List of Figures
1
EDMA3 Controller Block Diagram ....................................................................................... 13
2
EDMA3 Channel Controller (EDMA3CC) Block Diagram ............................................................ 16
3
EDMA3 Transfer Controller (EDMA3TC) Block Diagram
17
4
Definition of ACNT, BCNT, and CCNT
18
5
6
7
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4
............................................................
................................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ......................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ....................................................
PaRAM Set .................................................................................................................
Linked Transfer ............................................................................................................
Link-to-Self Transfer ......................................................................................................
DMA Channel to PaRAM Mapping ......................................................................................
QDMA Channel to PaRAM Mapping ....................................................................................
Shadow Region Registers ................................................................................................
Interrupt Diagram ..........................................................................................................
Error Interrupt Operation .................................................................................................
EDMA3 Prioritization ......................................................................................................
Block Move Example ......................................................................................................
Block Move Example PaRAM Configuration ...........................................................................
Subframe Extraction Example ...........................................................................................
Subframe Extraction Example PaRAM Configuration ................................................................
Data Sorting Example .....................................................................................................
Data Sorting Example PaRAM Configuration ..........................................................................
Servicing Incoming ASP Data Example ................................................................................
Servicing Incoming ASP Data Example PaRAM ......................................................................
Servicing Peripheral Burst Example ....................................................................................
Servicing Peripheral Burst Example PaRAM ..........................................................................
Servicing Continuous ASP Data Example .............................................................................
Servicing Continuous ASP Data Example PaRAM ...................................................................
Servicing Continuous ASP Data Example Reload PaRAM ..........................................................
Ping-Pong Buffering for ASP Data Example ..........................................................................
Ping-Pong Buffering for ASP Example PaRAM .......................................................................
Ping-Pong Buffering for ASP Example Pong PaRAM ................................................................
Ping-Pong Buffering for ASP Example Ping PaRAM .................................................................
Intermediate Transfer Completion Chaining Example ................................................................
Single Large Block Transfer Example ..................................................................................
Smaller Packet Data Transfers Example ...............................................................................
Channel Options Parameter (OPT) .....................................................................................
Channel Source Address Parameter (SRC) ...........................................................................
A Count/B Count Parameter (A_B_CNT) ..............................................................................
Channel Destination Address Parameter (DST) ......................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ................................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) .......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ...............................................
C Count Parameter (CCNT) .............................................................................................
Peripheral ID Register (PID) .............................................................................................
EDMA3CC Configuration Register (CCCFG) ..........................................................................
DMA Channel Map n Registers (DCHMAPn) ..........................................................................
QDMA Channel Map n Registers (QCHMAPn) .......................................................................
List of Figures
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48
DMA Channel Queue Number Registers (DMAQNUMn) ............................................................ 89
49
QDMA Channel Queue Number Register (QDMAQNUM) ........................................................... 90
50
Event Missed Register (EMR) ........................................................................................... 91
51
Event Missed Register High (EMRH) ................................................................................... 91
52
Event Missed Clear Register (EMCR) .................................................................................. 92
53
Event Missed Clear Register High (EMCRH) .......................................................................... 92
54
QDMA Event Missed Register (QEMR) ................................................................................ 93
55
QDMA Event Missed Clear Register (QEMCR) ....................................................................... 94
56
EDMA3CC Error Register (CCERR) .................................................................................... 95
57
EDMA3CC Error Clear Register (CCERRCLR) ....................................................................... 96
58
Error Evaluation Register (EEVAL)
59
60
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..................................................................................... 97
DMA Region Access Enable Register for Region m (DRAEm) ..................................................... 98
DMA Region Access Enable High Register for Region m (DRAEHm) ............................................. 98
QDMA Region Access Enable for Region m (QRAEm) .............................................................. 99
Event Queue Entry Registers (QxEy) ................................................................................. 100
Queue n Status Register (QSTATn) ................................................................................... 101
Queue Watermark Threshold A Register (QWMTHRA) ............................................................ 102
EDMA3CC Status Register (CCSTAT)................................................................................ 103
Event Register (ER) ..................................................................................................... 105
Event Register High (ERH) ............................................................................................. 105
Event Clear Register (ECR) ............................................................................................ 106
Event Clear Register High (ECRH) .................................................................................... 106
Event Set Register (ESR) ............................................................................................... 107
Event Set Register High (ESRH) ...................................................................................... 108
Chained Event Register (CER)......................................................................................... 109
Chained Event Register High (CERH) ................................................................................ 109
Event Enable Register (EER) .......................................................................................... 110
Event Enable Register High (EERH) .................................................................................. 110
Event Enable Clear Register (EECR) ................................................................................. 111
Event Enable Clear Register High (EECRH) ......................................................................... 111
Event Enable Set Register (EESR) .................................................................................... 112
Event Enable Set Register High (EESRH) ........................................................................... 112
Secondary Event Register (SER) ...................................................................................... 113
Secondary Event Register High (SERH).............................................................................. 113
Secondary Event Clear Register (SECR) ............................................................................. 114
Secondary Event Clear Register High (SECRH) .................................................................... 114
Interrupt Enable Register (IER) ........................................................................................ 115
Interrupt Enable Register High (IERH) ................................................................................ 115
Interrupt Enable Clear Register (IECR) ............................................................................... 116
Interrupt Enable Clear Register High (IECRH) ....................................................................... 116
Interrupt Enable Set Register (IESR).................................................................................. 117
Interrupt Enable Set Register High (IESRH) ......................................................................... 117
Interrupt Pending Register (IPR) ....................................................................................... 118
Interrupt Pending Register High (IPRH) .............................................................................. 118
Interrupt Clear Register (ICR) .......................................................................................... 119
Interrupt Clear Register High (ICRH) .................................................................................. 119
Interrupt Evaluate Register (IEVAL) ................................................................................... 120
QDMA Event Register (QER) .......................................................................................... 121
QDMA Event Enable Register (QEER) ............................................................................... 122
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97
QDMA Event Enable Clear Register (QEECR) ...................................................................... 123
98
QDMA Event Enable Set Register (QEESR) ......................................................................... 124
99
QDMA Secondary Event Register (QSER) ........................................................................... 125
100
QDMA Secondary Event Clear Register (QSECR) .................................................................. 126
101
Peripheral ID Register (PID) ............................................................................................ 128
102
EDMA3TC Configuration Register (TCCFG) ......................................................................... 129
103
EDMA3TC Channel Status Register (TCSTAT) ..................................................................... 130
104
Error Register (ERRSTAT)
131
105
Error Enable Register (ERREN)
132
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6
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.......................................................................................
Error Clear Register (ERRCLR) ........................................................................................
Error Details Register (ERRDET) ......................................................................................
Error Interrupt Command Register (ERRCMD) ......................................................................
Read Rate Register (RDRATE) ........................................................................................
Source Active Options Register (SAOPT) ............................................................................
Source Active Source Address Register (SASRC) ..................................................................
Source Active Count Register (SACNT) ..............................................................................
Source Active Destination Address Register (SADST) .............................................................
Source Active Source B-Dimension Index Register (SABIDX) ....................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) .................................................
Source Active Count Reload Register (SACNTRLD) ...............................................................
Source Active Source Address B-Reference Register (SASRCBREF) ...........................................
Source Active Destination Address B-Reference Register (SADSTBREF) ......................................
Destination FIFO Options Register (DFOPTn) .......................................................................
Destination FIFO Source Address Register (DFSRCn) .............................................................
Destination FIFO Count Register (DFCNTn) .........................................................................
Destination FIFO Destination Address Register (DFDSTn) ........................................................
Destination FIFO B-Index Register (DFBIDXn) ......................................................................
Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) ............................................
Destination FIFO Count Reload Register (DFCNTRLDn) ..........................................................
Destination FIFO Source Address B-Reference Register (DFSRCBREFn)......................................
Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) .................................
List of Figures
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149
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List of Tables
1
EDMA3 Parameter RAM Contents ...................................................................................... 21
2
EDMA3 Channel Parameter Description ............................................................................... 23
3
Dummy and Null Transfer Request ..................................................................................... 26
4
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ...................................... 28
5
EDMA3 Channel Synchronization Events .............................................................................. 32
6
Expected Number of Transfers for Non-Null Transfer ................................................................ 36
7
Shadow Region Registers ................................................................................................ 40
8
EDMA3 Shadow Regions
9
Chain Event Triggers
10
11
12
13
14
15
16
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18
19
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................................................................................................ 42
..................................................................................................... 43
EDMA3 Transfer Completion Interrupts ................................................................................ 44
EDMA3 Error Interrupts ................................................................................................... 44
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping .................................................. 45
Number of Interrupts ...................................................................................................... 45
Read/Write Command Optimization Rules ............................................................................. 53
EDMA3 Transfer Controller Configurations ............................................................................ 55
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries ..................................... 76
Channel Options Parameters (OPT) Field Descriptions .............................................................. 77
Channel Source Address Parameter (SRC) Field Descriptions ..................................................... 78
A Count/B Count Parameter (A_B_CNT) Field Descriptions ........................................................ 79
Channel Destination Address Parameter (DST) Field Descriptions ................................................ 79
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions ......................... 80
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ................................. 80
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ......................... 81
C Count Parameter (CCNT) Field Descriptions ....................................................................... 81
EDMACC Registers ....................................................................................................... 82
Peripheral ID Register (PID) Field Descriptions ....................................................................... 86
EDMA3CC Configuration Register (CCCFG) Field Descriptions.................................................... 87
DMA Channel Map n Registers (DCHMAPn) Field Descriptions ................................................... 88
QDMA Channel Map n Registers (QCHMAPn) Field Descriptions ................................................. 88
DMA Channel Queue Number Registers (DMAQNUMn) Field Descriptions ...................................... 89
Bits in DMAQNUMn ...................................................................................................... 89
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ..................................... 90
Event Missed Register (EMR) Field Descriptions ..................................................................... 91
Event Missed Register High (EMRH) Field Descriptions ............................................................. 91
Event Missed Clear Register (EMCR) Field Descriptions ............................................................ 92
Event Missed Clear Register High (EMCRH) Field Descriptions ................................................... 92
QDMA Event Missed Register (QEMR) Field Descriptions .......................................................... 93
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................. 94
EDMA3CC Error Register (CCERR) Field Descriptions .............................................................. 95
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................. 96
Error Evaluation Register (EEVAL) Field Descriptions ............................................................... 97
DMA Region Access Enable Registers for Region m (DRAEm/DRAEHm) Field Descriptions ................. 98
QDMA Region Access Enable for Region m (QRAEm) Field Descriptions ........................................ 99
Event Queue Entry Registers (QxEy) Field Descriptions ........................................................... 100
Queue n Status Register (QSTATn) Field Descriptions ............................................................ 101
Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ...................................... 102
EDMA3CC Status Register (CCSTAT) Field Descriptions ......................................................... 103
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8
48
Event Register (ER) Field Descriptions ............................................................................... 105
49
Event Register High (ERH) Field Descriptions ....................................................................... 105
50
Event Clear Register (ECR) Field Descriptions ...................................................................... 106
51
Event Clear Register High (ECRH) Field Descriptions.............................................................. 106
52
Event Set Register (ESR) Field Descriptions
53
Event Set Register High (ESRH) Field Descriptions ................................................................ 108
54
Chained Event Register (CER) Field Descriptions .................................................................. 109
55
Chained Event Register High (CERH) Field Descriptions .......................................................... 109
56
Event Enable Register (EER) Field Descriptions .................................................................... 110
57
Event Enable Register High (EERH) Field Descriptions ............................................................ 110
58
Event Enable Clear Register (EECR) Field Descriptions ........................................................... 111
59
Event Enable Clear Register High (EECRH) Field Descriptions................................................... 111
60
Event Enable Set Register (EESR) Field Descriptions
61
Event Enable Set Register High (EESRH) Field Descriptions ..................................................... 112
62
Secondary Event Register (SER) Field Descriptions................................................................ 113
63
Secondary Event Register High (SERH) Field Descriptions ....................................................... 113
64
Secondary Event Clear Register (SECR) Field Descriptions
65
Secondary Event Clear Register High (SECRH) Field Descriptions .............................................. 114
66
Interrupt Enable Register (IER) Field Descriptions .................................................................. 115
67
Interrupt Enable Register High (IERH) Field Descriptions .......................................................... 115
68
Interrupt Enable Clear Register (IECR) Field Descriptions ......................................................... 116
69
Interrupt Enable Clear Register High (IECRH) Field Descriptions
70
Interrupt Enable Set Register (IESR) Field Descriptions ........................................................... 117
71
Interrupt Enable Set Register High (IESRH) Field Descriptions ................................................... 117
72
Interrupt Pending Register (IPR) Field Descriptions
73
Interrupt Pending Register High (IPRH) Field Descriptions ........................................................ 118
74
Interrupt Clear Register (ICR) Field Descriptions .................................................................... 119
75
Interrupt Clear Register High (ICRH) Field Descriptions
76
Interrupt Evaluate Register (IEVAL) Field Descriptions ............................................................. 120
77
QDMA Event Register (QER) Field Descriptions .................................................................... 121
78
QDMA Event Enable Register (QEER) Field Descriptions ......................................................... 122
79
QDMA Event Enable Clear Register (QEECR) Field Descriptions ................................................ 123
80
QDMA Event Enable Set Register (QEESR) Field Descriptions
81
QDMA Secondary Event Register (QSER) Field Descriptions..................................................... 125
82
QDMA Secondary Event Clear Register (QSECR) Field Descriptions
83
EDMA3 Transfer Controller Registers ................................................................................. 127
84
Peripheral ID Register (PID) Field Descriptions
85
EDMA3TC Configuration Register (TCCFG) Field Descriptions ................................................... 129
86
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ............................................... 130
87
Error Register (ERRSTAT) Field Descriptions ....................................................................... 131
88
Error Enable Register (ERREN) Field Descriptions ................................................................. 132
89
Error Clear Register (ERRCLR) Field Descriptions
90
Error Details Register (ERRDET) Field Descriptions................................................................ 134
91
Error Interrupt Command Register (ERRCMD) Field Descriptions ................................................ 135
92
Read Rate Register (RDRATE) Field Descriptions .................................................................. 136
93
Source Active Options Register (SAOPT) Field Descriptions ...................................................... 137
94
Source Active Source Address Register (SASRC) Field Descriptions ............................................ 138
95
Source Active Count Register (SACNT) Field Descriptions ........................................................ 138
96
Source Active Destination Address Register (SADST) Field Descriptions ....................................... 139
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List of Tables
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112
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124
126
128
133
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97
Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions .............................. 139
98
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ........................... 140
99
Source Active Count Reload Register (SACNTRLD) Field Descriptions ......................................... 141
100
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
101
102
103
104
105
106
107
108
109
110
111
112
....................
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ................
Destination FIFO Options Register (DFOPTn) Field Descriptions ................................................
Destination FIFO Source Address Register (DFSRCn) Field Descriptions ......................................
Destination FIFO Count Register (DFCNTn) Field Descriptions ...................................................
Destination FIFO Destination Address Register (DFDSTn) Field Descriptions ..................................
Destination FIFO B-Index Register (DFBIDXn) Field Descriptions ................................................
Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field Descriptions......................
Destination FIFO Count Reload Register (DFCNTRLDn) Field Descriptions ....................................
Destination FIFO Source Address B-Reference Register (DFSRCBREFn) Field Descriptions ...............
Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) Field Descriptions ...........
Debug List.................................................................................................................
Document Revision History .............................................................................................
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9
Preface
SPRUEQ5B – January 2011
Read This First
About This Manual
Describes the operation of the enhanced direct memory access (EDMA3) controller in the
TMS320DM646x Digital Media System-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copies
of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
The current documentation that describes the DM646x DMSoC, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUEP8 — TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
SPRUEP9 — TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the DSP subsystem and a majority
of the peripherals and external memories.
SPRUEQ0 — TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overview
and briefly describes the peripherals available on the TMS320DM646x Digital Media
System-on-Chip (DMSoC).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
10
Preface
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User's Guide
SPRUEQ5B – January 2011
Enhanced Direct Memory Access (EDMA3) Controller
1
Introduction
This document describes the features and operations of the enhanced direct memory access (EDMA3)
controller in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
The EDMA3 is a high-performance, multichannel, multithreaded DMA controller that allows you to program
a wide variety of transfer geometries and transfer sequences.
1.1
Overview
The enhanced direct memory access (EDMA3) controller’s primary purpose is to service
user-programmed data transfers between two memory-mapped slave endpoints on the device. Typical
usage includes, but is not limited to:
• Servicing software driven paging transfers (for example, from external memory such as SDRAM to
internal device memory such as DSP L2 SRAM
• Servicing event driven peripherals, such as a serial port
• Performing sorting or subframe extraction of various data structures
• Offloading data transfers from the main device CPU(s) or DSP(s) (See the device data manual for
specific peripherals that are accessible via EDMA3. See the section on SCR connectivity in the device
data manual for EDMA3 connectivity.)
The EDMA3 has a different architecture from the previous EDMA2 controller on the TMS320C621x/C671x
DSPs and TMS320C64x DSPs. (See the EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x
DMSoC (SPRAAA6) for more details on new/advanced features.)
The EDMA3 controller consists of two principal blocks:
• EDMA3 channel controller (EDMA3CC)
• EDMA3 transfer controller(s) (EDMA3TC)
The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CC
includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The
EDMA3CC serves to prioritize incoming software requests or events from peripherals, and submits
transfer requests (TR) to the transfer controller.
The EDMA3 transfer controllers are slaves to the EDMA3 channel controller and are responsible for data
movement. The transfer controller issues read/write commands to the source and destination addresses
programmed for a given transfer. The operation is transparent to you.
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Introduction
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Features
The EDMA3 channel controller has the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions
– A-synchronized transfers: 1 dimension serviced per event
– AB- synchronized transfers: 2 dimensions serviced per event
– Independent indexes on source and destination
– Chaining feature allows 3-D transfer based on single event
• Flexible transfer definition
– Increment or FIFO transfer addressing modes
– Linking mechanism allows automatic PaRAM set update
– Chaining allows multiple transfers to execute with one event
• Interrupt generation for:
– DMA completion
– Error conditions
• Debug visibility
– Queue watermarking/threshold
– Error and status recording to facilitate debug
• 64 DMA channels
– Event synchronization
– Manual synchronization (CPU(s) write to event set register)
– Chain synchronization (completion of one transfer chains to next)
• 8 QDMA channels
– QDMA channels are triggered automatically upon writing to a PaRAM set entry
– Support for programmable QDMA channel to PaRAM mapping
• 512 PaRAM sets
– Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)
• 4 transfer controllers/event queues. The system-level priority of these queues is user programmable.
(See the device data manual for the possible system priorities.)
• 16 event entries per event queue
The EDMA3 transfer controller has the following features:
• 4 transfer controllers
• 64-bit wide read and write ports per channel
• Up to 4 in-flight transfer requests (TR)
• Programmable priority level
• Supports 2 dimensional transfers with independent indexes on source and destination (EDMA3CC
manages the 3rd dimension)
• Support for increment or constant addressing mode transfers
• Interrupt and error support
12
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1.3
Functional Block Diagram
Figure 1 shows a block diagram for the EDMA3 controller.
Figure 1. EDMA3 Controller Block Diagram
Transfer
controllers
MMR
Channel controller
To/from
EDMA3
programmer
DMA/QDMA
channel
logic
Event
queue
PaRAM
Transfer
request
submission
TC0
Read/write
commands
and data
TC3
Read/write
commands
and data
TCERRINT0
MMR
CCINT[7:0]
CCERRINT
1.4
Completion
and error
interrupt
logic
Completion
detection
TCERRINT3
Terminology Used in This Document
The following is a brief explanation of some terms used in this document:
Term
A-synchronized transfer
AB-synchronized transfer
Chaining
CPU(s)
Device
DMA channel
Dummy set or Dummy PaRAM set
Dummy transfer
EDMA3 channel controller
(EDMA3CC)
EDMA3
programmer
EDMA3 transfer controller(s)
(EDMA3TC)
Enhanced direct memory access
(EDMA3)
controller
Link parameter set
Linking
Memory-mapped slave
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Meaning
A transfer type where 1 dimension is serviced per synchronization event.
A transfer type where 2 dimensions are serviced per synchronization event.
A trigger mechanism in which a transfer can be initiated at the completion of another transfer
or subtransfer.
The main processing engine or engines on a device. Typically a DSP or general-purpose
processor. (See the device data manual to learn more about the CPU on your system.)
TMS320DM646x DMSoC
One of the 64 channels that can be triggered by external, manual, and chained events. All
DMA channels exist in the EDMA3CC.
A PaRAM set for which at least one of the count fields is equal to 0 and at dummy PaRAM
least one of the count fields is nonzero. A null PaRAM set has all the count set fields
cleared.
A dummy set results in the EDMA3CC performing a dummy transfer. This is not an error
condition. A null set results in an error condition.
The user-programmable portion of the EDMA3. The EDMA3CC contains the parameter RAM
(PaRAM) , event processing logic, DMA/QDMA channels, event queues, etc. The EDMA3CC
services events (external, manual, chained, QDMA) and is responsible for submitting
transfer requests to the transfer controllers (EDMA3TC), which perform the actual transfer.
Any entity on the chip that has read/write access to the EDMA3 registers and can program
an EDMA3 transfer.
Transfer controllers are the transfer engine for the EDMA3. Performs the read/writes as
dictated by the transfer requests submitted by the EDMA3CC.
Consists of the EDMA3 channel controller (EDMA3CC) and EDMA3 transfer controller(s)
(EDMA3TC). Is referred to as EDMA3 in this document.
A PaRAM set that is used for linking.
The mechanism of reloading a PaRAM set with new transfer characteristics on completion of
the current transfer.
All on-chip memories, off-chip memories, and slave peripherals. These typically rely on the
EDMA3 (or other master peripheral) to perform transfers to and from them.
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Introduction
Term
Master
peripherals
Null set or Null PaRAM set
Null transfer
QDMA channel
Parameter RAM (PaRAM)
Parameter RAM (PaRAM) set
Parameter RAM (PaRAM) set entry
Slave end points
Transfer request (TR)
Trigger event
Trigger word
TR synchronization (sync) event
14
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Meaning
All peripherals that are capable of initiating read and write transfers to the peripherals
system and may not solely rely on the EDMA3 for their data transfers.
A PaRAM set that has all count fields cleared (except for the link field). A dummy PaRAM
set has at least one of the count fields nonzero.
A trigger event for a null PaRAM set results in the EDMA3CC performing a null transfer. This
is an error condition. A dummy transfer is not an error condition.
One of the 8 channels that can be triggered when writing to the trigger word (TRWORD) of a
PaRAM set. All QDMA channels exist in the EDMA3CC.
Programmable RAM that stores PaRAM sets used by DMA channels, QDMA channels, and
linking.
A 32-byte EDMA3 channel transfer definition. Each parameter set consists of 8 words (
4-bytes each), which store the context for a DMA/QDMA/link transfer. A PaRAM set includes
source address, destination address, counts, indexes, options, etc.
One of the 4-byte components of the parameter set.
All on-chip memories, off-chip memories, and slave peripherals. These rely on the EDMA3 to
perform transfers to and from them.
A command for data movement that is issued from the EDMA3CC to the EDMA3TC. A TR
includes source and destination addresses, counts, indexes, options, etc.
Action that causes the EDMA3CC to service the PaRAM set and submit a transfer request to
the EDMA3TC. Trigger events for DMA channels include manual triggered (CPU triggered),
external event triggered, and chain triggered. Trigger events for QDMA channels include
autotriggered and link triggered.
For QDMA channels, the trigger word specifies the PaRAM set entry that when written
results in a QDMA trigger event. The trigger word is programmed via the QDMA channel
map register (QCHMAP) and can point to any PaRAM set entry.
See Trigger Event.
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2
Architecture
This section discusses the architecture of the EDMA3 controller.
2.1
Functional Overview
This section provides a functional overview of the EDMA3 channel controller (EDMA3CC) and EDMA3
transfer controller (EDMA3TC).
2.1.1
EDMA3 Channel Controller (EDMA3CC)
Figure 2 shows a functional block diagram of the EDMA3 channel controller (EDMA3CC).
The main blocks of the EDMA3CC are:
• Parameter RAM (PaRAM): Maintains parameter set entries for channel and reload parameter sets. The
PaRAM needs to be written with the transfer context for the desired channels and link parameter sets.
EDMA3CC processes PaRAM sets based on a trigger event and submits a transfer request (TR) to the
transfer controller.
• EDMA3 event and interrupt processing registers: Enable/disable events, enable/disable interrupt
conditions, and clearing interrupts.
• Completion detection: The completion detect block detects completion of transfers by the EDMA3TC
and/or slave peripherals. Completion of transfers can optionally be used to chain trigger new transfers
or to assert interrupts.
• Event queues: These form the interface between the event detection logic and the transfer request
submission logic.
Other functions include:
• Region registers: Allows DMA resources (DMA channels and interrupts) to be assigned to unique
regions, which are owned by different EDMA3 programmers (for example, ARM or DSP).
• Debug registers: Allows debug visibility by providing registers to read the queue status, controller
status, and missed event status.
The EDMA3CC includes two channel types: DMA channels (64 channels) and QDMA channels
(8 channels).
Each channel is associated with a given event queue/transfer controller, and with a given PaRAM set. The
main difference between a DMA channel and QDMA channel is how the transfers are triggered by the
system. Refer to Section 2.4.
A trigger event is needed to initiate a transfer. For DMA channels, a trigger event may be due to an
external event, manual write to the event set register, or chained event. QDMA channels are autotriggered
when a write is performed to the user-programmed trigger word. All such trigger events are logged into
appropriate registers upon recognition. Refer to DMA channel registers (Section 4.3.5) and QDMA
registers (Section 4.3.7).
Once a trigger event is recognized, the event type/channel is queued in the appropriate EDMA3CC event
queue. The assignment of each DMA/QDMA channel to event queue is programmable. Each queue is
16 deep, so up to 16 events may be queued (on a single queue) in the EDMA3CC at an instant in time.
Additional pending events mapped to a full queue are queued when event queue space becomes
available. Refer to Section 2.10.
If events on different channels are detected simultaneously, the events are queued based on fixed priority
arbitration scheme with the DMA channels being higher priority than the QDMA channels. Among the two
groups of channels, the lowest-numbered channel is the highest priority.
Each event in the event queue is processed in the order it was queued. On reaching the head of the
queue, the PaRAM associated with that channel is read to determine the transfer details. The TR
submission logic evaluates the validity of the TR and is responsible for submitting a valid transfer request
(TR) to the appropriate EDMA3TC (based on the event queue to EDMA3TC association, Q0 goes to TC0,
Q1 goes to TC1, etc.). For more details, see Section 2.3.
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Figure 2. EDMA3 Channel Controller (EDMA3CC) Block Diagram
From peripherals/external events
Event
enable
register
(EER/EERH)
64
15
Parameter
set 0
0
Queue 0
15
Parameter
set 1
0
Queue 1
15
0
Queue 2
Event
64
set
register
(ESR/ESRH)
15
0
Parameter
set 510
Queue 3
64
QDMA
event
register
(QER)
8
PaRAM
Queue bypass
Completion
interface
From
EDMA3TC0
QDMA trigger
EDMA3 channel
controller
To
EDMA3TC(s)
Parameter
set 511
Chained
event
register
(CER/CERH)
8:1 priority encoder
Chain
trigger
Transfer request submission
Manual
trigger
Event
queues
Event
register
(ER/ERH)
Channel mapping
Event
trigger
E1 E0
64:1 priority encoder
E63
Completion
detection
Error
detection
Completion
interrupt
From
EDMA3TC1
From
EDMA3TC2
From
EDMA3TC3
CCERRINT
CCINT[7:0]
to ARM/DSP/VICP0/VICP1
The EDMA3TC receives the request and is responsible for data movement as specified in the transfer
request packet (TRP) and other necessary tasks like buffering, ensuring transfers are carried out in an
optimal fashion wherever possible. For more details on EDMA3TC, see Section 2.1.2.
You may have chosen to receive an interrupt or chain to another channel on completion of the current
transfer in which case the EDMA3TC signals completion to the EDMA3CC completion detection logic
when the transfer is done. You can alternately choose to trigger completion when a TR leaves the
EDMA3CC boundary rather than wait for all the data transfers to complete. Based on the setting of the
EDMA3CC interrupt registers, the completion interrupt generation logic is responsible for generating
EDMA3CC completion interrupts to the CPU. For more details, see Section 2.5.
Additionally, the EDMA3CC also has an error detection logic, which causes error interrupt generation on
various error conditions (like missed events, exceeding event queue thresholds, etc.). For more details on
error interrupts, see Section 2.9.4.
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2.1.2
EDMA3 Transfer Controller (EDMA3TC)
Figure 3 shows a functional block diagram of the EDMA3 transfer controller (EDMA3TC).
The main blocks of the EDMA3TC are:
• DMA program register set: The DMA program register set stores the transfer requests received from
the EDMA3 channel controller (EDMA3CC).
• DMA source active register set: The DMA source active register set stores the context for the DMA
transfer request currently in progress in the read controller.
• Read controller: The read controller issues read commands to the source address.
• Destination FIFO register set: The destination (Dst) FIFO register set stores the context for the DMA
transfer request(s) currently in progress in the write controller.
• Write controller: The write controller issues write commands/write data to the destination slave.
• Data FIFO: The data FIFO exists for holding temporary in-flight data.
• Completion interface: The completion interface sends completion codes to the EDMA3CC when a
transfer completes, and is used for generating interrupts and chained events (also, refer to Section 2.5
for details on transfer completion reporting).
When the EDMA3TC is idle and receives its first TR, the TR is received in the DMA program register set,
where it transitions to the DMA source active set and the destination FIFO register set immediately. The
second TR (if pending from EDMA3CC) is loaded into the DMA program set, ensuring it can start as soon
as possible when the active transfer is completed. As soon as the current active set is exhausted, the TR
is loaded from the DMA program register set into the DMA source active register set as well as to the
appropriate entry in the destination FIFO register set.
The read controller issues read commands governed by the rules of command fragmentation and
optimization. These are issued only when the data FIFO has space available for the data read. When
sufficient data is in the data FIFO, the write controller starts issuing a write command again following the
rules for command fragmentation and optimization. For details on command fragmentation and
optimization, see Section 2.11.1.1.
Depending on the number of entries, the read controller can process up to 4 transfer requests ahead of
the destination subject to the amount of free data FIFO.
To completion
detection logic
in EDMA3CC
TCERRINTn
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SRC
Write
controller
Transfer request
submission
Program
register set
SRC active
register set
Read
controller
Figure 3. EDMA3 Transfer Controller (EDMA3TC) Block Diagram
Destination FIFO
register set
Read
command
Read data
Write
command
Write data
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Types of EDMA3 Transfers
An EDMA3 transfer is always defined in terms of three dimensions. Figure 4 shows the three dimensions
used by EDMA3 transfers. These three dimensions are defined as:
• 1st Dimension or Array (A): The 1st dimension in a transfer consists of ACNT contiguous bytes.
• 2nd Dimension or Frame (B): The 2nd dimension in a transfer consists of BCNT arrays of ACNT bytes.
Each array transfer in the 2nd dimension is separated from each other by an index programmed using
SRCBIDX or DSTBIDX.
• 3rd Dimension or Block (C): The 3rd dimension in a transfer consists of CCNT frames of BCNT arrays
of ACNT bytes. Each transfer in the 3rd dimension is separated from the previous by an index
programmed using SRCCIDX or DSTCIDX.
Note that the reference point for the index depends on the synchronization type. The amount of data
transferred upon receipt of a trigger/synchronization event is controlled by the synchronization types
(SYNCDIM bit in OPT). Of the three dimensions, only two synchronization types are supported:
A-synchronized transfers and AB-synchronized transfers.
Figure 4. Definition of ACNT, BCNT, and CCNT
ACNT bytes in
Array/1st dimension
Frame 0
Array 1
Array 2
Array BCNT
Frame 1
Array 1
Array 2
Array BCNT
Frame CCNT
Array 1
Array 2
Array BCNT
CCNT frames in
Block/3rd dimmension
BCNT arrays in Frame/2nd dimmension
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2.2.1
A-Synchronized Transfers
In an A-synchronized transfer, each EDMA3 sync event initiates the transfer of the 1st dimension of ACNT
bytes, or one array of ACNT bytes. In other words, each event/TR packet conveys the transfer information
for one array only. Thus, BCNT × CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by SRCBIDX and DSTBIDX, as shown in Figure 5, where the start address
of Array N is equal to the start address of Array N – 1 plus source (SRC) or destination (DST) BIDX.
Frames are always separated by SRCCIDX and DSTCIDX. For A-synchronized transfers, after the frame
is exhausted, the address is updated by adding SRCCIDX/DSTCIDX to the beginning address of the last
array in the frame. As in Figure 5, SRCCIDX/DSTCIDX is the difference between the start of Frame 0
Array 3 to the start of Frame 1 Array 0.
Figure 5 shows an A-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes. In
this example, a total of 12 sync events (BCNT × CCNT) exhaust a PaRAM set. See Section 2.3.6 for
details on parameter set updates.
Figure 5. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
Frame 0
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Array 0
Array 1
Array 2
Each array submit
as one TR
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 1
Array 0
(SRC|DST)
(SRC|DST)
BIDX
BIDX
Array 1
Array 2
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 2
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Array 0
(SRC|DST)
(SRC|DST)
BIDX
BIDX
Array 1
Array 2
Array 3
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AB-Synchronized Transfers
In a AB-synchronized transfer, each EDMA3 sync event initiates the transfer of 2 dimensions or one
frame. In other words, each event/TR packet conveys information for one entire frame of BCNT arrays of
ACNT bytes. Thus, CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 6. Frames are always
separated by SRCCIDX and DSTCIDX.
Note that for AB-synchronized transfers, after a TR for the frame is submitted, the address update is to
add SRCCIDX/DSTCIDX to the beginning address of the beginning array in the frame. This is different
from A-synchronized transfers where the address is updated by adding SRCCIDX/DSTCIDX to the start
address of the last array in the frame. See Section 2.3.6 for details on parameter set updates.
Figure 6 shows an AB-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes.
In this example, a total of 3 sync events (CCNT) exhaust a PaRAM set; that is, a total of 3 transfers of
4 arrays each completes the transfer.
Figure 6. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
AB_Sync transfer
Frame 0
(SRC|DST)
(SRC|DST)
(SRC|DST)
BIDX
BIDX
BIDX
Array 0
Array 1
Array 2
(SRC|DST)
(SRC|DST)
Each array submit
as one TR
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 1
Array 0
BIDX
BIDX
Array 1
Array 2
(SRC|DST)
(SRC|DST)
Array 3
(SRC|DST)
CIDX
(SRC|DST)
BIDX
Frame 2
Array 0
BIDX
Array 1
BIDX
Array 2
Array 3
NOTE: ABC-synchronized transfers are not directly supported. But can be logically achieved by
chaining between multiple AB-synchronized transfers.
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2.3
Parameter RAM (PaRAM)
The EDMA3 controller is a RAM-based architecture. The transfer context (source/destination addresses,
count, indexes, etc.) for DMA or QDMA channels is programmed in a parameter RAM table within
EDMA3CC, referred to as PaRAM. The PaRAM table is segmented into multiple PaRAM sets. Each
PaRAM set includes eight 4-byte PaRAM set entries (32-bytes total per PaRAM set), which includes
typical DMA transfer parameters such as source address, destination address, transfer counts, indexes,
options, etc. The PaRAM structure is shown in Table 1.
The PaRAM structure supports flexible ping-pong, circular buffering, channel chaining, and autoreloading
(linking). The contents of the PaRAM include:
• 512 PaRAM sets
• Any PaRAM entries can be used for DMA, QDMA, or link sets
• By default, all channels map to PaRAM set 0. These should be remapped before use. See the DMA
channel 0-63 mapping registers (Section 4.3.1.3) and the QDMA channel 0-7 mapping registers
(Section 4.3.1.4) for more information.
Table 1. EDMA3 Parameter RAM Contents
Address
Parameters
01C0 4000h to 01C0 401Fh
Parameters for event 0 (8 words)
01C0 4020h to 01C0 403Fh
Parameters for event 1 (8 words)
01C0 4040h to 01C0 405Fh
Parameters for event 2 (8 words)
01C0 4060h to 01C0 407Fh
Parameters for event 3 (8 words)
01C0 4080h to 01C0 409Fh
Parameters for event 4 (8 words)
01C0 40A0h to 01C0 40BFh
Parameters for event 5 (8 words)
01C0 40C0h to 01C0 40DFh
Parameters for event 6 (8 words)
01C0 40E0h to 01C0 40FFh
Parameters for event 7 (8 words)
01C0 4100h to 01C0 411Fh
Parameters for event 8 (8 words)
01C0 4120h to 01C0 413Fh
Parameters for event 9 (8 words)
01C0 4140h to 01C0 415Fh
Parameters for event 10 (8 words)
01C0 4160h to 01C0 417Fh
Parameters for event 11 (8 words)
01C0 4180h to 01C0 419Fh
Parameters for event 12 (8 words)
01C0 41A0h to 01C0 41BFh
Parameters for event 13 (8 words)
01C0 41C0h to 01C0 41DFh
Parameters for event 14 (8 words)
01C0 41E0h to 01C0 41FFh
Parameters for event 15 (8 words)
01C0 4200h to 01C0 421Fh
Parameters for event 16 (8 words)
...
...
01C0 7FC0h to 01C0 7FDFh
Parameters for event 510 (8 words)
01C0 7FE0h to 01C0 7FFFh
Parameters for event 511 (8 words)
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PaRAM Set
Each parameter set of PaRAM is organized into eight 32-bit words or 32 bytes, as shown in Figure 7 and
described in Table 2. Each PaRAM set consists of 16-bit and 32-bit parameters.
Figure 7. PaRAM Set
22
Byte
address
offset
Byte
address
Set
#
PaRAM
01C0 4000h
0
Parameter set 0
OPT
+0h
01C0 4020h
1
Parameter set 1
SRC
+4h
01C0 4040h
2
Parameter set 2
01C0 4060h
3
Parameter set 3
01C0 7FC0h
510
Parameter set 510
01C0 7FE0h
511
Parameter set 511
PaRAM set
BCNT
ACNT
+8h
+Ch
DST
DSTBIDX
SRCBIDX
+10h
BCNTRLD
LINK
+14h
DSTCIDX
SRCCIDX
+18h
Rsvd
CCNT
+1Ch
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Table 2. EDMA3 Channel Parameter Description
Offset Address
(bytes)
Acronym
Parameter
Description
0h
OPT
Channel Options
Transfer Configuration Options
4h
SRC
Channel Source Address
The byte address from which data is transferred.
ACNT
Count for 1st Dimension
Unsigned value specifying the number of contiguous
bytes within an array (first dimension of the transfer).
Valid values range from 1 to 65 535.
BCNT
Count for 2nd Dimension
Unsigned value specifying the number of arrays in a
frame, where an array is ACNT bytes. Valid values
range from 1 to 65 535.
DST
Channel Destination Address
The byte address to which data is transferred.
SRCBIDX
Source BCNT Index
Signed value specifying the byte address offset between
source arrays within a frame (2nd dimension). Valid
values range from –32 768 and 32 767.
DSTBIDX
Destination BCNT Index
Signed value specifying the byte address offset between
destination arrays within a frame (2nd dimension). Valid
values range from –32 768 and 32 767.
LINK
Link Address
The PaRAM address containing the PaRAM set to be
linked (copied from) when the current PaRAM set is
exhausted. A value of FFFFh specifies a null link.
BCNTRLD
BCNT Reload
The count value used to reload BCNT when BCNT
decrements to 0 (TR submitted for the last array in 2nd
dimension). Only relevant in A-synchronized transfers.
SRCCIDX
Source CCNT Index
Signed value specifying the byte address offset between
frames within a block (3rd dimension). Valid values
range from –32 768 and 32 767.
8h
(1)
Ch
10h (1)
14h (1)
18h (1)
A-synchronized transfers: The byte address offset from
the beginning of the last source array in a frame to the
beginning of the first source array in the next frame.
AB-synchronized transfers: The byte address offset from
the beginning of the first source array in a frame to the
beginning of the first source array in the next frame.
DSTCIDX
Destination CCNT index
Signed value specifying the byte address offset between
frames within a block (3rd dimension). Valid values
range from –32 768 and 32 767.
A-synchronized transfers: The byte address offset from
the beginning of the last destination array in a frame to
the beginning of the first destination array in the next
frame.
AB-synchronized transfers: The byte address offset from
the beginning of the first destination array in a frame to
the beginning of the first destination array in the next
frame.
1Ch
(1)
CCNT
Count for 3rd Dimension
Unsigned value specifying the number of frames in a
block, where a frame is BCNT arrays of ACNT bytes.
Valid values range from 1 to 65 535.
RSVD
Reserved
Reserved
It is recommended to access the parameter set entries as 32-bit words whenever possible.
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EDMA3 Channel Parameter Set Fields
2.3.2.1
Channel Options Parameter (OPT)
The 32-bit channel options parameter (OPT) specifies the transfer configuration options. The channel
options parameter (OPT) is described in Section 4.2.1.
2.3.2.2
Channel Source Address (SRC)
The 32-bit source address parameter specifies the starting byte address of the source. For SAM in
increment mode, there are no alignment restrictions imposed by EDMA3. For SAM in constant addressing
mode, you must program the source address to be aligned to a 256-bit aligned address (5 LSBs of
address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 2.11.2 for
additional details.
2.3.2.3
Channel Destination Address (DST)
The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM
in increment mode, there are no alignment restrictions imposed by EDMA3. For DAM in constant
addressing mode, you must program the destination address to be aligned to a 256-bit aligned address (5
LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 2.11.2
for additional details.
2.3.2.4
Count for 1st Dimension (ACNT)
ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned
value with valid values between 0 and 65 535. Therefore, the maximum number of bytes in an array is
65 535 bytes (64K – 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to
EDMA3TC. A transfer with ACNT equal to 0 is considered either a null or dummy transfer. A dummy or
null transfer generates a completion code depending on the settings of the completion bit fields in OPT.
See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions.
2.3.2.5
Count for 2nd Dimension (BCNT)
BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal
operation, valid values for BCNT are between 1 and 65 535. Therefore, the maximum number of arrays in
a frame is 65 535 (64K – 1 arrays). A transfer with BCNT equal to 0 is considered either a null or dummy
transfer. A dummy or null transfer generates a completion code depending on the settings of the
completion bit fields in OPT.
See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions.
2.3.2.6
Count for 3rd Dimension (CCNT)
CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are
between 1 and 65 535. Therefore, the maximum number of frames in a block is 65 535 (64K – 1 frames).
A transfer with CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer
generates a completion code depending on the settings of the completion bit fields in OPT.
A CCNT value of 0 is considered either a null or dummy transfer. See Section 2.3.5 and Section 2.5.3 for
details on dummy/null completion conditions.
2.3.2.7
BCNT Reload (BCNTRLD)
BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the
2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the
EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT reaches 0, the
EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value.
For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC
decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.
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2.3.2.8
Source B Index (SRCBIDX)
SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each
array in the 2nd dimension. Valid values for SRCBIDX are between –32 768 and 32 767. It provides a
byte address offset from the beginning of the source array to the beginning of the next source array. It
applies to both A-synchronized and AB-synchronized transfers. Some examples:
• SRCBIDX = 0000h (0): no address offset from the beginning of an array to the beginning of the next
array. All arrays are fixed to the same beginning address.
• SRCBIDX = 0003h (+3): the address offset from the beginning of an array to the beginning of the next
array in a frame is 3 bytes. For example, if the current array begins at address 1000h, the next array
begins at 1003h.
• SRCBIDX = FFFFh (–1): the address offset from the beginning of an array to the beginning of the next
array in a frame is –1 byte. For example, if the current array begins at address 5054h, the next array
begins at 5053h.
2.3.2.9
Destination B Index (DSTBIDX)
DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between
each array in the 2nd dimension. Valid values for DSTBIDX are between –32 768 and 32 767. It provides
a byte address offset from the beginning of the destination array to the beginning of the next destination
array within the current frame. It applies to both A-synchronized and AB-synchronized transfers. See
SRCBIDX for examples.
2.3.2.10
Source C Index (SRCCIDX)
SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the
3rd dimension. Valid values for SRCCIDX are between –32 768 and 32 767. It provides a byte address
offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first
source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that
when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame
(Figure 5), while the current array in an AB-synchronized transfer is the first array in the frame (Figure 6).
2.3.2.11
Destination C Index (DSTCIDX)
DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the
3rd dimension. Valid values are between –32 768 and 32 767. It provides a byte address offset from the
beginning of the current array (pointed to by DST address) to the beginning of the first destination array
TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when
DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame
(Figure 5), while the current array in a AB-synchronized transfer is the first array in the frame (Figure 6).
2.3.2.12
Link Address (LINK)
The EDMA3CC provides a mechanism, called linking, to reload the current PaRAM set upon its natural
termination (that is, after the count fields are decremented to 0) with a new PaRAM set. The 16-bit
parameter LINK specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads
the next PaRAM set during linking.
You must program the link address to point to a valid aligned 32-byte PaRAM set. The 5 LSBs of the LINK
field should be cleared to 0.
The EDMA3CC ignores the upper 2 bits of the LINK entry, allowing the programmer the flexibility of
programming the link address as either an absolute/literal byte address or use the PaRAM-base-relative
offset address. Therefore, if you make use of the literal address with a range from 4000h to 7FFFh, it will
be treated as a PaRAM-base-relative value of 0000h to 3FFFh.
You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM
address that falls in the range of the available PaRAM addresses on the device.
A LINK value of FFFFh is referred to as a NULL link that should cause the EDMA3CC to perform an
internal write of 0 to all entries of the current PaRAM set, except for the LINK field that is set to FFFFh.
Also, see Section 2.5 for details on terminating a transfer.
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Null PaRAM Set
A null PaRAM set is defined as a PaRAM set where all count fields (ACNT, BCNT, and CCNT) are
cleared to 0. If a PaRAM set associated with a channel is a NULL set, then when serviced by the
EDMA3CC, the bit corresponding to the channel is set in the associated event missed register (EMR,
EMRH, or QEMR). This bit remains set in the associated secondary event register (SER, SERH, or
QSER). This implies that any future events on the same channel are ignored by the EDMA3CC and you
are required to clear the bit in SER, SERH, or QSER for the channel. This is considered an error
condition, since events are not expected on a channel that is configured as a null transfer. See
Section 4.3.5.8 and Section 4.3.2.1 for more information on the SER and EMR registers, respectively.
2.3.4
Dummy PaRAM Set
A dummy PaRAM set is defined as a PaRAM set where at least one of the count fields (ACNT, BCNT, or
CCNT) is cleared to 0 and at least one of the count fields is nonzero.
If a PaRAM set associated with a channel is a dummy set, then when serviced by the EDMA3CC, it will
not set the bit corresponding to the channel (DMA/QDMA) in the event missed register (EMR, EMRH, or
QEMR) and the secondary event register (SER, SERH, or QSER) bit gets cleared similar to a normal
transfer. Future events on that channel are serviced. A dummy transfer is a legal transfer of 0 bytes. See
Section 4.3.5.8 and Section 4.3.2.1 for more information on the SER and EMR registers, respectively.
2.3.5
Dummy Versus Null Transfer Comparison
There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request.
A null transfer request is an error condition, but a dummy transfer is a legal transfer of 0 bytes. A null
transfer causes an error bit (En) in EMR to get set and the En bit in SER remains set, essentially
preventing any further transfers on that channel without clearing the associated error registers.
Table 3 summarizes the conditions and effects of null and dummy transfer requests.
Table 3. Dummy and Null Transfer Request
Feature
26
Null TR
Dummy TR
EMR/EMRH/QEMR is set
Yes
No
SER/SERH/QSER remains set
Yes
No
Link update (STATIC = 0 in OPT)
Yes
Yes
QER is set
Yes
Yes
IPR/IPRH CER/CERH is set using early completion
Yes
Yes
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2.3.6
Parameter Set Updates
When a TR is submitted for a given DMA/QDMA channel and its corresponding PaRAM set, the
EDMA3CC is responsible for updating the PaRAM set in anticipation of the next trigger event. For nonfinal
events, this includes address and count updates; for final events, this includes the link update.
The specific PaRAM set entries that are updated depend on the channel’s synchronization type
(A-synchronized or B-synchronized) and the current state of the PaRAM set. A B-update refers to the
decrementing of BCNT in the case of A-synchronized transfers after the submission of successive TRs. A
C-update refers to the decrementing of CCNT in the case of A-synchronized transfers after BCNT TRs for
ACNT byte transfers have submitted. For AB-synchronized transfers, a C-update refers to the
decrementing of CCNT after submission of every transfer request.
See Table 4 for details and conditions on the parameter updates. A link update occurs when the PaRAM
set is exhausted, as described in Section 2.3.7.
After the TR is read from the PaRAM (and is in process of being submitted to EDMA3TC), the following
fields are updated if needed:
• A-synchronized: BCNT, CCNT, SRC, DST
• AB-synchronized: CCNT, SRC, DST
The following fields are not updated (except for during linking, where all fields are overwritten by the link
PaRAM set):
• A-synchronized: ACNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK
• AB-synchronized: ACNT, BCNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK
Note that PaRAM updates only pertain to the information that is needed to properly submit the next
transfer request to the EDMA3TC. Updates that occur while data is moved within a transfer request are
tracked within the transfer controller, and is detailed in Section 2.11. For A-synchronized transfers, the
EDMA3CC always submits a TRP for ACNT bytes (BCNT = 1 and CCNT = 1). For AB-synchronized
transfers, the EDMA3CC always submits a TRP for ACNT bytes of BCNT arrays (CCNT = 1). The
EDMA3TC is responsible for updating source and destination addresses within the array based on ACNT
and FWID (in OPT). For AB-synchronized transfers, the EDMA3TC is also responsible to update source
and destination addresses between arrays based on SRCBIDX and DSTBIDX.
Table 4 shows the details of parameter updates that occur within EDMA3CC for A-synchronized and
AB-synchronized transfers.
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Table 4. Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set)
A-Synchronized Transfer
AB-Synchronized Transfer
B-Update
C-Update
Link Update
B-Update
C-Update
Link Update
BCNT > 1
BCNT == 1 &&
CCNT > 1
BCNT == 1 &&
CCNT == 1
N/A
CCNT > 1
CCNT == 1
SRC
+= SRCBIDX
+= SRCCIDX
= Link.SRC
in EDMA3TC
+= SRCCIDX
= Link.SRC
DST
+= DSTBIDX
+= DSTCIDX
= Link.DST
in EDMA3TC
+= DSTCIDX
= Link.DST
ACNT
None
None
= Link.ACNT
None
None
= Link.ACNT
BCNT
–= 1
= BCNTRLD
= Link.BCNT
in EDMA3TC
N/A
= Link.BCNT
CCNT
None
–= 1
= Link.CCNT
in EDMA3TC
–=1
= Link.CCNT
SRCBIDX
None
None
= Link.SRCBIDX
in EDMA3TC
None
= Link.SRCBIDX
DSTBIDX
None
None
= Link.DSTBIDX
None
None
= Link.DSTBIDX
SRCCIDX
None
None
= Link.SRCBIDX
in EDMA3TC
None
= Link.SRCBIDX
DSTCIDX
None
None
= Link.DSTBIDX
None
None
= Link.DSTBIDX
LINK
None
None
= Link.LINK
None
None
= Link.LINK
BCNTRLD
None
None
= Link.BCNTRLD
None
None
= Link.BCNTRLD
OPT (1)
None
None
= LINK.OPT
None
None
= LINK.OPT
Condition:
(1)
In all cases, no updates occur if OPT.STATIC == 1 for the current PaRAM set.
NOTE: The EDMA3CC includes no special hardware to detect when an indexed address update
calculation overflows/underflows. The address update will wrap across boundaries as
programmed by the user. You should ensure that no transfer is allowed to cross internal port
boundaries between peripherals. A single TR must target a single source/destination slave
endpoint.
2.3.7
Linking Transfers
The EDMA3CC provides a mechanism known as linking, which allows the entire PaRAM set to be
reloaded from a location within the PaRAM memory map (for both DMA and QDMA channels). Linking is
especially useful for maintaining ping-pong buffers, circular buffering, and repetitive/continuous transfers
all with no CPU intervention. Upon completion of a transfer, the current transfer parameters are reloaded
with the parameter set pointed to by the 16-bit link address field (of the current parameter set). Linking
only occurs when the STATIC bit in OPT is cleared to 0.
NOTE: A transfer (DMA or QDMA) should always be linked to another useful transfer. If it is
required to terminate a transfer, the transfer should be linked to a NULL set.
The link update occurs after the current PaRAM set event parameters have been exhausted. An event's
parameters are exhausted when the EDMA3 channel controller has submitted all the transfers associated
with the PaRAM set.
A link update occurs for null and dummy transfers depending on the state of the STATIC bit in OPT and
the LINK field. In both cases (null or dummy), if the value of LINK is FFFFh then a null PaRAM set (with all
0s and LINK set to FFFFh) is written to the current PaRAM set. Similarly, if LINK is set to a value other
than FFFFh then the appropriate PaRAM location pointed to by LINK is copied to the current PaRAM set.
Once the channel completion conditions are met for an event, the transfer parameters located at the link
address are loaded into the current DMA or QDMA channel’s associated parameter set. The EDMA3CC
reads the entire PaRAM set (8 words) from the PaRAM set specified by LINK and writes all 8 words to the
PaRAM set associated with the current channel. Figure 8 shows an example of a linked transfer.
Any PaRAM set in the PaRAM can be used as a link/reload parameter set. The PaRAM sets associated
with peripheral synchronization events (see Section 2.6) should only be used for linking if the
corresponding events are disabled.
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If a PaRAM set location is mapped to a QDMA channel (by QCHMAPn), then copying the link PaRAM set
onto the current QDMA channel PaRAM set is recognized as a trigger event and is latched in QER since a
write to the trigger word was performed. This feature can be used to create a linked list of transfers using
a single QDMA channel and multiple PaRAM sets.
Link-to-self transfers replicate the behavior of autoinitialization, which facilitates the use of circular
buffering and repetitive transfers. After an EDMA3 channel exhausts its current PaRAM set, it reloads all
the parameter set entries from another PaRAM set, which is initialized with values identical to the original
PaRAM set. Figure 9 shows an example of a linked-to-self transfer. In Figure 9, parameter set 127 has the
LINK field address pointing to the address of parameter set 127 (4FE0h), that is, linked-to-self.
NOTE: If the STATIC bit in OPT is set for a PaRAM set, then link updates are not performed.
2.3.7.1
Constant Addressing Mode Transfers/Alignment Issues
If either SAM or DAM is set to 1 (constant addressing mode), then the source or destination address must
be aligned to a 256-bit aligned address, respectively, and the corresponding BIDX should be an even
multiple of 32 bytes (256 bit). The EDMA3CC does not recognize errors here but the EDMA3TC asserts
an error, if this is not true. See Section 2.11.2.
NOTE: The EDMA3 should be configured for SAM/DAM = 1 (constant addressing mode) only if the
transfer source or destination (on-chip memory, off-chip memory controllers, slave
peripherals) support the constant addressing mode. See the device-specific peripheral user's
guide to verify if constant addressing mode is supported.
2.3.7.2
Element Size
The EDMA3 controller does not use the concept of element-size and element-indexing. Instead, all
transfers are defined in terms of all three dimensions: ACNT, BCNT, and CCNT. An element-indexed
transfer is logically achieved by programming ACNT to the size of the element and BCNT to the number of
elements that need to be transferred. For example, if you have 16-bit audio data and 256 audio samples
that needed to be transferred to a serial port, this can be done by programming the ACNT = 2 (2 bytes)
and BCNT = 256.
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Figure 8. Linked Transfer
(a) At initialization
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
BCNTRLD X Link X=4FE0h
DSTCIDX X
SRCCIDX X
CCNT X
Rsvd
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Parameter set 126
Parameter set 127
01C0 7FC0h
01C0 7FE0h
510
511
Parameter set 510
Parameter set 511
(b) After completion of PaRAM set 3
(link update)
OPT Y
SRC Y
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT Y
SRC Y
BCNT Y
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
Link
update
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
OPT Y
SRC Y
Parameter set 126
Parameter set 127
BCNT Y
01C0 7FC0h
01C0 7FE0h
510
511
Parameter set 510
Parameter set 511
ACNT Y
DST Y
DSTBIDX Y
SRCBIDX Y
BCNTRLD Y Link Y=FFFFh
DSTCIDX Y
SRCCIDX Y
Rsvd
CCNT Y
(c) After completion of PaRAM set 127
(link to null set)
30
Byte
address
Set
#
PaRAM
PaRAM set 3 (Null PaRAM set)
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
0h
0h
1CA0 4FE0h
01C0 4FC0h
127
126
01C0 7FC0h
01C0 7FE0h
510
511
0h
0h
0h
0h
0h
0h
0h
0h
Link=FFFFh
0h
0h
Parameter set 126
Parameter set 127
Parameter set 510
Parameter set 511
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Figure 9. Link-to-Self Transfer
(a) At initialization
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
BCNTRLD X
Link=4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Parameter set 126
Parameter set 127
01C0 7FC0h
01C0 7FE0h
510
511
Parameter set 510
Parameter set 511
(b) After completion of PaRAM set 3
(link update)
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link =4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 3
Byte
address
Set
#
PaRAM
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
BCNT X
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link =4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
PaRAM set 127
01C0 4FC0h
01C0 4FE0h
126
127
Link
update
OPT X
SRC X
Parameter set 126
Parameter set 127
BCNT X
01C0 7FC0h
01C0 7FE0h
510
511
Parameter set 510
Parameter set 511
(c) After completion of PaRAM set 127
(link to self)
ACNT X
DST X
DSTBIDX X
SRCBIDX X
BCNTRLD X
Link =4FE0h
DSTCIDX X
SRCCIDX X
Rsvd
CCNT X
Byte
address
Set
#
PaRAM
PaRAM set 3
01C0 4000h
01C0 4020h
01C0 4040h
01C0 4060h
0
1
2
3
Parameter set 0
Parameter set 1
Parameter set 2
Parameter set 3
OPT X
SRC X
01C0 4FC0h
1CA0 4FE0h
126
127
Parameter set 126
Parameter set 127
01C0 7FC0h
01C0 7FE0h
510
511
Parameter set 510
Parameter set 511
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BCNT X
ACNT X
DST X
SRCBIDX X
DSTBIDX X
Link=4FE0h
BCNTRLD X
SRCCIDX X
DSTCIDX X
CCNT X
Rsvd
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Initiating a DMA Transfer
There are multiple ways to initiate a programmed data transfer using the EDMA3 channel controller.
Transfers on DMA channels are initiated by three sources:
• Event-triggered transfer request (this is the more typical usage of EDMA3): Allows for a peripheral,
system, or externally-generated event to trigger a transfer request.
• Manually-triggered transfer request: The CPU manually triggers a transfer by writing a 1 to the
corresponding bit in the event set register (ESR/ESRH).
• Chain-triggered transfer request: A transfer is triggered on the completion of another transfer or
subtransfer.
Transfers on QDMA channels are initiated by two sources:
• Autotriggered transfer request: A transfer is triggered when the programmed trigger word is written
to.
• Link-triggered transfer requests: When linking occurs, the transfer is triggered when the trigger word
is written to.
2.4.1
DMA Channel
2.4.1.1
Event-Triggered Transfer Request
When an event is asserted from a peripheral or device pins, it gets latched in the corresponding bit of the
event register (ER.En = 1). See Table 5 for peripheral event to DMA event mapping. If the corresponding
event in the event enable register (EER) is enabled (EER.En = 1), then the EDMA3CC prioritizes and
queues the event in the appropriate event queue. When the event reaches the head of the queue, it is
evaluated for submission as a transfer request to the transfer controller.
If the PaRAM set is valid (not a NULL set), then a transfer request packet (TRP) is submitted to the
EDMA3TC and the En bit in ER is cleared. At this point, a new event can be safely received by the
EDMA3CC.
If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request
(TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding
channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to
a null TR being serviced. Good programming practices should include cleaning the event missed error
before retriggering the DMA channel.
When an event is received, the corresponding event bit in the event register is set (ER.En = 1), regardless
of the state of EER.En. If the event is disabled when an external event is received (ER.En = 1 and
EER.En = 0), the ER.En bit remains set. If the event is subsequently enabled (EER.En = 1), then the
pending event is processed by the EDMA3CC and the TR is processed/submitted, after which the ER.En
bit is cleared.
If an event is being processed (prioritized or is in the event queue) and another sync event is received for
the same channel prior to the original being cleared (ER.En != 0), then the second event is registered as a
missed event in the corresponding bit of the event missed register (EMR.En = 1).
Table 5. EDMA3 Channel Synchronization Events
32
EDMA3 Channel
Event Name
Event Description
0-3
-
Unused
4
AXEVTE0
McASP0 transmit event
5
AXEVTO0
McASP0 transmit event
6
AXEVT0
McASP0 transmit event
7
AREVTE0
McASP0 receive event
8
AREVTO0
McASP0 receive event
9
AREVT0
McASP0 receive event
10
AXEVTE1
McASP1 transmit event
11
AXEVTO1
McASP1 transmit event
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Table 5. EDMA3 Channel Synchronization Events (continued)
EDMA3 Channel
Event Name
Event Description
12
AXEVT1
McASP1 transmit event
13-15
-
Unused
16
SPIXEVT
SPI transmit event
17
SPIREVT
SPI receive event
18
URXEVT0
UART 0 receive event
19
UTXEVT0
UART 0 transmit event
20
URXEVT1
UART 1 receive event
21
UTXEVT1
UART 1 transmit event
22
URXEVT2
UART 2 receive event
23
UTXEVT2
UART 2 transmit event
24-27
-
Unused
28
ICREVT
I2C receive event
29
ICXEVT
I2C transmit event
30-31
-
Unused
32
GPINT0
GPIO 0 interrupt event
33
GPINT1
GPIO 1 interrupt event
34
GPINT2
GPIO 2 interrupt event
35
GPINT3
GPIO 3 interrupt event
36
GPINT4
GPIO 4 interrupt event
37
GPINT5
GPIO 5 interrupt event
38
GPINT6
GPIO 6 interrupt event
39
GPINT7
GPIO 7 interrupt event
40
GPBNKINT0
GPIO bank 0 interrupt event
41
GPBNKINT1
GPIO bank 1 interrupt event
42
GPBNKINT2
GPIO bank 2 interrupt event
43
CP_ECDCMP1
HDVICP1 ECDCMP event
44
CP_MC1
HDVICP1 MC event
45
CP_BS1
HDVICP1 BS event
46
CP_CALC1
HDVICP1 CALC event
47
CP_LPF1
HDVICP1 LPF event
48
TEVTL0
Timer 0 interrupt event
49
TEVTH0
Timer 0 interrupt event
50
TEVTL1
Timer 1 interrupt event
51
TEVTH1
Timer 1 interrupt event
52
PWM0
PWM 0 event
53
PWM1
PWM 1 event
54-56
-
Unused
57
CP_ME0
HDVICP0 ME event
58
CP_IPE0
HDVICP0 IPE event
59
CP_ECDCMP0
HDVICP0 ECDCMP event
60
CP_MC0
HDVICP0 MC event
61
CP_BS0
HDVICP0 BS event
62
CP_CALC0
HDVICP0 CALC event
63
CP_LPF0
HDVICP0 LPF event
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Manually-Triggered Transfer Request
A DMA transfer is initiated by a write to the event set register (ESR) by the CPU (or any EDMA
programmer). Writing a 1 to an event bit in the ESR results in the event being prioritized/queued in the
appropriate event queue, regardless of the state of the EER.En bit. When the event reaches the head of
the queue, it is evaluated for submission as a transfer request to the transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request
(TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding
channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to
a null TR being serviced. Good programming practices should include clearing the event missed error
before retriggering the DMA channel.
If an event is being processed (prioritized or is in the event queue) and the same channel is manually set
by a write to the corresponding channel bit of the event set register (ESR.En = 1) prior to the original
being cleared (ESR.En = 0), then the second event is registered as a missed event in the corresponding
bit of the event missed register (EMR.En = 1).
2.4.1.3
Chain-Triggered Transfer Request
Chaining is a mechanism by which the completion of one transfer automatically sets the event for another
channel. When a chained completion code is detected, the value of which is dictated by the transfer
completion code (TCC[5:0] in OPT of the PaRAM set associated with the channel), it results in the
corresponding bit in the chained event register (CER) to be set (CER.E[TCC] = 1).
Once a bit is set in CER, the EDMA3CC prioritizes and queues the event in the appropriate event queue.
When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request
(TR) is submitted and the corresponding En bit in CER is cleared and simultaneously the corresponding
channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to
a null TR being serviced. In this case, the error condition must be cleared by you before the DMA channel
can be retriggered. Good programming practices might include clearing the event missed error before
retriggering the DMA channel.
If a chaining event is being processed (prioritized or queued) and another chained event is received for
the same channel prior to the original being cleared (CER.En != 0), then the second chained event is
registered as a missed event in the corresponding channel bit of the event missed register (EMR.En = 1).
NOTE: Chained event registers, event registers, and event set registers operate independently. An
event (En) can be triggered by any of the trigger sources (event-triggered,
manually-triggered, or chain-triggered).
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2.4.2
QDMA Channels
2.4.2.1
Autotriggered and Link-Triggered Transfer Request
QDMA-based transfer requests are issued when a QDMA event gets latched in the QDMA event register
(QER.En = 1). A bit corresponding to a QDMA channel is set in the QDMA event register (QER) when the
following occurs:
• A CPU (or any EDMA3 programmer) write occurs to a PaRAM address that is defined as a QDMA
channel trigger word (programmed in the QDMA channel mapping register (QCHMAPn)) for the
particular QDMA channel and the QDMA channel is enabled via the QDMA event enable register
(QEER.En = 1).
• EDMA3CC performs a link update on a PaRAM set address that is configured as a QDMA channel
(matches QCHMAPn settings) and the corresponding channel is enabled via the QDMA event enable
register (QEER.En = 1).
Once a bit is set in QER, the EDMA3CC prioritizes and queues the event in the appropriate event queue.
When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the
transfer controller.
As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null
set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again.
If a bit is already set in QER (QER.En = 1) and a second QDMA event for the same QDMA channel
occurs prior to the original being cleared, the second QDMA event gets captured in the QDMA event miss
register (QEMR.En = 1).
2.4.3
Comparison Between DMA and QDMA Channels
The primary difference between DMA and QDMA channels is the event/channel synchronization. QDMA
events are either autotriggered or link triggered. Autotriggering allows QDMA channels to be triggered by
CPU(s) with a minimum number of linear writes to PaRAM. Link triggering allows a linked list of transfers
to be executed, using a single QDMA PaRAM set and multiple link PaRAM sets.
A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the
QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM
set that has been mapped to a QDMA channel (link triggered). Note that for CPU triggered (manually
triggered) DMA channels, in addition to writing to the PaRAM set, it is required to write to the event set
register (ESR) to kick-off the transfer.
QDMA channels are typically for cases where a single event will accomplish a complete transfer since the
CPU (or EDMA3 programmer) must reprogram some portion of the QDMA PaRAM set in order to retrigger
the channel. In other words, QDMA transfers are programmed with BCNT = CCNT = 1 for A-synchronized
transfers, and CCNT = 1 for AB-synchronized transfers.
Additionally, since linking is also supported (if STATIC = 0 in OPT) for QDMA transfers, it allows you to
initiate a linked list of QDMAs, so when EDMA3CC copies over a link PaRAM set (including the write to
the trigger word), the current PaRAM set mapped to the QDMA channel will automatically be recognized
as a valid QDMA event and initiate another set of transfers as specified by the linked set.
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Completion of a DMA Transfer
The TCC is used to generate an interrupt to the CPU and/or chain trigger another channel. Details on the
variations of this feature are described later.
See Section 2.9 for details on interrupts and Section 2.8 for details on chaining.
A parameter set for a given channel is complete when the required number of transfer requests is
submitted (based on receiving the number of synchronization events). The expected number of TRs for a
non-null/non-dummy transfer is shown in Table 6 for both synchronization types along with state of the
PaRAM set prior to the final TR being submitted. When the counts (BCNT and/or CCNT) are this value,
the next TR results in a:
• Final chaining or interrupt codes to be sent by the transfer controllers (instead of intermediate).
• Link updates (linking to either null or another valid link set).
Table 6. Expected Number of Transfers for Non-Null Transfer
Sync Mode
Counts at time 0
Total # Transfers
Counts prior to final TR
A-synchronized
ACNT
BCNT
CCNT
(BCNT × CCNT ) TRs of ACNT bytes each
BCNT == 1 && CCNT == 1
AB-synchronized
ACNT
BCNT
CCNT
CCNT TRs for ACNT × BCNT bytes each
CCNT == 1
You must program the PaRAM OPT field with a specific transfer completion code (TCC) along with the
other OPT fields (TCCHEN, TCINTEN, ITCCHEN, and ITCINTEN bits) to indicate whether the completion
code is to be used for generating a chained event or/and for generating an interrupt upon completion of a
transfer.
The specific TCC value (6-bit binary value) programmed dictates which of the 64-bits in the chain event
register (CER[TCC]) and/or interrupt pending register (IPR[TCC]) is set.
You can also selectively program whether the transfer controller sends back completion codes on
completion of the final transfer request (TR) of a parameter set (TCCHEN or TCINTEN), for all but the
final transfer request (TR) of a parameter set (ITCCHEN or ITCINTEN), or for all TRs of a parameter set
(both). See Section 2.8 for details on chaining (intermediate/final chaining) and Section 2.9 for details on
intermediate/final interrupt completion.
A completion detection interface exists between the EDMA3 channel controller and transfer controller(s).
This interface sends back information from the transfer controller to the channel controller to indicate that
a specific transfer is completed. Completion of a transfer is used for generating chained events and/or
generating interrupts to the CPU(s).
All DMA/QDMA PaRAM sets must also specify a link address value. For repetitive transfers such as
ping-pong buffers, the link address value should point to another predefined PaRAM set. Alternatively, a
nonrepetitive transfer should set the link address value to the null link value. The null link value is defined
as FFFFh. See Section 2.3.7 for more details.
NOTE: Any incoming events that are mapped to a null PaRAM set results in an error condition. The
error condition should be cleared before the corresponding channel is used again. See
Section 2.3.5.
There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal
completion, early completion, and dummy/null completion. This applies to both chained events and
completion interrupt generation.
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2.5.1
Normal Completion
In normal completion mode (TCCMODE = 0 in OPT), the transfer or sub-transfer is considered to be
complete when the EDMA3 channel controller receives the completion codes from the EDMA3 transfer
controller. In this mode, the completion code to the channel controller is posted by the transfer controller
after it receives a signal from the destination peripheral. Normal completion is typically used to generate
an interrupt to inform the CPU that a set of data is ready for processing.
2.5.2
Early Completion
In early completion mode (TCCMODE = 1 in OPT), the transfer is considered to be complete when the
EDMA3 channel controller submits the transfer request (TR) to the EDMA3 transfer controller. In this
mode, the channel controller generates the completion code internally. Early completion is typically useful
for chaining, as it allows subsequent transfers to be chained-triggered while the previous transfer is still in
progress within the transfer controller, maximizing the overall throughput of the set of the transfers.
2.5.3
Dummy or Null Completion
This is a variation of early completion. Dummy or null completion is associated with a dummy set
(Section 2.3.4) or null set (Section 2.3.3). In both cases, the EDMA3 channel controller does not submit
the associated transfer request to the EDMA3 transfer controller(s). However, if the set (dummy/null) has
the OPT field programmed to return completion code (intermediate/final interrupt/chaining completion),
then it will set the appropriate bits in the interrupt pending registers (IPR/IPRH) or chained event register
(CER/CERH). The internal early completion path is used by the channel controller to return the completion
codes internally (that is, EDMA3CC generates the completion code).
2.6
Event, Channel, and PaRAM Mapping
Several of the 64 DMA channels are tied to a specific hardware event, thus allowing transfers to be
triggered by events from device peripherals or external hardware. A DMA channel typically requests a
data transfer when it receives its event (apart from manually-triggered, chain-triggered, and other
transfers). The amount of data transferred per synchronization event depends on the channel’s
configuration (ACNT, BCNT, CCNT, etc.) and the synchronization type (A-synchronized or
AB-synchronized).
The association of an event to a channel is fixed. Each of the DMA channels has one specific event
associated with it. Table 5 provides the synchronization events associated with each of the programmable
DMA channels.
If in an application, a channel does not make use of the associated synchronization event or does not
have an associated synchronization event (unused), that channel can be used for manually-triggered or
chained-triggered transfers, for linking/reloading, or as a QDMA channel.
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DMA Channel to PaRAM Mapping
The mapping between the DMA channel numbers and the PaRAM sets is programmable (see Table 1).
The DMA channel mapping registers (DCHMAPn) in the EDMA3CC provide programmability that allows
the DMA channels to be mapped to any of the PaRAM sets in the PaRAM memory map. Figure 10
illustrates the use of DCHMAPn. There is one DCHMAPn per channel. See Table 1 for more information.
Figure 10. DMA Channel to PaRAM Mapping
31
DCHMAPn
14 13
0000 0000 0000 00
5 4
0
PAENTRY
00 0000 011
0 0000
Byte
address
Set
#
01C0 4000h
0
Parameter set 0
OPT
01C0 4020h
1
Parameter set 1
SRC
01C0 4040h
2
Parameter set 2
01C0 4060h
3
Parameter set 3
PaRAM
PaRAM set
BCNT
ACNT
DST
DSTBIDX
38
01C0 7FC0h
510
Parameter set 510
01C0 7FE0h
511
Parameter set 511
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SRCBIDX
BCNTRLD
LINK
DSTCIDX
SRCCIDX
Rsvd
CCNT
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2.6.2
QDMA Channel to PaRAM Mapping
The mapping between the QDMA channels and the PaRAM sets is programmable .The QDMA channel
mapping register (QCHMAP) in the EDMA3CC provides programmability for the QDMA channels to be
mapped to any of the PaRAM sets in the PaRAM memory map. Figure 11 illustrates the use of QCHMAP.
Additionally, QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel. A
trigger word is one of the 8 words in the PaRAM set. For a QDMA transfer to occur, a valid TR
synchronization event for EDMA3CC is a write to the trigger word in the PaRAM set pointed to by
QCHMAP for a particular QDMA channel. By default, QDMA channels are mapped to PaRAM set 0. Care
must be taken to appropriately remap PaRAM set 0 before it is used.
Figure 11. QDMA Channel to PaRAM Mapping
31
QCHMAPn
14 13
0000 0000 0000 00
5 4
PAENTRY
00 0000 011
2 1 0
TR WORD
1 11
Byte
address
Set
#
PaRAM
PaRAM set
01C0 4000h
0
Parameter set 0
OPT
01C0 4020h
1
Parameter set 1
01C0 4040h
2
Parameter set 2
01C0 4060h
3
Parameter set 3
01C0 7FC0h
510
Parameter set 510
01C0 7FE0h
511
Parameter set 511
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00
Byte
address
offset
+0h
+4h
SRC
ACNT
+8h
DSTBIDX
SRCBIDX
+10h
BCNTRLD
LINK
+14h
DSTCIDX
SRCCIDX
Rsvd
CCNT
+18h
+1Ch
BCNT
+Ch
DST
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EDMA3 Channel Controller Regions
The EDMA3 channel controller divides its address space into eight regions. Individual channel resources
are assigned to a specific region, where each region is typically assigned to a specific EDMA programmer.
Application software is required to use the appropriate region.
2.7.1
Region Overview
The EDMA3 channel controller memory-mapped registers are divided in three main categories:
1. Global registers
2. Global region channel registers
3. Shadow region channel registers
The global registers are located at a single/fixed location in the EDMA3CC memory map. These registers
control EDMA3 resource mapping and provide debug visibility and error tracking information. See the
device-specific data manual for the EDMA3CC memory map.
The channel registers (including DMA, QDMA, and interrupt registers) are accessible via the global
channel region address range, or in the shadow n channel region address range(s). For example, the
event enable register (EER) is visible at the global address of 01C0 1020h or region addresses of
01C0 2020h for region 0, 01C0 2220h for region 1 and 01C0 2C20h for region 7.
The underlying control register bits that are accessible via the shadow region address space (except for
IEVALn) are controlled by the DMA region access enable registers (DRAEm) and QDMA region access
enable registers (QRAEn) . Table 7 lists the registers in the shadow region memory map. (Refer to
EDMA3CC memory map figure for the complete global and shadow region memory maps.) Figure 12
illustrates the conceptual view of the regions.
Table 7. Shadow Region Registers
DRAEm
DRAEHm
QRAEn
ER
ERH
QER
ECR
ECRH
QEER
ESR
ESRH
QEECR
CER
CERH
QEESR
EER
EERH
QSER
EECR
EECRH
QSECR
EESR
EESRH
SER
SERH
SECR
SECRH
IER
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
Register not affected by DRAE\DRAEH
IEVAL
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Figure 12. Shadow Region Registers
Shadow region 0
Access address
01C0 2000h
01C0 2094h
except IEVAL
Physical register
ER, ERH
ER, ERH
ECR, ECRH
ESR, ESRH
CER, CERH
EER, EERH
EECR, EECRH
EESR, EESRH
SER, SERH
SECR, SECRH
DRAE0/
DRAE0H
QSECR
IEVAL
QRAE0
Shadow region 0
registers
01C0 1000h
IER, IERH
IECR,
IESR,
IPR,
ICR,
IEVAL,
QER
QEER
QEECR
QEESR
QSER
QSECR
ER, ERH
Access address
01C0 3000h
01C0 3094h
DRAE7/
DRAE7H
QSECR
IEVAL
QRAE7
01C0 1094h
Shadow region 7
registers
2.7.2
Channel Controller Regions
An EDMA3 transfer can be programmed/configured by the DSP, ARM, or the two HD image coprocessor
(HDVICP0 and HDVICP1). In order to provide autonomous operation for each master, the EDMA3
channel controller allows partitioning of the resources between different masters via the shadow regions.
There are eight EDMA3 shadow regions (and its associated memory maps). The shadow regions
associated to each of the EDMA3 programmers (DSP, ARM, HDVICP0, and HDVICP1) are given in
Table 8. The shadow regions that are reserved should not be used.
There are two regions for each of the HDVICP0 and HDVICP1. This provides additional flexibility for the
algorithm running on the HDVICP to differentiate one type of traffic from the other. For instance, HDVICP0
algorithm may choose to use Region 4 completion interrupt for all SDRAM traffic and use Region 5
completion interrupt for all non-SDRAM traffic.
Associated with each shadow region are a set of registers defining which channels and interrupt
completion codes belong to that region. These registers are user-programmed per region, in order to
assign ownership of the DMA/QDMA channels to a region.
• DRAEm and DRAEHm: One register pair exists for each of the shadow regions. The number of bits in
each register pair matches the number of DMA channels (64 DMA channels). These registers need to
be programmed to assign ownership of DMA channels and interrupt (or TCC codes) to the respective
region. Accesses to DMA and interrupt registers via the shadow region address view are filtered
through the DRAE/DRAEH pair. A value of 1 in the corresponding DRAE(H) bit implies that the
corresponding DMA/interrupt channel is accessible; a value of 0 in the corresponding DRAE(H) bit
forces writes to be discarded and returns a value of 0 for reads.
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QRAEn: One register exists for every region. The number of bits in each register matches the number
of QDMA channels (8 QDMA channels).These registers need to be programmed to assign ownership
of QDMA channels to the respective region. To enable a channel in a shadow region, using shadow
region 0 QEER, writing into QEESR will not have the desired effect if the respective bit in QRAE is not
set.
Table 8 provides the shadow region and region access registers assignment to each of the EDMA3
masters.
Table 8. EDMA3 Shadow Regions
EDMA3 Master
Shadow Region
Region Access Registers
ARM
0
DRAE0, DRAEH0, and QRAE0
DSP
1
DRAE1, DRAEH1, and QRAE1
Reserved
2
Reserved
Reserved
3
Reserved
Image coprocessor 0 (HDVICP0)
4
DRAE4, DRAEH4, and QRAE4
Image coprocessor 0 (HDVICP0)
5
DRAE5, DRAEH5, and QRAE5
Image coprocessor 1 (HDVICP1)
6
DRAE6, DRAEH6, and QRAE6
Image coprocessor 1 (HDVICP1)
7
DRAE7, DRAEH7, and QRAE7
A value of 1 in a given bit position in the DMA/QDMA region access enable register corresponding to a
particular shadow region implies that the corresponding channel (and the corresponding bit position) can
be manipulated via the EDMA3 master associated to that shadow region. For example, DRAEH0 =
0000 0001h implies that DMA channel 32 (which is accessed at bit position 32) is manipulated by ARM
(shadow region 0).
It is typical for an application that a unique assignment is given for a QDMA/DMA channel (and therefore a
given bit position) to a given region, that is, if channel 0 is accessed/owned by ARM, then it would not be
accessible by DSP. However, if DRAE0 = 0000 0001h and DRAE1 = 0000 0001h, then channel 0 (and the
corresponding bit position) is accessible by both shadow region 0 and 1.
NOTE: An EDMA programmer is limited to only using the appropriate region via software
convention. There is no hardware/active memory protection that restricts the ARM from
accessing a shadow region intended for use by the DSP.
Example 1. Resource Pool Division Across Two Regions
This example illustrates a judicious resource pool division across two regions, assuming the ARM needs to be
allocated 16 DMA channels (0-15) and 4 QDMA channels (0, 3, 5, and 7) and 32 TCC codes (0-15 and
48-63). The DSP needs to be allocated 16 DMA channels (16-32) and the remaining 4 QDMA channels (1, 2,
4, and 6) and TCC codes (16-47). DRAE should be equal to the OR of the bits required for the DMA channels
and the TCC codes:
Region 0: DRAEH, DRAE = 0xFFFF0000, 0x0000FFFF QRAE = 0x000000A9 Region 1: DRAEH, DRAE = 0x0000FFFF,
0xFFFF0000 QRAE = 0x00000056
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2.8
Chaining EDMA3 Channels
The channel chaining capability for the EDMA3 allows the completion of an EDMA3 channel transfer to
trigger another EDMA3 channel transfer. The purpose is to allow you the ability to chain several events
through one event occurrence.
Chaining is different from linking (Section 2.3.7). The EDMA3 link feature reloads the current channel
parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any
channel parameter set; it provides a synchronization event to the chained channel (see Section 2.4.1.3 for
chain-triggered transfer requests).
Chaining is achieved at either final transfer completion or intermediate transfer completion, or both, of the
current channel. Consider a channel m (DMA/QDMA) required to chain to channel n. Channel number n
(0-63) needs to be programmed into the TCC field of channel m channel options parameter (OPT) set.
• If final transfer completion chaining (TCCHEN = 1 and ITCCHEN = 0 in channel m OPT) is enabled,
the chain-triggered event occurs after the last transfer request of channel m is submitted (early
completion) or completed (normal completion).
• If intermediate transfer completion chaining (ITCCHEN = 1 and ITCCHEN = 0 in channel m OPT) is
enabled, the chain-triggered event occurs after every intermediate transfer request of channel m is
submitted (early completion) or completed (normal completion).
• If both final and intermediate transfer completion chaining (TCCHEN = 1 and ITCCHEN = 1 in channel
m OPT) are enabled, the chain-trigger event occurs after every transfer request of channel m is
submitted (early completion) or completed (normal completion).
Table 9 shows the number of chain event triggers occurring in different synchronized scenarios. Consider
channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 9. Chain Event Triggers
(Number of chained event triggers on channel 30)
Options
A-Synchronized
AB-Synchronized
TCCHEN = 1, ITCCHEN = 0
1 (Last TR)
1 (Last TR)
TCCHEN = 0, ITCCHEN = 1
19 (All but the last TR)
4 (All but the last TR)
TCCHEN = 1, ITCCHEN = 1
20 (All TRs)
5 (All TRs)
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EDMA3 Interrupts
The EDMA3 interrupts are divided into 2 categories:
• Transfer completion interrupts
• Error interrupts
The transfer completion interrupts are listed in Table 10 and the error interrupts are listed in Table 11.
For more information on the DSP interrupt controller (INTC) and the ARM interrupt controller (AINTC), see
the TMS320DM646x DMSoC DSP Subsystem Reference Guide (SPRUEP8) and the TMS320DM646x
DMSoC ARM Subsystem Reference Guide (SPRUEP9).
Table 10. EDMA3 Transfer Completion Interrupts
Interrupt Number
Name
Description
ARM
DSP
CCINT0
HDVICP0 HDVICP1
AINTC
EDMA3CC Transfer Completion
Interrupt Shadow Region 0
x
-
-
INTC
-
16
-
CCINT1
EDMA3CC Transfer Completion
Interrupt Shadow Region 1
-
x
-
-
-
84
CCINT4
EDMA3CC Transfer Completion
Interrupt Shadow Region 4
-
-
x
-
-
-
CCINT5
EDMA3CC Transfer Completion
Interrupt Shadow Region 5
-
-
x
-
-
-
CCINT6
EDMA3CC Transfer Completion
Interrupt Shadow Region 6
-
-
-
x
-
-
CCINT7
EDMA3CC Transfer Completion
Interrupt Shadow Region 7
-
-
-
x
-
-
Table 11. EDMA3 Error Interrupts
Interrupt Number
2.9.1
Name
Description
ARM
DSP
CCERRINT
TCERRINT0
HDVICP0 HDVICP1
AINTC
INTC
EDMA3CC Error Interrupt
x
x
-
EDMA3TC0 Error Interrupt
x
x
-
-
17
85
-
18
TCERRINT1
EDMA3TC1 Error Interrupt
x
x
86
-
-
19
87
TCERRINT2
EDMA3TC2 Error Interrupt
x
TCERRINT3
EDMA3TC3 Error Interrupt
x
x
-
-
20
88
x
-
-
21
89
Transfer Completion Interrupts
The EDMA3CC is responsible for generating transfer completion interrupts to the CPU(s) (and other
EDMA3 masters). The EDMA3 generates a single completion interrupt per shadow region on behalf of all
DMA/QDMA channels. Various control registers and bit fields facilitate EDMA3 interrupt generation.
The transfer completion code (TCC) value is directly mapped to the bits of the interrupt pending register
(IPR/IPRH), as shown in Table 12. For example, if TCC = 10 0001b, IPRH[1] is set after transfer
completion, and results in interrupt generation to the CPU(s) if the completion interrupt is enabled for the
CPU. See Section 2.9.1.1 for details on enabling EDMA3 transfer completion interrupts.
When a completion code is returned (as a result of early or normal completion), the corresponding bit in
IPR/IPRH is set. For the completion code to be returned, the PaRAM set associated with the transfer must
enable the transfer completion interrupt (final/intermediate) in the channel options parameter (OPT).
The transfer completion code (TCC) can be programmed to any value for a DMA/QDMA channel. There
does not need to be a direct relation between the channel number and the transfer completion code value.
This allows multiple channels having the same transfer completion code value to cause a CPU to execute
the same interrupt service routine (ISR) for different channels.
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If the channel is used in the context of a shadow region and you intend for the shadow region interrupt to
be asserted, then ensure that the bit corresponding to the TCC code is enabled in IER/IERH and in the
corresponding shadow regions's DMA region access registers (DRAE/DRAEH).
Table 12. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
(1)
TCC Bits in OPT
(TCINTEN/ITCINTEN = 1)
IPR Bit Set
TCC Bits in OPT
(TCINTEN/ITCINTEN = 1)
00 0000b
IPR0
10 0000b
IPR32/IPRH0
00 0001b
IPR1
10 0001b
IPR33/IPRH1
00 0010b
IPR2
10 0010b
IPR34/IPRH2
00 0011b
IPR3
10 0011b
IPR35/IPRH3
00 0100b
IPR4
10 0100b
IPR36/IPRH4
…
…
…
…
…
…
…
…
01 1110b
IPR30
11 1110b
IPR62/IPRH30
01 1111b
IPR31
11 1111b
IPR63/IPRH31
IPRH Bit Set
(1)
Bit fields IPR[32-63] correspond to bits 0 to 31 in IPRH, respectively.
You can enable Interrupt generation at either final transfer completion or intermediate transfer completion,
or both. Consider channel m as an example.
• If the final transfer interrupt (TCINTEN = 1 and ITCINTEN = 0 in OPT) is enabled, the interrupt occurs
after the last transfer request of channel m is either submitted or completed (depending on early or
normal completion).
• If the intermediate transfer interrupt (TCINTEN = 0 and ITCINTEN = 1 in OPT) is enabled, the interrupt
occurs after every intermediate transfer request of channel m is either submitted or completed
(depending on early or normal completion).
• If both final and intermediate transfer completion interrupts (TCINTEN = 1 and ITCINTEN = 1 in OPT)
are enabled, the interrupt occurs after every transfer request of channel m is submitted or completed
(depending on early or normal completion).
Table 13 shows the number of interrupts occurring in different synchronized scenarios. Consider channel
31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30.
Table 13. Number of Interrupts
2.9.1.1
Options
A-Synchronized
AB-Synchronized
TCINTEN = 1, ITCINTEN = 0
1 (Last TR)
1 (Last TR)
TCINTEN = 0, ITCINTEN = 1
19 (All but the last TR)
4 (All but the last TR)
TCINTEN = 1, ITCINTEN = 1
20 (All TRs)
5 (All TRs)
Enabling Transfer Completion Interrupts
For the EDMA3 channel controller to assert a transfer completion to the external world, the interrupts have
to be enabled in the EDMA3CC. This is in addition to setting up the TCINTEN and ITCINTEN bits in OPT
of the associated PaRAM set.
The EDMA3 channel controller has interrupt enable registers (IER/IERH) and each bit location in
IER/IERH serves as a primary enable for the corresponding interrupt pending registers (IPR/IPRH).
All the interrupt registers (IER, IESR, IECR, and IPR) are either manipulated from the global DMA channel
region or by way of the DMA channel shadow regions. The shadow regions provide a view to the same
set of physical registers that are in the global region.
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The EDMA3 channel controller has a hierarchical completion interrupt scheme that makes use of a single
set of interrupt pending registers (IPR/IPRH) and single set of interrupt enable registers (IER/IERH). A
second level of interrupt masking is provided by the programmable DMA region access enable registers
(DRAE/DRAEH) for asserting the completion interrupts. See Figure 13.
Figure 13. Interrupt Diagram
Interrupt pending
register (IPR)
X
1
0
Interrupt
enable
register
(IER)
X
DMA region
access enable 0
(DRAE0)
1
0
X
1
DMA region
access enable 1
(DRAE1)
0
IEVAL0.EVAL
X
1
DMA region
access enable 7
(DRAE7)
0
IEVAL1.EVAL
Eval
pulse
Eval
pulse
CCINT0 to ARM
CCINT1 to DSP
X
1
0
IEVAL7.EVAL
Eval
pulse
CCINT7 to HDVICP1
In order for the EDMA3CC to generate the transfer completion interrupts associated with each shadow
region, the following conditions need to be true:
• CCINT0 (to ARM): (IPR.E0 & IER.E0 & DRAE0.E0) | (IPR.E1 & IER.E1 & DRAE0.E1)
…| (IPRH.E63 & IERH.E63 & DRAHE0.E63)
• CCINT1 (to DSP): (IPR.E0 & IER.E0 & DRAE1.E0) | (IPR.E1 & IER.E1 & DRAE1.E1)
…| (IPRH.E63 & IERH.E63 & DRAHE1.E63)
• CCINT4 (to HDVICP0): (IPR.E0 & IER.E0 & DRAE4.E0) | (IPR.E1 & IER.E1 & DRAE4.E1)
…| (IPRH.E63 & IERH.E63 & DRAHE4.E63)
• CCINT5 (to HDVICP0): (IPR.E0 & IER.E0 & DRAE5.E0) | (IPR.E1 & IER.E1 & DRAE5.E1)
…| (IPRH.E63 & IERH.E63 & DRAHE5.E63)
• CCINT6 (to HDVICP1): (IPR.E0 & IER.E0 & DRAE6.E0) | (IPR.E1 & IER.E1 & DRAE6.E1)
…| (IPRH.E63 & IERH.E63 & DRAHE6.E63)
• CCINT7 (to HDVICP1): (IPR.E0 & IER.E0 & DRAE7.E0) | (IPR.E1 & IER.E1 & DRAE7.E1)
…| (IPRH.E63 & IERH.E63 & DRAHE7.E63)
|
|
|
|
|
|
Enabling the transfer completion region interrupts by DRAE/DRAEH makes provision for unique
assignment of channels and interrupts in a multiple-CPU environment. This allows independent operations
for all CPU(s) (or EDMA3 masters) in using the EDMA3 resources.
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NOTE: If your application does not require a multiple-CPU environment, if all the DMA channels
and interrupts are being controlled and owned by a single EDMA3 master, then you can
program the transfer and set up the interrupts by manipulating the global DMA channel
region registers (instead of DMA channel shadow region registers) and setting up the correct
DRAE/DRAEH to enable to region transfer completion interrupt for a particular EDMA3
master. However, for a multiple-CPU environment, where multiple channels are owned by
different CPUs (via DRAE/DRAEH and QRAE/QRAEH configuration), it is best to use the
shadow region memory map, so that your software monitors the set/clears for its own
assigned resources. For example, the DSP interrupt service routine (ISR) will only operate
on channel completion reported for channels assigned to the DSP (monitor for
IPR1.En/IPRH1.En, where n is the event/channels bits that are made accessible to shadow
region 1, which is associated with the DSP), similarly the ARM ISR will only operate on
resources assigned to shadow region 0.
Since there is no relation between the TCC value and the DMA/QDMA channel, it is
possible, for example, that DMA channel 0 has the OPT.TCC = 63 in its associated PaRAM
set. This would mean that if a transfer completion interrupt is enabled (OPT.TCINTEN or
OPT.ITCINTEN is set to 1), then based on the TCC value, IPRH.E63 is set to 1 on
completion. In order for proper channel operations and interrupt generation, using the
shadow region map, DRAE/DRAEH associated with the shadow region must be programmed
to have read/write access to both bit 0 (corresponding to channel 0 ) and bit 63
(corresponding to IPRH bit that is set on completion).
2.9.1.2
Clearing Transfer Completion Interrupts
Transfer completion interrupts that are latched to the interrupt pending registers (IPR/IPRH) are cleared by
writing a 1 to the corresponding bit in the interrupt pending clear register (ICR/ICRH). For example, a write
of 1 to ICR.E0 clears a pending interrupt in IPR.E0.
If an incoming transfer completion code (TCC) gets latched to a bit in IPR/IPRH, then additional bits that
get set due to a subsequent transfer completion will not result in asserting the EDMA3CC completion
interrupt. In order for the completion interrupt to be pulsed, the required transition is from a state where no
enabled interrupts are set to a state where at least one enabled interrupt is set.
2.9.2
EDMA3 Interrupt Servicing
On completion of a transfer (early or normal completion), the EDMA3 channel controller sets the
appropriate bit in the interrupt pending registers (IPR/IPRH) as specified by the transfer completion codes.
If the completion interrupts are appropriately enabled, then the CPU enters the interrupt service routine
(ISR) when the completion interrupt is asserted. Since there is a single completion interrupt for all
DMA/QDMA channels.
After servicing the interrupt, the ISR should clear the corresponding bit in IPR/IPRH; therefore, enabling
recognition of future interrupts. Only when all IPR/IPRH bits are cleared, the EDMA3CC will assert
additional completion interrupts.
It is possible that when one interrupt is serviced; many other transfer completions result in additional bits
being set in IPR/IPRH, thereby resulting in additional interrupts. It is likely that each of these bits in
IPR/IPRH would need different types of service; therefore, the ISR must check all pending interrupts and
continue until all the posted interrupts are appropriately serviced.
Following are examples (pseudo code) for a CPU interrupt service routine for an EDMA3CC completion
interrupt.
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The ISR routine in Example 2 is more exhaustive and incurs a higher latency.
Example 2. Interrupt Servicing
The pseudo code:
1. Read the interrupt pending register (IPR/IPRH).
2. Perform the operations needed.
3. Write to the interrupt pending clear register (ICR/ICRH) to clear the corresponding IPR/IPRH bit.
4. Read IPR/IPRH again:
(a) If IPR/IPRH is not equal to 0, repeat from step 2 (implies occurrence of new event between step 2 to
step 4).
(b) If IPR/IPRH is equal to 0, this should assure you that all enabled interrupts are inactive.
NOTE: It is possible that during step 4, an event occurs while the IPR/IPRH bits are read to be 0 and
the application is still in the interrupt service routine. If this happens, a new interrupt is recorded
in the device interrupt controller and a new interrupt is generated as soon as the application exits
the interrupt service routine.
Example 3 is less rigorous, with less burden on the software in polling for set interrupt bits, but can
occasionally cause a race condition, as mentioned above.
Example 3. Interrupt Servicing
If it is desired to leave any enabled and pending (possibly lower priority) interrupts, it is required to force the
interrupt logic to reassert the interrupt pulse by setting the EVAL bit in the interrupt evaluation register
(IEVAL).
The pseudo code:
1. Enter ISR.
2. Read IPR/IPRH.
3. For the condition set in IPR/IPRH that you desire to service:
(a) Service interrupt as required by application.
(b) Clear bit for serviced conditions (others may still be set, and other transfers may have resulted in
returning the TCC to EDMA3CC after step 2).
4. Read IPR/IPRH prior to exiting ISR:
(a) If IPR/IPRH is equal to 0, then exit ISR.
(b) If IPR/IPRH is not equal to 0, then set IEVAL so that upon exit of ISR, a new interrupt is triggered if any
enabled interrupts are still pending.
The EVAL bit must not be set when IPR and IPRH are read to be 0, to avoid generation of extra interrupt
pulses.
NOTE:
48
Since the DMA region access registers (DRAE/DRAEH) are required to enable the transfer
completion region interrupts, it is assumed that there will be a unique and nonoverlapping (in
most cases) assignment of the channels and interrupts among the different shadow regions.
This allows the interrupt registers (IER, IESR, IECR, IPR, and ICR) in the different shadow
regions to functionally operate in an independent manner and nonoverlapping. The above
examples for the interrupt service routine is based on this assumption.
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2.9.3
Interrupt Evaluation Operations
The EDMA3CC has interrupt evaluate registers (IEVAL) in each shadow region. These registers are the
only registers in the DMA channel shadow region memory map that are not affected by the settings for the
DMA region access enable registers (DRAE/DRAEH). A write of 1 to the EVAL bit in these registers
associated with a particular shadow region results in pulsing the associated region interrupt, if any
enabled interrupt (via IER/IERH) is still pending (IPR/IPRH). This register can be used in order to assure
that the interrupts are not missed by the CPU (or the EDMA3 master associated with the shadow region) if
the software architecture chooses not to use all interrupts. See Example 3 for the use of IEVAL in the
EDMA3 interrupt service routine (ISR).
Similarly an error evaluation register (EEVAL) exists in the global region. A write of 1 to the EVAL bit in
EEVAL causes the pulsing of the error interrupt if any pending errors are in EMR/EMRH, QEMR, or
CCERR. See Section 2.9.4 for additional details on error interrupts.
NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the
IEVAL operated upon is from that particular shadow region memory map.
2.9.4
Error Interrupts
The EDMA3CC error registers provide the capability to differentiate error conditions (event missed,
threshold exceed, etc.). Additionally, if the error bits are set in these registers, it results in asserting the
EDMA3CC error interrupt. If EDMA3CC error interrupt is enabled in the device interrupt controller(s), then
it allows the CPU(s) to handle the error conditions.
The EDMA3CC has a single error interrupt (CCERRINT) that gets asserted for all EDMA3CC error
conditions. There are four conditions that cause the error interrupt to be pulsed:
• DMA missed events: for all 64 DMA channels. These get latched in the event missed registers
(EMR/EMRH).
• QDMA missed events: for all QDMA channels. These get latched in the QDMA event missed register
(QEMR).
• Threshold exceed: for all event queues. These get latched in EDMA3CC error register (CCERR).
• TCC error: for outstanding transfer requests expected to return completion code (TCCHEN or
TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the
EDMA3CC error register (CCERR).
Figure 14 illustrates the EDMA3CC error interrupt generation operation.
If any of the bits are set in the error registers due to any error condition, the CCERRINT always is
asserted, as there are no enables for masking these error events. Similar to transfer completion interrupts
(CCINT), the error interrupt also is pulsed only when the error interrupt condition transitions from a state
where no errors are set to a state where at least one error bit is set. If additional error events are latched
prior to the original error bits being cleared, the EDMA3CC does not generate additional interrupt pulses.
To reduce the burden on the software, similar to the interrupt evaluate register (IEVAL), there is an error
evaluate register (EEVAL) that allows reevaluation of pending set error events/bits. This can be used so
that the CPU(s) does not miss any error events.
NOTE: It is a good practice to have the error interrupt enabled in the device interrupt controller and
associate an interrupt service routine with it to address the various error conditions
appropriately. This puts less burden on software (polling for error status) and additionally
provides a good debug mechanism for unexpected error conditions.
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Figure 14. Error Interrupt Operation
EMR/EMRH
63
QEMR
1
0
7
CCERR
1
0
16
1
0
EEVAL.EVAL
Eval/
pulse
CCERRINT
2.10 Event Queue(s)
Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the
event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC.
Each queue is 16 entries deep, that is, a maximum of 16 queued events per event queue. If there are
more than 16 events, then the events that cannot find a place in the event queue remain set in the
associated event register.
There are four event queues (Queue0, Queue1, Queue2 and Queue3) for DM646x devices. Events in
Queue_n result in submission of its associated transfer requests (TRs) to TC_n. Thus, transfer requests
associated with events in Queue0 are submitted to TC0 and so on.
An event that wins prioritization against other DMA and/or QDMA pending events is placed at the end of
the appropriate event queue. Each event queue is serviced in a FIFO (first in–first out) order. Once the
event reaches the head of its queue and the corresponding transfer controller is ready to receive another
TR, the event is dequeued and the PaRAM set corresponding to the dequeued event is processed and
submitted as a transfer request packet (TRP) to the associated EDMA3 transfer controller.
Queue0 has highest priority followed by Queue1, Queue2 and Queue3, if Queue0 and Queue1 both have
at least one event entry and if both TC0 and TC1 can accept transfer requests, then the event in Queue0
is dequeued first and its associated PaRAM set is processed and submitted as a transfer request (TR) to
TC0.
See Section 2.10.4 for system-level performance considerations. All the event entries in all the event
queues are software readable (not writeable) by accessing the event entry registers (Q0E0,
Q0E1,…Q1E15, etc.). Each event entry register characterizes the queued event in terms of the type of
event (manual, event, chained or autotriggered) and the event number. See Section 4.3.4.1 for a
description of the bit fields in the queue event entry registers.
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2.10.1
DMA/QDMA Channel to Event Queue Mapping
Each of the 64 DMA channels and 8 QDMA channels are independently programmed to map to a specific
queue using the DMA queue number register (DMAQNUM) and the QDMA queue number register
(QDMANUM). The mapping of DMA/QDMA channels is critical to achieving the desired performance level
for the EDMA and most importantly in meeting real-time deadlines. See Section 2.10.4.
NOTE: If an event is ready to be queued and both the event queue and the EDMA3 transfer
controller associated to the event queue are empty, then the event bypasses the event
queue, and goes to the PaRAM processing logic and eventually to the transfer request
submission logic for submission to the EDMA3TC. In this case, the event is not logged in the
event queue status registers.
2.10.2
Queue RAM Debug Visibility
Each event queue has 16 entries. These 16 entries are managed in a circular FIFO manner. All event
queue entries for all event queues are software readable by the event queue entry register (QxEx).
Additionally, for each queue there is a queue status register (QSTATn).
These registers provide user visibility and may be helpful while debugging real-time issues (typically
post-mortem), involving multiple events and event sources. The event queue entry register (QxEx)
uniquely identifies the specific event type (event-triggered, manually-triggered, chain-triggered, and QDMA
events) along with the event number (for DMA/QDMA channels) that are in the queue or have been
de-queued (passed through the queue). QSTATn includes fields for the start pointer (STRTPTR) that
provides the offset to the head entry of an event. It also includes a NUMVAL field that provides the total
number of valid entries residing in the event queue at a given instance of time. The STRTPTR field may
be used to index appropriately into the 16 event entries. The NUMVAL number of entries starting from
STRTPTR are indicative of events still queued in the respective queue. The remaining entries may be
read to determine which events have already been de-queued and submitted to the associated transfer
controller.
2.10.3
Queue Resource Tracking
The EDMA3CC event queue includes watermarking/threshold logic that allows you to keep track of
maximum usage of all event queues. This is useful for debugging real-time deadline violations that may
result from head-of-line blocking on a given EDMA3 event queue.
You can program the maximum number of events that can queue up in an event queue by programming
the threshold value (between 0 to 15) in the queue watermark threshold A register (QWMTHRA). The
maximum queue usage is recorded actively in the watermark (WM) field of the queue status register
(QSTATn) that keeps getting updated based on a comparison of number of valid entries, which is also
visible in the NUMVAL bit in QSTATn and the maximum number of entries (WM bit in QSTATn).
If the queue usage is exceeded, this status is visible in the EDMA3CC registers: the QTHRXCDn bit in the
channel controller error register (CCERR) and the THRXCD bit in QSTATn, where n stands for the event
queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt.
2.10.4
Performance Considerations
The main switched central resource (SCR) (see the data manual) arbitrates bus requests from all the
masters (ARM, DSP, master peripherals, VPIF, SPIO, etc., and the EDMA3 transfer controllers (TC0,
TC1, TC2, and TC3)) to the shared slave resources (peripherals and memories). The priorities of transfer
requests (read and write commands) from the EDMA3 transfer controllers with respect to other masters
within the system crossbar are programmed using the Master priority registers (MSTPRI0, MSTPRI1 and
MSTPRI2). MSTPRI0, MSTPRI1, and MSTPRI2 indirectly controls the priority of the event queues ( since
Queue0 transfer requests are submitted to TC0 , Queue1 to TC1, Queue2 to TC2, and Queue3 to TC3).
Therefore, the priority of unloading queues has a secondary affect compared to the priority of the transfers
as they are executed by the EDMA3TC (dictated by the priority set using MSTPRI0, MSTPRI1 and
MSTPRI2).
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2.11 EDMA3 Transfer Controller (EDMA3TC)
The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller
(EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR)
to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR; thus, the EDMA3TC
is a slave to the EDMA3CC.
2.11.1
Architecture Details
2.11.1.1
Command Fragmentation
The TC read and write controllers in conjunction with the source and destination register sets are
responsible for issuing optimally-sized reads and writes to the slave endpoints. An optimally-sized
command is defined by the transfer controller default burst size (DBS), which is defined in Section 2.11.4.
The EDMA3TC attempts to issue the largest possible command size as limited by the DBS value or the
ACNT/BCNT value of the TR. EDMA3TC obeys the following rules:
• The read/write controllers always issue commands less than or equal to the DBS value.
• The first command of a 1D transfer is always issued so that subsequent commands align to the DBS
value.
Example 4 shows the command fragmentation for a DBS of 32 bytes. In summary, if the ACNT value is
larger than the DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the
source/destination addresses. Each BCNT number of arrays are then serviced in succession.
Example 4. Command Fragmentation (DBS = 32)
The pseudo code:
1. ACNT = 8, BCNT = 8, SRCBIDX = 8, DSTBIDX = 10, SRCADDR = 64, DSTADDR = 191
Read Controller: This is optimized from a 2D-transfer to a 1D-transfer such that the read side is equivalent
to ACNT = 64, BCNT = 1.
Cmd0 = 32 byte, Cmd0 = 32 byte
Write Controller: Since DSTBIDX != ACNT, it is not optimized.
Cmd0 = 8 byte, Cmd1 = 8 byte, Cmd2 = 8 byte, Cmd3 = 8 byte, Cmd4 = 8 byte, Cmd5 = 8 byte, Cmd6 = 8
byte, Cmd7 = 8 byte.
2. ACNT=64, BCNT = 1, SRCADDR = 31, DSTADDR = 513
Read Controller: Read address is not aligned.
Cmd0 = 1 byte, (now the SRCADDR is aligned to 32 for the next command)
Cmd1 = 32 bytes
Cmd2 = 31 bytes
Write Controller: The write address is also not aligned.
Cmd0 = 31 bytes, (now the DSTADDR is aligned to 32 for the next command)
Cmd1 = 32 bytes
Cmd2 = 1 byte
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For BCNT arrays of ACNT bytes (that is, a 2D transfer), if the ACNT value is less than or equal to the
DBS value, then the TR may be optimized into a 1D-transfer in order to maximize efficiency, as per the
rules in Table 14. The optimization takes place if the EDMA3TC recognizes that the 2D-transfer is
organized as a single dimension (SAM/DAM = INCR), BIDX = ACNT, the ACNT value is a power of 2, and
the BCNT value is less than or equal to 1023.
Table 14 lists conditions in which the optimizations are performed.
Table 14. Read/Write Command Optimization Rules
2.11.1.2
ACNT ≤ DBS
ACNT is power of 2
BIDX = ACNT
BCNT ≤ 1023
SAM/DAM =
Increment
Yes
Yes
Yes
Yes
Yes
No
x
x
x
x
Not Optimized
x
No
x
x
x
Not Optimized
x
x
No
x
x
Not Optimized
x
x
x
No
x
Not Optimized
x
x
x
x
No
Not Optimized
Description
Optimized
TR Pipelining
TR pipelining refers to the ability of the source active set to get ahead of the destination active set.
Essentially, the reads for a given TR may already be in progress while the writes of a previous TR may
not have completed.
The number of outstanding TRs is limited by the number of destination FIFO register entries. A single TR
must be assured to target a single source peripheral endpoint.
TR pipelining is useful for maintaining throughput on back-to-back small TRs. It eliminates the read
overhead because reads start in the background of a previous TR writes.
2.11.1.3
Performance Tuning
By default, reads are as issued as fast as possible. In some cases, the reads issued by the EDMA3TC
could fill the available command buffering for a slave, delaying other (potentially higher priority) masters
from successfully submitting commands to that slave. The rate at which read commands are issued by the
EDMA3TC is controlled by the RDRATE register. The RDRATE register defines the number of cycles that
the EDMA3TC read controller waits before issuing subsequent commands for a given TR, thus minimizing
the chance of the EDMA3TC consuming all available slave resources. The RDRATE value should be set
to a relatively small value if the transfer controller is targeted for high priority transfers and to a higher
value if the transfer controller is targeted for low priority transfers.
In contrast, the Write Interface does not have any performance turning knobs because writes always have
an interval between commands as write commands are submitted along with the associated write data.
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Error Generation
Errors are generated if enabled under three conditions:
• EDMA3TC detection of an error signaled by the source or destination address.
• Attempt to read or write to an invalid address in the configuration memory map.
• Detection of a constant addressing mode TR violating the constant addressing mode transfer rules (the
source/destination addresses and source/destination indexes must be aligned to 32 bytes).
Either or all error types may be disabled. If an error bit is set and enabled, the error interrupt for the
concerned transfer controller is pulsed.
2.11.3
Debug Features
The DMA program register set, DMA source active register set, and the destination FIFO register set are
used to derive a brief history of TRs serviced through the transfer controller.
Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing
activity within different parts of the transfer controller:
• The SRCACTV bit indicates whether the source active set is active.
• The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given
instance.
• The PROGBUSY bit indicates whether a valid TR is present in the DMA program set.
If the TRs are in progression, caution must be used and you must realize that there is a chance that the
values read from the EDMA3TC status registers will be inconsistent since the EDMA3TC may change the
values of these registers due to ongoing activities.
It is recommended that you ensure no additional submission of TRs to the EDMA3TC in order to facilitate
ease of debug.
2.11.3.1
Destination FIFO Register Pointer
The destination FIFO register pointer is implemented as a circular buffer with the start pointer being
DFSTRTPTR and a buffer depth of usually 2 or 4. The EDMA3TC maintains two important status details in
TCSTAT that may be used during advanced debugging, if necessary. The DFSTRTPTR is a start pointer,
that is, the index to the head of the destination FIFO register. The DSTACTV is a counter for the number
of valid (occupied) entries. These registers may be used to get a brief history of transfers.
Examples of some register field values and their interpretation:
• DFSTRTPTR = 0 and DSTACTV = 0 implies that no TRs are stored in the destination FIFO register.
• DFSTRTPTR = 1 and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 1 and the second pending TR is read from the destination
FIFO register entry 2.
• DFSTRTPTR = 3h and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 3 and the second pending TR is read from the destination
FIFO register entry 0.
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2.11.4
EDMA3TC Configuration
The EDMA transfer controller default burst size configuration register (EDMATCCFG) in the System
module configures the default burst size for the EDMA transfer controllers (EDMA3TC0, EDMA3TC1,
EDMA3TC2, and EDMA3TC3). Refer to the device-specific data manual for more information on this
register. Table 15 provides the configuration of the individual EDMA3 transfer controllers present on the
device.
Table 15. EDMA3 Transfer Controller Configurations
Name
TC0
TC1
TC2
TC3
FIFOSIZE
256 bytes
256 bytes
256 bytes
256 bytes
BUSWIDTH
8 bytes
8 bytes
8 bytes
8 bytes
DSTREGDEPTH
4 entries
4 entries
4 entries
4 entries
Default DBS
32 bytes
32 bytes
32 bytes
32 bytes
2.12 Event Dataflow
This section summarizes the data flow of a single event, from the time the event is latched to the channel
controller to the time the transfer completion code is returned. The following steps list the sequence of
EDMA3CC activity:
1. Event is asserted from an external source (peripheral or external interrupt). This also is similar for a
manually-triggered, chained-triggered, or QDMA-triggered event. The event is latched into the
ER.En/ERH.En (or CER.En/CERH.En, ESR.En /ESRH.En, QER.En) bit.
2. Once an event is prioritized and queued into the appropriate event queue, the SER.En\SERH.En (or
QSER.En) bit is set to inform the event prioritization/processing logic to disregard this event since it is
already in the queue. Alternatively, if the transfer controller and the event queue are empty, then the
event bypasses the queue.
3. The EDMA3CC processing and the submission logic evaluates the appropriate PaRAM set and
determines whether it is a non-null and non-dummy transfer request (TR).
4. The EDMA3CC clears the ER.En/ERH.En (or CER.En/CERH.En, ESR.En/ESRH.En, QER.En) bit and
the SER.En/SERH.En bit as soon as it determines the TR is non-null. In the case of a null set, the
SER.En/SERH.En bit remains set. It submits the non-null/non-dummy TR to the associated transfer
controller. If the TR was programmed for early completion, the EDMA3CC immediately sets the
interrupt pending register (IPR.I[TCC]/IPRH.I[TCC]-32).
5. If the TR was programmed for normal completion, the EDMA3CC sets the interrupt pending register
(IPR.I[TCC]/IPRH.I[TCC]) when the EDMA3TC informs the EDMA3CC about completion of the transfer
(returns transfer completion codes).
6. The EDMA3CC programs the associated EDMA3TCn's Program Register Set with the TR.
7. The TR is then passed to the Source Active set and the Dst FIFO Register Set, if both the register sets
are available.
8. The Read Controller processes the TR by issuing read commands to the source slave endpoint. The
Read Data lands in the Data FIFO of the EDMA3TCn.
9. As soon as sufficient data is available, the Write Controller begins processing the TR by issuing write
commands to the destination slave endpoint.
10. This continues until the TR completes and the EDMA3TCn then signals completion status to the
EDMA3CC.
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2.13 EDMA3 Prioritization
The EDMA3 controller has many implementation rules to deal with concurrent events/channels, transfers,
etc. The following subsections detail various arbitration details whenever there might be occurrence of
concurrent activity. Figure 15 shows the different places EDMA3 priorities come into play.
2.13.1
Channel Priority
The DMA event registers (ER and ERH) capture up to 64 events; likewise, the QDMA event register
(QER) captures QDMA events for all QDMA channels; therefore, it is possible for events to occur
simultaneously on the DMA/QDMA event inputs. For events arriving simultaneously, the event associated
with the lowest channel number is prioritized for submission to the event queues (for DMA events,
channel 0 has the highest priority and channel 63 has the lowest priority; similarly, for QDMA events,
channel 0 has the highest priority and channel 7 has the lowest priority). This mechanism only sorts
simultaneous events for submission to the event queues.
If a DMA and QDMA event occurs simultaneously, the DMA event always has prioritization against the
QDMA event for submission to the event queues.
Figure 15. EDMA3 Prioritization
Manual
trigger
Channel priority
Event
enable
register
(EER/EERH)
64
15
Queue 1
15
0
0
Parameter
set 510
Queue 3
TC0
TC3
8
8:1 priority encoder
Parameter
set 511
PaRAM
Queue bypass
Completion
interface
From EDMA3TC0
Completion
detection
Error
detection
Completion
interrupt
From EDMA3TC1
From EDMA3TC2
From EDMA3TC3
CCERRINT
56
Parameter
set 1
0
QDMA trigger
EDMA3 channel
controller
Parameter
set 0
0
Queue 0
15
Chained
event
register
(CER/CERH)
QDMA
event
register
(QER)
Event
queues
Queue 2
Event
64
set
register
(ESR/ESRH)
64
Chain
trigger
15
SCR
Event
register
(ER/ERH)
Dequeue priority
Channel mapping
Event
trigger
System priority
Trigger source priority
E1 E0
64:1 priority encoder
E63
Transfer request submission
From peripherals/external events
CCINT[7:0]
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2.13.2
Trigger Source Priority
If a DMA channel is associated with more than one trigger source (event trigger, manual trigger, and chain
trigger), and if multiple events are set simultaneously for the same channel (ER.En = 1, ESR.En = 1,
CER.En = 1), then the EDMA3CC always services these events in the following priority order: event
trigger (via ER) is higher priority than chain trigger (via CER) and chain trigger is higher priority than
manual trigger (via ESR).
This implies that if for channel 0, both ER.E0 = 1 and CER.E0 = 1 at the same time, then the ER.E0 event
is always queued before the CER.E0 event.
2.13.3
Dequeue Priority
The priority of the associated transfer request (TR) is further mitigated by which event queue is being used
for event submission (dictated by DMAQNUM and QDMAQNUM). For submission of a TR to the transfer
controller, events need to be dequeued from the event queues. Q0 has higher dequeue priority then Q1.
In other words, if there are multiple events in both Q0 and Q1, then the transfer requests associated with
events in Q0 will get submitted to TC0 prior to any transfer requests associated with events in Q1 getting
submitted to TC1.
2.13.4
System (Transfer Controller) Priority
Each transfer controller has a programmed system priority (programmed via the MSTPRI0, MSTPRI1 and
MSTPRI2 registers) that is implemented when multiple masters in the system are vying for the same
endpoint. The priority of the associated transfer request (TR) is further mitigated by system priority setting
of the transfer controller. This priority is necessary when several masters are submitting requests to the
main switched central resource (SCR), which in turn has to arbitrate the requests from these masters.
NOTE: The default priority for both TC0, TC1, TC2 and TC3 is the same, 2. This priority is higher
priority relative to other masters (like EMAC, ARM, GEM, PCI etc.). This default priority is
lower compared to masters like SPIO and VPIF. It is recommended that this priority be
changed only after careful system level considerations, such as real-time deadlines for all
masters including the priority of the transfer controllers with respect to each other.
(MSTPRI0, MSTPRI1 and MSTPRI2 registers control the priority of all the masters in the
system relative to one another. Refer the device-specific data manual for details).
2.14 EDMA3 Operating Frequency (Clock Control)
The EDMA3 channel controller and transfer controller are clocked from PLL0. The EDMA3 system runs at
DSP frequency divided by 2 (on DM646x devices, this is 297 MHZ).
2.15 Reset Considerations
A hardware reset resets the EDMA3 (EDMA3CC and EDMA3TC) and the EDMA3 configuration registers.
The PaRAM memory contents are undefined after device reset and you should not rely on parameters to
be reset to a known state. The PaRAM set must be initialized to a desired value before it is used.
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2.16 Power Management
The EDMA3 (EDMA3CC and EDMA3TC) can be placed in reduced-power modes to conserve power
during periods of low activity. The power management of the peripheral is controlled by the device Power
and Sleep Controller (PSC). The PSC acts as a master controller for power management for all
peripherals on the device. For detailed information on power management procedures using the PSC, see
the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9).
The EDMA3 controller can be idled on receiving a clock stop request from the PSC. The requests to
EDMA3CC and EDMA3TC are separate. In general, you should verify that there are no pending activities
in the EDMA3 controller before issuing a clock stop request via PSC.
The EDMA3CC checks for the following conditions:
• No pending DMA/QDMA events
• No outstanding events in the event queues
• Transfer request processing logic is not active
• No completion requests outstanding (early or normal completion)
• No configuration bus requests in progress
The first four conditions are software readable by the channel controller status register (CCSTAT) in the
EDMA3CC.
Similarly, from the EDMA3TC perspective, you should check that there are no outstanding TRs that are
getting processed and essentially the read/write controller is not busy processing a TR. The activity of
EDMA3TC logic is read in TCSTAT for each EDMA3TC..
It is generally recommended to first disable the EDMA3CC and then the EDMA3TC(s) to put the EDMA3
controller in reduced-power modes.
Additionally, when EDMA3 is involved in servicing a peripheral and it is required to power-down both the
peripheral and the EDMA, the recommended sequence is to first disable the peripheral, then disable the
DMA channel associated with the peripheral (clearing the EER/EERH bit for the channel), then disable the
EDMA3CC, and finally disable the EDMA3TC(s).
2.17 Emulation Considerations
During debug when using the emulator, the CPU(s) may be halted on an execute packet boundary for
single-stepping, benchmarking, profiling, or other debug purposes. During an emulation halt, the EDMA3
channel controller and transfer controller operations continue. Events continue to be latched and
processed and transfer requests continue to be submitted and serviced.
Since EDMA3 is involved in servicing multiple master and slave peripherals, it is not feasible to have an
independent behavior of the EDMA3 for emulation halts. EDMA3 functionality would be coupled with the
peripherals it is servicing, which might have different behavior during emulation halts. For example, if a
ASP is halted during an emulation access (FREE = 0 and SOFT = 0 or 1 in ASP registers), the ASP stops
generating the ASP receive or transmit events (REVT or XEVT) to the EDMA. From the point of view of
the ASP, the EDMA3 is suspended, but other peripherals (for example, a timer) still assert events and will
be serviced by the EDMA.
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3
EDMA3 Transfer Examples
The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration.
The following sections provides a description and PaRAM configuration for some typical use case
scenarios.
3.1
Block Move Example
The most basic transfer performed by the EDMA3 is a block move. During device operation it is often
necessary to transfer a block of data from one location to another, usually between on-chip and off-chip
memory.
In this example, a section of data is to be copied from external memory to internal L2 SRAM. A data block
of 256 bytes residing at address 8000 0000h (external memory) needs to be transferred to internal
address 1180 0000h (L2), as shown in Figure 16. Figure 17 shows the parameters for this transfer.
The source address for the transfer is set to the start of the data block in external memory, and the
destination address is set to the start of the data block in L2. If the data block is less than 64K bytes, the
PaRAM configuration in Figure 17 holds true with the synchronization type set to A-synchronized and
indexes cleared to 0. If the amount of data is greater than 64K bytes, BCNT and the B-indexes need to be
set appropriately with the synchronization type set to AB-synchronized. The STATIC bit in OPT is set to
prevent linking.
This transfer example may also be set up using QDMA. For successive transfer submissions, of a similar
nature, the number of cycles used to submit the transfer are fewer depending on the number of changing
transfer parameters. You may program the QDMA trigger word to be the highest numbered offset in the
PaRAM set that undergoes change.
Figure 16. Block Move Example
8000 0000h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
...
...
...
... 244 245 246 247 248
1180 0000h
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
...
...
...
... 244 245 246 247 248
249 250 251 252 253 254 255 256
249 250 251 252 253 254 255 256
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Figure 17. Block Move Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
Parameter
0010 0008h
Channel Options Parameter (OPT)
8000 0000h
Channel Source Address (SRC)
0001h
0100h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0000h
Destination BCNT Index (DSTBIDX)
0000h
FFFFh
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
60
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
0000
0
000
0000
1
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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3.2
Subframe Extraction Example
The EDMA3 can efficiently extract a small frame of data from a larger frame of data. By performing a
2D-to-1D transfer, the EDMA3 retrieves a portion of data for the CPU to process. In this example, a
640 × 480-pixel frame of video data is stored in external memory, DDR2. Each pixel is represented by a
16-bit halfword. The CPU extracts a 16 × 12-pixel subframe of the image for processing. To facilitate more
efficient processing time by the CPU, the EDMA3 places the subframe in internal L2 SRAM. Figure 18
shows the transfer of a subframe from external memory to L2. Figure 19 shows the parameters for this
transfer.
The same PaRAM set options are used for QDMA channels, as well as DMA channels. The STATIC bit in
OPT is set to 1 to prevent linking. For successive transfers, only changed parameters need to be
programmed before triggering the channel.
Figure 18. Subframe Extraction Example
8000 0000h
0
1180 0000h
8000 0788h
0_1 0_2 0_3 0_4 0_5 0_6 0_7 0_8 0_9 0_A 0_B 0_C 0_D 0_E 0_F 0_10
1_1 1_2 1_3 1_4 1_5 1_6 1_7 1_8 1_9 1_A 1_B 1_C 1_D 1_E 1_F 1_10
2_1 2_2 2_3 2_4 2_5 2_6 2_7 2_8 2_9 2_A 2_B 2_C 2_D 2_E 2_F 2_10
3_1 3_2 3_3 3_4 3_5 3_6 3_7 3_8 3_9 3_A 3_B 3_C 3_D 3_E 3_F 3_10
4_1 4_2 4_3 4_4 4_5 4_6 4_7 4_8 4_9 4_A 4_B 4_C 4_D 4_E 4_F 4_10
5_1 5_2 5_3 5_4 5_5 5_6 5_7 5_8 5_9 5_A 5_B 5_C 5_D 5_E 5_F 5_10
6_1 6_2 6_3 6_4 6_5 6_6 6_7 6_8 6_9 6_A 6_B 6_C 6_D 6_E 6_F 6_10
7_1 7_2 7_3 7_4 7_5 7_6 7_7 7_8 7_9 7_A 7_B 7_C 7_D 7_E 7_F 7_10
8_1 8_2 8_3 8_4 8_5 8_6 8_7 8_8 8_9 8_A 8_B 8_C 8_D 8_E 8_F 8_10
9_1 9_2 9_3 9_4 9_5 9_6 9_7 9_8 9_9 9_A 9_B 9_C 9_D 9_E 9_F 9_10
A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_A A_B A_C A_D A_E A_F A_10
B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_A B_B B_C B_D B_E B_F B_10
8002 5580h
479
6
3
9
0
Figure 19. Subframe Extraction Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
Parameter
0010 000Ch
Channel Options Parameter (OPT)
8000 0788h
Channel Source Address (SRC)
000Ch
0020h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0020h
0500h
Destination BCNT Index (DSTBIDX)
0000h
FFFFh
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
8
7
4
18
17
16
3
2
1
0
0000
0
000
0000
1
1
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Data Sorting Example
Many applications require the use of multiple data arrays; it is often desirable to have the arrays arranged
such that the first elements of each array are adjacent, the second elements are adjacent, and so on.
Often this is not how the data is presented to the device. Either data is transferred via a peripheral with
the data arrays arriving one after the other or the arrays are located in memory with each array occupying
a portion of contiguous memory spaces. For these instances, the EDMA3 can reorganize the data into the
desired format. Figure 20 shows the data sorting.
In
•
•
•
•
•
•
•
order to determine the parameter entry values, the following need to be considered:
ACNT – Program this to be the size in bytes of an element.
BCNT – Program this to be the number of elements in a frame.
CCNT – Program this to be the number of frames.
SRCBIDX – Program this to be the size of the element or ACNT.
DSTBIDX = CCNT × ACNT
SRCCDX = ACNT × BCNT
DSTCIDX = ACNT
The synchronization type needs to be AB-synchronized and the STATIC bit is 0 to allow updates to the
parameter set. It is advised to use normal DMA channels for sorting.
It is not possible to sort this with a single trigger event. Instead, the channel can be programmed to be
chained to itself. After BCNT elements get sorted, intermediate chaining could be used to trigger the
channel again causing the transfer of the next BCNT elements and so on. Figure 21 shows the parameter
set programming for this transfer, assuming channel 0 and an element size of 4 bytes.
Figure 20. Data Sorting Example
8000 0000h
A_1
A_2
A_3
...
...
A_1022 A_1023 A_1024
A_1
B_1
C_1
D_1
B_1
B_2
B_3
...
...
B_1022 B_1023 B_1024
A_2
B_2
C_2
D_2
C_1
C_2
C_3
...
...
C_1022 C_1023 C_1024
A_3
B_3
C_3
D_3
D_1
D_2
D_3
...
...
D_1022 D_1023 D_1024
...
...
...
...
...
...
...
...
1180 0000h
A_1022 B_1022 C_1022 D_1022
A_1023 B_1023 C_1023 D_1023
A_1024 B_1024 C_1024 D_1024
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Figure 21. Data Sorting Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents
Parameter
0090 0004h
Channel Options Parameter (OPT)
8000 0000h
Channel Source Address (SRC)
0400h
0004h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0010h
0001h
Destination BCNT Index (DSTBIDX)
0000h
FFFFh
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0001h
1000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0004h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
23
22
21
20
0
30
000
28
0000
1
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
8
7
4
18
17
16
3
2
1
0000
0
000
0000
0
1
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Peripheral Servicing Example
The EDMA3 channel controller also services peripherals in the background of CPU operation, without
requiring any CPU intervention. Through proper initialization of the DMA channels, they can be configured
to continuously service on-chip and off-chip peripherals throughout the device operation. Each event
available to the EDMA3 has its own dedicated channel, and all channels operate simultaneously. The only
requirements are to use the proper channel for a particular transfer and to enable the channel event in the
event enable register (EER). When programming a DMA channel to service a peripheral, it is necessary to
know how data is to be presented to the DSP. Data is always provided with some kind of synchronization
event as either one element per event (nonbursting) or multiple elements per event (bursting).
3.4.1
Nonbursting Peripherals
Nonbursting peripherals include the on-chip audio serial port (ASP) and many external devices, such as
codecs. Regardless of the peripheral, the DMA channel configuration is the same.
The ASP transmit and receive data streams are treated independently by the EDMA3. The transmit and
receive data streams can have completely different counts, data sizes, and formats. Figure 22 shows
servicing incoming ASP data.
To transfer the incoming data stream to its proper location in L2 memory, the DMA channel must be set
up for a 1D-to-1D transfer with A-synchronization. Since an event (REVT) is generated for every word as it
arrives, it is necessary to have the EDMA3 issue the transfer request for each element individually.
Figure 23 shows the parameters for this transfer. The source address of the DMA channel is set to the
data receive register (DRR) address for ASP, and the destination address is set to the start of the data
block in L2. Since the address of DRR is fixed, the source B index is cleared to 0 (no modification) and the
destination B index is set to 01b (increment).
Based on the premise that serial data is typically a high priority, the DMA channel should be programmed
to be on queue 0.
Figure 22. Servicing Incoming ASP Data Example
:
3
:
2
:
1
1180 0000h
Incoming serial data
AREVT0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
...
...
...
...
244
245
246
247
248
250
251
252
253
254
255
256
01D0 1400h
RSR
RBUF
249
64
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Figure 23. Servicing Incoming ASP Data Example PaRAM
(a) EDMA Parameters
Parameter Contents
Parameter
0010 0000h
Channel Options Parameter (OPT)
01D0 1400h
Channel Source Address (SRC)
0100h
0001h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0001h
0000h
Destination BCNT Index (DSTBIDX)
0000h
FFFFh
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0004h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
8
7
4
18
17
16
3
2
1
0000
0
000
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Bursting Peripherals
Higher bandwidth applications require that multiple data elements be presented to the CPU for every
synchronization event. This frame of data can either be from multiple sources that are working
simultaneously or from a single high-throughput peripheral that streams data to/from the CPU.
In this example, a port is receiving a video frame from a camera and presenting it to the CPU one array at
a time. The video image is 640 × 480 pixels, with each pixel represented by a 16-bit element. The image
is to be stored in external memory. Figure 24 shows this example.
To transfer data from an external peripheral to an external buffer one array at a time based on EVTn ,
channel n must be configured. Due to the nature of the data (a video frame made up of arrays of pixels)
the destination is essentially a 2D entity. Figure 25 shows the parameters to service the incoming data
with a 1D-to-2D transfer using AB-synchronization. The source address is set to the location of the video
framer peripheral, and the destination address is set to the start of the data buffer. Since the input address
is static, the SRCBIDX is 0 (no modification to the source address). The destination is made up of arrays
of contiguous, linear elements; therefore, the DSTBIDX is set to pixel size, 2 bytes. ANCT is equal to the
pixel size, 2 bytes. BCNT is set to the number of pixels in an array, 640. CCNT is equal to the total
number of arrays in the block, 480. SRCCIDX is 0 since the source address undergoes no increment. The
DSTCIDX is equal to the difference between the starting addresses of each array. Since a pixel is 16 bits
(2 bytes), DSTCIDX is equal to 640 × 2.
Figure 24. Servicing Peripheral Burst Example
EVTx
...1_2..1_1..0_2..0_1
A000 0000h
0_1
0_2
0_3
...
A000 0500h
1_1
1_2
9001 0000h
A000 0A00h
2_1
...
External
peripheral
...
...
...
...
A009 5100h
477_1
...
A009 5600h
478_1
478_2
...
A009 5B00h
479_1
479_2
479_3
...
...
0_638
0_639
0_640
...
1_639
1_640
...
2_640
...
...
...
...
...
477_640
478_639 478_640
479_638 479_639 479_640
...
Figure 25. Servicing Peripheral Burst Example PaRAM
(a) EDMA Parameters
Parameter Contents
Parameter
0010 0004h
Channel Options Parameter (OPT)
Channel Source Address
0280h
Channel Source Address (SRC)
0002h
Count for 2nd Dimension (BCNT)
8000 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0002h
0000h
Destination BCNT Index (DSTBIDX)
0000h
FFFFh
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0500h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
01E0h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
66
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
0
0000
0
000
0000
0
1
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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3.4.3
Continuous Operation
Configuring a DMA channel to receive a single frame of data is useful, and is applicable to some systems.
A majority of the time, however, data is going to be continuously transmitted and received throughout the
entire operation of the CPU. In this case, it is necessary to implement some form of linking such that the
DMA channels continuously reload the necessary parameter sets. In this example, the ASP is configured
to transmit and receive data on a array. To simplify the example, only two channels are active for both
transmit and receive data streams. Each channel receives packets of 128 elements. The packets are
transferred from the serial port to L2 memory and from L2 memory to the serial port, as shown in
Figure 26.
The ASP generates REVT for every element received and generates XEVT for every element transmitted.
To service the data streams, DMA channels 12 and 13 must be set up for 1D-to-1D transfers with
A-synchronization.
Figure 27 shows the parameters for the parameter entries for the channel for these transfers. In order to
service the ASP continuously throughout CPU operation, the channels must be linked to a duplicate
PaRAM set in the PaRAM. After all frames have been transferred, the DMA channels reload and continue.
Figure 28 shows the reload parameters for the channel.
3.4.3.1
Receive Channel
DMA channel 3 services the incoming data stream of the ASP. The source address is set to that of the
data receiver register (DRR), and the destination address is set to the first element of the data block.
Since there are two data channels being serviced, A and B, they are to be located separately within the
L2 SRAM.
In order to facilitate continuous operation, a copy of the PaRAM set for the channel is placed in PaRAM
set 64. The LINK option is set and the link address is provided in the PaRAM set. Upon exhausting the
channel 3 parameter set, the parameters located at the link address are loaded into the channel 3
parameter set and operation continues. This function continues throughout device operation until halted by
the CPU.
3.4.3.2
Transmit Channel
DMA channel 2 services the outgoing data stream of the ASP. In this case the destination address needs
no update, hence, the parameter set changes accordingly. Linking is also used to allow continuous
operation by the DMA channel, with duplicate PaRAM set entries at PaRAM set 65.
Figure 26. Servicing Continuous ASP Data Example
Incoming serial data
1180 0000h
AREVT0
..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1
RSR
01D0 1400h
AXEVT0
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5
Outgoing serial data
A2i
A4i
A9i
A10i A11i A12i A13i
B1i
B2i
B9i
B10i B11i B12i B13i
1180 1000h
01D0 14000h
B3i
B4i
B5i
A7i
...
...
B6i
B7i
...
...
A8i
B8i
A1o A2o A3o A4o A5o A6o A7o A8o
A9i
A10i A11i A12i A13i
...
...
XBUF
1180 1080h
B1o B2o B3o B4o B5o B6o B7o B8o
B9o B10o B11o B12o B13o
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A6i
RBUF
1180 0080h
XSR
A3i
A5i
A1i
...
...
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Figure 27. Servicing Continuous ASP Data Example PaRAM
(a) EDMA Parameters for Receive Channel (PaRAM Set 3) being Linked to PaRAM Set 64
Parameter Contents
Parameter
0010 0000h
Channel Options Parameter (OPT)
01D0 1400h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0001h
0000h
Destination BCNT Index (DSTBIDX)
0080h
4800h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
FFFFh
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content for Receive Channel (PaRAM Set 3)
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
10
8
7
19
4
18
17
16
3
2
1
0000
0
000
0000
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
(c) EDMA Parameters for Transmit Channel (PaRAM Set 2) being Linked to PaRAM Set 65
Parameter Contents
Parameter
0010 1000h
Channel Options Parameter (OPT)
1180 1000h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
01D0 1400h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0001h
Destination BCNT Index (DSTBIDX)
0080h
4820h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
FFFFh
Reserved
Count for 3rd Dimension (CCNT)
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 2)
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
68
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
0
0001
0
000
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Figure 28. Servicing Continuous ASP Data Example Reload PaRAM
(a) EDMA Reload Parameters (PaRAM Set 64) for Receive Channel
Parameter Contents
Parameter
0010 0000h
Channel Options Parameter (OPT)
01D0 1400h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0001h
0000h
Destination BCNT Index (DSTBIDX)
0080h
4800h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
FFFFh
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content for Receive Channel (PaRAM Set 64)
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
10
8
7
19
4
18
17
16
3
2
1
0000
0
000
0000
0
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
(c) EDMA Reload Parameters (PaRAM Set 65) for Transmit Channel
Parameter Contents
Parameter
0010 1000h
Channel Options Parameter (OPT)
1180 1000h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
01D0 1400h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0001h
Destination BCNT Index (DSTBIDX)
0080h
4820h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
FFFFh
Reserved
Count for 3rd Dimension (CCNT)
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65)
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
8
7
4
18
17
16
3
2
1
0
0001
0
000
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Ping-Pong Buffering
Although the previous configuration allows the EDMA3 to service a peripheral continuously, it presents a
number of restrictions to the CPU. Since the input and output buffers are continuously being filled/emptied,
the CPU must match the pace of the EDMA3 very closely in order to process the data. The EDMA3
receive data must always be placed in memory before the CPU accesses it, and the CPU must provide
the output data before the EDMA3 transfers it. Though not impossible, this is an unnecessary challenge. It
is particularly difficult in a 2-level cache scheme.
Ping-pong buffering is a simple technique that allows the CPU activity to be distanced from the EDMA3
activity. This means that there are multiple (usually two) sets of data buffers for all incoming and outgoing
data streams. While the EDMA3 transfers the data into and out of the ping buffers, the CPU manipulates
the data in the pong buffers. When both CPU and EDMA3 activity completes, they switch. The EDMA3
then writes over the old input data and transfers the new output data. Figure 29 shows the ping-pong
scheme for this example.
To change the continuous operation example, such that a ping-pong buffering scheme is used, the DMA
channels need only a moderate change. Instead of one parameter set, there are two; one for transferring
data to/from the ping buffers and one for transferring data to/from the pong buffers. As soon as one
transfer completes, the channel loads the PaRAM set for the other and the data transfers continue.
Figure 30 shows the DMA channel configuration required.
Each channel has two parameter sets, ping and pong. The DMA channel is initially loaded with the ping
parameters (Figure 30). The link address for the ping set is set to the PaRAM offset of the pong parameter
set (Figure 31). The link address for the pong set is set to the PaRAM offset of the ping parameter set
(Figure 32). The channel options, count values, and index values are all identical between the ping and
pong parameters for each channel. The only differences are the link address provided and the address of
the data buffer.
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3.4.4.1
Synchronization With the CPU
In order to utilize the ping-pong buffering technique, the system must signal the CPU when to begin to
access the new data set. After the CPU finishes processing an input buffer (ping), it waits for the EDMA3
to complete before switching to the alternate (pong) buffer. In this example, both channels provide their
channel numbers as their report word and set the TCINTEN bit to 1 to generate an interrupt after
completion. When channel 3 fills an input buffer, the E3 bit in the interrupt pending register (IPR) is set to
1; when channel 2 empties an output buffer, the E2 bit in IPR is set to 1. The CPU must manually clear
these bits. With the channel parameters set, the CPU polls IPR to determine when to switch. The EDMA3
and CPU could alternatively be configured such that the channel completion interrupts the CPU. By doing
this, the CPU could service a background task while waiting for the EDMA3 to complete.
Figure 29. Ping-Pong Buffering for ASP Data Example
..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1
RSR
Pong
Ping
1180 0000h
A1i
A2i
A3i
A4i
A5i
A6i
A7i
A9i
A10i A11i A12i A13i
...
...
A8i
1180 0800h
A1i
A2i
A3i
A4i
A9i
A10i A11i A12i A13i
A5i
A6i
A7i
...
...
B6i
B7i
...
...
A6o
A7o
...
...
B6o
B7o
...
...
A8i
RBUF
1180 0080h
1180 1000h
B1i
B2i
B5i
B6i
B7i
B9i
B10i B11i B12i B13i
...
...
A6o
A7o
...
...
B3i
A3o
B4i
A4o
A5o
A1o
A2o
A9i
A10i A11i A12i A13i
01D0 1400h
B8i
1180 0880h
AREVT0
A8o
1180 1800h
AXEVT0
B1i
B2i
B9i
B10i B11i B12i B13i
B3i
A3o
B4i
A4o
B5i
A1o
A2o
A9i
A10i A11i A12i A13i
A5o
B1o
B2o
B8i
A8o
XBUF
1180 1080h
B1o
B2o
B3o
B4o
B5o
B9o B10o B11o B12o B13o
B6o
B7o
...
...
B8o
1180 1880h
B3o
B4o
B5o
B9o B10o B11o B12o B13o
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5
B8o
XSR
01D0 1400h
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Figure 30. Ping-Pong Buffering for ASP Example PaRAM
(a) EDMA Parameters for Channel 3 (Using PaRAM Set 3 Linked to Pong Set 64)
Parameter Contents
Parameter
0010 3000h
Channel Options Parameter (OPT)
01D0 1400h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0001h
0000h
Destination BCNT Index (DSTBIDX)
0080h
4800h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content for Channel 3
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
12
27
24
11
10
8
7
19
4
18
17
16
3
2
1
0
0011
0
000
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
(c) EDMA Parameters for Channel 2 (Using PaRAM Set 2 Linked to Pong Set 65)
Parameter Contents
Parameter
0010 2000h
Channel Options Parameter (OPT)
1180 1000h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
01D0 1400h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0001h
Destination BCNT Index (DSTBIDX)
0080h
4840h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(d) Channel Options Parameter (OPT) Content for Channel 2
31
23
22
21
20
0
30
000
28
0000
0
0
0
1
00
00
PRIV
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
Reserved
TCC
15
72
12
27
24
11
10
8
7
4
19
18
17
16
3
2
1
0010
0
000
0000
0
0
0
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
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Figure 31. Ping-Pong Buffering for ASP Example Pong PaRAM
(a) EDMA Pong Parameters for Channel 3 at Set 64 Linked to Set 65
Parameter Contents
Parameter
0010 D000h
Channel Options Parameter (OPT)
01D0 1400h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
1180 0800h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0001h
0000h
Destination BCNT Index (DSTBIDX)
0080h
4820h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(b) EDMA Pong Parameters for Channel 2 at Set 66 Linked to Set 67
Parameter Contents
Parameter
0010 C000h
Channel Options Parameter (OPT)
1180 1800h
Channel Source Address (SRC)
0080h
0001h
Count for 2nd Dimension (BCNT)
01E0 2004h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0001h
Destination BCNT Index (DSTBIDX)
0080h
4860h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
Figure 32. Ping-Pong Buffering for ASP Example Ping PaRAM
(a) EDMA Ping Parameters for Channel 3 at Set 65 Linked to Set 64
Parameter Contents
Parameter
0010 D000h
Channel Options Parameter (OPT)
01D0 1400h
0080h
Channel Source Address (SRC)
0001h
Count for 2nd Dimension (BCNT)
1180 0000h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0001h
0000h
Destination BCNT Index (DSTBIDX)
0080h
4800h
BCNT Reload (BCNTRLD)
Source BCNT Index (SRCBIDX)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
(b) EDMA Ping Parameters for Channel 2 at Set 67 Linked to Set 66
Parameter Contents
Parameter
0010 C000h
Channel Options Parameter (OPT)
1180 1000h
0080h
Channel Source Address (SRC)
0001h
Count for 2nd Dimension (BCNT)
01E0 2004h
Count for 1st Dimension (ACNT)
Channel Destination Address (DST)
0000h
0001h
Destination BCNT Index (DSTBIDX)
0080h
4840h
BCNT Reload (BCNTRLD)
Link Address (LINK)
0000h
0000h
Destination CCNT Index (DSTCIDX)
Source CCNT Index (SRCCIDX)
0000h
0001h
Reserved
Count for 3rd Dimension (CCNT)
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Transfer Chaining Examples
The following examples explain the intermediate transfer complete chaining function.
3.4.5.1
Servicing Input/Output FIFOs with a Single Event
Many systems require the use of a pair of external FIFOs that must be serviced at the same rate. One
FIFO buffers data input, and the other buffers data output. The EDMA3 channels that service these FIFOs
can be set up for AB-synchronized transfers. While each FIFO is serviced with a different set of
parameters, both can be signaled from a single event. For example, an external interrupt pin can be tied
to the status flags of one of the FIFOs. When this event arrives, the EDMA3 needs to perform servicing for
both the input and output streams. Without the intermediate transfer complete chaining feature this would
require two events, and thus two external interrupt pins. The intermediate transfer complete chaining
feature allows the use of a single external event (for example, a GPIO event). Figure 33 shows the
EDMA3 setup and illustration for this example.
A GPIO event (in this case, GPINT0) triggers an array transfer. Upon completion of each intermediate
array transfer of channel 32, intermediate transfer complete chaining sets the E63 bit (specified by TCC of
63) in the chained event register high (CERH) and provides a synchronization event to channel 63. Upon
completion of the last array transfer of channel 32, transfer complete chaining—not intermediate transfer
complete chaining—sets the E63 bit in CERH (specified by TCCMODE:TCC) and provides a
synchronization event to channel 63. The completion of channel 63 sets the I63 bit (specified by
TCCMODE:TCC) in the interrupt pending register high (IPRH), which can generate an interrupt to the
CPU, if the I63 bit in the interrupt enable register high (IERH) is set to 1.
3.4.5.2
Breaking Up Large Transfers with Intermediate Chaining
Another feature of intermediate transfer chaining (ITCCHEN) is for breaking up large transfers. A large
transfer may lock out other transfers of the same priority level for the duration of the transfer. For example,
a large transfer on queue 0 from the internal memory to the external memory using the EMIF may starve
other EDMA3 transfers on the same queue. In addition, this large high-priority transfer may prevent the
EMIF for a long duration to service other lower priority transfers. When a large transfer is considered to be
high priority, it should be split into multiple smaller transfers. Figure 34 shows the EDMA3 setup and
illustration of an example single large block transfer.
The intermediate transfer chaining enable (ITCCHEN) provides a method to break up a large transfer into
smaller transfers. For example, to move a single large block of memory (16K bytes), the EDMA3 performs
an A-synchronized transfer. The element count is set to a reasonable value, where reasonable derives
from the amount of time it would take to move this smaller amount of data. Assume 1 Kbyte is a
reasonable small transfer in this example. The EDMA3 is set up to transfer 16 arrays of 1 Kbyte elements,
for a total of 16K byte elements. The TCC field in the channel options parameter (OPT) is set to the same
value as the channel number and ITCCHEN are set. In this example, DMA channel 25 is used and TCC is
also set to 25. The TCINTEN may also be set to trigger interrupt 25 when the last 1 Kbyte array is
transferred. The CPU starts the EDMA3 transfer by writing to the appropriate bit of the event set register
(ESR.E25). The EDMA3 transfers the first 1 Kbyte array. Upon completion of the first array, intermediate
transfer complete code chaining generates a synchronization event to channel 25, a value specified by the
TCC field. This intermediate transfer completion chaining event causes DMA channel 25 to transfer the
next 1 Kbyte array. This process continues until the transfer parameters are exhausted, at which point the
EDMA3 has completed the 16K byte transfer. This method breaks up a large transfer into smaller packets,
thus providing natural time slices in the transfer such that other events may be processed. Figure 35
shows the EDMA3 setup and illustration of the broken up smaller packet transfers.
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Figure 33. Intermediate Transfer Completion Chaining Example
Hardwired event
(tied to GPINT0, event 32)
Chained event
(event 63)
Event 32
Intermediate
transfer complete(A)
Channel 32, array 0
Channel 63, array 0
Event 32
Intermediate
transfer complete(A)
Channel 32, array 1
Channel 63, array 1
Event 32
Intermediate
transfer complete(A)
Channel 63, array 2
Channel 32, array 2
Event 32
Channel 32, array 3
(last array)
Notes:
Transfer complete(B)
Channel 63, array 3
Transfer complete
sets IPRH.I63 = 1
If IPRH.I63 = 1,
CCINTn sent
to CPU
(A) Intermediate transfer complete chaining synchronizes event 63
ITCCHEN = 1, TCC = 011 1111b and sets CERH.E63 = 1
(B) Transfer complete chaining synchronizes event 63
TCCHEN = 1, TCC = 011 1111b and sets CERH.E63 = 1
Setup
Channel 32 parameters
for chaining
Channel 63 parameters
for chaining
Event enable register (EER)
Enable transfer
complete chaining:
OPT.TCCHEN = 1
OPT.TCC = 011 1111b
Enable transfer
completion interrupt:
OPT.TCINTEN = 1
OPT.TCC = 011 1111b
Enable intermediate transfer
complete chaining:
OPT.ITCCHEN = 1
OPT.TCC = 011 1111b
Disable intermediate transfer
complete chaining:
OPT.ITCCHEN = 0
Enable channel 32
EERH.E32 = 1
Figure 34. Single Large Block Transfer Example
Event 25 (CPU writes 1 to ESR.E25)
16 KBytes data transfer
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ACNT = 16384
BCNT = 1
CCNT = 1
1D transfer of 16 KByte elements
OPT.ITCINTEN = 0
OPT.TCC = Don’t care
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Figure 35. Smaller Packet Data Transfers Example
Event 25 (CPU writes 1 to ESR.E25)
ITCCHEN=1, TCC=25 causes
channel 25 to be synchronized again
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
Time gaps allow other transfers on the same priority level
to be performed
EDMA channel 25 setup
ACNT = 1024
BCNT = 16
CCNT = 1
OPT.SYNCDIM = A SYNC
OPT.ITCCHEN = 1
OPT.TCINTEN = 1
OPT.TCC = 25
4
Registers
This section discusses the registers of the EDMA3 controller.
4.1
Register Memory Maps
See your device-specific data manual for the register memory maps.
4.2
Parameter RAM (PaRAM) Entries
Table 16 lists the parameter RAM (PaRAM) entries for the EDMA3 channel controller (EDMA3CC). See
the device-specific data manual for the memory address of these registers.
Table 16. EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries
Offset
76
Acronym
Parameter
0h
OPT
Channel Options
Section 4.2.1
4h
SRC
Channel Source Address
Section 4.2.2
8h
A_B_CNT
A Count/B Count
Section 4.2.3
Ch
DST
Channel Destination Address
Section 4.2.4
10h
SRC_DST_BIDX
Source B Index/Destination B Index
Section 4.2.5
14h
LINK_BCNTRLD
Link Address/B Count Reload
Section 4.2.6
18h
SRC_DST_CIDX
Source C Index/Destination C Index
Section 4.2.7
1Ch
CCNT
C Count
Section 4.2.8
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4.2.1
Channel Options Parameter (OPT)
The channel options parameter (OPT) is shown in Figure 36 and described in Table 17.
Figure 36. Channel Options Parameter (OPT)
31
28
23
22
21
20
Reserved
PRIVID
ITCCHEN
TCCHEN
ITCINTEN
TCINTEN
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
15
12
27
24
11
10
8
7
4
19
18
17
Reserved
R/W-0
16
TCC
R-0
R/W-0
3
2
1
0
TCC
TCCMOD
FWID
Reserved
STATIC
SYNCDIM
DAM
SAM
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Channel Options Parameters (OPT) Field Descriptions
Bit
Field
31-28
Reserved
27-24
PRIVID
23
Value
0
0-Fh
ITCCHEN
Description
Reserved
Privilege identification for the external host/CPU/DMA that programmed this PaRAM set. This value is
set with the EDMA3 master’s privilege identification value when any part of the PaRAM set is written.
Intermediate transfer completion chaining enable.
0
Intermediate transfer complete chaining is disabled.
1
Intermediate transfer complete chaining is enabled.
When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer
completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the
PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.
22
TCCHEN
Transfer complete chaining enable.
0
Transfer complete chaining is disabled.
1
Transfer complete chaining is enabled.
When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion
(upon completion of the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC
value specified.
21
ITCINTEN
Intermediate transfer completion interrupt enable.
0
Intermediate transfer complete interrupt is disabled.
1
Intermediate transfer complete interrupt is enabled.
When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer
completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the
PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a
completion interrupt to the CPU, the corresponding IER[TCC]/IERH[TCC] bit must be set to 1.
20
TCINTEN
Transfer complete interrupt enable.
0
Transfer complete interrupt is disabled.
1
Transfer complete interrupt is enabled.
When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon
completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value
specified. In order to generate a completion interrupt to the CPU, the corresponding
IER[TCC]/IERH[TCC] bit must be set to 1.
19
Reserved
0
Reserved. Always write 0 to this bit.
18
Reserved
0
Reserved
17-12
11
TCC
0-3Fh
TCCMODE
Transfer complete code. This 6-bit code is used to set the relevant bit in chaining enable register
(CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for
interrupts.
Transfer complete code mode. Indicates the point at which a transfer is considered completed for
chaining and interrupt generation.
0
Normal completion: A transfer is considered completed after the data has been transferred.
1
Early completion: A transfer is considered completed after the EDMA3CC submits a TR to the
EDMA3TC. TC may still be transferring data when interrupt/chain is triggered.
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Table 17. Channel Options Parameters (OPT) Field Descriptions (continued)
Bit
Field
Value
10-8
FWID
0-7h
7-4
3
2
1
0
4.2.2
Reserved
Description
FIFO Width. Applies if either SAM or DAM is set to constant addressing mode.
0
FIFO width is 8-bit.
1h
FIFO width is 16-bit.
2h
FIFO width is 32-bit.
3h
FIFO width is 64-bit.
4h
FIFO width is 128-bit.
5h
FIFO width is 256-bit.
6h-7h
Reserved
0
Reserved
STATIC
Static PaRAM set.
0
PaRAM set is not static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be
used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers.
1
PaRAM set is static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be
used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.
SYNCDIM
Transfer synchronization dimension.
0
A-synchronized. Each event triggers the transfer of a single array of ACNT bytes.
1
AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.
DAM
Destination address mode.
0
Increment (INCR) mode. Destination addressing within an array increments. Destination is not a FIFO.
1
Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
SAM
Source address mode.
0
Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
1
Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
Channel Source Address Parameter (SRC)
The channel source address parameter (SRC) specifies the starting byte address of the source. The SRC
is shown in Figure 37 and described in Table 18.
Figure 37. Channel Source Address Parameter (SRC)
31
16
SRC
R/W-x
15
0
SRC
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 18. Channel Source Address Parameter (SRC) Field Descriptions
78
Bit
Field
Value
31-0
SRC
0-FFFF FFFFh
Description
Source address. Specifies the starting byte address of the source.
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4.2.3
A Count/B Count Parameter (A_B_CNT)
The A count/B count parameter (A_B_CNT) specifies the number of bytes within the 1st dimension of a
transfer and the number of arrays of length ACNT. The A_B_CNT is shown in Figure 38 and described in
Table 19.
Figure 38. A Count/B Count Parameter (A_B_CNT)
31
16
BCNT
R/W-x
15
0
ACNT
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 19. A Count/B Count Parameter (A_B_CNT) Field Descriptions
Bit
Field
31-16
BCNT
0-FFFFh B count. Unsigned value specifying the number of arrays in a frame, where an array is ACNT bytes. Valid
values range from 1 to 65 535.
15-0
ACNT
0-FFFFh A count for 1st Dimension. Unsigned value specifying the number of contiguous bytes within an array (first
dimension of the transfer). Valid values range from 1 to 65 535.
4.2.4
Value
Description
Channel Destination Address Parameter (DST)
The channel destination address parameter (DST) specifies the starting byte address of the source. The
DST is shown in Figure 39 and described in Table 20.
Figure 39. Channel Destination Address Parameter (DST)
31
16
DST
R/W-x
15
0
DST
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 20. Channel Destination Address Parameter (DST) Field Descriptions
Bit
Field
Value
31-0
DST
0-FFFF FFFFh
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Description
Destination address. Specifies the starting byte address of the destination where data is
transferred.
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Source B Index/Destination B Index Parameter (SRC_DST_BIDX)
The source B index/destination B index parameter (SRC_DST_BIDX) specifies the value (2s complement)
used for source address modification between each array in the 2nd dimension and the value
(2s complement) used for destination address modification between each array in the 2nd dimension. The
SRC_DST_BIDX is shown in Figure 40 and described in Table 21.
Figure 40. Source B Index/Destination B Index Parameter (SRC_DST_BIDX)
31
16
DSTBIDX
R/W-x
15
0
SRCBIDX
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 21. Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions
Bit
Field
Value
Description
31-16
DSTBIDX
0-FFFFh
Destination B index. Signed value specifying the byte address offset between destination arrays
within a frame (2nd dimension). Valid values range from –32 768 and 32 767.
15-0
SRCBIDX
0-FFFFh
Source B index. Signed value specifying the byte address offset between source arrays within a
frame (2nd dimension). Valid values range from –32 768 and 32 767.
4.2.6
Link Address/B Count Reload Parameter (LINK_BCNTRLD)
The link address/B count reload parameter (LINK_BCNTRLD) specifies the byte address offset in the
PaRAM from which the EDMA3CC loads/reloads the next PaRAM set during linking and the value used to
reload the BCNT field in the A count/B count parameter (A_B_CNT) once the last array in the 2nd
dimension is transferred. The LINK_BCNTRLD is shown in Figure 41 and described in Table 22.
Figure 41. Link Address/B Count Reload Parameter (LINK_BCNTRLD)
31
16
BCNTRLD
R/W-x
15
0
LINK
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 22. Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions
Bit
Field
Value
Description
31-16
BCNTRLD
0-FFFFh
B count reload. The count value used to reload BCNT in the A count/B count parameter
(A_B_CNT) when BCNT decrements to 0 (TR submitted for the last array in 2nd dimension). Only
relevant in A-synchronized transfers.
15-0
LINK
0-FFFFh
Link address. The PaRAM address containing the PaRAM set to be linked (copied from) when the
current PaRAM set is exhausted. You must program the link address to point to a valid aligned
32-byte PaRAM set. The 5 LSBs of the LINK field should be cleared to 0. A value of FFFFh
specifies a null link.
80
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4.2.7
Source C Index/Destination C Index Parameter (SRC_DST_CIDX)
The source C index/destination C index parameter (SRC_DST_CIDX) specifies the value (2s complement)
used for source address modification between each array in the 3rd dimension and the value
(2s complement) used for destination address modification between each array in the 3rd dimension. The
SRC_DST_CIDX is shown in Figure 42 and described in Table 23.
Figure 42. Source C Index/Destination C Index Parameter (SRC_DST_CIDX)
31
16
DSTCIDX
R/W-x
15
0
SRCCIDX
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 23. Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions
Bit
Field
Value
Description
31-16
DSTCIDX
0-FFFFh
Destination C index. Signed value specifying the byte address offset between frames within a
block (3rd dimension). Valid values range from –32 768 and 32 767.
15-0
SRCCIDX
0-FFFFh
Source C index. Signed value specifying the byte address offset between frames within a block
(3rd dimension). Valid values range from –32 768 and 32 767.
4.2.8
C Count Parameter (CCNT)
The C count parameter (CCNT) specifies the number of frames in a block. The CCNT is shown in
Figure 43 and described in Table 24.
Figure 43. C Count Parameter (CCNT)
31
16
Reserved
R/W-x
15
0
CCNT
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 24. C Count Parameter (CCNT) Field Descriptions
Bit
Field
31-16
Reserved
15-0
CCNT
Value
0
0-FFFFh
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Description
Reserved
C counter. Unsigned value specifying the number of frames in a block, where a frame is BCNT
arrays of ACNT bytes. Valid values range from 1 to 65 535.
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EDMA3 Channel Controller Control Registers
Table 25 lists the memory-mapped registers for the EDMA3 channel controller (EDMACC). See the
device-specific data manual for the memory address of these registers and for the shadow region
addresses. All other register offset addresses not listed in Table 25 should be considered as reserved
locations and the register contents should not be modified.
Table 25. EDMACC Registers
Offset
Acronym
Register Description
0h
PID
Peripheral Identification Register
Section 4.3.1.1
Section
4h
CCCFG
EDMA3CC Configuration Register
Section 4.3.1.2
Global Registers
82
100h-1FCh
DCHMAP0DCHMAP63
DMA Channel 0-63 Mapping Registers
Section 4.3.1.3
200h
QCHMAP0
QDMA Channel 0 Mapping Register
Section 4.3.1.4
204h
QCHMAP1
QDMA Channel 1 Mapping Register
Section 4.3.1.4
208h
QCHMAP2
QDMA Channel 2 Mapping Register
Section 4.3.1.4
20Ch
QCHMAP3
QDMA Channel 3 Mapping Register
Section 4.3.1.4
210h
QCHMAP4
QDMA Channel 4 Mapping Register
Section 4.3.1.4
214h
QCHMAP5
QDMA Channel 5 Mapping Register
Section 4.3.1.4
218h
QCHMAP6
QDMA Channel 6 Mapping Register
Section 4.3.1.4
21Ch
QCHMAP7
QDMA Channel 7 Mapping Register
Section 4.3.1.4
240h
DMAQNUM0
DMA Queue Number Register 0
Section 4.3.1.5
244h
DMAQNUM1
DMA Queue Number Register 1
Section 4.3.1.5
248h
DMAQNUM2
DMA Queue Number Register 2
Section 4.3.1.5
24Ch
DMAQNUM3
DMA Queue Number Register 3
Section 4.3.1.5
250h
DMAQNUM4
DMA Queue Number Register 4
Section 4.3.1.5
254h
DMAQNUM5
DMA Queue Number Register 5
Section 4.3.1.5
258h
DMAQNUM6
DMA Queue Number Register 6
Section 4.3.1.5
25Ch
DMAQNUM7
DMA Queue Number Register 7
Section 4.3.1.5
260h
QDMAQNUM
QDMA Queue Number Register
Section 4.3.1.6
284h
QUEPRI
Queue Priority Register (Reserved)
Section 4.3.1.7
300h
EMR
Event Missed Register
Section 4.3.2.1
304h
EMRH
Event Missed Register High
Section 4.3.2.1
308h
EMCR
Event Missed Clear Register
Section 4.3.2.2
30Ch
EMCRH
Event Missed Clear Register High
Section 4.3.2.2
310h
QEMR
QDMA Event Missed Register
Section 4.3.2.3
314h
QEMCR
QDMA Event Missed Clear Register
Section 4.3.2.4
318h
CCERR
EDMA3CC Error Register
Section 4.3.2.5
31Ch
CCERRCLR
EDMA3CC Error Clear Register
Section 4.3.2.6
320h
EEVAL
Error Evaluate Register
Section 4.3.2.7
340h
DRAE0
DMA Region Access Enable Register for Region 0
Section 4.3.3.1
344h
DRAEH0
DMA Region Access Enable Register High for Region 0
Section 4.3.3.1
348h
DRAE1
DMA Region Access Enable Register for Region 1
Section 4.3.3.1
34Ch
DRAEH1
DMA Region Access Enable Register High for Region 1
Section 4.3.3.1
360h
DRAE4
DMA Region Access Enable Register for Region 4
Section 4.3.3.1
364h
DRAEH4
DMA Region Access Enable Register High for Region 4
Section 4.3.3.1
368h
DRAE5
DMA Region Access Enable Register for Region 5
Section 4.3.3.1
36Ch
DRAEH5
DMA Region Access Enable Register High for Region 5
Section 4.3.3.1
370h
DRAE6
DMA Region Access Enable Register for Region 6
Section 4.3.3.1
374h
DRAEH6
DMA Region Access Enable Register High for Region 6
Section 4.3.3.1
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Table 25. EDMACC Registers (continued)
Offset
Acronym
Register Description
378h
DRAE7
DMA Region Access Enable Register for Region 7
Section 4.3.3.1
Section
37Ch
DRAEH7
DMA Region Access Enable Register High for Region 7
Section 4.3.3.1
380h
QRAE0
QDMA Region Access Enable Register for Region 0
Section 4.3.3.2
384h
QRAE1
QDMA Region Access Enable Register for Region 1
Section 4.3.3.2
390h
QRAE4
QDMA Region Access Enable Register for Region 4
Section 4.3.3.2
394h
QRAE5
QDMA Region Access Enable Register for Region 5
Section 4.3.3.2
398h
QRAE6
QDMA Region Access Enable Register for Region 6
Section 4.3.3.2
39Ch
QRAE7
QDMA Region Access Enable Register for Region 7
Section 4.3.3.2
400h-43Ch
Q0E0-Q0E15
Event Queue Entry Registers Q0E0-Q0E15
Section 4.3.4.1
440h-47Ch
Q1E0-Q1E15
Event Queue Entry Registers Q1E0-Q1E15
Section 4.3.4.1
480h-4BCh
Q2E0-Q2E15
Event Queue Entry Registers Q2E0-Q2E15
Section 4.3.4.1
4C0h-4FCh
Q3E0-Q3E15
Event Queue Entry Registers Q3E0-Q3E15
Section 4.3.4.1
600h
QSTAT0
Queue 0 Status Register
Section 4.3.4.2
604h
QSTAT1
Queue 1 Status Register
Section 4.3.4.2
608h
QSTAT2
Queue 2 Status Register
Section 4.3.4.2
60Ch
QSTAT3
Queue 3 Status Register
Section 4.3.4.2
620h
QWMTHRA
Queue Watermark Threshold A Register
Section 4.3.4.3
640h
CCSTAT
EDMA3CC Status Register
Section 4.3.4.4
1000h
ER
Event Register
Section 4.3.5.1
1004h
ERH
Event Register High
Section 4.3.5.1
Global Channel Registers
1008h
ECR
Event Clear Register
Section 4.3.5.2
100Ch
ECRH
Event Clear Register High
Section 4.3.5.2
1010h
ESR
Event Set Register
Section 4.3.5.3
1014h
ESRH
Event Set Register High
Section 4.3.5.3
1018h
CER
Chained Event Register
Section 4.3.5.4
101Ch
CERH
Chained Event Register High
Section 4.3.5.4
1020h
EER
Event Enable Register
Section 4.3.5.5
1024h
EERH
Event Enable Register High
Section 4.3.5.5
1028h
EECR
Event Enable Clear Register
Section 4.3.5.6
102Ch
EECRH
Event Enable Clear Register High
Section 4.3.5.6
1030h
EESR
Event Enable Set Register
Section 4.3.5.7
1034h
EESRH
Event Enable Set Register High
Section 4.3.5.7
1038h
SER
Secondary Event Register
Section 4.3.5.8
103Ch
SERH
Secondary Event Register High
Section 4.3.5.8
1040h
SECR
Secondary Event Clear Register
Section 4.3.5.9
1044h
SECRH
Secondary Event Clear Register High
Section 4.3.5.9
1050h
IER
Interrupt Enable Register
Section 4.3.6.1
1054h
IERH
Interrupt Enable Register High
Section 4.3.6.1
1058h
IECR
Interrupt Enable Clear Register
Section 4.3.6.2
105Ch
IECRH
Interrupt Enable Clear Register High
Section 4.3.6.2
1060h
IESR
Interrupt Enable Set Register
Section 4.3.6.3
1064h
IESRH
Interrupt Enable Set Register High
Section 4.3.6.3
1068h
IPR
Interrupt Pending Register
Section 4.3.6.4
106Ch
IPRH
Interrupt Pending Register High
Section 4.3.6.4
1070h
ICR
Interrupt Clear Register
Section 4.3.6.5
1074h
ICRH
Interrupt Clear Register High
Section 4.3.6.5
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Table 25. EDMACC Registers (continued)
Offset
Acronym
Register Description
1078h
IEVAL
Interrupt Evaluate Register
Section 4.3.6.6
Section
1080h
QER
QDMA Event Register
Section 4.3.7.1
1084h
QEER
QDMA Event Enable Register
Section 4.3.7.2
1088h
QEECR
QDMA Event Enable Clear Register
Section 4.3.7.3
108Ch
QEESR
QDMA Event Enable Set Register
Section 4.3.7.4
1090h
QSER
QDMA Secondary Event Register
Section 4.3.7.5
1094h
QSECR
QDMA Secondary Event Clear Register
Section 4.3.7.6
Shadow Region 0 Channel Registers
84
2000h
ER
Event Register
2004h
ERH
Event Register High
2008h
ECR
Event Clear Register
200Ch
ECRH
Event Clear Register High
2010h
ESR
Event Set Register
2014h
ESRH
Event Set Register High
2018h
CER
Chained Event Register
201Ch
CERH
Chained Event Register High
2020h
EER
Event Enable Register
2024h
EERH
Event Enable Register High
2028h
EECR
Event Enable Clear Register
202Ch
EECRH
Event Enable Clear Register High
2030h
EESR
Event Enable Set Register
2034h
EESRH
Event Enable Set Register High
2038h
SER
Secondary Event Register
203Ch
SERH
Secondary Event Register High
2040h
SECR
Secondary Event Clear Register
2044h
SECRH
Secondary Event Clear Register High
2050h
IER
Interrupt Enable Register
2054h
IERH
Interrupt Enable Register High
2058h
IECR
Interrupt Enable Clear Register
205Ch
IECRH
Interrupt Enable Clear Register High
2060h
IESR
Interrupt Enable Set Register
2064h
IESRH
Interrupt Enable Set Register High
2068h
IPR
Interrupt Pending Register
206Ch
IPRH
Interrupt Pending Register High
2070h
ICR
Interrupt Clear Register
2074h
ICRH
Interrupt Clear Register High
2078h
IEVAL
Interrupt Evaluate Register
2080h
QER
QDMA Event Register
2084h
QEER
QDMA Event Enable Register
2088h
QEECR
QDMA Event Enable Clear Register
208Ch
QEESR
QDMA Event Enable Set Register
2090h
QSER
QDMA Secondary Event Register
2094h
QSECR
QDMA Secondary Event Clear Register
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Table 25. EDMACC Registers (continued)
Offset
Acronym
Register Description
Section
Shadow Region 1 Channel Registers
2200h
ER
Event Register
2204h
ERH
Event Register High
2208h
ECR
Event Clear Register
220Ch
ECRH
Event Clear Register High
2210h
ESR
Event Set Register
2214h
ESRH
Event Set Register High
2218h
CER
Chained Event Register
221Ch
CERH
Chained Event Register High
2220h
EER
Event Enable Register
2224h
EERH
Event Enable Register High
2228h
EECR
Event Enable Clear Register
222Ch
EECRH
Event Enable Clear Register High
2230h
EESR
Event Enable Set Register
2234h
EESRH
Event Enable Set Register High
2238h
SER
Secondary Event Register
223Ch
SERH
Secondary Event Register High
2240h
SECR
Secondary Event Clear Register
2244h
SECRH
Secondary Event Clear Register High
2250h
IER
Interrupt Enable Register
2254h
IERH
Interrupt Enable Register High
2258h
IECR
Interrupt Enable Clear Register
225Ch
IECRH
Interrupt Enable Clear Register High
2260h
IESR
Interrupt Enable Set Register
2264h
IESRH
Interrupt Enable Set Register High
2268h
IPR
Interrupt Pending Register
226Ch
IPRH
Interrupt Pending Register High
2270h
ICR
Interrupt Clear Register
2274h
ICRH
Interrupt Clear Register High
2278h
IEVAL
Interrupt Evaluate Register
2280h
QER
QDMA Event Register
2284h
QEER
QDMA Event Enable Register
2288h
QEECR
QDMA Event Enable Clear Register
228Ch
QEESR
QDMA Event Enable Set Register
2290h
QSER
QDMA Secondary Event Register
2294h
QSECR
QDMA Secondary Event Clear Register
2400h-2494h
—
Reserved (Shadow Region 2 Channel Registers)
2600h-2694h
—
Reserved (Shadow Region 3 Channel Registers)
2800h-2894h
—
Shadow Region 4 Channel Registers
2A00h-2A94h
—
Shadow Region 5 Channel Registers
2C00h-2C94h
—
Shadow Region 6 Channel Registers
2E00h-2E94h
—
Shadow Region 7 Channel Registers
4000h-7FFFh
—
Parameter RAM (PaRAM) (see Table 1)
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Global Registers
4.3.1.1
Peripheral Identification Register (PID)
The peripheral identification register (PID) uniquely identifies the EDMA3CC and the specific revision of
the EDMA3CC. The PID is shown in Figure 44 and described in Table 26.
Figure 44. Peripheral ID Register (PID)
31
16
PID
R-4001h
15
0
PID
R-1B00h
LEGEND: R = Read only; -n = value after reset
Table 26. Peripheral ID Register (PID) Field Descriptions
Bit
Field
31-0
Value
Description
PID
Peripheral identifier.
4001 1B00h
4.3.1.2
Uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC.
EDMA3CC Configuration Register (CCCFG)
The EDMA3CC configuration register (CCCFG) provides the features/resources for the EDMA3CC in a
particular device. The CCCFG is shown in Figure 45 and described in Table 27.
Figure 45. EDMA3CC Configuration Register (CCCFG)
31
26
23
22
25
24
Reserved
MP_EXIST
CHMAP_EXIST
R-x
R-0
R-1
21
20
19
18
16
Reserved
NUM_REGN
Reserved
NUM_EVQUE
R-0
R-3h
R-x
R-3
15
14
12
11
10
8
Reserved
NUM_PAENTRY
Reserved
NUM_INTCH
R-x
R-5h
R-x
R-4h
7
6
4
3
2
0
Reserved
NUM_QDMACH
Reserved
NUM_DMACH
R-x
R-4h
R-x
R-5h
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset
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Table 27. EDMA3CC Configuration Register (CCCFG) Field Descriptions
Bit
31-26
25
24
Field
Value
Description
Reserved
0-3Fh
Reserved
MP_EXIST
Reserved
21-20
NUM_REGN
18-16
0
No memory protection.
1
Reserved
CHMAP_EXIST
23-22
19
Memory protection existence.
Channel mapping existence
Reserved.
1
Channel mapping logic is included. This implies that there is no fixed association for a channel
number to a parameter entry number. In other words, using the DMA channel mapping registers
(DCHMAPn), a PaRAM entry can be mapped to any channel.
0
Reserved
0-3h
Number of shadow regions.
0-2h
Reserved
3h
8 regions
0
Reserved
Reserved
NUM_EVQUE
0
0-7h
Number of queues/number of TCs.
0-2h
Reserved
3h
15
14-12
11
10-8
Reserved
0
Reserved
Reserved
NUM_PAENTRY
0-7h
Number of PaRAM sets.
0-4h
Reserved
5h
512 sets
6h-7h
Reserved
0
Reserved
Reserved
NUM_INTCH
0-7h
Number of interrupt channels.
0-3h
Reserved
4h
7
6-4
Reserved
0
Reserved
0-7h
Number of QDMA channels.
0-3h
Reserved
4h
3
2-0
8 QDMA channels
5h-7h
Reserved
0
Reserved
Reserved
NUM_DMACH
64 interrupt channels
5h-7h
Reserved
NUM_QDMACH
4 EDMA3TC/Event Queues
4h-7h
0-7h
Number of DMA channels.
0-4h
Reserved
5h
6h-7h
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Reserved
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DMA Channel Map n Registers (DCHMAPn)
The DMA channel map n register (DCHMAPn) is shown in Figure 46 and described in Table 28.
Figure 46. DMA Channel Map n Registers (DCHMAPn)
31
16
Reserved
R-0
15
14
13
5
4
0
Reserved
PAENTRY
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. DMA Channel Map n Registers (DCHMAPn) Field Descriptions
Bit
Field
Value
31-14
Reserved
0
13-5
PAENTRY
0-1FFh
4-0
Reserved
0
4.3.1.4
Description
Reserved
Points to the PaRAM set number for DMA channel n.
Reserved
QDMA Channel Map n Registers (QCHMAPn)
Each QDMA channel in EDMA3CC can be associated with any PaRAM set available on the device.
Furthermore, the specific trigger word (0-7) of the PaRAM set can be programmed. The PaRAM set
association and trigger word for every QDMA channel register is configurable using the QDMA channel
map n register (QCHMAPn). The QCHMAPn is shown in Figure 47 and described in Table 29.
NOTE: At reset the QDMA channel map registers for all QDMA channels point to the PaRAM set 0.
Prior to using any QDMA channel, QCHMAPn should be programmed appropriately to point
to a different PaRAM set.
Figure 47. QDMA Channel Map n Registers (QCHMAPn)
31
16
Reserved
R-0
15
14
13
5
4
2
1
0
Reserved
PAENTRY
TRWORD
Reserved
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. QDMA Channel Map n Registers (QCHMAPn) Field Descriptions
Bit
Field
Value
31-14
Reserved
0
13-5
PAENTRY
0-1FFh
0-7Fh
80h-1FFh
88
4-2
TRWORD
0-7h
1-0
Reserved
0
Description
Reserved
PAENTRY points to the PaRAM set number for QDMA channel n.
PaRAM set number 0 through 127
Reserved
Points to the specific PaRAM entry or the trigger word in the PaRAM set pointed to by
PAENTRY. A write to the trigger word results in a QDMA event being recognized.
Reserved
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4.3.1.5
DMA Channel Queue Number Registers (DMAQNUMn)
The DMA channel queue number register (DMAQNUMn) allows programmability of each of the 64 DMA
channels in the EDMA3CC to submit its associated synchronization event to any event queue in the
EDMA3CC. At reset, all channels point to event queue 0. The DMAQNUMn is shown in Figure 48 and
described in Table 30. The channels and their corresponding bits in DMAQNUMn are shown in Table 31.
NOTE: Since the event queues in EDMA3CC have a fixed association to the transfer controllers,
that is, Q0 TRs are submitted to TC0, Q1 TRs are submitted to TC1, etc., by programming
DMAQNUMn for a particular DMA channel also dictates which transfer controller is utilized
for the data movement (or which EDMA3TC receives the TR request).
Figure 48. DMA Channel Queue Number Registers (DMAQNUMn)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
En
Rsvd
En
Rsvd
En
Rsvd
En
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
En
Rsvd
En
Rsvd
En
Rsvd
En
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. DMA Channel Queue Number Registers (DMAQNUMn) Field Descriptions
Bit
31-0
Field
Value
En
0-7h
Description
DMA queue number. Contains the event queue number to be used for the corresponding DMA channel.
Programming DMAQNUMn for an event queue number to a value more then the number of queues
available in the EDMA3CC results in undefined behavior.
0
Event n is queued on Q0.
1h
Event n is queued on Q1.
2h
Event n is queued on Q2.
3h
Event n is queued on Q3.
4h-7h
Reserved
Table 31. Bits in DMAQNUMn
DMAQNUMn
En bit
0
1
2
3
4
5
6
7
0-2
E0
E8
E16
E24
E32
E40
E48
E56
4-6
E1
E9
E17
E25
E33
E41
E49
E57
8-10
E2
E10
E18
E26
E34
E42
E50
E58
12-14
E3
E11
E19
E27
E35
E43
E51
E59
16-18
E4
E12
E20
E28
E36
E44
E52
E60
20-22
E5
E13
E21
E29
E37
E45
E53
E61
24-26
E6
E14
E22
E30
E38
E46
E54
E62
28-30
E7
E15
E23
E31
E39
E47
E55
E63
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QDMA Channel Queue Number Register (QDMAQNUM)
The QDMA channel queue number register (QDMAQNUM) is used to program all the QDMA channels in
the EDMA3CC to submit the associated QDMA event to any of the event queues in the EDMA3CC. The
QDMAQNUM is shown in Figure 49 and described in Table 32.
Figure 49. QDMA Channel Queue Number Register (QDMAQNUM)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
E7
Rsvd
E6
Rsvd
E5
Rsvd
E4
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
E3
Rsvd
E2
Rsvd
E1
Rsvd
E0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
Bit
Field
31-0
En
Value
0-7h
QDMA queue number. Contains the event queue number to be used for the corresponding QDMA
channel.
0
Event n is queued on Q0.
1h
Event n is queued on Q1.
2h
Event n is queued on Q2.
3h
Event n is queued on Q3.
4h-7h
4.3.1.7
Description
Reserved
Queue Priority Register (QUEPRI)
CAUTION
Use of the queue priority register (QUEPRI) to configure the queue/transfer
controller priority may cause undefined behavior. You should treat this register
as reserved and not attempt to modify the contents of this register.
The queue priority register (QUEPRI) is a reserved register. The priority of the individual queues is set and
changed at the system level by the bus master priority control registers (MSTPRI0, MSTPRI1, and
MSTPRI2). See the device-specific data manual for information on these registers.
4.3.2
Error Registers
The EDMA3CC contains a set of registers that provide information on missed DMA and/or QDMA events,
and instances when event queue thresholds are exceeded. If any of the bits in these registers is set, it
results in the EDMA3CC generating an error interrupt.
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4.3.2.1
Event Missed Registers (EMR/EMRH)
For a particular DMA channel, if a second event is received prior to the first event getting cleared/serviced,
the bit corresponding to that channel is set/asserted in the event missed registers (EMR/EMRH). All
trigger types are treated individually, that is, manual triggered (ESR/ESRH), chain triggered (CER/CERH),
and event triggered (ER/ERH) are all treated separately. The EMR/EMRH bits for a channel are also set if
an event on that channel encounters a NULL entry (or a NULL TR is serviced). If any EMR/EMRH bit is
set (and all errors, including bits in other error registers (QEMR, CCERR) were previously cleared), the
EDMA3CC generates an error interrupt. Refer to Section 2.9.4 for details on EDMA3CC error interrupt
generation.
The EMR is shown in Figure 50 and described in Table 33. The EMRH is shown in Figure 51 and
described in Table 34.
Figure 50. Event Missed Register (EMR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 33. Event Missed Register (EMR) Field Descriptions
Bit
31-0
Field
Value
Description
En
Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear
register (EMCR).
0
No missed event.
1
Missed event occurred.
Figure 51. Event Missed Register High (EMRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 34. Event Missed Register High (EMRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Channel 32–63 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed
clear register high (EMCRH).
0
No missed event.
1
Missed event occurred.
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Event Missed Clear Registers (EMCR/EMCRH)
Once a missed event is posted in the event missed registers (EMR/EMRH), the bit remains set and you
need to clear the set bit(s). This is done by way of CPU writes to the event missed clear registers
(EMCR/EMCRH). Writing a 1 to any of the bits clears the corresponding missed event (bit) in EMR/EMRH;
writing a 0 has no effect.
The EMCR is shown in Figure 52 and described in Table 35. The EMCRH is shown in Figure 53 and
described in Table 36.
Figure 52. Event Missed Clear Register (EMCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 35. Event Missed Clear Register (EMCR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event missed 0-31 clear. All error bits must be cleared before additional error interrupts will be asserted
by the EDMA3CC.
0
No effect.
1
Corresponding missed event bit in the event missed register (EMR) is cleared (En = 0).
Figure 53. Event Missed Clear Register High (EMCRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 36. Event Missed Clear Register High (EMCRH) Field Descriptions
Bit
31-0
92
Field
Value
En
Description
Event missed 32–63 clear. All error bits must be cleared before additional error interrupts will be asserted
by the EDMA3CC.
0
No effect.
1
Corresponding missed event bit in the event missed register high (EMRH) is cleared (En = 0).
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4.3.2.3
QDMA Event Missed Register (QEMR)
For a particular QDMA channel, if two QDMA events are detected without the first event getting
cleared/serviced, the bit corresponding to that channel is set/asserted in the QDMA event missed register
(QEMR). The QEMR bits for a channel are also set if a QDMA event on the channel encounters a NULL
entry (or a NULL TR is serviced). If any QEMR bit is set (and all errors, including bits in other error
registers (EMR/EMRH, CCERR) were previously cleared), the EDMA3CC generates an error interrupt.
Refer to Section 2.9.4 for details on EDMA3CC error interrupt generation.
The QEMR is shown in Figure 54 and described in Table 37.
Figure 54. QDMA Event Missed Register (QEMR)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 37. QDMA Event Missed Register (QEMR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
Value
0
Description
Reserved
Channel 0-7 QDMA event missed. En is cleared by writing a 1 to the corresponding bit in the QDMA
event missed clear register (QEMCR).
0
No missed event.
1
Missed event occurred.
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QDMA Event Missed Clear Register (QEMCR)
Once a missed event is posted in the QDMA event missed registers (QEMR), the bit remains set and you
need to clear the set bit(s). This is done by way of CPU writes to the QDMA event missed clear registers
(QEMCR). Writing a 1 to any of the bits clears the corresponding missed event (bit) in QEMR; writing a 0
has no effect.
The QEMCR is shown in Figure 55 and described in Table 38.
Figure 55. QDMA Event Missed Clear Register (QEMCR)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 38. QDMA Event Missed Clear Register (QEMCR) Field Descriptions
Bit
94
Field
31-8
Reserved
7-0
En
Value
0
Description
Reserved
QDMA event missed clear. All error bits must be cleared before additional error interrupts will be
asserted by the EDMA3CC.
0
No effect.
1
Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0).
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4.3.2.5
EDMA3CC Error Register (CCERR)
The EDMA3CC error register (CCERR) indicates whether or not at any instant of time the number of
events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set
in the queue watermark threshold register (QWMTHRA). Additionally, CCERR also indicates if when the
number of outstanding TRs that have been programmed to return transfer completion code (TRs which
have the TCINTEN or TCCHEN bit in OPT set to 1) to the EDMA3CC has exceeded the maximum
allowed value of 63. If any bit in CCERR is set (and all errors, including bits in other error registers
(EMR/EMRH, QEMR) were previously cleared), the EDMA3CC generates an error interrupt. Refer to
Section 2.9.4 for details on EDMA3CC error interrupt generation. Once the error bits are set in CCERR,
they can only be cleared by writing to the corresponding bits in the EDMA3CC error clear register
(CCERRCLR).
The CCERR is shown in Figure 56 and described in Table 39.
Figure 56. EDMA3CC Error Register (CCERR)
31
17
15
16
Reserved
TCCERR
R-0
R-0
3
2
1
0
Reserved
4
QTHRXCD3
QTHRXCD2
QTHRXCD1
QTHRXCD0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 39. EDMA3CC Error Register (CCERR) Field Descriptions
Bit
Field
31-17
Reserved
16
TCCERR
15-4
3
2
1
0
Reserved
Value
0
Description
Reserved
Transfer completion code error. TCCERR is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Total number of allowed TCCs outstanding has not been reached.
1
Total number of allowed TCCs has been reached.
0
Reserved
QTHRXCD3
Queue threshold error for queue 3. QTHRXCD3 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD2
Queue threshold error for queue 2. QTHRXCD2 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD1
Queue threshold error for queue 1. QTHRXCD1 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
QTHRXCD0
Queue threshold error for queue 0. QTHRXCD0 is cleared by writing a 1 to the corresponding bit in the
EDMA3CC error clear register (CCERRCLR).
0
Watermark/threshold has not been exceeded.
1
Watermark/threshold has been exceeded.
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EDMA3CC Error Clear Register (CCERRCLR)
The EDMA3CC error clear register (CCERRCLR) is used to clear any error bits that are set in the
EDMA3CC error register (CCERR). In addition, CCERRCLR also clears the values of some bit fields in
the queue status registers (QSTATn) associated with a particular event queue. Writing a 1 to any of the
bits clears the corresponding bit in CCERR; writing a 0 has no effect.
The CCERRCLR is shown in Figure 57 and described in Table 40.
Figure 57. EDMA3CC Error Clear Register (CCERRCLR)
31
17
16
Reserved
TCCERR
W-0
W-0
15
3
2
1
0
Reserved
4
QTHRXCD3
QTHRXCD2
QTHRXCD1
QTHRXCD0
W-0
W-0
W-0
W-0
W-0
LEGEND: W= Write only; -n = value after reset
Table 40. EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
Bit
Field
31-17
Reserved
16
TCCERR
15-4
3
2
1
0
96
Reserved
Value
0
Description
Reserved
Transfer completion code error clear.
0
No effect.
1
Clears the TCCERR bit in the EDMA3CC error register (CCERR).
0
Reserved
QTHRXCD3
Queue threshold error clear for queue 3.
0
No effect.
1
Clears the QTHRXCD3 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue 3 status register (QSTAT3).
QTHRXCD2
Queue threshold error clear for queue 2.
0
No effect.
1
Clears the QTHRXCD2 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue 2 status register (QSTAT2).
QTHRXCD1
Queue threshold error clear for queue 1.
0
No effect.
1
Clears the QTHRXCD1 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue 1 status register (QSTAT1).
QTHRXCD0
Queue threshold error clear for queue 0.
0
No effect.
1
Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in
the queue 0 status register (QSTAT0).
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4.3.2.7
Error Evaluation Register (EEVAL)
The EDMA3CC error interrupt is asserted whenever an error bit is set in any of the error registers
(EMR/EMRH, QEMR, and CCERR). For subsequent error bits that get set, the EDMA3CC error interrupt
is reasserted only when transitioning from an “all the error bits cleared” to “at least one error bit is set”.
Alternatively, a CPU write of 1 to the EVAL bit in the error evaluation register (EEVAL) results in
reasserting the EDMA3CC error interrupt, if there are any outstanding error bits set due to subsequent
error conditions. Writes of 0 have no effect.
The EEVAL is shown in Figure 58 and described in Table 41.
Figure 58. Error Evaluation Register (EEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
2
Rsvd
EVAL
R-0
R/W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 41. Error Evaluation Register (EEVAL) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
Reserved
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0
EVAL
Error interrupt evaluate.
0
No effect.
1
EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers
(EMR/EMRH, QEMR, or CCERR).
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Region Access Enable Registers
The region access enable register group consists of the DMA access enable registers (DRAEm and
DRAEHm) and the QDMA access enable registers (QRAEm). Where m is the number of shadow regions
in the EDMA3CC memory map for a device. You can configure these registers to assign ownership of
DMA/QDMA channels to a particular shadow region.
4.3.3.1
DMA Region Access Enable for Region m (DRAEm)
The DMA region access enable register for shadow region m (DRAEm/DRAEHm) is programmed to allow
or disallow read/write accesses on a bit-by-bit bases for all DMA registers in the shadow region m view of
the DMA channel registers. See the EDMA3CC register memory map for a list of all the DMA channel and
interrupt registers mapped in the shadow region view. Additionally, the DRAEm/DRAEHm configuration
determines completion of which DMA channels will result in assertion of the shadow region m DMA
completion interrupt (see Section 2.9).
The DRAEm is shown in Figure 59 and described in Table 42. The DRAEHm is shown in Figure 60 and
described in Table 42.
Figure 59. DMA Region Access Enable Register for Region m (DRAEm)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 60. DMA Region Access Enable High Register for Region m (DRAEHm)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 42. DMA Region Access Enable Registers for Region m (DRAEm/DRAEHm)
Field Descriptions
Bit
31-0
98
Field
Value
En
Description
DMA region access enable for bit n/channel n in region m.
0
Accesses via region m address space to bit n in any DMA channel register are not allowed. Reads return
0 on bit n and writes do not modify the state of bit n. Enabled interrupt bits for bit n do not contribute to the
generation of a transfer completion interrupt for shadow region m.
1
Accesses via region m address space to bit n in any DMA channel register are allowed. Reads return the
value from bit n and writes modify the state of bit n. Enabled interrupt bits for bit n contribute to the
generation of a transfer completion interrupt for shadow region m.
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4.3.3.2
QDMA Region Access Enable Registers (QRAEm)
The QDMA region access enable register for shadow region m (QRAEm) is programmed to allow or
disallow read/write accesses on a bit-by-bit bases for all QDMA registers in the shadow region m view of
the QDMA registers. This includes all 8-bit QDMA registers.
The QRAEm is shown in Figure 61 and described in Table 43.
Figure 61. QDMA Region Access Enable for Region m (QRAEm)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 43. QDMA Region Access Enable for Region m (QRAEm) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
Value
0
Description
Reserved
QDMA region access enable for bit n/QDMA channel n in region m.
0
Accesses via region m address space to bit n in any QDMA channel register are not allowed. Reads
return 0 on bit n and writes do not modify the state of bit n.
1
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return
the value from bit n and writes modify the state of bit n.
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Status/Debug Visibility Registers
The following set of registers provide visibility into the event queues and a TR lifecycle. These are useful
for system debug as they provide in-depth visibility for the events queued up in the event queue and also
provide information on what parts of the EDMA3CC logic are active once the event has been received by
the EDMA3CC.
4.3.4.1
Event Queue Entry Registers (QxEy)
The event queue entry registers (QxEy) exist for all 16 queue entries (the maximum allowed queue
entries) for all event queues in the EDMA3CC.
There are Q0E0 to Q0E15, Q1E0 to Q1E15, Q2E0 to Q2E15, and Q3E0 to Q3E15. Each register details
the event number (ENUM) and the event type (ETYPE). For example, if the value in Q1E4 is read as 000
004Fh, this means the 4th entry in queue 1 is a manually-triggered event on DMA channel 15.
The QxEy is shown in Figure 62 and described in Table 44.
Figure 62. Event Queue Entry Registers (QxEy)
31
16
Reserved
R-0
15
8
7
6
5
0
Reserved
ETYPE
ENUM
R-0
R-x
R-x
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 44. Event Queue Entry Registers (QxEy) Field Descriptions
Bit
Field
31-8
Reserved
7-6
ETYPE
5-0
ENUM
Value
0
0-3h
Reserved
Event entry y in queue x. Specifies the specific event type for the given entry in the event queue.
0
Event triggered via ER
1h
Manual triggered via ESR
2h
Chain triggered via CER
3h
Autotriggered via QER
0-3Fh
0-7h
0-3Fh
100
Description
Event entry y in queue x. Event number:
QDMA channel number (0 to 7)
DMA channel/event number (0 to 63)
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4.3.4.2
Queue n Status Registers (QSTATn)
The queue n status register (QSTATn) is shown in Figure 63 and described in Table 45.
Figure 63. Queue n Status Register (QSTATn)
31
25
15
13
24
23
21
20
16
Reserved
THRXCD
Reserved
WM
R-0
R-0
R-0
R-0
12
8
7
4
3
0
Reserved
NUMVAL
Reserved
STRTPTR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 45. Queue n Status Register (QSTATn) Field Descriptions
Bit
Field
31-25
Reserved
24
THRXCD
23-21
Reserved
20-16
WM
Value
0
Description
Reserved
Threshold exceeded. THRXCD is cleared by writing a 1 to the corresponding QTHRXCDn bit in
the EDMA3CC error clear register (CCERRCLR).
0
Threshold specified by the Qn bit in the queue watermark threshold A register (QWMTHRA) has
not been exceeded.
1
Threshold specified by the Qn bit in the queue watermark threshold A register (QWMTHRA) has
been exceeded.
0
Reserved
0-1Fh
Watermark for maximum queue usage. Watermark tracks the most entries that have been in
queue n since reset or since the last time that the watermark (WM) bit was cleared. WM is cleared
by writing a 1 to the corresponding QTHRXCDn bit in the EDMA3CC error clear register
(CCERRCLR).
0-10h
Legal values are 0 (empty) to 10h (full).
11h-1Fh
Reserved
15-13
Reserved
0
Reserved
12-8
NUMVAL
0-1Fh
Number of valid entries in queue n. The total number of entries residing in the queue manager
FIFO at a given instant. Always enabled.
0-10h
Legal values are 0 (empty) to 10h (full).
11h-1Fh
Reserved
Reserved
7-4
Reserved
0
3-0
STRTPTR
0-Fh
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Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal
values are 0 (0th entry) to Fh (15th entry).
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Queue Watermark Threshold A Register (QWMTHRA)
The queue watermark threshold A register (QWMTHRA) is shown in Figure 64 and described in Table 46.
Figure 64. Queue Watermark Threshold A Register (QWMTHRA)
31
29
28
24
23
21
20
16
Reserved
Q3
Reserved
Q2
R-0
R/W-10h
R-0
R/W-10h
15
13
12
8
7
5
4
0
Reserved
Q1
Reserved
Q0
R-0
R/W-10h
R-0
R/W-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 46. Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions
Bit
Field
31-29
Reserved
28-24
Q3
Value
0
Reserved
20-16
Q2
Queue threshold for queue 3 value. The QTHRXCD3 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue 3 status register (QSTAT3) are set when the number of events
in queue 3 at an instant in time (visible via the NUMVAL bit in QSTAT3) equals or exceeds the
value specified by Q3.
0-10h
The default is 16 (maximum allowed).
Reserved
12-8
Q1
Reserved
0
Reserved
0-1Fh
Queue threshold for queue 2 value. The QTHRXCD2 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue 2 status register (QSTAT2) are set when the number of events
in queue 2 at an instant in time (visible via the NUMVAL bit in QSTAT2) equals or exceeds the
value specified by Q2.
0-10h
The default is 16 (maximum allowed).
Reserved
4-0
Q0
Reserved
0
Reserved
0-1Fh
Queue threshold for queue 1 value. The QTHRXCD1 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue 1 status register (QSTAT1) are set when the number of events
in queue 1 at an instant in time (visible via the NUMVAL bit in QSTAT1) equals or exceeds the
value specified by Q1.
0-10h
The default is 16 (maximum allowed).
Disables the threshold errors.
12h-1Fh
Reserved
0
Reserved
0-1Fh
Queue threshold for queue 0 value. The QTHRXCD0 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue 0 status register (QSTAT0) are set when the number of events
in queue 0 at an instant in time (visible via the NUMVAL bit in QSTAT0) equals or exceeds the
value specified by Q0.
0-10h
The default is 16 (maximum allowed).
11h
12h-1Fh
102
Disables the threshold errors.
12h-1Fh
11h
7-5
Disables the threshold errors.
12h-1Fh
11h
15-13
Reserved
0-1Fh
11h
23-21
Description
Disables the threshold errors.
Reserved
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4.3.4.4
EDMA3CC Status Register (CCSTAT)
The EDMA3CC status register (CCSTAT) has a number of status bits that reflect which parts of the
EDMA3CC logic is active at any given instant of time. The CCSTAT is shown in Figure 65 and described
in Table 47.
Figure 65. EDMA3CC Status Register (CCSTAT)
31
24
Reserved
R-0
23
20
15
19
18
17
16
Reserved
QUEACTV3
QUEACTV2
QUEACTV1
QUEACTV0
R-0
R-0
R-0
R-0
R-0
14
13
8
Reserved
COMPACTV
R-0
R-0
7
4
3
2
1
0
Reserved
5
ACTV
WSTATACTV
TRACTV
QEVTACTV
EVTACTV
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 47. EDMA3CC Status Register (CCSTAT) Field Descriptions
Bit
31-20
19
18
17
16
Field
Value
Reserved
0
QUEACTV3
0
No events are queued in queue 3.
1
At least one TR is queued in queue 3.
Queue 2 active.
0
No events are queued in queue 2.
1
At least one TR is queued in queue 2.
QUEACTV1
Queue 1 active.
0
No events are queued in queue 1.
1
At least one TR is queued in queue 1.
QUEACTV0
Reserved
13-8
COMPACTV
Queue 0 active.
0
No events are queued in queue 0.
1
At least one TR is queued in queue 0.
0
Reserved
0-3Fh
0
1h-3Fh
7-5
4
Reserved
Queue 3 active.
QUEACTV2
15-14
Description
Reserved
0
ACTV
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Completion request active. The COMPACTV field reflects the count for the number of completion
requests submitted to the transfer controllers. This count increments every time a TR is submitted
and is programmed to report completion (the TCINTEN or TCCCHEN bits in OPT in the parameter
entry associated with the TR are set to 1). The counter decrements for every valid TCC received
back from the transfer controllers. If at any time the count reaches a value of 63, the EDMA3CC will
not service any new TRs until the count is less then 63 (or return a transfer completion code from a
transfer controller, which would decrement the count).
No completion requests outstanding.
Total of 1 completion request to 63 completion requests are outstanding.
Reserved
Channel controller active. Channel controller active is a logical-OR of each of the *ACTV bits. The
ACTV bit remains high through the life of a TR.
0
Channel is idle.
1
Channel is busy.
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Table 47. EDMA3CC Status Register (CCSTAT) Field Descriptions (continued)
Bit
Field
3
Value
WSTATACTV
2
Write status interface active.
0
Write status req is idle and write status fifo is idle.
1
Either the write status request is active or additional write status responses are pending in the write
status fifo.
TRACTV
1
Transfer request active.
0
Transfer request processing/submission logic is inactive.
1
Transfer request processing/submission logic is active.
QEVTACTV
0
QDMA event active.
0
No enabled QDMA events are active within the EDMA3CC.
1
At least one enabled QDMA event (QER) is active within the EDMA3CC.
EVTACTV
4.3.5
Description
DMA event active.
0
No enabled DMA events are active within the EDMA3CC.
1
At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC.
DMA Channel Registers
The following sets of registers pertain to the 64 DMA channels. The 64 DMA channels consist of a set of
registers (with exception of DMAQNUMn) that each have 64 bits and the bit position of each register
matches the DMA channel number. Each register is named with the format reg_name that corresponds to
DMA channels 0 through 31 and reg_name_High that corresponds to DMA channels 32 through 64.
For example, the event register (ER) corresponds to DMA channel 0 through 31 and the event register
high register (ERH) corresponds to DMA channel 32 through 63. The register is typically called the event
register.
The DMA channel registers are accessible via read/writes to the global address range. They are also
accessible via read/writes to the shadow address range. The read/write ability to the registers in the
shadow region are controlled by the DMA region access registers (DRAEm/DRAEHm). The registers are
described in Section 4.3.3.1 and the details for shadow region/global region usage is explained in
Section 2.7.
4.3.5.1
Event Registers (ER, ERH)
All external events are captured in the event register (ER/ERH). The events are latched even when the
events are not enabled. If the event bit corresponding to the latched event is enabled (EER.En/EERH.En
= 1), then the event is evaluated by the EDMA3CC logic for an associated transfer request submission to
the transfer controllers. The event register bits are automatically cleared (ER.En/ERH.En = 0) once the
corresponding events are prioritized and serviced. If ER.En/ERH.En are already set and another event is
received on the same channel/event, then the corresponding event is latched in the event miss register
(EMR.En/EMRH.En), provided that the event was enabled (EER.En/EERH.En = 1).
Event n can be cleared by the CPU writing a 1 to corresponding event bit in the event clear register
(ECR/ECRH). The setting of an event is a higher priority relative to clear operations (via hardware or
software). If set and clear conditions occur concurrently, the set condition wins. If the event was previously
set, then EMR/EMRH would be set since an event is lost. If the event was previously clear, then the event
remains set and is prioritized for submission to the event queues.
Table 5 provides the type of synchronization events and the EDMA3CC channels associated to each of
these external events.
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The ER is shown in Figure 66 and described in Table 48. The ERH is shown in Figure 67 and described in
Table 49.
Figure 66. Event Register (ER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
E20
19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 48. Event Register (ER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event 0-31. Events 0-31 are captured by the EDMA3CC and are latched into ER. The events are set
(En = 1) even when events are disabled (En = 0 in the event enable register, EER).
0
EDMA3CC event is not asserted.
1
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA
events for submission to the EDMA3TC.
Figure 67. Event Register High (ERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 49. Event Register High (ERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event 32-63. Events 32-63 are captured by the EDMA3CC and are latched into ERH. The events are set
(En = 1) even when events are disabled (En = 0 in the event enable register high, EERH).
0
EDMA3CC event is not asserted.
1
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA
events for submission to the EDMA3TC.
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Event Clear Registers (ECR, ECRH)
Once an event has been posted in the event registers (ER/ERH), the event is cleared in two ways. If the
event is enabled in the event enable register (EER/EERH) and the EDMA3CC submits a transfer request
for the event to the EDMA3TC, it clears the corresponding event bit in the event register. If the event is
disabled in the event enable register (EER/EERH), the CPU can clear the event by way of the event clear
registers (ECR/ECRH).
Writing a 1 to any of the bits clears the corresponding event; writing a 0 has no effect. Once an event bit is
set in the event register, it remains set until EDMA3CC submits a transfer request for that event or the
CPU clears the event by setting the corresponding bit in ECR/ECRH.
The ECR is shown in Figure 68 and described in Table 50. The ECRH is shown in Figure 69 and
described in Table 51.
Figure 68. Event Clear Register (ECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 50. Event Clear Register (ECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event clear for event 0-31. Any of the event bits in ECR is set to 1 to clear the event (En) in the event
register (ER). A write of 0 has no effect.
0
No effect.
1
EDMA3CC event is cleared in the event register (ER).
Figure 69. Event Clear Register High (ECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 51. Event Clear Register High (ECRH) Field Descriptions
Bit
31-0
106
Field
Value
En
Description
Event clear for event 32-63. Any of the event bits in ECRH is set to 1 to clear the event (En) in the event
register high (ERH). A write of 0 has no effect.
0
No effect.
1
EDMA3CC event is cleared in the event register high (ERH).
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4.3.5.3
Event Set Registers (ESR, ESRH)
The event set registers (ESR/ESRH) allow the CPU (or EDMA programmers) to manually set events to
initiate DMA transfer requests. CPU writes of 1 to any event set register (En) bits set the corresponding
bits in the registers. The set event is evaluated by the EDMA3CC logic for an associated transfer request
submission to the transfer controllers. Writing a 0 has no effect.
The event set registers operate independent of the event registers (ER/ERH), and a write of 1 is always
considered a valid event regardless of whether the event is enabled (the corresponding event bits are set
or cleared in EER.En/EERH.En).
Once the event is set in the event set registers, it cannot be cleared by CPU writes, in other words, the
event clear registers (ECR/ECRH) have no effect on the state of ESR/ESRH. The bits will only be cleared
once the transfer request corresponding to the event has been submitted to the transfer controller. The
setting of an event is a higher priority relative to clear operations (via hardware). If set and clear conditions
occur concurrently, the set condition wins. If the event was previously set, then EMR/EMRH would be set
since an event is lost. If the event was previously clear, then the event remains set and is prioritized for
submission to the event queues.
Manually-triggered transfers via writes to ESR/ESRH allow the CPU to submit DMA requests in the
system, these are relevant for memory-to-memory transfer scenarios. If the ESR.En/ESRH.En bit is
already set and another CPU write of 1 is attempted to the same bit, then the corresponding event is
latched in the event missed registers (EMR.En/EMRH.En = 1).
The ESR is shown in Figure 70 and described in Table 52. The ESRH is shown in Figure 71 and
described in Table 53.
Figure 70. Event Set Register (ESR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 52. Event Set Register (ESR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event set for event 0-31.
0
No effect.
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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Figure 71. Event Set Register High (ESRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 53. Event Set Register High (ESRH) Field Descriptions
Bit
Field
31-0
Value
En
4.3.5.4
Description
Event set for event 32-63.
0
No effect .
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
Chained Event Registers (CER, CERH)
When the OPTIONS parameter for a PaRAM entry is programmed to returned a chained completion code
(ITCCHEN = 1 and/or TCCHEN = 1), then the value dictated by the TCC[5:0] (also programmed in OPT)
forces the corresponding event bit to be set in the chained event registers (CER/CERH). The set chained
event is evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer
controllers. This results in a chained-triggered transfer.
The chained event registers do not have any enables. The generation of a chained event is essentially
enabled by the PaRAM entry that has been configured for intermediate and/or final chaining on transfer
completion. The En bit is set (regardless of the state of EER.En/EERH.En) when a chained completion
code is returned from one of the transfer controllers or is generated by the EDMA3CC via the early
completion path. The bits in the chained event register are cleared when the corresponding events are
prioritized and serviced.
If the En bit is already set and another chaining completion code is return for the same event, then the
corresponding event is latched in the event missed registers (EMR.En/EMRH.En = 1). The setting of an
event is a higher priority relative to clear operations (via hardware). If set and clear conditions occur
concurrently, the set condition wins. If the event was previously set, then EMR/EMRH would be set since
an event is lost. If the event was previously clear, then the event remains set and is prioritized for
submission to the event queues.
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The CER is shown in Figure 72 and described in Table 54. The CERH is shown in Figure 73 and
described in Table 55.
Figure 72. Chained Event Register (CER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 54. Chained Event Register (CER) Field Descriptions
Bit
31-0
Field
Value
Description
En
Chained event for event 0-31.
0
No effect.
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
Figure 73. Chained Event Register High (CERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 55. Chained Event Register High (CERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Chained event set for event 32-63.
0
No effect.
1
Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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Event Enable Registers (EER, EERH)
The EDMA3CC provides the option of selectively enabling/disabling each event in the event registers
(ER/ERH) by using the event enable registers (EER/EERH). If an event bit in EER/EERH is set to 1 (using
the event enable set registers, EESR/EESRH), it will enable that corresponding event. Alternatively, if an
event bit in EER/EERH is cleared (using the event enable clear registers, EECR/EECRH), it will disable
the corresponding event.
The event registers latch all events that are captured by EDMA3CC, even if the events are disabled
(although EDMA3CC does not process it). Enabling an event with a pending event already set in the event
registers enables the EDMA3CC to process the already set event like any other new event. The
EER/EERH settings do not have any effect on chained events (CER.En/CERH.En = 1) and manually set
events (ESR.En/ESRH.En = 1).
The EER is shown in Figure 74 and described in Table 56. Th EERH is shown in Figure 75 and described
in Table 57.
Figure 74. Event Enable Register (EER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 56. Event Enable Register (EER) Field Descriptions
Bit
31-0
Field
Value
Description
En
Event enable for events 0-31.
0
Event is not enabled. An external event latched in the event register (ER) is not evaluated by the
EDMA3CC.
1
Event is enabled. An external event latched in the event register (ER) is evaluated by the EDMA3CC.
Figure 75. Event Enable Register High (EERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 57. Event Enable Register High (EERH) Field Descriptions
Bit
31-0
110
Field
Value
En
Description
Event enable for events 32-63.
0
Event is not enabled. An external event latched in the event register high (ERH) is not evaluated by the
EDMA3CC.
1
Event is enabled. An external event latched in the event register high (ERH) is evaluated by the
EDMA3CC.
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4.3.5.6
Event Enable Clear Register (EECR, EECRH)
The event enable registers (EER/EERH) cannot be modified by directly writing to them. The intent is to
ease the software burden for the case where multiple tasks are attempting to simultaneously modify these
registers. The event enable clear registers (EECR/EECRH) are used to disable events. Writes of 1 to the
bits in EECR/EECRH clear the corresponding event bits in EER/EERH; writes of 0 have no effect.
The EECR is shown in Figure 76 and described in Table 58. The EECRH is shown in Figure 77 and
described in Table 59.
Figure 76. Event Enable Clear Register (EECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 58. Event Enable Clear Register (EECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable clear for events 0-31.
0
No effect.
1
Event is disabled. Corresponding bit in the event enable register (EER) is cleared (En = 0).
Figure 77. Event Enable Clear Register High (EECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 59. Event Enable Clear Register High (EECRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable clear for events 32-63.
0
No effect.
1
Event is disabled. Corresponding bit in the event enable register high (EERH) is cleared (En = 0).
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Event Enable Set Registers (EESR, EESRH)
The event enable registers (EER/EERH) cannot be modified by directly writing to them. The intent is to
ease the software burden for the case where multiple tasks are attempting to simultaneously modify these
registers. The event enable set registers (EESR/EESRH) are used to enable events. Writes of 1 to the bits
in EESR/EESRH set the corresponding event bits in EER/EERH; writes of 0 have no effect.
The EESR is shown in Figure 78 and described in Table 60. The EESRH is shown in Figure 79 and
described in Table 61.
Figure 78. Event Enable Set Register (EESR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 60. Event Enable Set Register (EESR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Event enable set for events 0-31.
0
No effect.
1
Event is enabled. Corresponding bit in the event enable register (EER) is set (En = 1).
Figure 79. Event Enable Set Register High (EESRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 61. Event Enable Set Register High (EESRH) Field Descriptions
Bit
31-0
112
Field
Value
En
Description
Event enable set for events 32-63.
0
No effect.
1
Event is enabled. Corresponding bit in the event enable register high (EERH) is set (En = 1).
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4.3.5.8
Secondary Event Registers (SER, SERH)
The secondary event registers (SER/SERH) provide information on the state of a DMA channel or event
(0 through 63). If the EDMA3CC receives a TR synchronization due to a manual-trigger, event-trigger, or
chained-trigger source (ESR.En/ESRH.En = 1, ER.En/ERH.En = 1, or CER.En/CERH.En = 1), which
results in the setting of a corresponding event bit in SER/SERH (SER.En/SERH.En = 1), it implies that the
corresponding DMA event is in the queue.
Once a bit corresponding to an event is set in SER/SERH, the EDMA3CC does not prioritize additional
events on the same DMA channel. Depending on the condition that leads to the setting of the SER bits,
either the EDMA3CC hardware or the software (using SECR/SECRH) needs to clear the SER/SERH bits
for the EDMA3CC to evaluate subsequent events and perform subsequent transfers on the same channel.
Based on whether the associated TR is valid, or it is a null or dummy TR, the implications on the state of
SER/SERH and the required user action in order to submit another DMA transfer might be different.
The SER is shown in Figure 80 and described in Table 62. The SERH is shown in Figure 81 and
described in Table 63.
Figure 80. Secondary Event Register (SER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 62. Secondary Event Register (SER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Secondary event register. The secondary event register is used to provide information on the state of an
event.
0
Event is not currently stored in the event queue.
1
Event is currently stored in the event queue. Event arbiter will not prioritize additional events.
Figure 81. Secondary Event Register High (SERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 63. Secondary Event Register High (SERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Secondary event register. The secondary event register is used to provide information on the state of an
event.
0
Event is not currently stored in the event queue.
1
Event is currently stored in the event queue. Event submission/prioritization logic will not prioritize
additional events.
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Secondary Event Clear Registers (SECR, SECRH)
The secondary event clear registers (SECR/SECRH) clear the status of the secondary event registers
(SER/SERH). CPU writes of 1 clear the corresponding set bits in SER/SERH. Writes of 0 have no effect.
The SECR is shown in Figure 82 and described in Table 64. The SECRH is shown in Figure 83 and
described in Table 65.
Figure 82. Secondary Event Clear Register (SECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E31
E30
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E19
E18
E17
E16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 64. Secondary Event Clear Register (SECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Secondary event clear register
0
No effect.
1
Corresponding bit in the secondary event register (SER) is cleared (En = 0).
Figure 83. Secondary Event Clear Register High (SECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
E63
E62
E61
E60
E59
E58
E57
E56
E55
E54
E53
E52
E51
E50
E49
E48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E47
E46
E45
E44
E43
E42
E41
E40
E39
E38
E37
E36
E35
E34
E33
E32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 65. Secondary Event Clear Register High (SECRH) Field Descriptions
Bit
31-0
114
Field
Value
En
Description
Secondary event clear register.
0
No effect.
1
Corresponding bit in the secondary event registers high (SERH) is cleared (En = 0).
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4.3.6
Interrupt Registers
All DMA/QDMA channels can be set to assert an EDMA3CC completion interrupt to the CPU on transfer
completion, by appropriately configuring the PaRAM entry associated with the channels. The following set
of registers is used for the transfer completion interrupt reporting/generating by the EDMA3CC. See
Section 2.9 for more details on EDMA3CC completion interrupt generation.
4.3.6.1
Interrupt Enable Registers (IER, IERH)
Interrupt enable registers (IER/IERH) are used to enable/disable the transfer completion interrupt
generation by the EDMA3CC for all DMA/QDMA channels. The IER/IERH cannot be written to directly. To
set any interrupt bit in IER/IERH, a 1 must be written to the corresponding interrupt bit in the interrupt
enable set registers (IESR/IESRH). Similarly, to clear any interrupt bit in IER/IERH, a 1 must be written to
the corresponding interrupt bit in the interrupt enable clear registers (IECR/IECRH).
The IER is shown in Figure 84 and described in Table 66. The IERH is shown in Figure 85 and described
in Table 67.
Figure 84. Interrupt Enable Register (IER)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27I
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 66. Interrupt Enable Register (IER) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable for channels 0-31.
0
Interrupt is not enabled.
1
Interrupt is enabled.
Figure 85. Interrupt Enable Register High (IERH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 67. Interrupt Enable Register High (IERH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable for channels 32-63.
0
Interrupt is not enabled.
1
Interrupt is enabled.
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Interrupt Enable Clear Register (IECR, IECRH)
The interrupt enable clear registers (IECR/IECRH) are used to clear interrupts. Writes of 1 to the bits in
IECR/IECRH clear the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0
have no effect.
The IECR is shown in Figure 86 and described in Table 68. The IECRH is shown in Figure 87 and
described in Table 69.
Figure 86. Interrupt Enable Clear Register (IECR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
16
16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 68. Interrupt Enable Clear Register (IECR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable clear for channels 0-31.
0
No effect.
1
Corresponding bit in the interrupt enable register (IER) is cleared (In = 0).
Figure 87. Interrupt Enable Clear Register High (IECRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 69. Interrupt Enable Clear Register High (IECRH) Field Descriptions
Bit
31-0
116
Field
Value
En
Description
Interrupt enable clear for channels 32-63.
0
No effect.
1
Corresponding bit in the interrupt enable register high (IERH) is cleared (In = 0).
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4.3.6.3
Interrupt Enable Set Registers (IESR, IESRH)
The interrupt enable set registers (IESR/IESRH) are used to enable interrupts. Writes of 1 to the bits in
IESR/IESRH set the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0
have no effect.
The IESR is shown in Figure 88 and described in Table 70. The IESRH is shown in Figure 89 and
described in Table 71.
Figure 88. Interrupt Enable Set Register (IESR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
II8
I17
I16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 70. Interrupt Enable Set Register (IESR) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable set for channels 0-31.
0
No effect.
1
Corresponding bit in the interrupt enable register (IER) is set (In = 1).
Figure 89. Interrupt Enable Set Register High (IESRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 71. Interrupt Enable Set Register High (IESRH) Field Descriptions
Bit
31-0
Field
Value
En
Description
Interrupt enable set for channels 32-63.
0
No effect.
1
Corresponding bit in the interrupt enable register high (IERH) is set (In = 1).
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Interrupt Pending Register (IPR, IPRH)
If the TCINTEN and/or ITCINTEN bit in the channel option parameter (OPT) is set to 1 in the PaRAM
entry associated with the channel (DMA or QDMA), then the EDMA3TC (for normal completion) or the
EDMA3CC (for early completion) returns a completion code on transfer or intermediate transfer
completion. The value of the returned completion code is equal to the TCC bit in OPT for the PaRAM
entry associated with the channel.
When an interrupt transfer completion code with TCC = n is detected by the EDMA3CC, then the
corresponding bit is set in the interrupt pending register (IPR.In, if n = 0 to 31; IPRH.In, if n = 32 to 63).
Note that once a bit is set in the interrupt pending registers, it remains set; it is your responsibility to clear
these bits. The bits set in IPR/IPRH are cleared by writing a 1 to the corresponding bits in the interrupt
clear registers (ICR/ICRH).
The IPR is shown in Figure 90 and described in Table 72. The IPRH is shown in Figure 91 and described
in Table 73.
Figure 90. Interrupt Pending Register (IPR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 72. Interrupt Pending Register (IPR) Field Descriptions
Bit
31-0
Field
Value
In
Description
Interrupt pending for TCC = 0-31.
0
Interrupt transfer completion code is not detected or was cleared.
1
Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
Figure 91. Interrupt Pending Register High (IPRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 73. Interrupt Pending Register High (IPRH) Field Descriptions
Bit
31-0
118
Field
Value
In
Description
Interrupt pending for TCC = 32-63.
0
Interrupt transfer completion code is not detected or was cleared.
1
Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]).
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4.3.6.5
Interrupt Clear Registers (ICR, ICRH)
The bits in the interrupt pending registers (IPR/IPRH) are cleared by writing a 1 to the corresponding bits
in the interrupt clear registers(ICR/ICRH). Writes of 0 have no effect. All set bits in IPR/IPRH must be
cleared to allow EDMA3CC to assert additional transfer completion interrupts.
The ICR is shown in Figure 92 and described in Table 74. The ICRH is shown in Figure 93 and described
in Table 75.
Figure 92. Interrupt Clear Register (ICR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I31
I30
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 74. Interrupt Clear Register (ICR) Field Descriptions
Bit
31-0
Field
Value
Description
In
Interrupt clear register for TCC = 0-31.
0
No effect.
1
Corresponding bit in the interrupt pending register (IPR) is cleared (In = 0).
Figure 93. Interrupt Clear Register High (ICRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I63
I62
I61
I60
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I49
I48
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I47
I46
I45
I44
I43
I42
I41
I40
I39
I38
I37
I36
I35
I34
I33
I32
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Table 75. Interrupt Clear Register High (ICRH) Field Descriptions
Bit
31-0
Field
Value
In
Description
Interrupt clear register for TCC = 32-63.
0
No effect.
1
Corresponding bit in the interrupt pending register high (IPRH) is cleared (In = 0).
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Interrupt Evaluate Register (IEVAL)
The interrupt evaluate register (IEVAL) is the only register that physically exists in both the global region
and the shadow regions. In other words, the read/write accessibility for the shadow region IEVAL is not
affected by the DMA/QDMA region access registers (DRAEm/DRAEHm, QRAEn/QRAEHn). IEVAL is
needed for robust ISR operations to ensure that interrupts are not missed by the CPU.
The IEVAL is shown in Figure 94 and described in Table 76.
Figure 94. Interrupt Evaluate Register (IEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
2
Rsvd
EVAL
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 76. Interrupt Evaluate Register (IEVAL) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
Reserved
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0
EVAL
Interrupt evaluate.
0
No effect.
1
Causes EDMA3CC completion interrupt to be pulsed, if any enabled (IERn/IERHn = 1) interrupts are
still pending (IPRn/IPRHn = 1).
The EDMA3CC completion region interrupt that is pulsed depends on which IEVAL is being exercised.
For example, writing to the EVAL bit in IEVAL0 pulses the region 0 completion interrupt, but writing to
the EVAL bit in IEVAL1 pulses the region 1 completion interrupt.
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4.3.7
QDMA Registers
The following sets of registers control the QDMA channels in the EDMA3CC. The QDMA channels (with
the exception of the QDMA queue number register) consist of a set of registers, each of which have a bit
location. Each bit position corresponds to a QDMA channel number. The QDMA channel registers are
accessible via read/writes to the global address range. They are also accessible via read/writes to the
shadow address range. The read/write accessibility in the shadow region address region is controlled by
the QDMA region access registers (QRAEn/QRAEHn). Section 2.7 details shadow region/global region
usage.
4.3.7.1
QDMA Event Register (QER)
The QDMA event register (QER) channel n bit is set (En = 1) when the CPU or any EDMA programmer
(including EDMA3) performs a write to the trigger word (using the QDMA channel mapping register
(QCHMAPn)) in the PaRAM entry associated with QDMA channel n (which is also programmed using
QCHMAPn). The En bit is also set when the EDMA3CC performs a link update on a PaRAM address that
matches the QCHMAPn settings. The QDMA event is latched only if the QDMA event enable register
(QEER) channel n bit is also enabled (QEER.En = 1). Once a bit is set in QER, then the corresponding
QDMA event (auto-trigger) is evaluated by the EDMA3CC logic for an associated transfer request
submission to the transfer controllers.
The setting of an event is a higher priority relative to clear operations (via hardware). If set and clear
conditions occur concurrently, the set condition wins. If the event was previously set, then the QDMA
event missed register (QEMR) would be set because an event is lost. If the event was previously clear,
then the event remains set and is prioritized for submission to the event queues.
The set bits in QER are only cleared when the transfer request associated with the corresponding
channels has been processed by the EDMA3CC and submitted to the transfer controller. If the En bit is
already set and a QDMA event for the same QDMA channel occurs prior to the original being cleared,
then the second missed event is latched in QEMR (En =1).
The QER is shown in Figure 95 and described in Table 77.
Figure 95. QDMA Event Register (QER)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 77. QDMA Event Register (QER) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
Value
0
Description
Reserved
QDMA event for channels 0-7.
0
No effect.
1
Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to
the EDMA3TC.
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QDMA Event Enable Register (QEER)
The EDMA3CC provides the option of selectively enabling/disabling each channel in the QDMA event
register (QER) by using the QDMA event enable register (QEER). If any of the event bits in QEER is set
to 1 (using the QDMA event enable set register, QEESR), it will enable that corresponding event.
Alternatively, if any event bit in QEER is cleared (using the QDMA event enable clear register, QEECR), it
will disable the corresponding QDMA channel. The QDMA event register will not latch any event for a
QDMA channel, if it is not enabled via QEER.
The QEER is shown in Figure 96 and described in Table 78.
Figure 96. QDMA Event Enable Register (QEER)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 78. QDMA Event Enable Register (QEER) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
122
Value
0
Description
Reserved
QDMA event enable for channels 0-7.
0
QDMA channel n is not enabled. QDMA event will not be recognized and will not latch in the QDMA
event register (QER).
1
QDMA channel n is enabled. QDMA events will be recognized and will get latched in the QDMA event
register (QER).
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4.3.7.3
QDMA Event Enable Clear Register (QEECR)
The QDMA event enable register (QEER) cannot be modified by directly writing to the register, in order to
ease the software burden when multiple tasks are attempting to simultaneously modify these registers.
The QDMA event enable clear register (QEECR) is used to disable events. Writes of 1 to the bits in
QEECR clear the corresponding QDMA channel bits in QEER; writes of 0 have no effect.
The QEECR is shown in Figure 97 and described in Table 79.
Figure 97. QDMA Event Enable Clear Register (QEECR)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 79. QDMA Event Enable Clear Register (QEECR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
Value
0
Description
Reserved
QDMA event enable clear for channels 0-7.
0
No effect.
1
QDMA event is disabled. Corresponding bit in the QDMA event enable register (QEER) is cleared
(En = 0).
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QDMA Event Enable Set Register (QEESR)
The QDMA event enable register (QEER) cannot be modified by directly writing to the register, in order to
ease the software burden when multiple tasks are attempting to simultaneously modify these registers.
The QDMA event enable set register (QEESR) is used to enable events. Writes of 1 to the bits in QEESR
set the corresponding QDMA channel bits in QEER; writes of 0 have no effect.
The QEESR is shown in Figure 98 and described in Table 80.
Figure 98. QDMA Event Enable Set Register (QEESR)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 80. QDMA Event Enable Set Register (QEESR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
124
Value
0
Description
Reserved
QDMA event enable set for channels 0-7.
0
No effect.
1
QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1).
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4.3.7.5
QDMA Secondary Event Register (QSER)
The QDMA secondary event register (QSER) provides information on the state of a QDMA event. If at any
time a bit corresponding to a QDMA channel is set in QSER, that implies that the corresponding QDMA
event is in the queue. Once a bit corresponding to a QDMA channel is set in QSER, the EDMA3CC does
not prioritize additional events on the same QDMA channel. Depending on the condition that lead to the
setting of the QSER bits, either the EDMA3CC hardware or the software (using QSECR) needs to clear
the QSER bits for the EDMA3CC to evaluate subsequent QDMA events on the channel. Based on
whether the associated TR is valid, or it is a null or dummy TR, the implications on the state of QSER and
the required user action in order to submit another QDMA transfer might be different.
The QSER is shown in Figure 99 and described in Table 81.
Figure 99. QDMA Secondary Event Register (QSER)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 81. QDMA Secondary Event Register (QSER) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
Value
0
Description
Reserved
QDMA secondary event register for channels 0-7.
0
QDMA event is not currently stored in the event queue.
1
QDMA event is currently stored in event queue. EDMA3CC will not prioritize additional events.
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QDMA Secondary Event Clear Register (QSECR)
The QDMA secondary event clear register (QSECR) clears the status of the QDMA secondary event
register (QSER) and the QDMA event register (QER). CPU writes of 1 clear the corresponding set bits in
QSER and QER. Writes of 0 have no effect. Note that this differs from the secondary event clear register
(SECR) operation, which only clears the secondary event register (SER) bits and does not affect the event
registers.
The QSECR is shown in Figure 100 and described in Table 82.
Figure 100. QDMA Secondary Event Clear Register (QSECR)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
8
E7
E6
E5
E4
E3
E2
E1
E0
R-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 82. QDMA Secondary Event Clear Register (QSECR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
En
126
Value
0
Description
Reserved
QDMA secondary event clear register for channels 0-7.
0
No effect.
1
Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER)
is cleared (En = 0).
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4.4
EDMA3 Transfer Controller Control Registers
Table 83 lists the memory-mapped registers for the EDMA3 transfer controller (EDMA3TC). See the
device-specific data manual for the memory address of these registers. All other register offset addresses
not listed in Table 83 should be considered as reserved locations and the register contents should not be
modified. The module base address is 01C1 0000h for EDMA3TC0, 01C1 0400h for EDMA3TC1,
01C1 0800h for EDMA3TC2, and 01C1 0C00h for EDMA3TC3.
Table 83. EDMA3 Transfer Controller Registers
Offset
Acronym
Register Description
0h
PID
Peripheral Identification Register
Section 4.4.1
Section
4h
TCCFG
EDMA3TC Configuration Register
Section 4.4.2
100h
TCSTAT
EDMA3TC Channel Status Register
120h
ERRSTAT
Error Register
Section 4.4.4.1
124h
ERREN
Error Enable Register
Section 4.4.4.2
Section 4.4.3
128h
ERRCLR
Error Clear Register
Section 4.4.4.3
12Ch
ERRDET
Error Details Register
Section 4.4.4.4
130h
ERRCMD
Error Interrupt Command Register
Section 4.4.4.5
140h
RDRATE
Read Rate Register
240h
SAOPT
Source Active Options Register
Section 4.4.6.1
244h
SASRC
Source Active Source Address Register
Section 4.4.6.2
248h
SACNT
Source Active Count Register
Section 4.4.6.3
24Ch
SADST
Source Active Destination Address Register
Section 4.4.6.4
250h
SABIDX
Source Active Source B-Index Register
Section 4.4.6.5
254h
SAMPPRXY
Source Active Memory Protection Proxy Register
Section 4.4.6.6
Section 4.4.5
258h
SACNTRLD
Source Active Count Reload Register
Section 4.4.6.7
25Ch
SASRCBREF
Source Active Source Address B-Reference Register
Section 4.4.6.8
260h
SADSTBREF
Source Active Destination Address B-Reference Register
Section 4.4.6.9
280h
DFCNTRLD
Destination FIFO Set Count Reload
Section 4.4.6.16
284h
DFSRCBREF
Destination FIFO Set Destination Address B Reference Register
Section 4.4.6.17
288h
DFDSTBREF
Destination FIFO Set Destination Address B Reference Register
Section 4.4.6.18
300h
DFOPT0
Destination FIFO Options Register 0
Section 4.4.6.10
304h
DFSRC0
Destination FIFO Source Address Register 0
Section 4.4.6.11
308h
DFCNT0
Destination FIFO Count Register 0
Section 4.4.6.12
30Ch
DFDST0
Destination FIFO Destination Address Register 0
Section 4.4.6.13
310h
DFBIDX0
Destination FIFO BIDX Register 0
Section 4.4.6.14
314h
DFMPPRXY0
Destination FIFO Memory Protection Proxy Register 0
Section 4.4.6.15
340h
DFOPT1
Destination FIFO Options Register 1
Section 4.4.6.10
344h
DFSRC1
Destination FIFO Source Address Register 1
Section 4.4.6.11
348h
DFCNT1
Destination FIFO Count Register 1
Section 4.4.6.12
34Ch
DFDST1
Destination FIFO Destination Address Register 1
Section 4.4.6.13
350h
DFBIDX1
Destination FIFO BIDX Register 1
Section 4.4.6.14
354h
DFMPPRXY1
Destination FIFO Memory Protection Proxy Register 1
Section 4.4.6.15
380h
DFOPT2
Destination FIFO Options Register 2
Section 4.4.6.10
384h
DFSRC2
Destination FIFO Source Address Register 2
Section 4.4.6.11
388h
DFCNT2
Destination FIFO Count Register 2
Section 4.4.6.12
38Ch
DFDST2
Destination FIFO Destination Address Register 2
Section 4.4.6.13
390h
DFBIDX2
Destination FIFO BIDX Register 2
Section 4.4.6.14
394h
DFMPPRXY2
Destination FIFO Memory Protection Proxy Register 2
Section 4.4.6.15
3C0h
DFOPT3
Destination FIFO Options Register 3
Section 4.4.6.10
3C4h
DFSRC3
Destination FIFO Source Address Register 3
Section 4.4.6.11
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Table 83. EDMA3 Transfer Controller Registers (continued)
4.4.1
Offset
Acronym
Register Description
3C8h
DFCNT3
Destination FIFO Count Register 3
Section 4.4.6.12
Section
3CCh
DFDST3
Destination FIFO Destination Address Register 3
Section 4.4.6.13
3D0h
DFBIDX3
Destination FIFO BIDX Register 3
Section 4.4.6.14
3D4h
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
Section 4.4.6.15
Peripheral Identification Register (PID)
The peripheral identification register (PID) is a constant register that uniquely identifies the EDMA3TC and
specific revision of the EDMA3TC. The PID is shown in Figure 101 and described in Table 84.
Figure 101. Peripheral ID Register (PID)
31
16
PID
R-0333h
15
0
PID
R-4425h
LEGEND: R = Read only; -n = value after reset
Table 84. Peripheral ID Register (PID) Field Descriptions
Bit
31-0
Field
Value
PID
Peripheral identifier.
0333 4425h
128
Description
Uniquely identifies the EDMA3TC and the specific revision of the EDMA3TC.
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4.4.2
EDMA3TC Configuration Register (TCCFG)
The EDMA3TC configuration register (TCCFG) is shown in Figure 102 and described in Table 85.
Figure 102. EDMA3TC Configuration Register (TCCFG)
31
16
Reserved
R-0
15
10
9
8
7
6
5
4
3
2
0
Reserved
DREGDEPTH
Reserved
BUSWIDTH
Rsvd
FIFOSIZE
R-0
R-x
R-0
R-x
R-0
R-x
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 85. EDMA3TC Configuration Register (TCCFG) Field Descriptions
Bit
31-10
9-8
Field
Value
Reserved
DREGDEPTH
7-6
Reserved
5-4
BUSWIDTH
0
Description
Reserved
0-3h
Destination register FIFO depth parameterization.
0-1h
Reserved
2h
4 entry (for TC0, TC1, TC2 and TC3)
3h
Reserved
0
Reserved
0-3h
Bus width parameterization.
0
Reserved
1h
64-bit (for TC0, TC1, TC2 and TC3)
2h-3h
Reserved
3
Reserved
0
Reserved
2-0
FIFOSIZE
0-7h
FIFO size.
0-1h
Reserved
2h
Reserved
3h
256 byte FIFO (for TC0, TC1, TC2 and TC3)
4h-7h
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EDMA3TC Channel Status Register (TCSTAT)
The EDMA3TC channel status register (TCSTAT) is shown in Figure 103 and described in Table 86.
Figure 103. EDMA3TC Channel Status Register (TCSTAT)
31
16
Reserved
R-0
15
13
12
11
10
9
8
Reserved
DFSTRTPTR
Reserved
Reserved
R-0
R-0
R-0
R-1
3
2
1
0
Reserved
7
6
DSTACTV
4
Reserved
WSACTV
SRCACTV
PROGBUSY
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 86. EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
Bit
Field
Value
0
Description
31-13
Reserved
12-11
DFSTRTPTR
10-9
Reserved
0
Reserved
8
Reserved
1
Reserved. Always read as 1.
7
Reserved
0
Reserved
6-4
DSTACTV
0-7h
0-3h
Reserved
Destination FIFO start pointer. The offset to the head entry of the destination register FIFO, in units of
*entries*.
Destination active state. Specifies the number of transfer requests (TRs) that are resident in the
destination register FIFO at a given instant. This bit field can be primarily used for advanced debugging.
0
Destination FIFO is empty.
1h
Destination FIFO contains 1 TR.
2h
Destination FIFO contains 2 TR.
3h
Destination FIFO contains 3 TR.
4h
Destination FIFO contains 4 TR. (Full if DSTREGDEPTH == 4)
If the destination register FIFO is empty, then any TR written to Prog Set immediately transitions to the
destination register FIFO. If the destination register FIFO is not empty and not full, then any TR written
to Prog Set immediately transitions to the destination register FIFO set if the source active state
(SRCACTV) bit is set to idle.
If the destination register FIFO is full, then TRs cannot transition to the destination register FIFO. The
destination register FIFO becomes not full when the TR at the head of the destination register FIFO is
completed.
3
Reserved
2
WSACTV
1
0
130
5h-7h
Reserved
0
Reserved
Write status active.
0
Write status is not pending. Write status has been received for all previously issued write commands.
1
Write status is pending. Write status has not been received for all previously issued write commands.
SRCACTV
Source active state.
0
Source controller is idle. Source active register set contains a previously processed transfer request.
1
Source controller is busy servicing a transfer request.
PROGBUSY
Program register set busy.
0
Program set idle and is available for programming by the EDMA3CC.
1
Program set busy.
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4.4.4
Error Registers
4.4.4.1
Error Register (ERRSTAT)
The error status register (ERRSTAT) is shown in Figure 104 and described in Table 87.
Figure 104. Error Register (ERRSTAT)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
MMRAERR
TRERR
Reserved
BUSERR
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 87. Error Register (ERRSTAT) Field Descriptions
Bit
31-4
3
2
Field
Reserved
Value
0
MMRAERR
Reserved
0
BUSERR
Reserved
MMR address error.
0
Condition is not detected
1
User attempted to read or write to an invalid address in configuration memory map.
TRERR
1
Description
Transfer request (TR) error event.
0
Condition is not detected.
1
TR detected that violates constant addressing mode transfer (SAM or DAM is set to 1) alignment rules
or has ACNT or BCNT == 0.
0
Reserved
Bus error event.
0
Condition is not detected.
1
EDMA3TC has detected an error at source or destination address. Error information can be read from
the error details register (ERRDET).
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Error Enable Register (ERREN)
The error enable register (ERREN) is shown in Figure 105 and described in Table 88. When any of the
enable bits in ERREN is set, a bit set in the corresponding error status register (ERRSTAT) causes an
assertion of the EDMA3TC interrupt.
Figure 105. Error Enable Register (ERREN)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
MMRAERR
TRERR
Reserved
BUSERR
R-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 88. Error Enable Register (ERREN) Field Descriptions
Bit
31-4
3
2
132
Field
Reserved
Value
0
MMRAERR
Reserved
0
BUSERR
Reserved
Interrupt enable for MMR address error (MMRAERR).
0
MMRAERR is disabled.
1
MMRAERR is enabled and contributes to the state of EDMA3TC error interrupt generation
TRERR
1
Description
Interrupt enable for transfer request error (TRERR).
0
TRERR is disabled.
1
TRERR is enabled and contributes to the state of EDMA3TC error interrupt generation.
0
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
Interrupt enable for bus error (BUSERR).
0
BUSERR is disabled.
1
BUSERR is enabled and contributes to the state of EDMA3TC error interrupt generation.
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4.4.4.3
Error Clear Register (ERRCLR)
The error clear register (ERRCLR) is shown in Figure 106 and described in Table 89.
Figure 106. Error Clear Register (ERRCLR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
MMRAERR
TRERR
Reserved
BUSERR
R-0
W-0
W-0
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 89. Error Clear Register (ERRCLR) Field Descriptions
Bit
31-4
3
2
Field
Reserved
Value
0
MMRAERR
Reserved
0
BUSERR
Reserved
Interrupt enable clear for the MMRAERR bit in the error status register (ERRSTAT).
0
No effect.
1
Clears the MMRAERR bit in ERRSTAT but does not clear the error details register (ERRDET).
TRERR
1
Description
Interrupt enable clear for the TRERR bit in the error status register (ERRSTAT).
0
No effect.
1
Clears the TRERR bit in ERRSTAT but does not clear the error details register (ERRDET).
0
Reserved
Interrupt clear for the BUSERR bit in the error status register (ERRSTAT).
0
No effect.
1
Clears the BUSERR bit in ERRSTAT and clears the error details register (ERRDET).
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4.4.4.4
Error Details Register (ERRDET)
The error details register (ERRDET) is shown in Figure 107 and described in Table 90.
Figure 107. Error Details Register (ERRDET)
31
18
17
Reserved
R-0
15
14
13
16
TCCHEN
TCINTEN
R-0
8
7
4
R-0
3
0
Reserved
TCC
Reserved
STAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 90. Error Details Register (ERRDET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
17
TCCHEN
0-1
Transfer completion chaining enable. Contains the TCCHEN value in the channel options parameter
(OPT) programmed by the channel controller for the read or write transaction that resulted in an error.
16
TCINTEN
0-1
Transfer completion interrupt enable. Contains the TCINTEN value in the channel options parameter
(OPT) programmed by the channel controller for the read or write transaction that resulted in an error.
15-14
Reserved
0
13 - 8
TCC
7-4
Reserved
3-0
STAT
0-3Fh
0
0-Fh
0
134
Reserved
Reserved
Transfer complete code. Contains the TCC value in the channel options parameter (OPT) programmed
by the channel controller for the read or write transaction that resulted in an error.
Reserved
Transaction status. Stores the nonzero status/error code that was detected on the read status or write
status bus. If read status and write status are returned on the same cycle, then the EDMA3TC chooses
nonzero version. If both are nonzero, then the write status is treated as higher priority.
No error
1h-7h
Read error
8h-Fh
Write error
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4.4.4.5
Error Interrupt Command Register (ERRCMD)
The error command register (ERRCMD) is shown in Figure 108 and described in Table 91.
Figure 108. Error Interrupt Command Register (ERRCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
Rsvd
EVAL
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 91. Error Interrupt Command Register (ERRCMD) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
Reserved
0
Reserved. Writes of 1 to this bit are not supported. Attempts to do so may result in undefined behavior.
0
EVAL
Error evaluate.
0
No effect.
1
EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set to 1.
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Read Rate Register (RDRATE)
The EDMA3 transfer controller issues read commands at a rate controlled by the read rate register
(RDRATE). The RDRATE defines the number of idle cycles that the read controller must wait before
issuing subsequent commands. This applies both to commands within a transfer request packet (TRP)
and for commands that are issued for different transfer requests (TRs). For instance, if RDRATE is set to
4 cycles between reads, there are 3 inactive cycles between reads.
RDRATE allows flexibility in transfer controller access requests to an endpoint. For an application,
RDRATE can be manipulated to slow down the access rate, so that the endpoint may service requests
from other masters during the inactive EDMA3TC cycles.
The RDRATE is shown in Figure 109 and described in Table 92.
NOTE: It is expected that the RDRATE value for a transfer controller is static, as it is decided based
on the application requirement. It is not recommended to change this setting on the fly.
Figure 109. Read Rate Register (RDRATE)
31
16
Reserved
R-0
15
3
2
0
Reserved
RDRATE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 92. Read Rate Register (RDRATE) Field Descriptions
Bit
Field
Value
31-3
Reserved
0
2-0
RDRATE
0-7h
Reserved
Read rate. Controls the number of cycles between read commands. This is a global setting that applies
to all TRs for this EDMA3TC.
0
Reads issued as fast as possible.
1h
4 cycles between reads.
2h
8 cycles between reads.
3h
16 cycles between reads.
4h
32 cycles between reads.
5h-7h
4.4.6
Description
Reserved
EDMA3TC Channel Registers
The EDMA3TC channel registers are split into three parts: the programming registers, the source active
registers, and the destination FIFO register. This section describes the registers and their functions. The
program register set is programmed by the channel controller, and is for internal use. The other two sets
are read-only and provided to facilitate advanced debug capabilities. The number of destination FIFO
register sets depends on the destination FIFO depth.
Both TC0 and TC1 have a destination FIFO depth of 4, and there are four sets of destination FIFO
registers. The number of destination FIFO register sets depends on the destination FIFO depth.
136
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4.4.6.1
Source Active Options Register (SAOPT)
The source active options register (SAOPT) is shown in Figure 110 and described in Table 93.
Figure 110. Source Active Options Register (SAOPT)
31
23
15
22
21
20
Reserved
TCCHEN
Rsvd
TCINTEN
Reserved
TCC
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
12
11
10
8
7
6
4
19
18
3
17
2
TCC
Rsvd
FWID
Rsvd
PRI
Reserved
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
16
1
0
DAM
SAM
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 93. Source Active Options Register (SAOPT) Field Descriptions
Bit
Field
31-23
Reserved
22
TCCHEN
21
Reserved
20
TCINTEN
19-18
Reserved
17-12
TCC
11
10-8
7
6-4
Reserved
FWID
Reserved
PRI
Value
0
0
Transfer complete chaining is disabled.
1
Transfer complete chaining is enabled.
0
Reserved
Transfer complete interrupt enable.
0
Transfer complete interrupt is disabled.
1
Transfer complete interrupt is enabled.
0
Reserved
0-3Fh
0
0-7h
1
0
Transfer complete code. This 6-bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC
module.
Reserved
FIFO width. Applies if either SAM or DAM is set to constant addressing mode.
0
FIFO width is 8 bits.
1h
FIFO width is 16 bits.
2h
FIFO width is 32 bits.
3h
FIFO width is 64 bits.
4h
FIFO width is 128 bits.
5h
FIFO width is 256 bits.
6h-7h
Reserved
0
Reserved
0-7h
1h-6h
Reserved
Reserved
Transfer complete chaining enable.
0
3-2
Description
Transfer priority. Reflects the values programmed in the QUEPRI register in the EDMACC.
Priority 0 - Highest priority
Priority 1 to priority 6
7h
Priority 7 - Lowest priority
0
Reserved
DAM
Destination address mode within an array.
0
Increment (INCR) mode. Destination addressing within an array increments.
1
Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
SAM
Source address mode within an array.
0
Increment (INCR) mode. Source addressing within an array increments.
1
Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
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Source Active Source Address Register (SASRC)
The source active source address register (SASRC) is shown in Figure 111 and described in Table 94.
Figure 111. Source Active Source Address Register (SASRC)
31
16
SADDR
R-0
15
0
SADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 94. Source Active Source Address Register (SASRC) Field Descriptions
Bit
Field
31-0
SADDR
4.4.6.3
Value
Description
0-FFFF FFFFh
Source address for program register set. EDMA3TC updates value according to source
addressing mode (SAM bit in the source active options register, SAOPT) .
Source Active Count Register (SACNT)
The source active count register (SACNT) is shown in Figure 112 and described in Table 95.
Figure 112. Source Active Count Register (SACNT)
31
16
BCNT
R-0
15
0
ACNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 95. Source Active Count Register (SACNT) Field Descriptions
Bit
Field
31-16
BCNT
0-FFFFh B dimension count. Number of arrays to be transferred, where each array is ACNT in length. It is
decremented after each read command appropriately. Represents the amount of data remaining to be
read. It should be 0 when transfer request (TR) is complete.
15-0
ACNT
0-FFFFh A dimension count. Number of bytes to be transferred in first dimension. It is decremented after each read
command appropriately. Represents the amount of data remaining to be read. It should be 0 when
transfer request (TR) is complete.
138
Value
Description
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4.4.6.4
Source Active Destination Address Register (SADST)
The source active destination address register (SADST) is shown in Figure 113 and described in
Table 96.
Figure 113. Source Active Destination Address Register (SADST)
31
16
DADDR
R-0
15
0
DADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 96. Source Active Destination Address Register (SADST) Field Descriptions
Bit
Field
31-0
DADDR
4.4.6.5
Value
Description
0
Always reads as 0
Source Active Source B-Dimension Index Register (SABIDX)
The source active set B-dimension index register (SABIDX) is shown in Figure 114 and described in
Table 97.
Figure 114. Source Active Source B-Dimension Index Register (SABIDX)
31
16
DSTBIDX
R-0
15
0
SRCBIDX
R-0
LEGEND: R = Read only; -n = value after reset
Table 97. Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions
Bit
Field
Value
31-16
DSTBIDX
0
15-0
SRCBIDX
0-FFFFh
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B-Index offset between destination arrays. Represents the offset in bytes between the starting
address of each destination. Always reads as 0.
B-Index offset between source arrays. Represents the offset in bytes between the starting address
of each source array.
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Source Active Memory Protection Proxy Register (SAMPPRXY)
The source active memory protection proxy register (SAMPPRXY) is shown in Figure 115 and described
in Table 98.
Figure 115. Source Active Memory Protection Proxy Register (SAMPPRXY)
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
PRIV
Reserved
PRIVID
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 98. Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions
Bit
31-9
8
Field
Reserved
Value
0
PRIV
Description
Reserved
Privilege level. The privilege level used by the host to set up the parameter entry in the channel
controller. This field is set up when the associated TR is submitted to the EDMA3TC.
The privilege ID is used while issuing read and write command to the target endpoints so that the target
endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA
transaction.
7-4
Reserved
3-0
PRIVID
0
User-level privilege
1
Supervisor-level privilege
0
Reserved
0-Fh
Privilege ID. This contains the privilege ID of the host that set up the parameter entry in the channel
controller. This field is set up when the associated TR is submitted to the EDMA3TC.
This PRIVID value is used while issuing read and write commands to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIVID of the host that set up
the DMA transaction.
140
0
For any other master that sets up the PaRAM entry.
1
If DSP sets up the PaRAM entry.
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4.4.6.7
Source Active Count Reload Register (SACNTRLD)
The source active count reload register (SACNTRLD) is shown in Figure 116 and described in Table 99.
Figure 116. Source Active Count Reload Register (SACNTRLD)
31
16
Reserved
R-0
15
0
ACNTRLD
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 99. Source Active Count Reload Register (SACNTRLD) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-0
ACNTRLD
0-FFFFh
4.4.6.8
Description
Reserved
A-count reload value. Represents the originally programmed value of ACNT. The reload value is
used to reinitialize ACNT after each array is serviced.
Source Active Source Address B-Reference Register (SASRCBREF)
The source active source address B-reference register (SASRCBREF) is shown in Figure 117 and
described in Table 100.
Figure 117. Source Active Source Address B-Reference Register (SASRCBREF)
31
16
SADDRBREF
R-0
15
0
SADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 100. Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
Bit
31-0
Field
SADDRBREF
Value
0-FFFF FFFFh
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Source address B-reference. Represents the starting address for the array currently being
read.
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Source Active Destination Address B-Reference Register (SADSTBREF)
The source active destination address B-reference register (SADSTBREF) is shown in Figure 118 and
described in Table 101.
Figure 118. Source Active Destination Address B-Reference Register (SADSTBREF)
31
16
DADDRBREF
R-0
15
0
DADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 101. Source Active Destination Address B-Reference Register (SADSTBREF)
Field Descriptions
Bit
31-0
142
Field
DADDRBREF
Value
0
Description
Always reads as 0
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4.4.6.10
Destination FIFO Options Register (DFOPTn)
The destination FIFO options register (DFOPTn) is shown in Figure 119 and described in Table 102.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 119. Destination FIFO Options Register (DFOPTn)
31
23
15
22
21
20
Reserved
TCCHEN
Rsvd
TCINTEN
Reserved
TCC
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
12
11
10
8
7
6
4
19
18
3
2
TCC
Rsvd
FWID
Rsvd
PRI
Reserved
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
17
16
1
0
DAM
SAM
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 102. Destination FIFO Options Register (DFOPTn) Field Descriptions
Bit
Field
31-23
Reserved
22
TCCHEN
21
Reserved
20
TCINTEN
19-18
Reserved
17-12
TCC
11
10-8
7
6-4
Reserved
FWID
Reserved
PRI
Value
0
Transfer complete chaining enable.
Transfer complete chaining is disabled.
1
Transfer complete chaining is enabled.
0
Reserved
Transfer complete interrupt enable.
0
Transfer complete interrupt is disabled.
1
Transfer complete interrupt is enabled.
0
Reserved
0-3Fh
0
0-7h
1
Transfer complete code. This 6-bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC
module.
Reserved
FIFO width. Applies if either SAM or DAM is set to constant addressing mode.
0
FIFO width is 8 bits.
1h
FIFO width is 16 bits.
2h
FIFO width is 32 bits.
3h
FIFO width is 64 bits.
4h
FIFO width is 128 bits.
5h
FIFO width is 256 bits.
6h-7h
Reserved
0
Reserved
0-7h
1h-6h
Reserved
Reserved
0
0
3-2
Description
Transfer priority.
Priority 0 - Highest priority
Priority 1 to priority 6
7h
Priority 7 - Lowest priority
0
Reserved
DAM
Destination address mode within an array.
0
Increment (INCR) mode. Destination addressing within an array increments.
1
Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
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Table 102. Destination FIFO Options Register (DFOPTn) Field Descriptions (continued)
Bit
Field
0
SAM
4.4.6.11
Value
Description
Source address mode within an array.
0
Increment (INCR) mode. Source addressing within an array increments.
1
Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
Destination FIFO Source Address Register (DFSRCn)
The destination FIFO source address register (DFSRCn) is shown in Figure 120 and described in
Table 103.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 120. Destination FIFO Source Address Register (DFSRCn)
31
16
SADDR
R-0
15
0
SADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 103. Destination FIFO Source Address Register (DFSRCn) Field Descriptions
Bit
31-0
144
Field
SADDR
Value
0
Description
Always read as 0.
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4.4.6.12
Destination FIFO Count Register (DFCNTn)
The destination FIFO count register (DFCNTn) is shown in Figure 121 and described in Table 104.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 121. Destination FIFO Count Register (DFCNTn)
31
16
BCNT
R-0
15
0
ACNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 104. Destination FIFO Count Register (DFCNTn) Field Descriptions
Bit
Field
Value
31-16
BCNT
0-FFFFh B-dimension count. Number of arrays to be transferred, where each array is ACNT in length. Count/count
remaining for destination register set. Represents the amount of data remaining to be written.
15-0
ACNT
0-FFFFh A-dimension count. Number of bytes to be transferred in first dimension count/count remaining for
destination register set. Represents the amount of data remaining to be written.
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Destination FIFO Destination Address Register (DFDSTn)
The destination FIFO destination address register (DFDSTn) is shown in Figure 122 and described in
Table 105.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 122. Destination FIFO Destination Address Register (DFDSTn)
31
16
DADDR
R-0
15
0
DADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 105. Destination FIFO Destination Address Register (DFDSTn) Field Descriptions
Bit
Field
31-0
DADDR
4.4.6.14
Value
Description
0
Destination address for the destination FIFO register set. When a transfer request (TR) is complete, the
final value should be the address of the last write command issued.
Destination FIFO B-Index Register (DFBIDXn)
The destination FIFO B-index register (DFBIDXn) is shown in Figure 123 and described in Table 106.
NOTE:
The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 123. Destination FIFO B-Index Register (DFBIDXn)
31
16
DSTBIDX
R-0
15
0
SRCBIDX
R-0
LEGEND: R = Read only; -n = value after reset
Table 106. Destination FIFO B-Index Register (DFBIDXn) Field Descriptions
Bit
Field
Value
31-16
DSTBIDX
0-FFFFh
15-0
SRCBIDX
0
146
Description
B-Index offset between destination arrays. Represents the offset in bytes between the starting
address of each destination.
Always read as 0.
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4.4.6.15
Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
The destination FIFO memory protection proxy register (DFMPPRXYn) is shown in Figure 124 and
described in Table 107.
Figure 124. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
PRIV
Reserved
PRIVID
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 107. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field Descriptions
Bit
31-9
8
Field
Reserved
Value
0
PRIV
Description
Reserved
Privilege level. This contains the privilege level used by the EDMA programmer to set up the parameter
entry in the channel controller. This field is set up when the associated TR is submitted to the
EDMA3TC.
The privilege ID is used while issuing read and write command to the target endpoints so that the target
endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA
transaction.
7-4
Reserved
3-0
PRIVID
0
User-level privilege
1
Supervisor-level privilege
0
Reserved
0-Fh
Privilege ID. This contains the Privilege ID of the EDMA programmer that set up the parameter entry in
the channel controller. This field is set up when the associated TR is submitted to the EDMA3TC.
This PRIVID value is used while issuing read and write commands to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIVID of the host that set up
the DMA transaction.
0
For any other master that sets up the PaRAM entry
1
If DSP sets up the PaRAM entry
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Destination FIFO Count Reload Register (DFCNTRLDn)
The destination FIFO count reload register (DFCNTRLDn) is shown in Figure 125 and described in
Table 108.
Figure 125. Destination FIFO Count Reload Register (DFCNTRLDn)
31
16
Reserved
R-0
15
0
ACNTRLD
R-0
LEGEND: R = Read only; -n = value after reset
Table 108. Destination FIFO Count Reload Register (DFCNTRLDn) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-0
ACNTRLD
0-FFFFh
4.4.6.17
Reserved
A-count reload value. Represents the originally programmed value of ACNT. The reload value is
used to reinitialize ACNT after each array is serviced.
Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
The destination FIFO source address B-reference register (DFSRCBREFn) is shown in Figure 126 and
described in Table 109.
Figure 126. Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
31
16
SADDRBREF
R-0
15
0
SADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 109. Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
Field Descriptions
Bit
31-0
148
Field
SADDRBREF
Value
0
Description
Not applicable. Always read as 0.
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4.4.6.18
Destination FIFO Destination Address B-Reference (DFDSTBREFn)
The destination FIFO destination address B-reference register (DFDSTBREFn) is shown in Figure 127
and described in Table 110.
Figure 127. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn)
31
16
DADDRBREF
R-0
15
0
DADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 110. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn)
Field Descriptions
Bit
31-0
Field
DADDRBREF
Value
0-FFFF FFFFh
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Description
Destination address reference for the destination FIFO register set. Represents the starting
address for the array currently being written.
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Appendix A Tips
A.1
Debug Checklist
This section lists some tips to keep in mind while debugging applications using the EDMA3. Table 111
provides some common issues and their probable causes and resolutions.
Table 111. Debug List
Issue
Description/Solution
The transfer associated with the channel
does not happen. The channel does not
get serviced.
The EDMA3 channel controller (EDMA3CC) may not service a transfer request, even
though the associated PaRAM set is programmed appropriately. Check for the
following:
1) Verify that events are enabled, that is, if an external/peripheral event is latched in
the event registers (ER/ERH), make sure that the event is enabled in the event enable
registers (EER/EERH). Similarly for QDMA channels, make sure that QDMA events are
appropriately enabled in the QDMA event enable register (QEER).
2) Verify that the DMA or QDMA secondary event register (SER/SERH/QSERH) bits
corresponding to the particular event or channel are not set.
The secondary event register bits are set,
not allowing additional transfers to occur
on a channel.
It is possible that a trigger event was received when the parameter set associated with
the channel/event was a NULL set for a previous transfer on the channel. This is
typical in two cases:
1) QDMA channels: Typically if the parameter set is nonstatic and expected to be
terminated by a NULL set (OPT.STATIC = 0, LINK = FFFFh), the parameter set is
updated with a NULL set after submission of the last TR. Because QDMA channels are
autotriggered, this update caused the generation of an event. An event generated for a
NULL set causes an error condition and results in setting the bits corresponding to the
QDMA channel in QEMR and QSER. This will disable further prioritization of the
channel.
2) DMA channels used in a continuous mode: The peripheral may be set up to
continuously generate infinite events (for instance, in case of the ASP, every time the
data shifts out from the DXR register, it generates an XEVT). The parameter set may
be programmed to expect only a finite number of events and to be terminated by a
NULL link. After the expected number of events, the parameter set is reloaded with a
NULL parameter set. Because the peripheral will generate additional events, an error
condition is set in SER.En and EMR.En, preventing further event prioritization.
You must ensure that the number of events received is limited to the expected number
of events for which the parameter set is programmed, or you must ensure that bits
corresponding to a particular channel or event are not set in the secondary event
registers (SER/SERH/QSER) and the event missed registers (EMR/EMRH/QEMR)
before trying to perform subsequent transfers for the event/channel.
Completion interrupts are not asserted, or You must ensure the following:
no further interrupts are received after the 1) The interrupt generation is enabled in the OPT of the associated PaRAM set
first completion interrupt.
(TCINTEN = 1 and/or ITCINTEN = 1).
2) The interrupts are enabled in the EDMA3 channel controller (EDMA3CC), via the
interrupt enable registers (IER/IERH).
3) The corresponding interrupts are enabled in the device interrupt controller.
4) The set interrupts are cleared in the interrupt pending registers (IPR/IPRH) before
exiting the transfer completion interrupt service routine (ISR). See Section 2.9.1.2 for
details on writing EDMA3 ISRs.
5) If working with shadow region interrupts, make sure that the DMA region access
enable registers (DRAE/DRAEH) are set up properly, because DRAE/DRAEH act as
secondary enables for shadow region completion interrupts, along with IER/IERH.
If working with shadow region interrupts, make sure that the bits corresponding to the
transfer completion code (TCC) value are also enabled in DRAE/DRAEH. For instance,
if the PaRAM set associated with channel 0 returns a completion code of 63 (OPT.TCC
= 63), make sure that DRAEH.E63 is also set for a shadow region completion interrupt
because the interrupt pending register bit set will be IPRH.I63 (not IPR.I0).
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A.2
Miscellaneous Programming/Debug Tips
1. For several registers, the setting and clearing of bits needs to be done via separate dedicated
registers. For example, the event register (ER/ERH) bits can only be cleared by writing a 1 to the
corresponding bits in the event clear registers (ECR/ECRH). Similarly, the event enable register
(EER/EERH) bits can only be set with writes of 1 to the corresponding bits in the event enable set
registers (EESR/EESRH) and can only be cleared with writes of 1 to the corresponding bits in the
event enable clear registers (EECR/EECRH).
2. Writes to the shadow region memory maps are governed by region access enable registers
(DRAE/DRAEH/QRAE). If the appropriate channels are not enabled in these registers, read/write
access to the shadow region memory map is not enabled.
3. When working with shadow region completion interrupts, ensure that the DMA region access enable
registers (DRAE/DRAEH) for every region are set in a mutually exclusive way (unless it is a
requirement for an application). If there is an overlap in the allocated channels and transfer completion
codes (setting of interrupt pending register bits) in the region resource allocation, it results in multiple
shadow region completion interrupts. For example, if DRAE0.E0 and DRAE1.E0 are both set, then on
completion of a transfer that returns a TCC = 0, they will generate both shadow region 0 and 1
completion interrupts.
4. While programming a non-dummy parameter set, ensure the CCNT is not left to zero.
5. Enable the EDMA3CC error interrupt in the device controller and attach an interrupt service routine
(ISR) to ensure that error conditions are not missed in an application and are appropriately addressed
with the ISR.
6. Depending on the application, you may want to break large transfers into smaller transfers and use
self-chaining to prevent starvation of other events in an event queue.
7. In applications where a large transfer is broken into sets of small transfers using chaining or other
methods, you might choose to use the early chaining option to reduce the time between the sets of
transfers and increase the throughput. However, keep in mind that with early completion, all data might
have not been received at the end point when completion is reported because the EDMA3CC internally
signals completion when the TR is submitted to the EDMA3TC, potentially before any data has been
transferred.
8. The event queue entries can be observed to determine the last few events if there is a system failure
(provided the entries were not bypassed).
9. In order to put the EDMA3CC and EDMA3TC in power-down modes, you should ensure that there is
no activity with the EDMA3CC and EDMA3TC. The EDMA3CC status register (CCSTAT) and the
EDMA3TC channel status register (TCSTAT) should be used.
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Appendix B Setting Up a Transfer
The following list provides a quick guide for the typical steps involved in setting up a transfer.
1. Initiating a DMA/QDMA channel:
(a) Determine the type of channel (QDMA or DMA) to be used.
(b) If using a QDMA channel, program the QDMA channel n mapping register (QCHMAPn) with the
parameter set number to which the channel maps and the trigger word.
(c) If the channel is being used in the context of a shadow region, ensure the DMA region access
enable registers (DRAE/DRAEH) for the region is properly set up to allow read/write accesses to
bits in the event registers and interrupt registers in the shadow region memory map. The
subsequent steps in this process should be done using the respective shadow region registers.
(Shadow region descriptions and usage are provided in Section 2.7.1.)
(d) Determine the type of triggering used.
(i) If external events are used for triggering (DMA channels), enable the respective event in
EER/EERH by writing into EESR/EESRH.
(ii) If a QDMA channel is used, enable the channel in QEER by writing into QEESR.
(e) Queue setup.
(i) If a QDMA channel is used, set up QDMAQNUM to map the channel to the respective event
queue.
(ii) If a DMA channel is used, set up DMAQNUM to map the event to the respective event queue.
2. Parameter set setup: Program the PaRAM set number associated with the channel. Note that if it is a
QDMA channel, the PaRAM entry that is configured as trigger word is written last. Alternatively, enable
the QDMA channel just before the write to the trigger word.
See Section 3 for parameter set field setups for different types of transfers. See the sections on
chaining (Section 2.8) and interrupt completion (Section 2.9) on how to set up final/intermediate
completion chaining and/or interrupts.
3. Interrupt setup:
(a) If working in the context of a shadow region, ensure the relevant bits in DRAE/DRAEH are set.
(b) Enable the interrupt in IER/IERH by writing into IESR/IESRH.
(c) Ensure that the EDMA3CC completion interrupt is enabled properly in the device interrupt
controller.
(d) Set up the interrupt controller properly to receive the expected EDMA3 interrupt.
4. Initiate transfer (this step is highly dependent on the event trigger source):
(a) If the source is an external event coming from a peripheral, the peripheral will be enabled to start
generating relevant EDMA3 events that can be latched to the ER transfer.
(b) For QDMA events, writes to the trigger word will initiate the transfer.
(c) Manually-triggered transfers will be initiated by writes to the event set registers (ESR/ESRH).
(d) Chained-trigger events initiate when a previous transfer returns a transfer completion code equal to
the chained channel number.
5. Wait for completion:
(a) If the interrupts are enabled as mentioned in step 3, then the EDMA3CC generates a completion
interrupt to the CPU whenever transfer completion results in setting the corresponding bits in the
interrupt pending register (IPR/IPRH). The set bits must be cleared in IPR\IPRH by writing to the
corresponding bit in ICR\ICRH.
(b) If polling for completion (interrupts not enabled in the device controller), then the application code
can wait on the expected bits to be set in IPR\IPRH. Again, the set bits in IPR\IPRH must be
manually cleared by writing to ICR\ICRH before the next set of transfers is performed for the same
transfer completion code values.
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Appendix C Revision History
Table 112 lists the changes made since the previous version of this document.
Table 112. Document Revision History
Reference
Section 4.3.1.7
Additions/Modifications/Deletions
Added Caution.
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microcontroller.ti.com
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www.ti.com/lprf
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