Texas Instruments | TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference (Rev. B) | User Guides | Texas Instruments TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference (Rev. B) User guides

Texas Instruments TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference (Rev. B) User guides
TMS320C6474 DSP
Viterbi-Decoder Coprocessor 2 (VCP2)
User's Guide
Literature Number: SPRUG20B
October 2008 – Revised December 2009
2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Preface ....................................................................................................................................... 6
1
Features ............................................................................................................................. 7
2
Introduction ........................................................................................................................ 8
3
Overview .......................................................................................................................... 10
4
Input Data ......................................................................................................................... 11
..........................................................................................
4.2
Soft Input Dynamic Ranges ..........................................................................................
5
Decision Data ....................................................................................................................
6
Registers ..........................................................................................................................
6.1
VCP2 Input Configuration Register 0 (VCPIC0) ...................................................................
6.2
VCP2 Input Configuration Register 1 (VCPIC1) ...................................................................
6.3
VCP2 Input Configuration Register 2 (VCPIC2) ...................................................................
6.4
VCP2 Input Configuration Register 3 (VCPIC3) ...................................................................
6.5
VCP2 Input Configuration Register 4 (VCPIC4) ...................................................................
6.6
VCP2 Input Configuration Register 5 (VCPIC5) ...................................................................
6.7
VCP2 Output Register 0 (VCPOUT0) ...............................................................................
6.8
VCP2 Output Register 1 (VCPOUT1) ...............................................................................
6.9
VCP2 Execution Register (VCPEXE) ...............................................................................
6.10 VCP2 Endian Mode Register (VCPEND) ...........................................................................
6.11 VCP2 Status Register 0 (VCPSTAT0) ..............................................................................
6.12 VCP2 Status Register 1 (VCPSTAT1) ..............................................................................
6.13 VCP2 Error Register (VCPERR) .....................................................................................
6.14 VCP2 Emulation Control Register (VCPEMU) .....................................................................
7
Endianness .......................................................................................................................
7.1
Branch Metrics .........................................................................................................
8
Architecture ......................................................................................................................
8.1
Sliding-Windows Processing .........................................................................................
8.2
Yamamoto Parameters ................................................................................................
8.3
Input FIFO (Branch Metrics) ..........................................................................................
8.4
Output FIFO (Decisions) ..............................................................................................
9
Programming ....................................................................................................................
9.1
EDMA3 Resources ....................................................................................................
9.2
Input Configuration Words ............................................................................................
10
Output Parameters ............................................................................................................
11
Event Generation ...............................................................................................................
11.1 VCPXEVT Generation .................................................................................................
11.2 VCPREVT Generation ................................................................................................
12
Operational Modes ............................................................................................................
12.1 Debugging Features ...................................................................................................
13
Errors and Status ..............................................................................................................
Appendix A Revision History ......................................................................................................
4.1
Branch Metrics Calculations
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Table of Contents
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
30
30
33
33
36
36
37
39
39
43
43
44
44
44
45
45
46
47
3
www.ti.com
List of Figures
1
Convolutional Encoder Example Block Diagram........................................................................ 8
2
Trellis Diagram for Convolutional Encoder Example ................................................................... 9
3
VCP2 Block Diagram...................................................................................................... 10
4
VCP2 Input Configuration Register 0 (VCPIC0) ....................................................................... 15
5
VCP2 Input Configuration Register 1 (VCPIC1) ....................................................................... 16
6
VCP2 Input Configuration Register 2 (VCPIC2) ....................................................................... 17
7
VCP2 Input Configuration Register 3 (VCPIC3) ....................................................................... 18
8
VCP2 Input Configuration Register 4 (VCPIC4) ....................................................................... 19
9
VCP2 Input Configuration Register 5 (VCPIC5) ....................................................................... 20
10
VCP2 Output Register 0 (VCPOUT0)
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
4
..................................................................................
VCP2 Output Register 1 (VCPOUT1) ..................................................................................
VCP2 Execution Register (VCPEXE) ...................................................................................
VCP2 Endian Mode Register (VCPEND) ..............................................................................
VCP2 Status Register 0 (VCPSTAT0) ..................................................................................
VCP2 Status Register 1 (VCPSTAT1) ..................................................................................
VCP2 Error Register (VCPERR) ........................................................................................
VCP2 Emulation Control Register (VCPEMU) .........................................................................
Data Source - VBUSP/DMA (BM = 1) ..................................................................................
Data Destination - Kernel for Processing Unit (BM = 1)..............................................................
Data Source - VBUSP/DMA (BM = 0) ..................................................................................
Data Destination - Kernel for Processing Unit (BM = 0)..............................................................
Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) ....................................
Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ....................................
Processing Unit ............................................................................................................
Tailed Traceback Mode ...................................................................................................
Mixed Traceback Mode-Example With Five Sliding Windows .......................................................
Convergent Traceback Mode-Example With Five Sliding Windows ................................................
Input FIFO (Branch Metrics) .............................................................................................
Output FIFO (Decisions Data) ...........................................................................................
EDMA3 Parameters Structure ...........................................................................................
List of Figures
21
22
23
24
25
26
27
29
30
30
31
31
32
32
33
33
34
34
37
38
39
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
www.ti.com
List of Tables
1
Branch Metrics for Rate 1/2 .............................................................................................. 11
2
Branch Metrics for Rate 1/3 .............................................................................................. 12
3
Branch Metrics for Rate 1/4 .............................................................................................. 12
4
VCP2 Soft Inputs Quantization .......................................................................................... 12
5
VCP2 Registers ............................................................................................................ 14
6
VCP2 Memories ........................................................................................................... 14
7
VCP2 Input Configuration Register 0 (VCPIC0) Field Descriptions
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
................................................
VCP2 Input Configuration Register 1 (VCPIC1) Field Descriptions ................................................
VCP2 Input Configuration Register 2 (VCPIC2) Field Descriptions ................................................
VCP2 Input Configuration Register 3 (VCPIC3) Field Descriptions ................................................
VCP2 Input Configuration Register 4 (VCPIC4) Field Descriptions ................................................
VCP2 Input Configuration Register 5 (VCPIC5) Field Descriptions ................................................
VCP2 Output Register 0 (VCPOUT0) Field Descriptions ............................................................
VCP2 Output Register 1 (VCPOUT1) Field Descriptions ............................................................
VCP2 Execution Register (VCPEXE) Field Descriptions.............................................................
VCP2 Endian Mode Register (VCPEND) Field Descriptions ........................................................
VCP2 Status Register 0 (VCPSTAT0) Field Descriptions ...........................................................
VCP2 Status Register 1 (VCPSTAT1) Field Descriptions ...........................................................
VCP2 Error Register (VCPERR) Field Descriptions ..................................................................
VCP2 Emulation Control Register (VCPEMU) Field Descriptions ..................................................
Branch Metrics .............................................................................................................
Branch Metrics in DSP Memory (BM = 1) ..............................................................................
Branch Metrics in DSP Memory (BM = 0) ..............................................................................
Soft Decision Organization ...............................................................................................
Traceback Soft Decision Sliding Window Limits ......................................................................
Traceback Hard Decision Sliding Window Limits .....................................................................
Code Rate versus SYMX .................................................................................................
Required EDMA3 Links Per User Channel ............................................................................
C6474 Revision History ...................................................................................................
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
List of Tables
15
16
17
18
19
20
21
22
23
24
25
26
27
29
30
30
31
32
35
35
36
39
47
5
Preface
SPRUG20B – October 2008 – Revised December 2009
Read This First
About This Manual
Channel decoding of voice and low bit-rate data channels found in third generation (3G) cellular standards
requires decoding of convolutional encoded data. The Viterbi-decoder coprocessor 2 (VCP2) provided in
the C6474 devices has been designed to perform Viterbi decoding for IS2000 and 3GPP wireless
standards. The VCP2 coprocessor has been designed to perform forward-error correction for 2G and 3G
wireless systems. The VCP2 coprocessor offers a very cost effective and synergistic solution when
combined with Texas Instruments (TI) DSPs. The VCP2 supports 1941 12.2 Kbps class A 3G voice
channels running at 333 MHz. This document describes the operation and programming of the VCP2.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
• The term "word" describes a 32-bit value.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors
(DSPs).
SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for
the TMS320C6000™ DSPs and includes application program examples.
SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™
integrated development environment and software tools.
SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.
Describes the Code Composer Studio™ application programming interface (API), which allows you
to program custom plug-ins for Code Composer.
SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal
processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6
Preface
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
User's Guide
SPRUG20B – October 2008 – Revised December 2009
TMS320C6474 Viterbi-Decoder Coprocessor 2
Channel decoding of voice and low bit-rate data channels found in cellular standards such as 2.5G, 3G,
and WiMAX requires the decoding of convolutional encoded data. The Viterbi-decoder coprocessor 2
(VCP2) provided in the C6474 devices performs Viterbi decoding for IS2000 and 3GPP wireless
standards. The VCP2 coprocessor also performs forward-error correction for 2G and 3G wireless systems.
The VCP2 coprocessor offers a very cost effective and synergistic solution when combined with Texas
Instruments (TI) DSPs. The VCP2 supports 1941 12.2 Kbps class A 3G voice channels running at
333 MHz.
1
Features
The VCP2 provides:
• High flexibility:
– Variable constraint length, K = 5, 6, 7, 8, or 9
– User-supplied code coefficients
– Code rates (1/2, 1/3, or 1/4)
– Configurable trace back settings (convergence distance, frame structure)
– Branch metrics calculation and depuncturing done in software by the DSP
• System and development cost optimization:
– The VCP2 releases DSP resources for other processing
– Reduces board space and power consumption by performing on-chip decoding
– Communication between the DSP and the VCP2 is performed through the high-performance
EDMA3 engine
– Uses its own optimized working memories
– Provides debug capabilities during frame processing
– Libraries are provided for reduced development time
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
7
Introduction
2
www.ti.com
Introduction
A convolutional code is generated by passing the information sequence to be transmitted through a linear
finite-state shift register. The VCP2 is able to decode only a subset of those codes known as a single-shift
register, nonrecursive convolutional code (an example is given in Figure 1). Important parameters for this
type of codes are:
• The constraint length K (length of the delay line, the VCP2 supports K values from 5 to 9).
• The rate R given by R = k/n where k is the number of information bits needed to produce n output bits
also known as codewords (the VCP2 supports 1/2, 1/3, and 1/4 codes with rates).
• The generator polynomials Gn describe how the outputs are generated from the inputs.
Figure 1. Convolutional Encoder Example Block Diagram
output 0
output 1
input
z
-1
-1
z
output 2
NOTE: K = 3, R = k/n = 1/3, G0 = (100)8, G1 = (101)8, G2 = (111)8 0/000 means input is 0, output0 is
0, output1 is 0, output2 is 0.There are 2(K-1) states and 2k incoming branches per state.
From the parameters, we can derive a trellis diagram providing a useful representation of the code, but
whose complexity grows exponentially with the constraint length K. Figure 2 shows the trellis diagram of
the code from Figure 1. The fact that there is a limited number of possible transitions from one state to
another makes the code powerful and will be used in the decoding process.
As a maximum-likelihood sequence estimation (MLSE) decoder, the Viterbi decoder identifies the code
sequence with the highest probability of matching the transmitted sequence based on the received
sequence.
The Viterbi algorithm is composed of a metric update and a traceback routine. The metric update performs
a forward recursion in the trellis over a finite number of symbol periods where probabilities are
accumulated (the VCP2 accumulates on 13 bits) for each individual state based on the current input
symbol (branch metric information). The accumulated metric is known as path metrics or state metrics.
Once a path through the trellis is identified, the traceback routine performs a backward recursion in the
trellis and outputs hard decisions or soft decisions.
8
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Introduction
www.ti.com
Figure 2. Trellis Diagram for Convolutional Encoder Example
State
0/000
00
1/111
0/011
01
1/100
0/001
10
0/010
1/110
11
1/101
Time t
Time t+T
NOTE: K = 3, R = k/n = 1/3, G0 = (100)8, G1 = (101)8, G2 = (111)8 0/000 means input is 0, output1 is
0, output2 is 0, output3 is 0. There are 2(K-1) states and 2k incoming branches per state.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
9
Overview
3
www.ti.com
Overview
The DSP controls the operation of the VCP2 (Figure 3) using memory-mapped registers. The DSP
typically sends and receives data using synchronized EDMA3 transfers through the 64-bit EDMA3 bus.
The VCP2 sends two synchronization events to the EDMA3: a receive event (VCPREVT) and a transmit
event (VCPXEVT). The VCP2 input data corresponds to the branch metrics and the output data to the
hard decisions or soft decisions.
Figure 3. VCP2 Block Diagram
VCP2_INT
Configuration bus
EDMA3 bus
CPU
interrupt
generation
VCPXEVT VCPREVT
REVT/XEVT
generation
VCP Control
EDMA3 I/F unit
Memory block
Processing unit
Viterbi-decoder coprocessor 2 (VCP2)
10
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Input Data
www.ti.com
4
Input Data
4.1
Branch Metrics Calculations
The branch metrics (BM) are calculated by the DSP and stored in the DSP memory subsystem as 8-bit
signed values. Per symbol interval T, for a rate R = k/n and a constraint length K, there are a total of 2K-1+k
branches in the trellis. For rate 1/n codes, only 2n-1 branch metrics need to be computed per symbol period
and passed to the VCP2. Moreover, n symbols are required to calculate 1 branch metric.
Assuming BSPK modulated bits (0 → 1, 1 → -1), the branch metrics are calculated as follows:
• Rate 1/2: there are 2 branch metrics per symbol period
– BM0(t) = r0(t) + r1(t)
– BM1(t) = r0(t) - r1(t)
where r(t) is the received codeword at time t (2 symbols, r 0(t) is the symbol corresponding to the encoder
upper branch, see Figure 1).
• Rate 1/3: there are 4 branch metrics per symbol period
– BM0(t) = r0(t) + r1(t) + r2(t)
– BM1(t) = r0(t) + r1(t) - r2(t)
– BM2(t) = r0(t) - r1(t) + r2(t)
– BM3(t) = r0(t) - r1(t) - r2(t)
where r(t) is the received codeword (3 symbols, r 0(t) is the symbol corresponding to the encoder upper
branch, see Figure 1).
• Rate 1/4: there are 8 branch metrics per symbol period
– BM0(t) = r0(t) + r1(t) + r2(t) + r3(t)
– BM1(t) = r0(t) + r1(t) + r2(t) - r3(t)
– BM2(t) = r0(t) + r1(t) - r2(t) + r3(t)
– BM3(t) = r0(t) + r1(t) - r2(t) - r3(t)
– BM4(t) = r0(t) - r1(t) + r2(t) + r3(t)
– BM5(t) = r0(t) - r1(t) + r2(t) - r3(t)
– BM6(t) = r0(t) - r1(t) - r2(t) + r3(t)
– BM7(t) = r0(t) - r1(t) - r2(t) - r3(t)
where r(t) is the received codeword (4 symbols, r 0(t) is the symbol corresponding to the encoder upper
branch, see Figure 1).
The data must be sent to the VCP2 as described in Table 1, Table 2, and Table 3 for rates 1/2, 1/3, and
1/4, respectively (the base address must be double-word aligned).
The branch metrics can be saved in the DSP memory subsystem in either their native format or packed in
words (user implementation). When working in big-endian mode, the VCP2 endian mode register
(VCPEND) indicates if the data is 32-bit word packed or native 8-bit format and the VCP2 will handle the
endianness byte swapping accordingly (see Section 7).
Table 1. Branch Metrics for Rate 1/2
Data
Address (hex)
MSB
LSB
Base
BM1(t=T)
BM0(t=T)
BM 1(t=0)
BM0(t=0)
Base + 4h
BM1(t=3T)
BM0(t=3T)
BM1(t=2T)
BM0(t=2T)
Base + 8h
...
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
11
Input Data
www.ti.com
Table 2. Branch Metrics for Rate 1/3
Data
Address (hex)
MSB
LSB
Base
BM3(t=0)
BM2(t=0)
BM1(t=0)
BM0(t=0)
Base + 4h
BM3(t=T)
BM2(t=T)
BM1(t=T)
BM0(t=T)
Base + 8h
...
Table 3. Branch Metrics for Rate 1/4
Data
Address (hex)
MSB
LSB
Base
BM3(t=0)
BM2(t=0)
BM1(t=0)
Base + 4h
BM7(t=0)
BM6(t=0)
BM5(t=0)
BM0(t=0)
BM4(t=0)
Base + 8h
BM3(t=T)
BM2(t=T)
BM1(t=T)
BM0(t=T)
Base + Ch
BM7(t=T)
BM6(t=T)
BM5(t=T)
BM4(t=T)
Base + 10h
...
The state metric accumulation resolution is 13 bits on the VCP2. Consequently, full 8-bit dynamic range is
available for branch metrics on the C6474 VCP2, for all constraint lengths and all code rates.
4.2
Soft Input Dynamic Ranges
The VCP2 implementation implies that the soft inputs need to be quantized so that the branch metrics
satisfy the following bound B1 (branch metrics upper bound - absolute value):
2(C - 1) - 1 ≥ (2 × (K - 1) + 2) × B 1
K is the constraint length and C determines the truncation of state metrics that can be performed without
loss of decoding performance.
The VCP2 is designed with C = 13. The branch metrics can have a maximum dynamic range of 7 + 1 sign
bits [-128; +127]. This gives another branch metrics upper bound B 2 ≤ 128.
So for a given constraint length, min (B 1, B 2) gives the final branch metrics maximum bound B.
To satisfy B in the branch metrics calculation, the soft input values, delivered as 8-bit-signed equalized
values, are linearly scaled with the following formula where 1/n is the rate.
Scaled = min (B 1, B 2)/n × SoftValue/128
Example
K = 9, then B 1 ≤ 227.5 and the branch metrics range B 2 is [-128; +127]. So the branch metrics need to be
in [-128;+127] range.
If rate 1/3, 128/3 42, so the soft inputs need to be scaled by a factor of 0.333333 and saturated within
the range [-42; +42].
Table 4 summarizes the calculations for the different constraint length and rate:
Table 4. VCP2 Soft Inputs Quantization
12
1/Rate
K
Scaling Factor
Range
2
5, 6, 7, 8, 9
0.5
[-64; +63]
3
5, 6, 7, 8, 9
0.333333
[-42; +42]
4
5, 6, 7, 8, 9
0.25
[-31; +31]
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Decision Data
www.ti.com
5
Decision Data
The VCP2 can be configured to generate either hard decisions (one bit per decision), or soft decisions
(8-bit value per decision). Ordering of the VCP2 decisions depends on the OUT_ORDER field of VCPIC3
and the SD field of VCPEND. If the DSP is set to work in big-endian mode and the results are soft
decisions (see the VCP2 endian mode register, Section 6.2). The decisions buffer start address must be
double-word aligned and the buffer size must be a multiple of 8 bytes.
The soft decisions in the VCP2 are initially computed with the path metrics at 13-bit values. The results
are then clipped to 8-bit signed integer values before being stored in the traceback soft decision memory.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
13
Registers
6
www.ti.com
Registers
The VCP2 contains several memory-mapped registers accessible by the CPU, the IDMA, the QDMA, and
the EDMA3. A configuration-bus access is faster than an EDMA3-bus access for isolated accesses
(typically when accessing control registers). EDMA3-bus accesses are used for EDMA3 transfers and
provide maximum throughput to/from the VCP2. The registers are listed in Table 5. For the memory map
and full register addresses, see the device-specific data manual.
The branch metric and traceback decision memories contents are not accessible and the memories can
be regarded as FIFOs by the DSP, meaning you do not have to perform any indexing on the addresses.
Table 5. VCP2 Registers
EDMA3 Bus
Offsets
Configuration Bus
Offsets
Acronym
Register Name
See
0000h
VCPIC0
VCP input configuration register 0
Section 6.1
0004h
VCPIC1
VCP input configuration register 1
Section 6.2
0008h
VCPIC2
VCP input configuration register 2
Section 6.3
000Ch
VCPIC3
VCP input configuration register 3
Section 6.4
0010h
VCPIC4
VCP input configuration register 4
Section 6.5
0014h
VCPIC5
VCP input configuration register 5
Section 6.6
0048h
VCPOUT0
VCP output register 0
Section 6.7
004Ch
VCPOUT1
VCP output register 1
Section 6.8
0080h
VCPWBM
VCP branch metrics write FIFO register
00C0h
VCPRDECS
VCP decisions read FIFO register
0018h
VCPEXE
VCP execution register
Section 6.9
0020h
VCPEND
VCP endian mode register
Section 6.10
0040h
VCPSTAT0
VCP status register 0
Section 6.11
0044h
VCPSTAT1
VCP status register 1
Section 6.12
0050h
VCPERR
VCP error register
Section 6.13
0060h
VCPEMU
VCP emulation control register
Section 6.14
Table 6. VCP2 Memories
14
EDMA3 Bus Offsets
Acronym
1000h
BM
Branch Metrics (BM)
512 Bytes
2000h
SM
State Metric (SM)
448 Bytes
3000h
TBHD
Traceback Hard Decision
4K Bytes
6000h
TBSD
Traceback Soft Decision
16K Bytes
F000h
IO
Decoded Bits (IO)
512 Bytes
TMS320C6474 Viterbi-Decoder Coprocessor 2
Name
Size
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.1
VCP2 Input Configuration Register 0 (VCPIC0)
The VCP2 input configuration register 0 (VCPIC0) is shown in Figure 4 and described in Table 7.
Figure 4. VCP2 Input Configuration Register 0 (VCPIC0)
31
24 23
16 15
8
7
0
POLY3
POLY2
POLY1
POLY0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. VCP2 Input Configuration Register 0 (VCPIC0) Field Descriptions
Field
Value
Description (1)
31-24
POLY3
0-FFh
Polynomial generator G3 (see Section 9.2).
23-16
POLY2
0-FFh
Polynomial generator G2 (see Section 9.2).
15-8
POLY1
0-FFh
Polynomial generator G1 (see Section 9.2).
7-0
POLY0
0-FFh
Polynomial generator G0 (see Section 9.2).
Bit
(1)
The polynomial generators are 9-bit values defined as G(z) = b8z-8 + b7z-7 + b6z-6 + b5z-5 + b4z-4 + b3z-3 + b2z-2 + b1z-1 + b0, but only 8 bits
are passed in the POLYn bitfields so that b1 is the most significant bit and b8 is the least significant bit (b0 is not passed, but set by the
internal VCP hardware).
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
15
Registers
6.2
www.ti.com
VCP2 Input Configuration Register 1 (VCPIC1)
The VCP2 input configuration register 1 (VCPIC1) is shown in Figure 5 and described in Table 8.
Figure 5. VCP2 Input Configuration Register 1 (VCPIC1)
31
29
28
27
16
Reserved
YAMEN
YAMT
R/W-0
R/W-0
R/W-0
15
0
Reserved
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. VCP2 Input Configuration Register 1 (VCPIC1) Field Descriptions
Bit
31-29
28
Field
Reserved
0
YAMEN
27-16
YAMT
15-0
Reserved
16
Value
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Yamamoto algorithm enable bit. See Section 8.2.
0
Yamamoto algorithm is disabled.
1
Yamamoto algorithm is enabled.
0-FFFh Yamamoto threshold value bits. See Section 8.2.
0
Reserved. These reserved bit locations must be 0. A value written to this field has no effect.
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.3
VCP2 Input Configuration Register 2 (VCPIC2)
The VCP2 input configuration register 2 (VCPIC2) is shown in Figure 6 and described in Table 9.
Figure 6. VCP2 Input Configuration Register 2 (VCPIC2)
31
16 15
0
R
FL
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. VCP2 Input Configuration Register 2 (VCPIC2) Field Descriptions
Bit
Field
Value
Description
31-16
R
0-FFFFh
Reliability length bits (see Section 8.1).
15-0
FL
0-FFFFh
Frame length bits (see Section 8.1).
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
17
Registers
6.4
www.ti.com
VCP2 Input Configuration Register 3 (VCPIC3)
The VCP2 input configuration register 3 (VCPIC3) is shown in Figure 7 and described in Table 10.
Figure 7. VCP2 Input Configuration Register 3 (VCPIC3)
31
29
28
27
25
24
23
16
Reserved
OUT_
ORDER
Reserved
ITBEN
ITBI
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
0
C
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. VCP2 Input Configuration Register 3 (VCPIC3) Field Descriptions
Bit
31-29
28
27-25
24
Field
Reserved
OUT_ORDER
Reserved
ITBEN
23-16
ITBI
15-0
C
18
Value
0
0 and 1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
Defines the order of VCP output for decoded data.
0
0 to 31
1
31 to 0
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
0 and 1
Traceback state index enable/disable.
0
Disabled
1
Initialization of traceback starting state is enabled
0-FFh
0-FFFFh
Traceback state index. The index of the starting state for the traceback unit.
Convergence distance bits. The length of the convergent section of the siding window. This is
only used if f > F + (K-1) in mixed mode, or if f > F + C in convergence mode.
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.5
VCP2 Input Configuration Register 4 (VCPIC4)
The VCP2 input configuration register 4 (VCPIC4) is shown in Figure 8 and described in Table 11.
Figure 8. VCP2 Input Configuration Register 4 (VCPIC4)
31
29
28
16
Reserved
IMINS
R/W-0
R/W-0
15
13
12
0
Reserved
IMAXS
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. VCP2 Input Configuration Register 4 (VCPIC4) Field Descriptions
Bit
Field
31-29
Reserved
28-16
IMINS
15-13
Reserved
12-0
IMAXS
Value
0
0-1FFFh
0
0-1FFFh
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
Minimum initial state metric (13 bits).
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
Maximum initial state metric (13 bits).
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
19
Registers
6.6
www.ti.com
VCP2 Input Configuration Register 5 (VCPIC5)
The VCP2 input configuration register 5 (VCPIC5) is shown in Figure 9 and described in Table 12.
Figure 9. VCP2 Input Configuration Register 5 (VCPIC5)
31
30
SDHD
OUTF
29
TB
28
27
Reserved
25
24
SYMR
SYMX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
8
20
19
16
7
0
Reserved
IMAXI
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. VCP2 Input Configuration Register 5 (VCPIC5) Field Descriptions
Bit
Field
31
SDHD
30
29-28
Value
Output decision type select bit.
0
Hard decisions
1
Soft decisions
OUTF
Output parameters read flag bit.
0
VCPREVT is not generated by VCP for output parameters read
1
VCPREVT generated by VCP for output parameters read
TB
27-25
Reserved
24-20
SYMR
Description
Traceback mode select bits.
0
Not allowed
1h
Tailed, F ≤ Fmax
2h
Convergent, (no tail bits)
3h
Mixed, F ≥ Fmax and tail bits are used
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-1Fh
(1)
Determines decision buffer length in output FIFO. When programming register values for the SYMR
bits, always subtract 1 from the value calculated. Valid values for the SYMR bits are from 0 to 1Fh.
For hard decision:
If F ≤ 2048; then SYMR = ceil[f/64] - 1
If F > 2048; then SYMR = 15 or 31
For soft decision:
If F ≤ 256; then SYMR = ceil[f/8] - 1
If F > 256; then SYMR = 15 or 31
19-16
SYMX
15-8
Reserved
7-0
IMAXI
(1)
20
0-Fh
0
0-FFh
Determines branch metrics buffer length in input FIFO. For information on selecting the appropriate
SYMX value, see Section 8.3.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Maximum initial state metric value bits. IMAXI bits determine which state should be initialized with
the maximum state metrics value (IMAXS) bits in VCPIC4; all the other states are initialized with the
value in the IMINS bits.
For more details on Fmax, see Section 8.1.4.
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.7
VCP2 Output Register 0 (VCPOUT0)
The VCP2 output register 0 (VCPOUT0) is shown in Figure 10 and described in Table 13.
Figure 10. VCP2 Output Register 0 (VCPOUT0)
31
29
28
16
Reserved
FMINS
R/W-0
R/W-0
15
13
12
0
Reserved
FMAXS
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. VCP2 Output Register 0 (VCPOUT0) Field Descriptions
Bit
Field
31-29
Reserved
28-16
FMINS
15-13
Reserved
12-0
FMAXS
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-FFFh Minimum final state metric value (13 bits).
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-FFFh Maximum state metric value for the final trellis stage (at trellis stage R+C). 13 bits
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
21
Registers
6.8
www.ti.com
VCP2 Output Register 1 (VCPOUT1)
The VCP2 output register 1 (VCPOUT1) is shown in Figure 11 and described in Table 14.
Figure 11. VCP2 Output Register 1 (VCPOUT1)
31
17
15
16
Reserved
YAM
R/W-0
R-0
8
7
0
Reserved
FMAXI
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. VCP2 Output Register 1 (VCPOUT1) Field Descriptions
Bit
31-17
16
22
Field
Reserved
Value
0
YAM
15-8
Reserved
7-0
FMAXI
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Yamamoto bit result. This bit is a quality indicator bit and is only used if the Yamamoto logic is
enabled. See Section 8.2.
0
At least one trellis stage had an absolute difference less than the Yamamoto threshold and the
decided frame has poor quality
1
No trellis stage had an absolute difference less than the Yamamoto threshold and the frame has
good quality
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-FFFh State index for the state with the final maximum state metric. There are 2(k-1) state metrics for each
trellis stage. Valid range for FMAXI is 0 to 2(k-1) -1.
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.9
VCP2 Execution Register (VCPEXE)
The VCP2 execution register (VCPEXE) is shown in Figure 12 and described in Table 15.
Figure 12. VCP2 Execution Register (VCPEXE)
31
4
3
0
Reserved
COMMAND
R/W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. VCP2 Execution Register (VCPEXE) Field Descriptions
Bit
Field
31-4
Reserved
3-0
COMMAND
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
VCP command select bits; see Section 10.
0
Reserved (no instruction)
1h
Start VCP (normal mode)
2h
Halt or Pause VCP (debug mode). The VCP is halted (or paused) after processing the state
metric for the current sliding window and before the start of the traceback.
3h
Restart VCP and process one sliding window (debug mode). The VCP is restarted from the
pause state and begins the traceback operation. The VCP is again paused after processing
the state metrics for next sliding window.
4h
Restart VCP (debug mode). The VCP is restarted from the paused state and begins the
traceback operation. The VCP will run to normal completion.
5h
Stop. Soft reset all VCP registers to their initial condition. All registers in the VCP are reset in
this mode except for the execution register, endian register, emulation register, and other
internal registers.
6h-FFh
Reserved
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
23
Registers
www.ti.com
6.10 VCP2 Endian Mode Register (VCPEND)
The VCP2 endian mode register (VCPEND) is shown in Figure 13 and described in Table 16. VCPEND
has an effect only in big-endian mode.
Figure 13. VCP2 Endian Mode Register (VCPEND)
31
16
Reserved
R/W-0
15
8
Reserved
R/W-0
7
1
0
Reserved
2
SD
BM
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. VCP2 Endian Mode Register (VCPEND) Field Descriptions
Bit
31-2
1
0
24
Field
Reserved
Value
0
SD
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Traceback soft-decision memory format select bit.
0
32-bit-word packed.
1
Native format (8 bits).
BM
Branch metrics memory format select bit.
0
32-bit-word packed.
1
Native format (8 bits).
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.11 VCP2 Status Register 0 (VCPSTAT0)
The VCP2 status register 0 (VCPSTAT0) is shown in Figure 14 and described in Table 17.
Figure 14. VCP2 Status Register 0 (VCPSTAT0)
31
29
28
16
Reserved
NSYMPROC
R/W-0
R-0
15
12
11
8
NSYMPROC
Reserved
R-0
R/W-0
7
6
5
4
3
2
1
0
Reserved
EMU
HALT
OFFUL
IFEMP
WIC
ERR
RUN
PAUSE
R/W-0
R-0
R-0
R-1
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. VCP2 Status Register 0 (VCPSTAT0) Field Descriptions
Bit
Field
31-29
Reserved
28-12
NSYMPROC
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Number of symbols processed bits. The NSYMPROC bits indicate how many symbols have been
processed in the state metric unit with respect to time.
The maximum number of processed stages is equal to f + (k-1) in tailed or mixed mode. The
maximum number of processed stages is equal to f + c in convergent mode.
11-7
Reserved
6
EMUHALT
5
4
3
2
1
0
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Emulation halt status bit.
0
No halt due to emulation.
1
Halt due to emulation.
OFFUL
Output FIFO buffer full status bit.
0
Output FIFO buffer is not full.
1
Output FIFO buffer is full.
IFEMP
Input FIFO buffer empty status bit.
0
Input FIFO buffer is not empty.
1
Input FIFO buffer is empty.
WIC
Waiting for input configuration bit. The WIC bit indicates that the VCP is waiting for new input
control parameters to be written. This bit is always set after decoding of a user channel.
0
Not waiting for input configuration words.
1
Waiting for input configuration words.
ERR
VCP error status bit. The ERR bit is cleared as soon as the DSP reads the VCP error register
(VCPERR).
0
No error.
1
VCP paused due to error.
RUN
VCP running status bit.
0
VCP is not running.
1
VCP is running.
PAUSE
VCP pause status bit.
0
VCP is not paused. The UNPAUSE command is acknowledged by clearing the PAUSE bit.
1
VCP is paused. The PAUSE command is acknowledged by setting the PAUSE bit. The PAUSE bit
can also be set, if the input FIFO buffer is becoming empty or if the output FIFO buffer is full.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
25
Registers
www.ti.com
6.12 VCP2 Status Register 1 (VCPSTAT1)
The VCP2 status register 1 (VCPSTAT1) is shown in Figure 15 and described in Table 18.
Figure 15. VCP2 Status Register 1 (VCPSTAT1)
31
16 15
0
NSYMOF
NSYMIF
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. VCP2 Status Register 1 (VCPSTAT1) Field Descriptions
Bit
Field
Value
Description
31-16
NSYMOF
0-FFFFh
Number of symbols in the output FIFO buffer.
15-0
NSYMIF
0-FFFFh
Number of symbols in the input FIFO buffer.
26
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.13 VCP2 Error Register (VCPERR)
The VCP2 error register (VCPERR) is shown in Figure 16 and described in Table 19.
Figure 16. VCP2 Error Register (VCPERR)
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
FCTLERR
FTLERR
TBNAERR
ERROR
R-0
R-0
R-0
R-0
Reserved
E_SYMR
E_SYMX
MAXMIN
ERR
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. VCP2 Error Register (VCPERR) Field Descriptions
Bit
Value
Description
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
6
E_SYMR
0
No error for SMAR, as shown in the following relationships:
5
4
E_SYMX
MAXMINERR
3
FCTLERR
2
FTLERR
1
(1)
Field
31-7
TBNAERR
TB Mode
SYMR
# of 64 Bit Transfers
Condition
Transfer
Hard
0 to 31
1 to 32
f ≤ 2048
Hard
31
32
f > 2048
Hard
15
16
f ≥ 2048
Soft
0 to 31
1 to 32
f ≤ 2048
Soft
31
32
f ≥ 2048
Soft
15
16
f > 2048
1
Error occurred
0
No error for SMAX, as shown in the following relationships:
Code Rate
SYMX
# of 64 Bit Transfers
# of BM per
# trellis per
1/4
3
16
128
16
1/4
1
8
64
8
1/3
7
16
128
32
1/3
3
8
64
16
1/2
15
16
128
64
1/2
7
8
64
32
1
Error occurred
0
No error. Error check for the following relationships:
Sign IMAXS
Sign IMINS
Check Equation
0
0
0 ≤ IMAXS - IMINS < 2048
1
1
0 ≤ IMAXS - IMINS < 2048
0
1
0 ≤ IMAXS - IMINS < 2048
1
0
0 ≤ (2 × 4096 + IMAXS) - IMINS < 2048
1
Error occurred
0
No error
1
1 = r + c too large [( r + c) > (r + c)max] for mixed or convergent traceback modes
0
No error
1
F too large (f > Fmax) for tailed traceback mode (1).
0
No error
1
Traceback mode is not allowed. (1 to 3 are valid modes)
For more details on Fmax, see Section 8.1.4.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
27
Registers
www.ti.com
Table 19. VCP2 Error Register (VCPERR) Field Descriptions (continued)
Bit
0
28
Field
ERROR
Value
Description
0
No error is detected.
1
An error has occurred
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Registers
www.ti.com
6.14 VCP2 Emulation Control Register (VCPEMU)
The VCP2 emulation control register (VCPEMU) is shown in Figure 17 and described in Table 20.
Figure 17. VCP2 Emulation Control Register (VCPEMU)
31
1
0
Reserved
FREE
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. VCP2 Emulation Control Register (VCPEMU) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
FREE
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Free bit
0
Reserved
1
Free run mode - vcp_emususp signal and functions normally.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
29
Endianness
7
www.ti.com
Endianness
The VCP endian mode register (VCPEND) is intended to solve possible big-endian issues and is,
therefore, used only when the DSP is in big-endian mode. Depending on whether the data is saved in the
DSP memory subsystem in its native format or is 32-bit word packed, data interpretation will be different.
7.1
Branch Metrics
When the data are saved in their 8-bit native format (BM = 1), they must be organized in the DSP memory
as described in Table 22. When the data are packed on 32-bit words (BM = 0), they must be organized in
the DSP memory as described in Table 23.
Table 21. Branch Metrics
Little_big_endian
BM
Description (MSB to LSB)
0
0
3,2,1,0,7,6,5,4 Þ 7,6,5,4,3,2,1,0 (bytes)
0
1
0,1,2,3,4,5,6,7 Þ 7,6,5,4,3,2,1,0 (bytes)
1
0
Endianness manager has no effect
7,6,5,4,3,2,1,0 Þ 7,6,5,4,3,2,1,0 (bytes)
1
1
Endianness manager has no effect
7,6,5,4,3,2,1,0 Þ 7,6,5,4,3,2,1,0 (bytes)
Table 22. Branch Metrics in DSP Memory (BM = 1)
Address (hex bytes)
Data
Base
BM0
Base + 1
BM1
Base + 2
BM2
Base + 3
BM3
Base + 4
BM4
Base + 5
BM5
Base + 6
BM6
Base + 7
BM7
Data are presented to the EDMA3 as shown in Figure 18. The endianness manager reorders the BMs, as
shown in Figure 19, for processing.
Figure 18. Data Source - VBUSP/DMA (BM = 1)
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
BM0
BM1
BM2
BM3
BM4
BM5
BM6
BM7
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
BM7
BM6
BM5
BM4
BM3
BM2
BM1
BM0
Figure 19. Data Destination - Kernel for Processing Unit (BM = 1)
30
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Endianness
www.ti.com
Table 23. Branch Metrics in DSP Memory (BM = 0)
Address (hex bytes)
Data
Base
BM3
Base + 1
BM2
Base + 2
BM1
Base + 3
BM0
Base + 4
BM7
Base + 5
BM6
Base + 6
BM5
Base + 7
BM4
Data are presented to the EDMA3 as shown in Figure 20. The endianness manager reorders the BMs, as
shown in Figure 21, for processing.
Figure 20. Data Source - VBUSP/DMA (BM = 0)
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
BM3
BM2
BM1
BM0
BM7
BM7
BM5
BM4
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
BM7
BM6
BM5
BM4
BM3
BM2
BM1
BM0
Figure 21. Data Destination - Kernel for Processing Unit (BM = 0)
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
31
Endianness
7.1.1
www.ti.com
Hard Decisions
The VCP2 hard-decisions bit ordering within the 32-bit hard-decision word is programmable via the
OUT_ORDER = 0 register, such that the oldest bit can be either in the MSB or the LSB position.
Figure 22. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0)
63
62
...
32
31
...
1
0
Stage
N
Stage
N-1
...
Stage
N - 31
Stage
N - 32
...
Stage
N - 62
Stage
N - 63
OUT_ORDER = 1 orders the hard-decision data in the order it is calculated in the state metric
computation, from 31 to 0 in the 32-bit word output.
Figure 23. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
63
62
Stage
N - 31
Stage
N - 30
7.1.2
...
32
31
...
Stage
N
Stage
N - 63
...
1
0
...
Stage
N - 33
Stage
N - 32
Soft Decisions
The VCP2 soft decisions are 8-bit results and output 64 bits at a time. The soft decisions are organized as
shown in Table 24, based on the CPU's endianness and whether SD is set for native or 32-bit packed
results.
Table 24. Soft Decision Organization
32
Little_big_endian
BM
0
0
7,6,5,4,3,2,1,0 Þ 3, 2, 1, 0, 7, 6, 5, 4 (bytes)
0
1
7,6,5,4,3,2,1,0 Þ 0, 1, 2, 3, 4, 5, 6, 7 (bytes)
1
0
Endianness manager has no effect
7,6,5,4,3,2,1,0 Þ 7,6,5,4,3,2,1,0 (bytes)
1
1
Endianness manager has no effect
7,6,5,4,3,2,1,0 Þ 7,6,5,4,3,2,1,0 (bytes)
TMS320C6474 Viterbi-Decoder Coprocessor 2
Description (MSB to LSB)
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Architecture
www.ti.com
8
Architecture
The VCP2 processing unit is shown in Figure 24. The state metrics unit performs the Viterbi forward
recursion using branch metrics as inputs and updates the states metrics for all states (add/compare/select
or ACS operations) at every trellis stage. The state metrics memory is not accessible by the DSP. The
traceback unit performs the Viterbi backward recursion and generates hard decisions or soft decisions.
The traceback memories are not directly accessible by the DSP.
Figure 24. Processing Unit
Branch metrics
Decisions
State metric unit
State
metrics
memory
Traceback unit
SD and HD
traceback
memories
Viterbi Processing Unit
8.1
Sliding-Windows Processing
The traceback hard-decision memory can store up to 32768 traceback bits and there are 2(K-1) bits stored
at each trellis stage. Therefore, the traceback hard-decision memory can store decisions of 32768/2(K-1)
symbols. The traceback soft-decision memory can store up to 8192 traceback soft values and, therefore,
contain up to 8192 soft decisions of 8192/2(K-1) symbols. Assume a terminated frame of length F (excluding
tail bits) and a constraint length K, F and K determine whether all decisions can be stored in the traceback
memories.
If the decisions do not fit in the traceback HD/SD memory, then the convergent or mixed mode is used
and the original frame is segmented into sliding windows (SW); otherwise, the traceback mode is set to
tailed and no segmentation is required.
8.1.1
Tailed Traceback Mode
This mode is used when a full frame resides within the coprocessor traceback memory (see Figure 25).
The state metrics are computed over F + K - 1 symbols, the traceback is initialized with the tailed state
and executed over F + K - 1 symbols. It should be noted that only F decisions are output. They are output
in reverse order and in blocks of user-defined size.
Figure 25. Tailed Traceback Mode
SM computation
F
K−1
TB computation
Only output F decisions
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
33
Architecture
8.1.2
www.ti.com
Mixed Traceback Mode
This mode is used when the frame is terminated and does not fit within the coprocessor traceback
memory. The frame is split into sliding windows (see Figure 26). The state metrics are computed over F +
K - 1 symbols, the traceback is initialized with the tailed state and executed over F + K - 1 symbols. It
should be noted that only F decisions are output in blocks of user-defined size (see Section 8.3). The
state metrics computation of sliding window I + 1 is done in parallel with the traceback computation of
sliding window I. Tailed traceback type is used on the last sliding window.
8.1.3
Convergent Traceback Mode
This mode is used with non-terminated frames or when you want to decode a portion of the frame. When
the frame does not fit into the coprocessor traceback memory, then the frame is split into sliding windows
(see Figure 27). The state metrics are computed over F + C symbols, the traceback is initialized with the
tailed state and executed over F + C symbols. It should be noted that only F decisions are output in blocks
of user-defined size (see Section 8.4). The state metrics computation of sliding window I + 1 is done in
parallel with the traceback computation of sliding window I.
Figure 26. Mixed Traceback Mode-Example With Five Sliding Windows
F
R
K−1
C
SW : R+C symbols
R
C
SW : R+C symbols
R
C
SW : R+C symbols
R
R
C
SW : R+C symbols
C
R’
K−1
Last SW : R’+K−1 symbols
SM computation
TB computation
Only output R decisions
Figure 27. Convergent Traceback Mode-Example With Five Sliding Windows
F
R
K−1
C
SW : R+C symbols
R
C
SW : R+C symbols
R
C
SW : R+C symbols
R
R
C
SW : R+C symbols
C
R’
K−1
Last SW : R’+K−1 symbols
SM computation
TB computation
Only output R decisions
34
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Architecture
www.ti.com
8.1.4
F, R, and C Limitations
VCP2 has increased the traceback soft-decision memory and output FIFO compared to the memory in
VCP. The traceback soft-decision memory size has been increased from 1024 × 96 bits to 2048 × 64 bits.
The output FIFO memory has been increased from 32 × 64 bits to 64 × 64 bits. In addition, the
soft-decision resolution is increased internally to 13 bits and is clipped to 8 bits when output from VCP2.
These memory sizes have an effect on the Fmax parameter (i.e., the max. frame size for tailed processing),
and the (R+C)max parameter (i.e., the max. sliding window length for mixed/convergent processing).
The differences between VCP and VCP2 are related to Fmax, (R+C)max, and C. The impact on VCP2
performance is as follows:
• Soft decisions:
– Allowed values for C are C = N*(K - 1), where N is a convergence multiplier. Table 25 and Table 26
show the possible values of N for each value of K for hard and soft decisions.
– R is constrained to be less than or equal to 248.
– Fmax and (R+C)max for VCP2 have been increased over VCP. This change reduces the number of
sliding windows and, therefore, decreases the number of VCP2 cycles needed for traceback.
Overall, there is no major improvement in the processing delay because a larger portion of cycles is
spent in state metric accumulation, which is largely unaffected by the choice of R and C.
• Hard decisions:
– (R+C)max for mixed/convergent processing for hard decisions has been increased from 605 to 635
for K = 6, and from 1020 to 2044 for K = 5. As with soft decisions, this change results in a small
decrease in VCP2 cycle counts during traceback.
The procedure to calculate the reliability length is as follows [the reliability length cannot be larger than
1920, C ≤ 1920 - (k - 1)]:
1. Determine the convergence length.
2. Determine the number of sliding windows: Nsw = ceil(f/[(r + c)max - c]).
3. Determine the reliability length: R = m × ceil[f/(Nsw × m)].
4. If hard decisions are being used and R > 1920 or if soft decisions are being used and R > 248, then
increment the number of sliding windows and go back to step 3.
5. For hard decision and soft-decision limits, see Table 25 and Table 26.
Table 25. Traceback Soft Decision Sliding Window Limits
K
Maximum Frame Size
Fmax
(r + c)max
Multiple (m)
Convergent Multiplier
(N)
9
64
56
60
4
3,6
8
112
105
105
7
3,6,9,12
7
192
186
186
6
3,6,9,12,15,18
Special
Constraint
6
320
315
315
5
3,6,9,12,15,18
r ≤ 248
5
1024
1020
320
4
3,6,9,12,15,18
r ≤ 248
Table 26. Traceback Hard Decision Sliding Window Limits
K
Maximum Frame Size
Fmax
(r + c)max
Multiple (m)
Convergent Multiplier (N)
9
128
120
124
4
3,6,9,12,15
8
224
217
217
7
3,6,9,12,15,18
7
384
378
378
6
3,6,9,12,15,18
6
640
635
635
5
3,6,9,12,15,18
5
2048
2044
2044
4
3,6,9,12,15,18
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
35
Architecture
8.2
www.ti.com
Yamamoto Parameters
During the standard forward recursion, an entity called the Yamamoto bit is computed for each state and
updated every symbol interval. The Yamamoto bit was proposed by Hirosuke Yamamoto (Hirosuke
Yamamoto, Viterbi Decoding Algorithm for Convolutional Codes with Repeat Request, IEEE Transactions
on Information Theory, Vol. IT-26, No. 5, September 1980).
Basically, a bit (the Yamamoto bit) is associated with each state in the decoding process. Initially, all the
Yamamoto bits are set (1). During the decoding process, the Yamamoto bit for a particular state comes
from a couple of decisions made on the path metrics and the Yamamoto bit of previous states. The
metrics of all paths leading to a particular state are compared. If the difference between any two metrics is
less than a given threshold (YAMT bits in VCPIC1), then the Yamamoto bit is cleared; otherwise, the
Yamamoto bit is inherited from the previous state of the path with the largest metric. The end result of this
process (YAM bit in VCPOUT1) yields a zero (0) if anywhere along the decoding path there was a point
where the decision between two paths was ambiguous. The YAM bit can therefore be used as a binary
frame quality indicator.
The Yamamoto algorithm can be enabled or disabled by toggling the YAMEN bit in VCPIC1.
8.3
Input FIFO (Branch Metrics)
Figure 28 shows how the FIFO is used in either a double- or quad-buffering scheme. The VCP2 generates
a VCPXEVT synchronization event each time the nx1/4 of the buffer is empty, where (n =1, 2, 3, 4) or (n =
2, 4), depending on the value of SYMX.
VCPIC5 contains the SYMX bits, which define the buffer length as well as the VCPXEVT event rate. The
maximum allocatable size for the buffer in the input FIFO is 16 64-bit words.
SYMX defines the branch metric buffer length (minus one) to be transmitted to the VCP for each
VCPXEVT. Table 27 has the valid values for SYMX, along with the corresponding number of 64-bit
transfers. If the number of 64 bit transfers is 16, then the double buffering scheme is used and VCPXEVTs
will be generated when half the FIFO is empty (either top or bottom half). If the number of 64-bit transfers
is 8, then a quad buffering scheme is used and VCPXEVTs are generated as each quarter of the FIFO is
emptied. The VCP2 only generates as many VCPXEVTs as needed to produce all the BMs required
based on the SYMX value, frame length, and rate. In other words, no potential excess VCPXEVTs will be
generated based on the FIFO being partially empty at the end of processing.
Table 27. Code Rate versus SYMX
36
Code Rate
SYMX
Number of 64-Bit Transfers
1/4
3
16
1/4
1
8
1/3
7
16
1/3
3
8
1/2
15
16
1/2
7
8
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Architecture
www.ti.com
Figure 28. Input FIFO (Branch Metrics)
64 bits
First 1/4
VCPXEVT
Second 1/4
32
VCPXEVT
Third 1/4
VCPXEVT
Fourth 1/4
VCPXEVT
8.4
Output FIFO (Decisions)
Figure 29 shows how the output FIFO is used in either a double- or quad-buffering scheme. The VCP2
generates a VCPREVT synchronization event each time the nx1/4 of the buffer is empty, where (n =1, 2,
3, 4) or (n = 2, 4), depending on the value of SYMR.
VCPIC5 contains the SYMR bits, which define the buffer length, as well as the VCPREVT event rate. The
maximum size for buffer is 16 64-bit words.
• For hard decisions:
– If F ≤ 2048, then symr = ceil [f/64]-1
– If F > 2048, then symr = 15 or 31
• For soft decisions:
– If F ≤ 256, then symr = ceil [f/8]-1
– If F > 256, then symr = 15 or 31
If SYMR = 31, double buffering is used and a VCPREVT is generated when the first or second half of the
buffer is filled. If SYMR = 15, then VCPREVT is generated after each quarter of the buffer is filled. When F
≤ 2048 for HD or F ≤ 256 for SD outputs and SYMR is determined as described above, a single
VCPREVT is generated once all decisions have been written to the output FIFO.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
37
Architecture
www.ti.com
Figure 29. Output FIFO (Decisions Data)
64 bits
First 1/4
VCPREVT
Second 1/4
32
VCPREVT
Third 1/4
VCPREVT
Fourth 1/4
VCPREVT
38
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Programming
www.ti.com
9
Programming
The VCP2 requires setting up the following context per user channel:
• 3 to 4 EDMA3 parameters (see Table 28)
• The input configurations parameters
Several user channels can be programmed prior to starting the VCP2. A suggested implementation is to
use the EDMA3 interrupt generation capabilities [see the TMS320C6474 DSP Enhanced DMA (EDMA3)
Controller User's Guide (SPRUG11)] and program the EDMA3 to generate an interrupt after the user
channel's last VCPREVT synchronized EDMA3 transfer has completed.
Table 28. Required EDMA3 Links Per User Channel
Direction
Data
Usage
Required/Optional
Transmit
Input configuration parameters
Send the input configuration
parameters
Required
Transmit
Branch metrics
Send branch metrics
Required
Receive
Decisions
Read decisions
Required
Receive
Output parameters
Read output parameters
Optional (OUTF bit)
(1)
9.1
9.1.1
(1)
Transmit direction (DSP → VCP), receive direction (VCP → DSP)
EDMA3 Resources
VCP2 Dedicated EDMA3 Resources
Within the available 64 EDMA3 channel event sources, two are assigned to the VCP2: event 28 and event
29.
• Event 28 is associated to the VCP2 receive event (VCPREVT) and is used as the synchronization
event for EDMA3 transfers from the VCP2 to the DSP (receive). EDMA3 channel 28 is primarily
intended to serve VCP2-to-DSP transfers.
• Event 29 is associated to the VCP2 transmit event (VCPXEVT) and is used as the synchronization
event for EDMA3 transfers from the DSP to the VCP2 (transmit). EDMA3 channel 29 is primarily
intended to serve DSP-to-VCP2 transfers.
9.1.2
Special VCP2 EDMA3 Programming Considerations
The EDMA parameters consist of eight words as shown in Figure 30. All EDMA transfers, in the context of
the VCP, must contain an even number of words, and have source and destination addresses
double-word aligned.
All EDMA transfers must be double-word aligned and the ACNT for the VCP EDMA transfer must be a
multiple of 8. Single-word transfers that are not double-word aligned cause errors in the TCP2/VCP2
memory.
For more information, see the TMS320C6474 DSP Enhanced DMA (EDMA3) Controller User's Guide
(SPRUG11).
Figure 30. EDMA3 Parameters Structure
31
0
EDMA3 Channel Options Parameter (OPT)
EDMA3 Channel Source Address (SRC)
Number of arrays of length ACNT (BCNT)
Number of bytes in array (ACNT)
EDMA3 Channel Destination Address (DST)
Destination 2nd Dimension Index (DSTBIDX)
Source 2nd Dimension Index (SRCBIDX)
BCNTRLD
LINK
Destination 3rd Dimension Index (DSTCIDX)
Source 3rd Dimension Index (SRCCIDX)
Reserved
Number of frames in block (CCNT)
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
39
Programming
9.1.2.1
www.ti.com
Input Configuration Parameters Transfer
This EDMA3 transfer to the input configuration parameters is a 6-word VCPXEVT frame-synchronized
transfer. The OPTIONS should be set as:
• ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
• TCCEN = 0 (Transfer complete chaining is disabled)
• ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)
• WIMODE = 0 (Normal operation)
• TCINTEN = 0 (Transfer complete interrupt is disabled)
• TCC = 1 to 63 (Transfer complete code)
• TCCMODE = 0 (Normal completion)
• FWID = Don't care
• STAT = 0 (Entry is updated as normal)
• SYNCDIM = 0 (A-sync transfer, each event triggers the transfer of ACNT elements)
• DAM = 0 (Dst address within an array increments. Dst is not a FIFO.)
• SAM = 0 (Src Address within an array increments. Src is not a FIFO.)
• SOURCE ADDRESS: User input configuration parameters start address
• ACNT = 24 (Number of bytes in an array)
• BCNT = 1 (Number of arrays in a frame)
• Destination Address: VCPIC0
• SRCBIDX = 0
• DSTBIDX = 0
• SRCCIDX = 0
• DSTCIDX = 0
• CCNT = 1 (Number of frames in a block)
Upon completion, this EDMA3 transfer is linked to the EDMA3 for branch metrics transfer parameters.
9.1.2.2
Branch Metrics Transfer
This EDMA3 transfer to the branch metrics FIFO is a VCPXEVT frame-synchronized transfer. The
OPTIONS should be set as:
• ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
• TCCEN = 0 (Transfer complete chaining is disabled)
• ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)
• TCINTEN = 1 (Transfer complete interrupt is Enabled)
• WIMODE = 0 (Normal operation)
• TCC = 1 to 63 (Transfer complete code)
• TCCMODE = 0 (Normal completion)
• FWID = Don't care
• STAT = 0 (Entry is updated as normal)
• SYNCDIM = 0 (A-sync transfer, each event triggers the transfer of ACNT elements)
• DAM = 1 (Dst address is fixed. Dst is a FIFO.)
• SAM = 0 (Src Address within an array increments. Src is not a FIFO.)
• SOURCE ADDRESS: Branch Metrics Array start address
• ACNT = 4×(SYMX+1)×2(r-1) (Number of branch metrics bytes in an array)
• BCNT = CEIL(TNBM/ACNT) (Number of arrays in a frame)
Where TNBM = Total Number of Branch Metrics, in bytes
To calculate total number of branch metrics data in bytes:
For mixed and tailed traceback mode, Total number of Branch Metrics = (F + K - 1) ×(2(r - 1))
40
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Programming
www.ti.com
•
•
•
•
•
•
For convergent mode, Total number of Branch Metrics = (F + C) × (2(r − 1))
DESTINATION ADDRESS: VCPWBM branch metrics FIFO address
SRCBIDX = ACNT
DSTBIDX = 0
SRCCIDX = 0
DSTCIDX = 0
CCNT = 1 (Number of frames in a block)
Upon completion, this EDMA3 transfer is linked to one of the following:
• The DMA input configuration parameters transfer parameters of the next user channel, if there is one
ready to be decoded.
• Dummy DMA transfer parameters, if there are no more user channels ready to be decoded [for
information on how to set up a dummy Xfer, see the TMS320C6474 DSP Enhanced DMA (EDMA3)
Controller User's Guide (SPRUG11)]. Do not link to a NULL transfer, as the secondary event register
will set the event flag for Event 29. The final VCPXEVT is generated upon the reading of the decisions
and output registers, which is intended to transfer the input configuration of the next user channel. If a
NULL transfer link is in place, the final VCPXEVT will set the event 29 flag of SER and no further VCP
execution will occur until it is cleared.
9.1.2.3
Decisions Transfer
EDMA3 transfers from the decision buffer are VCPREVT frame-synchronized transfers. The programming
of these transfers depend on the decision type and the traceback mode.
Upon completion, this EDMA3 transfer is linked to one of the following:
1. The decisions EDMA3 transfer parameters of the next user channel, if there is one ready to be
decoded and the OUTF bit is 0.
2. Null EDMA3 transfer parameters (with all zeros), if there are no more user channels ready to be
decoded and the OUTF bit is 0.
3. The output parameters EDMA3 transfer parameters, if the OUTF bit is 1.
9.1.2.4
Hard-Decisions Mode
The OPTIONS should be set as:
• ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
• TCCEN = 0 (Transfer complete chaining is disabled)
• ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)
• TCINTEN = 0 (Transfer complete interrupt is disabled)
• WIMODE = 0 (Normal operation)
• TCC = 1 to 63 (Transfer complete code)
• TCCMODE = 0 (Normal completion)
• FWID = Don't care
• STAT = 0 (Entry is updated as normal)
• SYNCDIM = 0 (A-sync transfer, each event triggers the transfer of ACNT elements)
• DAM = 0 (Dst address within an array increments. Dst is not a FIFO.)
• SAM = 1 (Src Address is fixed. Src is a FIFO.)
• SOURCE ADDRESS: VCPRDECS Decision FIFO address
• ACNT = (SYMR+1) × 8 (Number of hard decision bytes in an array)
• BCNT = CEIL(TNHD/ACNT) (Number of arrays in a frame) Where TNHD is the total number of hard
decisions in bytes (Framelength/8).
• Destination Address: hard-decision array address
• SRCBIDX = 0
• DSTBIDX = ACNT
• SRCCIDX = 0
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
41
Programming
•
•
9.1.2.5
www.ti.com
DSTCIDX = 0
CCNT = 1 (Number of frames in a block)
Soft-Decisions Mode
The OPTIONS should be set as:
• ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
• TCCEN = 0 (Transfer complete chaining is disabled)
• ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)
• TCINTEN = 0 (Transfer complete interrupt is disabled)
• WIMODE = 0 (Normal operation)
• TCC = 1 to 63 (Transfer complete code)
• TCCMODE = 0 (Normal completion)
• FWID = Don't care
• STAT = 0 (Entry is updated as normal)
• SYNCDIM = 0 (A-sync transfer, each event triggers the transfer of ACNT elements)
• DAM = 0 (Dst address within an array increments. Dst is not a FIFO.)
• SAM = 1 (Src Address is fixed. Src is a FIFO.)
• SOURCE ADDRESS: VCPRDECS Decision FIFO address
• ACNT = (SYMR+1) × 8 (Number of soft decision bytes in an array)
• BCNT = CEIL(TNSD/ACNT) (Number of arrays in a frame) Where TNSD is the total number of soft
decisions (framelength)
• Destination Address: soft-decision array address
• SRCBIDX = 0
• DSTBIDX = ACNT
• SRCCIDX = 0
• DSTCIDX = 0
• CCNT = 1 (Number of frames in a block)
9.1.2.6
Output Parameters Transfer
This transfer is optional and depends on the OUTF bit. It is a 2- to 32-bit word VCPREVT frame
synchronized transfer. The OPTIONS should be set as:
• ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
• TCCEN = 0 (Transfer complete chaining is disabled)
• ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)
• TCINTEN = 0 (Transfer complete interrupt is disabled)
• WIMODE = 0 (Normal operation)
• TCC = 1 to 63 (Transfer complete code)
• TCCMODE = 0 (Normal completion)
• FWID = Don't care
• STAT = 0 (Entry is updated as normal)
• SYNCDIM = 0 (A-sync transfer, each event triggers the transfer of ACNT elements)
• DAM = 0 (Dst address within an array increments. Dst is not a FIFO.)
• SAM = 0 (Src Address within an array increments. Src is not a FIFO.)
• SOURCE ADDRESS: VCP2 output register 0 address
• ACNT = 8
• BCNT = 1
• Destination Address: output register store array address
• SRCBIDX = 0
• DSTBIDX = 0
42
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Output Parameters
www.ti.com
•
•
•
SRCCIDX = 0
DSTCIDX = 0
CCNT = 1 (Number of frames in a block)
Upon completion, this EDMA3 transfer is linked to one of the following:
• The EDMA3 decisions transfer parameters of the next user channel, if there is one ready to be
decoded.
• Null EDMA3 transfer parameters (with all zeros), if there are no more user channels ready to be
decoded.
9.2
Input Configuration Words
The input configuration words should reflect the parameters of the user channels to be decoded.
The POLYn bits in VCPIC0 correspond to the generator polynomials in the encoder (see Figure 1). The
values in each POLYn bit field must be entered in reverse order. The POLYn least-significant bit is set by
the VCP2 logic.
• For rate 1/2, POLY0 and POLY1 are required.
• For rate 1/3, POLY0, POLY1, and POLY2 are required.
• For rate 1/4, all the POLYn bits are required.
The YAMT and YAMEN bits in VCPIC1 are described in Section 8.2.
The F and R bits in VCPIC2, the C bit in VCPIC3, and the TB bits in VCPIC5 are described in Section 8.1.
The IMAXI bits in VCPIC5 determine which state should be initialized with the maximum state metrics
value (IMAXS), all the other states are initialized with the minimum state metrics value (IMINS). The IMAXI
can range from 0 to 2K-1-1. The IMAXS and IMINS are 13-bit signed values.
The SYMX and SYMR bits in VCPIC5 are described in Section 8.3 and Section 8.4.
The OUTF bit in VCPIC5 indicates whether the VCP should generate a VCPREVT for reading the output
parameters. The OUTF bit setting will impact the EDMA3 programming (see Section 9.1.2.3).
10
Output Parameters
The FMAXS and FMINS bits in VCPOUT0 indicate the final maximum and minimum state metric values,
respectively. The FMAXI bit in VCPOUT1 indicates the state index for the state with the final maximum
state metric.
The YAM bit in VCPOUT1 is described in Section 8.2.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
43
Event Generation
11
www.ti.com
Event Generation
11.1 VCPXEVT Generation
A
•
•
•
VCP2 transmit event (VCPXEVT) is generated when any of the following conditions appear:
A START command write in VCPEXE.
All input control words have been received and are correct.
Top one-fourth and half or bottom one-fourth and half of the input FIFO buffer (see Figure 28) is
empty.
• After all decisions have been read and OUTF is cleared, or if all decisions have been read and the
output registers have been read and OUTF is set. Note that this extra XEVT pulls the next set of input
configurations via EDMA3. If EDMA3 is not set up to link in another set of input configurations, then a
dummy transfer should be set up to avoid an SER event flag being set for the EDMA3 parameter entry.
If the flag is set, it effectively locks the VCP2, and must be cleared before any future events can be
processed for that entry.
11.2 VCPREVT Generation
A VCP2 receive event (VCPREVT) is generated when any of the following conditions appear:
• The traceback unit has written top one fourth and half or bottom one-fourth and half of the output FIFO
buffer (see Figure 29).
• After the traceback is completed (the whole frame has been decoded).
• OUTF bit in VCPIC5 is 1 and all decisions have been read to read the output registers.
44
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Operational Modes
www.ti.com
12
Operational Modes
•
•
•
•
•
•
0: Value at reset or value written by the coprocessor when previous instruction is read and its
execution is ongoing. DSP may test the status word in the output control memory to check if the
instruction is being executed.
1: Start - CPU orders the coprocessor to start a processing block. The first action of the coprocessor is
then to generate the first XEVT to trigger DMA transfer of the input control words.
2: Pause - CPU orders the coprocessor to pause a processing block at the beginning of traceback.
3: Unpause (single_traceback) - CPU orders the coprocessor to restart at the beginning of traceback
and halt at next traceback.
4: Unpause (finish_traceback) - CPU orders the coprocessor to restart at the beginning of traceback
and complete decode.
Stop - CPU orders the coprocessor to reset. The coprocessor resets all VCP2 registers.
12.1 Debugging Features
Visibility into the internal operation of the VCP2 (i.e., the state metric accumulation, traceback memory) is
available to the CPU via a pause command. However, since the pause command is not synchronized with
the internal VCP2 state machine but is rather sent from the CPU at a random moment in time, this feature
is of limited use.
The pause command on the VCP2 is augmented to provide visibility into VCP2 operation on a sliding
window basis. Instead of using the normal start command which tells the VCP2 to perform a complete
decode of one frame (including input/output transfers via EDMA3), halt at beginning of traceback and
resume until next traceback commands are used, and the internal VCP2 memories can be inspected at
various points in the decoding process. The procedure for using this command is as follows:
• VCP2 configuration and branch metrics are prepared
• A halt at beginning of traceback command is sent
• The VCP2 generates necessary interrupts to the EDMA3 to transfer input configuration and to start
transferring branch metrics. The VCP2 performs state metric accumulation as branch metrics become
available. When it reaches the end of the first sliding window (i.e., the reliability portion and the
convergence portion), the VCP2 halts.
• The CPU polls the VCP2 status register until the VCP2 state changes from running to paused. At that
point, the state metrics memory can be inspected, as well as the traceback memory. To perform an
inspection, halt the CPU via a software breakpoint set at an appropriate point in the code, for instance.
Then, the memory can be inspected visually via the debugger GUI, or, alternatively, the CPU can copy
the relevant internal VCP2 memories to another location for later analysis.
– The CPU sends the resume until next traceback command to the VCP2.
– The VCP2 performs the traceback, generates a portion of hard or soft decisions, and continues with
state metric accumulation until the end of the next sliding window (i.e., another number of R stages,
where R is the reliability length).
– The process continues until the decoding is complete. Alternatively, the decoding process can be
run to completion after any sliding window by sending the resume to completion command instead
of the resume until next traceback command.
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
TMS320C6474 Viterbi-Decoder Coprocessor 2
Copyright © 2008–2009, Texas Instruments Incorporated
45
Errors and Status
13
www.ti.com
Errors and Status
When the coprocessor detects an error, the coprocessor sets the status and error words, then sends an
interrupt to the CPU. Any coprocessor processing is paused and the DSP must reset or start the
coprocessor. An error occurs if the VCP2 receives an invalid value in the input configuration parameters. If
an error is detected, the VCPERR bit field is set accordingly, the ERR bit in VCPSTAT0 is set, the
VCP2_INT interrupt is generated, and no processing is engaged. The only way to restart the VCP2 is to
read VCPERR and send another START command. VCP2_INT has an interrupt selector value of 32. For
details on how to set up interrupts, see the TMS320C6000 DSP Interrupt Selector Reference Guide
(SPRU646).
The status registers are provided for debugging purposes and are best used when either the processor is
halted or the VCP2 is halted. If an error occurs, the VCP2 is halted and a VCP2_INT interrupt is generated
that can be mapped to a CPU interrupt. There may be cases where you would want to view the status
registers when the VCP2 is still running. One such case is when the VCP2 seems to have taken a long
time in processing the current frame. In such cases, a watchdog timer should be used and set according
to the frame length and VCP2 configuration, in addition to some overhead to allow for EDMA3 usage.
46
TMS320C6474 Viterbi-Decoder Coprocessor 2
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
www.ti.com
Appendix A Revision History
This revision history highlights the technical changes made to the document in this revision.
Table 29. C6474 Revision History
See
Section 8.1.4
Additions/Modifications/Deletions
Modified step 4 in numbered list
SPRUG20B – October 2008 – Revised December 2009
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Revision History
47
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising