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Texas Instruments TMS320DM647/DM648 DSP Subsystem (Rev. B) User guides
TMS320DM647/DM648
DSP Subsystem
Reference Guide
Literature Number: SPRUEU6B
June 2009
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Contents
Preface ............................................................................................................................... 9
1
1.1
1.2
1.3
2
2.1
2.2
2.3
2.4
2.5
............................................................................................................. 13
Introduction .................................................................................................................. 14
Block Diagram .............................................................................................................. 14
DSP Subsystem in TMS320DM647/DM648 ............................................................................ 15
1.3.1 Components of the DSP Subsystem ........................................................................... 15
Introduction
....................................................................................... 17
Introduction .................................................................................................................. 18
TMS320C64x+ CPU ....................................................................................................... 18
Memory Controllers ........................................................................................................ 20
2.3.1 L1P Controller ..................................................................................................... 20
2.3.2 L1D Controller ..................................................................................................... 22
2.3.3 L2 Controller ....................................................................................................... 22
2.3.4 Memory Protection ................................................................................................ 23
2.3.5 External Memory Controller (EMC) ............................................................................. 23
2.3.6 Internal DMA (IDMA) .............................................................................................. 23
Internal Peripherals ........................................................................................................ 24
2.4.1 Interrupt Controller (INTC) ....................................................................................... 24
2.4.2 Power-Down Controller (PDC)................................................................................... 24
2.4.3 Bandwidth Manager ............................................................................................... 25
Advanced Event Triggering (AET) ....................................................................................... 25
TMS320C64x+ Megamodule
....................................................................................................... 27
3
System Memory
3.1
Memory Map ................................................................................................................ 28
..........................................................................
3.1.2 External Memory ..................................................................................................
3.1.3 Internal Peripherals ...............................................................................................
3.1.4 Device Peripherals ................................................................................................
Memory Interfaces Overview .............................................................................................
3.2.1 DDR2 External Memory Interface ...............................................................................
3.2.2 External Memory Interface .......................................................................................
3.1.1
3.2
4
4.1
4.2
5
5.1
5.2
DSP Internal Memory (L1P, L1D, L2)
28
28
28
28
29
29
29
....................................................................................................... 31
Overview..................................................................................................................... 32
Clock Domains.............................................................................................................. 33
4.2.1 Core Domains ..................................................................................................... 33
4.2.2 Core Frequency Flexibility ....................................................................................... 34
4.2.3 DDR2/EMIF Clock ................................................................................................. 34
4.2.4 I/O Domains ........................................................................................................ 35
Device Clocking
.......................................................................................................... 37
PLL Module ................................................................................................................. 38
PLL1 Control ................................................................................................................ 38
PLL Controller
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5.3
5.2.1
Device Clock Generation ......................................................................................... 39
5.2.2
Steps for Changing PLL1/Core Domain Frequency .......................................................... 39
PLL2 Control ................................................................................................................ 43
5.3.1
5.4
PLL Controller Registers .................................................................................................. 44
5.4.1
Peripheral ID Register (PID) ..................................................................................... 45
5.4.2
Reset Type Status Register (RSTYPE) ........................................................................ 46
5.4.3
PLL Control Register (PLLCTL) ................................................................................. 47
5.4.4
PLL Multiplier Control Register (PLLM)
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
5.4.10
5.4.11
5.4.12
........................................................................
PLL Pre-Divider Control Register (PREDIV) ...................................................................
PLL Controller Divider 2 Register (PLLDIV2) ..................................................................
PLL Controller Divider 4 Register (PLLDIV4) ..................................................................
PLL Controller Command Register (PLLCMD) ................................................................
PLL Controller Status Register (PLLSTAT) ....................................................................
PLL Controller SYSCLK Status Register (SYSTAT).........................................................
PLL Controller Clock Align Control Register (ALNCTL) .....................................................
PLLDIV Ratio Change Status Register (DCHANGE) ........................................................
48
48
49
50
51
51
52
53
54
....................................................................................... 55
6
Power and Sleep Controller
6.1
Introduction .................................................................................................................. 56
6.2
Power Domain and Module Topology ................................................................................... 57
6.3
Power Domain and Module States ....................................................................................... 58
6.3.1
6.4
6.5
6.6
6.7
Power Domain States............................................................................................. 58
.....................................................................................................
........................................................................................................
Executing State Transitions ...............................................................................................
6.4.1 Power Domain State Transitions ................................................................................
6.4.2 Module State Transitions .........................................................................................
IcePick Emulation Support in the PSC ..................................................................................
PSC Interrupts ..............................................................................................................
6.6.1 Interrupt Events ....................................................................................................
6.6.2 Interrupt Registers.................................................................................................
6.6.3 Interrupt Handling .................................................................................................
PSC Registers ..............................................................................................................
6.7.1 Peripheral Revision and Class Information Register (PID) ..................................................
6.7.2 Interrupt Evaluation Register (INTEVAL) .......................................................................
6.7.3 Module Error Pending Register 1 (mod 33) (MERRPR1) ....................................................
6.7.4 Module Error Clear Register 1 (mod 33) (MERRCR1) .......................................................
6.7.5 Power Domain Transition Command Register (PTCMD) ....................................................
6.7.6 Power Domain Transition Status Register (PTSTAT) ........................................................
6.7.7 Power Domain Status n Register (PDSTATn) .................................................................
6.7.8 Power Domain Control n Register (PDCTLn) .................................................................
6.7.9 Module Status n Register (MDSTATn) .........................................................................
6.7.10 Module Control n Register (MDCTLn) .........................................................................
6.3.2
Module States
58
6.3.3
Local Reset
59
59
59
59
60
60
60
61
62
63
63
64
65
66
67
68
69
70
71
72
.................................................................................................. 73
7
Power Management
7.1
Overview..................................................................................................................... 74
7.2
PSC and PLLC Overview ................................................................................................. 74
7.3
Clock Management
7.3.1
4
Device Clock Generation ......................................................................................... 43
Contents
........................................................................................................
...........................................................................................
Module Clock ON/OFF
75
75
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7.4
8
7.3.2
Module Clock Frequency Scaling ............................................................................... 75
7.3.3
PLL Bypass and Power Down ................................................................................... 75
DSP Sleep Mode Management
..........................................................................................
76
7.4.1
DSP Sleep Modes ................................................................................................. 76
7.4.2
DSP Module Clock ON/OFF ..................................................................................... 76
Interrupt Controller
................................................................................................... 79
........................................................................................................ 81
9
System Module
9.1
Overview..................................................................................................................... 82
9.2
Device Identification........................................................................................................ 82
9.3
Device Configuration ....................................................................................................... 82
..........................................................................................
9.3.2 Device Boot Configuration Status ...............................................................................
Ethernet Subsystem Control ..............................................................................................
Bandwidth Management ...................................................................................................
9.5.1 Bus Master DMA Priority Control................................................................................
Boot Control .................................................................................................................
9.3.1
9.4
9.5
9.6
Pin Multiplexing Control
82
82
82
83
83
83
...................................................................................................................... 85
10
Reset
10.1
Overview..................................................................................................................... 86
10.2
Reset Pins ................................................................................................................... 86
10.3
Device Configurations at Reset
86
10.4
DSP Reset
86
10.4.1
86
10.4.2
11
..........................................................................................
..................................................................................................................
DSP Local Reset .................................................................................................
DSP Module Reset ...............................................................................................
Boot Modes
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............................................................................................................. 89
Contents
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List of Figures
1-1
2-1
2-2
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6
TMS320DM647/DM648 Block Diagram .................................................................................
TMS320C64x+ Megamodule Block Diagram ...........................................................................
C64x+ Cache Memory Architecture......................................................................................
Clocking Diagram ..........................................................................................................
PLL1 Structure ..............................................................................................................
PLL2 Structure in the TMS320DM647/DM648 .........................................................................
Peripheral ID Register (PID) ..............................................................................................
Reset Type Status Register (RSTYPE) .................................................................................
PLL Control Register (PLLCTL) ..........................................................................................
PLL Multiplier Control Register (PLLM) .................................................................................
PLL Pre-Divider Control Register (PREDIV) ............................................................................
PLL Controller Divider 2 Register (PLLDIV2) ..........................................................................
PLL Controller Divider 4 Register (PLLDIV4) ..........................................................................
PLL Controller Command Register (PLLCMD) .........................................................................
PLL Controller Status Register (PLLSTAT) .............................................................................
PLL Controller SYSCLK Status Register (SYSTAT) ...................................................................
PLL Controller Clock Align Control Register (ALNCTL) ...............................................................
PLLDIV Ratio Change Status Register (DCHANGE) ..................................................................
Power and Sleep Controller (PSC) Integration .........................................................................
Peripheral Revision and Class Information Register (PID) ...........................................................
Interrupt Evaluation Register (INTEVAL) ................................................................................
Module Error Pending Register 1 (mod 33) (MERRPR1) .............................................................
Module Error Clear Register 1 (mod 33) (MERRCR1) ................................................................
Power Domain Transition Command Register (PTCMD) .............................................................
Power Domain Transition Status Register (PTSTAT) .................................................................
Power Domain Status n Register (PDSTATn) ..........................................................................
Power Domain Control n Register (PDCTLn) ..........................................................................
Module Status n Register (MDSTATn) ..................................................................................
Module Control n Register (MDCTLn) ...................................................................................
List of Figures
14
19
21
33
39
43
45
46
47
48
48
49
50
51
51
52
53
54
56
63
64
65
66
67
68
69
70
71
72
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List of Tables
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
7-1
9-1
10-1
System Clock Modes and Fixed Ratios for Core Clock Domains....................................................
Example PLL1 Frequencies and Dividers (36 MHZ Clock Input) ....................................................
Example PLL2 Frequencies (Core Voltage = 1.2 V)...................................................................
Peripheral I/O Domain Clock .............................................................................................
System PLLC1 Output Clocks ............................................................................................
DDR PLLC2 Output Clocks ...............................................................................................
PLL and Reset Controller List ............................................................................................
PLL and Reset Controller Registers .....................................................................................
Peripheral ID Register (PID) Field Descriptions ........................................................................
Reset Type Status Register (RSTYPE) Field Descriptions ...........................................................
PLL Control Register (PLLCTL) Field Descriptions ....................................................................
PLL Multiplier Control Register (PLLM) Field Descriptions ...........................................................
PLL Controller Pre-Divider Control Register (PREDIV) Field Descriptions .........................................
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions ....................................................
PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions ....................................................
PLL Controller Command Register (PLLCMD) Field Descriptions...................................................
PLL Controller Status Register (PLLSTAT) Field Descriptions.......................................................
PLL Controller SYSCLK Status Register (SYSTAT) Field Descriptions ............................................
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................
PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ...........................................
DM647/DM648 Default Module Configuration ..........................................................................
Module States ..............................................................................................................
IcePick Emulation Commands ............................................................................................
PSC Interrupt Events ......................................................................................................
Power and Sleep Controller (PSC) Registers ..........................................................................
Peripheral Revision and Class Information Register (PID) Field Descriptions .....................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions .........................................................
Module Error Pending Register 1 (mod 33) (MERRPR1) Field Descriptions ......................................
Module Error Clear Register 1 (mod 33) (MERRCR1) Field Descriptions ..........................................
Power Domain Transition Command Register (PTCMD) Field Descriptions .......................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions ...........................................
Power Domain Status n Register (PDSTATn) Field Descriptions ...................................................
Power Domain Control n Register (PDCTLn) Field Descriptions ....................................................
Module Status n Register (MDSTATn) Field Descriptions ............................................................
Module Control n Register (MDCTLn) Field Descriptions.............................................................
Power Management Features ............................................................................................
TMS320DM647/DM648 Master IDs......................................................................................
Reset Types.................................................................................................................
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List of Tables
32
34
34
35
39
43
44
44
45
46
47
48
48
49
50
51
51
52
53
54
57
58
60
60
63
63
64
65
66
67
68
69
70
71
72
74
83
86
7
8
List of Tables
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Preface
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Read This First
About This Manual
This document describes the DSP subsystem in the TMS320DM647/DM648 device.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM647/DM648 Digital Signal Processor (DSP). Copies of
these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRUEK5 — TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2
memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The DDR2/mDDR
memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM
devices and standard Mobile DDR SDRAM devices.
SPRUEK6 — TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describes
the operation of the asynchronous external memory interface (EMIF) in the TMS320DM647/DM648
Digital Signal Processor (DSP). The EMIF supports a glueless interface to a variety of external
devices.
SPRUEK7 — TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide
describes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648 Digital
Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an input, you can detect the state of the
input by reading the state of an internal register. When configured as an output, you can write to an
internal register to control the state driven on the output pin.
SPRUEK8 — TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide
describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal
Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices
compliant with the I2C-bus specification and connected by way of an I2C-bus. External components
attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the
DSP through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus
specification.
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Notational Conventions
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SPRUEL0 — TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the
64-bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can be
configured as a general-purpose 64-bit timer or dual general-purpose 32-bit timers.
SPRUEL1 — TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide
describes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital Signal
Processor (DSP). The McASP functions as a general-purpose audio serial port optimized for the
needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface
transmission (DIT).
SPRUEL2 — TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describes
the operation of the enhanced direct memory access (EDMA3) controller in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary purpose is
to service user-programmed data transfers between two memory-mapped slave endpoints on the
DSP.
SPRUEL4 — TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guide
describes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648 Digital
Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a PCI host via the
integrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhanced
DMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, while
keeping the EDMA channel resources available for other applications.
SPRUEL5 — TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the host
port interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is a
parallel port through which a host processor can directly access the CPU memory space. The host
device functions as a master to the interface, which increases ease of access. The host and CPU
can exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the
enhanced direct memory access (EDMA) controller.
SPRUEL8 — TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART)
User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral performs
serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial
conversion on data received from the CPU.
SPRUEL9 — TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed
point-to-point serial interface for connecting to host processors and other VLYNQ compatible
devices. It is a full-duplex serial bus where transmit and receive operations occur separately and
simultaneously without interference.
SPRUEM1 — TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User's
Guide discusses the video port and VCXO interpolated control (VIC) port in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a video
capture port, video display port, or transport channel interface (TCI) capture port. The VIC port
provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. When the
video port is used in TCI mode, the VIC port is used to control the system clock, VCXO, for MPEG
transport channel.
SPRUEM2 — TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial
Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference
guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface.
The SPI is a programmable-length shift register, used for high speed communication between
external peripherals or other DSPs.
10
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Notational Conventions
SPRUEU6 — TMS320DM647/DM648 DSP Subsystem User's Guide describes the subsystem in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible for
performing digital signal processing for digital media applications. The subsystem acts as the
overall system controller, responsible for handling many system functions such as system-level
initialization, configuration, user interface, user command execution, connectivity functions, and
overall system control.
SPRUF57 — TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide
describes the operation of the 3 port switch (3PSW) ethernet subsystem in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet
subsystem provides ethernet packet communication and can be configured as an ethernet switch
(DM648 only). It provides the serial gigabit media independent interface (SGMII), the management
data input output (MDIO) for physical layer device (PHY) management.
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TMS320C6000, C6000 are trademarks of Texas Instruments.
12
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Chapter 1
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Introduction
Topic
1.1
1.2
1.3
..................................................................................................
Page
Introduction.............................................................................. 14
Block Diagram .......................................................................... 14
DSP Subsystem in TMS320DM647/DM648 .................................... 15
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Introduction
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Introduction
1.1
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Introduction
The TMS320DM647/DM648 contains a powerful DSP to handle image, video, and audio processing tasks
efficiently. The device consists of the following primary components and sub-systems:
• DSP Subsystem (DSPSS), including the C64x+ Megamodule and associated memory
• Five Video Ports
• Ethernet Subsystem
• Set of I/O peripherals
• Powerful DMA subsystem and DDR2 memory controller interface
The DSP subsystem includes TI’s standard TMS320C64x+ Megamodule and several blocks of internal
memory (L1P, L1D, and L2). For more information, see the TMS320C64x+ DSP Megamodule Peripherals
Reference Guide (SPRU871), the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(SPRU732), and the TMS320C64x+ DSP Cache User’s Guide (SPRU862).
1.2
Block Diagram
An example block diagram for the TMS320DM647/DM648 is shown in Figure 1-1.
Figure 1-1. TMS320DM647/DM648 Block Diagram
BT.656, RAW, Y/C, TCI
JTAG interface
DSP subsystem
C64x+ DSP CPU
System control
Video port
256KB/512KB L2 RAM
PLLs/clock generator
32KB
L1 pgm
Power sleep controller
Pin multiplexing
BT.656,
RAW,
Y/C
32KB
L1 data
VIC
Boot ROM
Switched central resources (SCR)
Peripherals
System
Serial Interfaces
McASP
I2C
SPI
UART
Generalpurpose
timer
GPIO
EDMA
VICP
Connectivity
PCI
(33/66 MHZ)
14
Introduction
VLYNQ
HPI
Program/data storage
3 Port
Ethernet
SubSystem
DDR2 mem
ctrl (32b)
Async
EMIF/
NOR (16b)
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1.3
DSP Subsystem in TMS320DM647/DM648
DSP Subsystem in TMS320DM647/DM648
In the DM647/DM648, the DSP subsystem is responsible for performing digital signal processing for digital
media applications. In addition, the DSP subsystem acts as the overall system controller, responsible for
handling many system functions such as system-level initialization, configuration, user interface, user
command execution, connectivity functions, and overall system control.
1.3.1 Components of the DSP Subsystem
The DSP subsystem in the DM647/DM648 consists of the following components:
• C64x+ Megamodule
• DSP Internal Memories
– Level-1 program memory (L1P)
– Level-1 data memory (L1D)
– Level-2 unified memory (L2)
The DSP also manages/controls all peripherals on the device. See the device-specific data manual for the
full list of peripherals.
Figure 1-1 shows the functional block diagram of the DM647/DM648 and how the DSP subsystem is
connected to the rest of the device. The DM647/DM648 architecture uses the System Infrastructure
(Switched Central Resource) to transfer data within the system.
Chapter 2 discusses the C64x+ Megamodule in more details, including its detailed block diagram.
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Introduction
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16
Introduction
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Chapter 2
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TMS320C64x+ Megamodule
Topic
2.1
2.2
2.3
2.4
2.5
..................................................................................................
Introduction..............................................................................
TMS320C64x+ CPU....................................................................
Memory Controllers ...................................................................
Internal Peripherals ...................................................................
Advanced Event Triggering (AET) ...............................................
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18
18
20
24
25
TMS320C64x+ Megamodule
17
Introduction
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Introduction
The C64x+ Megamodule (Figure 2-1) consists of the following components:
• TMS320C64x+ CPU
• Internal memory controllers:
– Level-1 program memory controller (L1P controller)
– Level-1 data memory controller (L1D controller)
– Level-2 unified memory controller (L2 controller)
– External memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals
– Interrupt controller (INTC)
– Power-down controller (PDC)
• Advanced Event Triggering (AET)
2.2
TMS320C64x+ CPU
The C64x+ Megamodule includes the C64x+ CPU. The C64x+ CPU is a member of the TMS320C6000™
generation of devices. The C6000™ devices execute up to eight 32-bit instructions per cycle. The CPU
consists of 64 general-purpose 32-bit registers and eight functional units. The eight functional units contain
two multipliers and six ALUs. For more information on the CPU, see the TMS320C64x/C64x+ DSP CPU
and Instruction Set Reference Guide (SPRU732).
Features of the C6000 devices include:
• Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units
– Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
– Allows designers to develop highly effective RISC-like code for rapid development time
• Instruction packing
– Gives code-size equivalence for eight instructions that execute serially or in parallel
– Reduces code size, program fetches, and power consumption
• Conditional execution of most instructions
– Reduces costly branching
– Increases parallelism for higher sustained performance
• Efficient code execution on independent functional units
– Industry's most efficient C compiler on DSP benchmark suite
– Industry's first assembly optimizer for rapid development and improved parallelization
• 8/16/32-bit data support, providing efficient memory support for a variety of applications
• 40-bit arithmetic options add extra precision for vocoders and other computationally intensive
applications
• Saturation and normalization provide support for key arithmetic operations
• Field manipulation and instruction extract, set, clear, and bit counting support a common operation
found in control and data manipulation applications
The C64x+ devices include the following additional features:
• Each multiplier can perform two 16 × 16-bit or four 8 × 8-bit multiplies every clock cycle
• Quad 8-bit and dual 16-bit instruction set extensions with data flow support
• Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses
• Special communication-specific instructions to address common operations in error-correcting codes
• Bit count and rotate hardware extends support for bit-level algorithms
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•
•
•
•
•
Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code
size
Protected mode operation: a two-level system of privileged program execution to support higher
capability operating systems and system features, such as memory protection
Exceptions support for error detection and program redirection to provide robust code execution
Hardware support for modulo loop operation to reduce code size
Industry's first assembly optimizer for rapid development and improved parallelization
Figure 2-1. TMS320C64x+ Megamodule Block Diagram
RAM/
Cache
RAM/
cache
256
256
256
Cache control
Memory protect
ROM
Cache control
256
L1P
Bandwidth mgmt
Memory protect
128
256
256
Instruction fetch
Power down
Interrupt
controller
IDMA
C64x+ CPU
Register
file B
128
L2
Bandwidth mgmt
256
Register
file A
256
128
Bandwidth mgmt
Memory protect
CFG
EMC
L1D
32
Chip
registers
256
Cache control
MDMA
SDMA
64
8 x 32
RAM/
cache
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TMS320C64x+ Megamodule
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Memory Controllers
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Memory Controllers
The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory
(L1D memory). Figure 2-2 shows a diagram of the memory architecture. L1P and L1D are configurable as
part L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to the
CPU without stalls. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chip
memory) and L2 cache for caching external memory locations.
The following controllers manage RAM/cache configuration and cache data paths:
• L1P controller
• L1D controller
• L2 controller
• External memory controller (EMC)
The internal direct memory access (IDMA) controller manages DMA among the L1P, L1D, and L2
memories.
This section briefly describes the cache and DMA controllers. For detailed information about each of these
controllers, see the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871).
Note:
The C64x+ Megamodule includes the memory controllers; however, the physical L1P, L1D,
and L2 memories are not part of the megamodule, even though they reside in the DSP
subsystem. Thus, the physical memories are described separately because the C64x+
Megamodule supports a variety of memory configurations. See the Section 3.1 for more
information on the L1P, L1D, and L2 memory configuration specific to the DM647/DM648.
2.3.1 L1P Controller
The L1P controller is the hardware interface between level 1 program memory (L1P memory) and the
other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The
L1P controller responds to instruction fetch requests from the C64x+ CPU and manages transfer
operations between L1P memory and the L2 controller and between L1P memory and the EMC.
See the device-specific data manual for the amount of L1P memory on the device. The L1P controller has
a register interface that allows you to configure part or all of the L1P RAM as normal RAM or as cache.
You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
The L1P is divided into two regions—denoted L1P region 0 and L1P region 1. This is the L1P architecture
on the DM647/DM648:
• L1P region 0: Not populated with memory.
• L1P region 1: Populated with memory that can be configured as mapped memory or cache. The L1P
region 1 memory has 0 wait states. This region is shown as “L1P RAM/Cache” in the device-specific
data manual.
The DM647/DM648 supports the L1P memory protection feature of the standard C64x+ Megamodule.
See the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L1P controller section of the
TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L1P
controller, description of its control registers and memory protection features.
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Figure 2-2. C64x+ Cache Memory Architecture
C64x+ CPU
Data Path
256 bit
Fetch Path
L1D
SRAM
L1P
Cache
L1D
Cache
Write
Buffer
256 bit
256 bit
128 bit
L1 Data
L1 Program
256 bit
L1P
SRAM
2 x 64 bit
L2 Cache
L2 SRAM
64 bit
L2 Unified Data/Program Memory
External Memory
Legend:
addressable memory
cache memory
data paths managed by
cache controller
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2.3.2 L1D Controller
The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the other
components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1D
controller responds to data requests from the C64x+ CPU and manages transfer operations between L1D
memory and the L2 controller and between L1D memory and the EMC.
See the device-specific data manual for the amount of L1D memory on the device. The L1D controller has
a register interface that allows you to configure part of the L1D RAM as normal data RAM or as cache.
You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
The L1D is divided into two regions—denoted L1D region 0 and L1D region 1. This is the L1D architecture
on the DM647/DM648:
• L1D region 0: Not populated with memory.
• L1D region 1: Populated with memory that can be configured as mapped memory or cache. This
region is shown as “L1D RAM/Cache” in the device-specific data manual.
The DM647/DM648 supports the L1D memory protection features of the standard C64x+ Megamodule.
See the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L1D controller section of the
TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L1D
controller, description of its control registers and memory protection features.
2.3.3 L2 Controller
The L2 controller is the hardware interface between level 2 memory (L2 memory) and the other
components in the C64x+ Megamodule (for example, L1P controller, L1D controller, and EMC). The L2
controller manages transfer operations between L2 memory and the other memory controllers (L1P
controller, L1D controller, and EMC).
See device-specific data manual for the amount of L2 memory on the device. The L2 controller has a
register interface that allows you to configure part or all of the L2 RAM as normal RAM or as cache. You
can configure cache sizes of 0 KB, 32 KB, 64 KB, 128 KB, or 256 KB of the RAM.
The L2 memory implements two separate memory ports with the following architecture:
• Port 0
– L2 RAM/Boot ROM
– Banking scheme:4 × 128-bit banks
– Latency: 2 cycle
• Port 1
– VICP
– Banking scheme: 1 × 256-bit bank
– Latency:Ack based
The DM647/DM648 supports the L2 memory protection feature of the standard C64x+ Megamodule.
See the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L2 controller section of the
TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L2 controller,
description of its control registers and memory protection features.
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2.3.4 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 Controllers divide the memory they control into
pages. Region 1 of the L1D Controller has 16 pages at 2KB each, Region 1 of the L1P Controller has 16
pages at 2KB each, and Port 0 of the L2 Controller has 32 pages at 128KB each. (Note: The L2 Port 0
pages are contiguous and span the 4MByte address range from 0x00800000-0x00BFFFFF, covering the
ROM, RAM, and Reserved regions of the memory map.) The DMC, PMC, and UMC memory controllers in
the C64x+ Megamodule are equipped with a set of registers that specify the permissions for each memory
page: L1DMPPA[31:16] for L1D Region 1 , L1PMPPA[31:16] for L1P Region 1, and L2MPPA[31:0] for L2
Port 0. Registers L1DMPPA16, L1PMPPA16, and L2MPPA0 control the page at the smallest address in
their respective memory map ranges; i.e. L1DMPPA16 controls the page at address 0x00F00000,
L1DPMPPA16 controls the page at address 0x00E00000, and L2MPPA0 controls the page at address
0x00800000.
Each page can be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. Additionally, a page can be marked as either (or both) locally or globally accessible. A local
access is a direct CPU access to L1D, L1P, and L2, while a global access is initiated by a DMA (either
IDMA or the EDMA3) or by other system masters. EDMA or IDMA transfers programmed by the CPU
count as global accesses. The CPU is assigned a privilege ID of 0 and all other system masters are all
assigned a privilege ID of 1. Therefore, the AID0 field and AID1 field can be used to control accesses from
the CPU and other system masters, respectively.
For more information on memory protection for L1D, L1P, and L2, see the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871).
2.3.5 External Memory Controller (EMC)
The external memory controller (EMC) is the hardware interface between the external memory map
(external memory and external registers) and the other controllers in the C64x+ Megamodule (for
example, L1P controller, L1D controller, and L2 controller). The EMC manages transfer operations
between external memory and registers and the other memory controllers (L1P controller, L1D controller,
and EMC).
EMC does not support the memory protection feature of the standard C64x+ Megamodule.
See the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871) for more information on the EMC and for a description of its
control registers.
2.3.6 Internal DMA (IDMA)
The internal DMA (IDMA) controller facilitates DMA transfers between any two internal memory-mapped
locations. Internal memory-mapped locations include L1P, L1D, L2, and internal peripheral configuration
registers.
Note:
The IDMA cannot facilitate DMA to or from external memory-mapped locations. The EDMA
facilitates external DMA transfers. See Section 3.1 and the device-specific Enhanced Direct
Memory Access (EDMA) Controller User's Guide for information on EDMA.
The IDMA controller enables the rapid paging of data sections to any local memory-mapped RAM. A key
advantage of the IDMA is that it allows paging between slower L2 and faster L1D data memory. These
transfers take place without CPU intervention and without cache stalls.
Another key advantage is that you can use the IDMA controller to program internal peripheral
configuration registers without CPU intervention.
See the internal DMA (IDMA) controller section in the TMS320C64x+ DSP Megamodule Reference Guide
(SPRU871) for more information on the IDMA controller and for a description of its control registers.
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Internal Peripherals
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Internal Peripherals
This C64x+ Megamodule includes the following internal peripherals:
• Interrupt controller (INTC)
• Power-down controller (PDC)
This section briefly describes the INTC and PDC.
2.4.1 Interrupt Controller (INTC)
The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps the 0 to 127 DSP device events to 12 CPU interrupts. See device-specific data manual for a list of
all the DSP device events. The interrupt controller section of the TMS320C64x+ DSP Megamodule
Reference Guide (SPRU871) fully describes the INTC and how it maps the DSP device events to the
12 CPU interrupts.
2.4.2 Power-Down Controller (PDC)
The C64x+ Megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C64x+ Megamodule:
• C64x+ CPU
• L1P controller
• L1D controller
• L2 controller
• Extended memory controller (EMC)
• Internal direct memory access (IDMA) controller
The DM647/DM648 does not support power-down of the internal memories of the DSP subsystem.
The C64x+ Megamodule is capable of providing both dynamic and static power-down; however, only static
power-down is supported on the DM647/DM648. The TMS320C64x+ DSP Megamodule Reference Guide
(SPRU871) describes the power-down control in more detail.
• Static power-down: The PDC initiates power down of the entire C64x+ Megamodule and all internal
memories immediately upon command from software.
On the DM647/DM648, static power-down affects all components of the C64x+ Megamodule. The
DM647/DM648 does not support power-down of the internal memories. Software can initiate static
power-down via a register bit in the PDC register.
Note:
24
The DM647/DM648 does not support dynamic power-down.
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2.4.3 Bandwidth Manager
The bandwidth manager provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA-initiated DMA transfers (and resulting coherency operations)
• IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of C64x+ Megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA, IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The programmable priority
level has a single meaning throughout the system. There are a total of nine priority levels, where priority
zero is the highest priority and priority eight is the lowest priority. When requests for a single resource
contend, access is granted to the highest-priority requestor. When the contention occurs for multiple
successive cycles, a contention counter assures that the lower-priority requestor gets access to the
resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1 represents a
transfer whose priority has been increased due to expiration of the contention counter or a transfer that is
fixed as the highest-priority transfer to a given resource.
2.5
Advanced Event Triggering (AET)
The C64x+ Megamodule supports Advanced Event Triggering (AET). This capability can be used to
debug complex problems as well as understand performance characteristics of user applications. AET
provides the following capabilities:
•
•
•
•
Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
Counters: count the occurrence of an event or cycles for performance monitoring.
State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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Chapter 3
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System Memory
Topic
3.1
3.2
..................................................................................................
Page
Memory Map ............................................................................. 28
Memory Interfaces Overview ...................................................... 29
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Memory Map
3.1
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Memory Map
See your device-specific data manual for memory-map information.
3.1.1 DSP Internal Memory (L1P, L1D, L2)
This section describes the configuration of the DSP internal memory in the DM647/DM648 that consists of
L1P, L1D, and L2. In the DM647/DM648:
• L1P memory: The L1P controller allows you to configure part or all of the L1P RAM as normal program
RAM or as direct mapped cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB
of the RAM.
• L1D memory: The L1D controller allows you to configure part of the L1D RAM as normal data RAM or
as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
• L2 memory: The L2 controller allows you to configure part or all of the L2 RAM as normal RAM or as
cache. You can configure cache sizes of 0 KB, 32 KB, 64 KB, 128 KB, or 256 KB of the RAM.
See the device-specific data manual for the exact amount of RAM/cache. See the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871) for information on how to configure the cache.
3.1.2 External Memory
The DSP has access to the following external memories:
• DDR2 synchronous DRAM
• Asynchronous EMIF/NOR
• Synchronous EMIF
The external memory controller (EMC) facilitates DSP access to these memories in the C64x+
Megamodule. The following external memories are accessible to the DSP:
• DDR2 port
• Asynchronous EMIF
• Synchronous EMIF
For the memory-map locations of these external memories, See the memory-map section of the
device-specific data manual.
3.1.3 Internal Peripherals
The following internal peripherals are accessible to the DSP:
• Power-down controller (PDC)
• Interrupt controller (INTC)
For more information on the internal peripherals, see the TMS320C64x+ DSP Megamodule Reference
Guide (SPRU871).
3.1.4 Device Peripherals
The DSP has access to all peripherals on the device. See the device-specific data manual for the full list
of peripherals.
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3.2
Memory Interfaces Overview
Memory Interfaces Overview
This section describes the different memory interfaces of DM647/DM648. The device supports several
memory and external device interfaces, including the following:
• DDR2 synchronous DRAM
• Asynchronous EMIF/NOR Flash
• Synchronous EMIF SBSRAM and ZBTSRAM
3.2.1 DDR2 External Memory Interface
The DDR2 external memory interface (EMIF) port is a dedicated interface to DDR2 SDRAM. It supports
JESD79D-2A standard compliant DDR2 SDRAM devices and can support either 16-bit or 32-bit interfaces.
DDR2 SDRAM plays a key role in a DM647/DM648-based system. Such a system is expected to require a
significant amount of high-speed external memory for the following:
• Buffering input image data from sensors or video sources
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable firmware for DSP
3.2.2 External Memory Interface
The DM647/DM648 external memory interface (EMIF) provides a 16-bit data bus, an address bus width of
up to 25-bits, and 2 dedicated chip selects, along with memory control signals.
The EMIFA signals are multiplexed with other peripheral signals on the device. See the device-specific
data manual for details on pin multiplexing.
3.2.2.1
Asynchronous EMIF Interface
The asynchronous EMIF (EMIFA) interface provides asynchronous EMIF interfaces. Two chip selects are
provided. Each is individually configurable to provide asynchronous EMIF.
• The asynchronous EMIF mode supports asynchronous devices (RAM, ROM, and NOR Flash)
• 128MB asynchronous address range over 2 chip selects (64MB each)
• Supports 16-bit data bus width
• Programmable asynchronous cycle timings
• Supports extended waits
• Supports Select Strobe mode
• Supports TI DSP HPI interface
• Supports booting DM647/DM648 from CS2 (SRAM/NOR Flash)
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Chapter 4
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Device Clocking
Topic
4.1
4.2
..................................................................................................
Page
Overview .................................................................................. 32
Clock Domains ......................................................................... 33
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Overview
4.1
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Overview
The DM647/DM648 requires two primary reference clocks. The primary reference clocks are driven by
external oscillators. An external oscillator from 25 MHz to 66.6 MHz can be used as CLKIN1, which
generates the clocks for the DSP, peripherals, DMA. But for some boot options to work, the device must
boot up with 27-MHz CLKIN1. See Using the TMS320DM647/DM648 Bootloader Application Report
(SPRAAJ1) for more details. A 26.66-MHZ external oscillator at the CLKIN2 pin is recommended for the
DDR PLL, which generates the clocks for DDR.
For detailed specifications on clock frequency and voltage requirements, see the TMS320DM647,
TMS320DM648 Digital Media Processor Data Manual (SPRS372).
There are two clocking modes:
• PLL Bypass Mode - power saving (device defaults to this mode)
• PLL Mode - PLL multiplies input clock up to the desired operating frequency
The clock of the major chip subsystems must be programmed to operate at fixed ratios of the primary
system/DSP clock frequency within each mode, as shown in Table 4-1. The DM647/DM648 clocking
architecture is shown in Figure 4-1.
Table 4-1. System Clock Modes and Fixed Ratios for Core Clock Domains
Subsystem
SYSCLKS
Fixed Ratio vs. DSP
frequency
DSP
CLKDIV1
Peripherals (CLKDIV3 Domain)
CLKDIV3
SYSCLK1
1:3
CLKDIV4 1
SYSCLK2
1:4
Emulation/Trace
Peripherals (CLKDIV6 Domain)
-
CLKDIV6
SYSCLK3
1:6
Internal EMIFA Clock
CLKDIV4 0
SYSCLK4
1:4
VICP cop_clk/2
CLKDIV4 2
SYSCLK5
1:4
CLKDIV2
SYSCLK6
1:2
VICP cop_clk
32
Core Clock Domain
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4.2
Clock Domains
4.2.1 Core Domains
The core domains see the clock domains for all of the internal processing elements of the DM647/DM648,
such as the DSP/EDMA/peripherals, etc. All internal communications between DSP and modules operate
at core domain clock frequencies. All of the core clock domains are synchronous to each other, come from
a single PLL (PLL1), have aligned clock edges, and have fixed divide by ratio requirements, as shown in
Table 4-1 and Figure 4-1. It is user's responsibility to ensure the fixed divide ratios between these core
clock domains are achieved.
The DSP is in the CLKDIV1 domain and receives the PLL1 frequency directly from PLLC1 output. The
DSP has internal clock dividers that it uses to create the DSP ÷ 3 clock frequency to communicate with
other components on-chip.
Modules in the CLKDIV3 domain (EDMA, VP, CLKDIV3 domain peripherals) must run at 1/3 the DSP
frequency.
Modules in the CLKDIV6 domain (for example, CLKDIV6 domain peripherals) must run at 1/6 the DSP
frequency.
Modules in the CLKDIV2 domain (for example, VICP) must run at 1/2 the DSP frequency.
Modules in the CLKDIV4 2 domain (for example, VICP) must run at 1/4 the DSP frequency.
Modules in the CLKDIV4 0 domain (for example, EMIFA) must run at 1/4 the DSP frequency.
Modules in the CLKDIV4 1 domain (for example, Emulation/Trace) must run at 1/4 the DSP frequency.
Modules in the CLKDIV4 2 domain (for example, VICP cop_clk/2) must run at 1/4 the DSP frequency.
Modules in the CLKDIV2 domain (for example, VICP cop_clk) must run at 1/2 the DSP frequency.
See the TMS320DM647, TMS320DM648 Digital Media Processor Data Manual (SPRS372) for the core
clock domain for each peripheral.
Figure 4-1. Clocking Diagram
PLL controller 1
CLKIN1
PLLDIV3(/6)
PLLDIV2(/4)
PLLDIV4(/4)
PLLDIV5(/4)
PLLDIV6(/2)
PLLDIV1(/3)
SYSREFCLK
SYSCLK3
SYSCLK2
SYSCLK4
DSP Subsystem
PCI
Emulation/trace
HPI
EMIFA
UART
SYSCLK5
SYSCLK6
SYSCLK1
McASP
VICP
GPIO
Video port (x5)
TIMER(x4)
EDMA
VLYNQ
SCR
SPI
DDR2 Memory
Controller
I2C
DDR2CLK
CLKIN2
PLL
controller 2
REFCLK P/N
SerDes PLL
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VIC
DDR2 PHY(/2)
ESS
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4.2.2 Core Frequency Flexibility
The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks are
flexible, to a degree, within the limitations specified in the device-specific data manual. All of the following
frequency ranges and multiplier/divider ratios in the data manual must be adhered to:
• Input clock frequency range (CLKIN1, CLKIN2)
• PLL1 multiplier (PLLM) range
• PLL1 output (PLLOUT) frequency range
• Maximum device speed
As specified in the data manual, the PLLC1 can be driven by any input ranging from 25 to 66.6 MHZ and
the PLLC2 can be driven by 26.6 MHZ.
Table 4-2 shows some example PLL1 multiplier and divider settings assuming CLKIN1 frequency of 36
MHZ. The Applicable to Device Core Voltage column indicates whether the setting is allowed for a given
device core voltage. You must ensure the SYSREFCLK frequency does not exceed the speed grade of
the device. For example, for a device rated at 720 MHZ speed grade, SYSREFCLK must not exceed 720
MHZ.
Table 4-2. Example PLL1 Frequencies and Dividers (36 MHZ Clock Input)
CLKDIV2 Domain
(SYSCLK6)
CLKDIV3 Domain
(SYSCLK1)
CLKDIV4 Domain
(SYSCLK2)
CLKDIV6 Domain
(SYSCLK3)
Applicable
to Device
Core
Voltage
PLL1
Multiplier
PLL1
PLLOUT
Freq
(MHZ)
Divider (1)
Freq
(MHZ)
Divider (1)
Freq
(MHZ)
Divider (1)
Freq
(MHZ)
Divider (1)
Freq
(MHZ)
1.2 V
20
720
2
360.0
3
240.0
4
180.0
6
120.0
YES
21
756
2
378.0
3
252.0
4
189.0
6
126.0
YES
22
792
2
396.0
3
264.0
4
198.0
6
132.0
YES
23
828
2
414.0
3
276.0
4
207.0
6
138.0
YES
24
864
2
432.0
3
288.0
4
216.0
6
144.0
YES
25
900
2
450.0
3
300.0
4
225.0
6
150.0
YES
(1)
The RATIO bit in PLLDIVn is programmed as Divider - 1. For example, for a SYSCLK1 divider of 3, you should program
PLLDIV1.RATIO = 2, PLLDIV2.RATIO = 3, PLLDIV3.RATIO = 5, PLLDIV4.RATIO = 3, PLLDIV5.RATIO = 3,
PLLDIV6.RATIO = 1.
4.2.3 DDR2/EMIF Clock
The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from the
PLL2. This dedicated clock allows the reduction of the core clock rates to save power while maintaining
the required minimum clock rate (266.5 MHZ) for DDR2. PLL2 must be configured to output a 2 × clock to
the DDR2 PHY interface.
You must adhere to all of the following frequency ranges and multiplier/divider ratios in the device-specific
data manual when configuring PLL2:
• Input clock frequency range (CLKIN2)
• PLL2 multiplier (PLLM) is fixed
• PLL2 controller only operates in PLL mode.
Table 4-3 shows some PLL2/DDR2 clock rates assuming a CLKIN2 frequency of 26.66 MHZ.
Table 4-3. Example PLL2 Frequencies (Core Voltage = 1.2 V)
34
PLL2 Multiplier
PLL2 PLLOUT Freq (MHZ)
PHY [2× clock] (MHZ)
DDR2 Clock (MHZ)
20
533
533
266.5
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4.2.4 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the core frequency domain by definition.
Table 4-4 lists peripherals with external I/O interface, and their I/O domain clock/frequency. It also shows
the core clock domain as a reference to show the core clock used for internal communications. See
Section 4.2.1 for more details on core clock domains. See the device-specific data manual for the exact
I/O clock frequency supported on the device.
Table 4-4. Peripheral I/O Domain Clock
I/O (External) Domain Clock Source Options
Peripheral
I/O Domain Clock
Frequency
Internal Clock
Source
External Clock Source
Core Clock
Domain
DDR2
266.5 MHZ
PLLC2 SYSCLK1
—
CLKDIV1
VP0-4
27 MHz (BT656 Mode)
—
VP0CLK0, VP0CLK1, VP1CLK0,
VP1CLK1, VP2CLK0, VP2CLK1,
VP3CLK0, VP3CLK1, VP4CLK0,
VP4CLK1
CLKDIV3
80 MHz (Capture Mode)
110 MHz (Display Mode)
PCI
—
PCLK
CLKDIV6
Ethernet Subsystem 125 MHZ
33/66 MHZ
—
REFCLKN, REFCLKP
TXBCLK
VLYNQ
up to 80 MHZ
PLLC1 SYSCLK3
VCLK
CLKDIV6
McASP
up to 40 MHZ
PLLC1 SYSCLK3
AHCLKX, AHCLKR, ACLKX,
ACLKR
CLKDIV6
SPI
up to 12 MHZ
PLLC1 SYSCLK3
-
CLKDIV6
GPIO
NA (asynchronous
interface)
—
—
CLKDIV6
EMIFA
NA (asynchronous
interface)
SYSCLK4 /2
—
CLKDIV6
AECLKIN
CLKDIV6
HPI
up to 166 MHZ
NA (asynchronous
interface)
—
—
CLKDIV6
I2C
up to 400 kHz
PLLC1 SYSCLK3
SCL
CLKDIV6
Timer
output up to 1/2 CLKIN
frequency
PLLC1 SYSCLK3
T0INP12 (Timer 0), T1INP12
(Timer 1)
CLKDIV6
UART
NA
—
—
CLKDIV6
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36
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Chapter 5
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PLL Controller
Topic
5.1
5.2
5.3
5.4
..................................................................................................
PLL Module ..............................................................................
PLL1 Control ............................................................................
PLL2 Control ............................................................................
PLL Controller Registers ............................................................
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43
44
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PLL Module
5.1
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PLL Module
The device has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1
provides clocks (through various dividers) to most of the components of the device. PLL2 is dedicated to
the DDR2 port. The typical reference clock is the 36 MHZ clock input, as mentioned in Chapter 4.
The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK[1:n]
Various dividers that can be used on the DM647/DM648 are as follows:
• PLL Controller Dividers (for SYSCLK[1:n]): PLLDIV1, ..., PLLDIVn
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software-programmable PLL Bypass: PLLEN
5.2
PLL1 Control
PLL1 supplies the primary system clock. Software controls the PLL1 operation through the system PLL
controller 1 (PLLC1) registers. The registers used in PLLC1 are listed in Section 5.4. Figure 5-1 shows the
customization of PLL1 in the DM647/DM648. The domain clocks are distributed to the core clock domains
(discussed in Section 4.2.1) and the rest of the device as follows:
• SYSCLK1: CLKDIV3 Domain
• SYSCLK2: CLKDIV4 1 Domain
• SYSCLK3: CLKDIV6 Domain
• SYSCLK4: CLKDIV4 0 Domain
• SYSCLK5: CLKDIV4 2 Domain
• SYSCLK6: CLKDIV2 Domain
The PLL1 multiplier is controlled by the PLLM bit of the PLL multiplier control register (PLLM). The PLL1
output clock may be divided using the PLLC1 SYSCLK divider PLLDIV4.
You are responsible for adhering to the PLLC1 frequency ranges and multiplier/divider ratios specified in
the data manual. See also Section 4.2.1 and Section 4.2.2.
By default, the system operates in bypass mode and the system clock is provided directly from the input
reference clock (CLKIN1 pin). Once the PLL is locked, you can switch the device to PLL mode operation
in software by setting the PLLEN bit in PLLCTL to 1. If the boot mode of the device is set to fast boot
(FASTBOOT = 1), the bootloader code in the Boot ROM follows the previous process to lock the PLL and
switches the device to PLL mode to accelerate the boot process. Therefore, coming out of a fast boot, the
device operates in PLL mode.
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Figure 5-1. PLL1 Structure
PLLOUT
CLKIN1
PLLEN
1
PLL
PLLDIV1 (/3)
SYSCLK1
(CLKDIV3 domain)
PLLDIV2 (/4)
SYSCLK2
(CLKDIV41 domain)
PLLDIV3 (/6)
SYSCLK3
(CLKDIV6 domain)
PLLDIV4 (/4)
SYSCLK4
(CLKDIV4 0 domain)
PLLDIV5 (/4)
SYSCLK5
(CLKDIV42 domain)
PLLDIV6 (/2)
SYSCLK6
(CLKDIV2 domain)
0
PLLM
5.2.1 Device Clock Generation
PLLC1 generates several clocks from the PLL1 output clock for use by processor and various modules.
These are summarized in Table 5-1.
Table 5-1. System PLLC1 Output Clocks
PLLC1 Output Clock
Used by
Default Divider
REFSYSCLK
DSP Subsystem
-
SYSCLK1
SCR, EDMA, DDR2 peripherals
/3
SYSCLK2
Emulation/Trace peripherals
/4
SYSCLK3
CLKDIV6 Domain peripherals
/6
SYSCLK4
EMIFA Domain peripheral
/4
SYSCLK5
VICP cop_clk/2 Domain peripherals
/4
SYSCLK6
VICP cop_clk Domain peripherals
/2
5.2.2 Steps for Changing PLL1/Core Domain Frequency
See the appropriate subsection on how to program the PLL1/Core Domain clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 5.2.2.1 to initialize the PLL.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 5.2.2.2 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers,
follow the sequence in Section 5.2.2.3.
Note that the PLL is powered up after the following device-level global resets:
• Power-on Reset (POR)
• Warm Reset (RESET)
• Max Reset
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PLL1 Control
5.2.2.1
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Initialization to PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below
to change PLL1 frequencies. The recommendation is to stop all peripheral operation before changing the
PLL1 frequency, with the exception of the C64x+ DSP and DDR2. The C64x+ DSP must be operational to
program the PLL controller. DDR2 operates off of the clock from PLLC2.
Step 1. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 4 CLKIN1 cycles to ensure PLLC switches to bypass mode properly.
Step 2. Set the PLLRST bit in PLLCTL to 1 (reset PLL).
Step 3. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
Step 4. Wait for PLL stabilization time. See the device-specific data manual for PLL stabilization time.
Step 5. Program the required multiplier value in PLLM.
Step 6. Program PLLDIV4.RATIO=0x1 register to change the SYSCLK4 divide value:
a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is
currently in progress.
b. Program the RATIO field in PLLDIV4.RATIO = 0x1. See the device-specific data manual
for more details on Clock Domains. In addition, make sure in this step you leave the
PLLDIV4.D4EN bit set (default).
c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this
transition, SYSCLK4 is paused momentarily.
d. Wait for N number of PLLDIVn source clock cycles to ensure divider changes have
completed. See Section 5.2.2.3 for the formula on calculating the number of cycles N.
e. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
Step 7. Wait for PLL to reset properly. See the device-specific data manual for PLL reset time.
Step 8. Clear the PLLRST bit in PLLCTL to 0 to bring the PLL out of reset.
Step 9. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
Step 10. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
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5.2.2.2
PLL1 Control
Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time
is previously met (step 4 in Section 5.2.2.1), follow this procedure to change PLL1 multiplier. The
recommendation is to stop all peripheral operation before changing the PLL multiplier, with the exception
of the C64x+ DSP and DDR2. The C64x+ DSP must be operational to program the PLL controller. DDR2
operates off of the clock from PLLC2.
Step 1. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 4 CLKIN1 cycles to ensure PLLC switches to bypass mode properly.
Step 2. Set the PLLRST bit in PLLCTL to 1 (reset PLL).
Step 3. Program the required multiplier value in PLLM.
Step 4. Program PLLDIV4.RATIO = 0x1 register to change the SYSCLK4 divide value:
a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is
currently in progress.
b. Program the RATIO field in PLLDIV4.RATIO = 0x1. See the device-specific data manual
for more details on Clock Domains. In addition, make sure you leave the PLLDIV4.D4EN
bit set (default) in this step.
c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this
transition, SYSCLK4 is paused momentarily.
d. Wait for N number of PLLDIVn source clock cycles to ensure divider changes have
completed. See Section 5.2.2.3 for the formula on calculating the number of cycles N.
e. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
Step 5. Wait for PLL to reset properly. See the device-specific data manual for PLL reset time.
Step 6. Clear the PLLRST bit in PLLCTL to 0 to bring the PLL out of reset.
Step 7. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
Step 8. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
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PLL1 Control
5.2.2.3
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Changing SYSCLK Dividers
This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider
change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in
PLLCMD) to initiate the divider change. The recommendation is to stop all peripheral operation before
changing the SYSCLK dividers, with the exception of the C64x+ DSP and DDR2. The C64x+ DSP must
be operational to program the PLL controller. DDR2 operates off of the clock from PLLC2.
Step 1. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is
currently in progress.
Step 2. Program the PLLDIV4.RATIO = 0x1. See the device-specific data manual for more details on
Clock Domains. In addition, make sure in this step you leave the PLLDIV4.D4EN bit set
(default).
Step 3. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition,
SYSCLK4 is paused momentarily.
Step 4. Wait for N number of PLLDIVn source clock cycles to ensure divider changes have
completed. Use the following formula for calculating the number of cycles N.
Step 5. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
The following formula should be used to calculate the number of PLLDIVn source clock cycles:
N = (2 × Least Common Multiple [LCM] of all the old SYSCLK divide values) + 50 cycles overhead
Example 5-1. Calculating Number of Clock Cycles N
This example calculates the number of clock cycles N.
• Settings before divider change:
– PLLDIV4.RATIO = 3 (divide-by-4)
• New divider settings:
– PLLDIV4.RATIO = 1 (divide-by-2)
The least common multiple between the old divider values of /4 is /4; therefore, the number of cycles N
is:
N = (2 × 4) + 50 cycles overhead = 58 PLLDIVn source clock cycles
If PLLC1 is in PLL mode (PLLCTL.PLLEN = 1), the PLLDIVn source clock is the PLL1 output clock. If
PLLC1 is in PLL bypass mode (PLLCTL.PLLEN = 0), the PLLDIVn source clock is the device clock
source CLKIN1.
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5.3
PLL2 Control
PLL2 provides the clock from which the DDR2 memory controller clocks are derived. The DDR PLL
controller 2 (PLLC2) controls PLL2, which accepts the clock from CLKIN2. Figure 5-2 shows the
customization of PLL2 in the DM647/DM648. The PLL2 clocks are distributed to the device as follows:
• PLLOUT: DDR2 PHY
PLL2 supplies the DDR2 memory controller clock. PLL2 Controller operates only in PLL mode. The
registers used in PLLC2 are listed in Section 5.4.
Figure 5-2. PLL2 Structure in the TMS320DM647/DM648
PLLOUT
CLKIN2
PLL
DDR2PHY(/2)
DDR2
Memory
Controller
DDR2CLK
PLLM
5.3.1 Device Clock Generation
PLLC2 generates clocks from the PLL2 output clock for use by the DDR2 memory controller module.
These are summarized in Table 5-2.
Table 5-2. DDR PLLC2 Output Clocks
Output Clock
Used by
Default
Divider
PLLOUT
DDR Phy
-
The PLLOUT output clock fed to DDR2 PHY, PLLOUT (DDR2 PHY clock) is divided by 2 and generates
DDR2 clock . Assuming a 26.6 MHZ CLKIN2 and the PLL2 multiplier of ×20, this results in a 533 MHZ
DDR Phy clock (266 MHZ DDR2 Clock).
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PLL Controller Registers
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PLL Controller Registers
Table 5-3 lists the base address and end address for the PLL controllers. Table 5-4 lists the
memory-mapped registers for the PLL and reset controller. See the device-specific data manual for the
memory address of these registers.
Table 5-3. PLL and Reset Controller List
PLL and Reset Controller
Base Address
End Address
Size
PLLC1
020E 0000h
020E 0400h
400h
PLLC2
0212 0000h
0212 0400h
400h
Table 5-4. PLL and Reset Controller Registers
Offset
(1)
44
Acronym
Register Description
Section
00h
PID
Peripheral ID Register
Section 5.4.1
E4h
RSTYPE (1)
Reset Type Status Register
Section 5.4.2
100h
PLLCTL
PLL Control Register
Section 5.4.3
110h
PLLM
PLL Multiplier Control Register
Section 5.4.4
114h
PREDIV (1)
PLL Pre-Divider Control Register
Section 5.4.5
(1)
11Ch
PLLDIV2
PLL Controller Divider 2 Register (SYSCLK2)
Section 5.4.6
138h
PLLCMD (1)
PLL Controller Command Register
Section 5.4.8
13Ch
PLLSTAT (1)
PLL Controller Status Register
Section 5.4.9
140h
ALNCTL (1)
PLL Controller Clock Align Control Register
Section 5.4.11
144h
DCHANGE (1)
PLLDIV Ratio Change Status Register
Section 5.4.12
150h
SYSTAT (1)
PLL Controller System Clock Status Register
Section 5.4.10
160h
PLLDIV4 (1)
PLL Controller Divider 4 Register (SYSCLK4)
Section 5.4.7
not supported for PLL2.
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5.4.1 Peripheral ID Register (PID)
The peripheral ID register (PID) is shown in Figure 5-3 and described in Table 5-5.
Figure 5-3. Peripheral ID Register (PID)
31
24
23
16
Reserved
TYPE
R-0
R-1h
15
8
7
0
CLASS
REV
R-8h
R-2h
LEGEND: R = Read only; -n = value after reset
Table 5-5. Peripheral ID Register (PID) Field Descriptions
Bit
Field
31-24
Reserved
23-16
TYPE
Value
0
CLASS
7-0
REV
Reserved
Peripheral type
1h
15-8
Description
PLLC
Peripheral class
8h
Current class
Peripheral revision
2h
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5.4.2 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) is shown in Figure 5-4 and described in Table 5-6. It latches
cause of the last reset. Although the reset value of all bits is 0 after coming out of reset, one bit is set to 1
to indicate the cause of the reset.
Figure 5-4. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
4
SRST
MRST
XWRST
POR
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-4
46
Field
Reserved
Value
0
Description
Reserved
3
SRST
0-1
System reset. If 1, system reset was the reset to occur that is of highest priority.
2
MRST
0-1
Maximum reset. If 1, maximum reset was the reset to occur that is of highest priority.
1
XWRST
0-1
External warm reset. If 1, warm reset (RESET) was the last reset to occur that is of highest priority.
0
POR
0-1
Power on reset. If 1, power on reset (POR) was the last reset to occur that is of highest priority.
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5.4.3 PLL Control Register (PLLCTL)
The PLL control register (PLLCTL) is shown in Figure 5-5 and described in Table 5-7.
Figure 5-5. PLL Control Register (PLLCTL)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
8
Reserved
7
6
PLLENSRC
PLLDIS
PLLRST
Rsvd
PLLPWRDN
PLLEN
R-0
R-1h
R/W-1
R/W-0
R/W-1
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-7. PLL Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared to 0 before PLLEN will have any effect.
4
PLLDIS
3
0
PLL disable is de-asserted.
1
PLL disable is asserted. PLL output is disabled and not toggling.
PLLRST
2
Reserved
1
PLLPWRDN
0
Asserts DISABLE to PLL
Asserts RESET to PLL if supported.
0
PLL reset is not asserted.
1
PLL reset is asserted. See the device-specific data manual for the PLL reset time required.
0
Reserved
PLL power-down. After powering up the PLL (PLLPWRDN 1 to 0 transition), you must wait for the
PLL to stabilize. See the device-specific data manual for the PLL stabilization time.
0
PLL operational
1
PLL power-down
PLLEN
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PLL mode enable
0
Bypass mode
1
PLL mode, not bypassed
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5.4.4 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 5-6 and described in Table 5-8.
Figure 5-6. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, PLLM defaults to 13h (PLL1 multiply by 20); for PLLC2, PLLM defaults to 13h (PLL2 multiply by 20), PLLM field of PLLC2 is
read-only.
Table 5-8. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
PLLM
0
0-1Fh
Description
Reserved
PLL multiplier select. Multiplier value = PLLM + 1. For example, PLLM = 19 (13h) means multiply by 20.
See the device-specific data manual for valid multiplier values for each PLL.
5.4.5 PLL Pre-Divider Control Register (PREDIV)
The PLL Pre-Divider control register (PREDIV) is shown in Figure 5-7 and described in Table 5-9.
Figure 5-7. PLL Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
3
2
1
PREDEN
Reserved
RATIO
R-1
R-0
R/W-0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-9. PLL Controller Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
PREDEN
48
14-3
Reserved
2-0
RATIO
PLL Controller
Value
0
Description
Reserved
Pre Divider enable.
0
Pre Divider is disabled.
1
Pre Divider is enabled.
0
Reserved
0-7h
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 2 means divide by 3.
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5.4.6 PLL Controller Divider 2 Register (PLLDIV2)
The PLL controller divider 2 register (PLLDIV2) is shown in Figure 5-8 and described in Table 5-10.
Divider 2 controls divider for SYSCLK2.
Figure 5-8. PLL Controller Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
3
2
0
D2EN
Reserved
RATIO
R-1
R-0
R/W-3h (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, RATIO defaults to 3h (PLL1 divide by 4); Not used by PLLC2.
Table 5-10. PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-3
Reserved
2-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-7h
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Divider ratio. Divider value = RATIO + 1. For example, RATIO = 3 means divide by 4.
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5.4.7 PLL Controller Divider 4 Register (PLLDIV4)
The PLL controller divider 4 register (PLLDIV4) is shown in Figure 5-9 and described in Table 5-11.
Divider 4 controls divider for SYSCLK4. PLLDIV4 is not used on PLLC2.
Figure 5-9. PLL Controller Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
3
2
0
D4EN
Reserved
RATIO
R-1
R-0
R/W-3h (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, RATIO defaults to 3h (PLL1 divide by 4);
Table 5-11. PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
50
Field
Reserved
Value
0
D4EN
14-3
Reserved
2-0
RATIO
PLL Controller
Description
Reserved
Divider 4 enable.
0
Divider 4 is disabled.
1
Divider 4 is enabled.
0
Reserved
0-7h
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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5.4.8 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) is shown in Figure 5-10 and described in Table 5-12.
PLLCMD contains the command bit for the GO operation. Writes of 1 initiate command. Writes of 0 clear
the bit, but have no effect.
Figure 5-10. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-12. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for SYSCLKx loading new dividers and phase alignment.
0
Clear bit (no effect).
1
Initiate SYSCLKx phase alignment.
5.4.9 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 5-11 and described in Table 5-13.
Figure 5-11. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
STABLE
Reserved
GOSTAT
R-0
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-13. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation.
0
GO operation is not in progress.
1
GO operation is in progress.
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5.4.10 PLL Controller SYSCLK Status Register (SYSTAT)
The PLL controller SYSCLK status register (SYSTAT) is shown in Figure 5-12 and described in
Table 5-14. SYSTAT shows the enable/disable status of SYSCLKs.
Figure 5-12. PLL Controller SYSCLK Status Register (SYSTAT)
31
16
Reserved
R-0
15
6
Reserved
R-0
5
4
3
2
1
0
SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON
R-1 (1)
R-1 (1)
R-1 (1)
R-1 (1)
R-1 (1)
R-1 (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, this bit defaults to 1.
Table 5-14. PLL Controller SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Reserved
5
SYS6ON
4
3
2
1
0
52
Field
31-6
Value
0
Reserved
SYS6ON on
0
Clock is gated.
1
Clock is on.
SYS5ON
SYS5ON on
0
Clock is gated.
1
Clock is on.
SYS4ON
SYS4ON on
0
Clock is gated.
1
Clock is on.
SYS3ON
SYS3ON on
0
Clock is gated.
1
Clock is on.
SYS2ON
SYS2ON on
0
Clock is gated.
1
Clock is on.
SYS1ON
PLL Controller
Description
SYS1ON on
0
Clock is gated.
1
Clock is on.
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5.4.11 PLL Controller Clock Align Control Register (ALNCTL)
The PLL controller clock align control register (ALNCTL) is shown in Figure 5-13 and described in
Table 5-15. ALNCTL indicates which SYSCLKs need to be aligned for proper device operation.
Figure 5-13. PLL Controller Clock Align Control Register (ALNCTL)
31
16
Reserved
15
5
4
3
2
1
0
Reserved
6
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-0
R-1 (1)
R-1 (1)
R-1 (1)
R-1 (1)
R-1 (1)
R-1 (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, this bit defaults to 1.
Table 5-15. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-6
5
4
3
2
1
0
Field
Reserved
Value
0
ALN6
Description
Reserved
SYSCLK6 needs to be aligned to others selected in this register.
0
SYSCLK6 does not need to be aligned.
1
SYSCLK6 does need to be aligned.
ALN5
SYSCLK5 needs to be aligned to others selected in this register.
0
SYSCLK5 does not need to be aligned.
1
SYSCLK5 does need to be aligned.
ALN4
SYSCLK4 needs to be aligned to others selected in this register.
0
SYSCLK4 does not need to be aligned.
1
SYSCLK4 does need to be aligned.
ALN3
SYSCLK3 needs to be aligned to others selected in this register.
0
SYSCLK3 does not need to be aligned.
1
SYSCLK3 does need to be aligned.
ALN2
SYSCLK2 needs to be aligned to others selected in this register.
0
SYSCLK2 does not need to be aligned.
1
SYSCLK2 does need to be aligned.
ALN1
SYSCLK1 needs to be aligned to others selected in this register.
0
SYSCLK1 does not need to be aligned.
1
SYSCLK1 does need to be aligned
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5.4.12 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLDIV ratio change status register (DCHANGE) is shown in Figure 5-14 and described in
Table 5-16. DCHANGE indicates if the SYSCLK divide ratio has been modified.
Figure 5-14. PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 5-16. PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-6
5
4
3
2
1
0
54
Field
Reserved
Value
0
SYS6
Reserved
SYSCLK6 divide ratio is modified.
0
SYSCLK6 divide ratio is not modified.
1
SYSCLK6 divide ratio is modified.
SYS5
SYSCLK5 divide ratio is modified.
0
SYSCLK5 divide ratio is not modified.
1
SYSCLK5 divide ratio is modified.
SYS4
SYSCLK4 divide ratio is modified.
0
SYSCLK4 divide ratio is not modified.
1
SYSCLK4 divide ratio is modified.
SYS3
SYSCLK3 divide ratio is modified.
0
SYSCLK3 divide ratio is not modified.
1
SYSCLK3 divide ratio is modified.
SYS2
SYSCLK2 divide ratio is modified.
0
SYSCLK2 divide ratio is not modified.
1
SYSCLK2 divide ratio is modified.
SYS1
PLL Controller
Description
SYSCLK1 divide ratio is modified.
0
SYSCLK1 divide ratio is not modified.
1
SYSCLK1 divide ratio is modified.
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Power and Sleep Controller
Topic
6.1
6.2
6.3
6.4
6.5
6.6
6.7
..................................................................................................
Introduction..............................................................................
Power Domain and Module Topology ..........................................
Power Domain and Module States ...............................................
Executing State Transitions .......................................................
IcePick Emulation Support in the PSC .........................................
PSC Interrupts ..........................................................................
PSC Registers ..........................................................................
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57
58
59
60
60
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Introduction
6.1
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Introduction
The Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off,
clock on/off, and reset. The DM647/DM648 only utilizes the clock gating feature of the PSC for power
savings. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC
contains memory mapped registers, PSC interrupt control, and a state machine for each
peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset
control. Figure 6-1 shows how the PSC is integrated on the device. Many of the operations of the PSC are
transparent to software, such as power-on and hard reset operations. However, the PSC provides you
with an interface to control several important power, clock, and reset operations. The power, clock, and
reset operations are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off and resets
• Provides a software interface to:
– Control module clock ON/OFF
– Control module resets
– Control DSP local reset (CPU reset)
• Supports IcePick emulation features: power, clock, and reset
Figure 6-1. Power and Sleep Controller (PSC) Integration
PLLC
clks
Emulation
POR
RESET
VDD
56
Power and Sleep Controller
PSC
DSP
DSP clock
DSP module reset
DSP local reset
DSP power
Always on
domain
MODx
Peripheral clock
Peripheral module reset
Peripheral power
Ethernet
subsystem
domain
ESS clock
ESS module reset
ESS power
ESS
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6.2
Power Domain and Module Topology
The DM647/DM648 includes two power domains--the AlwaysOn power domain(Power Domain 0) and
Ethernet Subsystem power domain(Power Domain 1). The AlwaysOn power domain and Ethernet
Subsystem power domain are always ON when the chip is on. The AlwaysOn domain and Ethernet
Subsystem domain are powered by the VDD pins of the DM647/DM648 (see the device-specific data
manual). All of the modules reside within the AlwaysOn power domain except SGMII reside within the
Ethernet Subsystem power domain. Table 6-1 lists all the possible peripherals on the DM647/DM648, their
LPSC assignments, and default module states. See the device-specific data manual for the peripherals
available on a given device. The module states are defined in Section 6.3.2.
Table 6-1. DM647/DM648 Default Module Configuration
LPSC
Number
Module Name
Default Module State (MDSTAT.STATE)
0
EDMACC
Enable
1
Reserved
—
2
Reserved
—
3
Reserved
—
4
Reserved
—
5
Reserved
SwRstDisable
6
Reserved
SwRstDisable
7
DDR2 Memory Controller
Enable
8
UHPI
Enable, if pin UHPIEN =1b
9
VLYNQ
SwRstDisable
10
GPIO
SwRstDisable
11
TIMER0
Enable
12
TIMER1
Enable
13
Reserved
—
14
Reserved
—
15
Reserved
—
16
Reserved
—
17
SPI
SwRstDisable
18
I2C
SwRstDisable
19
PCI
SwRstDisable, if pin UHPIEN = 1b
20
VP0
SwRstDisable
21
VP1
SwRstDisable
22
VP2
SwRstDisable
23
VP3
SwRstDisable
24
VP4
SwRstDisable
25
EMIFA
SwRstDisable, if pins BOOTMODE[3:0] ≠ 0100b
26
TIMER2
Enable
27
TIMER3
Enable
28
VIC
SwRstDisable
29
McASP
SwRstDisable
30
UART
SwRstDisable
31
VICP
Enable
32
CHIP REGISTERS
Enable
SwRstDisable, if pin UHPIEN = 0b
Enable, if pin UHPIEN = 0b
Enable, if pins BOOTMODE[3:0] = 0100b
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Table 6-1. DM647/DM648 Default Module Configuration (continued)
6.3
LPSC
Number
Module Name
Default Module State (MDSTAT.STATE)
33
C64x+ CPU
Enable
34
Ethernet 3PSW
Enable
Power Domain and Module States
Table 6-1 shows the state of each module after chip Power-on Reset (POR), Warm Reset (RESET), or
Max Reset. These states are defined in the following sections.
6.3.1 Power Domain States
A power domain can only be in one of two states: ON or OFF, defined as follows:
• ON: power to the power domain is on.
• OFF: power to the power domain is off.
In the DM647/DM648, the AlwaysOn Power Domain and Ethernet Subsystem Power Domain are always
in the ON state when the chip is powered-on.
6.3.2 Module States
A module can be in one of four states: Disable, Enable, SyncReset, or SwRstDisable. These four states
correspond to combinations of module reset asserted or de-asserted and module clock on or off, as
shown in Table 6-2.
Table 6-2. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and
it has its clock on. This is the normal run-time state for a given
module.
Disable
De-asserted
Off
A module in the disable state has its module reset de-asserted and
it has its clock off. This state is typically used for disabling a module
clock to save power. The DM647/DM648 is designed in full static
CMOS, so when you stop a module clock, it retains the module's
state. When the clock is restarted, the module resumes operating
from the stopping point.
SyncReset
Asserted
On
A module in the SyncReset state has its module reset asserted and
it has its clock on. Generally, software is not expected to initiate this
state.
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset
asserted and it has its clock set to off. After initial power-on, most
modules are in the SwRstDisable state by default (see Table 6-1).
Generally, software is not expected to initiate this state.
Note:
Module Reset is defined to completely reset a given module, so that all hardware returns to
its default state. See Chapter 10 for more information on module reset.
For more information on power management, see Chapter 7.
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6.3.3 Local Reset
In addition to module reset (described in Section 6.3.2), the DSP CPU can be reset using a special local
reset. When DSP local reset is asserted, the DSPs internal memories (L1P, L1D, and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of the DSP subsystem, as the DSP
module reset would.
Module reset takes precedence over Local Reset; therefore, Local Reset is not useful when the DSP is in
SyncReset or SwRstDisable state.
See Chapter 10 for more information on local reset and scenarios where this can be used.
The procedures for asserting and de-asserting DSP local reset are as follows:
1. Clear the LRST bit in MDCTL33 to 0 (assert the DSP local reset).
2. Set the LRST bit in MDCTL33 to 1 (de-assert DSP local reset). If the DSP is in the enable state, it
immediately executes program instructions after reset is de-asserted.
6.4
Executing State Transitions
This section describes how to execute state transitions for device modules.
6.4.1 Power Domain State Transitions
The DM647/DM648 consists of two power domains--the AlwaysOn power domain(Power Domain 0) and
Ethernet Subsystem Power Domain(Power domain 1). AlwaysOn Power Domain and Ethernet Subsystem
Power Domain are always in the ON state when the chip is powered-on. You are not allowed to change
this power domain state to OFF.
6.4.2 Module State Transitions
This section describes the procedure for transitioning the module state. All DM647/DM648 modules are on
the AlwaysOn domain (Power Domain 0) except SGMII reside in Ethernet Subsystem power
domain(Power Domain 1).
Note that some peripherals have special programming requirements and steps you must take before you
can invoke the PSC module state transition. See the individual peripheral reference guide for more details.
For example, the DDR2 memory controller requires that you first place the DDR memory in self-refresh
mode before you invoke the PSC module state transition, if you want to maintain the memory content.
Note:
The following procedure is directly applicable for all modules, except for the DSP in the
DM647/DM648. To transition the DSP module state, you must be aware of several system
considerations.
The procedure for module state transitions is as follows (where n corresponds to the module):
1. Wait for the GOSTAT[0]/GOSTAT[1] bit in PTSTAT to clear to 0. You must wait for any previously
initiated transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), or Enable (3h).
Note:
You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[0]/GO[1] bit in PTCMD in a later step. GO[0] and
GOSTAT[0] for AlwaysOn power domain peripherals and GO[1] and GOSTAT[1] for Ethernet
Subsystem power domain peripheral.
3. Set the GO[0]/GO[1] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[0]/GOSTAT[1] bit in PTSTAT to clear to 0. The modules are safely in the new
states only after the GOSTAT[0]/GOSTAT[1] bit in PTSTAT is cleared to 0.
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IcePick Emulation Support in the PSC
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IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick aware emulation tools to have some control over
the state of power domains and modules. On the DM647/DM648, this IcePick support only applies to the
C64x+ CPU (Module number 33 in the AlwaysOn power domain 0).
In particular, Table 6-3 shows IcePick emulation commands recognized by the PSC. Except as noted
these commands apply to the C64x+ CPU on the DM647/DM648.
Table 6-3. IcePick Emulation Commands
Power On and
Enable
Features
Reset
Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the module’s
local reset.
Force Power
Allows emulation to force the power domain into an
on state. Not applicable on the DM647/DM648 as
AlwaysOn power domain and Ethernet Subsystem
power domain are always on.
Wait Reset
Allows emulation to keep local reset
asserted for an extended period of time
after software initiates local reset
de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block software
initiated local and module resets.
Note:
6.6
Power On and Enable Descriptions
When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTLn and the NEXT bit in
MDCTLn, as set by software.
PSC Interrupts
The PSC has an interrupt that is tied to the C64x+ interrupt controller (INTC). This interrupt is named
PSCINT in the interrupt map. The PSC interrupt is generated when certain IcePick emulation events
occur.
6.6.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Module State Emulation Event
• Module Local Reset Emulation Event
These interrupt events are summarized in Table 6-4 and described in more detail in this section.
Table 6-4. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Status Bit
MDCTLn
EMUIHB
Interrupt Condition
Interrupt occurs when the emulation alters the module state.
MDCTLn
EMURST
Interrupt occurs when the emulation alters the module's local reset.
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the
user-programmed state in the NEXT bit in MDCTLn. As discussed in Section 6.5, on the DM647/DM648,
IcePick support only applies to the C64x+ CPU (module 33), therefore the PSC interrupt condition only
applies to module 33.
The DM647/DM648 is a single-processor device. The C64x+ CPU must not program its own module state.
The C64x+ CPU module state can only be programmed by an external host (for example, PCI, HPI). As a
result, interrupt events listed in Table 6-4 can only occur in the scenario where an external host programs
the C64x+ CPU module state but the emulator alters that desired state.
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6.6.1.1
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in MDSTATn. In particular, a module state emulation event occurs under the following
conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state.
• When force active is asserted by emulation and module is not already in the enable state.
6.6.1.2
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in MDSTATn. In particular, a module local reset emulation event occurs under the
following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset.
• When wait reset is asserted by emulation.
• When block reset is asserted by emulation and software attempts to change the state of local reset.
6.6.2 Interrupt Registers
The PSC interrupt enable bits are the EMUIHBIE bit in MDCTL33 and the EMURSTIE bit in MDCTL33.
Note:
To interrupt the DSP, the power and sleep controller interrupt (PSCINT) must also be
enabled in the DSP interrupt controller. See Section 2.4.1 for more information on the
interrupt controller.
The PSC interrupt status bits are the M[33] bit in MERRPR1, the EMUIHB bit in MDSTAT33, and the
EMURST bit in MDSTAT33. The status bit in MERRPR1 is read by software to determine which module
has generated an emulation interrupt, and then software can read the corresponding status bits in
MDSTAT33 to determine which event caused the interrupt.
The PSC interrupt clear bit is the M[33] bit in MERRCR1.
The PSC interrupt evaluation bit is the ALLEV bit in INTEVAL. When set, this bit forces the PSC interrupt
logic to re-evaluate event status. If any events are still active (if any status bits are set) when the ALLEV
bit in INTEVAL is set to 1, the PSCINT is re-asserted to the DSP interrupt controller. Set the ALLEV bit in
INTEVAL before exiting your PSCINT interrupt service routine to ensure that you do not miss any PSC
interrupts.
See Section 6.7 for complete descriptions of all PSC registers.
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6.6.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt.
Step 1. Set the EMUIHBIE bit and the EMURSTIE bit in MDCTL33 to enable the interrupt events that
you want.
Note:
Step 2.
The PSC interrupt PSCINT is sent to the DSP interrupt controller when at least one enabled
event becomes active.
Enable the power and sleep controller interrupt (PSCINT) in the DSP interrupt controller. To
interrupt the DSP, PSCINT must be enabled in the DSP interrupt controller. See
Section 2.4.1 for more information.
The DSP enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the Mn bit in MERRPR1 to determine the source of the interrupt(s). Note that on the
DM647/DM648, only M[33] can cause an interrupt.
2. For each active event that you want to service:
a. Read the event status bits in MDSTAT33, depending on the status bits read in the previous step to
determine the event that caused the interrupt.
b. Service the interrupt as required by your application.
c. Write the M[33] bit in MERRCR1 to clear corresponding status.
d. Set the ALLEV bit in INTEVAL to 1. Setting this bit reasserts the PSCINT to the DSP interrupt
controller, if there are still any active interrupt events.
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6.7
PSC Registers
Table 6-5 lists the memory-mapped registers for the PSC. See the device-specific data manual for the
memory address of these registers.
Table 6-5. Power and Sleep Controller (PSC) Registers
Offset
Register
Description
0h
PID
Peripheral Revision and Class Information Register
Section 6.7.1
Section
18h
INTEVAL
Interrupt Evaluation Register
Section 6.7.2
44h
MERRPR1
Module Error Pending Register 1 (mod 32-34)
Section 6.7.3
54h
MERRCR1
Module Error Clear Register 1 (mod 32-34)
Section 6.7.4
120h
PTCMD
Power Domain Transition Command Register
Section 6.7.5
128h
PTSTAT
Power Domain Transition Status Register
Section 6.7.6
200h-204h
PDSTAT0-1
Power Domain Status n Register
Section 6.7.7
300h-304h
PDCTL0-1
Power Domain Control n Register
Section 6.7.8
800h-888h
MDSTAT0-34
Module Status n Register
Section 6.7.9
A00h-A88h
MDCTL0-34
Module Control n Register
Section 6.7.10
6.7.1 Peripheral Revision and Class Information Register (PID)
The peripheral revision and class information (PID) register is shown in Figure 6-2 and described in
Table 6-6.
Figure 6-2. Peripheral Revision and Class Information Register (PID)
31
30
29
28
27
16
SCHEME
Reserved
FUNC
R-1
R-0
R-482h
15
11
10
8
7
6
5
0
RTL
MAJOR
CUSTOM
MINOR
R-4h
R-1
R-0
R-5h
LEGEND: R = Read only; -n = value after reset
Table 6-6. Peripheral Revision and Class Information Register (PID) Field Descriptions
Bit
Field
31-30
SCHEME
29-28
Reserved
27-16
FUNC
15-11
RTL
Value
0-3h
0
MAJOR
7-6
CUSTOM
5-0
MINOR
Distinguishes between the old scheme and the current scheme. There is a spare bit to encode future
schemes.
Reserved
0-FFFh Indicates a software compatible module family.
RTL version.
4h
10-8
Description
Current RTL version.
Major revision.
1h
0-3h
Current major revision.
Indicates a special version for a particular device.
Minor revision.
5h
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6.7.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 6-3 and described in Table 6-7.
Figure 6-3. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 6-7. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
64
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt.
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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6.7.3 Module Error Pending Register 1 (mod 33) (MERRPR1)
The module error pending register 1 (mod 33) (MERRPR1) is shown in Figure 6-4 and described in
Table 6-8. Only the C64x+ DSP (module 33) can have an error condition, as it is the only module with
IcePick support. See Section 6.5 for more information.
Figure 6-4. Module Error Pending Register 1 (mod 33) (MERRPR1)
31
16
Reserved
R-0
15
8
7
6
2
1
0
M[33]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-8. Module Error Pending Register 1 (mod 33) (MERRPR1) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-2
Reserved
0
Reserved
1
0
M[33]
Reserved
Module interrupt status bit for module 33 (C64x+ DSP).
0
Module 33 does not have an error condition.
1
Module 33 has an error condition. See the module status 33 register (MDSTAT33) for the exact error
condition.
0
Reserved
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6.7.4 Module Error Clear Register 1 (mod 33) (MERRCR1)
The module error clear register 1 (mod 33) (MERRCR1) is shown in Figure 6-5 and described in
Table 6-9.
Figure 6-5. Module Error Clear Register 1 (mod 33) (MERRCR1)
31
16
Reserved
R-0
15
8
7
6
2
1
Reserved
Reserved
M[33]
R-0
R-0
W-0
0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 6-9. Module Error Clear Register 1 (mod 33) (MERRCR1) Field Descriptions
Bit
Value
Description
Reserved
0
Reserved
7-2
Reserved
0
Reserved
1
0
66
Field
31-8
M[33]
Reserved
Clears the interrupt status bits set in the corresponding module error pending register 1 (mod 33)
(MERRPR1) and the module status 33 register (MDSTAT33). This pertains to module 33.
0
A write of 0 has no effect.
1
Clears module interrupt status bits: the M[33] bit in MERRPR1, the EMURST bit and the EMUIHB bit in
MDSTAT33.
0
Reserved
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6.7.5 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 6-6 and described in
Table 6-10.
Figure 6-6. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
2
1
0
Reserved
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 6-10. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GO[1]
Description
Reserved
Ethernet Subsystem Power domain GO transition command.
0
A write of 0 has no effect.
1
Writing 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including the
NEXT bit in MDCTLn for all the modules residing on this domain). If any of the NEXT fields are not
matching the corresponding current state (STATE bit in MDSTATn), the PSC will transition those
respective domain/modules to the new NEXT state.
GO[0]
AlwaysOn Power domain GO transition command.
0
A write of 0 has no effect.
1
Writing 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including the
NEXT bit in MDCTLn for all the modules residing on this domain). If any of the NEXT fields are not
matching the corresponding current state (STATE bit in MDSTATn), the PSC will transition those
respective domain/modules to the new NEXT state.
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6.7.6 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 6-7 and described in Table 6-11.
Figure 6-7. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-11. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
68
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
Ethernet Subsystem Power domain transition status.
0
No transition is in progress.
1
Modules in Ethernet Subsystem Power domain are transitioning.
GOSTAT[0]
AlwaysOn Power domain transition status.
0
No transition is in progress.
1
Modules in AlwaysOn power domain are transitioning.
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6.7.7 Power Domain Status n Register (PDSTATn)
The power domain status n register (PDSTAT0-PDSTAT1) is shown in Figure 6-8 and described in
Table 6-12. PDSTAT0 applies to the AlwaysOn power domain and PDSTAT1 applies to Ethernet
Subsystem power domain.
Figure 6-8. Power Domain Status n Register (PDSTATn)
31
16
Reserved
R-0
15
9
8
Reserved
10
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-1
R-1
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 6-12. Power Domain Status n Register (PDSTATn) Field Descriptions
Bit
31-10
9
8
Field
Reserved
Value
0
PORDONE
Reserved
4-0
STATE
Reserved
Power_On_Reset (POR) done status.
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power domain Power_On_Reset (POR) status. This bit reflects the POR status for this power domain
including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
Power domain status
0
Power domain is in the off state.
1
Power domain is in the on state.
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6.7.8 Power Domain Control n Register (PDCTLn)
The power domain control n register (PDCTL0-PTDCTL1) is shown in Figure 6-9 and described in
Table 6-13. PDCTL0 applies to the AlwaysOn power domain and PDCTL1 applies to Ethernet Subsystem
power domain.
Figure 6-9. Power Domain Control n Register (PDCTLn)
31
16
Reserved
R-0
15
1
0
Reserved
NEXT
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-13. Power Domain Control n Register (PDCTLn) Field Descriptions
Bit
31-1
0
70
Field
Reserved
Value
0
NEXT
Description
Reserved
Power domain next state.
0
Power domain off.
1
Power domain on. AlwaysOn domain and Ethernet Subsystem domain must always be programmed to
this value.
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6.7.9 Module Status n Register (MDSTATn)
The module status n register (MDSTAT0-MDSTAT34) is shown in Figure 6-10 and described in
Table 6-14.
Figure 6-10. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
7
6
5
0
Reserved
MCKOUT
Reserved
MRST
LRSTDONE
LRST
Reserved
STATE
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-14. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in MDCTL33.
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL33.
If you desire to generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL33..
Emulation Alters Module Reset. This bit applies to DSP module only (module 33). This field is 0 for
all other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state.
If you desire to generate a PSCINT upon this event, you must set the EMURSTIE bit in MDCTL33.
0
Reserved
Module clock output status. Shows actual status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to the DSP module only (module 33). This field is 1 for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Reserved
0
LRSTDONE
7-6
Description
Emulation Alters Module State. This bit applies to DSP module only (module 33). This field is 0 for
all other modules.
EMURST
15-13
9
Value
Module local reset status. This bit applies to the DSP module only (module 33).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
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Module state status. Indicates current module status.
0
Indicates transition
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6.7.10 Module Control n Register (MDCTLn)
The module control n register (MDCTL0-MDCTL34) is shown in Figure 6-11 and described in Table 6-15.
Figure 6-11. Module Control n Register (MDCTLn)
31
16
Reserved
R-0
15
11
10
9
8
7
3
2
0
Reserved
EMUIHBIE
EMURSTIE
LRST
Reserved
NEXT
R-0
R/W-0
R/W-0
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-15. Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31-11
Reserved
10
EMUIHBIE
9
8
Value
0
0
Disable interrupt.
1
Enable interrupt.
Interrupt enable for emulation alters reset. This bit applies to the DSP module only (module 33).
Program this field to 0 for all other modules.
0
Disable interrupt.
1
Enable interrupt.
LRST
Reserved
2-0
NEXT
Module local reset control. This bit applies to the DSP module only (module 33). Program this field to 1
for all other modules.
0
Assert local reset.
1
De-assert local reset.
0
Reserved
0-7h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-7h
72
Reserved
Interrupt enable for emulation alters module state. This bit applies to the DSP module only (module 33).
Program this field to 0 for all other modules.
EMURSTIE
7-3
Description
Power and Sleep Controller
Reserved
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Power Management
Topic
7.1
7.2
7.3
7.4
..................................................................................................
Overview ..................................................................................
PSC and PLLC Overview ............................................................
Clock Management ....................................................................
DSP Sleep Mode Management ....................................................
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Overview
7.1
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Overview
In many applications, there may be specific requirements to minimize power consumption for both power
supply (or battery) and thermal considerations. There are two components to power consumption: active
power and leakage power. Active power is the power consumed to perform work and scales roughly with
clock frequency and the amount of computations being performed. Active power can be reduced by
controlling the clocks in such a way as to either operate at a clock setting just high enough to complete
the required operation in the required timeline or to run at a clock setting until the work is complete and
then drastically cut the clocks (that is, to PLL Bypass mode) until additional work must be performed.
Leakage power is due to static current leakage and occurs regardless of the clock rate. Leakage, or
standby power, is unavoidable while power is applied and scales roughly with the operating junction
temperatures. Leakage power can only be avoided by removing power completely from a device or
subsystem.
The TMS320DM647/DM648 has several means of managing the power consumption, as detailed in the
following sections. There is extensive use of automatic clock gating in the design as well as
software-controlled module clock gating to not only reduce the clock tree power, but to also reduce
module power by basically freezing its state while not operating. Clock management enables you to slow
the clocks down on the chip in order to reduce switching power. In particular, the DM647/DM648 includes
all of the power management features described in Table 7-1.
Table 7-1. Power Management Features
Power Management Features
Description
Clock Management
PLL power-down
The PLLs can be powered-down when not in use to reduce switching power
Module clock ON/OFF
Module clocks can be turned on/off to reduce switching power
Module clock frequency scaling
Module clock frequency can be scaled to reduce switching power
DSP sleep modes
The DSP can be put into sleep mode to reduce switching power
DSP Sleep Management
7.2
PSC and PLLC Overview
The power and sleep controller (PSC) plays an important role in managing system power on/off, clock
on/off, and reset. Similarly, the PLL controller (PLLC) plays an important role in device clock generation.
The PSC and the PLLC are mentioned throughout this chapter. For detailed information on the PSC, see
Chapter 6. For detailed information on the PLLC, see Chapter 4 and Chapter 5.
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7.3
Clock Management
7.3.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's active power consumption to 0. The DM647/DM648 is designed in full static CMOS; thus,
when a module clock stops, the module's state is preserved. When the clock is restarted, the module
resumes operating from the stopping point.
Note:
Stopping clocks to a module only affects active power consumption, it does not affect
leakage power consumption.
If a module's clock(s) is stopped while being accessed, the access may not occur, and could potentially
lock-up the device. User must ensure that all of the transactions to the module are finished prior to
stopping the clocks. The power and sleep controller (PSC) controls module clock gating. The PSC
provides some protection against system hang by monitoring the internal bus activity—it only gates
internal clock to the module after checking that there is no access to the module from the internal bus.
The procedure to turn module clocks on/off using the PSC is described in Chapter 6. Furthermore, special
consideration must be given to DSP clock on/off. The procedure to turn the DSP clock on/off is further
described in Section 7.4.2.
Some peripherals provide additional power saving features by clock gating components within its module
boundary. See the peripheral-specific user's guide for more details on these additional power saving
features.
7.3.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL's multiply and divide parameters. Reducing
the clock frequency reduces the active switching power consumption linearly with frequency. It has no
impact on leakage power consumption.
Chapter 4 and Chapter 5 describe the how to program the PLL frequency and the frequency constraints.
7.3.3 PLL Bypass and Power Down
You can bypass the PLLs in the DM647/DM648. Bypassing the PLLs sends the PLL reference clock
(CLKIN1) instead of the PLL output (PLLOUT) to the SYSCLK dividers (PLLDIVn) of the PLLC. The PLL
reference clock is typically at 36 MHZ; therefore, you can use this mode to reduce the core and module
clock frequencies to very low maintenance levels without using the PLL during periods of very low system
activity. Furthermore, you can power-down the PLL when bypassing it to save additional active power.
Chapter 4 and Chapter 5 describe PLL bypass and PLL power down.
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DSP Sleep Mode Management
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DSP Sleep Mode Management
The C64x+ DSP supports sleep mode management to reduce power:
• DSP clock can be completely shut off
• C64x+ Megamodule can be put in sleep mode
– C64x+ CPU can be put in sleep mode
On the DM647/DM648, sleep mode for the DSP internal memories (L1P, L1D, L2) is not supported.
7.4.1 DSP Sleep Modes
The C64x+ Megamodule of the DSP subsystem includes a power-down controller (PDC) that controls the
power-down of the C64x+ Megamodule components. See Section 2.4.2 and the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871) for more details on the PDC.
7.4.2 DSP Module Clock ON/OFF
As discussed in Section 7.4.1, the C64x+ Megamodule can clock gate its own components to save power.
Additional power saving can be achieved by stopping the clock source to the C64x+ Megamodule by
programming the power and sleep controller (PSC) to place the C64x+ Megamodule in Disable state. The
C64x+ DSP cannot perform this programming task on its own, because the C64x+ DSP will not be able to
complete the PSC programming sequence if the C64x+ DSP clock source is gated in the middle of the
process. If stopping the clock source to the C64x+ DSP is desired for additional power saving, an external
host is responsible for programming the PSC (for example, via HPI, PCI interfaces) to disable the C64x+
Megamodule. Similarly, in that case the external host is responsible for programming the PSC to enable
the C64x+ Megamodule.
7.4.2.1
DSP Module Clock ON
In the clock Enable state, the DSP’s module clock is enabled while DSP module reset is de-asserted. This
is the state for normal DSP run-time. DSP defaults to Enable state, therefore this DSP Module Clock ON
process is typically not needed. This process is only required to wake up the DSP after an external host
puts the DSP in Disable state (Section 7.4.2.2).
• Host: Enable clocks to the DSP.
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish
any previously initiated transitions before initiating a new transition.
– Set the NEXT bit in MDCTL33 to 3h to prepare the DSP module for an enable transition.
– Set the GO[0] bit in PTCMD to 1 to initiate the state transition.
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state
after the GOSTAT[0] bit is cleared to 0.
– Wait for the STATE bit in MDSTAT33 to change to 3h. The module is only safely in the new state
after the STATE bit in MDSTAT33 changes to reflect the new state.
• Host: Wake the DSP.
– If transitioning from the disable state, trigger a DSP interrupt that has previously been configured as
a wake-up interrupt.
Note:
76
This step only applies if you are transitioning from the disable state. If previously in the
disable state, a wake-up interrupt must be triggered in order to wake the DSP. This example
assumes that the DSP enabled this interrupt before entering its IDLE state. If previously in
the software reset disable or synchronous reset state, it is not necessary to wake the DSP
because these states assert the DSP module reset. See Chapter 10 for information on the
software reset disable and synchronous reset states. See the TMS320C64x+ DSP
Megamodule Reference Guide (SPRU871) for more information on DSP interrupts.
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7.4.2.2
DSP Module Clock Off
In the clock Disable state, the DSP’s module clock is disabled, while DSP reset remains de-asserted. This
state is typically used to disable the DSP clock to save power. As mentioned in Section 7.4.2, the DSP
cannot put itself in Disable state. An external host is responsible for performing this task. For example, it
can be an external host interfacing through the HPI or PCI peripheral.
• Host: Notify the DSP to prepare for power-down.
• DSP: Drain all existing operations and ensure there are no accesses to the C64x+ megamodule prior
to DSP power-down.
– Program the PSC to disable all master peripherals (except the Host) that are capable of initiating
transfers to the C64x+ Megamodule.
– Check EDMA transfer status to ensure there is no outstanding EDMA transfers that can access the
C64x+ Megamodule.
• DSP: Prepare for power-down.
– Set PDCCMD to 0001 5555h. PDCCMD is a control register in the DSP power-down controller
module.
Note:
•
This register can only be written while the DSP is in supervisor mode.
– Enable one of the interrupts that the host would like to use to wake the DSP in the DSP clock-on
sequence.
– Execute the IDLE instruction. IDLE is a program instruction in the C64x+ CPU instruction set. When
the CPU executes IDLE, the PDC is notified and initiates DSP power-down according to the bits
that you set in the PDCCMD (0181 0000h) register. See the TMS320C64x+ DSP Megamodule
Reference Guide (SPRU871) for more information on the PDC and the IDLE instruction.
Host: Disable the DSP clock.
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish
any previously initiated transitions before initiating a new transition.
– Set the NEXT bit in MDCTL33 to 2h to prepare the DSP module for a disable transition.
– Set the GO[0] bit in PTCMD to 1 to initiate the state transition.
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state
after the GOSTAT[0] bit is cleared to 0.
– Wait for the STATE bit in MDSTAT33 to change to 2h. The module is only safely in the new state
after the STATE bit in MDSTAT33 changes to reflect the new state.
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Chapter 8
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Interrupt Controller
The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The interrupt
controller interfaces the system events to the CPU's interrupt and exception inputs. The interrupt controller
supports up to 128 system events, and it maps these system events to the 12 CPU interrupts. See the
device-specific data manual for the list of system events. The interrupt controller section of the
TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) fully describes the INTC and how it maps
the DSP device events to the 12 CPU interrupts.
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Chapter 9
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System Module
Topic
9.1
9.2
9.3
9.4
9.5
9.6
..................................................................................................
Overview ..................................................................................
Device Identification ..................................................................
Device Configuration .................................................................
Ethernet Subsystem Control ......................................................
Bandwidth Management.............................................................
Boot Control .............................................................................
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Overview
9.1
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Overview
The TMS320DM647/DM648 System Module is a system-level module containing status and top-level
control logic required by the device. The System Module consists of a set of status and control registers,
accessible by the DSP, supporting all of the following system features and operations:
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device boot configuration status
• Ethernet Subsystem Control
• Bandwidth Management
– Bus master DMA priority control
• Boot Control
This chapter describes the System Module.
9.2
Device Identification
The JTAGID register of the System Module contains a software readable version of the JTAG ID device.
Software can use this register to determine the version of the device on which it is executing. The register
format and description are shown in the device-specific data manual.
9.3
Device Configuration
The System Module contains registers for controlling pin multiplexing and registers that reflect the boot
configuration status.
9.3.1 Pin Multiplexing Control
The DM647/DM648 makes extensive use of pin multiplexing to accommodate the large number of
peripheral functions in the smallest possible package. A combination of hardware configuration
(configuration pins latched at device reset) and register program control (PINMUX register) controls pin
multiplexing to accomplish this. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used.
Detailed information about the pin multiplexing and control is covered in the device-specific data manual.
9.3.2 Device Boot Configuration Status
The device boot and configuration settings are latched at device reset (POR or RESET), and captured in
the BOOTCFG register. See the device-specific data manual for details on this register and the boot and
configuration settings.
9.4
Ethernet Subsystem Control
The System Module contains the following Ethernet Subsystem control registers:
• SerDes PLL Configuration Register (CFGPLL)
• SerDes Transmitter Configuration Registers(CFGTX0, CFGTX1)
• SerDes Receiver Configuration Registers(CFGRX0, CFGRX1)
See the device-specific Ethernet Subsystem guide for descriptions of these registers.
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9.5
Bandwidth Management
9.5.1 Bus Master DMA Priority Control
In order to determine allowed connections between masters and slaves, each master request source must
have a unique master ID (mstid) associated with it. The master ID for each DM647/DM648 master is
shown in Table 9-1.
Table 9-1. TMS320DM647/DM648 Master IDs
MSTID
Master
0
EDMA3TC0
0
EDMA3TC1
0
EDMA3TC2
0
EDMA3TC3
7
64X+_DMAP
1
64X+_CFGP
3
Ethernet Subsystem
4
VLYNQ
4
UHPI
4
PCI
5
VICP
Each switched central resource (SCR) performs prioritization based on the priority level of the master that
sends the command. Each bus master's priority is programmed in the chip-level Bus Master Priority
Allocation Registers (PRI_ALLOC). Application software is expected to modify these values to obtain the
desired system performance.
9.6
Boot Control
The System Module contains the following boot control registers:
• Device Boot Configuration Register (BOOTCFG)
• Boot Complete Register (BOOTCMPLT)
• DSP Boot Address Register (DSPBOOTADDR)
See Chapter 11 and the device-specific data manual for descriptions of these registers.
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Chapter 10
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Reset
Topic
..................................................................................................
10.1
10.2
10.3
10.4
Overview ..................................................................................
Reset Pins ................................................................................
Device Configurations at Reset...................................................
DSP Reset ................................................................................
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10.1 Overview
There are different types of reset in the TMS320DM647/DM648. The types of reset differ by how they are
initiated and/or by their effect on the chip. Each type is briefly described in Table 10-1. See the
device-specific data manual for more details on each of the reset types.
Table 10-1. Reset Types
Type
Initiator
Effect
POR (Power-On-Reset)
POR pin low
Total reset of the chip (cold reset). Resets entire chip including test and
emulation logic. The power-on reset (POR) pin must be driven low
during power ramp of the device. Device boot and configuration pins
are latched.
Warm Reset
RESET pin low
Resets everything except for test and emulation logic and Ethernet
Subsystem. Emulator stays alive during warm reset. Device boot and
configuration pins are latched.
System Reset
PCI via the PRST pin
A soft reset, does not affect or reset clocks or power states. Does not
reset test and emulator logic and Ethernet Subsystem. The Device
boot and configuration pins are not re-latched.
Module/Peripheral Local
Reset
DSP or external host software
Independently resets a specific module. Module reset is intended as a
debug tool, not necessarily as a tool to use in production.
DSP Local Reset
External host software
Resets the DSP CPU. DSP internal memories (L1P, L1D, and L2) are
not reset.
10.2 Reset Pins
There are two device-level global reset pins on the device: Power-On-Reset (POR) and warm reset
(RESET). See the device-specific data manual for more details on these reset pins.
10.3 Device Configurations at Reset
Upon POR and warm reset, the device latches the values from the boot and configuration pins. See the
device-specific data manual for the list of boot and configuration pins, and the device's default states.
10.4 DSP Reset
With access to the power and sleep controller (PSC) registers, the external host (for example, PCI, HPI)
can assert and de-assert DSP local reset and DSP module reset. When DSP local reset is asserted, the
DSP’s internal memories (L1P, L1D, and L2) are still accessible. Local reset only resets the DSP CPU.
Local reset is useful when the DSP module is in the enable or disable states, since module reset is
asserted in the SyncReset and SwRstDisable states and module reset supersedes local reset. The intent
of DSP module reset is for the external host to completely reset the DSP. The intent of DSP local reset is
to allow the host to hold the CPU in reset while it is loading code into the DSP internal memory—this step
can be useful after the host puts the DSP in module reset and then subsequently enables the DSP. For
more information on the PSC, see Chapter 6. This section describes how to initiate DSP local reset and
module reset.
10.4.1 DSP Local Reset
The following steps describe how an external host can assert/de-assert local reset to the DSP:
1. Clear the LRST bit in MDCTL33 to 0 to assert DSP reset.
2. Set the LRST bit in MDCTL33 to 1 to de-assert DSP reset.
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10.4.2 DSP Module Reset
The external host may program the PSC to assert DSP module reset by placing the DSP in either
Software Reset Disable (SwRstDisable) state or Synchronous Reset (SyncReset) state. See Chapter 6 for
descriptions of these PSC states.
10.4.2.1 Software Reset Disable (SwRstDisable)
In the software reset disable (SwRstDisable) state, the DSP’s module reset is asserted and its module
clock is turned off. You can use this state to reset the DSP. The following steps describe how to put the
DSP in the software reset disable state:
• Host: Notify the DSP to prepare for power-down.
• DSP: Put the DSP in the IDLE state.
– Set PDCCMD to 0001 5555h. PDCCMD is a control register in the DSP power-down controller
module.
Note:
This register can only be written while the DSP is in its supervisor mode.
– Execute the IDLE instruction if the DSP is in the enable state. IDLE is a program instruction in the
C64x+ CPU instruction set. When the CPU executes IDLE, the PDC is notified and will initiate the
DSP power-down according to the bits that you set in the PDCCMD (0181 0000h) register. See the
TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the PDC
and the IDLE instruction.
•
•
Host: Software reset disable DSP.
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish
any previously initiated transitions before initiating a new transition.
– Clear the NEXT bit in MDCTL33 to 0 to prepare the DSP module for a SwRstDisable transition.
– Set the GO[0] bit in PTCMD to 1 to initiate the state transition.
– Wait for GOSTAT[0] bit in PTSTAT to clear to 0. The module is safely in the new state only after
the GOSTAT[0] bit is cleared to 0.
Host: Assert the DSP local reset (Optional)
– Clear the LRST bit in MDCTL33 to 0. This step is optional. This step asserts the DSP local reset,
and is included here so that the DSP does not start running immediately upon it is subsequently
enable by the host. Typically, the host only de-asserts local reset to the DSP after it makes sure
that code is properly loaded.
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10.4.2.2 Synchronous Reset (SyncReset)
In the synchronous reset (SyncReset) state, the DSP’s module reset is asserted and its module clock is
enabled. You can use this state to reset the DSP. The following steps describe how to put the DSP in the
synchronous reset state:
• Host: Notify the DSP to prepare for power-down.
• DSP: Put the DSP in the IDLE state.
– Set PDCCMD to 0001 5555h. PDCCMD is a control register in the DSP power-down controller
module.
Note:
•
•
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This register can only be written while the DSP is in supervisor mode.
– Execute the IDLE instruction.
Host: Sync reset DSP
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish
any previously initiated transitions before initiating a new transition.
– Set the NEXT bit in MDCTL33 to 1 to prepare the DSP module for a SyncReset transition.
– Set the GO[0] bit in PTCMD to 1 to initiate the state transition.
– Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The module is safely in the new state only
after the GOSTAT[0] bit is cleared to 0.
Host: Assert DSP local reset (Optional)
– Clear the LRST bit in MDCTL33 to 0. This step is optional. This step asserts the DSP local reset
and is included here so that the DSP does not start running immediately upon it is subsequently
enabled by the host. Typically, software de-asserts local reset to the DSP after it makes sure that
code is properly loaded.
Reset
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Chapter 11
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Boot Modes
The TMS320DM647/DM648 can boot from either asynchronous EMIF/NOR Flash/Synchronous EMIF
directly or from internal boot ROM, as determined by the setting of the device boot and configuration pins.
The input states of the boot and configuration pins are sampled and latched into the BOOTCFG register
when device reset is deasserted. See the device-specific data manual for the list of boot and configuration
pins and a list of boot modes supported on the DM647/DM648.
In all boot modes, the C64x+ CPU is immediately released from reset and begins executing from one of
the two possible addresses:
• EMIFA Chip Select Space 2 (A000 0000h)
• Internal Boot ROM (0080 0000h)
For the boot modes that start at the internal boot ROM, the ROM Boot Loader (RBL) software is
responsible for completing the boot sequence. See the Using the TMS320DM647/DM648 Bootloader
Application Report (SPRAAJ1) for more details on the ROM Boot Loader.
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