Texas Instruments | TMS320C645x DSP General-Purpose Input/Output (GPIO) (Rev. A) | User Guides | Texas Instruments TMS320C645x DSP General-Purpose Input/Output (GPIO) (Rev. A) User guides

Texas Instruments TMS320C645x DSP General-Purpose Input/Output (GPIO) (Rev. A) User guides
TMS320C645x DSP
General-Purpose Input/Output (GPIO)
User’s Guide
Literature Number: SPRU724A
December 2005 − Revised December 2008
This page is intentionally left blank.
2
Preface
Read This First
About This Manual
This document describes the general-purpose input/output (GPIO) peripheral
in the digital signal processors (DSPs) of the TMS320C645x DSP family.
Notational Conventions
This document uses the following conventions.
- Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
- When referencing specific register bits, the X in the register bit name is
replaced with the bit number; for example, GPXDIR refers to the bit field
of the GPIO direction register and GP15DIR refers to bit 15 of GPDIR.
- Registers in this document are shown in figures and described in tables.
J
Each register figure shows a rectangle divided into fields that represent
the fields of the register. Each field is labeled with its bit name, its
beginning and ending bit numbers above, and its read/write properties
below. A legend explains the notation used for the properties.
J
Reserved bits in a register figure designate a bit that is used for future
device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000 devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) gives an introduction to the TMS320C62xt and
TMS320C67xt DSPs, development tools, and third-party support.
TMS320C6455 Technical Reference (literature number SPRU965) gives an
introduction to the TMS320C6455t DSP and discusses the application
areas that are enhanced.
SPRU724
General-Purpose Input/Output (GPIO)
3
Trademarks
Related Documentation From Texas Instruments / Trademarks
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000t DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studiot integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studiot application programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number
SPRU871) describes the TMS320C64x+ digital signal processor (DSP)
megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power−down controller, memory protection, bandwidth management, and the memory and
cache.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature
number SPRU190) provides a brief description of the peripherals available on the TMS320C6000 digital signal processors (DSPs).
TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234)
is a download with the latest chip support libraries.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
4
General-Purpose Input/Output (GPIO)
SPRU724
Contents
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
GPIO Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Interrupt and Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Emulation Halt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Interrupt Per-Bank Enable Register (BINTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Direction Register (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Output Data Register (OUT_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Set Data Register (SET_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Clear Data Register (CLR_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Input Data Register (IN_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Set Rising Edge Interrupt Register (SET_RIS_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Set Falling Edge Interrupt Register (SET_FAL_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRU724
General-Purpose Input/Output (GPIO)
15
16
17
18
19
20
21
22
23
24
25
5
Figures
Figures
1
2
3
4
5
6
7
8
9
10
11
12
6
TMS320C645x DSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Peripheral Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Per-Bank Enable Register (BINTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direction Register (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Data Register (OUT_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Data Register (SET_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Data Register (CLR_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Data Register (IN_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Rising Edge Interrupt Register (SET_RIS_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Falling Edge Interrupt Register (SET_FAL_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output (GPIO)
10
11
16
17
18
19
20
21
22
23
24
25
SPRU724
Tables
Tables
1
2
3
4
5
6
7
8
9
10
11
12
GPIO Interrupt and EDMA Event Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions . . . . . . . . . . . . . . . . . . . . .
Direction Register (DIR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Data Register (OUT_DATA) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Data Register (SET_DATA) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Data Register (CLR_DATA) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Data Register (IN_DATA) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Rising Edge Interrupt Register (SET_RIS_TRIG) Field Descriptions . . . . . . . . . . . . . . .
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) Field Descriptions . . . . . . . . . . . . .
Set Falling Edge Interrupt Register (SET_FAL_TRIG) Field Descriptions . . . . . . . . . . . . . .
Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) Field Descriptions . . . . . . . . . . . .
SPRU724
General-Purpose Input/Output (GPIO)
13
15
16
17
18
19
20
21
22
23
24
25
7
This page is intentionally left blank.
8
General-Purpose Input/Output (GPIO)
SPRU724
GeneralĆPurposeĄInput/OutputĄ(GPIO)
This document describes the general-purpose input/output (GPIO) peripheral
in the digital signal processors (DSPs) of the TMS320C645x DSP family.
1
Overview
The general-purpose input/output (GPIO) peripheral provides dedicated
general-purpose pins that can be configured as either inputs or outputs. When
configured as an output, you can write to an internal register to control the state
driven on the output pin. When configured as an input, you can detect the state
of the input by reading the state of an internal register.
In addition, the GPIO peripheral can produce CPU interrupts and EDMA
synchronization events in different interrupt/event generation modes.
Figure 1 shows the GPIO peripheral in the TMS320C645x DSP. Figure 2
shows the GPIO peripheral block diagram.
SPRU724A
General-Purpose Input/Output (GPIO)
9
Overview
Figure 1.
TMS320C645x DSP Block Diagram
L1P
cache/SRAM
EMIFA
Switched central resource
DDR2 memory
controller
PLL2
GPIO
L2 memory
L2 memory
controller
Bandwidth
management
External
memory
controller
Configuration
registers
Other
peripherals
Master
DMA
Slave
DMA
EDMA
controller
Boot
configuration
Cache control
Bandwidth management
Memory protection
Cache
control
Memory
protection
Advanced
event
triggering
(AET)
L1 program memory controller
C64x+ CPU
Instruction fetch
SPLOOP buffer
16/32−bit instruction dispatch
Instruction decode
IDMA
Data path A
L1
S1
M1
Data path B
D1
Register file A
L1 data memory controller
Cache control
Memory protection
Bandwidth management
D2
M2
S2
L2
Register file B
Interrupt
and exception
controller
Power control
PLL2
L1D
cache/SRAM
Some GPIO pins are MUXed with other device pins. Refer to the device-specific
datasheet for details on specific MUXing and for the availability of the register
bits. GPINT[0:15] are all available as synchronization events to the EDMA
controller and as interrupt sources to the CPU.
10
General-Purpose Input/Output (GPIO)
SPRU724A
Overview
Figure 2.
GPIO Peripheral Block Diagram
GPIO peripheral
Data input/output
Direction
DIR
Set
data
SET_DATA
Output
data
OUT_DATA
Clear
data
CLR_DATA
Input
data
IN_DATA
EDMA event and interrupt
generation
Set rising
edge trigger
SET_RIS_TRIG
Rising edge
trigger
RIS_TRIG§
Clear rising
edge trigger
CLR_RIS_TRIG
Set falling
edge trigger
SET_FAL_TRIG
Falling edge
trigger
FAL_TRIG§
Clear falling
edge trigger
CLR_FAL_TRIG
GPn†
Peripheral clock
(CPU/6)
Synchronization
logic
Edge detection
logic
Interrupt and
EDMA event
(GPINTn‡)
† Some of the GPn pins are MUXed with other device signals. Refer to the device-specific datasheet for details.
‡ All GPINTn can be used as CPU interrupts and synchronization events to the EDMA controller.
§ The RIS_TRIG and FAL_TRIG registers are internal to the GPIO module and are not visible to the CPU.
SPRU724A
General-Purpose Input/Output (GPIO)
11
GPIO Function
2
GPIO Function
You can independently configure each GPIO pin (GPn) as either an input or
an output using the GPIO direction registers. The GPIO direction register
(DIR) specifies the direction of each GPIO signal. Logic 0 indicates the GPIO
pin is configured as output, and logic 1 indicates input.
When configured as output, writing a 1 to a bit in the set data register drives
the corresponding GPn to a logic-high state. Writing a 1 to a bit in the clear data
register drives the corresponding GPn to a logic-low state. The output state of
each GPn can also be directly controlled by writing to the output data register.
For example, to set GP8 to a logic-high state, the software can perform one
of the following:
- Write 0x100 to the SET_DATA register
- Read in OUT_DATA register, change the eighth bit to 1, and write the new
value back to OUT_DATA
To set GP8 to a logic-low state, the software can perform one of the following:
- Write 0x100 to the CLR_DATA register
- Read in OUT_DATA register, change the eighth bit to 0, and write the new
value back to OUT_DATA
Note that writing a 0 to bits in the set data and clear data registers does not
affect the GPIO pin state. Also, for GPIO pins configured as input, writing to
the set data, clear data, or output data registers does not affect the pin state.
For a GPIO pin configured as input, reading the input data register (IN_DATA)
will return the pin state.
Reading the SET_DATA register or the CLR_DATA data register will return the
value in OUT_DATA, not the actual pin state. The pin state is available by
reading the input data register.
12
General-Purpose Input/Output (GPIO)
SPRU724A
Interrupt and Event Generation
3
Interrupt and Event Generation
Each GPIO pin (GPn) can be configured to generate a CPU interrupt (GPINTn)
and a synchronization event to the EDMA controller (GPINTn). The interrupt
and EDMA event can be generated on the rising-edge, falling-edge, or on both
edges of the GPIO signal. The edge detection logic is synchronized to the
GPIO peripheral clock.
The direction of the GPIO pin does not need to be input when using the pin to
generate the interrupt and EDMA event. When the GPIO pin is configured as
input, transitions on the pin trigger interrupts and EDMA events. When the
GPIO pin is configured as output, software can toggle the GPIO output register
to change the pin state and in turn trigger the interrupt and EDMA event.
Two internal registers, RIS_TRIG and FAL_TRIG, specify which edge of the
GPn signal generates an interrupt and EDMA event. Each bit in these two
registers corresponds to a GPn pin. Table 1 describes the CPU interrupt and
EDMA event generation of GPn pin based on the bit settings of the RIS_TRIG
and FAL_TRIG registers.
Table 1.
GPIO Interrupt and EDMA Event Configuration Options
RIS_TRIG bit n
FAL_TRIG bit n CPU Interrupt and EDMA Event Generation
0
0
GPINTn interrupt and EDMA event is disabled
0
1
GPINTn interrupt and EDMA event is triggered on falling edge of GPn
signal
1
0
GPINTn interrupt and EDMA event is triggered on rising edge of GPn
signal
1
1
GPINTn interrupt and EDMA event is triggered on both rising and falling
edge of GPn signal
RIS_TRIG and FAL_TRIG are not directly accessible or visible to the CPU.
These registers are accessed indirectly through four registers:
SET_RIS_TRIG, CLR_RIS_TRIG, SET_FAL_TRIG, and CLR_FAL_TRIG.
Writing 1 to a bit on the SET_RIS_TRIG register sets the corresponding bit on
the RIS_TRIG register. Writing 1 to a bit of CLR_RIS_TRIG register clears the
corresponding bit on the RIS_TRIG register. Writing to SET_FAL_TRIG and
CLR_FAL_TRIG works the same way on the FAL_TRIG register.
SPRU724A
General-Purpose Input/Output (GPIO)
13
Emulation
HaltEvent
Operation
Interrupt and
Generation / Interrupts and Events
Reading the SET_RIS_TRIG or CLR_RIS_TRIG register returns the value of
RIS_TRIG register. Reading from SET_FAL_TRIG and CLR_FAL_TRIG
register returns the value of FAL_TRIG register.
To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0
in the bank interrupt enable register (BINTEN) must be set to 1.
4
Emulation Halt Operation
The GPIO peripheral is not affected by emulation halts.
14
General-Purpose Input/Output (GPIO)
SPRU724A
Registers
5
Registers
The GPIO peripheral is configured through the registers listed in Table 2. See
the device-specific datasheet for the memory address of these registers.
Table 2.
GPIO Registers
Offsets
Acronym
Register Name
0008
BINTEN
Interrupt Per-Bank Enable Register
5.1
0010
DIR
Direction Register
5.2
0014
OUT_DATA
Output Data Register
5.3
0018
SET_DATA
Set Data Register
5.4
001C
CLR_DATA
Clear Data Register
5.5
0020
IN_DATA
Input Data Register
5.6
0024
SET_RIS_TRIG
Set Rising Edge Interrupt Register
5.7
0028
CLR_RIS_TRIG
Clear Rising Edge Interrupt Register
5.8
002C
SET_FAL_TRIG
Set Falling Edge Interrupt Register
5.8
0030
CLR_FAL_TRIG
Clear Falling Edge Interrupt Register
5.9
SPRU724A
Section
General-Purpose Input/Output (GPIO)
15
Registers
5.1
Interrupt Per-Bank Enable Register (BINTEN)
To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0
in the bank interrupt enable register (BINTEN) must be set. BINTEN is shown
in Figure 3 and described in Table 3.
Figure 3.
Interrupt Per-Bank Enable Register (BINTEN)
31
1
0
Reserved
EN
R-0
RW-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 3.
Bit
31−1
0
16
Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions
Field
Reserved
Value
0
EN
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Enables all GPIO pins as interrupt sources to the DSP CPU.
0
Disables GPIO interrupts
1
Enables GPIO interrupts
General-Purpose Input/Output (GPIO)
SPRU724A
Registers
5.2
Direction Register (DIR)
The GPIO direction register (DIR) determines if a given GPIO pin is an input
or an output. The GPDIR is shown in Figure 4 and described in Table 4. By
default, all the GPIO pins are configured as input pins.
When GPIO pins are configured as output pins, the GPIO output buffer drives
the GPIO pin. If it is necessary to place the GPIO output buffer in a
high-impedance state, the GPIO pin must be configured as an input pin
(DIRn = 1). At reset, GPIO pins default to input mode.
Figure 4.
Direction Register (DIR)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
DIR15
DIR14
DIR13
DIR12
DIR11
DIR10
DIR9
DIR8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4.
Bit
Direction Register (DIR) Field Descriptions
Field
31−16
Reserved
15−0
DIRn
SPRU724A
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Controls the direction of the GPn pin.
0
GPn pin configured as output pin
1
GPn pin configured as input pin
General-Purpose Input/Output (GPIO)
17
Registers
5.3
Output Data Register (OUT_DATA)
The GPIO output data register (OUT_DATA) indicates the value to be driven
on a given GPIO output pin. The OUT_DATA registers are shown in Figure 5
and described in Table 5.
Figure 5.
Output Data Register (OUT_DATA)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 5.
Bit
Output Data Register (OUT_DATA) Field Descriptions
Field
31−16
Reserved
15−0
OUTn
18
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Controls the drive state of the corresponding GPn pin. These bits do not
affect the state of the pin when the pin is configured as an input. Reading
these bits returns the value of this register, not the state of the pin.
General-Purpose Input/Output (GPIO)
SPRU724A
Registers
5.4
Set Data Register (SET_DATA)
The GPIO set data register (SET_DATA) is shown in Figure 6 and described
in Table 6. SET_DATA provides an alternate means of driving GPIO outputs
high. Writing a 1 to a bit of SET_DATA sets the corresponding bit in
OUT_DATA. Writing a 0 has no effect. Reading SET_DATA returns the
contents of OUT_DATA.
Figure 6.
Set Data Register (SET_DATA)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
SET15
SET14
SET13
SET12
SET11
SET10
SET9
SET8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SET7
SET6
SET5
SET4
SET3
SET2
SET1
SET0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 6.
Bit
Set Data Register (SET_DATA) Field Descriptions
Field
31−16
Reserved
15−0
SETn
SPRU724A
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Writing 1 sets the corresponding bit the OUT_DATA register. Reading this
register returns the contents of the OUT_DATA register. Writing a 0 has no
effect.
0
No effect
1
Sets the corresponding bit in OUT_DATA
General-Purpose Input/Output (GPIO)
19
Registers
5.5
Clear Data Register (CLR_DATA)
The GPIO clear data register (CLR_DATA) is shown in Figure 7 and described
in Table 7. CLR_DATA provides an alternate means of driving GPIO outputs
low. Writing a 1 to a bit of CLR_DATA clears the corresponding bit in
OUT_DATA. Writing a 0 has no effect. Reading CLR_DATA returns the
contents of OUT_DATA.
Figure 7.
Clear Data Register (CLR_DATA)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
CLR15
CLR14
CLR13
CLR12
CLR11
CLR10
CLR9
CLR8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLR7
CLR6
CLR5
CLR4
CLR3
CLR2
CLR1
CLR0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 7.
Bit
Clear Data Register (CLR_DATA) Field Descriptions
Field
31−16
Reserved
15−0
CLRn
20
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Writing 1 clears the corresponding bit the OUT_DATA register. Reading this
register returns the contents of the OUT_DATA register. Writing a 0 has no
effect.
0
No effect
1
Clears the corresponding bit in OUT_DATA
General-Purpose Input/Output (GPIO)
SPRU724A
Registers
5.6
Input Data Register (IN_DATA)
The GPIO input data register (IN_DATA) reflects the state of the GPIO pins.
The IN_DATA register is shown in Figure 8 and described in Table 8. When
read, IN_DATA returns the state of the GPIO pins regardless of the state of the
corresponding bits in the DIR and OUT_DATA registers.
Figure 8.
Input Data Register (IN_DATA)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
IN15
IN14
IN13
IN12
IN11
IN10
IN9
IN8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 8.
Bit
Input Data Register (IN_DATA) Field Descriptions
Field
31−16
Reserved
15−0
INn
SPRU724A
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Returns the status of the corresponding GPn pin.
General-Purpose Input/Output (GPIO)
21
Registers
5.7
Set Rising Edge Interrupt Register (SET_RIS_TRIG)
The GPIO rising trigger register (RIS_TRIG) configures the edge detection
logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO
signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO
interrupt and EDMA event (GPINTn) to be generated on the rising edge of
GPn. RIS_TRIG is not directly accessible by the CPU; it must be configured
using the GPIO set rising trigger and clear rising trigger registers.
The GPIO set rising trigger register (SET_RIS_TRIG) is shown in Figure 9 and
described in Table 9. Writing a 1 to a bit of SET_RIS_TRIG sets the
corresponding bit in RIS_TRIG. Writing a 0 has no effect. Reading
SET_RIS_TRIG returns the value in RIS_TRIG.
Figure 9.
Set Rising Edge Interrupt Register (SET_RIS_TRIG)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
SETRIS15
SETRIS14
SETRIS13
SETRIS12
SETRIS11
SETRIS10
SETRIS9
SETRIS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETRIS7
SETRIS6
SETRIS5
SETRIS4
SETRIS3
SETRIS2
SETRIS1
SETRIS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 9.
Bit
Set Rising Edge Interrupt Register (SET_RIS_TRIG) Field Descriptions
Field
31−16
Reserved
15−0
SETRISn
22
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Writing a 1 enables the rising edge detection for the corresponding GPn pin.
Reading this register returns the state of the RIS_TRIG register.
0
No effect
1
Sets the corresponding bit in RIS_TRIG
General-Purpose Input/Output (GPIO)
SPRU724A
Registers
5.8
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG)
The GPIO rising trigger register (RIS_TRIG) configures the edge detection
logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO
signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO
interrupt and EDMA event (GPINTn) to be generated on the rising edge of
GPn. RIS_TRIG is not directly accessible by the CPU; it must be configured
using the GPIO set rising trigger and clear rising trigger registers.
The GPIO clear rising trigger register (CLR_RIS_TRIG) is shown in Figure 10
and described in Table 10. Writing a 1 to a bit of CLR_RIS_TRIG clears the
corresponding bit in RIS_TRIG. Writing a 0 has no effect. Reading
CLR_RIS_TRIG returns the value in RIS_TRIG.
Figure 10.
Clear Rising Edge Interrupt Register (CLR_RIS_TRIG)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
CLRRIS15
CLRRIS14
CLRRIS13
CLRRIS12
CLRRIS11
CLRRIS10
CLRRIS9
CLRRIS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRRIS7
CLRRIS6
CLRRIS5
CLRRIS4
CLRRIS3
CLRRIS2
CLRRIS1
CLRRIS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 10. Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) Field Descriptions
Bit
Field
31−16
Reserved
15−0
CLRRISn
SPRU724A
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
Writing a 1 disables rising edge detection for the corresponding GPn pin.
Reading this register returns the state of the RIS_TRIG register.
0
No effect
1
Clears the corresponding bit in RIS_TRIG
General-Purpose Input/Output (GPIO)
23
Registers
5.9
Set Falling Edge Interrupt Register (SET_FAL_TRIG)
The GPIO falling trigger register (FAL_TRIG) configures the edge detection
logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO
signals. Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO
interrupt and EDMA event (GPINTn) to be generated on the falling edge of
GPn. FAL_TRIG is not directly accessible by the CPU; it must be configured
using the GPIO set falling trigger and clear falling trigger registers.
The GPIO set falling trigger register (SET_FAL_TRIG) is shown in Figure 11
and described in Table 11. Writing a 1 to a bit of SET_FAL_TRIG sets the
corresponding bit in FAL_TRIG. Writing a 0 has no effect. Reading
SET_FAL_TRIG returns the value in FAL_TRIG.
Figure 11.
Set Falling Edge Interrupt Register (SET_FAL_TRIG)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
SETFAL15
SETFAL14
SETFAL13
SETFAL12
SETFAL11
SETFAL10
SETFAL9
SETFAL8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETFAL7
SETFAL6
SETFAL5
SETFAL4
SETFAL3
SETFAL2
SETFAL1
SETFAL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 11.
Bit
Set Falling Edge Interrupt Register (SET_FAL_TRIG) Field Descriptions
Field
31−16
Reserved
15−0
SETFALn
24
Value
0
Description
Reserved. The reserved bit location is always read as zero. A value
written to this field has no effect.
Writing a 1 enables the falling edge detection for the corresponding GPn
pin. Reading this register returns the state of the FAL_TRIG register.
0
No effect
1
Sets the corresponding bit in FAL_TRIG
General-Purpose Input/Output (GPIO)
SPRU724A
Registers
5.10
Clear Falling Edge Interrupt Register (CLR_FAL_TRIG)
The GPIO falling trigger register (FAL_TRIG) configures the edge detection
logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO
signals. Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO
interrupt and EDMA event (GPINTn) to be generated on the falling edge of
GPn. FAL_TRIG is not directly accessible by the CPU; it must be configured
using the GPIO set falling trigger and clear falling trigger registers.
The GPIO clear falling trigger register (CLR_FAL_TRIG) is shown in Figure 11
and described in Table 11. Writing a 1 to a bit of CLR_FAL_TRIG clears the
corresponding bit in FAL_TRIG. Writing a 0 has no effect. Reading
CLR_FAL_TRIG returns the value in FAL_TRIG.
Figure 12.
Clear Falling Edge Interrupt Register (CLR_FAL_TRIG)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
CLRFAL15
CLRFAL14
CLRFAL13
CLRFAL12
CLRFAL11
CLRFAL10
CLRFAL9
CLRFAL8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRFAL7
CLRFAL6
CLRFAL5
CLRFAL4
CLRFAL3
CLRFAL2
CLRFAL1
CLRFAL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 12. Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) Field Descriptions
Bit
Field
31−16
Reserved
15−0
CLRFALn
SPRU724A
Value
0
Description
Reserved. The reserved bit location is always read as zero. A value
written to this field has no effect.
Writing a 1 disables falling edge detection for the corresponding GPn pin.
Reading this register returns the state of the FAL_TRIG register.
0
No effect
1
Clears the corresponding bit in FAL_TRIG
General-Purpose Input/Output (GPIO)
25
This page is intentionally left blank.
26
General-Purpose Input/Output (GPIO)
SPRU724A
Index
Index
B
I
block diagram
C645x DSP
GPIO 11
interrupt generation
interrupts 14
13
10
N
notational conventions
E
O
overview
event generation
events
3
14
9
13
R
registers 15
related documentation from Texas Instruments
F
function 12
SPRU724A
3
T
trademarks
4
General-Purpose Input/Output (GPIO)
27
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising