Texas Instruments | TMS320DM643x DMP General-Purpose Input/Output (GPIO) (Rev. B) | User Guides | Texas Instruments TMS320DM643x DMP General-Purpose Input/Output (GPIO) (Rev. B) User guides

Texas Instruments TMS320DM643x DMP General-Purpose Input/Output (GPIO) (Rev. B) User guides
TMS320DM643x DMP
General-Purpose Input/Output (GPIO)
User's Guide
Literature Number: SPRU988B
March 2008
2
SPRU988B – March 2008
Submit Documentation Feedback
Contents
Preface ............................................................................................................................... 6
1
Introduction................................................................................................................ 7
2
1.1
Purpose of the Peripheral ....................................................................................... 7
1.2
Features ........................................................................................................... 7
1.3
Functional Block Diagram ....................................................................................... 7
1.4
Industry Standard(s) Compliance Statement ................................................................. 7
Peripheral Architecture ................................................................................................ 8
..................................................................................................... 8
2.2
Signal Descriptions .............................................................................................. 8
2.3
Pin Multiplexing ................................................................................................... 8
2.4
Endianness Considerations ..................................................................................... 8
2.5
GPIO Register Structure ........................................................................................ 9
2.6
Using a GPIO Signal as an Output ........................................................................... 12
2.7
Using a GPIO Signal as an Input ............................................................................. 12
2.8
Reset Considerations .......................................................................................... 13
2.9
Initialization ...................................................................................................... 13
2.10 Interrupt Support ................................................................................................ 13
2.11 EDMA Event Support .......................................................................................... 15
2.12 Power Management ............................................................................................ 15
2.13 Emulation Considerations ..................................................................................... 16
3
Registers .................................................................................................................. 16
3.1
Peripheral Identification Register (PID) ...................................................................... 17
3.2
Peripheral Control Register (PCR) ........................................................................... 18
3.3
GPIO Interrupt Per-Bank Enable Register (BINTEN) ...................................................... 19
3.4
GPIO Direction Registers (DIRn) ............................................................................. 20
3.5
GPIO Output Data Register (OUT_DATAn)................................................................. 22
3.6
GPIO Set Data Register (SET_DATAn) ..................................................................... 24
3.7
GPIO Clear Data Register (CLR_DATAn)................................................................... 26
3.8
GPIO Input Data Register (IN_DATAn) ...................................................................... 28
3.9
GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn) ............................................ 30
3.10 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn).......................................... 32
3.11 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn) ........................................... 34
3.12 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) ........................................ 36
3.13 GPIO Interrupt Status Register (INTSTATn) ................................................................ 38
Appendix A Revision History ............................................................................................. 40
2.1
Clock Control
SPRU988B – March 2008
Submit Documentation Feedback
Table of Contents
3
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
4
GPIO Peripheral Block Diagram ........................................................................................... 8
Peripheral Identification Register (PID).................................................................................. 17
Peripheral Control Register (PCR) ....................................................................................... 18
GPIO Interrupt Per-Bank Enable Register (BINTEN).................................................................. 19
GPIO Banks 0 and 1 Direction Register (DIR01) ...................................................................... 20
GPIO Banks 2 and 3 Direction Register (DIR23) ...................................................................... 20
GPIO Banks 4 and 5 Direction Register (DIR45) ...................................................................... 20
GPIO Bank 6 Direction Register (DIR6) ................................................................................. 20
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01)......................................................... 22
GPIO Banks 2 and 3 Output Data Register (OUT_DATA23)......................................................... 22
GPIO Banks 4 and 5 Output Data Register (OUT_DATA45)......................................................... 22
GPIO Bank 6 Output Data Register (OUT_DATA6) ................................................................... 22
GPIO Banks 0 and 1 Set Data Register (SET_DATA01) ............................................................. 24
GPIO Banks 2 and 3 Set Data Register (SET_DATA23) ............................................................. 24
GPIO Banks 4 and 5 Set Data Register (SET_DATA45) ............................................................. 24
GPIO Bank 6 Set Data Register (SET_DATA6) ....................................................................... 24
GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) .......................................................... 26
GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .......................................................... 26
GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) .......................................................... 26
GPIO Bank 6 Clear Data Register (CLR_DATA6) ..................................................................... 26
GPIO Banks 0 and 1 Input Data Register (IN_DATA01) .............................................................. 28
GPIO Banks 2 and 3 Input Data Register (IN_DATA23) .............................................................. 28
GPIO Banks 4 and 5 Input Data Register (IN_DATA45) .............................................................. 28
GPIO Bank 6 Input Data Register (IN_DATA6) ........................................................................ 28
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (SET_RIS_TRIG01) .................................... 30
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (SET_RIS_TRIG23) .................................... 30
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register (SET_RIS_TRIG45) .................................... 31
GPIO Bank 6 Set Rising Edge Interrupt Register (SET_RIS_TRIG6) .............................................. 31
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG01) ................................. 32
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG23) ................................. 32
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG45) ................................. 33
GPIO Bank 6 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG6) ............................................ 33
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (SET_FAL_TRIG01) ................................... 34
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (SET_FAL_TRIG23) ................................... 34
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register (SET_FAL_TRIG45) ................................... 35
GPIO Bank 6 Set Falling Edge Interrupt Register (SET_FAL_TRIG6).............................................. 35
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG01)................................. 36
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG23)................................. 36
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG45)................................. 37
GPIO Bank 6 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG6) ........................................... 37
GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ........................................................ 38
GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ........................................................ 38
GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) ........................................................ 39
GPIO Bank 6 Interrupt Status Register (INTSTAT6) .................................................................. 39
List of Figures
SPRU988B – March 2008
Submit Documentation Feedback
List of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A-1
GPIO Register Bits and Banks Associated With GPIO Signals ....................................................... 9
GPIO Interrupts to the DSP CPU ........................................................................................ 14
GPIO Synchronization Events to the EDMA ............................................................................ 15
General-Purpose Input/Output (GPIO) Registers ...................................................................... 16
Peripheral Identification Register (PID) Field Descriptions ........................................................... 17
Peripheral Control Register (PCR) Field Descriptions................................................................. 18
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ........................................... 19
GPIO Direction Register (DIRn) Field Descriptions .................................................................... 21
GPIO Output Data Register (OUT_DATAn) Field Descriptions ...................................................... 23
GPIO Set Data Register (SET_DATAn) Field Descriptions .......................................................... 25
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ........................................................ 27
GPIO Input Data Register (IN_DATAn) Field Descriptions ........................................................... 29
GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn) Field Descriptions ................................. 31
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions ............................... 33
GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn) Field Descriptions................................. 35
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions .............................. 37
GPIO Interrupt Status Register (INTSTATn) Field Descriptions ..................................................... 39
Document Revision History ............................................................................................... 40
SPRU988B – March 2008
Submit Documentation Feedback
List of Tables
5
Preface
SPRU988B – March 2008
Read This First
About This Manual
Describes the general-purpose input/output (GPIO) peripheral in the TMS320DM643x Digital Media
Processor (DMP). The GPIO peripheral provides dedicated general-purpose pins that can be configured
as either inputs or outputs. When configured as an input, you can detect the state of the input by reading
the state of an internal register. When configured as an output, you can write to an internal register to
control the state driven on the output pin.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
The current documentation that describes the DM643x DMP, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRU978 — TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM643x Digital Media Processor (DMP).
SPRU983 — TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
6
Preface
SPRU988B – March 2008
Submit Documentation Feedback
User's Guide
SPRU988B – March 2008
General-Purpose Input/Output (GPIO)
1
Introduction
The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or
outputs. When configured as an output, you can write to an internal register to control the state driven on
the output pin. When configured as an input, you can detect the state of the input by reading the state of
an internal register.
1.1
Purpose of the Peripheral
Most system-on-chip (SoC) devices require some general-purpose input/output (GPIO) functionality in
order to interact with other components in the system using low-speed interface pins. The control and use
of the GPIO capability on this device is grouped together in the GPIO peripheral and is described in the
following sections.
1.2
Features
The GPIO peripheral consists of the following features.
• Output set/clear functionality through separate data set and clear registers allows multiple software
processes to control GPIO signals without critical section protection.
• Set/clear functionality through writing to a single output data register is also supported.
• Separate input/output registers
– Output register can be read to reflect output drive status.
– Input register can be read to reflect pin status.
• All GPIO signals can be used as interrupt sources with configurable edge detection.
• All GPIO signals can be used to generate events to the EDMA.
1.3
Functional Block Diagram
Figure 1 shows a block diagram of the GPIO peripheral.
1.4
Industry Standard(s) Compliance Statement
The GPIO peripheral connects to external devices. While it is possible that the software implements some
standard connectivity protocol over GPIO, the GPIO peripheral itself is not compliant with any such
standards.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
7
www.ti.com
Peripheral Architecture
Figure 1. GPIO Peripheral Block Diagram
DIR
register
Direction
logic
SET_DATA
register
CLR_DATA
register
OUTDATA
register
GPIO
signal
Synchronizing flip−flops
INDATA
register
SET_RIS_TRIG
register
CLR_RIS_TRIG
register
SET_FAL_TRIG
register
Interrupt to
DSP CPU
Edge
detection
logic
CLR_FAL_TRIG
register
EDMA event
INSTAT
register
2
Peripheral Architecture
The following sections describe the GPIO peripheral.
2.1
Clock Control
The input clock to the GPIO peripheral represents PLL1 divided by 6. The maximum operation speed for
the GPIO peripheral is 10 MHz.
2.2
Signal Descriptions
The DM643x device supports up to 111 GPIO signals, GP[110-0]. For information on the package pinout
of each GPIO signal, refer to the device data manual.
2.3
Pin Multiplexing
On the DM643x DMP extensive pin multiplexing is used to accommodate the largest number of peripheral
functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. Refer to the device-specific
data manual to determine how pin multiplexing affects the GPIO module.
2.4
Endianness Considerations
The GPIO operation is independent of endianness; therefore, there are no endianness considerations for
the GPIO module.
8
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5
GPIO Register Structure
The GPIO signals are grouped into banks of 16 signals per bank.
Associated with each bank of GPIO signals, there are several registers that control use of the GPIO bits,
and within those registers, various control fields for each GPIO signal. The GPIO control registers are
organized as one 32-bit register per pair of banks of GPIO signals. These control registers are further
grouped into banks with one set of control registers per bank.
The register names for each bank of control registers (or pair of banks of GPIO bits) are all of the form
register_nameXY, where X and Y are the two banks of GPIO bits controlled, such as 01, 23, 45, etc. The
register fields associated with each GPIO are all of the form field_nameN, where N is the number of the
GPIO signal. For example, for GP[0], which is located in GPIO bank 0, the control register names are of
the form register_name01, and the register fields associated with GP[0] are all of the form field_name0.
The GP[0] control bits are located in bit 0 of each of these registers. Contrastingly, for GP[110], which is
located in GPIO bank 6, the control register names are all of the form register_name6, and the register
fields associated with GP[110] are of the form field_name110. The GP[110] control bits are located in
bit 14 of each of these registers.
Table 1 shows the banks and register control bit information associated with each GPIO pin on the device.
Table 1 can be used to locate the register bits that control each GPIO signal. Detailed information
regarding the specific register names for each bank and the contents and function of these registers is
presented in Section 3.
Since there are an odd number of banks of GPIOs, the upper 16-bit of registers for the last pair are
reserved and have no effect. For the interrupt configuration, the registers associated with GPIO signals
that do not support interrupt capability are also reserved and have no effect.
Table 1. GPIO Register Bits and Banks Associated With GPIO Signals
GPIO Signal
Bank Number
Control Registers
Register Field
Bit Number
GP[0]
0
register_name01
field_name0
Bit 0
GP[1]
0
register_name01
field_name1
Bit 1
GP[2]
0
register_name01
field_name2
Bit 2
GP[3]
0
register_name01
field_name3
Bit 3
GP[4]
0
register_name01
field_name4
Bit 4
GP[5]
0
register_name01
field_name5
Bit 5
GP[6]
0
register_name01
field_name6
Bit 6
GP[7]
0
register_name01
field_name7
Bit 7
GP[8]
0
register_name01
field_name8
Bit 8
GP[9]
0
register_name01
field_name9
Bit 9
GP[10]
0
register_name01
field_name10
Bit 10
GP[11]
0
register_name01
field_name11
Bit 11
GP[12]
0
register_name01
field_name12
Bit 12
GP[13]
0
register_name01
field_name13
Bit 13
GP[14]
0
register_name01
field_name14
Bit 14
GP[15]
0
register_name01
field_name15
Bit 15
GP[16]
1
register_name01
field_name16
Bit 16
GP[17]
1
register_name01
field_name17
Bit 17
GP[18]
1
register_name01
field_name18
Bit 18
GP[19]
1
register_name01
field_name19
Bit 19
GP[20]
1
register_name01
field_name20
Bit 20
GP[21]
1
register_name01
field_name21
Bit 21
GP[22]
1
register_name01
field_name22
Bit 22
GP[23]
1
register_name01
field_name23
Bit 23
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
9
www.ti.com
Peripheral Architecture
Table 1. GPIO Register Bits and Banks Associated With GPIO Signals (continued)
10
GPIO Signal
Bank Number
Control Registers
Register Field
Bit Number
GP[24]
1
register_name01
field_name24
Bit 24
GP[25]
1
register_name01
field_name25
Bit 25
GP[26]
1
register_name01
field_name26
Bit 26
GP[27]
1
register_name01
field_name27
Bit 27
GP[28]
1
register_name01
field_name28
Bit 28
GP[29]
1
register_name01
field_name29
Bit 29
GP[30]
1
register_name01
field_name30
Bit 30
GP[31]
1
register_name01
field_name31
Bit 31
GP[32]
2
register_name23
field_name32
Bit 0
GP[33]
2
register_name23
field_name33
Bit 1
GP[34]
2
register_name23
field_name34
Bit 2
GP[35]
2
register_name23
field_name35
Bit 3
GP[36]
2
register_name23
field_name36
Bit 4
GP[37]
2
register_name23
field_name37
Bit 5
GP[38]
2
register_name23
field_name38
Bit 6
GP[39]
2
register_name23
field_name39
Bit 7
GP[40]
2
register_name23
field_name40
Bit 8
GP[41]
2
register_name23
field_name41
Bit 9
GP[42]
2
register_name23
field_name42
Bit 10
GP[43]
2
register_name23
field_name43
Bit 11
GP[44]
2
register_name23
field_name44
Bit 12
GP[45]
2
register_name23
field_name45
Bit 13
GP[46]
2
register_name23
field_name46
Bit 14
GP[47]
2
register_name23
field_name47
Bit 15
GP[48]
3
register_name23
field_name48
Bit 16
GP[49]
3
register_name23
field_name49
Bit 17
GP[50]
3
register_name23
field_name50
Bit 18
GP[51]
3
register_name23
field_name51
Bit 19
GP[52]
3
register_name23
field_name52
Bit 20
GP[53]
3
register_name23
field_name53
Bit 21
GP[54]
3
register_name23
field_name54
Bit 22
GP[55]
3
register_name23
field_name55
Bit 23
GP[56]
3
register_name23
field_name56
Bit 24
GP[57]
3
register_name23
field_name57
Bit 25
GP[58]
3
register_name23
field_name58
Bit 26
GP[59]
3
register_name23
field_name59
Bit 27
GP[60]
3
register_name23
field_name60
Bit 28
GP[61]
3
register_name23
field_name61
Bit 29
GP[62]
3
register_name23
field_name62
Bit 30
GP[63]
3
register_name23
field_name63
Bit 31
GP[64]
4
register_name45
field_name64
Bit 0
GP[65]
4
register_name45
field_name65
Bit 1
GP[66]
4
register_name45
field_name66
Bit 2
GP[67]
4
register_name45
field_name67
Bit 3
GP[68]
4
register_name45
field_name68
Bit 4
GP[69]
4
register_name45
field_name69
Bit 5
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
Table 1. GPIO Register Bits and Banks Associated With GPIO Signals (continued)
GPIO Signal
Bank Number
Control Registers
Register Field
Bit Number
GP[70]
4
register_name45
field_name70
Bit 6
GP[71]
4
register_name45
field_name71
Bit 7
GP[72]
4
register_name45
field_name72
Bit 8
GP[73]
4
register_name45
field_name73
Bit 9
GP[74]
4
register_name45
field_name74
Bit 10
GP[75]
4
register_name45
field_name75
Bit 11
GP[76]
4
register_name45
field_name76
Bit 12
GP[77]
4
register_name45
field_name77
Bit 13
GP[78]
4
register_name45
field_name78
Bit 14
GP[79]
4
register_name45
field_name79
Bit 15
GP[80]
5
register_name45
field_name80
Bit 16
GP[81]
5
register_name45
field_name81
Bit 17
GP[82]
5
register_name45
field_name82
Bit 18
GP[83]
5
register_name45
field_name83
Bit 19
GP[84]
5
register_name45
field_name84
Bit 20
GP[85]
5
register_name45
field_name85
Bit 21
GP[86]
5
register_name45
field_name86
Bit 22
GP[87]
5
register_name45
field_name87
Bit 23
GP[88]
5
register_name45
field_name88
Bit 24
GP[89]
5
register_name45
field_name89
Bit 25
GP[90]
5
register_name45
field_name90
Bit 26
GP[91]
5
register_name45
field_name91
Bit 27
GP[92]
5
register_name45
field_name92
Bit 28
GP[93]
5
register_name45
field_name93
Bit 29
GP[94]
5
register_name45
field_name94
Bit 30
GP[95]
5
register_name45
field_name95
Bit 31
GP[96]
6
register_name6
field_name96
Bit 0
GP[97]
6
register_name6
field_name97
Bit 1
GP[98]
6
register_name6
field_name98
Bit 2
GP[99]
6
register_name6
field_name99
Bit 3
GP[100]
6
register_name6
field_name100
Bit 4
GP[101]
6
register_name6
field_name101
Bit 5
GP[102]
6
register_name6
field_name102
Bit 6
GP[103]
6
register_name6
field_name103
Bit 7
GP[104]
6
register_name6
field_name104
Bit 8
GP[105]
6
register_name6
field_name105
Bit 9
GP[106]
6
register_name6
field_name106
Bit 10
GP[107]
6
register_name6
field_name107
Bit 11
GP[108]
6
register_name6
field_name108
Bit 12
GP[109]
6
register_name6
field_name109
Bit 13
GP[110]
6
register_name6
field_name110
Bit 14
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
11
www.ti.com
Peripheral Architecture
2.6
Using a GPIO Signal as an Output
GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO
direction register (DIR). This section describes using the GPIO signal as an output signal.
2.6.1
Configuring a GPIO Output Signal
To configure a given GPIO signal as an output, clear the bit in DIR that is associated with the desired
GPIO signal. For detailed information on DIR, see Section 3.
2.6.2
Controlling the GPIO Output Signal State
There are three registers that control the output state driven on a GPIO signal configured as an output:
• GPIO set data register (SET_DATA) controls driving GPIO signals high
• GPIO clear data register (CLR_DATA) controls driving GPIO signals low
• GPIO output data register (OUT_DATA) contains the current state of the output signals
Reading SET_DATA, CLR_DATA, and OUT_DATA returns the output state not necessarily the actual
signal state (since some signals may be configured as inputs). The actual signal state is read using the
GPIO input data register (IN_DATA) associated with the desired GPIO signal. IN_DATA contains the
actual logic state on the external signal.
For detailed information on these registers, see Section 3.
2.6.2.1
Driving a GPIO Output Signal High
To drive a GPIO signal high, use one of the following methods:
• Write a logic 1 to the bit in SET_DATA associated with the desired GPIO signal(s) to be driven high.
Bit positions in SET_DATA containing logic 0 do not affect the state of the associated output signals.
• Modify the bit in OUT_DATA associated with the desired GPIO signal by using a read-modify-write
operation. The logic states driven on the GPIO output signals match the logic values written to all bits
in OUT_DATA.
For GPIO signals configured as inputs, the values written to the associated SET_DATA, CLR_DATA, and
OUT_DATA bits have no effect.
2.6.2.2
Driving a GPIO Output Signal Low
To drive a GPIO signal low, use one of the following methods:
•
•
Write a logic 1 to the bit in CLR_DATA associated with the desired GPIO signal(s) to be driven low. Bit
positions in CLR_DATA containing logic 0 do not affect the state of the associated output signals.
Modify the bit in OUT_DATA associated with the desired GPIO signal by using a read-modify-write
operation. The logic states driven on the GPIO output signals match the logic values written to all bits
in OUT_DATA.
For GPIO signals configured as inputs, the values written to the associated SET_DATA, CLR_DATA, and
OUT_DATA bits have no effect.
2.7
Using a GPIO Signal as an Input
GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO
direction register (DIR). This section describes using the GPIO signal as an input signal.
2.7.1
Configuring a GPIO Input Signal
To configure a given GPIO signal as an input, set the bit in DIR that is associated with the desired GPIO
signal. For detailed information on DIR, see Section 3.
12
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.7.2
Reading a GPIO Input Signal
The current state of the GPIO signals is read using the GPIO input data register (IN_DATA).
• For GPIO signals configured as inputs, reading IN_DATA returns the state of the input signal
synchronized to the GPIO peripheral clock.
• For GPIO signals configured as outputs, reading IN_DATA returns the output value being driven by the
device.
Some signals may utilize open-drain output buffers for wired-logic operations. For open-drain GPIO
signals, reading IN_DATA returns the wired-logic value on the signal (which will not be driven by the
device alone). Information on any signals using open-drain outputs is available in the device data manual.
To use GPIO input signals as interrupt sources, see section Section 2.10.
2.8
Reset Considerations
The GPIO peripheral has two reset sources: software reset and hardware reset.
2.8.1
Software Reset Considerations
A software reset (such as a reset initiated through the emulator) does not modify the configuration and
state of the GPIO signals. A reset invoked via the Power and Sleep Controller (PSC) (GPIO clock disable,
PSC reset, followed by GPIO clock enable) will result in the default configuration register settings.
2.8.2
Hardware Reset Considerations
A hardware reset does reset the GPIO configuration and data registers to their default states; therefore,
affecting the configuration and state of the GPIO signals.
2.9
Initialization
The following steps are required to configure the GPIO module after a hardware reset:
1. Perform the necessary device pin multiplexing setup (see the device-specific data manual).
2. Program the VDD3P3V_PWDN register to power up the IO pins for the GPIO module (see the
device-specific data manual).
3. Program the Power and Sleep Controller (PSC) to enable the GPIO module. For details on the PSC,
see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).
4. Program the direction, data, and interrupt control registers to set the configuration of the desired GPIO
pins (described in this document).
The GPIO module is now ready to perform data transactions.
2.10 Interrupt Support
The GPIO peripheral can send an interrupt event to the DSP CPU.
2.10.1
Interrupt Events and Requests
All GPIO signals can be configured to generate interrupts. The DM643x device supports interrupts from
single GPIO signals, interrupts from banks of GPIO signals, or both. The interrupt mapping from the GPIO
peripheral to the DSP CPU is shown in Table 2. Note that the GPIO interrupts can also be used to provide
synchronization events to the EDMA. See Section 2.11 for additional information.
2.10.2
Enabling GPIO Interrupt Events
GPIO interrupt events are enabled in banks of 16 by setting the appropriate bit(s) in the GPIO interrupt
per-bank enable register (BINTEN). For example, to enable bank 0 interrupts (events from GP[15-0]), set
bit 0 in BINTEN; to enable bank 3 interrupts (events from GP[63-48]), set bit 3 in BINTEN.
For detailed information on BINTEN, see Section 3.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
13
www.ti.com
Peripheral Architecture
Table 2. GPIO Interrupts to the DSP CPU
2.10.3
Interrupt Source
Acronym
DSP Interrupt Number
GP[0]
GPIO0
64
GP[1]
GPIO1
65
GP[2]
GPIO2
66
GP[3]
GPIO3
67
GP[4]
GPIO4
68
GP[5]
GPIO5
69
GP[6]
GPIO6
70
GP[7]
GPIO7
71
GPIO Bank 0
GPIOBNK0
72
GPIO Bank 1
GPIOBNK1
73
GPIO Bank 2
GPIOBNK2
74
GPIO Bank 3
GPIOBNK3
75
GPIO Bank 4
GPIOBNK4
76
GPIO Bank 5
GPIOBNK5
77
GPIO Bank 6
GPIOBNK6
78
Configuring GPIO Interrupt Edge Triggering
Each GPIO interrupt source can be configured to generate an interrupt on the GPIO signal rising edge,
falling edge, both edges, or neither edge (no event). The edge detection is synchronized to the GPIO
peripheral module clock.
The following four registers control the configuration of the GPIO interrupt edge detection:
• The GPIO set rising edge interrupt register (SET_RIS_TRIG) enables GPIO interrupts
occurrence of a rising edge on the GPIO signal.
• The GPIO clear rising edge interrupt register (CLR_RIS_TRIG) disables GPIO interrupts
occurrence of a rising edge on the GPIO signal.
• The GPIO set falling edge interrupt register (SET_FAL_TRIG) enables GPIO interrupts
occurrence of a falling edge on the GPIO signal.
• The GPIO clear falling edge interrupt register (CLR_FAL_TRIG) disables GPIO interrupts
occurrence of a falling edge on the GPIO signal.
on the
on the
on the
on the
To configure a GPIO interrupt to occur only on rising edges of the GPIO signal:
• Write a logic 1 to the associated bit in SET_RIS_TRIG.
• Write a logic 1 to the associated bit in CLR_FAL_TRIG.
To configure a GPIO interrupt to occur only on falling edges of the GPIO signal:
• Write a logic 1 to the associated bit in SET_FAL_TRIG.
• Write a logic 1 to the associated bit in CLR_RIS_TRIG.
To configure a GPIO interrupt to occur on both the rising and falling edges of the GPIO signal:
• Write a logic 1 to the associated bit in SET_RIS_TRIG.
• Write a logic 1 to the associated bit in SET_FAL_TRIG.
To disable a specific GPIO interrupt:
• Write a logic 1 to the associated bit in CLR_RIS_TRIG.
• Write a logic 1 to the associated bit in CLR_FAL_TRIG.
For detailed information on these registers, see Section 3.
Note that the direction of the GPIO signal does not have to be an input for the interrupt event generation
to work. When a GPIO signal is configured as an output, the software can change the GPIO signal state
and, in turn, generate an interrupt. This can be useful for debugging interrupt signal connectivity.
14
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.10.4
GPIO Interrupt Status
The status of GPIO interrupt events can be monitored by reading the GPIO interrupt status register
(INTSTAT). Pending GPIO interrupts are indicated with a logic 1 in the associated bit position; interrupts
that are not pending are indicated with a logic 0.
For individual GPIO interrupts that are directly routed to the DSP subsystem, the interrupt status can be
read by reading the associated interrupt flag in the CPU. For the GPIO bank interrupts, INTSTAT can be
used to determine which GPIO interrupt occurred. It is the responsibility of software to ensure that all
pending GPIO interrupts are appropriately serviced.
Pending GPIO interrupt flags can be cleared by writing a logic 1 to the associated bit position in INTSTAT.
For detailed information on INTSTAT, see Section 3.
2.10.5
Interrupt Multiplexing
No GPIO interrupts are multiplexed with other interrupt functions on the DM643x device.
2.11 EDMA Event Support
The GPIO peripheral can provide synchronization events to the EDMA. The EDMA events supported on
this device are listed in Table 3.
Table 3. GPIO Synchronization Events to the EDMA
Event Source
Event Name
EDMA Synchronization Event Number
GP[0] Interrupt
GPINT0
32
GP[1] Interrupt
GPINT1
33
GP[2] Interrupt
GPINT2
34
GP[3] Interrupt
GPINT3
35
GP[4] Interrupt
GPINT4
36
GP[5] Interrupt
GPINT5
37
GP[6] Interrupt
GPINT6
38
GP[7] Interrupt
GPINT7
39
GPIO Bank 0 Interrupt
GPBNKINT0
40
GPIO Bank 1 Interrupt
GPBNKINT1
41
GPIO Bank 2 Interrupt
GPBNKINT2
42
GPIO Bank 3 Interrupt
GPBNKINT3
43
GPIO Bank 4 Interrupt
GPBNKINT4
44
GPIO Bank 5 Interrupt
GPBNKINT5
45
GPIO Bank 6 Interrupt
GPBNKINT6
46
2.12 Power Management
The GPIO peripheral can be placed in reduced-power modes to conserve power during periods of low
activity. The power management of the GPIO peripheral is controlled by the processor Power and Sleep
Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on
the device. For detailed information on power management procedures using the PSC, see the
TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).
When the GPIO peripheral is placed in a low-power state by the PSC, the interrupt generation capability is
suspended until the GPIO peripheral is removed from the low-power state. While in the low-power state,
the GPIO signals configured as outputs are maintained at their state prior to the GPIO peripheral entering
the low-power state.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
15
www.ti.com
Registers
2.13 Emulation Considerations
The GPIO peripheral is not affected by emulation suspend events (such as halts and breakpoints).
3
Registers
Table 4 lists the memory-mapped registers for the general-purpose input/output (GPIO). See the
device-specific data manual for the memory address of these registers.
Table 4. General-Purpose Input/Output (GPIO) Registers
Offset
Acronym
Register Description
0h
PID
Peripheral Identification Register
Section 3.1
Section
4h
PCR
Peripheral Control Register
Section 3.2
8h
BINTEN
GPIO Interrupt Per-Bank Enable Register
Section 3.3
Ch
-
Reserved
GPIO Banks 0 and 1
10h
DIR01
GPIO Banks 0 and 1 Direction Register
Section 3.4
14h
OUT_DATA01
GPIO Banks 0 and 1 Output Data Register
Section 3.5
18h
SET_DATA01
GPIO Banks 0 and 1 Set Data Register
Section 3.6
1Ch
CLR_DATA01
GPIO Banks 0 and 1 Clear Data Register
Section 3.7
20h
IN_DATA01
GPIO Banks 0 and 1 Input Data Register
Section 3.8
24h
SET_RIS_TRIG01
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
Section 3.9
28h
CLR_RIS_TRIG01
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
Section 3.10
2Ch
SET_FAL_TRIG01
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
Section 3.11
30h
CLR_FAL_TRIG01
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
Section 3.12
34h
INTSTAT01
GPIO Banks 0 and 1 Interrupt Status Register
Section 3.13
GPIO Banks 2 and 3
38h
DIR23
GPIO Banks 2 and 3 Direction Register
Section 3.4
3Ch
OUT_DATA23
GPIO Banks 2 and 3 Output Data Register
Section 3.5
40h
SET_DATA23
GPIO Banks 2 and 3 Set Data Register
Section 3.6
44h
CLR_DATA23
GPIO Banks 2 and 3 Clear Data Register
Section 3.7
48h
IN_DATA23
GPIO Banks 2 and 3 Input Data Register
Section 3.8
4Ch
SET_RIS_TRIG23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
Section 3.9
50h
CLR_RIS_TRIG23
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
Section 3.10
54h
SET_FAL_TRIG23
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
Section 3.11
58h
CLR_FAL_TRIG23
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
Section 3.12
5Ch
INTSTAT23
GPIO Banks 2 and 3 Interrupt Status Register
Section 3.13
60h
DIR45
GPIO Banks 4 and 5 Direction Register
Section 3.4
64h
OUT_DATA45
GPIO Banks 4 and 5 Output Data Register
Section 3.5
GPIO Banks 4 and 5
16
68h
SET_DATA45
GPIO Banks 4 and 5 Set Data Register
Section 3.6
6Ch
CLR_DATA45
GPIO Banks 4 and 5 Clear Data Register
Section 3.7
70h
IN_DATA45
GPIO Banks 4 and 5 Input Data Register
Section 3.8
74h
SET_RIS_TRIG45
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
Section 3.9
78h
CLR_RIS_TRIG45
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
Section 3.10
7Ch
SET_FAL_TRIG45
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
Section 3.11
80h
CLR_FAL_TRIG45
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
Section 3.12
84h
INTSTAT45
GPIO Banks 4 and 5 Interrupt Status Register
Section 3.13
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Table 4. General-Purpose Input/Output (GPIO) Registers (continued)
Offset
Acronym
Register Description
Section
GPIO Bank 6
3.1
88h
DIR6
GPIO Bank 6 Direction Register
Section 3.4
8Ch
OUT_DATA6
GPIO Bank 6 Output Data Register
Section 3.5
90h
SET_DATA6
GPIO Bank 6 Set Data Register
Section 3.6
94h
CLR_DATA6
GPIO Bank 6 Clear Data Register
Section 3.7
98h
IN_DATA6
GPIO Bank 6 Input Data Register
Section 3.8
9Ch
SET_RIS_TRIG6
GPIO Bank 6 Set Rising Edge Interrupt Register
Section 3.9
A0h
CLR_RIS_TRIG6
GPIO Bank 6 Clear Rising Edge Interrupt Register
Section 3.10
A4h
SET_FAL_TRIG6
GPIO Bank 6 Set Falling Edge Interrupt Register
Section 3.11
A8h
CLR_FAL_TRIG6
GPIO Bank 6 Clear Falling Edge Interrupt Register
Section 3.12
ACh
INTSTAT6
GPIO Bank 6 Interrupt Status Register
Section 3.13
Peripheral Identification Register (PID)
The peripheral identification register (PID) contains identification data (type, class, and revision) for the
peripheral. PID is shown in Figure 2 and described in Table 5.
Figure 2. Peripheral Identification Register (PID)
31
30
29
28
27
16
SCHEME
Reserved
FUNCTION
R-1
R-0
R-483h
15
11
10
8
7
6
5
0
RTL
MAJOR
CUSTOM
MINOR
R-0
R-1
R-0
R-5h
LEGEND: R = Read only; -n = value after reset
Table 5. Peripheral Identification Register (PID) Field Descriptions
Bit
Field
Value
Description
31-30
SCHEME
1
Scheme of PID encoding. This field is fixed to 01.
29-28
Reserved
0
Reserved
27-16
FUNCTION
0-FFFh
Function.
15-11
RTL
0-1Fh
10-8
MAJOR
0-Fh
7-6
CUSTOM
0-3h
5-0
MINOR
0-Fh
For GPIO = 483h
RTL identification.
For GPIO = 0
Major Revision. GPIO code revisions are indicated by a revision code taking the format
MAJOR_REVISION.MINOR_REVISION.
Major revision = 1h
Custom identification.
For GPIO = 0
Minor Revision. GPIO code revisions are indicated by a revision code taking the format
MAJOR_REVISION.MINOR_REVISION.
Minor revision = 5h
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
17
www.ti.com
Registers
3.2
Peripheral Control Register (PCR)
The peripheral control register (PCR) determines the emulation suspend mode. The FREE bit is fixed at 1
so the GPIO ignores an emulation suspend request signal and operates as usual in emulation suspension.
PCR is shown in Figure 3 and described in Table 6.
Figure 3. Peripheral Control Register (PCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
SOFT
FREE
R-0
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 6. Peripheral Control Register (PCR) Field Descriptions
Bit
31-2
18
Field
Value
Description
Reserved
0
Reserved
1
SOFT
0
Soft bit enable mode bit. This bit is used in conjunction with FREE bit to determine the emulation
suspend mode. FREE = 1, so this bit has no effect.
0
FREE
1
Free-running enable mode bit. The FREE bit is fixed at 1, so the GPIO is free-running in emulation
suspend mode.
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
3.3
GPIO Interrupt Per-Bank Enable Register (BINTEN)
The GPIO interrupt per-bank enable register (BINTEN) is shown in Figure 4 and described in Table 7. For
information on which GPIO signals are associated with each bank, see Table 1. Note that the bits in
BINTEN control both the interrupt and EDMA events.
Figure 4. GPIO Interrupt Per-Bank Enable Register (BINTEN)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
Field
Reserved
Value
0
EN6
Description
Reserved
Bank 6 interrupt enable is used to disable or enable the bank 6 interrupts (events from GP[110- 96]).
0
Bank 6 interrupts are disabled.
1
Bank 6 interrupts are enabled.
EN5
Bank 5 interrupt enable is used to disable or enable the bank 5 interrupts (events from GP[95- 80]).
0
Bank 5 interrupts are disabled.
1
Bank 5 interrupts are enabled.
EN4
Bank 4 interrupt enable is used to disable or enable the bank 4 interrupts (events from GP[79- 64]).
0
Bank 4 interrupts are disabled.
1
Bank 4 interrupts are enabled.
EN3
Bank 3 interrupt enable is used to disable or enable the bank 3 interrupts (events from GP[63- 48])
0
Bank 3 interrupts are disabled.
1
Bank 3 interrupts are enabled.
EN2
Bank 2 interrupt enable is used to disable or enable the bank 2 interrupts (events from GP[47- 32]).
0
Bank 2 interrupts are disabled.
1
Bank 2 interrupts are enabled.
EN1
Bank 1 interrupt enable is used to disable or enable the bank 1 interrupts (events from GP[31- 16]).
0
Bank 1 interrupts are disabled.
1
Bank 1 interrupts are enabled.
EN0
Bank 0 interrupt enable is used to disable or enable the bank 0 interrupts (events from GP[15- 0]).
0
Bank 0 interrupts are disabled.
1
Bank 0 interrupts are enabled.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
19
www.ti.com
Registers
3.4
GPIO Direction Registers (DIRn)
The GPIO direction register (DIRn) determines if GPIO pin n in GPIO bank I is an input or an output. Each
of the GPIO banks may have up to 16 GPIO pins. By default, all the GPIO pins are configured as inputs
(bit value = 1). The GPIO direction register (DIR01) is shown in Figure 5, DIR23 is shown in Figure 6,
DIR45 is shown in Figure 7, DIR6 is shown in Figure 8, and described in Table 8. See Table 1 to
determine the DIRn bit associated with each GPIO bank and pin number.
Figure 5. GPIO Banks 0 and 1 Direction Register (DIR01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DIR31
DIR30
DIR29
DIR28
DIR27
DIR26
DIR25
DIR24
DIR23
DIR22
DIR21
DIR20
DIR19
DIR18
DIR17
DIR16
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIR15
DIR14
DIR13
DIR12
DIR11
DIR10
DIR9
DIR8
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Figure 6. GPIO Banks 2 and 3 Direction Register (DIR23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DIR63
DIR62
DIR61
DIR60
DIR59
DIR58
DIR57
DIR56
DIR55
DIR54
DIR53
DIR52
DIR51
DIR50
DIR49
DIR48
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIR47
DIR46
DIR45
DIR44
DIR43
DIR42
DIR41
DIR40
DIR39
DIR38
DIR37
DIR36
DIR35
DIR34
DIR33
DIR32
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Figure 7. GPIO Banks 4 and 5 Direction Register (DIR45)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DIR95
DIR94
DIR93
DIR92
DIR91
DIR90
DIR89
DIR88
DIR87
DIR86
DIR85
DIR84
DIR83
DIR82
DIR81
DIR80
7
6
5
4
3
2
1
0
DIR71
DIR70
DIR69
DIR68
DIR67
DIR66
DIR65
DIR64
R/W-1
15
14
13
12
11
10
9
8
DIR79
DIR78
DIR77
DIR76
DIR75
DIR74
DIR73
DIR72
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Figure 8. GPIO Bank 6 Direction Register (DIR6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rsvd
DIR110
DIR109
DIR108
DIR107
DIR106
DIR105
DIR104
DIR103
DIR102
DIR101
DIR100
DIR99
DIR98
DIR97
DIR96
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
20
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Table 8. GPIO Direction Register (DIRn) Field Descriptions
Bit
Field
31-16
DIRn
15-0
Value
Description
Direction of GPIO pin n. The DIRn bit is used to control the direction (output = 0, input = 1) of pin n on
GPIO bank 2I + 1. This bit field configures the GPIO pins on GPIO banks 1, 3, and 5.
0
GPIO pin n is an output.
1
GPIO pin n is an input.
DIRn
Direction of GPIO pin n. The DIRn bit is used to control the direction (output = 0, input = 1) of pin n on
GPIO bank 2I. This bit field configures the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
GPIO pin n is an output.
1
GPIO pin n is an input.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
21
www.ti.com
Registers
3.5
GPIO Output Data Register (OUT_DATAn)
The GPIO output data register (OUT_DATAn) determines the value driven on the corresponding GPIO pin
n in GPIO bank I, if the pin is configured as an output (DIRn = 0). Writes do not affect pins not configured
as GPIO outputs. The bits in OUT_DATAn are set or cleared by writing directly to this register. A read of
OUT_DATAn returns the value of the register not the value at the pin (that might be configured as an
input). The GPIO output data register (OUT_DATA01) is shown in Figure 9, OUT_DATA23 is shown in
Figure 10, OUT_DATA45 is shown in Figure 11, OUT_DATA6 is shown in Figure 12, and described in
Table 9. See Table 1 to determine the OUT_DATAn bit associated with each GPIO bank and pin number.
Figure 9. GPIO Banks 0 and 1 Output Data Register (OUT_DATA01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 10. GPIO Banks 2 and 3 Output Data Register (OUT_DATA23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OUT63
OUT62
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT53
OUT52
OUT51
OUT50
OUT49
OUT48
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
OUT38
OUT37
OUT36
OUT35
OUT34
OUT33
OUT32
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 11. GPIO Banks 4 and 5 Output Data Register (OUT_DATA45)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OUT95
OUT94
OUT93
OUT92
OUT91
OUT90
OUT89
OUT88
OUT87
OUT86
OUT85
OUT84
OUT83
OUT82
OUT81
OUT80
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OUT79
OUT78
OUT77
OUT76
OUT75
OUT74
OUT73
OUT72
OUT71
OUT70
OUT69
OUT68
OUT67
OUT66
OUT65
OUT64
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 12. GPIO Bank 6 Output Data Register (OUT_DATA6)
31
16
Reserved
R-0
15
Rsvd
14
13
12
11
10
9
8
7
6
5
4
3
OUT110 OUT109 OUT108 OUT107 OUT106 OUT105 OUT104 OUT103 OUT102 OUT101 OUT100 OUT99
2
1
0
OUT98
OUT97
OUT96
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
22
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Table 9. GPIO Output Data Register (OUT_DATAn) Field Descriptions
Bit
Field
31-16
OUTn
15-0
Value
Description
Output drive state of GPIO pin n. The OUTn bit is used to drive the output (low = 0, high = 1) of pin n on
GPIO bank 2I + 1 only when pin n is configured as an output (DIRn = 0). The OUTn bit is ignored when
GPIO pin n is configured as an input. This bit field configures the GPIO pins on GPIO banks 1, 3, and 5.
0
GPIO pin n is driven low.
1
GPIO pin n is driven high.
OUTn
Output drive state of GPIO pin n. The OUTn bit is used to drive the output (low = 0, high = 1) of pin n on
GPIO bank 2I only when pin n is configured as an output (DIRn = 0). The OUTn bit is ignored when GPIO
pin n is configured as an input. This bit field configures the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
GPIO pin n is driven low.
1
GPIO pin n is driven high.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
23
www.ti.com
Registers
3.6
GPIO Set Data Register (SET_DATAn)
The GPIO set data register (SET_DATAn) controls driving high the corresponding GPIO pin n in GPIO
bank I, if the pin is configured as an output (DIRn = 0). Writes do not affect pins not configured as GPIO
outputs. The bits in SET_DATAn are set or cleared by writing directly to this register. A read of the SETn
bit returns the output drive state of the corresponding GPIO pin n. The GPIO set data register
(SET_DATA01) is shown in Figure 13, SET_DATA23 is shown in Figure 14, SET_DATA45 is shown in
Figure 15, SET_DATA6 is shown in Figure 16, and described in Table 10. See Table 1 to determine the
SET_DATAn bit associated with each GPIO bank and pin number.
Figure 13. GPIO Banks 0 and 1 Set Data Register (SET_DATA01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET31 SET30 SET29 SET28 SET27 SET26 SET25 SET24 SET23 SET22 SET21 SET20 SET19 SET18 SET17 SET16
R/W-0
15
14
13
12
11
10
SET15 SET14 SET13 SET12 SET11 SET10
9
8
7
6
5
4
3
2
1
0
SET9
SET8
SET7
SET6
SET5
SET4
SET3
SET2
SET1
SET0
17
16
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 14. GPIO Banks 2 and 3 Set Data Register (SET_DATA23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
SET63 SET62 SET61 SET60 SET59 SET58 SET57 SET56 SET55 SET54 SET53 SET52 SET51 SET50 SET49 SET48
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SET47 SET46 SET45 SET44 SET43 SET42 SET41 SET40 SET39 SET38 SET37 SET36 SET35 SET34 SET33 SET32
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 15. GPIO Banks 4 and 5 Set Data Register (SET_DATA45)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET95 SET94 SET93 SET92 SET91 SET90 SET89 SET88 SET87 SET86 SET85 SET84 SET83 SET82 SET81 SET80
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SET79 SET78 SET77 SET76 SET75 SET74 SET73 SET72 SET71 SET70 SET69 SET68 SET67 SET66 SET65 SET64
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 16. GPIO Bank 6 Set Data Register (SET_DATA6)
31
16
Reserved
R-0
15
Rsvd
14
13
12
11
10
9
8
7
6
5
4
SET110 SET109 SET108 SET107 SET106 SET105 SET104 SET103 SET102 SET101 SET100
3
2
1
0
SET99
SET98
SET97
SET96
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
24
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Table 10. GPIO Set Data Register (SET_DATAn) Field Descriptions
Bit
Field
31-16
SETn
15-0
Value
Description
Set output drive state of GPIO pin n. The SETn bit is used to set the output of pin n on GPIO bank 2I + 1
only when pin n is configured as an output (DIRn = 0). The SETn bit is ignored when GPIO pin n is
configured as an input. Writing a 1 to the SETn bit sets the output drive state of the corresponding GPIO
pin n; reading the SETn bit returns the output drive state of the corresponding GPIO pin n. This bit field
configures the GPIO pins on GPIO banks 1, 3, and 5.
0
No effect.
1
Set GPIO pin n output to 1.
SETn
Set output drive state of GPIO pin n. The SETn bit is used to set the output of pin n on GPIO bank 2I only
when pin n is configured as an output (DIRn = 0). The SETn bit is ignored when GPIO pin n is configured
as an input. Writing a 1 to the SETn bit sets the output drive state of the corresponding GPIO pin n;
reading the SETn bit returns the output drive state of the corresponding GPIO pin n. This bit field
configures the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
No effect.
1
Set GPIO pin n output to 1.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
25
www.ti.com
Registers
3.7
GPIO Clear Data Register (CLR_DATAn)
The GPIO clear data register (CLR_DATAn) controls driving low the corresponding GPIO pin n in GPIO
bank I, if the pin is configured as an output (DIRn = 0). Writes do not affect pins not configured as GPIO
outputs. The bits in CLR_DATAn are set or cleared by writing directly to this register. A read of the CLRn
bit returns the output drive state of the corresponding GPIO pin n. The GPIO clear data register
(CLR_DATA01) is shown in Figure 17, CLR_DATA23 is shown in Figure 18, CLR_DATA45 is shown in
Figure 19, CLR_DATA6 is shown in Figure 20, and described in Table 11. See Table 1 to determine the
CLR_DATAn bit associated with each GPIO bank and pin number.
Figure 17. GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR31 CLR30 CLR29 CLR28 CLR27 CLR26 CLR25 CLR24 CLR23 CLR22 CLR21 CLR20 CLR19 CLR18 CLR17 CLR16
R/W-0
15
14
13
12
11
10
CLR15 CLR14 CLR13 CLR12 CLR11 CLR10
9
8
7
6
5
4
3
2
1
0
CLR9
CLR8
CLR7
CLR6
CLR5
CLR4
CLR3
CLR2
CLR1
CLR0
17
16
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 18. GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
CLR63 CLR62 CLR61 CLR60 CLR59 CLR58 CLR57 CLR56 CLR55 CLR54 CLR53 CLR52 CLR51 CLR50 CLR49 CLR48
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR47 CLR46 CLR45 CLR44 CLR43 CLR42 CLR41 CLR40 CLR39 CLR38 CLR37 CLR36 CLR35 CLR34 CLR33 CLR32
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 19. GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR95 CLR94 CLR93 CLR92 CLR91 CLR90 CLR89 CLR88 CLR87 CLR86 CLR85 CLR84 CLR83 CLR82 CLR81 CLR80
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR79 CLR78 CLR77 CLR76 CLR75 CLR74 CLR73 CLR72 CLR71 CLR70 CLR69 CLR68 CLR67 CLR66 CLR65 CLR64
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 20. GPIO Bank 6 Clear Data Register (CLR_DATA6)
31
16
Reserved
R-0
15
Rsvd
14
13
12
11
10
9
8
7
6
5
4
CLR110 CLR109 CLR108 CLR107 CLR106 CLR105 CLR104 CLR103 CLR102 CLR101 CLR100
3
2
1
0
CLR99
CLR98
CLR97
CLR96
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
26
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Table 11. GPIO Clear Data Register (CLR_DATAn) Field Descriptions
Bit
Field
31-16
CLRn
15-0
Value
Description
Clear output drive state of GPIO pin n. The CLRn bit is used to clear the output of pin n on GPIO bank
2/ + 1 only when pin n is configured as an output (DIRn = 0). The CLRn bit is ignored when GPIO pin n is
configured as an input. Writing a 1 to the CLRn bit clears the output drive state of the corresponding GPIO
pin n; reading the CLRn bit returns the output drive state of the corresponding GPIO pin n. This bit field
configures the GPIO pins on GPIO banks 1, 3, and 5.
0
No effect.
1
Clear GPIO pin n output to 0.
CLRn
Clear output drive state of GPIO pin n. The CLRn bit is used to clear the output of pin n on GPIO bank 2I
only when pin n is configured as an output (DIRn = 0). The CLRn bit is ignored when GPIO pin n is
configured as an input. Writing a 1 to the CLRn bit clears the output drive state of the corresponding GPIO
pin n; reading the CLRn bit returns the output drive state of the corresponding GPIO pin n. This bit field
configures the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
No effect.
1
Clear GPIO pin n output to 0.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
27
www.ti.com
Registers
3.8
GPIO Input Data Register (IN_DATAn)
The current state of the GPIO signals is read using the GPIO input data register (IN_DATAn).
• For GPIO signals configured as inputs, reading IN_DATAn returns the state of the input signal
synchronized to the GPIO peripheral clock.
• For GPIO signals configured as outputs, reading IN_DATAn returns the output value being driven by
the device.
The GPIO input data register (IN_DATA01) is shown in Figure 21, IN_DATA23 is shown in Figure 22,
IN_DATA45 is shown in Figure 23, IN_DATA6 is shown in Figure 24, and described in Table 12. See
Table 1 to determine the IN_DATAn bit associated with each GPIO bank and pin number.
Figure 21. GPIO Banks 0 and 1 Input Data Register (IN_DATA01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IN31
IN30
IN29
IN28
IN27
IN26
IN25
IN24
IN23
IN22
IN21
IN20
IN19
IN18
IN17
IN16
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IN15
IN14
IN13
IN12
IN11
IN10
IN9
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 22. GPIO Banks 2 and 3 Input Data Register (IN_DATA23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IN63
IN62
IN61
IN60
IN59
IN58
IN57
IN56
IN55
IN54
IN53
IN52
IN51
IN50
IN49
IN48
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IN47
IN46
IN45
IN44
IN43
IN42
IN41
IN40
IN39
IN38
IN37
IN36
IN35
IN34
IN33
IN32
R-0
LEGEND: R = Read only; -n = value after reset
Figure 23. GPIO Banks 4 and 5 Input Data Register (IN_DATA45)
31
30
29
28
27
26
25
24
IN95
IN94
IN93
IN92
IN91
IN90
IN89
IN88
23
22
21
20
19
18
17
16
IN87
IN86
IN85
IN84
IN83
IN82
IN81
IN80
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IN79
IN78
IN77
IN76
IN75
IN74
IN73
IN72
IN71
IN70
IN69
IN68
IN67
IN66
IN65
IN64
R-0
LEGEND: R = Read only; -n = value after reset
Figure 24. GPIO Bank 6 Input Data Register (IN_DATA6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rsvd
IN110
IN109
IN108
IN107
IN106
IN105
IN104
IN103
IN102
IN101
IN100
IN99
IN98
IN97
IN96
R-0
LEGEND: R = Read only; -n = value after reset
28
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Table 12. GPIO Input Data Register (IN_DATAn) Field Descriptions
Bit
31-16
15-0
Field
Value
INn
Description
Status of GPIO pin n. Reading the INn bit returns the state of pin n on GPIO bank 2I + 1. This bit field
returns the status of the GPIO pins on GPIO banks 1, 3, and 5.
0
GPIO pin n is logic low.
1
GPIO pin n is logic high.
INn
Status of GPIO pin n. Reading the INn bit returns the state of pin n on GPIO bank 2I. This bit field returns
the status of the GPIO pins on GPIO banks 0, 2, 4 and 6.
0
GPIO pin n is logic low.
1
GPIO pin n is logic high.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
29
www.ti.com
Registers
3.9
GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn)
The GPIO set rising edge interrupt register (SET_RIS_TRIGn) enables a rising edge on the GPIO pin to
generate a GPIO interrupt. The GPIO set rising edge interrupt register (SET_RIS_TRIG01) is shown in
Figure 25, SET_RIS_TRIG23 is shown in Figure 26, SET_RIS_TRIG45 is shown in Figure 27,
SET_RIS_TRIG6 is shown in Figure 28, and described in Table 13. See Table 1 to determine the
SET_RIS_TRIGn bit associated with each GPIO bank and pin number.
Figure 25. GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (SET_RIS_TRIG01)
31
30
29
28
27
26
25
24
SETRIS31
SETRIS30
SETRIS29
SETRIS28
SETRIS27
SETRIS26
SETRIS25
SETRIS24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
SETRIS23
SETRIS22
SETRIS21
SETRIS20
SETRIS19
SETRIS18
SETRIS17
SETRIS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
SETRIS15
SETRIS14
SETRIS13
SETRIS12
SETRIS11
SETRIS10
SETRIS9
SETRIS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETRIS7
SETRIS6
SETRIS5
SETRIS4
SETRIS3
SETRIS2
SETRIS1
SETRIS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 26. GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (SET_RIS_TRIG23)
31
30
29
28
27
26
25
24
SETRIS63
SETRIS62
SETRIS61
SETRIS60
SETRIS59
SETRIS58
SETRIS57
SETRIS56
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
SETRIS55
SETRIS54
SETRIS53
SETRIS52
SETRIS51
SETRIS50
SETRIS49
SETRIS48
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
SETRIS47
SETRIS46
SETRIS45
SETRIS44
SETRIS43
SETRIS42
SETRIS41
SETRIS40
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETRIS39
SETRIS38
SETRIS37
SETRIS36
SETRIS35
SETRIS34
SETRIS33
SETRIS32
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
30
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Figure 27. GPIO Banks 4 and 5 Set Rising Edge Interrupt Register (SET_RIS_TRIG45)
31
30
29
28
27
26
25
24
SETRIS95
SETRIS94
SETRIS93
SETRIS92
SETRIS91
SETRIS90
SETRIS89
SETRIS88
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
SETRIS87
SETRIS86
SETRIS85
SETRIS84
SETRIS83
SETRIS82
SETRIS81
SETRIS80
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
SETRIS79
SETRIS78
SETRIS77
SETRIS76
SETRIS75
SETRIS74
SETRIS73
SETRIS72
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETRIS71
SETRIS70
SETRIS69
SETRIS68
SETRIS67
SETRIS66
SETRIS65
SETRIS64
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 28. GPIO Bank 6 Set Rising Edge Interrupt Register (SET_RIS_TRIG6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
SETRIS110
SETRIS109
SETRIS108
SETRIS107
SETRIS106
SETRIS105
SETRIS104
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETRIS103
SETRIS102
SETRIS101
SETRIS100
SETRIS99
SETRIS98
SETRIS97
SETRIS96
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn) Field Descriptions
Bit
31-16
15-0
Field
Value
SETRISn
Description
Enable rising edge interrupt detection on GPIO pin n. Reading the SETRISn bit in either
SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt
generation function is enabled for pin n on GPIO bank 2I + 1. Therefore, this bit will be one in both
registers if the function is enabled, and zero in both registers if the function is disabled. This bit field
configures the GPIO pins on GPIO banks 1, 3, and 5.
0
No effect.
1
Interrupt is caused by a low-to-high transition on GPIO pin n.
SETRISn
Enable rising edge interrupt detection on GPIO pin n. Reading the SETRISn bit in either
SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt
generation function is enabled for pin n on GPIO bank 2I. Therefore, this bit will be one in both registers
if the function is enabled, and zero in both registers if the function is disabled. This bit field configures
the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
No effect.
1
Interrupt is caused by a low-to-high transition on GPIO pin n.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
31
www.ti.com
Registers
3.10 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn)
The GPIO clear rising edge interrupt register (CLR_RIS_TRIGn) disables a rising edge on the GPIO pin
from generating a GPIO interrupt. The GPIO clear rising edge interrupt register (CLR_RIS_TRIG01) is
shown in Figure 29, CLR_RIS_TRIG23 is shown in Figure 30, CLR_RIS_TRIG45 is shown in Figure 31,
CLR_RIS_TRIG6 is shown in Figure 32, and described in Table 14. See Table 1 to determine the
CLR_RIS_TRIGn bit associated with each GPIO bank and pin number.
Figure 29. GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG01)
31
30
29
28
27
26
25
24
CLRRIS31
CLRRIS30
CLRRIS29
CLRRIS28
CLRRIS27
CLRRIS26
CLRRIS25
CLRRIS24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
CLRRIS23
CLRRIS22
CLRRIS21
CLRRIS20
CLRRIS19
CLRRIS18
CLRRIS17
CLRRIS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
CLRRIS15
CLRRIS14
CLRRIS13
CLRRIS12
CLRRIS11
CLRRIS10
CLRRIS9
CLRRIS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRRIS7
CLRRIS6
CLRRIS5
CLRRIS4
CLRRIS3
CLRRIS2
CLRRIS1
CLRRIS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 30. GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG23)
31
30
29
28
27
26
25
24
CLRRIS63
CLRRIS62
CLRRIS61
CLRRIS60
CLRRIS59
CLRRIS58
CLRRIS57
CLRRIS56
R/W-10
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
CLRRIS55
CLRRIS54
CLRRIS53
CLRRIS52
CLRRIS51
CLRRIS50
CLRRIS49
CLRRIS48
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
CLRRIS47
CLRRIS46
CLRRIS45
CLRRIS44
CLRRIS43
CLRRIS42
CLRRIS41
CLRRIS40
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRRIS39
CLRRIS38
CLRRIS37
CLRRIS36
CLRRIS35
CLRRIS34
CLRRIS33
CLRRIS32
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
32
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Figure 31. GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG45)
31
30
29
28
27
26
25
24
CLRRIS95
CLRRIS94
CLRRIS93
CLRRIS92
CLRRIS91
CLRRIS90
CLRRIS89
CLRRIS88
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
CLRRIS87
CLRRIS86
CLRRIS85
CLRRIS84
CLRRIS83
CLRRIS82
CLRRIS81
CLRRIS80
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
CLRRIS79
CLRRIS78
CLRRIS77
CLRRIS76
CLRRIS75
CLRRIS74
CLRRIS73
CLRRIS72
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRRIS71
CLRRIS70
CLRRIS69
CLRRIS68
CLRRIS67
CLRRIS66
CLRRIS65
CLRRIS64
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 32. GPIO Bank 6 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
CLRRIS110
CLRRIS109
CLRRIS108
CLRRIS107
CLRRIS106
CLRRIS105
CLRRIS104
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRRIS103
CLRRIS102
CLRRIS101
CLRRIS100
CLRRIS99
CLRRIS98
CLRRIS97
CLRRIS96
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions
Bit
31-16
15-0
Field
Value
CLRRISn
Description
Disable rising edge interrupt detection on GPIO pin n. Reading the CLRRISn bit in either
SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt
generation function is enabled for pin n on GPIO bank 2I + 1. Therefore, this bit will be one in both
registers if the function is enabled, and zero in both registers if the function is disabled. This bit field
configures the GPIO pins on GPIO banks 1, 3, and 5.
0
No effect.
1
No interrupt is caused by a low-to-high transition on GPIO pin n.
CLRRISn
Disable rising edge interrupt detection on GPIO pin n. Reading the CLRRISn bit in either
SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt
generation function is enabled for pin n on GPIO bank 2I. Therefore, this bit will be one in both registers
if the function is enabled, and zero in both registers if the function is disabled. This bit field configures
the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
No effect.
1
No interrupt is caused by a low-to-high transition on GPIO pin n.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
33
www.ti.com
Registers
3.11 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn)
The GPIO set falling edge interrupt register (SET_FAL_TRIGn) enables a falling edge on the GPIO pin to
generate a GPIO interrupt. The GPIO set falling edge interrupt register (SET_FAL_TRIG01) is shown in
Figure 33, SET_FAL_TRIG23 is shown in Figure 34, SET_FAL_TRIG45 is shown in Figure 35,
SET_FAL_TRIG6 is shown in Figure 36, and described in Table 15. See Table 1 to determine the
SET_FAL_TRIGn bit associated with each GPIO bank and pin number.
Figure 33. GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (SET_FAL_TRIG01)
31
30
29
28
27
26
25
24
SETFAL31
SETFAL30
SETFAL29
SETFAL28
SETFAL27
SETFAL26
SETFAL25
SETFAL24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
SETFAL23
SETFAL22
SETFAL21
SETFAL20
SETFAL19
SETFAL18
SETFAL17
SETFAL16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
SETFAL15
SETFAL14
SETFAL13
SETFAL12
SETFAL11
SETFAL10
SETFAL9
SETFAL8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETFAL7
SETFAL6
SETFAL5
SETFAL4
SETFAL3
SETFAL2
SETFAL1
SETFAL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 34. GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (SET_FAL_TRIG23)
31
30
29
28
27
26
25
24
SETFAL63
SETFAL62
SETFAL61
SETFAL60
SETFAL59
SETFAL58
SETFAL57
SETFAL56
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
SETFAL55
SETFAL54
SETFAL53
SETFAL52
SETFAL51
SETFAL50
SETFAL49
SETFAL48
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
SETFAL47
SETFAL46
SETFAL45
SETFAL44
SETFAL43
SETFAL42
SETFAL41
SETFAL40
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETFAL39
SETFAL38
SETFAL37
SETFAL36
SETFAL35
SETFAL34
SETFAL33
SETFAL32
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
34
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Figure 35. GPIO Banks 4 and 5 Set Falling Edge Interrupt Register (SET_FAL_TRIG45)
31
30
29
28
27
26
25
24
SETFAL95
SETFAL94
SETFAL93
SETFAL92
SETFAL91
SETFAL90
SETFAL89
SETFAL88
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
SETFAL87
SETFAL86
SETFAL85
SETFAL84
SETFAL83
SETFAL82
SETFAL81
SETFAL80
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
SETFAL79
SETFAL78
SETFAL77
SETFAL76
SETFAL75
SETFAL74
SETFAL73
SETFAL72
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETFAL71
SETFAL70
SETFAL69
SETFAL68
SETFAL67
SETFAL66
SETFAL65
SETFAL64
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 36. GPIO Bank 6 Set Falling Edge Interrupt Register (SET_FAL_TRIG6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
SETFAL110
SETFAL109
SETFAL108
SETFAL107
SETFAL106
SETFAL105
SETFAL104
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
SETFAL103
SETFAL102
SETFAL101
SETFAL100
SETFAL99
SETFAL98
SETFAL97
SETFAL96
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn) Field Descriptions
Bit
31-16
15-0
Field
Value
SETFALn
Description
Enable falling edge interrupt detection on GPIO pin n. Reading the SETFALn bit in either
SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt
generation function is enabled for pin n on GPIO bank 2I + 1. Therefore, this bit will be one in both
registers if the function is enabled, and zero in both registers if the function is disabled. This bit field
configures the GPIO pins on GPIO banks 1, 3, and 5.
0
No effect.
1
Interrupt is caused by a high-to-low transition on GPIO pin n.
SETFALn
Enable falling edge interrupt detection on GPIO pin n. Reading the SETFALn bit in either
SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt
generation function is enabled for pin n on GPIO bank 2I. Therefore, this bit will be one in both registers
if the function is enabled, and zero in both registers if the function is disabled. This bit field configures
the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
No effect.
1
Interrupt is caused by a high-to-low transition on GPIO pin n.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
35
www.ti.com
Registers
3.12 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn)
The GPIO clear falling edge interrupt register (CLR_FAL_TRIGn) disables a falling edge on the GPIO pin
from generating a GPIO interrupt. The GPIO clear falling edge interrupt register (CLR_FAL_TRIG01) is
shown in Figure 37, CLR_FAL_TRIG23 is shown in Figure 38, CLR_FAL_TRIG45 is shown in Figure 39,
CLR_FAL_TRIG6 is shown in Figure 40, and described in Table 16. See Table 1 to determine the
CLR_FAL_TRIGn bit associated with each GPIO bank and pin number.
Figure 37. GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG01)
31
30
29
28
27
26
25
24
CLRFAL31
CLRFAL30
CLRFAL29
CLRFAL28
CLRFAL27
CLRFAL26
CLRFAL25
CLRFAL24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
CLRFAL23
CLRFAL22
CLRFAL21
CLRFAL20
CLRFAL19
CLRFAL18
CLRFAL17
CLRFAL16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
CLRFAL15
CLRFAL14
CLRFAL13
CLRFAL12
CLRFAL11
CLRFAL10
CLRFAL9
CLRFAL8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRFAL7
CLRFAL6
CLRFAL5
CLRFAL4
CLRFAL3
CLRFAL2
CLRFAL1
CLRFAL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 38. GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG23)
31
30
29
28
27
26
25
24
CLRFAL63
CLRFAL62
CLRFAL61
CLRFAL60
CLRFAL59
CLRFAL58
CLRFAL57
CLRFAL56
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
CLRFAL55
CLRFAL54
CLRFAL53
CLRFAL52
CLRFAL51
CLRFAL50
CLRFAL49
CLRFAL48
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
CLRFAL47
CLRFAL46
CLRFAL45
CLRFAL44
CLRFAL43
CLRFAL42
CLRFAL41
CLRFAL40
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRFAL39
CLRFAL38
CLRFAL37
CLRFAL36
CLRFAL35
CLRFAL34
CLRFAL33
CLRFAL32
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
36
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Figure 39. GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG45)
31
30
29
28
27
26
25
24
CLRFAL95
CLRFAL94
CLRFAL93
CLRFAL92
CLRFAL91
CLRFAL90
CLRFAL89
CLRFAL88
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
CLRFAL87
CLRFAL86
CLRFAL85
CLRFAL84
CLRFAL83
CLRFAL82
CLRFAL81
CLRFAL80
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
CLRFAL79
CLRFAL78
CLRFAL77
CLRFAL76
CLRFAL75
CLRFAL74
CLRFAL73
CLRFAL72
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRFAL71
CLRFAL70
CLRFAL69
CLRFAL68
CLRFAL67
CLRFAL66
CLRFAL65
CLRFAL64
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 40. GPIO Bank 6 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
CLRFAL110
CLRFAL109
CLRFAL108
CLRFAL107
CLRFAL106
CLRFAL105
CLRFAL104
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLRFAL103
CLRFAL102
CLRFAL101
CLRFAL100
CLRFAL99
CLRFAL98
CLRFAL97
CLRFAL96
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions
Bit
31-16
15-0
Field
Value
CLRFALn
Description
Disable falling edge interrupt detection on GPIO pin n. Reading the CLRFALn bit in either
SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt
generation function is enabled for pin n on GPIO bank 2I + 1. Therefore, this bit will be one in both
registers if the function is enabled, and zero in both registers if the function is disabled. This bit field
configures the GPIO pins on GPIO banks 1, 3, and 5.
0
No effect.
1
No interrupt is caused by a high-to-low transition on GPIO pin n.
CLRFALn
Disable falling edge interrupt detection on GPIO pin n. Reading the CLRFALn bit in either
SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt
generation function is enabled for pin n on GPIO bank 2I. Therefore, this bit will be one in both registers
if the function is enabled, and zero in both registers if the function is disabled. This bit field configures
the GPIO pins on GPIO banks 0, 2, 4, and 6.
0
No effect.
1
No interrupt is caused by a high-to-low transition on GPIO pin n.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
37
www.ti.com
Registers
3.13 GPIO Interrupt Status Register (INTSTATn)
The status of GPIO interrupt events can be monitored by reading the GPIO interrupt status register
(INTSTATn). In the associated bit position, pending GPIO interrupts are indicated with a logic 1 and GPIO
interrupts that are not pending are indicated with a logic 0. The GPIO interrupt status register
(INTSTAT01) is shown in Figure 41, INTSTAT23 is shown in Figure 42, INTSTAT45 is shown in
Figure 43, INTSTAT6 is shown in Figure 44, and described in Table 17. See Table 1 to determine the
INTSTATn bit associated with each GPIO bank and pin number.
Figure 41. GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01)
31
30
29
28
27
26
25
24
STAT31
STAT30
STAT29
STAT28
STAT27
STAT26
STAT25
STAT24
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
23
22
21
20
19
18
17
16
STAT23
STAT22
STAT21
STAT20
STAT19
STAT18
STAT17
STAT16
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
15
14
13
12
11
10
9
8
STAT15
STAT14
STAT13
STAT12
STAT11
STAT10
STAT9
STAT8
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
7
6
5
4
3
2
1
0
STAT7
STAT6
STATSTAT5
STAT4
STAT3
STAT2
STAT1
STAT0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset
Figure 42. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23)
31
30
29
28
27
26
25
24
STAT63
STAT62
STAT61
STAT60
STAT59
STAT58
STAT57
STAT56
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
23
22
21
20
19
18
17
16
STAT55
STAT54
STAT53
STAT52
STAT51
STAT50
STAT49
STAT48
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
15
14
13
12
11
10
9
8
STAT47
STAT46
STATSTAT45
STAT44
STAT43
STAT42
STAT41
STAT40
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
7
6
5
4
3
2
1
0
STAT39
STAT38
STAT37
STAT36
STAT35
STAT34
STAT33
STAT32
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset
38
General-Purpose Input/Output (GPIO)
SPRU988B – March 2008
Submit Documentation Feedback
www.ti.com
Registers
Figure 43. GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45)
31
30
29
28
27
26
25
24
STAT95
STAT94
STAT93
STAT92
STAT91
STAT90
STAT89
STAT88
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
23
22
21
20
19
18
17
16
STAT87
STAT86
STAT85
STAT84
STAT83
STAT82
STAT81
STAT80
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
15
14
13
12
11
10
9
8
STAT79
STAT78
STAT77
STAT76
STAT75
STAT74
STAT73
STAT72
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
7
6
5
4
3
2
1
0
STAT71
STAT70
STAT69
STAT68
STAT67
STAT66
STAT65
STAT64
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset
Figure 44. GPIO Bank 6 Interrupt Status Register (INTSTAT6)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
Reserved
STAT110
STAT109
STAT108
STAT107
STAT106
STAT105
STAT104
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
7
6
5
4
3
2
1
0
STAT103
STAT102
STAT101
STAT100
STAT99
STAT98
STAT97
STAT96
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset
Table 17. GPIO Interrupt Status Register (INTSTATn) Field Descriptions
Bit
31-16
15-0
Field
Value
STATn
Description
Interrupt status of GPIO pin n. The STATn bit is used to monitor pending GPIO interrupts on pin n of
GPIO bank 2I + 1. This bit field returns the status of GPIO pins on GPIO banks 1, 3, and 5. Write a 1 to
the STATn bit to clear the STATn bit; a write of 0 has no effect.
0
No pending interrupt on GPIO pin n.
1
Pending interrupt on GPIO pin n.
STATn
Interrupt status of GPIO pin n. The STATn bit is used to monitor pending GPIO interrupts on pin n of
GPIO bank 2I. This bit field returns the status of GPIO pins on GPIO banks 0, 2, 4, and 6. Write a 1 to the
STATn bit to clear the STATn bit; a write of 0 has no effect.
0
No pending interrupt on GPIO pin n.
1
Pending interrupt on GPIO pin n.
SPRU988B – March 2008
Submit Documentation Feedback
General-Purpose Input/Output (GPIO)
39
www.ti.com
Appendix A
Appendix A Revision History
Table A-1 lists the changes made since the previous version of this document.
Table A-1. Document Revision History
Reference
40
Additions/Modifications/Deletions
Table 13
Revised descriptions for bits 31-16 and 15-0.
Table 14
Revised descriptions for bits 31-16 and 15-0.
Table 15
Revised descriptions for bits 31-16 and 15-0.
Table 16
Revised descriptions for bits 31-16 and 15-0.
Revision History
SPRU988B – March 2008
Submit Documentation Feedback
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising