Texas Instruments | TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) (Rev. B) | User Guides | Texas Instruments TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) (Rev. B) User guides

Texas Instruments TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) (Rev. B) User guides
TMS320DM35x Digital Media
System-on-Chip (DMSoC)
Asynchronous External Memory Interface
(EMIF)
Reference Guide
Literature Number: SPRUED1B
May 2006 – Revised October 2007
2
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Contents
Preface ............................................................................................................................... 7
1
Introduction .............................................................................................................. 10
1.1
2
3
4
Purpose of the Peripheral ..................................................................................... 10
......................................................................................................... 10
1.3
Functional Block Diagram ..................................................................................... 11
Peripheral Architecture .............................................................................................. 12
2.1
Clock Control .................................................................................................... 12
2.2
EMIF Requests ................................................................................................. 12
2.3
Signal Descriptions ............................................................................................. 12
2.4
Pin Multiplexing ................................................................................................. 13
2.5
Asynchronous Controller and Interface ...................................................................... 13
2.6
Program Execution ............................................................................................. 34
2.7
Power Management ............................................................................................ 34
2.8
Emulation Considerations ..................................................................................... 35
Example Configuration............................................................................................... 36
3.1
Interfacing to Asynchronous SRAM (ASRAM) .............................................................. 36
3.2
Interfacing to NAND Flash..................................................................................... 45
Registers .................................................................................................................. 54
4.1
Asynchronous Wait Cycle Configuration Register (AWCCR) ............................................. 55
4.2
Asynchronous Configuration Registers (A1CR-A2CR) .................................................... 56
4.3
EMIF Interrupt Raw Register (EIRR) ......................................................................... 57
4.4
EMIF Interrupt Mask Register (EIMR) ....................................................................... 58
4.5
EMIF Interrupt Mask Set Register (EIMSR) ................................................................. 59
4.6
EMIF Interrupt Mask Clear Register (EIMCR) .............................................................. 60
4.7
OneNAND Flash Control Register (ONENANDCTL) ...................................................... 61
4.8
NAND Flash Control Register (NANDFCR) ................................................................. 62
4.9
NAND Flash Status Register (NANDFSR) .................................................................. 63
4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF2ECC)............................................ 64
4.11 NAND Flash 4-bit ECC LOAD Register (NAND4BITECCLOAD) ........................................ 66
4.12 NAND Flash 4-bit ECC Register 1 (NAND4BITECC1) .................................................... 67
4.13 NAND Flash 4-bit ECC Register 2 (NAND4BITECC2) .................................................... 68
4.14 NAND Flash 4-bit ECC Register 3 (NAND4BITECC3) .................................................... 69
4.15 NAND Flash 4-bit ECC Register 4 (NAND4BITECC4) .................................................... 70
4.16 NAND Flash 4-bit ECC Error Address Register 1 (NANDERRADD1) ................................... 71
4.17 NAND Flash 4-bit ECC Error Address Register 2 (NANDERRADD2) ................................... 72
4.18 NAND Flash 4-bit ECC Error Value Register 1 (NANDERRVAL1) ...................................... 73
4.19 NAND Flash 4-bit ECC Error Value Register 2 (NANDERRVAL2) ...................................... 74
1.2
Features
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Table of Contents
3
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
4
EMIF Functional Block Diagram ..........................................................................................
EMIF Asynchronous Interface ............................................................................................
EMIF to 8-bit and 16-bit Memory Interfaces ............................................................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode ...............................................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode ...............................................
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode .......................................
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ........................................
EMIF to NAND Flash Interface ...........................................................................................
ECC Value for 8-Bit NAND Flash ........................................................................................
Connecting to a 16-Bit OneNAND Flash in Asynchronous Read Mode ............................................
Connecting to a 16-Bit OneNAND Flash in Synchronous Read Mode ..............................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode with Extended Wait .......................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode with Extended Wait .......................
Connecting the EMIF to the TC55V16100FT-12 .......................................................................
Timing Waveform of an ASRAM Read .................................................................................
Timing Waveform of an ASRAM Write .................................................................................
Timing Waveform of an ASRAM Read with PCB Delays .............................................................
Timing Waveform of an ASRAM Write with PCB Delays .............................................................
Timing Waveform of a NAND Flash Read .............................................................................
Timing Waveform of a NAND Flash Command Write ................................................................
Timing Waveform of a NAND Flash Address Write ...................................................................
Timing Waveform of a NAND Flash Data Write .......................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) ........................................................
Asynchronous n Configuration Register (AnCR) .......................................................................
EMIF Interrupt Raw Register (EIRR) ....................................................................................
EMIF Interrupt Mask Register (EIMR) ...................................................................................
EMIF Interrupt Mask Set Register (EIMSR) ............................................................................
EMIF Interrupt Mask Clear Register (EIMCR) ..........................................................................
OneNAND Flash Control Register (ONENANDCTL) ..................................................................
NAND Flash Control Register (NANDFCR).............................................................................
NAND Flash Status Register (NANDFSR) ..............................................................................
NAND Flash n ECC Register (NANDFnECC) ..........................................................................
NAND Flash 4-bit ECC LOAD Register (NAND4BITECCLOAD) ....................................................
NAND Flash 4-bit ECC1 Register (NAND4BITECC1) .................................................................
NAND Flash 4-bit ECC2 Register (NAND4BITECC2) .................................................................
NAND Flash 4-bit ECC3 Register (NAND4BITECC3) .................................................................
NAND Flash 4-bit ECC Register 4 (NAND4BITECC4) ................................................................
NAND Flash 4-bit ECC Error Address Register 1 (NANDERRADD1) ..............................................
NAND Flash 4-bit ECC Error Address Register 2 (NANDERRADD2) ..............................................
NAND Flash 4-bit ECC Error Value Register 1 (NANDERRVAL1) ..................................................
NAND Flash 4-bit ECC Error Value Register 2 (NANDERRVAL2) ..................................................
List of Figures
11
14
14
18
20
22
24
26
28
31
31
32
33
36
38
39
41
42
47
49
49
50
55
56
57
58
59
60
61
62
63
64
66
67
68
69
70
71
72
73
74
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
List of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
EMIF Pins ...................................................................................................................
Behavior of EM_CE Signal Between Normal Mode and Select Strobe Mode .....................................
Description of the Asynchronous Configuration Register (AnCR) ...................................................
Description of the Asynchronous Wait Cycle Configuration Register (AWCCR) ..................................
Description of the EMIF Interrupt Mask Set Register (EIMSR) ......................................................
Description of the EMIF Interrupt Mast Clear Register (EIMCR) ....................................................
Asynchronous Read Operation in Normal Mode .......................................................................
Asynchronous Write Operation in Normal Mode .......................................................................
Asynchronous Read Operation in Select Strobe Mode ...............................................................
Asynchronous Write Operation in Select Strobe Mode ...............................................................
Description of the NAND Flash Control Register (NANDFCR) .......................................................
Configuration For NAND Flash ..........................................................................................
Interrupt Monitor and Control Bit Fields Register Name Bit Name Description ....................................
EMIF Input Timing Requirements ........................................................................................
ASRAM Output Timing Characteristics ..................................................................................
ASRAM Input Timing Requirement for a Read .........................................................................
ASRAM Input Timing Requirements for a Write .......................................................................
ASRAM Timing Requirements With PCB Delays ......................................................................
EMIF Timing Requirements for TC5516100FT-12 Example .........................................................
ASRAM Timing Requirements for TC5516100FT-12 Example ......................................................
Measured PCB Delays for TC5516100FT-12 Example ...............................................................
Configuring A2CR for TC5516100FT-12 Example .....................................................................
Recommended Margins ...................................................................................................
EMIF Read Timing Requirements........................................................................................
NAND Flash Read Timing Requirements ...............................................................................
NAND Flash Write Timing Requirements ..............................................................................
EMIF Timing Requirements for HY27UA081G1M Example ..........................................................
NAND Flash Timing Requirements for HY27UA081G1M Example .................................................
Configuring A1CR for HY27UA081G1M Example .....................................................................
Configuring NANDFCR for HY27UA081G1M Example ...............................................................
External Memory Interface (EMIF) Registers ...........................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ..................................
Asynchronous n Configuration Register (AnCR) Field Descriptions.................................................
EMIF Interrupt Raw Register (EIRR) Field Descriptions ..............................................................
EMIF Interrupt Mask Register (EIMR) Field Descriptions .............................................................
EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions ......................................................
EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions ...................................................
OneNAND Flash Control Register (ONENANDCTL) Field Descriptions ............................................
NAND Flash Control Register (NANDFCR) Field Descriptions ......................................................
NAND Flash Status Register (NANDFSR) Field Descriptions .......................................................
NAND Flash n ECC Register (NANDFnECC) Field Descriptions ....................................................
NAND Flash 4-bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ..............................
NAND Flash 4-bit ECC Register 1 (NAND4BITECC1) Field Descriptions..........................................
NAND Flash 4-bit ECC2 Register (NAND4BITECC2) Field Descriptions ..........................................
NAND Flash 4-bit ECC Register 3 (NAND4BITECC3) Field Descriptions..........................................
NAND Flash 4-bit ECC Register 4 (NAND4BITECC4) Field Descriptions..........................................
NAND Flash 4-bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ........................
NAND Flash 4-bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ........................
NAND Flash 4-bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions ............................
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
List of Tables
12
13
15
16
16
16
17
19
21
23
24
25
34
37
37
37
38
40
43
43
43
45
45
46
46
48
51
51
53
53
54
55
56
57
58
59
60
61
62
63
65
66
67
68
69
70
71
72
73
5
50
6
NAND Flash 4-bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions ............................ 74
List of Tables
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Preface
SPRUED1B – May 2006 – Revised October 2007
Read This First
This document describes the Asynchronous External Memory Interface (EMIF) in the DM35x Digital Media
System-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
TMS320DM355 Digital Media System-on-Chip (DMSoC)
Related Documentation From Texas Instruments
The following documents describe the TMS320DM355 Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet at www.ti.com. Contact your TI representative for Extranet
access.
SPRS463— TMS320DM355 Digital Media System-on-Chip (DMSoC) Data Manual This document
describes the overall TMS320DM355 system, including device architecture and features, memory
map, pin descriptions, timing characteristics and requirements, device mechanicals, etc.
SPRZ264— TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functional
specifications for the TMS320DM355 DMSoC.
SPRUFB3— TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM
Subsystem in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the components of the ARM
Subsystem, the peripherals, and the external memories.
SPRUED1— TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) Reference
Guide This document describes the asynchronous external memory interface (EMIF) in the
TMS320DM35x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to
a variety of external devices.
SPRUED2— TMS320DM35x DMSoC Universal Serial Bus (USB) Controller Reference Guide This
document describes the universal serial bus (USB) controller in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It
provides a mechanism for data transfer between USB devices and also supports host negotiation.
SPRUED3— TMS320DM35x DMSoC Audio Serial Port (ASP) Reference Guide This document
describes the operation of the audio serial port (ASP) audio interface in the TMS320DM35x Digital
Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the
AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port
receive and transmit operation, but is not intended to be used as a high-speed interface.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Preface
7
www.ti.com
TMS320DM355 Digital Media System-on-Chip (DMSoC)
SPRUED4— TMS320DM35x DMSoC Serial Peripheral Interface (SPI) Reference Guide This
document describes the serial peripheral interface (SPI) in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allows
a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI is normally used for communication between the DMSoC
and external peripherals. Typical applications include an interface to external I/O or peripheral
expansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital
converters.
SPRUED9— TMS320DM35x DMSoC Universal Asynchronous Receiver/Transmitter (UART)
Reference Guide This document describes the universal asynchronous receiver/transmitter
(UART) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The UART
peripheral performs serial-to-parallel conversion on data received from a peripheral device, and
parallel-to-serial conversion on data received from the CPU.
SPRUEE0— TMS320DM35x DMSoC Inter-Integrated Circuit (I2C) Peripheral Reference Guide This
document describes the inter-integrated circuit (I2C) peripheral in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other
devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and
from the DMSoC through the I2C peripheral. This document assumes the reader is familiar with the
I2C-bus specification.
SPRUEE2— TMS320DM35x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller
Reference Guide This document describes the multimedia card (MMC)/secure digital (SD) card
controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The MMC/SD card is
used in a number of applications to provide removable data storage. The MMC/SD controller
provides an interface to external MMC and SD cards. The communication between the MMC/SD
controller and MMC/SD card(s) is performed by the MMC/SD protocol.
SPRUEE4— TMS320DM35x DMSoC Enhanced Direct Memory Access (EDMA) Controller Reference
Guide This document describes the operation of the enhanced direct memory access (EDMA3)
controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The EDMA controller's
primary purpose is to service user-programmed data transfers between two memory-mapped slave
endpoints on the DMSoC.
SPRUEE5— TMS320DM35x DMSoC 64-bit Timer Reference Guide This document describes the
operation of the software-programmable 64-bit timers in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are used as general-purpose (GP) timers
and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode;
Timer 2 is used only as a watchdog timer. The GP timer modes can be used to generate periodic
interrupts or enhanced direct memory access (EDMA) synchronization events and Real Time
Output (RTO) events (Timer 3 only). The watchdog timer mode is used to provide a recovery
mechanism for the device in the event of a fault condition, such as a non-exiting code loop.
SPRUEE6— TMS320DM35x DMSoC General-Purpose Input/Output (GPIO) Reference Guide This
document describes the general-purpose input/output (GPIO) peripheral in the TMS320DM35x
Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose
pins that can be configured as either inputs or outputs. When configured as an input, you can
detect the state of the input by reading the state of an internal register. When configured as an
output, you can write to an internal register to control the state driven on the output pin.
SPRUEE7— TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This document
describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUEH7— TMS320DM35x DMSoC DDR2/Mobile DDR (DDR2/mDDR) Memory Controller
Reference Guide This document describes the DDR2 / mobile DDR memory controller in the
TMS320DM35x Digital Media System-on-Chip (DMSoC). The DDR2 / mDDR memory controller is
used to interface with JESD79D-2A standard compliant DDR2 SDRAM and mobile DDR devices.
8
Read This First
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
TMS320DM355 Digital Media System-on-Chip (DMSoC)
SPRUF71— TMS320DM35x DMSoC Video Processing Front End (VPFE) Users Guide This document
describes the Video Processing Front End (VPFE) in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUF72— TMS320DM35x DMSoC Video Processing Back End (VPBE) Users Guide This document
describes the Video Processing Back End (VPBE) in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUF74— TMS320DM35x DMSoC Real Time Out (RTO) Controller Reference Guide This document
describes the Real Time Out (RTO) controller in the TMS320DM35x Digital Media System-on-Chip
(DMSoC).
SPRUFC8— TMS320DM355 DMSoC Peripherals Overview Reference Guide This document provides
an overview of the peripherals in the TMS320DM355 Digital Media System-on-Chip (DMSoC).
The following documents describe TMS320DM35x Digital Media System-on-Chip (DMSoC) that are not
available by literature number. Copies of these documents are available (by title only) on the internet at
www.ti.com. Contact your TI representative for Extranet access.
—
TMS320DM35x DDR2 / mDDR Board Design Application Note This provides board design
recommendations and guidelines for DDR2 and mobile DDR.
—
TMS320DM35x USB Board Design and Layout Guidelines Application Note This provides
board design recommendations and guidelines for high speed USB.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Read This First
9
Reference Guide
SPRUED1B – May 2006 – Revised October 2007
Asynchronous External Memory Interface (EMIF)
1
Introduction
This document describes the operation of the external memory interface (EMIF) in the TMS320DM35x
Digital Media System-on-Chip (DMSoC).
1.1
Purpose of the Peripheral
The purpose of this EMIF is to provide a means to connect to a variety of external devices including:
• Asynchronous devices including Flash and SRAM
• NAND Flash
• OneNAND flash
The most common use for the EMIF is to interface with both flash devices and SRAM devices. The
Example Configuration section contains examples of operating the EMIF in this configuration.
1.2
Features
The EMIF supports the following interfaces:
• Programmable asynchronous EMIF for interfacing to SRAM, etc.
• NAND flash memories
• OneNAND flash memories
The EMIF supports the following features:
• SRAM on up to two asynchronous chip selects addressable up to 64KB each
• Supports 8-bit or 16-bit data bus widths
• Programmable asynchronous cycle timings
• Supports extended wait mode
• Supports select strobe mode
• Data bus parking
The NAND features of the EMIF are as follows:
• NAND flash on up to two asynchronous chip selects
• 8- and 16-bit data bus widths
• Programmable cycle timings
• Performs 1-bit and 4-bit ECC calculation
• NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
10
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Introduction
The OneNAND features of the EMIF are as follows:
• OneNAND flash on up to two asynchronous chip selects
• Only 16-bit data bus widths
• Supports asynchronous writes and reads
• Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads
with wrap burst modes)
• Programmable cycle timings for each chip select in asynchronous mode
1.3
Functional Block Diagram
Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external
EMIF pins. Section 2.2 contains a description of the entities internal to the device that can send requests
to the EMIF, along with their prioritization. Section 2.3 describes the EMIF's external pins and summarizes
their purpose when interfacing with SDRAM and asynchronous devices.
Figure 1. EMIF Functional Block Diagram
EMIF
EM_CE
EM_OE
ARM
WAIT
DMA
VICP
SCR
EM_WE
EM_BA[1:0]
EM_D[15:0]
EM_A[13:0]
EM_CLK
EM_ADV
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
11
www.ti.com
Peripheral Architecture
2
Peripheral Architecture
This section provides details about the architecture and operation of the EMIF.
2.1
Clock Control
The EMIF's internal clock is sourced from PLL controller 1. The EMIF's internal clock cannot be sourced
directly from an external input clock. Changing the PLL controller 1 input reference clock and/or multiplier
and divider parameters alters the operating frequency of the EMIF. See the TMS320DM355 DMSoC ARM
Subsystem Reference Guide (SPRUFB3) for more information on how to program the PLL controller.
2.2
EMIF Requests
Different sources within the device can make requests to the EMIF. These requests consist of accesses to
asynchronous memory and EMIF memory mapped registers. Because the EMIF can process only one
request at a time, a high performance switched central resource (SCR) exists to provide prioritized
requests from the different sources to the EMIF. Each requester has a programmable priority value that
may be configured in the System Control Module register MSTRPRIO or in the EDMA CC QUEPRI
register. See the TMS320DM355 DMSoC ARM Subsystem Reference Guide (SPRUFB3) for more
information on the System Control Module. See the TMS320DM35x DMSoC Enhanced Direct Memory
Access (EDMA) Controller User's Guide (SPRUEE4) for more information on the EDMA. The sources are
listed below from higheset to lowest default priority value:
1. DMA
2. ARM
3. VICP
If a request is submitted from two or more sources simultaneously, the SCR will forward the highest
priority request to the EMIF first. Upon completion of a request, the SCR again evaluates the pending
requests and forwards the highest priority pending request to the EMIF.
2.3
Signal Descriptions
Table 1 describes the function of each of the EMIF pins.
Table 1. EMIF Pins
Pins(s)
I/O
Description
EM_ A[13:0]
O
EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address
that is sent to the device.
EM_BA[1:0]
O
EMIF bank address. These pins are used in conjunction with the EM_A pins to form the address
that is sent to the device. Note that EM_A[0] does not represent the lowest AEMIF address bit. The
EMIF supports only 16-bit and 8-bit data widths. In 16-bit mode, EM_BA[1] represents the least
significant address bit (the half-word address) and EM_BA[0] represents the most significant
address bit (A[14]). In 8-bit mode, EM_BA[1:0] represent the 2 least significant address bits.
O
Active-low chip enable pin for asynchronous devices. These pins are meant to be connected to the
chip-select pin of the attached asynchronous device.
EM_D[15:0]
I/O
EMIF data bus.
EM_OE
O
Active-low pin enable for asynchronous devices. This pin provides a signal which is active-low
during the strobe period of an asynchronous read access cycle.
EM_WE
O
Active-low write enable. This pin provides a signal which is active-low during the strobe period of an
asynchronous write access cycle.
EM_WAIT
I
Wait input with programmable polarity. A connected asynchronous device can extend the strobe
period of an access cycle by asserting the WAIT input to the EMIF as described in Section 2.5.8.
To enable this functionality, the EW bit in the asynchronous configuration register (AnCR) must be
set to 1. In addition, the WP0 bit in AnCR must be configured to define the polarity of the EM_WAIT
pin.
EM_CLK
O
OneNAND clock. This pin drives CLK input on connected OneNAND devices.
EM_CE[3:2]
(1)
12
(1)
The DM35x has two chip select pins. Throughout this document the chip select pins are named EM_CE[3:2], however, in the
DM355 Data Manual and all other DM35x documents these pins are named EM_CE[1:0].
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
Table 1. EMIF Pins (continued)
2.4
Pins(s)
I/O
Description
EM_ADV
O
OneNAND address valid. This pin drives ADV# input on connected OneNAND devices.
Pin Multiplexing
The EMIF pins are multiplexed with other peripherals. Please see the device-specific data manual for
instructions on how to select the EMIF pins for proper operation.
2.5
Asynchronous Controller and Interface
The EMIF easily interfaces to a variety of asynchronous devices including Flash and ASRAM. It can be
operated in three major modes:
• Normal mode
• Select Strobe (SS) mode
• NAND Flash mode
• OneNAND Flash mode
The behavior of the EM_CE signal is the single difference between Normal mode and Select Strobe mode
(see Table 2). In Normal mode, the EM_CE signal becomes active at the beginning of the setup period
and remains active for the duration of the transfer. In Select Strobe mode, the EM_CE signal functions as
a strobe signal, active only during the strobe period of an access.
In NAND Flash mode, the EMIF hardware is able to calculate the error correction code (ECC) for each
512 byte data transfer. All NAND flash operations can be divided into single asychronous cycles and can
be performed using the EMIF's asynchronous interface. In OneNAND Flash mode, the EMIF supports
16-bit non-multiplexed OneNAND Flash on its asynchronous interface. All OneNAND Flash asynchronous
operations can be divided into single asynchronous cycles, and can be performed using the EMIF's
asynchronous interface. The EMIF also supports synchronous OneNAND Flash read operations. In
addition to the four modes of operation, the EMIF also provides configurable cycle timing parameters and
an Extended Wait mode that allows the connected device to extend the strobe period of an access cycle.
The following sections describe the features related to interfacing with external asynchronous devices.
Interfacing with OneNAND is described in Section 2.5.8.
Table 2. Behavior of EM_CE Signal Between Normal Mode and
Select Strobe Mode
2.5.1
Mode
Operation of EM_CE[3:2]
Normal
Active during the entire asynchronous access cycle
Select Strobe
Active only during the strobe period of an access cycle
Interfacing to Asynchronous Memory
Figure 2 shows the EMIF's external pins used in interfacing with an asynchronous device. Of special note
is the connection between the EMIF and the external device's address bus. The EMIF address pin
EM_A[0] always provides the least significant bit of a 32-bit address. Therefore, EM_A[0] does not
represent the lowest AEMIF address bit. The EMIF supports only 16-bit and 8-bit data widths. In 16-bit
mode, EM_BA[1] represents the least significant address bit (the half-word address) and EM_BA[0]
represents the most significant address bit (A[14]). In 8-bit mode, EM_BA[1:0] represent the 2 least
significant address bits. Figure 2 and Figure 3 show the mapping between the EMIF and the connected
device's data and address pins for various programmed data bus widths. The data bus width may be
configured in the asynchronous configuration register (AnCR).
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
13
www.ti.com
Peripheral Architecture
Figure 2. EMIF Asynchronous Interface
EMIF
EM_CE[3:2]
EM_WE
EM_OE
EM_WAIT
EM_D[15:0]
EM_A[13:0]
EM_BA[1:0]
Figure 3. EMIF to 8-bit and 16-bit Memory Interfaces
EMIF
8−bit
asynchronous
memory
EM_D[7:0]
EM_A[13:0]
EM_BA[1:0]
DQ[7:0]
A[15:2]
A[1:0]
a) EMIF to 8-bit memory interface
EMIF
16−bit
asynchronous
memory
EM_D[15:0]
EM_A[13:0]
EM_BA[1]
DQ_A[15:0]
A[14:1]
A[0]
b) EMIF to 16-bit memory interface
14
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.2
Programmable Asynchronous Parameters
The EMIF allows a high degree of programmability for shaping asynchronous accesses. The
programmable parameters are:
• Setup: The time between the beginning of a memory cycle (address valid) and the activation of the
output enable or write enable strobe
• Strobe: The time between the activation and deactivation of output enable or write enable strobe.
• Hold: The time between the deactivation of output enable or write enable strobe and the end of the
cycle, which may be indicated by an address change or the deactivation of the EM_CE signal.
Separate parameters are provided for read and write cycles. Each parameter is programmed in terms of
EMIF clock cycles.
2.5.3
Configuring the EMIF for Asynchronous Accesses
The operation of the EMIF's asynchronous interface can be configured by programming the appropriate
memory-mapped registers. The reset value and bit position for each register field can be found in
Section 4. The following tables list the programmable register fields and describe the purpose of each
field. These registers should not be programmed while an asynchronous access is in progress. The
transfer following a write to these registers will use the new configuration.
Table 3 describes the asynchronous configuration register (AnCR). There are four AnCRs. Each chip
select space has a dedicated AnCR. This allows each chip select space to be programmed independently
to interface to different asynchronous memory types.
Table 3. Description of the Asynchronous Configuration Register (AnCR)
Parameter
Description
SS
Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:
• SS = 0h selects Normal mode. EM_CE is active for duration of access.
• SS = 1h selects Select Strobe mode. EM_CE acts as a strobe.
EW
Extended Wait mode enable.
• EW = 0h disables Extended Wait mode
• EW = 1h enables Extended Wait mode
When set to 1, the EMIF enables its Extended Wait mode in which the strobe width of an access
cycle can be extended in response to the assertion of the EM_WAIT pin. The WP0 bit in the
asynchronous wait cycle configuration register (AWCCR) controls to polarity of EM_WAIT pin. See
Section 2.5.8 for more details on this mode of operation.
W_SETUP/R_SETUP
Read/Write setup widths.
These fields define the number of EMIF clock cycles of setup time for the address pins (EM_A and
EM_BA) and asynchronous chip enable (EM_CE) before the read strobe pin (READ_OE) or write
strobe pin (WRITE_WE) falls, minus 1 cycle. For writes, the W_SETUP field also defines the setup
time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to
determine the appropriate setting for this field.
W_STROBE/R_STROBE
Read/Write strobe widths.
These fields define the number of EMIF clock cycles between the falling and rising of the read strobe
pin (READ_OE) or write strobe pin (WRITE_WE), minus 1 cycle. If Extended Wait mode is enabled
by setting the EW bit in the asynchronous configuration register (AnCR), these fields must be set to
a value greater than zero. Refer to the datasheet of the external asynchronous device to determine
the appropriate setting for this field.
W_HOLD/R_HOLD
Read/Write hold widths.
These fields define the number of EMIF clock cycles of hold time for the address pins (EM_A and
EM_BA) and asynchronous chip enable (EM_CE) after the read strobe pin (READ_OE) or write
strobe pin (WRITE_WE) rises, minus 1 cycle. For writes, the W_HOLD field also defines the hold
time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to
determine the appropriate setting for this field.
TA
Minimum turnaround time.
This field defines the minimum number of EMIF clock cycles between the end of one asynchronous
access and the start of another, minus 1 cycle. This delay is not incurred when a read is followed by
a read, or a write is followed by a write to the same chip select space. The purpose of this feature is
to avoid contention on the bus. Refer to the datasheet of the external asynchronous device to
determine the appropriate setting for this field.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
15
www.ti.com
Peripheral Architecture
Table 3. Description of the Asynchronous Configuration Register (AnCR) (continued)
Parameter
Description
ASIZE
Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
• ASIZE = 0h selects an 8-bit bus
• ASIZE = 1h selects a 16-bit bus
The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in
Section 2.5.1. This field also determines the number of external accesses required to fulfill a request
generated by one of the sources mentioned in Section 2.2. For example, a request for a 32-bit word
would require four external access when ASIZE = 0h. Refer to the datasheet of the external
asynchronous device to determine the appropriate setting for this field.
Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)
Parameter
Description
WP0
WAIT Polarity.
• WP0 = 0h selects active-high polarity
• WP0 = 1h selects active-low polarity
When set to 1, the EMIF will wait if the EM_WAIT pin is high. When cleared to 0, the EMIF will wait if the
EM_WAIT pin is low. The EMIF must have the Extended Wait mode enabled for the EM_WAIT pin to affect the
width of the strobe period.
MEWC
Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF will wait for the EM_WAIT pin to be deactivated
during the strobe period of an access cycle. The maximum number of EMIF clock cycles the EMIF will wait is
determined by the following formula:
Maximum Extended Wait Cycles = (MEWC + 1) = 16
If the EM_WAIT pin is not deactivated within the time specified by this field, the EMIF resumes the access cycle,
registering whatever data is on the bus and preceding to the hold period of the access cycle. This situation is
referred to as an asynchronous timeout. An asynchronous timeout generates an interrupt if it has been enabled in
the EMIF interrupt mask set register (EIMSR). Refer to Section 2.5.1 for more information about the EMIF
interrupts.
Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)
Parameter
Description
WRMSET
Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EM_WAIT occurs.
ATMSET
Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an asynchronous timeout occurs.
Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR)
16
Parameter
Description
WRMCLR
Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WRMSET bit in the EMIF interrupt mask set register
(EIMSR).
ATMCLR
Asynchronous Timeout Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the ATMSET bit in the EMIF interrupt mask set register
(EIMSR).
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.4
Read and Write Operations in Normal Mode
Normal mode is the asynchronous interface's default mode of operation. The Normal mode is selected
when the SS bit in the asynchronous configuration register (AnCR) is cleared to 0. In this mode, the
EM_CE signal operates as a chip enable signal, active throughout the duration of the memory access.
2.5.4.1
Asynchronous Read Operations (Normal Mode)
An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read
from the attached asynchronous memory. In the event that the read request cannot be serviced by a
single access cycle to the external device, multiple access cycles will be performed by the EMIF until the
entire request is fulfilled. The details of an asynchronous read operation in Normal mode are described in
Table 7 and an example timing diagram of a basic read operation is shown in Figure 4.
Note:
During the entirety of an asynchronous read operation, the WRITE_WE pin is driven high.
Table 7. Asynchronous Read Operation in Normal Mode
Time Interval
Pin Activity in WE Strobe Mode
Turnaround
period
Once the EMIF receives a read request, the EMIF waits for the programmed number of turn-around cycles
before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA
field of the asynchronous configuration register (AnCR). There are two exceptions to this rule:
• If the current read operation was directly proceeded by another read operation to the same CS space, no
turnaround cycles are inserted.
• If the current read operation was not directly proceeded by a read operation to the same CS space and the
TA field has been cleared to 0, one turn-around cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values
in AnCR.
• The address pins EM_A and EM_BA become valid
• EM_CE falls to enable the external device (if not already low from a previous operation)
Start of strobe
period
At the beginning of the strobe period
• READ_OE falls
Start of hold
period
At the beginning of the hold period:
• READ_OE rises
• The EMIF samples the data on the EM_D bus.
End of hold
period
At the end of the hold period:
• The address pins EM_A and EM_BA become invalid
• EM_CE rises (if no more operations are required to complete the current request)
The EMIF will be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
17
www.ti.com
Peripheral Architecture
Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode
Setup
2
Strobe
3
Hold
2
Internal clock
EM_CE[3:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
18
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.4.2
Asynchronous Write Operations (Normal Mode)
An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write
to asynchronous memory. In the event that the write request cannot be serviced by a single access cycle
to the external device, multiple access cycles will be performed by the EMIF until the entire request is
fulfilled. The details of an asynchronous write operation in Normal mode are described in Table 8 and an
example timing diagram of a basic write operation is shown in Figure 5.
Note:
During the entirety of an asynchronous write operation, the EM_OE pin is driven high.
Table 8. Asynchronous Write Operation in Normal Mode
Time Interval
Pin Activity in WE Strobe Mode
Turnaround
period
Once the EMIF receives a write request, the EMIF waits for the programmed number of turn-around cycles
before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA
field of the asynchronous configuration register (AnCR). There are two exceptions to this rule:
• If the current write operation was directly proceeded by another write operation to the same CS space, no
turnaround cycles are inserted.
• If the current write operation was not directly proceeded by a write operation to the same CS space and the
TA field has been cleared to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in AnCR.
• The address pins EM_A and EM_BA and the data pins EM_D become valid.
• EM_CE falls to enable the external device (if not already low from a previous operation).
Start of strobe
period
At the beginning of the strobe period of a write operation:
• EM_WE falls
Start of hold
period
At the beginning of the hold period
• EM_WE rises
End of hold
period
At the end of the hold period:
• The address pins EM_A and EM_BA become invalid
• The data pins become invalid
• EM_CE rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the
turnaround period for the pending read or write operation.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
19
www.ti.com
Peripheral Architecture
Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode
Setup
2
Strobe
3
Hold
2
Internal clock
EM_CE[3:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
20
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.5
Read and Write Operations in Select Strobe Mode
Select Strobe mode is the EMIF's second mode of operation. The SS mode is selected when the SS bit in
the asynchronous configuration register (AnCR) is set to 1. In this mode, the EM_CE pin functions as a
strobe signal and is therefore only active during the strobe period of an access cycle.
2.5.5.1
Asynchronous Read Operations (Select Strobe Mode)
An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read
from the attached asynchronous memory. In the event that the read request cannot be serviced by a
single access cycle to the external device, multiple access cycles will be performed by the EMIF until the
entire request is fulfilled. The details of an asynchronous read operation in Select Strobe mode are
described in Table 9 and an example timing diagram of a basic read operation is shown in Figure 6.
Note:
During the entirety of an asynchronous read operation, the EM_WE pin is driven high.
Table 9. Asynchronous Read Operation in Select Strobe Mode
Time Interval
Pin Activity in Select Strobe Mode
Turnaround
period
Once the EMIF receives a read request, the EMIF waits for the programmed number of turnaround cycles before
proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA field of
the asynchronous configuration register (AnCR). There are two exceptions to this rule:
• If the current read operation was directly proceeded by another read operation to the same CS space, no
turnaround cycles are inserted.
• If the current read operation was not directly proceeded by a read operation to the same CS space and the
TA field has been cleared to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values
in AnCR.
• The address pins EM_A and EM_BA become valid.
Start of strobe
period
At the beginning of the strobe period:
• EM_CE and EM_OE fall at the start of the strobe period
Start of hold
period
At the beginning of the hold period:
• EM_CE and EM_OE rise
• The EMIF samples the data on the EM_D bus
End of hold
period
At the end of the hold period:
• The address pins EM_A and EM_BA become invalid
The EMIF may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the
turnaround period for the pending read or write operation.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
21
www.ti.com
Peripheral Architecture
Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode
Setup
2
Strobe
3
Hold
2
Internal clock
EM_CE[3:2]]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
22
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.5.2
Asynchronous Write Operations (Select Strobe Mode)
An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write
to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be serviced
by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until
the entire request is fulfilled. The details of an asynchronous write operation in Select Strobe mode are
described in Table 10 and an example timing diagram of a basic write operation is shown in Figure 7.
Note:
During the entirety of an asynchronous write operation, the EM_OE pin is driven high.
Table 10. Asynchronous Write Operation in Select Strobe Mode
Time Interval
Pin Activity in Select Strobe Mode
Turnaround
period
Once the EMIF receives a write request, the EMIF waits for the programmed number of turnaround cycles
before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA
field of the asynchronous configuration register (AnCR). There are two exceptions to this rule:
• If the current write operation was directly proceeded by another write operation to the same CS space, no
turnaround cycles are inserted.
• If the current write operation was directly proceeded by a write operation to the same CS space and the TA
field has been cleared to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in AnCR.
• The address pins EM_A and EM_BA and the data pins EM_D become valid.
Start of strobe
period
At the beginning of the strobe period:
• EM_CE and EM_WE fall
Start of hold
period
At the beginning of the hold period:
• EM_CE and EM_WE rise
End of hold
period
At the end of the hold period:
• The address pins EM_A and EM_BA become invalid
• The data pins become invalid
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the
turn-around period for the pending read or write operation.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
23
www.ti.com
Peripheral Architecture
Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode
Setup
2
Strobe
3
Hold
2
Internal clock
EM_CE[3:2]
EM_A/EM_BA
Address
EM_D
Data
EM_OE
EM_WE
2.5.6
NAND Flash Mode
NAND Flash mode is the EMIF's third mode of operation. Each chip select space may be placed in NAND
Flash mode individually by setting the appropriate CSnNAND bit in the NAND Flash control register
(NANDFCR). Table 11 displays the bit fields present in NANDFCR and briefly describes their use.
When a chip select space is configured to operate in NAND Flash mode, the EMIF hardware can calculate
the error correction code (ECC) for each 512 byte data transfer to that chip select space. The EMIF
hardware will not generate the NAND access cycle, which includes the command, address, and data
phases, necessary to complete a transfer to NAND Flash. All NAND Flash operations can be divided into
single asynchronous cycles and with the help of software, the EMIF can execute a complete NAND
access cycle.
Table 11. Description of the NAND Flash Control Register (NANDFCR)
2.5.6.1
Parameter
Description
CS3ECC
NAND Flash ECC state for chip select 3.
• Set to 1 to start an ECC calculation.
• Cleared to 0 when NAND Flash 2 ECC register (NANDF1ECC) is read.
CS2ECC
NAND Flash ECC state for chip select 2.
• Set to 1 to start an ECC calculation.
• Cleared to 0 when NAND Flash 1 ECC register (NANDF1ECC) is read.
CS3NAND
NAND Flash mode for chip select 3.
• Set to 1 to enable NAND Flash mode.
CS2NAND
NAND Flash mode for chip select 2.
• Set to 1 to enable NAND Flash mode.
Configuring for NAND Flash Mode
Similar to the asynchronous accesses previously described, the EMIF's memory-mapped registers must
be programmed appropriately to interface to a NAND Flash device. Table 12 lists the bit fields that must
be programmed when operating in NAND Flash mode and the values to set each bit. NAND Flash mode
cannot be used with Extended Wait mode.
24
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
Table 12. Configuration For NAND Flash
Register
Bit Field
Configuration Value
Asynchronous configuration
register (AnCR)
SS
0
EW
0
W_SETUP/R_SETUP
See Section 2.5.6.2 for information on how to program.
W_STROBE/R_STROBE
See Section 2.5.6.2 for information on how to program.
W_HOLD/R_HOLD
See Section 2.5.6.2 for information on how to program.
ASIZE
Programmed to equal the width of the NAND Flash device
CSnNAND
1
NAND Flash control register
(NANDFCR)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
25
www.ti.com
Peripheral Architecture
2.5.6.2
Connecting to NAND Flash
Figure 8 shows the EMIF external pins used to interface with a NAND Flash device. EMIF address lines
are used to drive the NAND Flash device's command latch enable (CLE) and address latch enable (ALE)
signals. Any EMIF address line may be used to drive the CLE and ALE signals of the NAND Flash.
However, it is recommended, especially when booting from NAND Flash, that EM_A[2:1] be used. This is
because these pins are not muxed with another peripheral and are therefore always available.
Note:
The EMIF will not control the NAND Flash device's write protect pin. The write protect pin
must be controlled outside of the EMIF.
Figure 8. EMIF to NAND Flash Interface
EMIF
CLE_EM_A[2]
ALE_EM_A[1]
EM_CE[n]
EM_WE
EM_OE
EM_D[7:0]
EM_WAIT
NAND flash
CLE
ALE
CE
WE
OE
IO[7:0]
R/B
a) Connection to 8−bit NAND device
EMIF
CLE_EM_A[2]
ALE_EM_A[1]
EM_CE[n]
EM_WE
EM_OE
EM_D[15:0]
EM_WAIT
NAND flash
CLE
ALE
CE
WE
OE
IO[15:0]
R/B
b) Connection to 16−bit NAND device
26
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.6.3
Driving CLE and ALE
As stated in Section 2.5.1, the EMIF always drives the least significant bit of a 32-bit word address on
EM_A[0]. This functionality must be considered when attempting to drive the address lines connected to
CLE and ALE to the appropriate state.
For example, if using EM_A[2] and EM_A[1] to connect to CLE and ALE, respectively, the following offsets
should be chosen:
• 00h to drive CLE and ALE low
• 10h to drive CLE high and ALE low
• 0Bh to drive CLE low and ALE high
These offsets should be added to the base address for the chip select space the NAND Flash device is
connected to. For example, if the base address of the CS space the NAND Flash device is connected to is
0200 0000h, then the above lists translates to the following memory-mapped addresses: 0200 0000h,
0200 0010h, and 0200 000Bh, respectively. Therefore, when attempting to drive CLE high and ALE low,
the memory-mapped address of 0200 0010h would be written to.
2.5.6.4
NAND Read and Program Operations
A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will not
automatically generate these three phases to complete a NAND access with one transfer request. To
complete a NAND access cycle, multiple single asynchronous access cycles (as described above) must
be completed by the EMIF. Software must be used to request the appropriate asynchronous accesses to
complete a NAND Flash access cycle. This software must be developed to the specification of the chosen
NAND Flash device.
Since NAND operations are divided into single asynchronous access cycles, the chip select signal will not
remain activated for the duration of the NAND operation. Instead, the chip select signal will deactivate
between each asynchronous access cycle. For this reason, the EMIF does not support NAND Flash
devices that require the chip select signal to remain low during the tR time for a read. See Section 2.5.6.8
for workaround.
Care must be taken when performing a NAND read or write operation via the EDMA. See Section 2.5.6.5
for more details.
Note:
2.5.6.5
The EMIF does not support NAND Flash devices that require the chip select signal to remain
low during the tR time for a read. See Section 2.5.6.8 for workaround.
NAND Data Read and Write via DMA
When performing NAND accesses, the EDMA is most efficiently used for the data phase of the access.
The command and address phases of the NAND access require only a few words of data to be
transferred and therefore do not take advantage of the EDMA's ability to transfer larger quantities of data
with a single request. In this section we will focus on using the EDMA for the data phase of a NAND
access.
There are two conditions that require care to be taken when performing NAND reads and writes via the
EDMA. These are:
• CLE_EM_A[2] and ALE_EM_A[1] are lower address lines and must be driven low
• The EMIF does not support a constant address mode, but only supports linear incrementing address
modes.
Since the EMIF does not support a constant addressing mode, when programming the EDMA, a linear
incrementing address mode must be used. When using a linear incrementing address mode, since the
CLE and ALE are driven by lower address lines, care must be taken not to increase the address into a
range the drives CLE and/or ALE high. To prevent the address from incrementing into a range that drives
CLE and/or ALE high, the EDMA ACNT, BCNT, SIDX, DIDX, and synchronization type must be
programmed appropriately. The proper EDMA configurations are described below.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
27
www.ti.com
Peripheral Architecture
EDMA setup for a NAND Flash data read:
• ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)
• BCNT = transfer size in bytes/ACNT
• SIDX (source index) = 0
• DIDX (destination index) = ACNT
• AB synchronized
EDMA setup for a NAND Flash data write:
• ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)
• BCNT = transfer size in bytes/ACNT
• SIDX (source index) = ACNT
• DIDX (destination index) = 0
• AB synchronized
2.5.6.6
ECC Generation
2.5.6.6.1
1-Bit ECC
If the CSnNAND bit in the NAND Flash control register (NANDFCR) is set to 1, the EMIF supports ECC
calculation for up to 512 bytes for the corresponding chip select. To perform the ECC calculation, the
CSnECC bit in NANDFCR must be set to 1. The ECC calculation for each chip select space is
independent of each other. It is the responsibility of the software to start the ECC calculation by writing to
the CSnECC bit prior to issuing a write or read to NAND Flash n . It is also the responsibility of the
software to read the calculated ECC from the NAND Flash n ECC register (NANDFEnCC) once the
transfer to NAND Flash has completed. If the software writes or reads more than 512 bytes, the ECC will
be incorrect. There is a NANDFnECC for each chip select space and when read, the corresponding
CSnECC bit in NANDFCR is cleared. The NANDFnECC is cleared upon writing a 1 to the CSnECC bit.
Figure 9 shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash.
For an 8-bit NAND Flash p1e through p4e are column parities and p8e through p2048 are row parities.
Similarly, the algorithm can be extended to a 16-bit NAND Flash. For a 16-bit NAND Flash p1e through
p8e are column parities and p16e through p2048 are row parities. The software must ignore the unwanted
parity bits if ECC is desired for less than 512 bytes of data. For example. p2048e and p2048o are not
required for ECC on 256 bytes of data. Similarly, p1024e, p1024o, p2048e, and p2048o are not required
for ECC on 128 bytes of data.
Figure 9. ECC Value for 8-Bit NAND Flash
28
Byte 1
Byte 2
Byte 3
Byte 4
Bit 7
Bit 7
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
Bit 4
Bit 4
Bit 4
Bit 4
Byte 1
Byte 2
Byte 3
Byte 4
Bit 7 Bit 6 Bit 5 Bit 4
Bit 7 Bit 6 Bit 5 Bit 4
Bit 7 Bit 6 Bit 5 Bit 4
Bit 7 Bit 6 Bit 5 Bit 4
p1o
p1e
p1o
p1e
p2o
p2e
p4o
Bit 3
Bit 3
Bit 3
Bit 3
Bit 0
Bit 0
Bit 0
Bit 0
p8e
p8o
p8e
p8o
Bit 3 Bit 2 Bit 1 Bit 0
Bit 3 Bit 2 Bit 1 Bit 0
Bit 3 Bit 2 Bit 1 Bit 0
Bit 3 Bit 2 Bit 1 Bit 0
p1o
p1e
p1o
p1e
p2o
p2e
p4e
p8e
p8o
p8e
p8o
Asynchronous External Memory Interface (EMIF)
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
p16e
p32e
p2048e
p16o
p16e
p2048o
p32e
p16o
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.5.6.6.2
4-Bit ECC
The EMIF supports 4-bit ECC only for 8-bit NAND Flash. In NAND mode, if the NAND Flash 4-bit ECC
start bit (4BITECC_START) in the in the NAND Flash Control register (NANDFCR) is set, the EMIF
calculates 4-bit ECC for the selected chip select. Only one chip select can be selected for the 4-bit ECC
calculation at one time. The selection of the chip select is done by programming the 4-bit ECC CS select
bit field (4BITECCSEL) in the NAND Flash Control register (NANDFCR). The calculated parity (for writes)
and syndrome (for reads) can be read from the NAND Flash 4-Bit ECC 1-4 registers
(NAND4BITECC[4:1]). The 4-bit ECC start bit (4BITECC_START) is cleared upon reading any of the
NAND Flash 4-bit ECC 1-4 registers (NAND4BITECC[4:1]). The NAND Flash 4-Bit ECC 1-4 registers are
cleared upon writing one to the 4-bit ECC start bit (4BITECC_START).
The 4-bit ECC algorithm works on a 10-bit data bus. Since the 4-bit ECC is only used for an 8-bit NAND
Flash, the EMIF zeros the upper two bits. However, the parity and the syndrome value read from the
NAND Flash 4-bit ECC 1-4 registers (NAND4BITECC[4:1]) are 10 bits wide. It is the responsibility of
software to convert 10-bit parity values to 8 bits before writing to the spare location of the NAND Flash
after a write operation. Similarly, it is the responsibility of software of the software to convert the 8-bit
parity values read from the spare location of the NAND Flash after a read operation, to 10 bits before
writing the NAND Flash 4-bit ECC Load register (NAND4BITECCLOAD).
At the end of the syndrome calculation after read, the error address and the error value can be calculated
by setting the address and error value calculation start bit (4BITECC_ADD_CALC_START) in the NAND
Flash Control register (NANDFCR). The end of address calculation is flagged by the 4-bit ECC correction
state field (ECC_STATE) in the NAND Flash Status register (NANDFSR). The number of errors can be
read from the 4-bit number of errors field (ECC_ERRNUM) in the NAND Flash Status register
(NANDFSR). The error address value can be read from the NAND Flash Error Address 1-2 registers
(NANDERRADD[2:1]). The error value can be read from the NAND Flash Error Address Value 1-2
registers (NANDERRVAL[2:1]). The address and error value start bit (4BITECC_ADD_CALC_START) is
cleared upon reading any of the NAND Flash Error Address 1-2 registers (NANDERRADD[2:1]) or the
NAND Flash Error Value 1-2 registers (NANDERRVAL[2:1]). The EMIF registers the syndrome value
internally before the error address and error value calculation. Therefore, a new read operation can be
performed simultaneously with the error address calculation.
The EMIF supports 4-bit ECC calculation up to 518 bytes. The software needs to follow the following
procedure for 4-bit ECC calculation:
For writes:
1. Set the (4BITECC_START) bit in the NAND Flash Control register (NANDFCR) to 1.
2. Write 518 bytes of data to the NAND Flash.
3. Read the parity from the NAND Flash 4-Bit ECC 1-4 registers (NAND4BITECC[4:1]).
4. Convert the 10-bit parity values to 8-bits. All 10-bit parity values can be concatenated together with
ECC value 1 (4BITECCVAL1) as lsb and ECC value 8 (4BITECCVAL8) as msb. Then the
concatenated value can be broken down into ten 8-bit values.
5. Store the parity to spare location in the NAND Flash.
For reads:
1. Set the (4BITECC_START) bit in the NAND Flash Control register (NANDFCR ) to 1.
2. Read 518 bytes of data from the NAND Flash.
3. Clear the (4BITECC_START) bit in the NAND Flash Control register (NANDFCR) by reading any of the
NAND Flash 4-Bit ECC registers.
4. Read the parity stored in the spare location in the NAND Flash.
5. Convert the 8-bit parity values to 10-bits. Reverse of the conversion that was done during writes.
6. Write the parity values in the NAND Flash 4-bit ECC Load register (NAND4BITECCLOAD). Write each
parity value one at a time starting from 4BITECCVAL1 to 4BITECCVAL8.
7. Perform a dummy read to the NAND Flash Status register (NANDFSR). This is only required to ensure
time for syndrome calculation after writing the ECC values in step 6.
8. Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers (NAND4BITECC[4:1]). A syndrome
value of 0 means no bit errors. If the syndrome is non-zero continue to step 9.
9. Set the (4BITECC_ADD_CALC_START) it in the NAND Flash Control register (NANDFCR) to 1.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
29
www.ti.com
Peripheral Architecture
10. Start another read from NAND if required (a new thread from step 1).
11. Wait for the 4-bit ECC correction state field (ECC_STATE) in the NAND Flash Status register
(NANDFSR) to be equal to 0x1, 0x2, or 0x3.
12. The number of errors can be read from the 4-bit number of errors field (ECC_ERRNUM) in the NAND
Flash Status register (NANDFSR).
13. Read the error address from the NAND Flash Error Address 1-2 registers (NANDERRADD[2:1]).
Address for the errored word is equal to (total_words_read + 7 - address_value). For 518 bytes, the
address will be equal to (525 - address_value).
14. Read the error value from the NAND Flash Error Value 1-2 registers (NANDERRVAL[2:1]). Errors can
be corrected by XORing the errored word with the error value from the NAND Flash Error Value 1-2
registers (NANDERRVAL[2:1]).
2.5.6.7
NAND Flash Status Register (NANDFSR)
The NAND Flash status register (NANDFSR) indicates the raw status of the EM_WAIT pin. The EM_WAIT
pin should be connected to the NAND Flash device's R/B signal, so that it indicates whether or not the
NAND Flash device is busy. During a read, the R/B signal will transition and remain low while the NAND
Flash retrieves the data requested. Once the R/B signal transitions high, the requested data is ready and
should be read by the EMIF. During a write/program operation, the R/B signal transitions and remains low
while the NAND Flash is programming the Flash with the data it has received from the EMIF. Once the
R/B signal transitions high, the data has been written to the Flash and the next phase of the transaction
may be performed. From this explanation, you can see that the NAND Flash status register is useful to the
software for indicating the status of the NAND Flash device and determining when to proceed to the next
phase of a NAND Flash operation.
When a rising edge occurs on the EM_WAIT pin, the EMIF sets the WR (wait rise) bit in the EMIF
interrupt raw register (EIRR). Therefore, the EMIF wait rise interrupt may be used to indicate the status of
the NAND Flash device. The WP0 bit in the asynchronous wait cycle configuration register (AWCCR)
does not affect the NAND Flash status register (NANDFSR) or the WR bit in EIRR. See Section 2.5.11.1
for more a detailed description of the wait rise interrupt.
2.5.6.8
Interfacing to a Non-CE Don't Care NAND Flash
As explained in Section 2.5.6.4, the EMIF does not support NAND Flash devices that require the chip
select signal to remain low during the tR time for a read. One way to work around this limitation is to use a
GPIO pin to drive the CE signal of the NAND Flash device. If this work around is implemented, software
will configure the selected GPIO to be low, then begin the NAND Flash operation, starting with the
command phase. Once the NAND Flash operation has completed the software will configure the selected
GPIO to be high. The pins EM_CE[3:2] are multiplexed with GPIO pins and can be used for this
workaround. Refer to the device data manual for more information on pin multiplexing.
2.5.7
OneNAND Flash Mode
The EMIF supports 16-bit non-multiplexed OneNAND Flash on its asynchronous interface. All OneNAND
Flash asynchronous operations can be divided into single asynchronous cycles, and can be performed
using the EMIF’s asynchronous interface. The EMIF also supports synchronous OneNAND Flash read
operations.
If the OneNAND Flash enable bit (CSnONENANDSEL) in the OneNAND Flash Control register
(ONENANDCTL) is set, then the EMIF operates in OneNAND Flash mode for the corresponding chip
select. The OneNAND Flash asynchronous timing values must be programmed in the corresponding
Async Config register (AnCR) for the chip select. OneNAND mode cannot be used with the Extended Wait
mode.
The EMIF by default is in OneNAND asynchronous read mode after reset. To use OneNAND synchronous
reads, the read mode bit (CSnONENANDRDMOD) in the OneNAND Flash Control register
(ONENANDCTL) must be set to 1 for the corresponding chip select. This bit must be set after putting the
OneNAND device into synchronous read mode because the OneNAND device is in asynchronous read
mode after powerup.
30
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
The read latency for synchronous reads must be programmed in the synchronous mode read latency bit
field (RD_LATENCY) in the OneNAND Flash Control register (ONENANDCTL). The same read latency is
used for all OneNAND Flashes connected to the interface. The read latency bit field (RD_LATENCY)
defaults to a value of 4 after reset. If the read latency bit field (RD_LATENCY) needs to be changed, it
must be written after programming the OneNAND device’s internal read latency because the OneNAND
device powers up with a read latency of 4.
The NAND Flash Status register (NANDFSR) indicates the raw status of the EM_WAIT pin, and can be
used to determine the status of the OneNAND Flashes connected to the respective EM_WAIT pin. The
EMIF sets the wait rise (WR) bits in the Interrupt Raw register on a rising edge of EM_WAIT pin. The
interrupts can be used to indicate that the OneNAND Flashes connected to the respective EM_WAIT pin
are ready. The MEWC bits in the Asynch Wait Cycle Config register (AWCCR) have no effect on the wait
status bit (WAITST) in the NAND Flash Status register (NANDFSR) or the wait rise (WR) bits in the
Interrupt Raw register (EIRR). The EM_WAIT pin should be connected to the OneNAND Flash device's
INT signal.
See figures below for OneNAND connection diagrams.
Figure 10. Connecting to a 16-Bit OneNAND Flash in Asynchronous Read Mode
EMIF
EM_CE
CE
EM_WE
WE
EM_OE
OE
16−bit
OneNAND
flash
ADV
EM_BA[0]
EM_A[13:0]
EM_BA[1]
EM_D[15:0]
EM_WAIT
EM_A[15]
EM_A[14:1]
A[0]
DQ[15:0]
INT
Figure 11. Connecting to a 16-Bit OneNAND Flash in Synchronous Read Mode
EM_CLK from Chip Clock Controller
EMIF
EM_CE
CE
EM_WE
WE
EM_OE
OE
EM_ADV
EM_BA[0]
EM_A[13:0]
EM_BA[1]
EM_D[15:0]
EM_WAIT
2.5.8
CLK
16−bit
OneNAND
flash
ADV
EM_A[15]
EM_A[14:1]
A[0]
DQ[15:0]
INT
Extended Wait Mode and the EM_WAIT Pin
The Extended Wait mode is a mode in which the external asynchronous device may assert control over
the length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in the
asynchronous configuration register (AnCR). When the EW bit is set, the EMIF monitors the EM_WAIT pin
to determine if the attached device wishes to extend the strobe period of the current access cycle beyond
the programmed number of clock cycles.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
31
www.ti.com
Peripheral Architecture
When the EMIF detects that the EM_WAIT pin has been asserted, it will begin inserting extra strobe
cycles into the operation until the EM_WAIT pin is deactivated by the external device. The EMIF will then
return to the last cycle of the programmed strobe period and the operation will proceed as usual from this
point. Refer to the device-specific data manual for details on the timing requirements of the EM_WAIT
signal.
The EM_WAIT pin cannot be used to extend the strobe period indefinitely. The programmable MEWC bit
in the asynchronous wait cycle configuration register (AWCCR) determines the maximum number of EMIF
clock cycles the strobe period may be extended beyond the programmed length. When the number of
cycles programmed in the MEWC bit expires, the EMIF proceeds to the hold period of the operation
regardless of the state of the EM_WAIT pin. The EMIF can also generate an interrupt upon expiration of
this counter.
For the EMIF to function properly in the Extended Wait mode, the WP0 bit in AWCCR must be
programmed to match the polarity of the attached device. When WP0 is in its reset state of 1, the EMIF
will insert wait cycles when the EM_WAIT pin is sampled high; when WP0 is cleared to 0, the EMIF will
insert wait cycles only when the EM_WAIT pin is sampled low. This programmability allows for a glueless
connection to larger variety of asynchronous devices.
Finally, a restriction is placed on the setup and strobe period timing parameters when operating in
Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than
4, and the sum of the R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize
the EM_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields
are in AnCR.
Figure 12. Timing Waveform of an Asynchronous Read Cycle in Normal Mode with Extended Wait
Strobe=2
Setup
1
1
Latched active
Latched inactive
Hold
1
1
Internal clock
EM_CE[3:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
WAIT
32
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
Figure 13. Timing Waveform of an Asynchronous Write Cycle in Normal Mode with Extended Wait
Strobe=2
Setup
1
1
Latched active
Latched inactive
1
Hold
1
Internal clock
EM_CE[2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
WAIT
2.5.9
Data Bus Parking
The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called
data bus parking. Only when the EMIF issues a read command to the external memory does it stop
driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.
2.5.10
Reset and Initialization Considerations
The EMIF and its registers will be reset when any of the following events occur:
• The RESET pin on the device is asserted
• The EMIF is placed in reset by the Power and Sleep Controller.
When a reset occurs, the EMIF will immediately abandon any access request that is in progress and reset
all registers and internal logic to their default state. Following device power up and deassertion of the
RESET pin, the internal clock to the EMIF is turned on and the EMIF memory-mapped registers are
programmed to their default values.
2.5.11
Interrupt Support
The EMIF supports a single interrupt to the CPU. Section 2.5.11.1 details the generation and internal
masking of EMIF interrupts and Section 2.5.11.2 describes how the EMIF interrupts are sent to the CPU.
2.5.11.1
Interrupt Events
There are two conditions that may cause the EMIF to generate an interrupt to the CPU. These two
conditions are:
• A rising edge on the EM_WAIT signal (wait rise interrupt)
• An asynchronous time out
The wait rise interrupt is not affected by the WP0 bit in the asynchronous wait cycle configuration register
(AWCCR). The asynchronous time out interrupt condition occurs when the attached asynchronous device
fails to deassert the EM_WAIT pin within the number of cycles defined by the MEWC bit in AWCCR.
Only when the interrupt is enabled by setting the appropriate bit (WRMSET or ATMSET) in the EMIF
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
33
www.ti.com
Peripheral Architecture
interrupt mask set register (EIMSR) to 1, will the interrupt be sent to the CPU. Once enabled, the interrupt
may be disabled by writing a 1 to the corresponding bit in the EMIF interrupt mask clear register (EIMCR).
The bit fields in both the EIMSR and EIMCR may be used to indicate whether the interrupt is enabled.
When the interrupt is enabled, the corresponding bit field in both the EIMSR and EIMCR will have a value
of 1; when the interrupt is disabled, the corresponding bit field will have a value of 0.
The EMIF interrupt raw register (EIRR) and the EMIF interrupt mask register (EIMR) indicate the status of
each interrupt. The appropriate bit (WR or AT) in EIRR is set when the interrupt condition occurs, whether
or not the interrupt has been enabled. Whereas, the appropriate bit (WRM or ATM) in EIMR is set only
when the interrupt condition occurs and the interrupt is enabled. Writing a 1 to the bit in EIRR clears the
EIRR bit as well as the corresponding bit in EIMR.
Table 13 contains a brief summary of the interrupt status and control bit fields. See Section 4 for complete
details on the register fields.
Table 13. Interrupt Monitor and Control Bit Fields Register Name Bit Name Description
Register Name
Bit Name
Description
EMIF interrupt raw register
(EIRR)
WR
This bit is always set when an rising edge on the EM_WAIT
signal occurs. Writing a 1 clears the WR bit as well as the WRM
bit in EIMR
AT
This bit is always set when an asynchronous timeout occurs.
Writing a 1 clears the AT bit as well as the ATM bit in EIMR.
WRM
This bit is only set when a rising edge on the EM_WAIT signal
occurs and the interrupt has been enabled by writing a 1 to the
WRMSET bit in EIMSR.
ATM
This bit is only set when an asynchronous timeout occurs and
the interrupt has been enabled by writing a 1 to the ATMSET bit
in EIMSR.
EMIF interrupt mask set
register (EIMSR)
WRMSET
Writing a 1 to this bit enables the wait rise interrupt.
ATMSET
Writing a 1 to this bit enables the asynchronous timeout
interrupt.
EMIF interrupt mask clear
register (EIMCR)
WRCLR
Writing a 1 to this bit disables the wait rise interrupt.
ATMCLR
Writing a 1 to this bit disables the asynchronous timeout
interrupt.
EMIF interrupt mask register
(EIMR)
2.5.11.2
Interrupt Multiplexing
The EMIF interrupt is supported by the ARM. The interrupt is not multiplexed with another interrupt and is
therefore always available.
2.6
Program Execution
Since the EMIF does not have byte enable or data mask pins, byte accesses to memory are not
supported when the data bus width is equal to 16 bits. When performing data accesses on a 16-bit bus,
this may be worked around by performing a write modify read back operation. When executing code from
the EMIF, the bus width must be configured to be an 8-bit data bus.
2.7
Power Management
Power dissipation to the EMIF may be managed by gating the input clock to the EMIF off. The input clock
is turned off outside of the EMIF through the use of the Power and Sleep Controller (PSC). When the PSC
sends a clock stop request to the EMIF, the EMIF will complete pending transfers before issuing a clock
stop acknowledge, allowing the PSC to stop the clock. See the TMS320DM42x DMSoC ARM Subsystem
Reference Guide (SPRUFB3) for more information.
34
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Peripheral Architecture
2.8
Emulation Considerations
The operation of the EMIF is not affected when a breakpoint is reached or an emulation halt occurs.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
35
www.ti.com
Example Configuration
3
Example Configuration
This section presents examples describing how to interface the EMIF to asynchronous SRAM and NAND
Flash devices.
3.1
Interfacing to Asynchronous SRAM (ASRAM)
The following example describes how to interface the EMIF to the Toshiba TC55V16100FT-12 device.
3.1.1
Connecting to ASRAM
Figure 14 shows how to connect the EMIF to the TC55V16100FT-12 device. Since the EMIF does not
include data mask or byte enable signals, the LB and UB signals of the ASRAM must be tied high.
Figure 14. Connecting the EMIF to the TC55V16100FT-12
EMIF
EM_CE
CE
EM_WE
WE
EM_OE
OE
EM_BA[0]
A[13:0]
EM_BA[1]
EM_D[15:0]
36
TC5516100FT−12
Asynchronous External Memory Interface (EMIF)
VCC
LB
VCC
UB
A[15]
A[14:1]
A[0]
DQ[15:0]
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
3.1.2
Meeting AC Timing Requirements for ASRAM
When configuring the EMIF to interface to ASRAM, you must consider the AC timing requirements of the
ASRAM as well as the AC timing requirements of the EMIF. These can be found in the data sheet for
each respective device. The read and write asynchronous cycles are programmed separately in the
asynchronous configuration register (AnCR).
For a read access, Table 14 to Table 16 list the AC timing specifications that must be considered.
Table 14. EMIF Input Timing Requirements
Parameter
Description
tSU
Data Setup time, data valid before EM_OE high
tH
Data Hold time, data valid after EM_OE high
Table 15. ASRAM Output Timing Characteristics
Parameter
Description
tACC
Address Access time
tOH
Output data Hold time for address change
tCOD
Output Disable time from chip enable
Table 16. ASRAM Input Timing Requirement for a Read
Parameter
Description
tRC
Read Cycle time
Figure 15 shows an asynchronous read access and describes how the EMIF and ASRAM AC timing
requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.
From Figure 15, the following equations may be derived. tcyc is the period at which the EMIF operates.
The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the
data sheet specifications are typically given in nano seconds. This explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
AnCR is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
R_SETUP ) R_STROBE w
ǒt ACC(m) ) t SUǓ
t cyc
R_SETUP ) R_STROBE ) R_HOLD w
R_HOLD w
*1
t RC(m)
*3
t cyc
ǒt H * t OH(m)Ǔ
*1
t cyc
The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write
cycles. This parameter protects against the situation when the output turn-off time of the memory is longer
than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same
time as the memory, causing contention on the bus. By examining Figure 15, the equation for TA can be
derived as:
TA w
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
t COD(m)
*1
t cyc
Asynchronous External Memory Interface (EMIF)
37
www.ti.com
Example Configuration
Figure 15. Timing Waveform of an ASRAM Read
Setup
Strobe
Hold
EM_CE
tWC(m)
tWR(m)
EM_A[13:0]
EM_BA[1:0]
tWP(m)
tAW(m)
EM_WE
tDS(m)
tDH(m)
EM_D[15:0]
For a write access, Table 17 lists the AC timing specifications that must be satisfied.
Table 17. ASRAM Input Timing Requirements for a Write
38
Parameter
Description
tWP
Write Pulse width
tAW
Address valid to end of Write
tDS
Data Setup time
tWR
Write Recovery time
tDH
Data Hold time
tWC
Write Cycle time
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
Figure 16 shows an asynchronous write access and describes how the EMIF and ASRAM AC timing
requirements work together to define values for W_SETUP, W_STROBE, and W_HOLD.
From Figure 16, the following equations may be derived. tcyc is the period at which the EMIF operates.
The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the
data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
AnCR is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to
W_SETUP width in EMIF clock cycles minus 1 cycle.
W_STROBE w
t WP(m)
*1
t cyc
W_SETUP ) W_STROBE w max
W_HOLD w max
ǒt t (m) , t t (m)Ǔ * 1
AW
cyc
DS
cyc
ǒt t (m) , t t (m)Ǔ * 1
WR
DH
cyc
cyc
W_SETUP ) W_STROBE ) W_HOLD w
t WC(m)
*3
t cyc
Figure 16. Timing Waveform of an ASRAM Write
Setup
Strobe
Hold
EM_CE
tRC(m)
EM_A[13:0]
EM_BA[1:0]
EM_OE
tCOD(m)
tSU
tACC(m)
tOH(m)
tH
EM_D[15:0]
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
39
www.ti.com
Example Configuration
3.1.3
Taking Into Account PCB Delays
The equations described in Section 3.1.2 are for the ideal case, when board design does not contribute
delays. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the
device driver behaves. Signals driven by the EMIF will be delayed when they reach the ASRAM and
conversely. Table 18 lists the delays shown in Figure 17 and Figure 18 due to PCB affects. The PCB
delays are board specific and must be estimated or determined though the use of IBIS modeling. The
signals denoted (ASRAM) are the signals seen at the ASRAM. For example, EM_CE represents the signal
at the EMIF and EM_CE (ASRAM) represents the delayed signal seen at the ASRAM.
Table 18. ASRAM Timing Requirements With PCB Delays
Parameter
Description
Read Access
tEM_CE
Delay on EM_CE from EMIF to ASRAM. EM_CE is driven by EMIF.
tEM_A
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
tEM_OE
Delay on EM_OE from EMIF to ASRAM. EM_OE is driven by EMIF.
tEM_D
Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM.
tEM_CE
Delay on EM_CE from EMIF to ASRAM. EM_CE is driven by EMIF.
tEM_A
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
tEM_WE
Delay on EM_WE from EMIF to ASRAM. EM_WE is driven by EMIF.
tEM_D
Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF.
Write Access
40
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
From Figure 17, the following equations may be derived. tcyc is the period at which the EMIF operates.
The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the
data sheet specifications are typically given in nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
AnCR is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
R_SETUP ) R_STROBE w
ǒtEM_A ) tACC(m) ) tSU ) tEM_DǓ
t cyc
R_SETUP ) R_STROBE ) R_HOLD w
R_HOLD w
TA w
t RC(m)
*3
t cyc
ǒt H * t EM_D * t OH(m) * t EM_AǓ
t cyc
ǒt EM_CE ) t COD(m) ) t EM_DǓ
t cyc
*1
*1
*1
Figure 17. Timing Waveform of an ASRAM Read with PCB Delays
Setup
2
1
Hold
4
Strobe
3
EM_CE
tCS
tCS
EM_CE (ASRAM)
EM_A[13:0]/
EM_BA[1:0]
tEM_A
tEM_A
tRC(m)
EM_A[13:0]/
EM_BA[1:0] (ASRAM)
EM_OE
tEM_OE
tEM_OE
EM_OE (ASRAM)
tH
tSU
tEM_D
tEM_D
EM_D[15:0]
tACC(m)
tCOD(m)
tOH(m)
EM_D[15:0]
(ASRAM)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
41
www.ti.com
Example Configuration
From Figure 18, the following equations may be derived. tcyc is the period at which the EMIF operates.
The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the
data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
AnCR is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to
W_SETUP width in EMIF clock cycles minus 1 cycle.
W_STROBE w
W_SETUP ) W_STROBE w max
W_HOLD w max
ǒ
ǒ
t WP(m)
*1
t cyc
Ǔ
ǒtEM_A ) tAW(m) * tEM_WEǓ ǒt EM_D ) t DS(m) * t EM_WEǓ
,
t cyc
t cyc
Ǔ
ǒt EM_WE ) t WR(m) * t EM_AǓ ǒtEM_WE ) t DH(m) * t EM_DǓ
t cyc
,
t cyc
W_SETUP ) W_STROBE ) W_HOLD w
*1
*1
t WC(m)
*3
t cyc
Figure 18. Timing Waveform of an ASRAM Write with PCB Delays
Setup
2
1
Hold
4
Strobe
3
EM_CE
tEM_CE
tEM_CE
EM_CE (ASRAM)
EM_A[13:0]/
EM_BA[1:0]
tEM_A
tWC(m)
tEM_A
tWR(m)
EM_A[13:0]/
EM_BA[1:0] (ASRAM)
EM_WE
tWP(m)
tEM_WE
tAW(m)
tEM_WE
EM_WE (ASRAM)
EM_D[15:0]
tDH(m)
tEM_D
tDS(m)
tEM_D
EM_D[15:0]
(ASRAM)
42
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
3.1.4
Example Using TC5516100FT-12
This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12
ASRAM with the EMIF. The following assumptions are made:
•
•
ASRAM is connected to chip select space 3 (EM_CE[3])
EMIF clock speed is 100 MHz (tcyc = 10 nS)
Table 19 lists the data sheet specifications for the EMIF and Table 20 lists the data sheet specifications
for the ASRAM.
Table 19. EMIF Timing Requirements for TC5516100FT-12 Example
Parameter
Description
Min
tSU
Data Setup time, data valid before EM_OE high
5
Max
Units
nS
tH
Data Hold time, data valid after EM_OE high
0
nS
Table 20. ASRAM Timing Requirements for TC5516100FT-12 Example
Parameter
Description
tACC
Address Access time
Min
Max
Units
12
tOH
Output data Hold time for address change
3
nS
nS
tRC
Read cycle time
12
nS
tWP
Write Pulse width
8
nS
tAW
Address valid to end of Write
9
nS
tDS
Data Setup time
7
nS
tWR
Write Recovery time
0
nS
tDH
Data Hold time
0
nS
tWC
Write Cycle time
12
nS
tCOD
Output Disable time from chip enable
7
Table 21 lists the values of the PCB board delays. The delays were estimated using the rule that there is
180 pS of delay for every 1 inch of trace.
Table 21. Measured PCB Delays for TC5516100FT-12 Example
Parameter
Description
Delay (ns)
tEM_CE
Delay on EM_CE from EMIF to ASRAM. EM_CE is driven by EMIF.
0.36
tEM_A
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
0.27
tEM_OE
Delay on EM_OE from EMIF to ASRAM. EM_OE is driven by EMIF.
0.36
tEM_D
Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM.
0.45
Read Access
Write Access
tEM_CE
Delay on EM_CE from EMIF to ASRAM. EM_CE is driven by EMIF.
0.36
tEM_A
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
0.27
tEM_WE
Delay on EM_WE from EMIF to ASRAM. EM_WE is driven by EMIF.
0.36
tEM_D
Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF.
0.45
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
43
www.ti.com
Example Configuration
Inserting these values into the equations defined above allows you to determine the values for SETUP,
STROBE, HOLD, and TA. For a read:
R_SETUP ) R_STROBE w
ǒtEM_A ) tACC(m) ) tSU ) tEM_DǓ
t cyc
R_SETUP ) R_STROBE ) R_HOLD w
R_HOLD w
ǒt H * t EM_D * t OH(m) * t EM_AǓ
t cyc
TA ³
*1 w
(0.27 ) 12 ) 5 ) 0.45)
* 1 w 0.78
10
t RC(m)
*3 w
t cyc
*1 w
ǒ12
Ǔ * 3 w * 1.8
10
(0 * 0.45 * 3 * 0.27)
* 1 w * 1.37
10
(tEM _ CE + TCOD (m ) + tEM _ D ) - 1 ³ (0.36 + 7 + 0.45 ) - 1 ³ - 0.22
10
tCYC
Therefore if R_SETUP = 0, then R_STROBE = 0, R_HOLD = 0, and TA = 0.
For a write:
W_STROBE w
W_SETUP ) W_STROBE w max
ǒ
w max
W_HOLD w max
w max
t WP(m)
*1 w
t cyc
ǒ
ǒ108 Ǔ * 1 w * 0.2
Ǔ
ǒtEM_A ) tAW(m) * tEM_WEǓ ǒt EM_D ) t DS (m) * t EM_WEǓ
,
t cyc
t cyc
*1
ǒ(0.36 )100 * 0.27) , (0.36 )100 * 0.45)Ǔ * 1 w * 0.92
Ǔ
ǒt EM_WE ) t WR(m) * t EM_AǓ ǒtEM_WE ) t DH(m) * t EM_DǓ
t cyc
,
t cyc
*1
ǒ(0.27 )109 * 0.36) , (0.45 )107 * 0.36)Ǔ * 1 w * 0.1
W_SETUP ) W_STROBE ) W_HOLD w
t WC(m)
*3 w
t cyc
ǒ12
Ǔ * 3 w * 1.8
10
Therefore, W_SETUP = 0, W_STROBE = 0, and W_HOLD = 0.
44
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
are equal to EMIF clock cycles minus 1 cycle, the A2CR should be configured as in Table 22. In this
example, the EM_WAIT signal is not implemented; therefore, the asynchronous wait cycle configuration
register (AWCCR) does not need to be programmed.
Table 22. Configuring A2CR for TC5516100FT-12 Example
3.2
Parameter
Setting
SS
Select Strobe mode.
• SS = 0. Places EMIF in Normal Mode.
EW
Extended Wait mode enable.
• EW = 0. Disabled Extended wait mode.
W_SETUP/R_SETUP
Read/Write setup widths.
• W_SETUP = 0
• R_SETUP = 0
W_STROBE/R_STROBE
Read/Write strobe widths.
• W_STROBE = 0
• R_STROBE = 0
W_HOLD/R_HOLD
Read/Write hold widths.
• W_HOLD = 0
• R_HOLD = 0
TA
Minimum turnaround time.
• TA = 0
ASIZE
Asynchronous Device Bus Width.
• ASIZE = 1, select a 16-bit data bus width
Interfacing to NAND Flash
The following example explains how to interface the EMIF to the Hynix HY27UA081G1M NAND Flash
device. Section 2.5.6.2 describes how to connect the EMIF to the HY27UA081G1M.
3.2.1
Margin Requirements
The Flash interface is typically a low-performance interface compared to synchronous memory interfaces,
high-speed asynchronous memory interfaces, and high-speed FIFO interfaces. For this reason, this
example gives little attention to minimizing the amount of margin required when programming the
asynchronous timing parameters. The approach used requires approximately 10 ns of margin on all
parameters, which is not significant for a 100-ns read or write cycle. For additional details on minimizing
the amount of margin, see the ASRAM example given in Section 3.1.
Table 23. Recommended Margins
Timing Parameter
Recommended Margin
Output Setup
10 nS
Output Hold
10 nS
Input Setup
10 nS
Input Hold
10 nS
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
45
www.ti.com
Example Configuration
3.2.2
Meeting AC Timing Requirements for NAND Flash
When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements of
the NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheet
for each respective device. The read and write asynchronous cycles are programmed separately in the
asynchronous configuration register (AnCR).
As described in Section 2.5.6, a NAND Flash access cycle is composed of a command, address, and data
phases. The EMIF will not automatically generate these three phases to complete a NAND access with
one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles
must be completed by the EMIF. The command and address phases of a NAND Flash access cycle are
asynchronous writes performed by the EMIF where as the data phase can be either an asynchronous
write or a read depending on whether the NAND Flash is being programmed or read.
Therefore, to determine the required EMIF configuration to interface to the NAND Flash for a read
operation, Table 24 and Table 25 list the AC timing parameters that must be considered.
Table 24. EMIF Read Timing Requirements
Parameter
Description
tSU
Data Setup time, data valid before EM_OE high
tH
Data Hold time, data valid after EM_OE high
Table 25. NAND Flash Read Timing Requirements
Parameter
Description
tRP
Read Pulse width
tREA
Read Enable Access time
tCEA
Chip Enable low to output valid
tCHZ
Chip Enable high to output High-Z
tRC
Read Cycle time
tRHZ
Read enable high to output High-Z
tCLR
Command Latch low to Read enable low
Figure 19 shows an asynchronous read access and describes how the EMIF and NAND Flash AC timing
requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.
46
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
From Figure 19, the following equations may be derived. tcyc is the period at which the EMIF operates.
The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the
data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
AnCR is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
R_SETUP w
R_STROBE w max
ǒ
t CLR(m)
*1
t cyc
ǒt REA(m) ) t SUǓ
t cyc
R_SETUP ) R_STROBE w
R_HOLD w
,
Ǔ
t RP(m)
*1
t cyc
ǒt CEA(m) ) t SUǓ
t cyc
*1
ǒt H * t CHZ(m)Ǔ
*1
t cyc
R_SETUP ) R_STROBE ) R_HOLD w
t RC(m)
*3
t cyc
The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write
cycles. This parameter protects against the situation when the output turn-off time of the memory is longer
than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same
time as the memory, causing contention on the bus. By examining Figure 19, the equation for TA can be
derived as:
TA w max
ǒ
Ǔ
t CHZ(m) t RHZ(m) * (R_HOLD ) 1)t cyc
,
*1
t cyc
t cyc
Figure 19. Timing Waveform of a NAND Flash Read
Setup
Hold
Strobe
EM_CE
tRC(m)
ALE_EM_A[1]
CLE_EM_A[2]
tRP(m)
tCLR(m)
EM_OE
tCHZ(m)
tREA(m)
tCEA(m)
tSU
tH
tRHZ(m)
EM_D[7:0]
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
47
www.ti.com
Example Configuration
To determine the required EMIF configuration to interface to the NAND Flash for a write operation,
Table 26 lists the NAND AC timing parameters for a command latch, address latch, and data input latch
that must be considered.
Table 26. NAND Flash Write Timing Requirements
Parameter
Description
tWP
Write Pulse width
tCLS
CLE Setup time
tALS
ALE Setup time
tCS
CS Setup time
tDS
Data Setup time
tCLH
CLE Hold time
tALH
ALE Hold time
tCH
CS Hold time
tDH
Data Hold time
tWC
Write Cycle time
Figure 20 to Figure 22 show the command latch, address latch, and data input latch of the NAND access.
From Figure 20 to Figure 22, the following equations may be derived. tcyc is the period at which the EMIF
operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles
where as the data sheet specifications are typically given is nano seconds. This is explains the presence
of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each
field in AnCR is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is
equal to W_SETUP width in EMIF clock cycles minus 1 cycle.
W_SETUP w max
ǒt t (m) , t t (m) , t t (m)Ǔ * 1
CLS
ALS
cyc
W_STROBE w
cyc
t WP(m)
*1
t cyc
W_SETUP ) W_STROBE w
W_HOLD w max
CS
cyc
t DS(m)
*1
t cyc
ǒt t (m) , t t (m) , t t (m) , t t (m)Ǔ * 1
CLH
cyc
ALH
cyc
CH
cyc
W_SETUP ) W_STROBE ) W_HOLD w
48
Asynchronous External Memory Interface (EMIF)
DH
cyc
t WC(m)
*3
t cyc
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
Figure 20. Timing Waveform of a NAND Flash Command Write
Setup
Hold
Strobe
tCH(m)
EM_CE
tWC(m)
tALH(m)
ALE_EM_A[1]
tCLH(m)
CLE_EM_A[2]
tWP(m)
tCS(m)
tALS(m)
tCLS(m)
EM_WE
tDS(m)
tDH(m)
EM_D[7:0]
Figure 21. Timing Waveform of a NAND Flash Address Write
Setup
Hold
Strobe
tCH(m)
EM_CE
tWC(m)
tALH(m)
ALE_EM_A[1]
tCLH(m)
CLE_EM_A[2]
tWP(m)
tCS(m)
tALS(m)
tCLS(m)
EM_WE
tDS(m)
tDH(m)
EM_D[7:0]
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
49
www.ti.com
Example Configuration
Figure 22. Timing Waveform of a NAND Flash Data Write
Setup
Hold
Strobe
tCH(m)
EM_CE
tWC(m)
tALH(m)
ALE_EM_A[1]
tCLH(m)
CLE_EM_A[2]
tWP(m)
tCS(m)
tALS(m)
tCLS(m)
EM_WE
tDS(m)
tDH(m)
EM_D[7:0]
50
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
3.2.3
Example Using Hynix HY27UA081G1M
This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1M
NAND Flash with the EMIF. The following assumptions are made:
•
•
NAND Flash is connected to chip select space 2 (EM_CE[2])
EMIF clock speed is 100 MHz (tcyc = 10 nS)
Table 27 lists the data sheet specifications for the EMIF and Table 28 lists the data sheet specifications
for the NAND Flash.
Table 27. EMIF Timing Requirements for HY27UA081G1M Example
Parameter
Description
Min
tSU
Data Setup time, data valid before EM_OE high
5
Max
Units
nS
tH
Data Hold time, data valid after EM_OE high
0
nS
Table 28. NAND Flash Timing Requirements for HY27UA081G1M Example
Parameter
Description
Min
tRP
Read Pulse width
60
tREA
Read Enable Access time
60
nS
tCEA
Chip Enable low to output valid
75
nS
tCHZ
Chip Enable high to output High-Z
20
nS
tRC
Read Cycle time
tRHZ
Read Enable high to output High-Z
tCLR
Command Latch low to Read enable low
10
nS
tWP
Write Pulse width
60
nS
tCLS
CLE Setup time
0
nS
tALS
ALE Setup time
0
nS
tCS
CS Setup time
0
nS
tDS
Data Setup time
20
nS
tCLH
CLE Hold time
10
nS
tALH
ALE Hold time
10
nS
tCH
CS Hold time
10
nS
tDH
Data Hold time
10
nS
tWC
Write Cycle time
80
nS
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Max
Units
nS
80
nS
30
nS
Asynchronous External Memory Interface (EMIF)
51
www.ti.com
Example Configuration
Inserting these values into the equations defined above allows you to determine the values for SETUP,
STROBE, HOLD, and TA. For a read:
R_SETUP w
R_STROBE w max
t CLR(m)
* 1 w 10 * 1 w 0
t cyc
10
ǒ Ǔ
ǒ
ǒt REA(m) ) t SUǓ
t cyc
R_SETUP ) R_STROBE w
R_HOLD w
,
Ǔ
t RP
* 1 w 65 * 1 w 5.5
t cyc
10
ǒt CEA ) t SUǓ
t cyc
ǒ Ǔ
*1w
(75 ) 5)
*1w7
10
ǒt H * t CHZ(m)Ǔ
(0 * 20)
*1w
*1w*3
t cyc
10
R_SETUP ) R_STROBE ) R_HOLD w
t RC(m)
* 3 w 80 * 3 w 5
t cyc
10
ǒ Ǔ
Therefore with a 10 nS margin added in, R_SETUP ≥ 1.0, R_STROBE ≥ 6.5, and R_HOLD ≥ 0.
After solving for R_HOLD, TA may be calculated:
TA w max
ǒ
Ǔ
t CHZ(m) t RHZ(m) * (R_HOLD ) 1)t cyc
,
* 1 w 20 * 1 w 1
t cyc
t cyc
10
ǒ Ǔ
Adding a 10 ns margin, TA ≥ 2.
For a write:
W_STROBE w
W_SETUP w max
t WP(m)
* 1 w 60 * 1 w 5
t cyc
10
ǒ Ǔ
ǒt t (m) , t t (m) , t t (m)Ǔ * 1 w ǒ100 Ǔ * 1 w * 1
CLS
ALS
cyc
CS
cyc
cyc
W_SETUP ) W_STROBE w
W_HOLD w max
t DS(m)
* 1 w 20 * 1 w 1
t cyc
10
ǒ Ǔ
ǒt t (m) , t t (m) , t t (m) , t t (m)Ǔ * 1 w ǒ1010Ǔ * 1 w 0
CLH
cyc
ALH
cyc
CH
cyc
W_SETUP ) W_STROBE ) W_HOLD w
DH
cyc
t WC(m)
* 3 w 80 * 3 w 5
t cyc
10
ǒ Ǔ
Therefore with a 10 nS margin added in, W_SETUP ≥ 0, W_STROBE ≥ 6, and W_HOLD ≥ 1.
52
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Example Configuration
Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
are equal to EMIF clock cycles minus 1 cycle, the A1CR should be configured as in Table 29. In this
example, although the EM_WAIT signal is connected to the R/B signal of the NAND Flash the Extended
Wait mode of the EMIF is not used, therefore the asynchronous wait cycle configuration register (AWCCR)
does not need to be programmed.
Table 29. Configuring A1CR for HY27UA081G1M Example
Parameter
Setting
SS
Select Strobe mode.
• SS = 0. Places EMIF in Normal Mode.
EW
Extended Wait mode enable.
• EW = 0. Disabled Extended wait mode.
W_SETUP/R_SETUP
Read/Write setup widths.
• W_SETUP = 0
• R_SETUP = 2
W_STROBE/R_STROBE
Read/Write strobe widths.
• W_STROBE = 6
• R_STROBE = 7
W_HOLD/R_HOLD
Read/Write hold widths.
• W_HOLD = 1
• R_HOLD = 0
TA
Minimum turnaround time.
• TA = 2
ASIZE
Asynchronous device bus width.
• ASIZE = 0, select an 8-bit data bus width.
Since this is a NAND Flash example, the EMIF must be configured for NAND Flash mode. This is
accomplished by configuring the NAND Flash control register (NANDFCR) as in Table 30. In NANDFCR,
chip select space 2 must be configured with NAND Flash mode enabled.
Table 30. Configuring NANDFCR for HY27UA081G1M Example
Parameter
Setting
CS3ECC
NAND Flash ECC start for chip select 3.
• CS3ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS2ECC
NAND Flash ECC start for chip select 2.
• CS2ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
CS3NAND
NAND Flash mode for chip select 3.
• CS3NAND = 0. NAND Flash mode is disabled.
CS2NAND
NAND Flash mode for chip select 2.
• CS5NAND = 1. NAND Flash mode is enabled.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
53
www.ti.com
Registers
4
Registers
The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers
(MMRs). Table 31 lists the memory-mapped registers for the EMIF. See the device-specific data manual
for the memory address of these registers. All other register offset addresses not listed in Table 31 should
be considered as reserved locations and the register contents should not be modified.
Note:
The EMIF MMRs only support word (4 byte) accesses. Performing a byte (8-bit) or halfword
(16-bit) write to a register results in unknown behavior.
Table 31. External Memory Interface (EMIF) Registers
54
Offset
Acronym
Register Description
04h
AWCCR
Asynchronous Wait Cycle Configuration Register
Section 4.1
10h
A1CR
Asynchronous 1 Configuration Register (CS2 space)
Section 4.2
14h
A2CR
Asynchronous 2 Configuration Register (CS3 space)
Section 4.2
40h
EIRR
EMIF Interrupt Raw Register
Section 4.3
44h
EIMR
EMIF Interrupt Mask Register
Section 4.4
48h
EIMSR
EMIF Interrupt Mask Set Register
Section 4.5
4Ch
EIMCR
EMIF Interrupt Mask Clear Register
Section 4.6
5Ch
ONENANDCTL
OneNAND Flash Control Register
Section 4.7
60h
NANDFCR
NAND Flash Control Register
Section 4.8
64h
NANDFSR
NAND Flash Status Register
Section 4.9
70h
NANDF1ECC
NAND Flash 1-Bit ECC Register 1 (CS2 Space)
Section 4.10
74h
NANDF2ECC
NAND Flash 1-Bit ECC Register 2 (CS3 Space)
Section 4.10
BCh
NAND4BITECCLOAD NANDFlash 4-Bit ECC Load Register
Section 4.11
C0h
NAND4BITECC1
NAND Flash 4-Bit ECC Register 1
Section 4.12
C4h
NAND4BITECC2
NAND Flash 4-Bit ECC Register 2
Section 4.13
C8h
NAND4BITECC3
NAND Flash 4-Bit ECC Register 3
Section 4.14
CCh
NAND3BITECC4
NAND Flash 4-Bit ECC Register 4
Section 4.15
D0h
NANDERRADD1
NAND Flash 4-Bit ECC Error Address Register 1
Section 4.16
D4h
NANDERRADD2
NAND Flash 4-Bit ECC Error Address Register 2
Section 4.17
D8h
NANDERRVAL1
NAND Flash 4-Bit ECC Error Value Register 1
Section 4.18
DCh
NANDERRVAL2
NAND Flash 4-Bit ECC Error Value Register 2
Section 4.19
Asynchronous External Memory Interface (EMIF)
Section
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.1
Asynchronous Wait Cycle Configuration Register (AWCCR)
The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters for
extended wait cycles. Both the polarity of the EM_WAIT pin and the maximum allowable number of
extended wait cycles can be configured. the AWCCR is shown in Figure 23 and described in Table 32.
Note:
The EW bit in the asynchronous configuration register (AnCR) must be set to allow for the
insertion of extended wait cycles.
Figure 23. Asynchronous Wait Cycle Configuration Register (AWCCR)
31
29
28
27
18
17
16
Reserved
WP0
Reserved
Reserved
R-0
R/W-1
R-0
R-0
15
8
7
0
Reserved
MEWC
R-0
R/W-80h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions
Bit
31-29
28
Field
Reserved
Value
0
WP0
Description
Reserved
WAIT polarity bit. This bit defines the polarity of the EM_WAIT pin.
0
Insert wait cycles if EM_WAIT is low.
1
Insert wait cycles if EM_WAIT is high.
27-18
Reserved
0
Reserved
17-16
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
15-8
Reserved
0
Reserved
7-0
MEWC
0-FFh
Maximum extended wait cycles. The EMIF will wait for a maximum of (MEWC + 1) = 16 clock cycles
before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
55
www.ti.com
Registers
4.2
Asynchronous Configuration Registers (A1CR-A2CR)
The asynchronous configuration register (AnCR) is used to configure the shaping of the address and
control signals during an access to asynchronous memory. It is also used to program the width of
asynchronous interface and to select from various modes of operation. This register can be written prior to
any transfer, and any asynchronous transfer following the write will use the new configuration. The AnCR
is shown in Figure 24 and described in Table 33. There are two AnCRs. Each chip select space has a
dedicated AnCR. This allows each chip select space to be programmed independently to interface to
different asynchronous memory types.
Figure 24. Asynchronous n Configuration Register (AnCR)
31
30
SS
EW(A)
29
W_SETUP
26
W_STROBE(B)
R/W-0
R/W-0
R/W-Fh
R/W-3Fh
23
20
15
13
25
19
24
17
16
W_STROBE(B)
W_HOLD
R_SETUP
R/W-3Fh
R/W-7h
R/W-Fh
12
7
(B)
R_SETUP
R_STROBE
R/W-Fh
R/W-3Fh
6
4
3
2
1
0
R_HOLD
TA
ASIZE
R/W-7h
R/W-3h
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
A
The EW bit must be cleared to 0 when operating in NAND Flash mode.
B
The W_STROBE and R_STROBE bits must not be cleared to 0 when operating in Extended Wait mode.
Table 33. Asynchronous n Configuration Register (AnCR) Field Descriptions
Bit
Field
31
SS
30
Value
Description
Select Strobe bit. This bit defines whether the asynchronous interface operates in Normal mode or
Select Strobe mode. See Section 2.5 for details on the two modes of operation.
0
Normal mode is enabled.
1
Select Strobe mode is enabled.
EW
Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 2.5.8 on
extended wait cycles for details. This bit field must be cleared to 0, if the EMIF on your device does
not have a EM_WAIT pin.
0
Extended wait cycles are disabled.
1
Extended wait cycles are enabled.
29-26
W_SETUP
0-Fh
Write setup width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.
25-20
W_STROBE
0-3Fh
Write strobe width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.
19-17
W_HOLD
0-7h
Write hold width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.
16-13
R_SETUP
0-Fh
Read setup width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.
12-7
R_STROBE
0-3Fh
Read strobe width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.
6-4
R_HOLD
0-7h
Read hold width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.
3-2
TA
0-3h
Minimum Turn-Around time. This field defines the minimum number of EMIF clock cycles between
the end of one asynchronous access and the start of another, minus 1 cycle. This delay is not
incurred by a read followed by a read or a write followed by a write to the same CS space. See
Section 2.5.3 for details.
1-0
ASIZE
0-3h
Asynchronous data bus width. This bit defines the width of the asynchronous device's data bus.
0
8-bit data bus
1h
16-bit data bus
2h-3h
56
Reserved.
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.3
EMIF Interrupt Raw Register (EIRR)
The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generated
interrupts. The bits in EIRR will be set when an interrupt condition occurs regardless of the status of the
EMIF interrupt mask set register (EIMSR) and EMIF interrupt mask clear register (EIMCR). Writing a 1 to
these bit fields will clear them as well as the corresponding bit field in the EMIF interrupt mask register
(EIMR). The EIRR is shown in Figure 25 and described in Table 34.
Figure 25. EMIF Interrupt Raw Register (EIRR)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
WR
Reserved
AT
R-0
R/W1C-0
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 34. EMIF Interrupt Raw Register (EIRR) Field Descriptions
Bit
31-3
2
Field
Reserved
Value
0
WR
1
Reserved
0
AT
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT pin has
occurred.
0
Indicates that a rising edge has not occurred on the EM_WAIT pin. Writing a 0 has no effect.
1
Indicates that a rising edge has occurred on the EM_WAIT pin. Writing a 1 will clear this bit and the
WRM bit in the EMIF interrupt mask register (EIMR).
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Asynchronous Timeout. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle the EM_WAIT pin did not go inactive within the number of cycles
defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR).
0
Indicates that an asynchronous timeout has not occurred. Writing a 0 has no effect.
1
Indicates that an asynchronous timeout has occurred. Writing a 1 will clear this bit and the ATM bit in
the EMIF interrupt mask register (EIMR).
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
57
www.ti.com
Registers
4.4
EMIF Interrupt Mask Register (EIMR)
Like the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to monitor
and clear the status of the EMIF’s hardware-generated interrupts. The main difference between the two
registers is that when the bit fields in EIMR are set, an active-high pulse will be sent to the CPU interrupt
controller. Also, the bit fields in EIMR are only set to 1 if the associated interrupt has been enabled in the
EMIF interrupt set register (EISR). The EIMR is shown in Figure 26 and described in Table 35.
Figure 26. EMIF Interrupt Mask Register (EIMR)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
WRM
Reserved
ATM
R-0
R/W1C-0
R-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 35. EMIF Interrupt Mask Register (EIMR) Field Descriptions
Bit
31-3
2
58
Field
Reserved
Value
0
WRM
1
Reserved
0
ATM
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EM_WAIT pin, provided that the WRMSET bit is set to 1 in the EMIF interrupt mask set register
(EIMSR).
0
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
1
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WR bit in
the EMIF interrupt mask register (EIMR).
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle the EM_WAIT pin did not go inactive within the number of cycles
defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR), provided
that the ATMSET bit is set to 1 in the EMIF interrupt mask set register (EIMSR).
0
Indicates that an asynchronous timeout interrupt has not been generated. Writing a 0 has no effect.
1
Indicates that an asynchronous timeout interrupt has been generated. Writing a 1 will clear this bit and
the AT bit in the EMIF interrupt mask register (EIMR).
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.5
EMIF Interrupt Mask Set Register (EIMSR)
The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the
corresponding bit in the EMIF interrupt masked register (EIMR) will be set and an interrupt will be
generated when the associated interrupt condition occurs. If a bit is cleared to 0, the the corresponding bit
in EIMR will always read 0 and no interrupts will be generated when the associated interrupt condition
occurs. Writing a 1 to the WRMSET and ATMSET bits enables each respective interrupt. The EIMSR is
shown in Figure 27 and described in Table 36.
Figure 27. EMIF Interrupt Mask Set Register (EIMSR)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
WRMSET
Reserved
ATMSET
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions
Bit
Field
31-3
Reserved
2
WRMSET
1
Reserved
0
ATMSET
Value
0
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. Writing a 1 to
this bit sets this bit, sets the WRMCLR bit in the EMIF interrupt mask clear register (EIMCR), and
enables the wait rise interrupt. To clear this bit, a 1 must be written to the WRMCLR bit in EIMCR.
0
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR bit in the
EMIF interrupt mask clear register (EIMCR).
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Asynchronous Timeout Mask Set. This bit determines whether or not the asynchronous timeout interrupt
is enabled. Writing a 1 to this bit sets this bit, sets the ATMCLR bit in the EMIF interrupt mask clear
register (EIMCR), and enables the asynchronous timeout interrupt. To clear this bit, a 1 must be written
to the ATMCLR bit in EIMCR.
0
Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 sets this bit and the ATMCLR
bit in the EMIF interrupt mask clear register (EIMCR).
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
59
www.ti.com
Registers
4.6
EMIF Interrupt Mask Clear Register (EIMCR)
The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If a bit is read as 1, the
corresponding bit in the EMIF interrupt masked register (EIMR) will be set and an interrupt will be
generated when the associated interrupt condition occurs. If a bit is read as 0, the corresponding bit in
EIMR will always read 0 and no interrupt will be generated when the corresponding interrupt condition
occurs. Writing a 1 to the ATMCLR and WRMCLR bits disables each respective interrupt. The EIMCR is
shown in Figure 28 and described in Table 37.
Figure 28. EMIF Interrupt Mask Clear Register (EIMCR)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
WRMCLR
Reserved
ATMCLR
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions
Bit
60
Field
31-3
Reserved
2
WRMCLR
1
Reserved
0
ATMCLR
Value
0
Description
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1
to this bit clears this bit, clears the WRMSET bit in the EMIF interrupt mask set register (EIMSR), and
disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET bit in EIMSR.
0
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET bit in the
EMIF interrupt mask set register (EIMSR).
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Asynchronous Timeout Mask Clear. This bit determines whether or not the asynchronous timeout
interrupt is enabled. Writing a 1 to this bit clears this bit, clears the ATMSET bit in the EMIF interrupt
mask set register (EIMSR), and disables the asynchronous timeout interrupt. To set this bit, a 1 must be
written to the ATMSET bit in EIMSR.
0
Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.
1
Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 clears this bit and the ATMSET
bit in the EMIF interrupt mask set register (EIMSR).
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.7
OneNAND Flash Control Register (ONENANDCTL)
OneNAND Flash Control Register
Figure 29. OneNAND Flash Control Register (ONENANDCTL)
31-16
_RESV
N-0x00000
LEGEND: R = Read only; -n = value after reset
15-11
10-8
7-6
5
4
3-2
1
0
_RESV
RD_LATENCY
_RESV
CS3O
NENA
NDRD
MOD
CS2O
NENA
NDRD
MOD
_RESV
CS3O
NENA
NDSE
L
CS2O
NENA
NDSE
L
N-0x00000
RW-0x4
N-0x0
RW0x0
RW0x0
N-x
RW-x
RW-x
LEGEND: R = Read only; -n = value after reset
Table 38. OneNAND Flash Control Register (ONENANDCTL) Field Descriptions
Bit
Field
Value
Description
31-11
_RESV
Reserved
10-8
RD_LATENCY
Synchronous Mode Read Latency. Set to the required read latency value. For example, if
OneNAND needs to operate with read latency of 6, program this field to 0x6.
7-6
_RESV
Reserved
5
4
3-2
1
0
CS3ONENANDR
DMOD
CS2ONENANDR
DMOD
CS3 One NAND Read Mode. Set to 1 if using OneNAND Flash synchronous read mode on CS3.
0
Async mode OneNAND operation
1
Sync mode OneNAND operation
CS2 One NAND Read Mode. Set to 1 if using OneNAND Flash synchronous read mode on CS2.
0
Async mode OneNAND operation
1
Sync mode OneNAND operation
_RESV
CS3ONENANDS
EL
CS2ONENANDS
EL
Reserved
CS3 used for ONENAND mode operation. Set to 1 if using OneNAND Flash on CS3.
0
Do not enable OneNAND mode on chip select
1
Enable OneNAND mode on chip select
CS2 used for ONENAND mode operation. Set to 1 if using OneNAND Flash on CS2.
0
Do not enable OneNAND mode on chip select
1
Enable OneNAND mode on chip select
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
61
www.ti.com
Registers
4.8
NAND Flash Control Register (NANDFCR)
The NAND Flash control register (NANDFCR) is shown in Figure 30 and described in Table 39.
Figure 30. NAND Flash Control Register (NANDFCR)
31-16
_RESV
N-0
LEGEND: R = Read only; -n = value after reset
15-14
_RESV
N-0
13
12
4BITE 4BITE
CC_A CC_S
DD_C TART
ALC_S
TART
RW-0
RW-0
11
10
9
8
7-6
5-4
3
2
1
0
_RES
V
_RES
V
CS3E
CC
CS2E
CC
_RESV
4BITECCSEL
_RES
V
_RES
V
CS3N
AND
CS2N
AND
N-0
N-0
RW-0
RW-0
N-0
RW-0
N-0
N-0
RW-0
RW-0
LEGEND: R = Read only; -n = value after reset
Table 39. NAND Flash Control Register (NANDFCR) Field Descriptions
Bit
31-14
13
Field
Value
Description
_RESV
Reserved
4BITECC_ADD_
CALC_START
NAND Flash 4-bit ECC address and error value calculation Start. Set to 1 to start 4_bit ECC error
address and erro value calculation on read syndrome. This bit is cleared when any of the NAND
Flash Error Address registers or NAND Flash Error Value registers are read.
0
1
12
4BITECC_START
Begins 4-bit ECC Address and Value Calculation
Nand Flash 4-bit ECC start for the selected chip select. Set to 1 to start 4_bit ECC calculation on
data for NAND Flash on chip select selected by bit 4BITECCSEL. This bit is cleared when ay of the
NAND Flash 4_bit ECC registers are read.
0
1
_RESV
Reserved
10
_RESV
Reserved
9
CS3ECC
NAND Flash 1_bit ECC start for chip select 3. Set to 1 to start 1_bit ECC calculation on data for
NAND Flash for this chip select. This bit is cleared when CS3 1_bit EEC register is read.
8
0
Do not start ECC calculation on chip select
1
Start 1_bit ECC calculation on chip select
CS2ECC
7-6
_RESV
5-4
4BITECCSEL
NAND Flash ECC start for chip select 2. Set to 1 to start 1_bit ECC calculation on data for NAND
Flash for this chip select. This bit is cleared when CS2 1_bit EEC register is read.
0
Do not start ECC calculation on chip select
1
Start ECC calculation on chip select
Reserved
4Bit ECC CS selection. This field selects the chip select on which the 4_bit ECC will be calculated.
0
Select the CS2 for for the 4bit ECC calculation
1
Select the CS3 for for the 4bit ECC calculation
3
_RESV
Reserved
2
_RESV
Reserved
1
CS3NAND
0
62
Begins 4-bit ECC Calculation
11
NAND Flash mode for chip select 3.
0
Do not enable NAND Flash on chip select
1
Enable NAND Flash on chip select
CS2NAND
NAND Flash mode for chip select 2.
0
Do not enable NAND Flash on chip select
1
Enable NAND Flash on chip select
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.9
NAND Flash Status Register (NANDFSR)
The NAND Flash status register (NANDFSR) is shown in Figure 31 and described in Table 40.
Figure 31. NAND Flash Status Register (NANDFSR)
31-18
17-16
_RESV
ECC_ERRNUM
N-0x0000000
R-0x0
LEGEND: R = Read only; -n = value after reset
15-12
11-8
7-4
3-0
_RESV
ECC_STATE
_RESV
WAITST
N-0x0
-0x0
N-0x0
R-0
LEGEND: R = Read only; -n = value after reset
Table 40. NAND Flash Status Register (NANDFSR) Field Descriptions
Bit
Field
31-18
_RESV
17-16
ECC_ERRNUM
15-12
_RESV
11-8
ECC_STATE
Value
Description
Reserved
Number of Errors found after the 4-Bit ECC Error Address and Error Value Calculation is done
0
1 error found
1
2 errors found
2
3 errors found
3
4 errors found
Reserved
ECC correction state while performing 4-bit ECC Address and Error Value Calculation
0h
No errors detected
1h
Errors cannot be corrected (5 or more)
2h
Error correction complete
3h
Error correction complete
4h
Reserved
5h
Calculating number of errors
6h - 7h
8h
Preparing for error search
Searching for errors
9h - Bh Reserved
Ch - Fh Calculating error value
7-4
_RESV
Reserved for furture use.
3-0
WAITST
Raw status of the EM_WAIT input pin. Note that the WP0 bit in the asynchronous wait cycle
configuration register (AWCCR) has no effect on WAITST.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
63
www.ti.com
Registers
4.10
NAND Flash n ECC Registers (NANDF1ECC-NANDF2ECC)
The NAND Flash n ECC register (NANDF1ECC-NANDF2CC) is shown in Figure 32 and described in
Table 41. For 8-bit NAND Flash, P1O, P2O, and P4O bits are column parities; P8O to P2048O bits are
row parities. For 16-bit NAND Flash, P1O, P2O, P4O, and P8O bits are column parities; P16O to P2048O
bits are row parities.
Figure 32. NAND Flash n ECC Register (NANDFnECC)
31
27
26
25
24
Reserved
28
P2048O
P1024O
P512O
P256O
R-0
R-0
R-0
R-0
R-0
23
22
21
20
19
18
17
16
P128O
P64O
P32O
P16O
P8O
P4O
P2O
P1O
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
15
11
10
9
8
Reserved
12
P2048E
P1024E
P512E
P256E
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
P128E
P64E
P32E
P16E
P8E
P4E
P2E
P1E
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
64
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
Table 41. NAND Flash n ECC Register (NANDFnECC) Field Descriptions
Bit
31-28
Field
Reserved
Value
0
Description
Reserved
27
P2048O
0-1
ECC code calculated while reading/writing NAND Flash.
26
P1024O
0-1
ECC code calculated while reading/writing NAND Flash.
25
P512O
0-1
ECC code calculated while reading/writing NAND Flash.
24
P256O
0-1
ECC code calculated while reading/writing NAND Flash.
23
P128O
0-1
ECC code calculated while reading/writing NAND Flash.
22
P64O
0-1
ECC code calculated while reading/writing NAND Flash.
21
P32O
0-1
ECC code calculated while reading/writing NAND Flash.
20
P16O
0-1
ECC code calculated while reading/writing NAND Flash.
19
P8O
0-1
ECC code calculated while reading/writing NAND Flash.
18
P4O
0-1
ECC code calculated while reading/writing NAND Flash.
17
P2O
0-1
ECC code calculated while reading/writing NAND Flash.
16
P1O
0-1
ECC code calculated while reading/writing NAND Flash.
15-12
Reserved
0
Reserved
11
P2948E
0-1
ECC code calculated while reading/writing NAND Flash.
10
P102E
0-1
ECC code calculated while reading/writing NAND Flash.
9
P512E
0-1
ECC code calculated while reading/writing NAND Flash.
8
P256E
0-1
ECC code calculated while reading/writing NAND Flash.
7
P128E
0-1
ECC code calculated while reading/writing NAND Flash.
6
P64E
0-1
ECC code calculated while reading/writing NAND Flash.
5
P32E
0-1
ECC code calculated while reading/writing NAND Flash.
4
P15E
0-1
ECC code calculated while reading/writing NAND Flash.
3
P8E
0-1
ECC code calculated while reading/writing NAND Flash.
2
P4E
0-1
ECC code calculated while reading/writing NAND Flash.
1
P2E
0-1
ECC code calculated while reading/writing NAND Flash.
0
P1E
0-1
ECC code calculated while reading/writing NAND Flash.
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
65
www.ti.com
Registers
4.11 NAND Flash 4-bit ECC LOAD Register (NAND4BITECCLOAD)
The NAND Flash 4-bit ECC load register (NAND4BITECCLOAD) is shown in Figure 33 and described in
Table 42.
Figure 33. NAND Flash 4-bit ECC LOAD Register (NAND4BITECCLOAD)
31-16
_RESV
N-0x0
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCLOAD
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 42. NAND Flash 4-bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions
Bit
31-10
9-0
66
Field
Value
Description
_RESV
Reserved
4BITECCLOAD
4-bit ECC load. This register is used to load the ECC values when performing the Syndrome
calculation during reads
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.12 NAND Flash 4-bit ECC Register 1 (NAND4BITECC1)
The NAND Flash 4-bit ECC register 1 (NAND4BITECC1) is shown in Figure 34 and described in Table 43.
Figure 34. NAND Flash 4-bit ECC1 Register (NAND4BITECC1)
31-26
25-16
_RESV
4BITECCVAL2
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCVAL1
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 43. NAND Flash 4-bit ECC Register 1 (NAND4BITECC1) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCVAL2
Calculated 4-bit ECC or Syndrom Value2
15-10
_RESV
Reserved
4BITECCVAL1
Calculated 4-bit ECC or Syndrom Value1
9-0
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
67
www.ti.com
Registers
4.13 NAND Flash 4-bit ECC Register 2 (NAND4BITECC2)
The NAND Flash 4-bit ECC register 2 (NAND4BITECC2) is shown in Figure 35 and described in Table 44.
Figure 35. NAND Flash 4-bit ECC2 Register (NAND4BITECC2)
31-26
25-16
_RESV
4BITECCVAL4
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCVAL3
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 44. NAND Flash 4-bit ECC2 Register (NAND4BITECC2) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCVAL4
Calculated 4-bit ECC or Syndrom Value4
15-10
_RESV
Reserved
4BITECCVAL3
Calculated 4-bit ECC or Syndrom Value3
9-0
68
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.14 NAND Flash 4-bit ECC Register 3 (NAND4BITECC3)
The NAND Flash 4-bit ECC register 3 (NAND4BITECC3) is shown in Figure 36 and described in Table 45.
Figure 36. NAND Flash 4-bit ECC3 Register (NAND4BITECC3)
31-26
25-16
_RESV
4BITECCVAL6
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCVAL5
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 45. NAND Flash 4-bit ECC Register 3 (NAND4BITECC3) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCVAL6
Calculated 4-bit ECC or Syndrom Value6
15-10
_RESV
Reserved
4BITECCVAL5
Calculated 4-bit ECC or Syndrom Value5
9-0
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
69
www.ti.com
Registers
4.15 NAND Flash 4-bit ECC Register 4 (NAND4BITECC4)
The NAND Flash 4-bit ECC register 4 (NAND4BITECC4) is shown in Figure 37 and described in Table 46.
Figure 37. NAND Flash 4-bit ECC Register 4 (NAND4BITECC4)
31-26
25-16
_RESV
4BITECCVAL8
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCVAL7
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 46. NAND Flash 4-bit ECC Register 4 (NAND4BITECC4) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCVAL8
Calculated 4-bit ECC or Syndrom Value8
15-10
_RESV
Reserved
4BITECCVAL7
Calculated 4-bit ECC or Syndrom Value7
9-0
70
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.16 NAND Flash 4-bit ECC Error Address Register 1 (NANDERRADD1)
The NAND Flash 4-bit ECC error register 1 (NANDERRADD1) is shown in Figure 38 and described in
Table 47.
Figure 38. NAND Flash 4-bit ECC Error Address Register 1 (NANDERRADD1)
31-26
25-16
_RESV
4BITECCERRADD2
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCERRADD1
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 47. NAND Flash 4-bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCERRAD
D2
Calculated 4-bit ECC Error Address 2
15-10
_RESV
Reserved
4BITECCERRAD
D1
Calculated 4-bit ECC Error Address 1
9-0
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
71
www.ti.com
Registers
4.17 NAND Flash 4-bit ECC Error Address Register 2 (NANDERRADD2)
The NAND Flash 4-bit ECC error register 2 (NANDERRADD2) is shown in Figure 39 and described in
Table 48.
Figure 39. NAND Flash 4-bit ECC Error Address Register 2 (NANDERRADD2)
31-26
25-16
_RESV
4BITECCERRADD4
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCERRADD3
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 48. NAND Flash 4-bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCERRAD
D4
Calculated 4-bit ECC Error Address 4
15-10
_RESV
Reserved
4BITECCERRAD
D3
Calculated 4-bit ECC Error Address 3
9-0
72
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
www.ti.com
Registers
4.18 NAND Flash 4-bit ECC Error Value Register 1 (NANDERRVAL1)
The NAND Flash 4-bit ECC error value register 1 (NANDERRVAL1) is shown in Figure 40 and described
in Table 49.
Figure 40. NAND Flash 4-bit ECC Error Value Register 1 (NANDERRVAL1)
31-26
25-16
_RESV
4BITECCERRVAL2
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCERRVAL1
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 49. NAND Flash 4-bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCERRVA
L2
Calculated 4-bit ECC Error Value 2
15-10
_RESV
Reserved
4BITECCERRVA
L1
Calculated 4-bit ECC Error Value 1
9-0
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
Asynchronous External Memory Interface (EMIF)
73
www.ti.com
Registers
4.19 NAND Flash 4-bit ECC Error Value Register 2 (NANDERRVAL2)
The NAND Flash 4-bit ECC error value register 2 (NANDERRVAL2) is shown in Figure 41 and described
in Table 50.
Figure 41. NAND Flash 4-bit ECC Error Value Register 2 (NANDERRVAL2)
31-26
25-16
_RESV
4BITECCERRVAL4
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
15-10
9-0
_RESV
4BITECCERRVAL3
N-0x0
RW-0x000
LEGEND: R = Read only; -n = value after reset
Table 50. NAND Flash 4-bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions
Bit
Field
Value
Description
31-26
_RESV
Reserved
25-16
4BITECCERRVA
L4
Calculated 4-bit ECC Error Value 4
15-10
_RESV
Reserved
4BITECCERRVA
L3
Calculated 4-bit ECC Error Value 3
9-0
74
Asynchronous External Memory Interface (EMIF)
SPRUED1B – May 2006 – Revised October 2007
Submit Documentation Feedback
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising