Texas Instruments | TMS320C645x DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2) UG | User Guides | Texas Instruments TMS320C645x DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2) UG User guides

Texas Instruments TMS320C645x DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2) UG User guides
TMS320C645x DSP
Universal Test and Operations
PHY Interface for ATM 2 (UTOPIA2)
User’s Guide
Literature Number: SPRUE48
December 2005
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Preface
Read This First
About This Manual
This document describes the universal test and operations PHY interface for
asynchronous transfer mode (ATM) 2 (UTOPIA2) in the TMS320C645x™ digital signal processors (DSPs) of the TMS320C6000™ DSP family.
Notational Conventions
This document uses the following conventions.
- Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
- Registers in this document are shown in figures and described in tables.
J
Each register figure shows a rectangle divided into fields that represent
the fields of the register. Each field is labeled with its bit name, its
beginning and ending bit numbers above, and its read/write properties
below. A legend explains the notation used for the properties.
J
Reserved bits in a register figure designate a bit that is used for future
device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) gives an introduction to the TMS320C62xt and
TMS320C67xt DSPs, development tools, and third-party support.
TMS320C6455 Technical Reference (literature number SPRU965) gives an
introduction to the TMS320C6455t DSP and discusses the application
areas that are enhanced.
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000t DSPs and includes application program examples.
SPRUE48
UTOPIA
3
Trademarks
Related Documentation From Texas Instruments / Trademarks
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studio™ application programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number
SPRU871) describes the TMS320C64x+ digital signal processor (DSP)
megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power−down controller, memory protection, bandwidth management, and the memory and
cache.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature
number SPRU190) provides a brief description of the peripherals available on the TMS320C6000 digital signal processors (DSPs).
TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234)
is a download with the latest chip support libraries.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, and VelociTI are trademarks of Texas Instruments.
PowerQUICC II is a trademark of Motorola, Inc.
4
UTOPIA
SPRUE48
Contents
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Cell Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
UTOPIA Slave as ATM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
UTOPIA Slave Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Slave-Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Slave-Transmit Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Slave-Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Slave-Receive Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
UTOPIA Events Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Multi-PHY (MPHY) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
EDMA Servicing UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
EDMA Setup for UTOPIA Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
EDMA Setup for UTOPIA Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
CPU Servicing UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
UTOPIA Clocking and Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Special Transfer Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Endian Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
UTOPIA Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13
13
15
16
17
18
18
19
10 UTOPIA Slave Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11 ATM Adaptation Layer (AAL) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 UTOPIA Control Register (UCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Clock Detect Register (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Error Interrupt Enable Register (EIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Error Interrupt Pending Register (EIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRUE48
UTOPIA
32
32
35
36
38
5
Figures
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
6
TMS320C645x DSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Transfer Formats for 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Slave Interfaced to Motorola MPC8260 PowerQUICC IIE Master
in 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Controller Slave Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Controller Slave Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA3 Setup for UTOPIA Transmitter Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA3 Setup for UTOPIA Receiver Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit UTOPIA Slave in Little-Endian Mode (BEND = 0) with RUDC/XUDC = 0 . . . . . . . . . .
8-Bit UTOPIA Slave in Big-Endian Mode (BEND = 1) with RUDC/XUDC = 0 . . . . . . . . . . .
8-Bit UTOPIA Slave in Big-Endian Mode (BEND = 1) with RUDC/XUDC = 1 . . . . . . . . . . .
8-Bit UTOPIA Slave in Little-Endian Mode (BEND = 0) with RUDC/XUDC = 7 . . . . . . . . . .
8-Bit UTOPIA Slave in Little-Endian Mode (BEND = 0) with RUDC/XUDC = 11 . . . . . . . . .
8-Bit UTOPIA Slave in Big-Endian Mode (BEND = 1) with RUDC/XUDC = 11 . . . . . . . . . .
UTOPIA Control Register (UCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Detect Register (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Enable Registers (EIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Pending Register (EIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA
10
11
12
13
15
17
21
23
27
28
28
28
29
29
32
35
36
38
SPRUE48
Tables
Tables
1
2
3
4
5
6
7
8
9
10
UTOPIA Slave Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA Synchronization Events from UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit UTOPIA Slave Modes Depending on BEND, XUDC, and RUDC Bits . . . . . . . . . . . . .
UTOPIA Pin Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Control Register (UCR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Detect Register (CDR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Enable Register (EIER) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Interrupt Pending Register (EIPR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRUE48
UTOPIA
14
20
27
30
32
32
33
35
37
38
7
This page is intentionally left blank.
8
UTOPIA
SPRUE48
UTOPIA
This document describes the universal test and operations PHY interface for
asynchronous transfer mode [ATM] 2 (UTOPIA2) in the TMS320C645x™
digital signal processors (DSPs) of the TMS320C6000™ DSP family.
1
Overview
The UTOPIA is an ATM controller (ATMC) slave device that interfaces to a
master ATM controller. The UTOPIA port conforms to the ATM Forum standard
specification af-phy-0039.000. Specifically, this interface supports the UTOPIA
Level 2 interface that allows 8-bit slave operation up to 50 MHz for both
transmit and receive operations.
The UTOPIA slave interface relies on the master ATM controller to provide the
necessary control signals such as the clock, enable and address values. Only
cell-level handshaking is supported.
The enhanced DMA (EDMA) controller can service the UTOPIA. The ATM
Adaptation Layer (AAL) commonly called as Segmentation and Reassembly
(SAR) functions should be performed in software.
All references to the term slave devices are analogous to multi-PHYs (MPHYs)
as referenced in the ATM Forum specification. For multi-PHY systems,
reference ATM Forum standard specification af-phy-0039.000. For
single-PHY (single device) systems, reference ATM Forum standard
specification af-phy-0017.000.
Figure 1 shows the UTOPIA interface on some C645x™ DSPs.
The UTOPIA slave consists of the transmit interface and the receive interface
as shown in Figure 2. The interface signals are described in section 3.1. The
UTOPIA sends synchronization events to the EDMA controller via the UXEVT and
UREVT signals. An interrupt signal (UINT) is also generated to the CPU to
communicate error conditions (see section 7).
SPRUE48
UTOPIA
9
Overview
Figure 1.
TMS320C645x DSP Block Diagram
L1P
cache/SRAM
EMIFA
Switched central resource
DDR2 memory
controller
PLL2
UTOPIA
L2 memory
L2 memory
controller
L1 program memory controller
Cache control
Bandwidth management
Memory protection
Cache
control
Bandwidth
management
Memory
protection
C64x+ CPU
Instruction fetch
SPLOOP buffer
16/32−bit instruction dispatch
Instruction decode
IDMA
Data path A
External
memory
controller
L1
Configuration
registers
Other
peripherals
Master
DMA
Boot
configuration
S1
M1
Data path B
D1
Register file A
L1 data memory controller
Slave
DMA
EDMA
controller
Advanced
event
triggering
(AET)
Cache control
Memory protection
Bandwidth management
D2
M2
S2
L2
Register file B
Interrupt
and exception
controller
Power control
PLL2
L1D
cache/SRAM
Note:
10
Refer to your device-specific datasheet for your peripheral set.
UTOPIA
SPRUE48
Overview
Figure 2.
UTOPIA Block Diagram
UTOPIA
UXCLK
UXADDR[4−0]
UXCLAV
UXENB
Transmit
slave
Slave transmit
queue (UXQ)
EDMA
controller
Receive
slave
Slave receive
queue (URQ)
EDMA
controller
UXSOC
UXDATA[7−0]
URCLK
URADDR[4−0]
URCLAV
URENB
URSOC
URDATA[7−0]
UXEVT
SPRUE48
Synchronization
UREVT
Events to EDMA
UINT
Interrupt to CPU
UTOPIA
11
Cell Transfer Format
2
Cell Transfer Format
The ATM Forum specification for UTOPIA Level 2 specifies the order in which
header and payload information is sent across the ATM-PHY interface. The
header information is sent first, followed by the 48-byte payload. A standard
ATM cell is 53 bytes (5-byte header + 48-byte payload) as shown in Figure 3.
The UTOPIA also supports a nonstandard ATM cell of size 54 to 64 bytes
(R/XUDC = 1 to 11 + 5-byte header + 48-byte payload) as shown in Figure 3.
The UTOPIA transmit queue and receive queue each accommodate two cells.
The number of cells each queue accommodates is not dependent upon cell size.
For the C6000™ DSP, each ATM cell must be aligned on a word-boundary.
Therefore, each ATM cell (53 bytes) in the DSP memory (internal or external)
and in the UTOPIA transmit/receive queues is padded with dummy bytes as
necessary before the ATM header. The standard 56-byte cell-packet consists
of the 53-byte ATM cell, plus 3 bytes of dummy data before the ATM header.
This 56-byte packet is referred to as a cell packet. See also section 8.
Figure 3.
Cell Transfer Formats for 8-Bit Mode
Standard
Bits 7
12
UTOPIA
Nonstandard
0
Bits 7
0
Header 1
Time 0
UDB 1
Time 0
Header 2
|
UDB 2
|
Header 3
|
::
|
Header 4
|
UDB 11
|
UDF
|
Header 1
|
Payload 1
|
Header 2
|
Payload 2
|
Header 3
|
::
|
Header 4
|
::
V
UDF
|
Payload 48
Time N
Payload 1
|
Payload 2
|
::
|
::
V
Payload 48
Time N
SPRUE48
UTOPIA Slave as ATM Controller
3
UTOPIA Slave as ATM Controller
The UTOPIA interface can be used as an ATM controller slave in either a
single-PHY or multi-PHY (MPHY) configuration. As a slave, the clock,
address, and enable signals of the transmit and receive interfaces are driven
by the master. An example configuration is shown in Figure 4.
UTOPIA Slave Interfaced to Motorola MPC8260 PowerQUICC II™ Master
in 8-Bit Mode
Figure 4.
FCC1_TXCLK
FCC1_UTM_TXADDR[4:0]
URCLAV
FCC1_UTM_TXENB
URENB
FCC1_UT8_TXD[7:0]
FCC1_RXCLK
FCC1_UTM_RXADDR[4:0]
URSOC
URDATA[7:0]
UXCLK
UXADDR[4:0]
FCC1_UTM_RCCLAV
UXCLAV
FCC1_UTM_RXENB
UXENB
FCC1_UT_RXSOC
UXSOC
FCC1_UT8_RXD[7:0]
3.1
URADDR[4:0]
FCC1_UTM_TXCLAV
FCC1_UT_TXSOC
MPC8260
(FCC1)
master ATM
controller
URCLK
C645x
slave ATM
controller/
PHY
UXDATA[7:0]
UTOPIA Slave Pins
As a slave device in an ATM system, the UTOPIA performs all ATM cell
transfers when directed by the master. The clock, address, and enable signals
are inputs. The master can configure the slave’s address in the UTOPIA
control register (UCR) through the HPI/PCI interface. Table 1 shows the pins
and their direction relevant to the UTOPIA slave interface.
The slave responds when it detects its assigned address on the address bus
by asserting its UXCLAV or URCLAV signal, if a cell is available for transmit
or receive, respectively. If the slave does not have a cell to transmit or cell
space to receive, it does not assert the relevant CLAV signal, but the master
continues to poll the remaining slaves/PHYs in the system on the address bus.
SPRUE48
UTOPIA
13
UTOPIA Slave as ATM Controller
Table 1.
UTOPIA Slave Pin Descriptions
Pin
Direction
Description
UTOPIA Transmit Interface (Slave mode)
UXCLK
In
UTOPIA Transmit Clock. An input driven by the master in the system.
Transmit data and transmit control signals are synchronous to this clock.
UXADDR[4−0]
In
5-bit address input driven by the master ATM Controller to identify each of the
slave devices (up to 31) in the ATM system.
UXCLAV
Out
Transmit Cell Available status output signal of the slave. For cell-level
handshake, the following is true:
0: Indicates that the slave does not have a complete cell available for
transmit.
1: Indicates that the slave has a complete cell available to transmit.
UXENB
In
UTOPIA Transmit Interface Enable input signal. Asserted active low by the
master to indicate that the slave should put first byte of valid data and assert
SOC signal in the next clock cycle.
UXSOC
Out
Transmit Start-Of-Cell signal (active high) output by the slave on rising edge
of UXCLK to indicate that the first valid byte of the cell is available on the
Transmit Data Bus UXDATA[7−0].
UXDATA[7−0]
Out
8-bit Transmit Data Bus. Slave transmits ATM cells to the master using this
bus on rising edge of UXCLK.
UTOPIA Receive Interface (Slave mode)
URCLK
In
UTOPIA Receive Clock is an input signal driven by the ATM master. Receive
data and control signals are sampled and synchronous to this clock.
URADDR[4−0]
In
5-bit address bus input driven by the master to select a slave.
URCLAV
Out
Receive Cell Available status signal is an output from the slave to indicate
that it has space available to receive a cell from the master. For cell-level
handshake, the following is true:
0: No space is available to receive a cell from the master.
1: Space is available to receive a cell from the master.
URENB
In
UTOPIA Receive Interface Enable. An active-low signal driven by the master
to enable the receive interface of the slave. It indicates to the slave to sample
Receive Data and SOC signal in the next clock cycle or thereafter.
URSOC
In
Receive Start-Of-Cell signal driven by the master to indicate that the first valid
byte of the cell is available on the Receive Data Bus for the slave to sample.
URDATA[7−0]
In
8-bit UTOPIA Receive Data Bus. Data from the master is received on this
bus. Data is sampled on the rising edge of URCLK.
14
UTOPIA
SPRUE48
UTOPIA Slave as ATM Controller
3.2
Slave-Transmit Operation
The UTOPIA slave-transmit block consists of a UTOPIA Level 2 pin interface
that interfaces internally to the slave-transmit queue. Figure 2 shows the
UTOPIA slave-transmit block diagram. The slave-transmit queue can be
accessed via the UXQ data port. The EDMA controller services the
slave-transmit queue with 32-bit writes when a transmit event is generated by
the UTOPIA transmit section.
When the UTOPIA slave interface detects its address on the transmit address
bus, UXADDR[4−0], it drives the UXCLAV signal to indicate to the master that
a cell is or is not available for transmit. In the following cycles when the master
chooses (after completion of any on-going data transfers) to get the data from
this UTOPIA slave, the master asserts the slave address along with the enable
signal, UXENB. Next, the slave starts transmitting the data on its
UXDATA[7−0] pins, by asserting the start-of-cell signal, UXSOC. Figure 5
shows the UTOPIA slave-transmit interface timing. The clock for the UTOPIA
slave-transmit interface, UXCLK, is an input driven by the external master.
Figure 5.
ATM Controller Slave Transmit Timing Diagram
Master Polling
UXCLK (input)
UXADDR[4−0]
(input)
Slave N+2 selected
N+1
UXCLAV (output)
0x1F
N+2
N+1
0x1F
N+2
N+2
0x1F
N+2
UXENB (input)
Data Transmission
UXSOC (output)
Slave N+2 starts transmission to Master
UXDATA [7−0]
(output)
SPRUE48
P44
P45
P46
P47
P48
X
H1
H5
P1
P2
UTOPIA
15
UTOPIA Slave as ATM Controller
3.3
Slave-Transmit Queue
The slave-transmit queue facilitates the UTOPIA interface to be ready to transmit
data whenever the master requests one. The slave-transmit queue generates
a transmit event (UXEVT) when it is not full. This transmit event triggers the
EDMA controller to perform 32-bit writes to the slave-transmit queue. A total
of 14 word writes are required to fill one standard ATM cell packet in the queue.
As soon as the first write to the queue occurs, the transmit event is cleared.
The next transmit event is generated if the queue is not full. This allows the
EDMA controller to begin the next cell-packet write without having to wait for
the current cell to be fully written to the queue. This process repeats as
described below.
The transmit event is generated and cleared as follows:
1) UXEVT is generated when the queue is not full. The queue is not full when
there is space for at least one cell packet (56B).
2) UXEVT is cleared when the first write (by the EDMA controller) of that cell
occurs.
3) UXEVT is regenerated immediately (without waiting for the previous cell
to be fully written) if the queue is not full.
4) Go to step 2.
The UTOPIA slave will agree for transmission to the master by asserting its
UXCLAV signal when there is at least one cell available in the slave-transmit
queue. If the slave cannot provide the next cell in a contiguous fashion, it
deasserts its UXCLAV signal in the cycle following the completion of the
current cell transmission. The UXCLAV signal remains asserted if the slave
has another cell available to transfer to the master. The master may disable
RXENB on its side (connected to the UXENB pin for this ATMC slave), which
causes the UTOPIA slave to hold off the next cell transfer until the master
commands it.
16
UTOPIA
SPRUE48
UTOPIA Slave as ATM Controller
3.4
Slave-Receive Operation
The UTOPIA slave-receive block consists of a UTOPIA Level 2 pin interface
that interfaces internally to a slave-receive queue. The UTOPIA slave-receive
block diagram is shown in Figure 2. The slave-receive queue can be accessed
via the URQ data port. The EDMA controller services the slave-receive queue
with 32-bit reads when a receive event is generated by the UTOPIA receive
section.
When the master polls for slaves in the system that can receive its cells, the
UTOPIA slave responds with an active cell-available signal on its URCLAV pin
if it has space in the slave-receive queue to receive a complete cell. The
master can choose to transmit to this slave or continue to poll to find a suitable
slave for its data. In any case, the UTOPIA slave responds to its assigned
address by asserting its appropriate URCLAV state a cycle after its address
is detected on the receive address bus, URADDR[4−0]. The master then
outputs the slave address that has an active RCLAV signal and also provides
the enable signal (URENB on slave) to enable slave-receive operation. The
UTOPIA receive slave starts receiving data in the cycle when the master
asserts its start-of-cell signal, URSOC. The bytes are assembled into words
and written into the slave-receive queue. Figure 6 shows the UTOPIA
slave-receive interface timing. The clock for the UTOPIA slave-receive
interface, URCLK, is an input driven by the external master.
Figure 6.
ATM Controller Slave Receive Timing Diagram
Master Polling
URCLK (input)
Slave N+2 selected
URADDR[4−0]
(input)
N+1
0x1F
N+2
N+1
URCLAV (output)
0x1F
N+2
N+2
0x1F
N+2
Data Reception
URENB (input)
URSOC (output)
URDATA [7−0]
P45
P46
P47
P48
Slave N+2 receiving data from Master
H1
H5
P1
P2
(input)
SPRUE48
UTOPIA
17
UTOPIA Slave as ATM Controller
3.5
Slave-Receive Queue
When the master initiates the transfers to the slave, the slave-receive queue
generates a receive event (UREVT) to the EDMA controller when at least one
cell worth of data is available. As soon as the first read is performed by the
EDMA controller, the receive event is cleared. The next receive event is
generated when the next cell is fully available and the process repeats.
The receive event is generated and cleared as follows:
1) UREVT is generated when a complete cell is available.
2) UREVT is cleared when the first read (by the EDMA controller) of that cell
occurs.
3) UREVT is regenerated when the next complete cell is available in the
slave-receive queue.
4) Go to step 2.
The UTOPIA slave will agree for reception from the master by asserting its
URCLAV signal when there is at least one cell space available in the
slave-receive queue. If the slave cannot receive the next cell immediately, it
deasserts its URCLAV signal at least 4 URCLK cycles before the end of this
cell transfer. If it remains asserted, it indicates that the slave can receive another
cell from the master. The master may disable TXENB on its side (URENB for
this ATMC slave) at its discretion.
3.6
UTOPIA Events Generation
The UTOPIA transmit and receive queues generate not-full and not-empty
events to the EDMA controller. The events are generated when the queues
have space available for at least one cell and not when the queues are
completely full or empty. This allows for more throughput and better
performance because the transmit and receive data can be continuously
transferred without having to wait for a full or empty queue. See section 3.3 and
section 3.5 for details on the generation of these events. The EDMA controller
will service the UTOPIA in response to these events, as discussed in section 4.
18
UTOPIA
SPRUE48
UTOPIA Slave as ATM Controller
3.7
Multi-PHY (MPHY) Operation
The UTOPIA interface supports multi-PHY operation as per UTOPIA Level 2
specification. The multi-PHY (MPHY) mode is enabled when the MPHY bit in
the UTOPIA control register (UCR) is set to 1 (default state). In MPHY mode,
the slave ID (SLID) bit in UCR indicates the PHY address of the UTOPIA.
Either the DSP or the external master programs the SLID bits. The
programming interface can either be the HPI or the PCI.
MPHY operation is based on cell-level handshaking. As shown in Figure 5 and
Figure 6, the external ATM master polls for available slave devices before the
beginning of the actual data transaction. The UTOPIA output signals URCLAV,
UXCLAV, UXSOC, and UXDATA[7−0] are in high-impedance state when the
UTOPIA slave is not selected by the master. When the UTOPIA slave detects
its address at the UXADDR[4−0] or URADDR[4−0] pins, it asserts the UXCLAV
or URCLAV signal, respectively.
When used in single-PHY mode (MPHY = 0 in UCR), there is no need to program
the address.
SPRUE48
UTOPIA
19
EDMA Controller Servicing UTOPIA
4
EDMA Controller Servicing UTOPIA
The EDMA controller is used to service the UTOPIA interface. Table 2 lists the
UTOPIA synchronization events to the EDMA controller and their
corresponding EDMA channel.
Table 2.
EDMA Synchronization Events from UTOPIA
EDMA
Event
EDMA
Channel
UXEVT
40
Transmit event from the UTOPIA to the EDMA controller. UXEVT is asserted if the
transmit queue has space for at least one cell packet.
UREVT
32
Receive event from the UTOPIA to the EDMA controller. UREVT is asserted if a
complete cell packet is available in the receive queue.
4.1
Synchronization Event Description
EDMA Setup for UTOPIA Transmitter
As mentioned in section 3.6, the UTOPIA transmitter generates a UXEVT
synchronization event to the EDMA controller when at least one cell-packet
space is available in the slave-transmit queue. EDMA event 40 is dedicated
to the UXEVT event. Per the UXEVT synchronization event, one frame of
cell-packet data is transferred to the slave-transmit queue. A standard
cell-packet consists of 14 words (56 bytes), while a nonstandard cell-packet
consists of 14, 15, or 16 words (56, 60, or 64 bytes). The EDMA access to the
UTOPIA is always 32 bits. The EDMA source address should point to the
UTOPIA source buffer in the DSP memory (internal or external). The EDMA
destination address should point to the slave-transmit queue data port UXQ.
Figure 7 provides a code example of an EDMA3 setup to service a UTOPIA
transmitter for a single cell-packet.
20
UTOPIA
SPRUE48
EDMA Controller Servicing UTOPIA
Figure 7.
EDMA3 Setup for UTOPIA Transmitter Code Example
//***************************************************\
* EDMA TX Channel Configuration
\****************************************************/
void TXChannelParamSetup()
{
paramSetupTx.option =
CSL_EDMA_OPT_MAKE(
FALSE,
/* ITCCEN = 0 (Intermediate transfer complete
chaining) */
FALSE,
/* TCCEN = 0 (Transfer complete chaining */
FALSE,
/* ITCINTEN = 0 (Intermediate transfer
complete interrupt */
TRUE,
/* TCINTEN = 1 (Transfer complete interrupt */
CSL_EDMA_CHA40, /* TCC = 1 to 63 (Transfer Complete Code)*/
CSL_EDMA_TCC_NORMAL, /* TCCMODE = 0 ( Normal Completion) */
CSL_EDMA_FIFOWIDTH_NONE, /* FWid = NONE(Fifo Width) */
FALSE,
/* STAT = 0 (Entry is updated as normal) */
CSL_EDMACC_OPT_SYNCDIM_ASYNC, /* SYNCDIM = 0 (A-Sync. Each event triggers
the transfer ACNT elements) */
CSL_EDMA_ADDRMODE_INCR, /* DAM = 0 (Dst addressing within an array
increments. Dst is not a FIFO) */
CSL_EDMA_ADDRMODE_INCR /*SAM = 0 (Src addressing within an array
increments. Source is not a FIFO) */
);
paramSetupTx.srcAddr = srcTxAddr;
/* Source Address : start address of the source buffer
(must be double−word aligned) */
paramSetupTx.aCntbCnt = CSL_EDMA_CNT_MAKE(TxACnt, TxBCnt);
/* ACNT = 56 (Number of bytes in an array, should be
equal to number of bytes in one receive cell) It can have
only values 56, 60 and 64 */
/* BCNT = 1 (Number of arrays of length ACNT, should be
equal to number of cell−packets to be transferred) */
paramSetupTx.dstAddr = UTOPIA_TXQ_ADDR;
/* Utopia Transmit Queue Base Address (0x3C000400)/*
paramSetupTx.srcDstBidx = CSL_EDMA_BIDX_MAKE(TxBIdx, 0);
/* SRCBIDX = TxBIdx = ACNT (Source 2nd Dimension Index)*/
/* DSTBIDX = 0 (Destination 2nd Dimension Index) */
paramSetupTx.linkBcntrld = CSL_EDMA_LINKBCNTRLD_MAKE(CSL_EDMA_LINK_NULL, 0);
paramSetupTx.srcDstCidx = CSL_EDMA_CIDX_MAKE(TxCIdx, TxCIdx);
/ * SRCCCIDX = TxCIdx = 0 (Source 3rd Dimension Index)*/
/* DSTCIDX = 0 (Destination 3rd Dimension Index) */
paramSetupTx.cCnt = TxCCnt; /* CCNT = 1 (Number of frames in a block)*/
paramSetupTx.triggerWord = CSL_EDMA_TRIGWORD_NONE;
hParamTx = CSL_edmaGetParamHandle(hChTx,PARAM_NUMTx,NULL);
CSL_edmaParamSetup(hParamTx,&paramSetupTx,CSL_EDMA_PARAM_BASIC);
}
SPRUE48
UTOPIA
21
EDMA Controller Servicing UTOPIA
4.2
EDMA Setup for UTOPIA Receiver
As mentioned in section 3.6, the UTOPIA receiver generates a UREVT
synchronization event to the EDMA controller when the slave-receive queue
has space for at least one cell-packet. EDMA event 32 is dedicated to the
UREVT event. Per UREVT synchronization event, one frame of cell-packet
data is read from the slave-receive queue via the data port URQ. A standard
cell-packet consists of 14 words (56 bytes), while a nonstandard cell-packet
consists of 14, 15, or 16 words (56, 60, or 64 bytes). The EDMA destination
address should point to the destination buffer in the DSP memory (internal or
external).
Figure 8 shows a code example of an EDMA3 setup to service a UTOPIA
receiver for a single cell-packet.
22
UTOPIA
SPRUE48
EDMA Controller Servicing UTOPIA
Figure 8.
EDMA3 Setup for UTOPIA Receiver Code Example
//***************************************************\
* EDMA RX Channel Configuration
\****************************************************/
void RXChannelParamSetup()
{
CSL_EDMA_OPT_MAKE(paramSetupRx.option
FALSE,
/* ITCCEN = 0 (Intermediate transfer complete
chaining) */
FALSE,
/* TCCEN = 0 (Transfer complete chaining */
FALSE,
/* ITCINTEN = 0 (Intermediate transfer
complete interrupt */
TRUE,
/* TCINTEN = 1 (Transfer complete interrupt */
CSL_EDMA_CHA32, /* TCC = 1 to 63 (Transfer Complete Code)*/
CSL_EDMA_TCC_NORMAL, /* TCCMODE = 0 ( Normal Completion) */
CSL_EDMA_FIFOWIDTH_NONE, /* FWid = NONE(Fifo Width) */
FALSE,
/* STAT = 0 (Entry is updated as normal) */
CSL_EDMACC_OPT_SYNCDIM_ASYNC, /* SYNCDIM = 0 (A-Sync. Each event triggers
the transfer ACNT elements) */
CSL_EDMA_ADDRMODE_INCR, /* DAM = 0 (Dst addressing within an array
increments. Dst is not a FIFO) */
CSL_EDMA_ADDRMODE_INCR /*SAM = 0 (Src addressing within an array
increments. Source is not a FIFO) */
);
paramSetupRx.srcAddr = UTOPIA_RXQ_ADDR
/* UTOPIA Receive Queue base Address = (0x3C00 0000h); */
/* srcRxAddr */
paramSetupRx.aCntbCnt = CSL_EDMA_CNT_MAKE(RxACnt, RxBCnt);
/* RxAcnt = 56 (Number of bytes in an array, should be
equal to number of bytes in one receive cell) It can have
only values 56, 60 and 64. */
/* RxBCnt = 1 (Number of arrays of length ACNT, should be
equal to number of cell−packets to be transferred) */
paramSetupRx.dstAddr = dstRxAddr
/* DESTINATION ADDRESS: start address of the destination
array (must be double−word aligned) */
paramSetupRx.srcDstBidx = CSL_EDMA_BIDX_MAKE(RxBIdx, 0);
/* RxBIdx = 0 (Source 2nd Dimension Index)*/
/* DstBIdx = RxBIdx = ACNT (Destination 2nd Dimension
Index) */
paramSetupRx.linkBcntrld = CSL_EDMA_LINKBCNTRLD_MAKE(CSL_EDMA_LINK_NULL, 0);
paramSetupRx.srcDstCidx = CSL_EDMA_CIDX_MAKE(RxCIdx, RxCIdx);
/ * SRCCCIdx = 0 (Source 3rd Dimension Index)*/
/* DSTCIdx = 0 (Destination 3rd Dimension Index) */
paramSetupRx.cCnt = RxCCnt; /* RxCCNT = 1 (Number of frames in a block)*/
paramSetupRx.triggerWord = CSL_EDMA_TRIGWORD_NONE;
hParamRx = CSL_edmaGetParamHandle(hChRx,PARAM_NUMTx,NULL);
CSL_edmaParamSetup(hParamRx,&paramSetupRx,CSL_EDMA_PARAM_BASIC);
}
SPRUE48
UTOPIA
23
CPU
CPU Servicing
Servicing UTOPIA
UTOPIA / UTOPIA Clocking and Clock Detection
5
CPU Servicing UTOPIA
The CPU should not be used to service the UTOPIA peripheral on C645x
devices.
6
UTOPIA Clocking and Clock Detection
The transmit and receive clock for the UTOPIA interface is supplied by an
external clock source such as the master ATM controller. This allows for
accurate clocks as required by most applications. Internal to the DSP, the
UTOPIA registers and queues are synchronized to the DSP peripheral clock
at a CPU/6 rate.
Clock detection logic has been implemented to facilitate proper reset of the
UTOPIA interface when the clock(s) is removed from the system. It uses a
user-programmable Clock Detect Register to trigger the clock detection based
on the (R/X) CCNT bit-field parameters. Receive and transmit logic are
independent of each other.
24
UTOPIA
SPRUE48
Special Transfer Conditions
7
Special Transfer Conditions
This section explains how the UTOPIA slave interface handles some of the
error conditions.
- Runt cells: Runt cells are those cells that are shorter than the standard
ATM cell (53 bytes for 8-bit mode). This occurs when the device sending
data asserts SOC in the middle of a cell transfer. If the receive section of
the UTOPIA detects a SOC before a complete cell is received, the byte
count is reset and the runt cell is overwritten by the next new data. In the
transmit direction, you cannot force SOC; intentional runt cell generation
is not supported.
- Absence of UTOPIA clocks: If, for any reason during a cell transfer in either
direction, the receive clock (URCLK) or transmit clock (UXCLK) stop
toggling, the corresponding section of the UTOPIA may be reset
depending on the duration of absence. The queues are returned to their
reset state, and all control registers are reset. In addition, the receive clock
failed (RCFP) or transmit clock failed (XCFP) bit, respectively, is set in the
error interrupt pending register (EIPR). An interrupt UINT is generated to
the CPU if the corresponding bits in the error interrupt enable register
(EIER) are set. This helps when recovering from conditions where the
master card (that supplies the clocks) is pulled from the system.
The receive clock present (RCPP) and transmit clock present (XCPP) bits
in EIPR are set if the URCLK and UXCLK are detected, regardless of the
state of the UTOPIA port. If the corresponding bits are enabled in EIER, an
interrupt UINT is generated. This is useful in reenabling the UTOPIA ports
once the UTOPIA clocks are detected.
- Abrupt reset: In slave mode, typically the master issues a reset command
via the management interface to ensure a graceful stop of transfers. But
if this is violated, data corruption occurs and the system software should
comprehend this. In short, abrupt reset causes data loss/corruption. It is
your responsibility to avoid such conditions.
SPRUE48
UTOPIA
25
Endian
SpecialConsiderations
Transfer Conditions / Endian Considerations
- FIFO read/write stall conditions: There are two potential stall conditions
when a read or a write to the transmit/receive queues is attempted when
the transmit/receive queues are not ready (when UXEVT and UREVT are
not active):
8
J
Writes to a FULL slave-transmit queue: Writing to the transmit queue
that is full renders the queue not ready. In other words, writes are
stalled until the queue is drained and space is available for further
writes. Therefore, data is not overwritten. When such a condition
occurs, the transmit queue stall interrupt pending (XQSP) status bit in
EIPR is set to indicate the stall condition. The XQSP bit is a read-only
bit and is cleared once the queue has space available, and writes can
continue.
J
Reads from an EMPTY slave-receive queue: Attempting to read a
queue that has no data results in stalling that operation until valid data
is available. This also sets the receive queue stall interrupt pending
(RQSP) bit in EIPR to indicate the read stall condition. This is a user
error, because a read access is performed when there is no active
UREVT. The RQSP bit is a read-only bit and is cleared as soon as valid
data is available in the receive queue and the read is performed.
Endian Considerations
For 8-bit operation, bytes are assembled into words in the UTOPIA queues.
Device endian configuration is selected during reset. Pin-level endian
configuration ensures the desired endian mode for the DSP/CPU. For the
UTOPIA interface to present the data transferred across its interface to the
DSP in accordance with the device endian mode, the big-endian mode enable
bit (BEND) in the UTOPIA control register (UCR) has to be programmed. By
default/reset, the UTOPIA data is presented to the DSP in little-endian format
(BEND = 0). If big-endian is preferred, the BEND bit should be programmed
to 1. The data bytes are swapped in hardware based on the BEND value.
When the DSP is a UTOPIA slave in a system, it only communicates to the
master. Therefore, the communication from the slave’s perspective is always
point-to-point. The cell-packet transfer formats are shown in Figure 3.
Depending on the user-defined cell (RUDC and XUDC bits) and endian format
(BEND bit) as listed in Table 3, bytes are placed in the transmit and receive
queues as shown in Figure 9 through Figure 14.
The cell-packet formats in Figure 9 through Figure 14 indicate the data stored
in the DSP memory (internal or external) and in the transmit/receive queues.
Only the ATM data, including the header and payload information but not the
Dummy bytes, is actually sent or received across the UTOPIA pins.
26
UTOPIA
SPRUE48
Endian Considerations
Table 3.
8-Bit UTOPIA Slave Modes Depending on BEND, XUDC, and RUDC Bits
UCR Bits
Endian mode
BEND bit
XUDC value
RUDC value
See ...
Little endian
0
0 (disabled)
0 (disabled)
Figure 9
Big endian
1
0 (disabled)
0 (disabled)
Figure 10
Big endian
1
1
1
Figure 11
Little endian
0
7
7
Figure 12
Little endian
0
11
11
Figure 13
Big endian
1
11
11
Figure 14
Figure 9.
8-Bit UTOPIA Slave in Little-Endian Mode (BEND = 0) with RUDC/XUDC = 0
Queue Bits
31−24
23−16
15−8
7−0
Address n
Header 1
Dummy
Dummy
Dummy
Word 0
Address n+4
UDF
Header 4
Header 3
Header 2
Word 1
Address n+8
Payload 4
Payload 3
Payload 2
Payload 1
:
::
::
::
::
::
:
Address n+48
Payload 44
Payload 43
Payload 42
Payload 41
:
Address n+52
Payload 48
Payload 47
Payload 46
Payload 45
Word 13
SPRUE48
UTOPIA
27
Endian Considerations
Figure 10.
8-Bit UTOPIA Slave in Big-Endian Mode (BEND = 1) with RUDC/XUDC = 0
Queue Bits
31−24
23−16
15−8
7−0
Address n
Dummy
Dummy
Dummy
Header 1
Word 0
Address n+4
Header 2
Header 3
Header 4
UDF
Word 1
Address n+8
Payload 1
Payload 2
Payload 3
Payload 4
:
::
::
::
::
::
:
Address n+48
Payload 41
Payload 42
Payload 43
Payload 44
:
Address n+52
Payload 45
Payload 46
Payload 47
Payload 48
Word 13
Figure 11.
8-Bit UTOPIA Slave in Big-Endian Mode (BEND = 1) with RUDC/XUDC = 1
Queue Bits
31−24
23−16
15−8
7−0
Address n
Dummy
Dummy
UDB 1
Header 1
Word 0
Address n+4
Header 2
Header 3
Header 4
UDF
Word 1
Address n+8
Payload 1
Payload 2
Payload 3
Payload 4
:
::
::
::
::
::
:
Address n+48
Payload 41
Payload 42
Payload 43
Payload 44
:
Address n+52
Payload 45
Payload 46
Payload 47
Payload 48
Word 13
Figure 12.
28
8-Bit UTOPIA Slave in Little-Endian Mode (BEND = 0) with RUDC/XUDC = 7
Queue Bits
31−24
23−16
15−8
7−0
Address n
UDB 4
UDB 3
UDB 2
UDB 1
Word 0
Address n+4
Header 1
UDB 7
UDB 6
UDB 5
Word 1
Address n+8
UDF
Header 4
Header 3
Header 2
:
Address n+12
Payload 4
Payload 3
Payload 2
Payload 1
:
::
::
::
::
::
:
Address n+56
Payload 48
Payload 47
Payload 46
Payload 45
Word 14
UTOPIA
SPRUE48
Endian Considerations
Figure 13.
8-Bit UTOPIA Slave in Little-Endian Mode (BEND = 0) with RUDC/XUDC = 11
Queue Bits
31−24
23−16
15−8
7−0
Address n
UDB 4
UDB 3
UDB 2
UDB 1
Word 0
Address n+4
UDB 8
UDB 7
UDB 6
UDB 5
Word 1
Address n+8
Header 1
UDB 11
UDB 10
UDB 9
Word 2
Address n+12
UDF
Header 4
Header 3
Header 2
:
Address n+16
Payload 4
Payload 3
Payload 2
Payload 1
:
::
::
::
::
::
:
Address n+60
Payload 48
Payload 47
Payload 46
Payload 45
Word 15
Figure 14.
8-Bit UTOPIA Slave in Big-Endian Mode (BEND = 1) with RUDC/XUDC = 11
Queue Bits
31−24
23−16
15−8
7−0
Address n
UDB 1
UDB 2
UDB 3
UDB 4
Word 0
Address n+4
UDB 5
UDB 6
UDB 7
UDB 8
Word 1
Address n+8
UDB 9
UDB 10
UDB 11
Header 1
Word 2
Address n+12
Header 2
Header 3
Header 4
UDF
:
Address n+16
Payload 1
Payload 2
Payload 3
Payload 4
:
::
::
::
::
::
:
Address n+60
Payload 45
Payload 46
Payload 47
Payload 48
Word 15
SPRUE48
UTOPIA
29
UTOPIA Reset
9
UTOPIA Reset
The UTOPIA interface is in reset state during device reset. The UTOPIA
interface can also be reset through software by programming the UREN and
UXEN bits in the UTOPIA control register (UCR) when the device is out of
reset. The peripheral reset via software ensures that the state machine is in
a known state and there is no activity in the corresponding section. The
software reset does not reset registers to their default values.
The UTOPIA pins have no internal pull-up or pull-down resistors; therefore, all
input pins should be pulled externally to bring inputs to a known state. The
Reset Value column of Table 4 shows the recommended state for the UTOPIA
pins during reset. Note that the address pins are pulled high to give the address
of a null PHY/slave (address 11111b) during reset. At reset, all outputs are
driven to a high-impedance state to facilitate MPHY operation.
Table 4.
UTOPIA Pin Reset Values
UTOPIA Pin
30
UTOPIA
ATM Controller SLAVE (Direction)
Reset Value
UXCLK
In
Low
UXADDR[4−0]
In
High
UXCLAV
Out
High impedance
UXENB
In
High
UXSOC
Out
High impedance
UXDATA[7−0]
Out
High impedance
URCLK
In
Low
URADDR[4−0]
In
High
URCLAV
Out
High impedance
URENB
In
High
URSOC
In
Low
URDATA[7−0]
In
Low
SPRUE48
UTOPIA
Slave Initialization
UTOPIA Slave Initialization Sequence / ATM
Adaptation
Layer (AAL) Sequence
Functions
10
UTOPIA Slave Initialization Sequence
A device reset or a programmable reset via the UTOPIA control register (UCR)
resets the UTOPIA interface. To initialize the UTOPIA interface for slave
operation, the following steps are required:
- The UTOPIA master device in the system provides the clock input to
URCLK and UXCLK. The UTOPIA port cannot be initialized without these
clocks.
- Ensure that the DSP is out of reset.
- Program the EDMA channel(s) for data transmission and reception to/from
the UTOPIA interface.
- Set up the UTOPIA configuration registers as required.
- Either the DSP or the external ATM master can write the address of this
slave/PHY in UCR. The external ATM master can write to UCR via the HPI
or PCI interfaces.
- Take the interface out of reset by setting the UREN bit to enable the receive
interface and setting the UXEN bit to enable the transmit interface. Note
that the transmit and receive interfaces are independent of each other. In
typical systems, both are used.
11
ATM Adaptation Layer (AAL) Functions
The UTOPIA interface provides a standard hardware interface between an
ATM Layer device (master) and a PHY device (slave). The ATM adaptation
layer functions such as segmentation and re-assembly (SAR) for AAL2, AAL5
should be implemented in software.
SPRUE48
UTOPIA
31
Registers
12
Registers
The UTOPIA port is configured via the configuration registers listed in Table 5.
The data for transmit and receive queues are accessible via the EDMA controller
or CPU at the data port listed in Table 6. See the device-specific datasheet for
the memory address of these registers.
Table 5.
UTOPIA Configuration Registers
Offsets
Acronym
Register Name
0000
UCR
UTOPIA Control Register
12.1
0014
CDR
Clock Detect Register
12.2
0018
EIER
Error Interrupt Enable Register
12.3
001C
EIPR
Error Interrupt Pending Register
12.4
Table 6.
Section
UTOPIA Data Ports
Offsets
Acronym
Queue Name
0000
URQ
UTOPIA Receive Queue
3.5
0004
UXQ
UTOPIA Transmit Queue
3.3
12.1
Section
UTOPIA Control Register (UCR)
The UTOPIA interface is configured via the UTOPIA control register (UCR)
and contains UTOPIA status and control bits. The UCR is shown in Figure 15
and described in Table 7.
Figure 15.
31
UTOPIA Control Register (UCR)
30
29 28
24 23
22 21
18
17
16
BEND
Reserved
SLID
Reserved
XUDC
Rsvd
UXEN
R/W-0
R-1
R/W-0
R-0
R/W-0
R-0
R/W-0
1
0
15
14
13
6 5
2
Rsvd
MPHY
Reserved
RUDC
Rsvd
UREN
R-0
R/W-1
R-0
R/W-0
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
32
UTOPIA
SPRUE48
Registers
Table 7.
UTOPIA Control Register (UCR) Field Descriptions
Bit
Field
31
BEND
30−29
Reserved
28−24
SLID
Value
Description
Big-endian mode enable bit for data transferred by way of the UTOPIA
interface.
0
Data is assembled to conform to little-endian format.
1
Data is assembled to conform to big-endian format.
1
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
0−1Fh Slave ID bits. Applicable in multi-PHY mode (MPHY = 1). This 5-bit value is
used to identify the UTOPIA in a MPHY set up. Does not apply to single-PHY
slave operation (MPHY = 0).
0
1Fh
23−22
Reserved
21−18
XUDC
Null PHY/slave address.
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
0−Fh
Transmit user-defined cell bits. Valid values are 0 to 11, the remaining values
are reserved.
0
XUDC feature is disabled. The UTOPIA interface transmits a normal ATM cell
of 53 bytes.
1h−Bh UTOPIA interface transmits the programmed number (1 to 11) of bytes as extra
header. A UDC may have a minimum of 54 bytes (XUDC = 1h) up to a
maximum of 64 bytes (XUDC = Bh).
Ch−Fh Reserved
17
Reserved
16
UXEN
15
Reserved
SPRUE48
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
UTOPIA transmitter enable bit.
0
UTOPIA port transmitter is disabled and in reset state.
1
UTOPIA port transmitter is enabled.
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
UTOPIA
33
Registers
Table 7.
UTOPIA Control Register (UCR) Field Descriptions (Continued)
Bit
Field
14
MPHY
13−6
Reserved
5−2
RUDC
Value
Description
UTOPIA receive/transmit multi-PHY mode enable bit.
0
Single PHY mode is selected for receive and transmit UTOPIA.
1
Multi-PHY mode is selected for receive and transmit UTOPIA.
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
0−Fh
Receive user-defined cell bits. Valid values are 0 to 11, the remaining values
are reserved.
0
RUDC feature is disabled. The UTOPIA interface expects a normal ATM cell of
53 bytes.
1h−Bh UTOPIA interface expects to receive the programmed number (1 to 11) of
bytes as extra header. A UDC may have a minimum of 54 bytes (RUDC = 1h)
up to a maximum of 64 bytes (RUDC = Bh).
Ch−Fh Reserved
34
1
Reserved
0
UREN
UTOPIA
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
UTOPIA receiver enable bit.
0
UTOPIA port receiver is disabled and in reset state.
1
UTOPIA port receiver is enabled.
SPRUE48
Registers
12.2
Clock Detect Register (CDR)
The clock detect register (CDR) and the UTOPIA clock detection feature
allows the DSP to detect the presence of the URCLK and/or UXCLK. The CDR
is shown in Figure 16 and described in Table 8.
If a URCLK or a UXCLK edge is not detected within the respective time period
specified in CDR, an error bit, RCFP or XCFP, respectively, is set in the error
interrupt pending register (EIPR). In addition, the RCPP and XCPP bits in
EIPR indicate the presence of the URCLK and UXCLK, respectively. See
section 7 for usage of these interrupts to the CPU.
Figure 16.
Clock Detect Register (CDR)
31
24 23
16
Reserved
XCCNT
R-0
R/W-FFh
15
8 7
0
Reserved
RCCNT
R-0
R/W-FFh
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 8.
Bit
Clock Detect Register (CDR) Field Descriptions
Field
31−24
Reserved
23−16
XCCNT
Value
Description
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
0−FFh
Transmit clock count bits specify the number of peripheral clock cycles that
the external UTOPIA transmit clock (UXCLK) must have a low-to-high
transition to avoid a reset of the transmit interface. If a UXCLK clock edge is
undetected within XCCNT peripheral clock cycles, the transmit UTOPIA port
is reset by hardware. The XCF error bit (XCFP) in the error interrupt pending
register (EIPR) is set.
0
Transmit clock detect feature is disabled.
1h−FEh Transmit clock detect feature is enabled. This 8-bit value is the number of
peripheral clock cycles before the next UTOPIA clock edge (UXCLK) must be
present.
FFh
SPRUE48
Transmit clock detect feature is enabled. There must be 255 peripheral clock
cycles before the next UTOPIA clock edge (UXCLK).
UTOPIA
35
Registers
Table 8.
Bit
Clock Detect Register (CDR) Field Descriptions (Continued)
Field
Value
15−8
Reserved
7−0
RCCNT
0
Description
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
0−FFh
0
Receive clock count bits specify the number of peripheral clock cycles that
the external UTOPIA receive clock must have a low-to-high transition to
avoid a reset of the receive interface. If a URCLK clock edge is undetected
within RCCNT peripheral clock cycles, the receive UTOPIA port is reset by
hardware. The RCF error bit (RCFP) in the error interrupt pending register
(EIPR) is set.
Receive clock detect feature is disabled.
1h−FEh Receive clock detect feature is enabled. This 8-bit value is the number of
peripheral clock cycles before the next UTOPIA clock edge (URCLK) must be
present.
FFh
12.3
Receive clock detect feature is enabled. There must be 255 peripheral clock
cycles before the next UTOPIA clock edge (URCLK).
Error Interrupt Enable Register (EIER)
If an error condition is set in the error interrupt enable register (EIER) and the
corresponding error is set in the error interrupt pending register (EIPR), an
interrupt is generated to the CPU. The EIER is shown in Figure 17 and
described in Table 9.
Figure 17.
Error Interrupt Enable Registers (EIER)
31
19
18
17
16
Reserved
XCPE
XCFE
XQSE
R-0
R/W-0
R/W-0
R/W-0
2
1
0
15
3
Reserved
RCPE
RCFE
RQSE
R-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
36
UTOPIA
SPRUE48
Registers
Table 9.
Bit
31−19
18
17
16
15−3
2
1
0
Error Interrupt Enable Register (EIER) Field Descriptions
Field
Reserved
Value
0
XCPE
0
Transmit clock present interrupt is disabled.
1
Transmit clock present interrupt is enabled.
Transmit clock failed interrupt enable bit.
0
Transmit clock failed interrupt is disabled.
1
Transmit clock failed interrupt is enabled.
XQSE
Transmit queue stall interrupt enable bit.
0
Transmit queue stall interrupt is disabled.
1
Transmit queue stall interrupt is enabled.
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
RCPE
Receive clock present interrupt enable bit.
0
Receive clock present interrupt is disabled.
1
Receive clock present interrupt is enabled.
RCFE
Receive clock failed interrupt enable bit.
0
Receive clock failed interrupt is disabled.
1
Receive clock failed interrupt is enabled.
RQSE
SPRUE48
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
Transmit clock present interrupt enable bit.
XCFE
Reserved
Description
Receive queue stall interrupt enable bit.
0
Receive queue stall interrupt is disabled.
1
Receive queue stall interrupt is enabled.
UTOPIA
37
Registers
12.4
Error Interrupt Pending Register (EIPR)
The UTOPIA error conditions are recorded in the error interrupt pending
register (EIPR). The EIPR is shown in Figure 18 and described in Table 10. A
write of 1 to the XCPP, XCFP, RCPP, or RCFP bit clears the corresponding bit.
A write of 0 has no effect. The XQSP and RQSP bits are read-only bits and are
cleared automatically by the UTOPIA interface once the error conditions
cease. The error conditions in EIPR can generate an interrupt to the CPU, if
the corresponding bits are set in the error interrupt enable register (EIER).
Figure 18.
Error Interrupt Pending Register (EIPR)
31
19
18
17
16
Reserved
XCPP
XCFP
XQSP
R-0
R/W-0
R/W-0
R-0
2
1
0
Reserved
RCPP
RCFP
RQSP
R-0
R/W-0
R/W-0
R-0
15
3
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 10. Error Interrupt Pending Register (EIPR) Field Descriptions
Bit
31−19
18
17
38
Field
Reserved
Value
0
XCPP
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
Transmit clock present interrupt pending bit indicates if the UTOPIA transmit
clock (UXCLK) is present. XCPP is valid regardless if the transmit interface is
enabled or disabled.
0
UXCLK is not present.
1
UXCLK is present. If the corresponding bit in EIER is set, an interrupt UINT is
sent to the CPU.
XCFP
UTOPIA
Description
Transmit clock failed interrupt pending bit is activated only when the UTOPIA
transmit interface is enabled (UXEN in UCR = 1).
0
UXCLK is present.
1
UXCLK failed. No UXCLK is detected for a period longer than that specified in
the XCCNT field of CDR. If the corresponding bit in EIER is set, an interrupt
UINT is sent to the CPU.
SPRUE48
Registers
Table 10. Error Interrupt Pending Register (EIPR) Field Descriptions (Continued)
Bit
Field
16
XQSP
15−3
2
1
0
Reserved
Value
Transmit queue stall interrupt pending bit.
0
No transmit queue stall condition.
1
Transmit queue stalled, a write is performed to a full transmit queue. The write
is stalled until the queue is drained and space is available. Data is not
overwritten. XQSP is cleared once the queue has space available and writes
can continue.
0
Reserved. The reserved bit location always returns the default value. A value
written to this field has no effect. If writing to this field, always write the default
value for future device compatibility.
RCPP
Receive clock present interrupt pending bit indicates if the UTOPIA receive
clock (URCLK) is present. RCPP is valid regardless if the receive interface is
enabled or disabled.
0
URCLK is not present.
1
URCLK is present. If the corresponding bit in EIER is set, an interrupt UINT is
sent to the CPU.
RCFP
Receive clock failed interrupt pending bit is activated only when the UTOPIA
receive interface is enabled (UREN in UCR = 1).
0
URCLK is present.
1
URCLK failed. No URCLK is detected for a period longer than that specified in
the RCCNT field of CDR. If the corresponding bit in EIER is set, an interrupt
UINT is sent to the CPU.
RQSP
SPRUE48
Description
Receive queue stall interrupt pending bit.
0
No receive queue stall condition.
1
Receive queue stalled, a read is performed from an empty receive queue. The
read is stalled until valid data is available in the queue. RQSP is cleared as
soon as valid data is available and the read is performed.
UTOPIA
39
This page is intentionally left blank.
40
UTOPIA
SPRUE48
Index
Index
A
ATM adaption layer interface
I
31
B
BEND bit 32
block diagram
nonstandard cell transfer format 12
standard cell transfer format 12
TMS320C64x DSP 10
UTOPIA 11
UTOPIA slave interfaced to Motorola MPC8260
PowerQUICC II master 13
C
CDR 35
cell transfer format 12
clock detect register (CDR) 35
clocking 24
CPU interrupt (UINT) 24
CPU servicing UTOPIA 24
E
EDMA servicing UTOPIA 20
EDMA setup for UTOPIA receiver 22
EDMA setup for UTOPIA transmitter 20
EIER 36
EIPR 38
endian considerations 26
error interrupt enable register (EIER) 36
error interrupt pending register (EIPR) 38
events generation 18
SPRUE48
interface signals
interrupts 24
9
M
MPHY bit 32
multi-PHY operation
19
N
notational conventions
3
O
operation
multi-PHY 19
slave-receive 17
slave-transmit 15
overview 9
R
RCCNT bits 35
RCFE bit 36
RCFP bit 38
RCPE bit 36
RCPP bit 38
receive event from UTOPIA to EDMA (UREVT) 22
registers 32
clock detect register (CDR) 35
error interrupt enable register (EIER) 36
error interrupt pending register (EIPR) 38
UTOPIA control register (UCR) 32
related documentation from Texas Instruments 3
reset 30
UTOPIA
41
Index
RQSE bit
36
RQSP bit
38
RUDC bits
U
UCR 32
UINT 24
UREN bit 32
UREVT 22
UTOPIA control register (UCR) 32
UTOPIA slave as ATM controller 13
UTOPIA slave initialization sequence 31
UTOPIA slave pins 13
UXEN bit 32
UXEVT 20
32
S
servicing UTOPIA
CPA 24
EDMA 20
slave-receive operation
slave-receive queue
17
18
slave-transmit operation
slave-transmit queue
SLID bits
15
X
16
32
special transfers
25
T
trademarks
4
transmit event from UTOPIA to EDMA (UXEVT)
42
UTOPIA
20
XCCNT bits 35
XCFE bit 36
XCFP bit 38
XCPE bit 36
XCPP bit 38
XQSE bit 36
XQSP bit 38
XUDC bits 32
SPRUE48
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