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Texas Instruments TMS320DM644x DMSoC DSP Subsystem Reference User guides
TMS320DM644x DMSoC
DSP Subsystem
Reference Guide
Literature Number: SPRUE15
December 2005
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Contents
Preface ........................................................................................................................................ 5
1
Introduction......................................................................................................................... 7
2
TMS320C64x+ Megamodule ................................................................................................... 7
3
2.1
TMS320C64x+ CPU ...................................................................................................... 9
2.2
Memory Controllers
2.3
Internal Peripherals ...................................................................................................... 13
10
Memory Map ...................................................................................................................... 15
3.1
DSP Internal Memory (L1P, L1D, L2) ................................................................................. 15
3.2
External Memory ......................................................................................................... 15
3.3
ARM Internal Memory ................................................................................................... 16
3.4
Internal Peripherals ...................................................................................................... 16
......................................................................................................
ARM–DSP Integration .........................................................................................................
DSP Subsystem Clock ........................................................................................................
Power Management ............................................................................................................
Boot and Reset ..................................................................................................................
3.5
4
5
6
7
.....................................................................................................
Device Peripherals
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Table of Contents
16
16
18
18
18
3
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List of Figures
1
2
DSP Subsystem Block Diagram ........................................................................................... 8
C64x+ Cache Memory Architecture...................................................................................... 11
List of Tables
1
2
3
4
DSP Interrupt Map ......................................................................................................... 13
External Memory Table .................................................................................................... 15
DSP Boot Configuration ................................................................................................... 18
List of Figures
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Preface
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Read This First
About This Manual
Describes the digital signal processor (DSP) subsystem in the TMS320DM644x Digital Media
System-on-Chip (DMSoC). The DM644x DSP subsystem includes TI’s standard TMS320C64x+™
Megamodule and several blocks of internal memory (L1P, L1D, and L2). This document provides an
overview of the DSP subsystem and the following considerations associated with it:
• Memory mapping
• Interrupts
• ARM–DSP integration
• DSP subsystem clocking
• Boot and reset
• Power management
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copies
of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
The current documentation that describes the DM644x DMSoC, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUE14 — TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the DSP subsystem, the video
processing subsystem, and a majority of the peripherals and external memories.
SPRUE15 — TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).
SPRUE19 — TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overview
and briefly describes the peripherals available on the TMS320DM644x Digital Media
System-on-Chip (DMSoC).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
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Preface
5
Related Documentation From Texas Instruments
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SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRAAA6 — EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating
from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory
access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This
document summarizes the key differences between the EDMA3 and the EDMA2 and provides
guidance for migrating from EDMA2 to EDMA3.
6
Read This First
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Reference Guide
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TMS320DM644x DMSoC DSP Subsystem
1
Introduction
The TMS320DM644x DSP subsystem (Figure 1) includes TI’s standard TMS320C64x+ Megamodule and
several blocks of internal memory (L1P, L1D, and L2). This document provides an overview of the DSP
subsystem and the following considerations associated with it:
• Memory mapping
• Interrupts
• ARM-DSP integration
• DSP subsystem clocking
• Boot and reset
• Power management
For more information, see the TMS320C64x+ Megamodule Peripherals Reference Guide (SPRU871), the
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732), and the TMS320C64x+
DSP Cache User’s Guide (SPRU862).
2
TMS320C64x+ Megamodule
The C64x+ Megamodule consists of the following components:
• TMS320C64x+ CPU
• Internal memory controllers:
– Program memory controller (PMC)
– Data memory controller (DMC)
– Unified memory controller (UMC)
– External memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals
– Interrupt controller
– Power-down controller (PDC)
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Figure 1. DSP Subsystem Block Diagram
RAM/
cache
RAM/
ROM/
cache
ROM/
RAM
256
256
256
256
Cache control
Memory protect
RAM/
ROM/
SMC
Cache control
256
L1P
Bandwidth mgmt
Memory protect
128
256
256
Instruction fetch
Power down
Interrupt
controller
IDMA
C64x + CPU
Register
file B
128
L2
Bandwidth mgmt
256
Register
file A
256
128
Bandwidth mgmt
Memory protect
32
CFG
EMC
L1D
Chip
registers
256
Cache control
SDMA
32/64/128
8 x 32
RAM/
cache
8
MDMA
TMS320DM644x DMSoC DSP Subsystem
32/64/128
System
infrastructure
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2.1
TMS320C64x+ Megamodule
TMS320C64x+ CPU
The C64x+ Megamodule includes the C64x+ CPU. The C64x+ CPU is a member of the TMS320C6000™
generation of devices. The C6000™ devices execute up to eight 32-bit instructions per cycle. The CPU
consists of 64 general-purpose 32-bit registers and eight functional units. The eight functional units contain
two multipliers and six ALUs. For more information on the CPU, see the TMS320C64x/C64x+ DSP CPU
and Instruction Set Reference Guide (SPRU732).
Features of the C6000 devices include:
• Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units
– Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
– Allows designers to develop highly effective RISC-like code for rapid development time
• Instruction packing
– Gives code-size equivalence for eight instructions that execute serially or in parallel
– Reduces code size, program fetches, and power consumption
• Conditional execution of most instructions
– Reduces costly branching
– Increases parallelism for higher sustained performance
• Efficient code execution on independent functional units
– Industry's most efficient C compiler on DSP benchmark suite
– Industry's first assembly optimizer for rapid development and improved parallelization
• 8/16/32-bit data support, providing efficient memory support for a variety of applications
• 40-bit arithmetic options add extra precision for vocoders and other computationally intensive
applications
• Saturation and normalization provide support for key arithmetic operations
• Field manipulation and instruction extract, set, clear, and bit counting support a common operation
found in control and data manipulation applications
The C64x+ devices include the following additional features:
• Each multiplier can perform two 16 × 16-bit or four 8 × 8-bit multiplies every clock cycle
• Quad 8-bit and dual 16-bit instruction set extensions with data flow support
• Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses
• Special communication-specific instructions to address common operations in error-correcting codes
• Bit count and rotate hardware extends support for bit-level algorithms
• Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code
size
• Protected mode operation: a two-level system of privileged program execution to support higher
capability operating systems and system features, such as memory protection
• Exceptions support for error detection and program redirection to provide robust code execution
• Hardware support for modulo loop operation to reduce code size
• Industry's first assembly optimizer for rapid development and improved parallelization
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Memory Controllers
The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory
(L1D memory). Figure 2 shows a diagram of the memory architecture. L1P and L1D are configurable as
part L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to the
CPU without stalls. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chip
memory) and L2 cache for caching external memory locations.
The following controllers manage RAM/cache configuration and cache data paths:
• Program memory controller (PMC)
• Data memory controller (DMC)
• Unified memory controller (UMC)
• External memory controller (EMC)
The Internal Direct Memory Access Controller (IDMA) manages DMA among the L1P, L1D, and L2
memories.
This section briefly describes the cache and DMA controllers. For detailed information about each of these
controllers, see the TMS320C6000 DSP Cache User’s Guide (SPRU656) and the TMS320C64x+
Megamodule Reference Guide (SPRU871).
Note:
2.2.1
The C64x+ Megamodule includes the memory controllers; however, the physical L1P, L1D,
and L2 memories are not part of the megamodule. Thus, they are described separately
because the C64x+ Megamodule supports a variety of memory configurations. Refer to
Section 3 for more information on the L1P, L1D, and L2 memory configuration specific to the
DM644x DMSoC.
Program Memory Controller (PMC)
The program memory controller (PMC) is the hardware interface between level 1 program memory (L1P
memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, UMC, and
EMC). The PMC responds to instruction fetch requests from the C64x+ CPU and manages transfer
operations between L1P memory and the UMC and between L1P memory and the EMC.
The DM644x DMSoC does not support the PMC memory protection feature of the standard C64x+
Megamodule.
Refer to the TMS320C6000 DSP Cache User’s Guide (SPRU656) and to the program memory controller
section of the TMS320C64x+ Megamodule Reference Guide (SPRU871) for more information on the PMC
and for a description of its control registers.
2.2.2
Data Memory Controller (DMC)
The data memory controller (DMC) is the hardware interface between level 1 data memory (L1D memory)
and the other components in the C64x+ Megamodule (for example, C64x+ CPU, UMC, and EMC). The
DMC responds to data requests from the C64x+ CPU and manages transfer operations between L1D
memory and the UMC and between L1D memory and the EMC.
L1D memory includes 64 KB of RAM in the DM644x DMSoC. The DMC has a register interface that
allows you to configure part of the L1D RAM as normal data RAM or as cache. You can configure cache
sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 64 KB of RAM. The DM644x DMSoC does not support
the DMC memory protection features of the standard C64x+ Megamodule.
Refer to the TMS320C6000 DSP Cache User’s Guide (SPRU656) and to the data memory controller
(DMC) section of the TMS320C64x+ Megamodule Reference Guide (SPRU871) for more information on
the DMC and for a description of its control registers.
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TMS320C64x+ Megamodule
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Figure 2. C64x+ Cache Memory Architecture
C64x+ CPU
Data Path
256 bit
Fetch Path
L1D
SRAM
L1P
Cache
L1D
Cache
Write
Buffer
256 bit
256 bit
128 bit
L1 Data
L1 Program
256 bit
L1P
SRAM
2 x 64 bit
L2 Cache
L2 SRAM
128/64/32 bit
L2 Unified Data/Program Memory
External Memory
Legend:
addressable memory
cache memory
data paths managed by
cache controller
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Unified Controller (UMC)
The unified memory controller (UMC) is the hardware interface between level 2 memory (L2 memory) and
the other components in the C64x+ Megamodule (for example, PMC, DMC, and EMC). The UMC
manages transfer operations between L2 memory and the other memory controllers (PMC, DMC, and
EMC).
L2 memory includes 64 KB of RAM in the DM644x DMSoC. The UMC has a register interface that allows
you to configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of
0 KB, 4 KB, 8 KB, 16 KB, 32 KB, or 64 KB of the 64 KB of RAM.
The DM644x DMSoC does not support the UMC memory protection feature of the standard C64x+
Megamodule.
Refer to the TMS320C6000 DSP Cache User’s Guide (SPRU656) and to the program unified controller
section of the TMS320C64x+ Megamodule Reference Guide (SPRU871) for more information on the UMC
and for a description of its control registers.
2.2.4
External Memory Controller (EMC)
The external memory controller (EMC) is the hardware interface between the external memory map
(external memory and external registers) and the other controllers in the C64x+ Megamodule (for
example, PMC, DMC, and UMC). The EMC manages transfer operations between external memory and
registers and the other memory controllers (PMC, DMC, and EMC).
L2 memory includes 64 KB of RAM in the DM644x DMSoC. The UMC has a register interface that allows
you to configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of
0 KB, 4 KB, 8 KB, 16 KB, 32 KB, or 64 KB of the 64 KB of RAM.
EMC does not support the UMC memory protection feature of the standard C64x+ Megamodule.
Refer to the TMS320C6000 DSP Cache User’s Guide (SPRU656) and to the TMS320C64x+ Megamodule
Reference Guide (SPRU871) for more information on the EMC and for a description of its control
registers.
2.2.5
Internal DMA (IDMA)
The internal DMA (IDMA) controller facilitates DMA transfers between any two internal memory-mapped
locations. Internal memory-mapped locations include L1P, L1D, L2, and internal peripheral configuration
registers.
Note:
The IDMA cannot facilitate DMA to or from external memory-mapped locations. The EDMA
facilitates external DMA transfers. Refer to Section 3 and to the TMS320DM644x DMSoC
Enhanced DMA (EDMA) Controller Reference Guide (SPRUE23) for information on EDMA.
The IDMA controller enables the rapid paging of data sections to any local memory-mapped RAM. A key
advantage of the IDMA is that it allows paging between slower L2 and faster L1D data memory. These
transfers take place without CPU intervention and without cache stalls.
Another key advantage is that you can use the IDMA controller to program internal peripheral
configuration registers without CPU intervention.
Refer to the internal DMA (IDMA) controller section in the TMS320C64x+ Megamodule Reference Guide
(SPRU871) for more information on the IDMA controller and for a description of its control registers.
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2.3
Internal Peripherals
This C64x+ Megamodule includes the following internal peripherals:
• Interrupt controller (INTC)
• Power-down controller (PDC)
This section briefly describes the INTC and PDC. For more information on these peripherals, see the
TMS320C64x+ Megamodule Reference Guide (SPRU871).
2.3.1
Interrupt Controller (INTC)
The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps DSP device events to 12 CPU interrupts. All DSP device events are listed in Table 1. Shaded
entries are standard C64x+ megamodule interrupt events. The interrupt controller section of the
TMS320C64x+ Megamodule Reference Guide (SPRU871) fully describes the INTC.
Table 1. DSP Interrupt Map
EVT
Abbreviation
Source
EVT
Abbreviation
Source
0
EVT0
DSP – Interrupt Control
48
MBXINT0
ASP
1
EVT1
DSP – Interrupt Control
49
MBRINT0
ASP
2
EVT2
DSP – Interrupt Control
96
INTERR
DSP – INT CTL
3
EVT3
DSP – Interrupt Control
97
EMC_IDMAERR DSP – EMC
4
TINT0
Timer 0 – TINT12
98
PBISTINT
PBIST
5
TINT1
Timer 0 – TINT34
100
EFIINTA
DSP – EFI A
6
TINT2
Timer 1 – TINT12
101
EFIITNB
DSP – EFI B
7
TINT3
Timer 1 – TINT34
112
PMC_ED
DSP – PMC
9
EMU_DTDMA
DSP – ECM
116
UMC_ED1
DSP – UMC
11
EMU_RTDXRX
DSP – RTDX
117
UMC_ED2
DSP – UMC
12
EMU_RTDXTX
DSP – RTDX
118
PDC_ERR
DSP – PDC
13
IDMAINT0
DSP – EMC
119
PVC_INT
DSP – PDC
14
IDMAINT1
DSP – EMC
120
PMC-CMPA
DSP – PMC
16
ARM2DSP0
ARM
121
PMC-DMPA
DSP – PMC
17
ARM2DSP1
ARM
122
DMC-CMPA
DSP – DMC
18
ARM2DSP2
ARM
123
DMC-DMPA
DSP – DMC
19
ARM2DSP3
ARM
124
UMC-CMPA
DSP – UMC
20
DSQINT
VICP – SEQ (DSP int)
125
UMC-DMPA
DSP – UMC
21
IMXINT
VICP – IMX
126
EMC-CMPA
DSP – EMC
22
VLCDINT
VICP – VLCD
127
EMC-DMPA
DSP – EMC
36
CCINT1
Region 1 CC Interrupt
37
CCERRINT
CC Error
38
TCERRINT0
TC0 Error
39
TCERRINT1
TC1 Error
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Power-Down Controller (PDC)
The C64x+ Megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C64x+ Megamodule and internal memories of the DSP subsystem:
• C64x+ CPU
• Program memory controller (PMC)
• Data memory controller (DMC)
• Unified memory controller (UMC)
• Extended memory controller (EMC)
• Internal Direct Memory Access controller (IDMA)
• L1P memory
• L1D memory
• L2 memory
The C64x Megamodule is capable of providing both dynamic and static power-down; however, only static
power-down in supported on the DM644x DMSoC. The TMS320C64x+ Megamodule Reference Guide
(SPRU871) describes the power-down control in more detail.
• Static power-down: The PDC initiates power down of the entire C64x+ Megamodule and all internal
memories immediately upon command from software.
Static power-down affects all components of the C64x+ Megamodule and all internal memories. Software
can initiate static power-down via a register bit in the PDC register. For more information on the PDC, see
the TMS320C64x+ Megamodule Reference Guide (SPRU871).
Note:
2.3.3
The DM644x DMSoC does not support dynamic power-down.
Bandwidth Manager
The bandwidth manager provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA-initiated DMA transfers (and resulting coherency operations)
• IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Configuration bus
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
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Memory Map
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The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA, IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The programmable priority
level has a single meaning throughout the system. There are a total of nine priority levels, where priority
zero is the highest priority and priority eight is the lowest priority. When requests for a single resource
contend, access is granted to the highest-priority requestor. When the contention occurs for multiple
successive cycles, a contention counter assures that the lower-priority requestor gets access to the
resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1 represents a
transfer whose priority has been increased due to expiration of the contention counter or a transfer that is
fixed as the highest-priority transfer to a given resource.
3
Memory Map
Refer to your device-specific data manual for memory-map information.
3.1
DSP Internal Memory (L1P, L1D, L2)
This section describes the configuration of the DSP internal memory in the DM644x DMSoC that consists
of L1P, L1D, and L2. In the DM644x DMSoC:
• L1P memory includes 32 KB of RAM. The PMC allows you to configure part or all of the L1P RAM as
normal program RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or
32 KB of the 32 KB of RAM.
• L1D memory includes 80 KB of RAM. The DMC allows you to configure part of the L1D RAM as
normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of
the 80 KB of RAM.
• L2 memory includes 64 KB of RAM. The UMC allows you to configure part or all of the L2 RAM as
normal RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, 32 KB, or 64 KB
of the 64 KB of RAM.
3.2
External Memory
Devices connected to the DDR2 port and to the asynchronous EMIF are accessible to the DSP. Making
the devices accessible to the DSP allows the DSP to access program memory and data memory from
DDR2 on the DDR2 port and from devices attached to the asynchronous EMIF, such as NOR FLASH or
SRAM. The EMC facilitates DSP access to these memories in the C64x+ Megamodule. The following
external memories are accessible to the DSP:
• DDR2 port (8000:0000h–8FFF:FFFFh)
• Asynchronous EMIF (for example, NOR and NAND FLASH in 4 EM_CE regions)
Note:
The DSP has access to the data space of the DDR2 port and asynchronous EMIF, but the
DSP does not have access to the control registers of these EMIF controllers. The ARM is
responsible for configuring the control registers of the DDR2 port and the asynchronous
EMIF in the DM644x system. Refer to the TMS320DM644x DMSoC ARM Subsystem
Reference Guide (SPRUE14) for more information on how the ARM configures the DDR2
port and the asynchronous EMIF.
Table 2. External Memory Table
Address
Accessibility
Region
Start
End
Size
ARM
DSP
EDMA
ASYNC EMIF Data (EM_CS2)
200 0000h
3FF FFFFh
32M
√
√
√
ASYNC EMIF Data (EM_CS3)
400 0000h
5FF FFFFh
32M
√
√
√
ASYNC EMIF Data (EM_CS4)
600 0000h
7FF FFFFh
32M
√
√
√
ASYNC EMIF Data (EM_CS5)
800 0000h
9FF FFFFh
32M
√
√
√
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ARM Internal Memory
ARM internal memory is accessible to the DSP and includes 16 KB of ARM internal RAM and 8 KB of
ARM internal ROM.
Note:
3.4
ARM internal memory is external to the C64x+ Megamodule. The EMC facilitates DSP
access to ARM internal memory in C64x+ Megamodule for the DDR2 port and for
asynchronous EMIF. Refer to the memory mapping section in the TMS320DM644x DMSoC
ARM Subsystem Reference Guide (SPRUE14) for more information on the ARM’s internal
memory.
Internal Peripherals
The following internal peripherals are accessible to the DSP:
• Power-down controller (PDC)
• Interrupt controller
For more information on the internal peripherals, see the TMS320C64x+ Megamodule Reference Guide
(SPRU871).
3.5
Device Peripherals
The following device peripherals (external to the C64x+ DSP megamodule) are accessible to the DSP:
• ASP (audio serial port)
• EDMA (enhanced direct memory access)
Note:
The ASP and EDMA peripherals are not in the DSP internal memory-map because these
peripherals are not part of the standard C64x+ Megamodule, by design. Hence, such
peripherals are occasionally described as external peripherals, with respect to the C64x+
Megamodule.
Refer to the TMS320DM644x DMSoC Peripherals Overview Reference Guide (SPRUE19) for more
information on these peripherals.
4
ARM–DSP Integration
See the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14) for complete information
on ARM–DSP integration.
The DM644x DMSoC integrates an ARM core for overall system control functions and a DSP subsystem
for complex data and image/ video processing functions. In the system, the ARM is typically responsible
for managing DSP boot, DSP power-on/off, DSP clock enable/disable, DSP reset, DDR2 port initialization,
and asynchronous EMIF initialization. The DM644x DMSoC includes the following features associated with
ARM–DSP integration:
• Shared peripherals:
– ARM and DSP have access to EDMA
– ARM and DSP have access to ASP
– ARM and DSP have access to Timer 0 and Timer 1
• Shared memory:
– ARM can access DSP internal memory
– DSP can access ARM internal memory
– ARM and DSP can access DDR2 port and asynchronous EMIF
16
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ARM–DSP Integration
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•
ARM–DSP interrupts:
– ARM can interrupt the DSP (via four general interrupts and one NMI)
– DSP can interrupt the ARM (via two general interrupts)
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TMS320DM644x DMSoC DSP Subsystem
17
DSP Subsystem Clock
•
–
–
–
–
5
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As system master, the ARM may manage the following DSP functions:
Boot the DSP
DSP power management
Enable/disable the DSP clock
Reset the DSP
DSP Subsystem Clock
See the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14) for complete information
on DSP subsystem clocking.
PLL1 drives the DSP subsystem. The clock at device pin MXI drives the DSP in PLL bypass mode. Refer
to the device-specific data manual for more information on supported clock speeds. The ARM controls
turning the DSP clock on/off.
6
Power Management
See the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14) for complete information
on DSP subsystem power management.
• DSP clock can be completely shut off
• C64x Megamodule can be put in sleep mode (refer to Section 2.3.2)
– C64x+ CPU can be put in sleep mode
– DSP internal memories (L1P, L1D, L2) can be statically put in sleep mode
7
Boot and Reset
The DSP can boot in either ARM boots DSP mode or DSP self-boot mode.
The ARM is responsible for managing DSP boot after power-on/reset in the ARM boots DSP mode. The
DSP boots without intervention from the ARM immediately upon power-on/reset in DSP self-boot mode.
The mode is determined by sampling the COUT3_BTSEL pin at power-on/reset (See Table 3). Refer to
the boot and reset section and to the ARM–DSP integration section of the TMS320DM644x DMSoC ARM
Subsystem Reference Guide (SPRUE14) for more information on boot and reset modes.
Table 3. DSP Boot Configuration
Device Configuration
Function
Sampled Pin
Default Setting
DSP Boot
0 = ARM Boots DSP
COUT3_BTSEL
ARM Boots DSP
1 = DSP Self-Boots
18
TMS320DM644x DMSoC DSP Subsystem
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