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Texas Instruments TMS320C6000 DSP 32-bit Timer Reference (Rev. B) User guides
TMS320C6000 DSP 32-Bit Timer
Reference Guide
Literature Number: SPRU582B
July 2003 – Revised January 2005
2
SPRU582B – July 2003 – Revised January 2005
Contents
Preface ............................................................................................................................... 5
1
Overview ................................................................................................................... 7
2
Resetting the Timers and Enabling Counting ................................................................. 9
3
Timer Counting .......................................................................................................... 9
4
Timer Clock Source Selection ...................................................................................... 9
5
Timer Pulse Generation .............................................................................................. 9
6
Boundary Conditions in the Control Registers ............................................................. 11
7
Timer Interrupts ....................................................................................................... 11
8
Timer Pins as General-Purpose Input/Output ............................................................... 11
9
Emulation Operation ................................................................................................. 11
10
Timer Registers ........................................................................................................ 12
................................................................................... 12
................................................................................... 14
10.3 Timer Count Register (CNT) .................................................................................... 15
Appendix A Revision History ............................................................................................. 17
10.1
Timer Control Register (CTL)
10.2
Timer Period Register (PRD)
List of Figures
1
2
3
4
5
6
7
Timer Block Diagram ........................................................................................................ 8
Timer Operation in Pulse Mode (CP = 0) ............................................................................... 10
Timer Operation in Clock Mode (CP = 1) ............................................................................... 10
TMS320C62x/C67x Timer Control Register (CTL) .................................................................... 12
TMS320C64x Timer Control Register (CTL) ........................................................................... 12
Timer Period Register (PRD) ............................................................................................. 14
Timer Count Register (CNT) ............................................................................................. 15
List of Tables
1
2
3
4
5
6
7
A-1
Differences in TMS320C6000 DSP Timers .............................................................................. 7
Timer Operation Using GO and HLD Bits ................................................................................ 9
TSTAT Parameters in Pulse and Clock Modes ....................................................................... 10
Timer Registers ............................................................................................................. 12
Timer Control Register (CTL) Field Descriptions ...................................................................... 13
Timer Period Register (PRD) Field Descriptions ....................................................................... 14
Timer Count Register (CNT) Field Descriptions........................................................................ 15
Document Revision History .............................................................................................. 17
SPRU582B – July 2003 – Revised January 2005
Table of Contents
3
4
List of Tables
SPRU582B – July 2003 – Revised January 2005
Read This First
SPRU582B – July 2003 – Revised January 2005
Preface
About This Manual
This document describes the 32-bit timer in the digital signal processors (DSPs) of the TMS320C6000™
DSP family.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
TMS320C6000™ CPU architecture, instruction set, pipeline, and interrupts for these digital signal
processors.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) describes
the peripherals available on the TMS320C6000™ DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x™
and TMS320C67x™ DSPs, development tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the TMS320C64x™ DSP and
discusses the application areas that are enhanced by the TMS320C64x VelociTI™.
TMS320C6000 Programmer's Guide (literature number SPRU198) describes ways to optimize C and
assembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial(literature number SPRU301) introduces the Code
Composer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature number
SPRU321) describes the Code Composer Studio™ application programming interface (API), which allows
you to program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer's Reference (literature number SPRU273)
describes the contents of the TMS320C6000™ peripheral support library of functions and macros. It lists
functions and macros both by header file and alphabetically, provides a complete description of each, and
gives code examples to show how they are used.
SPRU582B – July 2003 – Revised January 2005
Preface
5
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Related Documentation From Texas Instruments
TMS320C6000 Chip Support Libraty API Reference Guide(literature number SPRU401) describes a set
of application programming interfaces (APIs) used to configure and control the on-chip peripherals.
Trademarks
C6000, TMS320C6000, TMS320C62x, TMS320C67x, TMS320C64x, VelociTI, Code Composer Studio are
trademarks of Texas Instruments.
6
Preface
SPRU582B – July 2003 – Revised January 2005
SPRU582B – July 2003 – Revised January 2005
32-Bit Timer
This document describes the 32-bit timer in the digital signal processors (DSPs) of the
TMS320C6000™ DSP family.
1
Overview
The C6000™ DSP device has 32-bit general-purpose timers that can be used to:
• Time events
• Count events
• Generate pulses
• Interrupt the CPU
• Send synchronization events to the DMA
The timers have two signaling modes and can be clocked by an internal or an external source. The timers
have an input pin and an output pin. The input and output pins (TINP and TOUT) can function as timer
clock input and clock output. They can also be respectively configured for general-purpose input and
output.
With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or
it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count
external events and interrupt the CPU after a specified number of events. Table 1 summarizes the
differences between the C6000 timers. Figure 1 shows a block diagram of the timers.
Table 1. Differences in TMS320C6000 DSP Timers
Features
C620x/C670x DSP
C621x/C671x DSP
C64x DSP
Emulation halt support
Yes
No
Yes
Internal timer input clock source frequency
CPU rate/4
CPU rate/4
CPU rate/8
SPRU582B – July 2003 – Revised January 2005
32-Bit Timer
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Overview
Figure 1. Timer Block Diagram
Peripheral Bus to CPU and DMA
HLD
Count
enable
0
Count
zero
Equals comparator
CLKSRC
CP
Pulse generator
PWID
DATOUT
TINP pin
A
8
TSTAT, timer output TINT, timer
interrupt to CPU and DMA
INVOUT
INVINP
Synchronizer
HLD
Timer period
register
Internal clock
source(A)
DATIN
GO
Timer count
register
Edge detect
1
0
1
FUNC
TOUT pin
C62x/C67x DSP uses CPU/4 clock as the internal clock source to the timer. C64x DSP uses CPU/8 clock as the
internal clock source to the timer.
32-Bit Timer
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Resetting the Timers and Enabling Counting
2
Resetting the Timers and Enabling Counting
Table 2 describes how using the GO and HLD bits in the timer control register (CTL) enable basic features
of timer operation.
Table 2. Timer Operation Using GO and HLD Bits
Operation
GO
HLD
Description
Holding the timer
0
0
Counting is disabled.
Restarting the timer after hold
0
1
Timer continues from the value before hold. The timer counter is
not reset.
Reserved
1
0
Undefined.
Starting the timer
1
1
Timer counter resets to 0 and starts counting whenever enabled.
Once set, GO self-clears.
Configuring a timer requires four basic steps:
1. If the timer is not currently in the hold state, place the timer in hold (HLD = 0). Note that after device
reset, the timer is already in the hold state.
2. Write the desired value to the timer period register (PRD).
3. Write the desired value to the timer control register (CTL). Do not change the GO and HLD bits in CTL.
4. Start the timer by setting the GO and HLD bits in CTL to 1.
3
Timer Counting
The timer counter runs at the CPU clock rate. However, counting is enabled on the low-to-high transition
of the timer count enable source. This transition is detected by the edge-detect circuit shown in Figure 1.
Each time an active transition is detected, one CPU-clock-wide clock enable pulse is generated. This
makes the counter appear as if it were getting clocked by the count enable source. Thus, this count
enable source is referred to as the timer input clock source.
Once the timer reaches a value equal to the value in the timer period register (PRD), the timer is reset to 0
on the next CPU clock. Thus, the counter counts from 0 to N. Consider the case where the period is 2 and
the CPU clock/4 is selected as the timer clock source (CLKSRC = 1) for C62x/C67x DSP. Once started,
the timer counts the following sequence: 0, 0, 0, 0, 1, 1, 1, 1, 2, 0, 0, 0, 1, 1, 1, 1, 2, 0, 0, 0…. Note that
although the counter counts from 0 to 2, the period is 8 (2 × 4) CPU clock cycles rather than 12 (3 × 4)
CPU clock cycles. Thus, the countdown period is the value of TIMER PERIOD, not TIMER PERIOD + 1.
4
Timer Clock Source Selection
Low-to-high transitions (or high-to-low transitions, if INVINP = 1) of the timer input clock allow the timer
counter to increment. Two sources are available to drive the timer input clock:
• The input value on the TINP pin, selected by CLKSRC = 0. This signal is synchronized to prevent any
metastability caused by asynchronous external inputs. The value present on the TINP pin is reflected
by DATIN.
• Internal clock source, selected by CLKSRC = 1. The C62x/C67x DSPs use CPU clock/4 as an internal
clock source. The C64x DSPs use CPU clock/8 as an internal clock source.
5
Timer Pulse Generation
The two basic pulse generation modes are pulse mode ( Figure 2) and clock mode ( Figure 3). You can
select the mode with the CP bit in the timer control register (CTL). Note that in pulse mode, PWID in the
CTL can set the pulse width to either one or two input clock periods. The purpose of this feature is to
provide minimum pulse widths if TSTAT drives the TOUT output. TSTAT drives this pin when TOUT is
used as a timer pin (FUNC = 1), and may be inverted by setting INVOUT = 1. Table 3 gives equations for
various TSTAT timing parameters in pulse and clock modes.
SPRU582B – July 2003 – Revised January 2005
32-Bit Timer
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Timer Pulse Generation
Figure 2. Timer Operation in Pulse Mode (CP = 0)
1 × timer clock source period (PWID = 0)
2 × timer clock source period (PWID = 1)
TSTAT, TINT
Period Register f(timer input clock)
Timer counter = timer period, TINT timer interrupt period
Figure 3. Timer Operation in Clock Mode (CP = 1)
Timer clock source period
Period
TSTAT, TINT
timer counter = timer period
TINT timer interrupt period
2 × Period Register f(timer input clock)
Table 3. TSTAT Parameters in Pulse and Clock Modes
Mode
Pulse
Clock
10
Frequency
Period
Width High
Width Low
f (clock source)
timer period register
(PWID + 1)
timer period register - (PWID + 1)
timer period register
f (clock source)
f (clock source)
f (clock source)
f (clock source)
2 * timer period register
timer period register
timer period register
2 * timer period register
f (clock source)
f (clock source)
f (clock source)
32-Bit Timer
SPRU582B – July 2003 – Revised January 2005
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Boundary Conditions in the Control Registers
6
Boundary Conditions in the Control Registers
The following boundary conditions affect timer operation:
1. Timer period (PRD) and timer count (CNT) value is 0: After device reset and before the timer starts
counting, TSTAT is held at 0. After the timer starts running by setting HLD = 1 and GO = 1 while the
period and counter registers are 0, the operation of the timer depends on the CP mode selected. In
pulse mode, TSTAT = 1 regardless of whether or not the timer is held. In clock mode, when the timer
is held (HLD = 0), TSTAT keeps its previous value and when HLD = 1, TSTAT toggles with a
frequency of 1/2 of the CPU clock frequency. Note that in clock mode interrupts occur at twice the PRD
period, except for the first interrupt. The first interrupt generated occurs after one PRD clock period
only, and subsequent interrupts are generated every two PRD clock periods.
2. Counter overflow: When the timer count register (CNT) is set to a value greater than the value of the
timer period register (PRD), the counter reaches its maximum value (FFFF FFFFh), rolls over to 0, and
continues.
3. Writing to registers of an active timer: Writes from the peripheral bus override register updates to CNT
and new status updates to the timer control register (CTL).
4. Small timer period values in pulse mode: Note that small periods in pulse mode can cause TSTAT to
remain high. This condition occurs when TIMER PERIOD ≤ PWID + 1.
7
Timer Interrupts
The TSTAT signal directly drives the CPU interrupt, as well as a DMA synchronization event. The
frequency of the interrupt is the same as the frequency of TSTAT.
8
Timer Pins as General-Purpose Input/Output
Upon device reset, the timer pins TINP and TOUT are general-purpose input and output (I/O) pins,
respectively. By configuring the timer control register (CTL), the TINP and TOUT pins can operate as
general-purpose pins even when the timer is running.
The TINP pin is always a general-purpose input pin, if the timer is not running. If the timer is running, the
TINP pin is a general-purpose input pin if CLKSRC = 1 in CTL, which indicates that an internal clock
source is used instead of the TINP pin. When TINP is a general-purpose input pin, the input value is
readable from the DATIN bit in CTL.
The TOUT pin is a general-purpose output pin if FUNC = 0 in CTL, independent of timer operation. The
FUNC bit, as shown in Figure 1, selects either the DATOUT or the TSTAT value to be driven on the TOUT
pin.
9
Emulation Operation
During debug using the emulator, the CPU may be halted on an execute packet boundary for single
stepping, benchmarking, profiling, or other debug uses. For C620x/C670x DSP, during an emulation halt
the timer halts when the CPU clock/4 is selected as the clock source (CLKSRC = 1). For C64x DSP,
during an emulation halt the timer halts when the CPU clock/8 is selected as the clock source (CLKSRC =
1). Here, the counter is only enabled to count during those cycles when the CPU is not stalled due to the
emulation halt. Thus, counting is reenabled during single-step operation. If CLKSRC = 0, the timer
continues counting as programmed. For C621x/C671x DSP, the timer continues counting during emulation
halt regardless of clock source.
SPRU582B – July 2003 – Revised January 2005
32-Bit Timer
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Timer Registers
10
Timer Registers
Table 4 describes the three registers that configure timer operation.
Table 4. Timer Registers
10.1
Acronym
Register Name
CTL
Timer Control Register
Section 10.1
Section
PRD
Timer Period Register
Section 10.2
CNT
Timer Count Register
Section 10.3
Timer Control Register (CTL)
The timer control register (CTL) determines the operating mode of the timer, monitors the timer status,
and controls the function of the TOUT pin. The timer control register is shown in Figure 4, for the
C62x/C67x DSP, and in Figure 5, for the C64x DSP, and described in Table 5.
Figure 4. TMS320C62x/C67x Timer Control Register (CTL)
31
16
Reserved
R-0
15
12
11
10
9
8
Reserved
TSTAT
INVINP
CLKSRC
CP
R-0
R-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
HLD
GO
Reserved
PWID
DATIN
DATOUT
INVOUT
FUNC
R/W-0
R/W-0
R-0
R/W-0
R-x
R/W-0
R/W-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Figure 5. TMS320C64x Timer Control Register (CTL)
31
16
Reserved
R-0
15
14
12
11
10
9
8
SPND
Reserved
TSTAT
INVINP
CLKSRC
CP
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
HLD
GO
Reserved
PWID
DATIN
DATOUT
INVOUT
FUNC
R/W-0
R/W-0
R-0
R/W-0
R-x
R/W-0
R/W-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
12
32-Bit Timer
SPRU582B – July 2003 – Revised January 2005
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Timer Registers
Table 5. Timer Control Register (CTL) Field Descriptions
Bit
(1)
31-16
Reserved
15
SPND (2)
14-12
11
10
9
8
7
6
Reserved
(1)
-
Value
0
Timer continues counting during an emulation halt.
1
Timer stops counting during an emulation halt.
-
0
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
0
0
1
1
NO
0
Noninverted TINP drives timer.
YES
1
Inverted TINP drives timer.
EXTERNAL
0
External clock source drives the TINP pin.
CUPOVR4
1
Internal clock source.
For C62x/C67x DSP: CPU clock/4
For C64x DSP: CPU clock/8
PULSE
0
Pulse mode. TSTAT is active one CPU clock after the timer reaches the
timer period. PWID determines when it goes inactive.
CLOCK
1
Clock mode. TSTAT has a 50% duty cycle with each high and low period
one countdown period wide.
Timer status bit. Value of timer output.
TINP inverter control bit. Only affects operation if CLKSRC = 0.
Timer input clock source bit.
CP
Clock/pulse mode enable bit.
HLD
Hold bit. Counter may be read or written regardless of HLD value.
YES
0
Counter is disabled and held in the current state.
NO
1
Counter is allowed to count.
GO
PWID
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
0
CLKSRC
4
Description
Suspend mode bit. Stops timer from counting during an emulation halt. Only
affects operation if the clock source is internal, CLKSRC = 1. Reads always
return a 0.
INVINP
Reserved
2
symval
TSTAT
5
3
(1)
(2)
field
GO bit. Resets and starts the timer counter.
NO
0
No effect on the timers.
YES
1
If HLD = 1, the counter register is zeroed and begins counting on the next
clock.
-
0
Reserved. The reserved bit location is always read as 0. A value written to
this field has no effect.
ONE
0
TSTAT goes inactive one timer input clock cycle after the timer counter
value equals the timer period value.
TWO
1
TSTAT goes inactive two timer input clock cycles after the timer counter
value equals the timer period value.
Pulse width bit. Only used in pulse mode (CP = 0).
DATIN
Data in bit. Value on TINP pin.
0
0
Value on TINP pin is logic low.
1
1
Value on TINP pin is logic high.
DATOUT
Data output bit.
0
0
DATOUT is driven on TOUT.
1
1
TSTAT is driven on TOUT after inversion by INVOUT.
For CSL implementation, use the notation TIMER_CTL_field_symval
For C620x/C670x/C64x DSPs ; for C621x/C671x DSP, this bit is reserved.
SPRU582B – July 2003 – Revised January 2005
32-Bit Timer
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Timer Registers
Table 5. Timer Control Register (CTL) Field Descriptions (continued)
Bit
1
0
10.2
field
(1)
symval
(1)
Value
INVOUT
Description
TOUT inverter control bit (used only if FUNC = 1).
NO
0
Noninverted TSTAT drives TOUT.
YES
1
Inverted TSTAT drives TOUT.
FUNC
Function of TOUT pin.
GPIO
0
TOUT is a general-purpose output pin.
TOUT
1
TOUT is a timer output pin.
Timer Period Register (PRD)
The timer period register (PRD) contains the number of timer input clock cycles to count. This number
controls the TSTAT signal frequency. The timer period register is shown in Figure 6 and described in
Table 6.
Figure 6. Timer Period Register (PRD)
31
0
Timer Period (PRD)
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 6. Timer Period Register (PRD) Field Descriptions
(1)
14
(1)
Bit
Field
symval
31-0
PRD
OF(value)
Value
0-FFFF FFFFh
Description
Period bits. This 32-bit value is the number of timer input clock cycles to
count and is used to reload the timer count register (CNT). This number
controls the frequency of the timer output status bit (TSTAT).
For CSL implementation, use the notation TIMER_PRD_PRD_symval
32-Bit Timer
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Timer Registers
10.3
Timer Count Register (CNT)
The timer count register (CNT) contains the current value of the incrementing counter The timer count
register increments by 1 when it is enabled to count and resets to 0 on the next CPU clock after the value
in the timer period register (PRD) is reached. The timer count register is shown in Figure 7 and described
in Table 7.
Figure 7. Timer Count Register (CNT)
31
0
Timer Count (CNT)
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 7. Timer Count Register (CNT) Field Descriptions
(1)
(1)
Bit
Field
symval
31-0
CNT
OF(value)
Value
0-FFFF FFFFh
Description
Main count bits. This 32-bit value is the current count of the main
counter. This value is incremented by 1 every input clock cycle.
For CSL implementation, use the notation TIMER_CNT_CNT_symval
SPRU582B – July 2003 – Revised January 2005
32-Bit Timer
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Timer Registers
16
32-Bit Timer
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Appendix A
Appendix A Revision History
Table A-1 lists the changes made since the previous version of this document.
Table A-1. Document Revision History
Page
Table 1
Additions/Modifications/Deletions
Changed the emulation halt support feature from No to Yes under the C64x DSP column of Table 1.
Section 6
Changed number 1 of Section 6 .
Figure 1
Changed Figure 1.
Section 9
Changed Section 9.
Table 5
Changed the second footnote of Table 5.
SPRU582B – July 2003 – Revised January 2005
Revision History
17
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Appendix A
Index
time events 3
count events 3
generate pulses 3
send synchronization events to the
DMA 3
interrupt the CPU 3
overview 3
timer 3
overview 3
timer 3
resetting 3
timer 3
enabling counting 3
enabling counting 3
resetting the timer 3
timer 3
counting 3
counting 3
clock source selection 3
timer 3
clock source selection 3
selection of clock sources 3
timer 3
pulse generation 3
pulse generation 3
timer 3
register boundary conditions 3
control register boundary conditions
3
registers 3
boundary conditions 3
timer 3
interrupts 3
interrupts 3
timer 3
general-purpose input/output 3
general-purpose input/output 3
timer 3
emulation operation 3
emulation operation 3
timer 3
registers 3
registers 3
timer 3
registers 3
timer control register (CTL) 3
timer control register (CTL) 3
CTL 3
registers 3
timer period register (PRD) 3
timer period register (PRD) 3
PRD 3
registers 3
18
Revision History
timer count register (CNT) 3
timer count register (CNT) 3
CNT 3
TSTAT bit 3
INVINP bit 3
CLKSRC bit 3
CP bit 3
HLD bit 3
GO bit 3
PWID bit 3
DATIN bit 3
DATOUT bit 3
INVOUT bit 3
FUNC bit 3
SPND bit 3
CNT bits 3
modes 3
pulse and clock 3
TSTAT parameters 3
notational conventions 5
related documentation from Texas Instruments 5
trademarks 6
related documentation from Texas Instruments 6
time events 7
count events 7
generate pulses 7
send synchronization events to the
DMA 7
interrupt the CPU 7
overview 7
timer 7
overview 7
time events 8
count events 8
generate pulses 8
send synchronization events to the
DMA 8
interrupt the CPU 8
overview 8
timer 8
overview 8
timer 9
resetting 9
timer 9
enabling counting 9
enabling counting 9
resetting the timer 9
timer 9
counting 9
counting 9
clock source selection 9
timer 9
clock source selection 9
selection of clock sources 9
timer 9
pulse generation 9
pulse generation 9
timer 9
resetting 9
timer 9
enabling counting 9
enabling counting 9
resetting the timer 9
modes 10
pulse and clock 10
TSTAT parameters 10
timer 10
pulse generation 10
pulse generation 10
timer 11
register boundary conditions 11
control register boundary conditions
11
registers 11
boundary conditions 11
timer 11
interrupts 11
interrupts 11
timer 11
general-purpose input/output 11
general-purpose input/output 11
timer 11
emulation operation 11
emulation operation 11
timer 11
register boundary conditions 11
control register boundary conditions
11
registers 11
boundary conditions 11
timer 12
registers 12
registers 12
timer 12
registers 12
timer control register (CTL) 12
timer control register (CTL) 12
CTL 12
TSTAT bit 12
INVINP bit 12
CLKSRC bit 12
CP bit 12
HLD bit 12
GO bit 12
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Appendix A
PWID bit 12
DATIN bit 12
DATOUT bit 12
INVOUT bit 12
FUNC bit 12
SPND bit 12
timer 12
registers 12
registers 12
timer 12
timer 13
registers 13
SPRU582B – July 2003 – Revised January 2005
registers 13
timer 13
registers 14
timer period register (PRD) 14
timer period register (PRD) 14
PRD 14
timer 14
registers 14
registers 14
timer 14
registers 15
timer count register (CNT) 15
timer count register (CNT) 15
CNT 15
CNT bits 15
timer 15
registers 15
registers 15
timer 15
timer 16
registers 16
registers 16
timer 16
Revision History
19
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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in which TI products or services are used. Information published by TI regarding third-party products or services
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2005, Texas Instruments Incorporated
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