Texas Instruments | TMP63 100-kΩ Linear Thermistor With 0402 Package Option (Rev. A) | Datasheet | Texas Instruments TMP63 100-kΩ Linear Thermistor With 0402 Package Option (Rev. A) Datasheet

Texas Instruments TMP63 100-kΩ Linear Thermistor With 0402 Package Option (Rev. A) Datasheet
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TMP63
SNIS211A – OCTOBER 2019 – REVISED DECEMBER 2019
TMP63 100-kΩ Linear Thermistor With 0402 Package Option
1 Features
3 Description
•
The TMP63 series of linear thermistors exhibit a large
change in resistance with temperature.
1
•
•
•
•
•
•
•
Silicon-based thermistor with a
Positive Temperature Coefficient (PTC)
Linear resistance change across temperature
100-kΩ nominal resistance at 25°C (R25)
– ±1% maximum (0°C to 70°C)
Wide operating temperature of –40°C to +125°C
Consistent sensitivity across temperature
– 6400 ppm/°C TCR (25°C)
– 0.2% typical TCR tolerance across
temperature range
Fast thermal response time of 0.6 s (DEC)
Long lifetime and robust performance
– Built-in fail-safe in case of short-circuit failures
– <1% maximum long term sensor drift
Available package options:
– X1SON (DEC/0402 footprint)
2 Applications
•
•
•
Its linearity and consistent sensitivity across
temperature enable simple and accurate methods for
temperature conversion. Low power consumption and
a small thermal mass minimize the impact of selfheating. The built-in failsafe behavior at high
temperatures and powerful immunity to environmental
variation of these devices is designed for a long
lifetime of high performance. The small size of the
TMP63 series allows for close placement to heat
sources and quick response times.
Take advantage of benefits over NTC thermistors
such as no extra linearization circuitry, minimized
calibration, less resistance tolerance variation, larger
sensitivity at high temperatures, and simplified
conversion methods to save time and memory in the
processor.
The TMP63 series is currently available in a 0402
footprint-compatible X1SON package.
For complete resistance vs temperature table (R-T
table) computation and helpful methods to derive
temperature, see the Thermistor Design Tool.
Temperature Monitoring
– HVAC & thermostats
– Industrial control and appliances
Thermal compensation
– Display backlights
– Building automation
Thermal threshold detection
– Motor control
– Chargers
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TMP63
X1SON (2)
0.60 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Implementation Circuits
Typical Resistances vs Ambient Temperature
VBias
200
180
IBias
RBias
RTMP63
VTemp
RTMP63
VTemp
Resistance (k:)
160
140
120
100
80
60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
TMP6
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP63
SNIS211A – OCTOBER 2019 – REVISED DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 TMP63 R-T table....................................................... 9
7.4 Feature Description................................................... 9
7.5 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 10
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2019) to Revision A
•
2
Page
Changed device status from Advanced Information to Production Data ............................................................................... 1
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5 Pin Configuration and Functions
DEC Package
2-Pin X1SON
Top View (Angled)
1
2
Pin Functions
PIN
NAME
X1SON
(DEC)
–
1
+
2
TYPE
—
DESCRIPTION
Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +
terminal is at a higher voltage potential than the – terminal.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
Voltage across pins 2 (+) and 1(–)
Current through the device
UNIT
+6
V
+450
µA
Junction temperature (TJ)
–40
+150
°C
Storage temperature (Tstg)
–65
+150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM) per JESD22-A114
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VSns
Voltage across pins 2 (+) and 1 (–)
0
5.5
V
ISns
Current through the device
0
400
µA
TA
Operating free-air temperature (specified performance) (X1SON/DEC Package)
–40
125
°C
6.4 Thermal Information
TMP63
THERMAL METRIC
(1)
DEC (X1SON)
Units
2 PINS
RθJA
Junction-to-ambient thermal resistance (2) (3)
443.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
195.7
°C/W
RθJB
Junction-to-board thermal resistance
254.6
°C/W
ΨJT
Junction-to-top characterization parameter
19.9
°C/W
ΨJB
Junction-to-board characterization parameter
254.5
°C/W
RθJC(bot)
Junction-to-case (bot) thermal resistance
–
°C/W
(1)
(2)
(3)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.
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6.5 Electrical Characteristics
TA = -40°C - 125°C, ISns = 20 μA (unless otherwise noted)
PARAMETER
R25
Thermistor Resistance at 25°C
TEST CONDITIONS
TA = 25°C
RTOL
Resistance Tolerance
TA = 0°C - 70°C
TA = -40°C - 125°C
TCR-35
TCR25
Temperature Coefficient of Resistance
TCR85
TCR-35 %
TCR25 %
Temperature Coefficient of Resistance Tolerance
TCR85 %
ΔR
tRES (stirred
Sensor Long Term Drift (Reliability)
TYP
MAX
100
–1
UNIT
kΩ
1
–1
1
–1.5
1.5
T1 = -40°C, T2 = -30°C
+6220
T1 = 20°C, T2 = 30°C
+6400
T1 = 80°C, T2 = 90°C
+5910
T1 = -40°C, T2 = -30°C
±0.4
T1 = 20°C, T2 = 30°C
±0.2
T1 = 80°C, T2 = 90°C
±0.3
%
ppm/°C
%
96 hours continuous operation
RH = 85%, TA = 130°C, VBias = 5.5 V
0.1
0.8
600 hours continuous operation
TA = 150°C, VBias = 5.5 V
0.1
1
%
Thermal response to 63%
T1 = 25°C in Still Air to T2 = 125°C in Stirred
Liquid
0.6
s
Thermal response to 63%
T1 = 25°C to T2 = 70°C in Still Air
3.2
s
liquid)
tRES (still air)
MIN
TA = 25°C
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6.6 Typical Characteristics
at TA = 25°C, (unless otherwise noted)
200
200
175
180
160
Resistance (k:)
Resistance (k:)
150
125
100
75
140
120
100
80
60
50
IBIAS = 1 PA
IBIAS = 2 PA
IBIAS = 10 PA
25
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
20
0
-40
140
20
40
60
80
Temperature (qC)
100
120
140
TMP6
Figure 2. Resistance vs. Ambient Temperature Using
Multiple Bias Voltages
6500
6500
6400
6400
TCR ( ppm/qC)
TCR (ppm/qC)
0
TMP63: VBias = 1.8 V, 2.5 V, 3.3 V, and 5.0 V, RBias = 100 kΩ with
±0.01% Tolerance
Figure 1. Resistance vs. Ambient Temperature Using
Multiple Bias Currents
6300
6200
6100
6300
6200
6100
6000
0
5
10
15
20
25
Bias Current (PA)
30
35
6000
1.5
40
180
160
160
140
140
Resistance (k:)
200
180
120
100
80
60
-40 qC
25 qC
50 qC
3
3.5
Bias Voltage (V)
4
4.5
5
TMP6
Figure 4. TCR as a Function of Sense Voltages, VSns
200
20
2.5
TMP63: VSns = 1.8 V, 2.5 V, 3.3 V, and 5.0 V, RBias = 100 kΩ with
±0.01% Tolerance
Figure 3. TCR as a Function of Sense Currents ISns
40
2
TMP6
TMP1
TMP63: ISns = 1 µA, 10 µA, 20 µA, and 40 µA
120
100
80
60
40
100 qC
125 qC
-40 qC
25 qC
50 qC
20
0
100 qC
125 qC
0
0
5
10
15
20
25
30
35
Bias Current (PA)
40
45
50
0
TMP6
TMP63: TA = –40°C, 25°C, 50°C, 100°C, and 125°C
0.5
1
1.5
2 2.5 3 3.5
Bias Voltage (V)
4
4.5
5
5.5
TMP6
TMP63: TA = –40°C, 25°C, 50°C, 100°C, and 125°C, RBias = 100
kΩ with ±0.01% Tolerance
Figure 5. Supply Dependence R vs. IBias
6
-20
TMP6
TMP63: IBias = 1 µA, 10 µA, 20 µA, and 40 µA
Resistance (k:)
VBIAS = 1.8 V
VBIAS = 2.5 V
VBIAS = 3.3 V
VBIAS = 5 V
40
IBIAS = 20 PA
IBIAS = 40 PA
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Figure 6. Supply Dependence R vs. VBias
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Typical Characteristics (continued)
at TA = 25°C, (unless otherwise noted)
2.5
180
VBIAS
VSNS
160
Resistance (k:)
Output (V)
2
1.5
1
0.5
140
120
100
0
80
0
1
2
3
4
5
6 7 8
Time (Ps)
9
10 11 12 13 14
0
1
2
3
4
Time (s)
TMP1
TMP6
TMP63: VSns = 1 V
5
TMP6
TMP63: Stirred Liquid
Figure 7. Step Response
Figure 8. Thermal Response Time
130
125
Resistance (k:)
120
115
110
105
100
95
0
2
4
6
8
Time (s)
10
12
14
16
TMP6
TMP63: Still Air
Figure 9. Thermal Response Time
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7 Detailed Description
7.1 Overview
The TMP63 series of silicon linear thermistors has a linear positive temperature coefficient (PTC) that results in a
uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. To
fabricate the TMP63, a special silicon process is used where the devices key characteristics—the temperature
coefficient resistance (TCR) and nominal resistance (R25)—are controlled by the doping level and active region
area. Note that the TMP63 has an active area and a substrate due to the polarized terminals of the device. The
positive terminal should be connected to the highest potential, while the negative terminal should be connected
to the lowest potential.
The TMP63 is different from a NTC, where a NTC is a purely resistive device, the TMP63's resistance is affected
by the current across the part and will change with temperature. In a voltage divider circuit, it is recommended
that the top resistor is kept at 100 kΩ. Changing the top resistor or the VBIAS will change the resistance vs
temperature table (R-T table) of the TMP63, and subsequently the polynomials as described in Design
Requirements. Consult the TMP63 R-T table section for more information.
Equation 1 can help the user approximate the TCR.
TCR (ppm/°C) = (RT2 – RT1) / ((T2 – T1) × R(T2+T1)/2)
(1)
Below are the definitions of the key terms used throughout this document:
• ISns: Current flowing through the TMP63.
• VSns: Voltage across the two TMP63 terminals.
• IBIAS: Current supplied by the biasing circuit.
• VBIAS: Voltage supplied by the biasing circuit.
• VTEMP: Output voltage that corresponds to the measured temperature. Note that this is different from VSns. In
the use case of a voltage divider circuit with the TMP63 in the high side, VTEMP is taken across RBIAS.
7.2 Functional Block Diagram
VBias
IBias
RBias
RTMP63
VTemp
VTemp
RTMP63
Figure 10. Typical Implementation Circuits
8
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7.3 TMP63 R-T table
The TMP63 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current. TI
provides a Thermistor Design Tool to calculate the R-T table. The system designer should always validate the
calculations provided.
7.4 Feature Description
7.4.1 Linear resistance curve
The TMP63 has good linear behavior across the whole temperature range as shown in Figure 3. This allows a
simpler resistance to temperature conversion method that reduces look up table memory requirements.
Additionally the linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary
with TMP63.
Because the TMP63 is linear across the entire temperature range, this has an added benefit that the TMP63 will
also not lose sensitivity at higher operating temperatures.
7.4.2 Positive Temperature Coefficient (PTC)
The TMP63 has a positive temperature coefficient. As temperature increases the TMP63 resistance will increase
leading to a reduction in power consumption of the bias circuit. A negative coefficient system will have power
consumption increase with temperature as the resistance decreases.
The TMP63 will also benefit from the reduced power consumption of the bias circuit with less self-heating than a
typical NTC system.
7.5 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP63 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves like a
temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on the
system-level requirements. The TMP63 has a nominal resistance at 25°C (R25) of 100 kΩ, a maximum operating
voltage of 5.5 V (VSns), and maximum supply current of 400 µA (ISns). This device may be used in a variety of
applications to monitor temperature close to a heat source with the very small DEC package option compatible
with the typical 0402 (inch) footprint. Some of the factors that influence the total measurement error include the
ADC resolution (if applicable), the tolerance of the bias current or voltage, the tolerance of the bias resistance in
the case of a voltage divider configuration, and the location of the sensor with respect to the heat source.
8.2 Typical Application
8.2.1 Thermistor Biasing Circuits
Figure 11. Biasing Circuit Implementations With Linear Thermistor (Left) vs. Non-Linear Thermistor
(Right)
8.2.1.1 Design Requirements
Existing thermistors, in general, have a non-linear temperature vs. resistance curve. To linearize the thermistor
response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or a resistance
linearization circuit by adding another resistance in parallel with the thermistor, RP. Thermistor Biasing Circuits
highlights the two implementations where RT is the thermistor resistance. To generate an output voltage across
the thermistor, the engineer can use a voltage divider circuit with the thermistor placed at either the high side
(close to supply) or low side (close to ground), depending on the desired voltage response (negative or positive).
Alternatively, the thermistor can be biased directly using a precision current source (yielding the highest accuracy
10
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Typical Application (continued)
and voltage gain). It is common to use a voltage divider with thermistors because of its simple implementation
and lower cost. The TMP63, on the other hand, has a linear positive temperature coefficient (PTC) of resistance
such that the voltage measured across it increases linearly with temperature. As such, the need for a
linearization circuits is no longer a requirement, and a simple current source or a voltage divider circuit can be
used to generate the temperature voltage.
This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature
trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback
input for an active feedback control circuit.
The voltage across the TMP63, as described in Equation 2, can be translated to temperature using either a
lookup table method (LUT) or a fitting polynomial, V(T). The Thermistor Design Tool must be used to translate
Vtemp to Temperature. The temperature voltage must first be digitized using an ADC. The necessary resolution
of this ADC is dependent on the biasing method used. Additionally, for best accuracy, the bias voltage (VBIAS)
should be tied to the reference voltage of the ADC to create a measurement where the difference in tolerance
between the bias voltage and the reference voltage cancels out. The engineer can also implement a low-pass
filter to reject system level noise, and the user should place the filter as close to the ADC input as possible.
8.2.1.2 Detailed Design Procedure
The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage
(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due to
the voltage supply will be canceled and will not affect the temperature accuracy. This type of configuration is
shown in Figure 12. Equation 2 describes the output voltage (VTEMP) based on the variable resistance of the
TMP63 (RTMP63) and bias resistor (RBIAS). The ADC code that corresponds to that output voltage, ADC full-scale
range, and ADC resolution is given in Equation 3.
VBias
RBias
RFilter
REF
IN
RTMP63
ADC
CFilter
IN
GND
Figure 12. TMP63 Voltage Divider With an ADC
VTEMP
§
·
RTMP63
VBIAS u ¨
¸
© RBIAS RTMP63 ¹
ADC Code
§ VTEMP
¨ FSR
©
(2)
· n
¸u2
¹
where
•
•
FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
n is the resolution of the ADC
(3)
Equation 4 shows whenever VREF = VBIAS, VBIAS cancels out.
ADC Code
§
§
RTMP63
¨ VBIAS u ¨
R
© BIAS RTMP63
¨
¨
VBIAS
¨
¨
©
··
¸¸
¹ ¸ u 2n
¸
¸
¸
¹
§
RTMP63
¨
R
© BIAS RTMP63
· n
¸u2
¹
(4)
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Typical Application (continued)
The engineer can use a polynomial equation or a LUT to extract the temperature reading based on the ADC
code read in the microcontroller. The Thermistor Design Tool should be used to translate the TMP63 resistance
to temperature.
The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the
output voltage of the divider circuit cannot increase much. Therefore, not all of the ADC codes will be used due
to the small voltage output range compared to the FSR. This application is very common, however, and is simple
to implement.
The engineer can use a current source-based circuit, like the one shown in Figure 13, to have better control over
the sensitivity of the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I ×
R. For example, if a current source of 40 µA is used with the TMP63, the output voltage will span approximately
5.5 V and will have a gain up to 40 mV/°C. Having control over the voltage range and sensitivity allows for full
utilization of the ADC codes and full-scale range. Based on the bias current, the temperature voltage is shown in
Figure 18. Similar to the ratiometric approach above, if the ADC has a built-in current source that shares the
same bias as the reference voltage of the ADC, the tolerance of the supply current cancels out. In this case, a
precision ADC is not required. This method yields the best accuracy, but can increase the system
implementation cost.
IBias
Precision
Current Source
VTemp
RTMP63
Figure 13. TMP63 Biasing Circuit With Current Source
In comparison to the non-linear NTC thermistor in a voltage divider, the TMP63 has an enhanced linear output
characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are shown in
Figure 14. Consider an example where VBIAS = 5 V, RBIAS = 100 kΩ, and a parallel resistor (RP) is used with the
NTC thermistor (RNTC) to linearize the output voltage with an additional 100-kΩ resistor. The TMP63 produces a
linear curve across the entire temperature range while the NTC curve is only linear across a small temperature
region. When the parallel resistor (RP) is added to the NTC circuit, the added resistor makes the curve much
more linear but greatly affects the output voltage range.
VBias
VBias
RBias
RTMP63
RBias
VTemp
RNTC
RP
VTemp
Figure 14. TMP63 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits
12
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Typical Application (continued)
8.2.1.2.1 Thermal Protection With Comparator
The engineer can use the TMP63, a voltage reference, and a comparator to program the thermal protection. As
shown in Figure 15, the output of the comparator will remain low until the voltage of the thermistor divider, with
RBIAS and RTMP63, rises above the threshold voltage set by R1 and R2. When the output goes high, the
comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent
the output from continuously toggling around the temperature threshold when the output returns low. Either a
comparator with built-in hysteresis or feedback resistors may be used.
VBias
RBias
R1
VTrip
RTMP63
R2
Figure 15. Temperature Switch Using TMP63 Voltage Divider and a Comparator
8.2.1.2.2 Thermal Foldback
One application that uses the output voltage of the TMP63 in an active control circuit is thermal foldback. This is
performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures, the
LEDs begin to heat up due to environmental conditions and self heating. Thus, at a certain temperature threshold
based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs and prevent
thermal runaway. The TMP63 voltage output increases with temperature when the output is in the lower position
of the voltage divider and can provide a response used to fold back the current. Typically, the current is held at a
specified level until a high temperature is reached, known as the knee point, where the current must be rapidly
reduced. To better control the temperature/voltage sensitivity of the TMP63, a rail-to-rail operational amplifier is
used. In the example shown in Figure 16, the temperature “knee” where the foldback begins is set by the
reference voltage (2.5 V) at the positive input, and the feedback resistors set the response of the foldback curve.
The foldback knee point may be chosen based on the output of the voltage divider and the corresponding
temperature from Equation 5 (like 110°C, for example). A buffer is used in-between the voltage divider with
RTMP63 and the input to the op amp to prevent loading and variations in VTEMP.
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Typical Application (continued)
5V
RBias
200 k
RFB
300 k
R2
200 k
R1
10 k
VOut
VTemp
VRef
RTMP63
R3
200 k
Figure 16. Thermal Foldback Using TMP63 Voltage Divider and a Rail-to-Rail Op Amp
The op amp will remain high as long as the voltage output is below VRef. When the temperature goes above
110°C, then the output will swing low to the 0-V rail of the op amp. The rate at which the foldback occurs is
dependent on the feedback network, RFB and R1, which varies the gain of the op amp, G, given by Equation 6.
This in return controls the voltage/temperature sensitivity of the circuit. This voltage output is fed into a LED
driver IC that will adjust output current accordingly. The final output voltage used for thermal foldback is VOUT,
and is given in Equation 7. In this example where the knee point is set at 110°C, the output voltage curve is as
shown in Figure 17.
VTEMP
G
§
·
RTMP63
VBIAS u ¨
¸
© RBIAS RTMP63 ¹
(5)
RFB
R1
VOUT
(6)
G u VTEMP
1 G u VREF
(7)
6
5
VTEMP (V)
4
3
2
1
0
0
25
50
75
100
Temperature (qC)
125
150
D014
Figure 17. Thermal Foldback Voltage Output Curve
14
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Typical Application (continued)
8.2.2 Application Curve
9
8
7
VTemp (V)
6
IBias = 5 PA
IBias = 10 PA
IBias = 20 PA
IBias = 30 PA
IBias = 40 PA
5
4
3
2
1
0
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
TMP6
Figure 18. TMP63 Temperature Voltage With Varying Current Sources
9 Power Supply Recommendations
The maximum recommended operating voltage of the TMP63 is 5.5 V (VSns), and the maximum current through
the device is 400 µA (ISns).
10 Layout
10.1 Layout Guidelines
The layout of the TMP63 is similar to that of a passive component. If the device is biased with a current source,
the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the circuit is
biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is connected
to ground, and V+ is connected to the output (VTEMP). If the device is placed on the upper side of the divider, V+
is connected to the voltage source and V– is connected to the output voltage (VTEMP). Figure 19 shows the
device layout.
10.2 Layout Example
Figure 19. Recommended Layout: DEC Package
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TMP6331DECR
ACTIVE
X1SON
DEC
2
10000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC
TMP6331DECT
ACTIVE
X1SON
DEC
2
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TMP6331DECR
X1SON
DEC
2
10000
178.0
8.4
0.7
1.15
0.47
2.0
8.0
Q1
TMP6331DECT
X1SON
DEC
2
250
178.0
8.4
0.7
1.15
0.47
2.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMP6331DECR
X1SON
DEC
2
10000
205.0
200.0
33.0
TMP6331DECT
X1SON
DEC
2
250
205.0
200.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
DEC0002A
X1SON - 0.5 mm max height
SCALE 11.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
0.65
0.55
0.50
0.41
C
SEATING PLANE
0.05
0.00
0.03 C
0.65
1
2
SYMM
0.55
0.45
0.1
C A B
2X
PIN 1 ID
(45 X0.125)
SYMM
2X
0.3
0.2
0.1
C A B
4224506/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.25)
SYMM
1
SYMM
2X (0.5)
2
(R0.05) TYP
(0.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
EXPOSED
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224506/A 08/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
(0.05)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2X (0.5)
1
2
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224506/A 08/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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