Texas Instruments | TMP392 Ultra-Small, Dual-Channel (Hot and Warm Trip), 0.5-µA, Resistor-Programmable Temperature Switch | Datasheet | Texas Instruments TMP392 Ultra-Small, Dual-Channel (Hot and Warm Trip), 0.5-µA, Resistor-Programmable Temperature Switch Datasheet

Texas Instruments TMP392 Ultra-Small, Dual-Channel (Hot and Warm Trip), 0.5-µA, Resistor-Programmable Temperature Switch Datasheet
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TMP392
SNIS216 – NOVEMBER 2019
TMP392 Ultra-Small, Dual-Channel (Hot and Warm Trip), 0.5-µA, Resistor-Programmable
Temperature Switch
1 Features
3 Description
•
The TMP392 device is part of a family of ultra-low
power, dual channel, resistor programmable
temperature switches that enable protection and
detection of system thermal events from 30°C to
130°C. The TMP392 offers dual overtemperature (hot
and warm) detection. The trip temperatures (TTRIP)
and thermal hysteresis (THYST) options are
programmed by two E96-series resistors (1%
tolerance) on the SETA and SETB pins. Channel A
resistors can range from 1.05 KΩ to 909 KΩ,
representing one of 48 unique values. Channel B
resistors can range from 10.5 KΩ to 909 KΩ
1
•
•
•
•
•
•
•
Resistor programmable temperature trip points
and hysteresis options
– Resistor tolerances contribute zero error
– Hysteresis options: 5°C, 10°C and 20°C
Dual outputs for overtemperature detection
– Channel A (overtemperature-hot): +30 to
+124°C, 2°C steps
– Channel B (overtemperature-warm): +30 to
+105°C, 5°C steps
Accuracy level options (maximum at +30°C to
+130°C):
– A2 Level: ±3.0°C (±1.5°C from +30°C to
+70°C)
– A3 Level: ±3.5°C (±2.0°C from +30°C to
+70°C)
Ultra-low power consumption: 0.5 µA typical at
25°C
Supply voltage: 1.62 to 5.5 V
Open-drain outputs
Trip test function enables in-system testing
Available in a SOT-563 (1.60-mm × 1.20-mm),
6-pin package
The value of the resistor to ground on SETA input
sets the TTRIP threshold of Channel A. The value of
the resistor to ground on SETB input sets the TTRIP
threshold of Channel B, as well as the THYST options
of 5°C, or 10°C for both channels, to prevent
undesired digital output switching. When the SETB
input is connected to ground, Channel A operates
with 20°C hysteresis. Resistors accuracy has no
impact to TTRIP accuracy.
To enable customer board-level manufacturing, the
TMP392 supports a trip test function where the digital
outputs are activated by exercising the SETA or
SETB pin.
Device Information(1)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
DC/AC inverter
DC/DC converter
Temperature transmitters
Environmental control systems (ECS)
Power tools
Power banks
Lighting Control
Industrial Robots
Machine Vision
STB & DVR
WLAN/Wi-Fi access points
PART
NUMBER
TMP392
PACKAGE
BODY SIZE (NOM)
SOT-563 (6)
1.60 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Device Comparison
PART NUMBER
FUNCTION
TMP390
Hot / Cold
TMP392
Hot / Warm
OUTPUT TYPE
Open-Drain
Simplified Schematic
RSETA and RSETB select trip
thresholds and hysteresis options.
VDD or VDDIO
VDD
RP
SETA
Optional Trip
Test
SETB
RSETA
RP
OUTA
TMP39x
OUTB
RSETB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP392
SNIS216 – NOVEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Applications Information.......................................... 11
8.2 Typical Applications ................................................ 11
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2019
*
Initial release.
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5 Pin Configuration and Functions
DRL Package
6-Pin SOT-563
Top View
SETA
1
6
OUTA
SETB
2
5
VDD
GND
3
4
OUTB
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
SETA
Input
Channel A temperature set point. Connect a standard E96, 1% resistance between SETA
and GND.
2
SETB
Input
Channel B temperature and Hysteresis set point. Connect a standard E96, 1% resistance
between SETB and GND.
3
GND
Ground
4
OUTB
Logic Output
5
VDD
Supply
6
OUTA
Logic Output
Device ground.
Channel B logic open-drain active low output. If unused, the output can be left floating or
connected to GND.
Power supply voltage (1.62 V – 5.5 V).
Channel A logic open-drain active low output. If unused, the output can be left floating or
connected to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage
VDD
Voltage at
OUTA, OUTB
Voltage at
SETA, SETB
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
MIN
MAX
–0.3
6
UNIT
V
-0.3
6
V
–0.3
VDD + 0.3
V
–55
150
°C
–60
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Powering the device when the operating junction temperature is outside the Recommended Operating Conditions, may affect the
functional operation of the device. The device must be power cycled after the system has returned to conditions as indicated under
Recommended Operating Conditions.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
1.62
3.3
5.5
V
Channel A output pull-up voltage (open-drain)
VDD + 0.3
V
VOUTB
Channel B output pull-up voltage (open-drain)
VDD + 0.3
V
ISETA
SETA pin circuit leakage current
-20
20
nA
ISETB
SETB pin circuit leakage current
-20
20
nA
RPA
Pullup resistor connected from OUTA to VDDIO (1)
RPB
Pullup resistor connected from OUTB to VDDIO (1)
TA
Operating free-air temperature (specified performance)
VDD
Supply voltage
VOUTA
(1)
1
10
UNIT
kΩ
–55
130
°C
Where VDDIO is an independent power supply other than VDD, and shall not exceed (VDD + 0.3) V.
6.4 Thermal Information
TMP392
THERMAL METRIC
(1)
DRL (SOT)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
230
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
103.4
°C/W
RθJB
Junction-to-board thermal resistance
111.6
°C/W
ψJT
Junction-to-top characterization parameter
5.3
°C/W
ψJB
Junction-to-board characterization parameter
110.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor IC Package Thermal Metrics application report,
(SPRA953).
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6.5 Electrical Characteristics
Minimum and maximum specifications are over -55°C to 130°C and VDD = 1.62V - 5.5V (unless otherwise noted); typical
specifications are at TA = 25°C and VDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
30°C to 70°C, VDD = 2.5V
to 5.5V (1)
-1.5
±0.5
1.5
30°C to 70°C, VDD =
1.62V to 2.5V (1)
-2.0
±0.5
2.0
30°C to 130°C, VDD =
2.5V to 5.5V (1)
-2.5
±0.5
2.5
30°C to 130°C, VDD =
1.62V to 2.5V (1)
-3.0
±0.5
3.0
-2.0
±0.5
2.0
°C
3.5
°C
TEMPERATURE TO DIGITAL CONVERTER
TEMPERATURE MEASUREMENT
TMP392A2
Trip Point Accuracy
TMP392A3
THYST
Trip point hysteresis
30°C to 70°C
(1)
30°C to 130°C (1)
°C
-3.5
Table 2 selection column 2
5
°C
Table 2 selection column 3
10
°C
Channel A only when SETB connected
to GND
20
°C
TRIP POINT RESISTOR PROGRAMMING
SETA resistor range
1.05
909
kΩ
SETB resistor range
10.5
909
kΩ
SETA & SETB resistor tolerance
-1.0
1.0
%
SETA & SETB resistor
temperature coefficient (2)
TA=25°C
-100
100
ppm/°C
SETA & SETB resistor lifetime
drift (2)
-0.2
0.2
%
50
pF
DIGITAL INPUT/OUTPUT
CIN
Input capacitance for SETA &
SETB (includes PCB)
RPD
Internal Pull down resistance
SETA & SETB
VOL
Output logic low level
IOL = -3 mA
ILKG
Leakage current on output high
level
TCov
Conversion duration
TS
Sampling period
125
kΩ
0
0.4
V
-0.1
0.1
µA
0.65
ms
0.5
s
POWER SUPPLY
IQ
Average Quiescent current
IStandby
Standby current
IConv
Conversion current
135
μA
ISU
Startup (Reset) peak current
Reset Time interval only.
250
μA
VPOR
Power-on-reset threshold voltage
Supply going up
1.5
V
Brownout detect
Supply going down
1.1
V
Power Reset Time
Time required by device to reset after
power up
10
ms
(1)
(2)
VDD = 1.62V to 3.3V
0.5
1
0.25
μA
Trip point accuracy test conditions is from 30°C to 130°C, since for the TMP392 the trip points for both channels is from 30°C to 124°C
Recommended Value
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6.6 Typical Characteristics
1.4
3
1.62 V
3.3 V
4.4 V
5.5 V
1.2
2
1.5
Trip Error (qC)
I (uA)
1
2.5
0.8
0.6
0.4
1
0.5
0
-0.5
-1
-1.5
0.2
-2
0
-60
-2.5
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
-3
30
D002
40
50
60
(VS = 1.62 V, 3.3 V, 4.4 V, 5.5 V)
70
80
90
Temperature (qC)
100
110
120
D006
(VS = 3.3 V)
Figure 2. Hot Trip Point Accuracy vs Operating Temperature
3
6
2.5
5
2
4
1.5
3
1
2
Change (%)
Trip Error (qC)
Figure 1. Average Supply Current vs Operating Temperature
0.5
0
-0.5
1
0
-1
-1
-2
-1.5
-3
-2
-4
-2.5
-5
-3
30
40
50
60
70
80
Temperature (qC)
90
-55qC
25qC
130qC
-6
1.5
100
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
D001
D002
(VS = 3.3 V)
Figure 4. Sampling Period Variation vs Supply Voltage
200
200
190
180
180
160
170
140
VOUT (mV)
Current (uA)
Figure 3. Warm Trip Point Accuracy vs Operating
Temperature
160
150
140
120
100
80
130
60
120
40
110
20
100
1.5
1.62 V
2.2 V
3.3 V
5.5 V
0
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
0
1
D005
2
3
4
5
6
Load Current (mA)
7
8
9
10
D004
(TAMB = 25°C)
Figure 5. Conversion Current vs Supply Voltage
6
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Figure 6. Output Voltage vs Load Current
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7 Detailed Description
7.1 Overview
The TMP392 ultra-low power, dual channel, resistor programmable temperature switches enable detection and
protection of system thermal events over a wide temperature range. The TMP392 offers dual overtemperature
(hot and warm) detection. Channel A is referred to as the hot channel, and Channel B is referred to as the warm
channel. The trip temperatures and hysteresis options are programmed by two E96-series (1%) standard decade
value resistors on the SETA and SETB pins. The TMP392 can enable a customer board-level manufacturing test
through the trip test function that can force the SETA or SETB pins to logic high to activates the digital outputs.
7.2 Functional Block Diagram
RSETA and RSETB select trip
thresholds and hysteresis options.
VDD
VDD or VDDIO
RP
RP
SETA
C
SETB
RSETA
OUTA
TMP39x
OUTB
RSETB
Figure 7. Simplified Schematic
7.3 Feature Description
The TMP392 requires two resistors to set the two trip points and hysteresis, according to Table 1 and Table 2 for
the hot and warm channel device. The output of the TMP392 is open-drain and requires two pullup resistors. TI
recommends to use a pullup voltage supply that does not exceed VDD + 0.3 V. The pullup resistors used in
between the OUTA and OUTB pins and the pullup supply should be greater than 1 kΩ. The device powers on
when the supply voltage goes beyond 1.5 V, and starts sampling the input resistors to set the two trip points and
hysteresis value after power-on. These values will remain the same until the device goes through a power cycle.
After the device sets the trip points and hysteresis level, the device will update the output every half a second.
The conversion time is typically 0.65 ms when the temperature is checked against the trip points and the outputs
are updated. The device remains in standby mode between conversions. If either channel is not used, the output
can be grounded or left floating.
7.3.1 TMP392 Programming Tables
The temperature threshold and hysteresis options for the TMP392 device are programmed using two external
1% E96 standard resistors. The specific resistor value to ground on the SETA input sets the temperature
threshold of channel A. The specific resistor value to ground on the SETB input sets the temperature threshold of
channel B, as well as the hysteresis for both channel A and channel B.
Table 1. TMP392 Channel A Threshold Setting
CHANNEL A (HOT)
TRIP TEMPERATURE
(°C)
CHANNEL A NOMINAL 1%
RESISTORS (KΩ)
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 5°C
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 10°C
30
1.05
25
20
32
1.21
27
22
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Feature Description (continued)
Table 1. TMP392 Channel A Threshold Setting (continued)
8
CHANNEL A (HOT)
TRIP TEMPERATURE
(°C)
CHANNEL A NOMINAL 1%
RESISTORS (KΩ)
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 5°C
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 10°C
34
1.40
29
24
36
1.62
31
26
38
1.87
33
28
40
2.15
35
30
42
2.49
37
32
44
2.87
39
34
46
3.32
41
36
48
3.83
43
38
50
4.42
45
40
52
5.11
47
42
54
5.90
49
44
56
6.81
51
46
58
7.87
53
48
60
9.09
55
50
62
10.5
57
52
64
12.1
59
54
66
14.0
61
56
68
16.2
63
58
70
18.7
65
60
72
21.5
67
62
74
24.9
69
64
76
28.7
71
66
78
33.2
73
68
80
38.3
75
70
82
44.2
77
72
84
51.1
79
74
86
59.0
81
76
88
68.1
83
78
90
78.7
85
80
92
90.9
87
82
94
105
89
84
96
121
91
86
98
140
93
88
100
162
95
90
102
187
97
92
104
215
99
94
106
249
101
96
108
287
103
98
110
332
105
100
112
383
107
102
114
442
109
104
116
511
111
106
118
590
113
108
120
681
115
110
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Feature Description (continued)
Table 1. TMP392 Channel A Threshold Setting (continued)
CHANNEL A (HOT)
TRIP TEMPERATURE
(°C)
CHANNEL A NOMINAL 1%
RESISTORS (KΩ)
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 5°C
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 10°C
122
787
117
112
124
909
119
114
NOTE
When the SETA pin is grounded or left floating during the device power up, the OUTA pin
always stays low. The Channel B functionality is not affected by the SETA channel.
Table 2. TMP392 Channel B Threshold and Hysteresis Setting
CHANNEL B
(WARM) TRIP
TEMPERATURE (°C)
CHANNEL B NOMINAL 1% RESISTORS (KΩ)
CHANNEL B (WARM) TRIP RESET TEMPERATURE (°C)
HYSTERESIS = 5°C
HYSTERESIS = 10°C
HYSTERESIS = 5°C
HYSTERESIS = 10°C
30
90.9
105
25
20
35
78.7
121
30
25
40
68.1
140
35
30
45
59.0
162
40
35
50
51.1
187
45
40
55
44.2
215
50
45
60
38.3
249
55
50
65
33.2
287
60
55
70
28.7
332
65
60
75
24.9
383
70
65
80
21.5
442
75
70
85
18.7
511
80
75
90
16.2
590
85
80
95
14.0
681
90
85
100
12.1
787
95
90
105
10.5
909
100
95
NOTE
When the SETB pin is grounded or left floating during the POR, the OUTB pin always
stays low and the Channel A hysteresis is set to 20°C.
7.3.2 Trip Test
The purpose of the trip test is in system manufacturing test without putting the TMP392 through costly
temperature verification of the assembly of TMP392 and pullup resistors. When the SETA or SETB pin is set to a
high logic level, the associated output goes low. When the input pin level goes low, the output goes to its
previous condition before the trip test. The trip test does not affect the current condition of the device. The trip
test signals should stay above 0.8 × VDD for logic high and below 0.2 × VDD for logic low.
The trip test operation is shown in Figure 8. The trip test must be performed with a single toggle when the device
is operating at a temperature that will not cause the corresponding output to trip. The trip test is intended for
production testing after assembly, and must not be used as a functional feature.
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Measured
Temperature (°C)
(Channel A)
Hot threshold
Hysteresis:
5°C, or 10°C
(Channel B)
Warm threshold
Time (s)
OUTA
OUTB
Trip test
asserts output
SETA
SETB
Time (s)
Figure 8. TMP392 Trip Test Operation
7.3.3 20°C Hysteresis
The 20°C hysteresis feature is only available on Channel A. To activate the feature, the SETB pin must be
connected to ground and SETA pin connected to the resistor to set the appropriate trip point on Channel A.
7.4 Device Functional Modes
The device has one mode of operation, as described above, that applies when operated within the
Recommended Operating Conditions.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Applications Information
The TMP392 device is part of a family of ultra-low power, dual channel, resistor programmable temperature
switches that can enable detection and protection of system thermal events over a wide temperature range. The
trip temperatures (TTRIP) and hysteresis options are programmed by two E96-series (1%) standard decade value
resistors on the SETA and SETB pins. The thermal hysteresis (THYST) function is to prevent undesired digital
output switching due to small temperature changes.
8.2 Typical Applications
8.2.1 Simplified Application Schematic
Figure 9 shows the simplified schematic where RSETA and RSETB are used to set channel A trip point (SETA) and
channel B trip point and hysteresis for both channels (SETB). SETA and SETB can be programmed at a variety
of temperatures based on the device, as described in Table 1 for channel A trip point, and Table 2 for channel B
trip point and hysteresis for both channels. OUTA and OUTB outputs correspond to the temperature threshold
detection at SETA and SETB, respectively.
RSETA and RSETB select trip
thresholds and hysteresis options.
VDD or VDDIO
VDD
RP
SETA
Optional Trip
Test
SETB
RSETA
RP
OUTA
TMP39x
OUTB
RSETB
Figure 9. Simplified Schematic
8.2.1.1 Design Requirements
The TMP392 requires two resistors to set the high and low trip points and hysteresis, and two pullup resistors for
the open-drain device. TI also highly recommends to place a 0.1-µF, power-supply bypassing capacitor close to
the VDD supply pin. To minimize the internal power dissipation, use two pullup resistors greater than 1 kΩ from
the OUTA and OUTB pins to the VDD pin. A separate supply, VDDIO, may be used for the pullup voltage to set
the output voltage level to the level required by the MCU, as shown in Figure 9. The open-drain output gives
flexibility of pulling up to any voltage independent of VDD (VDDIO must be less than or equal to VDD + 0.3 V).
This allows for use of longer cables or different power supply options. If a separate voltage level is not required,
TI recommends to tie the pullup to the TMP392 VDD.
If the SETA or SETB connected resistor value is outside the legal range, the associated output goes to
permanent output zero stage and the channel cannot be used. The other channel still will be in operating
condition, and device can be used in one channel mode. If the SETB input is grounded or left floating, the
Channel B cannot be used and the hysteresis for Channel A will be 20°C. The SETA and SETB connected
resistors are measured during POR. If two consecutive measurements are not matching each other, then the
device sets the associated channel output to zero and repeats the resistor measurements until the
measurements match. When the measurements match, the channel output is released. Note that it is possible to
connect some device outputs together by shorting the OUTA or OUTB line.
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The resistor to ground values on the SETA input sets the TTRIP threshold of Channel A. The resistor to ground
value on the SETB input sets the TTRIP threshold of Channel B—as well as the THYST 5°C and 10°C options. TI
recommends that the resistors at SETA and SETB have a 1% tolerance at room temperature. Each resistor can
range from 1.05 KΩ to 909 KΩ, representing one of 48 unique values. The exact temperature thresholds and trip
points are shown in Table 1 and Table 2. The pullup resistors should be at least 1 kΩ to minimize internal power
dissipation. To get the correct threshold for resistor values, take care to minimize the board level capacitance
and leakage at the SETA and SETB pins.
The waveform for the TMP392 output for hot/warm thresholds is shown in Figure 10. The hysteresis can be set
to 5°C, 10°C, or 20°C. When the temperature exceeds the hot trip point threshold, OUTA goes low until the
temperature drops below the hysteresis threshold. When the temperature exceeds the warm trip threshold,
OUTB goes low and returns high after the temperature drops below the hysteresis threshold. If the switch has
already tripped and the temperature is in the hysteresis band, a POR event will cause the output to go high after
the power is restored.
8.2.1.3 Application Curves
Measured
Temperature (°C)
(Channel A)
Hot threshold
(Channel B)
Warm threshold
Time (s)
OUTA
OUTB
Time (s)
Figure 10. TMP392 Output With Hot/Warm Thresholds and Hysteresis
12
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Typical Applications (continued)
8.2.2 TMP392 With 10°C Hysteresis
Figure 11 shows an example circuit for dual overtemperature protection using the TMP392. In this example, the
trip points are set at +60°C and +90°C with 10°C hysteresis. This circuit is useful in cases where a lower
overtemperature detection may be used to warn the application of rising system temperature and take software
corrective actions such as lowering the performance, while the higher overtemperature detection may be used to
start a fan to cool the system to a lower temperature.
VDD = 3.0 V
0.1 µF
3.3 V
10 kŸ
VDD
OUTA
SETA
78.7 kŸ
Channel A Trip Temp = +90°C
and Hysteresis = 10°C
10 kŸ
TMP392
SETB
249 kŸ
VCC
Microprocessor
OUTB
GND
GND
Channel B Trip Temp = 60°C
and Hysteresis = 10°C
Figure 11. TMP392 Example Circuit at +90°C and +60°C Thresholds With 10°C Hysteresis
8.2.2.1 Design Requirements
In this example, VDD can be ≥ 3 V. The output pins may be tied to a switch to control a fan or other analog
circuitry. Figure 11 uses 10-kΩ pullup resistors at the OUTA and OUTB outputs. Place a 0.1-µF bypass capacitor
close to the TMP392 device to reduce noise coupled from the power supply. If needed, the output of multiple
parts can be connected together.
8.2.2.2 Detailed Design Procedure
SETA sets the +90°C threshold using 78.7 kΩ. SETB sets the +60°C trip point and 10°C hysteresis using 249
kΩ. These values were determined using Table 1 and Table 2. These resistors should have maximum of 1%
tolerance at room temperature and 100 ppm/°C or less over the desired temperature range. A summary of the
resistor settings used in this example is shown in Table 3. See Table 1 and Table 2 for additional trip points and
hysteresis configurations.
The switching output of the TMP392 can be visualized with the output diagram shown in Figure 12. It is key to
notice that hysteresis is subtracted from both Channel A and Channel B threshold values. OUTA remains high
until the sensor reaches +90°C where the output goes low, and returns high after the temperature drops back
down to +80°C. OUTB remains high until the sensor reaches +60°C where the output goes low, and returns high
after the temperature drops back down to +50°C.
Table 3. Example Resistor Settings and Trip Points
CHANNEL
RESISTOR SETTING (kΩ)
SETA
78.7
SETB
249
HYSTERESIS (°C)
10
TRIP TEMPERATURE (°C)
+90
+60
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8.2.2.3 Application Curve
OUTA
OUTB
VCC
VCC
+80°C
+90°C
TTRIP
+50°C
+60°C
TTRIP
Figure 12. TMP392 Output Response With Hysteresis
14
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8.2.3 One Channel Operation for Hot Trip Point up to 124°C
Figure 13 shows the TMP392 configured for one channel operation, with a single resistor to set the hot trip point
and hysteresis. Table 4 shows the possible resistor values and hysteresis values that may be used for one
channel applications.
3.3 V
0.1 µF
10 kŸ
VDD
OUTA
SETA
33.2 kŸ
TMP39x
SETB
OUTB
GND
Figure 13. TMP392 One Channel (Hot) Operation Example Circuit With 78°C Trip Point and 5°C
Hysteresis
Table 4. Single Resistor One Channel Setting
NOMINAL 1% RESISTOR (KΩ)
CHANNEL A TRIP
TEMPERATURE (°C)
HYSTERESIS (°C)
10.5
62
5
12.1
64
5
14.0
66
5
16.2
68
5
18.7
70
5
21.5
72
5
24.9
74
5
28.7
76
5
33.2
78
5
38.3
80
5
44.2
82
5
51.1
84
5
59.0
86
5
68.1
88
5
78.7
90
5
90.0
92
5
105
94
10
121
96
10
140
98
10
162
100
10
187
102
10
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Table 4. Single Resistor One Channel Setting (continued)
NOMINAL 1% RESISTOR (KΩ)
CHANNEL A TRIP
TEMPERATURE (°C)
HYSTERESIS (°C)
215
104
10
249
106
10
287
108
10
332
110
10
383
112
10
442
114
10
511
116
10
590
118
10
681
120
10
787
122
10
909
124
10
8.2.3.1 Application Curve
Measured
Temperature (°C)
Hot threshold
Hysteresis
5°C
Time (s)
OUTA
VDD
When VDD supply voltage is zero, the pullup output voltage is still present
Time (s)
Figure 14. TMP392 One Channel (Hot) Operation Thresholds and Hysteresis
16
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8.2.4 One Channel Operation for Warm Trip Point from 30°C up to 105°C
Figure 15 shows the TMP392 configured for one channel operation, with a single resistor to set the warm trip
point and hysteresis. The resistor values for one channel warm trip point is same as described in Table 2.
3.3 V
0.1 µF
10 kŸ
VDD
OUTA
SETA
TMP392
215 kŸ
SETB
OUTB
GND
Figure 15. TMP392 One Channel (Warm) Operation Example Circuit With 55°C Trip Point and 10°C
Hysteresis
9 Power Supply Recommendations
The low supply current and wide supply range of the TMP392 allow the device to be powered from many
sources. VDDIO must always be lower than or equal to VDD + 0.3 V.
Power supply bypassing is strongly recommended by adding a 0.1-µF capacitor from VDD to GND. In noisy
environments, TI recommends to add a filter with 0.1-µF capacitor and 100-Ω resistor between external supply
and VDD to limit the power supply noise.
10 Layout
10.1 Layout Guidelines
The TMP392 is extremely simple to layout. Place the power supply bypass capacitor as close to the device as
possible, and connect the capacitor as shown in Figure 16. Place the RSETA and RSETB resistors as close to the
device as possible. Carefully consider the resistor placement to avoid additional leakage or parasitic capacitance,
as this may affect the actual resistor sense value for the trip thresholds and hysteresis. If there is a possibility of
moisture condensation on the SETA and SETB circuits, which may lead to additional leakage current, consider
adding a conformal coating to the circuits.
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10.2 Layout Example
VIA to ground plane
VIA to power plane
RSETA
SETA
OUTA
0.1 …F
RSETB
SETB
VDD
GND
OUTB
Figure 16. TMP392 Recommended Layout
18
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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22-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TMP392A2DRLR
ACTIVE
SOT-5X3
DRL
6
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 130
1CH
TMP392A2DRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 130
1CH
TMP392A3DRLR
ACTIVE
SOT-5X3
DRL
6
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 130
1CI
TMP392A3DRLT
ACTIVE
SOT-5X3
DRL
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 130
1CI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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22-Nov-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TMP392A2DRLR
SOT-5X3
DRL
6
4000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.98
1.78
0.69
4.0
8.0
Q3
TMP392A2DRLT
SOT-5X3
DRL
6
250
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
TMP392A3DRLR
SOT-5X3
DRL
6
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
TMP392A3DRLT
SOT-5X3
DRL
6
250
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMP392A2DRLR
SOT-5X3
DRL
6
4000
183.0
183.0
20.0
TMP392A2DRLT
SOT-5X3
DRL
6
250
183.0
183.0
20.0
TMP392A3DRLR
SOT-5X3
DRL
6
4000
183.0
183.0
20.0
TMP392A3DRLT
SOT-5X3
DRL
6
250
183.0
183.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
SCALE 8.000
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
1
A
6
4X 0.5
1.7
1.5
NOTE 3
2X 1
4
3
B
1.3
1.1
6X
0.3
0.1
0.6 MAX
0.05
TYP
0.00
C
SEATING PLANE
6X
0.18
0.08
0.05 C
SYMM
SYMM
6X
6X
0.4
0.2
0.27
0.15
0.1
0.05
C A B
4223266/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4223266/A 09/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/A 09/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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