Texas Instruments | TMP61-Q1 Automotive Grade, 10 kΩ Linear Thermistor With Small 0402 and Grade 0 Package Options (Rev. B) | Datasheet | Texas Instruments TMP61-Q1 Automotive Grade, 10 kΩ Linear Thermistor With Small 0402 and Grade 0 Package Options (Rev. B) Datasheet

Texas Instruments TMP61-Q1 Automotive Grade, 10 kΩ Linear Thermistor With Small 0402 and Grade 0 Package Options (Rev. B) Datasheet
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TMP61-Q1
SNIS210C – APRIL 2019 – REVISED JANUARY 2020
TMP61-Q1 Automotive Grade, 10-kΩ Linear Thermistor
With Small 0402 and Grade 0 Package Options
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications
Temperature options:
– TMP61QDEC Grade 1: –40°C to +125°C, TA
– TMP61QLPG Grade 1: –40°C to +125°C, TA
– TMP61ELPG Grade 0: –40°C to +150°C, TA
Silicon-based thermistor with a
Positive temperature coefficient (PTC)
Linear resistance change across with temperature
compared to non-linear thermistors
– Simplifies resistance-to-temperature
conversion methods
– Reduces look up table memory requirements
– Eliminates the need for linearization circuitry or
multipoint calibration
– Decreases the accuracy spread across a wide
temperature range
10-kΩ nominal resistance at 25°C (R25)
– ±1% maximum (0°C to 70°C)
Consistent sensitivity across temperature
– 6400 ppm/°C TCR (25°C)
– 0.2% typical TCR tolerance across
temperature (–40°C to 125°C)
Fast thermal response time:
– 0.6 second for DEC package
Long lifetime and robust performance
– Ultra-low-power consumption than traditional
NTCs reduce self heating errors
– Built-in fail-safe in case of short-circuit failures
– <1% maximum drift after high temperature and
high humidity stress tests
Typical Implementation
VBIAS
3 Description
The TMP61-Q1 small silicon linear thermistors are
designed for temperature measurement, protection,
compensation, and control systems. Compared to
traditional NTC thermistors, the TMP61-Q1 device
offers enhanced linearity and consistent sensitivity
across the full temperature range. The TMP61-Q1
offers robust performance due to device immunity to
environmental variation and built-in fail-safe
behaviors at high temperatures. This device is
available in a 2-pin, surface-mount, 0402 footprintcompatible X1SON package and a 2-pin, throughhole, mini-sized transistor-outline TO-92S package.
Device Information(1)
PART NUMBER
TMP61-Q1
±
VBIAS × R TMP61
R BIAS + R TMP61
0.60 mm × 1.00 mm
TO-92S (2)
4.00 mm × 3.15 mm
SOT-5×3 (2)
0.80 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) PREVIEW status only
Typical Resistances vs Ambient Temperature
20
IBIAS
VTEMP
BODY SIZE (NOM)
X1SON (2)
25
+
RTMP61
PACKAGE
(2)
VBIAS
RBIAS
VTEMP =
•
•
Automotive infotainment and cluster
– Automotive head unit
– Automotive external amplifier
– Automotive cluster display
Automotive display module
Automotive lighting
– Headlights
– Interior lights
+
RTMP61
VTEMP
±
VTEMP = I BIAS × R TMP61
Resistance (k:)
1
15
10
5
-40
-20
0
20
40
60
80 100
Temperature (qC)
120
140
160
d001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP61-Q1
SNIS210C – APRIL 2019 – REVISED JANUARY 2020
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Examples................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2019) to Revision C
Page
•
Added DYA package in PREVIEW status .............................................................................................................................. 3
•
Standardized pinout diagrams ................................................................................................................................................ 3
•
Clarified Equation 1 ................................................................................................................................................................ 8
Changes from Revision A (June 2019) to Revision B
Page
•
Changed data sheet status from Production Mixed to Production Data ............................................................................... 1
•
Added preview SOT-5X3 package ........................................................................................................................................ 1
•
Added 'Long Term Drift' spec for LPG package ..................................................................................................................... 5
•
Added Thermal Response Time graphs for the LPG package ............................................................................................. 6
•
Added transfer tables for the LPG package ........................................................................................................................ 10
Changes from Original (April 2019) to Revision A
•
2
Page
Changed data sheet status from Advanced Information to Production Mixed ...................................................................... 1
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5 Device Comparison Table
PART
NUMBER
RATING
TMP61QDEC
Automotive Grade 1
TMP61QLPG
Automotive Grade 1
TMP61ELPG
Automotive Grade 0
R25 TYP
R25 %TOL
10 kΩ
PACKAGE
TA
X1SON / DEC (0402)
–40°C to 125°C
TO92S / LPG
–40°C to 125°C
TO92S / LPG
–40°C to 150°C
1%
6 Pin Configuration and Functions
DEC Package
2-Pin X1SON
(Top View)
±
1
LPG Package
2-Pin TO-92S
(Top View)
2
1
2
±
+
+
DYA Package
2-Pin SOT-5X3
(Top View)
ID Area
±
(1)
1
PR
EW
EVI
2
+
The DYA package option is PREVIEW status only
Pin Functions
PIN
NAME
NO.
–
1
+
2
TYPE
—
DESCRIPTION
Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +
terminal is at a higher voltage potential than the – terminal.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
Voltage across the device
Junction temperature (TJ)
-40
Current through the device
Storage temperature (Tstg)
(1)
UNIT
6
-65
V
150
°C
450
µA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002 (1)
HBM classification level 2
±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5
±1000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VSns
Voltage Across Pins 2 (+) and 1 (–)
0
5.5
V
ISns
Current passing through the device
0
400
µA
TA
Operating free-air temperature (specified performance) (X1SON/DEC Package)
–40
125
°C
TA
Operating free-air temperature (specified performance) (TO-92S/LPG Package)
–40
150
°C
7.4 Thermal Information
TMP61-Q1
THERMAL METRIC (1) (2)
DEC (X1SON)
LPG (TO-92)
DYA (SOT-5X3)
UNIT
2 PINS
2 PINS
2 PINS
RθJA
Junction-to-ambient thermal resistance (3) (4)
443.4
215
742.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
195.7
99.9
315.8
°C/W
RθJB
Junction-to-board thermal resistance
254.6
191.7
506.2
°C/W
ΨJT
Junction-to-top characterization parameter
19.9
35.1
109.3
°C/W
ΨJB
Junction-to-board characterization parameter
254.5
191.7
500.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
–
°C/W
(1)
(2)
(3)
(4)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
For information on self-heating and thermal response time see Layout Guidelines section.
The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.
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7.5 Electrical Characteristics
TA = -40°C to 125°C (TMP61Q), TA = -40°C to 150°C (TMP61E), ISns = 200 μA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Thermistor Resistance at 25°C (1)
R25
Resistance Tolerance (1)
RTOL
MIN
TYP
MAX
UNIT
TA = 25°C
9.9
10
10.1
kΩ
TA = 25°C
–1
TA = 0°C to 70°C
TA = -40°C to 150°C
TCR-35
TCR25
Temperature Coefficient of Resistance
TCR85
TCR-35 %
TCR25 %
Temperature Coefficient of Resistance Tolerance
TCR85 %
ΔR
+1
–1
+1
–1.5
+1.5
T1 = -40°C, T2 = -30°C
+6220
T1 = 20°C, T2 = 30°C
+6400
T1 = 80°C, T2 = 90°C
+5910
T1 = -40°C, T2 = -30°C
±0.4
T1 = 20°C, T2 = 30°C
±0.2
T1 = 80°C, T2 = 90°C
±0.3
%
ppm/°C
%
Sensor Long Term Drift (Reliability)
96 hours continuous operation
RH=85%, TA = 130°C, VBias = 5.5V
0.1
0.8
Sensor Long Term Drift (Reliability)
600 hours continuous operation
TA = 150°C, VBias = 5.5V, DEC Package
0.1
1
Sensor Long Term Drift (Reliability)
1000 hours continuous operation
TA = 150°C, VBias = 5.5V, LPG Package
0.1
1.1
%
%
tRES (stirred liquid) Thermal response to 63% (DEC Package)
T1=25°C in Still Air to T2=125°C in Stirred Liquid
0.6
s
tRES (stirred liquid) Thermal response to 63% (LPG Package)
T1=25°C in Still Air to T2=125°C in Stirred Liquid
2.9
s
tRES (still air)
Thermal response to 63% (DEC Package)
T1=25°C to T2=70°C in Still Air
3.2
s
tRES (still air)
Thermal response to 63% (LPG Package)
T1=25°C to T2=70°C in Still Air
20
s
(1)
Limits defined based on 4th order equation
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7.6 Typical Characteristics
at TA = 25°C, (unless otherwise noted)
22
20
20
18
16
Resistance (k:)
Resistance (k:)
18
16
14
12
IBIAS 10 PA
IBIAS 50 PA
IBIAS 100 PA
IBIAS 200 PA
IBIAS 400 PA
10
8
6
-40
-20
0
20
40
60
80 100
Temperature (qC)
120
140
14
12
10
8
6
VBias 1.8 V
VBias 2.5 V
VBias 3.3 V
VBias 5 V
4
2
0
-40
160
-20
0
20
d002
40
60
80
Temperature (qC)
100
120
140
d003
RBIAS = 10 kΩ (±0.01% tol)
Figure 1. Resistance vs. Ambient Temperature Using
Multiple Bias Currents
Figure 2. Resistance vs. Ambient Temperature Using
Multiple Bias Voltages
6510
6340
6480
6330
6450
TCR (ppm/qC)
TCR (ppm/qC)
6420
6390
6360
6330
6300
6320
6310
6300
6270
6240
10
6290
50
100
200
Current Through TMP61, ISns (PA)
400
0.9
1.25
1.65
Voltage Across TMP61, VSns (V)
d004
2.5
d005
RBIAS = 10 kΩ (±0.01% tol)
-40 qC
-25 qC
0
50
100
150
50 qC
100 qC
200 250 300 350
Bias Current (PA)
125 qC
400
450
Figure 4. TCR vs. Sense Voltage (VSNS)
Resistance (k:)
Resistance (k:)
Figure 3. TCR as a Function of Sense Currents ISNS
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
500
19
18
17
16
15
14
13
12
11
10
9
8
7
6
-40 qC
-25 qC
0
0.5
1
1.5
d006
2
2.5
3
Bias Voltage (V)
50 qC
100 qC
3.5
125 qC
4
4.5
5
d007
RBIAS = 10 kΩ (±0.01% tol)
Figure 5. Supply Dependence vs. Bias Current
6
Figure 6. Supply Dependence vs. Bias Voltage
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Typical Characteristics (continued)
at TA = 25°C, (unless otherwise noted)
2.5
20
VBias
VSns
18
2
Resistance (k:)
Output (V)
16
1.5
1
14
12
10
0.6s
0.5
8
0
6
0
1.6
3.2
4.8
Time (Ps)
6.4
8
0
0.19
0.38
0.57
d008
VSNS = 1 V
0.76 0.95
Time (s)
1.14
1.33
1.52
1.71
d009
Ambient condition: stirred liquid
Figure 7. Step Response
Figure 8. Thermal Response Time [DEC Package]
13
12
12.5
11.5
Resistance (k:)
Resistance (k:)
12
11
10.5
20s
.
.
11.5
11
10.5
10
10
3.2s
9.5
3.39
9.5
4.38
5.37
6.36
7.35 8.34
Time (s)
9.33
0
10.32 11.31
20
40
d010
Ambient condition: still air
Ambient condition: still air
Figure 9. Thermal Response Time [DEC Package]
60
80
100
Time (s)
120
140
160
TMP6
LPG package
Figure 10. Thermal Response Time [LPG Package]
20
18
2.9s
f
Resistance (k:)
16
s
14
12
10
8
6
0
2
4
6
Ambient condition: stirred liquid
8
10
Time (s)
12
14
16
18
d011
LPG package
Figure 11. Thermal Response Time
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8 Detailed Description
8.1 Overview
The TMP61-Q1 series of silicon linear thermistors has a linear positive temperature coefficient (PTC) that results
in a uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range.
8.2 Functional Block Diagram
VBIAS
VBIAS
IBIAS
RBIAS
+
RTMP61
+
VTEMP
RTMP61
±
VTEMP =
VTEMP
±
VBIAS × R TMP61
R BIAS + R TMP61
VTEMP = I BIAS × R TMP61
Figure 12. Typical Implementation
8.3 Feature Description
As shown in Figure 1 and Figure 2, the TMP61-Q1 has good linear behaviour across the whole temperature
range, but a small non-linearity can be observed, as well as supply dependence, as shown in Figure 3 and
Figure 4. To fabricate the TMP61-Q1, the engineer can use a special silicon process where the device key
characteristics—the temperature coefficient resistance (TCR) and nominal resistance (R25)—are controlled by
the doping level and active region area. Note that the TMP61-Q1 has an active area and a substrate due to the
polarized terminals of the device. Connect the positive terminal to the highest potential, and connect the negative
terminal (which is tied to the substrate internally) to the lowest potential. Equation 1 can help the user
approximate the TCR.
Table 1, Table 2, Table 3, and Table 4 show the typical resistance, resistance spread, and maximum expected
error across temperature using a direct ideal bias current or an ideal voltage bias in a divider circuit.
TCR =
:R T2 F R T1 ;
:T2 F T1; × R :T2+T1;
2
where
•
TCR is in ppm/°C
(1)
Key terms and definitions:
• ISns: Current flowing through the TMP61-Q1 device.
• VSns: Voltage across the two TMP61-Q1 terminals.
• IBIAS: Current supplied by the biasing circuit.
• VBIAS: Voltage supplied by the biasing circuit.
• VTemp: Output voltage that corresponds to the measured temperature. Note that this is different from VSNS. In
a case of a voltage divider circuit with the TMP61-Q1 in the high side, VTEMP is taken across RBIAS.
8
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Feature Description (continued)
Table 1. TMP61-Q1 Transfer Table Using an Ideal IBIAS of 200 µA [DEC Package]
RESISTANCE (Ω) (1)
(1)
(2)
TEMPERATURE
ERROR (2) (1)
(°C)
MIN
TYP
MAX
ΔR/ΔT
(Ω/°C)
–40
6445
6543
6641
42
2.32
–35
6657
6759
6860
44
2.30
–30
6879
6983
7088
46
2.29
–25
7109
7217
7325
48
2.28
–20
7347
7459
7571
49
2.27
–15
7594
7710
7825
51
2.27
–10
7849
7968
8088
53
2.27
–5
8112
8235
8359
54
2.28
0
8425
8510
8595
56
1.53
5
8704
8792
8880
57
1.53
10
8992
9083
9173
59
1.54
15
9287
9381
9475
60
1.55
20
9590
9687
9783
62
1.56
25
9900
10000
10100
63
1.58
30
10218
10321
10424
65
1.59
35
10544
10650
10757
67
1.60
40
10877
10987
11097
68
1.61
45
11218
11332
11445
70
1.62
50
11568
11685
11801
71
1.64
55
11925
12045
12166
73
1.65
60
12291
12415
12539
75
1.66
65
12665
12792
12920
76
1.67
70
13047
13179
13311
78
1.69
75
13371
13574
13778
80
2.55
80
13769
13979
14188
82
2.56
85
14177
14393
14608
84
2.58
90
14594
14816
15038
86
2.59
TEMPERATURE (°C)
95
15021
15250
15479
88
2.61
100
15458
15694
15929
90
2.62
105
15906
16148
16391
92
2.63
110
16365
16614
16863
94
2.64
115
16835
17091
17348
97
2.65
120
17317
17581
17844
99
2.66
125
17811
18082
18353
102
2.67
Table defined based on 4th order equation: R(Ω) = 8509.73 + 55.728 × T + 0.1571 × T2– 1.10E-4 × T3 + 1.5E –6 × T4
Assuming ideal current source
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Table 2. TMP61-Q1 Transfer Table Using an Ideal IBIAS of 200 µA [LPG Package]
RESISTANCE (Ω) (1)
(1)
(2)
10
TEMPERATURE
ERROR (2) (1)
(°C)
MIN
TYP
MAX
ΔR/ΔT
(Ω/°C)
–40
6486
6585
6684
43
2.32
–35
6700
6802
6904
44
2.31
–30
6922
7027
7132
46
2.30
–25
7151
7260
7368
47
2.30
–20
7387
7500
7612
49
2.31
–15
7631
7748
7864
50
2.31
–10
7883
8003
8123
52
2.32
–5
8142
8266
8390
53
2.33
0
8450
8536
8621
55
1.56
5
8725
8813
8902
56
1.57
10
9008
9099
9190
58
1.57
15
9298
9392
9485
59
1.58
20
9595
9692
9789
61
1.59
25
9900
10000
10100
62
1.60
30
10213
10316
10419
64
1.61
35
10533
10639
10746
66
1.62
40
10861
10971
11081
67
1.63
45
11198
11311
11424
69
1.64
50
11542
11659
11775
70
1.66
55
11895
12015
12135
72
1.67
60
12256
12380
12504
74
1.68
65
12626
12754
12881
76
1.69
70
13005
13136
13268
77
1.70
75
13325
13528
13731
79
2.56
80
13721
13929
14138
81
2.57
85
14125
14340
14555
83
2.59
90
14540
14761
14983
85
2.60
95
14964
15192
15420
87
2.61
100
15399
15633
15868
89
2.62
105
15844
16086
16327
92
2.64
110
16301
16549
16797
94
2.65
115
16768
17024
17279
96
2.66
120
17248
17510
17773
99
2.67
125
17739
18009
18279
101
2.68
130
18242
18520
18798
104
2.68
135
18759
19044
19330
106
2.69
140
19288
19582
19876
109
2.70
145
19831
20133
20435
112
2.70
150
20388
20699
21009
115
TEMPERATURE (°C)
2
2.71
Table defined based on 4th order equation: R(Ω) = 8535.76 + 54.79454 × T + 0.14982 × T + 2.06739E-5 × T + 9.94E-7 × T4
Assuming ideal current source
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Table 3. TMP61-Q1 Transfer Table Using a Voltage Divider With an Ideal VBIAS of 2.5 V and RBIAS of 10
kΩ With ±0.01% Tolerance [DEC Package]
(1)
(2)
RESISTANCE (Ω) (1)
TEMPERATURE ERROR (2)
(°C)
MIN
TYP
MAX
ΔR/ΔT
(Ω/°C)
–40
6411
6508
6606
41
2.39
–35
6617
6717
6818
43
2.35
–30
6833
6937
7041
45
2.32
–25
7058
7165
7273
47
2.30
–20
7293
7404
7515
49
2.29
–15
7536
7651
7765
50
2.28
–10
7788
7906
8025
52
2.28
–5
8048
8170
8293
54
2.29
0
8358
8442
8527
55
1.53
TEMPERATURE (°C)
5
8635
8722
8809
57
1.54
10
8920
9010
9100
58
1.55
15
9212
9305
9398
60
1.56
20
9511
9607
9703
61
1.57
25
9817
9916
10016
63
1.58
30
10131
10233
10335
64
1.60
35
10451
10557
10662
65
1.61
40
10779
10888
10997
67
1.63
45
11113
11226
11338
68
1.64
50
11455
11571
11687
70
1.66
55
11804
11923
12043
71
1.67
60
12161
12283
12406
73
1.69
65
12524
12651
12777
74
1.70
70
12896
13026
13156
76
1.72
75
13208
13409
13610
77
2.60
80
13593
13800
14007
79
2.62
85
13987
14200
14413
81
2.64
90
14390
14609
14828
83
2.65
95
14801
15026
15252
84
2.67
100
15222
15453
15685
86
2.68
105
15652
15890
16129
88
2.70
110
16093
16338
16583
91
2.71
115
16544
16796
17048
93
2.72
120
17006
17265
17524
95
2.73
125
17480
17746
18012
97
2
2.73
3
4
Table defined based on 4th order equation: R(Ω) = 8442.33 + 55.196 × T + 0.1564 × T - 2.83E-4 × T + 2.1E-6 × T
Assuming ideal voltage source, 10 kΩ with ±0.01% RBIAS
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Table 4. TMP61-Q1 Transfer Table Using a Voltage Divider With an Ideal VBIAS of 2.5 V and RBIAS of 10
kΩ With ±0.01% Tolerance [LPG Package]
(1)
(2)
RESISTANCE (Ω) (1)
TEMPERATURE ERROR (2)
(°C)
MIN
TYP
MAX
ΔR/ΔT
(Ω/°C)
–40
6460
6559
6657
42
2.32
–35
6673
6774
6876
44
2.32
–30
6892
6997
7102
45
2.32
–25
7119
7227
7336
47
2.32
–20
7353
7465
7576
48
2.33
–15
7593
7709
7824
50
2.33
–10
7841
7960
8079
51
2.34
–5
8095
8218
8342
52
2.35
0
8399
8484
8569
54
1.58
TEMPERATURE (°C)
5
8669
8756
8844
55
1.59
10
8946
9036
9126
57
1.60
15
9230
9323
9416
58
1.61
20
9521
9617
9713
60
1.62
25
9819
9918
10017
61
1.63
30
10124
10227
10329
62
1.64
35
10437
10543
10648
64
1.65
40
10758
10866
10975
65
1.66
45
11086
11198
11310
67
1.67
50
11421
11536
11652
69
1.68
55
11764
11883
12002
70
1.69
60
12115
12238
12360
72
1.71
65
12475
12601
12727
73
1.72
70
12842
12972
13101
75
1.73
75
13151
13351
13551
77
2.61
80
13533
13739
13945
78
2.63
85
13923
14136
14348
80
2.64
90
14323
14541
14759
82
2.66
95
14731
14956
15180
84
2.68
100
15149
15380
15610
86
2.69
105
15576
15813
16050
88
2.71
110
16013
16256
16500
90
2.72
115
16459
16710
16960
92
2.73
120
16915
17173
17430
94
2.75
125
17382
17647
17911
96
2.76
130
17859
18131
18403
98
2.78
135
18347
18627
18906
100
2.79
140
18847
19134
19421
103
2.80
145
19357
19652
19947
105
2.81
150
19879
20182
20485
107
2.82
Table defined based on 4th order equation: R(Ω) = 8483.75 + 53.7927 × T + 0.142 × T2 + 3.2956E-5 × T3 + 6.40E-7 × T4
Assuming ideal voltage source, 10 kΩ with ±0.01% RBIAS
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMP61-Q1 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves like a
temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on the
system-level requirements. The TMP61-Q1 has a nominal resistance at 25°C (R25) of 10 kΩ with ±1% maximum
tolerance, a maximum operating voltage of 5.5 V (VSNS), and maximum supply current of 400 µA (ISNS). This
device may be used in a variety of applications to monitor temperature close to a heat source with the very small
DEC package option compatible with the typical 0402 (inch) footprint. Some of the factors that influence the total
measurement error include the ADC resolution (if applicable), the tolerance of the bias current or voltage, the
tolerance of the bias resistance in the case of a voltage divider configuration, and the location of the sensor with
respect to the heat source.
9.2 Typical Application
9.2.1 Thermistor Biasing Circuits
+
±
IBIAS
VBIAS
RBIAS
RBIAS
+
+
RT
VTEMP
RT
VTEMP
±
±
Figure 13. Voltage Biasing Circuit With Linear
Thermistor
+
±
Figure 14. Current Biasing Circuit With Linear
Thermistor
IBIAS
VBIAS
RBIAS
RBIAS
+
+
RT
RP
RT
VTEMP
RP
VTEMP
±
±
Figure 15. Voltage Biasing Circuit With Non-Linear
Thermistor
Figure 16. Current Biasing Circuit With Non-Linear
Thermistor
9.2.1.1 Design Requirements
Existing thermistors, in general, have a non-linear temperature vs. resistance curve. To linearize the thermistor
response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or a resistance
linearization circuit by adding another resistance in parallel with the thermistor, RP. Figure 13 highlights the two
implementations, where RT is the thermistor resistance. To generate an output voltage across the thermistor, the
engineer can use a voltage divider circuit with the thermistor placed at either the high side (close to supply) or
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Typical Application (continued)
low side (close to ground), depending on the desired voltage response (negative or positive). Alternatively, the
resistor can be biased directly using a precision current source (yielding the highest accuracy and voltage gain).
It is common to use a voltage divider with thermistors because of its simple implementation and lower cost. The
TMP61-Q1, on the other hand, has a linear positive temperature coefficient (PTC) of resistance such that the
voltage measured across it increases linearly with temperature. As such, the need for linearization circuits is no
longer a requirement, and a simple current source or a voltage divider circuit can be used to generate the
temperature voltage.
This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature
trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback
input for an active feedback control circuit.
The voltage across the TMP61-Q1 can be translated to temperature using either a lookup table method (LUT) or
a fitting polynomial, V(T), as described in Equation 2. The temperature voltage must first be digitized using an
ADC. The necessary resolution of this ADC is dependent on the biasing method used. Additionally, for best
accuracy, the bias voltage (VBIAS) should be tied to the reference voltage of the ADC to create a measurement
where the difference in tolerance between the bias voltage and the reference voltage cancels out. The engineer
can also implement a low-pass filter to reject system level noise, and the user should place the filter as close to
the ADC input as possible.
9.2.1.2 Detailed Design Procedure
The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage
(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due to
the voltage supply are cancelled and do not affect the temperature accuracy. This type of configuration is shown
in Figure 17. Equation 2 describes the output voltage (VTEMP) based on the variable resistance of the TMP61-Q1
(RTMP61) and bias resistor (RBIAS). The ADC code that corresponds to that output voltage, ADC full-scale range,
and ADC resolution is given in Equation 3.
Figure 17. TMP61-Q1 Voltage Divider With an ADC
§
·
RTMP61
VBIAS × ¨
¸
R
+
R
© TMP61 BIAS ¹
VTEMP n
ADC Code
2
FSR
VTEMP
(2)
where
•
•
FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
n is the resolution of the ADC
(3)
Equation 4 shows when VREF = VBIAS, VBIAS cancels out.
14
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Typical Application (continued)
ADC Code
§
·
RTMP61
VBIAS u ¨
¸
© RTMP61+ RBIAS ¹ 2n
VBIAS
§
· n
RTMP61
¨
¸2
R
+
R
© TMP61 BIAS ¹
(4)
The engineer can use a polynomial equation or a LUT to extract the temperature reading based on the ADC
code read in the microcontroller.
The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the
output voltage of the divider circuit cannot increase much. Therefore, not all of the ADC codes are used due to
the small voltage output range compared to the FSR. This application is very common, however, and is simple to
implement.
The engineer can use a current source-based circuit, like the one shown in Figure 18, to have better control over
the sensitivity of the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I ×
R. For example, if a current source of 400 µA is used with the TMP61-Q1, the output voltage spans
approximately 5.5 V and has a gain up to 40 mV/°C. Having control over the voltage range and sensitivity allows
for full utilization of the ADC codes and full-scale range. Based on the bias current, the temperature voltage is
shown in Figure 19. Similar to the ratiometric approach above, if the ADC has a built-in current source that
shares the same bias as the reference voltage of the ADC, the tolerance of the supply current cancels out. In this
case, a precision ADC is not required. This method yields the best accuracy, but can increase the system
implementation cost.
Figure 18. TMP61-Q1 Biasing Circuit With Current Source
9
8
7
VTEMP (V)
6
IBIAS = 50 PA
IBIAS = 100 PA
IBIAS = 200 PA
IBIAS = 300 PA
IBIAS = 400 PA
5
4
3
2
1
0
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
d013
Figure 19. TMP61-Q1 Temperature Voltage With Varying Current Sources
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Typical Application (continued)
In comparison to the non-linear NTC thermistor in a voltage divider, the TMP61-Q1 has an enhanced linear
output characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are
shown in Figure 20. For example, consider an example where VBIAS = 5 V, RBIAS = 10 kΩ, and a parallel resistor
(RP) is used with the NTC thermistor (RNTC) to linearize the output voltage with an additional 10-kΩ resistor. The
output characteristics of the voltage dividers are shown in Figure 21. The TMP61-Q1 produces a linear curve
across the entire temperature range while the NTC curve is only linear across a small temperature region. When
the parallel resistor (RP) is added to the NTC circuit, the added resistor makes the curve much more linear but
greatly affects the output voltage range.
Figure 20. TMP61-Q1 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits
5
VNTC
VTMP61
VNTC with RP
VTEMP (V)
4
3
2
1
0
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
d012
Figure 21. NTC With and Without a Linearization Resistor vs. TMP61-Q1 Temperature Voltages
9.2.1.2.1 Thermal Compensation
The TMP61-Q1 can be used to compensate for components within systems whose characteristics vary over
temperature. For example, resistance changed with temperature based on the specified temperature coefficient.
In certain systems where these resistors are included in the feedback loop, the performance over temperature
may be greatly affected by the changes in resistance. Examples include components like those in control
systems within the feedback loop, linear dropout regulators with feedback resistors, and solenoids or coils with
varying impedance. One implementation is to put the TMP61-Q1 in a feedback loop to compensate for
temperature drift, along with other resistive components to better control the temperature coefficient (α) of the
compensation circuit.
Equation 5 can describe this type of circuit:
R(T) R(T0 ) u (1 D'T)
where
16
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Typical Application (continued)
•
•
•
R(T0) is the resistance
the temperature coefficient, α, is specified (25°C)
the change in temperature, ΔT, is the temperature of interest, T, minus T0 (25°C)
This circuit is shown in Figure 22.
RTMP61u RP
R total RS
RTMP61u RP
(5)
(6)
Figure 22. TMP61-Q1 Thermal Compensation Circuit
9.2.1.2.2 Thermal Protection With Comparator
The engineer can use the TMP61-Q1, a voltage reference, and a comparator to program the thermal protection.
As shown in Figure 23, the output of the comparator remains low until the voltage of the thermistor divider, with
RBIAS and RTMP61, rises above the threshold voltage set by R1 and R2. When the output goes high, the
comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent
the output from continuously toggling around the temperature threshold when the output returns low. Either a
comparator with built-in hysteresis or feedback resistors may be used.
Figure 23. Temperature Switch Using TMP61-Q1 Voltage Divider and a Comparator
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Typical Application (continued)
9.2.1.2.3 Thermal Foldback
One application that uses the output voltage of the TMP61-Q1 in an active control circuit is thermal foldback.
This is performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures,
the LEDs begin to heat up due to environmental conditions and self-heating. Thus, at a certain temperature
threshold based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs
and prevent thermal runaway. The TMP61-Q1 voltage output increases with temperature when the output is in
the lower position of the voltage divider and can provide a response used to fold back the current. Typically, the
current is held at a specified level until a high temperature is reached, known as the knee point, where the
current must be rapidly reduced. To better control the temperature/voltage sensitivity of the TMP61-Q1, a rail-torail operational amplifier is used. In the example shown in Figure 24, the temperature “knee” where the foldback
begins is set by the reference voltage (2.5 V) at the positive input, and the feedback resistors set the response of
the foldback curve. The foldback knee point may be chosen based on the output of the voltage divider and the
corresponding temperature from Equation 7 (like 110°C, for example). A buffer is used in-between the voltage
divider with RTMP61 and the input to the op amp to prevent loading and variations in VTEMP.
Figure 24. Thermal Foldback Using TMP61-Q1 Voltage Divider and a Rail-to-Rail Op Amp
The op amp remains high as long as the voltage output is below VRef. When the temperature goes above 110°C,
then the output decreases to the 0-V rail of the op amp. The rate at which the foldback occurs is dependent on
the feedback network, RFB and R1, which varies the gain of the op amp, G, given by Equation 8. This in return
controls the voltage/temperature sensitivity of the circuit. This voltage output is fed into a LED driver IC that
adjusts output current accordingly. The final output voltage used for thermal foldback is VOUT, and is given in
Equation 9. In this example where the knee point is set at 110°C, the output voltage curve is as shown in
Figure 25.
§
·
RTMP61
VTEMP = VBIAS × ¨
¸
© RTMP61+ RBIAS ¹
(7)
G=
RFB
R1
VOUT
18
(8)
G× VTEMP + (1+ G) × VREF
(9)
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Typical Application (continued)
6
5
VTEMP (V)
4
3
2
1
0
0
25
50
75
100
Temperature (qC)
125
150
D014
Figure 25. Thermal Foldback Voltage Output Curve
9.2.1.3 Application Curve
The TMP61-Q1 accuracy varies depending on the selected biasing circuit. This variation can be seen in
Figure 26. VTEMP is shown with either VBIAS at 2 V in a resistor divider circuit (RBIAS = 10 kΩ ±1%) or IBIAS at 200
µA. Supply sources used are assumed to be ideal. The best accuracy is achieved using a direct current bias
method.
7
VTEMP (V)
5
4.8
4
4
3.2
3
2.4
2
1.6
1
0.8
0
-60
-40
-20
0
20 40 60 80
Temperature (qC)
Error (qC)
6
5.6
VTemp (IBIAS= 200 PA)
VTemp (VBIAS = 2 V)
Error (qC) (IBIAS = 200 PA)
Error (qC) (VBIAS = 2 V)
0
100 120 140 160
d011
Figure 26. TMP61-Q1 Voltage Output and Temperature Error Based on the Bias Method
10 Power Supply Recommendations
The maximum recommended operating voltage of the TMP61-Q1 is 5.5 V (VSNS), and the maximum current
through the device is 400 µA (ISNS).
11 Layout
11.1 Layout Guidelines
The layout of the TMP61-Q1 is similar to that of a passive component. If the device is biased with a current
source, the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the
circuit is biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is
connected to ground and V+ is connected to the output, VTEMP. If the device is placed on the upper side of the
divider, V+ is connected to the voltage source and V– is connected to the output voltage, VTEMP. Figure 27 shows
the device layout.
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11.2 Layout Examples
Figure 27. Recommended Layout: DEC Package
20
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
MSL Ratings and Reflow Profiles (SPRABY1)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTMP6131QDYATQ1
ACTIVE
SOT-5X3
DYA
2
250
TBD
Call TI
Call TI
-40 to 125
TMP6131ELPGMQ1
ACTIVE
TO-92
LPG
2
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 150
TMP61
TMP6131QDECRQ1
ACTIVE
X1SON
DEC
2
10000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
EL
TMP6131QDECTQ1
ACTIVE
X1SON
DEC
2
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
EL
TMP6131QLPGMQ1
ACTIVE
TO-92
LPG
2
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
TMP61
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMP61-Q1 :
• Catalog: TMP61
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TMP6131QDECRQ1
X1SON
DEC
2
10000
178.0
8.4
0.7
1.15
0.47
2.0
8.0
Q1
TMP6131QDECTQ1
X1SON
DEC
2
250
178.0
8.4
0.7
1.15
0.47
2.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMP6131QDECRQ1
X1SON
DEC
2
10000
205.0
200.0
33.0
TMP6131QDECTQ1
X1SON
DEC
2
250
205.0
200.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
B
1.3
1.1
2X
0.3
0.1
0.7
TYP
0.5
0.77 MAX
C
SEATING PLANE
2X
0.15
0.08
0.05 C
SYMM
SYMM
2X
2X
0.4
0.2
0.35
0.25
0.1
0.05
C A B
4224978/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
1
2X (0.4)
2
SYMM
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4224978/A 04/2019
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
2X (0.67)
SYMM
1
(R0.05) TYP
2
2X (0.4)
SYMM
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DEC0002A
X1SON - 0.5 mm max height
SCALE 11.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
0.65
0.55
0.50
0.41
C
SEATING PLANE
0.05
0.00
0.03 C
0.65
1
2
SYMM
0.55
0.45
0.1
C A B
2X
PIN 1 ID
(45 X0.125)
SYMM
2X
0.3
0.2
0.1
C A B
4224506/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.25)
SYMM
1
SYMM
2X (0.5)
2
(R0.05) TYP
(0.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
EXPOSED
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224506/A 08/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
(0.05)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2X (0.5)
1
2
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224506/A 08/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
LPG0002A
TO-92 - 5.05 mm max height
SCALE 1.300
TO-92
4.1
3.9
3.25
3.05
3X
2.3
2.0
2
1
0.51
0.40
5.05
MAX
2 MAX
6X 0.076 MAX
2X
15.5
15.1
3X
0.48
0.33
3X
2X 1.27 0.05
0.51
0.33
2.64
2.44
2.68
2.28
1.62
1.42
2X (45° )
(0.55)
1
2
0.86
0.66
4221971/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
LPG0002A
TO-92 - 5.05 mm max height
TO-92
0.05 MAX
ALL AROUND
TYP
(1.07)
METAL
TYP
3X ( 0.75) VIA
(1.7)
(R0.05) TYP
SOLDER MASK
OPENING
TYP
(1.7)
2
1
(1.27)
(1.07)
(2.54)
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE:20X
4221971/A 03/2015
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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