Texas Instruments | DRV425-Q1 Automotive, Integrated Fluxgate Magnetic-Field Sensor | Datasheet | Texas Instruments DRV425-Q1 Automotive, Integrated Fluxgate Magnetic-Field Sensor Datasheet

Texas Instruments DRV425-Q1 Automotive, Integrated Fluxgate Magnetic-Field Sensor Datasheet
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DRV425-Q1
SBOS988 – AUGUST 2019
DRV425-Q1 Automotive, Integrated Fluxgate Magnetic-Field Sensor
1 Features
3 Description
•
The DRV425-Q1 automotive device is designed for
single-axis magnetic field-sensing applications, and
enables electrically-isolated, high-sensitivity, and
precise dc- and ac-field measurements. The device
provides the unique and proprietary, integrated
fluxgate sensor (IFG) with an internal compensation
coil to support a high-accuracy sensing range of ±2
mT, with a measurement bandwidth of up to 47 kHz.
The low offset, offset drift, and noise of the sensor,
combined with the precise gain, low gain drift, and
very low nonlinearity provided by the internal
compensation coil, result in unrivaled magnetic field
measurement precision.This high level of sensitivity
and accuracy enables more current measurements in
high-current busbar applications, such as traction
inverters or battery-management systems. Torque
sensor or motor diagnostic systems can benefit from
the ability to precisely measure the position or
displacement of a magnetic field. The output of the
DRV425-Q1 is an analog signal proportional to the
sensed magnetic field.
1
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
High-precision, integrated fluxgate sensor:
– Offset: ±8 µT (max)
– Offset drift: ±5 nT/°C (typ)
– Gain error: 0.04% (typ)
– Gain drift: ±7 ppm/°C (typ)
– Linearity: ±0.1%
– Noise: 1.5 nT/√Hz (typ)
Sensor range: ±2 mT (max)
– Range and gain adjustable with external
resistor
Selectable bandwidth: 47 kHz or 32 kHz
Precision reference:
– Accuracy: 2% (max), drift: 50 ppm/°C (max)
– Pin-selectable voltage: 2.5 V or 1.65 V
– Selectable ratiometric mode: VDD / 2
Diagnostic features: Overrange and error flags
Supply voltage range: 3.0 V to 5.5 V
The device offers a complete set of features,
including an internal difference amplifier, on-chip
precision reference, and diagnostic functions to
minimize component count and system-level cost.
2 Applications
•
•
•
•
•
•
The device is available in a thermally-enhanced,
nonmagnetic, thin WQFN package, with a thermal
pad for optimized heat dissipation, and is specified for
operation over the automotive temperature range of
–40°C to +125°C.
Battery management system (BMS)
Inverter and motor control
DC/DC converter
Powertrain current sensor
Powertrain torque sensor
Motor diagnostics and monitoring
Device Information
PART NUMBER
DRV425-Q1
PACKAGE
WQFN (20)
(1)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic
RSHU NT
COMP1
COMP2
DRV2
DRV1 AINP
AINN
DRV425-Q1
Fluxgate
Sen sor
and
Compensation
Coil
Differen tia l
Driver
Shu nt
Sen se
Amplifier
Inte grator
VOUT
ADC
REFIN
Fluxgate S ensor Fro nt-End
Device Control and Diagno stic
Reference
REFOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV425-Q1
SBOS988 – AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Power Supply Recommendations...................... 29
9.1 Power Supply Decoupling ....................................... 29
9.2 Power-On Start-Up and Brownout .......................... 29
9.3 Power Dissipation ................................................... 29
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 17
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8.1 Application Information............................................ 24
8.2 Typical Applications ................................................ 24
17
17
18
23
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
Application and Implementation ........................ 24
4 Revision History
2
DATE
REVISION
NOTES
August 2019
*
Initial release.
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5 Pin Configuration and Functions
GND
ERROR
GND
COMP2
COMP1
20
19
18
17
16
RTJ Package
20-Pin WQFN
Top View
BSEL
1
15
OR
RSEL1
2
14
AINN
RSEL0
3
13
AINP
REFOUT
4
12
DRV1
REFIN
5
11
DRV2
6
7
8
9
10
VOUT
GND
VDD
VDD
GND
Thermal Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
AINN
14
I
Inverting input of the shunt-sense amplifier
AINP
13
I
Noninverting input of the shunt-sense amplifier
BSEL
1
I
Filter bandwidth select input
COMP1
16
I
Internal compensation coil input 1
COMP2
17
I
Internal compensation coil input 2
DRV1
12
O
Compensation coil driver output 1
DRV2
11
O
Compensation coil driver output 2
ERROR
19
O
Error flag: open-drain, active-low output
7, 10, 18, 20
—
Ground reference
OR
15
O
Shunt-sense amplifier overrange indicator: open-drain, active-low output
REFIN
5
I
Common-mode reference input for the shunt-sense amplifier
REFOUT
4
O
Voltage reference output
RSEL0
3
I
Voltage reference mode selection input 0
RSEL1
2
I
Voltage reference mode selection input 1
8, 9
—
Supply voltage, 3.0 V to 5.5 V. Decouple both pins using 1-µF ceramic capacitors placed as
close as possible to the device. See the Power Supply Decoupling and Layout sections for
further details.
6
O
Shunt-sense amplifier output
Thermal Pad
—
Connect the thermal pad to GND
GND
VDD
VOUT
Thermal Pad
DESCRIPTION
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.3
6.5
Input voltage, except AINP and AINN pins (2)
GND – 0.5
VDD + 0.5
Shunt-sense amplifier inputs (AINP and AINN pins) (3)
GND – 6.0
VDD + 6.0
–300
300
Supply voltage (VDD to GND)
Voltage
DRV1 and DRV2 pins (short-circuit current, IOS) (4)
Current
Shunt-sense amplifier input pins AINP and AINN
Temperature
(1)
(2)
(3)
(4)
–5
5
All remaining pins
–25
25
Junction, TJ
–50
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited, except for the differential amplifier input pins.
These inputs are not diode-clamped to the power-supply rails.
Power-limited; observe maximum junction temperature.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
HBM ESD classification level 2
Electrostatic discharge
UNIT
(1)
±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VDD
Supply voltage range (VDD to GND)
3.0
5.0
5.5
UNIT
V
TA
Specified ambient temperature
–40
125
°C
6.4 Thermal Information
DRV425-Q1
THERMAL METRIC (1)
RTJ (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
34.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.1
°C/W
RθJB
Junction-to-board thermal resistance
11
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
11
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics
all minimum and maximum specifications are at TA = 25°C, VDD = 3.0 V to 5.5 V, and IDRV1 = IDRV2 = 0 mA (unless otherwise
noted); typical values are at VDD = 5.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–8
±2
8
UNIT
FLUXGATE SENSOR FRONT-END
G
Offset
No magnetic field
Offset drift
No magnetic field
Gain
Current at DRV1 and DRV2 outputs
±5
12.2
Gain error
µT
nT/°C
mA/mT
±0.04%
Gain drift
Best-fit line method
±7
Linearity error
ppm/°C
0.1%
Hysteresis
Magnetic field sweep from –10 mT to 10 mT
1.4
µT
Noise
f = 0.1 Hz to 10 Hz
17
nTrms
Noise density
f = 1 kHz
Compensation range
Saturation trip level for the
ERROR pin (1)
Open-loop, uncompensated field
ERROR delay
BW
Bandwidth
IOS
Short-circuit current
1.5
–2
nT/√Hz
2
mT
1.6
mT
Open-loop at B > 1.6 mT
4 to 6
µs
BSEL = 0, RSHUNT = 22 Ω
32
BSEL = 1, RSHUNT = 22 Ω
47
VDD = 5 V
250
VDD = 3.3 V
150
Common-mode output voltage at the
DRV1 and DRV2 pins
Compensation coil resistance
kHz
mA
VREFOUT
V
100
Ω
SHUNT-SENSE AMPLIFIER
VOO
Output offset voltage
VAINP = VAINN = VREFIN, VDD = 3.0 V
Output offset voltage drift
CMRR
Common-mode rejection ratio, RTO (2)
VCM = –1 V to VDD + 1 V, VREFIN = VDD / 2
PSRRAMP
Power-supply rejection ratio, RTO (2)
VDD = 3.0 V to 5.5 V, VCM = VREFIN
VICR
Common-mode input voltage range
zid
Differential input impedance
zic
Common-mode input impedance
Gnom
Nominal gain
EG
Gain error
–0.075
±0.01
0.075
–2
±0.4
2
µV/°C
–250
±50
250
µV/V
–86
±4
86
µV/V
–1
Gain error drift
V
kΩ
20
23.5
40
50
60
4
±0.02%
0.3%
–5
±1
5
12
Voltage output swing from negative
rail (OR pin trip level) (1)
48
85
VDD = 3.0 V, IVOUT = 2.5 mA
56
100
Voltage output swing from positive rail
(OR pin trip level) (1)
VDD = 5.5 V, IVOUT = –2.5 mA
VDD – 85
VDD – 48
VDD = 3.0 V, IVOUT = –2.5 mA
VDD – 100
VDD – 56
IOS
Short-circuit current
BW–3dB
Bandwidth
SR
Slew rate
VIN = 1-V step
–18
VOUT connected to VDD
20
Large signal
ΔV = ± 2 V to 1%, no external filter
Small signal
ΔV = ± 0.4 V to 0.01%
tsa
Settling time
en
Output voltage noise density
f = 1 kHz, compensation loop disabled
VREFIN
Input voltage range at pin REFIN
Input voltage range at REFIN pin
µs
mA
2
MHz
6.5
V/µs
0.9
µs
8
170
GND
mV
mV
2.5 to 3.5
VOUT connected to GND
ppm/°C
ppm
VDD = 5.5 V, IVOUT = 2.5 mA
Signal overrange indication delay
(OR pin) (1)
kΩ
V/V
–0.3%
Linearity error
(1)
(2)
VDD + 1
16.5
VVOUT / (VAINP – VAINN)
mV
nV/√Hz
VDD
V
See the Magnetic Field Range, Overrange Indicator, and Error Flag section for details on the behavior of the ERROR and OR outputs.
Parameter value is referred-to-output (RTO).
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Electrical Characteristics (continued)
all minimum and maximum specifications are at TA = 25°C, VDD = 3.0 V to 5.5 V, and IDRV1 = IDRV2 = 0 mA (unless otherwise
noted); typical values are at VDD = 5.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE
Reference output voltage at the
REFOUT pin
VREFOUT
PSRRREF
ΔVO(ΔIO)
IOS
RSEL[1:0] = 00, no load
2.45
2.5
2.55
RSEL[1:0] = 01, no load
1.6
1.65
1.7
RSEL[1:0] = 1x, no load
45
50
55
% of
VDD
V
Reference output voltage drift
RSEL[1:0] = 0x
–50
±10
50
ppm/°C
Voltage divider gain error drift
RSEL[1:0] = 1x
–50
±10
50
ppm/°C
Power-supply rejection ratio
RSEL[1:0] = 0x
–300
±15
300
µV/V
RSEL[1:0] = 0x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C
0.15
0.35
RSEL[1:0] = 1x, load to GND or VDD,
ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C
0.3
0.8
Load regulation
Short-circuit current
mV/mA
REFOUT connected to VDD
20
mA
REFOUT connected to GND
–18
mA
DIGITAL INPUTS/OUTPUTS (CMOS)
IIL
Input leakage current
VIH
High-level input voltage
TA = –40°C to +125°C
0.7 × VDD
0.01
VDD + 0.3
µA
V
VIL
Low-level input voltage
TA = –40°C to +125°C
–0.3
0.3 × VDD
V
VOH
High-level output voltage
Open-drain output
VOL
Low-level output voltage
4-mA sink current
Set by external pullup resistor
V
0.3
V
POWER SUPPLY
IQ
VPOR
6
Quiescent current
IDRV1/2 = 0 mA, 3.0 V ≤ VDD ≤ 3.6 V,
TA = –40°C to +125°C
6
8
IDRV1/2 = 0 mA, 4.5 V ≤ VDD ≤ 5.5 V,
TA = –40°C to +125°C
7
10
Power-on reset threshold
mA
2.4
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6.6 Typical Characteristics
50
40
40
D001
Offset (PT)
3
3
2
2
1
1
0
-1
8
7
6
5
4
3
2
1
-1
-2
-3
-3
5
Device 1
Device 2
Device 3
0
-2
-4
-4
-40
5.5
-25
-10
5
D003
Figure 3. Fluxgate Sensor Front-End Offset vs
Supply Voltage
20 35 50 65
Temperature (°C)
80
95
110 125
D004
Figure 4. Fluxgate Sensor Front-End Offset vs
Temperature
50
100
40
80
Devices (%)
30
20
60
40
20
10
D005
Figure 5. Fluxgate Sensor Front-End Offset Drift Histogram
12.3
12.28
12.26
12.24
12.22
12.2
12.18
12.16
12.14
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Offset Drift (nT/qC)
12.12
0
0
12.1
Devices (%)
0
Figure 2. Fluxgate Sensor Front-End Offset Histogram
4
Offset (PT)
Offset (PT)
Figure 1. Fluxgate Sensor Front-End Offset Histogram
4
4.5
Supply Voltage (V)
-1
VDD = 3.3 V
4
3.5
D002
Offset (PT)
VDD = 5 V
3
-2
-3
-8
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
0
-5
0
-6
10
-7
10
-4
20
-5
20
30
-6
30
-7
Devices (%)
50
-8
Devices (%)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
D046
Gain (mA/mT)
Figure 6. Fluxgate Sensor Front-End Gain Histogram
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Typical Characteristics (continued)
12.35
12.35
12.3
12.3
12.25
12.25
Gain (mA/mT)
Gain (mA/mT)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
12.2
12.15
12.1
Device 1
Device 2
Device 3
12.2
12.15
12.1
12.05
3
3.5
4
4.5
Supply Voltage (V)
5
12.05
-40
5.5
-25
-10
D008
Figure 7. Fluxgate Sensor Front-End Gain vs
Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
D009
Figure 8. Fluxgate Sensor Front-End Gain vs Temperature
50
0.2
0.175
40
Linearity (%)
Devices (%)
0.15
30
20
0.125
0.1
0.075
0.05
10
0.025
0.14
0.13
0.12
0.11
0.1
0.09
0.08
0.07
0.06
0.05
0
0
3
3.5
D057
4
4.5
Supply Voltage (V)
5
5.5
D010
Linearity (%)
Figure 9. Fluxgate Sensor Front-End Linearity Histogram
Figure 10. Fluxgate Sensor Front-End Linearity vs
Supply Voltage
100
0.2
Device 1
Device 2
Device 3
Noise Density (nT/—Hz)
0.175
Linearity (%)
0.15
0.125
0.1
0.075
0.05
10
1
0.025
0
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D011
Figure 11. Fluxgate Sensor Front-End Linearity vs
Temperature
8
0.1
0.0001
0.001
0.01
0.1
1
Noise Frequency (kHz)
10
100
D006
Figure 12. Fluxgate Sensor Front-End Noise Density vs
Noise Frequency
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Typical Characteristics (continued)
80
70
70
60
60
50
50
D007
Saturation Trip Level (mT)
2.1
2
1.9
1.8
1.3
2.1
2
1.9
0
1.8
0
1.7
10
1.6
10
1.5
20
1.4
20
1.7
30
1.6
30
40
1.5
40
1.4
Devices (%)
80
1.3
Devices (%)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
D013
Saturation Trip Level (mT)
VDD = 5 V
VDD = 3.3 V
Figure 13. Fluxgate Sensor Saturation (ERROR Pin)
Trip Level Histogram
Figure 14. Fluxgate Sensor Saturation (ERROR Pin)
Trip Level Histogram
2
60
50
1.8
1.7
Devices (%)
1.6
1.5
40
30
20
1.4
10
1.3
114
112
110
108
D052
106
0
110 125
104
95
102
80
100
20 35 50 65
Temperature (°C)
98
5
96
-10
94
-25
90
1.2
-40
92
Saturation Trip Level (mT)
1.9
D053
Compensation Coil Resistance (:)
Figure 16. Compensation Coil Resistance Histogram
150
70
140
60
130
50
30
90
20
80
10
D054
0
50
110 125
40
95
30
80
20
20 35 50 65
Temperature (°C)
10
5
0
-10
-10
-25
-50
70
-40
-20
100
40
-30
110
-40
120
Devices (%)
Compensation Coil Resistance (:)
Figure 15. Fluxgate Sensor Saturation (ERROR Pin) Trip
Level vs Temperature
Output Offset (PV)
D015
VDD = 5 V
Figure 17. Compensation Coil Resistance vs Temperature
Figure 18. Shunt-Sense Amplifier Output Offset Histogram
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Typical Characteristics (continued)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
70
75
60
50
Output Offset (PV)
Devices (%)
50
40
30
20
25
0
-25
50
40
30
20
10
0
-10
-20
-75
-30
0
-40
-50
-50
10
3
3.5
4
4.5
Supply Voltage (V)
D015
D016
Output Offset (PV)
5
5.5
D018
VDD = 3.3 V
Figure 20. Shunt-Sense Amplifier Output Offset vs
Supply Voltage
Figure 19. Shunt-Sense Amplifier Output Offset Histogram
75
50
Device 1
Device 2
Device 3
40
25
Devices (%)
Output Offset (PV)
50
0
30
20
-25
10
-50
0
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-250
-225
-200
-175
-150
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
175
200
225
250
-75
-40
110 125
Common-Mode Rejection Ratio (PV/V)
D017
Figure 21. Shunt-Sense Amplifier Output Offset vs
Temperature
Figure 22. Shunt-Sense Amplifier CMRR Histogram
70
60
80
50
Devices (%)
60
40
40
30
20
20
Figure 23. Shunt-Sense Amplifier CMRR vs
Input Signal Frequency
Power-Supply Rejection Ratio (PV/V)
D020
50
40
30
20
10
0
-10
1000
-20
1
10
100
Input Signal Frequency (kHz)
-30
0
0.1
-40
0
0.01
10
-50
Common-Mode Rejection Ratio (dB)
100
10
D019
D021
Figure 24. Shunt-Sense Amplifier PSRR Histogram
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Typical Characteristics (continued)
100
100
80
80
Devices (%)
60
40
60
40
20
20
60
58
56
54
52
50
1000
48
100
46
1
10
Ripple Frequency (kHz)
44
0.1
42
0
0
0.01
40
Power-Supply Rejection Ratio (dB)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
D023
AINP Input Impedance (k:)
D022
Figure 26. Shunt-Sense Amplifier AINP Input Impedance
Histogram
Figure 25. Shunt-Sense Amplifier PSRR vs
Ripple Frequency
50
51
40
50.6
50.4
Devices (%)
50.2
50
49.8
30
20
49.6
10
49.4
49.2
12
11.75
11
10
9.5
9
8.5
11.5
110 125
11.25
95
10.5
80
10.75
20 35 50 65
Temperature (°C)
10.25
5
9.75
-10
9.25
-25
8.75
0
8
49
-40
8.25
AINP Input Impedance (k:)
50.8
D025
AINN Input Impedance (k:)
D024
Figure 27. Shunt-Sense Amplifier AINP Input Impedance
vs Temperature
Figure 28. Shunt-Sense Amplifier AINN Input Impedance
Histogram
100
11
80
10.6
10.4
Devices (%)
AINN Input Impedance (k:)
10.8
10.2
10
9.8
60
40
9.6
20
9.4
9.2
D026
0.1
0.08
0.06
0.04
110 125
0.02
95
0
80
-0.02
20 35 50 65
Temperature (°C)
-0.04
5
-0.06
-10
-0.08
0
-25
-0.1
9
-40
D027
Gain Error (%)
Including IFG, VDD = 5 V
Figure 29. Shunt-Sense Amplifier AINN Input Impedance
vs Temperature
Figure 30. Shunt-Sense Amplifier Gain Error Histogram
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Typical Characteristics (continued)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
100
0.3
0.25
0.2
80
Gain Error (%)
Devices (%)
0.15
60
40
0.1
0.05
0
-0.05
-0.1
-0.15
20
-0.2
-0.25
-0.3
-40
0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
-25
-10
D055
5
20 35 50 65
Temperature (°C)
80
95
110 125
D028
Gain Error (%)
Including IFG, VDD = 3.3 V
Figure 32. Shunt-Sense Amplifier Gain Error vs
Temperature
Figure 31. Shunt-Sense Amplifier Gain Error Histogram
20
40
35
Linearity Error (ppm)
Gain (dB)
15
10
5
30
25
20
15
10
5
0
0.01
0
0.1
1
10
100
Input Signal Frequency (kHz)
1000
10000
3
Figure 33. Shunt-Sense Amplifier Gain vs
Input Signal Frequency
5
5.5
D030
0.5
VDD = 5.5 V
VDD = 3.0 V
Voltage Difference to VDD or GND (V)
Voltage Difference to VDD or GND (V)
4
4.5
Supply Voltage (V)
Figure 34. Shunt-Sense Amplifier Linearity Error vs
Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
Output Current (mA)
8
9
10
3
3.5
D031
Figure 35. OR Pin Trip Level vs Output Current
12
3.5
D029
4
4.5
Supply Voltage (V)
5
5.5
D056
Figure 36. OR Pin Trip Level vs Supply Voltage
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Typical Characteristics (continued)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
4
VDD = 5.5 V
VDD = 3.0 V
3.75
0.4
3.5
Trip Delay (Ps)
Voltage Difference to VDD or GND (V)
0.5
0.3
0.2
3.25
3
2.75
2.5
0.1
2.25
0
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
2
-40
110 125
-25
Figure 37. OR Pin Trip Level vs Temperature
20 35 50 65
Temperature (°C)
80
95
110 125
D033
40
VOUT to GND
VOUT to VDD
VOUT to GND
VOUT to VDD
30
Short-Circuit Current (mA)
30
Short-Circuit Current (mA)
5
Figure 38. OR Pin Trip Delay vs Temperature
40
20
10
0
-10
-20
-30
20
10
0
-10
-20
-30
-40
3
3.5
4
4.5
Supply Voltage (V)
5
-40
-40
5.5
-25
-10
5
D035
Figure 39. Shunt-Sense Amplifier Output Short-Circuit
Current vs Supply Voltage
20 35 50 65
Temperature (°C)
80
95
110 125
D034
Figure 40. Shunt-Sense Amplifier Output Short-Circuit
Current vs Temperature
0.25
0.25
0.2
0.2
0.15
0.15
VVOUT
VAINP - VAINN
0.1
Voltage (V)
0.1
Voltage (V)
-10
D032
0.05
0
-0.05
0.05
0
-0.05
-0.1
-0.1
-0.15
-0.15
VVOUT
VAINP - VAINN
-0.2
-0.25
-2.5
0
2.5
5
7.5
10
Time (Ps)
12.5
15
-0.2
17.5
-0.25
-2.5
D012
Rising edge
0
2.5
5
7.5
10
Time (Ps)
12.5
15
17.5
D049
Falling edge
Figure 41. Shunt-Sense Amplifier Small-Signal
Settling Time
Figure 42. Shunt-Sense Amplifier Small-Signal
Settling Time
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Typical Characteristics (continued)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
1.25
1.25
1
1
0.75
0.75
0.5
Voltage (V)
0.5
0.25
0
-0.25
0.25
0
-0.25
-0.5
-0.5
-0.75
-0.75
VVOUT
VAINP - VAINN
-1
-1.25
-0.5
0
0.5
1
Time (Ps)
1.5
2
-1
-1.25
-0.5
2.5
0
0.5
Rising edge
2
2.5
D051
Figure 44. Shunt-Sense Amplifier Large-Signal
Settling Time
5
5
VAINP - VAINN
VVOUT
4
3
3
2
2
1
0
-1
1
0
-1
-2
-2
-3
-3
-4
-4
-5
-0.1
-0.075 -0.05 -0.025
0
0.025
Time (ms)
0.05
0.075
VAINP - VAINN
VVOUT
4
Voltage (V)
-5
-0.1
0.1
D036
-0.075 -0.05 -0.025
0
0.025
Time (ms)
VDD = 5 V
0.05
0.075
0.1
D037
VDD = 3.3 V
Figure 45. Shunt-Sense Amplifier Overload Recovery
Response
Figure 46. Shunt-Sense Amplifier Overload Recovery
Response
10000
70
60
50
Devices (%)
1000
100
40
30
20
10
2.505
2.504
2.503
2.502
2.501
D038
2.498
100000
2.497
1000
10000
Noise Frequency (Hz)
2.496
0
100
2.495
10
10
2.5
Voltage (V)
1.5
Falling edge
Figure 43. Shunt-Sense Amplifier Large-Signal
Settling Time
Output Voltage Noise Density (nV/—Hz)
1
Time (Ps)
D050
2.499
Voltage (V)
VVOUT
VAINP - VAINN
D039
Reference Voltge (V)
VREFOUT = 2.5 V
Figure 47. Shunt-Sense Amplifier Output Voltage Noise
Density vs Noise Frequency
14
Figure 48. Reference Voltage Histogram
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Typical Characteristics (continued)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
3
60
2.8
Reference Voltage (V)
70
Devices (%)
50
40
30
20
2.6
2.4
2.2
2
1.8
1.655
1.654
1.653
1.652
1.651
1.65
1.649
1.4
1.648
0
1.647
1.6
1.646
10
1.645
RSEL[1:0] = 00
RSEL[1:0] = 01
3
3.5
D058
4
4.5
Supply Voltage (V)
5
5.5
D042
Reference Voltage (V)
VREFOUT = 1.65 V
Figure 50. Reference Voltage vs Supply Voltage
Figure 49. Reference Voltage Histogram
3
2.55
Device 1
Device 2
Device 3
2.54
Reference Voltage (V)
Reference Voltage (V)
2.53
RSEL[1:0] = 00
RESL[1:0] = 01
RSEL[1:0] = 1x
2.8
2.52
2.51
2.5
2.49
2.48
2.6
2.4
2.2
2
1.8
2.47
1.6
2.46
2.45
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
1.4
-5
110 125
Figure 51. Reference Voltage vs Temperature
-3
-2
-1
0
1
2
Referene Current (mA)
3
4
5
D043
Figure 52. Reference Voltage vs Reference Output Current
30
50
25
40
20
15
10
30
20
10
0
0
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
5
D041
Reference Voltage Drift (ppm/qC)
-300
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
30
60
90
120
150
180
210
240
270
300
Devices (%)
Devices (%)
-4
D040
D044
Power-Supply Rejection Ratio (PV/V)
Figure 53. Reference Voltage Drift Histogram
Figure 54. Reference Voltage PSRR Histogram
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Typical Characteristics (continued)
at VDD = 5 V and TA = 25°C (unless otherwise noted)
100
30
REFOUT to GND
REFOUT to VDD
25
Short-Circuit Current (mA)
Devices (%)
80
60
40
20
20
15
10
5
0
-5
-10
-15
0.3
0.35
0.2
0.25
0.15
0.1
0
0.05
-0.1
-0.05
-0.2
-0.15
-0.25
-0.3
-0.35
0
-20
-40
-25
-10
5
20 35 50 65
Temperature (°C)
D045
80
95
110 125
D060
Load Regulation (mV/mA)
Figure 56. Reference Short-Circuit Current vs Temperature
Figure 55. Reference Voltage Load Regulation Histogram
10
10
VDD = 3.3 V
VDD = 5 V
9
Quiescent Current (mA)
Quiescent Current (mA)
9.5
8
7
9
8.5
8
7.5
7
6.5
6
6
5.5
5
-40
5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D048
Figure 58. Quiescent Current vs Temperature
Figure 57. Quiescent Current vs Supply Voltage
2.55
40
VDD = 3.3 V
VDD = 5 V
35
30
Reset Threshold (V)
Supply Current (mA)
-25
D061
25
20
15
10
2.45
2.35
5
0
0
0.25
0.5
0.75
1
1.25
Magnetic Field (mT)
1.5
1.75
2.25
-40
-25
D014
Figure 59. Supply Current vs Magnetic Field
16
2
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D047
Figure 60. Power-On Reset Threshold vs Temperature
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7 Detailed Description
7.1 Overview
Magnetic sensors are used in a broad range of applications, such as position, indirect ac and dc current, or
torque measurement. Hall-effect sensors are most commonly used in magnetic field sensing, but offset, noise,
gain variation, and nonlinearity limit the achievable resolution and accuracy of the system. Fluxgate sensors offer
significantly higher sensitivity, lower drift, lower noise, high linearity, and enable up to 1000-times better
measurement accuracy.
As shown in the Functional Block Diagram section, the DRV425-Q1 consists of a magnetic fluxgate sensor with
the necessary sensor conditioning and compensation coil to internally close the control loop. The fluxgate sensor
is repeatedly driven in and out of saturation, and supports hysteresis-free operation with excellent accuracy. The
internal compensation coil assures stable gain and high linearity.
The magnetic field, B, is detected by the internal fluxgate sensor in the DRV425-Q1. The device integrates the
sensor output to assure high-loop gain. The integrator output connects to the built-in differential driver that drives
an opposing compensation current through the internal compensation coil. The compensation coil generates an
opposite magnetic field that brings the original magnetic field at the sensor back to zero.
The compensation current is proportional to the external magnetic field, with a value of 12.2 mA/mT. This
compensation current generates a voltage drop across an external shunt resistor, RSHUNT. An integrated
difference amplifier with a fixed gain of 4 V/V measures this voltage and generates an output voltage that is
referenced to REFIN, and is proportional to the magnetic field. The value of the output voltage at the VOUT pin
(VVOUT) is calculated using Equation 1:
VVOUT [V] = B × G × RSHUNT × GAMP = B [mT] × 12.2 mA/mT × RSHUNT [Ω] × 4 [V/V]
(1)
7.2 Functional Block Diagram
RSHU NT
COMP1
COMP2
DRV2
DRV1
Fluxgate Sensor Front-End
Compensation
Coil
Inte grator
Fluxgate
Sen sor
AINP
AINN
Shu nt
Sen se
Amplifier
Differen tia l
Driver
VOUT
REFIN
Device Control
OR
ERROR BSE L
DRV425-Q1
Voltage Reference
RSEL0
REFOUT
RSEL1
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7.3 Feature Description
7.3.1 Fluxgate Sensor Front-End
The following sections describe the functional blocks and features of the integrated fluxgate sensor front-end.
7.3.1.1 Fluxgate Sensor
The fluxgate sensor of the DRV425-Q1 is uniquely designed for high-performance magnetic-field sensors
because of the high sensitivity, low noise, and low offset of the sensor. The fluxgate principle relies on repeatedly
driving the sensor in and out of saturation; therefore, the sensor is free of any significant magnetic hysteresis.
The feedback loop accurately drives a compensation current through the integrated compensation coil and drives
the magnetic field at the sensor back to zero. This approach supports excellent gain stability and high linearity of
the measurement.
The device package is free of any ferromagnetic materials in order to prevent magnetization by external fields
and to obtain accurate and hysteresis-free operation. Select materials that cannot be magnetized for the printed
circuit board (PCB) and passive components in the direct vicinity of the DRV425-Q1; see the Layout Guidelines
section for more details.
The orientation and the sensitivity axis of the fluxgate sensor is indicated by a dashed line on the top of the
package, as shown in Figure 61. The figure also shows the location of the sensor inside the package.
1.74 mm ± 0.025 mm
Sen sitivity Axi s In dicatio n
(Top View)
Sen sor Lo cation
(Top View)
Sen sor Lo cation
(Side Vi ew)
>
0.4 mm ± 0.025 mm
Top
DRV425-Q1
TI Date
Code
Bottom
2 mm ± 0.025 mm
Figure 61. Magnetic Sensitivity Direction of the Integrated Fluxgate Sensor
The sensitivity of the fluxgate sensor is a vector function of the sensitivity axis and the magnitude of the magnetic
field along that axis. Figure 62 shows the output of the DRV425-Q1 versus the angle of the device orientation
relative to a constant magnetic field.
2.65
2.6
VVOUT (V)
2.55
2.5
2.45
2.4
2.35
0
30
60
90 120 150 180 210 240 270 300 330 360
Angle (q)
D063
Figure 62. Device Output vs Magnetic Field Orientation
18
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Feature Description (continued)
7.3.1.2 Bandwidth
The small-signal bandwidth of the DRV425-Q1 is determined by the behavior of the compensation loop versus
frequency. The implemented integrator limits the bandwidth of the loop to provide a stable response. Use digital
input pin BSEL to select the bandwidth. With a shunt resistor of 22 Ω and BSEL = 0, the bandwidth is 32 kHz; for
BSEL = 1, the bandwidth is 47 kHz.
The shunt resistor and the compensation coil resistance form a voltage divider; therefore, to reduce the
bandwidth, increase the value of the shunt resistor. To calculate the reduced bandwidth (BW), use Equation 2:
RCOIL 22 :
122 :
u BW22 :
u BW22 :
BW
RCOIL RSHUNT
100 : RSHUNT
where
•
•
•
RCOIL = internal compensation coil resistance (100 Ω).
RSHUNT = external shunt resistance.
BW22Ω = sensor bandwidth with RSHUNT = 22 Ω (depending on the BSEL setting).
(2)
The bandwidth for a given shunt resistor value can also be calculated using the DRV425 System Parameter
Calculator. For large magnetic fields (B > 500 μT), the effective bandwidth of the sensor is limited by fluxgate
saturation effects. For a magnetic signal with a 2-mT amplitude, the large-signal bandwidth is 10 kHz with BSEL
= 0, or 15 kHz with BSEL = 1.
Although the analog output responds slowly to large fields, a magnetic field with a magnitude ≥ 1.6 mT beyond
the measurement range of the DRV425-Q1 triggers the ERROR pin within 4 µs to 6 µs. See the Magnetic Field
Range, Overrange Indicator, and Error Flag section for more details.
7.3.1.3 Differential Driver for the Internal Compensation Coil
The differential compensation coil driver provides the current for the internal compensation coil at the DRV1 and
DRV2 pins. The driver is capable of sourcing up to ±250 mA with a 5-V supply, or up to ±150 mA with a 3.3-V
supply. The current capability is not internally limited. The actual value of the compensation coil current depends
on the magnetic field strength, and is limited by the sum of the resistance of the internal compensation coil and
the external shunt resistor value. The internal compensation coil resistance depends on temperature (see
Figure 17), and this dependancy must be taken into account when designing the system. Select the value of the
shunt resistor to avoid OR pin trip levels in normal operation.
The common-mode voltage of the compensation coil driver outputs is set by the RSEL pins; see the Voltage
Reference section. Thus, the common-mode voltage of the shunt-sense amplifier is matched if the internal
reference is used.
Consider the polarity of the compensation coil connection to the output of the compensation coil driver. If the
polarity is incorrect, then the driver output drives to the power-supply rails, even at low primary-current levels. In
this case, interchange the connection of the DRV1 and DRV2 pins to the compensation coil.
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Feature Description (continued)
7.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
The measurement range of the DRV425-Q1 is determined by the amount of current driven into the compensation
coil and the output voltage range of the shunt-sense amplifier. The maximum compensation current is limited by
the supply voltage and the series resistance of the compensation coil and the shunt.
The magnetic field range is adjusted with the external shunt resistor. The DRV425 System Parameter Calculator
provides the maximum shunt resistor values depending on the supply voltage (VDD) and the selected reference
voltage (VREFIN) for various magnetic field ranges.
For proper operation at a maximum field (BMAX), choose a shunt resistor (RSHUNT) using Equation 3:
RSHUNT d
min VDD VREFIN ,VREFIN
0.085 V
BMAX u 12.2 A/T u 4 V/V
where
•
•
•
VDD = minimum supply voltage of the DRV425-Q1 (V).
VREFIN = common-mode voltage of the shunt-sense amplifier (V).
BMAX = desired magnetic field range (T).
(3)
Alternatively, to adjust the output voltage of the DRV425-Q1 for a desired maximum voltage (VVOUTMAX), use
Equation 4:
VVOUTMAX VREFIN
RSHUNT d
BMAX u 12.2 A/T u 4 V/V
where
•
•
VVOUTMAX = desired maximum output voltage at VOUT pin (V).
BMAX = desired magnetic field range (T).
(4)
To avoid railing of the compensation coil driver, make sure that Equation 5 is fulfilled:
BMAX u (RCOIL RSHUNT ) u 12.2A / T
0.1V d min VDD VREFIN ,VREFIN
2
where
•
•
•
•
BMAX = desired magnetic field range (T).
RCOIL = compensation coil resistance (Ω).
VDD = minimum supply voltage of the DRV425-Q1 (V).
VREFIN = selected internal reference voltage value (V).
(5)
The DRV425 System Parameter Calculator is designed to assist with selecting the system parameters.
The DRV425-Q1 offers two diagnostic output pins to detect large fields that exceed the measurement range of
the sensor: the overrange indicator (OR) and the ERROR flag.
In normal operation, the DRV425-Q1 sensor feedback loop compensates the magnetic field inside the fluxgate to
zero. Therefore, a large field inside the fluxgate indicates that the feedback loop is not properly working, and the
sensor output is invalid. To detect this condition, the ERROR pin is pulled low if the internal field exceeds 1.6
mT. The ERROR output is suppressed for 4 µs to 6 µs to prevent an undesired reaction to transients or noise.
For static and slowly varying ambient fields, the ERROR pin triggers when the ambient field exceeds the sensor
measurement range by more than 1.6 mT. For dynamic magnetic fields that exceed the sensor bandwidth as
specified in the Specifications section, the feedback loop response is too slow to accurately compensate the
internal field to zero. Therefore, high-frequency fields can trigger the ERROR pin, even if the ambient field does
not exceed the measurement range by 1.6 mT.
In addition, the active-low overrange pin (OR) indicates railing of the output of the shunt-sense amplifier. The OR
output is suppressed for 2.5 µs to 3.5 µs to prevent an undesired reaction to transients or noise. The OR pin trip
level refers to the output voltage value of the shunt-sense amplifier, as specified in the Specifications section.
Use Equation 3 and Equation 4 to adjust the OR pin behavior to the specific system-level requirements.
Both the ERROR and OR pins are open-drain outputs that require an external pullup resistor. If desired, connect
both pins together with a single pullup resistor to provide a single diagnostic flag.
20
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Feature Description (continued)
Based on the DRV425 System Parameter Calculator, for a design for a ±2-mT magnetic field input range with a
supply of 5 V (±5%), a shunt resistor value of 22 Ω is selected. Figure 63 shows the status of the diagnostic flags
in the resulting three operation ranges.
Sensor Saturation: B > 3.6 mT
(OR = 0, ERROR = 0)
4
Magnetic Field B (mT)
3
Magnetic Overrange: 2 mT < % ” 3.6 mT
(OR = 0, ERROR = 1)
2
1
0
Designated Operating Range: 2 P7 ” % ” 2 mT
(OR = 1, ERROR = 1)
1
2
3
Magnetic Overrange: 3.6 P7 ” % < 2 mT
(OR = 0, ERROR = 1)
4
Sensor Saturation: B < 3.6 mT
(OR = 0, ERROR = 0)
Figure 63. Magnetic Field Range of the DRV425-Q1 (VDD = 5 V and RSHUNT = 22 Ω)
With the proper RSHUNT value, the differential amplifier output rails and activates the overrange flag (OR = 0)
when the magnetic field exceeds the designated operating range. For fields that exceed the measurement range
of the DRV425-Q1 by ≥ 1.6 mT, the fluxgate is saturated and the ERROR pin is pulled low. In this condition, the
fluxgate sensor does not provide a valid output value; therefore, the output VOUT of the DRV425-Q1 must be
ignored. In applications where the ERROR pin cannot be separately monitored, combine the VOUT and ERROR
outputs as shown in Figure 64. This method indicates that a magnetic field is outside of the sensor range by
pulling the device output to ground.
BSEL
RSEL0
RSEL1
5V
1 k:
VDD
VDD
GND
VOUT
REFIN
TI Device REFOUT
OR
ERROR
GND
RSHUNT
DRV2
DRV1
AINP
AINN
COMP1
COMP2
1 µF
1 µF
5V
Figure 64. Field Overrange Detection Using a Combined VOUT and ERROR Pin
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Feature Description (continued)
7.3.2 Shunt-Sense Amplifier
The compensation coil current creates a voltage drop across the external shunt resistor, RSHUNT. The internal
differential amplifier senses this voltage drop. This differential amplifier offers wide bandwidth and a high slew
rate. Excellent dc stability and accuracy result from a chopping technique. The voltage gain is 4 V/V, set by
precisely matched and thermally stable internal resistors.
Both the AINN and AINP differential amplifier inputs are connected to the external shunt resistor. This shunt
resistor, in series with the internal 10-kΩ input resistors of the shunt-sense amplifier, causes an additional gain
error. Therefore, for best common-mode rejection performance, place a dummy shunt resistor (R5) with a value
higher than the shunt resistor in series with the REFIN pin to restore the matching of both resistor dividers, as
shown in Figure 65.
TI Device
AINN
R1
10 k
R2
40 k
_
Shunt-Sense
Amplifier
RSHUNT
VOUT
AINP
R4
40 k
Optional
ADC
CF
0 …F
+
R3
10 k
RF
500
REFIN
R5
(Dummy Shunt)
DRV1
REFIN
(Compensated)
DRV2
ICOMP2
ICOMP1
Figure 65. Internal Difference Amplifier With an Example of a Decoupling Filter
For an overall gain of 4 V/V, calculate the value of R5 using Equation 6:
R 4 + R5
R
4= 2 =
R1
RSHUNT + R3
where:
•
•
R2 / R1 = R4 / R3 = 4.
R5 = RSHUNT × 4.
(6)
If the input signal is large, the amplifier output drives close to the supply rails. The amplifier output is able to drive
the input of a successive approximation register (SAR) analog-to-digital converter (ADC). For best performance,
add an RC low-pass filter stage between the shunt-sense amplifier output and the ADC input. This filter limits the
noise bandwidth, and decouples the high-frequency sampling noise of the ADC input from the amplifier output.
For filter resistor RF and filter capacitor CF values, see the specific converter recommendations in the respective
product data sheet.
The shunt-sense amplifier output drives 100 pF directly, and shows a 50% overshoot with a 1-nF capacitance.
Filter resistor RF extends the capacitive load range. With an RF of only 20 Ω, the load capacitor must be either
less than 1 nF or more than 33 nF to avoid overshoot; with an RF of 50 Ω, this transient area is avoided.
Reference input REFIN is the common-mode voltage node for the output signal VOUT. To use the internal
voltage reference of the DRV425-Q1, connect the REFIN pin to the reference output REFOUT. To avoid
mismatch errors, use the same reference voltage for REFIN and the ADC. Alternatively, use an ADC with a
pseudodifferential input, with the positive input of the ADC connected to VOUT, and the negative input connected
to REFIN of the device.
22
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Feature Description (continued)
7.3.3 Voltage Reference
The internal precision voltage reference circuit offers low-drift performance at the REFOUT output pin, and is
used for internal biasing. The reference output is intended to be the common-mode voltage of the output (the
VOUT pin) to provide a bipolar signal swing. This low-impedance output tolerates sink and source currents of ±5
mA. However, fast load transients can generate ringing on this line. A small series resistor of a few ohms
improves the response, particularly for capacitive loads equal to or greater than 1 μF.
To adjust the value of the voltage reference output to the power supply of the DRV425-Q1, use mode selection
pins RSEL0 and RSEL1, as shown in Table 1.
Table 1. Reference Output Voltage Selection
MODE
RSEL1
RSEL0
DESCRIPTION
VREFOUT = 2.5 V
0
0
Use with a sensor module supply of 5 V
VREFOUT = 1.65 V
0
1
Use with a sensor module supply of 3.3 V
Ratiometric output
1
x
Provides an output centered on VDD / 2
In ratiometric output mode, an internal resistor divider divides the power-supply voltage by a factor of two.
7.3.4 Low-Power Operation
In applications with low-bandwidth or low sample-rate requirements, significantly reduce the average power
dissipation of the DRV425-Q1 by powering down the device between measurements. The DRV425-Q1 requires
300 μs to fully settle the analog output VOUT, as shown in Figure 66. To minimize power dissipation, power
down the device immediately after the ADC acquires the sample.
startup
VDD
VOUT
Settling time:
300 µs
Figure 66. Settling Time of the DRV425-Q1 VOUT Output
7.4 Device Functional Modes
The DRV425-Q1 is operational when the power supply VDD is applied, as specified in the Specifications section.
The DRV425-Q1 has no additional functional modes.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV425-Q1 is a high-sensitivity and high-performance magnetic-field sensor. The analog output of the
DRV425-Q1 can be processed by a 12-bit to 16-bit analog to digital converter (ADC). The following sections
show application design examples.
8.2 Typical Applications
8.2.1 Linear Position Sensing
The high sensitivity of the fluxgate sensor, combined with the high linearity of the compensation loop and low
noise of the DRV425-Q1, make the device an excellent choice for high-performance linear-position sense
applications. A typical schematic of such a 5-V application using an internal 2.5-V reference is shown in
Figure 67.
BSEL
RSEL0
RSEL1
5V
DRV2
DRV1
AINP
AINN
COMP1
COMP2
VOUT
REFIN
TI Device REFOUT
OR
ERROR
10 k:
1 µF
ADC
GPIO0
GPIO1
GND
VDD
VDD
GND
RSHUNT
MCU
10 k:
5V
1 µF
Figure 67. Linear-Position Sensing
8.2.1.1 Design Requirements
For the example shown in Figure 67, use the parameters listed in Table 2 as a starting point of the design.
Table 2. Design Parameters
DESIGN PARAMETER
Magnetic field range
Supply voltage, VDD
3.0 V to 5.5 V
Reference voltage, VREFIN
Shunt resistor, RSHUNT
24
EXAMPLE VALUE
VDD = 5 V: ±2 mT (max)
VDD = 3.3 V: ±1.3 mT (max)
Range: GND to VDD
If an internal reference is used: 2.5 V, 1.65 V, or VDD / 2
Depends on the desired magnetic field range, reference, and supply
voltage; see the DRV425 System Parameter Calculator for details.
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8.2.1.2 Detailed Design Procedure
Use the following procedure to design a solution for a linear-position sensor based on the DRV425-Q1:
1. Select the proper supply voltage, VDD, to support the desired magnetic field range (see Table 2 for
reference).
2. Select the proper reference voltage, VREFIN, to support the desired magnetic field range and to match the
input voltage specifications of the desired ADC.
3. Use the RangeCalculator tab in the DRV425 System Parameter Calculator to select the proper shunt resistor
value of RSHUNT.
4. The sensitivity drift performance of a DRV425-Q1 based linear position sensor is dominated by the
temperature coefficient of the external shunt resistor. Select a low-drift shunt resistor for best sensor
performance.
5. Use the Problems Detected Table in DRV425 System Parameters tab in the DRV425 System Parameter
Calculator to verify the system response.
The amplitude of the magnetic field is a function of distance to, and the shape of, the magnet, as shown in
Figure 69. If the magnetic field to be measured exceeds 3.6 mT, see the magnet datasheet to calculate the
appropriate minimum distance to the DRV425-Q1 to avoid saturating the fluxgate sensor.
The high sensitivity of the DRV425-Q1 may require shielding of the sensing area to avoid influence of undesired
magnetic field sources (such as the earth magnetic field). Alternatively, an additional DRV425-Q1 can be used to
perform difference measurement to cancel the influence of a static magnetic field source, as shown in Figure 68.
Figure 70 shows the differential voltage generated by two DRV425-Q1 devices in such a circuit.
DRV425-Q1-1
Directio n o f Linea r
Movement
DRV425-Q1-2
>
>
REFOUT
REFIN
VOUT
REFOUT
REFIN
VOUT
ADC
Figure 68. Differential Linear-Position Sensing Using Two DRV425-Q1 Devices
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VVOUTDRV425-1 - VVOUTDRV425-2 (mV)
VVOUT (V)
8.2.1.3 Application Curves
0
50
100
150
200 250 300
Distance (mm)
350
400
450
500
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
20
D064
Figure 69. Analog Output Voltage of the DRV425-Q1 vs
Distance to the Magnet
40
60
80 100 120
Distance (mm)
140
160
180
200
D065
Figure 70. Difference Between Two DRV425-Q1 Outputs vs
Distance to the Magnet
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8.2.2 Current Sensing in Busbars
In existing applications that use busbars for power distribution, closed-loop current modules are usually used to
accurately measure and control the current. These modules are usually bulky because of the required large
magnetic core. Additionally, because the compensation current generated inside the module is proportional to the
usually high busbar current, the power dissipation of this solution is usually as high as several watts.
Figure 71 shows an alternative approach with two DRV425-Q1 devices. If a hole is drilled in the middle of the
busbar, the current is split in two equal parts that generate magnetic field gradients with opposite directions
inside the hole. These magnetic fields are termed BR and BL in Figure 72. The opposite fields cancel each other
out in the middle of the hole. The high sensitivity and linearity of two DRV425-Q1 devices positioned at the same
distance from the middle of the hole allow the small opposite fields to be sensed and the current measured with
high-accuracy levels. The differential measurement rejects outside fields that generate a common-mode error
that is subtracted at the output.
Busbar
(Top View)
I/2
Hole
DRV425-Q1-1
I
I
DRV425-Q1-2
PCB
I/2
Figure 71. Current Sensing in Busbars
I
Axis of
cross-section
I/2
I/2
Cross-section
PCB
DRV425-Q1 - 1
BR
I/2
I/2
Y-Axis
BL
DRV425-Q1 - 2
Figure 72. Magnetic Field Distribution Inside a Busbar Hole
26
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8.2.2.1 Design Requirements
In order to measure the field gradient in the busbar, two DRV425-Q1 sensors are placed inside the hole at a
well-defined distance by mounting them on opposite sides of a PCB that is inserted in the hole. The
measurement range and resolution of this solution depends on the following factors:
• Busbar geometry: a wider busbar means a larger measurement range and lower resolution.
• Size of the hole: a larger diameter means a larger measurement range and lower resolution.
• Distance between the two DRV425-Q1 sensors: a smaller distance increases the measurement range and
resolution.
Each of these factors can be optimized to create the desired measurement range for a particular application.
Measurement ranges of ±250 A to ±1500 A are achievable with this approach. Larger currents are supported
with large busbar structures and minimized distance between the two DRV425-Q1 sensors. Use the parameters
listed in Table 3 as a starting point of the design.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Current range
Up to ±1500 A
Supply voltage, VDD
3.0 V to 5.5 V
Reference voltage, VREFIN
VDD / 2
8.2.2.2 Detailed Design Procedure
Figure 73 shows the schematic diagram of a differential gradient field measurement circuit.
BSEL
RSEL0
RSEL1
BSEL
RSEL0
RSEL1
VDD
1 µF
1 µF
1 µF
R1
5.1 :
VDIFF
GND
GND
VDD
VDD
VDD
DRV2
VOUT
DRV1
REFIN
AINP
U2
REFOUT
DRV425-Q1
AINN
OR
COMP1
ERROR
COMP2
VCM
GND
VDD
VDD
GND
DRV2
VOUT
DRV1
REFIN
AINP
U1
REFOUT
DRV425-Q1
AINN
OR
COMP1
ERROR
COMP2
1 µF
VDD
R2
5.1 :
VDD
10 k
1 …F
+
U3
OPA320
R3
10 :
VREF
10 k
±
Figure 73. Busbar Current-Sensing Circuit
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In Figure 73, the feedback loops of both DRV425-Q1 sensors are combined to directly produce differential output
VDIFF that is proportional to the sensed magnetic field difference inside the busbar hole. Both compensation coils
are connected in series and are driven from a single side of the compensation coil driver (the DRV1 pins of each
DRV425-Q1). Therefore, both driver stages make sure that a current proportional to the magnetic fields BR and
BL is driven through the respective compensation coil. The difference in current through both compensation coils,
and thus the difference field between the sensors, flows through resistor R3, and is sensed by the shunt-sense
amplifier of U2. The current proportional to the common-mode field inside the busbar hole flows through R1 and
R2, and is sensed by the shunt-sense amplifier of U1.
Use the output VCM to verify that the sensors are correctly positioned in the busbar hole with the following steps:
1. Measure VCM with no current flow through the busbar and the PCB in the middle of the busbar hole. This
value is the offset voltage VOFFSET. The value of VOFFSET only depends on stray fields and varies little with the
absolute position of the sensors.
2. Apply current through the busbar and move the PCB along the y-axis in the busbar hole, as shown in
Figure 72. The PCB is in the center of the hole if VCM = VOFFSET.
The sensitivity drift performance of the circuit shown in Figure 73 is dominated by the temperature coefficient of
the external resistors R1, R2, and R3. Select low-drift resistors for best sensor performance. For overall system
error calculation, also consider the affect of thermal expansion on the PCB and busbar.
The internal voltage reference of the DRV425-Q1 cannot be used in this application because of its limited driver
capability. The OPA320 (U3) is a low-noise operational amplifier with a short-circuit current capability of ±65 mA,
and is used to support the required compensation current.
The advantage of this solution is the simplicity: the currents are subtracted by the two DRV425-Q1 devices
without additional components. The series connection of the compensation coils halves the voltage swing, and
reduces the measurement range of the sensors also by 50%. If a larger sensing range is required, operate the
two sensors independently, and use a differential amplifier or ADC to subtract both voltage outputs (VOUT).
Use the ERROR outputs for fast overcurrent detection on the system level.
8.2.2.3 Application Curves
Figure 74 and Figure 75 show the measurement results on a 16-mm wide and 6-mm thick copper busbar with a
12-mm hole diameter using the circuit shown in Figure 73. The two DRV425-Q1 devices are placed at a distance
of 1 mm from each other on opposite sides of the PCB. The measurement range is ±500 A; measurement results
are limited by test setup. Independent operation of the two DRV425-Q1 sensors increases the measurement
range to ±1000 A with the same busbar geometry.
400
0.5
350
0.4
0.3
Linearity Error (%FS)
VDIFF - VREF (mV)
300
250
200
150
100
0.2
0.1
0
-0.1
-0.2
-0.3
50
-0.4
0
-0.5
0
20
40
60
80 100 120 140
Busbar Current (A)
160
180
0
20
D066
Figure 74. Analog Output Voltage vs
Busbar Current
28
200
40
60
80 100 120 140
Busbar Current (A)
160
180
200
D067
Figure 75. Linearity Error vs Busbar Current
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9 Power Supply Recommendations
9.1 Power Supply Decoupling
Decouple both VDD pins of the DRV425-Q1 with 1-µF, X7R-type ceramic capacitors to the adjacent GND pin, as
illustrated in Figure 76. For best performance, place both decoupling capacitors as as possible close to the
related power-supply pins. Connect these capacitors to the power-supply source in a way that allows the current
to flow through the pads of the decoupling capacitors.
9.2 Power-On Start-Up and Brownout
Power-on is detected when the supply voltage exceeds 2.4 V at the VDD pin. At this point, the DRV425-Q1
initiates the following start-up sequence:
1. Digital logic starts up and waits for 26 μs for the supply to settle.
2. The fluxgate sensor powers up.
3. The compensation loop is active 70 μs after the supply voltage exceeds 2.4 V.
During this startup sequence, the DRV1 and DRV2 outputs are pulled low to prevent undesired signals on the
compensation coil and the ERROR pin is asserted low.
The DRV425-Q1 tests for low supply voltages with a brownout-voltage level of 2.4 V. Use a power-supply source
capable of supporting large current pulses driven by the DRV425-Q1, and low-ESR bypass capacitors for a
stable supply voltage in the system. A supply drop to less than 2.4 V that lasts longer than 20 μs generates a
power-on reset; the device ignores shorter voltage drops. A voltage drop on the VDD pin to below 1.8 V
immediately initiates a power-on reset. After the power supply returns to 2.4 V, the device initiates a start-up
cycle.
9.3 Power Dissipation
The thermally-enhanced, WQFN package with thermal pad reduces the thermal impedance from junction to
case. This package has a downset leadframe to which the die is mounted. The leadframe has an exposed
thermal pad on the underside of the package, and provides a good thermal path for heat dissipation.
The power dissipation on both linear outputs DRV1 and DRV2 is calculated with Equation 7:
PD(DRV) = IDRV × (VDRV – VSUPPLY)
where
•
•
•
IDRV = supply current as shown in Figure 59.
VDRV = voltage potential on the DRV1 or DRV2 output pin.
VSUPPLY = voltage potential closer to VDRV: VDD or GND.
(7)
9.3.1 Thermal Pad
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
board layout greatly influences the overall heat dissipation. Technical details are described in the PowerPad
Thermally Enhanced Package, application report, available for download at www.ti.com.
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10 Layout
10.1 Layout Guidelines
The unique, integrated fluxgate of the DRV425-Q1 has a very high sensitivity that enables designing a closedloop magnetic-field sensor with best-in-class precision and linearity. Observe proper PCB layout techniques
because any current-conducting wire in the direct vicinity of the DRV425-Q1 generates a magnetic field that can
distort measurements. Common passive components and some PCB plating materials contain ferromagnetic
materials that are magnetizable. For best performance, use the following layout guidelines:
• Route current-conducting wires in pairs: route a wire with an incoming supply current next to, or on top of, the
return current path. The opposite magnetic field polarity of these connections cancel each other. To facilitate
this layout approach, the DRV425-Q1 positive and negative supply pins are located adjacently.
• Route the compensation coil connections close to each other as a pair to reduce coupling effects.
• Minimize the length of the compensation coil connections between the DRV1/2 and COMP1/2 pins.
• Route currents parallel to the fluxgate sensor sensitivity axis as illustrated in Figure 76. As a result, magnetic
fields are perpendicular to the fluxgate sensitivity and have limited affect.
• Vertical current flow (for example, through vias) generates a field in the fluxgate-sensitive direction. Minimize
the number of vias in the vicinity of the DRV425-Q1.
• Use passive components (for example, decoupling capacitors and the shunt resistor) that cannot be
magnetized to prevent magnetic effects near the DRV425-Q1.
• Do not use PCB trace finishes with nickel-gold plating because of the potential for magnetization.
• Connect all GND pins to a local ground plane.
Ferrite beads in series with the power-supply connection reduce interaction with other circuits powered from the
same supply voltage source. However, to prevent influence of the magnetic fields if ferrite beads are used, do
not place them next to the DRV425-Q1.
The reference output (the REFOUT pin) refers to GND. Use a low-impedance and star-type connection to reduce
the driver current and the fluxgate sensor current modulating the voltage drop on the ground track. The REFOUT
and VOUT outputs are able to drive some capacitive load, but avoid large direct capacitive loading because of
increased internal pulse currents. Given the wide bandwidth of the shunt-sense amplifier, isolate large capacitive
loads with a small series resistor.
Solder the exposed thermal pad on the bottom of the package to the ground layer because the thermal pad is
internally connected to the substrate that must be connected to the most-negative potential.
Figure 76 illustrates a generic layout example that highlights the placement of components that are critical to the
DRV425-Q1 performance. For specific layout examples, see the DRV425EVM users guide.
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10.2 Layout Example
Fluxgate sensor sensitivity axis
Keep this area free of components
creating magnetic fields.
COMP1
COMP2
GND
ERROR
GND
To MCU
To MCU
BSEL
OR
RSEL1
AINN
RSEL0
AINP
RSHUNT
1206
LEGEND
VDD
VDD
GND
X7R
0603
1 µF
X7R
0603
DRV2
GND
REFIN
1 µF
DRV1
VOUT
REFOUT
To ADC
Top Layer:
Copper Pour and Traces
Via to Ground Plane
Via to Supply Plane
Figure 76. Generic Layout Example (Top View)
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx320 Precision, 20-MHz, Low-Noise, Low-Power, RRIO, CMOS Op Amp With
Shutdown data sheet
• Texas Instruments, DRV425EVM user's guide
• Texas Instruments, DRV425 System Parameter Calculator
• Texas Instruments, PowerPad Thermally Enhanced Package application report
• Texas Instruments, ±100-A Busbar Current Sensor Reference Design Using Open-Loop Fluxgate Sensors
reference design TIPD205
• Texas Instruments, Bus Bar Theory of Operation application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RTJ0020J
WQFN - 0.8 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
0.5
0.3
0.3
0.2
PIN 1 INDEX AREA
DETAIL
4.1
3.9
OPTIONAL TERMINAL
TYPICAL
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 25.000
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
2.5 0.1
EXPOSED
THERMAL PAD
A3
2X 2
6
(0.2) TYP
4X ( 0.35)
10
A2
SEE TERMINAL
DETAIL
5
11
2X
2
A
21
(1.695)
TYP
SYMM
A
1
15
16X 0.5
A4
20X
A1
20
PIN 1 ID
(OPTIONAL)
SYMM
20X
16
0.3
0.2
0.1
0.05
C A B
0.5
0.3
(1.695) TYP
4223320/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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Product Folder Links: DRV425-Q1
33
DRV425-Q1
SBOS988 – AUGUST 2019
www.ti.com
EXAMPLE BOARD LAYOUT
RTJ0020J
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.5)
(1.695)
TYP
16
20
20X (0.6)
A1
20X (0.25)
A4
1
15
(1.695)
TYP
21
SYMM
(3.8)
(1)
TYP
16X (0.5)
11
5
(R0.05)
TYP
4X ( 0.35)
A2
A3
6
10
(1) TYP
( 0.2) TYP
VIA
SYMM
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223320/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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34
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DRV425-Q1
DRV425-Q1
www.ti.com
SBOS988 – AUGUST 2019
EXAMPLE STENCIL DESIGN
RTJ0020J
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(1.695)
(0.655) TYP
20
16
4X ( 0.35)
20X (0.6)
A1
A4
21
1
15
(1.695)
20X (0.25)
(0.655)
TYP
SYMM
(3.8)
16X (0.5)
11
5
(R0.05)
TYP
METAL
TYP
A2
A3
10
6
4X ( 1.11)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21:
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223320/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: DRV425-Q1
35
PACKAGE OPTION ADDENDUM
www.ti.com
22-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV425QWRTJRQ1
Package Type Package Pins Package
Drawing
Qty
ACTIVE
QFN
RTJ
20
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
----->
425-Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV425-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Sep-2019
• Catalog: DRV425
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV425QWRTJRQ1
Package Package Pins
Type Drawing
QFN
RTJ
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.25
B0
(mm)
K0
(mm)
P1
(mm)
4.25
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV425QWRTJRQ1
QFN
RTJ
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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