Texas Instruments | TPS8802 Smoke Alarm AFE | Datasheet | Texas Instruments TPS8802 Smoke Alarm AFE Datasheet

Texas Instruments TPS8802 Smoke Alarm AFE Datasheet
TPS8802
SLVSF25 – OCTOBER 2019
TPS8802 Smoke Alarm AFE
1 Features
•
•
•
•
•
Photo Chamber AFE
– Dual 8-bit programmable current LED drivers
– Temperature compensation of LED current
– Ultra-low offset trans-impedance amplifier for
photodiodes
– Programmable and bypassable gain stage
Carbon Monoxide Sensor AFE
– Ultra-low offset gain stage
– Programmable gain and reference
Horn Driver
– Two-terminal and three-terminal piezoelectric
buzzer driver
– Self-resonant driver with duty cycle tuning
– PWM support for arbitrary sound waveforms
Power Management
– Low quiescent current LDO for internal supply
– Programmable LDO for external
microcontroller
– DC-DC boost converter for horn, interconnect,
battery test
Interconnection bus
– Interconnect driver and receiver
– Short-circuit current limit
Ultra-low power consumption
2 Applications
•
Smoke and CO alarm
3 Description
The TPS8802 is a smoke alarm ASIC specialized for
residential smoke alarms. The TPS8802 integrates all
of the regulators, amplifiers, and drivers required for a
dual-wave photoelectric smoke alarm and carbon
monoxide (CO) detection system. Its high flexibility is
ideal for smoke alarm systems where precision and
power consumption are critical.
The wide input voltage range combined with low
standby power consumption and power-saving
features support 10-year battery life operation from a
single lithium primary battery. The TPS8802 also
supports battery backup smoke alarms, seamlessly
remaining powered when the mains supply drops or if
the battery is disconnected.
Device Information(1)
PART NUMBER
TPS8802
PACKAGE
TSSOP (38)
BODY SIZE (NOM)
9.7 mm x 4.4 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
VLX
VBAT
TPS8802
COO
VBST
CON
VCC
COP
CO
Sensor
PLDO
3V Battery
REF0P3
VINT
LEDLDO
VMCU
PREF
Photo
Chamber
MCUSEL
VBAT
PDP
PDN
VIN
ADC
LEDEN
GPIO
2
IR
PDO
GPIO
DINA
HBEN
MCU
Blue
AMUX
DINB
SCL
CSA
SDA
CSB
I C
CSEL
GPIO
GND
HORNSL
HBEN
HORNFB
Piezo Horn
DGND AGND PGND
HORNBR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
•
1
I2C serial interface
Programmable battery test load
Configurable fault monitor with pin interrupt signal
•
•
•
TPS8802
SLVSF25 – OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
1
1
1
2
3
5.1
5.2
5.3
5.4
5
5
6
6
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
6.6 Register Maps ........................................................ 37
7
7.1 Application Information............................................ 49
7.2 Typical Application ................................................. 50
8
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Power Supply Recommendations...................... 54
Layout ................................................................... 55
9.1 Layout Guidelines ................................................... 55
9.2 Layout Example ...................................................... 56
10 Device and Documentation Support ................. 60
10.1
10.2
10.3
10.4
10.5
Detailed Description ............................................ 21
6.1
6.2
6.3
6.4
6.5
Application and Implementation ........................ 49
21
22
23
35
37
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
60
60
60
60
60
ADVANCE INFORMATION
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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Copyright © 2019, Texas Instruments Incorporated
TPS8802
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5 Pin Configuration and Functions
RESERVE D
1
38
REF0P3
RESERVE D
2
37
PREF
RESERVE D
3
36
COP
LEDLDO
4
35
CON
AGND
5
34
COO
PDP
6
33
AMUX
PDN
7
32
DGND
PDO
8
31
LEDEN
CSA
9
30
HBEN
DINA
10
29
CSEL
CSB
11
28
SDA
DINB
12
27
SCL
MCUSE L
13
26
GPIO
HORNB R
14
25
INT_MCU
HORNS L
15
24
INT_UNIT
HORNFB
16
23
VMCU
PGND
17
22
VINT
VLX
18
21
PLDO
VBS T
19
20
VCC
Thermal
Pad
ADVANCE INFORMATION
DCP Package
38-Pin TSSOP
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
5
I
Analog ground. Connect to ground plane.
AMUX
33
O
Analog multiplexer output.
CON
35
I
Negative terminal of CO operational amplifier. Connect to GND if unused.
COO
34
O
Output of CO operational amplifier. Connect to GND if unused.
COP
36
I
Positive terminal of CO operational amplifier. Connect to GND if unused.
CSA
9
I
Photo LED current sense.
CSB
11
I
Photo LED current sense. Connect to GND if unused.
CSEL
29
I
Device address select pin for I2C serial interface. Pull to GND for I2C address 0x3F. Pull to
VMCU for I2C address 0x2A. Do not leave floating.
DGND
32
I
Digital ground. Connect to AGND.
DINA
10
I
Photo LED current sink. Connect to cathode of LED.
DINB
12
I
Photo LED current sink. Connect to cathode of LED. Connect to GND if unused.
GPIO
26
I/O
HBEN
30
I
Horn block enable. Do not leave floating while device is powered.
HORNBR
14
O
Brass terminal of piezo horn.
HORNFB
16
I
Feedback terminal of a three-terminal piezo horn. Do not leave floating while device is
powered.
HORNSL
15
O
Silver terminal of piezo horn.
INT_MCU
25
I/O
Interconnect and interrupt signal to microcontroller.
INT_UNIT
24
I/O
Interconnect bus to connect other smoke alarms.
LEDEN
31
I
Photo LED enable. Do not leave floating while device is powered.
LEDLDO
4
O
LDO output for charging LED supply capacitor. Connect to GND if unused.
MCUSEL
13
I
Default MCULDO and VBST voltage selection input. Leave floating for VMCU = 3.3V, VBST
= 4.7V. Tie to VINT for VMCU = 2.5V, VBST = 3.8V. Tie to GND for VMCU = 1.8V, VBST =
2.7V. Connect to GND with a 620-Ω resistor for VMCU = 1.5V, VBST = 2.7V.
Copyright © 2019, Texas Instruments Incorporated
Multi-purpose digital input and output.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
PDN
7
I
Photo input amplifier negative input. Connect to cathode of photodiode.
PDO
8
O
Photo input amplifier output pin.
PDP
6
I
Photo input amplifier positive Input. Connect to anode of photodiode.
PGND
17
I
Power ground. Connect to AGND.
PLDO
21
O
Capacitor connection to PLDO block.
PREF
37
O
Photo reference voltage and output for testing CO sensor connectivity.
300mV reference. Connect to GND if unused.
REF0P3
38
O
1, 2, 3
N/A
SCL
27
I
SDA
28
I/O
VBST
19
I
Boost converter feedback and power input.
VCC
20
I
Input supply pin.
VINT
22
O
Capacitor connection to internal supply LDO.
VLX
18
I
Boost converter switch node.
VMCU
23
I/O
LDO supply for external microcontroller and internal IO buffers.
Thermal Pad
39
N/A
Metal connection for thermal dissipation. Connect to ground plane.
RESERVED
ADVANCE INFORMATION
4
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Connect to GND.
Clock input for I2C serial interface.
Data line for I2C serial interface.
Copyright © 2019, Texas Instruments Incorporated
TPS8802
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SLVSF25 – OCTOBER 2019
5.1 Absolute Maximum Ratings
PARAMETER
MIN
MAX
UNIT
Power IO
HORNSL, HORNBR, VBST, VCC
–0.3
16.5
V
Analog IO
DINA, DINB, LEDLDO
–0.3
12
V
Horn feedback
HORNFB
–3
6.5
V
Boost switch
VLX
–0.3
16.5
V
Analog
connections
AMUX, CON, COO, COP, PREF, MCUSEL, PDO, REF0P3
–0.3
VINT + 0.3 or
3.6, whichever
is lower
V
LDO outputs
VINT, VMCU
–0.3
PLDO + 0.3 or
3.6, whichever
is lower
V
LED current
sense
CSA
–0.3
DINA + 0.3 or
3.6, whichever
is lower
V
LED current
sense
CSB
–0.3
DINB + 0.3 or
3.6, whichever
is lower
V
Photo amplifier
inputs
PDN, PDP
–0.3
3.6
V
PLDO voltage
PLDO
–0.3
7.0
V
Interconnect
bus
INT_UNIT
–0.3
18
V
Digital IO
CSEL, GPIO, HBEN, INT_MCU, LEDEN, SCL, SDA
–0.3
VMCU + 0.3 or
3.6, whichever
is lower
V
Max operating
ambient
temperature
TA
-40
125
°C
Max operating
junction
temperature
TJ
-40
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
3 V battery
voltage
9 V battery
voltage
MIN
MAX
VBAT
2.0
3.3
V
VBAT
6.0
10
V
(1)
15.6
V
0
11.5
V
Power supply
VCC, VBST
LED driver
DINA, DINB
Horn feedback
HORNFB
–2
6
V
Interconnect
bus
INT_UNIT
0
17
V
Digital IO
INT_MCU, SCL, SDA, CSEL, LEDEN, HBEN, GPIO
0
VMCU
V
Digital IO
supply
VMCU
1.425
3.6
V
Ambient
temperature
TA
–40
85
°C
Junction
temperature
TJ
–40
85
°C
(1)
2.6
UNIT
Device powers up with VCC < 2.6 V but is not parametrically guaranteed
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ADVANCE INFORMATION
over operating free-air temperature range (unless otherwise noted) (1)
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5.3 Thermal Information
TPS8802 DCP (38 pin TSSOP)
UNIT
RθJA
Junction-to-ambient thermal resistance
THERMAL METRIC
29.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.0
°C/W
RθJB
Junction-to-board thermal resistance
10.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
10.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.2
°C/W
5.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE AND CURRENTS
ADVANCE INFORMATION
VPWRUP
Power up threshold. Note:
Device enters active state
when MCU_PG=1.
VCC rising
1.2
1.7
2.0
V
VPWRDOWN
Power down threshold
VCC falling
0.95
1.5
2.0
V
VPWR,
VCC power up to power
down hysteresis
20
100
400
mV
2.35
2.55
2.7
V
92
125
158
µs
2.15
2.40
2.6
V
92
125
158
µs
All blocks that can be
disabled are off, TJ=27C,
VCC=3V, VMCU=1.8V
4.4
5.6
µA
All blocks that can be
disabled are off, TJ=27C,
VCC=9V, VMCU=3.3V
7.2
9.1
µA
HYS
VVCCLOW,
RISE
VVCCLOW,
FALL
ISTANDBY
VCC low warning reset
threshold
PLDO voltage rising
VCC low warning assert
threshold
PLDO voltage falling
Standby Supply Current
Deglitch time
Deglitch time
POWER LDO
VPLDO
Output Voltage
VCC = 2.0 V, IPLDO = 10 mA
1.93
1.96
1.99
V
VCC = 2.0 V, IPLDO = 30 mA
1.8
1.87
1.95
V
VCC = 3.3 V, IPLDO = 30 mA
3.1
3.23
3.3
V
VCC = 9 V, IPLDO = 30 mA
4.1
5
6.7
V
VCC = 11.5 V, IPLDO = 30 mA
4.1
5
6.7
V
0.7
1
1.3
µF
IVINT < 10 mA
2.25
2.3
2.35
V
IVINT < 10 uA, T>80C
2.25
2.3
2.40
V
PLDO capacitor required for
stability
CPLDO
INTERNAL LDO
Output Voltage
VINTLDO
DC Output Voltage Accuacy
No external/internal load,
VCC = 2.6 V - 11.5 V
–2
2
%
Line Regulation
VCC = 2.6 V-11.5 V, IOUT =
10 mA
–2
2
%
Load Regulation
IVINT = 0 mA - 10 mA, VCC =
3V
–2
2
%
IVINT stepped from 0 mA to
10 mA in 1us
–8
8
%
IVINT stepped from 10 mA to
0 mA in 1us
–5
5
%
VIN = 3.0 V, IOUT = 10 mA, f =
60 Hz (200 mVpp)
50
Transient regulation
PSRR
IINTLDO,
OUT
Output current range
IINTLDO,
SC
Short Circuit Current Limit
6
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dB
0
30
200
10
mA
500
mA
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VINTLDO,
DO
CINTLDO,
OUT
Dropout Voltage
Output Capacitor
ESR of Output Capacitor
TEST CONDITIONS
MIN
TYP
From PLDO to VINT, IVINT =
10 mA, PLDO = 2.2 V
Ceramic
MAX
60
0.7
1
UNIT
mV
1.3
µF
100
mΩ
VMCULDO
VMCULDO,PG
IMCULDO
VMCULDO, TR
IMCULDO, SC
Output Voltage (1)
1.425
1.5
1.575
V
IMCULDO < 10 uA, VCC > 2.2
V, VMCUSET = 00, T > 80°C
1.425
1.5
1.65
V
IMCULDO < 30 mA, VCC > 2.6
V, VMCUSET = 01 (T <
80°C for no load)
1.71
1.8
1.89
V
IMCULDO < 10 uA, VCC > 2.6
V, VMCUSET = 01, T > 80°C
1.71
1.8
1.98
V
IMCULDO < 30 mA, VCC > 3.65
V, VMCUSET = 10 (T <
80°C for no load)
2.38
2.5
2.63
V
IMCULDO < 10 uA, VCC > 3.65
V, VMCUSET = 10, T > 80°C
2.38
2.5
2.75
V
IMCULDO < 10 mA, VCC > 3.65
V, VMCUSET = 11 (T <
80°C for no load)
3.13
3.3
3.47
V
IMCULDO < 10 uA, VCC > 4.5
V, VMCUSET = 11, T > 80°C
3.13
3.3
3.60
V
IMCULDO < 50 mA, VCC > 5.5
V, VMCUSET = 11
3.13
3.3
3.47
V
DC Output Voltage Accuracy
T < 80°C
–5
5
%
MCULDO power good
threshold
VMCU rising
75
85
95
%
VMCU falling
65
75
Output Current Range
MCULDO load transient
regulation
85
%
VCC > 2.2 V, VMCUSET = 00
0
30
mA
VCC > 2.6 V, VMCUSET = 01
0
30
mA
VCC > 3.65 V, VMCUSET =
10
0
30
mA
VCC > 4.5 V, VMCUSET = 11
0
50
mA
IMCULDO stepped from 0 mA
to 10 mA in 1us, T < 80°C
–5
5
%
IMCULDO stepped from 0 mA
to 10 mA in 1us, T > 80°C
–8
8
%
IMCULDO stepped from 10 mA
to 0 mA in 1us, T < 80°C
–5
5
%
IMCULDO stepped from 10 mA
to 0 mA in 1us, T > 80°C
–8
8
%
Short Circuit current limit
tMCULDO, PWR
Power Up Time
TMCULDO, PG
MCULDO power good
deglitch time
(1)
IMCULDO < 30 mA, VCC > 2.2
V, VMCUSET = 00 (T < 80°C
for no load)
100
CMCULDO = 1µF, time from
VMCU=0V to 90% of target
voltage
92
160
270
mA
600
1100
µs
125
158
µs
ADVANCE INFORMATION
MCU LDO
MCU LDO output voltage on power-up is determined by the MCUSEL pin state.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TMCULDO,
MASK
IMCULDO, Q
CMCULDO
RMCUSEL
TEST CONDITIONS
MIN
MCULDO low voltage error
mask time. MCULDO_ERR is
masked for
T_MCULDO,MASK after
VMCUSET or MCU_DIS is
changed.
Quiescent Current
Output Capacitor
ESR of Output Capacitor
MCUSEL component
requirements. Not tested in
production
TYP
MAX
10
IMCULDO = 0µA
Ceramic
0.7
UNIT
ms
1.5
3
µA
1
1.3
µF
100
mΩ
682
Ω
ADVANCE INFORMATION
Pull-down resistance to set
VMCUSET[1:0]=00 on
powerup
558
Pull-down resistance to set
VMCUSET[1:0]=01 on
powerup
0
10
Ω
Pull-up resistance to VINT to
set VMCUSET[1:0]=10 on
powerup
0
10
Ω
Capacitance to set
VMCUSET[1:0]=11 on
powerup
300
1000
pF
IBST < 50 mA, 2.0 V < VBAT
< 2.5 V, VBST =
0000, BST_CLIM[3:0] = 1111
2.45
2.7
2.808
V
IBST < 50 mA, 2.0 V < VBAT
< 3.5 V, VBST =
0001, BST_CLIM[3:0] = 1111
3.55
3.8
3.952
V
IBST < 50 mA, 2.0 V < VBAT
< 4.0 V, VBST =
0010, BST_CLIM[3:0] = 1111
4.40
4.7
4.888
V
IBST < 50 mA, 2.0 V < VBAT
< 5.2 V, VBST =
0011, BST_CLIM[3:0] = 1111
5.60
6
6.24
V
IBST < 30 mA, 2.0 V < VBAT
< 8.0 V, VBST =
0100, BST_CLIM[3:0] = 1111
8.64
9
9.36
V
IBST < 30 mA, 2.0 V < VBAT
< 9.0 V, VBST =
0101, BST_CLIM[3:0] = 1111
9.6
10
10.4
V
IBST < 30 mA, 2.0 V < VBAT
< 9.5 V, VBST =
0110, BST_CLIM[3:0] = 1111
10.08
10.5
10.92
V
IBST < 30 mA, 2.0 V < VBAT
< 10.0 V, VBST =
0111, BST_CLIM[3:0] = 1111
10.56
11
11.44
V
IBST < 30 mA, 2.0 V < VBAT
< 10.5 V, VBST =
1000, BST_CLIM[3:0] = 1111
11.04
11.5
11.96
V
IBST < 20 mA, 2.0 V < VBAT
< 13.5 V, VBST =
1001, BST_CLIM[3:0] = 1111
14.4
15
15.6
V
620
DCDC BOOST REGULATOR
Boost minimum output
voltage. Load applied after
voltage settles. Note:
average output voltage
depends on ripple.
VBST
VBST
Boost minimum output
voltage. Load applied after
voltage settles. Note:
average output voltage
depends on ripple.
VBST, PG
Power good threshold
8
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VBST rising
95
VBST falling
85
%
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
IBST, PWRUP
IBST, PEAK
Output current when boost is
powering up. The boost
output current is limited when
VBST is below the specified
voltage.
Inductor peak current setting
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBST = 0000, VCC = VBST
< 2.7 V
5
mA
VBST = 0001:1000, VCC =
VBST < 3.0 V
5
mA
BST_CLIM[3:0] = 0000
10
30
70
mA
BST_CLIM[3:0] = 0001
20
40
75
mA
BST_CLIM[3:0] = 0010
30
50
90
mA
BST_CLIM[3:0] = 0011
40
60
105
mA
BST_CLIM[3:0] = 0100
60
80
130
mA
BST_CLIM[3:0] = 0101
80
100
150
mA
BST_CLIM[3:0] = 0110
110
130
190
mA
BST_CLIM[3:0] = 0111
140
160
220
mA
BST_CLIM[3:0] = 1000
170
200
275
mA
BST_CLIM[3:0] = 1001
210
240
320
mA
BST_CLIM[3:0] = 1010
240
280
370
mA
BST_CLIM[3:0] = 1011
270
320
420
mA
BST_CLIM[3:0] = 1100
300
360
475
mA
BST_CLIM[3:0] = 1101
330
400
520
mA
BST_CLIM[3:0] = 1110
380
450
585
mA
BST_CLIM[3:0] = 1111
410
500
645
mA
Low-side MOSFET on
resistance
VCC = 3.3 V, ILX = TBD
ISTANDBY
Standby current. Current
does not include bias block.
IBST = 0, BST_EN=1.
CBST
Output capacitance
4.7
µF
LBST
Nominal inductance
33
mH
RDS,
BST
RIND,
BST
100
Inductor DC resistance
TBST, PG
Boost power good deglitch
time
TBST, ACT
Boost activity monitor delay
time—BST_nACT is set to 1
when the boost converter has
not switched for T_BST,ACT
while BST_EN=1. Not tested
in production.
TBST, MASK
0
1
Ω
150
µA
0.8
Ω
µs
92
125
158
T_BSTACT[1:0] = 00
0.1
0.156
0.2
T_BSTACT[1:0] = 01
0.9
1
1.1
T_BSTACT[1:0] = 10
9.4
10
10.6
T_BSTACT[1:0] = 11
94
100
106
Boost converter BST_ERR
mask time. BST_ERR is
masked for TBST,MASK after
VBST or BST_EN is
changed.
10
ADVANCE INFORMATION
PARAMETER
ms
ms
PHOTO CHAMBER INPUT STAGE AMPLIFIER
VPDO
Output voltage range
fPDIN, BW
Unity Gain Bandwidth
VPDIN, OFS
Input Offset Voltage
VPDO, OFS
Output Offset Voltage
fPDIN, CHOP
Chop Frequency
Copyright © 2019, Texas Instruments Incorporated
PAMP_EN=1, Feedback
network: 1.5M Ω, 10pF
50mV applied to PDP with
1.5MΩ series resistor. 1.5MΩ
resistor connects PDN to
PDO. Voltage measured
between 50mV and PDO.
0
0.5
V
1
5
-200
200
µV
-10
10
mV
2
MHz
MHz
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9
TPS8802
SLVSF25 – OCTOBER 2019
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TPDIN, SET
Input amplifier settling time.
Time between stepping the
current and measuring 90%
of the final value + 10% of
the initial value at PDO
TEST CONDITIONS
MIN
TYP
MAX
Feedback network: 1.5M Ω,
10pF. 1 nA to 10 nA applied
from PDN to PDP. 0V
reference
0
30
40
µs
Feedback network: 1.5MΩ,
5pF. 1.5MΩ connected from
PDP to PREF. 1 nA to 10 nA
applied from PDN to PDP.
PREF_SEL=1
0
20
40
µs
160
195
µA
Active current. Current does
not include bias block or 8
MHz oscillator.
IPDIN, ACT
UNIT
PHOTO CHAMBER GAIN STAGE AMPLIFIER
ADVANCE INFORMATION
Closed Loop Gain
Slope (VAOUT_PH2VAOUT_PH1)/(VSIG2-VSIG1).
Apply VSIG1 from PREF to
PDO and measure
AOUT_PH. Apply VSIG2 from
COTEST to PDO and
measure AOUT_PH
GPGAIN
Closed Loop Gain
Slope (VAOUT_PH2VAOUT_PH1)/(VSIG2-VSIG1).
Apply VSIG1 from PREF to
PDO and measure
AOUT_PH. Apply VSIG2 from
PREF to PDO and measure
AOUT_PH
FPGAIN, BW
Unity Gain Bandwidth
VPGAIN, OFS
Input offset Voltage
TPGAIN, SET
IPGAIN, ACT
Gain amplifier settling time.
Time between stepping the
voltage and measuring 90%
of the final value + 10% of
the initial value at AOUT_PH
Active current. Current does
not include bias block.
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
00
4.85
5
5.15
V/V
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
01
10.67
11
11.33
V/V
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
10
19.4
20
20.6
V/V
VPDO1=10mV, VPDO2=20mV,
PREF_SEL=0, PGAIN[1:0] =
11
33.95
35
36.05
V/V
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
00
4.61
4.75
4.89
V/V
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
01
9.94
10.25
10.56
V/V
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
10
17.94
18.5
19.06
V/V
VSIG1=10mV, VSIG2=20mV,
PREF_SEL=1, PGAIN[1:0] =
11
31.28
32.25
33.22
V/V
1
5
8
MHz
4.5
mV
-4.5
PGAIN[1:0]=00. PDO
stepped from 3mV to 30mV.
PREF_SEL=0
0.38
2
µs
PGAIN[1:0]=00. Signal
applied from PREF to PDO.
Signal stepped from 3mV to
30mV. PREF_SEL=1
0.25
2
µs
40
70
µA
10
V
5
%
3
6
mA
35
60
µA
1.0 V input voltage,
PGAIN[1:0] = 00, PGAIN_EN
=1
LED LDO
LEDLDO output voltage
range
VLEDLDO
VLEDLDO,ACC
LDO output accuracy
VLEDLDO,
LED LDO output step size
RES
ILEDLDO,
OUT
LDO output current limit
ILEDLDO,
Q
Quiescent current. Current
does not include bias block.
10
Submit Documentation Feedback
7.5
I_LEDLDO = 0uA to 100uA
-5
0.5
1
V
Copyright © 2019, Texas Instruments Incorporated
TPS8802
www.ti.com
SLVSF25 – OCTOBER 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLEDLDO,
LED LDO dropout voltage
DROP
TEST CONDITIONS
MIN
TYP
VBST=7V,
VBST=7V,
ILEDLDO=100u ILEDLDO=100u
A
A
MAX
UNIT
1000
mV
LED DRIVER A
VCSA
Resolution
CSA output voltage
8
282
294
306
mV
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
582
594
606
mV
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
261
273
285
mV
TJ = 27°C TEMPCOA[1:0] =
01, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
561
573
585
mV
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
176
188
200
mV
TJ = 27°C TEMPCOA[1:0] =
10, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
476
488
500
mV
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
71
83
95
mV
TJ = 27°C TEMPCOA[1:0] =
11, PDAC_A = FF, RCSA=1
kOhms, VDINA=3V
371
383
395
mV
DAC step size
VPDACA, STEP
tPDACA, SET
KPDACA, COMP
Bits
TJ = 27°C TEMPCOA[1:0] =
00, PDAC_A = 00, RCSA=1
kOhms, VDINA=3V
1.18
mV
INL
-10
10
LSB
DNL
-1.5
1.5
LSB
Settling Time
CSA temperature
compensation coefficient
Copyright © 2019, Texas Instruments Incorporated
ADVANCE INFORMATION
NPDACA, RES
1
5
µs
TEMPCOA[1:0] = 00,
PDAC_A[7:0] =
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
0.174
0.347
0.521
mV/°C
TEMPCOA[1:0] = 01,
PDAC_A[7:0] =
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
0.208
0.416
0.624
mV/°C
TEMPCOA[1:0] = 10,
PDAC_A[7:0] =
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
0.346
0.693
1.039
mV/°C
TEMPCOA[1:0] = 11,
PDAC_A[7:0] =
0x00, RCSA=1 kOhms,
VDINA=3V, TJ=0°C, 50°C
0.520
1.040
1.560
mV/°C
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TPS8802
SLVSF25 – OCTOBER 2019
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VDINA, DROP
IDINA
Dropout voltage. Voltage
required between DINA and
CSA for current regulation.
TEST CONDITIONS
MAX
UNIT
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=11,
PDAC_A[7:0]=0x28, TJ=27°C
(I_LED≈158mA, 0.8% temp
coefficient)
300
mV
PLDO=3.6V, RCSA=820mΩ,
TEMPCOA[1:0]=01,
PDAC_A[7:0]=0x79, TJ=27°C
(I_LED≈507mA, 0.1% temp
coefficient)
500
mV
550
mA
LED current
MIN
TYP
0
LED DRIVER B
NPDACB, RES
ADVANCE INFORMATION
VCSB
Resolution
CSB output voltage
8
282
294
306
mV
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
582
594
606
mV
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
261
273
285
mV
TJ = 27°C TEMPCOB[1:0] =
01, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
561
573
585
mV
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
176
188
200
mV
TJ = 27°C TEMPCOB[1:0] =
10, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
476
488
500
mV
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
71
83
95
mV
TJ = 27°C TEMPCOB[1:0] =
11, PDAC_B = FF, RCSB=1
kOhms, VDINB=3V
371
383
395
mV
10
LSB
1.5
LSB
DAC step size
VPDACB, STEP
tPDACB, SET
KPDACB, COMP
12
1.18
INL
-10
DNL
-1.5
Settling time
CSB temperature
compensation coefficient
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Bits
TJ = 27°C TEMPCOB[1:0] =
00, PDAC_B = 00, RCSB=1
kOhms, VDINB=3V
mV
1
5
µs
TEMPCOB[1:0] = 00,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.174
0.347
0.521
mV/°C
TEMPCOB[1:0] = 01,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.208
0.416
0.624
mV/°C
TEMPCOB[1:0] = 10,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.346
0.693
1.039
mV/°C
TEMPCOB[1:0] = 11,
PDAC[7:0] = 0x00, RCSB=1
kOhms, VDINB=3V, TJ=0°C,
50°C
0.520
1.040
1.560
mV/°C
Copyright © 2019, Texas Instruments Incorporated
TPS8802
www.ti.com
SLVSF25 – OCTOBER 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VDINB, DROP
IDINB
Dropout voltage. Voltage
required between DINB and
CSB for current regulation.
TEST CONDITIONS
MAX
UNIT
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=11,
PDAC[7:0]=0x28, TJ=27°C
(I_LED≈158mA, 0.8% temp
coefficient)
300
mV
PLDO=3.6V, RCSA=820mΩ,
TEMPCOB[1:0]=01,
PDAC[7:0]=0x79, TJ=27°C
(I_LED≈507mA, 0.1% temp
coefficient)
500
mV
550
mA
LED current
MIN
TYP
0
RI, CO
CO input resistance
RF, CO
CO feedback resistance
COSWRI = 1
0.7
1
1.3
kΩ
COGAIN[1:0] = 00,
COSWRG = 1
770
1100
1430
kΩ
COGAIN[1:0] = 01,
COSWRG = 1
210
300
390
kΩ
COGAIN[1:0] = 10,
COSWRG = 1
350
500
650
kΩ
COGAIN[1:0] = 11,
COSWRG = 1
560
800
1040
kΩ
VIN,
COP
CO amplifier input voltage
(COP pin)
0
0.6
V
VIN,
CON
CO amplifier input voltage
(CON pin)
0
0.6
V
-180
180
µV
0.1
2
V
1
2.1
µA
5
12
20
kHz
3.8
4
4.2
kHz
70
100
130
kΩ
COSWREF=1, COREF[1:0] =
00
1.06
1.25
1.44
COSWREF=1, COREF[1:0] =
01
2.12
2.5
2.88
COSWREF=1, COREF[1:0] =
10
3.18
3.75
4.31
COSWREF=1, COREF[1:0] =
11
4.25
5
5.75
VOFFS,
VOUT,
CO
COO
CO amplifier input offset
voltage
CO amplifier output voltage
(COO pin)
ICO,
Q
CO amplifier quiescent
current
fCO,
BW
CO amplifier unity gain
bandwidth
fCO,
CHOP
CO amplifier chop frequency
CO amplifier output
resistance
RCOO
CO amplifier reference
voltage
VCOPREF
COSWRO = 1
ADVANCE INFORMATION
CO TRANSIMPEDANCE AMPLIFIER
mV
RCOTEST,
PU
COTEST pull up FET
resistance
0.36
0.63
1.1
kΩ
RCOTEST,
PD
COTEST pull-down FET
resistance
0.25
0.45
0.82
kΩ
INTERCONNECT
Copyright © 2019, Texas Instruments Incorporated
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TPS8802
SLVSF25 – OCTOBER 2019
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ISNK,
INT_UNIT
ADVANCE INFORMATION
ISRC, INT_UNIT
tINT,
IINT,
Interconnect sink current
Interconnect source current
Interconnect deglitch time
DEG
Q
TEST CONDITIONS
MIN
TYP
MAX
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 0.8 V
4
9
15
mA
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 2.0 V
5
15
30
mA
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 6.0 V
9
16
30
mA
INT_DIR = 1, INT_MCU = 0
V, VBST = 11.5 V, INT_UNIT
= 10 V
9
16
30
mA
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 0.8 V
4
8
15
mA
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 2.0 V
4
8
15
mA
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 6.0 V
4
8
13
mA
INT_DIR = 1, INT_MCU =
VMCU, VBST = 11.5
V, INT_UNIT = 10 V
1
1.8
4
mA
INT_DIR = 0, INT_DEG[1:0]
= 00
0
0
0.065
INT_DIR = 0, INT_DEG[1:0]
= 01
0.090
0.125
0.160
INT_DIR = 0, INT_DEG[1:0]
= 10
0.9
1
1.1
INT_DIR = 0, INT_DEG[1:0]
= 11
19.8
20
20.2
Interconnect standby current
INT_DIR = 0
UNIT
ms
0.5
uA
VINT_UNIT,
IHI
Interconnect input high
threshold voltage
INT_HYS = 0
1.3
1.9
2.7
V
VINT_UNIT,
IHI
Interconnect input high
threshold voltage
INT_HYS = 1
1.3
1.9
2.7
V
VINT_UNIT,
ILO
Interconnect low threshold
voltage
INT_HYS = 0
0.5
0.8
1.1
V
VINT_UNIT,
ILO
Interconnect low threshold
voltage
INT_HYS = 1
1.2
1.8
2.7
V
VINT_UNIT,
Interconnect input hysteresis
INT_HYS = 0
0.7
1.1
1.7
V
HYS
INT_HYS = 1
0.01
0.1
0.3
V
INT_PD=1
65
100
165
kΩ
INT_PD=0
3.5
50
MΩ
HORNSL output high voltage
VBST = 11.5 V, IHORNSL =
–16 mA
11
VOL, HORNSL
HORNSL output low voltage
VBST = 11.5 V, IHORNSL = 16
mA
VOH,
HORNBR output high voltage
VBST = 11.5 V, IHORNBR =
–16 mA
HORNBR output low voltage
VBST = 11.5 V, IHORNBR = 16
mA
RINT_UNIT,
PD
Interconnect input pulldown
resistance
HORN DRIVER
VOH,
HORNSL
HORNBR
VOL, HORNBR
14
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11.2
0.3
11
V
0.5
11.2
0.3
V
V
0.5
V
Copyright © 2019, Texas Instruments Incorporated
TPS8802
www.ti.com
SLVSF25 – OCTOBER 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HORNSL rise time, 2
terminal
VBST=11.5V, no load,
HORNSEL=0, HORNFB from
0 to VMCU. Time from
VHORNSL=1.15V to
VHORNSL=10.35V
20
ns
HORNSL fall time, 2 terminal
VBST=11.5V, no load,
HORNSEL=0, HORNFB from
VMCU to 0. Time from
VHORNSL=10.35V to
VHORNSL=1.15V
20
ns
tR, HORNBR2
HORNBR rise time, 2
terminal
VBST=11.5V, no load,
HORNSEL=0, HBEN from 0
to VMCU. Time from
VHORNBR=1.15V to
VHORNBR=10.35V
20
ns
tF, HORNBR2
VBST=11.5V, no load,
HORNSEL=0, HBEN from
HORNBR fall time, 2 terminal VMCU to 0. Time from
VHORNBR=10.35V to
VHORNBR=1.15V
20
ns
HORNSL rise time, 3
terminal
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
from 0V to 3V. Time from
VHORNSL=1.15V to
VHORNSL=10.35V
5
µs
HORNSL fall time, 3 terminal
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
from 3V to 0V. Time from
VHORNSL=10.35V to
VHORNSL=1.15V
5
µs
tR, HORNBR3
HORNBR rise time, 3
terminal
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
from 3V to 0V. Time from
VHORNBR=1.15V to
VHORNBR=10.35V
5
µs
tF, HORNBR3
VBST=11.5V, CHORNSL=82nF
to GND, HORNSEL=1,
HORN_THR=00, HORNFB
HORNBR fall time, 3 terminal
from 0V to 3V. Time from
VHORNBR=10.35V to
VHORNBR=1.15V
5
µs
VIH2, HORNFB
Horn driver input high
VBST = 11.5 V, HORNSEL =
voltage. HBEN and HORNFB 0
0.35×VMCU
0.7× VMCU
V
VIL2,
Horn driver input low voltage. VBST = 11.5 V, HORNSEL =
HBEN and HORNFB
0
0.25×VMCU
0.65×VMCU
V
tR, HORNSL2
tF, HORNSL2
tR, HORNSL3
tF, HORNSL3
HORNFB
tSKEW,HIGH
Horn driver output high delay
mismatch. Difference in
output delay between
HORNFB to HORNSL and
HBEN to HORNBR
HORNSEL=0, VBST=11.5V,
HORNFB and HBEN switch
from 0 to VMCU.
0
10
ns
tSKEW,LOW
Horn driver output low delay
mismatch. Difference in
output delay between
HORNFB to HORNSL and
HBEN to HORNBR
HORNSEL=0, VBST=11.5V,
HORNFB and HBEN switch
from VMCU to 0.
0
10
ns
Copyright © 2019, Texas Instruments Incorporated
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ADVANCE INFORMATION
PARAMETER
15
TPS8802
SLVSF25 – OCTOBER 2019
www.ti.com
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HORNSEL=0, VBST=11.5V,
HORNFB, HBEN=0,
HORN_EN=1. Current from
VBST, VCC pins measured
0
150
uA
HORNSEL=1, VBST=11.5V,
HORNFB=0, HBEN=1,
HORN_EN=1. Current from
VBST, VCC pins measured
0
150
uA
Multiplexer buffer input signal
AMUX_BYP=0
voltage range
0.05
2
V
GAIN
Multiplexer bufffer output gain AMUX_BYP=0
0.99
OFFS
Multiplexer buffer offset
voltage
AMUX_BYP=0
Horn driver quiescent
current. Current does not
include bias block.
IHORN,Q
ANALOG MULTIPLEXER
VMUX
GMUX,
VMUX,
ADVANCE INFORMATION
tMUX,
EN
1.01
V/V
-7
7
mV
Multiplexer buffer enable
settling time
AMUX_BYP=0, AMUX_SEL
stepped from 000 to 011 with
PDO=2V, PAMP_EN=0.
Time until AMUX reaches
99% of its final value
0
15
us
0
15
us
25
MHz
10
uA
50
uA
500
pF
tMUX,
STEP
Multiplexer buffer input step
settling time
AMUX_BYP=0,
AMUX_SEL=011, PDO
stepped from 50mV to 2V,
PAMP_EN=0. Time until
AMUX reaches 99% of its
final value
fMUX,
BW
Multiplexer bandwidth
AMUX_BYP=0
0.5
IMUX,
OUT
Multiplexer output current
AMUX_BYP=0
–10
Q
Multiplexer quiescent
current. Current does not
include bias block.
AMUX_BYP=0
IMUX,
Multiplexer buffer output
AMUX_BYP=0
capacitor required for stability
CMUX
1
1
150
BATTERY TEST
IBATTEST
Battery test load current.
VBST = 4.5 V to 11.5
V, IBATTEST = 000
9.20
10
10.80
mA
VBST = 4.5 V to 11.5
V, IBATTEST = 001
11.4
12
12.60
mA
VBST = 4.5 V to 11.5
V, IBATTEST = 010
12.88
14
15.12
mA
VBST = 4.5 V to 11.5
V, IBATTEST = 011
14.72
16
17.28
mA
VBST = 4.5 V to 11.5
V, IBATTEST = 100
16.56
18
19.44
mA
VBST = 4.5 V to 11.5
V, IBATTEST = 101
18.40
20
21.60
mA
tBATTEST,RISE
Battery test rise time. Time
from enabling battery test
until 90% of target current is
reached
VBST=10V, IBATTEST=101
10
us
tBATTEST,FALL
Battery test fall time. Time
from disabling battery test
until 10% of initial current is
reached
VBST=10V, IBATTEST=101
10
us
OSCILLATOR, REFERENCE SYSTEM
fOSC8
16
Oscillator frequency
Frequency accuracy
Submit Documentation Feedback
8
TA = -10°C to 70°C
–2
MHz
2
%
Copyright © 2019, Texas Instruments Incorporated
TPS8802
www.ti.com
SLVSF25 – OCTOBER 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
Low-power Oscillator
frequency
fOSC32
Frequency accuracy
TTIMEOUT
Error timeout time
IREF0P3,
REF0P3 buffer quiescent
current
Q
TREF0P3,
SET
REF0P3 settling time
VREF0P3,
OUT
REF0P3 output voltage
IVCCLOW,Q
MAX
32
TA = -10°C to 70°C
–3
0.9
VCC current difference
between REF0P3_EN=0 and
REF0P3=1. IREF0P3=0 µA
REF0P3 output capacitor
required for stability
CREF0P3
TYP
0.1
From REF0P3 enabled to
99% of final output voltage.
CREF0P3=1nF, IREF0P3=0 µA
UNIT
kHz
3
%
1
1.1
s
0.3
0.6
µA
1
1.5
nF
1
1.8
ms
IREF0P3 = 10 µA
270
300
330
mV
IREF0P3 = -25 µA
270
300
330
mV
1.3
2
uA
0.3×VMCU
0.7× VMCU
V
VCC_LOW quiescent current
ADVANCE INFORMATION
PARAMETER
IO BUFFERS
VIO,
ILO
IO buffer input low threshold
LEDEN, CSEL, INT_MCU,
GPIO
VIO,
ILO
IO buffer input low threshold
Percentage
LEDEN
30
70
%
VIO,
ILO
IO buffer input low threshold
Percentage
CSEL
30
70
%
VIO,
ILO
IO buffer input low threshold
Percentage
INT_MCU
30
70
%
VIO,
ILO
IO buffer input low threshold
Percentage
GPIO
30
70
%
VIO,
IHI
IO buffer input high threshold
LEDEN, CSEL, INT_MCU,
GPIO
0.3×VMCU
0.7× VMCU
V
VIO,
IHI
IO buffer input high threshold
Percentage
LEDEN
30
70
%
VIO,
IHI
IO buffer input high threshold
Percentage
CSEL
30
70
%
VIO,
IHI
IO buffer input high threshold
Percentage
INT_MCU
30
70
%
VIO,
IHI
IO buffer input high threshold
Percentage
GPIO
30
70
%
IIO,
LEAK
IO buffer input leakage
current
LEDEN
100
nA
IIO,
LEAK
IO buffer input leakage
current
HBEN
100
nA
IIO,
LEAK
IO buffer input leakage
current
CSEL
100
nA
VIO,
VIO,
OL
OL
IO buffer output low-level
IO buffer output low-level
Copyright © 2019, Texas Instruments Incorporated
INT_MCU, GPIO. IIO = 3
mA, VMCU = 1.8 V
0
0.6
V
INT_MCU, GPIO. IIO = 1
mA, VMCU = 1.5 V
0
0.6
V
0.6
V
INT_MCU. IIO
= 3 mA,
VMCU=1.8V;
IIO = 1 mA,
VMCU=1.5V.
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SLVSF25 – OCTOBER 2019
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIO,
TEST CONDITIONS
MIN
TYP
GPIO. IIO = 3
mA,
VMCU=1.8V;
IIO = 1 mA,
VMCU=1.5V.
V
0.6
V
0.6
V
OH
INT_MCU. IIO
IO buffer output high-level.
= -3 mA,
Spec is the voltage drop from VMCU=1.8V;
VMCU (i.e. VMCU - VOH)
IIO = -1 mA,
VMCU=1.5V.
0.6
V
VIO,
OH
GPIO. IIO = -3
IO buffer output high-level.
mA,
Spec is the voltage drop from VMCU=1.8V;
VMCU (i.e. VMCU - VOH)
IIO = -1 mA,
VMCU=1.5V.
0.6
V
CIN,
IO
Input capacitance
LEDEN, CSEL
2
10
pF
CIN,
IO
Input capacitance
HBEN
2
10
pF
IO
Input capacitance
INT_MCU, GPIO
2
10
pF
RIO,PD
IO buffer input pulldown
resistor
INT_MCU, GPIO
10
RIO,PD
IO buffer input pulldown
resistor
GPIO
0.8
10
50
MΩ
RIO,PD
IO buffer input pulldown
resistor
INT_MCU
0.8
10
50
MΩ
IIO,Q
IO and I2C block supply
current
LEDEN,
CSEL,
INT_MCU,
GPIO, SDA,
SCL=0V
800
nA
IIO,Q
HBEN block supply current
HBEN=0V
800
nA
VIO,
ADVANCE INFORMATION
CIN,
IO buffer output low-level
OH
INT_MCU, GPIO. IIO = -3
IO buffer output high-level.
mA, VMCU = 1.8 V
Spec is the voltage drop from
INT_MCU, GPIO. IIO = -1
VMCU (i.e. VMCU - VOH)
mA, VMCU = 1.5 V
UNIT
0.6
VIO,
OL
MAX
0
0.25
0
MΩ
THERMAL WARNING
TWARNING
Thermal trip point
110
C
THERMAL SHUTDOWN
TSHTDWN
tOTS,MASK
Thermal trip point
125
Thermal hysteresis
5
Thermal error mask time.
OTS_ERR is masked for
tOTS,MASK after device fully
powers up or OTS_EN set to
1
C
11
15
218.75
350
us
0.3 × VMCU
V
I2C IO
VI2C,IL
Low-level input voltage
-0.5
VI2C,IH
High-level input voltage
0.7 × VMCU
V
VI2C,HYS
Hysteresis of Schmitt trigger
inputs
0.05 × VMCU
V
VI2C,OL
II2C,OL
18
Low-level output voltage
Low-level output current
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3 mA sink current; VMCU
>2V
0
0.4
V
2 mA sink current; VMCU
< 2V
0
0.2 × VMCU
V
VOL = 0.4 V
2.5
mA
VOL = 0.6 V
4
mA
Copyright © 2019, Texas Instruments Incorporated
TPS8802
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SLVSF25 – OCTOBER 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
II2C,IN
Input current to each I/O pin
CI2C,IN
Capacitance for each I/O pin
tI2C,OF
tI2C,SP
TEST CONDITIONS
MAX
UNIT
µA
10
pF
From VIHmin to VILmax,
Standard-Mode
250
ns
From VIHmin to VILmax, FastMode
250
ns
0
50
ns
SCL clock frequency,
Standard-Mode
0
100
kHz
SCL clock frequency FastMode
0
400
kHz
Pulse width of spikes that
must be suppressed by the
input filter
-10
TYP
10
Output fall time
0.1VMCU < VI < 0.9VMCUmax
MIN
fSCL
hold time (repeated) START
condition, Standard-Mode
After this
period, the
first clock
pulse is
generated.
4
µs
hold time (repeated) START
condition, Fast-Mode
After this
period, the
first clock
pulse is
generated.
0.6
µs
LOW period of the SCL
clock, Standard-Mode
4.7
µs
LOW period of the SCL
clock, Fast-Mode
1.3
µs
HIGH period of the SCL
clock, Standard-Mode
4
µs
HIGH period of the SCL
clock, Fast-Mode
0.6
µs
set-up time for a repeated
START condition, StandardMode
4.7
µs
set-up time for a repeated
START condition, Fast-Mode
0.6
µs
CBUS
compatible
masters
5
µs
tHD;DAT
I2C-bus
devices
0
µs
tHD;DAT
CBUS
compatible
masters
0
µs
I2C-bus
devices
0
µs
data set-up time, StandardMode
250
ns
data set-up time, Fast-Mode
100
ns
tHD;STA
tSCL,LOW
tSCL,HIGH
tSU;STA
tHD;DAT
data hold time, StandardMode
data hold time, Fast-Mode
tHD;DAT
tSU;DAT
tI2C,RISE
rise time of both SDA and
SCL signals, Standard-Mode
rise time of both SDA and
SCL signals, Fast-Mode
Copyright © 2019, Texas Instruments Incorporated
20
1000
ns
300
ns
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ADVANCE INFORMATION
I2C BUS LINES
19
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SLVSF25 – OCTOBER 2019
www.ti.com
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tI2C,FALL
tSU;STO
tBUF
ADVANCE INFORMATION
tVD;DAT
tVD;ACK
CBUS
TEST CONDITIONS
fall time of both SDA and
SCL signals, Standard-Mode
fall time of both SDA and
SCL signals, Fast-Mode
20 × (VMCU /
5.5 V)
set-up time for STOP
condition, Standard-Mode
TYP
MAX
UNIT
300
ns
300
ns
4
µs
set-up time for STOP
condition, Fast-Mode
0.6
µs
bus free time between a
STOP and START condition,
Standard-Mode
4.7
µs
bus free time between a
STOP and START condition,
Fast-Mode
1.3
µs
data valid time, StandardMode
3.45
µs
data valid time, Fast-Mode
0.9
µs
data valid acknowledge time,
Standard-Mode
3.45
µs
data valid acknowledge time,
Fast-Mode
0.9
µs
capacitive load for each bus
line, Standard-Mode
400
pF
capacitive load for each bus
line, Fast-Mode
250
pF
VNL
noise margin at the LOW
level
for each
connected
device
(including
hysteresis)
VNH
noise margin at the HIGH
level
for each
connected
device
(including
hysteresis)
20
MIN
Submit Documentation Feedback
0.1 × VMCU
V
0.2 × VMCU
V
Copyright © 2019, Texas Instruments Incorporated
TPS8802
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SLVSF25 – OCTOBER 2019
6 Detailed Description
6.1 Overview
ADVANCE INFORMATION
The TPS8802 is a smoke alarm ASIC for photoelectric smoke detection and carbon monoxide (CO) alarms.
Designed to be an all-in-one smoke alarm solution, the TPS8802 integrates a boost converter, analog supply
LDO, microcontroller supply LDO, photoelectric chamber analog front end (AFE), carbon monoxide sensor AFE,
interconnect driver, piezo horn driver, analog multiplexer, and digital core. The TPS8802 can be powered from a
variety of sources—9V battery, 3V battery, AC/DC, or AC/DC with battery backup. The two LED drivers have
highly configurable temperature compensation to support IR and blue LEDs over a wide range of currents. The
photo-amplifier’s wide bandwidth saves power due to reduced LED on-time. The CO amplifier has integrated
gain resistors. The horn driver is compatible with two-terminal or three-terminal piezo horns, and the threeterminal self-resonant mode is tunable to maximize piezo loudness. The wired interconnection driver allows
multiple smoke alarm units to communicate alarm conditions. Each block is highly configurable with the digital
core’s I2C interface, supporting on-the-fly adjustment of amplifier gains, regulator voltages, and driver currents.
Digital features such as sleep mode, under-voltage boost enabling, and one-time boost charging are designed to
reduce power consumption for the 10-year battery alarms. Configurable status and interrupt signal registers alert
the MCU of fault conditions such as under-voltage, over-temperature, and interconnection alerts.
Copyright © 2019, Texas Instruments Incorporated
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6.2 Functional Block Diagram
VBS T
BST_EN
VCC
Power LDO
Boo st
PGND
Under-Voltage
Monitor
PLDO
VLX
To Digi tal Core
VBS T
VINT
VBS T
Inte rnal LDO
2.3V
MCU LDO
1.5V to 3.3V
HORNS L
Horn Drive r
HORN_EN
Battery Test
Loa d
VMCU
HORNFB
HORN_SEL
HORNB R
PGND
PGND
MCUSE L
LED Dr ive r A
ADVANCE INFORMATION
INT_DIR
INT_UNIT
INT_MCU
Inte rco nnect
Inte rface
VBS T
DINA
Temperature
Compensated
DAC
+
±
VINT
CSA
PDAC_A
SCL
LED Dr ive r B
SDA
I2C Interface
DINB
VMCU
Temperature
Compensated
DAC
CSEL
+
±
CSB
PDAC_B
GPIO
HBEN
Digital Cor e
VINT
COTEST_EN
LEDEN
PREF_SEL
PREF
Pho to Reference
and CO Te st
DGND
Pho to Amplifier
AMUX_SEL
AMUX_BYP
AMUX
AOUT_PH
AMUX
PDO
COO
±
PDO
+
PDN
PDP
±
+
COP
CO Amplifier
+
CON
±
COO
VBS T
REF0P3
300mV
Reference
REF0P3_EN
LEDLDO_EN
LED LDO
LEDLDO
AGND
22
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TPS8802
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SLVSF25 – OCTOBER 2019
6.3 Feature Description
6.3.1 System Power-up
Shu tdo wn
VCC<VPWRD OWN
Acti ve
VCC>VPWRU P
INTLDO enab led
Registe rs load ed
Set BST_EN=1
Set VBST[0:3] =1h
Wait for BST_PG=1
MCUSE L sen se
Write to VBST[0:3] and
VMCUS ET[0:1]
Wait for VBST_PG=1
BST_PG=1
Ena ble MCU LDO
Wait for MCU_PG=1
MCU_PG=1
Power Up
Figure 1. Power-up State Diagram
The TPS8802 can power-up from a battery above 2V connected to the input of the boost converter. This is
achieved with an automatic power-up sequence. As soon as sufficient voltage is applied to the VCC pin (typically
>1.8V), the boost converter is enabled and set to 3.8V. In a 3V battery powered system where VCC is connected
to VBST, this raises the VCC and VBST voltage to provide power to the internal digital and analog blocks. The
VBST voltage must exceed the power-good threshold for the 3.8V setting (typically 95% of its target voltage) for
the power-up sequence to proceed. The MCUSEL pin is then sensed to determine the MCULDO voltage and
program the VMCUSET and VBST register accordingly. Table 1 indicates the VMCU and VBST setting for each
MCUSEL configuration. Once VBST reaches its power-good threshold again, the MCULDO is enabled and the
system waits for VMCU to reach its power-good threshold (typically 85% of its target voltage). It is only after
VMCU reaches its power-good threshold that I2C communication is allowed with the TPS8802. This sequence of
events is outlined in Figure 1 and Figure 2.
If the boost converter is not being used, the same power-up sequence occurs, but the boost converter is not able
to raise the voltage higher than what is supplied. A minimum of 3.6V on VBST is required to meet the initial
VBST power-good threshold. If the MCUSEL pin is selected for VMCU = 3.3V, then VBST is set to 4.7V and thus
must be above 4.5V for power-up. The minimum VCC voltage depends on the VMCU voltage. If VMCU is set to
1.5V, 1.8V, or 2.5V, provide over 2.6V to VCC. If VMCU is set to 3.3V, provide over 3.6V to VCC.
Table 1. VMCU and VBST Power-up Voltage
MCUSEL Connection
VMCU
VBST
620-Ω to GND
1.5 V
2.7 V
Short to GND
1.8 V
2.7 V
Short to VINT
2.5 V
3.8 V
330-pF to GND
3.3 V
4.7 V
Copyright © 2019, Texas Instruments Incorporated
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ADVANCE INFORMATION
BST_PG=1
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SLVSF25 – OCTOBER 2019
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VBA T
VPWRU P
VBST_PG
VBST_PG
VBS T
tBST_PG
tBST_PG
BST_PG
MCUSE L_EN
ttMCU SELt
VMCU LD O,PG
tMCU LD O_PG
MCU_PG
Figure 2. Power-up Timing Diagram
6.3.2 Photo Chamber AFE
PDO
To A MUX
10 pF
VINT
+
7 pF
PAMP_EN
+
To A MUX
1.5 M
PDN
VINT
±
ADVANCE INFORMATION
VMCU
PGA IN_EN
470 k
PDP
Pho tod iode
±
PGA IN[1:0]
10 pF
1.5 M
Pho to Reference
1
5mV
±
+
50mV
PREF_SEL
0
PREF_SEL=1
+
±
PREF_SEL=0
PGA IN_EN
PAMP_EN
PREF
To CO Amp
Figure 3. Photo Amplifier Circuit
24
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TPS8802
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SLVSF25 – OCTOBER 2019
The TPS8802 photo amplifier connects to a photoelectric chamber’s photodiode and has two stages—an input
stage and gain stage. The output of each stage is connected to the AMUX for ADC reading. This configuration
provides a high dynamic range for the photodiode signal chain as the gain stage is on-the-fly adjustable.
6.3.2.1 Photo Input Amplifier
The input stage is a wide-bandwidth, low-offset op-amp designed for amplifying photodiode currents. Negative
feedback causes the photodiode to conduct with zero voltage bias. The photo-current flows through resistors
connected from PDP to GND/PREF and PDN to PDO. These two resistors determine the gain of the input stage.
The same value must be used for these two resistors because PDP and PDN leakage is amplified by these
resistors. This amplification affects the output if the resistors are not matched. Capacitors installed in parallel with
the resistors compensate the op-amp feedback loop for optimal response. It is recommended to use 5 pF when
the input amplifier is referenced to PREF, and 10pF when the input amplifier is referenced to GND. The 470 kΩ
resistor and 7 pF capacitor stabilize the feedback loop. The input stage outputs through the PDO pin, which is
internally connected to the integrated photo gain stage and AMUX.
6.3.2.2 Photo Gain Amplifier
The high-bandwidth, low noise photo gain amplifier connects to the output of the photo input stage to further
amplify the photodiode signal. The gain amplifier is adjustable on-the-fly using the I2C interface. The gain
amplifier has four settings:
• 5x
• 11x
• 20x
• 35x
The gain stage has the option of being referenced to GND or PREF with the PREF_SEL bit. When the PREF
reference is used, the gain stage output is kept above 50 mV. Referencing the gain stage to PREF causes the
50 mV reference to change depending on the PDO signal level. Because the reference is changing with the
signal level, the gain is slightly different. The gain stage output with zero photo-current varies when the gain
setting changes to keep the output above 50 mV.
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ADVANCE INFORMATION
The input stage has the option of being referenced to GND or PREF. PREF is a reference that is normally pulled
to VINT and is set to 50 mV when PREF_SEL = 1 and either PAMP_EN = 1 or PGAIN_EN = 1. The 50-mV
reference keeps the input amplifier in a linear operating region when no signal is applied, improving the speed
and zero-current sensitivity of the amplifier.
TPS8802
SLVSF25 – OCTOBER 2019
www.ti.com
6.3.3 LED Driver
VBS T
LEDLDO
IR LED
Blue LE D
VBA T
LEDLDO
LEDLDO_EN
LED LDO
LEDLDO[0:2]
1k
DINA
PLDO
TEMPCOA[1:0]
PDACA[7:0]
LED
DAC
Blue/IR
LED
+
100 F
±
CSA
GPIO[0:2]
To MCU
ADVANCE INFORMATION
To MCU
GPIO
PGND
GPIO
Log ic
LEDEN
IR LED
Blue LE D
VBA T
LEDLDO
LEDPIN_EN
LEDSE L=0
1k
DINB
Blue/IR
LED
PLDO
TEMPCOB[1:0]
PDACB[7:0]
LED
DAC
+
100 F
±
CSB
PGND
Figure 4. LED Driver Circuit
6.3.3.1 LED Current Sink
The two LED drivers are current regulated, temperature compensated, and adjustable with an 8-bit DAC. When
the LED driver is enabled, the CSA voltage is regulated, and the current through the CSA resistor also flows
through the LED and the DINA pin. A current sense resistor connects to the CSA pin and its resistance is
selected based on the required current through the LED. The LED driver is enabled with the LEDEN pin and
LEDPIN_EN bit. Both the pin and bit must be high for the LED driver to operate. The LEDSEL bit switches which
driver the LEDEN signal connects to. The GPIO pin can be configured to enable either LED driver.
The LED driver is temperature compensated to account for reduced LED intensity with increasing temperature.
Four temperature compensation settings are available to support a variety of IR and blue LEDs. Temperature
compensation is implemented by varying the CSA pin’s voltage with temperature, thus the temperature
compensation also depends on the CSA resistor.
Ensure that the LED current remains below 550 mA, and that the pulse width remains below 1 ms, and the duty
cycle remains below 1%. There is no protection to prevent operation outside these conditions, thus care must be
taken when using the LED driver to set the CSA resistor, registers, and the pulse width to safe levels.
26
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6.3.3.2 LED Voltage Supply
Enough voltage must be provided to the LED such that the DINA voltage is at least the dropout voltage
(VDINA,DROP) above the CSA voltage while the LED driver is enabled. The DINA voltage must not exceed 11.5V.
Because of the high LED drive currents, a large capacitor connected to the LED anode is required to provide
pulsed power to the LED. Any supply meeting the voltage requirements can be used to charge the LED
capacitor. Depending on the LED’s forward voltage, the LED anode can be connected to the battery or to the
LEDLDO. Do not connect the LED anode directly to VBST in low-power applications, because the large capacitor
charges and discharges every time the boost converter is enabled, wasting substantial power.
The LED LDO clamps the VBST voltage and blocks reverse current with an integrated diode. It is current limited
to prevent inrush current caused by charging the large capacitor. The regulation voltage is adjustable in the
LEDLDO register. The LED LDO may be operated with VBST below the regulation voltage. In this case, the
LEDLDO voltage will stabilize to VBST minus a diode voltage drop.
6.3.4 Carbon Monoxide Sensor AFE
To A MUX
RI=100 k
ADVANCE INFORMATION
COSWRO=1
COO
0.22 …F
COSWRG=1
VINT
COSWRI=1
RI=1 k
CON
±
COAMP_EN
Working
COP
10 k 100 k
+
CO
Sen sor
Counter
COSWREF=1
COREF[1:0]
+
±
PREF
To P hoto A mp
PREF_SEL=0
VINT
200 k
PREF_SEL=1
100 k
VINT
COTEST_EN
To MCU G PIO
COTEST_DIR
Figure 5. Carbon Monoxide Detection Circuit
The TPS8802 CO AFE connects to an electrochemical CO sensor. The amplifier converts the microamps of
sensor current into a voltage readable by an ADC. This is achieved with a low-offset, low-power op-amp with
configurable input, gain, and output resistors.
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6.3.4.1 CO Transimpedance Amplifier
The CO transimpedance amplifier is a low-offset, low-power op-amp with integrated input, gain, and output
resistors. Each of these resistors can be disconnected using the COSW register bits if external resistors are
preferred. The input resistor limits amplifier current during a CO sensor connectivity test. The gain resistor
amplifies the CO sensor signal. Adjust the gain resistor by changing the COGAIN register bits. Use the output
resistor to filter the CO amplifier output signal.
The CO amplifier has two integrated references. A 1.25-mV to 5-mV reference is internally connected to the opamp positive terminal. A 300-mV reference is connected to the REF0P3 pin. When the millivolt reference is used,
the CO sensor must be connected to GND. The millivolt reference is amplified to offset the amplifier’s output
above GND. When the 300 mV reference is used, the reference offsets the CO amplifier output by 300 mV. In
general, either reference can be used. The 300-mV reference offers slightly better DC accuracy at the cost of
extra power consumption. The 300 mV reference is generated with a reference and op-amp buffer for high
precision. The REF0P3 pin must connect to a 1 nF capacitor for stability. The buffer is designed to source and
sink small currents as required by the CO amplifier. Do not use both the 300 mV reference and the 1.25 mV to
5mV reference simultaneously.
A resistor connected in parallel with the CO sensor prevents charge from accumulating across its terminals. The
output of the CO amplifier is connected to the COO pin for continuous monitoring and the AMUX for periodic
sampling.
ADVANCE INFORMATION
6.3.4.2 CO Connectivity Test
The built-in CO connectivity test function connects to the PREF pin and is available when the photo amplifier is
not referenced to PREF. A pull-up and pull-down switch is programmable with the COTEST_EN and
COTEST_DIR register bits. A 200 kΩ pull-up resistor charges the 1 µF capacitor when the CO test is not in use.
When PREF is pulled low, charge is injected into the amplifier and the output pulse shape can be used to
determine if the sensor is connected.
6.3.5 Boost Converter
33 H
VLX
To B attery
VBS T_CLIM[3:0]
4.7 F
VBS T[3:0]
DCDC
Boo st
Hysteretic
Controller
BST_EN
BST_CHA RG E
BST_PG
VBS T
4.7 F
BST_nACT
PGND
To L ED LDO, Battery Test,
Horn Drive r, Inte rco nnect
Figure 6. DC to DC Hysteretic Boost Circuit
The boost converter operates with a wide range of input and output voltages to support multiple battery
configurations and driver voltages. The boost converter is internally connected to the LED LDO, interconnect
driver, horn driver, and battery test load, and may be externally connected to VCC. The boost converter has a
power-good register bit BST_PG to notify the MCU when the boost converter is above 95% of the target voltage.
The BST_PG signal is deglitched for 200 μs to prevent line or load transients from causing a false indication. If
the BST_PG signal is low after 10 ms of enabling the boost or changing the VBST setting, the BST_ERR signal
latches high. The BST_PG signal reads low if the boost converter is disabled.
The boost converter is enabled if any of the following conditions are met:
• BST_EN = 1, except if SLP_BST = 1 and SLP_EN = 1
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•
•
•
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BST_CHARGE = 1
VCCLOW_BST = 1 and the deglitched VCCLOW comparator trips
Device is in MCULDO_ERR state
The SLP_BST signal disables the boost while the device is in sleep mode if the boost is enabled with BST_EN.
The BST_CHARGE register bit enables the boost converter until the BST_PG signal is high, at which point
BST_CHARGE resets to 0 and the boost converter is disabled. VCCLOW_BST enables the boost if the
deglitched VCCLOW comparator trips. MCULDO_ERR state also enables the boost converter.
6.3.5.1 Boost Hysteretic Control
When the VBST voltage is above the boost regulation voltage, the boost does not switch. In a battery backup
system, the battery draws no power while the AC/DC supply is providing VBST voltage above the boost
regulation voltage. The boost starts switching if the AC/DC supply drops, drawing power from the battery to
regulate VBST. A timer, BST_nACT, monitors the time that the boost is not switching to notify the MCU if the
boost is inactive. This timer is programmable from 100 µs to 100 ms. This timer can be used to determine if the
battery voltage is higher than the regulation voltage or if an AC/DC supply is connected.
The default inductor peak current maximum is 500 mA. This sets the boost converter to provide maximum output
current by default. After the TPS8802 is powered, the peak current can be adjusted using the I2C interface to
change the boost switching frequency or to limit the battery current. The switching frequency is inversely
proportional to the square of the current limit. For example, changing the current limit from 500 mA to 50 mA
causes the frequency to increase by a factor of 100. The peak current determines how much current the boost
converter can output. Equation 1 calculates the maximum boost output current.
IOUT :max ; =
D × VBAT × IPEAK
2 × VBST
(1)
In a typical heavy load condition, the boost efficiency is approximately 85%. If the boost output current draw
exceeds the maximum, the boost voltage drops until the converter can supply the output current draw.
6.3.5.2 Boost Soft Start
When the boost converter is enabled and the VBST voltage is below 3 V, the peak inductor current is
automatically lowered to reduce inrush current. As a result, the boost converter cannot deliver full output current
while the VBST voltage is low. For the 2.7-V boost setting, the inductor current is released to the register value
when BST_PG = 1. It is recommended to maintain the VBST load current below 5 mA during the soft-start
period.
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The hysteretic control guarantees stability across input and output voltages and has a fast transient response.
When the VBST voltage is below its target, a charging cycle initiates by enabling the VLX switch until the current
through the inductor exceeds the programmable inductor peak current setting. Once the peak current is reached,
the VLX switch is disabled and the inductor charges the VBST output capacitor. The charging cycle completes
when the inductor current reaches zero, and a new cycle initiates when VBST drops again.
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6.3.6 Interconnect Driver
VBS T
INT_EN
Ena ble
INTDIR
INT_EN
INT_UNIT
VINT
INT_DIR
To MCU
INT_MCU
To S TA TUS1
Registe r
Digital
Deglitch
+
INT_UNIT
Inte rco nnect
Bus
±
INT_HYS
+
35 M
INT_DEG
Ena ble
±
INT_UNIT
Inte rrupt
STATUS_INT
Ena ble
INT_EN
ADVANCE INFORMATION
INT_PD
INTDIR
Figure 7. Interconnect Driver and Receiver
In mains-wired smoke alarm systems, the alarms can alert each other of smoke conditions with a wired
interconnect bus. The TPS8802 has a driver and comparator to interface with the interconnect bus. The driver
pulls the bus high when smoke is detected and low when smoke is cleared. The driver is current limited to
handle short circuit conditions, and has a diode on the high side driver to prevent the bus from driving VBST. The
hysteretic comparator senses when the bus is pulled high, filters the signal with a digital deglitch, and outputs the
result to the INT_MCU pin and STATUS1 register. The comparator output is synchronized with the 32 kHz clock.
The hysteresis has two settings and the deglitch is programmable from 0 ms to 20 ms. A 35-MΩ resistor
prevents the INT_UNIT pin from floating, and a switchable 100-kΩ resistor pulls down the bus to prevent leakage
from causing a false alarm. When the comparator outputs a high signal through the deglitch filter, the INT_UNIT
register bit is latched high in the STATUS1 register.
The INT_MCU pin has the additional function to output status interrupt signals. The STATUS_INT bit in the
MASK register will enable interrupt signals to output through the INT_MCU pin. However, when the interconnect
driver is enabled, the interrupt signal output is disconnected to allow the microcontroller to drive the INT_MCU
pin.
6.3.7 Piezoelectric Horn Driver
The horn driver is designed to drive two types of piezo horns: three-terminal self-resonant piezos and twoterminal piezos. The HORN_SEL bit configures the horn driver for the three-terminal or two-terminal operation.
During operation, 120-kΩ pulldown resistors discharge any residual charge on the piezo element. Because VBST
powers the horn driver, the loudness of the horn can be adjusted by changing the VBST voltage with the VBST
register bits.
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6.3.7.1 Three-Terminal Piezo
HORNFB
5.6 M
2.4 M
1nF
1M
0 k to 500 k
220 k (typ)
VBS T
0
HORNS L
1
HORN_THR
Horn Drive r
Log ic
HORN_SEL
VBS T
1
HORNB R
HORN_EN
HBEN
3-terminal
ena ble
Driver
ena ble
HORN_SEL
HORN_EN
120 k
0
2-terminal
ena ble
HORN_SEL=0 for 2 Terminal Piezo
HORN_SEL=1 for 3 Terminal Piezo
Figure 8. Three-Terminal Piezoelectric Horn Driver Circuit
In the three-terminal mode, the piezo silver and brass terminals connect directly to the HORNSL and HORNBR
pins, and the feedback terminal connects through a resistor-capacitor network to the HORNFB pin. The driver is
enabled and begins oscillating when the HORN_EN register bit and HBEN pin are set high. Adjust the value of
the resistor connected to the piezo feedback terminal to tune the oscillation frequency. Trial and error is required
to select this resistance. After the driver achieves resonant oscillation, the duty cycle of the HORNSL and
HORNBR outputs can be adjusted using the HORN_THR bits to maximize the loudness. It is recommended to
try each HORN_THR value and select the one that operates the horn closest to 50% duty cycle.
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ADVANCE INFORMATION
From MCU
120 k
HBEN
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6.3.7.2 Two-Terminal Piezo
HORNFB
From MCU
VBS T
0
HORNS L 1 mH
1
HORN_THR
Horn Drive r
Log ic
HORN_SEL
VBS T
1
HORNB R
From MCU
ADVANCE INFORMATION
HORN_EN
HBEN
3-terminal
ena ble
Driver
ena ble
HORN_SEL
HORN_EN
120 k
0
120 k
HBEN
2-terminal
ena ble
HORN_SEL=0 for 2 Terminal Piezo
HORN_SEL=1 for 3 Terminal Piezo
Figure 9. Two-Terminal Piezoelectric Horn Driver Circuit
In the two-terminal mode, the piezo connects to the HORNSL and HORNBR terminals through an inductor. The
HORNFB pin directly controls the HORNSL pin, and the HBEN pin directly controls the HORNBR pin. These two
drivers are matched to minimize skew between the two outputs. The MCU sends an arbitrary PWM signal to
control the driving voltage across the piezo. The PWM signal can be a square wave of the oscillation frequency,
a sine wave of the oscillation frequency, or an arbitrary shape for voice applications. The inductor improves the
rise time and fall time of the output and reduces power dissipation.
6.3.8 Battery Test
The battery test load is used to check the integrity of the battery connected to the TPS8802 device. When
enabled, a load is connected to VBST. The load is programmable from 10 mA to 20 mA with the I_BATTEST
register bits. This load emulates the horn driver current draw during an alarm condition. The boost input voltage,
output voltage, and efficiency affect the current drawn from the battery because the battery test load is
connected to VBST. Therefore, the battery current is programmable with the VBST register as well. The battery
test load is accurate only when VBST is greater than 4.5 V. The load is enabled with the BATTEST_EN register
bit or with the GPIO register bit and pin.
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6.3.9 AMUX
AMUX_BYP
AMUX_SEL[1:0]•0
VINT
To MCU
ADC
4.7 k
AMUX
330 pF
0
Hi-Z
COO
1
AMUX AOUT_PH
2
PDO
3
AMUX_BYP AMUX_SEL[1:0]
The AMUX switch and buffer are used to connect the various TPS8802 amplifier outputs to a single ADC. The
unity-gain amplifier improves the drive strength and fidelity of the analog signals when connected to an ADC. A
capacitor must be connected to the AMUX pin to stabilize its output; a 330 pF to 1 nF capacitor is recommended.
The 4.7-kΩ resistor filters high-frequency noise in the analog signal. The buffer has the option of being bypassed
to remove the added offset introduced by the unity-gain amplifier. Because the AMUX requires the bias block
(see Analog Bias Block and 8 MHz Oscillator section), bypassing the buffer does not eliminate the AMUX current
consumption.
6.3.10 Analog Bias Block and 8 MHz Oscillator
A central analog bias block connects to many of the amplifiers, drivers, and regulators. This block is enabled
when any of its connected blocks are enabled. Similarly, an internal 8-MHz oscillator is enabled when the boost
converter or photo input amplifier is enabled. Table 2 lists the conditions when the bias block and 8-MHz
oscillator are enabled. The bias block and 8-MHz oscillator consume current in addition to the connecting blocks
whenever they are enabled. Because the specified current consumption of each block does not include the bias
block or the 8-MHz oscillator, be sure to consider the bias block and 8-MHz oscillator currents when calculating
system power consumption.
Table 2. Conditions for Enabling the Bias Block and 8 MHz Oscillator
BLOCK
CONDITION
BIAS ENABLED?
8-MHZ OSC ENABLED?
Photo input amplifier
PAMP_EN = 1
Yes
Yes
Boost converter
BST_EN = 1
Yes
Yes
AMUX buffer
AMUX_SEL[0:2] ≠ 000
Yes
No
Horn driver
HORN_EN = 1
Yes
No
LED LDO
LEDLDO_EN = 1
Yes
No
Photo gain amplifier
PGAIN_EN = 1
Yes
No
Battery test load
BATTEST_EN = 1
Yes
No
LED driver
LEDEN = VMCU and
LEDPIN_EN = 1
Yes
No
Temperature monitor
OTS_EN = 1
Yes
No
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Figure 10. Analog Multiplexer Circuit
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6.3.11 Interrupt Signal Alerts
SLP_DONE
SLP_DONEM
VCCLOW
VCCLOWM
MCULDO_ERR
MCULDO_ERRM
OTS_ERR
OTS_ERRM
Inte rrupt
Sign al
To G PIO L ogic
To Interconne ct B lock
OTS_WRN
OTS_WRNM
BST_nACT
BST_nACTM
BST_ERR
BST_ERRM
Figure 11. Interrupt Signal Alert Logic
ADVANCE INFORMATION
Configurable interrupt signals notify the MCU when a system anomaly occurs. The interrupt signal indicates the
STATUS1 register, which has bits that latch high when reaching various condition limits such as temperature or
voltage. Each of the bits in the STATUS1 register can be independently configured to send an interrupt signal by
setting the MASK register bit corresponding to each STATUS1 bit. The GPIO[2:0] bits must be set to 0x2 to
output interrupt signals through the GPIO pin, and the STATUS_INT bit must be set to 1 to output interrupt
signals through the INT_MCU pin. By connecting the GPIO or INT_MCU pin to the microcontroller, the MCU can
be immediately notified when a STATUS1 bit changes instead of having to repeatedly read the STATUS1
register. After the device sends the interrupt signal, the signal remains high until the STATUS1 register is read, at
which point the fault clears if the error condition is removed.
Under some conditions the INT_MCU pin has other functions. If INT_EN = 1 and INT_DIR = 0, the INT_MCU pin
also outputs the INT_UNIT pin status. If INT_EN = 1 and INT_DIR = 1, the INT_MCU pin becomes an input to
control the INT_UNIT driver. See Interconnect Driver for more information.
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6.4 Device Functional Modes
6.4.1 Sleep Mode
Active
SLP_EN=1
Timeout
Set SLP_DONE=1
Set SLP_EN=0
Ena ble MCU LDO an d b oost
if pr evio usly enab led
Write S LP_EN=0 to E NA BLE2 regi ster
Start sleep timer
Sleep Mode
Figure 12. Sleep Mode State Diagram
The device integrates a sleep timer to help manage critical analog and regulator blocks independent of the
external microcontroller. When sleep mode is enabled, the timer starts and various blocks (MCU LDO, boost, or
drivers and amplifiers) are disabled depending on the CONFIG1 register configuration. After the sleep timer
finishes, the SLP_DONE bit in STATUS1 register is latched high and can be configured to output through the
GPIO or INT_MCU pins. This notifies the microcontroller that the sleep timer is finished and sleep mode is
exited. Alternatively, sleep mode is exited by writing zero to the SLP_EN bit. This does not trigger the
SLP_DONE bit in the STATUS1 register. Figure 13 shows the sleep mode state diagram.
Sleep
• by
• by
• by
mode reduces power consumption in three ways:
quickly disabling analog blocks
powering off the boost and MCU LDO during sleep mode
allowing the MCU to enter its lowest power idle state
Every I2C transaction takes time and consumes a small amount of power. The SLP_ANALOG bit configures
sleep mode to disable high-power amplifiers and drivers simultaneously when entering sleep mode. This
functionality can save several I2C transactions and reduces time that the amplifiers and drivers are idly enabled.
The device may require the boost converter and MCU LDO while the microcontroller is performing sensing and
testing operations, but may not require the boost and MCU LDO while the microcontroller is in its idle state.
SLP_BST and SLP_MCU disable the boost converter and MCU LDO during sleep mode. If the boost converter
and MCU LDO were previously enabled, they are re-enabled when sleep mode is exited. This process reduces
system current consumption caused by the MCU LDO and boost converter while preventing a system brown-out
if the MCU loses power, because the exit of sleep mode returns power to the MCU.
During sleep mode operation, the MCU can enter its lowest power idle state and monitor a GPIO pin for the
SLP_DONE interrupt signal. This monitoring allows the MCU clocks to be disabled as the sleep timer signals the
MCU to wake up after a precise programmed time. The amount of time is programmable from 1 ms to 65535 ms
in 1 ms intervals in the SLPTMR1 and SLPTMR2 registers.
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Disa ble MCU LDO if SLP_MCU=1
Disa ble boost if S LP_BST=1
Disa ble high-current analog bl ocks if
SLP_ANALO G=1
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Device Functional Modes (continued)
The TPS8802 is nearly fully functional in sleep mode. The microcontroller can access all registers and configure
all blocks. Only three functions are disabled in sleep mode:
• boost converter inactivity timer
• the MCULDO fault state
• over-temperature shutdown fault state
The MCULDO undervoltage and system over-temperature monitors remain enabled if the MCU LDO and OTS
monitors are enabled, so as soon as the device exits sleep mode, the system enters the fault state that
corresponds to any detected fault.
6.4.2 Fault States
Active
ADVANCE INFORMATION
Set MCULDO_ERR=1
Set OTS_ERR=1
MCUERR_DIS=1
MCU_PG=0 afte r 10 ms
of e nabling MCU LDO or
changi ng V MCUSET
TJ>125°C afte r 300 µs
of e nabling O TS_EN
MCUERR_DIS=0
Ena ble boost converter
Ena ble tempe ratu re mo nito r
Disa ble amplifiers an d d rive rs
TJ>125°C
Start 1-second timer
TJ>110°C
Start 1-second timer
MCU_PG=0
Timeout
Check MCU_PG
Check TJ
TJ<110°C
MCU_PG=1
Ena ble blocks if previou sly
ena bled
Ena ble blocks if previou sly
ena bled
No
Timeout
Was O TS entere d from MCU
LDO fa ult state?
Read STATUS1 regi ster wh ile MCU_PG=1
Read STATUS1 regi ster wh ile TJ<110°C
Ena ble tempe ratu re mo nito r
Disa ble amplifiers, drivers, boo st,
and MCU LDO
Yes
Ove r-Temperature Shutdow n
MCU LDO Fault
Figure 13. Fault States Diagram
The TPS8802 has several monitors to alert the MCU when system irregularities occur. In addition to alerting the
MCU, two monitors cause the TPS8802 to enter protective fault states:
• MCULDO under-voltage
• system over-temperature
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Device Functional Modes (continued)
The fault states reduce risk of damage and brown-outs to the system in the event of short circuits or other power
errors.
6.4.2.1 MCU LDO Fault
The MCU LDO has an undervoltage monitor to notify the MCU if the LDO falls out of regulation. This monitor is
enabled any time the MCU LDO is enabled and its status is in the MCU_PG register bit. A 200-μs deglitch time
rejects load and line transient spikes that may briefly drop the MCU LDO voltage below the under-voltage
threshold. If MCU_PG is low while the MCU LDO is enabled and it has been more than 10 ms since the LDO
was enabled or changed voltage, the MCU_ERR register bit latches high. When the MCU_ERR bit is set high
and the MCUERR_DIS bit is low, the MCU LDO fault state is entered.
If the input voltage drops, it is likely because the boost converter is disabled. If the load current exceeds the LDO
current limit, the die temperature could exceed safe limits. The MCU fault state automatically enables the boost
converter and temperature monitor (OTS_EN) to handle both of these cases. The device disables all analog
blocks to prevent further issues caused by an underpowered MCU.
There are two methods that cause the device to exit the fault state. Every second in the fault state, the MCU_PG
register bit is automatically read. If high, the fault state is exited. The MCU_ERR bit remains high until the
STATUS1 register is read. Alternatively, if the STATUS1 register is read and MCU_PG is high, the fault state is
exited. When the device exits the MCU_ERR fault state, the device re-enables all blocks that were enabled
before the fault state occurred.
If an over-temperature fault occurs while in the MCU LDO fault state, the device enters the over-temperature fault
state. The over-temperature fault state disables the MCU LDO and boost converter in addition to the blocks that
are disabled by the MCU LDO fault state. After the device exits the over-temperature fault state, it immediately
re-enters the MCU LDO fault state to confirm the MCU LDO status.
6.4.2.2 Over-Temperature Fault
An over-temperature shutdown (OTS) fault occurs if OTS_EN = 1 and the die temperature exceeds 125°C. The
fault is masked for 300 μs after setting OTS_EN = 1. OTS_EN must be enabled for at least 300 μs in order to
determine if the die has overheated. After the device detects an over-temperature condition, it disables all
drivers, amplifiers, and regulators and sets OTS_ERR to 1. This action prevents additional temperature stress
caused by a short circuit.
Similar to the MCU LDO fault, the device exits the OTS fault state with two methods:
• The device checks the die temperature once every second. If the temperature is below 110°C, the device
exits the fault state.
• Reading the STATUS1 register with the die temperature below 110°C exits the fault state.
When the device exits the OTS fault state, it re-enables all blocks that were enabled before the OTS fault
occurred.
6.5 Programming
The TPS8802 serial interface follows the I2C industry standard. The TPS8802 supports both standard and fast
mode, and it supports auto-increment for fast reading and writing of sequential registers. A 33 kΩ pullup resistor
connecting the SDA and SCL pins to VMCU is recommended for fast mode operation. The VMCU voltage
determines the logic level for I2C communication. The CSEL pin selects the device address. When CSEL is
pulled to GND, the device address is 0x3F. When CSEL is pulled to VMCU, the device address is 0x2A.
6.6 Register Maps
Table 3 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in
Table 3 should be considered as reserved locations and the register contents should not be modified.
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Two scenarios can cause the LDO to drop voltage:
• input voltage (PLDO) drops
• load current exceeds the LDO current limit
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Table 3. Device Registers
Offset
Acronym
Register Name
0h
REVID
Revision ID
Section
Go
1h
STATUS1
Status 1
Go
2h
STATUS2
Status 2
Go
3h
MASK
Interrupt Mask
Go
4h
CONFIG1
Config 1
Go
5h
CONFIG2
Config 2
Go
6h
ENABLE1
Enable 1
Go
7h
ENABLE2
Enable 2
Go
8h
CONTROL
Control
Go
9h
SLPTMR1
Sleep Timer 1
Go
Ah
SLPTMR2
Sleep Timer 2
Go
ADVANCE INFORMATION
Bh
GPIO_AMUX
GPIO and AMUX
Go
Ch
CO_BATTEST
CO and Battery Test
Go
Dh
CO
CO Amplifier
Go
Eh
VBOOST
Boost Converter
Go
Fh
LEDLDO
LED LDO
Go
10h
PH_CTRL
Photo Amplifier
Go
11h
LED_DAC_A
LED DAC A
Go
12h
LED_DAC_B
LED DAC B
Go
Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for
access types in this section.
Table 4. Device Access Type Codes
Access Type
Code
Description
R
R
Read
RC
R
C
Read
to Clear
W
Write
Read Type
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
6.6.1 REVID Register (Offset = 0h) [reset = 0h]
REVID is shown in Table 5.
Return to Summary Table.
Table 5. REVID Register Field Descriptions
38
Bit
Field
Type
Reset
Description
7-0
RESERVED
R
0h
Reserved
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6.6.2 STATUS1 Register (Offset = 1h) [reset = 0h]
STATUS1 is shown in Table 6.
Return to Summary Table.
Table 6. STATUS1 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
SLP_DONE
RC
0h
Sleep timer wakeup flag
0h = device has not transitioned from sleep to active state via timer
1h = device transitioned from sleep to active state via timer
6
VCCLOW
RC
0h
VCC low warning
0h = no VCCLOW error has occurred
1h = VCC below V_VCCLOW,FALL threshold and VCCLOW_DIS=1
for VCCLOW deglitch time
5
MCULDO_ERR
RC
0h
MCU LDO power good error
1h = MCU_PG=0 and MCU_EN=1 for TMCULDO,PG.
MCULDO_ERR is masked for TMCULDO,MASK after VMCUSET or
MCU_DIS has changed
4
OTS_ERR
RC
0h
Thermal shutdown error
0h = no thermal shutdown error has occurred
1h = junction temperature has exceeded T_SHUTDOWN
3
OTS_WRN
RC
0h
Thermal warning flag
0h = no thermal warning has occurred
1h = junction temperature has exceeded T_WARNING
2
BST_nACT
RC
0h
Boost activity monitor
0h = boost converter is actively switching or BST_EN=0 or
SLP_EN=1
1h = boost converter has not switched for T_BST,ACT, BST_EN=1
and SLP_EN=0
1
BST_ERR
RC
0h
Boost converter power good error
0h = no boost converter error has occurred
1h = BST_PG=0 and BST_EN=1. BST_ERR is masked for
T_BST,MASK after VBST or BST_EN has changed
0
INT_UNIT
RC
0h
INT_UNIT pin value
0h = INT_UNIT is below VINT_UNIT,ILO or INT_DIR=1
1h = INT_UNIT is high and INT_DIR=0
6.6.3 STATUS2 Register (Offset = 2h) [reset = 0h]
STATUS2 is shown in Table 7.
Return to Summary Table.
Table 7. STATUS2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
Reserved
MCU_PG
R
0h
MCU LDO power good indicator
1
0h = MCU LDO is below power good threshold or MCU_DIS=1
1h = MCU LDO is above power good threshold and MCU_DIS=0
0
BST_PG
R
0h
Boost power good indicator
0h = MCU LDO is below power good threshold or BST_EN=0
1h = MCU LDO is above power good threshold and BST_EN=1
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ADVANCE INFORMATION
0h = no MCULDO error has occurred
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6.6.4 MASK Register (Offset = 3h) [reset = 0h]
MASK is shown in Table 8.
Return to Summary Table.
Table 8. MASK Register Field Descriptions
Bit
7
Field
Type
Reset
Description
SLP_DONEM
R/W
0h
Sleep timer wakeup interrupt mask
0h = interrupt on device transition from sleep to active state
1h = no interrupt on device transition from sleep to active state
6
VCCLOWM
R/W
0h
VCC low warning interrupt mask
0h = interrupt on VCC low
1h = no interrupt on VCC low
5
MCULDO_ERRM
R/W
0h
MCU LDO power good error interrupt mask
0h = interrupt on MCULDO power good error
1h = no interrupt on MCULDO power good error
4
OTS_ERRM
R/W
0h
Thermal shutdown error interrupt mask
0h = interrupt on thermal shutdown error
ADVANCE INFORMATION
1h = no interrupt on thermal shutdown error
3
OTS_WRNM
R/W
0h
Thermal warning flag interrupt mask
0h = interrupt on thermal warning
1h = no interrupt on thermal warning
2
BST_nACTM
R/W
0h
Boost activity monitor interrupt mask
0h = interrupt if boost has not switched for T_BSTACT
1h = no interrupt if boost has not switched for T_BSTACT
1
BST_ERRM
R/W
0h
Boost converter power good error interrupt mask
0h = interrupt on BST_PG transition from 1 to 0 while BST_EN=1
1h = no interrupt on BST_PG transition from 1 to 0 while BST_EN=1
0
STATUS_INT
R/W
0h
Status interrupt on the INT_MCU pin
0h = disable
1h = INT_MCU outputs high if any unmasked STATUS1 flags
6.6.5 CONFIG1 Register (Offset = 4h) [reset = 38h]
CONFIG1 is shown in Table 9.
Return to Summary Table.
Table 9. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
INT_DEG_1:0
R/W
0h
INT_UNIT deglitch control
0h = none
1h = 125us
2h = 1ms
3h = 20ms
5
INT_PD
R/W
1h
INT_UNIT pulldown resistor enable
0h = >1MOhm pulldown resistor on INT_UNIT
1h = 100k pulldown resistor on INT_UNIT
4-3
VMCUSET_1:0
R/W
3h
MCU LDO voltage. Default value is set by MCUSEL on power-up.
0h = 1.5V
1h = 1.8V
2h = 2.5V
3h = 3.3V
40
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Table 9. CONFIG1 Register Field Descriptions (continued)
Bit
2
Field
Type
Reset
Description
SLP_BST
R/W
0h
Disable boost converter in sleep mode
0h = boost converter unchanged in sleep mode
1h = BST_EN=0, BST_CHARGE=0 when SLP_EN is set to 1.
BST_EN=1 upon exiting sleep mode
1
SLP_ANALOG
R/W
0h
Disable analog blocks in sleep mode. Set AMUX_SEL=000,
BATTEST_EN=0, HORN_EN=0, INT_EN=0, LEDLDO_EN=0,
PAMP_EN=0, PGAIN_EN=0 when SLP_EN is set to 1.
0h = analog blocks unchanged in sleep mode
1h = analog blocks shut off in sleep mode
0
SLP_MCU
R/W
0h
Disable MCULDO in sleep mode
0h = MCULDO unchanged in sleep mode
1h = MCULDO shut off in sleep mode and re-enabled upon exiting
sleep mode
6.6.6 CONFIG2 Register (Offset = 5h) [reset = 2h]
ADVANCE INFORMATION
CONFIG2 is shown in Table 10.
Return to Summary Table.
Table 10. CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6
RESERVED
R
0h
Reserved
5
INT_HYS
R/W
0h
Interconnect comparator hysteresis
0h = 1.2V hysteresis
1h = 0.1V hysteresis
4
HORN_SEL
R/W
0h
Horn block piezo select
0h = 2-terminal piezo
1h = 3-terminal piezo
3-2
HORN_THR_1:0
R/W
0h
Horn driver setting for three-terminal piezo duty cycle tuning
0h = -6%
1h = -3%
2h = Nominal
3h = +3%
1-0
T_BSTACT_1:0
R/W
2h
Boost activity monitor alert time. BST_nACT flag goes high if the
boost converter has not switched for the set amount of time
0h = 100us
1h = 1ms
2h = 10ms
3h = 100ms
6.6.7 ENABLE1 Register (Offset = 6h) [reset = 10h]
ENABLE1 is shown in Table 11.
Return to Summary Table.
Table 11. ENABLE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6
BATTEST_EN
R/W
0h
Battery test enable
0h = disabled
1h = enabled
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Table 11. ENABLE1 Register Field Descriptions (continued)
Bit
5
Field
Type
Reset
Description
INT_EN
R/W
0h
Control of interconnect interface
0h = disable
1h = enable
4
BST_EN
R/W
1h
Boost converter control
0h = disabled
1h = Boost converter enabled
3
PAMP_EN
R/W
0h
Photo input amplifier control
0h = amplifier disabled
1h = amplifier enabled
2
PGAIN_EN
R/W
0h
Photo Gain amplifier control
0h = amplifier disabled
1h = amplifier enabled
1
RESERVED
R
0h
Reserved
0
LEDLDO_EN
R/W
0h
LED LDO control
0h = disabled
ADVANCE INFORMATION
1h = enabled
6.6.8 ENABLE2 Register (Offset = 7h) [reset = 0h]
ENABLE2 is shown in Table 12.
Return to Summary Table.
Table 12. ENABLE2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
LEDSEL
R/W
0h
LED input select
0h = LEDENA
1h = LEDENB
6
BST_CHARGE
R/W
0h
Enable boost while BST_CHARGE=1. When BST_PG=1, set
BST_CHARGE=0.
0h = boost controlled by BST_EN
1h = Boost is enabled until BST_PG=1. Boost remains enabled if
BST_EN=1.
5-4
3
RESERVED
R
0h
Reserved
INT_DIR
R/W
0h
Interconnect direction control
0h = from INT_UNIT to INT_MCU
1h = from INT_MCU to INT_UNIT
2
LEDPIN_EN
R/W
0h
LEDEN pin enable
0h = LEDEN pin does not enable LED block
1h = LEDEN pin enables LED block
1
HORN_EN
R/W
0h
Horn block enable
0h = Horn block disabled
1h = HBEN enables horn block
0
SLP_EN
R/W
0h
Sleep timer enable
0h = sleep timer disabled, sleep mode is exited
1h = sleep timer initialized - SLP_DONE is set to 1 and SLP_EN is
set to 0 after sleep timer expires
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6.6.9 CONTROL Register (Offset = 8h) [reset = 0h]
CONTROL is shown in Table 13.
Return to Summary Table.
Table 13. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
Reserved
MCU_DIS
R/W
0h
MCU LDO disable
5
0h = MCU LDO enabled
1h = MCU LDO disabled
4
VCCLOW_DIS
R/W
0h
VCCLOW brown-out monitor disable.
0h = VCCLOW monitor is enabled
1h = VCCLOW monitor is disabled
3
MCUERR_DIS
R/W
0h
MCULDO error mode disable
1h = disable entering FAULT mode in case of MCULDO error.
MCULDO_ERR flag is still raised.
2
OTS_EN
R/W
0h
Over-temperature shutdown mode disable
0h = disable entering over-temperature FAULT mode. OTS_ERR
and OTS_WRN are set to 0
1h = in case of over-temperature, FAULT mode is entered and
OTS_ERR flag is raised.
1
SOFTRESET
R/W
0h
Set registers to the default value
0h = do not reset registers
1h = reset all registers. SOFTRESET is reset. BST_EN,
BST_CHARGE, VBST, VMCUSET bits and STATUS1 register is
unchanged.
0
VCCLOW_BST
R/W
0h
VCCLOW boost control
0h = boost controlled by BST_EN
1h = boost enabled if VCCLOW=1 or BST_EN=1
6.6.10 SLPTMR1 Register (Offset = 9h) [reset = 0h]
SLPTMR1 is shown in Table 14.
Return to Summary Table.
Table 14. SLPTMR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SLPTMR_15:8
R/W
0h
Sleep timer most significant bits. See SLPTMR2 register for details
6.6.11 SLPTMR2 Register (Offset = Ah) [reset = 0h]
SLPTMR2 is shown in Table 15.
Return to Summary Table.
Table 15. SLPTMR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SLPTMR_7:0
R/W
0h
Sleep timer duration. If SLPTMR is changed while SLP_EN=1, the
new sleep timer setting will apply the next time SLP_EN is enabled.
Sleep timer can be exited early if SLP_EN is written 0.
0000h = Sleep timer is disabled. If SLP_EN=1, then the sleep timer
is enabled when SLPTMR is changed.
0001h to FFFFh = 1 ms to 65535 ms
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ADVANCE INFORMATION
0h = in case of MCULDO error, FAULT mode is entered and
MCULDO_ERR flag is raised.
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6.6.12 GPIO_AMUX Register (Offset = Bh) [reset = 0h]
GPIO_AMUX is shown in Table 16.
Return to Summary Table.
Table 16. GPIO_AMUX Register Field Descriptions
Bit
7
Field
Type
Reset
Description
AMUX_BYP
R/W
0h
Analog multiplexer bypass
0h = analog multiplexer buffer is enabled when AMUX_SEL[1:0] !=
000
1h = analog multiplexer buffer is bypassed with a low-resistance
switch
6
5-4
RESERVED
R
0h
Reserved
AMUX_SEL_1:0
R/W
0h
Analog multiplexer input select
0h = AMUX off
1h = COO
2h = AOUT_PH
3h = PDO
ADVANCE INFORMATION
3
2-0
RESERVED
R
0h
Reserved
GPIO_2:0
R/W
0h
Multi-purpose digital input and output
0h = Hi-Z
1h = TI Reserved
2h = output low if no status errors, high if any unmasked errors
3h = TI Reserved
4h = GPIO or LEDENA enables LED A
5h = GPIO or LEDENB enables LED B
6h = TI Reserved
7h = GPIO or BATTEST_EN enables battery test
6.6.13 CO_BATTEST Register (Offset = Ch) [reset = 0h]
CO_BATTEST is shown in Table 17.
Return to Summary Table.
Table 17. CO_BATTEST Register Field Descriptions
Bit
7
Field
Type
Reset
Description
COSWRO
R/W
0h
CO amplifier output resistor (output of amplifier to COO pin) enable
0h = 0 Ohms
1h = 100 kOhms
6
COSWRG
R/W
0h
CO gain resistor (output of amplifier to inverting input of amplifier)
enable
0h = Hi-Z
1h = Resistance set by COGAIN register
5
COSWRI
R/W
0h
CO input resistor (inverting input of amplifier to CON pin) enable
0h = 0 Ohms
1h = 1 kOhms
4
COSWREF
R/W
0h
CO reference switch enable
0h = COREF disconnected from positive input of amplifier
1h = COREF connected to positive input of amplifier
3
44
RESERVED
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R
0h
Reserved
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Table 17. CO_BATTEST Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
I_BATTEST_2:0
R/W
0h
Battery test current
0h = 10mA
1h = 12mA
2h = 14mA
3h = 16mA
4h = 18mA
5h = 20mA
6h = Reserved
7h = Reserved
6.6.14 CO Register (Offset = Dh) [reset = 0h]
CO is shown in Table 18.
Return to Summary Table.
Bit
7
Field
Type
Reset
Description
REF0P3_EN
R/W
0h
300mV reference enable
ADVANCE INFORMATION
Table 18. CO Register Field Descriptions
0h = Buffer disabled
1h = Buffer enabled
6-5
COREF_1:0
R/W
0h
Reference voltage for CO amplifier
0h = 1.25mV
1h = 2.5mV
2h = 3.75mV
3h = 5mV
4-3
COGAIN_1:0
R/W
0h
CO amplifier feedback resistance
0h = 1100 kOhm
1h = 300 kOhm
2h = 500 kOhm
3h = 800 kOhm
2
COTEST_DIR
R/W
0h
CO test output direction
0h = pull-down
1h = pull-up
1
COTEST_EN
R/W
0h
Enable COTEST output on PREF
0h = disabled
1h = enabled
0
COAMP_EN
R/W
0h
CO amplifier control
0h = disabled
1h = enabled
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6.6.15 VBOOST Register (Offset = Eh) [reset = F2h]
VBOOST is shown in Table 19.
Return to Summary Table.
Table 19. VBOOST Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BST_CLIM_3:0
R/W
Fh
Boost converter inductor peak current setting
0h = 30mA
1h = 40mA
2h = 50mA
3h = 60mA
4h = 80mA
5h = 100mA
6h = 130mA
7h = 160mA
8h = 200mA
9h = 240mA
ADVANCE INFORMATION
Ah = 280mA
Bh = 320mA
Ch = 360mA
Dh = 400mA
Eh = 450mA
Fh = 500mA
3-0
VBST_3:0
R/W
2h
Boost converter output voltage setting. Default value is set during
power-up based on MCUSEL pin.
0h = 2.7V
1h = 3.8V
2h = 4.7V
3h = 6V
4h = 9V
5h = 10V
6h = 10.5V
7h = 11V
8h = 11.5V
9h = 15V
Ah = Reserved
Bh = Reserved
Ch = Reserved
Dh = Reserved
Eh = Reserved
Fh = Reserved
6.6.16 LEDLDO Register (Offset = Fh) [reset = 0h]
LEDLDO is shown in Table 20.
Return to Summary Table.
Table 20. LEDLDO Register Field Descriptions
46
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0h
Reserved
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Table 20. LEDLDO Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-1
LEDLDO_2:0
R/W
0h
LED LDO settings
0h = 7.5V
1h = 8.0V
2h = 8.5V
3h = 9.0V
4h = 9.5V
5h = 10V
6h = Reserved
7h = Reserved
0
RESERVED
R
0h
Reserved
6.6.17 PH_CTRL Register (Offset = 10h) [reset = 0h]
PH_CTRL is shown in Table 21.
Table 21. PH_CTRL Register Field Descriptions
Bit
7
6-5
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
TEMPCOB_1:0
R/W
0h
LED B Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
4-3
TEMPCOA_1:0
R/W
0h
LED A Temperature Coefficient Setting
0h = 0.347 mV/C
1h = 0.416 mV/C
2h = 0.693 mV/C
3h = 1.040 mV/C
2
PREF_SEL
R/W
0h
Photo Reference setting
0h = 0mV
1h = Photo gain amplifier and PREF pin connected to 50mV internal
reference
1-0
PGAIN_1:0
R/W
0h
Photo Gain setting
0h = 5
1h = 11
2h = 20
3h = 35
6.6.18 LED_DAC_A Register (Offset = 11h) [reset = 0h]
LED_DAC_A is shown in Table 22.
Return to Summary Table.
Table 22. LED_DAC_A Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PDAC_A_7:0
R/W
0h
LED DAC A setting
00h to FFh = 0mV to 300mV
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ADVANCE INFORMATION
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6.6.19 LED_DAC_B Register (Offset = 12h) [reset = 0h]
LED_DAC_B is shown in Table 23.
Return to Summary Table.
Table 23. LED_DAC_B Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PDAC_B_7:0
R/W
0h
LED DAC B setting
00h to FFh = 0mV to 300mV
ADVANCE INFORMATION
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
ADVANCE INFORMATION
The TPS8802 supports a variety of smoke alarm platforms:
• single-wave or dual-wave photoelectric smoke and CO detection
• 3-V battery, 9-V battery, or AC/DC supply with battery backup
• tone or voice alarm
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7.2 Typical Application
AC/DC
Sup ply
33 …H
VBS T
VBA T
VCC
0.1 …F
VLX
PLDO
3V or 9V
Battery
4.7 …F
PGND
1 …F
VINT
1 …F
VMCU
1 …F
1M
220 k
HORNFB
To MCU
HORNS L
MCUSE L
Piezoe lectric Hor n
HORNB R
To S mo ke Ala rm
Inte rco nnect Bus
INT_UNIT
INT_MCU
To MCU G PIO
DINA
ADVANCE INFORMATION
VMCU
IR LED
33 k
33 k
47 …F
CSA
SCL
To MCU I²C
To MCU I²C
SDA
CSEL
DINB
To MCU G PIO
GPIO
To MCU G PIO
HBEN
To MCU G PIO
LEDEN
To MCU
DGND
Blue LE D
47 …F
CSB
LEDLDO
To MCU
ADC P ort
AMUX
PDO
330 pF
1.5 M
PDN
COO
CON
PDP
COP
REF0P3
5 pF
PREF
GND
Thermal Pad
Pho tod iode
1.5 M
100 k
CO
Sen sor
7 pF
470 k
0.22 µF
5 pF
AGND
RESERVE D
Figure 14. Dual-Wave Photoelectric Smoke and CO Alarm with Backup Battery
7.2.1 Design Requirements
In this example, a smoke alarm requires the following:
• 100 MΩ photoamplifier transconductance with sub-nanoamp detection
• 100mA IR LED current with 1mA/°C temperature compensation
• 50mA blue LED current with 0.1mA/°C temperature compensation
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Typical Application (continued)
7.2.2 Detailed Design Procedure
7.2.2.1 Photo Amplifier Component Selection
To meet the 100-MΩ photoamplifier transconductance requirement, set the gain stage to 35x with PGAIN = 11.
Because the application requires sub-nanoamp current detection, reference the photo amplifier to PREF and set
PREF_SEL = 1. This reference offsets the input stage output by 50 mV and offsets the gain stage output by 225
mV. Because the application uses PREF, the gain stage amplification reduces to 32.25x. Divide 100 MΩ by
32.25x to get 3.1 MΩ. The gain is distributed across two resistors, therefore use a resistor with a value of
approximately 1.55 MΩ. A 1.5-MΩ resistor is selected. The achieved transconductance is 96.8 MΩ. Use 5-pF of
compensation capacitance in parallel with the 1.5-MΩ resistors and connect a 470-kΩ resistor in parallel with the
photodiode. Depending on the photodiode capacitance, the 5-pF and 7-pF capacitors may need to be adjusted to
achieve the fastest amplifier step response.
The LED current depends on the TEMPCO bits, PDAC registers and CSA resistor. Changing any of these values
affects the LED current and temperature compensation. The following method can be used to select which
TEMPCO, PDAC, and CSA resistor values to use. The 100-mA LED current and 1 mA/°C temperature
compensation is used as an example.
1. Determine the room temperature current and temperature compensation required by the application.
– 100mA and 1mA/°C is required by the design.
2. Calculate the compensation in percentage per degree by dividing the compensation coefficient by the current
and multiplying by 100.
– 1mA/°C divided by 100mA is 1%/°C.
3. Use Table 24 to select a TEMPCO setting which contains the desired compensation.
– 1%/°C is between the mimumum and maximum for TEMPCO = 11.
– If the required temperature coefficient is not in any of the ranges, choose the TEMPCO and PDAC setting
closest to the required temperature coefficient. Skip step 4.
4. Calculate the target CSA voltage. Divide the driver temperature coefficient [mV/°C] by the desired
temperature coefficient [%/°C] and multiply by 100.
– 1.040 mV/°C divided by 1 %/°C is 104 mV.
5. Calculate the CSA resistor by dividing the target CSA voltage by the required current.
– 104mV divided by 100mA is 1.04 Ω.
6. Select the closest available resistor and calculate the final CSA voltage by multiplying the required current by
the resistance.
– Use a 1 Ω resistor. Multiply 100 mA and 1 Ω to get 100mV CSA voltage.
7. Calculate the PDAC value by subtracting the CSA voltage by the CSA voltage at PDAC = 0x00 and dividing
the result by 1.176 mV (the DAC LSB, equal to 300 mV divided by 255).
– 100 mV minus 83 mV is 17mV, divided by 1.176mV is 14. Write 0x0E to PDAC register.
Table 24. Temperature Coefficients for Each TEMPCO and DAC setting
Register Setting
CSA Voltage [mV], T =
27°C
Temperature Coefficient
[mV/°C]
Temperature Coefficient
[%/°C]
Coefficient Detail
TEMPCO[1:0] = 11,
PDAC = 0x00
83
1.040
1.253%
Max for TEMPCO = 11
TEMPCO[1:0] = 11,
PDAC = 0xFF
383
1.040
0.272%
Min for TEMPCO = 11
TEMPCO[1:0] = 10,
PDAC = 0x00
188
0.693
0.369%
Max for TEMPCO = 10
TEMPCO[1:0] = 10,
PDAC = 0xFF
488
0.693
0.142%
Min for TEMPCO = 10
TEMPCO[1:0] = 01,
PDAC = 0x00
273
0.416
0.152%
Max for TEMPCO = 01
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Typical Application (continued)
Table 24. Temperature Coefficients for Each TEMPCO and DAC setting (continued)
Register Setting
CSA Voltage [mV], T =
27°C
Temperature Coefficient
[mV/°C]
Temperature Coefficient
[%/°C]
Coefficient Detail
TEMPCO[1:0] = 01,
PDAC = 0xFF
573
0.416
0.073%
Min for TEMPCO = 01
TEMPCO[1:0] = 00,
PDAC = 0x00
294
0.347
0.118%
Max for TEMPCO = 00
TEMPCO[1:0] = 00,
PDAC = 0xFF
594
0.347
0.058%
Min for TEMPCO = 00
Use the same procedure for the blue LED, requiring 50 mA and 0.1mA/°C, to calculate TEMPCOB = 10, RCSB =
6.8 Ω, VCSB = 340 mV, PDACB = 0x81.
The two drivers are identical, so the use of DINA for the IR LED and DINB for the blue LED is arbitrary.
7.2.2.3 LED Voltage Supply Selection
ADVANCE INFORMATION
Each of the LEDs must have enough voltage to forward bias the LED, regulate the CSA voltage, and exceed the
driver dropout voltage requirement from DINA to CSA. A typical IR LED at 100 mA has 1.5 V forward voltage.
The LED driver dropout voltage at 100 mA is 300 mV. With the CSA voltage set to 100 mV, the dropout voltage
of 300 mV, and forward bias voltage of 1.5 V, at least 1.9 V must be applied to the IR LED anode for current
regulation. Connect the IR LED anode to the LEDLDO. Enable the boost converter set to 2.7 V and the LED
LDO to charge the IR LED anode capacitor.
A typical blue LED at 50 mA has 4 V forward voltage. For the blue LED, the CSB voltage is 340 mV, the dropout
voltage is 300 mV, and the forward voltage is 4 V. Supply over 4.64 V to the anode for the duration of the LED
pulse. With a 47 µF capacitor derated to 30 µF, 100 µs LED pulse, the anode voltage drops by 170 mV. Thus,
the capacitor must be charged to 4.81 V. Enable the boost converter set to 6 V and enable the LED LDO to
charge the blue LED anode capacitor. The LED LDO has a diode voltage drop between the VBST voltage and
LEDLDO voltage. The LEDLDO prevents the DINA pin from exceeding its recommended operating limit of 11.5
V.
7.2.2.4 Boost Converter Component Selection
A 4.7-μF, 16-V or 25-V, X5R or X7R capacitor is recommended on VBST. This value provides the best tradeoff
between boost ripple and power loss (due to charging and discharging VBST). While there is no specific
requirement for the DC biased capacitance, a capacitor with >1 μF capacitance at 12 V is generally sufficient.
A 4.7-μF X5R or X7R capacitor rated for the battery voltage is recommended to be connected to the battery. This
capacitor provides a low-impedance supply for the inductor when it is rapidly switching.
A 33-μH inductor rated for 650 mA of saturation current with less than 800 mΩ of DC resistance (DCR) is
recommended. Smaller DCR improves the efficiency of the boost converter. Comparing 800 mΩ to 400 mΩ,
approximately 3% efficiency improvement is expected.
Table 25. Recommended Inductors for Boost Converter
PART NUMBER
SUPPLIER
VALUE
DCR (Ω)
ISAT (A)
DIMENSIONS
SDR0503-330KL
Bourns
33 μH
0.38
0.85
5.0mm × 4.8mm x
3.0mm
NRS4018T330MDGJ
V
Taiyo Yuden
33 μH
0.552
0.70
4.0mm x 4.0mm x
1.8mm
A Schottky diode with low forward voltage and low leakage current is recommended. Even though leakage
causes power loss, the leakage recharges the VBAT capacitor and thus some leaked current is re-used.
Table 26. Recommended Diode for Boost Converter
PART NUMBER
SUPPLIER
SIZE
MBR0520LT1
ON Semiconductor Corp.
SOD-123
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7.2.2.5 Regulator Component Selection
ADVANCE INFORMATION
To stabilize the output voltage on each regulator, install 1-µF capacitors on VINT, VMCU, and PLDO. Connect
the MCUSEL pin to GND to set the MCU LDO voltage to 1.8 V. The MCU LDO can be set to other voltages by
changing the MCUSEL pin connection. Connect MCUSEL to a 330-pF capacitor to set the MCU LDO to 3.3 V.
Connect MCUSEL to VINT to set the MCU LDO to 2.5 V. Connect MCUSEL to GND with a 620-Ω resistor to set
the MCU LDO to 1.5 V.
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TPS8802
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8 Power Supply Recommendations
These sources can power the TPS8802:
• 3-V lithium battery
• 9-V battery
• two 1.5-V batteries
• a AC/DC supply
When the boost converter is used, the power supply must be able to supply 650-mA peak current to the boost
converter. Ensure that the power supply voltage does not drop below 2 V during the initial powerup sequence.
If the boost converter is not used, ensure the power supply can tolerate transient currents caused by the LED
driver or horn driver. A supply capable of 50 mA average current is generally sufficient. The supply voltage must
be high enough to power the horn driver, LED driver and interconnect.
ADVANCE INFORMATION
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9 Layout
9.1 Layout Guidelines
These blocks require careful layout placement:
• Boost converter
• Photo amplifier
• CO amplifier
• Ground plane and traces
9.1.1 Photo Amplifier Layout
The photo amplifier is the most sensitive analog block in the TPS8802 device. Minimal trace lengths must be
used to connect to PDP, PDN, PDO, and AGND. If the photo amplifier is referenced to PREF, connect a 100-pF
filtering capacitor from PREF to GND near the PDP components. It is recommended to shield the PDP, PDN,
and PDO traces with the AGND plane.
Similar to the photo amplifier, the CO amplifier is very sensitive to noise. Connect the CO electrochemical sensor
close to the TPS8802 device and shield the COP, CON, and COO traces with the AGND plane.
9.1.3 Boost Converter Layout
The boost converter components must be positioned close to the VLX, VBST, and PGND pins. To minimize
switching noise, ensure that the VLX trace is as short as possible. A PGND plane can assist with connecting the
PGND connections together, but may not be necessary if the PGND routing is short enough without the PGND
plane. All PGND routing must remain separated from the AGND plane. Connect PGND to AGND at a single point
near the AGND pin.
9.1.4 Ground Plane Layout
Connect AGND and DGND to the ground plane. Ensure there is a short path from AGND to DGND. Route PGND
and its associated blocks (LED driver, boost converter, horn driver) separately from the ground plane. Connect
PGND to AGND at a single point near the IC.
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ADVANCE INFORMATION
9.1.2 CO Amplifier Layout
TPS8802
SLVSF25 – OCTOBER 2019
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9.2 Layout Example
ADVANCE INFORMATION
Figure 15. Photo Amplifier Layout
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ADVANCE INFORMATION
Layout Example (continued)
Figure 16. CO Amplifier Layout
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Layout Example (continued)
ADVANCE INFORMATION
Figure 17. Boost Converter Layout with PGND Plane
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Layout Example (continued)
AGND
DGND
ADVANCE INFORMATION
AGND Plane
PGND
PGND
PGND
PGND
PGND
PGND Pla ne
Figure 18. Ground Layout
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
60
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PACKAGE OUTLINE
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9.8
9.6
NOTE 3
9
19
20
38X
4.5
4.3
B
0.27
0.17
0.08
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
38X (1.5)
38X (0.3)
SYMM
SEE DETAILS
1
38
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(0.6) TYP
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
( 0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
SYMM
(4.7)
BASED ON
0.125 THICK
STENCIL
39
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
PTPS8802DCP
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
DCP
38
50
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
GENERIC PACKAGE VIEW
DCP 38
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.22 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/A
www.ti.com
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