Texas Instruments | DRV5056 unipolar ratiometric linear hall effect sensor (Rev. A) | Datasheet | Texas Instruments DRV5056 unipolar ratiometric linear hall effect sensor (Rev. A) Datasheet

Texas Instruments DRV5056 unipolar ratiometric linear hall effect sensor (Rev. A) Datasheet
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DRV5056
SBAS644A – APRIL 2018 – REVISED FEBRUARY 2019
DRV5056 unipolar ratiometric linear hall effect sensor
1 Features
3 Description
•
•
•
The DRV5056 is a linear Hall effect sensor that
responds proportionally to flux density of a magnetic
south pole. The device can be used for accurate
position sensing in a wide range of applications.
1
•
•
•
•
•
Unipolar linear hall effect magnetic sensor
Operates from 3.3-V and 5-V power supplies
Analog output with 0.6-V quiescent offset:
– Maximizes voltage swing for high accuracy
Magnetic sensitivity options (at VCC = 5 V):
– A1: 200 mV/mT, 20-mT range
– A2: 100 mV/mT, 39-mT range
– A3: 50 mV/mT, 79-mT range
– A4: 25 mV/mT, 158-mT range
– A6: 100 mV/mT, 39-mT range
Fast 20-kHz sensing bandwidth
Low-noise output with ±1-mA drive
Compensation for magnet temperature drift
Standard industry packages:
– Surface-mount SOT-23
– Through-hole TO-92
2 Applications
•
•
•
•
•
•
•
•
Precise position sensing
Industrial automation and robotics
Home appliances
Gamepads, pedals, keyboards, triggers
Height leveling, tilt and weight measurement
Fluid flow rate measurement
Medical devices
Current sensing
Featuring a unipolar magnetic response, the analog
output drives 0.6 V when no magnetic field is present,
and increases when a south magnetic pole is applied.
This response maximizes the output dynamic range
in applications that sense one magnetic pole. Four
sensitivity options further maximize the output swing
based on the required sensing range.
The device operates from 3.3-V or 5-V power
supplies. Magnetic flux perpendicular to the top of the
package is sensed, and the two package options
provide different sensing directions.
The device uses a ratiometric architecture that can
minimize error from VCC tolerance when the external
analog-to-digital converter (ADC) uses the same VCC
for its reference. Additionally, the device features
magnet temperature compensation to counteract how
magnets drift for linear performance across a wide
temperature range.
The A1 to A4 options support a temperature range of
–40°C to +125°C. The A6 version supports a
temperature range of 0°C to 85°C.
Device Information(1)
PART NUMBER
DRV5056
PACKAGE
BODY SIZE (NOM)
SOT-23 (3)
2.92 mm × 1.30 mm
TO-92 (3)
4.00 mm × 3.15 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Schematic
Magnetic Response
VCC
OUT
VCC
DRV5056
VCC
OUT
Controller
VL (MAX)
ADC
GND
0.6 V
0 mT
B
south
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV5056
SBAS644A – APRIL 2018 – REVISED FEBRUARY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Magnetic Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
8.3 What to Do and What Not to Do ............................. 17
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2018) to Revision A
•
2
Page
Added new A6 magnetic sensitivity option to the data sheet ................................................................................................. 1
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5 Pin Configuration and Functions
DBZ Package
3-Pin SOT-23
Top View
LPG Package
3-Pin TO-92
Top View
1
VCC
3
OUT
GND
2
1
VCC
2
3
GND OUT
Pin Functions
PIN
NAME
I/O
DESCRIPTION
SOT-23
TO-92
GND
3
2
—
Ground reference
OUT
2
3
O
Analog output
VCC
1
1
—
Power supply. TI recommends connecting this pin to a ceramic capacitor to ground
with a value of at least 0.1 µF.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Power supply voltage
VCC
–0.3
7
UNIT
V
Output voltage
OUT
–0.3
VCC + 0.3
V
Magnetic flux density, BMAX
Unlimited
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
T
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2500
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Power supply voltage (1)
IO
Output continuous current
TA
A1-A4 versions operating ambient temperature (2)
TA
A6 version operating ambient temperature (2)
(1)
(2)
MIN
MAX
3
3.6
4.5
5.5
UNIT
V
–1
1
mA
–40
125
°C
0
85
°C
There are two isolated operating VCC ranges. For more information see the Operating VCC Ranges section.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV5056
THERMAL METRIC (1)
SOT-23 (DBZ)
TO-92 (LPG)
3 PINS
3 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
170
121
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66
67
°C/W
RθJB
Junction-to-board thermal resistance
49
97
°C/W
YJT
Junction-to-top characterization parameter
1.7
7.6
°C/W
YJB
Junction-to-board characterization parameter
48
97
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
ICC
Operating supply current
tON
Power-on time (see Figure 19)
fBW
Sensing bandwidth
td
Propagation delay time
BND
Input-referred RMS noise density
BN
Input-referred noise
VN
(1)
(2)
4
Output-referred noise (2)
B = 0 mT, no load on OUT
From change in B to change in OUT
MIN
TYP
MAX
6
10
mA
150
300
µs
20
kHz
10
µs
VCC = 5 V
130
VCC = 3.3 V
215
BND × 6.6 × √20 kHz
BN × S
VCC = 5 V
UNIT
0.12
VCC = 3.3 V
0.2
DRV5056A1
24
DRV5056A2,
DRV5056A6
12
DRV5056A3
6
DRV5056A4
3
nT/√Hz
mTPP
mVPP
B is the applied magnetic flux density.
VN describes voltage noise on the device output. If the full device bandwidth is not needed, noise can be reduced with an RC filter.
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6.6 Magnetic Characteristics
for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
VQ
Quiescent voltage
B = 0 mT, TA = 25°C
VQΔT
B = 0 mT,
Quiescent voltage temperature drift TA = –40°C to 125°C
versus 25°C
VQΔL
Quiescent voltage lifetime drift
Sensitivity
VCC = 3.3 V,
TA = 25°C
VCC = 5 V,
TA = 25°C
BL
TYP
MAX
DRV5056A1
0.535
0.6
0.665
DRV5056A2,
DRV5056A6
0.54
0.6
0.66
DRV5056A3,
DRV5056A4
0.55
0.6
0.65
VCC = 5 V
0.08
VCC = 3.3 V
0.04
High-temperature operating stress for
1000 hours
VCC = 5 V,
TA = 25°C
S
MIN
Linear magnetic sensing range (2)
VCC = 3.3 V,
TA = 25°C
190
200
210
DRV5056A2,
DRV5056A6
95
100
105
DRV5056A3
47.5
50
52.5
DRV5056A4
23.8
25
26.2
DRV5056A1
114
120
126
DRV5056A2,
DRV5056A6
57
60
63
DRV5056A3
28.5
30
31.5
DRV5056A4
14.3
15
15.8
DRV5056A1
20
DRV5056A2,
DRV5056A6
39
DRV5056A3
79
DRV5056A4
158
DRV5056A1
19
DRV5056A2,
DRV5056A6
39
DRV5056A3
78
DRV5056A4
155
STC
Sensitivity temperature
compensation for magnets (4)
DRV5056A6
STC
Sensitivity temperature
compensation for magnets (4)
DRV5056A1, DRV5056A2, DRV5056A3,
DRV5056A4
0.12
SLE
Sensitivity linearity error (3)
VOUT is within VL
±1%
Sensitivity ratiometry error
SΔL
Sensitivity lifetime drift
(1)
(2)
(3)
(4)
(5)
VQ
High-temperature operating stress for
1000 hours
0.05
mV/mT
mT
Linear range of output voltage (3)
SRE
V
DRV5056A1
TA = 25°C,
with respect to VCC = 3.3 V or 5 V
V
< 0.5%
VL
(5)
UNIT
VCC – 0.2
0.12
-2.5%
0.19
V
%/°C
%/°C
2.5%
< 0.5%
B is the applied magnetic flux density.
BL describes the minimum linear sensing range at 25°C taking into account the maximum VQ and Sensitivity tolerances.
See the Sensitivity Linearity section.
STC describes the rate the device increases Sensitivity with temperature. For more information, see the Sensitivity Temperature
Compensation For Magnets section.
See the Ratiometric Architecture section.
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6.7 Typical Characteristics
at TA = 25°C (unless otherwise noted)
655
640
638
650
Quiescent Voltage (mV)
Quiescent Voltage (mV)
636
645
640
635
630
625
620
634
632
630
628
626
624
622
620
VCC = 3.3 V
VCC = 5 V
615
610
-40
618
616
-20
0
20
40
60
80 100
Temperature (qC)
120
140
160
3
3.5
3.75
4 4.25 4.5 4.75
Supply Voltage (V)
5
5.25
5.5
D003
Figure 2. Quiescent Voltage vs Supply Voltage
250
200
A1
A2
A3
A4
Y Axis Title (Unit)
Sensitivity (mV/MT)
Figure 1. Quiescent Voltage vs Temperature
140
130
120
110
100
90
80
70
60
50
40
30
20
10
3.25
D002
A1
A2
150
A3
A4
100
50
3
3.1
3.2
3.3
3.4
Supply Voltage (V)
3.5
0
4.5
3.6
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
D007
D006
VCC = 3.3 V
VCC = 5 V
Figure 3. Sensitivity vs Supply Voltage
Figure 4. Sensitivity vs Supply Voltage
7
150
6.75
145
Sensitivity (mV/mT)
Supply Current (mA)
140
6.5
6.25
6
5.75
135
130
125
120
115
5.5
110
5.25
5
-40
VCC = 3.3 V
VCC = 5 V
-20
0
20
40
60
80 100
Temperature (qC)
120
140
+3STD
AVG
-3STD
105
160
100
-40
D001
-20
0
20
40
60
80 100
Temperature (qC)
120
140
160
D008
DRV5056A1, VCC = 3.3 V
Figure 5. Supply Current vs Temperature
6
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Figure 6. Sensitivity vs Temperature
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Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
80
260
75
Sensitivity (mV/mT)
Sensitivity (mV/mT)
240
220
200
180
160
-40
+3STD
AVG
3STD
-20
0
20
40
60
80 100
Temperature (qC)
120
140
70
65
60
+3STD
AVG
3STD
55
50
-40
160
-20
0
DRV5056A1, VCC = 5.0 V
115
37
110
105
100
95
90
+3STD
AVG
3STD
85
0
20
40
60
80 100
Temperature (qC)
120
140
160
D010
Figure 8. Sensitivity vs Temperature
39
Sensitivity (mV/mT)
Sensitivity (mV/mT)
Figure 7. Sensitivity vs Temperature
-20
40
60
80 100
Temperature (qC)
DRV5056A2, VCC = 3.3 V
120
80
-40
20
D009
120
140
35
33
31
29
+3STD
AVG
3STD
27
25
-40
160
-20
0
20
D011
DRV5056A2, VCC = 5.0 V
40
60
80 100
Temperature (qC)
120
140
160
D012
DRV5056A3, VCC = 3.3 V
Figure 9. Sensitivity vs Temperature
Figure 10. Sensitivity vs Temperature
19
60
Sensitivity (mV/mT)
Sensitivity (mV/mT)
18
55
50
45
+3STD
AVG
3STD
40
-40
-20
0
20
40
60
80 100
Temperature (qC)
120
140
17
16
15
14
+3STD
AVG
3STD
13
160
12
-40
-20
D013
DRV5056A3, VCC = 5.0 V
0
20
40
60
80 100
Temperature (qC)
120
140
160
D014
DRV5056A4, VCC = 3.3 V
Figure 11. Sensitivity vs Temperature
Figure 12. Sensitivity vs Temperature
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Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
30
80
75
Sensitivity (mV/mT)
Sensitivity (mV/mT)
28
26
24
22
20
-40
+3STD
AVG
3STD
70
65
60
-3STD
AVG
+3STD
55
50
-20
0
20
40
60
80 100
Temperature (qC)
120
140
160
0
10
20
D015
DRV5056A4, VCC = 5.0 V
30
40
50
Temperature (C)
60
70
80 85
D016
DRV5056A6, VCC = 3.3 V
Figure 13. Sensitivity vs Temperature
Figure 14. Sensitivity vs Temperature
120
Sensitivity (mV/mT)
115
110
105
100
95
90
-3STD
AVG
+3STD
85
80
0
10
20
30
40
50
Temperature (C)
60
70
80 85
D017
DRV5056A6, VCC = 5.0 V
Figure 15. Sensitivity vs Temperature
8
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7 Detailed Description
7.1 Overview
The DRV5056 is a 3-pin linear Hall effect sensor with fully integrated signal conditioning, temperature
compensation circuits, mechanical stress cancellation, and amplifiers. The device operates from 3.3-V and 5-V
(±10%) power supplies, measures magnetic flux density, and outputs a proportional analog voltage that is
referenced to VCC.
7.2 Functional Block Diagram
Element Bias
Offset
Cancellation
Band-Gap
Reference
VCC
Trim
Registers
GND
0.1 F
Temperature
Compensation
VCC
Optional Filter
Precision
Amplifier
Output
Driver
OUT
7.3 Feature Description
7.3.1 Magnetic Flux Direction
As shown in Figure 16, the DRV5056 is sensitive to the magnetic field component that is perpendicular to the die
inside the package.
TO-92
B
B
SOT-23
PCB
Figure 16. Direction of Sensitivity
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Feature Description (continued)
Magnetic flux that travels from the bottom to the top of the package is considered positive. This condition exists
when a south magnetic pole is near the top (marked-side) of the package. Magnetic flux that travels from the top
to the bottom of the package results in negative millitesla values.
N
S
S
PCB
N
PCB
Figure 17. The Flux Direction for Positive B
7.3.2 Magnetic Response
The DRV5056 outputs an analog voltage according to Equation 1 when in the presence of a magnetic field:
(
)
VOUT = VQ + B × Sensitivity (25°C) × (1 + STC × (TA ± 25° C))
where
•
•
•
•
•
•
VQ is typically 600 mV
B is the applied magnetic flux density
Sensitivity(25°C) depends on the device option and VCC
STC is typically 0.12%/°C
TA is the ambient temperature
VOUT is within the VL range
(1)
As an example, consider the DRV5056A3 with VCC = 3.3 V, a temperature of 50°C, and 67 mT applied.
Excluding tolerances, VOUT = 600 mV + 67 mT × (30 mV/mT × [1 + 0.0012/°C × (50°C – 25°C)]) = 2.67 V.
The DRV5056 only responds to the flux density of a magnetic south pole.
10
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Feature Description (continued)
7.3.3 Sensitivity Linearity
The device produces a linear response when the output voltage is within the specified VL range. Outside this
range, sensitivity is reduced and nonlinear. Figure 18 graphs the magnetic response.
OUT
VCC
VL (MAX)
0.6 V
B
south
0 mT
Figure 18. Magnetic Response
Equation 2 calculates parameter BL, the minimum linear sensing range at 25°C taking into account the maximum
quiescent voltage and sensitivity tolerances.
VL(MAX) ± VQ(MAX)
BL(MIN) =
S(MAX)
(2)
The parameter SLE defines linearity error as the difference in sensitivity between any two positive B values when
the output is within the VL range.
7.3.4 Ratiometric Architecture
The DRV5056 has a ratiometric analog architecture that scales the sensitivity linearly with the power-supply
voltage. For example, the sensitivity is 5% higher when VCC = 5.25 V compared to VCC = 5 V. This behavior
enables external ADCs to digitize a more consistent value regardless of the power-supply voltage tolerance,
when the ADC uses VCC as its reference.
Equation 3 calculates sensitivity ratiometry error:
S(VCC) / S(5V)
SRE = 1 t
for VCC = 4.5 V to 5.5 V,
VCC / 5V
SRE = 1 t
S(VCC) / S(3.3V)
VCC / 3.3V
for VCC = 3 V to 3.6 V
where
•
•
•
S(VCC) is the sensitivity at the current VCC voltage
S(5V) or S(3.3V) is the sensitivity when VCC = 5 V or 3.3 V
VCC is the current VCC voltage
(3)
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Feature Description (continued)
7.3.5 Operating VCC Ranges
The DRV5056 has two recommended operating VCC ranges: 3 V to 3.6 V and 4.5 V to 5.5 V. When VCC is in the
middle region between 3.6 V to 4.5 V, the device continues to function, but sensitivity is less known because
there is a crossover threshold near 4 V that adjusts device characteristics.
7.3.6 Sensitivity Temperature Compensation For Magnets
Magnets generally produce weaker fields as temperature increases. The DRV5056 compensates by increasing
sensitivity with temperature, as defined by the parameter STC. The sensitivity at TA = 125°C is typically 12%
higher than at TA = 25°C.
7.3.7 Power-On Time
After the VCC voltage is applied, the DRV5056 requires a short initialization time before the output is set. The
parameter tON describes the time from when VCC crosses 3 V until OUT is within 5% of VQ, with 0 mT applied
and no load attached to OUT. Figure 19 shows this timing diagram.
VCC
3V
tON
time
Output
95% × V Q
Invalid
time
Figure 19. tON Definition
12
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Feature Description (continued)
7.3.8 Hall Element Location
Figure 20 shows the location of the sensing element inside each package option.
SOT-23
Top View
SOT-23
Side View
centered
650 µm
±50 µm
±80 µm
TO-92
Top View
2 mm
2 mm
TO-92
Side View
1.54 mm
1.61 mm
±50 µm
1030 µm
±115 µm
Figure 20. Hall Element Location
7.4 Device Functional Modes
The DRV5056 has one mode of operation that applies when the Recommended Operating Conditions are met.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Selecting the Sensitivity Option
Select the highest DRV5056 sensitivity option that can measure the required range of magnetic flux density, so
that the output voltage swing is maximized.
Larger magnets and greater sensing distances can generally enable better positional accuracy than very small
magnets at close distances, because magnetic flux density increases exponentially with the proximity to a
magnet.
8.1.2 Temperature Compensation for Magnets
The DRV5056 temperature compensation is designed to directly compensate the average drift of neodymium
(NdFeB) magnets and partially compensate ferrite magnets. The residual flux density (Br) of a magnet typically
reduces by 0.12%/°C for NdFeB, and 0.20%/°C for ferrite. When the operating temperature range of a system is
reduced, temperature drift errors are also reduced.
8.1.3 Adding a Low-Pass Filter
As illustrated in the Functional Block Diagram, an RC low-pass filter can be added to the device output for the
purpose of minimizing voltage noise when the full 20-kHz bandwidth is not needed. This filter can improve the
signal-to-noise ratio (SNR) and overall accuracy. Do not connect a capacitor directly to the device output without
a resistor in between because doing so can make the output unstable.
8.1.4 Designing for Wire Break Detection
Some systems must detect if interconnect wires become open or shorted. The DRV5056 can support this
function.
First, select a sensitivity option that causes the output voltage to stay within the VL range during normal
operation. Second, add a pullup resistor between OUT and VCC. TI recommends a value between 20 kΩ to
100 kΩ, and the current through OUT must not exceed the IO specification, including current going into an
external ADC. Then, if the output voltage is ever measured to be within 150 mV of VCC or GND, a fault condition
exists. Figure 21 shows the circuit, and Table 1 describes fault scenarios.
PCB
DRV5056
VCC
OUT
VCC
Cable
VOUT
GND
Figure 21. Wire Fault Detection Circuit
14
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SBAS644A – APRIL 2018 – REVISED FEBRUARY 2019
Table 1. Fault Scenarios and the Resulting VOUT
FAULT SCENARIO
VOUT
VCC disconnects
Close to GND
GND disconnects
Close to VCC
VCC shorts to OUT
Close to VCC
GND shorts to OUT
Close to GND
8.2 Typical Application
Mechanical Component
N
S
PCB
Figure 22. Unipolar Sensing Application
8.2.1 Design Requirements
Use the parameters listed in Table 2 for this design example.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VCC
3.3 V
Magnet
10-mm diameter × 6-mm long cylinder,
ferrite
Distance from magnet to sensor
From 20 mm to 3 mm
Maximum B at the sensor at 25°C
72 mT at 3 mm
Device option
DRV5056A3-Q1
8.2.2 Detailed Design Procedure
This design example consists of a mechanical component that moves back and forth, an embedded magnet with
the south pole facing the printed-circuit board, and a DRV5056. The DRV5056 outputs an analog voltage that
describes the precise position of the component. The component must not contain ferromagnetic materials such
as iron, nickel, and cobalt because these materials change the magnetic flux density at the sensor.
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When designing a linear magnetic sensing system, always consider these three variables: the magnet, sensing
distance, and range of the sensor. Select the DRV5056 with the highest sensitivity that has a BL (linear magnetic
sensing range) that is larger than the maximum magnetic flux density in the application.
Magnets are made from various ferromagnetic materials that have tradeoffs in cost, drift with temperature,
absolute maximum temperature ratings, remanence or residual induction (Br), and coercivity (Hc). The Br and the
dimensions of a magnet determine the magnetic flux density (B) produced in 3-dimensional space. For simple
magnet shapes, such as rectangular blocks and cylinders, there are simple equations that solve B at a given
distance centered with the magnet. Figure 23 shows diagrams for Equation 4 and Equation 5.
Thickness
Thickness
Width
Distance
Length
S
S
B
N
Distance
N
Diameter
B
Figure 23. Rectangular Block and Cylinder Magnets
Use Equation 4 for the rectangular block shown in Figure 23:
B=
Br
Œ
( (
WL
arctan
2
2
2D 4D + W + L
2
)
± arctan
Use Equation 5 for the cylinder shown in Figure 23:
Br
D+T
D
±
B=
2
2
2
(0.5C) + (D + T)
(0.5C)2 + D2
(
(
WL
2(D + T) 4(D + T)2 + W2 + L2
))
(4)
)
where
•
•
•
•
•
16
W is width
L is length
T is thickness (the direction of magnetization)
D is distance
C is diameter
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8.2.3 Application Curve
Figure 24 shows the magnetic flux density versus distance for a 10-mm × 6-mm cylinder ferrite magnet.
80
Magnetic Flux Density (mT)
70
60
50
40
30
20
10
0
3
6
9
12
15
Distance (mm)
18
21
D001
Figure 24. Magnetic Profile of a 10-mm × 6-mm Cylindrical Ferrite Magnet
8.3 What to Do and What Not to Do
Because the Hall element is sensitive to magnetic fields that are perpendicular to the top of the package, a
correct magnet approach must be used for the sensor to detect the field. Figure 25 illustrates correct and
incorrect approaches.
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What to Do and What Not to Do (continued)
CORRECT
N
S
S
N
N
S
INCORRECT
N
S
Figure 25. Correct and Incorrect Magnet Approaches
18
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SBAS644A – APRIL 2018 – REVISED FEBRUARY 2019
9 Power Supply Recommendations
A decoupling capacitor close to the device must be used to provide local energy with minimal inductance. TI
recommends using a ceramic capacitor with a value of at least 0.01 µF.
10 Layout
10.1 Layout Guidelines
Magnetic fields pass through most nonferromagnetic materials with no significant disturbance. Embedding Hall
effect sensors within plastic or aluminum enclosures and sensing magnets on the outside is common practice.
Magnetic fields also easily pass through most printed-circuit boards, which makes placing the magnet on the
opposite side possible.
10.2 Layout Examples
VCC
GND
VCC
GND
OUT
OUT
Figure 26. Layout Examples
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DRV5056
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www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Incremental rotary encoder design considerations application note
• Texas Instruments, Using linear hall effect sensors to measure angle application note
• Texas Instruments, Angle measurements with linear hall effect sensors
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV5056A1QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A1
DRV5056A1QDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A1
DRV5056A1QLPG
ACTIVE
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A1
DRV5056A1QLPGM
ACTIVE
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A1
DRV5056A2QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A2
DRV5056A2QDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A2
DRV5056A2QLPG
ACTIVE
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A2
DRV5056A2QLPGM
ACTIVE
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A2
DRV5056A3QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A3
DRV5056A3QDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A3
DRV5056A3QLPG
ACTIVE
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A3
DRV5056A3QLPGM
ACTIVE
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A3
DRV5056A4QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A4
DRV5056A4QDBZT
ACTIVE
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A4
DRV5056A4QLPG
ACTIVE
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A4
DRV5056A4QLPGM
ACTIVE
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
56A4
DRV5056A6QDBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
56A6
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
19-Feb-2019
Status
(1)
DRV5056A6QDBZT
Package Type Package Pins Package
Drawing
Qty
ACTIVE
SOT-23
DBZ
3
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
56A6
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV5056 :
• Automotive: DRV5056-Q1
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Feb-2019
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DRV5056A1QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A1QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A2QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A2QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A3QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A3QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A4QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A4QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A6QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5056A6QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV5056A1QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5056A1QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5056A2QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5056A2QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5056A3QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5056A3QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5056A4QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5056A4QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5056A6QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5056A6QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
LPG0003A
TO-92 - 5.05 mm max height
SCALE 1.300
TRANSISTOR OUTLINE
4.1
3.9
3.25
3.05
3X
0.55
0.40
5.05
MAX
3
1
3X (0.8)
3X
15.5
15.1
3X
0.48
0.35
3X
2X 1.27 0.05
0.51
0.36
2.64
2.44
2.68
2.28
1.62
1.42
2X (45 )
1
(0.5425)
2
3
0.86
0.66
4221343/C 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
LPG0003A
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
0.05 MAX
ALL AROUND
TYP
FULL R
TYP
METAL
TYP
(1.07)
3X ( 0.75) VIA
2X
METAL
(1.7)
2X (1.7)
2
1
2X
SOLDER MASK
OPENING
3
2X (1.07)
(R0.05) TYP
(1.27)
SOLDER MASK
OPENING
(2.54)
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE:20X
4221343/C 01/2018
www.ti.com
TAPE SPECIFICATIONS
LPG0003A
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
0
13.0
12.4
1
0
1
1 MAX
21
18
2.5 MIN
6.5
5.5
9.5
8.5
0.25
0.15
19.0
17.5
3.8-4.2 TYP
6.55
6.15
12.9
12.5
0.45
0.35
4221343/C 01/2018
www.ti.com
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.4
1.2
PIN 1
INDEX AREA
1.12 MAX
B
A
0.1 C
1
0.95
3.04
2.80
1.9
3X
3
0.5
0.3
0.2
2
(0.95)
C A B
0.25
GAGE PLANE
0 -8 TYP
0.10
TYP
0.01
0.20
TYP
0.08
0.6
TYP
0.2
SEATING PLANE
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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